From b422e11a068db6c3eb76651c3c2e8ff6f3f1aaf6 Mon Sep 17 00:00:00 2001 From: nxp58695 Date: Thu, 24 Oct 2019 17:56:09 +0800 Subject: [PATCH] added LPC55S6x BSP --- bsp/lpc55sxx/Libraries/Kconfig | 15 + .../CMSIS/Include/arm_common_tables.h | 121 + .../CMSIS/Include/arm_const_structs.h | 66 + .../LPC55S6X/CMSIS/Include/arm_math.h | 7160 ++ .../LPC55S6X/CMSIS/Include/cmsis_armcc.h | 870 + .../LPC55S6X/CMSIS/Include/cmsis_armclang.h | 1877 + .../LPC55S6X/CMSIS/Include/cmsis_compiler.h | 266 + .../LPC55S6X/CMSIS/Include/cmsis_gcc.h | 2088 + .../LPC55S6X/CMSIS/Include/cmsis_iccarm.h | 913 + .../LPC55S6X/CMSIS/Include/cmsis_version.h | 39 + .../LPC55S6X/CMSIS/Include/core_armv8mbl.h | 1896 + .../LPC55S6X/CMSIS/Include/core_armv8mml.h | 2960 + .../LPC55S6X/CMSIS/Include/core_cm33.h | 2963 + .../LPC55S6X/CMSIS/Include/core_dsp.h | 74 + .../LPC55S6X/CMSIS/Include/mpu_armv8.h | 333 + .../LPC55S6X/CMSIS/Include/tz_context.h | 70 + .../Libraries/LPC55S6X/CMSIS/LICENSE.txt | 201 + .../LPC55S6X/LPC55S6X/LPC55S69_cm33_core0.h | 25766 +++++ .../LPC55S6X/LPC55S6X/LPC55S69_cm33_core0.xml | 87406 ++++++++++++++++ .../LPC55S6X/LPC55S69_cm33_core0_features.h | 305 + .../LPC55S6X/LPC55S6X/LPC55S69_cm33_core1.h | 25763 +++++ .../LPC55S6X/LPC55S6X/LPC55S69_cm33_core1.xml | 87406 ++++++++++++++++ .../LPC55S6X/LPC55S69_cm33_core1_features.h | 305 + .../arm/LPC55S69_cm33_core0_flash.scf | 104 + .../arm/LPC55S69_cm33_core0_flash_ns.scf | 111 + .../arm/LPC55S69_cm33_core0_flash_s.scf | 122 + .../LPC55S6X/arm/LPC55S69_cm33_core0_ram.scf | 104 + .../arm/LPC55S69_cm33_core1_flash.scf | 90 + .../LPC55S6X/arm/LPC55S69_cm33_core1_ram.scf | 95 + .../arm/LPC55S69_cm33_core1_ram_s.scf | 95 + .../LPC55S6X/LPC55S6X/arm/LPC55XX_640.FLM | Bin 0 -> 23308 bytes .../LPC55S6X/LPC55S6X/arm/LPC55XX_S_640.FLM | Bin 0 -> 23316 bytes .../LPC55S6X/LPC55S6X/arm/LPC55xx.dbgconf | 18 + .../arm/keil_lib_power_cm33_core0.lib | Bin 0 -> 10032 bytes ...er_cm33_core0_disable_short_enum_wchar.lib | Bin 0 -> 10032 bytes .../arm/keil_lib_power_cm33_core0_s.lib | Bin 0 -> 10032 bytes ..._cm33_core0_s_disable_short_enum_wchar.lib | Bin 0 -> 10032 bytes .../arm/keil_lib_power_cm33_core1.lib | Bin 0 -> 10024 bytes ...er_cm33_core1_disable_short_enum_wchar.lib | Bin 0 -> 10024 bytes .../arm/startup_LPC55S69_cm33_core0.s | 732 + .../arm/startup_LPC55S69_cm33_core0_ns.s | 732 + .../arm/startup_LPC55S69_cm33_core1.s | 732 + .../LPC55S6X/LPC55S6X/drivers/fsl_anactrl.c | 320 + .../LPC55S6X/LPC55S6X/drivers/fsl_anactrl.h | 458 + .../LPC55S6X/LPC55S6X/drivers/fsl_casper.c | 2662 + .../LPC55S6X/LPC55S6X/drivers/fsl_casper.h | 301 + .../LPC55S6X/LPC55S6X/drivers/fsl_clock.c | 2099 + .../LPC55S6X/LPC55S6X/drivers/fsl_clock.h | 1300 + .../LPC55S6X/LPC55S6X/drivers/fsl_cmp.c | 55 + .../LPC55S6X/LPC55S6X/drivers/fsl_cmp.h | 293 + .../LPC55S6X/LPC55S6X/drivers/fsl_common.c | 147 + .../LPC55S6X/LPC55S6X/drivers/fsl_common.h | 597 + .../LPC55S6X/LPC55S6X/drivers/fsl_crc.c | 172 + .../LPC55S6X/LPC55S6X/drivers/fsl_crc.h | 181 + .../LPC55S6X/LPC55S6X/drivers/fsl_ctimer.c | 544 + .../LPC55S6X/LPC55S6X/drivers/fsl_ctimer.h | 488 + .../LPC55S6X/LPC55S6X/drivers/fsl_dma.c | 954 + .../LPC55S6X/LPC55S6X/drivers/fsl_dma.h | 823 + .../LPC55S6X/LPC55S6X/drivers/fsl_flexcomm.c | 400 + .../LPC55S6X/LPC55S6X/drivers/fsl_flexcomm.h | 64 + .../LPC55S6X/LPC55S6X/drivers/fsl_gint.c | 392 + .../LPC55S6X/LPC55S6X/drivers/fsl_gint.h | 222 + .../LPC55S6X/LPC55S6X/drivers/fsl_gpio.c | 303 + .../LPC55S6X/LPC55S6X/drivers/fsl_gpio.h | 365 + .../LPC55S6X/LPC55S6X/drivers/fsl_hashcrypt.c | 1198 + .../LPC55S6X/LPC55S6X/drivers/fsl_hashcrypt.h | 425 + .../LPC55S6X/LPC55S6X/drivers/fsl_i2c.c | 1869 + .../LPC55S6X/LPC55S6X/drivers/fsl_i2c.h | 1042 + .../LPC55S6X/LPC55S6X/drivers/fsl_i2c_dma.c | 588 + .../LPC55S6X/LPC55S6X/drivers/fsl_i2c_dma.h | 120 + .../LPC55S6X/LPC55S6X/drivers/fsl_i2s.c | 886 + .../LPC55S6X/LPC55S6X/drivers/fsl_i2s.h | 488 + .../LPC55S6X/LPC55S6X/drivers/fsl_i2s_dma.c | 619 + .../LPC55S6X/LPC55S6X/drivers/fsl_i2s_dma.h | 162 + .../LPC55S6X/LPC55S6X/drivers/fsl_iap.c | 285 + .../LPC55S6X/LPC55S6X/drivers/fsl_iap.h | 498 + .../LPC55S6X/LPC55S6X/drivers/fsl_iap_ffr.h | 261 + .../LPC55S6X/LPC55S6X/drivers/fsl_inputmux.c | 121 + .../LPC55S6X/LPC55S6X/drivers/fsl_inputmux.h | 97 + .../drivers/fsl_inputmux_connections.h | 409 + .../LPC55S6X/LPC55S6X/drivers/fsl_iocon.h | 288 + .../LPC55S6X/LPC55S6X/drivers/fsl_lpadc.c | 609 + .../LPC55S6X/LPC55S6X/drivers/fsl_lpadc.h | 841 + .../LPC55S6X/LPC55S6X/drivers/fsl_mailbox.h | 214 + .../LPC55S6X/LPC55S6X/drivers/fsl_mrt.c | 150 + .../LPC55S6X/LPC55S6X/drivers/fsl_mrt.h | 366 + .../LPC55S6X/LPC55S6X/drivers/fsl_ostimer.c | 266 + .../LPC55S6X/LPC55S6X/drivers/fsl_ostimer.h | 217 + .../LPC55S6X/LPC55S6X/drivers/fsl_pint.c | 855 + .../LPC55S6X/LPC55S6X/drivers/fsl_pint.h | 579 + .../LPC55S6X/LPC55S6X/drivers/fsl_plu.c | 97 + .../LPC55S6X/LPC55S6X/drivers/fsl_plu.h | 266 + .../LPC55S6X/LPC55S6X/drivers/fsl_power.c | 19 + .../LPC55S6X/LPC55S6X/drivers/fsl_power.h | 737 + .../LPC55S6X/LPC55S6X/drivers/fsl_powerquad.h | 2706 + .../LPC55S6X/drivers/fsl_powerquad_basic.c | 126 + .../LPC55S6X/drivers/fsl_powerquad_cmsis.c | 1657 + .../LPC55S6X/drivers/fsl_powerquad_data.c | 584 + .../LPC55S6X/drivers/fsl_powerquad_data.h | 48 + .../LPC55S6X/drivers/fsl_powerquad_filter.c | 413 + .../LPC55S6X/drivers/fsl_powerquad_math.c | 864 + .../LPC55S6X/drivers/fsl_powerquad_matrix.c | 134 + .../drivers/fsl_powerquad_transform.c | 103 + .../LPC55S6X/LPC55S6X/drivers/fsl_prince.c | 454 + .../LPC55S6X/LPC55S6X/drivers/fsl_prince.h | 238 + .../LPC55S6X/LPC55S6X/drivers/fsl_puf.c | 817 + .../LPC55S6X/LPC55S6X/drivers/fsl_puf.h | 231 + .../LPC55S6X/LPC55S6X/drivers/fsl_reset.c | 99 + .../LPC55S6X/LPC55S6X/drivers/fsl_reset.h | 281 + .../LPC55S6X/LPC55S6X/drivers/fsl_rng.c | 96 + .../LPC55S6X/LPC55S6X/drivers/fsl_rng.h | 95 + .../LPC55S6X/LPC55S6X/drivers/fsl_rtc.c | 321 + .../LPC55S6X/LPC55S6X/drivers/fsl_rtc.h | 318 + .../LPC55S6X/LPC55S6X/drivers/fsl_sctimer.c | 715 + .../LPC55S6X/LPC55S6X/drivers/fsl_sctimer.h | 825 + .../LPC55S6X/LPC55S6X/drivers/fsl_sdif.c | 1573 + .../LPC55S6X/LPC55S6X/drivers/fsl_sdif.h | 1033 + .../LPC55S6X/LPC55S6X/drivers/fsl_spi.c | 1040 + .../LPC55S6X/LPC55S6X/drivers/fsl_spi.h | 725 + .../LPC55S6X/LPC55S6X/drivers/fsl_spi_dma.c | 554 + .../LPC55S6X/LPC55S6X/drivers/fsl_spi_dma.h | 208 + .../LPC55S6X/LPC55S6X/drivers/fsl_sysctl.c | 206 + .../LPC55S6X/LPC55S6X/drivers/fsl_sysctl.h | 185 + .../LPC55S6X/LPC55S6X/drivers/fsl_usart.c | 939 + .../LPC55S6X/LPC55S6X/drivers/fsl_usart.h | 718 + .../LPC55S6X/LPC55S6X/drivers/fsl_usart_dma.c | 307 + .../LPC55S6X/LPC55S6X/drivers/fsl_usart_dma.h | 161 + .../LPC55S6X/LPC55S6X/drivers/fsl_utick.c | 220 + .../LPC55S6X/LPC55S6X/drivers/fsl_utick.h | 118 + .../LPC55S6X/LPC55S6X/drivers/fsl_wwdt.c | 250 + .../LPC55S6X/LPC55S6X/drivers/fsl_wwdt.h | 274 + .../LPC55S6X/LPC55S6X/fsl_device_registers.h | 44 + .../LPC55S6X/gcc/LPC55S69_cm33_core0_flash.ld | 231 + .../gcc/LPC55S69_cm33_core0_flash_ns.ld | 231 + .../gcc/LPC55S69_cm33_core0_flash_s.ld | 242 + .../LPC55S6X/gcc/LPC55S69_cm33_core0_ram.ld | 231 + .../LPC55S6X/gcc/LPC55S69_cm33_core1_flash.ld | 221 + .../LPC55S6X/gcc/LPC55S69_cm33_core1_ram.ld | 221 + .../LPC55S6X/gcc/LPC55S69_cm33_core1_ram_s.ld | 221 + .../LPC55S6X/LPC55S6X/gcc/libpower_hardabi.a | Bin 0 -> 50644 bytes .../LPC55S6X/gcc/libpower_hardabi_s.a | Bin 0 -> 50612 bytes .../LPC55S6X/LPC55S6X/gcc/libpower_soft.a | Bin 0 -> 50600 bytes .../LPC55S6X/LPC55S6X/gcc/libpower_softabi.a | Bin 0 -> 50644 bytes .../LPC55S6X/gcc/libpower_softabi_s.a | Bin 0 -> 50612 bytes .../gcc/startup_LPC55S69_cm33_core0.S | 875 + .../gcc/startup_LPC55S69_cm33_core1.S | 875 + .../iar/LPC55S69_cm33_core0_flash.icf | 111 + .../iar/LPC55S69_cm33_core0_flash_ns.icf | 111 + .../iar/LPC55S69_cm33_core0_flash_s.icf | 121 + .../LPC55S6X/iar/LPC55S69_cm33_core0_ram.icf | 111 + .../iar/LPC55S69_cm33_core1_flash.icf | 104 + .../LPC55S6X/iar/LPC55S69_cm33_core1_ram.icf | 104 + .../iar/LPC55S69_cm33_core1_ram_s.icf | 104 + .../LPC55S6X/iar/iar_lib_power_cm33_core0.a | Bin 0 -> 13510 bytes .../LPC55S6X/iar/iar_lib_power_cm33_core0_s.a | Bin 0 -> 13526 bytes .../LPC55S6X/iar/iar_lib_power_cm33_core1.a | Bin 0 -> 12664 bytes .../iar/startup_LPC55S69_cm33_core0.s | 627 + .../iar/startup_LPC55S69_cm33_core1.s | 627 + .../mcuxpresso/boot_multicore_slave.c | 78 + .../mcuxpresso/boot_multicore_slave.h | 46 + .../mcuxpresso/startup_lpc55s69_cm33_core0.c | 744 + .../startup_lpc55s69_cm33_core0.cpp | 744 + .../mcuxpresso/startup_lpc55s69_cm33_core1.c | 744 + .../startup_lpc55s69_cm33_core1.cpp | 744 + .../LPC55S6X/system_LPC55S69_cm33_core0.c | 363 + .../LPC55S6X/system_LPC55S69_cm33_core0.h | 110 + .../LPC55S6X/system_LPC55S69_cm33_core1.c | 366 + .../LPC55S6X/system_LPC55S69_cm33_core1.h | 110 + bsp/lpc55sxx/Libraries/LPC55S6X/SConscript | 70 + .../components/codec/fsl_codec_common.c | 238 + .../components/codec/fsl_codec_common.h | 363 + .../components/codec/i2c/fsl_codec_i2c.c | 113 + .../components/codec/i2c/fsl_codec_i2c.h | 107 + .../components/codec/port/fsl_codec_adapter.h | 145 + .../codec/port/wm8904/fsl_codec_adapter.c | 245 + .../components/codec/wm8904/fsl_wm8904.c | 1092 + .../components/codec/wm8904/fsl_wm8904.h | 496 + .../LPC55S6X/middleware/sdmmc/inc/fsl_mmc.h | 321 + .../LPC55S6X/middleware/sdmmc/inc/fsl_sd.h | 315 + .../LPC55S6X/middleware/sdmmc/inc/fsl_sdio.h | 507 + .../middleware/sdmmc/inc/fsl_sdmmc_common.h | 258 + .../middleware/sdmmc/inc/fsl_sdmmc_host.h | 780 + .../middleware/sdmmc/inc/fsl_sdmmc_spec.h | 1215 + .../middleware/sdmmc/port/fsl_sdmmc_event.h | 87 + .../port/sdif/freertos/fsl_sdmmc_event.c | 152 + .../sdmmc/port/sdif/freertos/fsl_sdmmc_host.c | 296 + .../port/sdif/interrupt/fsl_sdmmc_event.c | 143 + .../port/sdif/interrupt/fsl_sdmmc_host.c | 311 + .../sdmmc/port/sdif/polling/fsl_sdmmc_event.c | 142 + .../sdmmc/port/sdif/polling/fsl_sdmmc_host.c | 245 + .../port/sdif/rt_thread/fsl_sdmmc_event.c | 149 + .../port/sdif/rt_thread/fsl_sdmmc_host.c | 274 + .../LPC55S6X/middleware/sdmmc/src/fsl_mmc.c | 2671 + .../LPC55S6X/middleware/sdmmc/src/fsl_sd.c | 1982 + .../LPC55S6X/middleware/sdmmc/src/fsl_sdio.c | 1700 + .../middleware/sdmmc/src/fsl_sdmmc_common.c | 393 + bsp/lpc55sxx/Libraries/drivers/SConscript | 50 + bsp/lpc55sxx/Libraries/drivers/drv_adc.c | 110 + bsp/lpc55sxx/Libraries/drivers/drv_adc.h | 18 + bsp/lpc55sxx/Libraries/drivers/drv_hwtimer.c | 321 + bsp/lpc55sxx/Libraries/drivers/drv_hwtimer.h | 20 + bsp/lpc55sxx/Libraries/drivers/drv_i2c.c | 144 + bsp/lpc55sxx/Libraries/drivers/drv_i2c.h | 20 + bsp/lpc55sxx/Libraries/drivers/drv_key.c | 168 + bsp/lpc55sxx/Libraries/drivers/drv_key.h | 51 + bsp/lpc55sxx/Libraries/drivers/drv_led.c | 160 + bsp/lpc55sxx/Libraries/drivers/drv_led.h | 19 + bsp/lpc55sxx/Libraries/drivers/drv_log.h | 27 + bsp/lpc55sxx/Libraries/drivers/drv_mma8562.c | 162 + bsp/lpc55sxx/Libraries/drivers/drv_mma8562.h | 111 + bsp/lpc55sxx/Libraries/drivers/drv_pin.c | 431 + bsp/lpc55sxx/Libraries/drivers/drv_pin.h | 23 + bsp/lpc55sxx/Libraries/drivers/drv_pwm.c | 257 + bsp/lpc55sxx/Libraries/drivers/drv_pwm.h | 19 + bsp/lpc55sxx/Libraries/drivers/drv_rtc.c | 153 + bsp/lpc55sxx/Libraries/drivers/drv_rtc.h | 20 + bsp/lpc55sxx/Libraries/drivers/drv_sd.c | 243 + bsp/lpc55sxx/Libraries/drivers/drv_sd.h | 29 + bsp/lpc55sxx/Libraries/drivers/drv_spi.c | 448 + bsp/lpc55sxx/Libraries/drivers/drv_spi.h | 16 + bsp/lpc55sxx/Libraries/drivers/drv_uart.c | 437 + bsp/lpc55sxx/Libraries/drivers/drv_uart.h | 17 + bsp/lpc55sxx/Libraries/drivers/drv_wdt.c | 241 + bsp/lpc55sxx/Libraries/drivers/drv_wdt.h | 20 + .../Libraries/template/lpc55s6xxxx/.config | 419 + .../Libraries/template/lpc55s6xxxx/Kconfig | 26 + .../Libraries/template/lpc55s6xxxx/README.md | 214 + .../Libraries/template/lpc55s6xxxx/SConscript | 14 + .../Libraries/template/lpc55s6xxxx/SConstruct | 65 + .../lpc55s6xxxx/applications/SConscript | 16 + .../template/lpc55s6xxxx/applications/main.c | 41 + .../template/lpc55s6xxxx/board/Kconfig | 222 + .../board/MCUX_Config/LPCXpresso55S69.mex | 316 + .../board/MCUX_Config/board/clock_config.c | 300 + .../board/MCUX_Config/board/clock_config.h | 147 + .../board/MCUX_Config/board/pin_mux.c | 348 + .../board/MCUX_Config/board/pin_mux.h | 185 + .../template/lpc55s6xxxx/board/SConscript | 17 + .../template/lpc55s6xxxx/board/board.c | 98 + .../template/lpc55s6xxxx/board/board.h | 68 + .../LPC55S69_cm33_core0_flash.ld | 231 + .../LPC55S69_cm33_core0_flash_iar.icf | 111 + .../LPC55S69_cm33_core0_flash_mdk.scf | 104 + .../template/lpc55s6xxxx/figures/board.png | Bin 0 -> 938384 bytes .../template/lpc55s6xxxx/figures/flash.png | Bin 0 -> 25990 bytes .../template/lpc55s6xxxx/flashdebug.ini | 11 + .../template/lpc55s6xxxx/project.ewd | 1485 + .../template/lpc55s6xxxx/project.ewp | 1533 + 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SOC_LPC55S69_SERIES + bool + select ARCH_ARM_CORTEX_M33 + select ARCH_ARM_CORTEX_FPU + diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/arm_common_tables.h b/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/arm_common_tables.h new file mode 100644 index 000000000..dfea7460e --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/arm_common_tables.h @@ -0,0 +1,121 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_common_tables.h + * Description: Extern declaration for common tables + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_COMMON_TABLES_H +#define _ARM_COMMON_TABLES_H + +#include "arm_math.h" + +extern const uint16_t armBitRevTable[1024]; +extern const q15_t armRecipTableQ15[64]; +extern const q31_t armRecipTableQ31[64]; +extern const float32_t twiddleCoef_16[32]; +extern const float32_t twiddleCoef_32[64]; +extern const float32_t twiddleCoef_64[128]; +extern const float32_t twiddleCoef_128[256]; +extern const float32_t twiddleCoef_256[512]; +extern const float32_t twiddleCoef_512[1024]; +extern const float32_t twiddleCoef_1024[2048]; +extern const float32_t twiddleCoef_2048[4096]; +extern const float32_t twiddleCoef_4096[8192]; +#define twiddleCoef twiddleCoef_4096 +extern const q31_t twiddleCoef_16_q31[24]; +extern const q31_t twiddleCoef_32_q31[48]; +extern const q31_t twiddleCoef_64_q31[96]; +extern const q31_t twiddleCoef_128_q31[192]; +extern const q31_t twiddleCoef_256_q31[384]; +extern const q31_t twiddleCoef_512_q31[768]; +extern const q31_t twiddleCoef_1024_q31[1536]; +extern const q31_t twiddleCoef_2048_q31[3072]; +extern const q31_t twiddleCoef_4096_q31[6144]; +extern const q15_t twiddleCoef_16_q15[24]; +extern const q15_t twiddleCoef_32_q15[48]; +extern const q15_t twiddleCoef_64_q15[96]; +extern const q15_t twiddleCoef_128_q15[192]; +extern const q15_t twiddleCoef_256_q15[384]; +extern const q15_t twiddleCoef_512_q15[768]; +extern const q15_t twiddleCoef_1024_q15[1536]; +extern const q15_t twiddleCoef_2048_q15[3072]; +extern const q15_t twiddleCoef_4096_q15[6144]; +extern const float32_t twiddleCoef_rfft_32[32]; +extern const float32_t twiddleCoef_rfft_64[64]; +extern const float32_t twiddleCoef_rfft_128[128]; +extern const float32_t twiddleCoef_rfft_256[256]; +extern const float32_t twiddleCoef_rfft_512[512]; +extern const float32_t twiddleCoef_rfft_1024[1024]; +extern const float32_t twiddleCoef_rfft_2048[2048]; +extern const float32_t twiddleCoef_rfft_4096[4096]; + +/* floating-point bit reversal tables */ +#define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20) +#define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48) +#define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56) +#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208) +#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440) +#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448) +#define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800) +#define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808) +#define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032) + +extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH]; + +/* fixed-point bit reversal tables */ +#define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12) +#define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24) +#define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56) +#define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112) +#define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240) +#define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480) +#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992) +#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984) +#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032) + +extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH]; + +/* Tables for Fast Math Sine and Cosine */ +extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1]; +extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1]; +extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1]; + +#endif /* ARM_COMMON_TABLES_H */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/arm_const_structs.h b/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/arm_const_structs.h new file mode 100644 index 000000000..80a3e8bbe --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/arm_const_structs.h @@ -0,0 +1,66 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_const_structs.h + * Description: Constant structs that are initialized for user convenience. + * For example, some can be given as arguments to the arm_cfft_f32() function. + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_CONST_STRUCTS_H +#define _ARM_CONST_STRUCTS_H + +#include "arm_math.h" +#include "arm_common_tables.h" + + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096; + + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096; + + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096; + +#endif diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/arm_math.h b/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/arm_math.h new file mode 100644 index 000000000..62f87bec8 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/arm_math.h @@ -0,0 +1,7160 @@ +/****************************************************************************** + * @file arm_math.h + * @brief Public header file for CMSIS DSP LibraryU + * @version V1.5.3 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + \mainpage CMSIS DSP Software Library + * + * Introduction + * ------------ + * + * This user manual describes the CMSIS DSP software library, + * a suite of common signal processing functions for use on Cortex-M processor based devices. + * + * The library is divided into a number of functions each covering a specific category: + * - Basic math functions + * - Fast math functions + * - Complex math functions + * - Filters + * - Matrix functions + * - Transforms + * - Motor control functions + * - Statistical functions + * - Support functions + * - Interpolation functions + * + * The library has separate functions for operating on 8-bit integers, 16-bit integers, + * 32-bit integer and 32-bit floating-point values. + * + * Using the Library + * ------------ + * + * The library installer contains prebuilt versions of the libraries in the Lib folder. + * - arm_cortexM7lfdp_math.lib (Cortex-M7, Little endian, Double Precision Floating Point Unit) + * - arm_cortexM7bfdp_math.lib (Cortex-M7, Big endian, Double Precision Floating Point Unit) + * - arm_cortexM7lfsp_math.lib (Cortex-M7, Little endian, Single Precision Floating Point Unit) + * - arm_cortexM7bfsp_math.lib (Cortex-M7, Big endian and Single Precision Floating Point Unit on) + * - arm_cortexM7l_math.lib (Cortex-M7, Little endian) + * - arm_cortexM7b_math.lib (Cortex-M7, Big endian) + * - arm_cortexM4lf_math.lib (Cortex-M4, Little endian, Floating Point Unit) + * - arm_cortexM4bf_math.lib (Cortex-M4, Big endian, Floating Point Unit) + * - arm_cortexM4l_math.lib (Cortex-M4, Little endian) + * - arm_cortexM4b_math.lib (Cortex-M4, Big endian) + * - arm_cortexM3l_math.lib (Cortex-M3, Little endian) + * - arm_cortexM3b_math.lib (Cortex-M3, Big endian) + * - arm_cortexM0l_math.lib (Cortex-M0 / Cortex-M0+, Little endian) + * - arm_cortexM0b_math.lib (Cortex-M0 / Cortex-M0+, Big endian) + * - arm_ARMv8MBLl_math.lib (Armv8-M Baseline, Little endian) + * - arm_ARMv8MMLl_math.lib (Armv8-M Mainline, Little endian) + * - arm_ARMv8MMLlfsp_math.lib (Armv8-M Mainline, Little endian, Single Precision Floating Point Unit) + * - arm_ARMv8MMLld_math.lib (Armv8-M Mainline, Little endian, DSP instructions) + * - arm_ARMv8MMLldfsp_math.lib (Armv8-M Mainline, Little endian, DSP instructions, Single Precision Floating Point Unit) + * + * The library functions are declared in the public file arm_math.h which is placed in the Include folder. + * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single + * public header file arm_math.h for Cortex-M cores with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. + * Define the appropriate preprocessor macro ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or + * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application. + * For Armv8-M cores define preprocessor macro ARM_MATH_ARMV8MBL or ARM_MATH_ARMV8MML. + * Set preprocessor macro __DSP_PRESENT if Armv8-M Mainline core supports DSP instructions. + * + * + * Examples + * -------- + * + * The library ships with a number of examples which demonstrate how to use the library functions. + * + * Toolchain Support + * ------------ + * + * The library has been developed and tested with MDK version 5.14.0.0 + * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. + * + * Building the Library + * ------------ + * + * The library installer contains a project file to rebuild libraries on MDK toolchain in the CMSIS\\DSP_Lib\\Source\\ARM folder. + * - arm_cortexM_math.uvprojx + * + * + * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional preprocessor macros detailed above. + * + * Preprocessor Macros + * ------------ + * + * Each library project have different preprocessor macros. + * + * - UNALIGNED_SUPPORT_DISABLE: + * + * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access + * + * - ARM_MATH_BIG_ENDIAN: + * + * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. + * + * - ARM_MATH_MATRIX_CHECK: + * + * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices + * + * - ARM_MATH_ROUNDING: + * + * Define macro ARM_MATH_ROUNDING for rounding on support functions + * + * - ARM_MATH_CMx: + * + * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target + * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and + * ARM_MATH_CM7 for building the library on cortex-M7. + * + * - ARM_MATH_ARMV8MxL: + * + * Define macro ARM_MATH_ARMV8MBL for building the library on Armv8-M Baseline target, ARM_MATH_ARMV8MML for building library + * on Armv8-M Mainline target. + * + * - __FPU_PRESENT: + * + * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for floating point libraries. + * + * - __DSP_PRESENT: + * + * Initialize macro __DSP_PRESENT = 1 when Armv8-M Mainline core supports DSP instructions. + * + *
+ * CMSIS-DSP in ARM::CMSIS Pack + * ----------------------------- + * + * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories: + * |File/Folder |Content | + * |------------------------------|------------------------------------------------------------------------| + * |\b CMSIS\\Documentation\\DSP | This documentation | + * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) | + * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions | + * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library | + * + *
+ * Revision History of CMSIS-DSP + * ------------ + * Please refer to \ref ChangeLog_pg. + * + * Copyright Notice + * ------------ + * + * Copyright (C) 2010-2015 Arm Limited. All rights reserved. + */ + + +/** + * @defgroup groupMath Basic Math Functions + */ + +/** + * @defgroup groupFastMath Fast Math Functions + * This set of functions provides a fast approximation to sine, cosine, and square root. + * As compared to most of the other functions in the CMSIS math library, the fast math functions + * operate on individual values and not arrays. + * There are separate functions for Q15, Q31, and floating-point data. + * + */ + +/** + * @defgroup groupCmplxMath Complex Math Functions + * This set of functions operates on complex data vectors. + * The data in the complex arrays is stored in an interleaved fashion + * (real, imag, real, imag, ...). + * In the API functions, the number of samples in a complex array refers + * to the number of complex values; the array contains twice this number of + * real values. + */ + +/** + * @defgroup groupFilters Filtering Functions + */ + +/** + * @defgroup groupMatrix Matrix Functions + * + * This set of functions provides basic matrix math operations. + * The functions operate on matrix data structures. For example, + * the type + * definition for the floating-point matrix structure is shown + * below: + * 
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ *
+ * There are similar definitions for Q15 and Q31 data types. + * + * The structure specifies the size of the matrix and then points to + * an array of data. The array is of size numRows X numCols + * and the values are arranged in row order. That is, the + * matrix element (i, j) is stored at: + * 
+ *     pData[i*numCols + j]
+ *
+ * + * \par Init Functions + * There is an associated initialization function for each type of matrix + * data structure. + * The initialization function sets the values of the internal structure fields. + * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() + * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. + * + * \par + * Use of the initialization function is optional. However, if initialization function is used + * then the instance structure cannot be placed into a const data section. + * To place the instance structure in a const data + * section, manually initialize the data structure. For example: + * 
+ * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+ *
+ * where nRows specifies the number of rows, nColumns + * specifies the number of columns, and pData points to the + * data array. + * + * \par Size Checking + * By default all of the matrix functions perform size checking on the input and + * output matrices. For example, the matrix addition function verifies that the + * two input matrices and the output matrix all have the same number of rows and + * columns. If the size check fails the functions return: + * 
+ *     ARM_MATH_SIZE_MISMATCH
+ *
+ * Otherwise the functions return + * 
+ *     ARM_MATH_SUCCESS
+ *
+ * There is some overhead associated with this matrix size checking. + * The matrix size checking is enabled via the \#define + * 
+ *     ARM_MATH_MATRIX_CHECK
+ *
+ * within the library project settings. By default this macro is defined + * and size checking is enabled. By changing the project settings and + * undefining this macro size checking is eliminated and the functions + * run a bit faster. With size checking disabled the functions always + * return ARM_MATH_SUCCESS. + */ + +/** + * @defgroup groupTransforms Transform Functions + */ + +/** + * @defgroup groupController Controller Functions + */ + +/** + * @defgroup groupStats Statistics Functions + */ +/** + * @defgroup groupSupport Support Functions + */ + +/** + * @defgroup groupInterpolation Interpolation Functions + * These functions perform 1- and 2-dimensional interpolation of data. + * Linear interpolation is used for 1-dimensional data and + * bilinear interpolation is used for 2-dimensional data. + */ + +/** + * @defgroup groupExamples Examples + */ +#ifndef _ARM_MATH_H +#define _ARM_MATH_H + +/* Compiler specific diagnostic adjustment */ +#if defined ( __CC_ARM ) + +#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + +#elif defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +#elif defined ( __ICCARM__ ) + +#elif defined ( __TI_ARM__ ) + +#elif defined ( __CSMC__ ) + +#elif defined ( __TASKING__ ) + +#else + #error Unknown compiler +#endif + + +#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ + +#if defined(ARM_MATH_CM7) + #include "core_cm7.h" + #define ARM_MATH_DSP +#elif defined (ARM_MATH_CM4) + #include "core_cm4.h" + #define ARM_MATH_DSP +#elif defined (ARM_MATH_CM33) + #include "core_cm33.h" + #define ARM_MATH_DSP +#elif defined (ARM_MATH_CM3) + #include "core_cm3.h" +#elif defined (ARM_MATH_CM0) + #include "core_cm0.h" + #define ARM_MATH_CM0_FAMILY +#elif defined (ARM_MATH_CM0PLUS) + #include "core_cm0plus.h" + #define ARM_MATH_CM0_FAMILY +#elif defined (ARM_MATH_ARMV8MBL) + #include "core_armv8mbl.h" + #define ARM_MATH_CM0_FAMILY +#elif defined (ARM_MATH_ARMV8MML) + #include "core_armv8mml.h" + #if (defined (__DSP_PRESENT) && (__DSP_PRESENT == 1)) + #define ARM_MATH_DSP + #endif +#else + #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS, ARM_MATH_CM0, ARM_MATH_ARMV8MBL, ARM_MATH_ARMV8MML" +#endif + +#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ +#include "string.h" +#include "math.h" +#ifdef __cplusplus +extern "C" +{ +#endif + + + /** + * @brief Macros required for reciprocal calculation in Normalized LMS + */ + +#define DELTA_Q31 (0x100) +#define DELTA_Q15 0x5 +#define INDEX_MASK 0x0000003F +#ifndef PI + #define PI 3.14159265358979f +#endif + + /** + * @brief Macros required for SINE and COSINE Fast math approximations + */ + +#define FAST_MATH_TABLE_SIZE 512 +#define FAST_MATH_Q31_SHIFT (32 - 10) +#define FAST_MATH_Q15_SHIFT (16 - 10) +#define CONTROLLER_Q31_SHIFT (32 - 9) +#define TABLE_SPACING_Q31 0x400000 +#define TABLE_SPACING_Q15 0x80 + + /** + * @brief Macros required for SINE and COSINE Controller functions + */ + /* 1.31(q31) Fixed value of 2/360 */ + /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ +#define INPUT_SPACING 0xB60B61 + + /** + * @brief Macro for Unaligned Support + */ +#ifndef UNALIGNED_SUPPORT_DISABLE + #define ALIGN4 +#else + #if defined (__GNUC__) + #define ALIGN4 __attribute__((aligned(4))) + #else + #define ALIGN4 __align(4) + #endif +#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ + + /** + * @brief Error status returned by some functions in the library. + */ + + typedef enum + { + ARM_MATH_SUCCESS = 0, /**< No error */ + ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ + ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ + ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ + ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ + ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ + ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ + } arm_status; + + /** + * @brief 8-bit fractional data type in 1.7 format. + */ + typedef int8_t q7_t; + + /** + * @brief 16-bit fractional data type in 1.15 format. + */ + typedef int16_t q15_t; + + /** + * @brief 32-bit fractional data type in 1.31 format. + */ + typedef int32_t q31_t; + + /** + * @brief 64-bit fractional data type in 1.63 format. + */ + typedef int64_t q63_t; + + /** + * @brief 32-bit floating-point type definition. + */ + typedef float float32_t; + + /** + * @brief 64-bit floating-point type definition. + */ + typedef double float64_t; + + /** + * @brief definition to read/write two 16 bit values. + */ +#if defined ( __CC_ARM ) + #define __SIMD32_TYPE int32_t __packed + #define CMSIS_UNUSED __attribute__((unused)) + #define CMSIS_INLINE __attribute__((always_inline)) + +#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED __attribute__((unused)) + #define CMSIS_INLINE __attribute__((always_inline)) + +#elif defined ( __GNUC__ ) + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED __attribute__((unused)) + #define CMSIS_INLINE __attribute__((always_inline)) + +#elif defined ( __ICCARM__ ) + #define __SIMD32_TYPE int32_t __packed + #define CMSIS_UNUSED + #define CMSIS_INLINE + +#elif defined ( __TI_ARM__ ) + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED __attribute__((unused)) + #define CMSIS_INLINE + +#elif defined ( __CSMC__ ) + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED + #define CMSIS_INLINE + +#elif defined ( __TASKING__ ) + #define __SIMD32_TYPE __unaligned int32_t + #define CMSIS_UNUSED + #define CMSIS_INLINE + +#else + #error Unknown compiler +#endif + +#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) +#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr)) +#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr)) +#define __SIMD64(addr) (*(int64_t **) & (addr)) + +#if !defined (ARM_MATH_DSP) + /** + * @brief definition to pack two 16 bit values. + */ +#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ + (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) +#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ + (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) + +#endif /* !defined (ARM_MATH_DSP) */ + + /** + * @brief definition to pack four 8 bit values. + */ +#ifndef ARM_MATH_BIG_ENDIAN + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) +#else + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) + +#endif + + + /** + * @brief Clips Q63 to Q31 values. + */ + CMSIS_INLINE __STATIC_INLINE q31_t clip_q63_to_q31( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; + } + + /** + * @brief Clips Q63 to Q15 values. + */ + CMSIS_INLINE __STATIC_INLINE q15_t clip_q63_to_q15( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); + } + + /** + * @brief Clips Q31 to Q7 values. + */ + CMSIS_INLINE __STATIC_INLINE q7_t clip_q31_to_q7( + q31_t x) + { + return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? + ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; + } + + /** + * @brief Clips Q31 to Q15 values. + */ + CMSIS_INLINE __STATIC_INLINE q15_t clip_q31_to_q15( + q31_t x) + { + return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? + ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; + } + + /** + * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. + */ + + CMSIS_INLINE __STATIC_INLINE q63_t mult32x64( + q63_t x, + q31_t y) + { + return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + + (((q63_t) (x >> 32) * y))); + } + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. + */ + + CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q31( + q31_t in, + q31_t * dst, + q31_t * pRecipTable) + { + q31_t out; + uint32_t tempVal; + uint32_t index, i; + uint32_t signBits; + + if (in > 0) + { + signBits = ((uint32_t) (__CLZ( in) - 1)); + } + else + { + signBits = ((uint32_t) (__CLZ(-in) - 1)); + } + + /* Convert input sample to 1.31 format */ + in = (in << signBits); + + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 24); + index = (index & INDEX_MASK); + + /* 1.31 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0U; i < 2U; i++) + { + tempVal = (uint32_t) (((q63_t) in * out) >> 31); + tempVal = 0x7FFFFFFFu - tempVal; + /* 1.31 with exp 1 */ + /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */ + out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1U); + } + + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. + */ + CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q15( + q15_t in, + q15_t * dst, + q15_t * pRecipTable) + { + q15_t out = 0; + uint32_t tempVal = 0; + uint32_t index = 0, i = 0; + uint32_t signBits = 0; + + if (in > 0) + { + signBits = ((uint32_t)(__CLZ( in) - 17)); + } + else + { + signBits = ((uint32_t)(__CLZ(-in) - 17)); + } + + /* Convert input sample to 1.15 format */ + in = (in << signBits); + + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 8); + index = (index & INDEX_MASK); + + /* 1.15 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0U; i < 2U; i++) + { + tempVal = (uint32_t) (((q31_t) in * out) >> 15); + tempVal = 0x7FFFu - tempVal; + /* 1.15 with exp 1 */ + out = (q15_t) (((q31_t) out * tempVal) >> 14); + /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */ + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1); + } + + +/* + * @brief C custom defined intrinsic function for M3 and M0 processors + */ +#if !defined (ARM_MATH_DSP) + + /* + * @brief C custom defined QADD8 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QADD8( + uint32_t x, + uint32_t y) + { + q31_t r, s, t, u; + + r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); + } + + + /* + * @brief C custom defined QSUB8 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB8( + uint32_t x, + uint32_t y) + { + q31_t r, s, t, u; + + r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); + } + + + /* + * @brief C custom defined QADD16 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QADD16( + uint32_t x, + uint32_t y) + { +/* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */ + q31_t r = 0, s = 0; + + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHADD16 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SHADD16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QSUB16 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHSUB16 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SHSUB16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QASX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QASX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHASX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SHASX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QSAX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QSAX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHSAX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SHSAX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SMUSDX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSDX( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); + } + + /* + * @brief C custom defined SMUADX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMUADX( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); + } + + + /* + * @brief C custom defined QADD for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE int32_t __QADD( + int32_t x, + int32_t y) + { + return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y))); + } + + + /* + * @brief C custom defined QSUB for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE int32_t __QSUB( + int32_t x, + int32_t y) + { + return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y))); + } + + + /* + * @brief C custom defined SMLAD for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMLAD( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLADX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMLADX( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLSDX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMLSDX( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLALD for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALD( + uint32_t x, + uint32_t y, + uint64_t sum) + { +/* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + + ( ((q63_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLALDX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALDX( + uint32_t x, + uint32_t y, + uint64_t sum) + { +/* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q63_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMUAD for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMUAD( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); + } + + + /* + * @brief C custom defined SMUSD for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSD( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); + } + + + /* + * @brief C custom defined SXTB16 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SXTB16( + uint32_t x) + { + return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) | + ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) )); + } + + /* + * @brief C custom defined SMMLA for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE int32_t __SMMLA( + int32_t x, + int32_t y, + int32_t sum) + { + return (sum + (int32_t) (((int64_t) x * y) >> 32)); + } + +#endif /* !defined (ARM_MATH_DSP) */ + + + /** + * @brief Instance structure for the Q7 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q7; + + /** + * @brief Instance structure for the Q15 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_f32; + + + /** + * @brief Processing function for the Q7 FIR filter. + * @param[in] S points to an instance of the Q7 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q7( + const arm_fir_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 FIR filter. + * @param[in,out] S points to an instance of the Q7 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed. + */ + void arm_fir_init_q7( + arm_fir_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR filter. + * @param[in] S points to an instance of the Q15 FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_fast_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR filter. + * @param[in,out] S points to an instance of the Q15 FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if + * numTaps is not a supported value. + */ + arm_status arm_fir_init_q15( + arm_fir_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR filter. + * @param[in] S points to an instance of the Q31 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_fast_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR filter. + * @param[in,out] S points to an instance of the Q31 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ + void arm_fir_init_q31( + arm_fir_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR filter. + * @param[in] S points to an instance of the floating-point FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_f32( + const arm_fir_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR filter. + * @param[in,out] S points to an instance of the floating-point FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ + void arm_fir_init_f32( + arm_fir_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 Biquad cascade filter. + */ + typedef struct + { + int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + } arm_biquad_casd_df1_inst_q15; + + /** + * @brief Instance structure for the Q31 Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + } arm_biquad_casd_df1_inst_q31; + + /** + * @brief Instance structure for the floating-point Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_casd_df1_inst_f32; + + + /** + * @brief Processing function for the Q15 Biquad cascade filter. + * @param[in] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 Biquad cascade filter. + * @param[in,out] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cascade_df1_init_q15( + arm_biquad_casd_df1_inst_q15 * S, + uint8_t numStages, + q15_t * pCoeffs, + q15_t * pState, + int8_t postShift); + + + /** + * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_fast_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 Biquad cascade filter + * @param[in] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_fast_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 Biquad cascade filter. + * @param[in,out] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cascade_df1_init_q31( + arm_biquad_casd_df1_inst_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q31_t * pState, + int8_t postShift); + + + /** + * @brief Processing function for the floating-point Biquad cascade filter. + * @param[in] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_f32( + const arm_biquad_casd_df1_inst_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point Biquad cascade filter. + * @param[in,out] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df1_init_f32( + arm_biquad_casd_df1_inst_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float32_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f32; + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float64_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f64; + + /** + * @brief Instance structure for the Q15 matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q15_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_q15; + + /** + * @brief Instance structure for the Q31 matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q31_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_q31; + + + /** + * @brief Floating-point matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_add_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_add_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_add_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_cmplx_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_cmplx_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pScratch); + + + /** + * @brief Q31, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_cmplx_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_trans_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_trans_q15( + const arm_matrix_instance_q15 * pSrc, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_trans_q31( + const arm_matrix_instance_q31 * pSrc, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + + /** + * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_fast_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + + /** + * @brief Q31 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_fast_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_sub_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_sub_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_sub_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix scaling. + * @param[in] pSrc points to the input matrix + * @param[in] scale scale factor + * @param[out] pDst points to the output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_scale_f32( + const arm_matrix_instance_f32 * pSrc, + float32_t scale, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix scaling. + * @param[in] pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_scale_q15( + const arm_matrix_instance_q15 * pSrc, + q15_t scaleFract, + int32_t shift, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix scaling. + * @param[in] pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_scale_q31( + const arm_matrix_instance_q31 * pSrc, + q31_t scaleFract, + int32_t shift, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Q31 matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ + void arm_mat_init_q31( + arm_matrix_instance_q31 * S, + uint16_t nRows, + uint16_t nColumns, + q31_t * pData); + + + /** + * @brief Q15 matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ + void arm_mat_init_q15( + arm_matrix_instance_q15 * S, + uint16_t nRows, + uint16_t nColumns, + q15_t * pData); + + + /** + * @brief Floating-point matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ + void arm_mat_init_f32( + arm_matrix_instance_f32 * S, + uint16_t nRows, + uint16_t nColumns, + float32_t * pData); + + + + /** + * @brief Instance structure for the Q15 PID Control. + */ + typedef struct + { + q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ +#if !defined (ARM_MATH_DSP) + q15_t A1; + q15_t A2; +#else + q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ +#endif + q15_t state[3]; /**< The state array of length 3. */ + q15_t Kp; /**< The proportional gain. */ + q15_t Ki; /**< The integral gain. */ + q15_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q15; + + /** + * @brief Instance structure for the Q31 PID Control. + */ + typedef struct + { + q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + q31_t A2; /**< The derived gain, A2 = Kd . */ + q31_t state[3]; /**< The state array of length 3. */ + q31_t Kp; /**< The proportional gain. */ + q31_t Ki; /**< The integral gain. */ + q31_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q31; + + /** + * @brief Instance structure for the floating-point PID Control. + */ + typedef struct + { + float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + float32_t A2; /**< The derived gain, A2 = Kd . */ + float32_t state[3]; /**< The state array of length 3. */ + float32_t Kp; /**< The proportional gain. */ + float32_t Ki; /**< The integral gain. */ + float32_t Kd; /**< The derivative gain. */ + } arm_pid_instance_f32; + + + + /** + * @brief Initialization function for the floating-point PID Control. + * @param[in,out] S points to an instance of the PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_f32( + arm_pid_instance_f32 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + */ + void arm_pid_reset_f32( + arm_pid_instance_f32 * S); + + + /** + * @brief Initialization function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_q31( + arm_pid_instance_q31 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q31 PID Control structure + */ + + void arm_pid_reset_q31( + arm_pid_instance_q31 * S); + + + /** + * @brief Initialization function for the Q15 PID Control. + * @param[in,out] S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_q15( + arm_pid_instance_q15 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q15 PID Control. + * @param[in,out] S points to an instance of the q15 PID Control structure + */ + void arm_pid_reset_q15( + arm_pid_instance_q15 * S); + + + /** + * @brief Instance structure for the floating-point Linear Interpolate function. + */ + typedef struct + { + uint32_t nValues; /**< nValues */ + float32_t x1; /**< x1 */ + float32_t xSpacing; /**< xSpacing */ + float32_t *pYData; /**< pointer to the table of Y values */ + } arm_linear_interp_instance_f32; + + /** + * @brief Instance structure for the floating-point bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + float32_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_f32; + + /** + * @brief Instance structure for the Q31 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q31_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q31; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q15_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q15; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q7_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q7; + + + /** + * @brief Q7 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q15( + arm_cfft_radix2_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q15( + const arm_cfft_radix2_instance_q15 * S, + q15_t * pSrc); + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q15( + arm_cfft_radix4_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_q15( + const arm_cfft_radix4_instance_q15 * S, + q15_t * pSrc); + + /** + * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q31; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q31( + arm_cfft_radix2_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q31( + const arm_cfft_radix2_instance_q31 * S, + q31_t * pSrc); + + /** + * @brief Instance structure for the Q31 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q31; + +/* Deprecated */ + void arm_cfft_radix4_q31( + const arm_cfft_radix4_instance_q31 * S, + q31_t * pSrc); + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q31( + arm_cfft_radix4_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix2_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_f32( + arm_cfft_radix2_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_f32( + const arm_cfft_radix2_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix4_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_f32( + arm_cfft_radix4_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_f32( + const arm_cfft_radix4_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q15_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_q15; + +void arm_cfft_q15( + const arm_cfft_instance_q15 * S, + q15_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_q31; + +void arm_cfft_q31( + const arm_cfft_instance_q31 * S, + q31_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_f32; + + void arm_cfft_f32( + const arm_cfft_instance_f32 * S, + float32_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the Q15 RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q15; + + arm_status arm_rfft_init_q15( + arm_rfft_instance_q15 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q15( + const arm_rfft_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst); + + /** + * @brief Instance structure for the Q31 RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q31; + + arm_status arm_rfft_init_q31( + arm_rfft_instance_q31 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q31( + const arm_rfft_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint16_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_f32; + + arm_status arm_rfft_init_f32( + arm_rfft_instance_f32 * S, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_f32( + const arm_rfft_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ +typedef struct + { + arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ + uint16_t fftLenRFFT; /**< length of the real sequence */ + float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ + } arm_rfft_fast_instance_f32 ; + +arm_status arm_rfft_fast_init_f32 ( + arm_rfft_fast_instance_f32 * S, + uint16_t fftLen); + +void arm_rfft_fast_f32( + arm_rfft_fast_instance_f32 * S, + float32_t * p, float32_t * pOut, + uint8_t ifftFlag); + + /** + * @brief Instance structure for the floating-point DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + float32_t normalize; /**< normalizing factor. */ + float32_t *pTwiddle; /**< points to the twiddle factor table. */ + float32_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_f32; + + + /** + * @brief Initialization function for the floating-point DCT4/IDCT4. + * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure. + * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. + */ + arm_status arm_dct4_init_f32( + arm_dct4_instance_f32 * S, + arm_rfft_instance_f32 * S_RFFT, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint16_t N, + uint16_t Nby2, + float32_t normalize); + + + /** + * @brief Processing function for the floating-point DCT4/IDCT4. + * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_f32( + const arm_dct4_instance_f32 * S, + float32_t * pState, + float32_t * pInlineBuffer); + + + /** + * @brief Instance structure for the Q31 DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q31_t normalize; /**< normalizing factor. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + q31_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q31; + + + /** + * @brief Initialization function for the Q31 DCT4/IDCT4. + * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure + * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + arm_status arm_dct4_init_q31( + arm_dct4_instance_q31 * S, + arm_rfft_instance_q31 * S_RFFT, + arm_cfft_radix4_instance_q31 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q31_t normalize); + + + /** + * @brief Processing function for the Q31 DCT4/IDCT4. + * @param[in] S points to an instance of the Q31 DCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_q31( + const arm_dct4_instance_q31 * S, + q31_t * pState, + q31_t * pInlineBuffer); + + + /** + * @brief Instance structure for the Q15 DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q15_t normalize; /**< normalizing factor. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + q15_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q15; + + + /** + * @brief Initialization function for the Q15 DCT4/IDCT4. + * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure. + * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + arm_status arm_dct4_init_q15( + arm_dct4_instance_q15 * S, + arm_rfft_instance_q15 * S_RFFT, + arm_cfft_radix4_instance_q15 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q15_t normalize); + + + /** + * @brief Processing function for the Q15 DCT4/IDCT4. + * @param[in] S points to an instance of the Q15 DCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_q15( + const arm_dct4_instance_q15 * S, + q15_t * pState, + q15_t * pInlineBuffer); + + + /** + * @brief Floating-point vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a floating-point vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scale scale factor to be applied + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_f32( + float32_t * pSrc, + float32_t scale, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q7 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q7( + q7_t * pSrc, + q7_t scaleFract, + int8_t shift, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q15 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q15( + q15_t * pSrc, + q15_t scaleFract, + int8_t shift, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q31 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q31( + q31_t * pSrc, + q31_t scaleFract, + int8_t shift, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Dot product of floating-point vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t blockSize, + float32_t * result); + + + /** + * @brief Dot product of Q7 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q7( + q7_t * pSrcA, + q7_t * pSrcB, + uint32_t blockSize, + q31_t * result); + + + /** + * @brief Dot product of Q15 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + + /** + * @brief Dot product of Q31 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + + /** + * @brief Shifts the elements of a Q7 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q7( + q7_t * pSrc, + int8_t shiftBits, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Shifts the elements of a Q15 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q15( + q15_t * pSrc, + int8_t shiftBits, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Shifts the elements of a Q31 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q31( + q31_t * pSrc, + int8_t shiftBits, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_f32( + float32_t * pSrc, + float32_t offset, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q7 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q7( + q7_t * pSrc, + q7_t offset, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q15 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q15( + q15_t * pSrc, + q15_t offset, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q31 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q31( + q31_t * pSrc, + q31_t offset, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q7 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q15 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q31 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a floating-point vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q7 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a floating-point vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_f32( + float32_t value, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q7 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q7( + q7_t value, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q15 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q15( + q15_t value, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q31 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q31( + q31_t value, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Convolution of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + */ + void arm_conv_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + */ + void arm_conv_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + */ + void arm_conv_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + */ + void arm_conv_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Convolution of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + */ + void arm_conv_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Partial convolution of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q7 sequences + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Partial convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Instance structure for the Q15 FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_f32; + + + /** + * @brief Processing function for the floating-point FIR decimator. + * @param[in] S points to an instance of the floating-point FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_f32( + const arm_fir_decimate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR decimator. + * @param[in,out] S points to an instance of the floating-point FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_f32( + arm_fir_decimate_instance_f32 * S, + uint16_t numTaps, + uint8_t M, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR decimator. + * @param[in] S points to an instance of the Q15 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_fast_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR decimator. + * @param[in,out] S points to an instance of the Q15 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_q15( + arm_fir_decimate_instance_q15 * S, + uint16_t numTaps, + uint8_t M, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR decimator. + * @param[in] S points to an instance of the Q31 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_q31( + const arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_fast_q31( + arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR decimator. + * @param[in,out] S points to an instance of the Q31 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_q31( + arm_fir_decimate_instance_q31 * S, + uint16_t numTaps, + uint8_t M, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ + } arm_fir_interpolate_instance_f32; + + + /** + * @brief Processing function for the Q15 FIR interpolator. + * @param[in] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_q15( + const arm_fir_interpolate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR interpolator. + * @param[in,out] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_q15( + arm_fir_interpolate_instance_q15 * S, + uint8_t L, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR interpolator. + * @param[in] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_q31( + const arm_fir_interpolate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR interpolator. + * @param[in,out] S points to an instance of the Q31 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_q31( + arm_fir_interpolate_instance_q31 * S, + uint8_t L, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR interpolator. + * @param[in] S points to an instance of the floating-point FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_f32( + const arm_fir_interpolate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR interpolator. + * @param[in,out] S points to an instance of the floating-point FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_f32( + arm_fir_interpolate_instance_f32 * S, + uint8_t L, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the high precision Q31 Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ + } arm_biquad_cas_df1_32x64_ins_q31; + + + /** + * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cas_df1_32x64_q31( + const arm_biquad_cas_df1_32x64_ins_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cas_df1_32x64_init_q31( + arm_biquad_cas_df1_32x64_ins_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q63_t * pState, + uint8_t postShift); + + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f32; + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_stereo_df2T_instance_f32; + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f64; + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df2T_f32( + const arm_biquad_cascade_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_stereo_df2T_f32( + const arm_biquad_cascade_stereo_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df2T_f64( + const arm_biquad_cascade_df2T_instance_f64 * S, + float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df2T_init_f32( + arm_biquad_cascade_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_stereo_df2T_init_f32( + arm_biquad_cascade_stereo_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df2T_init_f64( + arm_biquad_cascade_df2T_instance_f64 * S, + uint8_t numStages, + float64_t * pCoeffs, + float64_t * pState); + + + /** + * @brief Instance structure for the Q15 FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_f32; + + + /** + * @brief Initialization function for the Q15 FIR lattice filter. + * @param[in] S points to an instance of the Q15 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_q15( + arm_fir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pCoeffs, + q15_t * pState); + + + /** + * @brief Processing function for the Q15 FIR lattice filter. + * @param[in] S points to an instance of the Q15 FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_q15( + const arm_fir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR lattice filter. + * @param[in] S points to an instance of the Q31 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_q31( + arm_fir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pCoeffs, + q31_t * pState); + + + /** + * @brief Processing function for the Q31 FIR lattice filter. + * @param[in] S points to an instance of the Q31 FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_q31( + const arm_fir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the floating-point FIR lattice filter. + * @param[in] S points to an instance of the floating-point FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_f32( + arm_fir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Processing function for the floating-point FIR lattice filter. + * @param[in] S points to an instance of the floating-point FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_f32( + const arm_fir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_f32; + + + /** + * @brief Processing function for the floating-point IIR lattice filter. + * @param[in] S points to an instance of the floating-point IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_f32( + const arm_iir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point IIR lattice filter. + * @param[in] S points to an instance of the floating-point IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_init_f32( + arm_iir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pkCoeffs, + float32_t * pvCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 IIR lattice filter. + * @param[in] S points to an instance of the Q31 IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_q31( + const arm_iir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 IIR lattice filter. + * @param[in] S points to an instance of the Q31 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to the state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_init_q31( + arm_iir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pkCoeffs, + q31_t * pvCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 IIR lattice filter. + * @param[in] S points to an instance of the Q15 IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_q15( + const arm_iir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 IIR lattice filter. + * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process per call. + */ + void arm_iir_lattice_init_q15( + arm_iir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pkCoeffs, + q15_t * pvCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the floating-point LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that controls filter coefficient updates. */ + } arm_lms_instance_f32; + + + /** + * @brief Processing function for floating-point LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_f32( + const arm_lms_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for floating-point LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to the coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_init_f32( + arm_lms_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q15; + + + /** + * @brief Initialization function for the Q15 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to the coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_init_q15( + arm_lms_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint32_t postShift); + + + /** + * @brief Processing function for Q15 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_q15( + const arm_lms_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q31; + + + /** + * @brief Processing function for Q31 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_q31( + const arm_lms_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q31 LMS filter. + * @param[in] S points to an instance of the Q31 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_init_q31( + arm_lms_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint32_t postShift); + + + /** + * @brief Instance structure for the floating-point normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that control filter coefficient updates. */ + float32_t energy; /**< saves previous frame energy. */ + float32_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_f32; + + + /** + * @brief Processing function for floating-point normalized LMS filter. + * @param[in] S points to an instance of the floating-point normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_f32( + arm_lms_norm_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for floating-point normalized LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_init_f32( + arm_lms_norm_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q31_t *recipTable; /**< points to the reciprocal initial value table. */ + q31_t energy; /**< saves previous frame energy. */ + q31_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q31; + + + /** + * @brief Processing function for Q31 normalized LMS filter. + * @param[in] S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_q31( + arm_lms_norm_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q31 normalized LMS filter. + * @param[in] S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_norm_init_q31( + arm_lms_norm_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint8_t postShift); + + + /** + * @brief Instance structure for the Q15 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< Number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q15_t *recipTable; /**< Points to the reciprocal initial value table. */ + q15_t energy; /**< saves previous frame energy. */ + q15_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q15; + + + /** + * @brief Processing function for Q15 normalized LMS filter. + * @param[in] S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_q15( + arm_lms_norm_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q15 normalized LMS filter. + * @param[in] S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_norm_init_q15( + arm_lms_norm_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint8_t postShift); + + + /** + * @brief Correlation of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Correlation of Q15 sequences + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + */ + void arm_correlate_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + + /** + * @brief Correlation of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + + void arm_correlate_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + + void arm_correlate_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + */ + void arm_correlate_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + + /** + * @brief Correlation of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + */ + void arm_correlate_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Instance structure for the floating-point sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_f32; + + /** + * @brief Instance structure for the Q31 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q31; + + /** + * @brief Instance structure for the Q15 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q15; + + /** + * @brief Instance structure for the Q7 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q7; + + + /** + * @brief Processing function for the floating-point sparse FIR filter. + * @param[in] S points to an instance of the floating-point sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_f32( + arm_fir_sparse_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + float32_t * pScratchIn, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point sparse FIR filter. + * @param[in,out] S points to an instance of the floating-point sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_f32( + arm_fir_sparse_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 sparse FIR filter. + * @param[in] S points to an instance of the Q31 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q31( + arm_fir_sparse_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + q31_t * pScratchIn, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 sparse FIR filter. + * @param[in,out] S points to an instance of the Q31 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q31( + arm_fir_sparse_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 sparse FIR filter. + * @param[in] S points to an instance of the Q15 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q15( + arm_fir_sparse_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + q15_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 sparse FIR filter. + * @param[in,out] S points to an instance of the Q15 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q15( + arm_fir_sparse_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q7 sparse FIR filter. + * @param[in] S points to an instance of the Q7 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q7( + arm_fir_sparse_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + q7_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 sparse FIR filter. + * @param[in,out] S points to an instance of the Q7 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q7( + arm_fir_sparse_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Floating-point sin_cos function. + * @param[in] theta input value in degrees + * @param[out] pSinVal points to the processed sine output. + * @param[out] pCosVal points to the processed cos output. + */ + void arm_sin_cos_f32( + float32_t theta, + float32_t * pSinVal, + float32_t * pCosVal); + + + /** + * @brief Q31 sin_cos function. + * @param[in] theta scaled input value in degrees + * @param[out] pSinVal points to the processed sine output. + * @param[out] pCosVal points to the processed cosine output. + */ + void arm_sin_cos_q31( + q31_t theta, + q31_t * pSinVal, + q31_t * pCosVal); + + + /** + * @brief Floating-point complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup PID PID Motor Control + * + * A Proportional Integral Derivative (PID) controller is a generic feedback control + * loop mechanism widely used in industrial control systems. + * A PID controller is the most commonly used type of feedback controller. + * + * This set of functions implements (PID) controllers + * for Q15, Q31, and floating-point data types. The functions operate on a single sample + * of data and each call to the function returns a single processed value. + * S points to an instance of the PID control data structure. in + * is the input sample value. The functions return the output value. + * + * \par Algorithm: + * 
+   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd
+ * + * \par + * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant + * + * \par + * \image html PID.gif "Proportional Integral Derivative Controller" + * + * \par + * The PID controller calculates an "error" value as the difference between + * the measured output and the reference input. + * The controller attempts to minimize the error by adjusting the process control inputs. + * The proportional value determines the reaction to the current error, + * the integral value determines the reaction based on the sum of recent errors, + * and the derivative value determines the reaction based on the rate at which the error has been changing. + * + * \par Instance Structure + * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. + * A separate instance structure must be defined for each PID Controller. + * There are separate instance structure declarations for each of the 3 supported data types. + * + * \par Reset Functions + * There is also an associated reset function for each data type which clears the state array. + * + * \par Initialization Functions + * There is also an associated initialization function for each data type. + * The initialization function performs the following operations: + * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. + * - Zeros out the values in the state buffer. + * + * \par + * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. + * + * \par Fixed-Point Behavior + * Care must be taken when using the fixed-point versions of the PID Controller functions. + * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup PID + * @{ + */ + + /** + * @brief Process function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + */ + CMSIS_INLINE __STATIC_INLINE float32_t arm_pid_f32( + arm_pid_instance_f32 * S, + float32_t in) + { + float32_t out; + + /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ + out = (S->A0 * in) + + (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @brief Process function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q31 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 64-bit accumulator. + * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + * Thus, if the accumulator result overflows it wraps around rather than clip. + * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. + * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. + */ + CMSIS_INLINE __STATIC_INLINE q31_t arm_pid_q31( + arm_pid_instance_q31 * S, + q31_t in) + { + q63_t acc; + q31_t out; + + /* acc = A0 * x[n] */ + acc = (q63_t) S->A0 * in; + + /* acc += A1 * x[n-1] */ + acc += (q63_t) S->A1 * S->state[0]; + + /* acc += A2 * x[n-2] */ + acc += (q63_t) S->A2 * S->state[1]; + + /* convert output to 1.31 format to add y[n-1] */ + out = (q31_t) (acc >> 31U); + + /* out += y[n-1] */ + out += S->state[2]; + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + } + + + /** + * @brief Process function for the Q15 PID Control. + * @param[in,out] S points to an instance of the Q15 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using a 64-bit internal accumulator. + * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + * Lastly, the accumulator is saturated to yield a result in 1.15 format. + */ + CMSIS_INLINE __STATIC_INLINE q15_t arm_pid_q15( + arm_pid_instance_q15 * S, + q15_t in) + { + q63_t acc; + q15_t out; + +#if defined (ARM_MATH_DSP) + __SIMD32_TYPE *vstate; + + /* Implementation of PID controller */ + + /* acc = A0 * x[n] */ + acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in); + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + vstate = __SIMD32_CONST(S->state); + acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)*vstate, (uint64_t)acc); +#else + /* acc = A0 * x[n] */ + acc = ((q31_t) S->A0) * in; + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc += (q31_t) S->A1 * S->state[0]; + acc += (q31_t) S->A2 * S->state[1]; +#endif + + /* acc += y[n-1] */ + acc += (q31_t) S->state[2] << 15; + + /* saturate the output */ + out = (q15_t) (__SSAT((acc >> 15), 16)); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + } + + /** + * @} end of PID group + */ + + + /** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + arm_status arm_mat_inverse_f32( + const arm_matrix_instance_f32 * src, + arm_matrix_instance_f32 * dst); + + + /** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + arm_status arm_mat_inverse_f64( + const arm_matrix_instance_f64 * src, + arm_matrix_instance_f64 * dst); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup clarke Vector Clarke Transform + * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. + * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents + * in the two-phase orthogonal stator axis Ialpha and Ibeta. + * When Ialpha is superposed with Ia as shown in the figure below + * \image html clarke.gif Stator current space vector and its components in (a,b). + * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta + * can be calculated using only Ia and Ib. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeFormula.gif + * where Ia and Ib are the instantaneous stator phases and + * pIalpha and pIbeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup clarke + * @{ + */ + + /** + * + * @brief Floating-point Clarke transform + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + */ + CMSIS_INLINE __STATIC_INLINE void arm_clarke_f32( + float32_t Ia, + float32_t Ib, + float32_t * pIalpha, + float32_t * pIbeta) + { + /* Calculate pIalpha using the equation, pIalpha = Ia */ + *pIalpha = Ia; + + /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ + *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); + } + + + /** + * @brief Clarke transform for Q31 version + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + CMSIS_INLINE __STATIC_INLINE void arm_clarke_q31( + q31_t Ia, + q31_t Ib, + q31_t * pIalpha, + q31_t * pIbeta) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIalpha from Ia by equation pIalpha = Ia */ + *pIalpha = Ia; + + /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); + + /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ + product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); + + /* pIbeta is calculated by adding the intermediate products */ + *pIbeta = __QADD(product1, product2); + } + + /** + * @} end of clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_q7_to_q31( + q7_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_clarke Vector Inverse Clarke Transform + * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeInvFormula.gif + * where pIa and pIb are the instantaneous stator phases and + * Ialpha and Ibeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_clarke + * @{ + */ + + /** + * @brief Floating-point Inverse Clarke transform + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] pIa points to output three-phase coordinate a + * @param[out] pIb points to output three-phase coordinate b + */ + CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pIa, + float32_t * pIb) + { + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ + *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta; + } + + + /** + * @brief Inverse Clarke transform for Q31 version + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] pIa points to output three-phase coordinate a + * @param[out] pIb points to output three-phase coordinate b + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the subtraction, hence there is no risk of overflow. + */ + CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pIa, + q31_t * pIb) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); + + /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); + + /* pIb is calculated by subtracting the products */ + *pIb = __QSUB(product2, product1); + } + + /** + * @} end of inv_clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_q7_to_q15( + q7_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup park Vector Park Transform + * + * Forward Park transform converts the input two-coordinate vector to flux and torque components. + * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents + * from the stationary to the moving reference frame and control the spatial relationship between + * the stator vector current and rotor flux vector. + * If we consider the d axis aligned with the rotor flux, the diagram below shows the + * current vector and the relationship from the two reference frames: + * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkFormula.gif + * where Ialpha and Ibeta are the stator vector components, + * pId and pIq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup park + * @{ + */ + + /** + * @brief Floating-point Park transform + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] pId points to output rotor reference frame d + * @param[out] pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * The function implements the forward Park transform. + * + */ + CMSIS_INLINE __STATIC_INLINE void arm_park_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pId, + float32_t * pIq, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ + *pId = Ialpha * cosVal + Ibeta * sinVal; + + /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ + *pIq = -Ialpha * sinVal + Ibeta * cosVal; + } + + + /** + * @brief Park transform for Q31 version + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] pId points to output rotor reference frame d + * @param[out] pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition and subtraction, hence there is no risk of overflow. + */ + CMSIS_INLINE __STATIC_INLINE void arm_park_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pId, + q31_t * pIq, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Ialpha * cosVal) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * sinVal) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Ialpha * sinVal) */ + product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * cosVal) */ + product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); + + /* Calculate pId by adding the two intermediate products 1 and 2 */ + *pId = __QADD(product1, product2); + + /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ + *pIq = __QSUB(product4, product3); + } + + /** + * @} end of park group + */ + + /** + * @brief Converts the elements of the Q7 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q7_to_float( + q7_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_park Vector Inverse Park transform + * Inverse Park transform converts the input flux and torque components to two-coordinate vector. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkInvFormula.gif + * where pIalpha and pIbeta are the stator vector components, + * Id and Iq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_park + * @{ + */ + + /** + * @brief Floating-point Inverse Park transform + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + */ + CMSIS_INLINE __STATIC_INLINE void arm_inv_park_f32( + float32_t Id, + float32_t Iq, + float32_t * pIalpha, + float32_t * pIbeta, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ + *pIalpha = Id * cosVal - Iq * sinVal; + + /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ + *pIbeta = Id * sinVal + Iq * cosVal; + } + + + /** + * @brief Inverse Park transform for Q31 version + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + CMSIS_INLINE __STATIC_INLINE void arm_inv_park_q31( + q31_t Id, + q31_t Iq, + q31_t * pIalpha, + q31_t * pIbeta, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Id * cosVal) */ + product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Iq * sinVal) */ + product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Id * sinVal) */ + product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Iq * cosVal) */ + product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); + + /* Calculate pIalpha by using the two intermediate products 1 and 2 */ + *pIalpha = __QSUB(product1, product2); + + /* Calculate pIbeta by using the two intermediate products 3 and 4 */ + *pIbeta = __QADD(product4, product3); + } + + /** + * @} end of Inverse park group + */ + + + /** + * @brief Converts the elements of the Q31 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_float( + q31_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup LinearInterpolate Linear Interpolation + * + * Linear interpolation is a method of curve fitting using linear polynomials. + * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line + * + * \par + * \image html LinearInterp.gif "Linear interpolation" + * + * \par + * A Linear Interpolate function calculates an output value(y), for the input(x) + * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) + * + * \par Algorithm: + * 
+   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   *
+ * + * \par + * This set of functions implements Linear interpolation process + * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single + * sample of data and each call to the function returns a single processed value. + * S points to an instance of the Linear Interpolate function data structure. + * x is the input sample value. The functions returns the output value. + * + * \par + * if x is outside of the table boundary, Linear interpolation returns first value of the table + * if x is below input range and returns last value of table if x is above range. + */ + + /** + * @addtogroup LinearInterpolate + * @{ + */ + + /** + * @brief Process function for the floating-point Linear Interpolation Function. + * @param[in,out] S is an instance of the floating-point Linear Interpolation structure + * @param[in] x input sample to process + * @return y processed output sample. + * + */ + CMSIS_INLINE __STATIC_INLINE float32_t arm_linear_interp_f32( + arm_linear_interp_instance_f32 * S, + float32_t x) + { + float32_t y; + float32_t x0, x1; /* Nearest input values */ + float32_t y0, y1; /* Nearest output values */ + float32_t xSpacing = S->xSpacing; /* spacing between input values */ + int32_t i; /* Index variable */ + float32_t *pYData = S->pYData; /* pointer to output table */ + + /* Calculation of index */ + i = (int32_t) ((x - S->x1) / xSpacing); + + if (i < 0) + { + /* Iniatilize output for below specified range as least output value of table */ + y = pYData[0]; + } + else if ((uint32_t)i >= S->nValues) + { + /* Iniatilize output for above specified range as last output value of table */ + y = pYData[S->nValues - 1]; + } + else + { + /* Calculation of nearest input values */ + x0 = S->x1 + i * xSpacing; + x1 = S->x1 + (i + 1) * xSpacing; + + /* Read of nearest output values */ + y0 = pYData[i]; + y1 = pYData[i + 1]; + + /* Calculation of output */ + y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); + + } + + /* returns output value */ + return (y); + } + + + /** + * + * @brief Process function for the Q31 Linear Interpolation Function. + * @param[in] pYData pointer to Q31 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + CMSIS_INLINE __STATIC_INLINE q31_t arm_linear_interp_q31( + q31_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q31_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (q31_t)0xFFF00000) >> 20); + + if (index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if (index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* shift left by 11 to keep fract in 1.31 format */ + fract = (x & 0x000FFFFF) << 11; + + /* Read two nearest output values from the index in 1.31(q31) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract) and y is in 2.30 format */ + y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); + + /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ + y += ((q31_t) (((q63_t) y1 * fract) >> 32)); + + /* Convert y to 1.31 format */ + return (y << 1U); + } + } + + + /** + * + * @brief Process function for the Q15 Linear Interpolation Function. + * @param[in] pYData pointer to Q15 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + CMSIS_INLINE __STATIC_INLINE q15_t arm_linear_interp_q15( + q15_t * pYData, + q31_t x, + uint32_t nValues) + { + q63_t y; /* output */ + q15_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (int32_t)0xFFF00000) >> 20); + + if (index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if (index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract) and y is in 13.35 format */ + y = ((q63_t) y0 * (0xFFFFF - fract)); + + /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ + y += ((q63_t) y1 * (fract)); + + /* convert y to 1.15 format */ + return (q15_t) (y >> 20); + } + } + + + /** + * + * @brief Process function for the Q7 Linear Interpolation Function. + * @param[in] pYData pointer to Q7 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + */ + CMSIS_INLINE __STATIC_INLINE q7_t arm_linear_interp_q7( + q7_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q7_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + uint32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + if (x < 0) + { + return (pYData[0]); + } + index = (x >> 20) & 0xfff; + + if (index >= (nValues - 1)) + { + return (pYData[nValues - 1]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index and are in 1.7(q7) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ + y = ((y0 * (0xFFFFF - fract))); + + /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ + y += (y1 * fract); + + /* convert y to 1.7(q7) format */ + return (q7_t) (y >> 20); + } + } + + /** + * @} end of LinearInterpolate group + */ + + /** + * @brief Fast approximation to the trigonometric sine function for floating-point data. + * @param[in] x input value in radians. + * @return sin(x). + */ + float32_t arm_sin_f32( + float32_t x); + + + /** + * @brief Fast approximation to the trigonometric sine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + q31_t arm_sin_q31( + q31_t x); + + + /** + * @brief Fast approximation to the trigonometric sine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + q15_t arm_sin_q15( + q15_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for floating-point data. + * @param[in] x input value in radians. + * @return cos(x). + */ + float32_t arm_cos_f32( + float32_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + q31_t arm_cos_q31( + q31_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + q15_t arm_cos_q15( + q15_t x); + + + /** + * @ingroup groupFastMath + */ + + + /** + * @defgroup SQRT Square Root + * + * Computes the square root of a number. + * There are separate functions for Q15, Q31, and floating-point data types. + * The square root function is computed using the Newton-Raphson algorithm. + * This is an iterative algorithm of the form: + * 
+   *      x1 = x0 - f(x0)/f'(x0)
+   *
+ * where x1 is the current estimate, + * x0 is the previous estimate, and + * f'(x0) is the derivative of f() evaluated at x0. + * For the square root function, the algorithm reduces to: + * 
+   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   *
+ */ + + + /** + * @addtogroup SQRT + * @{ + */ + + /** + * @brief Floating-point square root function. + * @param[in] in input value. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + CMSIS_INLINE __STATIC_INLINE arm_status arm_sqrt_f32( + float32_t in, + float32_t * pOut) + { + if (in >= 0.0f) + { + +#if (__FPU_USED == 1) && defined ( __CC_ARM ) + *pOut = __sqrtf(in); +#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) + *pOut = __builtin_sqrtf(in); +#elif (__FPU_USED == 1) && defined(__GNUC__) + *pOut = __builtin_sqrtf(in); +#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000) + __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in)); +#else + *pOut = sqrtf(in); +#endif + + return (ARM_MATH_SUCCESS); + } + else + { + *pOut = 0.0f; + return (ARM_MATH_ARGUMENT_ERROR); + } + } + + + /** + * @brief Q31 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q31( + q31_t in, + q31_t * pOut); + + + /** + * @brief Q15 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q15( + q15_t in, + q15_t * pOut); + + /** + * @} end of SQRT group + */ + + + /** + * @brief floating-point Circular write function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_f32( + int32_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const int32_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + + /** + * @brief floating-point Circular Read function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularRead_f32( + int32_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + int32_t * dst, + int32_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == (int32_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q15 Circular write function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q15( + q15_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q15_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + /** + * @brief Q15 Circular Read function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q15( + q15_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q15_t * dst, + q15_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == (q15_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update wOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q7 Circular write function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q7( + q7_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q7_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + /** + * @brief Q7 Circular Read function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q7( + q7_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q7_t * dst, + q7_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == (q7_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Sum of the squares of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q31( + q31_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q15( + q15_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q7( + q7_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Mean value of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult); + + + /** + * @brief Mean value of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Mean value of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Mean value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Variance of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Variance of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Variance of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Standard deviation of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Standard deviation of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Standard deviation of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Floating-point complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t numSamples, + q31_t * realResult, + q31_t * imagResult); + + + /** + * @brief Q31 complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t numSamples, + q63_t * realResult, + q63_t * imagResult); + + + /** + * @brief Floating-point complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t numSamples, + float32_t * realResult, + float32_t * imagResult); + + + /** + * @brief Q15 complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_q15( + q15_t * pSrcCmplx, + q15_t * pSrcReal, + q15_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_q31( + q31_t * pSrcCmplx, + q31_t * pSrcReal, + q31_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_f32( + float32_t * pSrcCmplx, + float32_t * pSrcReal, + float32_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Minimum value of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] result is output pointer + * @param[in] index is the array index of the minimum value in the input buffer. + */ + void arm_min_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * result, + uint32_t * index); + + + /** + * @brief Minimum value of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[in] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Minimum value of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Minimum value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q7 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q15 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q31 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a floating-point vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Q15 complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Converts the elements of the floating-point vector to Q31 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q31 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q31( + float32_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the floating-point vector to Q15 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q15 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q15( + float32_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the floating-point vector to Q7 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q7 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q7( + float32_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q15 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_q15( + q31_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q7 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_q7( + q31_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_float( + q15_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q31 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_q31( + q15_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q7 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_q7( + q15_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup BilinearInterpolate Bilinear Interpolation + * + * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. + * The underlying function f(x, y) is sampled on a regular grid and the interpolation process + * determines values between the grid points. + * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. + * Bilinear interpolation is often used in image processing to rescale images. + * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. + * + * Algorithm + * \par + * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. + * For floating-point, the instance structure is defined as: + * 
+   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   *
+ * + * \par + * where numRows specifies the number of rows in the table; + * numCols specifies the number of columns in the table; + * and pData points to an array of size numRows*numCols values. + * The data table pTable is organized in row order and the supplied data values fall on integer indexes. + * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. + * + * \par + * Let (x, y) specify the desired interpolation point. Then define: + * 
+   *     XF = floor(x)
+   *     YF = floor(y)
+   *
+ * \par + * The interpolated output point is computed as: + * 
+   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   *
+ * Note that the coordinates (x, y) contain integer and fractional components. + * The integer components specify which portion of the table to use while the + * fractional components control the interpolation processor. + * + * \par + * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. + */ + + /** + * @addtogroup BilinearInterpolate + * @{ + */ + + + /** + * + * @brief Floating-point bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate. + * @param[in] Y interpolation coordinate. + * @return out interpolated value. + */ + CMSIS_INLINE __STATIC_INLINE float32_t arm_bilinear_interp_f32( + const arm_bilinear_interp_instance_f32 * S, + float32_t X, + float32_t Y) + { + float32_t out; + float32_t f00, f01, f10, f11; + float32_t *pData = S->pData; + int32_t xIndex, yIndex, index; + float32_t xdiff, ydiff; + float32_t b1, b2, b3, b4; + + xIndex = (int32_t) X; + yIndex = (int32_t) Y; + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1)) + { + return (0); + } + + /* Calculation of index for two nearest points in X-direction */ + index = (xIndex - 1) + (yIndex - 1) * S->numCols; + + + /* Read two nearest points in X-direction */ + f00 = pData[index]; + f01 = pData[index + 1]; + + /* Calculation of index for two nearest points in Y-direction */ + index = (xIndex - 1) + (yIndex) * S->numCols; + + + /* Read two nearest points in Y-direction */ + f10 = pData[index]; + f11 = pData[index + 1]; + + /* Calculation of intermediate values */ + b1 = f00; + b2 = f01 - f00; + b3 = f10 - f00; + b4 = f00 - f01 - f10 + f11; + + /* Calculation of fractional part in X */ + xdiff = X - xIndex; + + /* Calculation of fractional part in Y */ + ydiff = Y - yIndex; + + /* Calculation of bi-linear interpolated output */ + out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; + + /* return to application */ + return (out); + } + + + /** + * + * @brief Q31 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + CMSIS_INLINE __STATIC_INLINE q31_t arm_bilinear_interp_q31( + arm_bilinear_interp_instance_q31 * S, + q31_t X, + q31_t Y) + { + q31_t out; /* Temporary output */ + q31_t acc = 0; /* output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q31_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q31_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* shift left xfract by 11 to keep 1.31 format */ + xfract = (X & 0x000FFFFF) << 11U; + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + (int32_t)nCols * (cI) ]; + x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1]; + + /* 20 bits for the fractional part */ + /* shift left yfract by 11 to keep 1.31 format */ + yfract = (Y & 0x000FFFFF) << 11U; + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ]; + y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ + out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); + acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); + + /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); + + /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* Convert acc to 1.31(q31) format */ + return ((q31_t)(acc << 2)); + } + + + /** + * @brief Q15 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + CMSIS_INLINE __STATIC_INLINE q15_t arm_bilinear_interp_q15( + arm_bilinear_interp_instance_q15 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q15_t x1, x2, y1, y2; /* Nearest output values */ + q31_t xfract, yfract; /* X, Y fractional parts */ + int32_t rI, cI; /* Row and column indices */ + q15_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ + + /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ + /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ + out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4U); + acc = ((q63_t) out * (0xFFFFF - yfract)); + + /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4U); + acc += ((q63_t) out * (xfract)); + + /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4U); + acc += ((q63_t) out * (yfract)); + + /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y2 * (xfract)) >> 4U); + acc += ((q63_t) out * (yfract)); + + /* acc is in 13.51 format and down shift acc by 36 times */ + /* Convert out to 1.15 format */ + return ((q15_t)(acc >> 36)); + } + + + /** + * @brief Q7 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + CMSIS_INLINE __STATIC_INLINE q7_t arm_bilinear_interp_q7( + arm_bilinear_interp_instance_q7 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q7_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q7_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & (q31_t)0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & (q31_t)0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ + out = ((x1 * (0xFFFFF - xfract))); + acc = (((q63_t) out * (0xFFFFF - yfract))); + + /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ + out = ((x2 * (0xFFFFF - yfract))); + acc += (((q63_t) out * (xfract))); + + /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y1 * (0xFFFFF - xfract))); + acc += (((q63_t) out * (yfract))); + + /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y2 * (yfract))); + acc += (((q63_t) out * (xfract))); + + /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ + return ((q7_t)(acc >> 40)); + } + + /** + * @} end of BilinearInterpolate group + */ + + +/* SMMLAR */ +#define multAcc_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMLSR */ +#define multSub_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMULR */ +#define mult_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) + +/* SMMLA */ +#define multAcc_32x32_keep32(a, x, y) \ + a += (q31_t) (((q63_t) x * y) >> 32) + +/* SMMLS */ +#define multSub_32x32_keep32(a, x, y) \ + a -= (q31_t) (((q63_t) x * y) >> 32) + +/* SMMUL */ +#define mult_32x32_keep32(a, x, y) \ + a = (q31_t) (((q63_t) x * y ) >> 32) + + +#if defined ( __CC_ARM ) + /* Enter low optimization region - place directly above function definition */ + #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("push") \ + _Pragma ("O1") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) + #define LOW_OPTIMIZATION_EXIT \ + _Pragma ("pop") + #else + #define LOW_OPTIMIZATION_EXIT + #endif + + /* Enter low optimization region - place directly above function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + + /* Exit low optimization region - place directly after end of function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined (__ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __GNUC__ ) + #define LOW_OPTIMIZATION_ENTER \ + __attribute__(( optimize("-O1") )) + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __ICCARM__ ) + /* Enter low optimization region - place directly above function definition */ + #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #define LOW_OPTIMIZATION_EXIT + + /* Enter low optimization region - place directly above function definition */ + #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __TI_ARM__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __CSMC__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __TASKING__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#endif + + +#ifdef __cplusplus +} +#endif + +/* Compiler specific diagnostic adjustment */ +#if defined ( __CC_ARM ) + +#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + +#elif defined ( __GNUC__ ) +#pragma GCC diagnostic pop + +#elif defined ( __ICCARM__ ) + +#elif defined ( __TI_ARM__ ) + +#elif defined ( __CSMC__ ) + +#elif defined ( __TASKING__ ) + +#else + #error Unknown compiler +#endif + +#endif /* _ARM_MATH_H */ + +/** + * + * End of file. + */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/cmsis_armcc.h b/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/cmsis_armcc.h new file mode 100644 index 000000000..093d35b9e --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/cmsis_armcc.h @@ -0,0 +1,870 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use Arm Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ + (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) + #define __ARM_ARCH_6M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) + #define __ARM_ARCH_7M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) + #define __ARM_ARCH_7EM__ 1 +#endif + + /* __ARM_ARCH_8M_BASE__ not applicable */ + /* __ARM_ARCH_8M_MAIN__ not applicable */ + + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE static __forceinline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION __packed union +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1U); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() do {\ + __schedule_barrier();\ + __isb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() do {\ + __schedule_barrier();\ + __dsb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() do {\ + __schedule_barrier();\ + __dmb(0xF);\ + __schedule_barrier();\ + } while (0U) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return result; +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/cmsis_armclang.h b/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/cmsis_armclang.h new file mode 100644 index 000000000..5c4c20e87 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/cmsis_armclang.h @@ -0,0 +1,1877 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + register uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + register uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + register uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + register uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + +#endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF); + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF); + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF); + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ (uint8_t)__builtin_clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/cmsis_compiler.h b/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/cmsis_compiler.h new file mode 100644 index 000000000..94212eb87 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/cmsis_compiler.h @@ -0,0 +1,266 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/cmsis_gcc.h b/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/cmsis_gcc.h new file mode 100644 index 000000000..5d0f07e8a --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/cmsis_gcc.h @@ -0,0 +1,2088 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.0.3 + * @date 16. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + register uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + register uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + register uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + register uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + +#endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ (uint8_t)__builtin_clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ + __extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/cmsis_iccarm.h b/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/cmsis_iccarm.h new file mode 100644 index 000000000..edcaee3d4 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/cmsis_iccarm.h @@ -0,0 +1,913 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.0.5 + * @date 10. January 2018 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2018 IAR Systems +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #define __RESTRICT restrict +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE))) + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE))) + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc"); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (*ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (*ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (*ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/cmsis_version.h b/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/cmsis_version.h new file mode 100644 index 000000000..660f612aa --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.2 + * @date 19. April 2017 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/core_armv8mbl.h b/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/core_armv8mbl.h new file mode 100644 index 000000000..47a39893a --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/core_armv8mbl.h @@ -0,0 +1,1896 @@ +/**************************************************************************//** + * @file core_armv8mbl.h + * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV8MBL_H_GENERIC +#define __CORE_ARMV8MBL_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MBL + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M ( 2U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MBL_H_DEPENDANT +#define __CORE_ARMV8MBL_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MBL_REV + #define __ARMv8MBL_REV 0x0000U + #warning "__ARMv8MBL_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MBL */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Armv8-M Baseline */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Armv8-M Baseline */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/core_armv8mml.h b/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/core_armv8mml.h new file mode 100644 index 000000000..0951a1f78 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/core_armv8mml.h @@ -0,0 +1,2960 @@ +/**************************************************************************//** + * @file core_armv8mml.h + * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV8MML_H_GENERIC +#define __CORE_ARMV8MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MML + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS Armv8MML definitions */ +#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (81U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MML_H_DEPENDANT +#define __CORE_ARMV8MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MML_REV + #define __ARMv8MML_REV 0x0000U + #warning "__ARMv8MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/core_cm33.h b/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/core_cm33.h new file mode 100644 index 000000000..b1efbcae7 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/core_cm33.h @@ -0,0 +1,2963 @@ +/**************************************************************************//** + * @file core_cm33.h + * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File + * @version V5.0.5 + * @date 08. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM33_H_GENERIC +#define __CORE_CM33_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M33 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM33 definitions */ +#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ + __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (33U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_PCS_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM33_H_DEPENDANT +#define __CORE_CM33_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM33_REV + #define __CM33_REV 0x0000U + #warning "__CM33_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M33 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< @Deprecated TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< @Deprecated TPI ACPR: PRESCALER Mask */ + +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/core_dsp.h b/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/core_dsp.h new file mode 100644 index 000000000..6c21a47d8 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/core_dsp.h @@ -0,0 +1,74 @@ +/**************************************************************************//** + * @file cmsis_xcc.h + * @brief CMSIS DSP Core Peripheral Access Layer Header File + * @version V1.0 + * @date 20. January 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CORE_DSP_H_GENERIC +#define __CORE_DSP_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +#define __STATIC_INLINE static inline + +#define __BKPT(value) do {} while(0) +#define __NOP() do {} while(0) + +#define NVIC_SetPriorityGrouping(value) do {} while(0) +#define NVIC_GetPriorityGrouping() do {} while(0) +#define NVIC_EnableIRQ(value) do {} while(0) +#define NVIC_GetEnableIRQ(value) do {} while(0) +#define NVIC_DisableIRQ(value) do {} while(0) +#define NVIC_GetPendingIRQ(value) do {} while(0) +#define NVIC_SetPendingIRQ(value) do {} while(0) +#define NVIC_ClearPendingIRQ(value) do {} while(0) +#define NVIC_GetActive(value) do {} while(0) + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_DSP_H_GENERIC */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/mpu_armv8.h b/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/mpu_armv8.h new file mode 100644 index 000000000..0ccfc74fe --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/mpu_armv8.h @@ -0,0 +1,333 @@ +/****************************************************************************** + * @file mpu_armv8.h + * @brief CMSIS MPU API for Armv8-M MPU + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV8_H +#define ARM_MPU_ARMV8_H + +/** \brief Attribute for device memory (outer only) */ +#define ARM_MPU_ATTR_DEVICE ( 0U ) + +/** \brief Attribute for non-cacheable, normal memory */ +#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) + +/** \brief Attribute for normal memory (outer and inner) +* \param NT Non-Transient: Set to 1 for non-transient data. +* \param WB Write-Back: Set to 1 to use write-back update policy. +* \param RA Read Allocation: Set to 1 to use cache allocation on read miss. +* \param WA Write Allocation: Set to 1 to use cache allocation on write miss. +*/ +#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ + (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U)) + +/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) + +/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) + +/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGRE (2U) + +/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_GRE (3U) + +/** \brief Memory Attribute +* \param O Outer memory attributes +* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes +*/ +#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U))) + +/** \brief Normal memory non-shareable */ +#define ARM_MPU_SH_NON (0U) + +/** \brief Normal memory outer shareable */ +#define ARM_MPU_SH_OUTER (2U) + +/** \brief Normal memory inner shareable */ +#define ARM_MPU_SH_INNER (3U) + +/** \brief Memory access permissions +* \param RO Read-Only: Set to 1 for read-only memory. +* \param NP Non-Privileged: Set to 1 for non-privileged memory. +*/ +#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U)) + +/** \brief Region Base Address Register value +* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. +* \param SH Defines the Shareability domain for this memory region. +* \param RO Read-Only: Set to 1 for a read-only memory region. +* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. +* \oaram XN eXecute Never: Set to 1 for a non-executable memory region. +*/ +#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ + ((BASE & MPU_RBAR_BASE_Pos) | \ + ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ + ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ + ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) + +/** \brief Region Limit Address Register value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR(LIMIT, IDX) \ + ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ + ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; /*!< Region Base Address Register value */ + uint32_t RLAR; /*!< Region Limit Address Register value */ +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DSB(); + __ISB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DSB(); + __ISB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +#ifdef MPU_NS +/** Enable the Non-secure MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) +{ + __DSB(); + __ISB(); + MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif +} + +/** Disable the Non-secure MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable_NS(void) +{ + __DSB(); + __ISB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} +#endif + +/** Set the memory attribute encoding to the given MPU. +* \param mpu Pointer to the MPU to be configured. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) +{ + const uint8_t reg = idx / 4U; + const uint32_t pos = ((idx % 4U) * 8U); + const uint32_t mask = 0xFFU << pos; + + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { + return; // invalid index + } + + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); +} + +/** Set the memory attribute encoding. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU, idx, attr); +} + +#ifdef MPU_NS +/** Set the memory attribute encoding to the Non-secure MPU. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); +} +#endif + +/** Clear and disable the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) +{ + mpu->RNR = rnr; + mpu->RLAR = 0U; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU, rnr); +} + +#ifdef MPU_NS +/** Clear and disable the given Non-secure MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU_NS, rnr); +} +#endif + +/** Configure the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + mpu->RNR = rnr; + mpu->RBAR = rbar; + mpu->RLAR = rlar; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); +} + +#ifdef MPU_NS +/** Configure the given Non-secure MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); +} +#endif + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table to the given MPU. +* \param mpu Pointer to the MPU registers to be used. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + if (cnt == 1U) { + mpu->RNR = rnr; + orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); + } else { + uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); + uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; + + mpu->RNR = rnrBase; + while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { + uint32_t c = MPU_TYPE_RALIASES - rnrOffset; + orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); + table += c; + cnt -= c; + rnrOffset = 0U; + rnrBase += MPU_TYPE_RALIASES; + mpu->RNR = rnrBase; + } + + orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); + } +} + +/** Load the given number of MPU regions from a table. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU, rnr, table, cnt); +} + +#ifdef MPU_NS +/** Load the given number of MPU regions from a table to the Non-secure MPU. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); +} +#endif + +#endif + diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/tz_context.h b/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/tz_context.h new file mode 100644 index 000000000..0d09749f3 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/tz_context.h @@ -0,0 +1,70 @@ +/****************************************************************************** + * @file tz_context.h + * @brief Context Management for Armv8-M TrustZone + * @version V1.0.1 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef TZ_CONTEXT_H +#define TZ_CONTEXT_H + +#include + +#ifndef TZ_MODULEID_T +#define TZ_MODULEID_T +/// \details Data type that identifies secure software modules called by a process. +typedef uint32_t TZ_ModuleId_t; +#endif + +/// \details TZ Memory ID identifies an allocated memory slot. +typedef uint32_t TZ_MemoryId_t; + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +uint32_t TZ_InitContextSystem_S (void); + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); + +#endif // TZ_CONTEXT_H diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/LICENSE.txt b/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/LICENSE.txt new file mode 100644 index 000000000..8dada3eda --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/LICENSE.txt @@ -0,0 +1,201 @@ + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. 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b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/LPC55S69_cm33_core0.h @@ -0,0 +1,25766 @@ +/* +** ################################################################### +** Processors: LPC55S69JBD100_cm33_core0 +** LPC55S69JBD64_cm33_core0 +** LPC55S69JET98_cm33_core0 +** +** Compilers: GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.4 25 Sep 2018 +** Version: rev. 1.0, 2018-08-22 +** Build: b190430 +** +** Abstract: +** CMSIS Peripheral Access Layer for LPC55S69_cm33_core0 +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2019 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2018-08-22) +** Initial version based on v0.2UM +** +** ################################################################### +*/ + +/*! + * @file LPC55S69_cm33_core0.h + * @version 1.0 + * @date 2018-08-22 + * @brief CMSIS Peripheral Access Layer for LPC55S69_cm33_core0 + * + * CMSIS Peripheral Access Layer for LPC55S69_cm33_core0 + */ + +#ifndef _LPC55S69_CM33_CORE0_H_ +#define _LPC55S69_CM33_CORE0_H_ /**< Symbol preventing repeated inclusion */ + +/** Memory map major version (memory maps with equal major version number are + * compatible) */ +#define MCU_MEM_MAP_VERSION 0x0100U +/** Memory map minor version */ +#define MCU_MEM_MAP_VERSION_MINOR 0x0000U + + +/* ---------------------------------------------------------------------------- + -- Interrupt vector numbers + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Interrupt_vector_numbers Interrupt vector numbers + * @{ + */ + +/** Interrupt Number Definitions */ +#define NUMBER_OF_INT_VECTORS 76 /**< Number of interrupts in the Vector table */ + +typedef enum IRQn { + /* Auxiliary constants */ + NotAvail_IRQn = -128, /**< Not available device specific interrupt */ + + /* Core interrupts */ + NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< Cortex-M33 SV Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /**< Cortex-M33 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< Cortex-M33 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< Cortex-M33 Usage Fault Interrupt */ + SecureFault_IRQn = -9, /**< Cortex-M33 Secure Fault Interrupt */ + SVCall_IRQn = -5, /**< Cortex-M33 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< Cortex-M33 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< Cortex-M33 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< Cortex-M33 System Tick Interrupt */ + + /* Device specific interrupts */ + WDT_BOD_IRQn = 0, /**< Windowed watchdog timer, Brownout detect, Flash interrupt */ + DMA0_IRQn = 1, /**< DMA0 controller */ + GINT0_IRQn = 2, /**< GPIO group 0 */ + GINT1_IRQn = 3, /**< GPIO group 1 */ + PIN_INT0_IRQn = 4, /**< Pin interrupt 0 or pattern match engine slice 0 */ + PIN_INT1_IRQn = 5, /**< Pin interrupt 1or pattern match engine slice 1 */ + PIN_INT2_IRQn = 6, /**< Pin interrupt 2 or pattern match engine slice 2 */ + PIN_INT3_IRQn = 7, /**< Pin interrupt 3 or pattern match engine slice 3 */ + UTICK0_IRQn = 8, /**< Micro-tick Timer */ + MRT0_IRQn = 9, /**< Multi-rate timer */ + CTIMER0_IRQn = 10, /**< Standard counter/timer CTIMER0 */ + CTIMER1_IRQn = 11, /**< Standard counter/timer CTIMER1 */ + SCT0_IRQn = 12, /**< SCTimer/PWM */ + CTIMER3_IRQn = 13, /**< Standard counter/timer CTIMER3 */ + FLEXCOMM0_IRQn = 14, /**< Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) */ + FLEXCOMM1_IRQn = 15, /**< Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) */ + FLEXCOMM2_IRQn = 16, /**< Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) */ + FLEXCOMM3_IRQn = 17, /**< Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) */ + FLEXCOMM4_IRQn = 18, /**< Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) */ + FLEXCOMM5_IRQn = 19, /**< Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) */ + FLEXCOMM6_IRQn = 20, /**< Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) */ + FLEXCOMM7_IRQn = 21, /**< Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) */ + ADC0_IRQn = 22, /**< ADC0 */ + Reserved39_IRQn = 23, /**< Reserved interrupt */ + ACMP_IRQn = 24, /**< ACMP interrupts */ + Reserved41_IRQn = 25, /**< Reserved interrupt */ + Reserved42_IRQn = 26, /**< Reserved interrupt */ + USB0_NEEDCLK_IRQn = 27, /**< USB Activity Wake-up Interrupt */ + USB0_IRQn = 28, /**< USB device */ + RTC_IRQn = 29, /**< RTC alarm and wake-up interrupts */ + Reserved46_IRQn = 30, /**< Reserved interrupt */ + MAILBOX_IRQn = 31, /**< WAKEUP,Mailbox interrupt (present on selected devices) */ + PIN_INT4_IRQn = 32, /**< Pin interrupt 4 or pattern match engine slice 4 int */ + PIN_INT5_IRQn = 33, /**< Pin interrupt 5 or pattern match engine slice 5 int */ + PIN_INT6_IRQn = 34, /**< Pin interrupt 6 or pattern match engine slice 6 int */ + PIN_INT7_IRQn = 35, /**< Pin interrupt 7 or pattern match engine slice 7 int */ + CTIMER2_IRQn = 36, /**< Standard counter/timer CTIMER2 */ + CTIMER4_IRQn = 37, /**< Standard counter/timer CTIMER4 */ + OS_EVENT_IRQn = 38, /**< OSEVTIMER0 and OSEVTIMER0_WAKEUP interrupts */ + Reserved55_IRQn = 39, /**< Reserved interrupt */ + Reserved56_IRQn = 40, /**< Reserved interrupt */ + Reserved57_IRQn = 41, /**< Reserved interrupt */ + SDIO_IRQn = 42, /**< SD/MMC */ + Reserved59_IRQn = 43, /**< Reserved interrupt */ + Reserved60_IRQn = 44, /**< Reserved interrupt */ + Reserved61_IRQn = 45, /**< Reserved interrupt */ + USB1_UTMI_IRQn = 46, /**< USB1_UTMI */ + USB1_IRQn = 47, /**< USB1 interrupt */ + USB1_NEEDCLK_IRQn = 48, /**< USB1 activity */ + SEC_HYPERVISOR_CALL_IRQn = 49, /**< SEC_HYPERVISOR_CALL interrupt */ + SEC_GPIO_INT0_IRQ0_IRQn = 50, /**< SEC_GPIO_INT0_IRQ0 interrupt */ + SEC_GPIO_INT0_IRQ1_IRQn = 51, /**< SEC_GPIO_INT0_IRQ1 interrupt */ + PLU_IRQn = 52, /**< PLU interrupt */ + SEC_VIO_IRQn = 53, /**< SEC_VIO interrupt */ + HASHCRYPT_IRQn = 54, /**< HASHCRYPT interrupt */ + CASER_IRQn = 55, /**< CASPER interrupt */ + PUF_IRQn = 56, /**< PUF interrupt */ + PQ_IRQn = 57, /**< PQ interrupt */ + DMA1_IRQn = 58, /**< DMA1 interrupt */ + FLEXCOMM8_IRQn = 59 /**< Flexcomm Interface 8 (SPI, , FLEXCOMM) */ +} IRQn_Type; + +/*! + * @} + */ /* end of group Interrupt_vector_numbers */ + + +/* ---------------------------------------------------------------------------- + -- Cortex M33 Core Configuration + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Cortex_Core_Configuration Cortex M33 Core Configuration + * @{ + */ + +#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */ +#define __NVIC_PRIO_BITS 3 /**< Number of priority bits implemented in the NVIC */ +#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ +#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ +#define __DSP_PRESENT 1 /**< Defines if Armv8-M Mainline core supports DSP instructions */ +#define __SAUREGION_PRESENT 1 /**< Defines if an SAU is present or not */ + +#include "core_cm33.h" /* Core Peripheral Access Layer */ +#include "system_LPC55S69_cm33_core0.h" /* Device specific configuration file */ + +/*! + * @} + */ /* end of group Cortex_Core_Configuration */ + + +/* ---------------------------------------------------------------------------- + -- Mapping Information + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Mapping_Information Mapping Information + * @{ + */ + +/** Mapping Information */ +/*! + * @addtogroup dma_request + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @brief Structure for the DMA hardware request + * + * Defines the structure for the DMA hardware request collections. The user can configure the + * hardware request to trigger the DMA transfer accordingly. The index + * of the hardware request varies according to the to SoC. + */ +typedef enum _dma_request_source +{ + kDma0RequestHashCrypt = 0U, /**< HashCrypt */ + kDma1RequestHashCrypt = 0U, /**< HashCrypt */ + kDma0RequestNoDMARequest1 = 1U, /**< No DMA request 1 */ + kDma1RequestNoDMARequest1 = 1U, /**< No DMA request 1 */ + kDma0RequestFlexcomm8Rx = 2U, /**< Flexcomm Interface 8 RX */ + kDma1RequestFlexcomm8Rx = 2U, /**< Flexcomm Interface 8 RX */ + kDma0RequestFlexcomm8Tx = 3U, /**< Flexcomm Interface 8 TX */ + kDma1RequestFlexcomm8Tx = 3U, /**< Flexcomm Interface 8 TX */ + kDma0RequestFlexcomm0Rx = 4U, /**< Flexcomm Interface 0 RX/I2C Slave */ + kDma1RequestFlexcomm0Rx = 4U, /**< Flexcomm Interface 0 RX/I2C Slave */ + kDma0RequestFlexcomm0Tx = 5U, /**< Flexcomm Interface 0 TX/I2C Master */ + kDma1RequestFlexcomm0Tx = 5U, /**< Flexcomm Interface 0 TX/I2C Master */ + kDma0RequestFlexcomm1Rx = 6U, /**< Flexcomm Interface 1 RX/I2C Slave */ + kDma1RequestFlexcomm1Rx = 6U, /**< Flexcomm Interface 1 RX/I2C Slave */ + kDma0RequestFlexcomm1Tx = 7U, /**< Flexcomm Interface 1 TX/I2C Master */ + kDma1RequestFlexcomm1Tx = 7U, /**< Flexcomm Interface 1 TX/I2C Master */ + kDma0RequestFlexcomm3Rx = 8U, /**< Flexcomm Interface 3 RX/I2C Slave */ + kDma1RequestFlexcomm2Rx = 8U, /**< Flexcomm Interface 2 RX/I2C Slave */ + kDma0RequestFlexcomm3Tx = 9U, /**< Flexcomm Interface 3 TX/I2C Master */ + kDma1RequestFlexcomm2Tx = 9U, /**< Flexcomm Interface 2 TX/I2C Master */ + kDma0RequestFlexcomm2Rx = 10U, /**< Flexcomm Interface 2 RX/I2C Slave */ + kDma0RequestFlexcomm2Tx = 11U, /**< Flexcomm Interface 2 TX/I2C Master */ + kDma0RequestFlexcomm4Rx = 12U, /**< Flexcomm Interface 4 RX/I2C Slave */ + kDma0RequestFlexcomm4Tx = 13U, /**< Flexcomm Interface 4 TX/I2C Master */ + kDma0RequestFlexcomm5Rx = 14U, /**< Flexcomm Interface 5 RX/I2C Slave */ + kDma0RequestFlexcomm5Tx = 15U, /**< Flexcomm Interface 5 TX/I2C Master */ + kDma0RequestFlexcomm6Rx = 16U, /**< Flexcomm Interface 6 RX/I2C Slave */ + kDma0RequestFlexcomm6Tx = 17U, /**< Flexcomm Interface 6 TX/I2C Master */ + kDma0RequestFlexcomm7Rx = 18U, /**< Flexcomm Interface 7 RX/I2C Slave */ + kDma0RequestFlexcomm7Tx = 19U, /**< Flexcomm Interface 7 TX/I2C Master */ + kDma0RequestNoDMARequest20 = 20U, /**< No DMA request 20 */ + kDma0RequestADC0FIFO0 = 21U, /**< ADC0 FIFO 0 */ + kDma0RequestADC0FIFO1 = 22U, /**< ADC0 FIFO 1 */ +} dma_request_source_t; + +/* @} */ + + +/*! + * @} + */ /* end of group Mapping_Information */ + + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- ADC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer + * @{ + */ + +/** ADC - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ + uint8_t RESERVED_0[8]; + __IO uint32_t CTRL; /**< ADC Control Register, offset: 0x10 */ + __IO uint32_t STAT; /**< ADC Status Register, offset: 0x14 */ + __IO uint32_t IE; /**< Interrupt Enable Register, offset: 0x18 */ + __IO uint32_t DE; /**< DMA Enable Register, offset: 0x1C */ + __IO uint32_t CFG; /**< ADC Configuration Register, offset: 0x20 */ + __IO uint32_t PAUSE; /**< ADC Pause Register, offset: 0x24 */ + uint8_t RESERVED_1[12]; + __IO uint32_t SWTRIG; /**< Software Trigger Register, offset: 0x34 */ + __IO uint32_t TSTAT; /**< Trigger Status Register, offset: 0x38 */ + uint8_t RESERVED_2[4]; + __IO uint32_t OFSTRIM; /**< ADC Offset Trim Register, offset: 0x40 */ + uint8_t RESERVED_3[92]; + __IO uint32_t TCTRL[16]; /**< Trigger Control Register, array offset: 0xA0, array step: 0x4 */ + __IO uint32_t FCTRL[2]; /**< FIFO Control Register, array offset: 0xE0, array step: 0x4 */ + uint8_t RESERVED_4[8]; + __I uint32_t GCC[2]; /**< Gain Calibration Control, array offset: 0xF0, array step: 0x4 */ + __IO uint32_t GCR[2]; /**< Gain Calculation Result, array offset: 0xF8, array step: 0x4 */ + struct { /* offset: 0x100, array step: 0x8 */ + __IO uint32_t CMDL; /**< ADC Command Low Buffer Register, array offset: 0x100, array step: 0x8 */ + __IO uint32_t CMDH; /**< ADC Command High Buffer Register, array offset: 0x104, array step: 0x8 */ + } CMD[15]; + uint8_t RESERVED_5[136]; + __IO uint32_t CV[4]; /**< Compare Value Register, array offset: 0x200, array step: 0x4 */ + uint8_t RESERVED_6[240]; + __I uint32_t RESFIFO[2]; /**< ADC Data Result FIFO Register, array offset: 0x300, array step: 0x4 */ + uint8_t RESERVED_7[248]; + __IO uint32_t CAL_GAR[33]; /**< Calibration General A-Side Registers, array offset: 0x400, array step: 0x4 */ + uint8_t RESERVED_8[124]; + __IO uint32_t CAL_GBR[33]; /**< Calibration General B-Side Registers, array offset: 0x500, array step: 0x4 */ + uint8_t RESERVED_9[2680]; + __IO uint32_t TST; /**< ADC Test Register, offset: 0xFFC */ +} ADC_Type; + +/* ---------------------------------------------------------------------------- + -- ADC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Register_Masks ADC Register Masks + * @{ + */ + +/*! @name VERID - Version ID Register */ +/*! @{ */ +#define ADC_VERID_RES_MASK (0x1U) +#define ADC_VERID_RES_SHIFT (0U) +/*! RES - Resolution + * 0b0..Up to 13-bit differential/12-bit single ended resolution supported. + * 0b1..Up to 16-bit differential/16-bit single ended resolution supported. + */ +#define ADC_VERID_RES(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_RES_SHIFT)) & ADC_VERID_RES_MASK) +#define ADC_VERID_DIFFEN_MASK (0x2U) +#define ADC_VERID_DIFFEN_SHIFT (1U) +/*! DIFFEN - Differential Supported + * 0b0..Differential operation not supported. + * 0b1..Differential operation supported. CMDLa[CTYPE] controls fields implemented. + */ +#define ADC_VERID_DIFFEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_DIFFEN_SHIFT)) & ADC_VERID_DIFFEN_MASK) +#define ADC_VERID_MVI_MASK (0x8U) +#define ADC_VERID_MVI_SHIFT (3U) +/*! MVI - Multi Vref Implemented + * 0b0..Single voltage reference high (VREFH) input supported. + * 0b1..Multiple voltage reference high (VREFH) inputs supported. + */ +#define ADC_VERID_MVI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MVI_SHIFT)) & ADC_VERID_MVI_MASK) +#define ADC_VERID_CSW_MASK (0x70U) +#define ADC_VERID_CSW_SHIFT (4U) +/*! CSW - Channel Scale Width + * 0b000..Channel scaling not supported. + * 0b001..Channel scaling supported. 1-bit CSCALE control field. + * 0b110..Channel scaling supported. 6-bit CSCALE control field. + */ +#define ADC_VERID_CSW(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CSW_SHIFT)) & ADC_VERID_CSW_MASK) +#define ADC_VERID_VR1RNGI_MASK (0x100U) +#define ADC_VERID_VR1RNGI_SHIFT (8U) +/*! VR1RNGI - Voltage Reference 1 Range Control Bit Implemented + * 0b0..Range control not required. CFG[VREF1RNG] is not implemented. + * 0b1..Range control required. CFG[VREF1RNG] is implemented. + */ +#define ADC_VERID_VR1RNGI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_VR1RNGI_SHIFT)) & ADC_VERID_VR1RNGI_MASK) +#define ADC_VERID_IADCKI_MASK (0x200U) +#define ADC_VERID_IADCKI_SHIFT (9U) +/*! IADCKI - Internal ADC Clock implemented + * 0b0..Internal clock source not implemented. + * 0b1..Internal clock source (and CFG[ADCKEN]) implemented. + */ +#define ADC_VERID_IADCKI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_IADCKI_SHIFT)) & ADC_VERID_IADCKI_MASK) +#define ADC_VERID_CALOFSI_MASK (0x400U) +#define ADC_VERID_CALOFSI_SHIFT (10U) +/*! CALOFSI - Calibration Function Implemented + * 0b0..Calibration Not Implemented. + * 0b1..Calibration Implemented. + */ +#define ADC_VERID_CALOFSI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CALOFSI_SHIFT)) & ADC_VERID_CALOFSI_MASK) +#define ADC_VERID_NUM_SEC_MASK (0x800U) +#define ADC_VERID_NUM_SEC_SHIFT (11U) +/*! NUM_SEC - Number of Single Ended Outputs Supported + * 0b0..This design supports one single ended conversion at a time. + * 0b1..This design supports two simultanious single ended conversions. + */ +#define ADC_VERID_NUM_SEC(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_SEC_SHIFT)) & ADC_VERID_NUM_SEC_MASK) +#define ADC_VERID_NUM_FIFO_MASK (0x7000U) +#define ADC_VERID_NUM_FIFO_SHIFT (12U) +/*! NUM_FIFO - Number of FIFOs + * 0b000..N/A + * 0b001..This design supports one result FIFO. + * 0b010..This design supports two result FIFOs. + * 0b011..This design supports three result FIFOs. + * 0b100..This design supports four result FIFOs. + */ +#define ADC_VERID_NUM_FIFO(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_FIFO_SHIFT)) & ADC_VERID_NUM_FIFO_MASK) +#define ADC_VERID_MINOR_MASK (0xFF0000U) +#define ADC_VERID_MINOR_SHIFT (16U) +#define ADC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MINOR_SHIFT)) & ADC_VERID_MINOR_MASK) +#define ADC_VERID_MAJOR_MASK (0xFF000000U) +#define ADC_VERID_MAJOR_SHIFT (24U) +#define ADC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MAJOR_SHIFT)) & ADC_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter Register */ +/*! @{ */ +#define ADC_PARAM_TRIG_NUM_MASK (0xFFU) +#define ADC_PARAM_TRIG_NUM_SHIFT (0U) +#define ADC_PARAM_TRIG_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_TRIG_NUM_SHIFT)) & ADC_PARAM_TRIG_NUM_MASK) +#define ADC_PARAM_FIFOSIZE_MASK (0xFF00U) +#define ADC_PARAM_FIFOSIZE_SHIFT (8U) +/*! FIFOSIZE - Result FIFO Depth + * 0b00000001..Result FIFO depth = 1 dataword. + * 0b00000100..Result FIFO depth = 4 datawords. + * 0b00001000..Result FIFO depth = 8 datawords. + * 0b00010000..Result FIFO depth = 16 datawords. + * 0b00100000..Result FIFO depth = 32 datawords. + * 0b01000000..Result FIFO depth = 64 datawords. + */ +#define ADC_PARAM_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_FIFOSIZE_SHIFT)) & ADC_PARAM_FIFOSIZE_MASK) +#define ADC_PARAM_CV_NUM_MASK (0xFF0000U) +#define ADC_PARAM_CV_NUM_SHIFT (16U) +#define ADC_PARAM_CV_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CV_NUM_SHIFT)) & ADC_PARAM_CV_NUM_MASK) +#define ADC_PARAM_CMD_NUM_MASK (0xFF000000U) +#define ADC_PARAM_CMD_NUM_SHIFT (24U) +#define ADC_PARAM_CMD_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CMD_NUM_SHIFT)) & ADC_PARAM_CMD_NUM_MASK) +/*! @} */ + +/*! @name CTRL - ADC Control Register */ +/*! @{ */ +#define ADC_CTRL_ADCEN_MASK (0x1U) +#define ADC_CTRL_ADCEN_SHIFT (0U) +/*! ADCEN - ADC Enable + * 0b0..ADC is disabled. + * 0b1..ADC is enabled. + */ +#define ADC_CTRL_ADCEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ADCEN_SHIFT)) & ADC_CTRL_ADCEN_MASK) +#define ADC_CTRL_RST_MASK (0x2U) +#define ADC_CTRL_RST_SHIFT (1U) +/*! RST - Software Reset + * 0b0..ADC logic is not reset. + * 0b1..ADC logic is reset. + */ +#define ADC_CTRL_RST(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RST_SHIFT)) & ADC_CTRL_RST_MASK) +#define ADC_CTRL_DOZEN_MASK (0x4U) +#define ADC_CTRL_DOZEN_SHIFT (2U) +/*! DOZEN - Doze Enable + * 0b0..ADC is enabled in Doze mode. + * 0b1..ADC is disabled in Doze mode. + */ +#define ADC_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_DOZEN_SHIFT)) & ADC_CTRL_DOZEN_MASK) +#define ADC_CTRL_CAL_REQ_MASK (0x8U) +#define ADC_CTRL_CAL_REQ_SHIFT (3U) +/*! CAL_REQ - Auto-Calibration Request + * 0b0..No request for auto-calibration has been made. + * 0b1..A request for auto-calibration has been made + */ +#define ADC_CTRL_CAL_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CAL_REQ_SHIFT)) & ADC_CTRL_CAL_REQ_MASK) +#define ADC_CTRL_CALOFS_MASK (0x10U) +#define ADC_CTRL_CALOFS_SHIFT (4U) +/*! CALOFS - Configure for offset calibration function + * 0b0..Calibration function disabled + * 0b1..Request for offset calibration function + */ +#define ADC_CTRL_CALOFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CALOFS_SHIFT)) & ADC_CTRL_CALOFS_MASK) +#define ADC_CTRL_RSTFIFO0_MASK (0x100U) +#define ADC_CTRL_RSTFIFO0_SHIFT (8U) +/*! RSTFIFO0 - Reset FIFO 0 + * 0b0..No effect. + * 0b1..FIFO 0 is reset. + */ +#define ADC_CTRL_RSTFIFO0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO0_SHIFT)) & ADC_CTRL_RSTFIFO0_MASK) +#define ADC_CTRL_RSTFIFO1_MASK (0x200U) +#define ADC_CTRL_RSTFIFO1_SHIFT (9U) +/*! RSTFIFO1 - Reset FIFO 1 + * 0b0..No effect. + * 0b1..FIFO 1 is reset. + */ +#define ADC_CTRL_RSTFIFO1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO1_SHIFT)) & ADC_CTRL_RSTFIFO1_MASK) +#define ADC_CTRL_CAL_AVGS_MASK (0x70000U) +#define ADC_CTRL_CAL_AVGS_SHIFT (16U) +/*! CAL_AVGS - Auto-Calibration Averages + * 0b000..Single conversion. + * 0b001..2 conversions averaged. + * 0b010..4 conversions averaged. + * 0b011..8 conversions averaged. + * 0b100..16 conversions averaged. + * 0b101..32 conversions averaged. + * 0b110..64 conversions averaged. + * 0b111..128 conversions averaged. + */ +#define ADC_CTRL_CAL_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CAL_AVGS_SHIFT)) & ADC_CTRL_CAL_AVGS_MASK) +/*! @} */ + +/*! @name STAT - ADC Status Register */ +/*! @{ */ +#define ADC_STAT_RDY0_MASK (0x1U) +#define ADC_STAT_RDY0_SHIFT (0U) +/*! RDY0 - Result FIFO 0 Ready Flag + * 0b0..Result FIFO 0 data level not above watermark level. + * 0b1..Result FIFO 0 holding data above watermark level. + */ +#define ADC_STAT_RDY0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY0_SHIFT)) & ADC_STAT_RDY0_MASK) +#define ADC_STAT_FOF0_MASK (0x2U) +#define ADC_STAT_FOF0_SHIFT (1U) +/*! FOF0 - Result FIFO 0 Overflow Flag + * 0b0..No result FIFO 0 overflow has occurred since the last time the flag was cleared. + * 0b1..At least one result FIFO 0 overflow has occurred since the last time the flag was cleared. + */ +#define ADC_STAT_FOF0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF0_SHIFT)) & ADC_STAT_FOF0_MASK) +#define ADC_STAT_RDY1_MASK (0x4U) +#define ADC_STAT_RDY1_SHIFT (2U) +/*! RDY1 - Result FIFO1 Ready Flag + * 0b0..Result FIFO1 data level not above watermark level. + * 0b1..Result FIFO1 holding data above watermark level. + */ +#define ADC_STAT_RDY1(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY1_SHIFT)) & ADC_STAT_RDY1_MASK) +#define ADC_STAT_FOF1_MASK (0x8U) +#define ADC_STAT_FOF1_SHIFT (3U) +/*! FOF1 - Result FIFO1 Overflow Flag + * 0b0..No result FIFO1 overflow has occurred since the last time the flag was cleared. + * 0b1..At least one result FIFO1 overflow has occurred since the last time the flag was cleared. + */ +#define ADC_STAT_FOF1(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF1_SHIFT)) & ADC_STAT_FOF1_MASK) +#define ADC_STAT_TEXC_INT_MASK (0x100U) +#define ADC_STAT_TEXC_INT_SHIFT (8U) +/*! TEXC_INT - Interrupt Flag For High Priority Trigger Exception + * 0b0..No trigger exceptions have occurred. + * 0b1..A trigger exception has occurred and is pending acknowledgement. + */ +#define ADC_STAT_TEXC_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TEXC_INT_SHIFT)) & ADC_STAT_TEXC_INT_MASK) +#define ADC_STAT_TCOMP_INT_MASK (0x200U) +#define ADC_STAT_TCOMP_INT_SHIFT (9U) +/*! TCOMP_INT - Interrupt Flag For Trigger Completion + * 0b0..Either IE[TCOMP_IE] is set to 0, or no trigger sequences have run to completion. + * 0b1..Trigger sequence has been completed and all data is stored in the associated FIFO. + */ +#define ADC_STAT_TCOMP_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TCOMP_INT_SHIFT)) & ADC_STAT_TCOMP_INT_MASK) +#define ADC_STAT_CAL_RDY_MASK (0x400U) +#define ADC_STAT_CAL_RDY_SHIFT (10U) +/*! CAL_RDY - Calibration Ready + * 0b0..Calibration is incomplete or hasn't been ran. + * 0b1..The ADC is calibrated. + */ +#define ADC_STAT_CAL_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CAL_RDY_SHIFT)) & ADC_STAT_CAL_RDY_MASK) +#define ADC_STAT_ADC_ACTIVE_MASK (0x800U) +#define ADC_STAT_ADC_ACTIVE_SHIFT (11U) +/*! ADC_ACTIVE - ADC Active + * 0b0..The ADC is IDLE. There are no pending triggers to service and no active commands are being processed. + * 0b1..The ADC is processing a conversion, running through the power up delay, or servicing a trigger. + */ +#define ADC_STAT_ADC_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_ADC_ACTIVE_SHIFT)) & ADC_STAT_ADC_ACTIVE_MASK) +#define ADC_STAT_TRGACT_MASK (0xF0000U) +#define ADC_STAT_TRGACT_SHIFT (16U) +/*! TRGACT - Trigger Active + * 0b0000..Command (sequence) associated with Trigger 0 currently being executed. + * 0b0001..Command (sequence) associated with Trigger 1 currently being executed. + * 0b0010..Command (sequence) associated with Trigger 2 currently being executed. + * 0b0011-0b1111..Command (sequence) from the associated Trigger number is currently being executed. + */ +#define ADC_STAT_TRGACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TRGACT_SHIFT)) & ADC_STAT_TRGACT_MASK) +#define ADC_STAT_CMDACT_MASK (0xF000000U) +#define ADC_STAT_CMDACT_SHIFT (24U) +/*! CMDACT - Command Active + * 0b0000..No command is currently in progress. + * 0b0001..Command 1 currently being executed. + * 0b0010..Command 2 currently being executed. + * 0b0011-0b1111..Associated command number is currently being executed. + */ +#define ADC_STAT_CMDACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CMDACT_SHIFT)) & ADC_STAT_CMDACT_MASK) +/*! @} */ + +/*! @name IE - Interrupt Enable Register */ +/*! @{ */ +#define ADC_IE_FWMIE0_MASK (0x1U) +#define ADC_IE_FWMIE0_SHIFT (0U) +/*! FWMIE0 - FIFO 0 Watermark Interrupt Enable + * 0b0..FIFO 0 watermark interrupts are not enabled. + * 0b1..FIFO 0 watermark interrupts are enabled. + */ +#define ADC_IE_FWMIE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE0_SHIFT)) & ADC_IE_FWMIE0_MASK) +#define ADC_IE_FOFIE0_MASK (0x2U) +#define ADC_IE_FOFIE0_SHIFT (1U) +/*! FOFIE0 - Result FIFO 0 Overflow Interrupt Enable + * 0b0..FIFO 0 overflow interrupts are not enabled. + * 0b1..FIFO 0 overflow interrupts are enabled. + */ +#define ADC_IE_FOFIE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE0_SHIFT)) & ADC_IE_FOFIE0_MASK) +#define ADC_IE_FWMIE1_MASK (0x4U) +#define ADC_IE_FWMIE1_SHIFT (2U) +/*! FWMIE1 - FIFO1 Watermark Interrupt Enable + * 0b0..FIFO1 watermark interrupts are not enabled. + * 0b1..FIFO1 watermark interrupts are enabled. + */ +#define ADC_IE_FWMIE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE1_SHIFT)) & ADC_IE_FWMIE1_MASK) +#define ADC_IE_FOFIE1_MASK (0x8U) +#define ADC_IE_FOFIE1_SHIFT (3U) +/*! FOFIE1 - Result FIFO1 Overflow Interrupt Enable + * 0b0..No result FIFO1 overflow has occurred since the last time the flag was cleared. + * 0b1..At least one result FIFO1 overflow has occurred since the last time the flag was cleared. + */ +#define ADC_IE_FOFIE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE1_SHIFT)) & ADC_IE_FOFIE1_MASK) +#define ADC_IE_TEXC_IE_MASK (0x100U) +#define ADC_IE_TEXC_IE_SHIFT (8U) +/*! TEXC_IE - Trigger Exception Interrupt Enable + * 0b0..Trigger exception interrupts are disabled. + * 0b1..Trigger exception interrupts are enabled. + */ +#define ADC_IE_TEXC_IE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_TEXC_IE_SHIFT)) & ADC_IE_TEXC_IE_MASK) +#define ADC_IE_TCOMP_IE_MASK (0xFFFF0000U) +#define ADC_IE_TCOMP_IE_SHIFT (16U) +/*! TCOMP_IE - Trigger Completion Interrupt Enable + * 0b0000000000000000..Trigger completion interrupts are disabled. + * 0b0000000000000001..Trigger completion interrupts are enabled for trigger source 0 only. + * 0b0000000000000010..Trigger completion interrupts are enabled for trigger source 1 only. + * 0b0000000000000011-0b1111111111111110..Associated trigger completion interrupts are enabled. + * 0b1111111111111111..Trigger completion interrupts are enabled for every trigger source. + */ +#define ADC_IE_TCOMP_IE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_TCOMP_IE_SHIFT)) & ADC_IE_TCOMP_IE_MASK) +/*! @} */ + +/*! @name DE - DMA Enable Register */ +/*! @{ */ +#define ADC_DE_FWMDE0_MASK (0x1U) +#define ADC_DE_FWMDE0_SHIFT (0U) +/*! FWMDE0 - FIFO 0 Watermark DMA Enable + * 0b0..DMA request disabled. + * 0b1..DMA request enabled. + */ +#define ADC_DE_FWMDE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE0_SHIFT)) & ADC_DE_FWMDE0_MASK) +#define ADC_DE_FWMDE1_MASK (0x2U) +#define ADC_DE_FWMDE1_SHIFT (1U) +/*! FWMDE1 - FIFO1 Watermark DMA Enable + * 0b0..DMA request disabled. + * 0b1..DMA request enabled. + */ +#define ADC_DE_FWMDE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE1_SHIFT)) & ADC_DE_FWMDE1_MASK) +/*! @} */ + +/*! @name CFG - ADC Configuration Register */ +/*! @{ */ +#define ADC_CFG_TPRICTRL_MASK (0x3U) +#define ADC_CFG_TPRICTRL_SHIFT (0U) +/*! TPRICTRL - ADC trigger priority control + * 0b00..If a higher priority trigger is detected during command processing, the current conversion is aborted + * and the new command specified by the trigger is started. + * 0b01..If a higher priority trigger is received during command processing, the current command is stopped after + * after completing the current conversion. If averaging is enabled, the averaging loop will be completed. + * However, CMDHa[LOOP] will be ignored and the higher priority trigger will be serviced. + * 0b10..If a higher priority trigger is received during command processing, the current command will be + * completed (averaging, looping, compare) before servicing the higher priority trigger. + * 0b11..RESERVED + */ +#define ADC_CFG_TPRICTRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TPRICTRL_SHIFT)) & ADC_CFG_TPRICTRL_MASK) +#define ADC_CFG_PWRSEL_MASK (0x30U) +#define ADC_CFG_PWRSEL_SHIFT (4U) +/*! PWRSEL - Power Configuration Select + * 0b00..Lowest power setting. + * 0b01..Higher power setting than 0b0. + * 0b10..Higher power setting than 0b1. + * 0b11..Highest power setting. + */ +#define ADC_CFG_PWRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWRSEL_SHIFT)) & ADC_CFG_PWRSEL_MASK) +#define ADC_CFG_REFSEL_MASK (0xC0U) +#define ADC_CFG_REFSEL_SHIFT (6U) +/*! REFSEL - Voltage Reference Selection + * 0b00..(Default) Option 1 setting. + * 0b01..Option 2 setting. + * 0b10..Option 3 setting. + * 0b11..Reserved + */ +#define ADC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK) +#define ADC_CFG_TRES_MASK (0x100U) +#define ADC_CFG_TRES_SHIFT (8U) +/*! TRES - Trigger Resume Enable + * 0b0..Trigger sequences interrupted by a high priority trigger exception will not be automatically resumed or restarted. + * 0b1..Trigger sequences interrupted by a high priority trigger exception will be automatically resumed or restarted. + */ +#define ADC_CFG_TRES(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TRES_SHIFT)) & ADC_CFG_TRES_MASK) +#define ADC_CFG_TCMDRES_MASK (0x200U) +#define ADC_CFG_TCMDRES_SHIFT (9U) +/*! TCMDRES - Trigger Command Resume + * 0b0..Trigger sequences interrupted by a high priority trigger exception will be automatically restarted. + * 0b1..Trigger sequences interrupted by a high priority trigger exception will be resumed from the command executing before the exception. + */ +#define ADC_CFG_TCMDRES(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TCMDRES_SHIFT)) & ADC_CFG_TCMDRES_MASK) +#define ADC_CFG_HPT_EXDI_MASK (0x400U) +#define ADC_CFG_HPT_EXDI_SHIFT (10U) +/*! HPT_EXDI - High Priority Trigger Exception Disable + * 0b0..High priority trigger exceptions are enabled. + * 0b1..High priority trigger exceptions are disabled. + */ +#define ADC_CFG_HPT_EXDI(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_HPT_EXDI_SHIFT)) & ADC_CFG_HPT_EXDI_MASK) +#define ADC_CFG_PUDLY_MASK (0xFF0000U) +#define ADC_CFG_PUDLY_SHIFT (16U) +#define ADC_CFG_PUDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PUDLY_SHIFT)) & ADC_CFG_PUDLY_MASK) +#define ADC_CFG_PWREN_MASK (0x10000000U) +#define ADC_CFG_PWREN_SHIFT (28U) +/*! PWREN - ADC Analog Pre-Enable + * 0b0..ADC analog circuits are only enabled while conversions are active. Performance is affected due to analog startup delays. + * 0b1..ADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the cost + * of higher DC current consumption). A single power up delay (CFG[PUDLY]) is executed immediately once PWREN + * is set, and any detected trigger does not begin ADC operation until the power up delay time has passed. + * After this initial delay expires the analog will remain pre-enabled, and no additional delays will be + * executed. + */ +#define ADC_CFG_PWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWREN_SHIFT)) & ADC_CFG_PWREN_MASK) +/*! @} */ + +/*! @name PAUSE - ADC Pause Register */ +/*! @{ */ +#define ADC_PAUSE_PAUSEDLY_MASK (0x1FFU) +#define ADC_PAUSE_PAUSEDLY_SHIFT (0U) +#define ADC_PAUSE_PAUSEDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEDLY_SHIFT)) & ADC_PAUSE_PAUSEDLY_MASK) +#define ADC_PAUSE_PAUSEEN_MASK (0x80000000U) +#define ADC_PAUSE_PAUSEEN_SHIFT (31U) +/*! PAUSEEN - PAUSE Option Enable + * 0b0..Pause operation disabled + * 0b1..Pause operation enabled + */ +#define ADC_PAUSE_PAUSEEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEEN_SHIFT)) & ADC_PAUSE_PAUSEEN_MASK) +/*! @} */ + +/*! @name SWTRIG - Software Trigger Register */ +/*! @{ */ +#define ADC_SWTRIG_SWT0_MASK (0x1U) +#define ADC_SWTRIG_SWT0_SHIFT (0U) +/*! SWT0 - Software trigger 0 event + * 0b0..No trigger 0 event generated. + * 0b1..Trigger 0 event generated. + */ +#define ADC_SWTRIG_SWT0(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT0_SHIFT)) & ADC_SWTRIG_SWT0_MASK) +#define ADC_SWTRIG_SWT1_MASK (0x2U) +#define ADC_SWTRIG_SWT1_SHIFT (1U) +/*! SWT1 - Software trigger 1 event + * 0b0..No trigger 1 event generated. + * 0b1..Trigger 1 event generated. + */ +#define ADC_SWTRIG_SWT1(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT1_SHIFT)) & ADC_SWTRIG_SWT1_MASK) +#define ADC_SWTRIG_SWT2_MASK (0x4U) +#define ADC_SWTRIG_SWT2_SHIFT (2U) +/*! SWT2 - Software trigger 2 event + * 0b0..No trigger 2 event generated. + * 0b1..Trigger 2 event generated. + */ +#define ADC_SWTRIG_SWT2(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT2_SHIFT)) & ADC_SWTRIG_SWT2_MASK) +#define ADC_SWTRIG_SWT3_MASK (0x8U) +#define ADC_SWTRIG_SWT3_SHIFT (3U) +/*! SWT3 - Software trigger 3 event + * 0b0..No trigger 3 event generated. + * 0b1..Trigger 3 event generated. + */ +#define ADC_SWTRIG_SWT3(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT3_SHIFT)) & ADC_SWTRIG_SWT3_MASK) +#define ADC_SWTRIG_SWT4_MASK (0x10U) +#define ADC_SWTRIG_SWT4_SHIFT (4U) +/*! SWT4 - Software trigger 4 event + * 0b0..No trigger 4 event generated. + * 0b1..Trigger 4 event generated. + */ +#define ADC_SWTRIG_SWT4(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT4_SHIFT)) & ADC_SWTRIG_SWT4_MASK) +#define ADC_SWTRIG_SWT5_MASK (0x20U) +#define ADC_SWTRIG_SWT5_SHIFT (5U) +/*! SWT5 - Software trigger 5 event + * 0b0..No trigger 5 event generated. + * 0b1..Trigger 5 event generated. + */ +#define ADC_SWTRIG_SWT5(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT5_SHIFT)) & ADC_SWTRIG_SWT5_MASK) +#define ADC_SWTRIG_SWT6_MASK (0x40U) +#define ADC_SWTRIG_SWT6_SHIFT (6U) +/*! SWT6 - Software trigger 6 event + * 0b0..No trigger 6 event generated. + * 0b1..Trigger 6 event generated. + */ +#define ADC_SWTRIG_SWT6(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT6_SHIFT)) & ADC_SWTRIG_SWT6_MASK) +#define ADC_SWTRIG_SWT7_MASK (0x80U) +#define ADC_SWTRIG_SWT7_SHIFT (7U) +/*! SWT7 - Software trigger 7 event + * 0b0..No trigger 7 event generated. + * 0b1..Trigger 7 event generated. + */ +#define ADC_SWTRIG_SWT7(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT7_SHIFT)) & ADC_SWTRIG_SWT7_MASK) +#define ADC_SWTRIG_SWT8_MASK (0x100U) +#define ADC_SWTRIG_SWT8_SHIFT (8U) +/*! SWT8 - Software trigger 8 event + * 0b0..No trigger 8 event generated. + * 0b1..Trigger 8 event generated. + */ +#define ADC_SWTRIG_SWT8(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT8_SHIFT)) & ADC_SWTRIG_SWT8_MASK) +#define ADC_SWTRIG_SWT9_MASK (0x200U) +#define ADC_SWTRIG_SWT9_SHIFT (9U) +/*! SWT9 - Software trigger 9 event + * 0b0..No trigger 9 event generated. + * 0b1..Trigger 9 event generated. + */ +#define ADC_SWTRIG_SWT9(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT9_SHIFT)) & ADC_SWTRIG_SWT9_MASK) +#define ADC_SWTRIG_SWT10_MASK (0x400U) +#define ADC_SWTRIG_SWT10_SHIFT (10U) +/*! SWT10 - Software trigger 10 event + * 0b0..No trigger 10 event generated. + * 0b1..Trigger 10 event generated. + */ +#define ADC_SWTRIG_SWT10(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT10_SHIFT)) & ADC_SWTRIG_SWT10_MASK) +#define ADC_SWTRIG_SWT11_MASK (0x800U) +#define ADC_SWTRIG_SWT11_SHIFT (11U) +/*! SWT11 - Software trigger 11 event + * 0b0..No trigger 11 event generated. + * 0b1..Trigger 11 event generated. + */ +#define ADC_SWTRIG_SWT11(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT11_SHIFT)) & ADC_SWTRIG_SWT11_MASK) +#define ADC_SWTRIG_SWT12_MASK (0x1000U) +#define ADC_SWTRIG_SWT12_SHIFT (12U) +/*! SWT12 - Software trigger 12 event + * 0b0..No trigger 12 event generated. + * 0b1..Trigger 12 event generated. + */ +#define ADC_SWTRIG_SWT12(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT12_SHIFT)) & ADC_SWTRIG_SWT12_MASK) +#define ADC_SWTRIG_SWT13_MASK (0x2000U) +#define ADC_SWTRIG_SWT13_SHIFT (13U) +/*! SWT13 - Software trigger 13 event + * 0b0..No trigger 13 event generated. + * 0b1..Trigger 13 event generated. + */ +#define ADC_SWTRIG_SWT13(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT13_SHIFT)) & ADC_SWTRIG_SWT13_MASK) +#define ADC_SWTRIG_SWT14_MASK (0x4000U) +#define ADC_SWTRIG_SWT14_SHIFT (14U) +/*! SWT14 - Software trigger 14 event + * 0b0..No trigger 14 event generated. + * 0b1..Trigger 14 event generated. + */ +#define ADC_SWTRIG_SWT14(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT14_SHIFT)) & ADC_SWTRIG_SWT14_MASK) +#define ADC_SWTRIG_SWT15_MASK (0x8000U) +#define ADC_SWTRIG_SWT15_SHIFT (15U) +/*! SWT15 - Software trigger 15 event + * 0b0..No trigger 15 event generated. + * 0b1..Trigger 15 event generated. + */ +#define ADC_SWTRIG_SWT15(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT15_SHIFT)) & ADC_SWTRIG_SWT15_MASK) +/*! @} */ + +/*! @name TSTAT - Trigger Status Register */ +/*! @{ */ +#define ADC_TSTAT_TEXC_NUM_MASK (0xFFFFU) +#define ADC_TSTAT_TEXC_NUM_SHIFT (0U) +/*! TEXC_NUM - Trigger Exception Number + * 0b0000000000000000..No triggers have been interrupted by a high priority exception. Or CFG[TRES] = 1. + * 0b0000000000000001..Trigger 0 has been interrupted by a high priority exception. + * 0b0000000000000010..Trigger 1 has been interrupted by a high priority exception. + * 0b0000000000000011-0b1111111111111110..Associated trigger sequence has interrupted by a high priority exception. + * 0b1111111111111111..Every trigger sequence has been interrupted by a high priority exception. + */ +#define ADC_TSTAT_TEXC_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_TSTAT_TEXC_NUM_SHIFT)) & ADC_TSTAT_TEXC_NUM_MASK) +#define ADC_TSTAT_TCOMP_FLAG_MASK (0xFFFF0000U) +#define ADC_TSTAT_TCOMP_FLAG_SHIFT (16U) +/*! TCOMP_FLAG - Trigger Completion Flag + * 0b0000000000000000..No triggers have been completed. Trigger completion interrupts are disabled. + * 0b0000000000000001..Trigger 0 has been completed and triger 0 has enabled completion interrupts. + * 0b0000000000000010..Trigger 1 has been completed and triger 1 has enabled completion interrupts. + * 0b0000000000000011-0b1111111111111110..Associated trigger sequence has completed and has enabled completion interrupts. + * 0b1111111111111111..Every trigger sequence has been completed and every trigger has enabled completion interrupts. + */ +#define ADC_TSTAT_TCOMP_FLAG(x) (((uint32_t)(((uint32_t)(x)) << ADC_TSTAT_TCOMP_FLAG_SHIFT)) & ADC_TSTAT_TCOMP_FLAG_MASK) +/*! @} */ + +/*! @name OFSTRIM - ADC Offset Trim Register */ +/*! @{ */ +#define ADC_OFSTRIM_OFSTRIM_A_MASK (0x1FU) +#define ADC_OFSTRIM_OFSTRIM_A_SHIFT (0U) +#define ADC_OFSTRIM_OFSTRIM_A(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFSTRIM_OFSTRIM_A_SHIFT)) & ADC_OFSTRIM_OFSTRIM_A_MASK) +#define ADC_OFSTRIM_OFSTRIM_B_MASK (0x1F0000U) +#define ADC_OFSTRIM_OFSTRIM_B_SHIFT (16U) +#define ADC_OFSTRIM_OFSTRIM_B(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFSTRIM_OFSTRIM_B_SHIFT)) & ADC_OFSTRIM_OFSTRIM_B_MASK) +/*! @} */ + +/*! @name TCTRL - Trigger Control Register */ +/*! @{ */ +#define ADC_TCTRL_HTEN_MASK (0x1U) +#define ADC_TCTRL_HTEN_SHIFT (0U) +/*! HTEN - Trigger enable + * 0b0..Hardware trigger source disabled + * 0b1..Hardware trigger source enabled + */ +#define ADC_TCTRL_HTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_HTEN_SHIFT)) & ADC_TCTRL_HTEN_MASK) +#define ADC_TCTRL_FIFO_SEL_A_MASK (0x2U) +#define ADC_TCTRL_FIFO_SEL_A_SHIFT (1U) +/*! FIFO_SEL_A - SAR Result Destination For Channel A + * 0b0..Result written to FIFO 0 + * 0b1..Result written to FIFO 1 + */ +#define ADC_TCTRL_FIFO_SEL_A(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_FIFO_SEL_A_SHIFT)) & ADC_TCTRL_FIFO_SEL_A_MASK) +#define ADC_TCTRL_FIFO_SEL_B_MASK (0x4U) +#define ADC_TCTRL_FIFO_SEL_B_SHIFT (2U) +/*! FIFO_SEL_B - SAR Result Destination For Channel B + * 0b0..Result written to FIFO 0 + * 0b1..Result written to FIFO 1 + */ +#define ADC_TCTRL_FIFO_SEL_B(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_FIFO_SEL_B_SHIFT)) & ADC_TCTRL_FIFO_SEL_B_MASK) +#define ADC_TCTRL_TPRI_MASK (0xF00U) +#define ADC_TCTRL_TPRI_SHIFT (8U) +/*! TPRI - Trigger priority setting + * 0b0000..Set to highest priority, Level 1 + * 0b0001-0b1110..Set to corresponding priority level + * 0b1111..Set to lowest priority, Level 16 + */ +#define ADC_TCTRL_TPRI(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TPRI_SHIFT)) & ADC_TCTRL_TPRI_MASK) +#define ADC_TCTRL_RSYNC_MASK (0x8000U) +#define ADC_TCTRL_RSYNC_SHIFT (15U) +#define ADC_TCTRL_RSYNC(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_RSYNC_SHIFT)) & ADC_TCTRL_RSYNC_MASK) +#define ADC_TCTRL_TDLY_MASK (0xF0000U) +#define ADC_TCTRL_TDLY_SHIFT (16U) +#define ADC_TCTRL_TDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TDLY_SHIFT)) & ADC_TCTRL_TDLY_MASK) +#define ADC_TCTRL_TCMD_MASK (0xF000000U) +#define ADC_TCTRL_TCMD_SHIFT (24U) +/*! TCMD - Trigger command select + * 0b0000..Not a valid selection from the command buffer. Trigger event is ignored. + * 0b0001..CMD1 is executed + * 0b0010-0b1110..Corresponding CMD is executed + * 0b1111..CMD15 is executed + */ +#define ADC_TCTRL_TCMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TCMD_SHIFT)) & ADC_TCTRL_TCMD_MASK) +/*! @} */ + +/* The count of ADC_TCTRL */ +#define ADC_TCTRL_COUNT (16U) + +/*! @name FCTRL - FIFO Control Register */ +/*! @{ */ +#define ADC_FCTRL_FCOUNT_MASK (0x1FU) +#define ADC_FCTRL_FCOUNT_SHIFT (0U) +#define ADC_FCTRL_FCOUNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FCOUNT_SHIFT)) & ADC_FCTRL_FCOUNT_MASK) +#define ADC_FCTRL_FWMARK_MASK (0xF0000U) +#define ADC_FCTRL_FWMARK_SHIFT (16U) +#define ADC_FCTRL_FWMARK(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FWMARK_SHIFT)) & ADC_FCTRL_FWMARK_MASK) +/*! @} */ + +/* The count of ADC_FCTRL */ +#define ADC_FCTRL_COUNT (2U) + +/*! @name GCC - Gain Calibration Control */ +/*! @{ */ +#define ADC_GCC_GAIN_CAL_MASK (0xFFFFU) +#define ADC_GCC_GAIN_CAL_SHIFT (0U) +#define ADC_GCC_GAIN_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCC_GAIN_CAL_SHIFT)) & ADC_GCC_GAIN_CAL_MASK) +#define ADC_GCC_RDY_MASK (0x1000000U) +#define ADC_GCC_RDY_SHIFT (24U) +/*! RDY - Gain Calibration Value Valid + * 0b0..The gain calibration value is invalid. Run the auto-calibration routine for this value to be written. + * 0b1..The gain calibration value is valid. It should be used to update the GCRa[GCALR] register field. + */ +#define ADC_GCC_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCC_RDY_SHIFT)) & ADC_GCC_RDY_MASK) +/*! @} */ + +/* The count of ADC_GCC */ +#define ADC_GCC_COUNT (2U) + +/*! @name GCR - Gain Calculation Result */ +/*! @{ */ +#define ADC_GCR_GCALR_MASK (0xFFFFU) +#define ADC_GCR_GCALR_SHIFT (0U) +#define ADC_GCR_GCALR(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCR_GCALR_SHIFT)) & ADC_GCR_GCALR_MASK) +#define ADC_GCR_RDY_MASK (0x1000000U) +#define ADC_GCR_RDY_SHIFT (24U) +/*! RDY - Gain Calculation Ready + * 0b0..The gain offset calculation value is invalid. + * 0b1..The gain calibration value is valid. + */ +#define ADC_GCR_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCR_RDY_SHIFT)) & ADC_GCR_RDY_MASK) +/*! @} */ + +/* The count of ADC_GCR */ +#define ADC_GCR_COUNT (2U) + +/*! @name CMDL - ADC Command Low Buffer Register */ +/*! @{ */ +#define ADC_CMDL_ADCH_MASK (0x1FU) +#define ADC_CMDL_ADCH_SHIFT (0U) +/*! ADCH - Input channel select + * 0b00000..Select CH0A or CH0B or CH0A/CH0B pair. + * 0b00001..Select CH1A or CH1B or CH1A/CH1B pair. + * 0b00010..Select CH2A or CH2B or CH2A/CH2B pair. + * 0b00011..Select CH3A or CH3B or CH3A/CH3B pair. + * 0b00100-0b11101..Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + * 0b11110..Select CH30A or CH30B or CH30A/CH30B pair. + * 0b11111..Select CH31A or CH31B or CH31A/CH31B pair. + */ +#define ADC_CMDL_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ADCH_SHIFT)) & ADC_CMDL_ADCH_MASK) +#define ADC_CMDL_CTYPE_MASK (0x60U) +#define ADC_CMDL_CTYPE_SHIFT (5U) +/*! CTYPE - Conversion Type + * 0b00..Single-Ended Mode. Only A side channel is converted. + * 0b01..Single-Ended Mode. Only B side channel is converted. + * 0b10..Differential Mode. A-B. + * 0b11..Dual-Single-Ended Mode. Both A side and B side channels are converted independently. + */ +#define ADC_CMDL_CTYPE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_CTYPE_SHIFT)) & ADC_CMDL_CTYPE_MASK) +#define ADC_CMDL_MODE_MASK (0x80U) +#define ADC_CMDL_MODE_SHIFT (7U) +/*! MODE - Select resolution of conversions + * 0b0..Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. + * 0b1..High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. + */ +#define ADC_CMDL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_MODE_SHIFT)) & ADC_CMDL_MODE_MASK) +/*! @} */ + +/* The count of ADC_CMDL */ +#define ADC_CMDL_COUNT (15U) + +/*! @name CMDH - ADC Command High Buffer Register */ +/*! @{ */ +#define ADC_CMDH_CMPEN_MASK (0x3U) +#define ADC_CMDH_CMPEN_SHIFT (0U) +/*! CMPEN - Compare Function Enable + * 0b00..Compare disabled. + * 0b01..Reserved + * 0b10..Compare enabled. Store on true. + * 0b11..Compare enabled. Repeat channel acquisition (sample/convert/compare) until true. + */ +#define ADC_CMDH_CMPEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_CMPEN_SHIFT)) & ADC_CMDH_CMPEN_MASK) +#define ADC_CMDH_WAIT_TRIG_MASK (0x4U) +#define ADC_CMDH_WAIT_TRIG_SHIFT (2U) +/*! WAIT_TRIG - Wait for trigger assertion before execution. + * 0b0..This command will be automatically executed. + * 0b1..The active trigger must be asserted again before executing this command. + */ +#define ADC_CMDH_WAIT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_WAIT_TRIG_SHIFT)) & ADC_CMDH_WAIT_TRIG_MASK) +#define ADC_CMDH_LWI_MASK (0x80U) +#define ADC_CMDH_LWI_SHIFT (7U) +/*! LWI - Loop with Increment + * 0b0..Auto channel increment disabled + * 0b1..Auto channel increment enabled + */ +#define ADC_CMDH_LWI(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LWI_SHIFT)) & ADC_CMDH_LWI_MASK) +#define ADC_CMDH_STS_MASK (0x700U) +#define ADC_CMDH_STS_SHIFT (8U) +/*! STS - Sample Time Select + * 0b000..Minimum sample time of 3 ADCK cycles. + * 0b001..3 + 21 ADCK cycles; 5 ADCK cycles total sample time. + * 0b010..3 + 22 ADCK cycles; 7 ADCK cycles total sample time. + * 0b011..3 + 23 ADCK cycles; 11 ADCK cycles total sample time. + * 0b100..3 + 24 ADCK cycles; 19 ADCK cycles total sample time. + * 0b101..3 + 25 ADCK cycles; 35 ADCK cycles total sample time. + * 0b110..3 + 26 ADCK cycles; 67 ADCK cycles total sample time. + * 0b111..3 + 27 ADCK cycles; 131 ADCK cycles total sample time. + */ +#define ADC_CMDH_STS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_STS_SHIFT)) & ADC_CMDH_STS_MASK) +#define ADC_CMDH_AVGS_MASK (0x7000U) +#define ADC_CMDH_AVGS_SHIFT (12U) +/*! AVGS - Hardware Average Select + * 0b000..Single conversion. + * 0b001..2 conversions averaged. + * 0b010..4 conversions averaged. + * 0b011..8 conversions averaged. + * 0b100..16 conversions averaged. + * 0b101..32 conversions averaged. + * 0b110..64 conversions averaged. + * 0b111..128 conversions averaged. + */ +#define ADC_CMDH_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_AVGS_SHIFT)) & ADC_CMDH_AVGS_MASK) +#define ADC_CMDH_LOOP_MASK (0xF0000U) +#define ADC_CMDH_LOOP_SHIFT (16U) +/*! LOOP - Loop Count Select + * 0b0000..Looping not enabled. Command executes 1 time. + * 0b0001..Loop 1 time. Command executes 2 times. + * 0b0010..Loop 2 times. Command executes 3 times. + * 0b0011-0b1110..Loop corresponding number of times. Command executes LOOP+1 times. + * 0b1111..Loop 15 times. Command executes 16 times. + */ +#define ADC_CMDH_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LOOP_SHIFT)) & ADC_CMDH_LOOP_MASK) +#define ADC_CMDH_NEXT_MASK (0xF000000U) +#define ADC_CMDH_NEXT_SHIFT (24U) +/*! NEXT - Next Command Select + * 0b0000..No next command defined. Terminate conversions at completion of current command. If lower priority + * trigger pending, begin command associated with lower priority trigger. + * 0b0001..Select CMD1 command buffer register as next command. + * 0b0010-0b1110..Select corresponding CMD command buffer register as next command + * 0b1111..Select CMD15 command buffer register as next command. + */ +#define ADC_CMDH_NEXT(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_NEXT_SHIFT)) & ADC_CMDH_NEXT_MASK) +/*! @} */ + +/* The count of ADC_CMDH */ +#define ADC_CMDH_COUNT (15U) + +/*! @name CV - Compare Value Register */ +/*! @{ */ +#define ADC_CV_CVL_MASK (0xFFFFU) +#define ADC_CV_CVL_SHIFT (0U) +#define ADC_CV_CVL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVL_SHIFT)) & ADC_CV_CVL_MASK) +#define ADC_CV_CVH_MASK (0xFFFF0000U) +#define ADC_CV_CVH_SHIFT (16U) +#define ADC_CV_CVH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVH_SHIFT)) & ADC_CV_CVH_MASK) +/*! @} */ + +/* The count of ADC_CV */ +#define ADC_CV_COUNT (4U) + +/*! @name RESFIFO - ADC Data Result FIFO Register */ +/*! @{ */ +#define ADC_RESFIFO_D_MASK (0xFFFFU) +#define ADC_RESFIFO_D_SHIFT (0U) +#define ADC_RESFIFO_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_D_SHIFT)) & ADC_RESFIFO_D_MASK) +#define ADC_RESFIFO_TSRC_MASK (0xF0000U) +#define ADC_RESFIFO_TSRC_SHIFT (16U) +/*! TSRC - Trigger Source + * 0b0000..Trigger source 0 initiated this conversion. + * 0b0001..Trigger source 1 initiated this conversion. + * 0b0010-0b1110..Corresponding trigger source initiated this conversion. + * 0b1111..Trigger source 15 initiated this conversion. + */ +#define ADC_RESFIFO_TSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_TSRC_SHIFT)) & ADC_RESFIFO_TSRC_MASK) +#define ADC_RESFIFO_LOOPCNT_MASK (0xF00000U) +#define ADC_RESFIFO_LOOPCNT_SHIFT (20U) +/*! LOOPCNT - Loop count value + * 0b0000..Result is from initial conversion in command. + * 0b0001..Result is from second conversion in command. + * 0b0010-0b1110..Result is from LOOPCNT+1 conversion in command. + * 0b1111..Result is from 16th conversion in command. + */ +#define ADC_RESFIFO_LOOPCNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_LOOPCNT_SHIFT)) & ADC_RESFIFO_LOOPCNT_MASK) +#define ADC_RESFIFO_CMDSRC_MASK (0xF000000U) +#define ADC_RESFIFO_CMDSRC_SHIFT (24U) +/*! CMDSRC - Command Buffer Source + * 0b0000..Not a valid value CMDSRC value for a dataword in RESFIFO. 0x0 is only found in initial FIFO state + * prior to an ADC conversion result dataword being stored to a RESFIFO buffer. + * 0b0001..CMD1 buffer used as control settings for this conversion. + * 0b0010-0b1110..Corresponding command buffer used as control settings for this conversion. + * 0b1111..CMD15 buffer used as control settings for this conversion. + */ +#define ADC_RESFIFO_CMDSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_CMDSRC_SHIFT)) & ADC_RESFIFO_CMDSRC_MASK) +#define ADC_RESFIFO_VALID_MASK (0x80000000U) +#define ADC_RESFIFO_VALID_SHIFT (31U) +/*! VALID - FIFO entry is valid + * 0b0..FIFO is empty. Discard any read from RESFIFO. + * 0b1..FIFO record read from RESFIFO is valid. + */ +#define ADC_RESFIFO_VALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_VALID_SHIFT)) & ADC_RESFIFO_VALID_MASK) +/*! @} */ + +/* The count of ADC_RESFIFO */ +#define ADC_RESFIFO_COUNT (2U) + +/*! @name CAL_GAR - Calibration General A-Side Registers */ +/*! @{ */ +#define ADC_CAL_GAR_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR_CAL_GAR_VAL_SHIFT (0U) +#define ADC_CAL_GAR_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR_CAL_GAR_VAL_MASK) +/*! @} */ + +/* The count of ADC_CAL_GAR */ +#define ADC_CAL_GAR_COUNT (33U) + +/*! @name CAL_GBR - Calibration General B-Side Registers */ +/*! @{ */ +#define ADC_CAL_GBR_CAL_GBR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GBR_CAL_GBR_VAL_SHIFT (0U) +#define ADC_CAL_GBR_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR_CAL_GBR_VAL_MASK) +/*! @} */ + +/* The count of ADC_CAL_GBR */ +#define ADC_CAL_GBR_COUNT (33U) + +/*! @name TST - ADC Test Register */ +/*! @{ */ +#define ADC_TST_CST_LONG_MASK (0x1U) +#define ADC_TST_CST_LONG_SHIFT (0U) +/*! CST_LONG - Calibration Sample Time Long + * 0b0..Normal sample time. Minimum sample time of 3 ADCK cycles. + * 0b1..Increased sample time. 67 ADCK cycles total sample time. + */ +#define ADC_TST_CST_LONG(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_CST_LONG_SHIFT)) & ADC_TST_CST_LONG_MASK) +#define ADC_TST_FOFFM_MASK (0x100U) +#define ADC_TST_FOFFM_SHIFT (8U) +/*! FOFFM - Force M-side positive offset + * 0b0..Normal operation. No forced offset. + * 0b1..Test configuration. Forced positive offset on MDAC. + */ +#define ADC_TST_FOFFM(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_FOFFM_SHIFT)) & ADC_TST_FOFFM_MASK) +#define ADC_TST_FOFFP_MASK (0x200U) +#define ADC_TST_FOFFP_SHIFT (9U) +/*! FOFFP - Force P-side positive offset + * 0b0..Normal operation. No forced offset. + * 0b1..Test configuration. Forced positive offset on PDAC. + */ +#define ADC_TST_FOFFP(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_FOFFP_SHIFT)) & ADC_TST_FOFFP_MASK) +#define ADC_TST_FOFFM2_MASK (0x400U) +#define ADC_TST_FOFFM2_SHIFT (10U) +/*! FOFFM2 - Force M-side negative offset + * 0b0..Normal operation. No forced offset. + * 0b1..Test configuration. Forced negative offset on MDAC. + */ +#define ADC_TST_FOFFM2(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_FOFFM2_SHIFT)) & ADC_TST_FOFFM2_MASK) +#define ADC_TST_FOFFP2_MASK (0x800U) +#define ADC_TST_FOFFP2_SHIFT (11U) +/*! FOFFP2 - Force P-side negative offset + * 0b0..Normal operation. No forced offset. + * 0b1..Test configuration. Forced negative offset on PDAC. + */ +#define ADC_TST_FOFFP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_FOFFP2_SHIFT)) & ADC_TST_FOFFP2_MASK) +#define ADC_TST_TESTEN_MASK (0x800000U) +#define ADC_TST_TESTEN_SHIFT (23U) +/*! TESTEN - Enable test configuration + * 0b0..Normal operation. Test configuration not enabled. + * 0b1..Hardware BIST Test in progress. + */ +#define ADC_TST_TESTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_TESTEN_SHIFT)) & ADC_TST_TESTEN_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group ADC_Register_Masks */ + + +/* ADC - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral ADC0 base address */ + #define ADC0_BASE (0x500A0000u) + /** Peripheral ADC0 base address */ + #define ADC0_BASE_NS (0x400A0000u) + /** Peripheral ADC0 base pointer */ + #define ADC0 ((ADC_Type *)ADC0_BASE) + /** Peripheral ADC0 base pointer */ + #define ADC0_NS ((ADC_Type *)ADC0_BASE_NS) + /** Array initializer of ADC peripheral base addresses */ + #define ADC_BASE_ADDRS { ADC0_BASE } + /** Array initializer of ADC peripheral base pointers */ + #define ADC_BASE_PTRS { ADC0 } + /** Array initializer of ADC peripheral base addresses */ + #define ADC_BASE_ADDRS_NS { ADC0_BASE_NS } + /** Array initializer of ADC peripheral base pointers */ + #define ADC_BASE_PTRS_NS { ADC0_NS } +#else + /** Peripheral ADC0 base address */ + #define ADC0_BASE (0x400A0000u) + /** Peripheral ADC0 base pointer */ + #define ADC0 ((ADC_Type *)ADC0_BASE) + /** Array initializer of ADC peripheral base addresses */ + #define ADC_BASE_ADDRS { ADC0_BASE } + /** Array initializer of ADC peripheral base pointers */ + #define ADC_BASE_PTRS { ADC0 } +#endif +/** Interrupt vectors for the ADC peripheral type */ +#define ADC_IRQS { ADC0_IRQn } + +/*! + * @} + */ /* end of group ADC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- AHB_SECURE_CTRL Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup AHB_SECURE_CTRL_Peripheral_Access_Layer AHB_SECURE_CTRL Peripheral Access Layer + * @{ + */ + +/** AHB_SECURE_CTRL - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x30 */ + __IO uint32_t SLAVE_RULE; /**< Security access rules for Flash and ROM slaves., array offset: 0x0, array step: 0x30 */ + uint8_t RESERVED_0[12]; + __IO uint32_t SEC_CTRL_FLASH_MEM_RULE[3]; /**< Security access rules for FLASH sector 0 to sector 20. Each Flash sector is 32 Kbytes. There are 20 FLASH sectors in total., array offset: 0x10, array step: index*0x30, index2*0x4 */ + uint8_t RESERVED_1[4]; + __IO uint32_t SEC_CTRL_ROM_MEM_RULE[4]; /**< Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total., array offset: 0x20, array step: index*0x30, index2*0x4 */ + } SEC_CTRL_FLASH_ROM[1]; + struct { /* offset: 0x30, array step: 0x14 */ + __IO uint32_t SLAVE_RULE; /**< Security access rules for RAMX slaves., array offset: 0x30, array step: 0x14 */ + uint8_t RESERVED_0[12]; + __IO uint32_t MEM_RULE[1]; /**< Security access rules for RAMX slaves., array offset: 0x40, array step: index*0x14, index2*0x4 */ + } SEC_CTRL_RAMX[1]; + uint8_t RESERVED_0[12]; + struct { /* offset: 0x50, array step: 0x18 */ + __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM0 slaves., array offset: 0x50, array step: 0x18 */ + uint8_t RESERVED_0[12]; + __IO uint32_t MEM_RULE[2]; /**< Security access rules for RAM0 slaves., array offset: 0x60, array step: index*0x18, index2*0x4 */ + } SEC_CTRL_RAM0[1]; + uint8_t RESERVED_1[8]; + struct { /* offset: 0x70, array step: 0x18 */ + __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM1 slaves., array offset: 0x70, array step: 0x18 */ + uint8_t RESERVED_0[12]; + __IO uint32_t MEM_RULE[2]; /**< Security access rules for RAM1 slaves., array offset: 0x80, array step: index*0x18, index2*0x4 */ + } SEC_CTRL_RAM1[1]; + uint8_t RESERVED_2[8]; + struct { /* offset: 0x90, array step: 0x18 */ + __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM2 slaves., array offset: 0x90, array step: 0x18 */ + uint8_t RESERVED_0[12]; + __IO uint32_t MEM_RULE[2]; /**< Security access rules for RAM2 slaves., array offset: 0xA0, array step: index*0x18, index2*0x4 */ + } SEC_CTRL_RAM2[1]; + uint8_t RESERVED_3[8]; + struct { /* offset: 0xB0, array step: 0x18 */ + __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM3 slaves., array offset: 0xB0, array step: 0x18 */ + uint8_t RESERVED_0[12]; + __IO uint32_t MEM_RULE[2]; /**< Security access rules for RAM3 slaves., array offset: 0xC0, array step: index*0x18, index2*0x4 */ + } SEC_CTRL_RAM3[1]; + uint8_t RESERVED_4[8]; + struct { /* offset: 0xD0, array step: 0x14 */ + __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM4 slaves., array offset: 0xD0, array step: 0x14 */ + uint8_t RESERVED_0[12]; + __IO uint32_t MEM_RULE[1]; /**< Security access rules for RAM4 slaves., array offset: 0xE0, array step: index*0x14, index2*0x4 */ + } SEC_CTRL_RAM4[1]; + uint8_t RESERVED_5[12]; + struct { /* offset: 0xF0, array step: 0x30 */ + __IO uint32_t SLAVE_RULE; /**< Security access rules for both APB Bridges slaves., array offset: 0xF0, array step: 0x30 */ + uint8_t RESERVED_0[12]; + __IO uint32_t SEC_CTRL_APB_BRIDGE0_MEM_CTRL0; /**< Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total., array offset: 0x100, array step: 0x30 */ + __IO uint32_t SEC_CTRL_APB_BRIDGE0_MEM_CTRL1; /**< Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total., array offset: 0x104, array step: 0x30 */ + __IO uint32_t SEC_CTRL_APB_BRIDGE0_MEM_CTRL2; /**< Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total., array offset: 0x108, array step: 0x30 */ + uint32_t SEC_CTRL_APB_BRIDGE0_MEM_CTRL3; /**< Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total., array offset: 0x10C, array step: 0x30 */ + __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL0; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0x110, array step: 0x30 */ + __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL1; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0x114, array step: 0x30 */ + __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL2; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0x118, array step: 0x30 */ + __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL3; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0x11C, array step: 0x30 */ + } SEC_CTRL_APB_BRIDGE[1]; + __IO uint32_t SEC_CTRL_AHB0_0_SLAVE_RULE; /**< Security access rules for AHB peripherals., offset: 0x120 */ + __IO uint32_t SEC_CTRL_AHB0_1_SLAVE_RULE; /**< Security access rules for AHB peripherals., offset: 0x124 */ + uint8_t RESERVED_6[8]; + __IO uint32_t SEC_CTRL_AHB1_0_SLAVE_RULE; /**< Security access rules for AHB peripherals., offset: 0x130 */ + __IO uint32_t SEC_CTRL_AHB1_1_SLAVE_RULE; /**< Security access rules for AHB peripherals., offset: 0x134 */ + uint8_t RESERVED_7[8]; + struct { /* offset: 0x140, array step: 0x14 */ + __IO uint32_t SEC_CTRL_AHB2_0_SLAVE_RULE; /**< Security access rules for AHB peripherals., array offset: 0x140, array step: 0x14 */ + __IO uint32_t SEC_CTRL_AHB2_1_SLAVE_RULE; /**< Security access rules for AHB peripherals., array offset: 0x144, array step: 0x14 */ + uint8_t RESERVED_0[8]; + __IO uint32_t SEC_CTRL_AHB2_0_MEM_RULE[1]; /**< Security access rules for AHB_SEC_CTRL_AHB., array offset: 0x150, array step: index*0x14, index2*0x4 */ + } SEC_CTRL_AHB2[1]; + uint8_t RESERVED_8[12]; + struct { /* offset: 0x160, array step: 0x14 */ + __IO uint32_t SLAVE_RULE; /**< Security access rules for USB High speed RAM slaves., array offset: 0x160, array step: 0x14 */ + uint8_t RESERVED_0[12]; + __IO uint32_t MEM_RULE[1]; /**< Security access rules for RAM_USB_HS., array offset: 0x170, array step: index*0x14, index2*0x4 */ + } SEC_CTRL_USB_HS[1]; + uint8_t RESERVED_9[3212]; + __I uint32_t SEC_VIO_ADDR[12]; /**< most recent security violation address for AHB layer n, array offset: 0xE00, array step: 0x4 */ + uint8_t RESERVED_10[80]; + __I uint32_t SEC_VIO_MISC_INFO[12]; /**< most recent security violation miscellaneous information for AHB layer n, array offset: 0xE80, array step: 0x4 */ + uint8_t RESERVED_11[80]; + __IO uint32_t SEC_VIO_INFO_VALID; /**< security violation address/information registers valid flags, offset: 0xF00 */ + uint8_t RESERVED_12[124]; + __IO uint32_t SEC_GPIO_MASK0; /**< Secure GPIO mask for port 0 pins., offset: 0xF80 */ + __IO uint32_t SEC_GPIO_MASK1; /**< Secure GPIO mask for port 1 pins., offset: 0xF84 */ + uint8_t RESERVED_13[8]; + __IO uint32_t SEC_CPU_INT_MASK0; /**< Secure Interrupt mask for CPU1, offset: 0xF90 */ + __IO uint32_t SEC_CPU_INT_MASK1; /**< Secure Interrupt mask for CPU1, offset: 0xF94 */ + uint8_t RESERVED_14[36]; + __IO uint32_t SEC_MASK_LOCK; /**< Security General Purpose register access control., offset: 0xFBC */ + uint8_t RESERVED_15[16]; + __IO uint32_t MASTER_SEC_LEVEL; /**< master secure level register, offset: 0xFD0 */ + __IO uint32_t MASTER_SEC_ANTI_POL_REG; /**< master secure level anti-pole register, offset: 0xFD4 */ + uint8_t RESERVED_16[20]; + __IO uint32_t CM33_LOCK_REG; /**< Miscalleneous control signals for in CM33 (CPU0), offset: 0xFEC */ + __IO uint32_t MCM33_LOCK_REG; /**< Miscalleneous control signals for in micro-CM33 (CPU1), offset: 0xFF0 */ + uint8_t RESERVED_17[4]; + __IO uint32_t MISC_CTRL_DP_REG; /**< secure control duplicate register, offset: 0xFF8 */ + __IO uint32_t MISC_CTRL_REG; /**< secure control register, offset: 0xFFC */ +} AHB_SECURE_CTRL_Type; + +/* ---------------------------------------------------------------------------- + -- AHB_SECURE_CTRL Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup AHB_SECURE_CTRL_Register_Masks AHB_SECURE_CTRL Register Masks + * @{ + */ + +/*! @name SEC_CTRL_FLASH_ROM_SLAVE_RULE - Security access rules for Flash and ROM slaves. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_SHIFT (0U) +/*! FLASH_RULE - Security access rules for the whole FLASH : 0x0000_0000 - 0x0009_FFFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_SHIFT (4U) +/*! ROM_RULE - Security access rules for the whole ROM : 0x0300_0000 - 0x0301_FFFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_COUNT (1U) + +/*! @name SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE - Security access rules for FLASH sector 0 to sector 20. Each Flash sector is 32 Kbytes. There are 20 FLASH sectors in total. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE0_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE0_SHIFT (0U) +/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE0_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE1_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE1_SHIFT (4U) +/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE1_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE2_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE2_SHIFT (8U) +/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE2_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE3_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE3_SHIFT (12U) +/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE3_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE4_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE4_SHIFT (16U) +/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE4_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE5_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE5_SHIFT (20U) +/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE5_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE6_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE6_SHIFT (24U) +/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE6_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE7_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE7_SHIFT (28U) +/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE7_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_COUNT (1U) + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_COUNT2 (3U) + +/*! @name SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE - Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE0_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE0_SHIFT (0U) +/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE0_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE1_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE1_SHIFT (4U) +/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE1_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE2_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE2_SHIFT (8U) +/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE2_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE3_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE3_SHIFT (12U) +/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE3_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE4_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE4_SHIFT (16U) +/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE4_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE5_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE5_SHIFT (20U) +/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE5_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE6_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE6_SHIFT (24U) +/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE6_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE7_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE7_SHIFT (28U) +/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE7_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_COUNT (1U) + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_COUNT2 (4U) + +/*! @name SEC_CTRL_RAMX_SLAVE_RULE - Security access rules for RAMX slaves. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_SHIFT (0U) +/*! RAMX_RULE - Security access rules for the whole RAMX : 0x0400_0000 - 0x0400_7FFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_COUNT (1U) + +/*! @name SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE - Security access rules for RAMX slaves. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE0_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE0_SHIFT (0U) +/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE0_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE1_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE1_SHIFT (4U) +/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE1_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE2_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE2_SHIFT (8U) +/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE2_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE3_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE3_SHIFT (12U) +/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE3_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE4_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE4_SHIFT (16U) +/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE4_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE5_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE5_SHIFT (20U) +/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE5_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE6_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE6_SHIFT (24U) +/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE6_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE7_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE7_SHIFT (28U) +/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE7_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_COUNT (1U) + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_COUNT2 (1U) + +/*! @name SEC_CTRL_RAM0_SLAVE_RULE - Security access rules for RAM0 slaves. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_SHIFT (0U) +/*! RAM0_RULE - Security access rules for the whole RAM0 : 0x2000_0000 - 0x2000_FFFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_COUNT (1U) + +/*! @name SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE - Security access rules for RAM0 slaves. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE0_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE0_SHIFT (0U) +/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE0_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE1_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE1_SHIFT (4U) +/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE1_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE2_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE2_SHIFT (8U) +/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE2_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE3_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE3_SHIFT (12U) +/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE3_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE4_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE4_SHIFT (16U) +/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE4_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE5_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE5_SHIFT (20U) +/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE5_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE6_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE6_SHIFT (24U) +/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE6_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE7_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE7_SHIFT (28U) +/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE7_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_COUNT (1U) + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_COUNT2 (2U) + +/*! @name SEC_CTRL_RAM1_SLAVE_RULE - Security access rules for RAM1 slaves. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM0_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM0_RULE_SHIFT (0U) +/*! RAM0_RULE - Security access rules for the whole RAM1 : 0x2001_0000 - 0x2001_FFFF" name="0 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM0_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_COUNT (1U) + +/*! @name SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE - Security access rules for RAM1 slaves. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE0_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE0_SHIFT (0U) +/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE0_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE1_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE1_SHIFT (4U) +/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE1_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE2_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE2_SHIFT (8U) +/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE2_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE3_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE3_SHIFT (12U) +/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE3_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE4_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE4_SHIFT (16U) +/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE4_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE5_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE5_SHIFT (20U) +/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE5_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE6_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE6_SHIFT (24U) +/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE6_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE7_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE7_SHIFT (28U) +/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE7_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_COUNT (1U) + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_COUNT2 (2U) + +/*! @name SEC_CTRL_RAM2_SLAVE_RULE - Security access rules for RAM2 slaves. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_SHIFT (0U) +/*! RAM2_RULE - Security access rules for the whole RAM2 : 0x2002_0000 - 0x2002_FFFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_COUNT (1U) + +/*! @name SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE - Security access rules for RAM2 slaves. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE0_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE0_SHIFT (0U) +/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE0_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE1_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE1_SHIFT (4U) +/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE1_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE2_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE2_SHIFT (8U) +/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE2_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE3_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE3_SHIFT (12U) +/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE3_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE4_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE4_SHIFT (16U) +/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE4_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE5_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE5_SHIFT (20U) +/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE5_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE6_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE6_SHIFT (24U) +/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE6_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE7_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE7_SHIFT (28U) +/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE7_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_COUNT (1U) + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_COUNT2 (2U) + +/*! @name SEC_CTRL_RAM3_SLAVE_RULE - Security access rules for RAM3 slaves. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE_SHIFT (0U) +/*! RAM3_RULE - Security access rules for the whole RAM3: 0x2003_0000 - 0x2003_FFFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_COUNT (1U) + +/*! @name SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE - Security access rules for RAM3 slaves. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE0_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE0_SHIFT (0U) +/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE0_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE1_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE1_SHIFT (4U) +/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE1_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE2_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE2_SHIFT (8U) +/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE2_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE3_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE3_SHIFT (12U) +/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE3_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE4_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE4_SHIFT (16U) +/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE4_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE5_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE5_SHIFT (20U) +/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE5_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE6_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE6_SHIFT (24U) +/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE6_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE7_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE7_SHIFT (28U) +/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE7_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_COUNT (1U) + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_COUNT2 (2U) + +/*! @name SEC_CTRL_RAM4_SLAVE_RULE - Security access rules for RAM4 slaves. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE_SHIFT (0U) +/*! RAM4_RULE - Security access rules for the whole RAM4 : 0x2004_0000 - 0x2004_3FFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_COUNT (1U) + +/*! @name SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE - Security access rules for RAM4 slaves. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE0_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE0_SHIFT (0U) +/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE0_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE1_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE1_SHIFT (4U) +/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE1_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE2_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE2_SHIFT (8U) +/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE2_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE3_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE3_SHIFT (12U) +/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE3_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_COUNT (1U) + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_COUNT2 (1U) + +/*! @name SEC_CTRL_APB_BRIDGE_SLAVE_RULE - Security access rules for both APB Bridges slaves. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_SHIFT (0U) +/*! APBBRIDGE0_RULE - Security access rules for the whole APB Bridge 0 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_SHIFT (4U) +/*! APBBRIDGE1_RULE - Security access rules for the whole APB Bridge 1 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_COUNT (1U) + +/*! @name SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_SHIFT (0U) +/*! SYSCON_RULE - System Configuration + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_SHIFT (4U) +/*! IOCON_RULE - I/O Configuration + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_SHIFT (8U) +/*! GINT0_RULE - GPIO input Interrupt 0 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_SHIFT (12U) +/*! GINT1_RULE - GPIO input Interrupt 1 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_SHIFT (16U) +/*! PINT_RULE - Pin Interrupt and Pattern match + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_SHIFT (20U) +/*! SEC_PINT_RULE - Secure Pin Interrupt and Pattern match + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PMUX_RULE_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PMUX_RULE_SHIFT (24U) +/*! PMUX_RULE - Peripherals mux + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PMUX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PMUX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PMUX_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0 */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_COUNT (1U) + +/*! @name SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_SHIFT (0U) +/*! CTIMER0_RULE - Standard counter/Timer 0 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_SHIFT (4U) +/*! CTIMER1_RULE - Standard counter/Timer 1 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_SHIFT (16U) +/*! WWDT_RULE - Windiwed wtachdog Timer + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_SHIFT (20U) +/*! MRT_RULE - Multi-rate Timer + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_SHIFT (24U) +/*! UTICK_RULE - Micro-Timer + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1 */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_COUNT (1U) + +/*! @name SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_SHIFT (12U) +/*! ANACTRL_RULE - Analog Modules controller + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_EFUSE_RULE_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_EFUSE_RULE_SHIFT (20U) +/*! EFUSE_RULE - eFUSE (One Time Programmable) memory controller + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_EFUSE_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_EFUSE_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_EFUSE_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2 */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_COUNT (1U) + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL3 */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL3_COUNT (1U) + +/*! @name SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_SHIFT (0U) +/*! PMC_RULE - Power Management Controller + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_SHIFT (12U) +/*! SYSCTRL_RULE - System Controller + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0 */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_COUNT (1U) + +/*! @name SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_SHIFT (0U) +/*! CTIMER2_RULE - Standard counter/Timer 2 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_SHIFT (4U) +/*! CTIMER3_RULE - Standard counter/Timer 3 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_SHIFT (8U) +/*! CTIMER4_RULE - Standard counter/Timer 4 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_SHIFT (16U) +/*! RTC_RULE - Real Time Counter + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_SHIFT (20U) +/*! OSEVENT_RULE - OS Event Timer + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1 */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_COUNT (1U) + +/*! @name SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_SHIFT (16U) +/*! FLASH_CTRL_RULE - Flash Controller + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_SHIFT (20U) +/*! PRINCE_RULE - Prince + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2 */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_COUNT (1U) + +/*! @name SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_SHIFT (0U) +/*! USBHPHY_RULE - USB High Speed Phy controller + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_SHIFT (8U) +/*! RNG_RULE - True Random Number Generator + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUFF_RULE_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUFF_RULE_SHIFT (12U) +/*! PUFF_RULE - PUF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUFF_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUFF_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUFF_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_SHIFT (20U) +/*! PLU_RULE - Programmable Look-Up logic + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3 */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_COUNT (1U) + +/*! @name SEC_CTRL_AHB0_0_SLAVE_RULE - Security access rules for AHB peripherals. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_DMA0_RULE_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_DMA0_RULE_SHIFT (8U) +/*! DMA0_RULE - DMA Controller + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_DMA0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_DMA0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_DMA0_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FS_USB_DEV_RULE_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FS_USB_DEV_RULE_SHIFT (16U) +/*! FS_USB_DEV_RULE - USB Full-speed device + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FS_USB_DEV_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FS_USB_DEV_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FS_USB_DEV_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_SCT_RULE_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_SCT_RULE_SHIFT (20U) +/*! SCT_RULE - SCTimer + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_SCT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_SCT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_SCT_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FLEXCOMM0_RULE_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FLEXCOMM0_RULE_SHIFT (24U) +/*! FLEXCOMM0_RULE - Flexcomm interface 0 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FLEXCOMM0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FLEXCOMM0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FLEXCOMM0_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FLEXCOMM1_RULE_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FLEXCOMM1_RULE_SHIFT (28U) +/*! FLEXCOMM1_RULE - Flexcomm interface 1 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FLEXCOMM1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FLEXCOMM1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FLEXCOMM1_RULE_MASK) +/*! @} */ + +/*! @name SEC_CTRL_AHB0_1_SLAVE_RULE - Security access rules for AHB peripherals. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM2_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM2_RULE_SHIFT (0U) +/*! FLEXCOMM2_RULE - Flexcomm interface 2 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM2_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM3_RULE_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM3_RULE_SHIFT (4U) +/*! FLEXCOMM3_RULE - Flexcomm interface 3 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM3_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM4_RULE_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM4_RULE_SHIFT (8U) +/*! FLEXCOMM4_RULE - Flexcomm interface 4 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM4_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM4_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM4_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_MAILBOX_RULE_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_MAILBOX_RULE_SHIFT (12U) +/*! MAILBOX_RULE - Inter CPU communication Mailbox + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_MAILBOX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_MAILBOX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_MAILBOX_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_GPIO0_RULE_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_GPIO0_RULE_SHIFT (16U) +/*! GPIO0_RULE - High Speed GPIO + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_GPIO0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_GPIO0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_GPIO0_RULE_MASK) +/*! @} */ + +/*! @name SEC_CTRL_AHB1_0_SLAVE_RULE - Security access rules for AHB peripherals. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_USB_HS_DEV_RULE_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_USB_HS_DEV_RULE_SHIFT (16U) +/*! USB_HS_DEV_RULE - USB high Speed device registers + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_USB_HS_DEV_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_USB_HS_DEV_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_USB_HS_DEV_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_CRC_RULE_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_CRC_RULE_SHIFT (20U) +/*! CRC_RULE - CRC engine + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_CRC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_CRC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_CRC_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_FLEXCOMM5_RULE_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_FLEXCOMM5_RULE_SHIFT (24U) +/*! FLEXCOMM5_RULE - Flexcomm interface 5 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_FLEXCOMM5_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_FLEXCOMM5_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_FLEXCOMM5_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_FLEXCOMM6_RULE_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_FLEXCOMM6_RULE_SHIFT (28U) +/*! FLEXCOMM6_RULE - Flexcomm interface 6 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_FLEXCOMM6_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_FLEXCOMM6_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_FLEXCOMM6_RULE_MASK) +/*! @} */ + +/*! @name SEC_CTRL_AHB1_1_SLAVE_RULE - Security access rules for AHB peripherals. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_FLEXCOMM7_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_FLEXCOMM7_RULE_SHIFT (0U) +/*! FLEXCOMM7_RULE - Flexcomm interface 7 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_FLEXCOMM7_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_FLEXCOMM7_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_FLEXCOMM7_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_SDIO_RULE_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_SDIO_RULE_SHIFT (12U) +/*! SDIO_RULE - SDMMC card interface + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_SDIO_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_SDIO_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_SDIO_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_DBG_MAILBOX_RULE_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_DBG_MAILBOX_RULE_SHIFT (16U) +/*! DBG_MAILBOX_RULE - Debug mailbox (aka ISP-AP) + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_DBG_MAILBOX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_DBG_MAILBOX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_DBG_MAILBOX_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_HS_LSPI_RULE_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_HS_LSPI_RULE_SHIFT (28U) +/*! HS_LSPI_RULE - High Speed SPI + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_HS_LSPI_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_HS_LSPI_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_HS_LSPI_RULE_MASK) +/*! @} */ + +/*! @name SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE - Security access rules for AHB peripherals. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_ADC_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_ADC_RULE_SHIFT (0U) +/*! ADC_RULE - ADC + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_ADC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_ADC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_ADC_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_USB_FS_HOST_RULE_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_USB_FS_HOST_RULE_SHIFT (8U) +/*! USB_FS_HOST_RULE - USB Full Speed Host registers. + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_USB_FS_HOST_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_USB_FS_HOST_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_USB_FS_HOST_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_USB_HS_HOST_RULE_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_USB_HS_HOST_RULE_SHIFT (12U) +/*! USB_HS_HOST_RULE - USB High speed host registers + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_USB_HS_HOST_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_USB_HS_HOST_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_USB_HS_HOST_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_HASH_RULE_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_HASH_RULE_SHIFT (16U) +/*! HASH_RULE - SHA-2 crypto registers + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_HASH_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_HASH_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_HASH_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_CASPER_RULE_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_CASPER_RULE_SHIFT (20U) +/*! CASPER_RULE - RSA/ECC crypto accelerator + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_CASPER_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_CASPER_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_CASPER_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_PQ_RULE_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_PQ_RULE_SHIFT (24U) +/*! PQ_RULE - Power Quad (CM33 processor hardware accelerator) + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_PQ_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_PQ_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_PQ_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_DMA1_RULE_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_DMA1_RULE_SHIFT (28U) +/*! DMA1_RULE - DMA Controller (Secure) + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_DMA1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_DMA1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_DMA1_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_COUNT (1U) + +/*! @name SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE - Security access rules for AHB peripherals. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE_GPIO1_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE_GPIO1_RULE_SHIFT (0U) +/*! GPIO1_RULE - Secure High Speed GPIO + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE_GPIO1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE_GPIO1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE_GPIO1_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE_AHB_SEC_CTRL_RULE_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE_AHB_SEC_CTRL_RULE_SHIFT (4U) +/*! AHB_SEC_CTRL_RULE - AHB Secure Controller + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE_AHB_SEC_CTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE_AHB_SEC_CTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE_AHB_SEC_CTRL_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE_COUNT (1U) + +/*! @name SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE - Security access rules for AHB_SEC_CTRL_AHB. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_SHIFT (0U) +/*! AHB_SEC_CTRL_SECT_0_RULE - Address space: 0x400A_0000 - 0x400A_CFFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_SHIFT (4U) +/*! AHB_SEC_CTRL_SECT_1_RULE - Address space: 0x400A_D000 - 0x400A_DFFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_SHIFT (8U) +/*! AHB_SEC_CTRL_SECT_2_RULE - Address space: 0x400A_E000 - 0x400A_EFFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_SHIFT (12U) +/*! AHB_SEC_CTRL_SECT_3_RULE - Address space: 0x400A_F000 - 0x400A_FFFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_COUNT (1U) + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_COUNT2 (1U) + +/*! @name SEC_CTRL_USB_HS_SLAVE_RULE - Security access rules for USB High speed RAM slaves. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_SHIFT (0U) +/*! RAM_USB_HS_RULE - Security access rules for the whole USB High Speed RAM : 0x4010_0000 - 0x4010_3FFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_COUNT (1U) + +/*! @name SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE - Security access rules for RAM_USB_HS. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_0_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_0_RULE_SHIFT (0U) +/*! SRAM_SECT_0_RULE - Address space: 0x4010_0000 - 0x4010_0FFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_0_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_1_RULE_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_1_RULE_SHIFT (4U) +/*! SRAM_SECT_1_RULE - Address space: 0x4010_1000 - 0x4010_1FFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_1_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_2_RULE_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_2_RULE_SHIFT (8U) +/*! SRAM_SECT_2_RULE - Address space: 0x4010_2000 - 0x4010_2FFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_2_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_3_RULE_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_3_RULE_SHIFT (12U) +/*! SRAM_SECT_3_RULE - Address space: 0x4010_3000 - 0x4010_3FFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_3_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_COUNT (1U) + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_COUNT2 (1U) + +/*! @name SEC_VIO_ADDR - most recent security violation address for AHB layer n */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_MASK (0xFFFFFFFFU) +#define AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_SHIFT (0U) +#define AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_VIO_ADDR */ +#define AHB_SECURE_CTRL_SEC_VIO_ADDR_COUNT (12U) + +/*! @name SEC_VIO_MISC_INFO - most recent security violation miscellaneous information for AHB layer n */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_MASK (0x1U) +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_SHIFT (0U) +/*! SEC_VIO_INFO_WRITE - security violation access read/write indicator. + * 0b0..Read access. + * 0b1..Write access. + */ +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_MASK) +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_MASK (0x2U) +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_SHIFT (1U) +/*! SEC_VIO_INFO_DATA_ACCESS - security violation access data/code indicator. + * 0b0..Code access. + * 0b1..Data access. + */ +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_MASK) +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_MASK (0xF0U) +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_SHIFT (4U) +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_MASK) +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_MASK (0xF00U) +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SHIFT (8U) +/*! SEC_VIO_INFO_MASTER - security violation master number + * 0b0000..CPU0 Code. + * 0b0001..CPU0 System. + * 0b0010..CPU1 Data. + * 0b0011..CPU1 System. + * 0b0100..USB-HS Device. + * 0b0101..SDMA0. + * 0b1000..SDIO. + * 0b1001..PowerQuad. + * 0b1010..HASH. + * 0b1011..USB-FS Host. + * 0b1100..SDMA1. + */ +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_VIO_MISC_INFO */ +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_COUNT (12U) + +/*! @name SEC_VIO_INFO_VALID - security violation address/information registers valid flags */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_MASK (0x1U) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_SHIFT (0U) +/*! VIO_INFO_VALID0 - violation information valid flag for AHB layer 0. Write 1 to clear. + * 0b0..Not valid. + * 0b1..Valid (violation occurred). + */ +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_MASK) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_MASK (0x2U) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_SHIFT (1U) +/*! VIO_INFO_VALID1 - violation information valid flag for AHB layer 1. Write 1 to clear. + * 0b0..Not valid. + * 0b1..Valid (violation occurred). + */ +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_MASK) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_MASK (0x4U) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_SHIFT (2U) +/*! VIO_INFO_VALID2 - violation information valid flag for AHB layer 2. Write 1 to clear. + * 0b0..Not valid. + * 0b1..Valid (violation occurred). + */ +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_MASK) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_MASK (0x8U) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_SHIFT (3U) +/*! VIO_INFO_VALID3 - violation information valid flag for AHB layer 3. Write 1 to clear. + * 0b0..Not valid. + * 0b1..Valid (violation occurred). + */ +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_MASK) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_MASK (0x10U) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_SHIFT (4U) +/*! VIO_INFO_VALID4 - violation information valid flag for AHB layer 4. Write 1 to clear. + * 0b0..Not valid. + * 0b1..Valid (violation occurred). + */ +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_MASK) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_MASK (0x20U) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_SHIFT (5U) +/*! VIO_INFO_VALID5 - violation information valid flag for AHB layer 5. Write 1 to clear. + * 0b0..Not valid. + * 0b1..Valid (violation occurred). + */ +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_MASK) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_MASK (0x40U) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_SHIFT (6U) +/*! VIO_INFO_VALID6 - violation information valid flag for AHB layer 6. Write 1 to clear. + * 0b0..Not valid. + * 0b1..Valid (violation occurred). + */ +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_MASK) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_MASK (0x80U) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_SHIFT (7U) +/*! VIO_INFO_VALID7 - violation information valid flag for AHB layer 7. Write 1 to clear. + * 0b0..Not valid. + * 0b1..Valid (violation occurred). + */ +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_MASK) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_MASK (0x100U) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_SHIFT (8U) +/*! VIO_INFO_VALID8 - violation information valid flag for AHB layer 8. Write 1 to clear. + * 0b0..Not valid. + * 0b1..Valid (violation occurred). + */ +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_MASK) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_MASK (0x200U) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_SHIFT (9U) +/*! VIO_INFO_VALID9 - violation information valid flag for AHB layer 9. Write 1 to clear. + * 0b0..Not valid. + * 0b1..Valid (violation occurred). + */ +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_MASK) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_MASK (0x400U) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_SHIFT (10U) +/*! VIO_INFO_VALID10 - violation information valid flag for AHB layer 10. Write 1 to clear. + * 0b0..Not valid. + * 0b1..Valid (violation occurred). + */ +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_MASK) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_MASK (0x800U) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_SHIFT (11U) +/*! VIO_INFO_VALID11 - violation information valid flag for AHB layer 11. Write 1 to clear. + * 0b0..Not valid. + * 0b1..Valid (violation occurred). + */ +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_MASK) +/*! @} */ + +/*! @name SEC_GPIO_MASK0 - Secure GPIO mask for port 0 pins. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_MASK (0x1U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_SHIFT (0U) +/*! PIO0_PIN0_SEC_MASK - Secure mask for pin P0_0 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_MASK (0x2U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_SHIFT (1U) +/*! PIO0_PIN1_SEC_MASK - Secure mask for pin P0_1 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_MASK (0x4U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_SHIFT (2U) +/*! PIO0_PIN2_SEC_MASK - Secure mask for pin P0_2 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_MASK (0x8U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_SHIFT (3U) +/*! PIO0_PIN3_SEC_MASK - Secure mask for pin P0_3 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_MASK (0x10U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_SHIFT (4U) +/*! PIO0_PIN4_SEC_MASK - Secure mask for pin P0_4 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_MASK (0x20U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_SHIFT (5U) +/*! PIO0_PIN5_SEC_MASK - Secure mask for pin P0_5 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_MASK (0x40U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_SHIFT (6U) +/*! PIO0_PIN6_SEC_MASK - Secure mask for pin P0_6 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_MASK (0x80U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_SHIFT (7U) +/*! PIO0_PIN7_SEC_MASK - Secure mask for pin P0_7 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_MASK (0x100U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_SHIFT (8U) +/*! PIO0_PIN8_SEC_MASK - Secure mask for pin P0_8 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_MASK (0x200U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_SHIFT (9U) +/*! PIO0_PIN9_SEC_MASK - Secure mask for pin P0_9 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_MASK (0x400U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_SHIFT (10U) +/*! PIO0_PIN10_SEC_MASK - Secure mask for pin P0_10 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_MASK (0x800U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_SHIFT (11U) +/*! PIO0_PIN11_SEC_MASK - Secure mask for pin P0_11 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_MASK (0x1000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_SHIFT (12U) +/*! PIO0_PIN12_SEC_MASK - Secure mask for pin P0_12 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_MASK (0x2000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_SHIFT (13U) +/*! PIO0_PIN13_SEC_MASK - Secure mask for pin P0_13 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_MASK (0x4000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_SHIFT (14U) +/*! PIO0_PIN14_SEC_MASK - Secure mask for pin P0_14 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_MASK (0x8000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_SHIFT (15U) +/*! PIO0_PIN15_SEC_MASK - Secure mask for pin P0_15 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_MASK (0x10000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_SHIFT (16U) +/*! PIO0_PIN16_SEC_MASK - Secure mask for pin P0_16 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_MASK (0x20000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_SHIFT (17U) +/*! PIO0_PIN17_SEC_MASK - Secure mask for pin P0_17 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_MASK (0x40000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_SHIFT (18U) +/*! PIO0_PIN18_SEC_MASK - Secure mask for pin P0_18 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_MASK (0x80000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_SHIFT (19U) +/*! PIO0_PIN19_SEC_MASK - Secure mask for pin P0_19 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_MASK (0x100000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_SHIFT (20U) +/*! PIO0_PIN20_SEC_MASK - Secure mask for pin P0_20 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_MASK (0x200000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_SHIFT (21U) +/*! PIO0_PIN21_SEC_MASK - Secure mask for pin P0_21 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_MASK (0x400000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_SHIFT (22U) +/*! PIO0_PIN22_SEC_MASK - Secure mask for pin P0_22 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_MASK (0x800000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_SHIFT (23U) +/*! PIO0_PIN23_SEC_MASK - Secure mask for pin P0_23 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_MASK (0x1000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_SHIFT (24U) +/*! PIO0_PIN24_SEC_MASK - Secure mask for pin P0_24 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_MASK (0x2000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_SHIFT (25U) +/*! PIO0_PIN25_SEC_MASK - Secure mask for pin P0_25 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_MASK (0x4000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_SHIFT (26U) +/*! PIO0_PIN26_SEC_MASK - Secure mask for pin P0_26 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_MASK (0x8000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_SHIFT (27U) +/*! PIO0_PIN27_SEC_MASK - Secure mask for pin P0_27 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_MASK (0x10000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_SHIFT (28U) +/*! PIO0_PIN28_SEC_MASK - Secure mask for pin P0_28 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_MASK (0x20000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_SHIFT (29U) +/*! PIO0_PIN29_SEC_MASK - Secure mask for pin P0_29 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_MASK (0x40000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_SHIFT (30U) +/*! PIO0_PIN30_SEC_MASK - Secure mask for pin P0_30 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_MASK (0x80000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_SHIFT (31U) +/*! PIO0_PIN31_SEC_MASK - Secure mask for pin P0_31 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_MASK) +/*! @} */ + +/*! @name SEC_GPIO_MASK1 - Secure GPIO mask for port 1 pins. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_MASK (0x1U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_SHIFT (0U) +/*! PIO1_PIN0_SEC_MASK - Secure mask for pin P1_0 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_MASK (0x2U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_SHIFT (1U) +/*! PIO1_PIN1_SEC_MASK - Secure mask for pin P1_1 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_MASK (0x4U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_SHIFT (2U) +/*! PIO1_PIN2_SEC_MASK - Secure mask for pin P1_2 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_MASK (0x8U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_SHIFT (3U) +/*! PIO1_PIN3_SEC_MASK - Secure mask for pin P1_3 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_MASK (0x10U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_SHIFT (4U) +/*! PIO1_PIN4_SEC_MASK - Secure mask for pin P1_4 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_MASK (0x20U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_SHIFT (5U) +/*! PIO1_PIN5_SEC_MASK - Secure mask for pin P1_5 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_MASK (0x40U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_SHIFT (6U) +/*! PIO1_PIN6_SEC_MASK - Secure mask for pin P1_6 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_MASK (0x80U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_SHIFT (7U) +/*! PIO1_PIN7_SEC_MASK - Secure mask for pin P1_7 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_MASK (0x100U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_SHIFT (8U) +/*! PIO1_PIN8_SEC_MASK - Secure mask for pin P1_8 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_MASK (0x200U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_SHIFT (9U) +/*! PIO1_PIN9_SEC_MASK - Secure mask for pin P1_9 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_MASK (0x400U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_SHIFT (10U) +/*! PIO1_PIN10_SEC_MASK - Secure mask for pin P1_10 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_MASK (0x800U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_SHIFT (11U) +/*! PIO1_PIN11_SEC_MASK - Secure mask for pin P1_11 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_MASK (0x1000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_SHIFT (12U) +/*! PIO1_PIN12_SEC_MASK - Secure mask for pin P1_12 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_MASK (0x2000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_SHIFT (13U) +/*! PIO1_PIN13_SEC_MASK - Secure mask for pin P1_13 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_MASK (0x4000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_SHIFT (14U) +/*! PIO1_PIN14_SEC_MASK - Secure mask for pin P1_14 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_MASK (0x8000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_SHIFT (15U) +/*! PIO1_PIN15_SEC_MASK - Secure mask for pin P1_15 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_MASK (0x10000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_SHIFT (16U) +/*! PIO1_PIN16_SEC_MASK - Secure mask for pin P1_16 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_MASK (0x20000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_SHIFT (17U) +/*! PIO1_PIN17_SEC_MASK - Secure mask for pin P1_17 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_MASK (0x40000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_SHIFT (18U) +/*! PIO1_PIN18_SEC_MASK - Secure mask for pin P1_18 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_MASK (0x80000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_SHIFT (19U) +/*! PIO1_PIN19_SEC_MASK - Secure mask for pin P1_19 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_MASK (0x100000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_SHIFT (20U) +/*! PIO1_PIN20_SEC_MASK - Secure mask for pin P1_20 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_MASK (0x200000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_SHIFT (21U) +/*! PIO1_PIN21_SEC_MASK - Secure mask for pin P1_21 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_MASK (0x400000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_SHIFT (22U) +/*! PIO1_PIN22_SEC_MASK - Secure mask for pin P1_22 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_MASK (0x800000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_SHIFT (23U) +/*! PIO1_PIN23_SEC_MASK - Secure mask for pin P1_23 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_MASK (0x1000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_SHIFT (24U) +/*! PIO1_PIN24_SEC_MASK - Secure mask for pin P1_24 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_MASK (0x2000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_SHIFT (25U) +/*! PIO1_PIN25_SEC_MASK - Secure mask for pin P1_25 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_MASK (0x4000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_SHIFT (26U) +/*! PIO1_PIN26_SEC_MASK - Secure mask for pin P1_26 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_MASK (0x8000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_SHIFT (27U) +/*! PIO1_PIN27_SEC_MASK - Secure mask for pin P1_27 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_MASK (0x10000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_SHIFT (28U) +/*! PIO1_PIN28_SEC_MASK - Secure mask for pin P1_28 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_MASK (0x20000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_SHIFT (29U) +/*! PIO1_PIN29_SEC_MASK - Secure mask for pin P1_29 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_MASK (0x40000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_SHIFT (30U) +/*! PIO1_PIN30_SEC_MASK - Secure mask for pin P1_30 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_MASK (0x80000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_SHIFT (31U) +/*! PIO1_PIN31_SEC_MASK - Secure mask for pin P1_31 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_MASK) +/*! @} */ + +/*! @name SEC_CPU_INT_MASK0 - Secure Interrupt mask for CPU1 */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ_MASK (0x1U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ_SHIFT (0U) +/*! SYS_IRQ - Watchdog Timer, Brown Out Detectors and Flash Controller interrupts + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ_MASK (0x2U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ_SHIFT (1U) +/*! SDMA0_IRQ - System DMA 0 (non-secure) interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ_MASK (0x4U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ_SHIFT (2U) +/*! GPIO_GLOBALINT0_IRQ - GPIO Group 0 interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ_MASK (0x8U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ_SHIFT (3U) +/*! GPIO_GLOBALINT1_IRQ - GPIO Group 1 interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0_MASK (0x10U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0_SHIFT (4U) +/*! GPIO_INT0_IRQ0 - Pin interrupt 0 or pattern match engine slice 0 interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1_MASK (0x20U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1_SHIFT (5U) +/*! GPIO_INT0_IRQ1 - Pin interrupt 1 or pattern match engine slice 1 interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2_MASK (0x40U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2_SHIFT (6U) +/*! GPIO_INT0_IRQ2 - Pin interrupt 2 or pattern match engine slice 2 interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3_MASK (0x80U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3_SHIFT (7U) +/*! GPIO_INT0_IRQ3 - Pin interrupt 3 or pattern match engine slice 3 interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ_MASK (0x100U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ_SHIFT (8U) +/*! UTICK_IRQ - Micro Tick Timer interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ_MASK (0x200U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ_SHIFT (9U) +/*! MRT_IRQ - Multi-Rate Timer interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ_MASK (0x400U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ_SHIFT (10U) +/*! CTIMER0_IRQ - Standard counter/timer 0 interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ_MASK (0x800U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ_SHIFT (11U) +/*! CTIMER1_IRQ - Standard counter/timer 1 interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ_MASK (0x1000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ_SHIFT (12U) +/*! SCT_IRQ - SCTimer/PWM interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ_MASK (0x2000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ_SHIFT (13U) +/*! CTIMER3_IRQ - Standard counter/timer 3 interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ_MASK (0x4000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ_SHIFT (14U) +/*! FLEXCOMM0_IRQ - Flexcomm 0 interrupt (USART, SPI, I2C, I2S). + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ_MASK (0x8000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ_SHIFT (15U) +/*! FLEXCOMM1_IRQ - Flexcomm 1 interrupt (USART, SPI, I2C, I2S). + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ_MASK (0x10000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ_SHIFT (16U) +/*! FLEXCOMM2_IRQ - Flexcomm 2 interrupt (USART, SPI, I2C, I2S). + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ_MASK (0x20000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ_SHIFT (17U) +/*! FLEXCOMM3_IRQ - Flexcomm 3 interrupt (USART, SPI, I2C, I2S). + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ_MASK (0x40000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ_SHIFT (18U) +/*! FLEXCOMM4_IRQ - Flexcomm 4 interrupt (USART, SPI, I2C, I2S). + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ_MASK (0x80000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ_SHIFT (19U) +/*! FLEXCOMM5_IRQ - Flexcomm 5 interrupt (USART, SPI, I2C, I2S). + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ_MASK (0x100000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ_SHIFT (20U) +/*! FLEXCOMM6_IRQ - Flexcomm 6 interrupt (USART, SPI, I2C, I2S). + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ_MASK (0x200000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ_SHIFT (21U) +/*! FLEXCOMM7_IRQ - Flexcomm 7 interrupt (USART, SPI, I2C, I2S). + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ_MASK (0x400000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ_SHIFT (22U) +/*! ADC_IRQ - General Purpose ADC interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0_MASK (0x800000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0_SHIFT (23U) +/*! RESERVED0 - Reserved. Read value is undefined, only zero should be written. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_CAPT0_IRQ_MASK (0x1000000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_CAPT0_IRQ_SHIFT (24U) +/*! ACMP_CAPT0_IRQ - Analog Comparator interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_CAPT0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_CAPT0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_CAPT0_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1_MASK (0x2000000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1_SHIFT (25U) +/*! RESERVED1 - Reserved. Read value is undefined, only zero should be written. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2_MASK (0x4000000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2_SHIFT (26U) +/*! RESERVED2 - Reserved. Read value is undefined, only zero should be written. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK_MASK (0x8000000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK_SHIFT (27U) +/*! USB0_NEEDCLK - USB Full Speed Controller Clock request interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ_MASK (0x10000000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ_SHIFT (28U) +/*! USB0_IRQ - USB High Speed Controller interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ_MASK (0x20000000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ_SHIFT (29U) +/*! RTC_IRQ - RTC_LITE0_ALARM_IRQ, RTC_LITE0_WAKEUP_IRQ + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3_MASK (0x40000000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3_SHIFT (30U) +/*! RESERVED3 - Reserved. Read value is undefined, only zero should be written. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ_MASK (0x80000000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ_SHIFT (31U) +/*! MAILBOX_IRQ - Mailbox interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ_MASK) +/*! @} */ + +/*! @name SEC_CPU_INT_MASK1 - Secure Interrupt mask for CPU1 */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4_MASK (0x1U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4_SHIFT (0U) +/*! GPIO_INT0_IRQ4 - Pin interrupt 4 or pattern match engine slice 4 interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5_MASK (0x2U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5_SHIFT (1U) +/*! GPIO_INT0_IRQ5 - Pin interrupt 5 or pattern match engine slice 5 interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6_MASK (0x4U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6_SHIFT (2U) +/*! GPIO_INT0_IRQ6 - Pin interrupt 6 or pattern match engine slice 6 interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7_MASK (0x8U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7_SHIFT (3U) +/*! GPIO_INT0_IRQ7 - Pin interrupt 7 or pattern match engine slice 7 interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ_MASK (0x10U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ_SHIFT (4U) +/*! CTIMER2_IRQ - Standard counter/timer 2 interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ_MASK (0x20U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ_SHIFT (5U) +/*! CTIMER4_IRQ - Standard counter/timer 4 interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ_MASK (0x40U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ_SHIFT (6U) +/*! OS_EVENT_TIMER_IRQ - OS Event Timer and OS Event Timer Wakeup interrupts + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0_MASK (0x80U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0_SHIFT (7U) +/*! RESERVED0 - Reserved. Read value is undefined, only zero should be written. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1_MASK (0x100U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1_SHIFT (8U) +/*! RESERVED1 - Reserved. Read value is undefined, only zero should be written. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2_MASK (0x200U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2_SHIFT (9U) +/*! RESERVED2 - Reserved. Read value is undefined, only zero should be written. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ_MASK (0x400U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ_SHIFT (10U) +/*! SDIO_IRQ - SDIO Controller interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3_MASK (0x800U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3_SHIFT (11U) +/*! RESERVED3 - Reserved. Read value is undefined, only zero should be written. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4_MASK (0x1000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4_SHIFT (12U) +/*! RESERVED4 - Reserved. Read value is undefined, only zero should be written. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5_MASK (0x2000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5_SHIFT (13U) +/*! RESERVED5 - Reserved. Read value is undefined, only zero should be written. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_UTMI_IRQ_MASK (0x4000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_UTMI_IRQ_SHIFT (14U) +/*! USB1_UTMI_IRQ - USB High Speed Controller UTMI interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_UTMI_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_UTMI_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_UTMI_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ_MASK (0x8000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ_SHIFT (15U) +/*! USB1_IRQ - USB High Speed Controller interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK_MASK (0x10000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK_SHIFT (16U) +/*! USB1_NEEDCLK - USB High Speed Controller Clock request interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ_MASK (0x20000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ_SHIFT (17U) +/*! SEC_HYPERVISOR_CALL_IRQ - Secure fault Hyper Visor call interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0_MASK (0x40000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0_SHIFT (18U) +/*! SEC_GPIO_INT0_IRQ0 - Secure Pin interrupt 0 or pattern match engine slice 0 interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1_MASK (0x80000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1_SHIFT (19U) +/*! SEC_GPIO_INT0_IRQ1 - Secure Pin interrupt 1 or pattern match engine slice 1 interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ_MASK (0x100000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ_SHIFT (20U) +/*! PLU_IRQ - Programmable Look-Up Controller interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ_MASK (0x200000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ_SHIFT (21U) +/*! SEC_VIO_IRQ - Security Violation interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ_MASK (0x400000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ_SHIFT (22U) +/*! SHA_IRQ - HASH-AES interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ_MASK (0x800000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ_SHIFT (23U) +/*! CASPER_IRQ - CASPER interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_QDDKEY_IRQ_MASK (0x1000000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_QDDKEY_IRQ_SHIFT (24U) +/*! QDDKEY_IRQ - PUF interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_QDDKEY_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_QDDKEY_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_QDDKEY_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ_MASK (0x2000000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ_SHIFT (25U) +/*! PQ_IRQ - Power Quad interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ_MASK (0x4000000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ_SHIFT (26U) +/*! SDMA1_IRQ - System DMA 1 (Secure) interrupt + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ_MASK (0x8000000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ_SHIFT (27U) +/*! LSPI_HS_IRQ - High Speed SPI interrupt + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ_MASK) +/*! @} */ + +/*! @name SEC_MASK_LOCK - Security General Purpose register access control. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_SHIFT (0U) +/*! SEC_GPIO_MASK0_LOCK - SEC_GPIO_MASK0 register write-lock. + * 0b10..Writable. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_MASK) +#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_MASK (0xCU) +#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_SHIFT (2U) +/*! SEC_GPIO_MASK1_LOCK - SEC_GPIO_MASK1 register write-lock. + * 0b10..Writable. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_MASK) +#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK_SHIFT (8U) +/*! SEC_CPU1_INT_MASK0_LOCK - SEC_CPU_INT_MASK0 register write-lock. + * 0b10..Writable. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK_MASK) +#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK_MASK (0xC00U) +#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK_SHIFT (10U) +/*! SEC_CPU1_INT_MASK1_LOCK - SEC_CPU_INT_MASK1 register write-lock. + * 0b10..Writable. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK_MASK) +/*! @} */ + +/*! @name MASTER_SEC_LEVEL - master secure level register */ +/*! @{ */ +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MCM33C_MASK (0x30U) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MCM33C_SHIFT (4U) +/*! MCM33C - Micro-CM33 (CPU1) Code bus. + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MCM33C(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MCM33C_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MCM33C_MASK) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MCM33S_MASK (0xC0U) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MCM33S_SHIFT (6U) +/*! MCM33S - Micro-CM33 (CPU1) System bus. + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MCM33S(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MCM33S_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MCM33S_MASK) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_MASK (0x300U) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_SHIFT (8U) +/*! USBFSD - USB Full Speed Device. + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_MASK) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_MASK (0xC00U) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_SHIFT (10U) +/*! SDMA0 - System DMA 0. + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_MASK) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO_MASK (0x30000U) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO_SHIFT (16U) +/*! SDIO - SDIO. + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO_MASK) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ_MASK (0xC0000U) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ_SHIFT (18U) +/*! PQ - Power Quad. + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ_MASK) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_MASK (0x300000U) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_SHIFT (20U) +/*! HASH - Hash. + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_MASK) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_MASK (0xC00000U) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_SHIFT (22U) +/*! USBFSH - USB Full speed Host. + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_MASK) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_MASK (0x3000000U) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_SHIFT (24U) +/*! SDMA1 - System DMA 1 security level. + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_MASK) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_MASK (0xC0000000U) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_SHIFT (30U) +/*! MASTER_SEC_LEVEL_LOCK - MASTER_SEC_LEVEL write-lock. + * 0b10..Writable. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_MASK) +/*! @} */ + +/*! @name MASTER_SEC_ANTI_POL_REG - master secure level anti-pole register */ +/*! @{ */ +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MCM33C_MASK (0x30U) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MCM33C_SHIFT (4U) +/*! MCM33C - Micro-CM33 (CPU1) Code bus. Must be equal to NOT(MASTER_SEC_LEVEL.MCM33C) + * 0b11..Non-secure and Non-priviledge user access allowed. + * 0b10..Non-secure and Privilege access allowed. + * 0b01..Secure and Non-priviledge user access allowed. + * 0b00..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MCM33C(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MCM33C_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MCM33C_MASK) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MCM33S_MASK (0xC0U) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MCM33S_SHIFT (6U) +/*! MCM33S - Micro-CM33 (CPU1) System bus. Must be equal to NOT(MASTER_SEC_LEVEL.MCM33S) + * 0b11..Non-secure and Non-priviledge user access allowed. + * 0b10..Non-secure and Privilege access allowed. + * 0b01..Secure and Non-priviledge user access allowed. + * 0b00..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MCM33S(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MCM33S_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MCM33S_MASK) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_MASK (0x300U) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_SHIFT (8U) +/*! USBFSD - USB Full Speed Device. Must be equal to NOT(MASTER_SEC_LEVEL.USBFSD) + * 0b11..Non-secure and Non-priviledge user access allowed. + * 0b10..Non-secure and Privilege access allowed. + * 0b01..Secure and Non-priviledge user access allowed. + * 0b00..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_MASK) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_MASK (0xC00U) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_SHIFT (10U) +/*! SDMA0 - System DMA 0. Must be equal to NOT(MASTER_SEC_LEVEL.SDMA0) + * 0b11..Non-secure and Non-priviledge user access allowed. + * 0b10..Non-secure and Privilege access allowed. + * 0b01..Secure and Non-priviledge user access allowed. + * 0b00..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_MASK) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO_MASK (0x30000U) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO_SHIFT (16U) +/*! SDIO - SDIO. Must be equal to NOT(MASTER_SEC_LEVEL.SDIO) + * 0b11..Non-secure and Non-priviledge user access allowed. + * 0b10..Non-secure and Privilege access allowed. + * 0b01..Secure and Non-priviledge user access allowed. + * 0b00..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO_MASK) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ_MASK (0xC0000U) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ_SHIFT (18U) +/*! PQ - Power Quad. Must be equal to NOT(MASTER_SEC_LEVEL.PQ) + * 0b11..Non-secure and Non-priviledge user access allowed. + * 0b10..Non-secure and Privilege access allowed. + * 0b01..Secure and Non-priviledge user access allowed. + * 0b00..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ_MASK) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_MASK (0x300000U) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_SHIFT (20U) +/*! HASH - Hash. Must be equal to NOT(MASTER_SEC_LEVEL.HASH) + * 0b11..Non-secure and Non-priviledge user access allowed. + * 0b10..Non-secure and Privilege access allowed. + * 0b01..Secure and Non-priviledge user access allowed. + * 0b00..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_MASK) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_MASK (0xC00000U) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_SHIFT (22U) +/*! USBFSH - USB Full speed Host. Must be equal to NOT(MASTER_SEC_LEVEL.USBFSH) + * 0b11..Non-secure and Non-priviledge user access allowed. + * 0b10..Non-secure and Privilege access allowed. + * 0b01..Secure and Non-priviledge user access allowed. + * 0b00..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_MASK) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_MASK (0x3000000U) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_SHIFT (24U) +/*! SDMA1 - System DMA 1 security level. Must be equal to NOT(MASTER_SEC_LEVEL.SDMA1) + * 0b11..Non-secure and Non-priviledge user access allowed. + * 0b10..Non-secure and Privilege access allowed. + * 0b01..Secure and Non-priviledge user access allowed. + * 0b00..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_MASK) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_MASK (0xC0000000U) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_SHIFT (30U) +/*! MASTER_SEC_LEVEL_ANTIPOL_LOCK - MASTER_SEC_ANTI_POL_REG register write-lock. + * 0b10..Writable. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_MASK) +/*! @} */ + +/*! @name CM33_LOCK_REG - Miscalleneous control signals for in CM33 (CPU0) */ +/*! @{ */ +#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_NS_VTOR_MASK (0x3U) +#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_NS_VTOR_SHIFT (0U) +/*! LOCK_NS_VTOR - CM33 (CPU0) VTOR_NS register write-lock. + * 0b10..Writable. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_NS_VTOR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_NS_VTOR_SHIFT)) & AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_NS_VTOR_MASK) +#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_NS_MPU_MASK (0xCU) +#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_NS_MPU_SHIFT (2U) +/*! LOCK_NS_MPU - CM33 (CPU0) non-secure MPU register write-lock. + * 0b10..Writable. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_NS_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_NS_MPU_SHIFT)) & AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_NS_MPU_MASK) +#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_S_VTAIRCR_MASK (0x30U) +#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_S_VTAIRCR_SHIFT (4U) +/*! LOCK_S_VTAIRCR - CM33 (CPU0) VTOR_S, AIRCR.PRIS, IRCR.BFHFNMINS registers write-lock. + * 0b10..Writable. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_S_VTAIRCR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_S_VTAIRCR_SHIFT)) & AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_S_VTAIRCR_MASK) +#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_S_MPU_MASK (0xC0U) +#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_S_MPU_SHIFT (6U) +/*! LOCK_S_MPU - CM33 (CPU0) Secure MPU registers write-lock. + * 0b10..Writable. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_S_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_S_MPU_SHIFT)) & AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_S_MPU_MASK) +#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_SAU_MASK (0x300U) +#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_SAU_SHIFT (8U) +/*! LOCK_SAU - CM33 (CPU0) SAU registers write-lock. + * 0b10..Writable. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_SAU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_SAU_SHIFT)) & AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_SAU_MASK) +#define AHB_SECURE_CTRL_CM33_LOCK_REG_CM33_LOCK_REG_LOCK_MASK (0xC0000000U) +#define AHB_SECURE_CTRL_CM33_LOCK_REG_CM33_LOCK_REG_LOCK_SHIFT (30U) +/*! CM33_LOCK_REG_LOCK - CM33_LOCK_REG write-lock. + * 0b10..Writable. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_CM33_LOCK_REG_CM33_LOCK_REG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CM33_LOCK_REG_CM33_LOCK_REG_LOCK_SHIFT)) & AHB_SECURE_CTRL_CM33_LOCK_REG_CM33_LOCK_REG_LOCK_MASK) +/*! @} */ + +/*! @name MCM33_LOCK_REG - Miscalleneous control signals for in micro-CM33 (CPU1) */ +/*! @{ */ +#define AHB_SECURE_CTRL_MCM33_LOCK_REG_LOCK_NS_VTOR_MASK (0x3U) +#define AHB_SECURE_CTRL_MCM33_LOCK_REG_LOCK_NS_VTOR_SHIFT (0U) +/*! LOCK_NS_VTOR - micro-CM33 (CPU1) VTOR_NS register write-lock. + * 0b10..Writable. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_MCM33_LOCK_REG_LOCK_NS_VTOR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MCM33_LOCK_REG_LOCK_NS_VTOR_SHIFT)) & AHB_SECURE_CTRL_MCM33_LOCK_REG_LOCK_NS_VTOR_MASK) +#define AHB_SECURE_CTRL_MCM33_LOCK_REG_LOCK_NS_MPU_MASK (0xCU) +#define AHB_SECURE_CTRL_MCM33_LOCK_REG_LOCK_NS_MPU_SHIFT (2U) +/*! LOCK_NS_MPU - micro-CM33 (CPU1) non-secure MPU register write-lock. + * 0b10..Writable. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_MCM33_LOCK_REG_LOCK_NS_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MCM33_LOCK_REG_LOCK_NS_MPU_SHIFT)) & AHB_SECURE_CTRL_MCM33_LOCK_REG_LOCK_NS_MPU_MASK) +#define AHB_SECURE_CTRL_MCM33_LOCK_REG_MCM33_LOCK_REG_LOCK_MASK (0xC0000000U) +#define AHB_SECURE_CTRL_MCM33_LOCK_REG_MCM33_LOCK_REG_LOCK_SHIFT (30U) +/*! MCM33_LOCK_REG_LOCK - MCM33_LOCK_REG write-lock. + * 0b10..Writable. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_MCM33_LOCK_REG_MCM33_LOCK_REG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MCM33_LOCK_REG_MCM33_LOCK_REG_LOCK_SHIFT)) & AHB_SECURE_CTRL_MCM33_LOCK_REG_MCM33_LOCK_REG_LOCK_MASK) +/*! @} */ + +/*! @name MISC_CTRL_DP_REG - secure control duplicate register */ +/*! @{ */ +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_MASK (0x3U) +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_SHIFT (0U) +/*! WRITE_LOCK - write lock. + * 0b10..Secure control registers can be written. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_MASK) +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_MASK (0xCU) +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_SHIFT (2U) +/*! ENABLE_SECURE_CHECKING - AHB bus matrix enable secure check. + * 0b10..Disable check. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_MASK) +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_MASK (0x30U) +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_SHIFT (4U) +/*! ENABLE_S_PRIV_CHECK - AHB bus matrix enable secure privilege check. + * 0b10..Disable check. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_MASK) +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_MASK (0xC0U) +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_SHIFT (6U) +/*! ENABLE_NS_PRIV_CHECK - AHB bus matrix enable non-secure privilege check. + * 0b10..Disable check. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_MASK) +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_MASK (0x300U) +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_SHIFT (8U) +/*! DISABLE_VIOLATION_ABORT - Disable secure violation abort. + * 0b10..Enable abort fort secure checker. + * 0b01..Disable abort fort secure checker. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_MASK) +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK (0xC00U) +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT (10U) +/*! DISABLE_SIMPLE_MASTER_STRICT_MODE - Disable simple master strict mode. + * 0b10..Simple master in strict mode. + * 0b01..Simple master in tier mode. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK) +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK (0x3000U) +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT (12U) +/*! DISABLE_SMART_MASTER_STRICT_MODE - Disable smart master strict mode. + * 0b10..Smart master in strict mode. + * 0b01..Smart master in tier mode. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK) +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_MASK (0xC000U) +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_SHIFT (14U) +/*! IDAU_ALL_NS - Disable IDAU. + * 0b10..IDAU is enabled. + * 0b01..IDAU is disable. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_MASK) +/*! @} */ + +/*! @name MISC_CTRL_REG - secure control register */ +/*! @{ */ +#define AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_MASK (0x3U) +#define AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_SHIFT (0U) +/*! WRITE_LOCK - write lock. + * 0b10..Secure control registers can be written. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_MASK) +#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_MASK (0xCU) +#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_SHIFT (2U) +/*! ENABLE_SECURE_CHECKING - AHB bus matrix enable secure check. + * 0b10..Disable check. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_MASK) +#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_MASK (0x30U) +#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_SHIFT (4U) +/*! ENABLE_S_PRIV_CHECK - AHB bus matrix enable secure privilege check. + * 0b10..Disable check. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_MASK) +#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_MASK (0xC0U) +#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_SHIFT (6U) +/*! ENABLE_NS_PRIV_CHECK - AHB bus matrix enable non-secure privilege check. + * 0b10..Disable check. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_MASK) +#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_MASK (0x300U) +#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_SHIFT (8U) +/*! DISABLE_VIOLATION_ABORT - Disable secure violation abort. + * 0b10..Enable abort fort secure checker. + * 0b01..Disable abort fort secure checker. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_MASK) +#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK (0xC00U) +#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT (10U) +/*! DISABLE_SIMPLE_MASTER_STRICT_MODE - Disable simple master strict mode. + * 0b10..Simple master in strict mode. + * 0b01..Simple master in tier mode. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK) +#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK (0x3000U) +#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT (12U) +/*! DISABLE_SMART_MASTER_STRICT_MODE - Disable smart master strict mode. + * 0b10..Smart master in strict mode. + * 0b01..Smart master in tier mode. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK) +#define AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_MASK (0xC000U) +#define AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_SHIFT (14U) +/*! IDAU_ALL_NS - Disable IDAU. + * 0b10..IDAU is enabled. + * 0b01..IDAU is disable. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group AHB_SECURE_CTRL_Register_Masks */ + + +/* AHB_SECURE_CTRL - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral AHB_SECURE_CTRL base address */ + #define AHB_SECURE_CTRL_BASE (0x500AC000u) + /** Peripheral AHB_SECURE_CTRL base address */ + #define AHB_SECURE_CTRL_BASE_NS (0x400AC000u) + /** Peripheral AHB_SECURE_CTRL base pointer */ + #define AHB_SECURE_CTRL ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_BASE) + /** Peripheral AHB_SECURE_CTRL base pointer */ + #define AHB_SECURE_CTRL_NS ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_BASE_NS) + /** Array initializer of AHB_SECURE_CTRL peripheral base addresses */ + #define AHB_SECURE_CTRL_BASE_ADDRS { AHB_SECURE_CTRL_BASE } + /** Array initializer of AHB_SECURE_CTRL peripheral base pointers */ + #define AHB_SECURE_CTRL_BASE_PTRS { AHB_SECURE_CTRL } + /** Array initializer of AHB_SECURE_CTRL peripheral base addresses */ + #define AHB_SECURE_CTRL_BASE_ADDRS_NS { AHB_SECURE_CTRL_BASE_NS } + /** Array initializer of AHB_SECURE_CTRL peripheral base pointers */ + #define AHB_SECURE_CTRL_BASE_PTRS_NS { AHB_SECURE_CTRL_NS } +#else + /** Peripheral AHB_SECURE_CTRL base address */ + #define AHB_SECURE_CTRL_BASE (0x400AC000u) + /** Peripheral AHB_SECURE_CTRL base pointer */ + #define AHB_SECURE_CTRL ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_BASE) + /** Array initializer of AHB_SECURE_CTRL peripheral base addresses */ + #define AHB_SECURE_CTRL_BASE_ADDRS { AHB_SECURE_CTRL_BASE } + /** Array initializer of AHB_SECURE_CTRL peripheral base pointers */ + #define AHB_SECURE_CTRL_BASE_PTRS { AHB_SECURE_CTRL } +#endif + +/*! + * @} + */ /* end of group AHB_SECURE_CTRL_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- ANACTRL Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ANACTRL_Peripheral_Access_Layer ANACTRL Peripheral Access Layer + * @{ + */ + +/** ANACTRL - Register Layout Typedef */ +typedef struct { + __IO uint32_t ANALOG_CTRL_CFG; /**< Various Analog blocks configuration (like FRO 192MHz trimmings source ...), offset: 0x0 */ + __I uint32_t ANALOG_CTRL_STATUS; /**< Analog Macroblock Identity registers, Flash Status registers, offset: 0x4 */ + uint8_t RESERVED_0[4]; + __IO uint32_t FREQ_ME_CTRL; /**< Frequency Measure function control register, offset: 0xC */ + __IO uint32_t FRO192M_CTRL; /**< 192MHz Free Running OScillator (FRO) Control register, offset: 0x10 */ + __I uint32_t FRO192M_STATUS; /**< 192MHz Free Running OScillator (FRO) Status register, offset: 0x14 */ + __IO uint32_t ADC_CTRL; /**< General Purpose ADC VBAT Divider branch control, offset: 0x18 */ + uint8_t RESERVED_1[4]; + __IO uint32_t XO32M_CTRL; /**< 32 MHz Crystal Oscillator Control register, offset: 0x20 */ + __I uint32_t XO32M_STATUS; /**< 32 MHz Crystal Oscillator Status register, offset: 0x24 */ + uint8_t RESERVED_2[8]; + __IO uint32_t BOD_DCDC_INT_CTRL; /**< Brown Out Detectors (BoDs) & DCDC interrupts generation control register, offset: 0x30 */ + __I uint32_t BOD_DCDC_INT_STATUS; /**< BoDs & DCDC interrupts status register, offset: 0x34 */ + uint8_t RESERVED_3[8]; + __IO uint32_t RINGO0_CTRL; /**< First Ring Oscillator module control register., offset: 0x40 */ + __IO uint32_t RINGO1_CTRL; /**< Second Ring Oscillator module control register., offset: 0x44 */ + __IO uint32_t RINGO2_CTRL; /**< Third Ring Oscillator module control register., offset: 0x48 */ + uint8_t RESERVED_4[100]; + __IO uint32_t LDO_XO32M; /**< High Speed Crystal Oscillator (12 MHz - 32 MHz) Voltage Source Supply Control register, offset: 0xB0 */ + uint8_t RESERVED_5[12]; + __IO uint32_t XO_CAL_CFG; /**< All Crystal Oscillators (both the 32 KHz and the High speed) Capacitive Banks Calibration Configuration register, offset: 0xC0 */ + __IO uint32_t XO_CAL_CMD; /**< All Crystal Oscillators (both the 32 KHz and the High Speed) Capacitive Banks Calibration Command register., offset: 0xC4 */ + __I uint32_t XO_CAL_STATUS; /**< All Crystal Oscillators (both the 32 KHz and the High speed) Capacitive Banks Calibration Status register., offset: 0xC8 */ + uint8_t RESERVED_6[52]; + __IO uint32_t USBHS_PHY_CTRL; /**< USB High Speed Phy Control, offset: 0x100 */ + __IO uint32_t USBHS_PHY_TRIM; /**< USB High Speed Phy Trim values, offset: 0x104 */ + __I uint32_t USBHS_PHY_STATUS; /**< USB High Speed Phy Status, offset: 0x108 */ +} ANACTRL_Type; + +/* ---------------------------------------------------------------------------- + -- ANACTRL Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ANACTRL_Register_Masks ANACTRL Register Masks + * @{ + */ + +/*! @name ANALOG_CTRL_CFG - Various Analog blocks configuration (like FRO 192MHz trimmings source ...) */ +/*! @{ */ +#define ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC_MASK (0x1U) +#define ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC_SHIFT (0U) +/*! FRO192M_TRIM_SRC - FRO192M trimming and 'Enable' source. + * 0b0..FRO192M trimming and 'Enable' comes from eFUSE. + * 0b1..FRO192M trimming and 'Enable' comes from FRO192M_CTRL registers. + */ +#define ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC_SHIFT)) & ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC_MASK) +/*! @} */ + +/*! @name ANALOG_CTRL_STATUS - Analog Macroblock Identity registers, Flash Status registers */ +/*! @{ */ +#define ANACTRL_ANALOG_CTRL_STATUS_PMU_ID_MASK (0x3FU) +#define ANACTRL_ANALOG_CTRL_STATUS_PMU_ID_SHIFT (0U) +#define ANACTRL_ANALOG_CTRL_STATUS_PMU_ID(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_STATUS_PMU_ID_SHIFT)) & ANACTRL_ANALOG_CTRL_STATUS_PMU_ID_MASK) +#define ANACTRL_ANALOG_CTRL_STATUS_OSC_ID_MASK (0xFC0U) +#define ANACTRL_ANALOG_CTRL_STATUS_OSC_ID_SHIFT (6U) +#define ANACTRL_ANALOG_CTRL_STATUS_OSC_ID(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_STATUS_OSC_ID_SHIFT)) & ANACTRL_ANALOG_CTRL_STATUS_OSC_ID_MASK) +#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_MASK (0x1000U) +#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_SHIFT (12U) +/*! FLASH_PWRDWN - Flash Power Down status. + * 0b0..Flash is not in power down mode. + * 0b1..Flash is in power down mode. + */ +#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_SHIFT)) & ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_MASK) +#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_MASK (0x2000U) +#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_SHIFT (13U) +/*! FLASH_INIT_ERROR - Flash initialization error status. + * 0b0..No error. + * 0b1..At least one error occured during flash initialization.. + */ +#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_SHIFT)) & ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_MASK) +#define ANACTRL_ANALOG_CTRL_STATUS_FINAL_TEST_DONE_VECT_MASK (0xF0000000U) +#define ANACTRL_ANALOG_CTRL_STATUS_FINAL_TEST_DONE_VECT_SHIFT (28U) +#define ANACTRL_ANALOG_CTRL_STATUS_FINAL_TEST_DONE_VECT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_STATUS_FINAL_TEST_DONE_VECT_SHIFT)) & ANACTRL_ANALOG_CTRL_STATUS_FINAL_TEST_DONE_VECT_MASK) +/*! @} */ + +/*! @name FREQ_ME_CTRL - Frequency Measure function control register */ +/*! @{ */ +#define ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_MASK (0x7FFFFFFFU) +#define ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_SHIFT (0U) +#define ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_SHIFT)) & ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_MASK) +#define ANACTRL_FREQ_ME_CTRL_PROG_MASK (0x80000000U) +#define ANACTRL_FREQ_ME_CTRL_PROG_SHIFT (31U) +#define ANACTRL_FREQ_ME_CTRL_PROG(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FREQ_ME_CTRL_PROG_SHIFT)) & ANACTRL_FREQ_ME_CTRL_PROG_MASK) +/*! @} */ + +/*! @name FRO192M_CTRL - 192MHz Free Running OScillator (FRO) Control register */ +/*! @{ */ +#define ANACTRL_FRO192M_CTRL_BIAS_TRIM_MASK (0x3FU) +#define ANACTRL_FRO192M_CTRL_BIAS_TRIM_SHIFT (0U) +#define ANACTRL_FRO192M_CTRL_BIAS_TRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_BIAS_TRIM_SHIFT)) & ANACTRL_FRO192M_CTRL_BIAS_TRIM_MASK) +#define ANACTRL_FRO192M_CTRL_TEMP_TRIM_MASK (0x3F80U) +#define ANACTRL_FRO192M_CTRL_TEMP_TRIM_SHIFT (7U) +#define ANACTRL_FRO192M_CTRL_TEMP_TRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_TEMP_TRIM_SHIFT)) & ANACTRL_FRO192M_CTRL_TEMP_TRIM_MASK) +#define ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK (0x4000U) +#define ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_SHIFT (14U) +/*! ENA_12MHZCLK - 12 MHz clock control. + * 0b0..12 MHz clock is disabled. + * 0b1..12 MHz clock is enabled. + */ +#define ANACTRL_FRO192M_CTRL_ENA_12MHZCLK(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_SHIFT)) & ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK) +#define ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_MASK (0x8000U) +#define ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_SHIFT (15U) +/*! ENA_48MHZCLK - 48 MHz clock control. + * 0b0..48 MHz clock is disabled. + * 0b1..48 MHz clock is enabled. + */ +#define ANACTRL_FRO192M_CTRL_ENA_48MHZCLK(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_SHIFT)) & ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_MASK) +#define ANACTRL_FRO192M_CTRL_DAC_TRIM_MASK (0xFF0000U) +#define ANACTRL_FRO192M_CTRL_DAC_TRIM_SHIFT (16U) +#define ANACTRL_FRO192M_CTRL_DAC_TRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_DAC_TRIM_SHIFT)) & ANACTRL_FRO192M_CTRL_DAC_TRIM_MASK) +#define ANACTRL_FRO192M_CTRL_USBCLKADJ_MASK (0x1000000U) +#define ANACTRL_FRO192M_CTRL_USBCLKADJ_SHIFT (24U) +#define ANACTRL_FRO192M_CTRL_USBCLKADJ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_USBCLKADJ_SHIFT)) & ANACTRL_FRO192M_CTRL_USBCLKADJ_MASK) +#define ANACTRL_FRO192M_CTRL_USBMODCHG_MASK (0x2000000U) +#define ANACTRL_FRO192M_CTRL_USBMODCHG_SHIFT (25U) +#define ANACTRL_FRO192M_CTRL_USBMODCHG(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_USBMODCHG_SHIFT)) & ANACTRL_FRO192M_CTRL_USBMODCHG_MASK) +#define ANACTRL_FRO192M_CTRL_ATB_CTRL_MASK (0x30000000U) +#define ANACTRL_FRO192M_CTRL_ATB_CTRL_SHIFT (28U) +#define ANACTRL_FRO192M_CTRL_ATB_CTRL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_ATB_CTRL_SHIFT)) & ANACTRL_FRO192M_CTRL_ATB_CTRL_MASK) +#define ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK (0x40000000U) +#define ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_SHIFT (30U) +/*! ENA_96MHZCLK - 96 MHz clock control. + * 0b0..96 MHz clock is disabled. + * 0b1..96 MHz clock is enabled. + */ +#define ANACTRL_FRO192M_CTRL_ENA_96MHZCLK(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_SHIFT)) & ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK) +#define ANACTRL_FRO192M_CTRL_WRTRIM_MASK (0x80000000U) +#define ANACTRL_FRO192M_CTRL_WRTRIM_SHIFT (31U) +#define ANACTRL_FRO192M_CTRL_WRTRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_WRTRIM_SHIFT)) & ANACTRL_FRO192M_CTRL_WRTRIM_MASK) +/*! @} */ + +/*! @name FRO192M_STATUS - 192MHz Free Running OScillator (FRO) Status register */ +/*! @{ */ +#define ANACTRL_FRO192M_STATUS_CLK_VALID_MASK (0x1U) +#define ANACTRL_FRO192M_STATUS_CLK_VALID_SHIFT (0U) +/*! CLK_VALID - Output clock valid signal. Indicates that CCO clock has settled. + * 0b0..No output clock present (None of 12 MHz, 48 MHz or 96 MHz clock is available). + * 0b1..Clock is present (12 MHz, 48 MHz or 96 MHz can be output if they are enable respectively by + * FRO192M_CTRL.ENA_12MHZCLK/ENA_48MHZCLK/ENA_96MHZCLK). + */ +#define ANACTRL_FRO192M_STATUS_CLK_VALID(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_STATUS_CLK_VALID_SHIFT)) & ANACTRL_FRO192M_STATUS_CLK_VALID_MASK) +#define ANACTRL_FRO192M_STATUS_ATB_VCTRL_MASK (0x2U) +#define ANACTRL_FRO192M_STATUS_ATB_VCTRL_SHIFT (1U) +#define ANACTRL_FRO192M_STATUS_ATB_VCTRL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_STATUS_ATB_VCTRL_SHIFT)) & ANACTRL_FRO192M_STATUS_ATB_VCTRL_MASK) +/*! @} */ + +/*! @name ADC_CTRL - General Purpose ADC VBAT Divider branch control */ +/*! @{ */ +#define ANACTRL_ADC_CTRL_VBATDIVENABLE_MASK (0x1U) +#define ANACTRL_ADC_CTRL_VBATDIVENABLE_SHIFT (0U) +/*! VBATDIVENABLE - Switch On/Off VBAT divider branch. + * 0b0..VBAT divider branch is disabled. + * 0b1..VBAT divider branch is enabled. + */ +#define ANACTRL_ADC_CTRL_VBATDIVENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ADC_CTRL_VBATDIVENABLE_SHIFT)) & ANACTRL_ADC_CTRL_VBATDIVENABLE_MASK) +/*! @} */ + +/*! @name XO32M_CTRL - 32 MHz Crystal Oscillator Control register */ +/*! @{ */ +#define ANACTRL_XO32M_CTRL_GM_MASK (0xEU) +#define ANACTRL_XO32M_CTRL_GM_SHIFT (1U) +#define ANACTRL_XO32M_CTRL_GM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_GM_SHIFT)) & ANACTRL_XO32M_CTRL_GM_MASK) +#define ANACTRL_XO32M_CTRL_SLAVE_MASK (0x10U) +#define ANACTRL_XO32M_CTRL_SLAVE_SHIFT (4U) +#define ANACTRL_XO32M_CTRL_SLAVE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_SLAVE_SHIFT)) & ANACTRL_XO32M_CTRL_SLAVE_MASK) +#define ANACTRL_XO32M_CTRL_AMP_MASK (0xE0U) +#define ANACTRL_XO32M_CTRL_AMP_SHIFT (5U) +#define ANACTRL_XO32M_CTRL_AMP(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_AMP_SHIFT)) & ANACTRL_XO32M_CTRL_AMP_MASK) +#define ANACTRL_XO32M_CTRL_OSC_CAP_IN_MASK (0x7F00U) +#define ANACTRL_XO32M_CTRL_OSC_CAP_IN_SHIFT (8U) +#define ANACTRL_XO32M_CTRL_OSC_CAP_IN(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_OSC_CAP_IN_SHIFT)) & ANACTRL_XO32M_CTRL_OSC_CAP_IN_MASK) +#define ANACTRL_XO32M_CTRL_OSC_CAP_OUT_MASK (0x3F8000U) +#define ANACTRL_XO32M_CTRL_OSC_CAP_OUT_SHIFT (15U) +#define ANACTRL_XO32M_CTRL_OSC_CAP_OUT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_OSC_CAP_OUT_SHIFT)) & ANACTRL_XO32M_CTRL_OSC_CAP_OUT_MASK) +#define ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK (0x400000U) +#define ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_SHIFT (22U) +/*! ACBUF_PASS_ENABLE - Bypass enable of XO AC buffer enable in pll and top level. + * 0b0..XO AC buffer bypass is disabled. + * 0b1..XO AC buffer bypass is enabled. + */ +#define ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_SHIFT)) & ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK) +#define ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK (0x800000U) +#define ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_SHIFT (23U) +/*! ENABLE_PLL_USB_OUT - Enable XO 32 MHz output to USB HS PLL. + * 0b0..XO 32 MHz output to USB HS PLL is disabled. + * 0b1..XO 32 MHz output to USB HS PLL is enabled. + */ +#define ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_SHIFT)) & ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK) +#define ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK (0x1000000U) +#define ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_SHIFT (24U) +/*! ENABLE_SYSTEM_CLK_OUT - Enable XO 32 MHz output to CPU system. + * 0b0..XO 32 MHz output to CPU system is disabled. + * 0b1..XO 32 MHz output to CPU system is enabled. + */ +#define ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_SHIFT)) & ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK) +#define ANACTRL_XO32M_CTRL_CAPTESTSTARTSRCSEL_MASK (0x2000000U) +#define ANACTRL_XO32M_CTRL_CAPTESTSTARTSRCSEL_SHIFT (25U) +/*! CAPTESTSTARTSRCSEL - Source selection for 'xo32k_captest_start' signal. + * 0b0..Sourced from CAPTESTSTART. + * 0b1..Sourced from calibration. + */ +#define ANACTRL_XO32M_CTRL_CAPTESTSTARTSRCSEL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_CAPTESTSTARTSRCSEL_SHIFT)) & ANACTRL_XO32M_CTRL_CAPTESTSTARTSRCSEL_MASK) +#define ANACTRL_XO32M_CTRL_CAPTESTSTART_MASK (0x4000000U) +#define ANACTRL_XO32M_CTRL_CAPTESTSTART_SHIFT (26U) +#define ANACTRL_XO32M_CTRL_CAPTESTSTART(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_CAPTESTSTART_SHIFT)) & ANACTRL_XO32M_CTRL_CAPTESTSTART_MASK) +#define ANACTRL_XO32M_CTRL_CAPTESTENABLE_MASK (0x8000000U) +#define ANACTRL_XO32M_CTRL_CAPTESTENABLE_SHIFT (27U) +/*! CAPTESTENABLE - Enable signal for captest. + * 0b0..Captest is disabled. + * 0b1..Captest is enabled. + */ +#define ANACTRL_XO32M_CTRL_CAPTESTENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_CAPTESTENABLE_SHIFT)) & ANACTRL_XO32M_CTRL_CAPTESTENABLE_MASK) +#define ANACTRL_XO32M_CTRL_CAPTESTOSCINSEL_MASK (0x10000000U) +#define ANACTRL_XO32M_CTRL_CAPTESTOSCINSEL_SHIFT (28U) +/*! CAPTESTOSCINSEL - Select the input for test. + * 0b0..osc_out (oscillator output) pin. + * 0b1..osc_in (oscillator) pin. + */ +#define ANACTRL_XO32M_CTRL_CAPTESTOSCINSEL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_CAPTESTOSCINSEL_SHIFT)) & ANACTRL_XO32M_CTRL_CAPTESTOSCINSEL_MASK) +/*! @} */ + +/*! @name XO32M_STATUS - 32 MHz Crystal Oscillator Status register */ +/*! @{ */ +#define ANACTRL_XO32M_STATUS_XO_READY_MASK (0x1U) +#define ANACTRL_XO32M_STATUS_XO_READY_SHIFT (0U) +/*! XO_READY - Indicates XO out frequency statibilty. + * 0b0..XO output frequency is not yet stable. + * 0b1..XO output frequency is stable. + */ +#define ANACTRL_XO32M_STATUS_XO_READY(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_STATUS_XO_READY_SHIFT)) & ANACTRL_XO32M_STATUS_XO_READY_MASK) +/*! @} */ + +/*! @name BOD_DCDC_INT_CTRL - Brown Out Detectors (BoDs) & DCDC interrupts generation control register */ +/*! @{ */ +#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_MASK (0x1U) +#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_SHIFT (0U) +/*! BODVBAT_INT_ENABLE - BOD VBAT interrupt control. + * 0b0..BOD VBAT interrupt is disabled. + * 0b1..BOD VBAT interrupt is enabled. + */ +#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_MASK) +#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_MASK (0x2U) +#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_SHIFT (1U) +#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_MASK) +#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_MASK (0x4U) +#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_SHIFT (2U) +/*! BODCORE_INT_ENABLE - BOD CORE interrupt control. + * 0b0..BOD CORE interrupt is disabled. + * 0b1..BOD CORE interrupt is enabled. + */ +#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_MASK) +#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_MASK (0x8U) +#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_SHIFT (3U) +#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_MASK) +#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_MASK (0x10U) +#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_SHIFT (4U) +/*! DCDC_INT_ENABLE - DCDC interrupt control. + * 0b0..DCDC interrupt is disabled. + * 0b1..DCDC interrupt is enabled. + */ +#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_MASK) +#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_MASK (0x20U) +#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_SHIFT (5U) +#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_MASK) +/*! @} */ + +/*! @name BOD_DCDC_INT_STATUS - BoDs & DCDC interrupts status register */ +/*! @{ */ +#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_MASK (0x1U) +#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_SHIFT (0U) +/*! BODVBAT_STATUS - BOD VBAT Interrupt status before Interrupt Enable. + * 0b0..No interrupt pending.. + * 0b1..Interrupt pending.. + */ +#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_MASK) +#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_MASK (0x2U) +#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_SHIFT (1U) +/*! BODVBAT_INT_STATUS - BOD VBAT Interrupt status after Interrupt Enable. + * 0b0..No interrupt pending.. + * 0b1..Interrupt pending.. + */ +#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_MASK) +#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_MASK (0x4U) +#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_SHIFT (2U) +/*! BODVBAT_VAL - Current value of BOD VBAT power status output. + * 0b0..VBAT voltage level is below the threshold. + * 0b1..VBAT voltage level is above the threshold. + */ +#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_MASK) +#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_MASK (0x8U) +#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_SHIFT (3U) +/*! BODCORE_STATUS - BOD CORE Interrupt status before Interrupt Enable. + * 0b0..No interrupt pending.. + * 0b1..Interrupt pending.. + */ +#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_MASK) +#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_MASK (0x10U) +#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_SHIFT (4U) +/*! BODCORE_INT_STATUS - BOD CORE Interrupt status after Interrupt Enable. + * 0b0..No interrupt pending.. + * 0b1..Interrupt pending.. + */ +#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_MASK) +#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_MASK (0x20U) +#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_SHIFT (5U) +/*! BODCORE_VAL - Current value of BOD CORE power status output. + * 0b0..CORE voltage level is below the threshold. + * 0b1..CORE voltage level is above the threshold. + */ +#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_MASK) +#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_MASK (0x40U) +#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_SHIFT (6U) +/*! DCDC_STATUS - DCDC Interrupt status before Interrupt Enable. + * 0b0..No interrupt pending.. + * 0b1..Interrupt pending.. + */ +#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_MASK) +#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_MASK (0x80U) +#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_SHIFT (7U) +/*! DCDC_INT_STATUS - DCDC Interrupt status after Interrupt Enable. + * 0b0..No interrupt pending.. + * 0b1..Interrupt pending.. + */ +#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_MASK) +#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_MASK (0x100U) +#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_SHIFT (8U) +/*! DCDC_VAL - Current value of DCDC power status output. + * 0b0..DCDC output Voltage is below the targeted regulation level. + * 0b1..DCDC output Voltage is above the targeted regulation level. + */ +#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_MASK) +/*! @} */ + +/*! @name RINGO0_CTRL - First Ring Oscillator module control register. */ +/*! @{ */ +#define ANACTRL_RINGO0_CTRL_SL_MASK (0x1U) +#define ANACTRL_RINGO0_CTRL_SL_SHIFT (0U) +/*! SL - Select short or long ringo (for all ringos types). + * 0b0..Select short ringo (few elements). + * 0b1..Select long ringo (many elements). + */ +#define ANACTRL_RINGO0_CTRL_SL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_SL_SHIFT)) & ANACTRL_RINGO0_CTRL_SL_MASK) +#define ANACTRL_RINGO0_CTRL_FS_MASK (0x2U) +#define ANACTRL_RINGO0_CTRL_FS_SHIFT (1U) +/*! FS - Ringo frequency output divider. + * 0b0..High frequency output (frequency lower than 100 MHz). + * 0b1..Low frequency output (frequency lower than 10 MHz). + */ +#define ANACTRL_RINGO0_CTRL_FS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_FS_SHIFT)) & ANACTRL_RINGO0_CTRL_FS_MASK) +#define ANACTRL_RINGO0_CTRL_SWN_SWP_MASK (0xCU) +#define ANACTRL_RINGO0_CTRL_SWN_SWP_SHIFT (2U) +/*! SWN_SWP - PN-Ringos (P-Transistor and N-Transistor processing) control. + * 0b00..Normal mode. + * 0b01..P-Monitor mode. Measure with weak P transistor. + * 0b10..P-Monitor mode. Measure with weak N transistor. + * 0b11..Don't use. + */ +#define ANACTRL_RINGO0_CTRL_SWN_SWP(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_SWN_SWP_SHIFT)) & ANACTRL_RINGO0_CTRL_SWN_SWP_MASK) +#define ANACTRL_RINGO0_CTRL_PD_MASK (0x10U) +#define ANACTRL_RINGO0_CTRL_PD_SHIFT (4U) +/*! PD - Ringo module Power control. + * 0b0..The Ringo module is enabled. + * 0b1..The Ringo module is disabled. + */ +#define ANACTRL_RINGO0_CTRL_PD(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_PD_SHIFT)) & ANACTRL_RINGO0_CTRL_PD_MASK) +#define ANACTRL_RINGO0_CTRL_E_ND0_MASK (0x20U) +#define ANACTRL_RINGO0_CTRL_E_ND0_SHIFT (5U) +/*! E_ND0 - First NAND2-based ringo control. + * 0b0..First NAND2-based ringo is disabled. + * 0b1..First NAND2-based ringo is enabled. + */ +#define ANACTRL_RINGO0_CTRL_E_ND0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_ND0_SHIFT)) & ANACTRL_RINGO0_CTRL_E_ND0_MASK) +#define ANACTRL_RINGO0_CTRL_E_ND1_MASK (0x40U) +#define ANACTRL_RINGO0_CTRL_E_ND1_SHIFT (6U) +/*! E_ND1 - Second NAND2-based ringo control. + * 0b0..Second NAND2-based ringo is disabled. + * 0b1..Second NAND2-based ringo is enabled. + */ +#define ANACTRL_RINGO0_CTRL_E_ND1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_ND1_SHIFT)) & ANACTRL_RINGO0_CTRL_E_ND1_MASK) +#define ANACTRL_RINGO0_CTRL_E_NR0_MASK (0x80U) +#define ANACTRL_RINGO0_CTRL_E_NR0_SHIFT (7U) +/*! E_NR0 - First NOR2-based ringo control. + * 0b0..First NOR2-based ringo is disabled. + * 0b1..First NOR2-based ringo is enabled. + */ +#define ANACTRL_RINGO0_CTRL_E_NR0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_NR0_SHIFT)) & ANACTRL_RINGO0_CTRL_E_NR0_MASK) +#define ANACTRL_RINGO0_CTRL_E_NR1_MASK (0x100U) +#define ANACTRL_RINGO0_CTRL_E_NR1_SHIFT (8U) +/*! E_NR1 - Second NOR2-based ringo control. + * 0b0..Second NORD2-based ringo is disabled. + * 0b1..Second NORD2-based ringo is enabled. + */ +#define ANACTRL_RINGO0_CTRL_E_NR1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_NR1_SHIFT)) & ANACTRL_RINGO0_CTRL_E_NR1_MASK) +#define ANACTRL_RINGO0_CTRL_E_IV0_MASK (0x200U) +#define ANACTRL_RINGO0_CTRL_E_IV0_SHIFT (9U) +/*! E_IV0 - First Inverter-based ringo control. + * 0b0..First INV-based ringo is disabled. + * 0b1..First INV-based ringo is enabled. + */ +#define ANACTRL_RINGO0_CTRL_E_IV0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_IV0_SHIFT)) & ANACTRL_RINGO0_CTRL_E_IV0_MASK) +#define ANACTRL_RINGO0_CTRL_E_IV1_MASK (0x400U) +#define ANACTRL_RINGO0_CTRL_E_IV1_SHIFT (10U) +/*! E_IV1 - Second Inverter-based ringo control. + * 0b0..Second INV-based ringo is disabled. + * 0b1..Second INV-based ringo is enabled. + */ +#define ANACTRL_RINGO0_CTRL_E_IV1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_IV1_SHIFT)) & ANACTRL_RINGO0_CTRL_E_IV1_MASK) +#define ANACTRL_RINGO0_CTRL_E_PN0_MASK (0x800U) +#define ANACTRL_RINGO0_CTRL_E_PN0_SHIFT (11U) +/*! E_PN0 - First PN (P-Transistor and N-Transistor processing) monitor control. + * 0b0..First PN-based ringo is disabled. + * 0b1..First PN-based ringo is enabled. + */ +#define ANACTRL_RINGO0_CTRL_E_PN0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_PN0_SHIFT)) & ANACTRL_RINGO0_CTRL_E_PN0_MASK) +#define ANACTRL_RINGO0_CTRL_E_PN1_MASK (0x1000U) +#define ANACTRL_RINGO0_CTRL_E_PN1_SHIFT (12U) +/*! E_PN1 - Second PN (P-Transistor and N-Transistor processing) monitor control. + * 0b0..Second PN-based ringo is disabled. + * 0b1..Second PN-based ringo is enabled. + */ +#define ANACTRL_RINGO0_CTRL_E_PN1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_PN1_SHIFT)) & ANACTRL_RINGO0_CTRL_E_PN1_MASK) +#define ANACTRL_RINGO0_CTRL_DIVISOR_MASK (0xF0000U) +#define ANACTRL_RINGO0_CTRL_DIVISOR_SHIFT (16U) +#define ANACTRL_RINGO0_CTRL_DIVISOR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_DIVISOR_SHIFT)) & ANACTRL_RINGO0_CTRL_DIVISOR_MASK) +#define ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_MASK (0x80000000U) +#define ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_SHIFT (31U) +#define ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_SHIFT)) & ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_MASK) +/*! @} */ + +/*! @name RINGO1_CTRL - Second Ring Oscillator module control register. */ +/*! @{ */ +#define ANACTRL_RINGO1_CTRL_S_MASK (0x1U) +#define ANACTRL_RINGO1_CTRL_S_SHIFT (0U) +/*! S - Select short or long ringo (for all ringos types). + * 0b0..Select short ringo (few elements). + * 0b1..Select long ringo (many elements). + */ +#define ANACTRL_RINGO1_CTRL_S(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_S_SHIFT)) & ANACTRL_RINGO1_CTRL_S_MASK) +#define ANACTRL_RINGO1_CTRL_FS_MASK (0x2U) +#define ANACTRL_RINGO1_CTRL_FS_SHIFT (1U) +/*! FS - Ringo frequency output divider. + * 0b0..High frequency output (frequency lower than 100 MHz). + * 0b1..Low frequency output (frequency lower than 10 MHz). + */ +#define ANACTRL_RINGO1_CTRL_FS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_FS_SHIFT)) & ANACTRL_RINGO1_CTRL_FS_MASK) +#define ANACTRL_RINGO1_CTRL_PD_MASK (0x4U) +#define ANACTRL_RINGO1_CTRL_PD_SHIFT (2U) +/*! PD - Ringo module Power control. + * 0b0..The Ringo module is enabled. + * 0b1..The Ringo module is disabled. + */ +#define ANACTRL_RINGO1_CTRL_PD(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_PD_SHIFT)) & ANACTRL_RINGO1_CTRL_PD_MASK) +#define ANACTRL_RINGO1_CTRL_E_R24_MASK (0x8U) +#define ANACTRL_RINGO1_CTRL_E_R24_SHIFT (3U) +/*! E_R24 - . + * 0b0..Ringo is disabled. + * 0b1..Ringo is enabled. + */ +#define ANACTRL_RINGO1_CTRL_E_R24(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_R24_SHIFT)) & ANACTRL_RINGO1_CTRL_E_R24_MASK) +#define ANACTRL_RINGO1_CTRL_E_R35_MASK (0x10U) +#define ANACTRL_RINGO1_CTRL_E_R35_SHIFT (4U) +/*! E_R35 - . + * 0b0..Ringo is disabled. + * 0b1..Ringo is enabled. + */ +#define ANACTRL_RINGO1_CTRL_E_R35(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_R35_SHIFT)) & ANACTRL_RINGO1_CTRL_E_R35_MASK) +#define ANACTRL_RINGO1_CTRL_E_M2_MASK (0x20U) +#define ANACTRL_RINGO1_CTRL_E_M2_SHIFT (5U) +/*! E_M2 - Metal 2 (M2) monitor control. + * 0b0..Ringo is disabled. + * 0b1..Ringo is enabled. + */ +#define ANACTRL_RINGO1_CTRL_E_M2(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_M2_SHIFT)) & ANACTRL_RINGO1_CTRL_E_M2_MASK) +#define ANACTRL_RINGO1_CTRL_E_M3_MASK (0x40U) +#define ANACTRL_RINGO1_CTRL_E_M3_SHIFT (6U) +/*! E_M3 - Metal 3 (M3) monitor control. + * 0b0..Ringo is disabled. + * 0b1..Ringo is enabled. + */ +#define ANACTRL_RINGO1_CTRL_E_M3(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_M3_SHIFT)) & ANACTRL_RINGO1_CTRL_E_M3_MASK) +#define ANACTRL_RINGO1_CTRL_E_M4_MASK (0x80U) +#define ANACTRL_RINGO1_CTRL_E_M4_SHIFT (7U) +/*! E_M4 - Metal 4 (M4) monitor control. + * 0b0..Ringo is disabled. + * 0b1..Ringo is enabled. + */ +#define ANACTRL_RINGO1_CTRL_E_M4(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_M4_SHIFT)) & ANACTRL_RINGO1_CTRL_E_M4_MASK) +#define ANACTRL_RINGO1_CTRL_E_M5_MASK (0x100U) +#define ANACTRL_RINGO1_CTRL_E_M5_SHIFT (8U) +/*! E_M5 - Metal 5 (M5) monitor control. + * 0b0..Ringo is disabled. + * 0b1..Ringo is enabled. + */ +#define ANACTRL_RINGO1_CTRL_E_M5(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_M5_SHIFT)) & ANACTRL_RINGO1_CTRL_E_M5_MASK) +#define ANACTRL_RINGO1_CTRL_DIVISOR_MASK (0xF0000U) +#define ANACTRL_RINGO1_CTRL_DIVISOR_SHIFT (16U) +#define ANACTRL_RINGO1_CTRL_DIVISOR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_DIVISOR_SHIFT)) & ANACTRL_RINGO1_CTRL_DIVISOR_MASK) +#define ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_MASK (0x80000000U) +#define ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_SHIFT (31U) +#define ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_SHIFT)) & ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_MASK) +/*! @} */ + +/*! @name RINGO2_CTRL - Third Ring Oscillator module control register. */ +/*! @{ */ +#define ANACTRL_RINGO2_CTRL_S_MASK (0x1U) +#define ANACTRL_RINGO2_CTRL_S_SHIFT (0U) +/*! S - Select short or long ringo (for all ringos types). + * 0b0..Select short ringo (few elements). + * 0b1..Select long ringo (many elements). + */ +#define ANACTRL_RINGO2_CTRL_S(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_S_SHIFT)) & ANACTRL_RINGO2_CTRL_S_MASK) +#define ANACTRL_RINGO2_CTRL_FS_MASK (0x2U) +#define ANACTRL_RINGO2_CTRL_FS_SHIFT (1U) +/*! FS - Ringo frequency output divider. + * 0b0..High frequency output (frequency lower than 100 MHz). + * 0b1..Low frequency output (frequency lower than 10 MHz). + */ +#define ANACTRL_RINGO2_CTRL_FS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_FS_SHIFT)) & ANACTRL_RINGO2_CTRL_FS_MASK) +#define ANACTRL_RINGO2_CTRL_PD_MASK (0x4U) +#define ANACTRL_RINGO2_CTRL_PD_SHIFT (2U) +/*! PD - Ringo module Power control. + * 0b0..The Ringo module is enabled. + * 0b1..The Ringo module is disabled. + */ +#define ANACTRL_RINGO2_CTRL_PD(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_PD_SHIFT)) & ANACTRL_RINGO2_CTRL_PD_MASK) +#define ANACTRL_RINGO2_CTRL_E_R24_MASK (0x8U) +#define ANACTRL_RINGO2_CTRL_E_R24_SHIFT (3U) +/*! E_R24 - . + * 0b0..Ringo is disabled. + * 0b1..Ringo is enabled. + */ +#define ANACTRL_RINGO2_CTRL_E_R24(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_R24_SHIFT)) & ANACTRL_RINGO2_CTRL_E_R24_MASK) +#define ANACTRL_RINGO2_CTRL_E_R35_MASK (0x10U) +#define ANACTRL_RINGO2_CTRL_E_R35_SHIFT (4U) +/*! E_R35 - . + * 0b0..Ringo is disabled. + * 0b1..Ringo is enabled. + */ +#define ANACTRL_RINGO2_CTRL_E_R35(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_R35_SHIFT)) & ANACTRL_RINGO2_CTRL_E_R35_MASK) +#define ANACTRL_RINGO2_CTRL_E_M2_MASK (0x20U) +#define ANACTRL_RINGO2_CTRL_E_M2_SHIFT (5U) +/*! E_M2 - Metal 2 (M2) monitor control. + * 0b0..Ringo is disabled. + * 0b1..Ringo is enabled. + */ +#define ANACTRL_RINGO2_CTRL_E_M2(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_M2_SHIFT)) & ANACTRL_RINGO2_CTRL_E_M2_MASK) +#define ANACTRL_RINGO2_CTRL_E_M3_MASK (0x40U) +#define ANACTRL_RINGO2_CTRL_E_M3_SHIFT (6U) +/*! E_M3 - Metal 3 (M3) monitor control. + * 0b0..Ringo is disabled. + * 0b1..Ringo is enabled. + */ +#define ANACTRL_RINGO2_CTRL_E_M3(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_M3_SHIFT)) & ANACTRL_RINGO2_CTRL_E_M3_MASK) +#define ANACTRL_RINGO2_CTRL_E_M4_MASK (0x80U) +#define ANACTRL_RINGO2_CTRL_E_M4_SHIFT (7U) +/*! E_M4 - Metal 4 (M4) monitor control. + * 0b0..Ringo is disabled. + * 0b1..Ringo is enabled. + */ +#define ANACTRL_RINGO2_CTRL_E_M4(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_M4_SHIFT)) & ANACTRL_RINGO2_CTRL_E_M4_MASK) +#define ANACTRL_RINGO2_CTRL_E_M5_MASK (0x100U) +#define ANACTRL_RINGO2_CTRL_E_M5_SHIFT (8U) +/*! E_M5 - Metal 5 (M5) monitor control. + * 0b0..Ringo is disabled. + * 0b1..Ringo is enabled. + */ +#define ANACTRL_RINGO2_CTRL_E_M5(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_M5_SHIFT)) & ANACTRL_RINGO2_CTRL_E_M5_MASK) +#define ANACTRL_RINGO2_CTRL_DIVISOR_MASK (0xF0000U) +#define ANACTRL_RINGO2_CTRL_DIVISOR_SHIFT (16U) +#define ANACTRL_RINGO2_CTRL_DIVISOR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_DIVISOR_SHIFT)) & ANACTRL_RINGO2_CTRL_DIVISOR_MASK) +#define ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ_MASK (0x80000000U) +#define ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ_SHIFT (31U) +#define ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ_SHIFT)) & ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ_MASK) +/*! @} */ + +/*! @name LDO_XO32M - High Speed Crystal Oscillator (12 MHz - 32 MHz) Voltage Source Supply Control register */ +/*! @{ */ +#define ANACTRL_LDO_XO32M_BYPASS_MASK (0x2U) +#define ANACTRL_LDO_XO32M_BYPASS_SHIFT (1U) +/*! BYPASS - Activate LDO bypass. + * 0b0..Disable bypass mode (for normal operations). + * 0b1..Activate LDO bypass. + */ +#define ANACTRL_LDO_XO32M_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_BYPASS_SHIFT)) & ANACTRL_LDO_XO32M_BYPASS_MASK) +#define ANACTRL_LDO_XO32M_HIGHZ_MASK (0x4U) +#define ANACTRL_LDO_XO32M_HIGHZ_SHIFT (2U) +/*! HIGHZ - . + * 0b0..Output in High normal state. + * 0b1..Output in High Impedance state. + */ +#define ANACTRL_LDO_XO32M_HIGHZ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_HIGHZ_SHIFT)) & ANACTRL_LDO_XO32M_HIGHZ_MASK) +#define ANACTRL_LDO_XO32M_VOUT_MASK (0x38U) +#define ANACTRL_LDO_XO32M_VOUT_SHIFT (3U) +/*! VOUT - Sets the LDO output level. + * 0b000..0.750 V. + * 0b001..0.775 V. + * 0b010..0.800 V. + * 0b011..0.825 V. + * 0b100..0.850 V. + * 0b101..0.875 V. + * 0b110..0.900 V. + * 0b111..0.925 V. + */ +#define ANACTRL_LDO_XO32M_VOUT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_VOUT_SHIFT)) & ANACTRL_LDO_XO32M_VOUT_MASK) +#define ANACTRL_LDO_XO32M_IBIAS_MASK (0xC0U) +#define ANACTRL_LDO_XO32M_IBIAS_SHIFT (6U) +#define ANACTRL_LDO_XO32M_IBIAS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_IBIAS_SHIFT)) & ANACTRL_LDO_XO32M_IBIAS_MASK) +#define ANACTRL_LDO_XO32M_STABMODE_MASK (0x300U) +#define ANACTRL_LDO_XO32M_STABMODE_SHIFT (8U) +#define ANACTRL_LDO_XO32M_STABMODE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_STABMODE_SHIFT)) & ANACTRL_LDO_XO32M_STABMODE_MASK) +/*! @} */ + +/*! @name XO_CAL_CFG - All Crystal Oscillators (both the 32 KHz and the High speed) Capacitive Banks Calibration Configuration register */ +/*! @{ */ +#define ANACTRL_XO_CAL_CFG_START_INV_MASK (0x1U) +#define ANACTRL_XO_CAL_CFG_START_INV_SHIFT (0U) +#define ANACTRL_XO_CAL_CFG_START_INV(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO_CAL_CFG_START_INV_SHIFT)) & ANACTRL_XO_CAL_CFG_START_INV_MASK) +#define ANACTRL_XO_CAL_CFG_START_OVR_MASK (0x2U) +#define ANACTRL_XO_CAL_CFG_START_OVR_SHIFT (1U) +#define ANACTRL_XO_CAL_CFG_START_OVR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO_CAL_CFG_START_OVR_SHIFT)) & ANACTRL_XO_CAL_CFG_START_OVR_MASK) +#define ANACTRL_XO_CAL_CFG_START_MASK (0x4U) +#define ANACTRL_XO_CAL_CFG_START_SHIFT (2U) +#define ANACTRL_XO_CAL_CFG_START(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO_CAL_CFG_START_SHIFT)) & ANACTRL_XO_CAL_CFG_START_MASK) +#define ANACTRL_XO_CAL_CFG_STOP_INV_MASK (0x8U) +#define ANACTRL_XO_CAL_CFG_STOP_INV_SHIFT (3U) +#define ANACTRL_XO_CAL_CFG_STOP_INV(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO_CAL_CFG_STOP_INV_SHIFT)) & ANACTRL_XO_CAL_CFG_STOP_INV_MASK) +#define ANACTRL_XO_CAL_CFG_STOP_CNTR_END_MASK (0x10U) +#define ANACTRL_XO_CAL_CFG_STOP_CNTR_END_SHIFT (4U) +#define ANACTRL_XO_CAL_CFG_STOP_CNTR_END(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO_CAL_CFG_STOP_CNTR_END_SHIFT)) & ANACTRL_XO_CAL_CFG_STOP_CNTR_END_MASK) +#define ANACTRL_XO_CAL_CFG_XO32K_MODE_MASK (0x20U) +#define ANACTRL_XO_CAL_CFG_XO32K_MODE_SHIFT (5U) +/*! XO32K_MODE - When 0 : High speed crystal oscillator calibration is used. When 1 : 32 kHz crystal oscillator calibration is used. + * 0b0..High speed crystal oscillator (12 MHz- 32 MHz) is used + * 0b1..32 kHz crystal oscillator calibration is used. + */ +#define ANACTRL_XO_CAL_CFG_XO32K_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO_CAL_CFG_XO32K_MODE_SHIFT)) & ANACTRL_XO_CAL_CFG_XO32K_MODE_MASK) +/*! @} */ + +/*! @name XO_CAL_CMD - All Crystal Oscillators (both the 32 KHz and the High Speed) Capacitive Banks Calibration Command register. */ +/*! @{ */ +#define ANACTRL_XO_CAL_CMD_START_MASK (0x1U) +#define ANACTRL_XO_CAL_CMD_START_SHIFT (0U) +#define ANACTRL_XO_CAL_CMD_START(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO_CAL_CMD_START_SHIFT)) & ANACTRL_XO_CAL_CMD_START_MASK) +#define ANACTRL_XO_CAL_CMD_STOP_MASK (0x2U) +#define ANACTRL_XO_CAL_CMD_STOP_SHIFT (1U) +#define ANACTRL_XO_CAL_CMD_STOP(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO_CAL_CMD_STOP_SHIFT)) & ANACTRL_XO_CAL_CMD_STOP_MASK) +#define ANACTRL_XO_CAL_CMD_OVR_MASK (0x4U) +#define ANACTRL_XO_CAL_CMD_OVR_SHIFT (2U) +#define ANACTRL_XO_CAL_CMD_OVR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO_CAL_CMD_OVR_SHIFT)) & ANACTRL_XO_CAL_CMD_OVR_MASK) +/*! @} */ + +/*! @name XO_CAL_STATUS - All Crystal Oscillators (both the 32 KHz and the High speed) Capacitive Banks Calibration Status register. */ +/*! @{ */ +#define ANACTRL_XO_CAL_STATUS_CAL_CNTR_MASK (0xFFFFU) +#define ANACTRL_XO_CAL_STATUS_CAL_CNTR_SHIFT (0U) +#define ANACTRL_XO_CAL_STATUS_CAL_CNTR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO_CAL_STATUS_CAL_CNTR_SHIFT)) & ANACTRL_XO_CAL_STATUS_CAL_CNTR_MASK) +#define ANACTRL_XO_CAL_STATUS_DONE_MASK (0x10000U) +#define ANACTRL_XO_CAL_STATUS_DONE_SHIFT (16U) +#define ANACTRL_XO_CAL_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO_CAL_STATUS_DONE_SHIFT)) & ANACTRL_XO_CAL_STATUS_DONE_MASK) +/*! @} */ + +/*! @name USBHS_PHY_CTRL - USB High Speed Phy Control */ +/*! @{ */ +#define ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext_MASK (0x1U) +#define ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext_SHIFT (0U) +#define ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext_SHIFT)) & ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext_MASK) +#define ANACTRL_USBHS_PHY_CTRL_usb_id_ext_MASK (0x2U) +#define ANACTRL_USBHS_PHY_CTRL_usb_id_ext_SHIFT (1U) +#define ANACTRL_USBHS_PHY_CTRL_usb_id_ext(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_CTRL_usb_id_ext_SHIFT)) & ANACTRL_USBHS_PHY_CTRL_usb_id_ext_MASK) +#define ANACTRL_USBHS_PHY_CTRL_iso_atx_MASK (0x8U) +#define ANACTRL_USBHS_PHY_CTRL_iso_atx_SHIFT (3U) +#define ANACTRL_USBHS_PHY_CTRL_iso_atx(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_CTRL_iso_atx_SHIFT)) & ANACTRL_USBHS_PHY_CTRL_iso_atx_MASK) +/*! @} */ + +/*! @name USBHS_PHY_TRIM - USB High Speed Phy Trim values */ +/*! @{ */ +#define ANACTRL_USBHS_PHY_TRIM_trim_usb_reg_env_tail_adj_vd_MASK (0x3U) +#define ANACTRL_USBHS_PHY_TRIM_trim_usb_reg_env_tail_adj_vd_SHIFT (0U) +#define ANACTRL_USBHS_PHY_TRIM_trim_usb_reg_env_tail_adj_vd(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usb_reg_env_tail_adj_vd_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usb_reg_env_tail_adj_vd_MASK) +#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_d_cal_MASK (0x3CU) +#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_d_cal_SHIFT (2U) +#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_d_cal(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_d_cal_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_d_cal_MASK) +#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dp_MASK (0x7C0U) +#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dp_SHIFT (6U) +#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dp(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dp_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dp_MASK) +#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dm_MASK (0xF800U) +#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dm_SHIFT (11U) +#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dm(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dm_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dm_MASK) +#define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_tst_MASK (0x30000U) +#define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_tst_SHIFT (16U) +#define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_tst(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_tst_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_tst_MASK) +#define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_vbgadj_MASK (0x1C0000U) +#define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_vbgadj_SHIFT (18U) +#define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_vbgadj(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_vbgadj_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_vbgadj_MASK) +#define ANACTRL_USBHS_PHY_TRIM_trim_pll_ctrl0_div_sel_MASK (0xE00000U) +#define ANACTRL_USBHS_PHY_TRIM_trim_pll_ctrl0_div_sel_SHIFT (21U) +#define ANACTRL_USBHS_PHY_TRIM_trim_pll_ctrl0_div_sel(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_pll_ctrl0_div_sel_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_pll_ctrl0_div_sel_MASK) +/*! @} */ + +/*! @name USBHS_PHY_STATUS - USB High Speed Phy Status */ +/*! @{ */ +#define ANACTRL_USBHS_PHY_STATUS_pfd_stable_MASK (0x1U) +#define ANACTRL_USBHS_PHY_STATUS_pfd_stable_SHIFT (0U) +#define ANACTRL_USBHS_PHY_STATUS_pfd_stable(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_STATUS_pfd_stable_SHIFT)) & ANACTRL_USBHS_PHY_STATUS_pfd_stable_MASK) +#define ANACTRL_USBHS_PHY_STATUS_vbusvalid_3vdetect_1p8v_MASK (0x2U) +#define ANACTRL_USBHS_PHY_STATUS_vbusvalid_3vdetect_1p8v_SHIFT (1U) +#define ANACTRL_USBHS_PHY_STATUS_vbusvalid_3vdetect_1p8v(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_STATUS_vbusvalid_3vdetect_1p8v_SHIFT)) & ANACTRL_USBHS_PHY_STATUS_vbusvalid_3vdetect_1p8v_MASK) +#define ANACTRL_USBHS_PHY_STATUS_sess_vld_1p8v_MASK (0x4U) +#define ANACTRL_USBHS_PHY_STATUS_sess_vld_1p8v_SHIFT (2U) +#define ANACTRL_USBHS_PHY_STATUS_sess_vld_1p8v(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_STATUS_sess_vld_1p8v_SHIFT)) & ANACTRL_USBHS_PHY_STATUS_sess_vld_1p8v_MASK) +#define ANACTRL_USBHS_PHY_STATUS_usb2_rx_vpin_fs_1p8v_MASK (0x8U) +#define ANACTRL_USBHS_PHY_STATUS_usb2_rx_vpin_fs_1p8v_SHIFT (3U) +#define ANACTRL_USBHS_PHY_STATUS_usb2_rx_vpin_fs_1p8v(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_STATUS_usb2_rx_vpin_fs_1p8v_SHIFT)) & ANACTRL_USBHS_PHY_STATUS_usb2_rx_vpin_fs_1p8v_MASK) +#define ANACTRL_USBHS_PHY_STATUS_usb2_rx_vmin_fs_1p8v_MASK (0x10U) +#define ANACTRL_USBHS_PHY_STATUS_usb2_rx_vmin_fs_1p8v_SHIFT (4U) +#define ANACTRL_USBHS_PHY_STATUS_usb2_rx_vmin_fs_1p8v(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_STATUS_usb2_rx_vmin_fs_1p8v_SHIFT)) & ANACTRL_USBHS_PHY_STATUS_usb2_rx_vmin_fs_1p8v_MASK) +#define ANACTRL_USBHS_PHY_STATUS_usb2_plugged_in_1p8v_MASK (0x20U) +#define ANACTRL_USBHS_PHY_STATUS_usb2_plugged_in_1p8v_SHIFT (5U) +#define ANACTRL_USBHS_PHY_STATUS_usb2_plugged_in_1p8v(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_STATUS_usb2_plugged_in_1p8v_SHIFT)) & ANACTRL_USBHS_PHY_STATUS_usb2_plugged_in_1p8v_MASK) +#define ANACTRL_USBHS_PHY_STATUS_usb2_iddig_1p8v_MASK (0x40U) +#define ANACTRL_USBHS_PHY_STATUS_usb2_iddig_1p8v_SHIFT (6U) +#define ANACTRL_USBHS_PHY_STATUS_usb2_iddig_1p8v(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_STATUS_usb2_iddig_1p8v_SHIFT)) & ANACTRL_USBHS_PHY_STATUS_usb2_iddig_1p8v_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group ANACTRL_Register_Masks */ + + +/* ANACTRL - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral ANACTRL base address */ + #define ANACTRL_BASE (0x50013000u) + /** Peripheral ANACTRL base address */ + #define ANACTRL_BASE_NS (0x40013000u) + /** Peripheral ANACTRL base pointer */ + #define ANACTRL ((ANACTRL_Type *)ANACTRL_BASE) + /** Peripheral ANACTRL base pointer */ + #define ANACTRL_NS ((ANACTRL_Type *)ANACTRL_BASE_NS) + /** Array initializer of ANACTRL peripheral base addresses */ + #define ANACTRL_BASE_ADDRS { ANACTRL_BASE } + /** Array initializer of ANACTRL peripheral base pointers */ + #define ANACTRL_BASE_PTRS { ANACTRL } + /** Array initializer of ANACTRL peripheral base addresses */ + #define ANACTRL_BASE_ADDRS_NS { ANACTRL_BASE_NS } + /** Array initializer of ANACTRL peripheral base pointers */ + #define ANACTRL_BASE_PTRS_NS { ANACTRL_NS } +#else + /** Peripheral ANACTRL base address */ + #define ANACTRL_BASE (0x40013000u) + /** Peripheral ANACTRL base pointer */ + #define ANACTRL ((ANACTRL_Type *)ANACTRL_BASE) + /** Array initializer of ANACTRL peripheral base addresses */ + #define ANACTRL_BASE_ADDRS { ANACTRL_BASE } + /** Array initializer of ANACTRL peripheral base pointers */ + #define ANACTRL_BASE_PTRS { ANACTRL } +#endif + +/*! + * @} + */ /* end of group ANACTRL_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CASPER Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CASPER_Peripheral_Access_Layer CASPER Peripheral Access Layer + * @{ + */ + +/** CASPER - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL0; /**< Contains the offsets of AB and CD in the RAM., offset: 0x0 */ + __IO uint32_t CTRL1; /**< Contains the opcode mode, iteration count, and result offset (in RAM) and also launches the accelerator. Note: with CP version: CTRL0 and CRTL1 can be written in one go with MCRR., offset: 0x4 */ + __IO uint32_t LOADER; /**< Contains an optional loader to load into CTRL0/1 in steps to perform a set of operations., offset: 0x8 */ + __IO uint32_t STATUS; /**< Indicates operational status and would contain the carry bit if used., offset: 0xC */ + __IO uint32_t INTENSET; /**< Sets interrupts, offset: 0x10 */ + __IO uint32_t INTENCLR; /**< Clears interrupts, offset: 0x14 */ + __I uint32_t INTSTAT; /**< Interrupt status bits (mask of INTENSET and STATUS), offset: 0x18 */ + uint8_t RESERVED_0[4]; + __IO uint32_t AREG; /**< A register, offset: 0x20 */ + __IO uint32_t BREG; /**< B register, offset: 0x24 */ + __IO uint32_t CREG; /**< C register, offset: 0x28 */ + __IO uint32_t DREG; /**< D register, offset: 0x2C */ + __IO uint32_t RES0; /**< Result register 0, offset: 0x30 */ + __IO uint32_t RES1; /**< Result register 1, offset: 0x34 */ + __IO uint32_t RES2; /**< Result register 2, offset: 0x38 */ + __IO uint32_t RES3; /**< Result register 3, offset: 0x3C */ + uint8_t RESERVED_1[32]; + __IO uint32_t MASK; /**< Optional mask register, offset: 0x60 */ + __IO uint32_t REMASK; /**< Optional re-mask register, offset: 0x64 */ + uint8_t RESERVED_2[24]; + __IO uint32_t LOCK; /**< Security lock register, offset: 0x80 */ +} CASPER_Type; + +/* ---------------------------------------------------------------------------- + -- CASPER Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CASPER_Register_Masks CASPER Register Masks + * @{ + */ + +/*! @name CTRL0 - Contains the offsets of AB and CD in the RAM. */ +/*! @{ */ +#define CASPER_CTRL0_ABBPAIR_MASK (0x1U) +#define CASPER_CTRL0_ABBPAIR_SHIFT (0U) +/*! ABBPAIR - Which bank-pair the offset ABOFF is within. This must be 0 if only 2-up + * 0b0..Bank-pair 0 (1st) + * 0b1..Bank-pair 1 (2nd) + */ +#define CASPER_CTRL0_ABBPAIR(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_ABBPAIR_SHIFT)) & CASPER_CTRL0_ABBPAIR_MASK) +#define CASPER_CTRL0_ABOFF_MASK (0x4U) +#define CASPER_CTRL0_ABOFF_SHIFT (2U) +#define CASPER_CTRL0_ABOFF(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_ABOFF_SHIFT)) & CASPER_CTRL0_ABOFF_MASK) +#define CASPER_CTRL0_CDBPAIR_MASK (0x10000U) +#define CASPER_CTRL0_CDBPAIR_SHIFT (16U) +/*! CDBPAIR - Which bank-pair the offset CDOFF is within. This must be 0 if only 2-up + * 0b0..Bank-pair 0 (1st) + * 0b1..Bank-pair 1 (2nd) + */ +#define CASPER_CTRL0_CDBPAIR(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_CDBPAIR_SHIFT)) & CASPER_CTRL0_CDBPAIR_MASK) +#define CASPER_CTRL0_CDOFF_MASK (0x1FFC0000U) +#define CASPER_CTRL0_CDOFF_SHIFT (18U) +#define CASPER_CTRL0_CDOFF(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_CDOFF_SHIFT)) & CASPER_CTRL0_CDOFF_MASK) +/*! @} */ + +/*! @name CTRL1 - Contains the opcode mode, iteration count, and result offset (in RAM) and also launches the accelerator. Note: with CP version: CTRL0 and CRTL1 can be written in one go with MCRR. */ +/*! @{ */ +#define CASPER_CTRL1_ITER_MASK (0xFFU) +#define CASPER_CTRL1_ITER_SHIFT (0U) +#define CASPER_CTRL1_ITER(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_ITER_SHIFT)) & CASPER_CTRL1_ITER_MASK) +#define CASPER_CTRL1_MODE_MASK (0xFF00U) +#define CASPER_CTRL1_MODE_SHIFT (8U) +#define CASPER_CTRL1_MODE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_MODE_SHIFT)) & CASPER_CTRL1_MODE_MASK) +#define CASPER_CTRL1_RESBPAIR_MASK (0x10000U) +#define CASPER_CTRL1_RESBPAIR_SHIFT (16U) +/*! RESBPAIR - Which bank-pair the offset RESOFF is within. This must be 0 if only 2-up. Ideally + * this is not the same bank as ABBPAIR (when 4-up supported) + * 0b0..Bank-pair 0 (1st) + * 0b1..Bank-pair 1 (2nd) + */ +#define CASPER_CTRL1_RESBPAIR(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_RESBPAIR_SHIFT)) & CASPER_CTRL1_RESBPAIR_MASK) +#define CASPER_CTRL1_RESOFF_MASK (0x1FFC0000U) +#define CASPER_CTRL1_RESOFF_SHIFT (18U) +#define CASPER_CTRL1_RESOFF(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_RESOFF_SHIFT)) & CASPER_CTRL1_RESOFF_MASK) +#define CASPER_CTRL1_CSKIP_MASK (0xC0000000U) +#define CASPER_CTRL1_CSKIP_SHIFT (30U) +/*! CSKIP - Skip rules on Carry if needed. This operation will be skipped based on Carry value (from previous operation) if not 0: + * 0b00..No Skip + * 0b01..Skip if Carry is 1 + * 0b10..Skip if Carry is 0 + * 0b11..Set CTRLOFF to CDOFF and Skip + */ +#define CASPER_CTRL1_CSKIP(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_CSKIP_SHIFT)) & CASPER_CTRL1_CSKIP_MASK) +/*! @} */ + +/*! @name LOADER - Contains an optional loader to load into CTRL0/1 in steps to perform a set of operations. */ +/*! @{ */ +#define CASPER_LOADER_COUNT_MASK (0xFFU) +#define CASPER_LOADER_COUNT_SHIFT (0U) +#define CASPER_LOADER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOADER_COUNT_SHIFT)) & CASPER_LOADER_COUNT_MASK) +#define CASPER_LOADER_CTRLBPAIR_MASK (0x10000U) +#define CASPER_LOADER_CTRLBPAIR_SHIFT (16U) +/*! CTRLBPAIR - Which bank-pair the offset CTRLOFF is within. This must be 0 if only 2-up. Does not + * matter which bank is used as this is loaded when not performing an operation. + * 0b0..Bank-pair 0 (1st) + * 0b1..Bank-pair 1 (2nd) + */ +#define CASPER_LOADER_CTRLBPAIR(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOADER_CTRLBPAIR_SHIFT)) & CASPER_LOADER_CTRLBPAIR_MASK) +#define CASPER_LOADER_CTRLOFF_MASK (0x1FFC0000U) +#define CASPER_LOADER_CTRLOFF_SHIFT (18U) +#define CASPER_LOADER_CTRLOFF(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOADER_CTRLOFF_SHIFT)) & CASPER_LOADER_CTRLOFF_MASK) +/*! @} */ + +/*! @name STATUS - Indicates operational status and would contain the carry bit if used. */ +/*! @{ */ +#define CASPER_STATUS_DONE_MASK (0x1U) +#define CASPER_STATUS_DONE_SHIFT (0U) +/*! DONE - Indicates if the accelerator has finished an operation. Write 1 to clear, or write CTRL1 to clear. + * 0b0..Busy or just cleared + * 0b1..Completed last operation + */ +#define CASPER_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_STATUS_DONE_SHIFT)) & CASPER_STATUS_DONE_MASK) +#define CASPER_STATUS_CARRY_MASK (0x10U) +#define CASPER_STATUS_CARRY_SHIFT (4U) +/*! CARRY - Last carry value if operation produced a carry bit + * 0b0..Carry was 0 or no carry + * 0b1..Carry was 1 + */ +#define CASPER_STATUS_CARRY(x) (((uint32_t)(((uint32_t)(x)) << CASPER_STATUS_CARRY_SHIFT)) & CASPER_STATUS_CARRY_MASK) +#define CASPER_STATUS_BUSY_MASK (0x20U) +#define CASPER_STATUS_BUSY_SHIFT (5U) +/*! BUSY - Indicates if the accelerator is busy performing an operation + * 0b0..Not busy - is idle + * 0b1..Is busy + */ +#define CASPER_STATUS_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CASPER_STATUS_BUSY_SHIFT)) & CASPER_STATUS_BUSY_MASK) +/*! @} */ + +/*! @name INTENSET - Sets interrupts */ +/*! @{ */ +#define CASPER_INTENSET_DONE_MASK (0x1U) +#define CASPER_INTENSET_DONE_SHIFT (0U) +/*! DONE - Set if the accelerator should interrupt when done. + * 0b0..Do not interrupt when done + * 0b1..Interrupt when done + */ +#define CASPER_INTENSET_DONE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_INTENSET_DONE_SHIFT)) & CASPER_INTENSET_DONE_MASK) +/*! @} */ + +/*! @name INTENCLR - Clears interrupts */ +/*! @{ */ +#define CASPER_INTENCLR_DONE_MASK (0x1U) +#define CASPER_INTENCLR_DONE_SHIFT (0U) +/*! DONE - Written to clear an interrupt set with INTENSET. + * 0b0..If written 0, ignored + * 0b1..If written 1, do not Interrupt when done + */ +#define CASPER_INTENCLR_DONE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_INTENCLR_DONE_SHIFT)) & CASPER_INTENCLR_DONE_MASK) +/*! @} */ + +/*! @name INTSTAT - Interrupt status bits (mask of INTENSET and STATUS) */ +/*! @{ */ +#define CASPER_INTSTAT_DONE_MASK (0x1U) +#define CASPER_INTSTAT_DONE_SHIFT (0U) +/*! DONE - If set, interrupt is caused by accelerator being done. + * 0b0..Not caused by accelerator being done + * 0b1..Caused by accelerator being done + */ +#define CASPER_INTSTAT_DONE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_INTSTAT_DONE_SHIFT)) & CASPER_INTSTAT_DONE_MASK) +/*! @} */ + +/*! @name AREG - A register */ +/*! @{ */ +#define CASPER_AREG_REG_VALUE_MASK (0xFFFFFFFFU) +#define CASPER_AREG_REG_VALUE_SHIFT (0U) +#define CASPER_AREG_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_AREG_REG_VALUE_SHIFT)) & CASPER_AREG_REG_VALUE_MASK) +/*! @} */ + +/*! @name BREG - B register */ +/*! @{ */ +#define CASPER_BREG_REG_VALUE_MASK (0xFFFFFFFFU) +#define CASPER_BREG_REG_VALUE_SHIFT (0U) +#define CASPER_BREG_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_BREG_REG_VALUE_SHIFT)) & CASPER_BREG_REG_VALUE_MASK) +/*! @} */ + +/*! @name CREG - C register */ +/*! @{ */ +#define CASPER_CREG_REG_VALUE_MASK (0xFFFFFFFFU) +#define CASPER_CREG_REG_VALUE_SHIFT (0U) +#define CASPER_CREG_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CREG_REG_VALUE_SHIFT)) & CASPER_CREG_REG_VALUE_MASK) +/*! @} */ + +/*! @name DREG - D register */ +/*! @{ */ +#define CASPER_DREG_REG_VALUE_MASK (0xFFFFFFFFU) +#define CASPER_DREG_REG_VALUE_SHIFT (0U) +#define CASPER_DREG_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_DREG_REG_VALUE_SHIFT)) & CASPER_DREG_REG_VALUE_MASK) +/*! @} */ + +/*! @name RES0 - Result register 0 */ +/*! @{ */ +#define CASPER_RES0_REG_VALUE_MASK (0xFFFFFFFFU) +#define CASPER_RES0_REG_VALUE_SHIFT (0U) +#define CASPER_RES0_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_RES0_REG_VALUE_SHIFT)) & CASPER_RES0_REG_VALUE_MASK) +/*! @} */ + +/*! @name RES1 - Result register 1 */ +/*! @{ */ +#define CASPER_RES1_REG_VALUE_MASK (0xFFFFFFFFU) +#define CASPER_RES1_REG_VALUE_SHIFT (0U) +#define CASPER_RES1_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_RES1_REG_VALUE_SHIFT)) & CASPER_RES1_REG_VALUE_MASK) +/*! @} */ + +/*! @name RES2 - Result register 2 */ +/*! @{ */ +#define CASPER_RES2_REG_VALUE_MASK (0xFFFFFFFFU) +#define CASPER_RES2_REG_VALUE_SHIFT (0U) +#define CASPER_RES2_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_RES2_REG_VALUE_SHIFT)) & CASPER_RES2_REG_VALUE_MASK) +/*! @} */ + +/*! @name RES3 - Result register 3 */ +/*! @{ */ +#define CASPER_RES3_REG_VALUE_MASK (0xFFFFFFFFU) +#define CASPER_RES3_REG_VALUE_SHIFT (0U) +#define CASPER_RES3_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_RES3_REG_VALUE_SHIFT)) & CASPER_RES3_REG_VALUE_MASK) +/*! @} */ + +/*! @name MASK - Optional mask register */ +/*! @{ */ +#define CASPER_MASK_MASK_MASK (0xFFFFFFFFU) +#define CASPER_MASK_MASK_SHIFT (0U) +#define CASPER_MASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << CASPER_MASK_MASK_SHIFT)) & CASPER_MASK_MASK_MASK) +/*! @} */ + +/*! @name REMASK - Optional re-mask register */ +/*! @{ */ +#define CASPER_REMASK_MASK_MASK (0xFFFFFFFFU) +#define CASPER_REMASK_MASK_SHIFT (0U) +#define CASPER_REMASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << CASPER_REMASK_MASK_SHIFT)) & CASPER_REMASK_MASK_MASK) +/*! @} */ + +/*! @name LOCK - Security lock register */ +/*! @{ */ +#define CASPER_LOCK_LOCK_MASK (0x1U) +#define CASPER_LOCK_LOCK_SHIFT (0U) +/*! LOCK - Reads back with security level locked to, or 0. Writes as 0 to unlock, 1 to lock. + * 0b0..unlock + * 0b1..Lock to current security level + */ +#define CASPER_LOCK_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOCK_LOCK_SHIFT)) & CASPER_LOCK_LOCK_MASK) +#define CASPER_LOCK_KEY_MASK (0x1FFF0U) +#define CASPER_LOCK_KEY_SHIFT (4U) +/*! KEY - Must be written as 0x73D to change the register. + * 0b0011100111101..If set during write, will allow lock or unlock + */ +#define CASPER_LOCK_KEY(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOCK_KEY_SHIFT)) & CASPER_LOCK_KEY_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group CASPER_Register_Masks */ + + +/* CASPER - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral CASPER base address */ + #define CASPER_BASE (0x500A5000u) + /** Peripheral CASPER base address */ + #define CASPER_BASE_NS (0x400A5000u) + /** Peripheral CASPER base pointer */ + #define CASPER ((CASPER_Type *)CASPER_BASE) + /** Peripheral CASPER base pointer */ + #define CASPER_NS ((CASPER_Type *)CASPER_BASE_NS) + /** Array initializer of CASPER peripheral base addresses */ + #define CASPER_BASE_ADDRS { CASPER_BASE } + /** Array initializer of CASPER peripheral base pointers */ + #define CASPER_BASE_PTRS { CASPER } + /** Array initializer of CASPER peripheral base addresses */ + #define CASPER_BASE_ADDRS_NS { CASPER_BASE_NS } + /** Array initializer of CASPER peripheral base pointers */ + #define CASPER_BASE_PTRS_NS { CASPER_NS } +#else + /** Peripheral CASPER base address */ + #define CASPER_BASE (0x400A5000u) + /** Peripheral CASPER base pointer */ + #define CASPER ((CASPER_Type *)CASPER_BASE) + /** Array initializer of CASPER peripheral base addresses */ + #define CASPER_BASE_ADDRS { CASPER_BASE } + /** Array initializer of CASPER peripheral base pointers */ + #define CASPER_BASE_PTRS { CASPER } +#endif + +/*! + * @} + */ /* end of group CASPER_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CRC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer + * @{ + */ + +/** CRC - Register Layout Typedef */ +typedef struct { + __IO uint32_t MODE; /**< CRC mode register, offset: 0x0 */ + __IO uint32_t SEED; /**< CRC seed register, offset: 0x4 */ + union { /* offset: 0x8 */ + __I uint32_t SUM; /**< CRC checksum register, offset: 0x8 */ + __O uint32_t WR_DATA; /**< CRC data register, offset: 0x8 */ + }; +} CRC_Type; + +/* ---------------------------------------------------------------------------- + -- CRC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CRC_Register_Masks CRC Register Masks + * @{ + */ + +/*! @name MODE - CRC mode register */ +/*! @{ */ +#define CRC_MODE_CRC_POLY_MASK (0x3U) +#define CRC_MODE_CRC_POLY_SHIFT (0U) +#define CRC_MODE_CRC_POLY(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CRC_POLY_SHIFT)) & CRC_MODE_CRC_POLY_MASK) +#define CRC_MODE_BIT_RVS_WR_MASK (0x4U) +#define CRC_MODE_BIT_RVS_WR_SHIFT (2U) +#define CRC_MODE_BIT_RVS_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_WR_SHIFT)) & CRC_MODE_BIT_RVS_WR_MASK) +#define CRC_MODE_CMPL_WR_MASK (0x8U) +#define CRC_MODE_CMPL_WR_SHIFT (3U) +#define CRC_MODE_CMPL_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_WR_SHIFT)) & CRC_MODE_CMPL_WR_MASK) +#define CRC_MODE_BIT_RVS_SUM_MASK (0x10U) +#define CRC_MODE_BIT_RVS_SUM_SHIFT (4U) +#define CRC_MODE_BIT_RVS_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_SUM_SHIFT)) & CRC_MODE_BIT_RVS_SUM_MASK) +#define CRC_MODE_CMPL_SUM_MASK (0x20U) +#define CRC_MODE_CMPL_SUM_SHIFT (5U) +#define CRC_MODE_CMPL_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_SUM_SHIFT)) & CRC_MODE_CMPL_SUM_MASK) +/*! @} */ + +/*! @name SEED - CRC seed register */ +/*! @{ */ +#define CRC_SEED_CRC_SEED_MASK (0xFFFFFFFFU) +#define CRC_SEED_CRC_SEED_SHIFT (0U) +#define CRC_SEED_CRC_SEED(x) (((uint32_t)(((uint32_t)(x)) << CRC_SEED_CRC_SEED_SHIFT)) & CRC_SEED_CRC_SEED_MASK) +/*! @} */ + +/*! @name SUM - CRC checksum register */ +/*! @{ */ +#define CRC_SUM_CRC_SUM_MASK (0xFFFFFFFFU) +#define CRC_SUM_CRC_SUM_SHIFT (0U) +#define CRC_SUM_CRC_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_SUM_CRC_SUM_SHIFT)) & CRC_SUM_CRC_SUM_MASK) +/*! @} */ + +/*! @name WR_DATA - CRC data register */ +/*! @{ */ +#define CRC_WR_DATA_CRC_WR_DATA_MASK (0xFFFFFFFFU) +#define CRC_WR_DATA_CRC_WR_DATA_SHIFT (0U) +#define CRC_WR_DATA_CRC_WR_DATA(x) (((uint32_t)(((uint32_t)(x)) << CRC_WR_DATA_CRC_WR_DATA_SHIFT)) & CRC_WR_DATA_CRC_WR_DATA_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group CRC_Register_Masks */ + + +/* CRC - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral CRC_ENGINE base address */ + #define CRC_ENGINE_BASE (0x50095000u) + /** Peripheral CRC_ENGINE base address */ + #define CRC_ENGINE_BASE_NS (0x40095000u) + /** Peripheral CRC_ENGINE base pointer */ + #define CRC_ENGINE ((CRC_Type *)CRC_ENGINE_BASE) + /** Peripheral CRC_ENGINE base pointer */ + #define CRC_ENGINE_NS ((CRC_Type *)CRC_ENGINE_BASE_NS) + /** Array initializer of CRC peripheral base addresses */ + #define CRC_BASE_ADDRS { CRC_ENGINE_BASE } + /** Array initializer of CRC peripheral base pointers */ + #define CRC_BASE_PTRS { CRC_ENGINE } + /** Array initializer of CRC peripheral base addresses */ + #define CRC_BASE_ADDRS_NS { CRC_ENGINE_BASE_NS } + /** Array initializer of CRC peripheral base pointers */ + #define CRC_BASE_PTRS_NS { CRC_ENGINE_NS } +#else + /** Peripheral CRC_ENGINE base address */ + #define CRC_ENGINE_BASE (0x40095000u) + /** Peripheral CRC_ENGINE base pointer */ + #define CRC_ENGINE ((CRC_Type *)CRC_ENGINE_BASE) + /** Array initializer of CRC peripheral base addresses */ + #define CRC_BASE_ADDRS { CRC_ENGINE_BASE } + /** Array initializer of CRC peripheral base pointers */ + #define CRC_BASE_PTRS { CRC_ENGINE } +#endif + +/*! + * @} + */ /* end of group CRC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CTIMER Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CTIMER_Peripheral_Access_Layer CTIMER Peripheral Access Layer + * @{ + */ + +/** CTIMER - Register Layout Typedef */ +typedef struct { + __IO uint32_t IR; /**< Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending., offset: 0x0 */ + __IO uint32_t TCR; /**< Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR., offset: 0x4 */ + __IO uint32_t TC; /**< Timer Counter, offset: 0x8 */ + __IO uint32_t PR; /**< Prescale Register, offset: 0xC */ + __IO uint32_t PC; /**< Prescale Counter, offset: 0x10 */ + __IO uint32_t MCR; /**< Match Control Register, offset: 0x14 */ + __IO uint32_t MR[4]; /**< Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC., array offset: 0x18, array step: 0x4 */ + __IO uint32_t CCR; /**< Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place., offset: 0x28 */ + __I uint32_t CR[4]; /**< Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input., array offset: 0x2C, array step: 0x4 */ + __IO uint32_t EMR; /**< External Match Register. The EMR controls the match function and the external match pins., offset: 0x3C */ + uint8_t RESERVED_0[48]; + __IO uint32_t CTCR; /**< Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting., offset: 0x70 */ + __IO uint32_t PWMC; /**< PWM Control Register. This register enables PWM mode for the external match pins., offset: 0x74 */ + __IO uint32_t MSR[4]; /**< Match Shadow Register, array offset: 0x78, array step: 0x4 */ +} CTIMER_Type; + +/* ---------------------------------------------------------------------------- + -- CTIMER Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CTIMER_Register_Masks CTIMER Register Masks + * @{ + */ + +/*! @name IR - Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */ +/*! @{ */ +#define CTIMER_IR_MR0INT_MASK (0x1U) +#define CTIMER_IR_MR0INT_SHIFT (0U) +#define CTIMER_IR_MR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR0INT_SHIFT)) & CTIMER_IR_MR0INT_MASK) +#define CTIMER_IR_MR1INT_MASK (0x2U) +#define CTIMER_IR_MR1INT_SHIFT (1U) +#define CTIMER_IR_MR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR1INT_SHIFT)) & CTIMER_IR_MR1INT_MASK) +#define CTIMER_IR_MR2INT_MASK (0x4U) +#define CTIMER_IR_MR2INT_SHIFT (2U) +#define CTIMER_IR_MR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR2INT_SHIFT)) & CTIMER_IR_MR2INT_MASK) +#define CTIMER_IR_MR3INT_MASK (0x8U) +#define CTIMER_IR_MR3INT_SHIFT (3U) +#define CTIMER_IR_MR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR3INT_SHIFT)) & CTIMER_IR_MR3INT_MASK) +#define CTIMER_IR_CR0INT_MASK (0x10U) +#define CTIMER_IR_CR0INT_SHIFT (4U) +#define CTIMER_IR_CR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR0INT_SHIFT)) & CTIMER_IR_CR0INT_MASK) +#define CTIMER_IR_CR1INT_MASK (0x20U) +#define CTIMER_IR_CR1INT_SHIFT (5U) +#define CTIMER_IR_CR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR1INT_SHIFT)) & CTIMER_IR_CR1INT_MASK) +#define CTIMER_IR_CR2INT_MASK (0x40U) +#define CTIMER_IR_CR2INT_SHIFT (6U) +#define CTIMER_IR_CR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR2INT_SHIFT)) & CTIMER_IR_CR2INT_MASK) +#define CTIMER_IR_CR3INT_MASK (0x80U) +#define CTIMER_IR_CR3INT_SHIFT (7U) +#define CTIMER_IR_CR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR3INT_SHIFT)) & CTIMER_IR_CR3INT_MASK) +/*! @} */ + +/*! @name TCR - Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */ +/*! @{ */ +#define CTIMER_TCR_CEN_MASK (0x1U) +#define CTIMER_TCR_CEN_SHIFT (0U) +/*! CEN - Counter enable. + * 0b0..Disabled.The counters are disabled. + * 0b1..Enabled. The Timer Counter and Prescale Counter are enabled. + */ +#define CTIMER_TCR_CEN(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CEN_SHIFT)) & CTIMER_TCR_CEN_MASK) +#define CTIMER_TCR_CRST_MASK (0x2U) +#define CTIMER_TCR_CRST_SHIFT (1U) +/*! CRST - Counter reset. + * 0b0..Disabled. Do nothing. + * 0b1..Enabled. The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of + * the APB bus clock. The counters remain reset until TCR[1] is returned to zero. + */ +#define CTIMER_TCR_CRST(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CRST_SHIFT)) & CTIMER_TCR_CRST_MASK) +/*! @} */ + +/*! @name TC - Timer Counter */ +/*! @{ */ +#define CTIMER_TC_TCVAL_MASK (0xFFFFFFFFU) +#define CTIMER_TC_TCVAL_SHIFT (0U) +#define CTIMER_TC_TCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TC_TCVAL_SHIFT)) & CTIMER_TC_TCVAL_MASK) +/*! @} */ + +/*! @name PR - Prescale Register */ +/*! @{ */ +#define CTIMER_PR_PRVAL_MASK (0xFFFFFFFFU) +#define CTIMER_PR_PRVAL_SHIFT (0U) +#define CTIMER_PR_PRVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PR_PRVAL_SHIFT)) & CTIMER_PR_PRVAL_MASK) +/*! @} */ + +/*! @name PC - Prescale Counter */ +/*! @{ */ +#define CTIMER_PC_PCVAL_MASK (0xFFFFFFFFU) +#define CTIMER_PC_PCVAL_SHIFT (0U) +#define CTIMER_PC_PCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PC_PCVAL_SHIFT)) & CTIMER_PC_PCVAL_MASK) +/*! @} */ + +/*! @name MCR - Match Control Register */ +/*! @{ */ +#define CTIMER_MCR_MR0I_MASK (0x1U) +#define CTIMER_MCR_MR0I_SHIFT (0U) +#define CTIMER_MCR_MR0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK) +#define CTIMER_MCR_MR0R_MASK (0x2U) +#define CTIMER_MCR_MR0R_SHIFT (1U) +#define CTIMER_MCR_MR0R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0R_SHIFT)) & CTIMER_MCR_MR0R_MASK) +#define CTIMER_MCR_MR0S_MASK (0x4U) +#define CTIMER_MCR_MR0S_SHIFT (2U) +#define CTIMER_MCR_MR0S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0S_SHIFT)) & CTIMER_MCR_MR0S_MASK) +#define CTIMER_MCR_MR1I_MASK (0x8U) +#define CTIMER_MCR_MR1I_SHIFT (3U) +#define CTIMER_MCR_MR1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1I_SHIFT)) & CTIMER_MCR_MR1I_MASK) +#define CTIMER_MCR_MR1R_MASK (0x10U) +#define CTIMER_MCR_MR1R_SHIFT (4U) +#define CTIMER_MCR_MR1R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1R_SHIFT)) & CTIMER_MCR_MR1R_MASK) +#define CTIMER_MCR_MR1S_MASK (0x20U) +#define CTIMER_MCR_MR1S_SHIFT (5U) +#define CTIMER_MCR_MR1S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1S_SHIFT)) & CTIMER_MCR_MR1S_MASK) +#define CTIMER_MCR_MR2I_MASK (0x40U) +#define CTIMER_MCR_MR2I_SHIFT (6U) +#define CTIMER_MCR_MR2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2I_SHIFT)) & CTIMER_MCR_MR2I_MASK) +#define CTIMER_MCR_MR2R_MASK (0x80U) +#define CTIMER_MCR_MR2R_SHIFT (7U) +#define CTIMER_MCR_MR2R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2R_SHIFT)) & CTIMER_MCR_MR2R_MASK) +#define CTIMER_MCR_MR2S_MASK (0x100U) +#define CTIMER_MCR_MR2S_SHIFT (8U) +#define CTIMER_MCR_MR2S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2S_SHIFT)) & CTIMER_MCR_MR2S_MASK) +#define CTIMER_MCR_MR3I_MASK (0x200U) +#define CTIMER_MCR_MR3I_SHIFT (9U) +#define CTIMER_MCR_MR3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3I_SHIFT)) & CTIMER_MCR_MR3I_MASK) +#define CTIMER_MCR_MR3R_MASK (0x400U) +#define CTIMER_MCR_MR3R_SHIFT (10U) +#define CTIMER_MCR_MR3R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3R_SHIFT)) & CTIMER_MCR_MR3R_MASK) +#define CTIMER_MCR_MR3S_MASK (0x800U) +#define CTIMER_MCR_MR3S_SHIFT (11U) +#define CTIMER_MCR_MR3S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3S_SHIFT)) & CTIMER_MCR_MR3S_MASK) +#define CTIMER_MCR_MR0RL_MASK (0x1000000U) +#define CTIMER_MCR_MR0RL_SHIFT (24U) +#define CTIMER_MCR_MR0RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0RL_SHIFT)) & CTIMER_MCR_MR0RL_MASK) +#define CTIMER_MCR_MR1RL_MASK (0x2000000U) +#define CTIMER_MCR_MR1RL_SHIFT (25U) +#define CTIMER_MCR_MR1RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1RL_SHIFT)) & CTIMER_MCR_MR1RL_MASK) +#define CTIMER_MCR_MR2RL_MASK (0x4000000U) +#define CTIMER_MCR_MR2RL_SHIFT (26U) +#define CTIMER_MCR_MR2RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2RL_SHIFT)) & CTIMER_MCR_MR2RL_MASK) +#define CTIMER_MCR_MR3RL_MASK (0x8000000U) +#define CTIMER_MCR_MR3RL_SHIFT (27U) +#define CTIMER_MCR_MR3RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3RL_SHIFT)) & CTIMER_MCR_MR3RL_MASK) +/*! @} */ + +/*! @name MR - Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */ +/*! @{ */ +#define CTIMER_MR_MATCH_MASK (0xFFFFFFFFU) +#define CTIMER_MR_MATCH_SHIFT (0U) +#define CTIMER_MR_MATCH(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MR_MATCH_SHIFT)) & CTIMER_MR_MATCH_MASK) +/*! @} */ + +/* The count of CTIMER_MR */ +#define CTIMER_MR_COUNT (4U) + +/*! @name CCR - Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */ +/*! @{ */ +#define CTIMER_CCR_CAP0RE_MASK (0x1U) +#define CTIMER_CCR_CAP0RE_SHIFT (0U) +#define CTIMER_CCR_CAP0RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0RE_SHIFT)) & CTIMER_CCR_CAP0RE_MASK) +#define CTIMER_CCR_CAP0FE_MASK (0x2U) +#define CTIMER_CCR_CAP0FE_SHIFT (1U) +#define CTIMER_CCR_CAP0FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0FE_SHIFT)) & CTIMER_CCR_CAP0FE_MASK) +#define CTIMER_CCR_CAP0I_MASK (0x4U) +#define CTIMER_CCR_CAP0I_SHIFT (2U) +#define CTIMER_CCR_CAP0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK) +#define CTIMER_CCR_CAP1RE_MASK (0x8U) +#define CTIMER_CCR_CAP1RE_SHIFT (3U) +#define CTIMER_CCR_CAP1RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1RE_SHIFT)) & CTIMER_CCR_CAP1RE_MASK) +#define CTIMER_CCR_CAP1FE_MASK (0x10U) +#define CTIMER_CCR_CAP1FE_SHIFT (4U) +#define CTIMER_CCR_CAP1FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1FE_SHIFT)) & CTIMER_CCR_CAP1FE_MASK) +#define CTIMER_CCR_CAP1I_MASK (0x20U) +#define CTIMER_CCR_CAP1I_SHIFT (5U) +#define CTIMER_CCR_CAP1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1I_SHIFT)) & CTIMER_CCR_CAP1I_MASK) +#define CTIMER_CCR_CAP2RE_MASK (0x40U) +#define CTIMER_CCR_CAP2RE_SHIFT (6U) +#define CTIMER_CCR_CAP2RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2RE_SHIFT)) & CTIMER_CCR_CAP2RE_MASK) +#define CTIMER_CCR_CAP2FE_MASK (0x80U) +#define CTIMER_CCR_CAP2FE_SHIFT (7U) +#define CTIMER_CCR_CAP2FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2FE_SHIFT)) & CTIMER_CCR_CAP2FE_MASK) +#define CTIMER_CCR_CAP2I_MASK (0x100U) +#define CTIMER_CCR_CAP2I_SHIFT (8U) +#define CTIMER_CCR_CAP2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2I_SHIFT)) & CTIMER_CCR_CAP2I_MASK) +#define CTIMER_CCR_CAP3RE_MASK (0x200U) +#define CTIMER_CCR_CAP3RE_SHIFT (9U) +#define CTIMER_CCR_CAP3RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3RE_SHIFT)) & CTIMER_CCR_CAP3RE_MASK) +#define CTIMER_CCR_CAP3FE_MASK (0x400U) +#define CTIMER_CCR_CAP3FE_SHIFT (10U) +#define CTIMER_CCR_CAP3FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3FE_SHIFT)) & CTIMER_CCR_CAP3FE_MASK) +#define CTIMER_CCR_CAP3I_MASK (0x800U) +#define CTIMER_CCR_CAP3I_SHIFT (11U) +#define CTIMER_CCR_CAP3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3I_SHIFT)) & CTIMER_CCR_CAP3I_MASK) +/*! @} */ + +/*! @name CR - Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input. */ +/*! @{ */ +#define CTIMER_CR_CAP_MASK (0xFFFFFFFFU) +#define CTIMER_CR_CAP_SHIFT (0U) +#define CTIMER_CR_CAP(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CR_CAP_SHIFT)) & CTIMER_CR_CAP_MASK) +/*! @} */ + +/* The count of CTIMER_CR */ +#define CTIMER_CR_COUNT (4U) + +/*! @name EMR - External Match Register. The EMR controls the match function and the external match pins. */ +/*! @{ */ +#define CTIMER_EMR_EM0_MASK (0x1U) +#define CTIMER_EMR_EM0_SHIFT (0U) +#define CTIMER_EMR_EM0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM0_SHIFT)) & CTIMER_EMR_EM0_MASK) +#define CTIMER_EMR_EM1_MASK (0x2U) +#define CTIMER_EMR_EM1_SHIFT (1U) +#define CTIMER_EMR_EM1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM1_SHIFT)) & CTIMER_EMR_EM1_MASK) +#define CTIMER_EMR_EM2_MASK (0x4U) +#define CTIMER_EMR_EM2_SHIFT (2U) +#define CTIMER_EMR_EM2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM2_SHIFT)) & CTIMER_EMR_EM2_MASK) +#define CTIMER_EMR_EM3_MASK (0x8U) +#define CTIMER_EMR_EM3_SHIFT (3U) +#define CTIMER_EMR_EM3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM3_SHIFT)) & CTIMER_EMR_EM3_MASK) +#define CTIMER_EMR_EMC0_MASK (0x30U) +#define CTIMER_EMR_EMC0_SHIFT (4U) +/*! EMC0 - External Match Control 0. Determines the functionality of External Match 0. + * 0b00..Do Nothing. + * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT0 pin is LOW if pinned out). + * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT0 pin is HIGH if pinned out). + * 0b11..Toggle. Toggle the corresponding External Match bit/output. + */ +#define CTIMER_EMR_EMC0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC0_SHIFT)) & CTIMER_EMR_EMC0_MASK) +#define CTIMER_EMR_EMC1_MASK (0xC0U) +#define CTIMER_EMR_EMC1_SHIFT (6U) +/*! EMC1 - External Match Control 1. Determines the functionality of External Match 1. + * 0b00..Do Nothing. + * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT1 pin is LOW if pinned out). + * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT1 pin is HIGH if pinned out). + * 0b11..Toggle. Toggle the corresponding External Match bit/output. + */ +#define CTIMER_EMR_EMC1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC1_SHIFT)) & CTIMER_EMR_EMC1_MASK) +#define CTIMER_EMR_EMC2_MASK (0x300U) +#define CTIMER_EMR_EMC2_SHIFT (8U) +/*! EMC2 - External Match Control 2. Determines the functionality of External Match 2. + * 0b00..Do Nothing. + * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT2 pin is LOW if pinned out). + * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT2 pin is HIGH if pinned out). + * 0b11..Toggle. Toggle the corresponding External Match bit/output. + */ +#define CTIMER_EMR_EMC2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC2_SHIFT)) & CTIMER_EMR_EMC2_MASK) +#define CTIMER_EMR_EMC3_MASK (0xC00U) +#define CTIMER_EMR_EMC3_SHIFT (10U) +/*! EMC3 - External Match Control 3. Determines the functionality of External Match 3. + * 0b00..Do Nothing. + * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT3 pin is LOW if pinned out). + * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT3 pin is HIGH if pinned out). + * 0b11..Toggle. Toggle the corresponding External Match bit/output. + */ +#define CTIMER_EMR_EMC3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC3_SHIFT)) & CTIMER_EMR_EMC3_MASK) +/*! @} */ + +/*! @name CTCR - Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */ +/*! @{ */ +#define CTIMER_CTCR_CTMODE_MASK (0x3U) +#define CTIMER_CTCR_CTMODE_SHIFT (0U) +/*! CTMODE - Counter/Timer Mode This field selects which rising APB bus clock edges can increment + * Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC + * is incremented when the Prescale Counter matches the Prescale Register. + * 0b00..Timer Mode. Incremented every rising APB bus clock edge. + * 0b01..Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2. + * 0b10..Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2. + * 0b11..Counter Mode dual edge. TC is incremented on both edges on the CAP input selected by bits 3:2. + */ +#define CTIMER_CTCR_CTMODE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CTMODE_SHIFT)) & CTIMER_CTCR_CTMODE_MASK) +#define CTIMER_CTCR_CINSEL_MASK (0xCU) +#define CTIMER_CTCR_CINSEL_SHIFT (2U) +/*! CINSEL - Count Input Select When bits 1:0 in this register are not 00, these bits select which + * CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input + * in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be + * programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the + * same timer. + * 0b00..Channel 0. CAPn.0 for CTIMERn + * 0b01..Channel 1. CAPn.1 for CTIMERn + * 0b10..Channel 2. CAPn.2 for CTIMERn + * 0b11..Channel 3. CAPn.3 for CTIMERn + */ +#define CTIMER_CTCR_CINSEL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CINSEL_SHIFT)) & CTIMER_CTCR_CINSEL_MASK) +#define CTIMER_CTCR_ENCC_MASK (0x10U) +#define CTIMER_CTCR_ENCC_SHIFT (4U) +#define CTIMER_CTCR_ENCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_ENCC_SHIFT)) & CTIMER_CTCR_ENCC_MASK) +#define CTIMER_CTCR_SELCC_MASK (0xE0U) +#define CTIMER_CTCR_SELCC_SHIFT (5U) +/*! SELCC - Edge select. When bit 4 is 1, these bits select which capture input edge will cause the + * timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to + * 0x3 and 0x6 to 0x7 are reserved. + * 0b000..Channel 0 Rising Edge. Rising edge of the signal on capture channel 0 clears the timer (if bit 4 is set). + * 0b001..Channel 0 Falling Edge. Falling edge of the signal on capture channel 0 clears the timer (if bit 4 is set). + * 0b010..Channel 1 Rising Edge. Rising edge of the signal on capture channel 1 clears the timer (if bit 4 is set). + * 0b011..Channel 1 Falling Edge. Falling edge of the signal on capture channel 1 clears the timer (if bit 4 is set). + * 0b100..Channel 2 Rising Edge. Rising edge of the signal on capture channel 2 clears the timer (if bit 4 is set). + * 0b101..Channel 2 Falling Edge. Falling edge of the signal on capture channel 2 clears the timer (if bit 4 is set). + */ +#define CTIMER_CTCR_SELCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_SELCC_SHIFT)) & CTIMER_CTCR_SELCC_MASK) +/*! @} */ + +/*! @name PWMC - PWM Control Register. This register enables PWM mode for the external match pins. */ +/*! @{ */ +#define CTIMER_PWMC_PWMEN0_MASK (0x1U) +#define CTIMER_PWMC_PWMEN0_SHIFT (0U) +/*! PWMEN0 - PWM mode enable for channel0. + * 0b0..Match. CTIMERn_MAT0 is controlled by EM0. + * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT0. + */ +#define CTIMER_PWMC_PWMEN0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN0_SHIFT)) & CTIMER_PWMC_PWMEN0_MASK) +#define CTIMER_PWMC_PWMEN1_MASK (0x2U) +#define CTIMER_PWMC_PWMEN1_SHIFT (1U) +/*! PWMEN1 - PWM mode enable for channel1. + * 0b0..Match. CTIMERn_MAT01 is controlled by EM1. + * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT1. + */ +#define CTIMER_PWMC_PWMEN1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN1_SHIFT)) & CTIMER_PWMC_PWMEN1_MASK) +#define CTIMER_PWMC_PWMEN2_MASK (0x4U) +#define CTIMER_PWMC_PWMEN2_SHIFT (2U) +/*! PWMEN2 - PWM mode enable for channel2. + * 0b0..Match. CTIMERn_MAT2 is controlled by EM2. + * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT2. + */ +#define CTIMER_PWMC_PWMEN2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN2_SHIFT)) & CTIMER_PWMC_PWMEN2_MASK) +#define CTIMER_PWMC_PWMEN3_MASK (0x8U) +#define CTIMER_PWMC_PWMEN3_SHIFT (3U) +/*! PWMEN3 - PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle. + * 0b0..Match. CTIMERn_MAT3 is controlled by EM3. + * 0b1..PWM. PWM mode is enabled for CT132Bn_MAT3. + */ +#define CTIMER_PWMC_PWMEN3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN3_SHIFT)) & CTIMER_PWMC_PWMEN3_MASK) +/*! @} */ + +/*! @name MSR - Match Shadow Register */ +/*! @{ */ +#define CTIMER_MSR_SHADOWW_MASK (0xFFFFFFFFU) +#define CTIMER_MSR_SHADOWW_SHIFT (0U) +#define CTIMER_MSR_SHADOWW(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MSR_SHADOWW_SHIFT)) & CTIMER_MSR_SHADOWW_MASK) +/*! @} */ + +/* The count of CTIMER_MSR */ +#define CTIMER_MSR_COUNT (4U) + + +/*! + * @} + */ /* end of group CTIMER_Register_Masks */ + + +/* CTIMER - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral CTIMER0 base address */ + #define CTIMER0_BASE (0x50008000u) + /** Peripheral CTIMER0 base address */ + #define CTIMER0_BASE_NS (0x40008000u) + /** Peripheral CTIMER0 base pointer */ + #define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) + /** Peripheral CTIMER0 base pointer */ + #define CTIMER0_NS ((CTIMER_Type *)CTIMER0_BASE_NS) + /** Peripheral CTIMER1 base address */ + #define CTIMER1_BASE (0x50009000u) + /** Peripheral CTIMER1 base address */ + #define CTIMER1_BASE_NS (0x40009000u) + /** Peripheral CTIMER1 base pointer */ + #define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) + /** Peripheral CTIMER1 base pointer */ + #define CTIMER1_NS ((CTIMER_Type *)CTIMER1_BASE_NS) + /** Peripheral CTIMER2 base address */ + #define CTIMER2_BASE (0x50028000u) + /** Peripheral CTIMER2 base address */ + #define CTIMER2_BASE_NS (0x40028000u) + /** Peripheral CTIMER2 base pointer */ + #define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE) + /** Peripheral CTIMER2 base pointer */ + #define CTIMER2_NS ((CTIMER_Type *)CTIMER2_BASE_NS) + /** Peripheral CTIMER3 base address */ + #define CTIMER3_BASE (0x50029000u) + /** Peripheral CTIMER3 base address */ + #define CTIMER3_BASE_NS (0x40029000u) + /** Peripheral CTIMER3 base pointer */ + #define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE) + /** Peripheral CTIMER3 base pointer */ + #define CTIMER3_NS ((CTIMER_Type *)CTIMER3_BASE_NS) + /** Peripheral CTIMER4 base address */ + #define CTIMER4_BASE (0x5002A000u) + /** Peripheral CTIMER4 base address */ + #define CTIMER4_BASE_NS (0x4002A000u) + /** Peripheral CTIMER4 base pointer */ + #define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE) + /** Peripheral CTIMER4 base pointer */ + #define CTIMER4_NS ((CTIMER_Type *)CTIMER4_BASE_NS) + /** Array initializer of CTIMER peripheral base addresses */ + #define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE } + /** Array initializer of CTIMER peripheral base pointers */ + #define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 } + /** Array initializer of CTIMER peripheral base addresses */ + #define CTIMER_BASE_ADDRS_NS { CTIMER0_BASE_NS, CTIMER1_BASE_NS, CTIMER2_BASE_NS, CTIMER3_BASE_NS, CTIMER4_BASE_NS } + /** Array initializer of CTIMER peripheral base pointers */ + #define CTIMER_BASE_PTRS_NS { CTIMER0_NS, CTIMER1_NS, CTIMER2_NS, CTIMER3_NS, CTIMER4_NS } +#else + /** Peripheral CTIMER0 base address */ + #define CTIMER0_BASE (0x40008000u) + /** Peripheral CTIMER0 base pointer */ + #define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) + /** Peripheral CTIMER1 base address */ + #define CTIMER1_BASE (0x40009000u) + /** Peripheral CTIMER1 base pointer */ + #define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) + /** Peripheral CTIMER2 base address */ + #define CTIMER2_BASE (0x40028000u) + /** Peripheral CTIMER2 base pointer */ + #define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE) + /** Peripheral CTIMER3 base address */ + #define CTIMER3_BASE (0x40029000u) + /** Peripheral CTIMER3 base pointer */ + #define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE) + /** Peripheral CTIMER4 base address */ + #define CTIMER4_BASE (0x4002A000u) + /** Peripheral CTIMER4 base pointer */ + #define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE) + /** Array initializer of CTIMER peripheral base addresses */ + #define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE } + /** Array initializer of CTIMER peripheral base pointers */ + #define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 } +#endif +/** Interrupt vectors for the CTIMER peripheral type */ +#define CTIMER_IRQS { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn, CTIMER3_IRQn, CTIMER4_IRQn } + +/*! + * @} + */ /* end of group CTIMER_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DGBMAILBOX Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DGBMAILBOX_Peripheral_Access_Layer DGBMAILBOX Peripheral Access Layer + * @{ + */ + +/** DGBMAILBOX - Register Layout Typedef */ +typedef struct { + __IO uint32_t CSW; /**< CRC mode register, offset: 0x0 */ + __IO uint32_t REQUEST; /**< CRC seed register, offset: 0x4 */ + __IO uint32_t RETURN; /**< Return value from ROM., offset: 0x8 */ + uint8_t RESERVED_0[240]; + __I uint32_t ID; /**< Identification register, offset: 0xFC */ +} DGBMAILBOX_Type; + +/* ---------------------------------------------------------------------------- + -- DGBMAILBOX Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DGBMAILBOX_Register_Masks DGBMAILBOX Register Masks + * @{ + */ + +/*! @name CSW - CRC mode register */ +/*! @{ */ +#define DGBMAILBOX_CSW_RESYNCH_REQ_MASK (0x1U) +#define DGBMAILBOX_CSW_RESYNCH_REQ_SHIFT (0U) +#define DGBMAILBOX_CSW_RESYNCH_REQ(x) (((uint32_t)(((uint32_t)(x)) << DGBMAILBOX_CSW_RESYNCH_REQ_SHIFT)) & DGBMAILBOX_CSW_RESYNCH_REQ_MASK) +#define DGBMAILBOX_CSW_REQ_PENDING_MASK (0x2U) +#define DGBMAILBOX_CSW_REQ_PENDING_SHIFT (1U) +#define DGBMAILBOX_CSW_REQ_PENDING(x) (((uint32_t)(((uint32_t)(x)) << DGBMAILBOX_CSW_REQ_PENDING_SHIFT)) & DGBMAILBOX_CSW_REQ_PENDING_MASK) +#define DGBMAILBOX_CSW_DBG_OR_ERR_MASK (0x4U) +#define DGBMAILBOX_CSW_DBG_OR_ERR_SHIFT (2U) +#define DGBMAILBOX_CSW_DBG_OR_ERR(x) (((uint32_t)(((uint32_t)(x)) << DGBMAILBOX_CSW_DBG_OR_ERR_SHIFT)) & DGBMAILBOX_CSW_DBG_OR_ERR_MASK) +#define DGBMAILBOX_CSW_AHB_OR_ERR_MASK (0x8U) +#define DGBMAILBOX_CSW_AHB_OR_ERR_SHIFT (3U) +#define DGBMAILBOX_CSW_AHB_OR_ERR(x) (((uint32_t)(((uint32_t)(x)) << DGBMAILBOX_CSW_AHB_OR_ERR_SHIFT)) & DGBMAILBOX_CSW_AHB_OR_ERR_MASK) +#define DGBMAILBOX_CSW_SOFT_RESET_MASK (0x10U) +#define DGBMAILBOX_CSW_SOFT_RESET_SHIFT (4U) +#define DGBMAILBOX_CSW_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << DGBMAILBOX_CSW_SOFT_RESET_SHIFT)) & DGBMAILBOX_CSW_SOFT_RESET_MASK) +#define DGBMAILBOX_CSW_CHIP_RESET_REQ_MASK (0x20U) +#define DGBMAILBOX_CSW_CHIP_RESET_REQ_SHIFT (5U) +#define DGBMAILBOX_CSW_CHIP_RESET_REQ(x) (((uint32_t)(((uint32_t)(x)) << DGBMAILBOX_CSW_CHIP_RESET_REQ_SHIFT)) & DGBMAILBOX_CSW_CHIP_RESET_REQ_MASK) +/*! @} */ + +/*! @name REQUEST - CRC seed register */ +/*! @{ */ +#define DGBMAILBOX_REQUEST_REQ_MASK (0xFFFFFFFFU) +#define DGBMAILBOX_REQUEST_REQ_SHIFT (0U) +#define DGBMAILBOX_REQUEST_REQ(x) (((uint32_t)(((uint32_t)(x)) << DGBMAILBOX_REQUEST_REQ_SHIFT)) & DGBMAILBOX_REQUEST_REQ_MASK) +/*! @} */ + +/*! @name RETURN - Return value from ROM. */ +/*! @{ */ +#define DGBMAILBOX_RETURN_RET_MASK (0xFFFFFFFFU) +#define DGBMAILBOX_RETURN_RET_SHIFT (0U) +#define DGBMAILBOX_RETURN_RET(x) (((uint32_t)(((uint32_t)(x)) << DGBMAILBOX_RETURN_RET_SHIFT)) & DGBMAILBOX_RETURN_RET_MASK) +/*! @} */ + +/*! @name ID - Identification register */ +/*! @{ */ +#define DGBMAILBOX_ID_ID_MASK (0xFFFFFFFFU) +#define DGBMAILBOX_ID_ID_SHIFT (0U) +#define DGBMAILBOX_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << DGBMAILBOX_ID_ID_SHIFT)) & DGBMAILBOX_ID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group DGBMAILBOX_Register_Masks */ + + +/* DGBMAILBOX - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral DGBMAILBOX base address */ + #define DGBMAILBOX_BASE (0x5009C000u) + /** Peripheral DGBMAILBOX base address */ + #define DGBMAILBOX_BASE_NS (0x4009C000u) + /** Peripheral DGBMAILBOX base pointer */ + #define DGBMAILBOX ((DGBMAILBOX_Type *)DGBMAILBOX_BASE) + /** Peripheral DGBMAILBOX base pointer */ + #define DGBMAILBOX_NS ((DGBMAILBOX_Type *)DGBMAILBOX_BASE_NS) + /** Array initializer of DGBMAILBOX peripheral base addresses */ + #define DGBMAILBOX_BASE_ADDRS { DGBMAILBOX_BASE } + /** Array initializer of DGBMAILBOX peripheral base pointers */ + #define DGBMAILBOX_BASE_PTRS { DGBMAILBOX } + /** Array initializer of DGBMAILBOX peripheral base addresses */ + #define DGBMAILBOX_BASE_ADDRS_NS { DGBMAILBOX_BASE_NS } + /** Array initializer of DGBMAILBOX peripheral base pointers */ + #define DGBMAILBOX_BASE_PTRS_NS { DGBMAILBOX_NS } +#else + /** Peripheral DGBMAILBOX base address */ + #define DGBMAILBOX_BASE (0x4009C000u) + /** Peripheral DGBMAILBOX base pointer */ + #define DGBMAILBOX ((DGBMAILBOX_Type *)DGBMAILBOX_BASE) + /** Array initializer of DGBMAILBOX peripheral base addresses */ + #define DGBMAILBOX_BASE_ADDRS { DGBMAILBOX_BASE } + /** Array initializer of DGBMAILBOX peripheral base pointers */ + #define DGBMAILBOX_BASE_PTRS { DGBMAILBOX } +#endif + +/*! + * @} + */ /* end of group DGBMAILBOX_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DMA Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer + * @{ + */ + +/** DMA - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< DMA control., offset: 0x0 */ + __I uint32_t INTSTAT; /**< Interrupt status., offset: 0x4 */ + __IO uint32_t SRAMBASE; /**< SRAM address of the channel configuration table., offset: 0x8 */ + uint8_t RESERVED_0[20]; + struct { /* offset: 0x20, array step: 0x5C */ + __IO uint32_t ENABLESET; /**< Channel Enable read and Set for all DMA channels., array offset: 0x20, array step: 0x5C */ + uint8_t RESERVED_0[4]; + __O uint32_t ENABLECLR; /**< Channel Enable Clear for all DMA channels., array offset: 0x28, array step: 0x5C */ + uint8_t RESERVED_1[4]; + __I uint32_t ACTIVE; /**< Channel Active status for all DMA channels., array offset: 0x30, array step: 0x5C */ + uint8_t RESERVED_2[4]; + __I uint32_t BUSY; /**< Channel Busy status for all DMA channels., array offset: 0x38, array step: 0x5C */ + uint8_t RESERVED_3[4]; + __IO uint32_t ERRINT; /**< Error Interrupt status for all DMA channels., array offset: 0x40, array step: 0x5C */ + uint8_t RESERVED_4[4]; + __IO uint32_t INTENSET; /**< Interrupt Enable read and Set for all DMA channels., array offset: 0x48, array step: 0x5C */ + uint8_t RESERVED_5[4]; + __O uint32_t INTENCLR; /**< Interrupt Enable Clear for all DMA channels., array offset: 0x50, array step: 0x5C */ + uint8_t RESERVED_6[4]; + __IO uint32_t INTA; /**< Interrupt A status for all DMA channels., array offset: 0x58, array step: 0x5C */ + uint8_t RESERVED_7[4]; + __IO uint32_t INTB; /**< Interrupt B status for all DMA channels., array offset: 0x60, array step: 0x5C */ + uint8_t RESERVED_8[4]; + __O uint32_t SETVALID; /**< Set ValidPending control bits for all DMA channels., array offset: 0x68, array step: 0x5C */ + uint8_t RESERVED_9[4]; + __O uint32_t SETTRIG; /**< Set Trigger control bits for all DMA channels., array offset: 0x70, array step: 0x5C */ + uint8_t RESERVED_10[4]; + __O uint32_t ABORT; /**< Channel Abort control for all DMA channels., array offset: 0x78, array step: 0x5C */ + } COMMON[1]; + uint8_t RESERVED_1[900]; + struct { /* offset: 0x400, array step: 0x10 */ + __IO uint32_t CFG; /**< Configuration register for DMA channel ., array offset: 0x400, array step: 0x10 */ + __I uint32_t CTLSTAT; /**< Control and status register for DMA channel ., array offset: 0x404, array step: 0x10 */ + __IO uint32_t XFERCFG; /**< Transfer configuration register for DMA channel ., array offset: 0x408, array step: 0x10 */ + uint8_t RESERVED_0[4]; + } CHANNEL[30]; +} DMA_Type; + +/* ---------------------------------------------------------------------------- + -- DMA Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMA_Register_Masks DMA Register Masks + * @{ + */ + +/*! @name CTRL - DMA control. */ +/*! @{ */ +#define DMA_CTRL_ENABLE_MASK (0x1U) +#define DMA_CTRL_ENABLE_SHIFT (0U) +/*! ENABLE - DMA controller master enable. + * 0b0..Disabled. The DMA controller is disabled. This clears any triggers that were asserted at the point when + * disabled, but does not prevent re-triggering when the DMA controller is re-enabled. + * 0b1..Enabled. The DMA controller is enabled. + */ +#define DMA_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CTRL_ENABLE_SHIFT)) & DMA_CTRL_ENABLE_MASK) +/*! @} */ + +/*! @name INTSTAT - Interrupt status. */ +/*! @{ */ +#define DMA_INTSTAT_ACTIVEINT_MASK (0x2U) +#define DMA_INTSTAT_ACTIVEINT_SHIFT (1U) +/*! ACTIVEINT - Summarizes whether any enabled interrupts (other than error interrupts) are pending. + * 0b0..Not pending. No enabled interrupts are pending. + * 0b1..Pending. At least one enabled interrupt is pending. + */ +#define DMA_INTSTAT_ACTIVEINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEINT_SHIFT)) & DMA_INTSTAT_ACTIVEINT_MASK) +#define DMA_INTSTAT_ACTIVEERRINT_MASK (0x4U) +#define DMA_INTSTAT_ACTIVEERRINT_SHIFT (2U) +/*! ACTIVEERRINT - Summarizes whether any error interrupts are pending. + * 0b0..Not pending. No error interrupts are pending. + * 0b1..Pending. At least one error interrupt is pending. + */ +#define DMA_INTSTAT_ACTIVEERRINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEERRINT_SHIFT)) & DMA_INTSTAT_ACTIVEERRINT_MASK) +/*! @} */ + +/*! @name SRAMBASE - SRAM address of the channel configuration table. */ +/*! @{ */ +#define DMA_SRAMBASE_OFFSET_MASK (0xFFFFFE00U) +#define DMA_SRAMBASE_OFFSET_SHIFT (9U) +#define DMA_SRAMBASE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << DMA_SRAMBASE_OFFSET_SHIFT)) & DMA_SRAMBASE_OFFSET_MASK) +/*! @} */ + +/*! @name COMMON_ENABLESET - Channel Enable read and Set for all DMA channels. */ +/*! @{ */ +#define DMA_COMMON_ENABLESET_ENA_MASK (0xFFFFFFFFU) +#define DMA_COMMON_ENABLESET_ENA_SHIFT (0U) +#define DMA_COMMON_ENABLESET_ENA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENA_SHIFT)) & DMA_COMMON_ENABLESET_ENA_MASK) +/*! @} */ + +/* The count of DMA_COMMON_ENABLESET */ +#define DMA_COMMON_ENABLESET_COUNT (1U) + +/*! @name COMMON_ENABLECLR - Channel Enable Clear for all DMA channels. */ +/*! @{ */ +#define DMA_COMMON_ENABLECLR_CLR_MASK (0xFFFFFFFFU) +#define DMA_COMMON_ENABLECLR_CLR_SHIFT (0U) +#define DMA_COMMON_ENABLECLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR_SHIFT)) & DMA_COMMON_ENABLECLR_CLR_MASK) +/*! @} */ + +/* The count of DMA_COMMON_ENABLECLR */ +#define DMA_COMMON_ENABLECLR_COUNT (1U) + +/*! @name COMMON_ACTIVE - Channel Active status for all DMA channels. */ +/*! @{ */ +#define DMA_COMMON_ACTIVE_ACT_MASK (0xFFFFFFFFU) +#define DMA_COMMON_ACTIVE_ACT_SHIFT (0U) +#define DMA_COMMON_ACTIVE_ACT(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACT_SHIFT)) & DMA_COMMON_ACTIVE_ACT_MASK) +/*! @} */ + +/* The count of DMA_COMMON_ACTIVE */ +#define DMA_COMMON_ACTIVE_COUNT (1U) + +/*! @name COMMON_BUSY - Channel Busy status for all DMA channels. */ +/*! @{ */ +#define DMA_COMMON_BUSY_BSY_MASK (0xFFFFFFFFU) +#define DMA_COMMON_BUSY_BSY_SHIFT (0U) +#define DMA_COMMON_BUSY_BSY(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BSY_SHIFT)) & DMA_COMMON_BUSY_BSY_MASK) +/*! @} */ + +/* The count of DMA_COMMON_BUSY */ +#define DMA_COMMON_BUSY_COUNT (1U) + +/*! @name COMMON_ERRINT - Error Interrupt status for all DMA channels. */ +/*! @{ */ +#define DMA_COMMON_ERRINT_ERR_MASK (0xFFFFFFFFU) +#define DMA_COMMON_ERRINT_ERR_SHIFT (0U) +#define DMA_COMMON_ERRINT_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR_SHIFT)) & DMA_COMMON_ERRINT_ERR_MASK) +/*! @} */ + +/* The count of DMA_COMMON_ERRINT */ +#define DMA_COMMON_ERRINT_COUNT (1U) + +/*! @name COMMON_INTENSET - Interrupt Enable read and Set for all DMA channels. */ +/*! @{ */ +#define DMA_COMMON_INTENSET_INTEN_MASK (0xFFFFFFFFU) +#define DMA_COMMON_INTENSET_INTEN_SHIFT (0U) +#define DMA_COMMON_INTENSET_INTEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN_SHIFT)) & DMA_COMMON_INTENSET_INTEN_MASK) +/*! @} */ + +/* The count of DMA_COMMON_INTENSET */ +#define DMA_COMMON_INTENSET_COUNT (1U) + +/*! @name COMMON_INTENCLR - Interrupt Enable Clear for all DMA channels. */ +/*! @{ */ +#define DMA_COMMON_INTENCLR_CLR_MASK (0xFFFFFFFFU) +#define DMA_COMMON_INTENCLR_CLR_SHIFT (0U) +#define DMA_COMMON_INTENCLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR_SHIFT)) & DMA_COMMON_INTENCLR_CLR_MASK) +/*! @} */ + +/* The count of DMA_COMMON_INTENCLR */ +#define DMA_COMMON_INTENCLR_COUNT (1U) + +/*! @name COMMON_INTA - Interrupt A status for all DMA channels. */ +/*! @{ */ +#define DMA_COMMON_INTA_IA_MASK (0xFFFFFFFFU) +#define DMA_COMMON_INTA_IA_SHIFT (0U) +#define DMA_COMMON_INTA_IA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_IA_SHIFT)) & DMA_COMMON_INTA_IA_MASK) +/*! @} */ + +/* The count of DMA_COMMON_INTA */ +#define DMA_COMMON_INTA_COUNT (1U) + +/*! @name COMMON_INTB - Interrupt B status for all DMA channels. */ +/*! @{ */ +#define DMA_COMMON_INTB_IB_MASK (0xFFFFFFFFU) +#define DMA_COMMON_INTB_IB_SHIFT (0U) +#define DMA_COMMON_INTB_IB(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_IB_SHIFT)) & DMA_COMMON_INTB_IB_MASK) +/*! @} */ + +/* The count of DMA_COMMON_INTB */ +#define DMA_COMMON_INTB_COUNT (1U) + +/*! @name COMMON_SETVALID - Set ValidPending control bits for all DMA channels. */ +/*! @{ */ +#define DMA_COMMON_SETVALID_SV_MASK (0xFFFFFFFFU) +#define DMA_COMMON_SETVALID_SV_SHIFT (0U) +#define DMA_COMMON_SETVALID_SV(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SV_SHIFT)) & DMA_COMMON_SETVALID_SV_MASK) +/*! @} */ + +/* The count of DMA_COMMON_SETVALID */ +#define DMA_COMMON_SETVALID_COUNT (1U) + +/*! @name COMMON_SETTRIG - Set Trigger control bits for all DMA channels. */ +/*! @{ */ +#define DMA_COMMON_SETTRIG_TRIG_MASK (0xFFFFFFFFU) +#define DMA_COMMON_SETTRIG_TRIG_SHIFT (0U) +#define DMA_COMMON_SETTRIG_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_TRIG_SHIFT)) & DMA_COMMON_SETTRIG_TRIG_MASK) +/*! @} */ + +/* The count of DMA_COMMON_SETTRIG */ +#define DMA_COMMON_SETTRIG_COUNT (1U) + +/*! @name COMMON_ABORT - Channel Abort control for all DMA channels. */ +/*! @{ */ +#define DMA_COMMON_ABORT_ABORTCTRL_MASK (0xFFFFFFFFU) +#define DMA_COMMON_ABORT_ABORTCTRL_SHIFT (0U) +#define DMA_COMMON_ABORT_ABORTCTRL(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORTCTRL_SHIFT)) & DMA_COMMON_ABORT_ABORTCTRL_MASK) +/*! @} */ + +/* The count of DMA_COMMON_ABORT */ +#define DMA_COMMON_ABORT_COUNT (1U) + +/*! @name CHANNEL_CFG - Configuration register for DMA channel . */ +/*! @{ */ +#define DMA_CHANNEL_CFG_PERIPHREQEN_MASK (0x1U) +#define DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT (0U) +/*! PERIPHREQEN - Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory + * move, any peripheral DMA request associated with that channel can be disabled to prevent any + * interaction between the peripheral and the DMA controller. + * 0b0..Disabled. Peripheral DMA requests are disabled. + * 0b1..Enabled. Peripheral DMA requests are enabled. + */ +#define DMA_CHANNEL_CFG_PERIPHREQEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT)) & DMA_CHANNEL_CFG_PERIPHREQEN_MASK) +#define DMA_CHANNEL_CFG_HWTRIGEN_MASK (0x2U) +#define DMA_CHANNEL_CFG_HWTRIGEN_SHIFT (1U) +/*! HWTRIGEN - Hardware Triggering Enable for this channel. + * 0b0..Disabled. Hardware triggering is not used. + * 0b1..Enabled. Use hardware triggering. + */ +#define DMA_CHANNEL_CFG_HWTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_HWTRIGEN_SHIFT)) & DMA_CHANNEL_CFG_HWTRIGEN_MASK) +#define DMA_CHANNEL_CFG_TRIGPOL_MASK (0x10U) +#define DMA_CHANNEL_CFG_TRIGPOL_SHIFT (4U) +/*! TRIGPOL - Trigger Polarity. Selects the polarity of a hardware trigger for this channel. + * 0b0..Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE. + * 0b1..Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE. + */ +#define DMA_CHANNEL_CFG_TRIGPOL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGPOL_SHIFT)) & DMA_CHANNEL_CFG_TRIGPOL_MASK) +#define DMA_CHANNEL_CFG_TRIGTYPE_MASK (0x20U) +#define DMA_CHANNEL_CFG_TRIGTYPE_SHIFT (5U) +/*! TRIGTYPE - Trigger Type. Selects hardware trigger as edge triggered or level triggered. + * 0b0..Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger. + * 0b1..Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = + * 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the + * trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger + * is, again, asserted. However, the transfer will not be paused until any remaining transfers within the + * current BURSTPOWER length are completed. + */ +#define DMA_CHANNEL_CFG_TRIGTYPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGTYPE_SHIFT)) & DMA_CHANNEL_CFG_TRIGTYPE_MASK) +#define DMA_CHANNEL_CFG_TRIGBURST_MASK (0x40U) +#define DMA_CHANNEL_CFG_TRIGBURST_SHIFT (6U) +/*! TRIGBURST - Trigger Burst. Selects whether hardware triggers cause a single or burst transfer. + * 0b0..Single transfer. Hardware trigger causes a single transfer. + * 0b1..Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a + * burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a + * hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is + * complete. + */ +#define DMA_CHANNEL_CFG_TRIGBURST(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGBURST_SHIFT)) & DMA_CHANNEL_CFG_TRIGBURST_MASK) +#define DMA_CHANNEL_CFG_BURSTPOWER_MASK (0xF00U) +#define DMA_CHANNEL_CFG_BURSTPOWER_SHIFT (8U) +#define DMA_CHANNEL_CFG_BURSTPOWER(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_BURSTPOWER_SHIFT)) & DMA_CHANNEL_CFG_BURSTPOWER_MASK) +#define DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK (0x4000U) +#define DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT (14U) +/*! SRCBURSTWRAP - Source Burst Wrap. When enabled, the source data address for the DMA is + * 'wrapped', meaning that the source address range for each burst will be the same. As an example, this + * could be used to read several sequential registers from a peripheral for each DMA burst, + * reading the same registers again for each burst. + * 0b0..Disabled. Source burst wrapping is not enabled for this DMA channel. + * 0b1..Enabled. Source burst wrapping is enabled for this DMA channel. + */ +#define DMA_CHANNEL_CFG_SRCBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK) +#define DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK (0x8000U) +#define DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT (15U) +/*! DSTBURSTWRAP - Destination Burst Wrap. When enabled, the destination data address for the DMA is + * 'wrapped', meaning that the destination address range for each burst will be the same. As an + * example, this could be used to write several sequential registers to a peripheral for each DMA + * burst, writing the same registers again for each burst. + * 0b0..Disabled. Destination burst wrapping is not enabled for this DMA channel. + * 0b1..Enabled. Destination burst wrapping is enabled for this DMA channel. + */ +#define DMA_CHANNEL_CFG_DSTBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK) +#define DMA_CHANNEL_CFG_CHPRIORITY_MASK (0x70000U) +#define DMA_CHANNEL_CFG_CHPRIORITY_SHIFT (16U) +#define DMA_CHANNEL_CFG_CHPRIORITY(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_CHPRIORITY_SHIFT)) & DMA_CHANNEL_CFG_CHPRIORITY_MASK) +/*! @} */ + +/* The count of DMA_CHANNEL_CFG */ +#define DMA_CHANNEL_CFG_COUNT (30U) + +/*! @name CHANNEL_CTLSTAT - Control and status register for DMA channel . */ +/*! @{ */ +#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK (0x1U) +#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT (0U) +/*! VALIDPENDING - Valid pending flag for this channel. This bit is set when a 1 is written to the + * corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel. + * 0b0..No effect. No effect on DMA operation. + * 0b1..Valid pending. + */ +#define DMA_CHANNEL_CTLSTAT_VALIDPENDING(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT)) & DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK) +#define DMA_CHANNEL_CTLSTAT_TRIG_MASK (0x4U) +#define DMA_CHANNEL_CTLSTAT_TRIG_SHIFT (2U) +/*! TRIG - Trigger flag. Indicates that the trigger for this channel is currently set. This bit is + * cleared at the end of an entire transfer or upon reload when CLRTRIG = 1. + * 0b0..Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out. + * 0b1..Triggered. The trigger for this DMA channel is set. DMA operations will be carried out. + */ +#define DMA_CHANNEL_CTLSTAT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_TRIG_SHIFT)) & DMA_CHANNEL_CTLSTAT_TRIG_MASK) +/*! @} */ + +/* The count of DMA_CHANNEL_CTLSTAT */ +#define DMA_CHANNEL_CTLSTAT_COUNT (30U) + +/*! @name CHANNEL_XFERCFG - Transfer configuration register for DMA channel . */ +/*! @{ */ +#define DMA_CHANNEL_XFERCFG_CFGVALID_MASK (0x1U) +#define DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT (0U) +/*! CFGVALID - Configuration Valid flag. This bit indicates whether the current channel descriptor + * is valid and can potentially be acted upon, if all other activation criteria are fulfilled. + * 0b0..Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting. + * 0b1..Valid. The current channel descriptor is considered valid. + */ +#define DMA_CHANNEL_XFERCFG_CFGVALID(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT)) & DMA_CHANNEL_XFERCFG_CFGVALID_MASK) +#define DMA_CHANNEL_XFERCFG_RELOAD_MASK (0x2U) +#define DMA_CHANNEL_XFERCFG_RELOAD_SHIFT (1U) +/*! RELOAD - Indicates whether the channel's control structure will be reloaded when the current + * descriptor is exhausted. Reloading allows ping-pong and linked transfers. + * 0b0..Disabled. Do not reload the channels' control structure when the current descriptor is exhausted. + * 0b1..Enabled. Reload the channels' control structure when the current descriptor is exhausted. + */ +#define DMA_CHANNEL_XFERCFG_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_RELOAD_SHIFT)) & DMA_CHANNEL_XFERCFG_RELOAD_MASK) +#define DMA_CHANNEL_XFERCFG_SWTRIG_MASK (0x4U) +#define DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT (2U) +/*! SWTRIG - Software Trigger. + * 0b0..Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by + * the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel. + * 0b1..Set. When written by software, the trigger for this channel is set immediately. This feature should not + * be used with level triggering when TRIGBURST = 0. + */ +#define DMA_CHANNEL_XFERCFG_SWTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_SWTRIG_MASK) +#define DMA_CHANNEL_XFERCFG_CLRTRIG_MASK (0x8U) +#define DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT (3U) +/*! CLRTRIG - Clear Trigger. + * 0b0..Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started. + * 0b1..Cleared. The trigger is cleared when this descriptor is exhausted + */ +#define DMA_CHANNEL_XFERCFG_CLRTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_CLRTRIG_MASK) +#define DMA_CHANNEL_XFERCFG_SETINTA_MASK (0x10U) +#define DMA_CHANNEL_XFERCFG_SETINTA_SHIFT (4U) +/*! SETINTA - Set Interrupt flag A for this channel. There is no hardware distinction between + * interrupt A and B. They can be used by software to assist with more complex descriptor usage. By + * convention, interrupt A may be used when only one interrupt flag is needed. + * 0b0..No effect. + * 0b1..Set. The INTA flag for this channel will be set when the current descriptor is exhausted. + */ +#define DMA_CHANNEL_XFERCFG_SETINTA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTA_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTA_MASK) +#define DMA_CHANNEL_XFERCFG_SETINTB_MASK (0x20U) +#define DMA_CHANNEL_XFERCFG_SETINTB_SHIFT (5U) +/*! SETINTB - Set Interrupt flag B for this channel. There is no hardware distinction between + * interrupt A and B. They can be used by software to assist with more complex descriptor usage. By + * convention, interrupt A may be used when only one interrupt flag is needed. + * 0b0..No effect. + * 0b1..Set. The INTB flag for this channel will be set when the current descriptor is exhausted. + */ +#define DMA_CHANNEL_XFERCFG_SETINTB(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTB_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTB_MASK) +#define DMA_CHANNEL_XFERCFG_WIDTH_MASK (0x300U) +#define DMA_CHANNEL_XFERCFG_WIDTH_SHIFT (8U) +/*! WIDTH - Transfer width used for this DMA channel. + * 0b00..8-bit. 8-bit transfers are performed (8-bit source reads and destination writes). + * 0b01..16-bit. 6-bit transfers are performed (16-bit source reads and destination writes). + * 0b10..32-bit. 32-bit transfers are performed (32-bit source reads and destination writes). + * 0b11..Reserved. Reserved setting, do not use. + */ +#define DMA_CHANNEL_XFERCFG_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_WIDTH_SHIFT)) & DMA_CHANNEL_XFERCFG_WIDTH_MASK) +#define DMA_CHANNEL_XFERCFG_SRCINC_MASK (0x3000U) +#define DMA_CHANNEL_XFERCFG_SRCINC_SHIFT (12U) +/*! SRCINC - Determines whether the source address is incremented for each DMA transfer. + * 0b00..No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device. + * 0b01..1 x width. The source address is incremented by the amount specified by Width for each transfer. This is + * the usual case when the source is memory. + * 0b10..2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer. + * 0b11..4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer. + */ +#define DMA_CHANNEL_XFERCFG_SRCINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SRCINC_SHIFT)) & DMA_CHANNEL_XFERCFG_SRCINC_MASK) +#define DMA_CHANNEL_XFERCFG_DSTINC_MASK (0xC000U) +#define DMA_CHANNEL_XFERCFG_DSTINC_SHIFT (14U) +/*! DSTINC - Determines whether the destination address is incremented for each DMA transfer. + * 0b00..No increment. The destination address is not incremented for each transfer. This is the usual case when + * the destination is a peripheral device. + * 0b01..1 x width. The destination address is incremented by the amount specified by Width for each transfer. + * This is the usual case when the destination is memory. + * 0b10..2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer. + * 0b11..4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer. + */ +#define DMA_CHANNEL_XFERCFG_DSTINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_DSTINC_SHIFT)) & DMA_CHANNEL_XFERCFG_DSTINC_MASK) +#define DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK (0x3FF0000U) +#define DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT (16U) +#define DMA_CHANNEL_XFERCFG_XFERCOUNT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT)) & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) +/*! @} */ + +/* The count of DMA_CHANNEL_XFERCFG */ +#define DMA_CHANNEL_XFERCFG_COUNT (30U) + + +/*! + * @} + */ /* end of group DMA_Register_Masks */ + + +/* DMA - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral DMA0 base address */ + #define DMA0_BASE (0x50082000u) + /** Peripheral DMA0 base address */ + #define DMA0_BASE_NS (0x40082000u) + /** Peripheral DMA0 base pointer */ + #define DMA0 ((DMA_Type *)DMA0_BASE) + /** Peripheral DMA0 base pointer */ + #define DMA0_NS ((DMA_Type *)DMA0_BASE_NS) + /** Peripheral DMA1 base address */ + #define DMA1_BASE (0x500A7000u) + /** Peripheral DMA1 base address */ + #define DMA1_BASE_NS (0x400A7000u) + /** Peripheral DMA1 base pointer */ + #define DMA1 ((DMA_Type *)DMA1_BASE) + /** Peripheral DMA1 base pointer */ + #define DMA1_NS ((DMA_Type *)DMA1_BASE_NS) + /** Array initializer of DMA peripheral base addresses */ + #define DMA_BASE_ADDRS { DMA0_BASE, DMA1_BASE } + /** Array initializer of DMA peripheral base pointers */ + #define DMA_BASE_PTRS { DMA0, DMA1 } + /** Array initializer of DMA peripheral base addresses */ + #define DMA_BASE_ADDRS_NS { DMA0_BASE_NS, DMA1_BASE_NS } + /** Array initializer of DMA peripheral base pointers */ + #define DMA_BASE_PTRS_NS { DMA0_NS, DMA1_NS } +#else + /** Peripheral DMA0 base address */ + #define DMA0_BASE (0x40082000u) + /** Peripheral DMA0 base pointer */ + #define DMA0 ((DMA_Type *)DMA0_BASE) + /** Peripheral DMA1 base address */ + #define DMA1_BASE (0x400A7000u) + /** Peripheral DMA1 base pointer */ + #define DMA1 ((DMA_Type *)DMA1_BASE) + /** Array initializer of DMA peripheral base addresses */ + #define DMA_BASE_ADDRS { DMA0_BASE, DMA1_BASE } + /** Array initializer of DMA peripheral base pointers */ + #define DMA_BASE_PTRS { DMA0, DMA1 } +#endif +/** Interrupt vectors for the DMA peripheral type */ +#define DMA_IRQS { DMA0_IRQn, DMA1_IRQn } + +/*! + * @} + */ /* end of group DMA_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FLASH Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLASH_Peripheral_Access_Layer FLASH Peripheral Access Layer + * @{ + */ + +/** FLASH - Register Layout Typedef */ +typedef struct { + __O uint32_t CMD; /**< command register, offset: 0x0 */ + __O uint32_t EVENT; /**< event register, offset: 0x4 */ + __IO uint32_t BURST; /**< read burst register, offset: 0x8 */ + uint8_t RESERVED_0[4]; + __IO uint32_t STARTA; /**< start (or only) address for next flash command, offset: 0x10 */ + __IO uint32_t STOPA; /**< end address for next flash command, if command operates on address ranges, offset: 0x14 */ + uint8_t RESERVED_1[104]; + __IO uint32_t DATAW[8]; /**< data register, word 0-7; Memory data, or command parameter, or command result., array offset: 0x80, array step: 0x4 */ + uint8_t RESERVED_2[3896]; + __O uint32_t INT_CLR_ENABLE; /**< Clear interrupt enable bits, offset: 0xFD8 */ + __O uint32_t INT_SET_ENABLE; /**< Set interrupt enable bits, offset: 0xFDC */ + __I uint32_t INT_STATUS; /**< Interrupt status bits, offset: 0xFE0 */ + __I uint32_t INT_ENABLE; /**< Interrupt enable bits, offset: 0xFE4 */ + __O uint32_t INT_CLR_STATUS; /**< Clear interrupt status bits, offset: 0xFE8 */ + __O uint32_t INT_SET_STATUS; /**< Set interrupt status bits, offset: 0xFEC */ + uint8_t RESERVED_3[12]; + __I uint32_t MODULE_ID; /**< Controller+Memory module identification, offset: 0xFFC */ +} FLASH_Type; + +/* ---------------------------------------------------------------------------- + -- FLASH Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLASH_Register_Masks FLASH Register Masks + * @{ + */ + +/*! @name CMD - command register */ +/*! @{ */ +#define FLASH_CMD_CMD_MASK (0xFFFFFFFFU) +#define FLASH_CMD_CMD_SHIFT (0U) +#define FLASH_CMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMD_CMD_SHIFT)) & FLASH_CMD_CMD_MASK) +/*! @} */ + +/*! @name EVENT - event register */ +/*! @{ */ +#define FLASH_EVENT_RST_MASK (0x1U) +#define FLASH_EVENT_RST_SHIFT (0U) +#define FLASH_EVENT_RST(x) (((uint32_t)(((uint32_t)(x)) << FLASH_EVENT_RST_SHIFT)) & FLASH_EVENT_RST_MASK) +#define FLASH_EVENT_WAKEUP_MASK (0x2U) +#define FLASH_EVENT_WAKEUP_SHIFT (1U) +#define FLASH_EVENT_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << FLASH_EVENT_WAKEUP_SHIFT)) & FLASH_EVENT_WAKEUP_MASK) +#define FLASH_EVENT_ABORT_MASK (0x4U) +#define FLASH_EVENT_ABORT_SHIFT (2U) +#define FLASH_EVENT_ABORT(x) (((uint32_t)(((uint32_t)(x)) << FLASH_EVENT_ABORT_SHIFT)) & FLASH_EVENT_ABORT_MASK) +/*! @} */ + +/*! @name BURST - read burst register */ +/*! @{ */ +#define FLASH_BURST_XOR_MASK_MASK (0xFFFFFU) +#define FLASH_BURST_XOR_MASK_SHIFT (0U) +#define FLASH_BURST_XOR_MASK(x) (((uint32_t)(((uint32_t)(x)) << FLASH_BURST_XOR_MASK_SHIFT)) & FLASH_BURST_XOR_MASK_MASK) +#define FLASH_BURST_DESCR1_MASK (0xF00000U) +#define FLASH_BURST_DESCR1_SHIFT (20U) +#define FLASH_BURST_DESCR1(x) (((uint32_t)(((uint32_t)(x)) << FLASH_BURST_DESCR1_SHIFT)) & FLASH_BURST_DESCR1_MASK) +#define FLASH_BURST_DESCR2_MASK (0xF000000U) +#define FLASH_BURST_DESCR2_SHIFT (24U) +#define FLASH_BURST_DESCR2(x) (((uint32_t)(((uint32_t)(x)) << FLASH_BURST_DESCR2_SHIFT)) & FLASH_BURST_DESCR2_MASK) +#define FLASH_BURST_DESCR3_MASK (0xF0000000U) +#define FLASH_BURST_DESCR3_SHIFT (28U) +#define FLASH_BURST_DESCR3(x) (((uint32_t)(((uint32_t)(x)) << FLASH_BURST_DESCR3_SHIFT)) & FLASH_BURST_DESCR3_MASK) +/*! @} */ + +/*! @name STARTA - start (or only) address for next flash command */ +/*! @{ */ +#define FLASH_STARTA_STARTA_MASK (0x3FFFFU) +#define FLASH_STARTA_STARTA_SHIFT (0U) +#define FLASH_STARTA_STARTA(x) (((uint32_t)(((uint32_t)(x)) << FLASH_STARTA_STARTA_SHIFT)) & FLASH_STARTA_STARTA_MASK) +/*! @} */ + +/*! @name STOPA - end address for next flash command, if command operates on address ranges */ +/*! @{ */ +#define FLASH_STOPA_STOPA_MASK (0x3FFFFU) +#define FLASH_STOPA_STOPA_SHIFT (0U) +#define FLASH_STOPA_STOPA(x) (((uint32_t)(((uint32_t)(x)) << FLASH_STOPA_STOPA_SHIFT)) & FLASH_STOPA_STOPA_MASK) +/*! @} */ + +/*! @name DATAW - data register, word 0-7; Memory data, or command parameter, or command result. */ +/*! @{ */ +#define FLASH_DATAW_DATAW_MASK (0xFFFFFFFFU) +#define FLASH_DATAW_DATAW_SHIFT (0U) +#define FLASH_DATAW_DATAW(x) (((uint32_t)(((uint32_t)(x)) << FLASH_DATAW_DATAW_SHIFT)) & FLASH_DATAW_DATAW_MASK) +/*! @} */ + +/* The count of FLASH_DATAW */ +#define FLASH_DATAW_COUNT (8U) + +/*! @name INT_CLR_ENABLE - Clear interrupt enable bits */ +/*! @{ */ +#define FLASH_INT_CLR_ENABLE_FAIL_MASK (0x1U) +#define FLASH_INT_CLR_ENABLE_FAIL_SHIFT (0U) +#define FLASH_INT_CLR_ENABLE_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_FAIL_SHIFT)) & FLASH_INT_CLR_ENABLE_FAIL_MASK) +#define FLASH_INT_CLR_ENABLE_ERR_MASK (0x2U) +#define FLASH_INT_CLR_ENABLE_ERR_SHIFT (1U) +#define FLASH_INT_CLR_ENABLE_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_ERR_SHIFT)) & FLASH_INT_CLR_ENABLE_ERR_MASK) +#define FLASH_INT_CLR_ENABLE_DONE_MASK (0x4U) +#define FLASH_INT_CLR_ENABLE_DONE_SHIFT (2U) +#define FLASH_INT_CLR_ENABLE_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_DONE_SHIFT)) & FLASH_INT_CLR_ENABLE_DONE_MASK) +#define FLASH_INT_CLR_ENABLE_ECC_ERR_MASK (0x8U) +#define FLASH_INT_CLR_ENABLE_ECC_ERR_SHIFT (3U) +#define FLASH_INT_CLR_ENABLE_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_ECC_ERR_SHIFT)) & FLASH_INT_CLR_ENABLE_ECC_ERR_MASK) +/*! @} */ + +/*! @name INT_SET_ENABLE - Set interrupt enable bits */ +/*! @{ */ +#define FLASH_INT_SET_ENABLE_FAIL_MASK (0x1U) +#define FLASH_INT_SET_ENABLE_FAIL_SHIFT (0U) +#define FLASH_INT_SET_ENABLE_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_FAIL_SHIFT)) & FLASH_INT_SET_ENABLE_FAIL_MASK) +#define FLASH_INT_SET_ENABLE_ERR_MASK (0x2U) +#define FLASH_INT_SET_ENABLE_ERR_SHIFT (1U) +#define FLASH_INT_SET_ENABLE_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_ERR_SHIFT)) & FLASH_INT_SET_ENABLE_ERR_MASK) +#define FLASH_INT_SET_ENABLE_DONE_MASK (0x4U) +#define FLASH_INT_SET_ENABLE_DONE_SHIFT (2U) +#define FLASH_INT_SET_ENABLE_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_DONE_SHIFT)) & FLASH_INT_SET_ENABLE_DONE_MASK) +#define FLASH_INT_SET_ENABLE_ECC_ERR_MASK (0x8U) +#define FLASH_INT_SET_ENABLE_ECC_ERR_SHIFT (3U) +#define FLASH_INT_SET_ENABLE_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_ECC_ERR_SHIFT)) & FLASH_INT_SET_ENABLE_ECC_ERR_MASK) +/*! @} */ + +/*! @name INT_STATUS - Interrupt status bits */ +/*! @{ */ +#define FLASH_INT_STATUS_FAIL_MASK (0x1U) +#define FLASH_INT_STATUS_FAIL_SHIFT (0U) +#define FLASH_INT_STATUS_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_FAIL_SHIFT)) & FLASH_INT_STATUS_FAIL_MASK) +#define FLASH_INT_STATUS_ERR_MASK (0x2U) +#define FLASH_INT_STATUS_ERR_SHIFT (1U) +#define FLASH_INT_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_ERR_SHIFT)) & FLASH_INT_STATUS_ERR_MASK) +#define FLASH_INT_STATUS_DONE_MASK (0x4U) +#define FLASH_INT_STATUS_DONE_SHIFT (2U) +#define FLASH_INT_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_DONE_SHIFT)) & FLASH_INT_STATUS_DONE_MASK) +#define FLASH_INT_STATUS_ECC_ERR_MASK (0x8U) +#define FLASH_INT_STATUS_ECC_ERR_SHIFT (3U) +#define FLASH_INT_STATUS_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_ECC_ERR_SHIFT)) & FLASH_INT_STATUS_ECC_ERR_MASK) +/*! @} */ + +/*! @name INT_ENABLE - Interrupt enable bits */ +/*! @{ */ +#define FLASH_INT_ENABLE_FAIL_MASK (0x1U) +#define FLASH_INT_ENABLE_FAIL_SHIFT (0U) +#define FLASH_INT_ENABLE_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_FAIL_SHIFT)) & FLASH_INT_ENABLE_FAIL_MASK) +#define FLASH_INT_ENABLE_ERR_MASK (0x2U) +#define FLASH_INT_ENABLE_ERR_SHIFT (1U) +#define FLASH_INT_ENABLE_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_ERR_SHIFT)) & FLASH_INT_ENABLE_ERR_MASK) +#define FLASH_INT_ENABLE_DONE_MASK (0x4U) +#define FLASH_INT_ENABLE_DONE_SHIFT (2U) +#define FLASH_INT_ENABLE_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_DONE_SHIFT)) & FLASH_INT_ENABLE_DONE_MASK) +#define FLASH_INT_ENABLE_ECC_ERR_MASK (0x8U) +#define FLASH_INT_ENABLE_ECC_ERR_SHIFT (3U) +#define FLASH_INT_ENABLE_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_ECC_ERR_SHIFT)) & FLASH_INT_ENABLE_ECC_ERR_MASK) +/*! @} */ + +/*! @name INT_CLR_STATUS - Clear interrupt status bits */ +/*! @{ */ +#define FLASH_INT_CLR_STATUS_FAIL_MASK (0x1U) +#define FLASH_INT_CLR_STATUS_FAIL_SHIFT (0U) +#define FLASH_INT_CLR_STATUS_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_FAIL_SHIFT)) & FLASH_INT_CLR_STATUS_FAIL_MASK) +#define FLASH_INT_CLR_STATUS_ERR_MASK (0x2U) +#define FLASH_INT_CLR_STATUS_ERR_SHIFT (1U) +#define FLASH_INT_CLR_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_ERR_SHIFT)) & FLASH_INT_CLR_STATUS_ERR_MASK) +#define FLASH_INT_CLR_STATUS_DONE_MASK (0x4U) +#define FLASH_INT_CLR_STATUS_DONE_SHIFT (2U) +#define FLASH_INT_CLR_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_DONE_SHIFT)) & FLASH_INT_CLR_STATUS_DONE_MASK) +#define FLASH_INT_CLR_STATUS_ECC_ERR_MASK (0x8U) +#define FLASH_INT_CLR_STATUS_ECC_ERR_SHIFT (3U) +#define FLASH_INT_CLR_STATUS_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_ECC_ERR_SHIFT)) & FLASH_INT_CLR_STATUS_ECC_ERR_MASK) +/*! @} */ + +/*! @name INT_SET_STATUS - Set interrupt status bits */ +/*! @{ */ +#define FLASH_INT_SET_STATUS_FAIL_MASK (0x1U) +#define FLASH_INT_SET_STATUS_FAIL_SHIFT (0U) +#define FLASH_INT_SET_STATUS_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_FAIL_SHIFT)) & FLASH_INT_SET_STATUS_FAIL_MASK) +#define FLASH_INT_SET_STATUS_ERR_MASK (0x2U) +#define FLASH_INT_SET_STATUS_ERR_SHIFT (1U) +#define FLASH_INT_SET_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_ERR_SHIFT)) & FLASH_INT_SET_STATUS_ERR_MASK) +#define FLASH_INT_SET_STATUS_DONE_MASK (0x4U) +#define FLASH_INT_SET_STATUS_DONE_SHIFT (2U) +#define FLASH_INT_SET_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_DONE_SHIFT)) & FLASH_INT_SET_STATUS_DONE_MASK) +#define FLASH_INT_SET_STATUS_ECC_ERR_MASK (0x8U) +#define FLASH_INT_SET_STATUS_ECC_ERR_SHIFT (3U) +#define FLASH_INT_SET_STATUS_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_ECC_ERR_SHIFT)) & FLASH_INT_SET_STATUS_ECC_ERR_MASK) +/*! @} */ + +/*! @name MODULE_ID - Controller+Memory module identification */ +/*! @{ */ +#define FLASH_MODULE_ID_APERTURE_MASK (0xFFU) +#define FLASH_MODULE_ID_APERTURE_SHIFT (0U) +#define FLASH_MODULE_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_APERTURE_SHIFT)) & FLASH_MODULE_ID_APERTURE_MASK) +#define FLASH_MODULE_ID_MINOR_REV_MASK (0xF00U) +#define FLASH_MODULE_ID_MINOR_REV_SHIFT (8U) +#define FLASH_MODULE_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_MINOR_REV_SHIFT)) & FLASH_MODULE_ID_MINOR_REV_MASK) +#define FLASH_MODULE_ID_MAJOR_REV_MASK (0xF000U) +#define FLASH_MODULE_ID_MAJOR_REV_SHIFT (12U) +#define FLASH_MODULE_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_MAJOR_REV_SHIFT)) & FLASH_MODULE_ID_MAJOR_REV_MASK) +#define FLASH_MODULE_ID_ID_MASK (0xFFFF0000U) +#define FLASH_MODULE_ID_ID_SHIFT (16U) +#define FLASH_MODULE_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_ID_SHIFT)) & FLASH_MODULE_ID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group FLASH_Register_Masks */ + + +/* FLASH - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral FLASH base address */ + #define FLASH_BASE (0x50034000u) + /** Peripheral FLASH base address */ + #define FLASH_BASE_NS (0x40034000u) + /** Peripheral FLASH base pointer */ + #define FLASH ((FLASH_Type *)FLASH_BASE) + /** Peripheral FLASH base pointer */ + #define FLASH_NS ((FLASH_Type *)FLASH_BASE_NS) + /** Array initializer of FLASH peripheral base addresses */ + #define FLASH_BASE_ADDRS { FLASH_BASE } + /** Array initializer of FLASH peripheral base pointers */ + #define FLASH_BASE_PTRS { FLASH } + /** Array initializer of FLASH peripheral base addresses */ + #define FLASH_BASE_ADDRS_NS { FLASH_BASE_NS } + /** Array initializer of FLASH peripheral base pointers */ + #define FLASH_BASE_PTRS_NS { FLASH_NS } +#else + /** Peripheral FLASH base address */ + #define FLASH_BASE (0x40034000u) + /** Peripheral FLASH base pointer */ + #define FLASH ((FLASH_Type *)FLASH_BASE) + /** Array initializer of FLASH peripheral base addresses */ + #define FLASH_BASE_ADDRS { FLASH_BASE } + /** Array initializer of FLASH peripheral base pointers */ + #define FLASH_BASE_PTRS { FLASH } +#endif + +/*! + * @} + */ /* end of group FLASH_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FLASH_CFPA Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLASH_CFPA_Peripheral_Access_Layer FLASH_CFPA Peripheral Access Layer + * @{ + */ + +/** FLASH_CFPA - Register Layout Typedef */ +typedef struct { + __IO uint32_t HEADER; /**< ., offset: 0x0 */ + __IO uint32_t VERSION; /**< ., offset: 0x4 */ + __IO uint32_t S_FW_VERSION; /**< Secure firmware version (Monotonic counter), offset: 0x8 */ + __IO uint32_t NS_FW_VERSION; /**< Non-Secure firmware version (Monotonic counter), offset: 0xC */ + __IO uint32_t IMAGE_KEY_REVOKE; /**< Image key revocation ID (Monotonic counter), offset: 0x10 */ + uint8_t RESERVED_0[4]; + __IO uint32_t ROTKH_REVOKE; /**< ., offset: 0x18 */ + __IO uint32_t VENDOR_USAGE; /**< ., offset: 0x1C */ + __IO uint32_t DCFG_CC_SOCU_PIN; /**< With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access., offset: 0x20 */ + __IO uint32_t DCFG_CC_SOCU_DFLT; /**< With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access., offset: 0x24 */ + __IO uint32_t ENABLE_FA_MODE; /**< Enable FA mode. SET_FA_MODE Command should write 0xC33CA55A to this word to indicate boot ROM to enter FA mode., offset: 0x28 */ + __IO uint32_t CMPA_PROG_IN_PROGRESS; /**< CMPA Page programming on going. This field shall be set to 0x5CC55AA5 in the active CFPA page each time CMPA page programming is going on. It shall always be set to 0x00000000 in the CFPA scratch area., offset: 0x2C */ + union { /* offset: 0x30 */ + __IO uint32_t PRINCE_REGION0_IV_CODE[14]; /**< ., array offset: 0x30, array step: 0x4 */ + struct { /* offset: 0x30 */ + __IO uint32_t PRINCE_REGION0_IV_HEADER0; /**< ., offset: 0x30 */ + __IO uint32_t PRINCE_REGION0_IV_HEADER1; /**< ., offset: 0x34 */ + __IO uint32_t PRINCE_REGION0_IV_BODY[12]; /**< ., array offset: 0x38, array step: 0x4 */ + } PRINCE_REGION0_IV_CODE_CORE; + }; + union { /* offset: 0x68 */ + __IO uint32_t PRINCE_REGION1_IV_CODE[14]; /**< ., array offset: 0x68, array step: 0x4 */ + struct { /* offset: 0x68 */ + __IO uint32_t PRINCE_REGION1_IV_HEADER0; /**< ., offset: 0x68 */ + __IO uint32_t PRINCE_REGION1_IV_HEADER1; /**< ., offset: 0x6C */ + __IO uint32_t PRINCE_REGION1_IV_BODY[12]; /**< ., array offset: 0x70, array step: 0x4 */ + } PRINCE_REGION1_IV_CODE_CORE; + }; + union { /* offset: 0xA0 */ + __IO uint32_t PRINCE_REGION2_IV_CODE[14]; /**< ., array offset: 0xA0, array step: 0x4 */ + struct { /* offset: 0xA0 */ + __IO uint32_t PRINCE_REGION2_IV_HEADER0; /**< ., offset: 0xA0 */ + __IO uint32_t PRINCE_REGION2_IV_HEADER1; /**< ., offset: 0xA4 */ + __IO uint32_t PRINCE_REGION2_IV_BODY[12]; /**< ., array offset: 0xA8, array step: 0x4 */ + } PRINCE_REGION2_IV_CODE_CORE; + }; + uint8_t RESERVED_1[40]; + __IO uint32_t CUSTOMER_DEFINED[56]; /**< Customer Defined (Programable through ROM API), array offset: 0x100, array step: 0x4 */ + __IO uint32_t SHA256_DIGEST[8]; /**< SHA256_DIGEST0 for DIGEST[31:0] SHA256_DIGEST1 for DIGEST[63:32] SHA256_DIGEST2 for DIGEST[95:64] SHA256_DIGEST3 for DIGEST[127:96] SHA256_DIGEST4 for DIGEST[159:128] SHA256_DIGEST5 for DIGEST[191:160] SHA256_DIGEST6 for DIGEST[223:192] SHA256_DIGEST7 for DIGEST[255:224], array offset: 0x1E0, array step: 0x4 */ +} FLASH_CFPA_Type; + +/* ---------------------------------------------------------------------------- + -- FLASH_CFPA Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLASH_CFPA_Register_Masks FLASH_CFPA Register Masks + * @{ + */ + +/*! @name HEADER - . */ +/*! @{ */ +#define FLASH_CFPA_HEADER_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_HEADER_FIELD_SHIFT (0U) +#define FLASH_CFPA_HEADER_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_HEADER_FIELD_SHIFT)) & FLASH_CFPA_HEADER_FIELD_MASK) +/*! @} */ + +/*! @name VERSION - . */ +/*! @{ */ +#define FLASH_CFPA_VERSION_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_VERSION_FIELD_SHIFT (0U) +#define FLASH_CFPA_VERSION_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_VERSION_FIELD_SHIFT)) & FLASH_CFPA_VERSION_FIELD_MASK) +/*! @} */ + +/*! @name S_FW_VERSION - Secure firmware version (Monotonic counter) */ +/*! @{ */ +#define FLASH_CFPA_S_FW_VERSION_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_S_FW_VERSION_FIELD_SHIFT (0U) +#define FLASH_CFPA_S_FW_VERSION_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_S_FW_VERSION_FIELD_SHIFT)) & FLASH_CFPA_S_FW_VERSION_FIELD_MASK) +/*! @} */ + +/*! @name NS_FW_VERSION - Non-Secure firmware version (Monotonic counter) */ +/*! @{ */ +#define FLASH_CFPA_NS_FW_VERSION_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_NS_FW_VERSION_FIELD_SHIFT (0U) +#define FLASH_CFPA_NS_FW_VERSION_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_NS_FW_VERSION_FIELD_SHIFT)) & FLASH_CFPA_NS_FW_VERSION_FIELD_MASK) +/*! @} */ + +/*! @name IMAGE_KEY_REVOKE - Image key revocation ID (Monotonic counter) */ +/*! @{ */ +#define FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_SHIFT (0U) +#define FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_SHIFT)) & FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_MASK) +/*! @} */ + +/*! @name ROTKH_REVOKE - . */ +/*! @{ */ +#define FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_MASK (0x3U) +#define FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_SHIFT (0U) +#define FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_SHIFT)) & FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_MASK) +#define FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_MASK (0xCU) +#define FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_SHIFT (2U) +#define FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_SHIFT)) & FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_MASK) +#define FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_MASK (0x30U) +#define FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_SHIFT (4U) +#define FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_SHIFT)) & FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_MASK) +/*! @} */ + +/*! @name VENDOR_USAGE - . */ +/*! @{ */ +#define FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_MASK (0xFFFFU) +#define FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_SHIFT (0U) +#define FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_SHIFT)) & FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_MASK) +#define FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE_MASK (0xFFFF0000U) +#define FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE_SHIFT (16U) +#define FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE_SHIFT)) & FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE_MASK) +/*! @} */ + +/*! @name DCFG_CC_SOCU_PIN - With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access. */ +/*! @{ */ +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_MASK (0x1U) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_SHIFT (0U) +/*! NIDEN - Non Secure non-invasive debug enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_MASK) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_MASK (0x2U) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_SHIFT (1U) +/*! DBGEN - Non Secure debug enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_MASK) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN_MASK (0x4U) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN_SHIFT (2U) +/*! SPNIDEN - Secure non-invasive debug enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN_MASK) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_MASK (0x8U) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_SHIFT (3U) +/*! SPIDEN - Secure invasive debug enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_MASK) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_MASK (0x10U) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_SHIFT (4U) +/*! TAPEN - JTAG TAP enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_MASK) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_MCM33_DBGEN_MASK (0x20U) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_MCM33_DBGEN_SHIFT (5U) +/*! MCM33_DBGEN - Micro CM33 invasive debug enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_MCM33_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_MCM33_DBGEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_MCM33_DBGEN_MASK) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_MASK (0x40U) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_SHIFT (6U) +/*! ISP_CMD_EN - ISP Boot Command enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_MASK) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_MASK (0x80U) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_SHIFT (7U) +/*! FA_CMD_EN - FA Command enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_MASK) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_MASK (0x100U) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_SHIFT (8U) +/*! ME_CMD_EN - Flash Mass Erase Command enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_ME_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_MASK) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_MCM33_NIDEN_MASK (0x200U) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_MCM33_NIDEN_SHIFT (9U) +/*! MCM33_NIDEN - Micro CM33 non-invasive debug enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_MCM33_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_MCM33_NIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_MCM33_NIDEN_MASK) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK_MASK (0x8000U) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK_SHIFT (15U) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK_MASK) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_MASK (0xFFFF0000U) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_SHIFT (16U) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_MASK) +/*! @} */ + +/*! @name DCFG_CC_SOCU_DFLT - With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access. */ +/*! @{ */ +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_MASK (0x1U) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_SHIFT (0U) +/*! NIDEN - Non Secure non-invasive debug fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_MASK) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_MASK (0x2U) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_SHIFT (1U) +/*! DBGEN - Non Secure debug fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_MASK) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN_MASK (0x4U) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN_SHIFT (2U) +/*! SPNIDEN - Secure non-invasive debug fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN_MASK) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN_MASK (0x8U) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN_SHIFT (3U) +/*! SPIDEN - Secure invasive debug fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN_MASK) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_MASK (0x10U) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_SHIFT (4U) +/*! TAPEN - JTAG TAP fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_MASK) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_MCM33_DBGEN_MASK (0x20U) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_MCM33_DBGEN_SHIFT (5U) +/*! MCM33_DBGEN - Micro CM33 invasive debug fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_MCM33_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_MCM33_DBGEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_MCM33_DBGEN_MASK) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_MASK (0x40U) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT (6U) +/*! ISP_CMD_EN - ISP Boot Command fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_MASK) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_MASK (0x80U) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_SHIFT (7U) +/*! FA_CMD_EN - FA Command fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_MASK) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_MASK (0x100U) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_SHIFT (8U) +/*! ME_CMD_EN - Flash Mass Erase Command fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_MASK) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_MCM33_NIDEN_MASK (0x200U) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_MCM33_NIDEN_SHIFT (9U) +/*! MCM33_NIDEN - Micro CM33 non-invasive debug fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_MCM33_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_MCM33_NIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_MCM33_NIDEN_MASK) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_MASK (0xFFFF0000U) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT (16U) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_MASK) +/*! @} */ + +/*! @name ENABLE_FA_MODE - Enable FA mode. SET_FA_MODE Command should write 0xC33CA55A to this word to indicate boot ROM to enter FA mode. */ +/*! @{ */ +#define FLASH_CFPA_ENABLE_FA_MODE_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_ENABLE_FA_MODE_FIELD_SHIFT (0U) +#define FLASH_CFPA_ENABLE_FA_MODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ENABLE_FA_MODE_FIELD_SHIFT)) & FLASH_CFPA_ENABLE_FA_MODE_FIELD_MASK) +/*! @} */ + +/*! @name CMPA_PROG_IN_PROGRESS - CMPA Page programming on going. This field shall be set to 0x5CC55AA5 in the active CFPA page each time CMPA page programming is going on. It shall always be set to 0x00000000 in the CFPA scratch area. */ +/*! @{ */ +#define FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_SHIFT (0U) +#define FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_SHIFT)) & FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_MASK) +/*! @} */ + +/*! @name PRINCE_REGION0_IV_CODE - . */ +/*! @{ */ +#define FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_SHIFT (0U) +#define FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_CFPA_PRINCE_REGION0_IV_CODE */ +#define FLASH_CFPA_PRINCE_REGION0_IV_CODE_COUNT (14U) + +/*! @name PRINCE_REGION0_IV_HEADER0 - . */ +/*! @{ */ +#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_SHIFT (0U) +#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_MASK) +/*! @} */ + +/*! @name PRINCE_REGION0_IV_HEADER1 - . */ +/*! @{ */ +#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_MASK (0x3U) +#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_SHIFT (0U) +#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_MASK) +#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_MASK (0xF00U) +#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_SHIFT (8U) +#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_MASK) +#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_MASK (0x3F000000U) +#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_SHIFT (24U) +#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_MASK) +/*! @} */ + +/*! @name PRINCE_REGION0_IV_BODY - . */ +/*! @{ */ +#define FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_SHIFT (0U) +#define FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_CFPA_PRINCE_REGION0_IV_BODY */ +#define FLASH_CFPA_PRINCE_REGION0_IV_BODY_COUNT (12U) + +/*! @name PRINCE_REGION1_IV_CODE - . */ +/*! @{ */ +#define FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_SHIFT (0U) +#define FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_CFPA_PRINCE_REGION1_IV_CODE */ +#define FLASH_CFPA_PRINCE_REGION1_IV_CODE_COUNT (14U) + +/*! @name PRINCE_REGION1_IV_HEADER0 - . */ +/*! @{ */ +#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_SHIFT (0U) +#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_MASK) +/*! @} */ + +/*! @name PRINCE_REGION1_IV_HEADER1 - . */ +/*! @{ */ +#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_MASK (0x3U) +#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_SHIFT (0U) +#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_MASK) +#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_MASK (0xF00U) +#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_SHIFT (8U) +#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_MASK) +#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_MASK (0x3F000000U) +#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_SHIFT (24U) +#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_MASK) +/*! @} */ + +/*! @name PRINCE_REGION1_IV_BODY - . */ +/*! @{ */ +#define FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_SHIFT (0U) +#define FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_CFPA_PRINCE_REGION1_IV_BODY */ +#define FLASH_CFPA_PRINCE_REGION1_IV_BODY_COUNT (12U) + +/*! @name PRINCE_REGION2_IV_CODE - . */ +/*! @{ */ +#define FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_SHIFT (0U) +#define FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_CFPA_PRINCE_REGION2_IV_CODE */ +#define FLASH_CFPA_PRINCE_REGION2_IV_CODE_COUNT (14U) + +/*! @name PRINCE_REGION2_IV_HEADER0 - . */ +/*! @{ */ +#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_SHIFT (0U) +#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_MASK) +/*! @} */ + +/*! @name PRINCE_REGION2_IV_HEADER1 - . */ +/*! @{ */ +#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_MASK (0x3U) +#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_SHIFT (0U) +#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_MASK) +#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_MASK (0xF00U) +#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_SHIFT (8U) +#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_MASK) +#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_MASK (0x3F000000U) +#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_SHIFT (24U) +#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_MASK) +/*! @} */ + +/*! @name PRINCE_REGION2_IV_BODY - . */ +/*! @{ */ +#define FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_SHIFT (0U) +#define FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_CFPA_PRINCE_REGION2_IV_BODY */ +#define FLASH_CFPA_PRINCE_REGION2_IV_BODY_COUNT (12U) + +/*! @name CUSTOMER_DEFINED - Customer Defined (Programable through ROM API) */ +/*! @{ */ +#define FLASH_CFPA_CUSTOMER_DEFINED_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_CUSTOMER_DEFINED_FIELD_SHIFT (0U) +#define FLASH_CFPA_CUSTOMER_DEFINED_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_CUSTOMER_DEFINED_FIELD_SHIFT)) & FLASH_CFPA_CUSTOMER_DEFINED_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_CFPA_CUSTOMER_DEFINED */ +#define FLASH_CFPA_CUSTOMER_DEFINED_COUNT (56U) + +/*! @name SHA256_DIGEST - SHA256_DIGEST0 for DIGEST[31:0] SHA256_DIGEST1 for DIGEST[63:32] SHA256_DIGEST2 for DIGEST[95:64] SHA256_DIGEST3 for DIGEST[127:96] SHA256_DIGEST4 for DIGEST[159:128] SHA256_DIGEST5 for DIGEST[191:160] SHA256_DIGEST6 for DIGEST[223:192] SHA256_DIGEST7 for DIGEST[255:224] */ +/*! @{ */ +#define FLASH_CFPA_SHA256_DIGEST_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_SHA256_DIGEST_FIELD_SHIFT (0U) +#define FLASH_CFPA_SHA256_DIGEST_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_SHA256_DIGEST_FIELD_SHIFT)) & FLASH_CFPA_SHA256_DIGEST_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_CFPA_SHA256_DIGEST */ +#define FLASH_CFPA_SHA256_DIGEST_COUNT (8U) + + +/*! + * @} + */ /* end of group FLASH_CFPA_Register_Masks */ + + +/* FLASH_CFPA - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral FLASH_CFPA0 base address */ + #define FLASH_CFPA0_BASE (0x1009E000u) + /** Peripheral FLASH_CFPA0 base address */ + #define FLASH_CFPA0_BASE_NS (0x9E000u) + /** Peripheral FLASH_CFPA0 base pointer */ + #define FLASH_CFPA0 ((FLASH_CFPA_Type *)FLASH_CFPA0_BASE) + /** Peripheral FLASH_CFPA0 base pointer */ + #define FLASH_CFPA0_NS ((FLASH_CFPA_Type *)FLASH_CFPA0_BASE_NS) + /** Peripheral FLASH_CFPA1 base address */ + #define FLASH_CFPA1_BASE (0x1009E200u) + /** Peripheral FLASH_CFPA1 base address */ + #define FLASH_CFPA1_BASE_NS (0x9E200u) + /** Peripheral FLASH_CFPA1 base pointer */ + #define FLASH_CFPA1 ((FLASH_CFPA_Type *)FLASH_CFPA1_BASE) + /** Peripheral FLASH_CFPA1 base pointer */ + #define FLASH_CFPA1_NS ((FLASH_CFPA_Type *)FLASH_CFPA1_BASE_NS) + /** Peripheral FLASH_CFPA_SCRATCH base address */ + #define FLASH_CFPA_SCRATCH_BASE (0x1009DE00u) + /** Peripheral FLASH_CFPA_SCRATCH base address */ + #define FLASH_CFPA_SCRATCH_BASE_NS (0x9DE00u) + /** Peripheral FLASH_CFPA_SCRATCH base pointer */ + #define FLASH_CFPA_SCRATCH ((FLASH_CFPA_Type *)FLASH_CFPA_SCRATCH_BASE) + /** Peripheral FLASH_CFPA_SCRATCH base pointer */ + #define FLASH_CFPA_SCRATCH_NS ((FLASH_CFPA_Type *)FLASH_CFPA_SCRATCH_BASE_NS) + /** Array initializer of FLASH_CFPA peripheral base addresses */ + #define FLASH_CFPA_BASE_ADDRS { FLASH_CFPA0_BASE, FLASH_CFPA1_BASE, FLASH_CFPA_SCRATCH_BASE } + /** Array initializer of FLASH_CFPA peripheral base pointers */ + #define FLASH_CFPA_BASE_PTRS { FLASH_CFPA0, FLASH_CFPA1, FLASH_CFPA_SCRATCH } + /** Array initializer of FLASH_CFPA peripheral base addresses */ + #define FLASH_CFPA_BASE_ADDRS_NS { FLASH_CFPA0_BASE_NS, FLASH_CFPA1_BASE_NS, FLASH_CFPA_SCRATCH_BASE_NS } + /** Array initializer of FLASH_CFPA peripheral base pointers */ + #define FLASH_CFPA_BASE_PTRS_NS { FLASH_CFPA0_NS, FLASH_CFPA1_NS, FLASH_CFPA_SCRATCH_NS } +#else + /** Peripheral FLASH_CFPA0 base address */ + #define FLASH_CFPA0_BASE (0x9E000u) + /** Peripheral FLASH_CFPA0 base pointer */ + #define FLASH_CFPA0 ((FLASH_CFPA_Type *)FLASH_CFPA0_BASE) + /** Peripheral FLASH_CFPA1 base address */ + #define FLASH_CFPA1_BASE (0x9E200u) + /** Peripheral FLASH_CFPA1 base pointer */ + #define FLASH_CFPA1 ((FLASH_CFPA_Type *)FLASH_CFPA1_BASE) + /** Peripheral FLASH_CFPA_SCRATCH base address */ + #define FLASH_CFPA_SCRATCH_BASE (0x9DE00u) + /** Peripheral FLASH_CFPA_SCRATCH base pointer */ + #define FLASH_CFPA_SCRATCH ((FLASH_CFPA_Type *)FLASH_CFPA_SCRATCH_BASE) + /** Array initializer of FLASH_CFPA peripheral base addresses */ + #define FLASH_CFPA_BASE_ADDRS { FLASH_CFPA0_BASE, FLASH_CFPA1_BASE, FLASH_CFPA_SCRATCH_BASE } + /** Array initializer of FLASH_CFPA peripheral base pointers */ + #define FLASH_CFPA_BASE_PTRS { FLASH_CFPA0, FLASH_CFPA1, FLASH_CFPA_SCRATCH } +#endif + +/*! + * @} + */ /* end of group FLASH_CFPA_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FLASH_CMPA Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLASH_CMPA_Peripheral_Access_Layer FLASH_CMPA Peripheral Access Layer + * @{ + */ + +/** FLASH_CMPA - Register Layout Typedef */ +typedef struct { + __IO uint32_t BOOT_CFG; /**< ., offset: 0x0 */ + __IO uint32_t SPI_FLASH_CFG; /**< ., offset: 0x4 */ + __IO uint32_t USB_ID; /**< ., offset: 0x8 */ + __IO uint32_t SDIO_CFG; /**< ., offset: 0xC */ + __IO uint32_t DCFG_CC_SOCU_PIN; /**< ., offset: 0x10 */ + __IO uint32_t DCFG_CC_SOCU_DFLT; /**< ., offset: 0x14 */ + __IO uint32_t DAP_VENDOR_USAGE_FIXED; /**< ., offset: 0x18 */ + __IO uint32_t SECURE_BOOT_CFG; /**< ., offset: 0x1C */ + __IO uint32_t PRINCE_BASE_ADDR; /**< ., offset: 0x20 */ + __IO uint32_t PRINCE_SR_0; /**< Region 0, sub-region enable, offset: 0x24 */ + __IO uint32_t PRINCE_SR_1; /**< Region 1, sub-region enable, offset: 0x28 */ + __IO uint32_t PRINCE_SR_2; /**< Region 2, sub-region enable, offset: 0x2C */ + uint8_t RESERVED_0[32]; + __IO uint32_t ROTKH[8]; /**< ROTKH0 for Root of Trust Keys Table hash[255:224] ROTKH1 for Root of Trust Keys Table hash[223:192] ROTKH2 for Root of Trust Keys Table hash[191:160] ROTKH3 for Root of Trust Keys Table hash[159:128] ROTKH4 for Root of Trust Keys Table hash[127:96] ROTKH5 for Root of Trust Keys Table hash[95:64] ROTKH6 for Root of Trust Keys Table hash[63:32] ROTKH7 for Root of Trust Keys Table hash[31:0], array offset: 0x50, array step: 0x4 */ + uint8_t RESERVED_1[144]; + __IO uint32_t CUSTOMER_DEFINED[56]; /**< Customer Defined (Programable through ROM API), array offset: 0x100, array step: 0x4 */ + __IO uint32_t SHA256_DIGEST[8]; /**< SHA256_DIGEST0 for DIGEST[31:0] SHA256_DIGEST1 for DIGEST[63:32] SHA256_DIGEST2 for DIGEST[95:64] SHA256_DIGEST3 for DIGEST[127:96] SHA256_DIGEST4 for DIGEST[159:128] SHA256_DIGEST5 for DIGEST[191:160] SHA256_DIGEST6 for DIGEST[223:192] SHA256_DIGEST7 for DIGEST[255:224], array offset: 0x1E0, array step: 0x4 */ +} FLASH_CMPA_Type; + +/* ---------------------------------------------------------------------------- + -- FLASH_CMPA Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLASH_CMPA_Register_Masks FLASH_CMPA Register Masks + * @{ + */ + +/*! @name BOOT_CFG - . */ +/*! @{ */ +#define FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_MASK (0x70U) +#define FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_SHIFT (4U) +/*! DEFAULT_ISP_MODE - Default ISP mode: + * 0b000..Auto ISP + * 0b001..USB_HID_MSC + * 0b010..SPI Slave ISP + * 0b011..I2C Slave ISP + * 0b111..Disable ISP fall through + */ +#define FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_SHIFT)) & FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_MASK) +#define FLASH_CMPA_BOOT_CFG_BOOT_SPEED_MASK (0x180U) +#define FLASH_CMPA_BOOT_CFG_BOOT_SPEED_SHIFT (7U) +/*! BOOT_SPEED - Core clock: + * 0b00..Defined by NMPA.SYSTEM_SPEED_CODE + * 0b01..48MHz FRO + * 0b10..96MHz FRO + */ +#define FLASH_CMPA_BOOT_CFG_BOOT_SPEED(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_BOOT_CFG_BOOT_SPEED_SHIFT)) & FLASH_CMPA_BOOT_CFG_BOOT_SPEED_MASK) +#define FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_MASK (0xFF000000U) +#define FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_SHIFT (24U) +#define FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_SHIFT)) & FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_MASK) +/*! @} */ + +/*! @name SPI_FLASH_CFG - . */ +/*! @{ */ +#define FLASH_CMPA_SPI_FLASH_CFG_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CMPA_SPI_FLASH_CFG_FIELD_SHIFT (0U) +#define FLASH_CMPA_SPI_FLASH_CFG_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SPI_FLASH_CFG_FIELD_SHIFT)) & FLASH_CMPA_SPI_FLASH_CFG_FIELD_MASK) +/*! @} */ + +/*! @name USB_ID - . */ +/*! @{ */ +#define FLASH_CMPA_USB_ID_USB_VENDOR_ID_MASK (0xFFFFU) +#define FLASH_CMPA_USB_ID_USB_VENDOR_ID_SHIFT (0U) +#define FLASH_CMPA_USB_ID_USB_VENDOR_ID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_USB_ID_USB_VENDOR_ID_SHIFT)) & FLASH_CMPA_USB_ID_USB_VENDOR_ID_MASK) +#define FLASH_CMPA_USB_ID_USB_PRODUCT_ID_MASK (0xFFFF0000U) +#define FLASH_CMPA_USB_ID_USB_PRODUCT_ID_SHIFT (16U) +#define FLASH_CMPA_USB_ID_USB_PRODUCT_ID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_USB_ID_USB_PRODUCT_ID_SHIFT)) & FLASH_CMPA_USB_ID_USB_PRODUCT_ID_MASK) +/*! @} */ + +/*! @name SDIO_CFG - . */ +/*! @{ */ +#define FLASH_CMPA_SDIO_CFG_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CMPA_SDIO_CFG_FIELD_SHIFT (0U) +#define FLASH_CMPA_SDIO_CFG_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SDIO_CFG_FIELD_SHIFT)) & FLASH_CMPA_SDIO_CFG_FIELD_MASK) +/*! @} */ + +/*! @name DCFG_CC_SOCU_PIN - . */ +/*! @{ */ +#define FLASH_CMPA_DCFG_CC_SOCU_PIN_NIDEN_MASK (0x1U) +#define FLASH_CMPA_DCFG_CC_SOCU_PIN_NIDEN_SHIFT (0U) +/*! NIDEN - Non Secure non-invasive debug enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CMPA_DCFG_CC_SOCU_PIN_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_PIN_NIDEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_PIN_NIDEN_MASK) +#define FLASH_CMPA_DCFG_CC_SOCU_PIN_DBGEN_MASK (0x2U) +#define FLASH_CMPA_DCFG_CC_SOCU_PIN_DBGEN_SHIFT (1U) +/*! DBGEN - Non Secure debug enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CMPA_DCFG_CC_SOCU_PIN_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_PIN_DBGEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_PIN_DBGEN_MASK) +#define FLASH_CMPA_DCFG_CC_SOCU_PIN_SPNIDEN_MASK (0x4U) +#define FLASH_CMPA_DCFG_CC_SOCU_PIN_SPNIDEN_SHIFT (2U) +/*! SPNIDEN - Secure non-invasive debug enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CMPA_DCFG_CC_SOCU_PIN_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_PIN_SPNIDEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_PIN_SPNIDEN_MASK) +#define FLASH_CMPA_DCFG_CC_SOCU_PIN_SPIDEN_MASK (0x8U) +#define FLASH_CMPA_DCFG_CC_SOCU_PIN_SPIDEN_SHIFT (3U) +/*! SPIDEN - Secure invasive debug enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CMPA_DCFG_CC_SOCU_PIN_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_PIN_SPIDEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_PIN_SPIDEN_MASK) +#define FLASH_CMPA_DCFG_CC_SOCU_PIN_TAPEN_MASK (0x10U) +#define FLASH_CMPA_DCFG_CC_SOCU_PIN_TAPEN_SHIFT (4U) +/*! TAPEN - JTAG TAP enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CMPA_DCFG_CC_SOCU_PIN_TAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_PIN_TAPEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_PIN_TAPEN_MASK) +#define FLASH_CMPA_DCFG_CC_SOCU_PIN_MCM33_DBGEN_MASK (0x20U) +#define FLASH_CMPA_DCFG_CC_SOCU_PIN_MCM33_DBGEN_SHIFT (5U) +/*! MCM33_DBGEN - Micro CM33 invasive debug enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CMPA_DCFG_CC_SOCU_PIN_MCM33_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_PIN_MCM33_DBGEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_PIN_MCM33_DBGEN_MASK) +#define FLASH_CMPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_MASK (0x40U) +#define FLASH_CMPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_SHIFT (6U) +/*! ISP_CMD_EN - ISP Boot Command enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CMPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_MASK) +#define FLASH_CMPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_MASK (0x80U) +#define FLASH_CMPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_SHIFT (7U) +/*! FA_CMD_EN - FA Command enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CMPA_DCFG_CC_SOCU_PIN_FA_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_MASK) +#define FLASH_CMPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_MASK (0x100U) +#define FLASH_CMPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_SHIFT (8U) +/*! ME_CMD_EN - Flash Mass Erase Command enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CMPA_DCFG_CC_SOCU_PIN_ME_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_MASK) +#define FLASH_CMPA_DCFG_CC_SOCU_PIN_MCM33_NIDEN_MASK (0x200U) +#define FLASH_CMPA_DCFG_CC_SOCU_PIN_MCM33_NIDEN_SHIFT (9U) +/*! MCM33_NIDEN - Micro CM33 non-invasive debug enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CMPA_DCFG_CC_SOCU_PIN_MCM33_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_PIN_MCM33_NIDEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_PIN_MCM33_NIDEN_MASK) +#define FLASH_CMPA_DCFG_CC_SOCU_PIN_UUID_CHECK_MASK (0x8000U) +#define FLASH_CMPA_DCFG_CC_SOCU_PIN_UUID_CHECK_SHIFT (15U) +#define FLASH_CMPA_DCFG_CC_SOCU_PIN_UUID_CHECK(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_PIN_UUID_CHECK_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_PIN_UUID_CHECK_MASK) +#define FLASH_CMPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_MASK (0xFFFF0000U) +#define FLASH_CMPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_SHIFT (16U) +#define FLASH_CMPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_MASK) +/*! @} */ + +/*! @name DCFG_CC_SOCU_DFLT - . */ +/*! @{ */ +#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_NIDEN_MASK (0x1U) +#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_NIDEN_SHIFT (0U) +/*! NIDEN - Non Secure non-invasive debug fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_DFLT_NIDEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_DFLT_NIDEN_MASK) +#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_DBGEN_MASK (0x2U) +#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_DBGEN_SHIFT (1U) +/*! DBGEN - Non Secure debug fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_DFLT_DBGEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_DFLT_DBGEN_MASK) +#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_SPNIDEN_MASK (0x4U) +#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_SPNIDEN_SHIFT (2U) +/*! SPNIDEN - Secure non-invasive debug fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_DFLT_SPNIDEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_DFLT_SPNIDEN_MASK) +#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_SPIDEN_MASK (0x8U) +#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_SPIDEN_SHIFT (3U) +/*! SPIDEN - Secure invasive debug fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_DFLT_SPIDEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_DFLT_SPIDEN_MASK) +#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_TAPEN_MASK (0x10U) +#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_TAPEN_SHIFT (4U) +/*! TAPEN - JTAG TAP fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_TAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_DFLT_TAPEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_DFLT_TAPEN_MASK) +#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_MCM33_DBGEN_MASK (0x20U) +#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_MCM33_DBGEN_SHIFT (5U) +/*! MCM33_DBGEN - Micro CM33 invasive debug fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_MCM33_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_DFLT_MCM33_DBGEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_DFLT_MCM33_DBGEN_MASK) +#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_MASK (0x40U) +#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT (6U) +/*! ISP_CMD_EN - ISP Boot Command fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_MASK) +#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_MASK (0x80U) +#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_SHIFT (7U) +/*! FA_CMD_EN - FA Command fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_MASK) +#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_MASK (0x100U) +#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_SHIFT (8U) +/*! ME_CMD_EN - Flash Mass Erase Command fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_MASK) +#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_MCM33_NIDEN_MASK (0x200U) +#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_MCM33_NIDEN_SHIFT (9U) +/*! MCM33_NIDEN - Micro CM33 non-invasive debug fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_MCM33_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_DFLT_MCM33_NIDEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_DFLT_MCM33_NIDEN_MASK) +#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_MASK (0xFFFF0000U) +#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT (16U) +#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_MASK) +/*! @} */ + +/*! @name DAP_VENDOR_USAGE_FIXED - . */ +/*! @{ */ +#define FLASH_CMPA_DAP_VENDOR_USAGE_FIXED_VENDOR_USAGE_MASK (0xFFFF0000U) +#define FLASH_CMPA_DAP_VENDOR_USAGE_FIXED_VENDOR_USAGE_SHIFT (16U) +#define FLASH_CMPA_DAP_VENDOR_USAGE_FIXED_VENDOR_USAGE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DAP_VENDOR_USAGE_FIXED_VENDOR_USAGE_SHIFT)) & FLASH_CMPA_DAP_VENDOR_USAGE_FIXED_VENDOR_USAGE_MASK) +/*! @} */ + +/*! @name SECURE_BOOT_CFG - . */ +/*! @{ */ +#define FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_MASK (0x3U) +#define FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_SHIFT (0U) +#define FLASH_CMPA_SECURE_BOOT_CFG_RSA4K(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_MASK) +#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_ENC_NXP_CFG_MASK (0xCU) +#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_ENC_NXP_CFG_SHIFT (2U) +#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_ENC_NXP_CFG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_DICE_ENC_NXP_CFG_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_DICE_ENC_NXP_CFG_MASK) +#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_MASK (0x30U) +#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_SHIFT (4U) +#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_MASK) +#define FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_MASK (0xC0U) +#define FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_SHIFT (6U) +#define FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_MASK) +#define FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_MASK (0x300U) +#define FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_SHIFT (8U) +#define FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_MASK) +#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_MASK (0xC00U) +#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_SHIFT (10U) +#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_MASK) +#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_MASK (0x3000U) +#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_SHIFT (12U) +#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_MASK) +#define FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_MASK (0xC0000000U) +#define FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_SHIFT (30U) +#define FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_MASK) +/*! @} */ + +/*! @name PRINCE_BASE_ADDR - . */ +/*! @{ */ +#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_MASK (0xFU) +#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_SHIFT (0U) +#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_MASK) +#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_MASK (0xF0U) +#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_SHIFT (4U) +#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_MASK) +#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_MASK (0xF00U) +#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_SHIFT (8U) +#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_MASK) +#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_MASK (0x30000U) +#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_SHIFT (16U) +#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_MASK) +#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_MASK (0xC0000U) +#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_SHIFT (18U) +#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_MASK) +#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG2_MASK (0x300000U) +#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG2_SHIFT (20U) +#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG2(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG2_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG2_MASK) +#define FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_MASK (0x3000000U) +#define FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_SHIFT (24U) +#define FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_MASK) +#define FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_MASK (0xC000000U) +#define FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_SHIFT (26U) +#define FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_MASK) +#define FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_MASK (0x30000000U) +#define FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_SHIFT (28U) +#define FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_MASK) +/*! @} */ + +/*! @name PRINCE_SR_0 - Region 0, sub-region enable */ +/*! @{ */ +#define FLASH_CMPA_PRINCE_SR_0_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CMPA_PRINCE_SR_0_FIELD_SHIFT (0U) +#define FLASH_CMPA_PRINCE_SR_0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_SR_0_FIELD_SHIFT)) & FLASH_CMPA_PRINCE_SR_0_FIELD_MASK) +/*! @} */ + +/*! @name PRINCE_SR_1 - Region 1, sub-region enable */ +/*! @{ */ +#define FLASH_CMPA_PRINCE_SR_1_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CMPA_PRINCE_SR_1_FIELD_SHIFT (0U) +#define FLASH_CMPA_PRINCE_SR_1_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_SR_1_FIELD_SHIFT)) & FLASH_CMPA_PRINCE_SR_1_FIELD_MASK) +/*! @} */ + +/*! @name PRINCE_SR_2 - Region 2, sub-region enable */ +/*! @{ */ +#define FLASH_CMPA_PRINCE_SR_2_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CMPA_PRINCE_SR_2_FIELD_SHIFT (0U) +#define FLASH_CMPA_PRINCE_SR_2_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_SR_2_FIELD_SHIFT)) & FLASH_CMPA_PRINCE_SR_2_FIELD_MASK) +/*! @} */ + +/*! @name ROTKH - ROTKH0 for Root of Trust Keys Table hash[255:224] ROTKH1 for Root of Trust Keys Table hash[223:192] ROTKH2 for Root of Trust Keys Table hash[191:160] ROTKH3 for Root of Trust Keys Table hash[159:128] ROTKH4 for Root of Trust Keys Table hash[127:96] ROTKH5 for Root of Trust Keys Table hash[95:64] ROTKH6 for Root of Trust Keys Table hash[63:32] ROTKH7 for Root of Trust Keys Table hash[31:0] */ +/*! @{ */ +#define FLASH_CMPA_ROTKH_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CMPA_ROTKH_FIELD_SHIFT (0U) +#define FLASH_CMPA_ROTKH_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_ROTKH_FIELD_SHIFT)) & FLASH_CMPA_ROTKH_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_CMPA_ROTKH */ +#define FLASH_CMPA_ROTKH_COUNT (8U) + +/*! @name CUSTOMER_DEFINED - Customer Defined (Programable through ROM API) */ +/*! @{ */ +#define FLASH_CMPA_CUSTOMER_DEFINED_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CMPA_CUSTOMER_DEFINED_FIELD_SHIFT (0U) +#define FLASH_CMPA_CUSTOMER_DEFINED_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CUSTOMER_DEFINED_FIELD_SHIFT)) & FLASH_CMPA_CUSTOMER_DEFINED_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_CMPA_CUSTOMER_DEFINED */ +#define FLASH_CMPA_CUSTOMER_DEFINED_COUNT (56U) + +/*! @name SHA256_DIGEST - SHA256_DIGEST0 for DIGEST[31:0] SHA256_DIGEST1 for DIGEST[63:32] SHA256_DIGEST2 for DIGEST[95:64] SHA256_DIGEST3 for DIGEST[127:96] SHA256_DIGEST4 for DIGEST[159:128] SHA256_DIGEST5 for DIGEST[191:160] SHA256_DIGEST6 for DIGEST[223:192] SHA256_DIGEST7 for DIGEST[255:224] */ +/*! @{ */ +#define FLASH_CMPA_SHA256_DIGEST_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CMPA_SHA256_DIGEST_FIELD_SHIFT (0U) +#define FLASH_CMPA_SHA256_DIGEST_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SHA256_DIGEST_FIELD_SHIFT)) & FLASH_CMPA_SHA256_DIGEST_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_CMPA_SHA256_DIGEST */ +#define FLASH_CMPA_SHA256_DIGEST_COUNT (8U) + + +/*! + * @} + */ /* end of group FLASH_CMPA_Register_Masks */ + + +/* FLASH_CMPA - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral FLASH_CMPA base address */ + #define FLASH_CMPA_BASE (0x1009E400u) + /** Peripheral FLASH_CMPA base address */ + #define FLASH_CMPA_BASE_NS (0x9E400u) + /** Peripheral FLASH_CMPA base pointer */ + #define FLASH_CMPA ((FLASH_CMPA_Type *)FLASH_CMPA_BASE) + /** Peripheral FLASH_CMPA base pointer */ + #define FLASH_CMPA_NS ((FLASH_CMPA_Type *)FLASH_CMPA_BASE_NS) + /** Array initializer of FLASH_CMPA peripheral base addresses */ + #define FLASH_CMPA_BASE_ADDRS { FLASH_CMPA_BASE } + /** Array initializer of FLASH_CMPA peripheral base pointers */ + #define FLASH_CMPA_BASE_PTRS { FLASH_CMPA } + /** Array initializer of FLASH_CMPA peripheral base addresses */ + #define FLASH_CMPA_BASE_ADDRS_NS { FLASH_CMPA_BASE_NS } + /** Array initializer of FLASH_CMPA peripheral base pointers */ + #define FLASH_CMPA_BASE_PTRS_NS { FLASH_CMPA_NS } +#else + /** Peripheral FLASH_CMPA base address */ + #define FLASH_CMPA_BASE (0x9E400u) + /** Peripheral FLASH_CMPA base pointer */ + #define FLASH_CMPA ((FLASH_CMPA_Type *)FLASH_CMPA_BASE) + /** Array initializer of FLASH_CMPA peripheral base addresses */ + #define FLASH_CMPA_BASE_ADDRS { FLASH_CMPA_BASE } + /** Array initializer of FLASH_CMPA peripheral base pointers */ + #define FLASH_CMPA_BASE_PTRS { FLASH_CMPA } +#endif + +/*! + * @} + */ /* end of group FLASH_CMPA_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FLASH_KEY_STORE Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLASH_KEY_STORE_Peripheral_Access_Layer FLASH_KEY_STORE Peripheral Access Layer + * @{ + */ + +/** FLASH_KEY_STORE - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0 */ + __IO uint32_t HEADER; /**< Valid Key Sore Header : 0x95959595, offset: 0x0 */ + __IO uint32_t PUF_DISCHARGE_TIME_IN_MS; /**< puf discharge time in ms., offset: 0x4 */ + } KEY_STORE_HEADER; + __IO uint32_t ACTIVATION_CODE[298]; /**< ., array offset: 0x8, array step: 0x4 */ + union { /* offset: 0x4B0 */ + __IO uint32_t SBKEY_KEY_CODE[14]; /**< ., array offset: 0x4B0, array step: 0x4 */ + struct { /* offset: 0x4B0 */ + __IO uint32_t SBKEY_HEADER0; /**< ., offset: 0x4B0 */ + __IO uint32_t SBKEY_HEADER1; /**< ., offset: 0x4B4 */ + __IO uint32_t SBKEY_BODY[12]; /**< ., array offset: 0x4B8, array step: 0x4 */ + } SBKEY_KEY_CODE_CORE; + }; + union { /* offset: 0x4E8 */ + __IO uint32_t USER_KEK_KEY_CODE[14]; /**< ., array offset: 0x4E8, array step: 0x4 */ + struct { /* offset: 0x4E8 */ + __IO uint32_t USER_KEK_HEADER0; /**< ., offset: 0x4E8 */ + __IO uint32_t USER_KEK_HEADER1; /**< ., offset: 0x4EC */ + __IO uint32_t USER_KEK_BODY[12]; /**< ., array offset: 0x4F0, array step: 0x4 */ + } USER_KEK_KEY_CODE_CORE; + }; + union { /* offset: 0x520 */ + __IO uint32_t UDS_KEY_CODE[14]; /**< ., array offset: 0x520, array step: 0x4 */ + struct { /* offset: 0x520 */ + __IO uint32_t UDS_HEADER0; /**< ., offset: 0x520 */ + __IO uint32_t UDS_HEADER1; /**< ., offset: 0x524 */ + __IO uint32_t UDS_BODY[12]; /**< ., array offset: 0x528, array step: 0x4 */ + } UDS_KEY_CODE_CORE; + }; + union { /* offset: 0x558 */ + __IO uint32_t PRINCE_REGION0_KEY_CODE[14]; /**< ., array offset: 0x558, array step: 0x4 */ + struct { /* offset: 0x558 */ + __IO uint32_t PRINCE_REGION0_HEADER0; /**< ., offset: 0x558 */ + __IO uint32_t PRINCE_REGION0_HEADER1; /**< ., offset: 0x55C */ + __IO uint32_t PRINCE_REGION0_BODY[12]; /**< ., array offset: 0x560, array step: 0x4 */ + } PRINCE_REGION0_KEY_CODE_CORE; + }; + union { /* offset: 0x590 */ + __IO uint32_t PRINCE_REGION1_KEY_CODE[14]; /**< ., array offset: 0x590, array step: 0x4 */ + struct { /* offset: 0x590 */ + __IO uint32_t PRINCE_REGION1_HEADER0; /**< ., offset: 0x590 */ + __IO uint32_t PRINCE_REGION1_HEADER1; /**< ., offset: 0x594 */ + __IO uint32_t PRINCE_REGION1_BODY[12]; /**< ., array offset: 0x598, array step: 0x4 */ + } PRINCE_REGION1_KEY_CODE_CORE; + }; + union { /* offset: 0x5C8 */ + __IO uint32_t PRINCE_REGION2_KEY_CODE[14]; /**< ., array offset: 0x5C8, array step: 0x4 */ + struct { /* offset: 0x5C8 */ + __IO uint32_t PRINCE_REGION2_HEADER0; /**< ., offset: 0x5C8 */ + __IO uint32_t PRINCE_REGION2_HEADER1; /**< ., offset: 0x5CC */ + __IO uint32_t PRINCE_REGION2_BODY[12]; /**< ., array offset: 0x5D0, array step: 0x4 */ + } PRINCE_REGION2_KEY_CODE_CORE; + }; +} FLASH_KEY_STORE_Type; + +/* ---------------------------------------------------------------------------- + -- FLASH_KEY_STORE Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLASH_KEY_STORE_Register_Masks FLASH_KEY_STORE Register Masks + * @{ + */ + +/*! @name HEADER - Valid Key Sore Header : 0x95959595 */ +/*! @{ */ +#define FLASH_KEY_STORE_HEADER_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_HEADER_FIELD_SHIFT (0U) +#define FLASH_KEY_STORE_HEADER_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_HEADER_FIELD_SHIFT)) & FLASH_KEY_STORE_HEADER_FIELD_MASK) +/*! @} */ + +/*! @name PUF_DISCHARGE_TIME_IN_MS - puf discharge time in ms. */ +/*! @{ */ +#define FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD_SHIFT (0U) +#define FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD_SHIFT)) & FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD_MASK) +/*! @} */ + +/*! @name ACTIVATION_CODE - . */ +/*! @{ */ +#define FLASH_KEY_STORE_ACTIVATION_CODE_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_ACTIVATION_CODE_FIELD_SHIFT (0U) +#define FLASH_KEY_STORE_ACTIVATION_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_ACTIVATION_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_ACTIVATION_CODE_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_KEY_STORE_ACTIVATION_CODE */ +#define FLASH_KEY_STORE_ACTIVATION_CODE_COUNT (298U) + +/*! @name SBKEY_KEY_CODE - . */ +/*! @{ */ +#define FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD_SHIFT (0U) +#define FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_KEY_STORE_SBKEY_KEY_CODE */ +#define FLASH_KEY_STORE_SBKEY_KEY_CODE_COUNT (14U) + +/*! @name SBKEY_HEADER0 - . */ +/*! @{ */ +#define FLASH_KEY_STORE_SBKEY_HEADER0_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_SBKEY_HEADER0_FIELD_SHIFT (0U) +#define FLASH_KEY_STORE_SBKEY_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_SBKEY_HEADER0_FIELD_MASK) +/*! @} */ + +/*! @name SBKEY_HEADER1 - . */ +/*! @{ */ +#define FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_MASK (0x3U) +#define FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_SHIFT (0U) +#define FLASH_KEY_STORE_SBKEY_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_MASK) +#define FLASH_KEY_STORE_SBKEY_HEADER1_INDEX_MASK (0xF00U) +#define FLASH_KEY_STORE_SBKEY_HEADER1_INDEX_SHIFT (8U) +#define FLASH_KEY_STORE_SBKEY_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_SBKEY_HEADER1_INDEX_MASK) +#define FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_MASK (0x3F000000U) +#define FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_SHIFT (24U) +#define FLASH_KEY_STORE_SBKEY_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_MASK) +/*! @} */ + +/*! @name SBKEY_BODY - . */ +/*! @{ */ +#define FLASH_KEY_STORE_SBKEY_BODY_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_SBKEY_BODY_FIELD_SHIFT (0U) +#define FLASH_KEY_STORE_SBKEY_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_SBKEY_BODY_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_KEY_STORE_SBKEY_BODY */ +#define FLASH_KEY_STORE_SBKEY_BODY_COUNT (12U) + +/*! @name USER_KEK_KEY_CODE - . */ +/*! @{ */ +#define FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD_SHIFT (0U) +#define FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_KEY_STORE_USER_KEK_KEY_CODE */ +#define FLASH_KEY_STORE_USER_KEK_KEY_CODE_COUNT (14U) + +/*! @name USER_KEK_HEADER0 - . */ +/*! @{ */ +#define FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD_SHIFT (0U) +#define FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD_MASK) +/*! @} */ + +/*! @name USER_KEK_HEADER1 - . */ +/*! @{ */ +#define FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE_MASK (0x3U) +#define FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE_SHIFT (0U) +#define FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE_MASK) +#define FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX_MASK (0xF00U) +#define FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX_SHIFT (8U) +#define FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX_MASK) +#define FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE_MASK (0x3F000000U) +#define FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE_SHIFT (24U) +#define FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE_MASK) +/*! @} */ + +/*! @name USER_KEK_BODY - . */ +/*! @{ */ +#define FLASH_KEY_STORE_USER_KEK_BODY_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_USER_KEK_BODY_FIELD_SHIFT (0U) +#define FLASH_KEY_STORE_USER_KEK_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_USER_KEK_BODY_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_KEY_STORE_USER_KEK_BODY */ +#define FLASH_KEY_STORE_USER_KEK_BODY_COUNT (12U) + +/*! @name UDS_KEY_CODE - . */ +/*! @{ */ +#define FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_SHIFT (0U) +#define FLASH_KEY_STORE_UDS_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_KEY_STORE_UDS_KEY_CODE */ +#define FLASH_KEY_STORE_UDS_KEY_CODE_COUNT (14U) + +/*! @name UDS_HEADER0 - . */ +/*! @{ */ +#define FLASH_KEY_STORE_UDS_HEADER0_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_UDS_HEADER0_FIELD_SHIFT (0U) +#define FLASH_KEY_STORE_UDS_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER0_FIELD_MASK) +/*! @} */ + +/*! @name UDS_HEADER1 - . */ +/*! @{ */ +#define FLASH_KEY_STORE_UDS_HEADER1_TYPE_MASK (0x3U) +#define FLASH_KEY_STORE_UDS_HEADER1_TYPE_SHIFT (0U) +#define FLASH_KEY_STORE_UDS_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER1_TYPE_MASK) +#define FLASH_KEY_STORE_UDS_HEADER1_INDEX_MASK (0xF00U) +#define FLASH_KEY_STORE_UDS_HEADER1_INDEX_SHIFT (8U) +#define FLASH_KEY_STORE_UDS_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER1_INDEX_MASK) +#define FLASH_KEY_STORE_UDS_HEADER1_SIZE_MASK (0x3F000000U) +#define FLASH_KEY_STORE_UDS_HEADER1_SIZE_SHIFT (24U) +#define FLASH_KEY_STORE_UDS_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER1_SIZE_MASK) +/*! @} */ + +/*! @name UDS_BODY - . */ +/*! @{ */ +#define FLASH_KEY_STORE_UDS_BODY_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_UDS_BODY_FIELD_SHIFT (0U) +#define FLASH_KEY_STORE_UDS_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_UDS_BODY_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_KEY_STORE_UDS_BODY */ +#define FLASH_KEY_STORE_UDS_BODY_COUNT (12U) + +/*! @name PRINCE_REGION0_KEY_CODE - . */ +/*! @{ */ +#define FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD_SHIFT (0U) +#define FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE */ +#define FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_COUNT (14U) + +/*! @name PRINCE_REGION0_HEADER0 - . */ +/*! @{ */ +#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD_SHIFT (0U) +#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD_MASK) +/*! @} */ + +/*! @name PRINCE_REGION0_HEADER1 - . */ +/*! @{ */ +#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE_MASK (0x3U) +#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE_SHIFT (0U) +#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE_MASK) +#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX_MASK (0xF00U) +#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX_SHIFT (8U) +#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX_MASK) +#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE_MASK (0x3F000000U) +#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE_SHIFT (24U) +#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE_MASK) +/*! @} */ + +/*! @name PRINCE_REGION0_BODY - . */ +/*! @{ */ +#define FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD_SHIFT (0U) +#define FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_KEY_STORE_PRINCE_REGION0_BODY */ +#define FLASH_KEY_STORE_PRINCE_REGION0_BODY_COUNT (12U) + +/*! @name PRINCE_REGION1_KEY_CODE - . */ +/*! @{ */ +#define FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD_SHIFT (0U) +#define FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE */ +#define FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_COUNT (14U) + +/*! @name PRINCE_REGION1_HEADER0 - . */ +/*! @{ */ +#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD_SHIFT (0U) +#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD_MASK) +/*! @} */ + +/*! @name PRINCE_REGION1_HEADER1 - . */ +/*! @{ */ +#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE_MASK (0x3U) +#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE_SHIFT (0U) +#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE_MASK) +#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX_MASK (0xF00U) +#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX_SHIFT (8U) +#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX_MASK) +#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE_MASK (0x3F000000U) +#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE_SHIFT (24U) +#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE_MASK) +/*! @} */ + +/*! @name PRINCE_REGION1_BODY - . */ +/*! @{ */ +#define FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD_SHIFT (0U) +#define FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_KEY_STORE_PRINCE_REGION1_BODY */ +#define FLASH_KEY_STORE_PRINCE_REGION1_BODY_COUNT (12U) + +/*! @name PRINCE_REGION2_KEY_CODE - . */ +/*! @{ */ +#define FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD_SHIFT (0U) +#define FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE */ +#define FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_COUNT (14U) + +/*! @name PRINCE_REGION2_HEADER0 - . */ +/*! @{ */ +#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD_SHIFT (0U) +#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD_MASK) +/*! @} */ + +/*! @name PRINCE_REGION2_HEADER1 - . */ +/*! @{ */ +#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE_MASK (0x3U) +#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE_SHIFT (0U) +#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE_MASK) +#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX_MASK (0xF00U) +#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX_SHIFT (8U) +#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX_MASK) +#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE_MASK (0x3F000000U) +#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE_SHIFT (24U) +#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE_MASK) +/*! @} */ + +/*! @name PRINCE_REGION2_BODY - . */ +/*! @{ */ +#define FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD_SHIFT (0U) +#define FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_KEY_STORE_PRINCE_REGION2_BODY */ +#define FLASH_KEY_STORE_PRINCE_REGION2_BODY_COUNT (12U) + + +/*! + * @} + */ /* end of group FLASH_KEY_STORE_Register_Masks */ + + +/* FLASH_KEY_STORE - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral FLASH_KEY_STORE base address */ + #define FLASH_KEY_STORE_BASE (0x1009E600u) + /** Peripheral FLASH_KEY_STORE base address */ + #define FLASH_KEY_STORE_BASE_NS (0x9E600u) + /** Peripheral FLASH_KEY_STORE base pointer */ + #define FLASH_KEY_STORE ((FLASH_KEY_STORE_Type *)FLASH_KEY_STORE_BASE) + /** Peripheral FLASH_KEY_STORE base pointer */ + #define FLASH_KEY_STORE_NS ((FLASH_KEY_STORE_Type *)FLASH_KEY_STORE_BASE_NS) + /** Array initializer of FLASH_KEY_STORE peripheral base addresses */ + #define FLASH_KEY_STORE_BASE_ADDRS { FLASH_KEY_STORE_BASE } + /** Array initializer of FLASH_KEY_STORE peripheral base pointers */ + #define FLASH_KEY_STORE_BASE_PTRS { FLASH_KEY_STORE } + /** Array initializer of FLASH_KEY_STORE peripheral base addresses */ + #define FLASH_KEY_STORE_BASE_ADDRS_NS { FLASH_KEY_STORE_BASE_NS } + /** Array initializer of FLASH_KEY_STORE peripheral base pointers */ + #define FLASH_KEY_STORE_BASE_PTRS_NS { FLASH_KEY_STORE_NS } +#else + /** Peripheral FLASH_KEY_STORE base address */ + #define FLASH_KEY_STORE_BASE (0x9E600u) + /** Peripheral FLASH_KEY_STORE base pointer */ + #define FLASH_KEY_STORE ((FLASH_KEY_STORE_Type *)FLASH_KEY_STORE_BASE) + /** Array initializer of FLASH_KEY_STORE peripheral base addresses */ + #define FLASH_KEY_STORE_BASE_ADDRS { FLASH_KEY_STORE_BASE } + /** Array initializer of FLASH_KEY_STORE peripheral base pointers */ + #define FLASH_KEY_STORE_BASE_PTRS { FLASH_KEY_STORE } +#endif + +/*! + * @} + */ /* end of group FLASH_KEY_STORE_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FLEXCOMM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLEXCOMM_Peripheral_Access_Layer FLEXCOMM Peripheral Access Layer + * @{ + */ + +/** FLEXCOMM - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[4088]; + __IO uint32_t PSELID; /**< Peripheral Select and Flexcomm ID register., offset: 0xFF8 */ + __I uint32_t PID; /**< Peripheral identification register., offset: 0xFFC */ +} FLEXCOMM_Type; + +/* ---------------------------------------------------------------------------- + -- FLEXCOMM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLEXCOMM_Register_Masks FLEXCOMM Register Masks + * @{ + */ + +/*! @name PSELID - Peripheral Select and Flexcomm ID register. */ +/*! @{ */ +#define FLEXCOMM_PSELID_PERSEL_MASK (0x7U) +#define FLEXCOMM_PSELID_PERSEL_SHIFT (0U) +/*! PERSEL - Peripheral Select. This field is writable by software. + * 0b000..No peripheral selected. + * 0b001..USART function selected. + * 0b010..SPI function selected. + * 0b011..I2C function selected. + * 0b100..I2S transmit function selected. + * 0b101..I2S receive function selected. + * 0b110..Reserved + * 0b111..Reserved + */ +#define FLEXCOMM_PSELID_PERSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_PERSEL_SHIFT)) & FLEXCOMM_PSELID_PERSEL_MASK) +#define FLEXCOMM_PSELID_LOCK_MASK (0x8U) +#define FLEXCOMM_PSELID_LOCK_SHIFT (3U) +/*! LOCK - Lock the peripheral select. This field is writable by software. + * 0b0..Peripheral select can be changed by software. + * 0b1..Peripheral select is locked and cannot be changed until this Flexcomm or the entire device is reset. + */ +#define FLEXCOMM_PSELID_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_LOCK_SHIFT)) & FLEXCOMM_PSELID_LOCK_MASK) +#define FLEXCOMM_PSELID_USARTPRESENT_MASK (0x10U) +#define FLEXCOMM_PSELID_USARTPRESENT_SHIFT (4U) +/*! USARTPRESENT - USART present indicator. This field is Read-only. + * 0b0..This Flexcomm does not include the USART function. + * 0b1..This Flexcomm includes the USART function. + */ +#define FLEXCOMM_PSELID_USARTPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_USARTPRESENT_SHIFT)) & FLEXCOMM_PSELID_USARTPRESENT_MASK) +#define FLEXCOMM_PSELID_SPIPRESENT_MASK (0x20U) +#define FLEXCOMM_PSELID_SPIPRESENT_SHIFT (5U) +/*! SPIPRESENT - SPI present indicator. This field is Read-only. + * 0b0..This Flexcomm does not include the SPI function. + * 0b1..This Flexcomm includes the SPI function. + */ +#define FLEXCOMM_PSELID_SPIPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_SPIPRESENT_SHIFT)) & FLEXCOMM_PSELID_SPIPRESENT_MASK) +#define FLEXCOMM_PSELID_I2CPRESENT_MASK (0x40U) +#define FLEXCOMM_PSELID_I2CPRESENT_SHIFT (6U) +/*! I2CPRESENT - I2C present indicator. This field is Read-only. + * 0b0..This Flexcomm does not include the I2C function. + * 0b1..This Flexcomm includes the I2C function. + */ +#define FLEXCOMM_PSELID_I2CPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2CPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2CPRESENT_MASK) +#define FLEXCOMM_PSELID_I2SPRESENT_MASK (0x80U) +#define FLEXCOMM_PSELID_I2SPRESENT_SHIFT (7U) +/*! I2SPRESENT - I 2S present indicator. This field is Read-only. + * 0b0..This Flexcomm does not include the I2S function. + * 0b1..This Flexcomm includes the I2S function. + */ +#define FLEXCOMM_PSELID_I2SPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2SPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2SPRESENT_MASK) +#define FLEXCOMM_PSELID_ID_MASK (0xFFFFF000U) +#define FLEXCOMM_PSELID_ID_SHIFT (12U) +#define FLEXCOMM_PSELID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_ID_SHIFT)) & FLEXCOMM_PSELID_ID_MASK) +/*! @} */ + +/*! @name PID - Peripheral identification register. */ +/*! @{ */ +#define FLEXCOMM_PID_Aperture_MASK (0xFFU) +#define FLEXCOMM_PID_Aperture_SHIFT (0U) +#define FLEXCOMM_PID_Aperture(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Aperture_SHIFT)) & FLEXCOMM_PID_Aperture_MASK) +#define FLEXCOMM_PID_Minor_Rev_MASK (0xF00U) +#define FLEXCOMM_PID_Minor_Rev_SHIFT (8U) +#define FLEXCOMM_PID_Minor_Rev(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Minor_Rev_SHIFT)) & FLEXCOMM_PID_Minor_Rev_MASK) +#define FLEXCOMM_PID_Major_Rev_MASK (0xF000U) +#define FLEXCOMM_PID_Major_Rev_SHIFT (12U) +#define FLEXCOMM_PID_Major_Rev(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Major_Rev_SHIFT)) & FLEXCOMM_PID_Major_Rev_MASK) +#define FLEXCOMM_PID_ID_MASK (0xFFFF0000U) +#define FLEXCOMM_PID_ID_SHIFT (16U) +#define FLEXCOMM_PID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_ID_SHIFT)) & FLEXCOMM_PID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group FLEXCOMM_Register_Masks */ + + +/* FLEXCOMM - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral FLEXCOMM0 base address */ + #define FLEXCOMM0_BASE (0x50086000u) + /** Peripheral FLEXCOMM0 base address */ + #define FLEXCOMM0_BASE_NS (0x40086000u) + /** Peripheral FLEXCOMM0 base pointer */ + #define FLEXCOMM0 ((FLEXCOMM_Type *)FLEXCOMM0_BASE) + /** Peripheral FLEXCOMM0 base pointer */ + #define FLEXCOMM0_NS ((FLEXCOMM_Type *)FLEXCOMM0_BASE_NS) + /** Peripheral FLEXCOMM1 base address */ + #define FLEXCOMM1_BASE (0x50087000u) + /** Peripheral FLEXCOMM1 base address */ + #define FLEXCOMM1_BASE_NS (0x40087000u) + /** Peripheral FLEXCOMM1 base pointer */ + #define FLEXCOMM1 ((FLEXCOMM_Type *)FLEXCOMM1_BASE) + /** Peripheral FLEXCOMM1 base pointer */ + #define FLEXCOMM1_NS ((FLEXCOMM_Type *)FLEXCOMM1_BASE_NS) + /** Peripheral FLEXCOMM2 base address */ + #define FLEXCOMM2_BASE (0x50088000u) + /** Peripheral FLEXCOMM2 base address */ + #define FLEXCOMM2_BASE_NS (0x40088000u) + /** Peripheral FLEXCOMM2 base pointer */ + #define FLEXCOMM2 ((FLEXCOMM_Type *)FLEXCOMM2_BASE) + /** Peripheral FLEXCOMM2 base pointer */ + #define FLEXCOMM2_NS ((FLEXCOMM_Type *)FLEXCOMM2_BASE_NS) + /** Peripheral FLEXCOMM3 base address */ + #define FLEXCOMM3_BASE (0x50089000u) + /** Peripheral FLEXCOMM3 base address */ + #define FLEXCOMM3_BASE_NS (0x40089000u) + /** Peripheral FLEXCOMM3 base pointer */ + #define FLEXCOMM3 ((FLEXCOMM_Type *)FLEXCOMM3_BASE) + /** Peripheral FLEXCOMM3 base pointer */ + #define FLEXCOMM3_NS ((FLEXCOMM_Type *)FLEXCOMM3_BASE_NS) + /** Peripheral FLEXCOMM4 base address */ + #define FLEXCOMM4_BASE (0x5008A000u) + /** Peripheral FLEXCOMM4 base address */ + #define FLEXCOMM4_BASE_NS (0x4008A000u) + /** Peripheral FLEXCOMM4 base pointer */ + #define FLEXCOMM4 ((FLEXCOMM_Type *)FLEXCOMM4_BASE) + /** Peripheral FLEXCOMM4 base pointer */ + #define FLEXCOMM4_NS ((FLEXCOMM_Type *)FLEXCOMM4_BASE_NS) + /** Peripheral FLEXCOMM5 base address */ + #define FLEXCOMM5_BASE (0x50096000u) + /** Peripheral FLEXCOMM5 base address */ + #define FLEXCOMM5_BASE_NS (0x40096000u) + /** Peripheral FLEXCOMM5 base pointer */ + #define FLEXCOMM5 ((FLEXCOMM_Type *)FLEXCOMM5_BASE) + /** Peripheral FLEXCOMM5 base pointer */ + #define FLEXCOMM5_NS ((FLEXCOMM_Type *)FLEXCOMM5_BASE_NS) + /** Peripheral FLEXCOMM6 base address */ + #define FLEXCOMM6_BASE (0x50097000u) + /** Peripheral FLEXCOMM6 base address */ + #define FLEXCOMM6_BASE_NS (0x40097000u) + /** Peripheral FLEXCOMM6 base pointer */ + #define FLEXCOMM6 ((FLEXCOMM_Type *)FLEXCOMM6_BASE) + /** Peripheral FLEXCOMM6 base pointer */ + #define FLEXCOMM6_NS ((FLEXCOMM_Type *)FLEXCOMM6_BASE_NS) + /** Peripheral FLEXCOMM7 base address */ + #define FLEXCOMM7_BASE (0x50098000u) + /** Peripheral FLEXCOMM7 base address */ + #define FLEXCOMM7_BASE_NS (0x40098000u) + /** Peripheral FLEXCOMM7 base pointer */ + #define FLEXCOMM7 ((FLEXCOMM_Type *)FLEXCOMM7_BASE) + /** Peripheral FLEXCOMM7 base pointer */ + #define FLEXCOMM7_NS ((FLEXCOMM_Type *)FLEXCOMM7_BASE_NS) + /** Peripheral FLEXCOMM8 base address */ + #define FLEXCOMM8_BASE (0x5009F000u) + /** Peripheral FLEXCOMM8 base address */ + #define FLEXCOMM8_BASE_NS (0x4009F000u) + /** Peripheral FLEXCOMM8 base pointer */ + #define FLEXCOMM8 ((FLEXCOMM_Type *)FLEXCOMM8_BASE) + /** Peripheral FLEXCOMM8 base pointer */ + #define FLEXCOMM8_NS ((FLEXCOMM_Type *)FLEXCOMM8_BASE_NS) + /** Array initializer of FLEXCOMM peripheral base addresses */ + #define FLEXCOMM_BASE_ADDRS { FLEXCOMM0_BASE, FLEXCOMM1_BASE, FLEXCOMM2_BASE, FLEXCOMM3_BASE, FLEXCOMM4_BASE, FLEXCOMM5_BASE, FLEXCOMM6_BASE, FLEXCOMM7_BASE, FLEXCOMM8_BASE } + /** Array initializer of FLEXCOMM peripheral base pointers */ + #define FLEXCOMM_BASE_PTRS { FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8 } + /** Array initializer of FLEXCOMM peripheral base addresses */ + #define FLEXCOMM_BASE_ADDRS_NS { FLEXCOMM0_BASE_NS, FLEXCOMM1_BASE_NS, FLEXCOMM2_BASE_NS, FLEXCOMM3_BASE_NS, FLEXCOMM4_BASE_NS, FLEXCOMM5_BASE_NS, FLEXCOMM6_BASE_NS, FLEXCOMM7_BASE_NS, FLEXCOMM8_BASE_NS } + /** Array initializer of FLEXCOMM peripheral base pointers */ + #define FLEXCOMM_BASE_PTRS_NS { FLEXCOMM0_NS, FLEXCOMM1_NS, FLEXCOMM2_NS, FLEXCOMM3_NS, FLEXCOMM4_NS, FLEXCOMM5_NS, FLEXCOMM6_NS, FLEXCOMM7_NS, FLEXCOMM8_NS } +#else + /** Peripheral FLEXCOMM0 base address */ + #define FLEXCOMM0_BASE (0x40086000u) + /** Peripheral FLEXCOMM0 base pointer */ + #define FLEXCOMM0 ((FLEXCOMM_Type *)FLEXCOMM0_BASE) + /** Peripheral FLEXCOMM1 base address */ + #define FLEXCOMM1_BASE (0x40087000u) + /** Peripheral FLEXCOMM1 base pointer */ + #define FLEXCOMM1 ((FLEXCOMM_Type *)FLEXCOMM1_BASE) + /** Peripheral FLEXCOMM2 base address */ + #define FLEXCOMM2_BASE (0x40088000u) + /** Peripheral FLEXCOMM2 base pointer */ + #define FLEXCOMM2 ((FLEXCOMM_Type *)FLEXCOMM2_BASE) + /** Peripheral FLEXCOMM3 base address */ + #define FLEXCOMM3_BASE (0x40089000u) + /** Peripheral FLEXCOMM3 base pointer */ + #define FLEXCOMM3 ((FLEXCOMM_Type *)FLEXCOMM3_BASE) + /** Peripheral FLEXCOMM4 base address */ + #define FLEXCOMM4_BASE (0x4008A000u) + /** Peripheral FLEXCOMM4 base pointer */ + #define FLEXCOMM4 ((FLEXCOMM_Type *)FLEXCOMM4_BASE) + /** Peripheral FLEXCOMM5 base address */ + #define FLEXCOMM5_BASE (0x40096000u) + /** Peripheral FLEXCOMM5 base pointer */ + #define FLEXCOMM5 ((FLEXCOMM_Type *)FLEXCOMM5_BASE) + /** Peripheral FLEXCOMM6 base address */ + #define FLEXCOMM6_BASE (0x40097000u) + /** Peripheral FLEXCOMM6 base pointer */ + #define FLEXCOMM6 ((FLEXCOMM_Type *)FLEXCOMM6_BASE) + /** Peripheral FLEXCOMM7 base address */ + #define FLEXCOMM7_BASE (0x40098000u) + /** Peripheral FLEXCOMM7 base pointer */ + #define FLEXCOMM7 ((FLEXCOMM_Type *)FLEXCOMM7_BASE) + /** Peripheral FLEXCOMM8 base address */ + #define FLEXCOMM8_BASE (0x4009F000u) + /** Peripheral FLEXCOMM8 base pointer */ + #define FLEXCOMM8 ((FLEXCOMM_Type *)FLEXCOMM8_BASE) + /** Array initializer of FLEXCOMM peripheral base addresses */ + #define FLEXCOMM_BASE_ADDRS { FLEXCOMM0_BASE, FLEXCOMM1_BASE, FLEXCOMM2_BASE, FLEXCOMM3_BASE, FLEXCOMM4_BASE, FLEXCOMM5_BASE, FLEXCOMM6_BASE, FLEXCOMM7_BASE, FLEXCOMM8_BASE } + /** Array initializer of FLEXCOMM peripheral base pointers */ + #define FLEXCOMM_BASE_PTRS { FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8 } +#endif +/** Interrupt vectors for the FLEXCOMM peripheral type */ +#define FLEXCOMM_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn } + +/*! + * @} + */ /* end of group FLEXCOMM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- GINT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GINT_Peripheral_Access_Layer GINT Peripheral Access Layer + * @{ + */ + +/** GINT - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< GPIO grouped interrupt control register, offset: 0x0 */ + uint8_t RESERVED_0[28]; + __IO uint32_t PORT_POL[2]; /**< GPIO grouped interrupt port 0 polarity register, array offset: 0x20, array step: 0x4 */ + uint8_t RESERVED_1[24]; + __IO uint32_t PORT_ENA[2]; /**< GPIO grouped interrupt port 0 enable register, array offset: 0x40, array step: 0x4 */ +} GINT_Type; + +/* ---------------------------------------------------------------------------- + -- GINT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GINT_Register_Masks GINT Register Masks + * @{ + */ + +/*! @name CTRL - GPIO grouped interrupt control register */ +/*! @{ */ +#define GINT_CTRL_INT_MASK (0x1U) +#define GINT_CTRL_INT_SHIFT (0U) +/*! INT - Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect. + * 0b0..No request. No interrupt request is pending. + * 0b1..Request active. Interrupt request is active. + */ +#define GINT_CTRL_INT(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_INT_SHIFT)) & GINT_CTRL_INT_MASK) +#define GINT_CTRL_COMB_MASK (0x2U) +#define GINT_CTRL_COMB_SHIFT (1U) +/*! COMB - Combine enabled inputs for group interrupt + * 0b0..Or. OR functionality: A grouped interrupt is generated when any one of the enabled inputs is active (based on its programmed polarity). + * 0b1..And. AND functionality: An interrupt is generated when all enabled bits are active (based on their programmed polarity). + */ +#define GINT_CTRL_COMB(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_COMB_SHIFT)) & GINT_CTRL_COMB_MASK) +#define GINT_CTRL_TRIG_MASK (0x4U) +#define GINT_CTRL_TRIG_SHIFT (2U) +/*! TRIG - Group interrupt trigger + * 0b0..Edge-triggered. + * 0b1..Level-triggered. + */ +#define GINT_CTRL_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_TRIG_SHIFT)) & GINT_CTRL_TRIG_MASK) +/*! @} */ + +/*! @name PORT_POL - GPIO grouped interrupt port 0 polarity register */ +/*! @{ */ +#define GINT_PORT_POL_POL_MASK (0xFFFFFFFFU) +#define GINT_PORT_POL_POL_SHIFT (0U) +#define GINT_PORT_POL_POL(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL_SHIFT)) & GINT_PORT_POL_POL_MASK) +/*! @} */ + +/* The count of GINT_PORT_POL */ +#define GINT_PORT_POL_COUNT (2U) + +/*! @name PORT_ENA - GPIO grouped interrupt port 0 enable register */ +/*! @{ */ +#define GINT_PORT_ENA_ENA_MASK (0xFFFFFFFFU) +#define GINT_PORT_ENA_ENA_SHIFT (0U) +#define GINT_PORT_ENA_ENA(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA_SHIFT)) & GINT_PORT_ENA_ENA_MASK) +/*! @} */ + +/* The count of GINT_PORT_ENA */ +#define GINT_PORT_ENA_COUNT (2U) + + +/*! + * @} + */ /* end of group GINT_Register_Masks */ + + +/* GINT - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral GINT0 base address */ + #define GINT0_BASE (0x50002000u) + /** Peripheral GINT0 base address */ + #define GINT0_BASE_NS (0x40002000u) + /** Peripheral GINT0 base pointer */ + #define GINT0 ((GINT_Type *)GINT0_BASE) + /** Peripheral GINT0 base pointer */ + #define GINT0_NS ((GINT_Type *)GINT0_BASE_NS) + /** Peripheral GINT1 base address */ + #define GINT1_BASE (0x50003000u) + /** Peripheral GINT1 base address */ + #define GINT1_BASE_NS (0x40003000u) + /** Peripheral GINT1 base pointer */ + #define GINT1 ((GINT_Type *)GINT1_BASE) + /** Peripheral GINT1 base pointer */ + #define GINT1_NS ((GINT_Type *)GINT1_BASE_NS) + /** Array initializer of GINT peripheral base addresses */ + #define GINT_BASE_ADDRS { GINT0_BASE, GINT1_BASE } + /** Array initializer of GINT peripheral base pointers */ + #define GINT_BASE_PTRS { GINT0, GINT1 } + /** Array initializer of GINT peripheral base addresses */ + #define GINT_BASE_ADDRS_NS { GINT0_BASE_NS, GINT1_BASE_NS } + /** Array initializer of GINT peripheral base pointers */ + #define GINT_BASE_PTRS_NS { GINT0_NS, GINT1_NS } +#else + /** Peripheral GINT0 base address */ + #define GINT0_BASE (0x40002000u) + /** Peripheral GINT0 base pointer */ + #define GINT0 ((GINT_Type *)GINT0_BASE) + /** Peripheral GINT1 base address */ + #define GINT1_BASE (0x40003000u) + /** Peripheral GINT1 base pointer */ + #define GINT1 ((GINT_Type *)GINT1_BASE) + /** Array initializer of GINT peripheral base addresses */ + #define GINT_BASE_ADDRS { GINT0_BASE, GINT1_BASE } + /** Array initializer of GINT peripheral base pointers */ + #define GINT_BASE_PTRS { GINT0, GINT1 } +#endif +/** Interrupt vectors for the GINT peripheral type */ +#define GINT_IRQS { GINT0_IRQn, GINT1_IRQn } + +/*! + * @} + */ /* end of group GINT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- GPIO Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer + * @{ + */ + +/** GPIO - Register Layout Typedef */ +typedef struct { + __IO uint8_t B[4][32]; /**< Byte pin registers for all port GPIO pins, array offset: 0x0, array step: index*0x20, index2*0x1 */ + uint8_t RESERVED_0[3968]; + __IO uint32_t W[4][32]; /**< Word pin registers for all port GPIO pins, array offset: 0x1000, array step: index*0x80, index2*0x4 */ + uint8_t RESERVED_1[3584]; + __IO uint32_t DIR[4]; /**< Direction registers for all port GPIO pins, array offset: 0x2000, array step: 0x4 */ + uint8_t RESERVED_2[112]; + __IO uint32_t MASK[4]; /**< Mask register for all port GPIO pins, array offset: 0x2080, array step: 0x4 */ + uint8_t RESERVED_3[112]; + __IO uint32_t PIN[4]; /**< Port pin register for all port GPIO pins, array offset: 0x2100, array step: 0x4 */ + uint8_t RESERVED_4[112]; + __IO uint32_t MPIN[4]; /**< Masked port register for all port GPIO pins, array offset: 0x2180, array step: 0x4 */ + uint8_t RESERVED_5[112]; + __IO uint32_t SET[4]; /**< Write: Set register for port. Read: output bits for port, array offset: 0x2200, array step: 0x4 */ + uint8_t RESERVED_6[112]; + __O uint32_t CLR[4]; /**< Clear port for all port GPIO pins, array offset: 0x2280, array step: 0x4 */ + uint8_t RESERVED_7[112]; + __O uint32_t NOT[4]; /**< Toggle port for all port GPIO pins, array offset: 0x2300, array step: 0x4 */ + uint8_t RESERVED_8[112]; + __O uint32_t DIRSET[4]; /**< Set pin direction bits for port, array offset: 0x2380, array step: 0x4 */ + uint8_t RESERVED_9[112]; + __O uint32_t DIRCLR[4]; /**< Clear pin direction bits for port, array offset: 0x2400, array step: 0x4 */ + uint8_t RESERVED_10[112]; + __O uint32_t DIRNOT[4]; /**< Toggle pin direction bits for port, array offset: 0x2480, array step: 0x4 */ +} GPIO_Type; + +/* ---------------------------------------------------------------------------- + -- GPIO Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPIO_Register_Masks GPIO Register Masks + * @{ + */ + +/*! @name B - Byte pin registers for all port GPIO pins */ +/*! @{ */ +#define GPIO_B_PBYTE_MASK (0x1U) +#define GPIO_B_PBYTE_SHIFT (0U) +#define GPIO_B_PBYTE(x) (((uint8_t)(((uint8_t)(x)) << GPIO_B_PBYTE_SHIFT)) & GPIO_B_PBYTE_MASK) +/*! @} */ + +/* The count of GPIO_B */ +#define GPIO_B_COUNT (4U) + +/* The count of GPIO_B */ +#define GPIO_B_COUNT2 (32U) + +/*! @name W - Word pin registers for all port GPIO pins */ +/*! @{ */ +#define GPIO_W_PWORD_MASK (0xFFFFFFFFU) +#define GPIO_W_PWORD_SHIFT (0U) +#define GPIO_W_PWORD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_W_PWORD_SHIFT)) & GPIO_W_PWORD_MASK) +/*! @} */ + +/* The count of GPIO_W */ +#define GPIO_W_COUNT (4U) + +/* The count of GPIO_W */ +#define GPIO_W_COUNT2 (32U) + +/*! @name DIR - Direction registers for all port GPIO pins */ +/*! @{ */ +#define GPIO_DIR_DIRP_MASK (0xFFFFFFFFU) +#define GPIO_DIR_DIRP_SHIFT (0U) +#define GPIO_DIR_DIRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP_SHIFT)) & GPIO_DIR_DIRP_MASK) +/*! @} */ + +/* The count of GPIO_DIR */ +#define GPIO_DIR_COUNT (4U) + +/*! @name MASK - Mask register for all port GPIO pins */ +/*! @{ */ +#define GPIO_MASK_MASKP_MASK (0xFFFFFFFFU) +#define GPIO_MASK_MASKP_SHIFT (0U) +#define GPIO_MASK_MASKP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP_SHIFT)) & GPIO_MASK_MASKP_MASK) +/*! @} */ + +/* The count of GPIO_MASK */ +#define GPIO_MASK_COUNT (4U) + +/*! @name PIN - Port pin register for all port GPIO pins */ +/*! @{ */ +#define GPIO_PIN_PORT_MASK (0xFFFFFFFFU) +#define GPIO_PIN_PORT_SHIFT (0U) +#define GPIO_PIN_PORT(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT_SHIFT)) & GPIO_PIN_PORT_MASK) +/*! @} */ + +/* The count of GPIO_PIN */ +#define GPIO_PIN_COUNT (4U) + +/*! @name MPIN - Masked port register for all port GPIO pins */ +/*! @{ */ +#define GPIO_MPIN_MPORTP_MASK (0xFFFFFFFFU) +#define GPIO_MPIN_MPORTP_SHIFT (0U) +#define GPIO_MPIN_MPORTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP_SHIFT)) & GPIO_MPIN_MPORTP_MASK) +/*! @} */ + +/* The count of GPIO_MPIN */ +#define GPIO_MPIN_COUNT (4U) + +/*! @name SET - Write: Set register for port. Read: output bits for port */ +/*! @{ */ +#define GPIO_SET_SETP_MASK (0xFFFFFFFFU) +#define GPIO_SET_SETP_SHIFT (0U) +#define GPIO_SET_SETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_SET_SETP_SHIFT)) & GPIO_SET_SETP_MASK) +/*! @} */ + +/* The count of GPIO_SET */ +#define GPIO_SET_COUNT (4U) + +/*! @name CLR - Clear port for all port GPIO pins */ +/*! @{ */ +#define GPIO_CLR_CLRP_MASK (0xFFFFFFFFU) +#define GPIO_CLR_CLRP_SHIFT (0U) +#define GPIO_CLR_CLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP_SHIFT)) & GPIO_CLR_CLRP_MASK) +/*! @} */ + +/* The count of GPIO_CLR */ +#define GPIO_CLR_COUNT (4U) + +/*! @name NOT - Toggle port for all port GPIO pins */ +/*! @{ */ +#define GPIO_NOT_NOTP_MASK (0xFFFFFFFFU) +#define GPIO_NOT_NOTP_SHIFT (0U) +#define GPIO_NOT_NOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP_SHIFT)) & GPIO_NOT_NOTP_MASK) +/*! @} */ + +/* The count of GPIO_NOT */ +#define GPIO_NOT_COUNT (4U) + +/*! @name DIRSET - Set pin direction bits for port */ +/*! @{ */ +#define GPIO_DIRSET_DIRSETP_MASK (0x1FFFFFFFU) +#define GPIO_DIRSET_DIRSETP_SHIFT (0U) +#define GPIO_DIRSET_DIRSETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP_SHIFT)) & GPIO_DIRSET_DIRSETP_MASK) +/*! @} */ + +/* The count of GPIO_DIRSET */ +#define GPIO_DIRSET_COUNT (4U) + +/*! @name DIRCLR - Clear pin direction bits for port */ +/*! @{ */ +#define GPIO_DIRCLR_DIRCLRP_MASK (0x1FFFFFFFU) +#define GPIO_DIRCLR_DIRCLRP_SHIFT (0U) +#define GPIO_DIRCLR_DIRCLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP_SHIFT)) & GPIO_DIRCLR_DIRCLRP_MASK) +/*! @} */ + +/* The count of GPIO_DIRCLR */ +#define GPIO_DIRCLR_COUNT (4U) + +/*! @name DIRNOT - Toggle pin direction bits for port */ +/*! @{ */ +#define GPIO_DIRNOT_DIRNOTP_MASK (0x1FFFFFFFU) +#define GPIO_DIRNOT_DIRNOTP_SHIFT (0U) +#define GPIO_DIRNOT_DIRNOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRNOT_DIRNOTP_SHIFT)) & GPIO_DIRNOT_DIRNOTP_MASK) +/*! @} */ + +/* The count of GPIO_DIRNOT */ +#define GPIO_DIRNOT_COUNT (4U) + + +/*! + * @} + */ /* end of group GPIO_Register_Masks */ + + +/* GPIO - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral GPIO base address */ + #define GPIO_BASE (0x5008C000u) + /** Peripheral GPIO base address */ + #define GPIO_BASE_NS (0x4008C000u) + /** Peripheral GPIO base pointer */ + #define GPIO ((GPIO_Type *)GPIO_BASE) + /** Peripheral GPIO base pointer */ + #define GPIO_NS ((GPIO_Type *)GPIO_BASE_NS) + /** Peripheral SECGPIO base address */ + #define SECGPIO_BASE (0x500A8000u) + /** Peripheral SECGPIO base address */ + #define SECGPIO_BASE_NS (0x400A8000u) + /** Peripheral SECGPIO base pointer */ + #define SECGPIO ((GPIO_Type *)SECGPIO_BASE) + /** Peripheral SECGPIO base pointer */ + #define SECGPIO_NS ((GPIO_Type *)SECGPIO_BASE_NS) + /** Array initializer of GPIO peripheral base addresses */ + #define GPIO_BASE_ADDRS { GPIO_BASE, SECGPIO_BASE } + /** Array initializer of GPIO peripheral base pointers */ + #define GPIO_BASE_PTRS { GPIO, SECGPIO } + /** Array initializer of GPIO peripheral base addresses */ + #define GPIO_BASE_ADDRS_NS { GPIO_BASE_NS, SECGPIO_BASE_NS } + /** Array initializer of GPIO peripheral base pointers */ + #define GPIO_BASE_PTRS_NS { GPIO_NS, SECGPIO_NS } +#else + /** Peripheral GPIO base address */ + #define GPIO_BASE (0x4008C000u) + /** Peripheral GPIO base pointer */ + #define GPIO ((GPIO_Type *)GPIO_BASE) + /** Peripheral SECGPIO base address */ + #define SECGPIO_BASE (0x400A8000u) + /** Peripheral SECGPIO base pointer */ + #define SECGPIO ((GPIO_Type *)SECGPIO_BASE) + /** Array initializer of GPIO peripheral base addresses */ + #define GPIO_BASE_ADDRS { GPIO_BASE, SECGPIO_BASE } + /** Array initializer of GPIO peripheral base pointers */ + #define GPIO_BASE_PTRS { GPIO, SECGPIO } +#endif + +/*! + * @} + */ /* end of group GPIO_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- HASHCRYPT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup HASHCRYPT_Peripheral_Access_Layer HASHCRYPT Peripheral Access Layer + * @{ + */ + +/** HASHCRYPT - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< Is control register to enable and operate Hash and Crypto, offset: 0x0 */ + __IO uint32_t STATUS; /**< Indicates status of Hash peripheral., offset: 0x4 */ + __IO uint32_t INTENSET; /**< Write 1 to enable interrupts; reads back with which are set., offset: 0x8 */ + __IO uint32_t INTENCLR; /**< Write 1 to clear interrupts., offset: 0xC */ + __IO uint32_t MEMCTRL; /**< Setup Master to access memory (if available), offset: 0x10 */ + __IO uint32_t MEMADDR; /**< Address to start memory access from (if available)., offset: 0x14 */ + uint8_t RESERVED_0[8]; + __O uint32_t INDATA; /**< Input of 16 words at a time to load up buffer., offset: 0x20 */ + __O uint32_t ALIAS[7]; /**< , array offset: 0x24, array step: 0x4 */ + __I uint32_t OUTDATA0[8]; /**< , array offset: 0x40, array step: 0x4 */ + __I uint32_t OUTDATA1[8]; /**< , array offset: 0x60, array step: 0x4 */ + __IO uint32_t CRYPTCFG; /**< Crypto settings for AES and Salsa and ChaCha, offset: 0x80 */ + __I uint32_t CONFIG; /**< Returns the configuration of this block in this chip - indicates what services are available., offset: 0x84 */ + uint8_t RESERVED_1[4]; + __IO uint32_t LOCK; /**< Lock register allows locking to the current security level or unlocking by the lock holding level., offset: 0x8C */ + __O uint32_t MASK[4]; /**< , array offset: 0x90, array step: 0x4 */ +} HASHCRYPT_Type; + +/* ---------------------------------------------------------------------------- + -- HASHCRYPT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup HASHCRYPT_Register_Masks HASHCRYPT Register Masks + * @{ + */ + +/*! @name CTRL - Is control register to enable and operate Hash and Crypto */ +/*! @{ */ +#define HASHCRYPT_CTRL_MODE_MASK (0x7U) +#define HASHCRYPT_CTRL_MODE_SHIFT (0U) +/*! Mode - The operational mode to use, or 0 if none. Note that the CONFIG register will indicate if + * specific modes beyond SHA1 and SHA2-256 are available. + * 0b000..Disabled + * 0b001..SHA1 is enabled + * 0b010..SHA2-256 is enabled + * 0b011..SHA2-512 is enabled (if available) + * 0b100..AES if available (see also CRYPTCFG register for more controls) + * 0b101..ICB-AES if available (see also CRYPTCFG register for more controls) + * 0b110..Salsa20/20 if available (including XSalsa - see also CRYPTCFG register) + * 0b111..ChaCha20 if available (see also CRYPTCFG register for more controls) + */ +#define HASHCRYPT_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_MODE_SHIFT)) & HASHCRYPT_CTRL_MODE_MASK) +#define HASHCRYPT_CTRL_NEW_HASH_MASK (0x10U) +#define HASHCRYPT_CTRL_NEW_HASH_SHIFT (4U) +/*! New_Hash - Written with 1 when starting a new Hash/Crypto. It self clears. Note that the WAITING + * Status bit will clear for a cycle during the initialization from New=1. + * 0b1..Starts a new Hash/Crypto and initializes the Digest/Result. + */ +#define HASHCRYPT_CTRL_NEW_HASH(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_NEW_HASH_SHIFT)) & HASHCRYPT_CTRL_NEW_HASH_MASK) +#define HASHCRYPT_CTRL_DMA_I_MASK (0x100U) +#define HASHCRYPT_CTRL_DMA_I_SHIFT (8U) +/*! DMA_I - Written with 1 to use DMA to fill INDATA. If Hash, will request from DMA for 16 words + * and then will process the Hash. If Cryptographic, it will load as many words as needed, + * including key if not already loaded. It will then request again. Normal model is that the DMA + * interrupts the processor when its length expires. Note that if the processor will write the key and + * optionally IV, it should not enable this until it has done so. Otherwise, the DMA will be + * expected to load those for the 1st block (when needed). + * 0b0..DMA is not used. Processor writes the necessary words when WAITING is set (interrupts), unless AHB Master is used. + * 0b1..DMA will push in the data. + */ +#define HASHCRYPT_CTRL_DMA_I(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_DMA_I_SHIFT)) & HASHCRYPT_CTRL_DMA_I_MASK) +#define HASHCRYPT_CTRL_DMA_O_MASK (0x200U) +#define HASHCRYPT_CTRL_DMA_O_SHIFT (9U) +/*! DMA_O - Written to 1 to use DMA to drain the digest/output. If both DMA_I and DMA_O are set, the + * DMA has to know to switch direction and the locations. This can be used for crypto uses. + * 0b0..DMA is not used. Processor reads the digest/output in response to DIGEST interrupt. + */ +#define HASHCRYPT_CTRL_DMA_O(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_DMA_O_SHIFT)) & HASHCRYPT_CTRL_DMA_O_MASK) +#define HASHCRYPT_CTRL_HASHSWPB_MASK (0x1000U) +#define HASHCRYPT_CTRL_HASHSWPB_SHIFT (12U) +#define HASHCRYPT_CTRL_HASHSWPB(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_HASHSWPB_SHIFT)) & HASHCRYPT_CTRL_HASHSWPB_MASK) +/*! @} */ + +/*! @name STATUS - Indicates status of Hash peripheral. */ +/*! @{ */ +#define HASHCRYPT_STATUS_WAITING_MASK (0x1U) +#define HASHCRYPT_STATUS_WAITING_SHIFT (0U) +/*! WAITING - If 1, the block is waiting for more data to process. + * 0b0..Not waiting for data - may be disabled or may be busy. Note that for cryptographic uses, this is not set + * if IsLast is set nor will it set until at least 1 word is read of the output. + * 0b1..Waiting for data to be written in (16 words) + */ +#define HASHCRYPT_STATUS_WAITING(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_WAITING_SHIFT)) & HASHCRYPT_STATUS_WAITING_MASK) +#define HASHCRYPT_STATUS_DIGEST_AKA_OUTDATA_MASK (0x2U) +#define HASHCRYPT_STATUS_DIGEST_AKA_OUTDATA_SHIFT (1U) +/*! DIGEST_aka_OUTDATA - For Hash, if 1 then a DIGEST is ready and waiting and there is no active + * next block already started. For Cryptographic uses, this will be set for each block processed, + * indicating OUTDATA (and OUTDATA2 if larger output) contains the next value to read out. This is + * cleared when any data is written, when New is written, for Cryptographic uses when the last + * word is read out, or when the block is disabled. + * 0b0..No Digest is ready + * 0b1..Digest is ready. Application may read it or may write more data + */ +#define HASHCRYPT_STATUS_DIGEST_AKA_OUTDATA(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_DIGEST_AKA_OUTDATA_SHIFT)) & HASHCRYPT_STATUS_DIGEST_AKA_OUTDATA_MASK) +#define HASHCRYPT_STATUS_ERROR_MASK (0x4U) +#define HASHCRYPT_STATUS_ERROR_SHIFT (2U) +/*! ERROR - If 1, an error occurred. For normal uses, this is due to an attempted overrun: INDATA + * was written when it was not appropriate. For Master cases, this is an AHB bus error; the COUNT + * field will indicate which block it was on. + * 0b0..No error. + * 0b1..An error occurred since last cleared (written 1 to clear). + */ +#define HASHCRYPT_STATUS_ERROR(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_ERROR_SHIFT)) & HASHCRYPT_STATUS_ERROR_MASK) +#define HASHCRYPT_STATUS_NEEDKEY_MASK (0x10U) +#define HASHCRYPT_STATUS_NEEDKEY_SHIFT (4U) +/*! NEEDKEY - Indicates the block wants the key to be written in (set along with WAITING) + * 0b0..No Key is needed and writes will not be treated as Key + * 0b1..Key is needed and INDATA/ALIAS will be accepted as Key. Will also set WAITING. + */ +#define HASHCRYPT_STATUS_NEEDKEY(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_NEEDKEY_SHIFT)) & HASHCRYPT_STATUS_NEEDKEY_MASK) +#define HASHCRYPT_STATUS_NEEDIV_MASK (0x20U) +#define HASHCRYPT_STATUS_NEEDIV_SHIFT (5U) +/*! NEEDIV - Indicates the block wants an IV/NONE to be written in (set along with WAITING) + * 0b0..No IV/Nonce is needed, either because written already or because not needed. + * 0b1..IV/Nonce is needed and INDATA/ALIAS will be accepted as IV/Nonce. Will also set WAITING. + */ +#define HASHCRYPT_STATUS_NEEDIV(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_NEEDIV_SHIFT)) & HASHCRYPT_STATUS_NEEDIV_MASK) +#define HASHCRYPT_STATUS_ICBIDX_MASK (0x3F0000U) +#define HASHCRYPT_STATUS_ICBIDX_SHIFT (16U) +#define HASHCRYPT_STATUS_ICBIDX(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_ICBIDX_SHIFT)) & HASHCRYPT_STATUS_ICBIDX_MASK) +/*! @} */ + +/*! @name INTENSET - Write 1 to enable interrupts; reads back with which are set. */ +/*! @{ */ +#define HASHCRYPT_INTENSET_WAITING_MASK (0x1U) +#define HASHCRYPT_INTENSET_WAITING_SHIFT (0U) +/*! WAITING - Indicates if should interrupt when waiting for data input. + * 0b0..Will not interrupt when waiting. + * 0b1..Will interrupt when waiting + */ +#define HASHCRYPT_INTENSET_WAITING(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENSET_WAITING_SHIFT)) & HASHCRYPT_INTENSET_WAITING_MASK) +#define HASHCRYPT_INTENSET_DIGEST_MASK (0x2U) +#define HASHCRYPT_INTENSET_DIGEST_SHIFT (1U) +/*! DIGEST - Indicates if should interrupt when Digest (or Outdata) is ready (completed a hash/crypto or completed a full sequence). + * 0b0..Will not interrupt when Digest is ready + * 0b1..Will interrupt when Digest is ready. Interrupt cleared by writing more data, starting a new Hash, or disabling (done). + */ +#define HASHCRYPT_INTENSET_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENSET_DIGEST_SHIFT)) & HASHCRYPT_INTENSET_DIGEST_MASK) +#define HASHCRYPT_INTENSET_ERROR_MASK (0x4U) +#define HASHCRYPT_INTENSET_ERROR_SHIFT (2U) +/*! ERROR - Indicates if should interrupt on an ERROR (as defined in Status) + * 0b0..Will not interrupt on Error. + * 0b1..Will interrupt on Error (until cleared). + */ +#define HASHCRYPT_INTENSET_ERROR(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENSET_ERROR_SHIFT)) & HASHCRYPT_INTENSET_ERROR_MASK) +/*! @} */ + +/*! @name INTENCLR - Write 1 to clear interrupts. */ +/*! @{ */ +#define HASHCRYPT_INTENCLR_WAITING_MASK (0x1U) +#define HASHCRYPT_INTENCLR_WAITING_SHIFT (0U) +#define HASHCRYPT_INTENCLR_WAITING(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENCLR_WAITING_SHIFT)) & HASHCRYPT_INTENCLR_WAITING_MASK) +#define HASHCRYPT_INTENCLR_DIGEST_MASK (0x2U) +#define HASHCRYPT_INTENCLR_DIGEST_SHIFT (1U) +#define HASHCRYPT_INTENCLR_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENCLR_DIGEST_SHIFT)) & HASHCRYPT_INTENCLR_DIGEST_MASK) +#define HASHCRYPT_INTENCLR_ERROR_MASK (0x4U) +#define HASHCRYPT_INTENCLR_ERROR_SHIFT (2U) +#define HASHCRYPT_INTENCLR_ERROR(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENCLR_ERROR_SHIFT)) & HASHCRYPT_INTENCLR_ERROR_MASK) +/*! @} */ + +/*! @name MEMCTRL - Setup Master to access memory (if available) */ +/*! @{ */ +#define HASHCRYPT_MEMCTRL_MASTER_MASK (0x1U) +#define HASHCRYPT_MEMCTRL_MASTER_SHIFT (0U) +/*! MASTER + * 0b0..Mastering is not used and the normal DMA or Interrupt based model is used with INDATA. + * 0b1..Mastering is enabled and DMA and INDATA should not be used. + */ +#define HASHCRYPT_MEMCTRL_MASTER(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_MEMCTRL_MASTER_SHIFT)) & HASHCRYPT_MEMCTRL_MASTER_MASK) +#define HASHCRYPT_MEMCTRL_COUNT_MASK (0x7FF0000U) +#define HASHCRYPT_MEMCTRL_COUNT_SHIFT (16U) +#define HASHCRYPT_MEMCTRL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_MEMCTRL_COUNT_SHIFT)) & HASHCRYPT_MEMCTRL_COUNT_MASK) +/*! @} */ + +/*! @name MEMADDR - Address to start memory access from (if available). */ +/*! @{ */ +#define HASHCRYPT_MEMADDR_BASE_MASK (0xFFFFFFFFU) +#define HASHCRYPT_MEMADDR_BASE_SHIFT (0U) +#define HASHCRYPT_MEMADDR_BASE(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_MEMADDR_BASE_SHIFT)) & HASHCRYPT_MEMADDR_BASE_MASK) +/*! @} */ + +/*! @name INDATA - Input of 16 words at a time to load up buffer. */ +/*! @{ */ +#define HASHCRYPT_INDATA_DATA_MASK (0xFFFFFFFFU) +#define HASHCRYPT_INDATA_DATA_SHIFT (0U) +#define HASHCRYPT_INDATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INDATA_DATA_SHIFT)) & HASHCRYPT_INDATA_DATA_MASK) +/*! @} */ + +/*! @name ALIAS - */ +/*! @{ */ +#define HASHCRYPT_ALIAS_DATA_MASK (0xFFFFFFFFU) +#define HASHCRYPT_ALIAS_DATA_SHIFT (0U) +#define HASHCRYPT_ALIAS_DATA(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_ALIAS_DATA_SHIFT)) & HASHCRYPT_ALIAS_DATA_MASK) +/*! @} */ + +/* The count of HASHCRYPT_ALIAS */ +#define HASHCRYPT_ALIAS_COUNT (7U) + +/*! @name OUTDATA0 - */ +/*! @{ */ +#define HASHCRYPT_OUTDATA0_DIGEST_OUTPUT_MASK (0xFFFFFFFFU) +#define HASHCRYPT_OUTDATA0_DIGEST_OUTPUT_SHIFT (0U) +#define HASHCRYPT_OUTDATA0_DIGEST_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_OUTDATA0_DIGEST_OUTPUT_SHIFT)) & HASHCRYPT_OUTDATA0_DIGEST_OUTPUT_MASK) +/*! @} */ + +/* The count of HASHCRYPT_OUTDATA0 */ +#define HASHCRYPT_OUTDATA0_COUNT (8U) + +/*! @name OUTDATA1 - */ +/*! @{ */ +#define HASHCRYPT_OUTDATA1_OUTPUT_MASK (0xFFFFFFFFU) +#define HASHCRYPT_OUTDATA1_OUTPUT_SHIFT (0U) +#define HASHCRYPT_OUTDATA1_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_OUTDATA1_OUTPUT_SHIFT)) & HASHCRYPT_OUTDATA1_OUTPUT_MASK) +/*! @} */ + +/* The count of HASHCRYPT_OUTDATA1 */ +#define HASHCRYPT_OUTDATA1_COUNT (8U) + +/*! @name CRYPTCFG - Crypto settings for AES and Salsa and ChaCha */ +/*! @{ */ +#define HASHCRYPT_CRYPTCFG_MSW1ST_OUT_MASK (0x1U) +#define HASHCRYPT_CRYPTCFG_MSW1ST_OUT_SHIFT (0U) +#define HASHCRYPT_CRYPTCFG_MSW1ST_OUT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_MSW1ST_OUT_SHIFT)) & HASHCRYPT_CRYPTCFG_MSW1ST_OUT_MASK) +#define HASHCRYPT_CRYPTCFG_SWAPKEY_MASK (0x2U) +#define HASHCRYPT_CRYPTCFG_SWAPKEY_SHIFT (1U) +#define HASHCRYPT_CRYPTCFG_SWAPKEY(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_SWAPKEY_SHIFT)) & HASHCRYPT_CRYPTCFG_SWAPKEY_MASK) +#define HASHCRYPT_CRYPTCFG_SWAPDAT_MASK (0x4U) +#define HASHCRYPT_CRYPTCFG_SWAPDAT_SHIFT (2U) +#define HASHCRYPT_CRYPTCFG_SWAPDAT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_SWAPDAT_SHIFT)) & HASHCRYPT_CRYPTCFG_SWAPDAT_MASK) +#define HASHCRYPT_CRYPTCFG_MSW1ST_MASK (0x8U) +#define HASHCRYPT_CRYPTCFG_MSW1ST_SHIFT (3U) +#define HASHCRYPT_CRYPTCFG_MSW1ST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_MSW1ST_SHIFT)) & HASHCRYPT_CRYPTCFG_MSW1ST_MASK) +#define HASHCRYPT_CRYPTCFG_AESMODE_MASK (0x30U) +#define HASHCRYPT_CRYPTCFG_AESMODE_SHIFT (4U) +/*! AESMODE - AES Cipher mode to use if plain AES + * 0b00..ECB - used as is + * 0b01..CBC mode (see details on IV/nonce) + * 0b10..CTR mode (see details on IV/nonce). See also AESCTRPOS. + * 0b11..reserved + */ +#define HASHCRYPT_CRYPTCFG_AESMODE(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESMODE_SHIFT)) & HASHCRYPT_CRYPTCFG_AESMODE_MASK) +#define HASHCRYPT_CRYPTCFG_AESDECRYPT_MASK (0x40U) +#define HASHCRYPT_CRYPTCFG_AESDECRYPT_SHIFT (6U) +/*! AESDECRYPT - AES ECB direction. Only encryption used if CTR mode or manual modes such as CFB + * 0b0..Encrypt + * 0b1..Decrypt + */ +#define HASHCRYPT_CRYPTCFG_AESDECRYPT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESDECRYPT_SHIFT)) & HASHCRYPT_CRYPTCFG_AESDECRYPT_MASK) +#define HASHCRYPT_CRYPTCFG_AESSECRET_MASK (0x80U) +#define HASHCRYPT_CRYPTCFG_AESSECRET_SHIFT (7U) +/*! AESSECRET - Selects the Hidden Secret key vs. User key, if provided. If security levels are + * used, only the highest level is permitted to select this. + * 0b0..User key provided in normal way + * 0b1..Secret key provided in hidden way by HW + */ +#define HASHCRYPT_CRYPTCFG_AESSECRET(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESSECRET_SHIFT)) & HASHCRYPT_CRYPTCFG_AESSECRET_MASK) +#define HASHCRYPT_CRYPTCFG_AESKEYSZ_MASK (0x300U) +#define HASHCRYPT_CRYPTCFG_AESKEYSZ_SHIFT (8U) +/*! AESKEYSZ - Sets the AES key size + * 0b00..128 bit key + * 0b01..192 bit key + * 0b10..256 bit key + * 0b11..reserved + */ +#define HASHCRYPT_CRYPTCFG_AESKEYSZ(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESKEYSZ_SHIFT)) & HASHCRYPT_CRYPTCFG_AESKEYSZ_MASK) +#define HASHCRYPT_CRYPTCFG_AESCTRPOS_MASK (0x1C00U) +#define HASHCRYPT_CRYPTCFG_AESCTRPOS_SHIFT (10U) +#define HASHCRYPT_CRYPTCFG_AESCTRPOS(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESCTRPOS_SHIFT)) & HASHCRYPT_CRYPTCFG_AESCTRPOS_MASK) +#define HASHCRYPT_CRYPTCFG_STREAMLAST_MASK (0x10000U) +#define HASHCRYPT_CRYPTCFG_STREAMLAST_SHIFT (16U) +#define HASHCRYPT_CRYPTCFG_STREAMLAST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_STREAMLAST_SHIFT)) & HASHCRYPT_CRYPTCFG_STREAMLAST_MASK) +#define HASHCRYPT_CRYPTCFG_XSALSA_MASK (0x20000U) +#define HASHCRYPT_CRYPTCFG_XSALSA_SHIFT (17U) +#define HASHCRYPT_CRYPTCFG_XSALSA(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_XSALSA_SHIFT)) & HASHCRYPT_CRYPTCFG_XSALSA_MASK) +#define HASHCRYPT_CRYPTCFG_ICBSZ_MASK (0x300000U) +#define HASHCRYPT_CRYPTCFG_ICBSZ_SHIFT (20U) +/*! ICBSZ - This sets the ICB size between 32 and 128 bits, using the following rules. Note that the + * counter is assumed to occupy the low order bits of the IV. + * 0b00..32 bits of the IV/ctr are used (from 127:96) + * 0b01..64 bits of the IV/ctr are used (from 127:64) + * 0b10..96 bits of the IV/ctr are used (from 127:32) + * 0b11..All 128 bits of the IV/ctr are used + */ +#define HASHCRYPT_CRYPTCFG_ICBSZ(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_ICBSZ_SHIFT)) & HASHCRYPT_CRYPTCFG_ICBSZ_MASK) +#define HASHCRYPT_CRYPTCFG_ICBSTRM_MASK (0xC00000U) +#define HASHCRYPT_CRYPTCFG_ICBSTRM_SHIFT (22U) +/*! ICBSTRM - The size of the ICB-AES stream that can be pushed before needing to compute a new + * IV/ctr (counter start). This optimizes the performance of the stream of blocks after the 1st. + * 0b00..8 blocks + * 0b01..16 blocks + * 0b10..32 blocks + * 0b11..64 blocks + */ +#define HASHCRYPT_CRYPTCFG_ICBSTRM(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_ICBSTRM_SHIFT)) & HASHCRYPT_CRYPTCFG_ICBSTRM_MASK) +/*! @} */ + +/*! @name CONFIG - Returns the configuration of this block in this chip - indicates what services are available. */ +/*! @{ */ +#define HASHCRYPT_CONFIG_DUAL_MASK (0x1U) +#define HASHCRYPT_CONFIG_DUAL_SHIFT (0U) +#define HASHCRYPT_CONFIG_DUAL(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_DUAL_SHIFT)) & HASHCRYPT_CONFIG_DUAL_MASK) +#define HASHCRYPT_CONFIG_DMA_MASK (0x2U) +#define HASHCRYPT_CONFIG_DMA_SHIFT (1U) +#define HASHCRYPT_CONFIG_DMA(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_DMA_SHIFT)) & HASHCRYPT_CONFIG_DMA_MASK) +#define HASHCRYPT_CONFIG_AHB_MASK (0x8U) +#define HASHCRYPT_CONFIG_AHB_SHIFT (3U) +#define HASHCRYPT_CONFIG_AHB(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_AHB_SHIFT)) & HASHCRYPT_CONFIG_AHB_MASK) +#define HASHCRYPT_CONFIG_SHA512_MASK (0x20U) +#define HASHCRYPT_CONFIG_SHA512_SHIFT (5U) +#define HASHCRYPT_CONFIG_SHA512(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_SHA512_SHIFT)) & HASHCRYPT_CONFIG_SHA512_MASK) +#define HASHCRYPT_CONFIG_AES_MASK (0x40U) +#define HASHCRYPT_CONFIG_AES_SHIFT (6U) +#define HASHCRYPT_CONFIG_AES(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_AES_SHIFT)) & HASHCRYPT_CONFIG_AES_MASK) +#define HASHCRYPT_CONFIG_AESKEY_MASK (0x80U) +#define HASHCRYPT_CONFIG_AESKEY_SHIFT (7U) +#define HASHCRYPT_CONFIG_AESKEY(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_AESKEY_SHIFT)) & HASHCRYPT_CONFIG_AESKEY_MASK) +#define HASHCRYPT_CONFIG_SECRET_MASK (0x100U) +#define HASHCRYPT_CONFIG_SECRET_SHIFT (8U) +#define HASHCRYPT_CONFIG_SECRET(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_SECRET_SHIFT)) & HASHCRYPT_CONFIG_SECRET_MASK) +#define HASHCRYPT_CONFIG_SALSA_MASK (0x200U) +#define HASHCRYPT_CONFIG_SALSA_SHIFT (9U) +#define HASHCRYPT_CONFIG_SALSA(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_SALSA_SHIFT)) & HASHCRYPT_CONFIG_SALSA_MASK) +#define HASHCRYPT_CONFIG_CHACHA_MASK (0x400U) +#define HASHCRYPT_CONFIG_CHACHA_SHIFT (10U) +#define HASHCRYPT_CONFIG_CHACHA(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_CHACHA_SHIFT)) & HASHCRYPT_CONFIG_CHACHA_MASK) +#define HASHCRYPT_CONFIG_ICB_MASK (0x800U) +#define HASHCRYPT_CONFIG_ICB_SHIFT (11U) +#define HASHCRYPT_CONFIG_ICB(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_ICB_SHIFT)) & HASHCRYPT_CONFIG_ICB_MASK) +/*! @} */ + +/*! @name LOCK - Lock register allows locking to the current security level or unlocking by the lock holding level. */ +/*! @{ */ +#define HASHCRYPT_LOCK_SECLOCK_MASK (0x3U) +#define HASHCRYPT_LOCK_SECLOCK_SHIFT (0U) +/*! SECLOCK - Write 1 to secure-lock this block (if running in a security state). Write 0 to unlock. + * If locked already, may only write if at same or higher security level as lock. Reads as: 0 if + * unlocked, else 1, 2, 3 to indicate security level it is locked at. NOTE: this and ID are the + * only readable registers if locked and current state is lower than lock level. + * 0b00..Unlocks, so block is open to all. But, AHB Master will only issue non-secure requests. + * 0b01..Locks to the current security level. AHB Master will issue requests at this level. + */ +#define HASHCRYPT_LOCK_SECLOCK(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_LOCK_SECLOCK_SHIFT)) & HASHCRYPT_LOCK_SECLOCK_MASK) +#define HASHCRYPT_LOCK_PATTERN_MASK (0xFFF0U) +#define HASHCRYPT_LOCK_PATTERN_SHIFT (4U) +#define HASHCRYPT_LOCK_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_LOCK_PATTERN_SHIFT)) & HASHCRYPT_LOCK_PATTERN_MASK) +/*! @} */ + +/*! @name MASK - */ +/*! @{ */ +#define HASHCRYPT_MASK_MASK_MASK (0xFFFFFFFFU) +#define HASHCRYPT_MASK_MASK_SHIFT (0U) +#define HASHCRYPT_MASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_MASK_MASK_SHIFT)) & HASHCRYPT_MASK_MASK_MASK) +/*! @} */ + +/* The count of HASHCRYPT_MASK */ +#define HASHCRYPT_MASK_COUNT (4U) + + +/*! + * @} + */ /* end of group HASHCRYPT_Register_Masks */ + + +/* HASHCRYPT - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral HASHCRYPT base address */ + #define HASHCRYPT_BASE (0x500A4000u) + /** Peripheral HASHCRYPT base address */ + #define HASHCRYPT_BASE_NS (0x400A4000u) + /** Peripheral HASHCRYPT base pointer */ + #define HASHCRYPT ((HASHCRYPT_Type *)HASHCRYPT_BASE) + /** Peripheral HASHCRYPT base pointer */ + #define HASHCRYPT_NS ((HASHCRYPT_Type *)HASHCRYPT_BASE_NS) + /** Array initializer of HASHCRYPT peripheral base addresses */ + #define HASHCRYPT_BASE_ADDRS { HASHCRYPT_BASE } + /** Array initializer of HASHCRYPT peripheral base pointers */ + #define HASHCRYPT_BASE_PTRS { HASHCRYPT } + /** Array initializer of HASHCRYPT peripheral base addresses */ + #define HASHCRYPT_BASE_ADDRS_NS { HASHCRYPT_BASE_NS } + /** Array initializer of HASHCRYPT peripheral base pointers */ + #define HASHCRYPT_BASE_PTRS_NS { HASHCRYPT_NS } +#else + /** Peripheral HASHCRYPT base address */ + #define HASHCRYPT_BASE (0x400A4000u) + /** Peripheral HASHCRYPT base pointer */ + #define HASHCRYPT ((HASHCRYPT_Type *)HASHCRYPT_BASE) + /** Array initializer of HASHCRYPT peripheral base addresses */ + #define HASHCRYPT_BASE_ADDRS { HASHCRYPT_BASE } + /** Array initializer of HASHCRYPT peripheral base pointers */ + #define HASHCRYPT_BASE_PTRS { HASHCRYPT } +#endif + +/*! + * @} + */ /* end of group HASHCRYPT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- I2C Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer + * @{ + */ + +/** I2C - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[2048]; + __IO uint32_t CFG; /**< Configuration for shared functions., offset: 0x800 */ + __IO uint32_t STAT; /**< Status register for Master, Slave, and Monitor functions., offset: 0x804 */ + __IO uint32_t INTENSET; /**< Interrupt Enable Set and read register., offset: 0x808 */ + __O uint32_t INTENCLR; /**< Interrupt Enable Clear register., offset: 0x80C */ + __IO uint32_t TIMEOUT; /**< Time-out value register., offset: 0x810 */ + __IO uint32_t CLKDIV; /**< Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function., offset: 0x814 */ + __I uint32_t INTSTAT; /**< Interrupt Status register for Master, Slave, and Monitor functions., offset: 0x818 */ + uint8_t RESERVED_1[4]; + __IO uint32_t MSTCTL; /**< Master control register., offset: 0x820 */ + __IO uint32_t MSTTIME; /**< Master timing configuration., offset: 0x824 */ + __IO uint32_t MSTDAT; /**< Combined Master receiver and transmitter data register., offset: 0x828 */ + uint8_t RESERVED_2[20]; + __IO uint32_t SLVCTL; /**< Slave control register., offset: 0x840 */ + __IO uint32_t SLVDAT; /**< Combined Slave receiver and transmitter data register., offset: 0x844 */ + __IO uint32_t SLVADR[4]; /**< Slave address register., array offset: 0x848, array step: 0x4 */ + __IO uint32_t SLVQUAL0; /**< Slave Qualification for address 0., offset: 0x858 */ + uint8_t RESERVED_3[36]; + __I uint32_t MONRXDAT; /**< Monitor receiver data register., offset: 0x880 */ + uint8_t RESERVED_4[1912]; + __I uint32_t ID; /**< Peripheral identification register., offset: 0xFFC */ +} I2C_Type; + +/* ---------------------------------------------------------------------------- + -- I2C Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2C_Register_Masks I2C Register Masks + * @{ + */ + +/*! @name CFG - Configuration for shared functions. */ +/*! @{ */ +#define I2C_CFG_MSTEN_MASK (0x1U) +#define I2C_CFG_MSTEN_SHIFT (0U) +/*! MSTEN - Master Enable. When disabled, configurations settings for the Master function are not + * changed, but the Master function is internally reset. + * 0b0..Disabled. The I2C Master function is disabled. + * 0b1..Enabled. The I2C Master function is enabled. + */ +#define I2C_CFG_MSTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MSTEN_SHIFT)) & I2C_CFG_MSTEN_MASK) +#define I2C_CFG_SLVEN_MASK (0x2U) +#define I2C_CFG_SLVEN_SHIFT (1U) +/*! SLVEN - Slave Enable. When disabled, configurations settings for the Slave function are not + * changed, but the Slave function is internally reset. + * 0b0..Disabled. The I2C slave function is disabled. + * 0b1..Enabled. The I2C slave function is enabled. + */ +#define I2C_CFG_SLVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_SLVEN_SHIFT)) & I2C_CFG_SLVEN_MASK) +#define I2C_CFG_MONEN_MASK (0x4U) +#define I2C_CFG_MONEN_SHIFT (2U) +/*! MONEN - Monitor Enable. When disabled, configurations settings for the Monitor function are not + * changed, but the Monitor function is internally reset. + * 0b0..Disabled. The I2C Monitor function is disabled. + * 0b1..Enabled. The I2C Monitor function is enabled. + */ +#define I2C_CFG_MONEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONEN_SHIFT)) & I2C_CFG_MONEN_MASK) +#define I2C_CFG_TIMEOUTEN_MASK (0x8U) +#define I2C_CFG_TIMEOUTEN_SHIFT (3U) +/*! TIMEOUTEN - I2C bus Time-out Enable. When disabled, the time-out function is internally reset. + * 0b0..Disabled. Time-out function is disabled. + * 0b1..Enabled. Time-out function is enabled. Both types of time-out flags will be generated and will cause + * interrupts if they are enabled. Typically, only one time-out will be used in a system. + */ +#define I2C_CFG_TIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_TIMEOUTEN_SHIFT)) & I2C_CFG_TIMEOUTEN_MASK) +#define I2C_CFG_MONCLKSTR_MASK (0x10U) +#define I2C_CFG_MONCLKSTR_SHIFT (4U) +/*! MONCLKSTR - Monitor function Clock Stretching. + * 0b0..Disabled. The Monitor function will not perform clock stretching. Software or DMA may not always be able + * to read data provided by the Monitor function before it is overwritten. This mode may be used when + * non-invasive monitoring is critical. + * 0b1..Enabled. The Monitor function will perform clock stretching in order to ensure that software or DMA can + * read all incoming data supplied by the Monitor function. + */ +#define I2C_CFG_MONCLKSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONCLKSTR_SHIFT)) & I2C_CFG_MONCLKSTR_MASK) +#define I2C_CFG_HSCAPABLE_MASK (0x20U) +#define I2C_CFG_HSCAPABLE_SHIFT (5U) +/*! HSCAPABLE - High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive + * and filter, as well as the timing for certain I2C signalling, enabling High-speed mode applies + * to all functions: Master, Slave, and Monitor. + * 0b0..Fast-mode plus. The I 2C interface will support Standard-mode, Fast-mode, and Fast-mode Plus, to the + * extent that the pin electronics support these modes. Any changes that need to be made to the pin controls, + * such as changing the drive strength or filtering, must be made by software via the IOCON register associated + * with each I2C pin, + * 0b1..High-speed. In addition to Standard-mode, Fast-mode, and Fast-mode Plus, the I 2C interface will support + * High-speed mode to the extent that the pin electronics support these modes. See Section 25.7.2.2 for more + * information. + */ +#define I2C_CFG_HSCAPABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_HSCAPABLE_SHIFT)) & I2C_CFG_HSCAPABLE_MASK) +/*! @} */ + +/*! @name STAT - Status register for Master, Slave, and Monitor functions. */ +/*! @{ */ +#define I2C_STAT_MSTPENDING_MASK (0x1U) +#define I2C_STAT_MSTPENDING_SHIFT (0U) +/*! MSTPENDING - Master Pending. Indicates that the Master is waiting to continue communication on + * the I2C-bus (pending) or is idle. When the master is pending, the MSTSTATE bits indicate what + * type of software service if any the master expects. This flag will cause an interrupt when set + * if, enabled via the INTENSET register. The MSTPENDING flag is not set when the DMA is handling + * an event (if the MSTDMA bit in the MSTCTL register is set). If the master is in the idle + * state, and no communication is needed, mask this interrupt. + * 0b0..In progress. Communication is in progress and the Master function is busy and cannot currently accept a command. + * 0b1..Pending. The Master function needs software service or is in the idle state. If the master is not in the + * idle state, it is waiting to receive or transmit data or the NACK bit. + */ +#define I2C_STAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTPENDING_SHIFT)) & I2C_STAT_MSTPENDING_MASK) +#define I2C_STAT_MSTSTATE_MASK (0xEU) +#define I2C_STAT_MSTSTATE_SHIFT (1U) +/*! MSTSTATE - Master State code. The master state code reflects the master state when the + * MSTPENDING bit is set, that is the master is pending or in the idle state. Each value of this field + * indicates a specific required service for the Master function. All other values are reserved. See + * Table 400 for details of state values and appropriate responses. + * 0b000..Idle. The Master function is available to be used for a new transaction. + * 0b001..Receive ready. Received data available (Master Receiver mode). Address plus Read was previously sent and Acknowledged by slave. + * 0b010..Transmit ready. Data can be transmitted (Master Transmitter mode). Address plus Write was previously sent and Acknowledged by slave. + * 0b011..NACK Address. Slave NACKed address. + * 0b100..NACK Data. Slave NACKed transmitted data. + */ +#define I2C_STAT_MSTSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTATE_SHIFT)) & I2C_STAT_MSTSTATE_MASK) +#define I2C_STAT_MSTARBLOSS_MASK (0x10U) +#define I2C_STAT_MSTARBLOSS_SHIFT (4U) +/*! MSTARBLOSS - Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to + * this bit. It is also cleared automatically a 1 is written to MSTCONTINUE. + * 0b0..No Arbitration Loss has occurred. + * 0b1..Arbitration loss. The Master function has experienced an Arbitration Loss. At this point, the Master + * function has already stopped driving the bus and gone to an idle state. Software can respond by doing nothing, + * or by sending a Start in order to attempt to gain control of the bus when it next becomes idle. + */ +#define I2C_STAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTARBLOSS_SHIFT)) & I2C_STAT_MSTARBLOSS_MASK) +#define I2C_STAT_MSTSTSTPERR_MASK (0x40U) +#define I2C_STAT_MSTSTSTPERR_SHIFT (6U) +/*! MSTSTSTPERR - Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to + * this bit. It is also cleared automatically a 1 is written to MSTCONTINUE. + * 0b0..No Start/Stop Error has occurred. + * 0b1..The Master function has experienced a Start/Stop Error. A Start or Stop was detected at a time when it is + * not allowed by the I2C specification. The Master interface has stopped driving the bus and gone to an + * idle state, no action is required. A request for a Start could be made, or software could attempt to insure + * that the bus has not stalled. + */ +#define I2C_STAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTSTPERR_SHIFT)) & I2C_STAT_MSTSTSTPERR_MASK) +#define I2C_STAT_SLVPENDING_MASK (0x100U) +#define I2C_STAT_SLVPENDING_SHIFT (8U) +/*! SLVPENDING - Slave Pending. Indicates that the Slave function is waiting to continue + * communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if + * enabled via INTENSET. The SLVPENDING flag is not set when the DMA is handling an event (if the + * SLVDMA bit in the SLVCTL register is set). The SLVPENDING flag is read-only and is + * automatically cleared when a 1 is written to the SLVCONTINUE bit in the SLVCTL register. The point in time + * when SlvPending is set depends on whether the I2C interface is in HSCAPABLE mode. See Section + * 25.7.2.2.2. When the I2C interface is configured to be HSCAPABLE, HS master codes are + * detected automatically. Due to the requirements of the HS I2C specification, slave addresses must + * also be detected automatically, since the address must be acknowledged before the clock can be + * stretched. + * 0b0..In progress. The Slave function does not currently need service. + * 0b1..Pending. The Slave function needs service. Information on what is needed can be found in the adjacent SLVSTATE field. + */ +#define I2C_STAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVPENDING_SHIFT)) & I2C_STAT_SLVPENDING_MASK) +#define I2C_STAT_SLVSTATE_MASK (0x600U) +#define I2C_STAT_SLVSTATE_SHIFT (9U) +/*! SLVSTATE - Slave State code. Each value of this field indicates a specific required service for + * the Slave function. All other values are reserved. See Table 401 for state values and actions. + * note that the occurrence of some states and how they are handled are affected by DMA mode and + * Automatic Operation modes. + * 0b00..Slave address. Address plus R/W received. At least one of the four slave addresses has been matched by hardware. + * 0b01..Slave receive. Received data is available (Slave Receiver mode). + * 0b10..Slave transmit. Data can be transmitted (Slave Transmitter mode). + */ +#define I2C_STAT_SLVSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSTATE_SHIFT)) & I2C_STAT_SLVSTATE_MASK) +#define I2C_STAT_SLVNOTSTR_MASK (0x800U) +#define I2C_STAT_SLVNOTSTR_SHIFT (11U) +/*! SLVNOTSTR - Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. + * This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave + * operation. This read-only flag reflects the slave function status in real time. + * 0b0..Stretching. The slave function is currently stretching the I2C bus clock. Deep-Sleep or Power-down mode cannot be entered at this time. + * 0b1..Not stretching. The slave function is not currently stretching the I 2C bus clock. Deep-sleep or + * Power-down mode could be entered at this time. + */ +#define I2C_STAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVNOTSTR_SHIFT)) & I2C_STAT_SLVNOTSTR_MASK) +#define I2C_STAT_SLVIDX_MASK (0x3000U) +#define I2C_STAT_SLVIDX_SHIFT (12U) +/*! SLVIDX - Slave address match Index. This field is valid when the I2C slave function has been + * selected by receiving an address that matches one of the slave addresses defined by any enabled + * slave address registers, and provides an identification of the address that was matched. It is + * possible that more than one address could be matched, but only one match can be reported here. + * 0b00..Address 0. Slave address 0 was matched. + * 0b01..Address 1. Slave address 1 was matched. + * 0b10..Address 2. Slave address 2 was matched. + * 0b11..Address 3. Slave address 3 was matched. + */ +#define I2C_STAT_SLVIDX(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVIDX_SHIFT)) & I2C_STAT_SLVIDX_MASK) +#define I2C_STAT_SLVSEL_MASK (0x4000U) +#define I2C_STAT_SLVSEL_SHIFT (14U) +/*! SLVSEL - Slave selected flag. SLVSEL is set after an address match when software tells the Slave + * function to acknowledge the address, or when the address has been automatically acknowledged. + * It is cleared when another address cycle presents an address that does not match an enabled + * address on the Slave function, when slave software decides to NACK a matched address, when + * there is a Stop detected on the bus, when the master NACKs slave data, and in some combinations of + * Automatic Operation. SLVSEL is not cleared if software NACKs data. + * 0b0..Not selected. The Slave function is not currently selected. + * 0b1..Selected. The Slave function is currently selected. + */ +#define I2C_STAT_SLVSEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSEL_SHIFT)) & I2C_STAT_SLVSEL_MASK) +#define I2C_STAT_SLVDESEL_MASK (0x8000U) +#define I2C_STAT_SLVDESEL_SHIFT (15U) +/*! SLVDESEL - Slave Deselected flag. This flag will cause an interrupt when set if enabled via + * INTENSET. This flag can be cleared by writing a 1 to this bit. + * 0b0..Not deselected. The Slave function has not become deselected. This does not mean that it is currently + * selected. That information can be found in the SLVSEL flag. + * 0b1..Deselected. The Slave function has become deselected. This is specifically caused by the SLVSEL flag + * changing from 1 to 0. See the description of SLVSEL for details on when that event occurs. + */ +#define I2C_STAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVDESEL_SHIFT)) & I2C_STAT_SLVDESEL_MASK) +#define I2C_STAT_MONRDY_MASK (0x10000U) +#define I2C_STAT_MONRDY_SHIFT (16U) +/*! MONRDY - Monitor Ready. This flag is cleared when the MONRXDAT register is read. + * 0b0..No data. The Monitor function does not currently have data available. + * 0b1..Data waiting. The Monitor function has data waiting to be read. + */ +#define I2C_STAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONRDY_SHIFT)) & I2C_STAT_MONRDY_MASK) +#define I2C_STAT_MONOV_MASK (0x20000U) +#define I2C_STAT_MONOV_SHIFT (17U) +/*! MONOV - Monitor Overflow flag. + * 0b0..No overrun. Monitor data has not overrun. + * 0b1..Overrun. A Monitor data overrun has occurred. This can only happen when Monitor clock stretching not + * enabled via the MONCLKSTR bit in the CFG register. Writing 1 to this bit clears the flag. + */ +#define I2C_STAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONOV_SHIFT)) & I2C_STAT_MONOV_MASK) +#define I2C_STAT_MONACTIVE_MASK (0x40000U) +#define I2C_STAT_MONACTIVE_SHIFT (18U) +/*! MONACTIVE - Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to + * be active. Active is defined here as when some Master is on the bus: a bus Start has occurred + * more recently than a bus Stop. + * 0b0..Inactive. The Monitor function considers the I2C bus to be inactive. + * 0b1..Active. The Monitor function considers the I2C bus to be active. + */ +#define I2C_STAT_MONACTIVE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONACTIVE_SHIFT)) & I2C_STAT_MONACTIVE_MASK) +#define I2C_STAT_MONIDLE_MASK (0x80000U) +#define I2C_STAT_MONIDLE_SHIFT (19U) +/*! MONIDLE - Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change + * from active to inactive. This can be used by software to decide when to process data + * accumulated by the Monitor function. This flag will cause an interrupt when set if enabled via the + * INTENSET register. The flag can be cleared by writing a 1 to this bit. + * 0b0..Not idle. The I2C bus is not idle, or this flag has been cleared by software. + * 0b1..Idle. The I2C bus has gone idle at least once since the last time this flag was cleared by software. + */ +#define I2C_STAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONIDLE_SHIFT)) & I2C_STAT_MONIDLE_MASK) +#define I2C_STAT_EVENTTIMEOUT_MASK (0x1000000U) +#define I2C_STAT_EVENTTIMEOUT_SHIFT (24U) +/*! EVENTTIMEOUT - Event Time-out Interrupt flag. Indicates when the time between events has been + * longer than the time specified by the TIMEOUT register. Events include Start, Stop, and clock + * edges. The flag is cleared by writing a 1 to this bit. No time-out is created when the I2C-bus + * is idle. + * 0b0..No time-out. I2C bus events have not caused a time-out. + * 0b1..Event time-out. The time between I2C bus events has been longer than the time specified by the TIMEOUT register. + */ +#define I2C_STAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_EVENTTIMEOUT_SHIFT)) & I2C_STAT_EVENTTIMEOUT_MASK) +#define I2C_STAT_SCLTIMEOUT_MASK (0x2000000U) +#define I2C_STAT_SCLTIMEOUT_SHIFT (25U) +/*! SCLTIMEOUT - SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the + * time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit. + * 0b0..No time-out. SCL low time has not caused a time-out. + * 0b1..Time-out. SCL low time has caused a time-out. + */ +#define I2C_STAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SCLTIMEOUT_SHIFT)) & I2C_STAT_SCLTIMEOUT_MASK) +/*! @} */ + +/*! @name INTENSET - Interrupt Enable Set and read register. */ +/*! @{ */ +#define I2C_INTENSET_MSTPENDINGEN_MASK (0x1U) +#define I2C_INTENSET_MSTPENDINGEN_SHIFT (0U) +/*! MSTPENDINGEN - Master Pending interrupt Enable. + * 0b0..Disabled. The MstPending interrupt is disabled. + * 0b1..Enabled. The MstPending interrupt is enabled. + */ +#define I2C_INTENSET_MSTPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTPENDINGEN_SHIFT)) & I2C_INTENSET_MSTPENDINGEN_MASK) +#define I2C_INTENSET_MSTARBLOSSEN_MASK (0x10U) +#define I2C_INTENSET_MSTARBLOSSEN_SHIFT (4U) +/*! MSTARBLOSSEN - Master Arbitration Loss interrupt Enable. + * 0b0..Disabled. The MstArbLoss interrupt is disabled. + * 0b1..Enabled. The MstArbLoss interrupt is enabled. + */ +#define I2C_INTENSET_MSTARBLOSSEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTARBLOSSEN_SHIFT)) & I2C_INTENSET_MSTARBLOSSEN_MASK) +#define I2C_INTENSET_MSTSTSTPERREN_MASK (0x40U) +#define I2C_INTENSET_MSTSTSTPERREN_SHIFT (6U) +/*! MSTSTSTPERREN - Master Start/Stop Error interrupt Enable. + * 0b0..Disabled. The MstStStpErr interrupt is disabled. + * 0b1..Enabled. The MstStStpErr interrupt is enabled. + */ +#define I2C_INTENSET_MSTSTSTPERREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTSTSTPERREN_SHIFT)) & I2C_INTENSET_MSTSTSTPERREN_MASK) +#define I2C_INTENSET_SLVPENDINGEN_MASK (0x100U) +#define I2C_INTENSET_SLVPENDINGEN_SHIFT (8U) +/*! SLVPENDINGEN - Slave Pending interrupt Enable. + * 0b0..Disabled. The SlvPending interrupt is disabled. + * 0b1..Enabled. The SlvPending interrupt is enabled. + */ +#define I2C_INTENSET_SLVPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVPENDINGEN_SHIFT)) & I2C_INTENSET_SLVPENDINGEN_MASK) +#define I2C_INTENSET_SLVNOTSTREN_MASK (0x800U) +#define I2C_INTENSET_SLVNOTSTREN_SHIFT (11U) +/*! SLVNOTSTREN - Slave Not Stretching interrupt Enable. + * 0b0..Disabled. The SlvNotStr interrupt is disabled. + * 0b1..Enabled. The SlvNotStr interrupt is enabled. + */ +#define I2C_INTENSET_SLVNOTSTREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVNOTSTREN_SHIFT)) & I2C_INTENSET_SLVNOTSTREN_MASK) +#define I2C_INTENSET_SLVDESELEN_MASK (0x8000U) +#define I2C_INTENSET_SLVDESELEN_SHIFT (15U) +/*! SLVDESELEN - Slave Deselect interrupt Enable. + * 0b0..Disabled. The SlvDeSel interrupt is disabled. + * 0b1..Enabled. The SlvDeSel interrupt is enabled. + */ +#define I2C_INTENSET_SLVDESELEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVDESELEN_SHIFT)) & I2C_INTENSET_SLVDESELEN_MASK) +#define I2C_INTENSET_MONRDYEN_MASK (0x10000U) +#define I2C_INTENSET_MONRDYEN_SHIFT (16U) +/*! MONRDYEN - Monitor data Ready interrupt Enable. + * 0b0..Disabled. The MonRdy interrupt is disabled. + * 0b1..Enabled. The MonRdy interrupt is enabled. + */ +#define I2C_INTENSET_MONRDYEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONRDYEN_SHIFT)) & I2C_INTENSET_MONRDYEN_MASK) +#define I2C_INTENSET_MONOVEN_MASK (0x20000U) +#define I2C_INTENSET_MONOVEN_SHIFT (17U) +/*! MONOVEN - Monitor Overrun interrupt Enable. + * 0b0..Disabled. The MonOv interrupt is disabled. + * 0b1..Enabled. The MonOv interrupt is enabled. + */ +#define I2C_INTENSET_MONOVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONOVEN_SHIFT)) & I2C_INTENSET_MONOVEN_MASK) +#define I2C_INTENSET_MONIDLEEN_MASK (0x80000U) +#define I2C_INTENSET_MONIDLEEN_SHIFT (19U) +/*! MONIDLEEN - Monitor Idle interrupt Enable. + * 0b0..Disabled. The MonIdle interrupt is disabled. + * 0b1..Enabled. The MonIdle interrupt is enabled. + */ +#define I2C_INTENSET_MONIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONIDLEEN_SHIFT)) & I2C_INTENSET_MONIDLEEN_MASK) +#define I2C_INTENSET_EVENTTIMEOUTEN_MASK (0x1000000U) +#define I2C_INTENSET_EVENTTIMEOUTEN_SHIFT (24U) +/*! EVENTTIMEOUTEN - Event time-out interrupt Enable. + * 0b0..Disabled. The Event time-out interrupt is disabled. + * 0b1..Enabled. The Event time-out interrupt is enabled. + */ +#define I2C_INTENSET_EVENTTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_EVENTTIMEOUTEN_SHIFT)) & I2C_INTENSET_EVENTTIMEOUTEN_MASK) +#define I2C_INTENSET_SCLTIMEOUTEN_MASK (0x2000000U) +#define I2C_INTENSET_SCLTIMEOUTEN_SHIFT (25U) +/*! SCLTIMEOUTEN - SCL time-out interrupt Enable. + * 0b0..Disabled. The SCL time-out interrupt is disabled. + * 0b1..Enabled. The SCL time-out interrupt is enabled. + */ +#define I2C_INTENSET_SCLTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SCLTIMEOUTEN_SHIFT)) & I2C_INTENSET_SCLTIMEOUTEN_MASK) +/*! @} */ + +/*! @name INTENCLR - Interrupt Enable Clear register. */ +/*! @{ */ +#define I2C_INTENCLR_MSTPENDINGCLR_MASK (0x1U) +#define I2C_INTENCLR_MSTPENDINGCLR_SHIFT (0U) +#define I2C_INTENCLR_MSTPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTPENDINGCLR_SHIFT)) & I2C_INTENCLR_MSTPENDINGCLR_MASK) +#define I2C_INTENCLR_MSTARBLOSSCLR_MASK (0x10U) +#define I2C_INTENCLR_MSTARBLOSSCLR_SHIFT (4U) +#define I2C_INTENCLR_MSTARBLOSSCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTARBLOSSCLR_SHIFT)) & I2C_INTENCLR_MSTARBLOSSCLR_MASK) +#define I2C_INTENCLR_MSTSTSTPERRCLR_MASK (0x40U) +#define I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT (6U) +#define I2C_INTENCLR_MSTSTSTPERRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT)) & I2C_INTENCLR_MSTSTSTPERRCLR_MASK) +#define I2C_INTENCLR_SLVPENDINGCLR_MASK (0x100U) +#define I2C_INTENCLR_SLVPENDINGCLR_SHIFT (8U) +#define I2C_INTENCLR_SLVPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVPENDINGCLR_SHIFT)) & I2C_INTENCLR_SLVPENDINGCLR_MASK) +#define I2C_INTENCLR_SLVNOTSTRCLR_MASK (0x800U) +#define I2C_INTENCLR_SLVNOTSTRCLR_SHIFT (11U) +#define I2C_INTENCLR_SLVNOTSTRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVNOTSTRCLR_SHIFT)) & I2C_INTENCLR_SLVNOTSTRCLR_MASK) +#define I2C_INTENCLR_SLVDESELCLR_MASK (0x8000U) +#define I2C_INTENCLR_SLVDESELCLR_SHIFT (15U) +#define I2C_INTENCLR_SLVDESELCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVDESELCLR_SHIFT)) & I2C_INTENCLR_SLVDESELCLR_MASK) +#define I2C_INTENCLR_MONRDYCLR_MASK (0x10000U) +#define I2C_INTENCLR_MONRDYCLR_SHIFT (16U) +#define I2C_INTENCLR_MONRDYCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONRDYCLR_SHIFT)) & I2C_INTENCLR_MONRDYCLR_MASK) +#define I2C_INTENCLR_MONOVCLR_MASK (0x20000U) +#define I2C_INTENCLR_MONOVCLR_SHIFT (17U) +#define I2C_INTENCLR_MONOVCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONOVCLR_SHIFT)) & I2C_INTENCLR_MONOVCLR_MASK) +#define I2C_INTENCLR_MONIDLECLR_MASK (0x80000U) +#define I2C_INTENCLR_MONIDLECLR_SHIFT (19U) +#define I2C_INTENCLR_MONIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONIDLECLR_SHIFT)) & I2C_INTENCLR_MONIDLECLR_MASK) +#define I2C_INTENCLR_EVENTTIMEOUTCLR_MASK (0x1000000U) +#define I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT (24U) +#define I2C_INTENCLR_EVENTTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_EVENTTIMEOUTCLR_MASK) +#define I2C_INTENCLR_SCLTIMEOUTCLR_MASK (0x2000000U) +#define I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT (25U) +#define I2C_INTENCLR_SCLTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_SCLTIMEOUTCLR_MASK) +/*! @} */ + +/*! @name TIMEOUT - Time-out value register. */ +/*! @{ */ +#define I2C_TIMEOUT_TOMIN_MASK (0xFU) +#define I2C_TIMEOUT_TOMIN_SHIFT (0U) +#define I2C_TIMEOUT_TOMIN(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TOMIN_SHIFT)) & I2C_TIMEOUT_TOMIN_MASK) +#define I2C_TIMEOUT_TO_MASK (0xFFF0U) +#define I2C_TIMEOUT_TO_SHIFT (4U) +#define I2C_TIMEOUT_TO(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TO_SHIFT)) & I2C_TIMEOUT_TO_MASK) +/*! @} */ + +/*! @name CLKDIV - Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function. */ +/*! @{ */ +#define I2C_CLKDIV_DIVVAL_MASK (0xFFFFU) +#define I2C_CLKDIV_DIVVAL_SHIFT (0U) +#define I2C_CLKDIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << I2C_CLKDIV_DIVVAL_SHIFT)) & I2C_CLKDIV_DIVVAL_MASK) +/*! @} */ + +/*! @name INTSTAT - Interrupt Status register for Master, Slave, and Monitor functions. */ +/*! @{ */ +#define I2C_INTSTAT_MSTPENDING_MASK (0x1U) +#define I2C_INTSTAT_MSTPENDING_SHIFT (0U) +#define I2C_INTSTAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTPENDING_SHIFT)) & I2C_INTSTAT_MSTPENDING_MASK) +#define I2C_INTSTAT_MSTARBLOSS_MASK (0x10U) +#define I2C_INTSTAT_MSTARBLOSS_SHIFT (4U) +#define I2C_INTSTAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTARBLOSS_SHIFT)) & I2C_INTSTAT_MSTARBLOSS_MASK) +#define I2C_INTSTAT_MSTSTSTPERR_MASK (0x40U) +#define I2C_INTSTAT_MSTSTSTPERR_SHIFT (6U) +#define I2C_INTSTAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTSTSTPERR_SHIFT)) & I2C_INTSTAT_MSTSTSTPERR_MASK) +#define I2C_INTSTAT_SLVPENDING_MASK (0x100U) +#define I2C_INTSTAT_SLVPENDING_SHIFT (8U) +#define I2C_INTSTAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVPENDING_SHIFT)) & I2C_INTSTAT_SLVPENDING_MASK) +#define I2C_INTSTAT_SLVNOTSTR_MASK (0x800U) +#define I2C_INTSTAT_SLVNOTSTR_SHIFT (11U) +#define I2C_INTSTAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVNOTSTR_SHIFT)) & I2C_INTSTAT_SLVNOTSTR_MASK) +#define I2C_INTSTAT_SLVDESEL_MASK (0x8000U) +#define I2C_INTSTAT_SLVDESEL_SHIFT (15U) +#define I2C_INTSTAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVDESEL_SHIFT)) & I2C_INTSTAT_SLVDESEL_MASK) +#define I2C_INTSTAT_MONRDY_MASK (0x10000U) +#define I2C_INTSTAT_MONRDY_SHIFT (16U) +#define I2C_INTSTAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONRDY_SHIFT)) & I2C_INTSTAT_MONRDY_MASK) +#define I2C_INTSTAT_MONOV_MASK (0x20000U) +#define I2C_INTSTAT_MONOV_SHIFT (17U) +#define I2C_INTSTAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONOV_SHIFT)) & I2C_INTSTAT_MONOV_MASK) +#define I2C_INTSTAT_MONIDLE_MASK (0x80000U) +#define I2C_INTSTAT_MONIDLE_SHIFT (19U) +#define I2C_INTSTAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONIDLE_SHIFT)) & I2C_INTSTAT_MONIDLE_MASK) +#define I2C_INTSTAT_EVENTTIMEOUT_MASK (0x1000000U) +#define I2C_INTSTAT_EVENTTIMEOUT_SHIFT (24U) +#define I2C_INTSTAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_EVENTTIMEOUT_SHIFT)) & I2C_INTSTAT_EVENTTIMEOUT_MASK) +#define I2C_INTSTAT_SCLTIMEOUT_MASK (0x2000000U) +#define I2C_INTSTAT_SCLTIMEOUT_SHIFT (25U) +#define I2C_INTSTAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SCLTIMEOUT_SHIFT)) & I2C_INTSTAT_SCLTIMEOUT_MASK) +/*! @} */ + +/*! @name MSTCTL - Master control register. */ +/*! @{ */ +#define I2C_MSTCTL_MSTCONTINUE_MASK (0x1U) +#define I2C_MSTCTL_MSTCONTINUE_SHIFT (0U) +/*! MSTCONTINUE - Master Continue. This bit is write-only. + * 0b0..No effect. + * 0b1..Continue. Informs the Master function to continue to the next operation. This must done after writing + * transmit data, reading received data, or any other housekeeping related to the next bus operation. + */ +#define I2C_MSTCTL_MSTCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTCONTINUE_SHIFT)) & I2C_MSTCTL_MSTCONTINUE_MASK) +#define I2C_MSTCTL_MSTSTART_MASK (0x2U) +#define I2C_MSTCTL_MSTSTART_SHIFT (1U) +/*! MSTSTART - Master Start control. This bit is write-only. + * 0b0..No effect. + * 0b1..Start. A Start will be generated on the I2C bus at the next allowed time. + */ +#define I2C_MSTCTL_MSTSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTART_SHIFT)) & I2C_MSTCTL_MSTSTART_MASK) +#define I2C_MSTCTL_MSTSTOP_MASK (0x4U) +#define I2C_MSTCTL_MSTSTOP_SHIFT (2U) +/*! MSTSTOP - Master Stop control. This bit is write-only. + * 0b0..No effect. + * 0b1..Stop. A Stop will be generated on the I2C bus at the next allowed time, preceded by a NACK to the slave + * if the master is receiving data from the slave (Master Receiver mode). + */ +#define I2C_MSTCTL_MSTSTOP(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTOP_SHIFT)) & I2C_MSTCTL_MSTSTOP_MASK) +#define I2C_MSTCTL_MSTDMA_MASK (0x8U) +#define I2C_MSTCTL_MSTDMA_SHIFT (3U) +/*! MSTDMA - Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type + * operations such as Start, address, Stop, and address match must always be done with software, + * typically via an interrupt. Address acknowledgement must also be done by software except when + * the I2C is configured to be HSCAPABLE (and address acknowledgement is handled entirely by + * hardware) or when Automatic Operation is enabled. When a DMA data transfer is complete, MSTDMA + * must be cleared prior to beginning the next operation, typically a Start or Stop.This bit is + * read/write. + * 0b0..Disable. No DMA requests are generated for master operation. + * 0b1..Enable. A DMA request is generated for I2C master data operations. When this I2C master is generating + * Acknowledge bits in Master Receiver mode, the acknowledge is generated automatically. + */ +#define I2C_MSTCTL_MSTDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTDMA_SHIFT)) & I2C_MSTCTL_MSTDMA_MASK) +/*! @} */ + +/*! @name MSTTIME - Master timing configuration. */ +/*! @{ */ +#define I2C_MSTTIME_MSTSCLLOW_MASK (0x7U) +#define I2C_MSTTIME_MSTSCLLOW_SHIFT (0U) +/*! MSTSCLLOW - Master SCL Low time. Specifies the minimum low time that will be asserted by this + * master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This + * corresponds to the parameter t LOW in the I2C bus specification. I2C bus specification parameters + * tBUF and tSU;STA have the same values and are also controlled by MSTSCLLOW. + * 0b000..2 clocks. Minimum SCL low time is 2 clocks of the I2C clock pre-divider. + * 0b001..3 clocks. Minimum SCL low time is 3 clocks of the I2C clock pre-divider. + * 0b010..4 clocks. Minimum SCL low time is 4 clocks of the I2C clock pre-divider. + * 0b011..5 clocks. Minimum SCL low time is 5 clocks of the I2C clock pre-divider. + * 0b100..6 clocks. Minimum SCL low time is 6 clocks of the I2C clock pre-divider. + * 0b101..7 clocks. Minimum SCL low time is 7 clocks of the I2C clock pre-divider. + * 0b110..8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider. + * 0b111..9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider. + */ +#define I2C_MSTTIME_MSTSCLLOW(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLLOW_SHIFT)) & I2C_MSTTIME_MSTSCLLOW_MASK) +#define I2C_MSTTIME_MSTSCLHIGH_MASK (0x70U) +#define I2C_MSTTIME_MSTSCLHIGH_SHIFT (4U) +/*! MSTSCLHIGH - Master SCL High time. Specifies the minimum high time that will be asserted by this + * master on SCL. Other masters in a multi-master system could shorten this time. This + * corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters + * tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH. + * 0b000..2 clocks. Minimum SCL high time is 2 clock of the I2C clock pre-divider. + * 0b001..3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider . + * 0b010..4 clocks. Minimum SCL high time is 4 clock of the I2C clock pre-divider. + * 0b011..5 clocks. Minimum SCL high time is 5 clock of the I2C clock pre-divider. + * 0b100..6 clocks. Minimum SCL high time is 6 clock of the I2C clock pre-divider. + * 0b101..7 clocks. Minimum SCL high time is 7 clock of the I2C clock pre-divider. + * 0b110..8 clocks. Minimum SCL high time is 8 clock of the I2C clock pre-divider. + * 0b111..9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider. + */ +#define I2C_MSTTIME_MSTSCLHIGH(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLHIGH_SHIFT)) & I2C_MSTTIME_MSTSCLHIGH_MASK) +/*! @} */ + +/*! @name MSTDAT - Combined Master receiver and transmitter data register. */ +/*! @{ */ +#define I2C_MSTDAT_DATA_MASK (0xFFU) +#define I2C_MSTDAT_DATA_SHIFT (0U) +#define I2C_MSTDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTDAT_DATA_SHIFT)) & I2C_MSTDAT_DATA_MASK) +/*! @} */ + +/*! @name SLVCTL - Slave control register. */ +/*! @{ */ +#define I2C_SLVCTL_SLVCONTINUE_MASK (0x1U) +#define I2C_SLVCTL_SLVCONTINUE_SHIFT (0U) +/*! SLVCONTINUE - Slave Continue. + * 0b0..No effect. + * 0b1..Continue. Informs the Slave function to continue to the next operation, by clearing the SLVPENDING flag + * in the STAT register. This must be done after writing transmit data, reading received data, or any other + * housekeeping related to the next bus operation. Automatic Operation has different requirements. SLVCONTINUE + * should not be set unless SLVPENDING = 1. + */ +#define I2C_SLVCTL_SLVCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVCONTINUE_SHIFT)) & I2C_SLVCTL_SLVCONTINUE_MASK) +#define I2C_SLVCTL_SLVNACK_MASK (0x2U) +#define I2C_SLVCTL_SLVNACK_SHIFT (1U) +/*! SLVNACK - Slave NACK. + * 0b0..No effect. + * 0b1..NACK. Causes the Slave function to NACK the master when the slave is receiving data from the master (Slave Receiver mode). + */ +#define I2C_SLVCTL_SLVNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVNACK_SHIFT)) & I2C_SLVCTL_SLVNACK_MASK) +#define I2C_SLVCTL_SLVDMA_MASK (0x8U) +#define I2C_SLVCTL_SLVDMA_SHIFT (3U) +/*! SLVDMA - Slave DMA enable. + * 0b0..Disabled. No DMA requests are issued for Slave mode operation. + * 0b1..Enabled. DMA requests are issued for I2C slave data transmission and reception. + */ +#define I2C_SLVCTL_SLVDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVDMA_SHIFT)) & I2C_SLVCTL_SLVDMA_MASK) +#define I2C_SLVCTL_AUTOACK_MASK (0x100U) +#define I2C_SLVCTL_AUTOACK_SHIFT (8U) +/*! AUTOACK - Automatic Acknowledge.When this bit is set, it will cause an I2C header which matches + * SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA + * to allow processing of the data without intervention. If this bit is clear and a header + * matches SLVADR0, the behavior is controlled by AUTONACK in the SLVADR0 register: allowing NACK or + * interrupt. + * 0b0..Normal, non-automatic operation. If AUTONACK = 0, an SlvPending interrupt is generated when a matching + * address is received. If AUTONACK = 1, received addresses are NACKed (ignored). + * 0b1..A header with matching SLVADR0 and matching direction as set by AUTOMATCHREAD will be ACKed immediately, + * allowing the master to move on to the data bytes. If the address matches SLVADR0, but the direction does + * not match AUTOMATCHREAD, the behavior will depend on the AUTONACK bit in the SLVADR0 register: if AUTONACK + * is set, then it will be Nacked; else if AUTONACK is clear, then a SlvPending interrupt is generated. + */ +#define I2C_SLVCTL_AUTOACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOACK_SHIFT)) & I2C_SLVCTL_AUTOACK_MASK) +#define I2C_SLVCTL_AUTOMATCHREAD_MASK (0x200U) +#define I2C_SLVCTL_AUTOMATCHREAD_SHIFT (9U) +/*! AUTOMATCHREAD - When AUTOACK is set, this bit controls whether it matches a read or write + * request on the next header with an address matching SLVADR0. Since DMA needs to be configured to + * match the transfer direction, the direction needs to be specified. This bit allows a direction to + * be chosen for the next operation. + * 0b0..The expected next operation in Automatic Mode is an I2C write. + * 0b1..The expected next operation in Automatic Mode is an I2C read. + */ +#define I2C_SLVCTL_AUTOMATCHREAD(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOMATCHREAD_SHIFT)) & I2C_SLVCTL_AUTOMATCHREAD_MASK) +/*! @} */ + +/*! @name SLVDAT - Combined Slave receiver and transmitter data register. */ +/*! @{ */ +#define I2C_SLVDAT_DATA_MASK (0xFFU) +#define I2C_SLVDAT_DATA_SHIFT (0U) +#define I2C_SLVDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVDAT_DATA_SHIFT)) & I2C_SLVDAT_DATA_MASK) +/*! @} */ + +/*! @name SLVADR - Slave address register. */ +/*! @{ */ +#define I2C_SLVADR_SADISABLE_MASK (0x1U) +#define I2C_SLVADR_SADISABLE_SHIFT (0U) +/*! SADISABLE - Slave Address n Disable. + * 0b0..Enabled. Slave Address n is enabled. + * 0b1..Ignored Slave Address n is ignored. + */ +#define I2C_SLVADR_SADISABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SADISABLE_SHIFT)) & I2C_SLVADR_SADISABLE_MASK) +#define I2C_SLVADR_SLVADR_MASK (0xFEU) +#define I2C_SLVADR_SLVADR_SHIFT (1U) +#define I2C_SLVADR_SLVADR(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SLVADR_SHIFT)) & I2C_SLVADR_SLVADR_MASK) +#define I2C_SLVADR_AUTONACK_MASK (0x8000U) +#define I2C_SLVADR_AUTONACK_SHIFT (15U) +/*! AUTONACK - Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD, allows + * software to ignore I2C traffic while handling previous I2C data or other operations. + * 0b0..Normal operation, matching I2C addresses are not ignored. + * 0b1..Automatic-only mode. All incoming addresses are ignored (NACKed), unless AUTOACK is set, it matches + * SLVADRn, and AUTOMATCHREAD matches the direction. + */ +#define I2C_SLVADR_AUTONACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_AUTONACK_SHIFT)) & I2C_SLVADR_AUTONACK_MASK) +/*! @} */ + +/* The count of I2C_SLVADR */ +#define I2C_SLVADR_COUNT (4U) + +/*! @name SLVQUAL0 - Slave Qualification for address 0. */ +/*! @{ */ +#define I2C_SLVQUAL0_QUALMODE0_MASK (0x1U) +#define I2C_SLVQUAL0_QUALMODE0_SHIFT (0U) +/*! QUALMODE0 - Qualify mode for slave address 0. + * 0b0..Mask. The SLVQUAL0 field is used as a logical mask for matching address 0. + * 0b1..Extend. The SLVQUAL0 field is used to extend address 0 matching in a range of addresses. + */ +#define I2C_SLVQUAL0_QUALMODE0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_QUALMODE0_SHIFT)) & I2C_SLVQUAL0_QUALMODE0_MASK) +#define I2C_SLVQUAL0_SLVQUAL0_MASK (0xFEU) +#define I2C_SLVQUAL0_SLVQUAL0_SHIFT (1U) +#define I2C_SLVQUAL0_SLVQUAL0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_SLVQUAL0_SHIFT)) & I2C_SLVQUAL0_SLVQUAL0_MASK) +/*! @} */ + +/*! @name MONRXDAT - Monitor receiver data register. */ +/*! @{ */ +#define I2C_MONRXDAT_MONRXDAT_MASK (0xFFU) +#define I2C_MONRXDAT_MONRXDAT_SHIFT (0U) +#define I2C_MONRXDAT_MONRXDAT(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRXDAT_SHIFT)) & I2C_MONRXDAT_MONRXDAT_MASK) +#define I2C_MONRXDAT_MONSTART_MASK (0x100U) +#define I2C_MONRXDAT_MONSTART_SHIFT (8U) +/*! MONSTART - Monitor Received Start. + * 0b0..No start detected. The Monitor function has not detected a Start event on the I2C bus. + * 0b1..Start detected. The Monitor function has detected a Start event on the I2C bus. + */ +#define I2C_MONRXDAT_MONSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONSTART_SHIFT)) & I2C_MONRXDAT_MONSTART_MASK) +#define I2C_MONRXDAT_MONRESTART_MASK (0x200U) +#define I2C_MONRXDAT_MONRESTART_SHIFT (9U) +/*! MONRESTART - Monitor Received Repeated Start. + * 0b0..No repeated start detected. The Monitor function has not detected a Repeated Start event on the I2C bus. + * 0b1..Repeated start detected. The Monitor function has detected a Repeated Start event on the I2C bus. + */ +#define I2C_MONRXDAT_MONRESTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRESTART_SHIFT)) & I2C_MONRXDAT_MONRESTART_MASK) +#define I2C_MONRXDAT_MONNACK_MASK (0x400U) +#define I2C_MONRXDAT_MONNACK_SHIFT (10U) +/*! MONNACK - Monitor Received NACK. + * 0b0..Acknowledged. The data currently being provided by the Monitor function was acknowledged by at least one master or slave receiver. + * 0b1..Not acknowledged. The data currently being provided by the Monitor function was not acknowledged by any receiver. + */ +#define I2C_MONRXDAT_MONNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONNACK_SHIFT)) & I2C_MONRXDAT_MONNACK_MASK) +/*! @} */ + +/*! @name ID - Peripheral identification register. */ +/*! @{ */ +#define I2C_ID_APERTURE_MASK (0xFFU) +#define I2C_ID_APERTURE_SHIFT (0U) +#define I2C_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_APERTURE_SHIFT)) & I2C_ID_APERTURE_MASK) +#define I2C_ID_MINOR_REV_MASK (0xF00U) +#define I2C_ID_MINOR_REV_SHIFT (8U) +#define I2C_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_MINOR_REV_SHIFT)) & I2C_ID_MINOR_REV_MASK) +#define I2C_ID_MAJOR_REV_MASK (0xF000U) +#define I2C_ID_MAJOR_REV_SHIFT (12U) +#define I2C_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_MAJOR_REV_SHIFT)) & I2C_ID_MAJOR_REV_MASK) +#define I2C_ID_ID_MASK (0xFFFF0000U) +#define I2C_ID_ID_SHIFT (16U) +#define I2C_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_ID_SHIFT)) & I2C_ID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group I2C_Register_Masks */ + + +/* I2C - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral I2C0 base address */ + #define I2C0_BASE (0x50086000u) + /** Peripheral I2C0 base address */ + #define I2C0_BASE_NS (0x40086000u) + /** Peripheral I2C0 base pointer */ + #define I2C0 ((I2C_Type *)I2C0_BASE) + /** Peripheral I2C0 base pointer */ + #define I2C0_NS ((I2C_Type *)I2C0_BASE_NS) + /** Peripheral I2C1 base address */ + #define I2C1_BASE (0x50087000u) + /** Peripheral I2C1 base address */ + #define I2C1_BASE_NS (0x40087000u) + /** Peripheral I2C1 base pointer */ + #define I2C1 ((I2C_Type *)I2C1_BASE) + /** Peripheral I2C1 base pointer */ + #define I2C1_NS ((I2C_Type *)I2C1_BASE_NS) + /** Peripheral I2C2 base address */ + #define I2C2_BASE (0x50088000u) + /** Peripheral I2C2 base address */ + #define I2C2_BASE_NS (0x40088000u) + /** Peripheral I2C2 base pointer */ + #define I2C2 ((I2C_Type *)I2C2_BASE) + /** Peripheral I2C2 base pointer */ + #define I2C2_NS ((I2C_Type *)I2C2_BASE_NS) + /** Peripheral I2C3 base address */ + #define I2C3_BASE (0x50089000u) + /** Peripheral I2C3 base address */ + #define I2C3_BASE_NS (0x40089000u) + /** Peripheral I2C3 base pointer */ + #define I2C3 ((I2C_Type *)I2C3_BASE) + /** Peripheral I2C3 base pointer */ + #define I2C3_NS ((I2C_Type *)I2C3_BASE_NS) + /** Peripheral I2C4 base address */ + #define I2C4_BASE (0x5008A000u) + /** Peripheral I2C4 base address */ + #define I2C4_BASE_NS (0x4008A000u) + /** Peripheral I2C4 base pointer */ + #define I2C4 ((I2C_Type *)I2C4_BASE) + /** Peripheral I2C4 base pointer */ + #define I2C4_NS ((I2C_Type *)I2C4_BASE_NS) + /** Peripheral I2C5 base address */ + #define I2C5_BASE (0x50096000u) + /** Peripheral I2C5 base address */ + #define I2C5_BASE_NS (0x40096000u) + /** Peripheral I2C5 base pointer */ + #define I2C5 ((I2C_Type *)I2C5_BASE) + /** Peripheral I2C5 base pointer */ + #define I2C5_NS ((I2C_Type *)I2C5_BASE_NS) + /** Peripheral I2C6 base address */ + #define I2C6_BASE (0x50097000u) + /** Peripheral I2C6 base address */ + #define I2C6_BASE_NS (0x40097000u) + /** Peripheral I2C6 base pointer */ + #define I2C6 ((I2C_Type *)I2C6_BASE) + /** Peripheral I2C6 base pointer */ + #define I2C6_NS ((I2C_Type *)I2C6_BASE_NS) + /** Peripheral I2C7 base address */ + #define I2C7_BASE (0x50098000u) + /** Peripheral I2C7 base address */ + #define I2C7_BASE_NS (0x40098000u) + /** Peripheral I2C7 base pointer */ + #define I2C7 ((I2C_Type *)I2C7_BASE) + /** Peripheral I2C7 base pointer */ + #define I2C7_NS ((I2C_Type *)I2C7_BASE_NS) + /** Array initializer of I2C peripheral base addresses */ + #define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE, I2C4_BASE, I2C5_BASE, I2C6_BASE, I2C7_BASE } + /** Array initializer of I2C peripheral base pointers */ + #define I2C_BASE_PTRS { I2C0, I2C1, I2C2, I2C3, I2C4, I2C5, I2C6, I2C7 } + /** Array initializer of I2C peripheral base addresses */ + #define I2C_BASE_ADDRS_NS { I2C0_BASE_NS, I2C1_BASE_NS, I2C2_BASE_NS, I2C3_BASE_NS, I2C4_BASE_NS, I2C5_BASE_NS, I2C6_BASE_NS, I2C7_BASE_NS } + /** Array initializer of I2C peripheral base pointers */ + #define I2C_BASE_PTRS_NS { I2C0_NS, I2C1_NS, I2C2_NS, I2C3_NS, I2C4_NS, I2C5_NS, I2C6_NS, I2C7_NS } +#else + /** Peripheral I2C0 base address */ + #define I2C0_BASE (0x40086000u) + /** Peripheral I2C0 base pointer */ + #define I2C0 ((I2C_Type *)I2C0_BASE) + /** Peripheral I2C1 base address */ + #define I2C1_BASE (0x40087000u) + /** Peripheral I2C1 base pointer */ + #define I2C1 ((I2C_Type *)I2C1_BASE) + /** Peripheral I2C2 base address */ + #define I2C2_BASE (0x40088000u) + /** Peripheral I2C2 base pointer */ + #define I2C2 ((I2C_Type *)I2C2_BASE) + /** Peripheral I2C3 base address */ + #define I2C3_BASE (0x40089000u) + /** Peripheral I2C3 base pointer */ + #define I2C3 ((I2C_Type *)I2C3_BASE) + /** Peripheral I2C4 base address */ + #define I2C4_BASE (0x4008A000u) + /** Peripheral I2C4 base pointer */ + #define I2C4 ((I2C_Type *)I2C4_BASE) + /** Peripheral I2C5 base address */ + #define I2C5_BASE (0x40096000u) + /** Peripheral I2C5 base pointer */ + #define I2C5 ((I2C_Type *)I2C5_BASE) + /** Peripheral I2C6 base address */ + #define I2C6_BASE (0x40097000u) + /** Peripheral I2C6 base pointer */ + #define I2C6 ((I2C_Type *)I2C6_BASE) + /** Peripheral I2C7 base address */ + #define I2C7_BASE (0x40098000u) + /** Peripheral I2C7 base pointer */ + #define I2C7 ((I2C_Type *)I2C7_BASE) + /** Array initializer of I2C peripheral base addresses */ + #define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE, I2C4_BASE, I2C5_BASE, I2C6_BASE, I2C7_BASE } + /** Array initializer of I2C peripheral base pointers */ + #define I2C_BASE_PTRS { I2C0, I2C1, I2C2, I2C3, I2C4, I2C5, I2C6, I2C7 } +#endif +/** Interrupt vectors for the I2C peripheral type */ +#define I2C_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } + +/*! + * @} + */ /* end of group I2C_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- I2S Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer + * @{ + */ + +/** I2S - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[3072]; + __IO uint32_t CFG1; /**< Configuration register 1 for the primary channel pair., offset: 0xC00 */ + __IO uint32_t CFG2; /**< Configuration register 2 for the primary channel pair., offset: 0xC04 */ + __IO uint32_t STAT; /**< Status register for the primary channel pair., offset: 0xC08 */ + uint8_t RESERVED_1[16]; + __IO uint32_t DIV; /**< Clock divider, used by all channel pairs., offset: 0xC1C */ + struct { /* offset: 0xC20, array step: 0x20 */ + __IO uint32_t PCFG1; /**< Configuration register 1 for channel pair, array offset: 0xC20, array step: 0x20 */ + __IO uint32_t PCFG2; /**< Configuration register 2 for channel pair, array offset: 0xC24, array step: 0x20 */ + __IO uint32_t PSTAT; /**< Status register for channel pair, array offset: 0xC28, array step: 0x20 */ + uint8_t RESERVED_0[20]; + } SECCHANNEL[3]; + uint8_t RESERVED_2[384]; + __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */ + __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ + __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */ + uint8_t RESERVED_3[4]; + __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */ + __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */ + __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */ + uint8_t RESERVED_4[4]; + __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ + __O uint32_t FIFOWR48H; /**< FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE24 */ + uint8_t RESERVED_5[8]; + __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */ + __I uint32_t FIFORD48H; /**< FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE34 */ + uint8_t RESERVED_6[8]; + __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */ + __I uint32_t FIFORD48HNOPOP; /**< FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE44 */ + uint8_t RESERVED_7[436]; + __I uint32_t ID; /**< I2S Module identification, offset: 0xFFC */ +} I2S_Type; + +/* ---------------------------------------------------------------------------- + -- I2S Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2S_Register_Masks I2S Register Masks + * @{ + */ + +/*! @name CFG1 - Configuration register 1 for the primary channel pair. */ +/*! @{ */ +#define I2S_CFG1_MAINENABLE_MASK (0x1U) +#define I2S_CFG1_MAINENABLE_SHIFT (0U) +/*! MAINENABLE - Main enable for I 2S function in this Flexcomm + * 0b0..All I 2S channel pairs in this Flexcomm are disabled and the internal state machines, counters, and flags + * are reset. No other channel pairs can be enabled. + * 0b1..This I 2S channel pair is enabled. Other channel pairs in this Flexcomm may be enabled in their individual PAIRENABLE bits. + */ +#define I2S_CFG1_MAINENABLE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MAINENABLE_SHIFT)) & I2S_CFG1_MAINENABLE_MASK) +#define I2S_CFG1_DATAPAUSE_MASK (0x2U) +#define I2S_CFG1_DATAPAUSE_SHIFT (1U) +/*! DATAPAUSE - Data flow Pause. Allows pausing data flow between the I2S serializer/deserializer + * and the FIFO. This could be done in order to change streams, or while restarting after a data + * underflow or overflow. When paused, FIFO operations can be done without corrupting data that is + * in the process of being sent or received. Once a data pause has been requested, the interface + * may need to complete sending data that was in progress before interrupting the flow of data. + * Software must check that the pause is actually in effect before taking action. This is done by + * monitoring the DATAPAUSED flag in the STAT register. When DATAPAUSE is cleared, data transfer + * will resume at the beginning of the next frame. + * 0b0..Normal operation, or resuming normal operation at the next frame if the I2S has already been paused. + * 0b1..A pause in the data flow is being requested. It is in effect when DATAPAUSED in STAT = 1. + */ +#define I2S_CFG1_DATAPAUSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATAPAUSE_SHIFT)) & I2S_CFG1_DATAPAUSE_MASK) +#define I2S_CFG1_PAIRCOUNT_MASK (0xCU) +#define I2S_CFG1_PAIRCOUNT_SHIFT (2U) +/*! PAIRCOUNT - Provides the number of I2S channel pairs in this Flexcomm This is a read-only field + * whose value may be different in other Flexcomms. 00 = there is 1 I2S channel pair in this + * Flexcomm. 01 = there are 2 I2S channel pairs in this Flexcomm. 10 = there are 3 I2S channel pairs + * in this Flexcomm. 11 = there are 4 I2S channel pairs in this Flexcomm. + * 0b00..1 I2S channel pairs in this flexcomm + * 0b01..2 I2S channel pairs in this flexcomm + * 0b10..3 I2S channel pairs in this flexcomm + * 0b11..4 I2S channel pairs in this flexcomm + */ +#define I2S_CFG1_PAIRCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_PAIRCOUNT_SHIFT)) & I2S_CFG1_PAIRCOUNT_MASK) +#define I2S_CFG1_MSTSLVCFG_MASK (0x30U) +#define I2S_CFG1_MSTSLVCFG_SHIFT (4U) +/*! MSTSLVCFG - Master / slave configuration selection, determining how SCK and WS are used by all channel pairs in this Flexcomm. + * 0b00..Normal slave mode, the default mode. SCK and WS are received from a master and used to transmit or receive data. + * 0b01..WS synchronized master. WS is received from another master and used to synchronize the generation of + * SCK, when divided from the Flexcomm function clock. + * 0b10..Master using an existing SCK. SCK is received and used directly to generate WS, as well as transmitting or receiving data. + * 0b11..Normal master mode. SCK and WS are generated so they can be sent to one or more slave devices. + */ +#define I2S_CFG1_MSTSLVCFG(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MSTSLVCFG_SHIFT)) & I2S_CFG1_MSTSLVCFG_MASK) +#define I2S_CFG1_MODE_MASK (0xC0U) +#define I2S_CFG1_MODE_SHIFT (6U) +/*! MODE - Selects the basic I2S operating mode. Other configurations modify this to obtain all + * supported cases. See Formats and modes for examples. + * 0b00..I2S mode a.k.a. 'classic' mode. WS has a 50% duty cycle, with (for each enabled channel pair) one piece + * of left channel data occurring during the first phase, and one pieces of right channel data occurring + * during the second phase. In this mode, the data region begins one clock after the leading WS edge for the + * frame. For a 50% WS duty cycle, FRAMELEN must define an even number of I2S clocks for the frame. If + * FRAMELEN defines an odd number of clocks per frame, the extra clock will occur on the right. + * 0b01..DSP mode where WS has a 50% duty cycle. See remark for mode 0. + * 0b10..DSP mode where WS has a one clock long pulse at the beginning of each data frame. + * 0b11..DSP mode where WS has a one data slot long pulse at the beginning of each data frame. + */ +#define I2S_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MODE_SHIFT)) & I2S_CFG1_MODE_MASK) +#define I2S_CFG1_RIGHTLOW_MASK (0x100U) +#define I2S_CFG1_RIGHTLOW_SHIFT (8U) +/*! RIGHTLOW - Right channel data is in the Low portion of FIFO data. Essentially, this swaps left + * and right channel data as it is transferred to or from the FIFO. This bit is not used if the + * data width is greater than 24 bits or if PDMDATA = 1. Note that if the ONECHANNEL field (bit 10 + * of this register) = 1, the one channel to be used is the nominally the left channel. POSITION + * can still place that data in the frame where right channel data is normally located. if all + * enabled channel pairs have ONECHANNEL = 1, then RIGHTLOW = 1 is not allowed. + * 0b0..The right channel is taken from the high part of the FIFO data. For example, when data is 16 bits, FIFO + * bits 31:16 are used for the right channel. + * 0b1..The right channel is taken from the low part of the FIFO data. For example, when data is 16 bits, FIFO + * bits 15:0 are used for the right channel. + */ +#define I2S_CFG1_RIGHTLOW(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_RIGHTLOW_SHIFT)) & I2S_CFG1_RIGHTLOW_MASK) +#define I2S_CFG1_LEFTJUST_MASK (0x200U) +#define I2S_CFG1_LEFTJUST_SHIFT (9U) +/*! LEFTJUST - Left Justify data. + * 0b0..Data is transferred between the FIFO and the I2S serializer/deserializer right justified, i.e. starting + * from bit 0 and continuing to the position defined by DATALEN. This would correspond to right justified data + * in the stream on the data bus. + * 0b1..Data is transferred between the FIFO and the I2S serializer/deserializer left justified, i.e. starting + * from the MSB of the FIFO entry and continuing for the number of bits defined by DATALEN. This would + * correspond to left justified data in the stream on the data bus. + */ +#define I2S_CFG1_LEFTJUST(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_LEFTJUST_SHIFT)) & I2S_CFG1_LEFTJUST_MASK) +#define I2S_CFG1_ONECHANNEL_MASK (0x400U) +#define I2S_CFG1_ONECHANNEL_SHIFT (10U) +/*! ONECHANNEL - Single channel mode. Applies to both transmit and receive. This configuration bit + * applies only to the first I2S channel pair. Other channel pairs may select this mode + * independently in their separate CFG1 registers. + * 0b0..I2S data for this channel pair is treated as left and right channels. + * 0b1..I2S data for this channel pair is treated as a single channel, functionally the left channel for this + * pair. In mode 0 only, the right side of the frame begins at POSITION = 0x100. This is because mode 0 makes a + * clear distinction between the left and right sides of the frame. When ONECHANNEL = 1, the single channel + * of data may be placed on the right by setting POSITION to 0x100 + the data position within the right side + * (e.g. 0x108 would place data starting at the 8th clock after the middle of the frame). In other modes, data + * for the single channel of data is placed at the clock defined by POSITION. + */ +#define I2S_CFG1_ONECHANNEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_ONECHANNEL_SHIFT)) & I2S_CFG1_ONECHANNEL_MASK) +#define I2S_CFG1_PDMDATA_MASK (0x800U) +#define I2S_CFG1_PDMDATA_SHIFT (11U) +/*! PDMDATA - PDM Data selection. This bit controls the data source for I2S transmit, and cannot be + * set in Rx mode. This bit only has an effect if the device the Flexcomm resides in includes a + * D-Mic subsystem. For the LPC55xx, this bit applies only to Flexcomm 6,7. + * 0b0..Normal operation, data is transferred to or from the Flexcomm FIFO. + * 0b1..The data source is the D-Mic subsystem. When PDMDATA = 1, only the primary channel pair can be used in + * this Flexcomm. If ONECHANNEL = 1, only the PDM left data is used. the WS rate must match the Fs (sample + * rate) of the D-Mic decimator. A rate mismatch will at some point cause the I2S to overrun or underrun. + */ +#define I2S_CFG1_PDMDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_PDMDATA_SHIFT)) & I2S_CFG1_PDMDATA_MASK) +#define I2S_CFG1_SCK_POL_MASK (0x1000U) +#define I2S_CFG1_SCK_POL_SHIFT (12U) +/*! SCK_POL - SCK polarity. + * 0b0..Data is launched on SCK falling edges and sampled on SCK rising edges (standard for I2S). + * 0b1..Data is launched on SCK rising edges and sampled on SCK falling edges. + */ +#define I2S_CFG1_SCK_POL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_SCK_POL_SHIFT)) & I2S_CFG1_SCK_POL_MASK) +#define I2S_CFG1_WS_POL_MASK (0x2000U) +#define I2S_CFG1_WS_POL_SHIFT (13U) +/*! WS_POL - WS polarity. + * 0b0..Data frames begin at a falling edge of WS (standard for classic I2S). + * 0b1..WS is inverted, resulting in a data frame beginning at a rising edge of WS (standard for most 'non-classic' variations of I2S). + */ +#define I2S_CFG1_WS_POL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_WS_POL_SHIFT)) & I2S_CFG1_WS_POL_MASK) +#define I2S_CFG1_DATALEN_MASK (0x1F0000U) +#define I2S_CFG1_DATALEN_SHIFT (16U) +#define I2S_CFG1_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATALEN_SHIFT)) & I2S_CFG1_DATALEN_MASK) +/*! @} */ + +/*! @name CFG2 - Configuration register 2 for the primary channel pair. */ +/*! @{ */ +#define I2S_CFG2_FRAMELEN_MASK (0x1FFU) +#define I2S_CFG2_FRAMELEN_SHIFT (0U) +#define I2S_CFG2_FRAMELEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_FRAMELEN_SHIFT)) & I2S_CFG2_FRAMELEN_MASK) +#define I2S_CFG2_POSITION_MASK (0x1FF0000U) +#define I2S_CFG2_POSITION_SHIFT (16U) +#define I2S_CFG2_POSITION(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_POSITION_SHIFT)) & I2S_CFG2_POSITION_MASK) +/*! @} */ + +/*! @name STAT - Status register for the primary channel pair. */ +/*! @{ */ +#define I2S_STAT_BUSY_MASK (0x1U) +#define I2S_STAT_BUSY_SHIFT (0U) +/*! BUSY - Busy status for the primary channel pair. Other BUSY flags may be found in the STAT register for each channel pair. + * 0b0..The transmitter/receiver for channel pair is currently idle. + * 0b1..The transmitter/receiver for channel pair is currently processing data. + */ +#define I2S_STAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_BUSY_SHIFT)) & I2S_STAT_BUSY_MASK) +#define I2S_STAT_SLVFRMERR_MASK (0x2U) +#define I2S_STAT_SLVFRMERR_SHIFT (1U) +/*! SLVFRMERR - Slave Frame Error flag. This applies when at least one channel pair is operating as + * a slave. An error indicates that the incoming WS signal did not transition as expected due to + * a mismatch between FRAMELEN and the actual incoming I2S stream. + * 0b0..No error has been recorded. + * 0b1..An error has been recorded for some channel pair that is operating in slave mode. ERROR is cleared by writing a 1 to this bit position. + */ +#define I2S_STAT_SLVFRMERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_SLVFRMERR_SHIFT)) & I2S_STAT_SLVFRMERR_MASK) +#define I2S_STAT_LR_MASK (0x4U) +#define I2S_STAT_LR_SHIFT (2U) +/*! LR - Left/Right indication. This flag is considered to be a debugging aid and is not expected to + * be used by an I2S driver. Valid when one channel pair is busy. Indicates left or right data + * being processed for the currently busy channel pair. + * 0b0..Left channel. + * 0b1..Right channel. + */ +#define I2S_STAT_LR(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_LR_SHIFT)) & I2S_STAT_LR_MASK) +#define I2S_STAT_DATAPAUSED_MASK (0x8U) +#define I2S_STAT_DATAPAUSED_SHIFT (3U) +/*! DATAPAUSED - Data Paused status flag. Applies to all I2S channels + * 0b0..Data is not currently paused. A data pause may have been requested but is not yet in force, waiting for + * an allowed pause point. Refer to the description of the DATAPAUSE control bit in the CFG1 register. + * 0b1..A data pause has been requested and is now in force. + */ +#define I2S_STAT_DATAPAUSED(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_DATAPAUSED_SHIFT)) & I2S_STAT_DATAPAUSED_MASK) +/*! @} */ + +/*! @name DIV - Clock divider, used by all channel pairs. */ +/*! @{ */ +#define I2S_DIV_DIV_MASK (0xFFFU) +#define I2S_DIV_DIV_SHIFT (0U) +#define I2S_DIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_DIV_DIV_SHIFT)) & I2S_DIV_DIV_MASK) +/*! @} */ + +/*! @name SECCHANNEL_PCFG1 - Configuration register 1 for channel pair */ +/*! @{ */ +#define I2S_SECCHANNEL_PCFG1_PAIRENABLE_MASK (0x1U) +#define I2S_SECCHANNEL_PCFG1_PAIRENABLE_SHIFT (0U) +#define I2S_SECCHANNEL_PCFG1_PAIRENABLE(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PCFG1_PAIRENABLE_SHIFT)) & I2S_SECCHANNEL_PCFG1_PAIRENABLE_MASK) +#define I2S_SECCHANNEL_PCFG1_ONECHANNEL_MASK (0x400U) +#define I2S_SECCHANNEL_PCFG1_ONECHANNEL_SHIFT (10U) +#define I2S_SECCHANNEL_PCFG1_ONECHANNEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PCFG1_ONECHANNEL_SHIFT)) & I2S_SECCHANNEL_PCFG1_ONECHANNEL_MASK) +/*! @} */ + +/* The count of I2S_SECCHANNEL_PCFG1 */ +#define I2S_SECCHANNEL_PCFG1_COUNT (3U) + +/*! @name SECCHANNEL_PCFG2 - Configuration register 2 for channel pair */ +/*! @{ */ +#define I2S_SECCHANNEL_PCFG2_POSITION_MASK (0x1FF0000U) +#define I2S_SECCHANNEL_PCFG2_POSITION_SHIFT (16U) +#define I2S_SECCHANNEL_PCFG2_POSITION(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PCFG2_POSITION_SHIFT)) & I2S_SECCHANNEL_PCFG2_POSITION_MASK) +/*! @} */ + +/* The count of I2S_SECCHANNEL_PCFG2 */ +#define I2S_SECCHANNEL_PCFG2_COUNT (3U) + +/*! @name SECCHANNEL_PSTAT - Status register for channel pair */ +/*! @{ */ +#define I2S_SECCHANNEL_PSTAT_BUSY_MASK (0x1U) +#define I2S_SECCHANNEL_PSTAT_BUSY_SHIFT (0U) +#define I2S_SECCHANNEL_PSTAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_BUSY_SHIFT)) & I2S_SECCHANNEL_PSTAT_BUSY_MASK) +#define I2S_SECCHANNEL_PSTAT_SLVFRMERR_MASK (0x2U) +#define I2S_SECCHANNEL_PSTAT_SLVFRMERR_SHIFT (1U) +#define I2S_SECCHANNEL_PSTAT_SLVFRMERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_SLVFRMERR_SHIFT)) & I2S_SECCHANNEL_PSTAT_SLVFRMERR_MASK) +#define I2S_SECCHANNEL_PSTAT_LR_MASK (0x4U) +#define I2S_SECCHANNEL_PSTAT_LR_SHIFT (2U) +#define I2S_SECCHANNEL_PSTAT_LR(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_LR_SHIFT)) & I2S_SECCHANNEL_PSTAT_LR_MASK) +#define I2S_SECCHANNEL_PSTAT_DATAPAUSED_MASK (0x8U) +#define I2S_SECCHANNEL_PSTAT_DATAPAUSED_SHIFT (3U) +#define I2S_SECCHANNEL_PSTAT_DATAPAUSED(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_DATAPAUSED_SHIFT)) & I2S_SECCHANNEL_PSTAT_DATAPAUSED_MASK) +/*! @} */ + +/* The count of I2S_SECCHANNEL_PSTAT */ +#define I2S_SECCHANNEL_PSTAT_COUNT (3U) + +/*! @name FIFOCFG - FIFO configuration and enable register. */ +/*! @{ */ +#define I2S_FIFOCFG_ENABLETX_MASK (0x1U) +#define I2S_FIFOCFG_ENABLETX_SHIFT (0U) +/*! ENABLETX - Enable the transmit FIFO. + * 0b0..The transmit FIFO is not enabled. + * 0b1..The transmit FIFO is enabled. + */ +#define I2S_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLETX_SHIFT)) & I2S_FIFOCFG_ENABLETX_MASK) +#define I2S_FIFOCFG_ENABLERX_MASK (0x2U) +#define I2S_FIFOCFG_ENABLERX_SHIFT (1U) +/*! ENABLERX - Enable the receive FIFO. + * 0b0..The receive FIFO is not enabled. + * 0b1..The receive FIFO is enabled. + */ +#define I2S_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLERX_SHIFT)) & I2S_FIFOCFG_ENABLERX_MASK) +#define I2S_FIFOCFG_TXI2SE0_MASK (0x4U) +#define I2S_FIFOCFG_TXI2SE0_SHIFT (2U) +/*! TXI2SE0 - Transmit I2S empty 0. Determines the value sent by the I2S in transmit mode if the TX + * FIFO becomes empty. This value is sent repeatedly until the I2S is paused, the error is + * cleared, new data is provided, and the I2S is un-paused. + * 0b0..If the TX FIFO becomes empty, the last value is sent. This setting may be used when the data length is 24 + * bits or less, or when MONO = 1 for this channel pair. + * 0b1..If the TX FIFO becomes empty, 0 is sent. Use if the data length is greater than 24 bits or if zero fill is preferred. + */ +#define I2S_FIFOCFG_TXI2SE0(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_TXI2SE0_SHIFT)) & I2S_FIFOCFG_TXI2SE0_MASK) +#define I2S_FIFOCFG_PACK48_MASK (0x8U) +#define I2S_FIFOCFG_PACK48_SHIFT (3U) +/*! PACK48 - Packing format for 48-bit data. This relates to how data is entered into or taken from the FIFO by software or DMA. + * 0b0..48-bit I2S FIFO entries are handled as all 24-bit values. + * 0b1..48-bit I2S FIFO entries are handled as alternating 32-bit and 16-bit values. + */ +#define I2S_FIFOCFG_PACK48(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_PACK48_SHIFT)) & I2S_FIFOCFG_PACK48_MASK) +#define I2S_FIFOCFG_SIZE_MASK (0x30U) +#define I2S_FIFOCFG_SIZE_SHIFT (4U) +#define I2S_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_SIZE_SHIFT)) & I2S_FIFOCFG_SIZE_MASK) +#define I2S_FIFOCFG_DMATX_MASK (0x1000U) +#define I2S_FIFOCFG_DMATX_SHIFT (12U) +/*! DMATX - DMA configuration for transmit. + * 0b0..DMA is not used for the transmit function. + * 0b1..Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. + */ +#define I2S_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMATX_SHIFT)) & I2S_FIFOCFG_DMATX_MASK) +#define I2S_FIFOCFG_DMARX_MASK (0x2000U) +#define I2S_FIFOCFG_DMARX_SHIFT (13U) +/*! DMARX - DMA configuration for receive. + * 0b0..DMA is not used for the receive function. + * 0b1..Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. + */ +#define I2S_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMARX_SHIFT)) & I2S_FIFOCFG_DMARX_MASK) +#define I2S_FIFOCFG_WAKETX_MASK (0x4000U) +#define I2S_FIFOCFG_WAKETX_SHIFT (14U) +/*! WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power + * modes (up to power-down, as long as the peripheral function works in that power mode) without + * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The + * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware + * Wake-up control register. + * 0b0..Only enabled interrupts will wake up the device form reduced power modes. + * 0b1..A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in + * FIFOTRIG, even when the TXLVL interrupt is not enabled. + */ +#define I2S_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKETX_SHIFT)) & I2S_FIFOCFG_WAKETX_MASK) +#define I2S_FIFOCFG_WAKERX_MASK (0x8000U) +#define I2S_FIFOCFG_WAKERX_SHIFT (15U) +/*! WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power + * modes (up to power-down, as long as the peripheral function works in that power mode) without + * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The + * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware + * Wake-up control register. + * 0b0..Only enabled interrupts will wake up the device form reduced power modes. + * 0b1..A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in + * FIFOTRIG, even when the RXLVL interrupt is not enabled. + */ +#define I2S_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKERX_SHIFT)) & I2S_FIFOCFG_WAKERX_MASK) +#define I2S_FIFOCFG_EMPTYTX_MASK (0x10000U) +#define I2S_FIFOCFG_EMPTYTX_SHIFT (16U) +#define I2S_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYTX_SHIFT)) & I2S_FIFOCFG_EMPTYTX_MASK) +#define I2S_FIFOCFG_EMPTYRX_MASK (0x20000U) +#define I2S_FIFOCFG_EMPTYRX_SHIFT (17U) +#define I2S_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYRX_SHIFT)) & I2S_FIFOCFG_EMPTYRX_MASK) +#define I2S_FIFOCFG_POPDBG_MASK (0x40000U) +#define I2S_FIFOCFG_POPDBG_SHIFT (18U) +/*! POPDBG - Pop FIFO for debug reads. + * 0b0..Debug reads of the FIFO do not pop the FIFO. + * 0b1..A debug read will cause the FIFO to pop. + */ +#define I2S_FIFOCFG_POPDBG(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_POPDBG_SHIFT)) & I2S_FIFOCFG_POPDBG_MASK) +/*! @} */ + +/*! @name FIFOSTAT - FIFO status register. */ +/*! @{ */ +#define I2S_FIFOSTAT_TXERR_MASK (0x1U) +#define I2S_FIFOSTAT_TXERR_SHIFT (0U) +#define I2S_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXERR_SHIFT)) & I2S_FIFOSTAT_TXERR_MASK) +#define I2S_FIFOSTAT_RXERR_MASK (0x2U) +#define I2S_FIFOSTAT_RXERR_SHIFT (1U) +#define I2S_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXERR_SHIFT)) & I2S_FIFOSTAT_RXERR_MASK) +#define I2S_FIFOSTAT_PERINT_MASK (0x8U) +#define I2S_FIFOSTAT_PERINT_SHIFT (3U) +#define I2S_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_PERINT_SHIFT)) & I2S_FIFOSTAT_PERINT_MASK) +#define I2S_FIFOSTAT_TXEMPTY_MASK (0x10U) +#define I2S_FIFOSTAT_TXEMPTY_SHIFT (4U) +#define I2S_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXEMPTY_SHIFT)) & I2S_FIFOSTAT_TXEMPTY_MASK) +#define I2S_FIFOSTAT_TXNOTFULL_MASK (0x20U) +#define I2S_FIFOSTAT_TXNOTFULL_SHIFT (5U) +#define I2S_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXNOTFULL_SHIFT)) & I2S_FIFOSTAT_TXNOTFULL_MASK) +#define I2S_FIFOSTAT_RXNOTEMPTY_MASK (0x40U) +#define I2S_FIFOSTAT_RXNOTEMPTY_SHIFT (6U) +#define I2S_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXNOTEMPTY_SHIFT)) & I2S_FIFOSTAT_RXNOTEMPTY_MASK) +#define I2S_FIFOSTAT_RXFULL_MASK (0x80U) +#define I2S_FIFOSTAT_RXFULL_SHIFT (7U) +#define I2S_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXFULL_SHIFT)) & I2S_FIFOSTAT_RXFULL_MASK) +#define I2S_FIFOSTAT_TXLVL_MASK (0x1F00U) +#define I2S_FIFOSTAT_TXLVL_SHIFT (8U) +#define I2S_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXLVL_SHIFT)) & I2S_FIFOSTAT_TXLVL_MASK) +#define I2S_FIFOSTAT_RXLVL_MASK (0x1F0000U) +#define I2S_FIFOSTAT_RXLVL_SHIFT (16U) +#define I2S_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXLVL_SHIFT)) & I2S_FIFOSTAT_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */ +/*! @{ */ +#define I2S_FIFOTRIG_TXLVLENA_MASK (0x1U) +#define I2S_FIFOTRIG_TXLVLENA_SHIFT (0U) +/*! TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled + * in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set. + * 0b0..Transmit FIFO level does not generate a FIFO level trigger. + * 0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register. + */ +#define I2S_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVLENA_SHIFT)) & I2S_FIFOTRIG_TXLVLENA_MASK) +#define I2S_FIFOTRIG_RXLVLENA_MASK (0x2U) +#define I2S_FIFOTRIG_RXLVLENA_SHIFT (1U) +/*! RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled + * in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. + * 0b0..Receive FIFO level does not generate a FIFO level trigger. + * 0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. + */ +#define I2S_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVLENA_SHIFT)) & I2S_FIFOTRIG_RXLVLENA_MASK) +#define I2S_FIFOTRIG_TXLVL_MASK (0xF00U) +#define I2S_FIFOTRIG_TXLVL_SHIFT (8U) +#define I2S_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVL_SHIFT)) & I2S_FIFOTRIG_TXLVL_MASK) +#define I2S_FIFOTRIG_RXLVL_MASK (0xF0000U) +#define I2S_FIFOTRIG_RXLVL_SHIFT (16U) +#define I2S_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVL_SHIFT)) & I2S_FIFOTRIG_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */ +/*! @{ */ +#define I2S_FIFOINTENSET_TXERR_MASK (0x1U) +#define I2S_FIFOINTENSET_TXERR_SHIFT (0U) +/*! TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. + * 0b0..No interrupt will be generated for a transmit error. + * 0b1..An interrupt will be generated when a transmit error occurs. + */ +#define I2S_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXERR_SHIFT)) & I2S_FIFOINTENSET_TXERR_MASK) +#define I2S_FIFOINTENSET_RXERR_MASK (0x2U) +#define I2S_FIFOINTENSET_RXERR_SHIFT (1U) +/*! RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. + * 0b0..No interrupt will be generated for a receive error. + * 0b1..An interrupt will be generated when a receive error occurs. + */ +#define I2S_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXERR_SHIFT)) & I2S_FIFOINTENSET_RXERR_MASK) +#define I2S_FIFOINTENSET_TXLVL_MASK (0x4U) +#define I2S_FIFOINTENSET_TXLVL_SHIFT (2U) +/*! TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level + * specified by the TXLVL field in the FIFOTRIG register. + * 0b0..No interrupt will be generated based on the TX FIFO level. + * 0b1..If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases + * to the level specified by TXLVL in the FIFOTRIG register. + */ +#define I2S_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXLVL_SHIFT)) & I2S_FIFOINTENSET_TXLVL_MASK) +#define I2S_FIFOINTENSET_RXLVL_MASK (0x8U) +#define I2S_FIFOINTENSET_RXLVL_SHIFT (3U) +/*! RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level + * specified by the TXLVL field in the FIFOTRIG register. + * 0b0..No interrupt will be generated based on the RX FIFO level. + * 0b1..If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level + * increases to the level specified by RXLVL in the FIFOTRIG register. + */ +#define I2S_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXLVL_SHIFT)) & I2S_FIFOINTENSET_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */ +/*! @{ */ +#define I2S_FIFOINTENCLR_TXERR_MASK (0x1U) +#define I2S_FIFOINTENCLR_TXERR_SHIFT (0U) +#define I2S_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXERR_SHIFT)) & I2S_FIFOINTENCLR_TXERR_MASK) +#define I2S_FIFOINTENCLR_RXERR_MASK (0x2U) +#define I2S_FIFOINTENCLR_RXERR_SHIFT (1U) +#define I2S_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXERR_SHIFT)) & I2S_FIFOINTENCLR_RXERR_MASK) +#define I2S_FIFOINTENCLR_TXLVL_MASK (0x4U) +#define I2S_FIFOINTENCLR_TXLVL_SHIFT (2U) +#define I2S_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXLVL_SHIFT)) & I2S_FIFOINTENCLR_TXLVL_MASK) +#define I2S_FIFOINTENCLR_RXLVL_MASK (0x8U) +#define I2S_FIFOINTENCLR_RXLVL_SHIFT (3U) +#define I2S_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXLVL_SHIFT)) & I2S_FIFOINTENCLR_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTSTAT - FIFO interrupt status register. */ +/*! @{ */ +#define I2S_FIFOINTSTAT_TXERR_MASK (0x1U) +#define I2S_FIFOINTSTAT_TXERR_SHIFT (0U) +#define I2S_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXERR_SHIFT)) & I2S_FIFOINTSTAT_TXERR_MASK) +#define I2S_FIFOINTSTAT_RXERR_MASK (0x2U) +#define I2S_FIFOINTSTAT_RXERR_SHIFT (1U) +#define I2S_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXERR_SHIFT)) & I2S_FIFOINTSTAT_RXERR_MASK) +#define I2S_FIFOINTSTAT_TXLVL_MASK (0x4U) +#define I2S_FIFOINTSTAT_TXLVL_SHIFT (2U) +#define I2S_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXLVL_SHIFT)) & I2S_FIFOINTSTAT_TXLVL_MASK) +#define I2S_FIFOINTSTAT_RXLVL_MASK (0x8U) +#define I2S_FIFOINTSTAT_RXLVL_SHIFT (3U) +#define I2S_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXLVL_SHIFT)) & I2S_FIFOINTSTAT_RXLVL_MASK) +#define I2S_FIFOINTSTAT_PERINT_MASK (0x10U) +#define I2S_FIFOINTSTAT_PERINT_SHIFT (4U) +#define I2S_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_PERINT_SHIFT)) & I2S_FIFOINTSTAT_PERINT_MASK) +/*! @} */ + +/*! @name FIFOWR - FIFO write data. */ +/*! @{ */ +#define I2S_FIFOWR_TXDATA_MASK (0xFFFFFFFFU) +#define I2S_FIFOWR_TXDATA_SHIFT (0U) +#define I2S_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR_TXDATA_SHIFT)) & I2S_FIFOWR_TXDATA_MASK) +/*! @} */ + +/*! @name FIFOWR48H - FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */ +/*! @{ */ +#define I2S_FIFOWR48H_TXDATA_MASK (0xFFFFFFU) +#define I2S_FIFOWR48H_TXDATA_SHIFT (0U) +#define I2S_FIFOWR48H_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR48H_TXDATA_SHIFT)) & I2S_FIFOWR48H_TXDATA_MASK) +/*! @} */ + +/*! @name FIFORD - FIFO read data. */ +/*! @{ */ +#define I2S_FIFORD_RXDATA_MASK (0xFFFFFFFFU) +#define I2S_FIFORD_RXDATA_SHIFT (0U) +#define I2S_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD_RXDATA_SHIFT)) & I2S_FIFORD_RXDATA_MASK) +/*! @} */ + +/*! @name FIFORD48H - FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */ +/*! @{ */ +#define I2S_FIFORD48H_RXDATA_MASK (0xFFFFFFU) +#define I2S_FIFORD48H_RXDATA_SHIFT (0U) +#define I2S_FIFORD48H_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48H_RXDATA_SHIFT)) & I2S_FIFORD48H_RXDATA_MASK) +/*! @} */ + +/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */ +/*! @{ */ +#define I2S_FIFORDNOPOP_RXDATA_MASK (0xFFFFFFFFU) +#define I2S_FIFORDNOPOP_RXDATA_SHIFT (0U) +#define I2S_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORDNOPOP_RXDATA_SHIFT)) & I2S_FIFORDNOPOP_RXDATA_MASK) +/*! @} */ + +/*! @name FIFORD48HNOPOP - FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */ +/*! @{ */ +#define I2S_FIFORD48HNOPOP_RXDATA_MASK (0xFFFFFFU) +#define I2S_FIFORD48HNOPOP_RXDATA_SHIFT (0U) +#define I2S_FIFORD48HNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48HNOPOP_RXDATA_SHIFT)) & I2S_FIFORD48HNOPOP_RXDATA_MASK) +/*! @} */ + +/*! @name ID - I2S Module identification */ +/*! @{ */ +#define I2S_ID_Aperture_MASK (0xFFU) +#define I2S_ID_Aperture_SHIFT (0U) +#define I2S_ID_Aperture(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_Aperture_SHIFT)) & I2S_ID_Aperture_MASK) +#define I2S_ID_Minor_Rev_MASK (0xF00U) +#define I2S_ID_Minor_Rev_SHIFT (8U) +#define I2S_ID_Minor_Rev(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_Minor_Rev_SHIFT)) & I2S_ID_Minor_Rev_MASK) +#define I2S_ID_Major_Rev_MASK (0xF000U) +#define I2S_ID_Major_Rev_SHIFT (12U) +#define I2S_ID_Major_Rev(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_Major_Rev_SHIFT)) & I2S_ID_Major_Rev_MASK) +#define I2S_ID_ID_MASK (0xFFFF0000U) +#define I2S_ID_ID_SHIFT (16U) +#define I2S_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_ID_SHIFT)) & I2S_ID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group I2S_Register_Masks */ + + +/* I2S - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral I2S0 base address */ + #define I2S0_BASE (0x50086000u) + /** Peripheral I2S0 base address */ + #define I2S0_BASE_NS (0x40086000u) + /** Peripheral I2S0 base pointer */ + #define I2S0 ((I2S_Type *)I2S0_BASE) + /** Peripheral I2S0 base pointer */ + #define I2S0_NS ((I2S_Type *)I2S0_BASE_NS) + /** Peripheral I2S1 base address */ + #define I2S1_BASE (0x50087000u) + /** Peripheral I2S1 base address */ + #define I2S1_BASE_NS (0x40087000u) + /** Peripheral I2S1 base pointer */ + #define I2S1 ((I2S_Type *)I2S1_BASE) + /** Peripheral I2S1 base pointer */ + #define I2S1_NS ((I2S_Type *)I2S1_BASE_NS) + /** Peripheral I2S2 base address */ + #define I2S2_BASE (0x50088000u) + /** Peripheral I2S2 base address */ + #define I2S2_BASE_NS (0x40088000u) + /** Peripheral I2S2 base pointer */ + #define I2S2 ((I2S_Type *)I2S2_BASE) + /** Peripheral I2S2 base pointer */ + #define I2S2_NS ((I2S_Type *)I2S2_BASE_NS) + /** Peripheral I2S3 base address */ + #define I2S3_BASE (0x50089000u) + /** Peripheral I2S3 base address */ + #define I2S3_BASE_NS (0x40089000u) + /** Peripheral I2S3 base pointer */ + #define I2S3 ((I2S_Type *)I2S3_BASE) + /** Peripheral I2S3 base pointer */ + #define I2S3_NS ((I2S_Type *)I2S3_BASE_NS) + /** Peripheral I2S4 base address */ + #define I2S4_BASE (0x5008A000u) + /** Peripheral I2S4 base address */ + #define I2S4_BASE_NS (0x4008A000u) + /** Peripheral I2S4 base pointer */ + #define I2S4 ((I2S_Type *)I2S4_BASE) + /** Peripheral I2S4 base pointer */ + #define I2S4_NS ((I2S_Type *)I2S4_BASE_NS) + /** Peripheral I2S5 base address */ + #define I2S5_BASE (0x50096000u) + /** Peripheral I2S5 base address */ + #define I2S5_BASE_NS (0x40096000u) + /** Peripheral I2S5 base pointer */ + #define I2S5 ((I2S_Type *)I2S5_BASE) + /** Peripheral I2S5 base pointer */ + #define I2S5_NS ((I2S_Type *)I2S5_BASE_NS) + /** Peripheral I2S6 base address */ + #define I2S6_BASE (0x50097000u) + /** Peripheral I2S6 base address */ + #define I2S6_BASE_NS (0x40097000u) + /** Peripheral I2S6 base pointer */ + #define I2S6 ((I2S_Type *)I2S6_BASE) + /** Peripheral I2S6 base pointer */ + #define I2S6_NS ((I2S_Type *)I2S6_BASE_NS) + /** Peripheral I2S7 base address */ + #define I2S7_BASE (0x50098000u) + /** Peripheral I2S7 base address */ + #define I2S7_BASE_NS (0x40098000u) + /** Peripheral I2S7 base pointer */ + #define I2S7 ((I2S_Type *)I2S7_BASE) + /** Peripheral I2S7 base pointer */ + #define I2S7_NS ((I2S_Type *)I2S7_BASE_NS) + /** Array initializer of I2S peripheral base addresses */ + #define I2S_BASE_ADDRS { I2S0_BASE, I2S1_BASE, I2S2_BASE, I2S3_BASE, I2S4_BASE, I2S5_BASE, I2S6_BASE, I2S7_BASE } + /** Array initializer of I2S peripheral base pointers */ + #define I2S_BASE_PTRS { I2S0, I2S1, I2S2, I2S3, I2S4, I2S5, I2S6, I2S7 } + /** Array initializer of I2S peripheral base addresses */ + #define I2S_BASE_ADDRS_NS { I2S0_BASE_NS, I2S1_BASE_NS, I2S2_BASE_NS, I2S3_BASE_NS, I2S4_BASE_NS, I2S5_BASE_NS, I2S6_BASE_NS, I2S7_BASE_NS } + /** Array initializer of I2S peripheral base pointers */ + #define I2S_BASE_PTRS_NS { I2S0_NS, I2S1_NS, I2S2_NS, I2S3_NS, I2S4_NS, I2S5_NS, I2S6_NS, I2S7_NS } +#else + /** Peripheral I2S0 base address */ + #define I2S0_BASE (0x40086000u) + /** Peripheral I2S0 base pointer */ + #define I2S0 ((I2S_Type *)I2S0_BASE) + /** Peripheral I2S1 base address */ + #define I2S1_BASE (0x40087000u) + /** Peripheral I2S1 base pointer */ + #define I2S1 ((I2S_Type *)I2S1_BASE) + /** Peripheral I2S2 base address */ + #define I2S2_BASE (0x40088000u) + /** Peripheral I2S2 base pointer */ + #define I2S2 ((I2S_Type *)I2S2_BASE) + /** Peripheral I2S3 base address */ + #define I2S3_BASE (0x40089000u) + /** Peripheral I2S3 base pointer */ + #define I2S3 ((I2S_Type *)I2S3_BASE) + /** Peripheral I2S4 base address */ + #define I2S4_BASE (0x4008A000u) + /** Peripheral I2S4 base pointer */ + #define I2S4 ((I2S_Type *)I2S4_BASE) + /** Peripheral I2S5 base address */ + #define I2S5_BASE (0x40096000u) + /** Peripheral I2S5 base pointer */ + #define I2S5 ((I2S_Type *)I2S5_BASE) + /** Peripheral I2S6 base address */ + #define I2S6_BASE (0x40097000u) + /** Peripheral I2S6 base pointer */ + #define I2S6 ((I2S_Type *)I2S6_BASE) + /** Peripheral I2S7 base address */ + #define I2S7_BASE (0x40098000u) + /** Peripheral I2S7 base pointer */ + #define I2S7 ((I2S_Type *)I2S7_BASE) + /** Array initializer of I2S peripheral base addresses */ + #define I2S_BASE_ADDRS { I2S0_BASE, I2S1_BASE, I2S2_BASE, I2S3_BASE, I2S4_BASE, I2S5_BASE, I2S6_BASE, I2S7_BASE } + /** Array initializer of I2S peripheral base pointers */ + #define I2S_BASE_PTRS { I2S0, I2S1, I2S2, I2S3, I2S4, I2S5, I2S6, I2S7 } +#endif +/** Interrupt vectors for the I2S peripheral type */ +#define I2S_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } + +/*! + * @} + */ /* end of group I2S_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- INPUTMUX Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup INPUTMUX_Peripheral_Access_Layer INPUTMUX Peripheral Access Layer + * @{ + */ + +/** INPUTMUX - Register Layout Typedef */ +typedef struct { + __IO uint32_t SCT0_INMUX[7]; /**< Input mux register for SCT0 input, array offset: 0x0, array step: 0x4 */ + uint8_t RESERVED_0[4]; + __IO uint32_t TIMER0CAPTSEL[4]; /**< Capture select registers for TIMER0 inputs, array offset: 0x20, array step: 0x4 */ + uint8_t RESERVED_1[16]; + __IO uint32_t TIMER1CAPTSEL[4]; /**< Capture select registers for TIMER1 inputs, array offset: 0x40, array step: 0x4 */ + uint8_t RESERVED_2[16]; + __IO uint32_t TIMER2CAPTSEL[4]; /**< Capture select registers for TIMER2 inputs, array offset: 0x60, array step: 0x4 */ + uint8_t RESERVED_3[80]; + __IO uint32_t PINTSEL[8]; /**< Pin interrupt select register, array offset: 0xC0, array step: 0x4 */ + __IO uint32_t DMA0_ITRIG_INMUX[23]; /**< Trigger select register for DMA0 channel, array offset: 0xE0, array step: 0x4 */ + uint8_t RESERVED_4[36]; + __IO uint32_t DMA0_OTRIG_INMUX[4]; /**< DMA0 output trigger selection to become DMA0 trigger, array offset: 0x160, array step: 0x4 */ + uint8_t RESERVED_5[16]; + __IO uint32_t FREQMEAS_REF; /**< Selection for frequency measurement reference clock, offset: 0x180 */ + __IO uint32_t FREQMEAS_TARGET; /**< Selection for frequency measurement target clock, offset: 0x184 */ + uint8_t RESERVED_6[24]; + __IO uint32_t TIMER3CAPTSEL[4]; /**< Capture select registers for TIMER3 inputs, array offset: 0x1A0, array step: 0x4 */ + uint8_t RESERVED_7[16]; + __IO uint32_t TIMER4CAPTSEL[4]; /**< Capture select registers for TIMER4 inputs, array offset: 0x1C0, array step: 0x4 */ + uint8_t RESERVED_8[16]; + __IO uint32_t PINTSECSEL[2]; /**< Pin interrupt secure select register, array offset: 0x1E0, array step: 0x4 */ + uint8_t RESERVED_9[24]; + __IO uint32_t DMA1_ITRIG_INMUX[10]; /**< Trigger select register for DMA1 channel, array offset: 0x200, array step: 0x4 */ + uint8_t RESERVED_10[24]; + __IO uint32_t DMA1_OTRIG_INMUX[4]; /**< DMA1 output trigger selection to become DMA1 trigger, array offset: 0x240, array step: 0x4 */ + uint8_t RESERVED_11[1264]; + __IO uint32_t DMA0_REQ_ENA; /**< Enable DMA0 requests, offset: 0x740 */ + uint8_t RESERVED_12[4]; + __O uint32_t DMA0_REQ_ENA_SET; /**< Set one or several bits in DMA0_REQ_ENA register, offset: 0x748 */ + uint8_t RESERVED_13[4]; + __O uint32_t DMA0_REQ_ENA_CLR; /**< Clear one or several bits in DMA0_REQ_ENA register, offset: 0x750 */ + uint8_t RESERVED_14[12]; + __IO uint32_t DMA1_REQ_ENA; /**< Enable DMA1 requests, offset: 0x760 */ + uint8_t RESERVED_15[4]; + __O uint32_t DMA1_REQ_ENA_SET; /**< Set one or several bits in DMA1_REQ_ENA register, offset: 0x768 */ + uint8_t RESERVED_16[4]; + __O uint32_t DMA1_REQ_ENA_CLR; /**< Clear one or several bits in DMA1_REQ_ENA register, offset: 0x770 */ + uint8_t RESERVED_17[12]; + __IO uint32_t DMA0_ITRIG_ENA; /**< Enable DMA0 triggers, offset: 0x780 */ + uint8_t RESERVED_18[4]; + __O uint32_t DMA0_ITRIG_ENA_SET; /**< Set one or several bits in DMA0_ITRIG_ENA register, offset: 0x788 */ + uint8_t RESERVED_19[4]; + __O uint32_t DMA0_ITRIG_ENA_CLR; /**< Clear one or several bits in DMA0_ITRIG_ENA register, offset: 0x790 */ + uint8_t RESERVED_20[12]; + __IO uint32_t DMA1_ITRIG_ENA; /**< Enable DMA1 triggers, offset: 0x7A0 */ + uint8_t RESERVED_21[4]; + __O uint32_t DMA1_ITRIG_ENA_SET; /**< Set one or several bits in DMA1_ITRIG_ENA register, offset: 0x7A8 */ + uint8_t RESERVED_22[4]; + __O uint32_t DMA1_ITRIG_ENA_CLR; /**< Clear one or several bits in DMA1_ITRIG_ENA register, offset: 0x7B0 */ +} INPUTMUX_Type; + +/* ---------------------------------------------------------------------------- + -- INPUTMUX Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup INPUTMUX_Register_Masks INPUTMUX Register Masks + * @{ + */ + +/*! @name SCT0_INMUX - Input mux register for SCT0 input */ +/*! @{ */ +#define INPUTMUX_SCT0_INMUX_INP_N_MASK (0x1FU) +#define INPUTMUX_SCT0_INMUX_INP_N_SHIFT (0U) +/*! INP_N - Input number to SCT0 inputs 0 to 6.. + * 0b00000..SCT_GPI0 function selected from IOCON register + * 0b00001..SCT_GPI1 function selected from IOCON register + * 0b00010..SCT_GPI2 function selected from IOCON register + * 0b00011..SCT_GPI3 function selected from IOCON register + * 0b00100..SCT_GPI4 function selected from IOCON register + * 0b00101..SCT_GPI5 function selected from IOCON register + * 0b00110..SCT_GPI6 function selected from IOCON register + * 0b00111..SCT_GPI7 function selected from IOCON register + * 0b01000..T0_OUT0 ctimer 0 match[0] output + * 0b01001..T1_OUT0 ctimer 1 match[0] output + * 0b01010..T2_OUT0 ctimer 2 match[0] output + * 0b01011..T3_OUT0 ctimer 3 match[0] output + * 0b01100..T4_OUT0 ctimer 4 match[0] output + * 0b01101..ADC_IRQ interrupt request from ADC + * 0b01110..GPIOINT_BMATCH + * 0b01111..USB0_FRAME_TOGGLE + * 0b10000..USB1_FRAME_TOGGLE + * 0b10001..COMP_OUTPUT output from analog comparator + * 0b10010..I2S_SHARED_SCK[0] output from I2S pin sharing + * 0b10011..I2S_SHARED_SCK[1] output from I2S pin sharing + * 0b10100..I2S_SHARED_WS[0] output from I2S pin sharing + * 0b10101..I2S_SHARED_WS[1] output from I2S pin sharing + * 0b10110..ARM_TXEV interrupt event from cpu0 or cpu1 + * 0b10111..DEBUG_HALTED from cpu0 or cpu1 + * 0b11000-0b11111..None + */ +#define INPUTMUX_SCT0_INMUX_INP_N(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_SCT0_INMUX_INP_N_SHIFT)) & INPUTMUX_SCT0_INMUX_INP_N_MASK) +/*! @} */ + +/* The count of INPUTMUX_SCT0_INMUX */ +#define INPUTMUX_SCT0_INMUX_COUNT (7U) + +/*! @name TIMER0CAPTSEL - Capture select registers for TIMER0 inputs */ +/*! @{ */ +#define INPUTMUX_TIMER0CAPTSEL_CAPTSEL_MASK (0x1FU) +#define INPUTMUX_TIMER0CAPTSEL_CAPTSEL_SHIFT (0U) +/*! CAPTSEL - Input number to TIMER0 capture inputs 0 to 4 + * 0b00000..CT_INP0 function selected from IOCON register + * 0b00001..CT_INP1 function selected from IOCON register + * 0b00010..CT_INP2 function selected from IOCON register + * 0b00011..CT_INP3 function selected from IOCON register + * 0b00100..CT_INP4 function selected from IOCON register + * 0b00101..CT_INP5 function selected from IOCON register + * 0b00110..CT_INP6 function selected from IOCON register + * 0b00111..CT_INP7 function selected from IOCON register + * 0b01000..CT_INP8 function selected from IOCON register + * 0b01001..CT_INP9 function selected from IOCON register + * 0b01010..CT_INP10 function selected from IOCON register + * 0b01011..CT_INP11 function selected from IOCON register + * 0b01100..CT_INP12 function selected from IOCON register + * 0b01101..CT_INP13 function selected from IOCON register + * 0b01110..CT_INP14 function selected from IOCON register + * 0b01111..CT_INP15 function selected from IOCON register + * 0b10000..CT_INP16 function selected from IOCON register + * 0b10001..CT_INP17 function selected from IOCON register + * 0b10010..CT_INP18 function selected from IOCON register + * 0b10011..CT_INP19 function selected from IOCON register + * 0b10100..USB0_FRAME_TOGGLE + * 0b10101..USB1_FRAME_TOGGLE + * 0b10110..COMP_OUTPUT output from analog comparator + * 0b10111..I2S_SHARED_WS[0] output from I2S pin sharing + * 0b11000..I2S_SHARED_WS[1] output from I2S pin sharing + * 0b11001-0b11111..None + */ +#define INPUTMUX_TIMER0CAPTSEL_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER0CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER0CAPTSEL_CAPTSEL_MASK) +/*! @} */ + +/* The count of INPUTMUX_TIMER0CAPTSEL */ +#define INPUTMUX_TIMER0CAPTSEL_COUNT (4U) + +/*! @name TIMER1CAPTSEL - Capture select registers for TIMER1 inputs */ +/*! @{ */ +#define INPUTMUX_TIMER1CAPTSEL_CAPTSEL_MASK (0x1FU) +#define INPUTMUX_TIMER1CAPTSEL_CAPTSEL_SHIFT (0U) +/*! CAPTSEL - Input number to TIMER1 capture inputs 0 to 4 + * 0b00000..CT_INP0 function selected from IOCON register + * 0b00001..CT_INP1 function selected from IOCON register + * 0b00010..CT_INP2 function selected from IOCON register + * 0b00011..CT_INP3 function selected from IOCON register + * 0b00100..CT_INP4 function selected from IOCON register + * 0b00101..CT_INP5 function selected from IOCON register + * 0b00110..CT_INP6 function selected from IOCON register + * 0b00111..CT_INP7 function selected from IOCON register + * 0b01000..CT_INP8 function selected from IOCON register + * 0b01001..CT_INP9 function selected from IOCON register + * 0b01010..CT_INP10 function selected from IOCON register + * 0b01011..CT_INP11 function selected from IOCON register + * 0b01100..CT_INP12 function selected from IOCON register + * 0b01101..CT_INP13 function selected from IOCON register + * 0b01110..CT_INP14 function selected from IOCON register + * 0b01111..CT_INP15 function selected from IOCON register + * 0b10000..CT_INP16 function selected from IOCON register + * 0b10001..CT_INP17 function selected from IOCON register + * 0b10010..CT_INP18 function selected from IOCON register + * 0b10011..CT_INP19 function selected from IOCON register + * 0b10100..USB0_FRAME_TOGGLE + * 0b10101..USB1_FRAME_TOGGLE + * 0b10110..COMP_OUTPUT output from analog comparator + * 0b10111..I2S_SHARED_WS[0] output from I2S pin sharing + * 0b11000..I2S_SHARED_WS[1] output from I2S pin sharing + * 0b11001-0b11111..None + */ +#define INPUTMUX_TIMER1CAPTSEL_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER1CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER1CAPTSEL_CAPTSEL_MASK) +/*! @} */ + +/* The count of INPUTMUX_TIMER1CAPTSEL */ +#define INPUTMUX_TIMER1CAPTSEL_COUNT (4U) + +/*! @name TIMER2CAPTSEL - Capture select registers for TIMER2 inputs */ +/*! @{ */ +#define INPUTMUX_TIMER2CAPTSEL_CAPTSEL_MASK (0x1FU) +#define INPUTMUX_TIMER2CAPTSEL_CAPTSEL_SHIFT (0U) +/*! CAPTSEL - Input number to TIMER2 capture inputs 0 to 4 + * 0b00000..CT_INP0 function selected from IOCON register + * 0b00001..CT_INP1 function selected from IOCON register + * 0b00010..CT_INP2 function selected from IOCON register + * 0b00011..CT_INP3 function selected from IOCON register + * 0b00100..CT_INP4 function selected from IOCON register + * 0b00101..CT_INP5 function selected from IOCON register + * 0b00110..CT_INP6 function selected from IOCON register + * 0b00111..CT_INP7 function selected from IOCON register + * 0b01000..CT_INP8 function selected from IOCON register + * 0b01001..CT_INP9 function selected from IOCON register + * 0b01010..CT_INP10 function selected from IOCON register + * 0b01011..CT_INP11 function selected from IOCON register + * 0b01100..CT_INP12 function selected from IOCON register + * 0b01101..CT_INP13 function selected from IOCON register + * 0b01110..CT_INP14 function selected from IOCON register + * 0b01111..CT_INP15 function selected from IOCON register + * 0b10000..CT_INP16 function selected from IOCON register + * 0b10001..CT_INP17 function selected from IOCON register + * 0b10010..CT_INP18 function selected from IOCON register + * 0b10011..CT_INP19 function selected from IOCON register + * 0b10100..USB0_FRAME_TOGGLE + * 0b10101..USB1_FRAME_TOGGLE + * 0b10110..COMP_OUTPUT output from analog comparator + * 0b10111..I2S_SHARED_WS[0] output from I2S pin sharing + * 0b11000..I2S_SHARED_WS[1] output from I2S pin sharing + * 0b11001-0b11111..None + */ +#define INPUTMUX_TIMER2CAPTSEL_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER2CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER2CAPTSEL_CAPTSEL_MASK) +/*! @} */ + +/* The count of INPUTMUX_TIMER2CAPTSEL */ +#define INPUTMUX_TIMER2CAPTSEL_COUNT (4U) + +/*! @name PINTSEL - Pin interrupt select register */ +/*! @{ */ +#define INPUTMUX_PINTSEL_INTPIN_MASK (0x7FU) +#define INPUTMUX_PINTSEL_INTPIN_SHIFT (0U) +#define INPUTMUX_PINTSEL_INTPIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PINTSEL_INTPIN_SHIFT)) & INPUTMUX_PINTSEL_INTPIN_MASK) +/*! @} */ + +/* The count of INPUTMUX_PINTSEL */ +#define INPUTMUX_PINTSEL_COUNT (8U) + +/*! @name DMA0_ITRIG_INMUX - Trigger select register for DMA0 channel */ +/*! @{ */ +#define INPUTMUX_DMA0_ITRIG_INMUX_INP_MASK (0x1FU) +#define INPUTMUX_DMA0_ITRIG_INMUX_INP_SHIFT (0U) +/*! INP - Trigger input number (decimal value) for DMA channel n (n = 0 to 22). + * 0b00000..Pin interrupt 0 + * 0b00001..Pin interrupt 1 + * 0b00010..Pin interrupt 2 + * 0b00011..Pin interrupt 3 + * 0b00100..Timer CTIMER0 Match 0 + * 0b00101..Timer CTIMER0 Match 1 + * 0b00110..Timer CTIMER1 Match 0 + * 0b00111..Timer CTIMER1 Match 1 + * 0b01000..Timer CTIMER2 Match 0 + * 0b01001..Timer CTIMER2 Match 1 + * 0b01010..Timer CTIMER3 Match 0 + * 0b01011..Timer CTIMER3 Match 1 + * 0b01100..Timer CTIMER4 Match 0 + * 0b01101..Timer CTIMER4 Match 1 + * 0b01110..COMP_OUTPUT + * 0b01111..DMA0 output trigger mux 0 + * 0b10000..DMA0 output trigger mux 1 + * 0b10001..DMA0 output trigger mux 1 + * 0b10010..DMA0 output trigger mux 3 + * 0b10011..SCT0 DMA request 0 + * 0b10100..SCT0 DMA request 1 + * 0b10101..HASH DMA RX trigger + * 0b10110-0b11111..None + */ +#define INPUTMUX_DMA0_ITRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA0_ITRIG_INMUX_INP_MASK) +/*! @} */ + +/* The count of INPUTMUX_DMA0_ITRIG_INMUX */ +#define INPUTMUX_DMA0_ITRIG_INMUX_COUNT (23U) + +/*! @name DMA0_OTRIG_INMUX - DMA0 output trigger selection to become DMA0 trigger */ +/*! @{ */ +#define INPUTMUX_DMA0_OTRIG_INMUX_INP_MASK (0x1FU) +#define INPUTMUX_DMA0_OTRIG_INMUX_INP_SHIFT (0U) +#define INPUTMUX_DMA0_OTRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_OTRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA0_OTRIG_INMUX_INP_MASK) +/*! @} */ + +/* The count of INPUTMUX_DMA0_OTRIG_INMUX */ +#define INPUTMUX_DMA0_OTRIG_INMUX_COUNT (4U) + +/*! @name FREQMEAS_REF - Selection for frequency measurement reference clock */ +/*! @{ */ +#define INPUTMUX_FREQMEAS_REF_CLKIN_MASK (0x1FU) +#define INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT (0U) +#define INPUTMUX_FREQMEAS_REF_CLKIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_REF_CLKIN_MASK) +/*! @} */ + +/*! @name FREQMEAS_TARGET - Selection for frequency measurement target clock */ +/*! @{ */ +#define INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK (0x1FU) +#define INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT (0U) +#define INPUTMUX_FREQMEAS_TARGET_CLKIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK) +/*! @} */ + +/*! @name TIMER3CAPTSEL - Capture select registers for TIMER3 inputs */ +/*! @{ */ +#define INPUTMUX_TIMER3CAPTSEL_CAPTSEL_MASK (0x1FU) +#define INPUTMUX_TIMER3CAPTSEL_CAPTSEL_SHIFT (0U) +/*! CAPTSEL - Input number to TIMER3 capture inputs 0 to 4 + * 0b00000..CT_INP0 function selected from IOCON register + * 0b00001..CT_INP1 function selected from IOCON register + * 0b00010..CT_INP2 function selected from IOCON register + * 0b00011..CT_INP3 function selected from IOCON register + * 0b00100..CT_INP4 function selected from IOCON register + * 0b00101..CT_INP5 function selected from IOCON register + * 0b00110..CT_INP6 function selected from IOCON register + * 0b00111..CT_INP7 function selected from IOCON register + * 0b01000..CT_INP8 function selected from IOCON register + * 0b01001..CT_INP9 function selected from IOCON register + * 0b01010..CT_INP10 function selected from IOCON register + * 0b01011..CT_INP11 function selected from IOCON register + * 0b01100..CT_INP12 function selected from IOCON register + * 0b01101..CT_INP13 function selected from IOCON register + * 0b01110..CT_INP14 function selected from IOCON register + * 0b01111..CT_INP15 function selected from IOCON register + * 0b10000..CT_INP16 function selected from IOCON register + * 0b10001..CT_INP17 function selected from IOCON register + * 0b10010..CT_INP18 function selected from IOCON register + * 0b10011..CT_INP19 function selected from IOCON register + * 0b10100..USB0_FRAME_TOGGLE + * 0b10101..USB1_FRAME_TOGGLE + * 0b10110..COMP_OUTPUT output from analog comparator + * 0b10111..I2S_SHARED_WS[0] output from I2S pin sharing + * 0b11000..I2S_SHARED_WS[1] output from I2S pin sharing + * 0b11001-0b11111..None + */ +#define INPUTMUX_TIMER3CAPTSEL_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER3CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER3CAPTSEL_CAPTSEL_MASK) +/*! @} */ + +/* The count of INPUTMUX_TIMER3CAPTSEL */ +#define INPUTMUX_TIMER3CAPTSEL_COUNT (4U) + +/*! @name TIMER4CAPTSEL - Capture select registers for TIMER4 inputs */ +/*! @{ */ +#define INPUTMUX_TIMER4CAPTSEL_CAPTSEL_MASK (0x1FU) +#define INPUTMUX_TIMER4CAPTSEL_CAPTSEL_SHIFT (0U) +/*! CAPTSEL - Input number to TIMER4 capture inputs 0 to 4 + * 0b00000..CT_INP0 function selected from IOCON register + * 0b00001..CT_INP1 function selected from IOCON register + * 0b00010..CT_INP2 function selected from IOCON register + * 0b00011..CT_INP3 function selected from IOCON register + * 0b00100..CT_INP4 function selected from IOCON register + * 0b00101..CT_INP5 function selected from IOCON register + * 0b00110..CT_INP6 function selected from IOCON register + * 0b00111..CT_INP7 function selected from IOCON register + * 0b01000..CT_INP8 function selected from IOCON register + * 0b01001..CT_INP9 function selected from IOCON register + * 0b01010..CT_INP10 function selected from IOCON register + * 0b01011..CT_INP11 function selected from IOCON register + * 0b01100..CT_INP12 function selected from IOCON register + * 0b01101..CT_INP13 function selected from IOCON register + * 0b01110..CT_INP14 function selected from IOCON register + * 0b01111..CT_INP15 function selected from IOCON register + * 0b10000..CT_INP16 function selected from IOCON register + * 0b10001..CT_INP17 function selected from IOCON register + * 0b10010..CT_INP18 function selected from IOCON register + * 0b10011..CT_INP19 function selected from IOCON register + * 0b10100..USB0_FRAME_TOGGLE + * 0b10101..USB1_FRAME_TOGGLE + * 0b10110..COMP_OUTPUT output from analog comparator + * 0b10111..I2S_SHARED_WS[0] output from I2S pin sharing + * 0b11000..I2S_SHARED_WS[1] output from I2S pin sharing + * 0b11001-0b11111..None + */ +#define INPUTMUX_TIMER4CAPTSEL_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER4CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER4CAPTSEL_CAPTSEL_MASK) +/*! @} */ + +/* The count of INPUTMUX_TIMER4CAPTSEL */ +#define INPUTMUX_TIMER4CAPTSEL_COUNT (4U) + +/*! @name PINTSECSEL - Pin interrupt secure select register */ +/*! @{ */ +#define INPUTMUX_PINTSECSEL_INTPIN_MASK (0x3FU) +#define INPUTMUX_PINTSECSEL_INTPIN_SHIFT (0U) +#define INPUTMUX_PINTSECSEL_INTPIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PINTSECSEL_INTPIN_SHIFT)) & INPUTMUX_PINTSECSEL_INTPIN_MASK) +/*! @} */ + +/* The count of INPUTMUX_PINTSECSEL */ +#define INPUTMUX_PINTSECSEL_COUNT (2U) + +/*! @name DMA1_ITRIG_INMUX - Trigger select register for DMA1 channel */ +/*! @{ */ +#define INPUTMUX_DMA1_ITRIG_INMUX_INP_MASK (0xFU) +#define INPUTMUX_DMA1_ITRIG_INMUX_INP_SHIFT (0U) +/*! INP - Trigger input number (decimal value) for DMA channel n (n = 0 to 9). + * 0b0000..Pin interrupt 0 + * 0b0001..Pin interrupt 1 + * 0b0010..Pin interrupt 2 + * 0b0011..Pin interrupt 3 + * 0b0100..Timer CTIMER0 Match 0 + * 0b0101..Timer CTIMER0 Match 1 + * 0b0110..Timer CTIMER2 Match 0 + * 0b0111..Timer CTIMER4 Match 0 + * 0b1000..DMA1 output trigger mux 0 + * 0b1001..DMA1 output trigger mux 1 + * 0b1010..DMA1 output trigger mux 2 + * 0b1011..DMA1 output trigger mux 3 + * 0b1100..SCT0 DMA request 0 + * 0b1101..SCT0 DMA request 1 + * 0b1110..HASH DMA RX trigger + * 0b1111..None + */ +#define INPUTMUX_DMA1_ITRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA1_ITRIG_INMUX_INP_MASK) +/*! @} */ + +/* The count of INPUTMUX_DMA1_ITRIG_INMUX */ +#define INPUTMUX_DMA1_ITRIG_INMUX_COUNT (10U) + +/*! @name DMA1_OTRIG_INMUX - DMA1 output trigger selection to become DMA1 trigger */ +/*! @{ */ +#define INPUTMUX_DMA1_OTRIG_INMUX_INP_MASK (0xFU) +#define INPUTMUX_DMA1_OTRIG_INMUX_INP_SHIFT (0U) +#define INPUTMUX_DMA1_OTRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_OTRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA1_OTRIG_INMUX_INP_MASK) +/*! @} */ + +/* The count of INPUTMUX_DMA1_OTRIG_INMUX */ +#define INPUTMUX_DMA1_OTRIG_INMUX_COUNT (4U) + +/*! @name DMA0_REQ_ENA - Enable DMA0 requests */ +/*! @{ */ +#define INPUTMUX_DMA0_REQ_ENA_REQ_ENA_MASK (0x7FFFFFU) +#define INPUTMUX_DMA0_REQ_ENA_REQ_ENA_SHIFT (0U) +#define INPUTMUX_DMA0_REQ_ENA_REQ_ENA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENA_REQ_ENA_SHIFT)) & INPUTMUX_DMA0_REQ_ENA_REQ_ENA_MASK) +/*! @} */ + +/*! @name DMA0_REQ_ENA_SET - Set one or several bits in DMA0_REQ_ENA register */ +/*! @{ */ +#define INPUTMUX_DMA0_REQ_ENA_SET_SET_MASK (0x7FFFFFU) +#define INPUTMUX_DMA0_REQ_ENA_SET_SET_SHIFT (0U) +#define INPUTMUX_DMA0_REQ_ENA_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENA_SET_SET_SHIFT)) & INPUTMUX_DMA0_REQ_ENA_SET_SET_MASK) +/*! @} */ + +/*! @name DMA0_REQ_ENA_CLR - Clear one or several bits in DMA0_REQ_ENA register */ +/*! @{ */ +#define INPUTMUX_DMA0_REQ_ENA_CLR_CLR_MASK (0x7FFFFFU) +#define INPUTMUX_DMA0_REQ_ENA_CLR_CLR_SHIFT (0U) +#define INPUTMUX_DMA0_REQ_ENA_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENA_CLR_CLR_SHIFT)) & INPUTMUX_DMA0_REQ_ENA_CLR_CLR_MASK) +/*! @} */ + +/*! @name DMA1_REQ_ENA - Enable DMA1 requests */ +/*! @{ */ +#define INPUTMUX_DMA1_REQ_ENA_REQ_ENA_MASK (0x3FFU) +#define INPUTMUX_DMA1_REQ_ENA_REQ_ENA_SHIFT (0U) +#define INPUTMUX_DMA1_REQ_ENA_REQ_ENA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENA_REQ_ENA_SHIFT)) & INPUTMUX_DMA1_REQ_ENA_REQ_ENA_MASK) +/*! @} */ + +/*! @name DMA1_REQ_ENA_SET - Set one or several bits in DMA1_REQ_ENA register */ +/*! @{ */ +#define INPUTMUX_DMA1_REQ_ENA_SET_SET_MASK (0x3FFU) +#define INPUTMUX_DMA1_REQ_ENA_SET_SET_SHIFT (0U) +#define INPUTMUX_DMA1_REQ_ENA_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENA_SET_SET_SHIFT)) & INPUTMUX_DMA1_REQ_ENA_SET_SET_MASK) +/*! @} */ + +/*! @name DMA1_REQ_ENA_CLR - Clear one or several bits in DMA1_REQ_ENA register */ +/*! @{ */ +#define INPUTMUX_DMA1_REQ_ENA_CLR_CLR_MASK (0x3FFU) +#define INPUTMUX_DMA1_REQ_ENA_CLR_CLR_SHIFT (0U) +#define INPUTMUX_DMA1_REQ_ENA_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENA_CLR_CLR_SHIFT)) & INPUTMUX_DMA1_REQ_ENA_CLR_CLR_MASK) +/*! @} */ + +/*! @name DMA0_ITRIG_ENA - Enable DMA0 triggers */ +/*! @{ */ +#define INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA_MASK (0x3FFFFFU) +#define INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA_SHIFT (0U) +#define INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA_SHIFT)) & INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA_MASK) +/*! @} */ + +/*! @name DMA0_ITRIG_ENA_SET - Set one or several bits in DMA0_ITRIG_ENA register */ +/*! @{ */ +#define INPUTMUX_DMA0_ITRIG_ENA_SET_SET_MASK (0x3FFFFFU) +#define INPUTMUX_DMA0_ITRIG_ENA_SET_SET_SHIFT (0U) +#define INPUTMUX_DMA0_ITRIG_ENA_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIG_ENA_SET_SET_SHIFT)) & INPUTMUX_DMA0_ITRIG_ENA_SET_SET_MASK) +/*! @} */ + +/*! @name DMA0_ITRIG_ENA_CLR - Clear one or several bits in DMA0_ITRIG_ENA register */ +/*! @{ */ +#define INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR_MASK (0x3FFFFFU) +#define INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR_SHIFT (0U) +#define INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR_SHIFT)) & INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR_MASK) +/*! @} */ + +/*! @name DMA1_ITRIG_ENA - Enable DMA1 triggers */ +/*! @{ */ +#define INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA_MASK (0x7FFFU) +#define INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA_SHIFT (0U) +#define INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA_SHIFT)) & INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA_MASK) +/*! @} */ + +/*! @name DMA1_ITRIG_ENA_SET - Set one or several bits in DMA1_ITRIG_ENA register */ +/*! @{ */ +#define INPUTMUX_DMA1_ITRIG_ENA_SET_SET_MASK (0x7FFFU) +#define INPUTMUX_DMA1_ITRIG_ENA_SET_SET_SHIFT (0U) +#define INPUTMUX_DMA1_ITRIG_ENA_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIG_ENA_SET_SET_SHIFT)) & INPUTMUX_DMA1_ITRIG_ENA_SET_SET_MASK) +/*! @} */ + +/*! @name DMA1_ITRIG_ENA_CLR - Clear one or several bits in DMA1_ITRIG_ENA register */ +/*! @{ */ +#define INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR_MASK (0x7FFFU) +#define INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR_SHIFT (0U) +#define INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR_SHIFT)) & INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group INPUTMUX_Register_Masks */ + + +/* INPUTMUX - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral INPUTMUX base address */ + #define INPUTMUX_BASE (0x50006000u) + /** Peripheral INPUTMUX base address */ + #define INPUTMUX_BASE_NS (0x40006000u) + /** Peripheral INPUTMUX base pointer */ + #define INPUTMUX ((INPUTMUX_Type *)INPUTMUX_BASE) + /** Peripheral INPUTMUX base pointer */ + #define INPUTMUX_NS ((INPUTMUX_Type *)INPUTMUX_BASE_NS) + /** Array initializer of INPUTMUX peripheral base addresses */ + #define INPUTMUX_BASE_ADDRS { INPUTMUX_BASE } + /** Array initializer of INPUTMUX peripheral base pointers */ + #define INPUTMUX_BASE_PTRS { INPUTMUX } + /** Array initializer of INPUTMUX peripheral base addresses */ + #define INPUTMUX_BASE_ADDRS_NS { INPUTMUX_BASE_NS } + /** Array initializer of INPUTMUX peripheral base pointers */ + #define INPUTMUX_BASE_PTRS_NS { INPUTMUX_NS } +#else + /** Peripheral INPUTMUX base address */ + #define INPUTMUX_BASE (0x40006000u) + /** Peripheral INPUTMUX base pointer */ + #define INPUTMUX ((INPUTMUX_Type *)INPUTMUX_BASE) + /** Array initializer of INPUTMUX peripheral base addresses */ + #define INPUTMUX_BASE_ADDRS { INPUTMUX_BASE } + /** Array initializer of INPUTMUX peripheral base pointers */ + #define INPUTMUX_BASE_PTRS { INPUTMUX } +#endif + +/*! + * @} + */ /* end of group INPUTMUX_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- IOCON Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOCON_Peripheral_Access_Layer IOCON Peripheral Access Layer + * @{ + */ + +/** IOCON - Register Layout Typedef */ +typedef struct { + __IO uint32_t PIO[2][32]; /**< Digital I/O control for port 0 pins PIO0_0..Digital I/O control for port 1 pins PIO1_31, array offset: 0x0, array step: index*0x80, index2*0x4 */ +} IOCON_Type; + +/* ---------------------------------------------------------------------------- + -- IOCON Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOCON_Register_Masks IOCON Register Masks + * @{ + */ + +/*! @name PIO - Digital I/O control for port 0 pins PIO0_0..Digital I/O control for port 1 pins PIO1_31 */ +/*! @{ */ +#define IOCON_PIO_FUNC_MASK (0xFU) +#define IOCON_PIO_FUNC_SHIFT (0U) +/*! FUNC - Selects pin function. + * 0b0000..Alternative connection 0. + * 0b0001..Alternative connection 1. + * 0b0010..Alternative connection 2. + * 0b0011..Alternative connection 3. + * 0b0100..Alternative connection 4. + * 0b0101..Alternative connection 5. + * 0b0110..Alternative connection 6. + * 0b0111..Alternative connection 7. + */ +#define IOCON_PIO_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FUNC_SHIFT)) & IOCON_PIO_FUNC_MASK) +#define IOCON_PIO_MODE_MASK (0x30U) +#define IOCON_PIO_MODE_SHIFT (4U) +/*! MODE - Selects function mode (on-chip pull-up/pull-down resistor control). + * 0b00..Inactive. Inactive (no pull-down/pull-up resistor enabled). + * 0b01..Pull-down. Pull-down resistor enabled. + * 0b10..Pull-up. Pull-up resistor enabled. + * 0b11..Repeater. Repeater mode. + */ +#define IOCON_PIO_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_MODE_SHIFT)) & IOCON_PIO_MODE_MASK) +#define IOCON_PIO_SLEW_MASK (0x40U) +#define IOCON_PIO_SLEW_SHIFT (6U) +/*! SLEW - Driver slew rate. + * 0b0..Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + * 0b1..Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + */ +#define IOCON_PIO_SLEW(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_SLEW_SHIFT)) & IOCON_PIO_SLEW_MASK) +#define IOCON_PIO_INVERT_MASK (0x80U) +#define IOCON_PIO_INVERT_SHIFT (7U) +/*! INVERT - Input polarity. + * 0b0..Disabled. Input function is not inverted. + * 0b1..Enabled. Input is function inverted. + */ +#define IOCON_PIO_INVERT(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_INVERT_SHIFT)) & IOCON_PIO_INVERT_MASK) +#define IOCON_PIO_DIGIMODE_MASK (0x100U) +#define IOCON_PIO_DIGIMODE_SHIFT (8U) +/*! DIGIMODE - Select Digital mode. + * 0b0..Analog mode, digital input is disabled. + * 0b1..Digital mode, digital input is enabled. + */ +#define IOCON_PIO_DIGIMODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_DIGIMODE_SHIFT)) & IOCON_PIO_DIGIMODE_MASK) +#define IOCON_PIO_OD_MASK (0x200U) +#define IOCON_PIO_OD_SHIFT (9U) +/*! OD - Controls open-drain mode. + * 0b0..Normal. Normal push-pull output + * 0b1..Open-drain. Simulated open-drain output (high drive disabled). + */ +#define IOCON_PIO_OD(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_OD_SHIFT)) & IOCON_PIO_OD_MASK) +#define IOCON_PIO_ASW_MASK (0x400U) +#define IOCON_PIO_ASW_SHIFT (10U) +/*! ASW - Analog switch input control. Usable only if DIGIMODE = 0b0 + * 0b0..Analog switch is open. + * 0b1..Analog switch is closed. + */ +#define IOCON_PIO_ASW(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_ASW_SHIFT)) & IOCON_PIO_ASW_MASK) +#define IOCON_PIO_SSEL_MASK (0x800U) +#define IOCON_PIO_SSEL_SHIFT (11U) +/*! SSEL - Supply Selection bit. + * 0b0..3V3 Signaling in I2C Mode. + * 0b1..1V8 Signaling in I2C Mode. + */ +#define IOCON_PIO_SSEL(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_SSEL_SHIFT)) & IOCON_PIO_SSEL_MASK) +#define IOCON_PIO_FILTEROFF_MASK (0x1000U) +#define IOCON_PIO_FILTEROFF_SHIFT (12U) +/*! FILTEROFF - Controls input glitch filter. + * 0b0..Filter enabled. Noise pulses below approximately 10 ns are filtered out. + * 0b1..Filter disabled. No input filtering is done. + */ +#define IOCON_PIO_FILTEROFF(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FILTEROFF_SHIFT)) & IOCON_PIO_FILTEROFF_MASK) +#define IOCON_PIO_ECS_MASK (0x2000U) +#define IOCON_PIO_ECS_SHIFT (13U) +/*! ECS - Pull-up current source enable in IIC mode. + * 0b1..Enabled. Pull resistor is conencted. + * 0b0..Disabled. IO is in open drain. + */ +#define IOCON_PIO_ECS(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_ECS_SHIFT)) & IOCON_PIO_ECS_MASK) +#define IOCON_PIO_EGP_MASK (0x4000U) +#define IOCON_PIO_EGP_SHIFT (14U) +/*! EGP - Controls slew rate of I2C pad. + * 0b0..I2C mode. + * 0b1..GPIO mode. + */ +#define IOCON_PIO_EGP(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_EGP_SHIFT)) & IOCON_PIO_EGP_MASK) +#define IOCON_PIO_I2CFILTER_MASK (0x8000U) +#define IOCON_PIO_I2CFILTER_SHIFT (15U) +/*! I2CFILTER - Configures I2C features for standard mode, fast mode, and Fast Mode Plus operation. + * 0b0..I2C 50 ns glitch filter enabled. Typically used for Fast-mode and Fast-mode Plus I2C. + * 0b1..I2C 10 ns glitch filter enabled. Typically used for Standard-mode I2C. + */ +#define IOCON_PIO_I2CFILTER(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CFILTER_SHIFT)) & IOCON_PIO_I2CFILTER_MASK) +/*! @} */ + +/* The count of IOCON_PIO */ +#define IOCON_PIO_COUNT (2U) + +/* The count of IOCON_PIO */ +#define IOCON_PIO_COUNT2 (32U) + + +/*! + * @} + */ /* end of group IOCON_Register_Masks */ + + +/* IOCON - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral IOCON base address */ + #define IOCON_BASE (0x50001000u) + /** Peripheral IOCON base address */ + #define IOCON_BASE_NS (0x40001000u) + /** Peripheral IOCON base pointer */ + #define IOCON ((IOCON_Type *)IOCON_BASE) + /** Peripheral IOCON base pointer */ + #define IOCON_NS ((IOCON_Type *)IOCON_BASE_NS) + /** Array initializer of IOCON peripheral base addresses */ + #define IOCON_BASE_ADDRS { IOCON_BASE } + /** Array initializer of IOCON peripheral base pointers */ + #define IOCON_BASE_PTRS { IOCON } + /** Array initializer of IOCON peripheral base addresses */ + #define IOCON_BASE_ADDRS_NS { IOCON_BASE_NS } + /** Array initializer of IOCON peripheral base pointers */ + #define IOCON_BASE_PTRS_NS { IOCON_NS } +#else + /** Peripheral IOCON base address */ + #define IOCON_BASE (0x40001000u) + /** Peripheral IOCON base pointer */ + #define IOCON ((IOCON_Type *)IOCON_BASE) + /** Array initializer of IOCON peripheral base addresses */ + #define IOCON_BASE_ADDRS { IOCON_BASE } + /** Array initializer of IOCON peripheral base pointers */ + #define IOCON_BASE_PTRS { IOCON } +#endif + +/*! + * @} + */ /* end of group IOCON_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- MAILBOX Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MAILBOX_Peripheral_Access_Layer MAILBOX Peripheral Access Layer + * @{ + */ + +/** MAILBOX - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x10 */ + __IO uint32_t IRQ; /**< Interrupt request register for the Cortex-M0+ CPU., array offset: 0x0, array step: 0x10 */ + __O uint32_t IRQSET; /**< Set bits in IRQ0, array offset: 0x4, array step: 0x10 */ + __O uint32_t IRQCLR; /**< Clear bits in IRQ0, array offset: 0x8, array step: 0x10 */ + uint8_t RESERVED_0[4]; + } MBOXIRQ[2]; + uint8_t RESERVED_0[216]; + __IO uint32_t MUTEX; /**< Mutual exclusion register[1], offset: 0xF8 */ +} MAILBOX_Type; + +/* ---------------------------------------------------------------------------- + -- MAILBOX Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MAILBOX_Register_Masks MAILBOX Register Masks + * @{ + */ + +/*! @name MBOXIRQ_IRQ - Interrupt request register for the Cortex-M0+ CPU. */ +/*! @{ */ +#define MAILBOX_MBOXIRQ_IRQ_INTREQ_MASK (0xFFFFFFFFU) +#define MAILBOX_MBOXIRQ_IRQ_INTREQ_SHIFT (0U) +#define MAILBOX_MBOXIRQ_IRQ_INTREQ(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MBOXIRQ_IRQ_INTREQ_SHIFT)) & MAILBOX_MBOXIRQ_IRQ_INTREQ_MASK) +/*! @} */ + +/* The count of MAILBOX_MBOXIRQ_IRQ */ +#define MAILBOX_MBOXIRQ_IRQ_COUNT (2U) + +/*! @name MBOXIRQ_IRQSET - Set bits in IRQ0 */ +/*! @{ */ +#define MAILBOX_MBOXIRQ_IRQSET_INTREQSET_MASK (0xFFFFFFFFU) +#define MAILBOX_MBOXIRQ_IRQSET_INTREQSET_SHIFT (0U) +#define MAILBOX_MBOXIRQ_IRQSET_INTREQSET(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MBOXIRQ_IRQSET_INTREQSET_SHIFT)) & MAILBOX_MBOXIRQ_IRQSET_INTREQSET_MASK) +/*! @} */ + +/* The count of MAILBOX_MBOXIRQ_IRQSET */ +#define MAILBOX_MBOXIRQ_IRQSET_COUNT (2U) + +/*! @name MBOXIRQ_IRQCLR - Clear bits in IRQ0 */ +/*! @{ */ +#define MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_MASK (0xFFFFFFFFU) +#define MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_SHIFT (0U) +#define MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_SHIFT)) & MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_MASK) +/*! @} */ + +/* The count of MAILBOX_MBOXIRQ_IRQCLR */ +#define MAILBOX_MBOXIRQ_IRQCLR_COUNT (2U) + +/*! @name MUTEX - Mutual exclusion register[1] */ +/*! @{ */ +#define MAILBOX_MUTEX_EX_MASK (0x1U) +#define MAILBOX_MUTEX_EX_SHIFT (0U) +#define MAILBOX_MUTEX_EX(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MUTEX_EX_SHIFT)) & MAILBOX_MUTEX_EX_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group MAILBOX_Register_Masks */ + + +/* MAILBOX - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral MAILBOX base address */ + #define MAILBOX_BASE (0x5008B000u) + /** Peripheral MAILBOX base address */ + #define MAILBOX_BASE_NS (0x4008B000u) + /** Peripheral MAILBOX base pointer */ + #define MAILBOX ((MAILBOX_Type *)MAILBOX_BASE) + /** Peripheral MAILBOX base pointer */ + #define MAILBOX_NS ((MAILBOX_Type *)MAILBOX_BASE_NS) + /** Array initializer of MAILBOX peripheral base addresses */ + #define MAILBOX_BASE_ADDRS { MAILBOX_BASE } + /** Array initializer of MAILBOX peripheral base pointers */ + #define MAILBOX_BASE_PTRS { MAILBOX } + /** Array initializer of MAILBOX peripheral base addresses */ + #define MAILBOX_BASE_ADDRS_NS { MAILBOX_BASE_NS } + /** Array initializer of MAILBOX peripheral base pointers */ + #define MAILBOX_BASE_PTRS_NS { MAILBOX_NS } +#else + /** Peripheral MAILBOX base address */ + #define MAILBOX_BASE (0x4008B000u) + /** Peripheral MAILBOX base pointer */ + #define MAILBOX ((MAILBOX_Type *)MAILBOX_BASE) + /** Array initializer of MAILBOX peripheral base addresses */ + #define MAILBOX_BASE_ADDRS { MAILBOX_BASE } + /** Array initializer of MAILBOX peripheral base pointers */ + #define MAILBOX_BASE_PTRS { MAILBOX } +#endif +/** Interrupt vectors for the MAILBOX peripheral type */ +#define MAILBOX_IRQS { MAILBOX_IRQn } + +/*! + * @} + */ /* end of group MAILBOX_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- MRT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MRT_Peripheral_Access_Layer MRT Peripheral Access Layer + * @{ + */ + +/** MRT - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x10 */ + __IO uint32_t INTVAL; /**< MRT Time interval value register. This value is loaded into the TIMER register., array offset: 0x0, array step: 0x10 */ + __I uint32_t TIMER; /**< MRT Timer register. This register reads the value of the down-counter., array offset: 0x4, array step: 0x10 */ + __IO uint32_t CTRL; /**< MRT Control register. This register controls the MRT modes., array offset: 0x8, array step: 0x10 */ + __IO uint32_t STAT; /**< MRT Status register., array offset: 0xC, array step: 0x10 */ + } CHANNEL[4]; + uint8_t RESERVED_0[176]; + __IO uint32_t MODCFG; /**< Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature., offset: 0xF0 */ + __I uint32_t IDLE_CH; /**< Idle channel register. This register returns the number of the first idle channel., offset: 0xF4 */ + __IO uint32_t IRQ_FLAG; /**< Global interrupt flag register, offset: 0xF8 */ +} MRT_Type; + +/* ---------------------------------------------------------------------------- + -- MRT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MRT_Register_Masks MRT Register Masks + * @{ + */ + +/*! @name CHANNEL_INTVAL - MRT Time interval value register. This value is loaded into the TIMER register. */ +/*! @{ */ +#define MRT_CHANNEL_INTVAL_IVALUE_MASK (0xFFFFFFU) +#define MRT_CHANNEL_INTVAL_IVALUE_SHIFT (0U) +#define MRT_CHANNEL_INTVAL_IVALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_IVALUE_SHIFT)) & MRT_CHANNEL_INTVAL_IVALUE_MASK) +#define MRT_CHANNEL_INTVAL_LOAD_MASK (0x80000000U) +#define MRT_CHANNEL_INTVAL_LOAD_SHIFT (31U) +/*! LOAD - Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. + * This bit is write-only. Reading this bit always returns 0. + * 0b0..No force load. The load from the INTVALn register to the TIMERn register is processed at the end of the + * time interval if the repeat mode is selected. + * 0b1..Force load. The INTVALn interval value IVALUE -1 is immediately loaded into the TIMERn register while TIMERn is running. + */ +#define MRT_CHANNEL_INTVAL_LOAD(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_LOAD_SHIFT)) & MRT_CHANNEL_INTVAL_LOAD_MASK) +/*! @} */ + +/* The count of MRT_CHANNEL_INTVAL */ +#define MRT_CHANNEL_INTVAL_COUNT (4U) + +/*! @name CHANNEL_TIMER - MRT Timer register. This register reads the value of the down-counter. */ +/*! @{ */ +#define MRT_CHANNEL_TIMER_VALUE_MASK (0xFFFFFFU) +#define MRT_CHANNEL_TIMER_VALUE_SHIFT (0U) +#define MRT_CHANNEL_TIMER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_TIMER_VALUE_SHIFT)) & MRT_CHANNEL_TIMER_VALUE_MASK) +/*! @} */ + +/* The count of MRT_CHANNEL_TIMER */ +#define MRT_CHANNEL_TIMER_COUNT (4U) + +/*! @name CHANNEL_CTRL - MRT Control register. This register controls the MRT modes. */ +/*! @{ */ +#define MRT_CHANNEL_CTRL_INTEN_MASK (0x1U) +#define MRT_CHANNEL_CTRL_INTEN_SHIFT (0U) +/*! INTEN - Enable the TIMERn interrupt. + * 0b0..Disabled. TIMERn interrupt is disabled. + * 0b1..Enabled. TIMERn interrupt is enabled. + */ +#define MRT_CHANNEL_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_INTEN_SHIFT)) & MRT_CHANNEL_CTRL_INTEN_MASK) +#define MRT_CHANNEL_CTRL_MODE_MASK (0x6U) +#define MRT_CHANNEL_CTRL_MODE_SHIFT (1U) +/*! MODE - Selects timer mode. + * 0b00..Repeat interrupt mode. + * 0b01..One-shot interrupt mode. + * 0b10..One-shot stall mode. + * 0b11..Reserved. + */ +#define MRT_CHANNEL_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_MODE_SHIFT)) & MRT_CHANNEL_CTRL_MODE_MASK) +/*! @} */ + +/* The count of MRT_CHANNEL_CTRL */ +#define MRT_CHANNEL_CTRL_COUNT (4U) + +/*! @name CHANNEL_STAT - MRT Status register. */ +/*! @{ */ +#define MRT_CHANNEL_STAT_INTFLAG_MASK (0x1U) +#define MRT_CHANNEL_STAT_INTFLAG_SHIFT (0U) +/*! INTFLAG - Monitors the interrupt flag. + * 0b0..No pending interrupt. Writing a zero is equivalent to no operation. + * 0b1..Pending interrupt. The interrupt is pending because TIMERn has reached the end of the time interval. If + * the INTEN bit in the CONTROLn is also set to 1, the interrupt for timer channel n and the global interrupt + * are raised. Writing a 1 to this bit clears the interrupt request. + */ +#define MRT_CHANNEL_STAT_INTFLAG(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INTFLAG_SHIFT)) & MRT_CHANNEL_STAT_INTFLAG_MASK) +#define MRT_CHANNEL_STAT_RUN_MASK (0x2U) +#define MRT_CHANNEL_STAT_RUN_SHIFT (1U) +/*! RUN - Indicates the state of TIMERn. This bit is read-only. + * 0b0..Idle state. TIMERn is stopped. + * 0b1..Running. TIMERn is running. + */ +#define MRT_CHANNEL_STAT_RUN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_RUN_SHIFT)) & MRT_CHANNEL_STAT_RUN_MASK) +#define MRT_CHANNEL_STAT_INUSE_MASK (0x4U) +#define MRT_CHANNEL_STAT_INUSE_SHIFT (2U) +/*! INUSE - Channel In Use flag. Operating details depend on the MULTITASK bit in the MODCFG + * register, and affects the use of IDLE_CH. See Idle channel register for details of the two operating + * modes. + * 0b0..This channel is not in use. + * 0b1..This channel is in use. + */ +#define MRT_CHANNEL_STAT_INUSE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INUSE_SHIFT)) & MRT_CHANNEL_STAT_INUSE_MASK) +/*! @} */ + +/* The count of MRT_CHANNEL_STAT */ +#define MRT_CHANNEL_STAT_COUNT (4U) + +/*! @name MODCFG - Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature. */ +/*! @{ */ +#define MRT_MODCFG_NOC_MASK (0xFU) +#define MRT_MODCFG_NOC_SHIFT (0U) +#define MRT_MODCFG_NOC(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOC_SHIFT)) & MRT_MODCFG_NOC_MASK) +#define MRT_MODCFG_NOB_MASK (0x1F0U) +#define MRT_MODCFG_NOB_SHIFT (4U) +#define MRT_MODCFG_NOB(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOB_SHIFT)) & MRT_MODCFG_NOB_MASK) +#define MRT_MODCFG_MULTITASK_MASK (0x80000000U) +#define MRT_MODCFG_MULTITASK_SHIFT (31U) +/*! MULTITASK - Selects the operating mode for the INUSE flags and the IDLE_CH register. + * 0b0..Hardware status mode. In this mode, the INUSE(n) flags for all channels are reset. + * 0b1..Multi-task mode. + */ +#define MRT_MODCFG_MULTITASK(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_MULTITASK_SHIFT)) & MRT_MODCFG_MULTITASK_MASK) +/*! @} */ + +/*! @name IDLE_CH - Idle channel register. This register returns the number of the first idle channel. */ +/*! @{ */ +#define MRT_IDLE_CH_CHAN_MASK (0xF0U) +#define MRT_IDLE_CH_CHAN_SHIFT (4U) +#define MRT_IDLE_CH_CHAN(x) (((uint32_t)(((uint32_t)(x)) << MRT_IDLE_CH_CHAN_SHIFT)) & MRT_IDLE_CH_CHAN_MASK) +/*! @} */ + +/*! @name IRQ_FLAG - Global interrupt flag register */ +/*! @{ */ +#define MRT_IRQ_FLAG_GFLAG0_MASK (0x1U) +#define MRT_IRQ_FLAG_GFLAG0_SHIFT (0U) +/*! GFLAG0 - Monitors the interrupt flag of TIMER0. + * 0b0..No pending interrupt. Writing a zero is equivalent to no operation. + * 0b1..Pending interrupt. The interrupt is pending because TIMER0 has reached the end of the time interval. If + * the INTEN bit in the CONTROL0 register is also set to 1, the interrupt for timer channel 0 and the global + * interrupt are raised. Writing a 1 to this bit clears the interrupt request. + */ +#define MRT_IRQ_FLAG_GFLAG0(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG0_SHIFT)) & MRT_IRQ_FLAG_GFLAG0_MASK) +#define MRT_IRQ_FLAG_GFLAG1_MASK (0x2U) +#define MRT_IRQ_FLAG_GFLAG1_SHIFT (1U) +#define MRT_IRQ_FLAG_GFLAG1(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG1_SHIFT)) & MRT_IRQ_FLAG_GFLAG1_MASK) +#define MRT_IRQ_FLAG_GFLAG2_MASK (0x4U) +#define MRT_IRQ_FLAG_GFLAG2_SHIFT (2U) +#define MRT_IRQ_FLAG_GFLAG2(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG2_SHIFT)) & MRT_IRQ_FLAG_GFLAG2_MASK) +#define MRT_IRQ_FLAG_GFLAG3_MASK (0x8U) +#define MRT_IRQ_FLAG_GFLAG3_SHIFT (3U) +#define MRT_IRQ_FLAG_GFLAG3(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG3_SHIFT)) & MRT_IRQ_FLAG_GFLAG3_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group MRT_Register_Masks */ + + +/* MRT - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral MRT0 base address */ + #define MRT0_BASE (0x5000D000u) + /** Peripheral MRT0 base address */ + #define MRT0_BASE_NS (0x4000D000u) + /** Peripheral MRT0 base pointer */ + #define MRT0 ((MRT_Type *)MRT0_BASE) + /** Peripheral MRT0 base pointer */ + #define MRT0_NS ((MRT_Type *)MRT0_BASE_NS) + /** Array initializer of MRT peripheral base addresses */ + #define MRT_BASE_ADDRS { MRT0_BASE } + /** Array initializer of MRT peripheral base pointers */ + #define MRT_BASE_PTRS { MRT0 } + /** Array initializer of MRT peripheral base addresses */ + #define MRT_BASE_ADDRS_NS { MRT0_BASE_NS } + /** Array initializer of MRT peripheral base pointers */ + #define MRT_BASE_PTRS_NS { MRT0_NS } +#else + /** Peripheral MRT0 base address */ + #define MRT0_BASE (0x4000D000u) + /** Peripheral MRT0 base pointer */ + #define MRT0 ((MRT_Type *)MRT0_BASE) + /** Array initializer of MRT peripheral base addresses */ + #define MRT_BASE_ADDRS { MRT0_BASE } + /** Array initializer of MRT peripheral base pointers */ + #define MRT_BASE_PTRS { MRT0 } +#endif +/** Interrupt vectors for the MRT peripheral type */ +#define MRT_IRQS { MRT0_IRQn } + +/*! + * @} + */ /* end of group MRT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- OSTIMER Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OSTIMER_Peripheral_Access_Layer OSTIMER Peripheral Access Layer + * @{ + */ + +/** OSTIMER - Register Layout Typedef */ +typedef struct { + __I uint32_t EVTIMERL; /**< EVTIMER Low Register, offset: 0x0 */ + __I uint32_t EVTIMERH; /**< EVTIMER High Register, offset: 0x4 */ + __I uint32_t CAPTUREN_L; /**< Local Capture Low Register for CPUn, offset: 0x8 */ + __I uint32_t CAPTUREN_H; /**< Local Capture High Register for CPUn, offset: 0xC */ + __IO uint32_t MATCHN_L; /**< Local Match Low Register for CPUn, offset: 0x10 */ + __IO uint32_t MATCHN_H; /**< Match High Register for CPUn, offset: 0x14 */ + uint8_t RESERVED_0[4]; + __IO uint32_t OSEVENT_CTRL; /**< OS_EVENT TIMER Control Register for CPUn, offset: 0x1C */ +} OSTIMER_Type; + +/* ---------------------------------------------------------------------------- + -- OSTIMER Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OSTIMER_Register_Masks OSTIMER Register Masks + * @{ + */ + +/*! @name EVTIMERL - EVTIMER Low Register */ +/*! @{ */ +#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_MASK (0xFFFFFFFFU) +#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_SHIFT (0U) +#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_SHIFT)) & OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_MASK) +/*! @} */ + +/*! @name EVTIMERH - EVTIMER High Register */ +/*! @{ */ +#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_MASK (0xFFFFFFFFU) +#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_SHIFT (0U) +#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_SHIFT)) & OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_MASK) +/*! @} */ + +/*! @name CAPTUREN_L - Local Capture Low Register for CPUn */ +/*! @{ */ +#define OSTIMER_CAPTUREN_L_CAPTUREn_VALUE_MASK (0xFFFFFFFFU) +#define OSTIMER_CAPTUREN_L_CAPTUREn_VALUE_SHIFT (0U) +#define OSTIMER_CAPTUREN_L_CAPTUREn_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_CAPTUREN_L_CAPTUREn_VALUE_SHIFT)) & OSTIMER_CAPTUREN_L_CAPTUREn_VALUE_MASK) +/*! @} */ + +/*! @name CAPTUREN_H - Local Capture High Register for CPUn */ +/*! @{ */ +#define OSTIMER_CAPTUREN_H_CAPTUREn_VALUE_MASK (0xFFFFFFFFU) +#define OSTIMER_CAPTUREN_H_CAPTUREn_VALUE_SHIFT (0U) +#define OSTIMER_CAPTUREN_H_CAPTUREn_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_CAPTUREN_H_CAPTUREn_VALUE_SHIFT)) & OSTIMER_CAPTUREN_H_CAPTUREn_VALUE_MASK) +/*! @} */ + +/*! @name MATCHN_L - Local Match Low Register for CPUn */ +/*! @{ */ +#define OSTIMER_MATCHN_L_MATCHn_VALUE_MASK (0xFFFFFFFFU) +#define OSTIMER_MATCHN_L_MATCHn_VALUE_SHIFT (0U) +#define OSTIMER_MATCHN_L_MATCHn_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_MATCHN_L_MATCHn_VALUE_SHIFT)) & OSTIMER_MATCHN_L_MATCHn_VALUE_MASK) +/*! @} */ + +/*! @name MATCHN_H - Match High Register for CPUn */ +/*! @{ */ +#define OSTIMER_MATCHN_H_MATCHn_VALUE_MASK (0xFFFFFFFFU) +#define OSTIMER_MATCHN_H_MATCHn_VALUE_SHIFT (0U) +#define OSTIMER_MATCHN_H_MATCHn_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_MATCHN_H_MATCHn_VALUE_SHIFT)) & OSTIMER_MATCHN_H_MATCHn_VALUE_MASK) +/*! @} */ + +/*! @name OSEVENT_CTRL - OS_EVENT TIMER Control Register for CPUn */ +/*! @{ */ +#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK (0x1U) +#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_SHIFT (0U) +#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_SHIFT)) & OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK) +#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK (0x2U) +#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_SHIFT (1U) +#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_SHIFT)) & OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group OSTIMER_Register_Masks */ + + +/* OSTIMER - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral OSTIMER base address */ + #define OSTIMER_BASE (0x5002D000u) + /** Peripheral OSTIMER base address */ + #define OSTIMER_BASE_NS (0x4002D000u) + /** Peripheral OSTIMER base pointer */ + #define OSTIMER ((OSTIMER_Type *)OSTIMER_BASE) + /** Peripheral OSTIMER base pointer */ + #define OSTIMER_NS ((OSTIMER_Type *)OSTIMER_BASE_NS) + /** Array initializer of OSTIMER peripheral base addresses */ + #define OSTIMER_BASE_ADDRS { OSTIMER_BASE } + /** Array initializer of OSTIMER peripheral base pointers */ + #define OSTIMER_BASE_PTRS { OSTIMER } + /** Array initializer of OSTIMER peripheral base addresses */ + #define OSTIMER_BASE_ADDRS_NS { OSTIMER_BASE_NS } + /** Array initializer of OSTIMER peripheral base pointers */ + #define OSTIMER_BASE_PTRS_NS { OSTIMER_NS } +#else + /** Peripheral OSTIMER base address */ + #define OSTIMER_BASE (0x4002D000u) + /** Peripheral OSTIMER base pointer */ + #define OSTIMER ((OSTIMER_Type *)OSTIMER_BASE) + /** Array initializer of OSTIMER peripheral base addresses */ + #define OSTIMER_BASE_ADDRS { OSTIMER_BASE } + /** Array initializer of OSTIMER peripheral base pointers */ + #define OSTIMER_BASE_PTRS { OSTIMER } +#endif +/** Interrupt vectors for the OSTIMER peripheral type */ +#define OSTIMER_IRQS { OS_EVENT_IRQn } + +/*! + * @} + */ /* end of group OSTIMER_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PINT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PINT_Peripheral_Access_Layer PINT Peripheral Access Layer + * @{ + */ + +/** PINT - Register Layout Typedef */ +typedef struct { + __IO uint32_t ISEL; /**< Pin Interrupt Mode register, offset: 0x0 */ + __IO uint32_t IENR; /**< Pin interrupt level or rising edge interrupt enable register, offset: 0x4 */ + __O uint32_t SIENR; /**< Pin interrupt level or rising edge interrupt set register, offset: 0x8 */ + __O uint32_t CIENR; /**< Pin interrupt level (rising edge interrupt) clear register, offset: 0xC */ + __IO uint32_t IENF; /**< Pin interrupt active level or falling edge interrupt enable register, offset: 0x10 */ + __O uint32_t SIENF; /**< Pin interrupt active level or falling edge interrupt set register, offset: 0x14 */ + __O uint32_t CIENF; /**< Pin interrupt active level or falling edge interrupt clear register, offset: 0x18 */ + __IO uint32_t RISE; /**< Pin interrupt rising edge register, offset: 0x1C */ + __IO uint32_t FALL; /**< Pin interrupt falling edge register, offset: 0x20 */ + __IO uint32_t IST; /**< Pin interrupt status register, offset: 0x24 */ + __IO uint32_t PMCTRL; /**< Pattern match interrupt control register, offset: 0x28 */ + __IO uint32_t PMSRC; /**< Pattern match interrupt bit-slice source register, offset: 0x2C */ + __IO uint32_t PMCFG; /**< Pattern match interrupt bit slice configuration register, offset: 0x30 */ +} PINT_Type; + +/* ---------------------------------------------------------------------------- + -- PINT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PINT_Register_Masks PINT Register Masks + * @{ + */ + +/*! @name ISEL - Pin Interrupt Mode register */ +/*! @{ */ +#define PINT_ISEL_PMODE_MASK (0xFFU) +#define PINT_ISEL_PMODE_SHIFT (0U) +#define PINT_ISEL_PMODE(x) (((uint32_t)(((uint32_t)(x)) << PINT_ISEL_PMODE_SHIFT)) & PINT_ISEL_PMODE_MASK) +/*! @} */ + +/*! @name IENR - Pin interrupt level or rising edge interrupt enable register */ +/*! @{ */ +#define PINT_IENR_ENRL_MASK (0xFFU) +#define PINT_IENR_ENRL_SHIFT (0U) +#define PINT_IENR_ENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENR_ENRL_SHIFT)) & PINT_IENR_ENRL_MASK) +/*! @} */ + +/*! @name SIENR - Pin interrupt level or rising edge interrupt set register */ +/*! @{ */ +#define PINT_SIENR_SETENRL_MASK (0xFFU) +#define PINT_SIENR_SETENRL_SHIFT (0U) +#define PINT_SIENR_SETENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENR_SETENRL_SHIFT)) & PINT_SIENR_SETENRL_MASK) +/*! @} */ + +/*! @name CIENR - Pin interrupt level (rising edge interrupt) clear register */ +/*! @{ */ +#define PINT_CIENR_CENRL_MASK (0xFFU) +#define PINT_CIENR_CENRL_SHIFT (0U) +#define PINT_CIENR_CENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENR_CENRL_SHIFT)) & PINT_CIENR_CENRL_MASK) +/*! @} */ + +/*! @name IENF - Pin interrupt active level or falling edge interrupt enable register */ +/*! @{ */ +#define PINT_IENF_ENAF_MASK (0xFFU) +#define PINT_IENF_ENAF_SHIFT (0U) +#define PINT_IENF_ENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENF_ENAF_SHIFT)) & PINT_IENF_ENAF_MASK) +/*! @} */ + +/*! @name SIENF - Pin interrupt active level or falling edge interrupt set register */ +/*! @{ */ +#define PINT_SIENF_SETENAF_MASK (0xFFU) +#define PINT_SIENF_SETENAF_SHIFT (0U) +#define PINT_SIENF_SETENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENF_SETENAF_SHIFT)) & PINT_SIENF_SETENAF_MASK) +/*! @} */ + +/*! @name CIENF - Pin interrupt active level or falling edge interrupt clear register */ +/*! @{ */ +#define PINT_CIENF_CENAF_MASK (0xFFU) +#define PINT_CIENF_CENAF_SHIFT (0U) +#define PINT_CIENF_CENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENF_CENAF_SHIFT)) & PINT_CIENF_CENAF_MASK) +/*! @} */ + +/*! @name RISE - Pin interrupt rising edge register */ +/*! @{ */ +#define PINT_RISE_RDET_MASK (0xFFU) +#define PINT_RISE_RDET_SHIFT (0U) +#define PINT_RISE_RDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_RISE_RDET_SHIFT)) & PINT_RISE_RDET_MASK) +/*! @} */ + +/*! @name FALL - Pin interrupt falling edge register */ +/*! @{ */ +#define PINT_FALL_FDET_MASK (0xFFU) +#define PINT_FALL_FDET_SHIFT (0U) +#define PINT_FALL_FDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_FALL_FDET_SHIFT)) & PINT_FALL_FDET_MASK) +/*! @} */ + +/*! @name IST - Pin interrupt status register */ +/*! @{ */ +#define PINT_IST_PSTAT_MASK (0xFFU) +#define PINT_IST_PSTAT_SHIFT (0U) +#define PINT_IST_PSTAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_IST_PSTAT_SHIFT)) & PINT_IST_PSTAT_MASK) +/*! @} */ + +/*! @name PMCTRL - Pattern match interrupt control register */ +/*! @{ */ +#define PINT_PMCTRL_SEL_PMATCH_MASK (0x1U) +#define PINT_PMCTRL_SEL_PMATCH_SHIFT (0U) +/*! SEL_PMATCH - Specifies whether the 8 pin interrupts are controlled by the pin interrupt function or by the pattern match function. + * 0b0..Pin interrupt. Interrupts are driven in response to the standard pin interrupt function. + * 0b1..Pattern match. Interrupts are driven in response to pattern matches. + */ +#define PINT_PMCTRL_SEL_PMATCH(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_SEL_PMATCH_SHIFT)) & PINT_PMCTRL_SEL_PMATCH_MASK) +#define PINT_PMCTRL_ENA_RXEV_MASK (0x2U) +#define PINT_PMCTRL_ENA_RXEV_SHIFT (1U) +/*! ENA_RXEV - Enables the RXEV output to the CPU and/or to a GPIO output when the specified boolean expression evaluates to true. + * 0b0..Disabled. RXEV output to the CPU is disabled. + * 0b1..Enabled. RXEV output to the CPU is enabled. + */ +#define PINT_PMCTRL_ENA_RXEV(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_ENA_RXEV_SHIFT)) & PINT_PMCTRL_ENA_RXEV_MASK) +#define PINT_PMCTRL_PMAT_MASK (0xFF000000U) +#define PINT_PMCTRL_PMAT_SHIFT (24U) +#define PINT_PMCTRL_PMAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_PMAT_SHIFT)) & PINT_PMCTRL_PMAT_MASK) +/*! @} */ + +/*! @name PMSRC - Pattern match interrupt bit-slice source register */ +/*! @{ */ +#define PINT_PMSRC_SRC0_MASK (0x700U) +#define PINT_PMSRC_SRC0_SHIFT (8U) +/*! SRC0 - Selects the input source for bit slice 0 + * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 0. + * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 0. + * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 0. + * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 0. + * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 0. + * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 0. + * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 0. + * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 0. + */ +#define PINT_PMSRC_SRC0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC0_SHIFT)) & PINT_PMSRC_SRC0_MASK) +#define PINT_PMSRC_SRC1_MASK (0x3800U) +#define PINT_PMSRC_SRC1_SHIFT (11U) +/*! SRC1 - Selects the input source for bit slice 1 + * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 1. + * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 1. + * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 1. + * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 1. + * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 1. + * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 1. + * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 1. + * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 1. + */ +#define PINT_PMSRC_SRC1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC1_SHIFT)) & PINT_PMSRC_SRC1_MASK) +#define PINT_PMSRC_SRC2_MASK (0x1C000U) +#define PINT_PMSRC_SRC2_SHIFT (14U) +/*! SRC2 - Selects the input source for bit slice 2 + * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 2. + * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 2. + * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 2. + * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 2. + * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 2. + * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 2. + * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 2. + * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 2. + */ +#define PINT_PMSRC_SRC2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC2_SHIFT)) & PINT_PMSRC_SRC2_MASK) +#define PINT_PMSRC_SRC3_MASK (0xE0000U) +#define PINT_PMSRC_SRC3_SHIFT (17U) +/*! SRC3 - Selects the input source for bit slice 3 + * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 3. + * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 3. + * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 3. + * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 3. + * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 3. + * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 3. + * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 3. + * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 3. + */ +#define PINT_PMSRC_SRC3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC3_SHIFT)) & PINT_PMSRC_SRC3_MASK) +#define PINT_PMSRC_SRC4_MASK (0x700000U) +#define PINT_PMSRC_SRC4_SHIFT (20U) +/*! SRC4 - Selects the input source for bit slice 4 + * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 4. + * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 4. + * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 4. + * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 4. + * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 4. + * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 4. + * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 4. + * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 4. + */ +#define PINT_PMSRC_SRC4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC4_SHIFT)) & PINT_PMSRC_SRC4_MASK) +#define PINT_PMSRC_SRC5_MASK (0x3800000U) +#define PINT_PMSRC_SRC5_SHIFT (23U) +/*! SRC5 - Selects the input source for bit slice 5 + * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 5. + * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 5. + * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 5. + * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 5. + * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 5. + * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 5. + * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 5. + * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 5. + */ +#define PINT_PMSRC_SRC5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC5_SHIFT)) & PINT_PMSRC_SRC5_MASK) +#define PINT_PMSRC_SRC6_MASK (0x1C000000U) +#define PINT_PMSRC_SRC6_SHIFT (26U) +/*! SRC6 - Selects the input source for bit slice 6 + * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 6. + * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 6. + * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 6. + * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 6. + * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 6. + * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 6. + * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 6. + * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 6. + */ +#define PINT_PMSRC_SRC6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC6_SHIFT)) & PINT_PMSRC_SRC6_MASK) +#define PINT_PMSRC_SRC7_MASK (0xE0000000U) +#define PINT_PMSRC_SRC7_SHIFT (29U) +/*! SRC7 - Selects the input source for bit slice 7 + * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 7. + * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 7. + * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 7. + * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 7. + * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 7. + * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 7. + * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 7. + * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 7. + */ +#define PINT_PMSRC_SRC7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC7_SHIFT)) & PINT_PMSRC_SRC7_MASK) +/*! @} */ + +/*! @name PMCFG - Pattern match interrupt bit slice configuration register */ +/*! @{ */ +#define PINT_PMCFG_PROD_ENDPTS0_MASK (0x1U) +#define PINT_PMCFG_PROD_ENDPTS0_SHIFT (0U) +/*! PROD_ENDPTS0 - Determines whether slice 0 is an endpoint. + * 0b0..No effect. Slice 0 is not an endpoint. + * 0b1..endpoint. Slice 0 is the endpoint of a product term (minterm). Pin interrupt 0 in the NVIC is raised if the minterm evaluates as true. + */ +#define PINT_PMCFG_PROD_ENDPTS0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS0_SHIFT)) & PINT_PMCFG_PROD_ENDPTS0_MASK) +#define PINT_PMCFG_PROD_ENDPTS1_MASK (0x2U) +#define PINT_PMCFG_PROD_ENDPTS1_SHIFT (1U) +/*! PROD_ENDPTS1 - Determines whether slice 1 is an endpoint. + * 0b0..No effect. Slice 1 is not an endpoint. + * 0b1..endpoint. Slice 1 is the endpoint of a product term (minterm). Pin interrupt 1 in the NVIC is raised if the minterm evaluates as true. + */ +#define PINT_PMCFG_PROD_ENDPTS1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS1_SHIFT)) & PINT_PMCFG_PROD_ENDPTS1_MASK) +#define PINT_PMCFG_PROD_ENDPTS2_MASK (0x4U) +#define PINT_PMCFG_PROD_ENDPTS2_SHIFT (2U) +/*! PROD_ENDPTS2 - Determines whether slice 2 is an endpoint. + * 0b0..No effect. Slice 2 is not an endpoint. + * 0b1..endpoint. Slice 2 is the endpoint of a product term (minterm). Pin interrupt 2 in the NVIC is raised if the minterm evaluates as true. + */ +#define PINT_PMCFG_PROD_ENDPTS2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS2_SHIFT)) & PINT_PMCFG_PROD_ENDPTS2_MASK) +#define PINT_PMCFG_PROD_ENDPTS3_MASK (0x8U) +#define PINT_PMCFG_PROD_ENDPTS3_SHIFT (3U) +/*! PROD_ENDPTS3 - Determines whether slice 3 is an endpoint. + * 0b0..No effect. Slice 3 is not an endpoint. + * 0b1..endpoint. Slice 3 is the endpoint of a product term (minterm). Pin interrupt 3 in the NVIC is raised if the minterm evaluates as true. + */ +#define PINT_PMCFG_PROD_ENDPTS3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS3_SHIFT)) & PINT_PMCFG_PROD_ENDPTS3_MASK) +#define PINT_PMCFG_PROD_ENDPTS4_MASK (0x10U) +#define PINT_PMCFG_PROD_ENDPTS4_SHIFT (4U) +/*! PROD_ENDPTS4 - Determines whether slice 4 is an endpoint. + * 0b0..No effect. Slice 4 is not an endpoint. + * 0b1..endpoint. Slice 4 is the endpoint of a product term (minterm). Pin interrupt 4 in the NVIC is raised if the minterm evaluates as true. + */ +#define PINT_PMCFG_PROD_ENDPTS4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS4_SHIFT)) & PINT_PMCFG_PROD_ENDPTS4_MASK) +#define PINT_PMCFG_PROD_ENDPTS5_MASK (0x20U) +#define PINT_PMCFG_PROD_ENDPTS5_SHIFT (5U) +/*! PROD_ENDPTS5 - Determines whether slice 5 is an endpoint. + * 0b0..No effect. Slice 5 is not an endpoint. + * 0b1..endpoint. Slice 5 is the endpoint of a product term (minterm). Pin interrupt 5 in the NVIC is raised if the minterm evaluates as true. + */ +#define PINT_PMCFG_PROD_ENDPTS5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS5_SHIFT)) & PINT_PMCFG_PROD_ENDPTS5_MASK) +#define PINT_PMCFG_PROD_ENDPTS6_MASK (0x40U) +#define PINT_PMCFG_PROD_ENDPTS6_SHIFT (6U) +/*! PROD_ENDPTS6 - Determines whether slice 6 is an endpoint. + * 0b0..No effect. Slice 6 is not an endpoint. + * 0b1..endpoint. Slice 6 is the endpoint of a product term (minterm). Pin interrupt 6 in the NVIC is raised if the minterm evaluates as true. + */ +#define PINT_PMCFG_PROD_ENDPTS6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS6_SHIFT)) & PINT_PMCFG_PROD_ENDPTS6_MASK) +#define PINT_PMCFG_CFG0_MASK (0x700U) +#define PINT_PMCFG_CFG0_SHIFT (8U) +/*! CFG0 - Specifies the match contribution condition for bit slice 0. + * 0b000..Constant HIGH. This bit slice always contributes to a product term match. + * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input + * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only + * cleared when the PMCFG or the PMSRC registers are written to. + * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + * 0b101..Low level. Match occurs when there is a low level on the specified input. + * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or + * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit + * is cleared after one clock cycle. + */ +#define PINT_PMCFG_CFG0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG0_SHIFT)) & PINT_PMCFG_CFG0_MASK) +#define PINT_PMCFG_CFG1_MASK (0x3800U) +#define PINT_PMCFG_CFG1_SHIFT (11U) +/*! CFG1 - Specifies the match contribution condition for bit slice 1. + * 0b000..Constant HIGH. This bit slice always contributes to a product term match. + * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input + * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only + * cleared when the PMCFG or the PMSRC registers are written to. + * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + * 0b101..Low level. Match occurs when there is a low level on the specified input. + * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or + * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit + * is cleared after one clock cycle. + */ +#define PINT_PMCFG_CFG1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG1_SHIFT)) & PINT_PMCFG_CFG1_MASK) +#define PINT_PMCFG_CFG2_MASK (0x1C000U) +#define PINT_PMCFG_CFG2_SHIFT (14U) +/*! CFG2 - Specifies the match contribution condition for bit slice 2. + * 0b000..Constant HIGH. This bit slice always contributes to a product term match. + * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input + * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only + * cleared when the PMCFG or the PMSRC registers are written to. + * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + * 0b101..Low level. Match occurs when there is a low level on the specified input. + * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or + * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit + * is cleared after one clock cycle. + */ +#define PINT_PMCFG_CFG2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG2_SHIFT)) & PINT_PMCFG_CFG2_MASK) +#define PINT_PMCFG_CFG3_MASK (0xE0000U) +#define PINT_PMCFG_CFG3_SHIFT (17U) +/*! CFG3 - Specifies the match contribution condition for bit slice 3. + * 0b000..Constant HIGH. This bit slice always contributes to a product term match. + * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input + * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only + * cleared when the PMCFG or the PMSRC registers are written to. + * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + * 0b101..Low level. Match occurs when there is a low level on the specified input. + * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or + * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit + * is cleared after one clock cycle. + */ +#define PINT_PMCFG_CFG3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG3_SHIFT)) & PINT_PMCFG_CFG3_MASK) +#define PINT_PMCFG_CFG4_MASK (0x700000U) +#define PINT_PMCFG_CFG4_SHIFT (20U) +/*! CFG4 - Specifies the match contribution condition for bit slice 4. + * 0b000..Constant HIGH. This bit slice always contributes to a product term match. + * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input + * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only + * cleared when the PMCFG or the PMSRC registers are written to. + * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + * 0b101..Low level. Match occurs when there is a low level on the specified input. + * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or + * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit + * is cleared after one clock cycle. + */ +#define PINT_PMCFG_CFG4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG4_SHIFT)) & PINT_PMCFG_CFG4_MASK) +#define PINT_PMCFG_CFG5_MASK (0x3800000U) +#define PINT_PMCFG_CFG5_SHIFT (23U) +/*! CFG5 - Specifies the match contribution condition for bit slice 5. + * 0b000..Constant HIGH. This bit slice always contributes to a product term match. + * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input + * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only + * cleared when the PMCFG or the PMSRC registers are written to. + * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + * 0b101..Low level. Match occurs when there is a low level on the specified input. + * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or + * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit + * is cleared after one clock cycle. + */ +#define PINT_PMCFG_CFG5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG5_SHIFT)) & PINT_PMCFG_CFG5_MASK) +#define PINT_PMCFG_CFG6_MASK (0x1C000000U) +#define PINT_PMCFG_CFG6_SHIFT (26U) +/*! CFG6 - Specifies the match contribution condition for bit slice 6. + * 0b000..Constant HIGH. This bit slice always contributes to a product term match. + * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input + * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only + * cleared when the PMCFG or the PMSRC registers are written to. + * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + * 0b101..Low level. Match occurs when there is a low level on the specified input. + * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or + * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit + * is cleared after one clock cycle. + */ +#define PINT_PMCFG_CFG6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG6_SHIFT)) & PINT_PMCFG_CFG6_MASK) +#define PINT_PMCFG_CFG7_MASK (0xE0000000U) +#define PINT_PMCFG_CFG7_SHIFT (29U) +/*! CFG7 - Specifies the match contribution condition for bit slice 7. + * 0b000..Constant HIGH. This bit slice always contributes to a product term match. + * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input + * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only + * cleared when the PMCFG or the PMSRC registers are written to. + * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + * 0b101..Low level. Match occurs when there is a low level on the specified input. + * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or + * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit + * is cleared after one clock cycle. + */ +#define PINT_PMCFG_CFG7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG7_SHIFT)) & PINT_PMCFG_CFG7_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group PINT_Register_Masks */ + + +/* PINT - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral PINT base address */ + #define PINT_BASE (0x50004000u) + /** Peripheral PINT base address */ + #define PINT_BASE_NS (0x40004000u) + /** Peripheral PINT base pointer */ + #define PINT ((PINT_Type *)PINT_BASE) + /** Peripheral PINT base pointer */ + #define PINT_NS ((PINT_Type *)PINT_BASE_NS) + /** Peripheral SECPINT base address */ + #define SECPINT_BASE (0x50005000u) + /** Peripheral SECPINT base address */ + #define SECPINT_BASE_NS (0x40005000u) + /** Peripheral SECPINT base pointer */ + #define SECPINT ((PINT_Type *)SECPINT_BASE) + /** Peripheral SECPINT base pointer */ + #define SECPINT_NS ((PINT_Type *)SECPINT_BASE_NS) + /** Array initializer of PINT peripheral base addresses */ + #define PINT_BASE_ADDRS { PINT_BASE, SECPINT_BASE } + /** Array initializer of PINT peripheral base pointers */ + #define PINT_BASE_PTRS { PINT, SECPINT } + /** Array initializer of PINT peripheral base addresses */ + #define PINT_BASE_ADDRS_NS { PINT_BASE_NS, SECPINT_BASE_NS } + /** Array initializer of PINT peripheral base pointers */ + #define PINT_BASE_PTRS_NS { PINT_NS, SECPINT_NS } +#else + /** Peripheral PINT base address */ + #define PINT_BASE (0x40004000u) + /** Peripheral PINT base pointer */ + #define PINT ((PINT_Type *)PINT_BASE) + /** Peripheral SECPINT base address */ + #define SECPINT_BASE (0x40005000u) + /** Peripheral SECPINT base pointer */ + #define SECPINT ((PINT_Type *)SECPINT_BASE) + /** Array initializer of PINT peripheral base addresses */ + #define PINT_BASE_ADDRS { PINT_BASE, SECPINT_BASE } + /** Array initializer of PINT peripheral base pointers */ + #define PINT_BASE_PTRS { PINT, SECPINT } +#endif +/** Interrupt vectors for the PINT peripheral type */ +#define PINT_IRQS { PIN_INT0_IRQn, PIN_INT1_IRQn, PIN_INT2_IRQn, PIN_INT3_IRQn, PIN_INT4_IRQn, PIN_INT5_IRQn, PIN_INT6_IRQn, PIN_INT7_IRQn, SEC_GPIO_INT0_IRQ0_IRQn, SEC_GPIO_INT0_IRQ1_IRQn } + +/*! + * @} + */ /* end of group PINT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PLU Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PLU_Peripheral_Access_Layer PLU Peripheral Access Layer + * @{ + */ + +/** PLU - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x20 */ + __IO uint32_t INP[5]; /**< LUT0 input 0 MUX..LUT25 input 4 MUX, array offset: 0x0, array step: index*0x20, index2*0x4 */ + uint8_t RESERVED_0[12]; + } LUT[26]; + uint8_t RESERVED_0[1216]; + __IO uint32_t LUT_TRUTH[26]; /**< Specifies the Truth Table contents for LUT0..Specifies the Truth Table contents for LUT25, array offset: 0x800, array step: 0x4 */ + uint8_t RESERVED_1[152]; + __I uint32_t OUTPUTS; /**< Provides the current state of the 8 designated PLU Outputs., offset: 0x900 */ + __IO uint32_t WAKEINT; /**< Wakeup interrupt control for PLU, offset: 0x904 */ + uint8_t RESERVED_2[760]; + __IO uint32_t OUTPUT_MUX[8]; /**< Selects the source to be connected to PLU Output 0..Selects the source to be connected to PLU Output 7, array offset: 0xC00, array step: 0x4 */ +} PLU_Type; + +/* ---------------------------------------------------------------------------- + -- PLU Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PLU_Register_Masks PLU Register Masks + * @{ + */ + +/*! @name LUT_INP - LUT0 input 0 MUX..LUT25 input 4 MUX */ +/*! @{ */ +#define PLU_LUT_INP_LUT_INP_MASK (0x3FU) +#define PLU_LUT_INP_LUT_INP_SHIFT (0U) +/*! LUT_INP - Selects the input source to be connected to LUT25 input4. + * 0b000000..The PLU primary inputs 0. + * 0b000001..The PLU primary inputs 1. + * 0b000010..The PLU primary inputs 2. + * 0b000011..The PLU primary inputs 3. + * 0b000100..The PLU primary inputs 4. + * 0b000101..The PLU primary inputs 5. + * 0b000110..Tie low. + * 0b000111..The output of LUT1. + * 0b001000..The output of LUT2. + * 0b001001..The output of LUT3. + * 0b001010..The output of LUT4. + * 0b001011..The output of LUT5. + * 0b001100..The output of LUT6. + * 0b001101..The output of LUT7. + * 0b001110..The output of LUT8. + * 0b001111..The output of LUT9. + * 0b010000..The output of LUT10. + * 0b010001..The output of LUT11. + * 0b010010..The output of LUT12. + * 0b010011..The output of LUT13. + * 0b010100..The output of LUT14. + * 0b010101..The output of LUT15. + * 0b010110..The output of LUT16. + * 0b010111..The output of LUT17. + * 0b011000..The output of LUT18. + * 0b011001..The output of LUT19. + * 0b011010..The output of LUT20. + * 0b011011..The output of LUT21. + * 0b011100..The output of LUT22. + * 0b011101..The output of LUT23. + * 0b011110..The output of LUT24. + * 0b011111..The output of LUT25. + * 0b100000..state(0). + * 0b100001..state(1). + * 0b100010..state(2). + * 0b100011..state(3). + */ +#define PLU_LUT_INP_LUT_INP(x) (((uint32_t)(((uint32_t)(x)) << PLU_LUT_INP_LUT_INP_SHIFT)) & PLU_LUT_INP_LUT_INP_MASK) +/*! @} */ + +/* The count of PLU_LUT_INP */ +#define PLU_LUT_INP_COUNT (26U) + +/* The count of PLU_LUT_INP */ +#define PLU_LUT_INP_COUNT2 (5U) + +/*! @name LUT_T_LUT_TRUTH - Specifies the Truth Table contents for LUT0..Specifies the Truth Table contents for LUT25 */ +/*! @{ */ +#define PLU_LUT_T_LUT_TRUTH_TRUTH_TABLE_MASK (0xFFFFFFFFU) +#define PLU_LUT_T_LUT_TRUTH_TRUTH_TABLE_SHIFT (0U) +#define PLU_LUT_T_LUT_TRUTH_TRUTH_TABLE(x) (((uint32_t)(((uint32_t)(x)) << PLU_LUT_T_LUT_TRUTH_TRUTH_TABLE_SHIFT)) & PLU_LUT_T_LUT_TRUTH_TRUTH_TABLE_MASK) +/*! @} */ + +/* The count of PLU_LUT_T_LUT_TRUTH */ +#define PLU_LUT_T_LUT_TRUTH_COUNT (26U) + +/*! @name OUTPUTS - Provides the current state of the 8 designated PLU Outputs. */ +/*! @{ */ +#define PLU_OUTPUTS_OUTPUT_STATE_MASK (0xFFU) +#define PLU_OUTPUTS_OUTPUT_STATE_SHIFT (0U) +#define PLU_OUTPUTS_OUTPUT_STATE(x) (((uint32_t)(((uint32_t)(x)) << PLU_OUTPUTS_OUTPUT_STATE_SHIFT)) & PLU_OUTPUTS_OUTPUT_STATE_MASK) +/*! @} */ + +/*! @name WAKEINT - Wakeup interrupt control for PLU */ +/*! @{ */ +#define PLU_WAKEINT_MASK_MASK (0xFFU) +#define PLU_WAKEINT_MASK_SHIFT (0U) +#define PLU_WAKEINT_MASK(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_MASK_SHIFT)) & PLU_WAKEINT_MASK_MASK) +#define PLU_WAKEINT_FILTER_MODE_MASK (0x300U) +#define PLU_WAKEINT_FILTER_MODE_SHIFT (8U) +/*! FILTER_MODE - control input of the PLU, add filtering for glitch + * 0b00..Bypass mode. + * 0b01..Filter 1 clock period. + * 0b10..Filter 2 clock period. + * 0b11..Filter 3 clock period. + */ +#define PLU_WAKEINT_FILTER_MODE(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_FILTER_MODE_SHIFT)) & PLU_WAKEINT_FILTER_MODE_MASK) +#define PLU_WAKEINT_FILTER_CLKSEL_MASK (0xC00U) +#define PLU_WAKEINT_FILTER_CLKSEL_SHIFT (10U) +#define PLU_WAKEINT_FILTER_CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_FILTER_CLKSEL_SHIFT)) & PLU_WAKEINT_FILTER_CLKSEL_MASK) +#define PLU_WAKEINT_LATCH_ENABLE_MASK (0x1000U) +#define PLU_WAKEINT_LATCH_ENABLE_SHIFT (12U) +#define PLU_WAKEINT_LATCH_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_LATCH_ENABLE_SHIFT)) & PLU_WAKEINT_LATCH_ENABLE_MASK) +#define PLU_WAKEINT_INTR_CLEAR_MASK (0x2000U) +#define PLU_WAKEINT_INTR_CLEAR_SHIFT (13U) +#define PLU_WAKEINT_INTR_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_INTR_CLEAR_SHIFT)) & PLU_WAKEINT_INTR_CLEAR_MASK) +/*! @} */ + +/*! @name OUTPUT_MUX - Selects the source to be connected to PLU Output 0..Selects the source to be connected to PLU Output 7 */ +/*! @{ */ +#define PLU_OUTPUT_MUX_OUTPUTn_MASK (0x1FU) +#define PLU_OUTPUT_MUX_OUTPUTn_SHIFT (0U) +/*! OUTPUTn - Selects the source to be connected to PLU Output 7. + * 0b00000..The PLU output 0. + * 0b00001..The PLU output 1. + * 0b00010..The PLU output 2. + * 0b00011..The PLU output 3. + * 0b00100..The PLU output 4. + * 0b00101..The PLU output 5. + * 0b00110..The PLU output 6. + * 0b00111..The PLU output 7. + * 0b01000..The PLU output 8. + * 0b01001..The PLU output 9. + * 0b01010..The PLU output 10. + * 0b01011..The PLU output 11. + * 0b01100..The PLU output 12. + * 0b01101..The PLU output 13. + * 0b01110..The PLU output 14. + * 0b01111..The PLU output 15. + * 0b10000..The PLU output 16. + * 0b10001..The PLU output 17. + * 0b10010..The PLU output 18. + * 0b10011..The PLU output 19. + * 0b10100..The PLU output 20. + * 0b10101..The PLU output 21. + * 0b10110..The PLU output 22. + * 0b10111..The PLU output 23. + * 0b11000..The PLU output 24. + * 0b11001..The PLU output 25. + * 0b11010..state(0). + * 0b11011..state(1). + * 0b11100..state(2). + * 0b11101..state(3). + */ +#define PLU_OUTPUT_MUX_OUTPUTn(x) (((uint32_t)(((uint32_t)(x)) << PLU_OUTPUT_MUX_OUTPUTn_SHIFT)) & PLU_OUTPUT_MUX_OUTPUTn_MASK) +/*! @} */ + +/* The count of PLU_OUTPUT_MUX */ +#define PLU_OUTPUT_MUX_COUNT (8U) + + +/*! + * @} + */ /* end of group PLU_Register_Masks */ + + +/* PLU - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral PLU base address */ + #define PLU_BASE (0x5003D000u) + /** Peripheral PLU base address */ + #define PLU_BASE_NS (0x4003D000u) + /** Peripheral PLU base pointer */ + #define PLU ((PLU_Type *)PLU_BASE) + /** Peripheral PLU base pointer */ + #define PLU_NS ((PLU_Type *)PLU_BASE_NS) + /** Array initializer of PLU peripheral base addresses */ + #define PLU_BASE_ADDRS { PLU_BASE } + /** Array initializer of PLU peripheral base pointers */ + #define PLU_BASE_PTRS { PLU } + /** Array initializer of PLU peripheral base addresses */ + #define PLU_BASE_ADDRS_NS { PLU_BASE_NS } + /** Array initializer of PLU peripheral base pointers */ + #define PLU_BASE_PTRS_NS { PLU_NS } +#else + /** Peripheral PLU base address */ + #define PLU_BASE (0x4003D000u) + /** Peripheral PLU base pointer */ + #define PLU ((PLU_Type *)PLU_BASE) + /** Array initializer of PLU peripheral base addresses */ + #define PLU_BASE_ADDRS { PLU_BASE } + /** Array initializer of PLU peripheral base pointers */ + #define PLU_BASE_PTRS { PLU } +#endif + +/*! + * @} + */ /* end of group PLU_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PMC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer + * @{ + */ + +/** PMC - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[8]; + __IO uint32_t RESETCTRL; /**< Reset Control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x8 */ + __IO uint32_t RESETCAUSE; /**< Reset Cause register [Reset by: PoR], offset: 0xC */ + uint8_t RESERVED_1[32]; + __IO uint32_t BODVBAT; /**< VBAT Brown Out Dectector (BoD) control register [Reset by: PoR, Pin Reset, Software Reset], offset: 0x30 */ + uint8_t RESERVED_2[4]; + __IO uint32_t BODCORE; /**< Digital Core logic Brown Out Dectector control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x38 */ + uint8_t RESERVED_3[8]; + __IO uint32_t FRO1M; /**< 1 MHz Free Running Oscillator control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x44 */ + __IO uint32_t FRO32K; /**< 32 KHz Free Running Oscillator (FRO) control register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x48 */ + __IO uint32_t XTAL32K; /**< 32 KHz Crystal oscillator (XTAL) control register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x4C */ + __IO uint32_t COMP; /**< Analog Comparator control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x50 */ + uint8_t RESERVED_4[20]; + __IO uint32_t WAKEIOCAUSE; /**< Allows to identify the Wake-up I/O source from Deep Power Down mode, offset: 0x68 */ + uint8_t RESERVED_5[8]; + __IO uint32_t STATUSCLK; /**< FRO and XTAL status register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x74 */ + uint8_t RESERVED_6[12]; + __IO uint32_t AOREG1; /**< General purpose always on domain data storage [Reset by: PoR, Brown Out Detectors Reset], offset: 0x84 */ + uint8_t RESERVED_7[16]; + __IO uint32_t RTCOSC32K; /**< RTC 1 KHZ and 1 Hz clocks source control register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x98 */ + __IO uint32_t OSTIMERr; /**< OS Timer control register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x9C */ + uint8_t RESERVED_8[16]; + __IO uint32_t PDSLEEPCFG0; /**< Controls the power to various modules during Low Power modes - DEEP SLEEP, POWER DOWN and DEEP POWER DOWN [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Software Reset], offset: 0xB0 */ + uint8_t RESERVED_9[4]; + __IO uint32_t PDRUNCFG0; /**< Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0xB8 */ + uint8_t RESERVED_10[4]; + __O uint32_t PDRUNCFGSET0; /**< Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0xC0 */ + uint8_t RESERVED_11[4]; + __O uint32_t PDRUNCFGCLR0; /**< Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0xC8 */ +} PMC_Type; + +/* ---------------------------------------------------------------------------- + -- PMC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PMC_Register_Masks PMC Register Masks + * @{ + */ + +/*! @name RESETCTRL - Reset Control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ +/*! @{ */ +#define PMC_RESETCTRL_DPDWAKEUPRESETENABLE_MASK (0x1U) +#define PMC_RESETCTRL_DPDWAKEUPRESETENABLE_SHIFT (0U) +/*! DPDWAKEUPRESETENABLE - Wake-up from DEEP POWER DOWN reset event (either from wake up I/O or RTC or OS Event Timer). + * 0b0..Reset event from DEEP POWER DOWN mode is disable. + * 0b1..Reset event from DEEP POWER DOWN mode is enable. + */ +#define PMC_RESETCTRL_DPDWAKEUPRESETENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_DPDWAKEUPRESETENABLE_SHIFT)) & PMC_RESETCTRL_DPDWAKEUPRESETENABLE_MASK) +#define PMC_RESETCTRL_BODVBATRESETENABLE_MASK (0x2U) +#define PMC_RESETCTRL_BODVBATRESETENABLE_SHIFT (1U) +/*! BODVBATRESETENABLE - BOD VBAT reset enable. + * 0b0..BOD VBAT reset is disable. + * 0b1..BOD VBAT reset is enable. + */ +#define PMC_RESETCTRL_BODVBATRESETENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_BODVBATRESETENABLE_SHIFT)) & PMC_RESETCTRL_BODVBATRESETENABLE_MASK) +#define PMC_RESETCTRL_BODCORERESETENABLE_MASK (0x4U) +#define PMC_RESETCTRL_BODCORERESETENABLE_SHIFT (2U) +/*! BODCORERESETENABLE - BOD CORE reset enable. + * 0b0..BOD CORE reset is disable. + * 0b1..BOD CORE reset is enable. + */ +#define PMC_RESETCTRL_BODCORERESETENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_BODCORERESETENABLE_SHIFT)) & PMC_RESETCTRL_BODCORERESETENABLE_MASK) +#define PMC_RESETCTRL_SWRRESETENABLE_MASK (0x8U) +#define PMC_RESETCTRL_SWRRESETENABLE_SHIFT (3U) +/*! SWRRESETENABLE - Software reset enable. + * 0b0..Software reset is disable. + * 0b1..Software reset is enable. + */ +#define PMC_RESETCTRL_SWRRESETENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_SWRRESETENABLE_SHIFT)) & PMC_RESETCTRL_SWRRESETENABLE_MASK) +/*! @} */ + +/*! @name RESETCAUSE - Reset Cause register [Reset by: PoR] */ +/*! @{ */ +#define PMC_RESETCAUSE_POR_MASK (0x1U) +#define PMC_RESETCAUSE_POR_SHIFT (0U) +#define PMC_RESETCAUSE_POR(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_POR_SHIFT)) & PMC_RESETCAUSE_POR_MASK) +#define PMC_RESETCAUSE_PADRESET_MASK (0x2U) +#define PMC_RESETCAUSE_PADRESET_SHIFT (1U) +#define PMC_RESETCAUSE_PADRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_PADRESET_SHIFT)) & PMC_RESETCAUSE_PADRESET_MASK) +#define PMC_RESETCAUSE_BODRESET_MASK (0x4U) +#define PMC_RESETCAUSE_BODRESET_SHIFT (2U) +#define PMC_RESETCAUSE_BODRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_BODRESET_SHIFT)) & PMC_RESETCAUSE_BODRESET_MASK) +#define PMC_RESETCAUSE_SYSTEMRESET_MASK (0x8U) +#define PMC_RESETCAUSE_SYSTEMRESET_SHIFT (3U) +#define PMC_RESETCAUSE_SYSTEMRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_SYSTEMRESET_SHIFT)) & PMC_RESETCAUSE_SYSTEMRESET_MASK) +#define PMC_RESETCAUSE_WDTRESET_MASK (0x10U) +#define PMC_RESETCAUSE_WDTRESET_SHIFT (4U) +#define PMC_RESETCAUSE_WDTRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_WDTRESET_SHIFT)) & PMC_RESETCAUSE_WDTRESET_MASK) +#define PMC_RESETCAUSE_SWRRESET_MASK (0x20U) +#define PMC_RESETCAUSE_SWRRESET_SHIFT (5U) +#define PMC_RESETCAUSE_SWRRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_SWRRESET_SHIFT)) & PMC_RESETCAUSE_SWRRESET_MASK) +#define PMC_RESETCAUSE_DPDRESET_WAKEUPIO_MASK (0x40U) +#define PMC_RESETCAUSE_DPDRESET_WAKEUPIO_SHIFT (6U) +#define PMC_RESETCAUSE_DPDRESET_WAKEUPIO(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_DPDRESET_WAKEUPIO_SHIFT)) & PMC_RESETCAUSE_DPDRESET_WAKEUPIO_MASK) +#define PMC_RESETCAUSE_DPDRESET_RTC_MASK (0x80U) +#define PMC_RESETCAUSE_DPDRESET_RTC_SHIFT (7U) +#define PMC_RESETCAUSE_DPDRESET_RTC(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_DPDRESET_RTC_SHIFT)) & PMC_RESETCAUSE_DPDRESET_RTC_MASK) +#define PMC_RESETCAUSE_DPDRESET_OSTIMER_MASK (0x100U) +#define PMC_RESETCAUSE_DPDRESET_OSTIMER_SHIFT (8U) +#define PMC_RESETCAUSE_DPDRESET_OSTIMER(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_DPDRESET_OSTIMER_SHIFT)) & PMC_RESETCAUSE_DPDRESET_OSTIMER_MASK) +/*! @} */ + +/*! @name BODVBAT - VBAT Brown Out Dectector (BoD) control register [Reset by: PoR, Pin Reset, Software Reset] */ +/*! @{ */ +#define PMC_BODVBAT_TRIGLVL_MASK (0x1FU) +#define PMC_BODVBAT_TRIGLVL_SHIFT (0U) +/*! TRIGLVL - BoD trigger level. + * 0b00000..1.00 V. + * 0b00001..1.10 V. + * 0b00010..1.20 V. + * 0b00011..1.30 V. + * 0b00100..1.40 V. + * 0b00101..1.50 V. + * 0b00110..1.60 V. + * 0b00111..1.65 V. + * 0b01000..1.70 V. + * 0b01001..1.75 V. + * 0b01010..1.80 V. + * 0b01011..1.90 V. + * 0b01100..2.00 V. + * 0b01101..2.10 V. + * 0b01110..2.20 V. + * 0b01111..2.30 V. + * 0b10000..2.40 V. + * 0b10001..2.50 V. + * 0b10010..2.60 V. + * 0b10011..2.70 V. + * 0b10100..2.806 V. + * 0b10101..2.90 V. + * 0b10110..3.00 V. + * 0b10111..3.10 V. + * 0b11000..3.20 V. + * 0b11001..3.30 V. + * 0b11010..3.30 V. + * 0b11011..3.30 V. + * 0b11100..3.30 V. + * 0b11101..3.30 V. + * 0b11110..3.30 V. + * 0b11111..3.30 V. + */ +#define PMC_BODVBAT_TRIGLVL(x) (((uint32_t)(((uint32_t)(x)) << PMC_BODVBAT_TRIGLVL_SHIFT)) & PMC_BODVBAT_TRIGLVL_MASK) +#define PMC_BODVBAT_HYST_MASK (0x60U) +#define PMC_BODVBAT_HYST_SHIFT (5U) +/*! HYST - BoD Hysteresis control. + * 0b00..25 mV. + * 0b01..50 mV. + * 0b10..75 mV. + * 0b11..100 mV. + */ +#define PMC_BODVBAT_HYST(x) (((uint32_t)(((uint32_t)(x)) << PMC_BODVBAT_HYST_SHIFT)) & PMC_BODVBAT_HYST_MASK) +/*! @} */ + +/*! @name BODCORE - Digital Core logic Brown Out Dectector control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ +/*! @{ */ +#define PMC_BODCORE_TRIGLVL_MASK (0x7U) +#define PMC_BODCORE_TRIGLVL_SHIFT (0U) +/*! TRIGLVL - BoD trigger level. + * 0b000..0.60 V. + * 0b001..0.65 V. + * 0b010..0.70 V. + * 0b011..0.75 V. + * 0b100..0.80 V. + * 0b101..0.85 V. + * 0b110..0.90 V. + * 0b111..0.95 V. + */ +#define PMC_BODCORE_TRIGLVL(x) (((uint32_t)(((uint32_t)(x)) << PMC_BODCORE_TRIGLVL_SHIFT)) & PMC_BODCORE_TRIGLVL_MASK) +#define PMC_BODCORE_HYST_MASK (0x30U) +#define PMC_BODCORE_HYST_SHIFT (4U) +/*! HYST - BoD Core Hysteresis control. + * 0b00..25 mV. + * 0b01..50 mV. + * 0b10..75 mV. + * 0b11..100 mV. + */ +#define PMC_BODCORE_HYST(x) (((uint32_t)(((uint32_t)(x)) << PMC_BODCORE_HYST_SHIFT)) & PMC_BODCORE_HYST_MASK) +/*! @} */ + +/*! @name FRO1M - 1 MHz Free Running Oscillator control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ +/*! @{ */ +#define PMC_FRO1M_FREQSEL_MASK (0x7FU) +#define PMC_FRO1M_FREQSEL_SHIFT (0U) +#define PMC_FRO1M_FREQSEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_FRO1M_FREQSEL_SHIFT)) & PMC_FRO1M_FREQSEL_MASK) +#define PMC_FRO1M_ATBCTRL_MASK (0x180U) +#define PMC_FRO1M_ATBCTRL_SHIFT (7U) +#define PMC_FRO1M_ATBCTRL(x) (((uint32_t)(((uint32_t)(x)) << PMC_FRO1M_ATBCTRL_SHIFT)) & PMC_FRO1M_ATBCTRL_MASK) +#define PMC_FRO1M_DIVSEL_MASK (0x3E00U) +#define PMC_FRO1M_DIVSEL_SHIFT (9U) +/*! DIVSEL - Divider selection bits. + * 0b00000..2.0. + * 0b00001..4.0. + * 0b00010..6.0. + * 0b00011..8.0. + * 0b00100..10.0. + * 0b00101..12.0. + * 0b00110..14.0. + * 0b00111..16.0. + * 0b01000..18.0. + * 0b01001..20.0. + * 0b01010..22.0. + * 0b01011..24.0. + * 0b01100..26.0. + * 0b01101..28.0. + * 0b01110..30.0. + * 0b01111..32.0. + * 0b10000..34.0. + * 0b10001..36.0. + * 0b10010..38.0. + * 0b10011..40.0. + * 0b10100..42.0. + * 0b10101..44.0. + * 0b10110..46.0. + * 0b10111..48.0. + * 0b11000..50.0. + * 0b11001..52.0. + * 0b11010..54.0. + * 0b11011..56.0. + * 0b11100..58.0. + * 0b11101..60.0. + * 0b11110..62.0. + * 0b11111..1.0. + */ +#define PMC_FRO1M_DIVSEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_FRO1M_DIVSEL_SHIFT)) & PMC_FRO1M_DIVSEL_MASK) +/*! @} */ + +/*! @name FRO32K - 32 KHz Free Running Oscillator (FRO) control register [Reset by: PoR, Brown Out Detectors Reset] */ +/*! @{ */ +#define PMC_FRO32K_NTAT_MASK (0xEU) +#define PMC_FRO32K_NTAT_SHIFT (1U) +#define PMC_FRO32K_NTAT(x) (((uint32_t)(((uint32_t)(x)) << PMC_FRO32K_NTAT_SHIFT)) & PMC_FRO32K_NTAT_MASK) +#define PMC_FRO32K_PTAT_MASK (0x70U) +#define PMC_FRO32K_PTAT_SHIFT (4U) +#define PMC_FRO32K_PTAT(x) (((uint32_t)(((uint32_t)(x)) << PMC_FRO32K_PTAT_SHIFT)) & PMC_FRO32K_PTAT_MASK) +#define PMC_FRO32K_CAPCAL_MASK (0xFF80U) +#define PMC_FRO32K_CAPCAL_SHIFT (7U) +#define PMC_FRO32K_CAPCAL(x) (((uint32_t)(((uint32_t)(x)) << PMC_FRO32K_CAPCAL_SHIFT)) & PMC_FRO32K_CAPCAL_MASK) +#define PMC_FRO32K_ATBCTRL_MASK (0x30000U) +#define PMC_FRO32K_ATBCTRL_SHIFT (16U) +#define PMC_FRO32K_ATBCTRL(x) (((uint32_t)(((uint32_t)(x)) << PMC_FRO32K_ATBCTRL_SHIFT)) & PMC_FRO32K_ATBCTRL_MASK) +/*! @} */ + +/*! @name XTAL32K - 32 KHz Crystal oscillator (XTAL) control register [Reset by: PoR, Brown Out Detectors Reset] */ +/*! @{ */ +#define PMC_XTAL32K_IREF_MASK (0x6U) +#define PMC_XTAL32K_IREF_SHIFT (1U) +#define PMC_XTAL32K_IREF(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_IREF_SHIFT)) & PMC_XTAL32K_IREF_MASK) +#define PMC_XTAL32K_TEST_MASK (0x8U) +#define PMC_XTAL32K_TEST_SHIFT (3U) +#define PMC_XTAL32K_TEST(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_TEST_SHIFT)) & PMC_XTAL32K_TEST_MASK) +#define PMC_XTAL32K_IBIAS_MASK (0x30U) +#define PMC_XTAL32K_IBIAS_SHIFT (4U) +#define PMC_XTAL32K_IBIAS(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_IBIAS_SHIFT)) & PMC_XTAL32K_IBIAS_MASK) +#define PMC_XTAL32K_AMPL_MASK (0xC0U) +#define PMC_XTAL32K_AMPL_SHIFT (6U) +#define PMC_XTAL32K_AMPL(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_AMPL_SHIFT)) & PMC_XTAL32K_AMPL_MASK) +#define PMC_XTAL32K_CAPBANKIN_MASK (0x7F00U) +#define PMC_XTAL32K_CAPBANKIN_SHIFT (8U) +#define PMC_XTAL32K_CAPBANKIN(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPBANKIN_SHIFT)) & PMC_XTAL32K_CAPBANKIN_MASK) +#define PMC_XTAL32K_CAPBANKOUT_MASK (0x3F8000U) +#define PMC_XTAL32K_CAPBANKOUT_SHIFT (15U) +#define PMC_XTAL32K_CAPBANKOUT(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPBANKOUT_SHIFT)) & PMC_XTAL32K_CAPBANKOUT_MASK) +#define PMC_XTAL32K_CAPTESTSTARTSRCSEL_MASK (0x400000U) +#define PMC_XTAL32K_CAPTESTSTARTSRCSEL_SHIFT (22U) +/*! CAPTESTSTARTSRCSEL - Source selection for xo32k_captest_start_ao_set. + * 0b0..Sourced from CAPTESTSTART. + * 0b1..Sourced from calibration. + */ +#define PMC_XTAL32K_CAPTESTSTARTSRCSEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPTESTSTARTSRCSEL_SHIFT)) & PMC_XTAL32K_CAPTESTSTARTSRCSEL_MASK) +#define PMC_XTAL32K_CAPTESTSTART_MASK (0x800000U) +#define PMC_XTAL32K_CAPTESTSTART_SHIFT (23U) +#define PMC_XTAL32K_CAPTESTSTART(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPTESTSTART_SHIFT)) & PMC_XTAL32K_CAPTESTSTART_MASK) +#define PMC_XTAL32K_CAPTESTENABLE_MASK (0x1000000U) +#define PMC_XTAL32K_CAPTESTENABLE_SHIFT (24U) +#define PMC_XTAL32K_CAPTESTENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPTESTENABLE_SHIFT)) & PMC_XTAL32K_CAPTESTENABLE_MASK) +#define PMC_XTAL32K_CAPTESTOSCINSEL_MASK (0x2000000U) +#define PMC_XTAL32K_CAPTESTOSCINSEL_SHIFT (25U) +/*! CAPTESTOSCINSEL - Select the input for test. + * 0b0..Oscillator output pin (osc_out). + * 0b1..Oscillator input pin (osc_in). + */ +#define PMC_XTAL32K_CAPTESTOSCINSEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPTESTOSCINSEL_SHIFT)) & PMC_XTAL32K_CAPTESTOSCINSEL_MASK) +/*! @} */ + +/*! @name COMP - Analog Comparator control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ +/*! @{ */ +#define PMC_COMP_HYST_MASK (0x2U) +#define PMC_COMP_HYST_SHIFT (1U) +/*! HYST - Hysteris when hyst = '1'. + * 0b0..Hysteresis is disable. + * 0b1..Hysteresis is enable. + */ +#define PMC_COMP_HYST(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_HYST_SHIFT)) & PMC_COMP_HYST_MASK) +#define PMC_COMP_VREFINPUT_MASK (0x4U) +#define PMC_COMP_VREFINPUT_SHIFT (2U) +/*! VREFINPUT - Dedicated control bit to select between internal VREF and VDDA (for the resistive ladder). + * 0b0..Select internal VREF. + * 0b1..Select VDDA. + */ +#define PMC_COMP_VREFINPUT(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_VREFINPUT_SHIFT)) & PMC_COMP_VREFINPUT_MASK) +#define PMC_COMP_LOWPOWER_MASK (0x8U) +#define PMC_COMP_LOWPOWER_SHIFT (3U) +/*! LOWPOWER - Low power mode. + * 0b0..High speed mode. + * 0b1..Low power mode (Low speed). + */ +#define PMC_COMP_LOWPOWER(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_LOWPOWER_SHIFT)) & PMC_COMP_LOWPOWER_MASK) +#define PMC_COMP_PMUX_MASK (0x70U) +#define PMC_COMP_PMUX_SHIFT (4U) +/*! PMUX - Control word for P multiplexer:. + * 0b000..VREF (See fiedl VREFINPUT). + * 0b001..Pin P0_0. + * 0b010..Pin P0_9. + * 0b011..Pin P0_18. + * 0b100..Pin P1_14. + * 0b101..Pin P2_23. + */ +#define PMC_COMP_PMUX(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_PMUX_SHIFT)) & PMC_COMP_PMUX_MASK) +#define PMC_COMP_NMUX_MASK (0x380U) +#define PMC_COMP_NMUX_SHIFT (7U) +/*! NMUX - Control word for N multiplexer:. + * 0b000..VREF (See field VREFINPUT). + * 0b001..Pin P0_0. + * 0b010..Pin P0_9. + * 0b011..Pin P0_18. + * 0b100..Pin P1_14. + * 0b101..Pin P2_23. + */ +#define PMC_COMP_NMUX(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_NMUX_SHIFT)) & PMC_COMP_NMUX_MASK) +#define PMC_COMP_VREF_MASK (0x7C00U) +#define PMC_COMP_VREF_SHIFT (10U) +#define PMC_COMP_VREF(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_VREF_SHIFT)) & PMC_COMP_VREF_MASK) +#define PMC_COMP_FILTERCGF_SAMPLEMODE_MASK (0x30000U) +#define PMC_COMP_FILTERCGF_SAMPLEMODE_SHIFT (16U) +#define PMC_COMP_FILTERCGF_SAMPLEMODE(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_FILTERCGF_SAMPLEMODE_SHIFT)) & PMC_COMP_FILTERCGF_SAMPLEMODE_MASK) +#define PMC_COMP_FILTERCGF_CLKDIV_MASK (0x1C0000U) +#define PMC_COMP_FILTERCGF_CLKDIV_SHIFT (18U) +#define PMC_COMP_FILTERCGF_CLKDIV(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_FILTERCGF_CLKDIV_SHIFT)) & PMC_COMP_FILTERCGF_CLKDIV_MASK) +#define PMC_COMP_PMUXCAPT_MASK (0xE00000U) +#define PMC_COMP_PMUXCAPT_SHIFT (21U) +#define PMC_COMP_PMUXCAPT(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_PMUXCAPT_SHIFT)) & PMC_COMP_PMUXCAPT_MASK) +/*! @} */ + +/*! @name WAKEIOCAUSE - Allows to identify the Wake-up I/O source from Deep Power Down mode */ +/*! @{ */ +#define PMC_WAKEIOCAUSE_WAKEUP0_MASK (0x1U) +#define PMC_WAKEIOCAUSE_WAKEUP0_SHIFT (0U) +/*! WAKEUP0 - Allows to identify Wake up I/O 0 as the wake-up source from Deep Power Down mode. + * 0b0..Last wake up from Deep Power down mode was NOT triggred by wake up I/O 0. + * 0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 0. + */ +#define PMC_WAKEIOCAUSE_WAKEUP0(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP0_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP0_MASK) +#define PMC_WAKEIOCAUSE_WAKEUP1_MASK (0x2U) +#define PMC_WAKEIOCAUSE_WAKEUP1_SHIFT (1U) +/*! WAKEUP1 - Allows to identify Wake up I/O 1 as the wake-up source from Deep Power Down mode. + * 0b0..Last wake up from Deep Power down mode was NOT triggred by wake up I/O 1. + * 0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 1. + */ +#define PMC_WAKEIOCAUSE_WAKEUP1(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP1_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP1_MASK) +#define PMC_WAKEIOCAUSE_WAKEUP2_MASK (0x4U) +#define PMC_WAKEIOCAUSE_WAKEUP2_SHIFT (2U) +/*! WAKEUP2 - Allows to identify Wake up I/O 2 as the wake-up source from Deep Power Down mode. + * 0b0..Last wake up from Deep Power down mode was NOT triggred by wake up I/O 2. + * 0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 2. + */ +#define PMC_WAKEIOCAUSE_WAKEUP2(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP2_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP2_MASK) +#define PMC_WAKEIOCAUSE_WAKEUP3_MASK (0x8U) +#define PMC_WAKEIOCAUSE_WAKEUP3_SHIFT (3U) +/*! WAKEUP3 - Allows to identify Wake up I/O 3 as the wake-up source from Deep Power Down mode. + * 0b0..Last wake up from Deep Power down mode was NOT triggred by wake up I/O 3. + * 0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 3. + */ +#define PMC_WAKEIOCAUSE_WAKEUP3(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP3_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP3_MASK) +/*! @} */ + +/*! @name STATUSCLK - FRO and XTAL status register [Reset by: PoR, Brown Out Detectors Reset] */ +/*! @{ */ +#define PMC_STATUSCLK_XTAL32KOK_MASK (0x1U) +#define PMC_STATUSCLK_XTAL32KOK_SHIFT (0U) +#define PMC_STATUSCLK_XTAL32KOK(x) (((uint32_t)(((uint32_t)(x)) << PMC_STATUSCLK_XTAL32KOK_SHIFT)) & PMC_STATUSCLK_XTAL32KOK_MASK) +#define PMC_STATUSCLK_FRO1MCLKVALID_MASK (0x2U) +#define PMC_STATUSCLK_FRO1MCLKVALID_SHIFT (1U) +#define PMC_STATUSCLK_FRO1MCLKVALID(x) (((uint32_t)(((uint32_t)(x)) << PMC_STATUSCLK_FRO1MCLKVALID_SHIFT)) & PMC_STATUSCLK_FRO1MCLKVALID_MASK) +#define PMC_STATUSCLK_XTAL32KOSCFAILURE_MASK (0x4U) +#define PMC_STATUSCLK_XTAL32KOSCFAILURE_SHIFT (2U) +/*! XTAL32KOSCFAILURE - XTAL32 KHZ oscillator oscillation failure detection indicator. + * 0b0..No oscillation failure has been detetced since the last time this bit has been cleared.. + * 0b1..At least one oscillation failure has been detetced since the last time this bit has been cleared.. + */ +#define PMC_STATUSCLK_XTAL32KOSCFAILURE(x) (((uint32_t)(((uint32_t)(x)) << PMC_STATUSCLK_XTAL32KOSCFAILURE_SHIFT)) & PMC_STATUSCLK_XTAL32KOSCFAILURE_MASK) +/*! @} */ + +/*! @name AOREG1 - General purpose always on domain data storage [Reset by: PoR, Brown Out Detectors Reset] */ +/*! @{ */ +#define PMC_AOREG1_DATA31_0_MASK (0xFFFFFFFFU) +#define PMC_AOREG1_DATA31_0_SHIFT (0U) +#define PMC_AOREG1_DATA31_0(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_DATA31_0_SHIFT)) & PMC_AOREG1_DATA31_0_MASK) +/*! @} */ + +/*! @name RTCOSC32K - RTC 1 KHZ and 1 Hz clocks source control register [Reset by: PoR, Brown Out Detectors Reset] */ +/*! @{ */ +#define PMC_RTCOSC32K_SEL_MASK (0x1U) +#define PMC_RTCOSC32K_SEL_SHIFT (0U) +/*! SEL - Select the 32K oscillator to be used in Deep Power Down Mode for the RTC (either XTAL32KHz or FRO32KHz) . + * 0b0..FRO 32 KHz. + * 0b1..XTAL 32KHz. + */ +#define PMC_RTCOSC32K_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_SEL_SHIFT)) & PMC_RTCOSC32K_SEL_MASK) +#define PMC_RTCOSC32K_CLK1KHZDIV_MASK (0xEU) +#define PMC_RTCOSC32K_CLK1KHZDIV_SHIFT (1U) +#define PMC_RTCOSC32K_CLK1KHZDIV(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1KHZDIV_SHIFT)) & PMC_RTCOSC32K_CLK1KHZDIV_MASK) +#define PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ_MASK (0x8000U) +#define PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ_SHIFT (15U) +#define PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ_SHIFT)) & PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ_MASK) +#define PMC_RTCOSC32K_CLK1HZDIV_MASK (0x7FF0000U) +#define PMC_RTCOSC32K_CLK1HZDIV_SHIFT (16U) +#define PMC_RTCOSC32K_CLK1HZDIV(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1HZDIV_SHIFT)) & PMC_RTCOSC32K_CLK1HZDIV_MASK) +#define PMC_RTCOSC32K_CLK1HZDIVHALT_MASK (0x40000000U) +#define PMC_RTCOSC32K_CLK1HZDIVHALT_SHIFT (30U) +#define PMC_RTCOSC32K_CLK1HZDIVHALT(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1HZDIVHALT_SHIFT)) & PMC_RTCOSC32K_CLK1HZDIVHALT_MASK) +#define PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ_MASK (0x80000000U) +#define PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ_SHIFT (31U) +#define PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ_SHIFT)) & PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ_MASK) +/*! @} */ + +/*! @name OSTIMER - OS Timer control register [Reset by: PoR, Brown Out Detectors Reset] */ +/*! @{ */ +#define PMC_OSTIMER_SOFTRESET_MASK (0x1U) +#define PMC_OSTIMER_SOFTRESET_SHIFT (0U) +#define PMC_OSTIMER_SOFTRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_OSTIMER_SOFTRESET_SHIFT)) & PMC_OSTIMER_SOFTRESET_MASK) +#define PMC_OSTIMER_CLOCKENABLE_MASK (0x2U) +#define PMC_OSTIMER_CLOCKENABLE_SHIFT (1U) +#define PMC_OSTIMER_CLOCKENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_OSTIMER_CLOCKENABLE_SHIFT)) & PMC_OSTIMER_CLOCKENABLE_MASK) +#define PMC_OSTIMER_DPDWAKEUPENABLE_MASK (0x4U) +#define PMC_OSTIMER_DPDWAKEUPENABLE_SHIFT (2U) +#define PMC_OSTIMER_DPDWAKEUPENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_OSTIMER_DPDWAKEUPENABLE_SHIFT)) & PMC_OSTIMER_DPDWAKEUPENABLE_MASK) +#define PMC_OSTIMER_OSC32KPD_MASK (0x8U) +#define PMC_OSTIMER_OSC32KPD_SHIFT (3U) +#define PMC_OSTIMER_OSC32KPD(x) (((uint32_t)(((uint32_t)(x)) << PMC_OSTIMER_OSC32KPD_SHIFT)) & PMC_OSTIMER_OSC32KPD_MASK) +/*! @} */ + +/*! @name PDSLEEPCFG0 - Controls the power to various modules during Low Power modes - DEEP SLEEP, POWER DOWN and DEEP POWER DOWN [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Software Reset] */ +/*! @{ */ +#define PMC_PDSLEEPCFG0_PDEN_DCDC_MASK (0x1U) +#define PMC_PDSLEEPCFG0_PDEN_DCDC_SHIFT (0U) +/*! PDEN_DCDC - Controls DCDC power during DEEP SLEEP (DCDC is always shut down during POWER DOWN and DEEP POWER DOWN). + * 0b0..DCDC is powered on during low power mode.. + * 0b1..DCDC is powered off during low power mode.. + */ +#define PMC_PDSLEEPCFG0_PDEN_DCDC(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_DCDC_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_DCDC_MASK) +#define PMC_PDSLEEPCFG0_PDEN_BIAS_MASK (0x2U) +#define PMC_PDSLEEPCFG0_PDEN_BIAS_SHIFT (1U) +/*! PDEN_BIAS - Controls Analog Bias power during DEEP SLEEP and POWER DOWN (always shut down during DEEP POWER DOWN). + * 0b0..Analog Bias is powered on during low power mode.. + * 0b1..Analog Bias is powered off during low power mode.. + */ +#define PMC_PDSLEEPCFG0_PDEN_BIAS(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_BIAS_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_BIAS_MASK) +#define PMC_PDSLEEPCFG0_PDEN_BODCORE_MASK (0x4U) +#define PMC_PDSLEEPCFG0_PDEN_BODCORE_SHIFT (2U) +/*! PDEN_BODCORE - Controls Core Logic BoD power during DEEP SLEEP and POWER DOWN (always shut down during DEEP POWER DOWN). + * 0b0..BOD CORE is powered on during low power mode.. + * 0b1..BOD CORE is powered off during low power mode.. + */ +#define PMC_PDSLEEPCFG0_PDEN_BODCORE(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_BODCORE_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_BODCORE_MASK) +#define PMC_PDSLEEPCFG0_PDEN_BODVBAT_MASK (0x8U) +#define PMC_PDSLEEPCFG0_PDEN_BODVBAT_SHIFT (3U) +/*! PDEN_BODVBAT - Controls VBAT BoD power during DEEP SLEEP and POWER DOWN (always shut down during DEEP POWER DOWN). + * 0b0..BOD VBAT is powered on during low power mode.. + * 0b1..BOD VBAT is powered off during low power mode.. + */ +#define PMC_PDSLEEPCFG0_PDEN_BODVBAT(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_BODVBAT_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_BODVBAT_MASK) +#define PMC_PDSLEEPCFG0_PDEN_FRO1M_MASK (0x10U) +#define PMC_PDSLEEPCFG0_PDEN_FRO1M_SHIFT (4U) +/*! PDEN_FRO1M - Controls 1 MHz Free Running Oscillator power during DEEP SLEEP, POWER DOWN and DEEP POWER DOWN. + * 0b0..FRO 1MHz is powered on during low power mode.. + * 0b1..FRO 1MHz is powered off during low power mode.. + */ +#define PMC_PDSLEEPCFG0_PDEN_FRO1M(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_FRO1M_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_FRO1M_MASK) +#define PMC_PDSLEEPCFG0_PDEN_FRO192M_MASK (0x20U) +#define PMC_PDSLEEPCFG0_PDEN_FRO192M_SHIFT (5U) +/*! PDEN_FRO192M - Controls 192MHz Free Running Oscillator power during DEEP SLEEP (always shut down + * during POWER DOWN and DEEP POWER DOWN). + * 0b0..FRO 192 MHz is powered on during low power mode.. + * 0b1..FRO 192 MHz is powered off during low power mode.. + */ +#define PMC_PDSLEEPCFG0_PDEN_FRO192M(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_FRO192M_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_FRO192M_MASK) +#define PMC_PDSLEEPCFG0_PDEN_FRO32K_MASK (0x40U) +#define PMC_PDSLEEPCFG0_PDEN_FRO32K_SHIFT (6U) +/*! PDEN_FRO32K - Controls power during DEEP SLEEP, POWER DOWN and DEEP POWER DOWN. + * 0b0..FRO 32 KHz is powered on during low power mode.. + * 0b1..FRO 32 KHz is powered off during low power mode.. + */ +#define PMC_PDSLEEPCFG0_PDEN_FRO32K(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_FRO32K_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_FRO32K_MASK) +#define PMC_PDSLEEPCFG0_PDEN_XTAL32K_MASK (0x80U) +#define PMC_PDSLEEPCFG0_PDEN_XTAL32K_SHIFT (7U) +/*! PDEN_XTAL32K - Controls crystal 32 KHz power during DEEP SLEEP, POWER DOWN and DEEP POWER DOWN. + * 0b0..crystal 32 KHz is powered on during low power mode.. + * 0b1..crystal 32 KHz is powered off during low power mode.. + */ +#define PMC_PDSLEEPCFG0_PDEN_XTAL32K(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_XTAL32K_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_XTAL32K_MASK) +#define PMC_PDSLEEPCFG0_PDEN_XTAL32M_MASK (0x100U) +#define PMC_PDSLEEPCFG0_PDEN_XTAL32M_SHIFT (8U) +/*! PDEN_XTAL32M - Controls crystal 32 MHz power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). + * 0b0..crystal 32 MHz is powered on during low power mode.. + * 0b1..crystal 32 MHz is powered off during low power mode.. + */ +#define PMC_PDSLEEPCFG0_PDEN_XTAL32M(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_XTAL32M_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_XTAL32M_MASK) +#define PMC_PDSLEEPCFG0_PDEN_PLL0_MASK (0x200U) +#define PMC_PDSLEEPCFG0_PDEN_PLL0_SHIFT (9U) +/*! PDEN_PLL0 - Controls System PLL (also refered as PLL0) power during DEEP SLEEP (always shut down + * during POWER DOWN and DEEP POWER DOWN). + * 0b0..System PLL (also refered as PLL0) is powered on during low power mode.. + * 0b1..System PLL (also refered as PLL0) is powered off during low power mode.. + */ +#define PMC_PDSLEEPCFG0_PDEN_PLL0(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_PLL0_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_PLL0_MASK) +#define PMC_PDSLEEPCFG0_PDEN_PLL1_MASK (0x400U) +#define PMC_PDSLEEPCFG0_PDEN_PLL1_SHIFT (10U) +/*! PDEN_PLL1 - Controls USB PLL (also refered as PLL1) power during DEEP SLEEP (always shut down + * during POWER DOWN and DEEP POWER DOWN). + * 0b0..USB PLL (also refered as PLL1) is powered on during low power mode.. + * 0b1..USB PLL (also refered as PLL1) is powered off during low power mode.. + */ +#define PMC_PDSLEEPCFG0_PDEN_PLL1(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_PLL1_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_PLL1_MASK) +#define PMC_PDSLEEPCFG0_PDEN_USBFSPHY_MASK (0x800U) +#define PMC_PDSLEEPCFG0_PDEN_USBFSPHY_SHIFT (11U) +/*! PDEN_USBFSPHY - Controls USB Full Speed phy power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). + * 0b0..USB Full Speed phy is powered on during low power mode.. + * 0b1..USB Full Speed phy is powered off during low power mode.. + */ +#define PMC_PDSLEEPCFG0_PDEN_USBFSPHY(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_USBFSPHY_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_USBFSPHY_MASK) +#define PMC_PDSLEEPCFG0_PDEN_USBHSPHY_MASK (0x1000U) +#define PMC_PDSLEEPCFG0_PDEN_USBHSPHY_SHIFT (12U) +/*! PDEN_USBHSPHY - Controls USB High Speed Phy power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). + * 0b0..USB High Speed Phy is powered on during low power mode.. + * 0b1..USB High Speed Phy is powered off during low power mode.. + */ +#define PMC_PDSLEEPCFG0_PDEN_USBHSPHY(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_USBHSPHY_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_USBHSPHY_MASK) +#define PMC_PDSLEEPCFG0_PDEN_COMP_MASK (0x2000U) +#define PMC_PDSLEEPCFG0_PDEN_COMP_SHIFT (13U) +/*! PDEN_COMP - Controls Analog Comparator power during DEEP SLEEP and POWER DOWN (always shut down during DEEP POWER DOWN). + * 0b0..Analog Comparator is powered on during low power mode.. + * 0b1..Analog Comparator is powered off during low power mode.. + */ +#define PMC_PDSLEEPCFG0_PDEN_COMP(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_COMP_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_COMP_MASK) +#define PMC_PDSLEEPCFG0_PDEN_TEMPSENS_MASK (0x4000U) +#define PMC_PDSLEEPCFG0_PDEN_TEMPSENS_SHIFT (14U) +/*! PDEN_TEMPSENS - Controls Temperature Sensor power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). + * 0b0..Temperature Sensor is powered on during low power mode.. + * 0b1..Temperature Sensor is powered off during low power mode.. + */ +#define PMC_PDSLEEPCFG0_PDEN_TEMPSENS(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_TEMPSENS_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_TEMPSENS_MASK) +#define PMC_PDSLEEPCFG0_PDEN_GPADC_MASK (0x8000U) +#define PMC_PDSLEEPCFG0_PDEN_GPADC_SHIFT (15U) +/*! PDEN_GPADC - Controls General Purpose ADC (GPADC) power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). + * 0b0..General Purpose ADC (GPADC) is powered on during low power mode.. + * 0b1..General Purpose ADC (GPADC) is powered off during low power mode.. + */ +#define PMC_PDSLEEPCFG0_PDEN_GPADC(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_GPADC_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_GPADC_MASK) +#define PMC_PDSLEEPCFG0_PDEN_LDOMEM_MASK (0x10000U) +#define PMC_PDSLEEPCFG0_PDEN_LDOMEM_SHIFT (16U) +/*! PDEN_LDOMEM - Controls Memories LDO power during DEEP SLEEP, POWER DOWN and DEEP POWER DOWN. + * 0b0..Memories LDO is powered on during low power mode.. + * 0b1..Memories LDO is powered off during low power mode.. + */ +#define PMC_PDSLEEPCFG0_PDEN_LDOMEM(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_LDOMEM_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_LDOMEM_MASK) +#define PMC_PDSLEEPCFG0_PDEN_LDODEEPSLEEP_MASK (0x20000U) +#define PMC_PDSLEEPCFG0_PDEN_LDODEEPSLEEP_SHIFT (17U) +/*! PDEN_LDODEEPSLEEP - Controls Deep Sleep LDO power during DEEP SLEEP and POWER DOWN (always shut down during DEEP POWER DOWN). + * 0b0..Deep Sleep LDO is powered on during low power mode.. + * 0b1..Deep Sleep LDO is powered off during low power mode.. + */ +#define PMC_PDSLEEPCFG0_PDEN_LDODEEPSLEEP(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_LDODEEPSLEEP_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_LDODEEPSLEEP_MASK) +#define PMC_PDSLEEPCFG0_PDEN_LDOUSBHS_MASK (0x40000U) +#define PMC_PDSLEEPCFG0_PDEN_LDOUSBHS_SHIFT (18U) +/*! PDEN_LDOUSBHS - Controls USB high speed LDO power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). + * 0b0..USB high speed LDO is powered on during low power mode.. + * 0b1..USB high speed LDO is powered off during low power mode.. + */ +#define PMC_PDSLEEPCFG0_PDEN_LDOUSBHS(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_LDOUSBHS_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_LDOUSBHS_MASK) +#define PMC_PDSLEEPCFG0_PDEN_AUXBIAS_MASK (0x80000U) +#define PMC_PDSLEEPCFG0_PDEN_AUXBIAS_SHIFT (19U) +/*! PDEN_AUXBIAS - during DEEP SLEEP and POWER DOWN (always shut down during DEEP POWER DOWN). + * 0b0..is powered on during low power mode.. + * 0b1..is powered off during low power mode.. + */ +#define PMC_PDSLEEPCFG0_PDEN_AUXBIAS(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_AUXBIAS_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_AUXBIAS_MASK) +#define PMC_PDSLEEPCFG0_PDEN_LDOXO32M_MASK (0x100000U) +#define PMC_PDSLEEPCFG0_PDEN_LDOXO32M_SHIFT (20U) +/*! PDEN_LDOXO32M - Controls crystal 32 MHz LDO power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). + * 0b0..crystal 32 MHz LDO is powered on during low power mode.. + * 0b1..crystal 32 MHz LDO is powered off during low power mode.. + */ +#define PMC_PDSLEEPCFG0_PDEN_LDOXO32M(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_LDOXO32M_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_LDOXO32M_MASK) +#define PMC_PDSLEEPCFG0_PDEN_LDOFLASHNV_MASK (0x200000U) +#define PMC_PDSLEEPCFG0_PDEN_LDOFLASHNV_SHIFT (21U) +/*! PDEN_LDOFLASHNV - Controls Flash NV (high voltage) LDO power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). + * 0b0..Flash NV (high voltage) is powered on during low power mode.. + * 0b1..Flash NV (high voltage) is powered off during low power mode.. + */ +#define PMC_PDSLEEPCFG0_PDEN_LDOFLASHNV(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_LDOFLASHNV_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_LDOFLASHNV_MASK) +#define PMC_PDSLEEPCFG0_PDEN_RNG_MASK (0x400000U) +#define PMC_PDSLEEPCFG0_PDEN_RNG_SHIFT (22U) +/*! PDEN_RNG - Controls True Random Number Genetaor (TRNG) clock sources power during DEEP SLEEP + * (always shut down during POWER DOWN and DEEP POWER DOWN). + * 0b0..True Random Number Genetaor (TRNG) clock sources are powered on during low power mode.. + * 0b1..True Random Number Genetaor (TRNG) clock sources are powered off during low power mode.. + */ +#define PMC_PDSLEEPCFG0_PDEN_RNG(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_RNG_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_RNG_MASK) +#define PMC_PDSLEEPCFG0_PDEN_PLL0_SSCG_MASK (0x800000U) +#define PMC_PDSLEEPCFG0_PDEN_PLL0_SSCG_SHIFT (23U) +/*! PDEN_PLL0_SSCG - Controls PLL0 Spread Sprectrum module power during DEEP SLEEP (PLL0 Spread + * Spectrum is always shut down during POWER DOWN and DEEP POWER DOWN). + * 0b0..PLL0 Spread Sprectrum module is powered on during low power mode.. + * 0b1..PLL0 Spread Sprectrum module is powered off during low power mode.. + */ +#define PMC_PDSLEEPCFG0_PDEN_PLL0_SSCG(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_PLL0_SSCG_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_PLL0_SSCG_MASK) +#define PMC_PDSLEEPCFG0_PDEN_ROM_MASK (0x1000000U) +#define PMC_PDSLEEPCFG0_PDEN_ROM_SHIFT (24U) +/*! PDEN_ROM - Controls ROM power during DEEP SLEEP (ROM is always shut down during POWER DOWN and DEEP POWER DOWN). + * 0b0..ROM is powered on during low power mode.. + * 0b1..ROM is powered off during low power mode.. + */ +#define PMC_PDSLEEPCFG0_PDEN_ROM(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_ROM_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_ROM_MASK) +/*! @} */ + +/*! @name PDRUNCFG0 - Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ +/*! @{ */ +#define PMC_PDRUNCFG0_PDEN_DCDC_MASK (0x1U) +#define PMC_PDRUNCFG0_PDEN_DCDC_SHIFT (0U) +/*! PDEN_DCDC - Controls power to Bulk DCDC Converter. + * 0b0..DCDC is powered. + * 0b1..DCDC is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_DCDC(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_DCDC_SHIFT)) & PMC_PDRUNCFG0_PDEN_DCDC_MASK) +#define PMC_PDRUNCFG0_PDEN_BIAS_MASK (0x2U) +#define PMC_PDRUNCFG0_PDEN_BIAS_SHIFT (1U) +/*! PDEN_BIAS - Controls power to . + * 0b0..Analog Bias is powered. + * 0b1..Analog Bias is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_BIAS(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_BIAS_SHIFT)) & PMC_PDRUNCFG0_PDEN_BIAS_MASK) +#define PMC_PDRUNCFG0_PDEN_BODCORE_MASK (0x4U) +#define PMC_PDRUNCFG0_PDEN_BODCORE_SHIFT (2U) +/*! PDEN_BODCORE - Controls power to Core Brown Out Detector (BOD). + * 0b0..BOD CORE is powered. + * 0b1..BOD CORE is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_BODCORE(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_BODCORE_SHIFT)) & PMC_PDRUNCFG0_PDEN_BODCORE_MASK) +#define PMC_PDRUNCFG0_PDEN_BODVBAT_MASK (0x8U) +#define PMC_PDRUNCFG0_PDEN_BODVBAT_SHIFT (3U) +/*! PDEN_BODVBAT - Controls power to VBAT Brown Out Detector (BOD). + * 0b0..BOD VBAT is powered. + * 0b1..BOD VBAT is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_BODVBAT(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_BODVBAT_SHIFT)) & PMC_PDRUNCFG0_PDEN_BODVBAT_MASK) +#define PMC_PDRUNCFG0_PDEN_FRO192M_MASK (0x20U) +#define PMC_PDRUNCFG0_PDEN_FRO192M_SHIFT (5U) +/*! PDEN_FRO192M - Controls power to the Free Running Oscillator (FRO) 192 MHz; The 12MHz, 48 MHz + * and 96 MHz clocks are derived from this FRO. + * 0b0..FRO 192MHz is powered. + * 0b1..FRO 192MHz is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_FRO192M(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_FRO192M_SHIFT)) & PMC_PDRUNCFG0_PDEN_FRO192M_MASK) +#define PMC_PDRUNCFG0_PDEN_FRO32K_MASK (0x40U) +#define PMC_PDRUNCFG0_PDEN_FRO32K_SHIFT (6U) +/*! PDEN_FRO32K - Controls power to the Free Running Oscillator (FRO) 32 KHz. + * 0b0..FRO32KHz is powered. + * 0b1..FRO32KHz is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_FRO32K(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_FRO32K_SHIFT)) & PMC_PDRUNCFG0_PDEN_FRO32K_MASK) +#define PMC_PDRUNCFG0_PDEN_XTAL32K_MASK (0x80U) +#define PMC_PDRUNCFG0_PDEN_XTAL32K_SHIFT (7U) +/*! PDEN_XTAL32K - Controls power to crystal 32 KHz. + * 0b0..Crystal 32KHz is powered. + * 0b1..Crystal 32KHz is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_XTAL32K(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_XTAL32K_SHIFT)) & PMC_PDRUNCFG0_PDEN_XTAL32K_MASK) +#define PMC_PDRUNCFG0_PDEN_XTAL32M_MASK (0x100U) +#define PMC_PDRUNCFG0_PDEN_XTAL32M_SHIFT (8U) +/*! PDEN_XTAL32M - Controls power to crystal 32 MHz. + * 0b0..Crystal 32MHz is powered. + * 0b1..Crystal 32MHz is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_XTAL32M(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_XTAL32M_SHIFT)) & PMC_PDRUNCFG0_PDEN_XTAL32M_MASK) +#define PMC_PDRUNCFG0_PDEN_PLL0_MASK (0x200U) +#define PMC_PDRUNCFG0_PDEN_PLL0_SHIFT (9U) +/*! PDEN_PLL0 - Controls power to System PLL (also refered as PLL0). + * 0b0..PLL0 is powered. + * 0b1..PLL0 is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_PLL0(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_PLL0_SHIFT)) & PMC_PDRUNCFG0_PDEN_PLL0_MASK) +#define PMC_PDRUNCFG0_PDEN_PLL1_MASK (0x400U) +#define PMC_PDRUNCFG0_PDEN_PLL1_SHIFT (10U) +/*! PDEN_PLL1 - Controls power to USB PLL (also refered as PLL1). + * 0b0..PLL1 is powered. + * 0b1..PLL1 is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_PLL1(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_PLL1_SHIFT)) & PMC_PDRUNCFG0_PDEN_PLL1_MASK) +#define PMC_PDRUNCFG0_PDEN_USBFSPHY_MASK (0x800U) +#define PMC_PDRUNCFG0_PDEN_USBFSPHY_SHIFT (11U) +/*! PDEN_USBFSPHY - Controls power to USB Full Speed phy. + * 0b0..USB Full Speed phy is powered. + * 0b1..USB Full Speed phy is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_USBFSPHY(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_USBFSPHY_SHIFT)) & PMC_PDRUNCFG0_PDEN_USBFSPHY_MASK) +#define PMC_PDRUNCFG0_PDEN_USBHSPHY_MASK (0x1000U) +#define PMC_PDRUNCFG0_PDEN_USBHSPHY_SHIFT (12U) +/*! PDEN_USBHSPHY - Controls power to USB High Speed Phy. + * 0b0..USB HS phy is powered. + * 0b1..USB HS phy is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_USBHSPHY(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_USBHSPHY_SHIFT)) & PMC_PDRUNCFG0_PDEN_USBHSPHY_MASK) +#define PMC_PDRUNCFG0_PDEN_COMP_MASK (0x2000U) +#define PMC_PDRUNCFG0_PDEN_COMP_SHIFT (13U) +/*! PDEN_COMP - Controls power to Analog Comparator. + * 0b0..Analog Comparator is powered. + * 0b1..Analog Comparator is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_COMP(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_COMP_SHIFT)) & PMC_PDRUNCFG0_PDEN_COMP_MASK) +#define PMC_PDRUNCFG0_PDEN_TEMPSENS_MASK (0x4000U) +#define PMC_PDRUNCFG0_PDEN_TEMPSENS_SHIFT (14U) +/*! PDEN_TEMPSENS - Controls power to Temperature Sensor. + * 0b0..Temperature Sensor is powered. + * 0b1..Temperature Sensor is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_TEMPSENS(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_TEMPSENS_SHIFT)) & PMC_PDRUNCFG0_PDEN_TEMPSENS_MASK) +#define PMC_PDRUNCFG0_PDEN_GPADC_MASK (0x8000U) +#define PMC_PDRUNCFG0_PDEN_GPADC_SHIFT (15U) +/*! PDEN_GPADC - Controls power to General Purpose ADC (GPADC). + * 0b0..GPADC is powered. + * 0b1..GPADC is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_GPADC(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_GPADC_SHIFT)) & PMC_PDRUNCFG0_PDEN_GPADC_MASK) +#define PMC_PDRUNCFG0_PDEN_LDOMEM_MASK (0x10000U) +#define PMC_PDRUNCFG0_PDEN_LDOMEM_SHIFT (16U) +/*! PDEN_LDOMEM - Controls power to Memories LDO. + * 0b0..Memories LDO is powered. + * 0b1..Memories LDO is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_LDOMEM(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_LDOMEM_SHIFT)) & PMC_PDRUNCFG0_PDEN_LDOMEM_MASK) +#define PMC_PDRUNCFG0_PDEN_LDODEEPSLEEP_MASK (0x20000U) +#define PMC_PDRUNCFG0_PDEN_LDODEEPSLEEP_SHIFT (17U) +/*! PDEN_LDODEEPSLEEP - Controls power to Deep Sleep LDO. + * 0b0..Deep Sleep LDO is powered. + * 0b1..Deep Sleep LDO is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_LDODEEPSLEEP(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_LDODEEPSLEEP_SHIFT)) & PMC_PDRUNCFG0_PDEN_LDODEEPSLEEP_MASK) +#define PMC_PDRUNCFG0_PDEN_LDOUSBHS_MASK (0x40000U) +#define PMC_PDRUNCFG0_PDEN_LDOUSBHS_SHIFT (18U) +/*! PDEN_LDOUSBHS - Controls power to USB high speed LDO. + * 0b0..USB high speed LDO is powered. + * 0b1..USB high speed LDO is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_LDOUSBHS(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_LDOUSBHS_SHIFT)) & PMC_PDRUNCFG0_PDEN_LDOUSBHS_MASK) +#define PMC_PDRUNCFG0_PDEN_AUXBIAS_MASK (0x80000U) +#define PMC_PDRUNCFG0_PDEN_AUXBIAS_SHIFT (19U) +/*! PDEN_AUXBIAS - Controls power to auxiliary biasing (AUXBIAS) + * 0b0..auxiliary biasing is powered. + * 0b1..auxiliary biasing is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_AUXBIAS(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_AUXBIAS_SHIFT)) & PMC_PDRUNCFG0_PDEN_AUXBIAS_MASK) +#define PMC_PDRUNCFG0_PDEN_LDOXO32M_MASK (0x100000U) +#define PMC_PDRUNCFG0_PDEN_LDOXO32M_SHIFT (20U) +/*! PDEN_LDOXO32M - Controls power to crystal 32 MHz LDO. + * 0b0..crystal 32 MHz LDO is powered. + * 0b1..crystal 32 MHz LDO is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_LDOXO32M(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_LDOXO32M_SHIFT)) & PMC_PDRUNCFG0_PDEN_LDOXO32M_MASK) +#define PMC_PDRUNCFG0_PDEN_LDOFLASHNV_MASK (0x200000U) +#define PMC_PDRUNCFG0_PDEN_LDOFLASHNV_SHIFT (21U) +/*! PDEN_LDOFLASHNV - Controls power to Flasn NV (high voltage) LDO. + * 0b0..Flash NV LDO is powered. + * 0b1..Flash NV LDO is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_LDOFLASHNV(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_LDOFLASHNV_SHIFT)) & PMC_PDRUNCFG0_PDEN_LDOFLASHNV_MASK) +#define PMC_PDRUNCFG0_PDEN_RNG_MASK (0x400000U) +#define PMC_PDRUNCFG0_PDEN_RNG_SHIFT (22U) +/*! PDEN_RNG - Controls power to all True Random Number Genetaor (TRNG) clock sources. + * 0b0..TRNG clocks are powered. + * 0b1..TRNG clocks are powered down. + */ +#define PMC_PDRUNCFG0_PDEN_RNG(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_RNG_SHIFT)) & PMC_PDRUNCFG0_PDEN_RNG_MASK) +#define PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK (0x800000U) +#define PMC_PDRUNCFG0_PDEN_PLL0_SSCG_SHIFT (23U) +/*! PDEN_PLL0_SSCG - Controls power to System PLL (PLL0) Spread Spectrum module. + * 0b0..PLL0 Sread spectrum module is powered. + * 0b1..PLL0 Sread spectrum module is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_PLL0_SSCG(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_PLL0_SSCG_SHIFT)) & PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK) +/*! @} */ + +/*! @name PDRUNCFGSET0 - Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ +/*! @{ */ +#define PMC_PDRUNCFGSET0_PDRUNCFGSET0_MASK (0xFFFFFFFFU) +#define PMC_PDRUNCFGSET0_PDRUNCFGSET0_SHIFT (0U) +#define PMC_PDRUNCFGSET0_PDRUNCFGSET0(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFGSET0_PDRUNCFGSET0_SHIFT)) & PMC_PDRUNCFGSET0_PDRUNCFGSET0_MASK) +/*! @} */ + +/*! @name PDRUNCFGCLR0 - Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ +/*! @{ */ +#define PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_MASK (0xFFFFFFFFU) +#define PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_SHIFT (0U) +#define PMC_PDRUNCFGCLR0_PDRUNCFGCLR0(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_SHIFT)) & PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group PMC_Register_Masks */ + + +/* PMC - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral PMC base address */ + #define PMC_BASE (0x50020000u) + /** Peripheral PMC base address */ + #define PMC_BASE_NS (0x40020000u) + /** Peripheral PMC base pointer */ + #define PMC ((PMC_Type *)PMC_BASE) + /** Peripheral PMC base pointer */ + #define PMC_NS ((PMC_Type *)PMC_BASE_NS) + /** Array initializer of PMC peripheral base addresses */ + #define PMC_BASE_ADDRS { PMC_BASE } + /** Array initializer of PMC peripheral base pointers */ + #define PMC_BASE_PTRS { PMC } + /** Array initializer of PMC peripheral base addresses */ + #define PMC_BASE_ADDRS_NS { PMC_BASE_NS } + /** Array initializer of PMC peripheral base pointers */ + #define PMC_BASE_PTRS_NS { PMC_NS } +#else + /** Peripheral PMC base address */ + #define PMC_BASE (0x40020000u) + /** Peripheral PMC base pointer */ + #define PMC ((PMC_Type *)PMC_BASE) + /** Array initializer of PMC peripheral base addresses */ + #define PMC_BASE_ADDRS { PMC_BASE } + /** Array initializer of PMC peripheral base pointers */ + #define PMC_BASE_PTRS { PMC } +#endif + +/*! + * @} + */ /* end of group PMC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- POWERQUAD Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup POWERQUAD_Peripheral_Access_Layer POWERQUAD Peripheral Access Layer + * @{ + */ + +/** POWERQUAD - Register Layout Typedef */ +typedef struct { + __IO uint32_t OUTBASE; /**< Base address register for output region, offset: 0x0 */ + __IO uint32_t OUTFORMAT; /**< Output format, offset: 0x4 */ + __IO uint32_t TMPBASE; /**< Base address register for temp region, offset: 0x8 */ + __IO uint32_t TMPFORMAT; /**< Temp format, offset: 0xC */ + __IO uint32_t INABASE; /**< Base address register for input A region, offset: 0x10 */ + __IO uint32_t INAFORMAT; /**< Input A format, offset: 0x14 */ + __IO uint32_t INBBASE; /**< Base address register for input B region, offset: 0x18 */ + __IO uint32_t INBFORMAT; /**< Input B format, offset: 0x1C */ + uint8_t RESERVED_0[224]; + __IO uint32_t CONTROL; /**< PowerQuad Control register, offset: 0x100 */ + __IO uint32_t LENGTH; /**< Length register, offset: 0x104 */ + __IO uint32_t CPPRE; /**< Pre-scale register, offset: 0x108 */ + __IO uint32_t MISC; /**< Misc register, offset: 0x10C */ + __IO uint32_t CURSORY; /**< Cursory register, offset: 0x110 */ + uint8_t RESERVED_1[108]; + __IO uint32_t CORDIC_X; /**< Cordic input X register, offset: 0x180 */ + __IO uint32_t CORDIC_Y; /**< Cordic input Y register, offset: 0x184 */ + __IO uint32_t CORDIC_Z; /**< Cordic input Z register, offset: 0x188 */ + __IO uint32_t ERRSTAT; /**< Read/Write register where error statuses are captured (sticky), offset: 0x18C */ + __IO uint32_t INTREN; /**< INTERRUPT enable register, offset: 0x190 */ + __IO uint32_t EVENTEN; /**< Event Enable register, offset: 0x194 */ + __IO uint32_t INTRSTAT; /**< INTERRUPT STATUS register, offset: 0x198 */ + uint8_t RESERVED_2[100]; + __IO uint32_t GPREG[16]; /**< General purpose register bank N., array offset: 0x200, array step: 0x4 */ + __IO uint32_t COMPREG[8]; /**< Compute register bank, array offset: 0x240, array step: 0x4 */ +} POWERQUAD_Type; + +/* ---------------------------------------------------------------------------- + -- POWERQUAD Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup POWERQUAD_Register_Masks POWERQUAD Register Masks + * @{ + */ + +/*! @name OUTBASE - Base address register for output region */ +/*! @{ */ +#define POWERQUAD_OUTBASE_OUTBASE_MASK (0xFFFFFFFFU) +#define POWERQUAD_OUTBASE_OUTBASE_SHIFT (0U) +#define POWERQUAD_OUTBASE_OUTBASE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTBASE_OUTBASE_SHIFT)) & POWERQUAD_OUTBASE_OUTBASE_MASK) +/*! @} */ + +/*! @name OUTFORMAT - Output format */ +/*! @{ */ +#define POWERQUAD_OUTFORMAT_OUT_FORMATINT_MASK (0x3U) +#define POWERQUAD_OUTFORMAT_OUT_FORMATINT_SHIFT (0U) +#define POWERQUAD_OUTFORMAT_OUT_FORMATINT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTFORMAT_OUT_FORMATINT_SHIFT)) & POWERQUAD_OUTFORMAT_OUT_FORMATINT_MASK) +#define POWERQUAD_OUTFORMAT_OUT_FORMATEXT_MASK (0x30U) +#define POWERQUAD_OUTFORMAT_OUT_FORMATEXT_SHIFT (4U) +#define POWERQUAD_OUTFORMAT_OUT_FORMATEXT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTFORMAT_OUT_FORMATEXT_SHIFT)) & POWERQUAD_OUTFORMAT_OUT_FORMATEXT_MASK) +#define POWERQUAD_OUTFORMAT_OUT_SCALER_MASK (0xFF00U) +#define POWERQUAD_OUTFORMAT_OUT_SCALER_SHIFT (8U) +#define POWERQUAD_OUTFORMAT_OUT_SCALER(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTFORMAT_OUT_SCALER_SHIFT)) & POWERQUAD_OUTFORMAT_OUT_SCALER_MASK) +/*! @} */ + +/*! @name TMPBASE - Base address register for temp region */ +/*! @{ */ +#define POWERQUAD_TMPBASE_TMPBASE_MASK (0xFFFFFFFFU) +#define POWERQUAD_TMPBASE_TMPBASE_SHIFT (0U) +#define POWERQUAD_TMPBASE_TMPBASE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPBASE_TMPBASE_SHIFT)) & POWERQUAD_TMPBASE_TMPBASE_MASK) +/*! @} */ + +/*! @name TMPFORMAT - Temp format */ +/*! @{ */ +#define POWERQUAD_TMPFORMAT_TMP_FORMATINT_MASK (0x3U) +#define POWERQUAD_TMPFORMAT_TMP_FORMATINT_SHIFT (0U) +#define POWERQUAD_TMPFORMAT_TMP_FORMATINT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPFORMAT_TMP_FORMATINT_SHIFT)) & POWERQUAD_TMPFORMAT_TMP_FORMATINT_MASK) +#define POWERQUAD_TMPFORMAT_TMP_FORMATEXT_MASK (0x30U) +#define POWERQUAD_TMPFORMAT_TMP_FORMATEXT_SHIFT (4U) +#define POWERQUAD_TMPFORMAT_TMP_FORMATEXT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPFORMAT_TMP_FORMATEXT_SHIFT)) & POWERQUAD_TMPFORMAT_TMP_FORMATEXT_MASK) +#define POWERQUAD_TMPFORMAT_TMP_SCALER_MASK (0xFF00U) +#define POWERQUAD_TMPFORMAT_TMP_SCALER_SHIFT (8U) +#define POWERQUAD_TMPFORMAT_TMP_SCALER(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPFORMAT_TMP_SCALER_SHIFT)) & POWERQUAD_TMPFORMAT_TMP_SCALER_MASK) +/*! @} */ + +/*! @name INABASE - Base address register for input A region */ +/*! @{ */ +#define POWERQUAD_INABASE_INABASE_MASK (0xFFFFFFFFU) +#define POWERQUAD_INABASE_INABASE_SHIFT (0U) +#define POWERQUAD_INABASE_INABASE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INABASE_INABASE_SHIFT)) & POWERQUAD_INABASE_INABASE_MASK) +/*! @} */ + +/*! @name INAFORMAT - Input A format */ +/*! @{ */ +#define POWERQUAD_INAFORMAT_INA_FORMATINT_MASK (0x3U) +#define POWERQUAD_INAFORMAT_INA_FORMATINT_SHIFT (0U) +#define POWERQUAD_INAFORMAT_INA_FORMATINT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INAFORMAT_INA_FORMATINT_SHIFT)) & POWERQUAD_INAFORMAT_INA_FORMATINT_MASK) +#define POWERQUAD_INAFORMAT_INA_FORMATEXT_MASK (0x30U) +#define POWERQUAD_INAFORMAT_INA_FORMATEXT_SHIFT (4U) +#define POWERQUAD_INAFORMAT_INA_FORMATEXT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INAFORMAT_INA_FORMATEXT_SHIFT)) & POWERQUAD_INAFORMAT_INA_FORMATEXT_MASK) +#define POWERQUAD_INAFORMAT_INA_SCALER_MASK (0xFF00U) +#define POWERQUAD_INAFORMAT_INA_SCALER_SHIFT (8U) +#define POWERQUAD_INAFORMAT_INA_SCALER(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INAFORMAT_INA_SCALER_SHIFT)) & POWERQUAD_INAFORMAT_INA_SCALER_MASK) +/*! @} */ + +/*! @name INBBASE - Base address register for input B region */ +/*! @{ */ +#define POWERQUAD_INBBASE_INBBASE_MASK (0xFFFFFFFFU) +#define POWERQUAD_INBBASE_INBBASE_SHIFT (0U) +#define POWERQUAD_INBBASE_INBBASE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBBASE_INBBASE_SHIFT)) & POWERQUAD_INBBASE_INBBASE_MASK) +/*! @} */ + +/*! @name INBFORMAT - Input B format */ +/*! @{ */ +#define POWERQUAD_INBFORMAT_INB_FORMATINT_MASK (0x3U) +#define POWERQUAD_INBFORMAT_INB_FORMATINT_SHIFT (0U) +#define POWERQUAD_INBFORMAT_INB_FORMATINT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBFORMAT_INB_FORMATINT_SHIFT)) & POWERQUAD_INBFORMAT_INB_FORMATINT_MASK) +#define POWERQUAD_INBFORMAT_INB_FORMATEXT_MASK (0x30U) +#define POWERQUAD_INBFORMAT_INB_FORMATEXT_SHIFT (4U) +#define POWERQUAD_INBFORMAT_INB_FORMATEXT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBFORMAT_INB_FORMATEXT_SHIFT)) & POWERQUAD_INBFORMAT_INB_FORMATEXT_MASK) +#define POWERQUAD_INBFORMAT_INB_SCALER_MASK (0xFF00U) +#define POWERQUAD_INBFORMAT_INB_SCALER_SHIFT (8U) +#define POWERQUAD_INBFORMAT_INB_SCALER(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBFORMAT_INB_SCALER_SHIFT)) & POWERQUAD_INBFORMAT_INB_SCALER_MASK) +/*! @} */ + +/*! @name CONTROL - PowerQuad Control register */ +/*! @{ */ +#define POWERQUAD_CONTROL_DECODE_OPCODE_MASK (0xFU) +#define POWERQUAD_CONTROL_DECODE_OPCODE_SHIFT (0U) +#define POWERQUAD_CONTROL_DECODE_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CONTROL_DECODE_OPCODE_SHIFT)) & POWERQUAD_CONTROL_DECODE_OPCODE_MASK) +#define POWERQUAD_CONTROL_DECODE_MACHINE_MASK (0xF0U) +#define POWERQUAD_CONTROL_DECODE_MACHINE_SHIFT (4U) +#define POWERQUAD_CONTROL_DECODE_MACHINE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CONTROL_DECODE_MACHINE_SHIFT)) & POWERQUAD_CONTROL_DECODE_MACHINE_MASK) +#define POWERQUAD_CONTROL_INST_BUSY_MASK (0x80000000U) +#define POWERQUAD_CONTROL_INST_BUSY_SHIFT (31U) +#define POWERQUAD_CONTROL_INST_BUSY(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CONTROL_INST_BUSY_SHIFT)) & POWERQUAD_CONTROL_INST_BUSY_MASK) +/*! @} */ + +/*! @name LENGTH - Length register */ +/*! @{ */ +#define POWERQUAD_LENGTH_INST_LENGTH_MASK (0xFFFFFFFFU) +#define POWERQUAD_LENGTH_INST_LENGTH_SHIFT (0U) +#define POWERQUAD_LENGTH_INST_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_LENGTH_INST_LENGTH_SHIFT)) & POWERQUAD_LENGTH_INST_LENGTH_MASK) +/*! @} */ + +/*! @name CPPRE - Pre-scale register */ +/*! @{ */ +#define POWERQUAD_CPPRE_CPPRE_IN_MASK (0xFFU) +#define POWERQUAD_CPPRE_CPPRE_IN_SHIFT (0U) +#define POWERQUAD_CPPRE_CPPRE_IN(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_IN_SHIFT)) & POWERQUAD_CPPRE_CPPRE_IN_MASK) +#define POWERQUAD_CPPRE_CPPRE_OUT_MASK (0xFF00U) +#define POWERQUAD_CPPRE_CPPRE_OUT_SHIFT (8U) +#define POWERQUAD_CPPRE_CPPRE_OUT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_OUT_SHIFT)) & POWERQUAD_CPPRE_CPPRE_OUT_MASK) +#define POWERQUAD_CPPRE_CPPRE_SAT_MASK (0x10000U) +#define POWERQUAD_CPPRE_CPPRE_SAT_SHIFT (16U) +#define POWERQUAD_CPPRE_CPPRE_SAT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_SAT_SHIFT)) & POWERQUAD_CPPRE_CPPRE_SAT_MASK) +#define POWERQUAD_CPPRE_CPPRE_SAT8_MASK (0x20000U) +#define POWERQUAD_CPPRE_CPPRE_SAT8_SHIFT (17U) +#define POWERQUAD_CPPRE_CPPRE_SAT8(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_SAT8_SHIFT)) & POWERQUAD_CPPRE_CPPRE_SAT8_MASK) +/*! @} */ + +/*! @name MISC - Misc register */ +/*! @{ */ +#define POWERQUAD_MISC_INST_MISC_MASK (0xFFFFFFFFU) +#define POWERQUAD_MISC_INST_MISC_SHIFT (0U) +#define POWERQUAD_MISC_INST_MISC(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_MISC_INST_MISC_SHIFT)) & POWERQUAD_MISC_INST_MISC_MASK) +/*! @} */ + +/*! @name CURSORY - Cursory register */ +/*! @{ */ +#define POWERQUAD_CURSORY_CURSORY_MASK (0x1U) +#define POWERQUAD_CURSORY_CURSORY_SHIFT (0U) +#define POWERQUAD_CURSORY_CURSORY(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CURSORY_CURSORY_SHIFT)) & POWERQUAD_CURSORY_CURSORY_MASK) +/*! @} */ + +/*! @name CORDIC_X - Cordic input X register */ +/*! @{ */ +#define POWERQUAD_CORDIC_X_CORDIC_X_MASK (0xFFFFFFFFU) +#define POWERQUAD_CORDIC_X_CORDIC_X_SHIFT (0U) +#define POWERQUAD_CORDIC_X_CORDIC_X(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CORDIC_X_CORDIC_X_SHIFT)) & POWERQUAD_CORDIC_X_CORDIC_X_MASK) +/*! @} */ + +/*! @name CORDIC_Y - Cordic input Y register */ +/*! @{ */ +#define POWERQUAD_CORDIC_Y_CORDIC_Y_MASK (0xFFFFFFFFU) +#define POWERQUAD_CORDIC_Y_CORDIC_Y_SHIFT (0U) +#define POWERQUAD_CORDIC_Y_CORDIC_Y(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CORDIC_Y_CORDIC_Y_SHIFT)) & POWERQUAD_CORDIC_Y_CORDIC_Y_MASK) +/*! @} */ + +/*! @name CORDIC_Z - Cordic input Z register */ +/*! @{ */ +#define POWERQUAD_CORDIC_Z_CORDIC_Z_MASK (0xFFFFFFFFU) +#define POWERQUAD_CORDIC_Z_CORDIC_Z_SHIFT (0U) +#define POWERQUAD_CORDIC_Z_CORDIC_Z(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CORDIC_Z_CORDIC_Z_SHIFT)) & POWERQUAD_CORDIC_Z_CORDIC_Z_MASK) +/*! @} */ + +/*! @name ERRSTAT - Read/Write register where error statuses are captured (sticky) */ +/*! @{ */ +#define POWERQUAD_ERRSTAT_OVERFLOW_MASK (0x1U) +#define POWERQUAD_ERRSTAT_OVERFLOW_SHIFT (0U) +#define POWERQUAD_ERRSTAT_OVERFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_OVERFLOW_SHIFT)) & POWERQUAD_ERRSTAT_OVERFLOW_MASK) +#define POWERQUAD_ERRSTAT_NAN_MASK (0x2U) +#define POWERQUAD_ERRSTAT_NAN_SHIFT (1U) +#define POWERQUAD_ERRSTAT_NAN(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_NAN_SHIFT)) & POWERQUAD_ERRSTAT_NAN_MASK) +#define POWERQUAD_ERRSTAT_FIXEDOVERFLOW_MASK (0x4U) +#define POWERQUAD_ERRSTAT_FIXEDOVERFLOW_SHIFT (2U) +#define POWERQUAD_ERRSTAT_FIXEDOVERFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_FIXEDOVERFLOW_SHIFT)) & POWERQUAD_ERRSTAT_FIXEDOVERFLOW_MASK) +#define POWERQUAD_ERRSTAT_UNDERFLOW_MASK (0x8U) +#define POWERQUAD_ERRSTAT_UNDERFLOW_SHIFT (3U) +#define POWERQUAD_ERRSTAT_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_UNDERFLOW_SHIFT)) & POWERQUAD_ERRSTAT_UNDERFLOW_MASK) +#define POWERQUAD_ERRSTAT_BUSERROR_MASK (0x10U) +#define POWERQUAD_ERRSTAT_BUSERROR_SHIFT (4U) +#define POWERQUAD_ERRSTAT_BUSERROR(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_BUSERROR_SHIFT)) & POWERQUAD_ERRSTAT_BUSERROR_MASK) +/*! @} */ + +/*! @name INTREN - INTERRUPT enable register */ +/*! @{ */ +#define POWERQUAD_INTREN_INTR_OFLOW_MASK (0x1U) +#define POWERQUAD_INTREN_INTR_OFLOW_SHIFT (0U) +#define POWERQUAD_INTREN_INTR_OFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_OFLOW_SHIFT)) & POWERQUAD_INTREN_INTR_OFLOW_MASK) +#define POWERQUAD_INTREN_INTR_NAN_MASK (0x2U) +#define POWERQUAD_INTREN_INTR_NAN_SHIFT (1U) +#define POWERQUAD_INTREN_INTR_NAN(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_NAN_SHIFT)) & POWERQUAD_INTREN_INTR_NAN_MASK) +#define POWERQUAD_INTREN_INTR_FIXED_MASK (0x4U) +#define POWERQUAD_INTREN_INTR_FIXED_SHIFT (2U) +#define POWERQUAD_INTREN_INTR_FIXED(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_FIXED_SHIFT)) & POWERQUAD_INTREN_INTR_FIXED_MASK) +#define POWERQUAD_INTREN_INTR_UFLOW_MASK (0x8U) +#define POWERQUAD_INTREN_INTR_UFLOW_SHIFT (3U) +#define POWERQUAD_INTREN_INTR_UFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_UFLOW_SHIFT)) & POWERQUAD_INTREN_INTR_UFLOW_MASK) +#define POWERQUAD_INTREN_INTR_BERR_MASK (0x10U) +#define POWERQUAD_INTREN_INTR_BERR_SHIFT (4U) +#define POWERQUAD_INTREN_INTR_BERR(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_BERR_SHIFT)) & POWERQUAD_INTREN_INTR_BERR_MASK) +#define POWERQUAD_INTREN_INTR_COMP_MASK (0x80U) +#define POWERQUAD_INTREN_INTR_COMP_SHIFT (7U) +#define POWERQUAD_INTREN_INTR_COMP(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_COMP_SHIFT)) & POWERQUAD_INTREN_INTR_COMP_MASK) +/*! @} */ + +/*! @name EVENTEN - Event Enable register */ +/*! @{ */ +#define POWERQUAD_EVENTEN_EVENT_OFLOW_MASK (0x1U) +#define POWERQUAD_EVENTEN_EVENT_OFLOW_SHIFT (0U) +#define POWERQUAD_EVENTEN_EVENT_OFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_OFLOW_SHIFT)) & POWERQUAD_EVENTEN_EVENT_OFLOW_MASK) +#define POWERQUAD_EVENTEN_EVENT_NAN_MASK (0x2U) +#define POWERQUAD_EVENTEN_EVENT_NAN_SHIFT (1U) +#define POWERQUAD_EVENTEN_EVENT_NAN(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_NAN_SHIFT)) & POWERQUAD_EVENTEN_EVENT_NAN_MASK) +#define POWERQUAD_EVENTEN_EVENT_FIXED_MASK (0x4U) +#define POWERQUAD_EVENTEN_EVENT_FIXED_SHIFT (2U) +#define POWERQUAD_EVENTEN_EVENT_FIXED(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_FIXED_SHIFT)) & POWERQUAD_EVENTEN_EVENT_FIXED_MASK) +#define POWERQUAD_EVENTEN_EVENT_UFLOW_MASK (0x8U) +#define POWERQUAD_EVENTEN_EVENT_UFLOW_SHIFT (3U) +#define POWERQUAD_EVENTEN_EVENT_UFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_UFLOW_SHIFT)) & POWERQUAD_EVENTEN_EVENT_UFLOW_MASK) +#define POWERQUAD_EVENTEN_EVENT_BERR_MASK (0x10U) +#define POWERQUAD_EVENTEN_EVENT_BERR_SHIFT (4U) +#define POWERQUAD_EVENTEN_EVENT_BERR(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_BERR_SHIFT)) & POWERQUAD_EVENTEN_EVENT_BERR_MASK) +#define POWERQUAD_EVENTEN_EVENT_COMP_MASK (0x80U) +#define POWERQUAD_EVENTEN_EVENT_COMP_SHIFT (7U) +#define POWERQUAD_EVENTEN_EVENT_COMP(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_COMP_SHIFT)) & POWERQUAD_EVENTEN_EVENT_COMP_MASK) +/*! @} */ + +/*! @name INTRSTAT - INTERRUPT STATUS register */ +/*! @{ */ +#define POWERQUAD_INTRSTAT_INTR_STAT_MASK (0x1U) +#define POWERQUAD_INTRSTAT_INTR_STAT_SHIFT (0U) +#define POWERQUAD_INTRSTAT_INTR_STAT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTRSTAT_INTR_STAT_SHIFT)) & POWERQUAD_INTRSTAT_INTR_STAT_MASK) +/*! @} */ + +/*! @name GPREG - General purpose register bank N. */ +/*! @{ */ +#define POWERQUAD_GPREG_GPREG_MASK (0xFFFFFFFFU) +#define POWERQUAD_GPREG_GPREG_SHIFT (0U) +#define POWERQUAD_GPREG_GPREG(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_GPREG_GPREG_SHIFT)) & POWERQUAD_GPREG_GPREG_MASK) +/*! @} */ + +/* The count of POWERQUAD_GPREG */ +#define POWERQUAD_GPREG_COUNT (16U) + +/*! @name COMPREGS_COMPREG - Compute register bank */ +/*! @{ */ +#define POWERQUAD_COMPREGS_COMPREG_COMPREG_MASK (0xFFFFFFFFU) +#define POWERQUAD_COMPREGS_COMPREG_COMPREG_SHIFT (0U) +#define POWERQUAD_COMPREGS_COMPREG_COMPREG(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_COMPREGS_COMPREG_COMPREG_SHIFT)) & POWERQUAD_COMPREGS_COMPREG_COMPREG_MASK) +/*! @} */ + +/* The count of POWERQUAD_COMPREGS_COMPREG */ +#define POWERQUAD_COMPREGS_COMPREG_COUNT (8U) + + +/*! + * @} + */ /* end of group POWERQUAD_Register_Masks */ + + +/* POWERQUAD - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral POWERQUAD base address */ + #define POWERQUAD_BASE (0x500A6000u) + /** Peripheral POWERQUAD base address */ + #define POWERQUAD_BASE_NS (0x400A6000u) + /** Peripheral POWERQUAD base pointer */ + #define POWERQUAD ((POWERQUAD_Type *)POWERQUAD_BASE) + /** Peripheral POWERQUAD base pointer */ + #define POWERQUAD_NS ((POWERQUAD_Type *)POWERQUAD_BASE_NS) + /** Array initializer of POWERQUAD peripheral base addresses */ + #define POWERQUAD_BASE_ADDRS { POWERQUAD_BASE } + /** Array initializer of POWERQUAD peripheral base pointers */ + #define POWERQUAD_BASE_PTRS { POWERQUAD } + /** Array initializer of POWERQUAD peripheral base addresses */ + #define POWERQUAD_BASE_ADDRS_NS { POWERQUAD_BASE_NS } + /** Array initializer of POWERQUAD peripheral base pointers */ + #define POWERQUAD_BASE_PTRS_NS { POWERQUAD_NS } +#else + /** Peripheral POWERQUAD base address */ + #define POWERQUAD_BASE (0x400A6000u) + /** Peripheral POWERQUAD base pointer */ + #define POWERQUAD ((POWERQUAD_Type *)POWERQUAD_BASE) + /** Array initializer of POWERQUAD peripheral base addresses */ + #define POWERQUAD_BASE_ADDRS { POWERQUAD_BASE } + /** Array initializer of POWERQUAD peripheral base pointers */ + #define POWERQUAD_BASE_PTRS { POWERQUAD } +#endif + +/*! + * @} + */ /* end of group POWERQUAD_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PRINCE Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PRINCE_Peripheral_Access_Layer PRINCE Peripheral Access Layer + * @{ + */ + +/** PRINCE - Register Layout Typedef */ +typedef struct { + __IO uint32_t ENC_ENABLE; /**< Encryption Enable register, offset: 0x0 */ + __O uint32_t MASK_LSB; /**< Data Mask register, 32 Least Significant Bits, offset: 0x4 */ + __O uint32_t MASK_MSB; /**< Data Mask register, 32 Most Significant Bits, offset: 0x8 */ + __IO uint32_t LOCK; /**< Lock register, offset: 0xC */ + __O uint32_t IV_LSB0; /**< Initial Vector register for region 0, Least Significant Bits, offset: 0x10 */ + __O uint32_t IV_MSB0; /**< Initial Vector register for region 0, Most Significant Bits, offset: 0x14 */ + __IO uint32_t BASE_ADDR0; /**< Base Address for region 0 register, offset: 0x18 */ + __IO uint32_t SR_ENABLE0; /**< Sub-Region Enable register for region 0, offset: 0x1C */ + __O uint32_t IV_LSB1; /**< Initial Vector register for region 1, Least Significant Bits, offset: 0x20 */ + __O uint32_t IV_MSB1; /**< Initial Vector register for region 1, Most Significant Bits, offset: 0x24 */ + __IO uint32_t BASE_ADDR1; /**< Base Address for region 1 register, offset: 0x28 */ + __IO uint32_t SR_ENABLE1; /**< Sub-Region Enable register for region 1, offset: 0x2C */ + __O uint32_t IV_LSB2; /**< Initial Vector register for region 2, Least Significant Bits, offset: 0x30 */ + __O uint32_t IV_MSB2; /**< Initial Vector register for region 2, Most Significant Bits, offset: 0x34 */ + __IO uint32_t BASE_ADDR2; /**< Base Address for region 2 register, offset: 0x38 */ + __IO uint32_t SR_ENABLE2; /**< Sub-Region Enable register for region 2, offset: 0x3C */ +} PRINCE_Type; + +/* ---------------------------------------------------------------------------- + -- PRINCE Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PRINCE_Register_Masks PRINCE Register Masks + * @{ + */ + +/*! @name ENC_ENABLE - Encryption Enable register */ +/*! @{ */ +#define PRINCE_ENC_ENABLE_EN_MASK (0x1U) +#define PRINCE_ENC_ENABLE_EN_SHIFT (0U) +/*! EN - Encryption Enable. + * 0b0..Encryption of writes to the flash controller DATAW* registers is disabled.. + * 0b1..Encryption of writes to the flash controller DATAW* registers is enabled.. + */ +#define PRINCE_ENC_ENABLE_EN(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_ENC_ENABLE_EN_SHIFT)) & PRINCE_ENC_ENABLE_EN_MASK) +/*! @} */ + +/*! @name MASK_LSB - Data Mask register, 32 Least Significant Bits */ +/*! @{ */ +#define PRINCE_MASK_LSB_MASKVAL_MASK (0xFFFFFFFFU) +#define PRINCE_MASK_LSB_MASKVAL_SHIFT (0U) +#define PRINCE_MASK_LSB_MASKVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_MASK_LSB_MASKVAL_SHIFT)) & PRINCE_MASK_LSB_MASKVAL_MASK) +/*! @} */ + +/*! @name MASK_MSB - Data Mask register, 32 Most Significant Bits */ +/*! @{ */ +#define PRINCE_MASK_MSB_MASKVAL_MASK (0xFFFFFFFFU) +#define PRINCE_MASK_MSB_MASKVAL_SHIFT (0U) +#define PRINCE_MASK_MSB_MASKVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_MASK_MSB_MASKVAL_SHIFT)) & PRINCE_MASK_MSB_MASKVAL_MASK) +/*! @} */ + +/*! @name LOCK - Lock register */ +/*! @{ */ +#define PRINCE_LOCK_LOCKREG0_MASK (0x1U) +#define PRINCE_LOCK_LOCKREG0_SHIFT (0U) +/*! LOCKREG0 - Lock Region 0 registers. + * 0b0..Disabled. IV_LSB0, IV_MSB0, BASE_ADDR0, and SR_ENABLE0 are writable.. + * 0b1..Enabled. IV_LSB0, IV_MSB0, BASE_ADDR0, and SR_ENABLE0 are not writable.. + */ +#define PRINCE_LOCK_LOCKREG0(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKREG0_SHIFT)) & PRINCE_LOCK_LOCKREG0_MASK) +#define PRINCE_LOCK_LOCKREG1_MASK (0x2U) +#define PRINCE_LOCK_LOCKREG1_SHIFT (1U) +/*! LOCKREG1 - Lock Region 1 registers. + * 0b0..Disabled. IV_LSB1, IV_MSB1, BASE_ADDR1, and SR_ENABLE1 are writable.. + * 0b1..Enabled. IV_LSB1, IV_MSB1, BASE_ADDR1, and SR_ENABLE1 are not writable.. + */ +#define PRINCE_LOCK_LOCKREG1(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKREG1_SHIFT)) & PRINCE_LOCK_LOCKREG1_MASK) +#define PRINCE_LOCK_LOCKREG2_MASK (0x4U) +#define PRINCE_LOCK_LOCKREG2_SHIFT (2U) +/*! LOCKREG2 - Lock Region 2 registers. + * 0b0..Disabled. IV_LSB2, IV_MSB2, BASE_ADDR2, and SR_ENABLE2 are writable.. + * 0b1..Enabled. IV_LSB2, IV_MSB2, BASE_ADDR2, and SR_ENABLE2 are not writable.. + */ +#define PRINCE_LOCK_LOCKREG2(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKREG2_SHIFT)) & PRINCE_LOCK_LOCKREG2_MASK) +#define PRINCE_LOCK_LOCKMASK_MASK (0x100U) +#define PRINCE_LOCK_LOCKMASK_SHIFT (8U) +/*! LOCKMASK - Lock the Mask registers. + * 0b0..Disabled. MASK_LSB, and MASK_MSB are writable.. + * 0b1..Enabled. MASK_LSB, and MASK_MSB are not writable.. + */ +#define PRINCE_LOCK_LOCKMASK(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKMASK_SHIFT)) & PRINCE_LOCK_LOCKMASK_MASK) +/*! @} */ + +/*! @name IV_LSB0 - Initial Vector register for region 0, Least Significant Bits */ +/*! @{ */ +#define PRINCE_IV_LSB0_IVVAL_MASK (0xFFFFFFFFU) +#define PRINCE_IV_LSB0_IVVAL_SHIFT (0U) +#define PRINCE_IV_LSB0_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_LSB0_IVVAL_SHIFT)) & PRINCE_IV_LSB0_IVVAL_MASK) +/*! @} */ + +/*! @name IV_MSB0 - Initial Vector register for region 0, Most Significant Bits */ +/*! @{ */ +#define PRINCE_IV_MSB0_IVVAL_MASK (0xFFFFFFFFU) +#define PRINCE_IV_MSB0_IVVAL_SHIFT (0U) +#define PRINCE_IV_MSB0_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_MSB0_IVVAL_SHIFT)) & PRINCE_IV_MSB0_IVVAL_MASK) +/*! @} */ + +/*! @name BASE_ADDR0 - Base Address for region 0 register */ +/*! @{ */ +#define PRINCE_BASE_ADDR0_ADDR_FIXED_MASK (0x3FFFFU) +#define PRINCE_BASE_ADDR0_ADDR_FIXED_SHIFT (0U) +#define PRINCE_BASE_ADDR0_ADDR_FIXED(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR0_ADDR_FIXED_SHIFT)) & PRINCE_BASE_ADDR0_ADDR_FIXED_MASK) +#define PRINCE_BASE_ADDR0_ADDR_PRG_MASK (0xC0000U) +#define PRINCE_BASE_ADDR0_ADDR_PRG_SHIFT (18U) +#define PRINCE_BASE_ADDR0_ADDR_PRG(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR0_ADDR_PRG_SHIFT)) & PRINCE_BASE_ADDR0_ADDR_PRG_MASK) +/*! @} */ + +/*! @name SR_ENABLE0 - Sub-Region Enable register for region 0 */ +/*! @{ */ +#define PRINCE_SR_ENABLE0_EN_MASK (0xFFFFFFFFU) +#define PRINCE_SR_ENABLE0_EN_SHIFT (0U) +#define PRINCE_SR_ENABLE0_EN(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_SR_ENABLE0_EN_SHIFT)) & PRINCE_SR_ENABLE0_EN_MASK) +/*! @} */ + +/*! @name IV_LSB1 - Initial Vector register for region 1, Least Significant Bits */ +/*! @{ */ +#define PRINCE_IV_LSB1_IVVAL_MASK (0xFFFFFFFFU) +#define PRINCE_IV_LSB1_IVVAL_SHIFT (0U) +#define PRINCE_IV_LSB1_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_LSB1_IVVAL_SHIFT)) & PRINCE_IV_LSB1_IVVAL_MASK) +/*! @} */ + +/*! @name IV_MSB1 - Initial Vector register for region 1, Most Significant Bits */ +/*! @{ */ +#define PRINCE_IV_MSB1_IVVAL_MASK (0xFFFFFFFFU) +#define PRINCE_IV_MSB1_IVVAL_SHIFT (0U) +#define PRINCE_IV_MSB1_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_MSB1_IVVAL_SHIFT)) & PRINCE_IV_MSB1_IVVAL_MASK) +/*! @} */ + +/*! @name BASE_ADDR1 - Base Address for region 1 register */ +/*! @{ */ +#define PRINCE_BASE_ADDR1_ADDR_FIXED_MASK (0x3FFFFU) +#define PRINCE_BASE_ADDR1_ADDR_FIXED_SHIFT (0U) +#define PRINCE_BASE_ADDR1_ADDR_FIXED(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR1_ADDR_FIXED_SHIFT)) & PRINCE_BASE_ADDR1_ADDR_FIXED_MASK) +#define PRINCE_BASE_ADDR1_ADDR_PRG_MASK (0xC0000U) +#define PRINCE_BASE_ADDR1_ADDR_PRG_SHIFT (18U) +#define PRINCE_BASE_ADDR1_ADDR_PRG(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR1_ADDR_PRG_SHIFT)) & PRINCE_BASE_ADDR1_ADDR_PRG_MASK) +/*! @} */ + +/*! @name SR_ENABLE1 - Sub-Region Enable register for region 1 */ +/*! @{ */ +#define PRINCE_SR_ENABLE1_EN_MASK (0xFFFFFFFFU) +#define PRINCE_SR_ENABLE1_EN_SHIFT (0U) +#define PRINCE_SR_ENABLE1_EN(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_SR_ENABLE1_EN_SHIFT)) & PRINCE_SR_ENABLE1_EN_MASK) +/*! @} */ + +/*! @name IV_LSB2 - Initial Vector register for region 2, Least Significant Bits */ +/*! @{ */ +#define PRINCE_IV_LSB2_IVVAL_MASK (0xFFFFFFFFU) +#define PRINCE_IV_LSB2_IVVAL_SHIFT (0U) +#define PRINCE_IV_LSB2_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_LSB2_IVVAL_SHIFT)) & PRINCE_IV_LSB2_IVVAL_MASK) +/*! @} */ + +/*! @name IV_MSB2 - Initial Vector register for region 2, Most Significant Bits */ +/*! @{ */ +#define PRINCE_IV_MSB2_IVVAL_MASK (0xFFFFFFFFU) +#define PRINCE_IV_MSB2_IVVAL_SHIFT (0U) +#define PRINCE_IV_MSB2_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_MSB2_IVVAL_SHIFT)) & PRINCE_IV_MSB2_IVVAL_MASK) +/*! @} */ + +/*! @name BASE_ADDR2 - Base Address for region 2 register */ +/*! @{ */ +#define PRINCE_BASE_ADDR2_ADDR_FIXED_MASK (0x3FFFFU) +#define PRINCE_BASE_ADDR2_ADDR_FIXED_SHIFT (0U) +#define PRINCE_BASE_ADDR2_ADDR_FIXED(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR2_ADDR_FIXED_SHIFT)) & PRINCE_BASE_ADDR2_ADDR_FIXED_MASK) +#define PRINCE_BASE_ADDR2_ADDR_PRG_MASK (0xC0000U) +#define PRINCE_BASE_ADDR2_ADDR_PRG_SHIFT (18U) +#define PRINCE_BASE_ADDR2_ADDR_PRG(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR2_ADDR_PRG_SHIFT)) & PRINCE_BASE_ADDR2_ADDR_PRG_MASK) +/*! @} */ + +/*! @name SR_ENABLE2 - Sub-Region Enable register for region 2 */ +/*! @{ */ +#define PRINCE_SR_ENABLE2_EN_MASK (0xFFFFFFFFU) +#define PRINCE_SR_ENABLE2_EN_SHIFT (0U) +#define PRINCE_SR_ENABLE2_EN(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_SR_ENABLE2_EN_SHIFT)) & PRINCE_SR_ENABLE2_EN_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group PRINCE_Register_Masks */ + + +/* PRINCE - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral PRINCE base address */ + #define PRINCE_BASE (0x50035000u) + /** Peripheral PRINCE base address */ + #define PRINCE_BASE_NS (0x40035000u) + /** Peripheral PRINCE base pointer */ + #define PRINCE ((PRINCE_Type *)PRINCE_BASE) + /** Peripheral PRINCE base pointer */ + #define PRINCE_NS ((PRINCE_Type *)PRINCE_BASE_NS) + /** Array initializer of PRINCE peripheral base addresses */ + #define PRINCE_BASE_ADDRS { PRINCE_BASE } + /** Array initializer of PRINCE peripheral base pointers */ + #define PRINCE_BASE_PTRS { PRINCE } + /** Array initializer of PRINCE peripheral base addresses */ + #define PRINCE_BASE_ADDRS_NS { PRINCE_BASE_NS } + /** Array initializer of PRINCE peripheral base pointers */ + #define PRINCE_BASE_PTRS_NS { PRINCE_NS } +#else + /** Peripheral PRINCE base address */ + #define PRINCE_BASE (0x40035000u) + /** Peripheral PRINCE base pointer */ + #define PRINCE ((PRINCE_Type *)PRINCE_BASE) + /** Array initializer of PRINCE peripheral base addresses */ + #define PRINCE_BASE_ADDRS { PRINCE_BASE } + /** Array initializer of PRINCE peripheral base pointers */ + #define PRINCE_BASE_PTRS { PRINCE } +#endif + +/*! + * @} + */ /* end of group PRINCE_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PUF Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PUF_Peripheral_Access_Layer PUF Peripheral Access Layer + * @{ + */ + +/** PUF - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< PUF Control register, offset: 0x0 */ + __IO uint32_t KEYINDEX; /**< PUF Key Index register, offset: 0x4 */ + __IO uint32_t KEYSIZE; /**< PUF Key Size register, offset: 0x8 */ + uint8_t RESERVED_0[20]; + __I uint32_t STAT; /**< PUF Status register, offset: 0x20 */ + uint8_t RESERVED_1[4]; + __I uint32_t ALLOW; /**< PUF Allow register, offset: 0x28 */ + uint8_t RESERVED_2[20]; + __O uint32_t KEYINPUT; /**< PUF Key Input register, offset: 0x40 */ + __O uint32_t CODEINPUT; /**< PUF Code Input register, offset: 0x44 */ + __I uint32_t CODEOUTPUT; /**< PUF Code Output register, offset: 0x48 */ + uint8_t RESERVED_3[20]; + __I uint32_t KEYOUTINDEX; /**< PUF Key Output Index register, offset: 0x60 */ + __I uint32_t KEYOUTPUT; /**< PUF Key Output register, offset: 0x64 */ + uint8_t RESERVED_4[116]; + __IO uint32_t IFSTAT; /**< PUF Interface Status and clear register, offset: 0xDC */ + uint8_t RESERVED_5[28]; + __I uint32_t VERSION; /**< PUF version register., offset: 0xFC */ + __IO uint32_t INTEN; /**< PUF Interrupt Enable, offset: 0x100 */ + __IO uint32_t INTSTAT; /**< PUF interrupt status, offset: 0x104 */ + __IO uint32_t PWRCTRL; /**< PUF RAM Power Control, offset: 0x108 */ + __IO uint32_t CFG; /**< PUF config register for block bits, offset: 0x10C */ + uint8_t RESERVED_6[240]; + __IO uint32_t KEYLOCK; /**< Only reset in case of full IC reset, offset: 0x200 */ + __IO uint32_t KEYENABLE; /**< , offset: 0x204 */ + __O uint32_t KEYRESET; /**< Reinitialize Keys shift registers counters, offset: 0x208 */ + __IO uint32_t IDXBLK_L; /**< , offset: 0x20C */ + __IO uint32_t IDXBLK_H_DP; /**< , offset: 0x210 */ + __O uint32_t KEYMASK[4]; /**< Only reset in case of full IC reset, array offset: 0x214, array step: 0x4 */ + uint8_t RESERVED_7[48]; + __IO uint32_t IDXBLK_H; /**< , offset: 0x254 */ + __IO uint32_t IDXBLK_L_DP; /**< , offset: 0x258 */ + __I uint32_t SHIFT_STATUS; /**< , offset: 0x25C */ +} PUF_Type; + +/* ---------------------------------------------------------------------------- + -- PUF Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PUF_Register_Masks PUF Register Masks + * @{ + */ + +/*! @name CTRL - PUF Control register */ +/*! @{ */ +#define PUF_CTRL_ZEROIZE_MASK (0x1U) +#define PUF_CTRL_ZEROIZE_SHIFT (0U) +#define PUF_CTRL_ZEROIZE(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_ZEROIZE_SHIFT)) & PUF_CTRL_ZEROIZE_MASK) +#define PUF_CTRL_ENROLL_MASK (0x2U) +#define PUF_CTRL_ENROLL_SHIFT (1U) +#define PUF_CTRL_ENROLL(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_ENROLL_SHIFT)) & PUF_CTRL_ENROLL_MASK) +#define PUF_CTRL_START_MASK (0x4U) +#define PUF_CTRL_START_SHIFT (2U) +#define PUF_CTRL_START(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_START_SHIFT)) & PUF_CTRL_START_MASK) +#define PUF_CTRL_GENERATEKEY_MASK (0x8U) +#define PUF_CTRL_GENERATEKEY_SHIFT (3U) +#define PUF_CTRL_GENERATEKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_GENERATEKEY_SHIFT)) & PUF_CTRL_GENERATEKEY_MASK) +#define PUF_CTRL_SETKEY_MASK (0x10U) +#define PUF_CTRL_SETKEY_SHIFT (4U) +#define PUF_CTRL_SETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_SETKEY_SHIFT)) & PUF_CTRL_SETKEY_MASK) +#define PUF_CTRL_GETKEY_MASK (0x40U) +#define PUF_CTRL_GETKEY_SHIFT (6U) +#define PUF_CTRL_GETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_GETKEY_SHIFT)) & PUF_CTRL_GETKEY_MASK) +/*! @} */ + +/*! @name KEYINDEX - PUF Key Index register */ +/*! @{ */ +#define PUF_KEYINDEX_KEYIDX_MASK (0xFU) +#define PUF_KEYINDEX_KEYIDX_SHIFT (0U) +#define PUF_KEYINDEX_KEYIDX(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYINDEX_KEYIDX_SHIFT)) & PUF_KEYINDEX_KEYIDX_MASK) +/*! @} */ + +/*! @name KEYSIZE - PUF Key Size register */ +/*! @{ */ +#define PUF_KEYSIZE_KEYSIZE_MASK (0x3FU) +#define PUF_KEYSIZE_KEYSIZE_SHIFT (0U) +#define PUF_KEYSIZE_KEYSIZE(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYSIZE_KEYSIZE_SHIFT)) & PUF_KEYSIZE_KEYSIZE_MASK) +/*! @} */ + +/*! @name STAT - PUF Status register */ +/*! @{ */ +#define PUF_STAT_BUSY_MASK (0x1U) +#define PUF_STAT_BUSY_SHIFT (0U) +#define PUF_STAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_BUSY_SHIFT)) & PUF_STAT_BUSY_MASK) +#define PUF_STAT_SUCCESS_MASK (0x2U) +#define PUF_STAT_SUCCESS_SHIFT (1U) +#define PUF_STAT_SUCCESS(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_SUCCESS_SHIFT)) & PUF_STAT_SUCCESS_MASK) +#define PUF_STAT_ERROR_MASK (0x4U) +#define PUF_STAT_ERROR_SHIFT (2U) +#define PUF_STAT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_ERROR_SHIFT)) & PUF_STAT_ERROR_MASK) +#define PUF_STAT_KEYINREQ_MASK (0x10U) +#define PUF_STAT_KEYINREQ_SHIFT (4U) +#define PUF_STAT_KEYINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_KEYINREQ_SHIFT)) & PUF_STAT_KEYINREQ_MASK) +#define PUF_STAT_KEYOUTAVAIL_MASK (0x20U) +#define PUF_STAT_KEYOUTAVAIL_SHIFT (5U) +#define PUF_STAT_KEYOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_KEYOUTAVAIL_SHIFT)) & PUF_STAT_KEYOUTAVAIL_MASK) +#define PUF_STAT_CODEINREQ_MASK (0x40U) +#define PUF_STAT_CODEINREQ_SHIFT (6U) +#define PUF_STAT_CODEINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_CODEINREQ_SHIFT)) & PUF_STAT_CODEINREQ_MASK) +#define PUF_STAT_CODEOUTAVAIL_MASK (0x80U) +#define PUF_STAT_CODEOUTAVAIL_SHIFT (7U) +#define PUF_STAT_CODEOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_CODEOUTAVAIL_SHIFT)) & PUF_STAT_CODEOUTAVAIL_MASK) +/*! @} */ + +/*! @name ALLOW - PUF Allow register */ +/*! @{ */ +#define PUF_ALLOW_ALLOWENROLL_MASK (0x1U) +#define PUF_ALLOW_ALLOWENROLL_SHIFT (0U) +#define PUF_ALLOW_ALLOWENROLL(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWENROLL_SHIFT)) & PUF_ALLOW_ALLOWENROLL_MASK) +#define PUF_ALLOW_ALLOWSTART_MASK (0x2U) +#define PUF_ALLOW_ALLOWSTART_SHIFT (1U) +#define PUF_ALLOW_ALLOWSTART(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWSTART_SHIFT)) & PUF_ALLOW_ALLOWSTART_MASK) +#define PUF_ALLOW_ALLOWSETKEY_MASK (0x4U) +#define PUF_ALLOW_ALLOWSETKEY_SHIFT (2U) +#define PUF_ALLOW_ALLOWSETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWSETKEY_SHIFT)) & PUF_ALLOW_ALLOWSETKEY_MASK) +#define PUF_ALLOW_ALLOWGETKEY_MASK (0x8U) +#define PUF_ALLOW_ALLOWGETKEY_SHIFT (3U) +#define PUF_ALLOW_ALLOWGETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWGETKEY_SHIFT)) & PUF_ALLOW_ALLOWGETKEY_MASK) +/*! @} */ + +/*! @name KEYINPUT - PUF Key Input register */ +/*! @{ */ +#define PUF_KEYINPUT_KEYIN_MASK (0xFFFFFFFFU) +#define PUF_KEYINPUT_KEYIN_SHIFT (0U) +#define PUF_KEYINPUT_KEYIN(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYINPUT_KEYIN_SHIFT)) & PUF_KEYINPUT_KEYIN_MASK) +/*! @} */ + +/*! @name CODEINPUT - PUF Code Input register */ +/*! @{ */ +#define PUF_CODEINPUT_CODEIN_MASK (0xFFFFFFFFU) +#define PUF_CODEINPUT_CODEIN_SHIFT (0U) +#define PUF_CODEINPUT_CODEIN(x) (((uint32_t)(((uint32_t)(x)) << PUF_CODEINPUT_CODEIN_SHIFT)) & PUF_CODEINPUT_CODEIN_MASK) +/*! @} */ + +/*! @name CODEOUTPUT - PUF Code Output register */ +/*! @{ */ +#define PUF_CODEOUTPUT_CODEOUT_MASK (0xFFFFFFFFU) +#define PUF_CODEOUTPUT_CODEOUT_SHIFT (0U) +#define PUF_CODEOUTPUT_CODEOUT(x) (((uint32_t)(((uint32_t)(x)) << PUF_CODEOUTPUT_CODEOUT_SHIFT)) & PUF_CODEOUTPUT_CODEOUT_MASK) +/*! @} */ + +/*! @name KEYOUTINDEX - PUF Key Output Index register */ +/*! @{ */ +#define PUF_KEYOUTINDEX_KEYOUTIDX_MASK (0xFU) +#define PUF_KEYOUTINDEX_KEYOUTIDX_SHIFT (0U) +#define PUF_KEYOUTINDEX_KEYOUTIDX(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYOUTINDEX_KEYOUTIDX_SHIFT)) & PUF_KEYOUTINDEX_KEYOUTIDX_MASK) +/*! @} */ + +/*! @name KEYOUTPUT - PUF Key Output register */ +/*! @{ */ +#define PUF_KEYOUTPUT_KEYOUT_MASK (0xFFFFFFFFU) +#define PUF_KEYOUTPUT_KEYOUT_SHIFT (0U) +#define PUF_KEYOUTPUT_KEYOUT(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYOUTPUT_KEYOUT_SHIFT)) & PUF_KEYOUTPUT_KEYOUT_MASK) +/*! @} */ + +/*! @name IFSTAT - PUF Interface Status and clear register */ +/*! @{ */ +#define PUF_IFSTAT_ERROR_MASK (0x1U) +#define PUF_IFSTAT_ERROR_SHIFT (0U) +#define PUF_IFSTAT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_IFSTAT_ERROR_SHIFT)) & PUF_IFSTAT_ERROR_MASK) +/*! @} */ + +/*! @name VERSION - PUF version register. */ +/*! @{ */ +#define PUF_VERSION_KEYOUT_MASK (0xFFFFFFFFU) +#define PUF_VERSION_KEYOUT_SHIFT (0U) +#define PUF_VERSION_KEYOUT(x) (((uint32_t)(((uint32_t)(x)) << PUF_VERSION_KEYOUT_SHIFT)) & PUF_VERSION_KEYOUT_MASK) +/*! @} */ + +/*! @name INTEN - PUF Interrupt Enable */ +/*! @{ */ +#define PUF_INTEN_READYEN_MASK (0x1U) +#define PUF_INTEN_READYEN_SHIFT (0U) +#define PUF_INTEN_READYEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_READYEN_SHIFT)) & PUF_INTEN_READYEN_MASK) +#define PUF_INTEN_SUCCESEN_MASK (0x2U) +#define PUF_INTEN_SUCCESEN_SHIFT (1U) +#define PUF_INTEN_SUCCESEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_SUCCESEN_SHIFT)) & PUF_INTEN_SUCCESEN_MASK) +#define PUF_INTEN_ERROREN_MASK (0x4U) +#define PUF_INTEN_ERROREN_SHIFT (2U) +#define PUF_INTEN_ERROREN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_ERROREN_SHIFT)) & PUF_INTEN_ERROREN_MASK) +#define PUF_INTEN_KEYINREQEN_MASK (0x10U) +#define PUF_INTEN_KEYINREQEN_SHIFT (4U) +#define PUF_INTEN_KEYINREQEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_KEYINREQEN_SHIFT)) & PUF_INTEN_KEYINREQEN_MASK) +#define PUF_INTEN_KEYOUTAVAILEN_MASK (0x20U) +#define PUF_INTEN_KEYOUTAVAILEN_SHIFT (5U) +#define PUF_INTEN_KEYOUTAVAILEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_KEYOUTAVAILEN_SHIFT)) & PUF_INTEN_KEYOUTAVAILEN_MASK) +#define PUF_INTEN_CODEINREQEN_MASK (0x40U) +#define PUF_INTEN_CODEINREQEN_SHIFT (6U) +#define PUF_INTEN_CODEINREQEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_CODEINREQEN_SHIFT)) & PUF_INTEN_CODEINREQEN_MASK) +#define PUF_INTEN_CODEOUTAVAILEN_MASK (0x80U) +#define PUF_INTEN_CODEOUTAVAILEN_SHIFT (7U) +#define PUF_INTEN_CODEOUTAVAILEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_CODEOUTAVAILEN_SHIFT)) & PUF_INTEN_CODEOUTAVAILEN_MASK) +/*! @} */ + +/*! @name INTSTAT - PUF interrupt status */ +/*! @{ */ +#define PUF_INTSTAT_READY_MASK (0x1U) +#define PUF_INTSTAT_READY_SHIFT (0U) +#define PUF_INTSTAT_READY(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_READY_SHIFT)) & PUF_INTSTAT_READY_MASK) +#define PUF_INTSTAT_SUCCESS_MASK (0x2U) +#define PUF_INTSTAT_SUCCESS_SHIFT (1U) +#define PUF_INTSTAT_SUCCESS(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_SUCCESS_SHIFT)) & PUF_INTSTAT_SUCCESS_MASK) +#define PUF_INTSTAT_ERROR_MASK (0x4U) +#define PUF_INTSTAT_ERROR_SHIFT (2U) +#define PUF_INTSTAT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_ERROR_SHIFT)) & PUF_INTSTAT_ERROR_MASK) +#define PUF_INTSTAT_KEYINREQ_MASK (0x10U) +#define PUF_INTSTAT_KEYINREQ_SHIFT (4U) +#define PUF_INTSTAT_KEYINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_KEYINREQ_SHIFT)) & PUF_INTSTAT_KEYINREQ_MASK) +#define PUF_INTSTAT_KEYOUTAVAIL_MASK (0x20U) +#define PUF_INTSTAT_KEYOUTAVAIL_SHIFT (5U) +#define PUF_INTSTAT_KEYOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_KEYOUTAVAIL_SHIFT)) & PUF_INTSTAT_KEYOUTAVAIL_MASK) +#define PUF_INTSTAT_CODEINREQ_MASK (0x40U) +#define PUF_INTSTAT_CODEINREQ_SHIFT (6U) +#define PUF_INTSTAT_CODEINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_CODEINREQ_SHIFT)) & PUF_INTSTAT_CODEINREQ_MASK) +#define PUF_INTSTAT_CODEOUTAVAIL_MASK (0x80U) +#define PUF_INTSTAT_CODEOUTAVAIL_SHIFT (7U) +#define PUF_INTSTAT_CODEOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_CODEOUTAVAIL_SHIFT)) & PUF_INTSTAT_CODEOUTAVAIL_MASK) +/*! @} */ + +/*! @name PWRCTRL - PUF RAM Power Control */ +/*! @{ */ +#define PUF_PWRCTRL_RAMON_MASK (0x1U) +#define PUF_PWRCTRL_RAMON_SHIFT (0U) +#define PUF_PWRCTRL_RAMON(x) (((uint32_t)(((uint32_t)(x)) << PUF_PWRCTRL_RAMON_SHIFT)) & PUF_PWRCTRL_RAMON_MASK) +#define PUF_PWRCTRL_RAMSTAT_MASK (0x2U) +#define PUF_PWRCTRL_RAMSTAT_SHIFT (1U) +#define PUF_PWRCTRL_RAMSTAT(x) (((uint32_t)(((uint32_t)(x)) << PUF_PWRCTRL_RAMSTAT_SHIFT)) & PUF_PWRCTRL_RAMSTAT_MASK) +/*! @} */ + +/*! @name CFG - PUF config register for block bits */ +/*! @{ */ +#define PUF_CFG_BLOCKENROLL_SETKEY_MASK (0x1U) +#define PUF_CFG_BLOCKENROLL_SETKEY_SHIFT (0U) +#define PUF_CFG_BLOCKENROLL_SETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CFG_BLOCKENROLL_SETKEY_SHIFT)) & PUF_CFG_BLOCKENROLL_SETKEY_MASK) +#define PUF_CFG_BLOCKKEYOUTPUT_MASK (0x2U) +#define PUF_CFG_BLOCKKEYOUTPUT_SHIFT (1U) +#define PUF_CFG_BLOCKKEYOUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PUF_CFG_BLOCKKEYOUTPUT_SHIFT)) & PUF_CFG_BLOCKKEYOUTPUT_MASK) +/*! @} */ + +/*! @name KEYLOCK - Only reset in case of full IC reset */ +/*! @{ */ +#define PUF_KEYLOCK_KEY0_MASK (0x3U) +#define PUF_KEYLOCK_KEY0_SHIFT (0U) +#define PUF_KEYLOCK_KEY0(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_KEY0_SHIFT)) & PUF_KEYLOCK_KEY0_MASK) +#define PUF_KEYLOCK_KEY1_MASK (0xCU) +#define PUF_KEYLOCK_KEY1_SHIFT (2U) +#define PUF_KEYLOCK_KEY1(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_KEY1_SHIFT)) & PUF_KEYLOCK_KEY1_MASK) +#define PUF_KEYLOCK_KEY2_MASK (0x30U) +#define PUF_KEYLOCK_KEY2_SHIFT (4U) +#define PUF_KEYLOCK_KEY2(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_KEY2_SHIFT)) & PUF_KEYLOCK_KEY2_MASK) +#define PUF_KEYLOCK_KEY3_MASK (0xC0U) +#define PUF_KEYLOCK_KEY3_SHIFT (6U) +#define PUF_KEYLOCK_KEY3(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_KEY3_SHIFT)) & PUF_KEYLOCK_KEY3_MASK) +/*! @} */ + +/*! @name KEYENABLE - */ +/*! @{ */ +#define PUF_KEYENABLE_KEY0_MASK (0x3U) +#define PUF_KEYENABLE_KEY0_SHIFT (0U) +#define PUF_KEYENABLE_KEY0(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_KEY0_SHIFT)) & PUF_KEYENABLE_KEY0_MASK) +#define PUF_KEYENABLE_KEY1_MASK (0xCU) +#define PUF_KEYENABLE_KEY1_SHIFT (2U) +#define PUF_KEYENABLE_KEY1(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_KEY1_SHIFT)) & PUF_KEYENABLE_KEY1_MASK) +#define PUF_KEYENABLE_KEY2_MASK (0x30U) +#define PUF_KEYENABLE_KEY2_SHIFT (4U) +#define PUF_KEYENABLE_KEY2(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_KEY2_SHIFT)) & PUF_KEYENABLE_KEY2_MASK) +#define PUF_KEYENABLE_KEY3_MASK (0xC0U) +#define PUF_KEYENABLE_KEY3_SHIFT (6U) +#define PUF_KEYENABLE_KEY3(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_KEY3_SHIFT)) & PUF_KEYENABLE_KEY3_MASK) +/*! @} */ + +/*! @name KEYRESET - Reinitialize Keys shift registers counters */ +/*! @{ */ +#define PUF_KEYRESET_KEY0_MASK (0x3U) +#define PUF_KEYRESET_KEY0_SHIFT (0U) +#define PUF_KEYRESET_KEY0(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_KEY0_SHIFT)) & PUF_KEYRESET_KEY0_MASK) +#define PUF_KEYRESET_KEY1_MASK (0xCU) +#define PUF_KEYRESET_KEY1_SHIFT (2U) +#define PUF_KEYRESET_KEY1(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_KEY1_SHIFT)) & PUF_KEYRESET_KEY1_MASK) +#define PUF_KEYRESET_KEY2_MASK (0x30U) +#define PUF_KEYRESET_KEY2_SHIFT (4U) +#define PUF_KEYRESET_KEY2(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_KEY2_SHIFT)) & PUF_KEYRESET_KEY2_MASK) +#define PUF_KEYRESET_KEY3_MASK (0xC0U) +#define PUF_KEYRESET_KEY3_SHIFT (6U) +#define PUF_KEYRESET_KEY3(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_KEY3_SHIFT)) & PUF_KEYRESET_KEY3_MASK) +/*! @} */ + +/*! @name IDXBLK_L - */ +/*! @{ */ +#define PUF_IDXBLK_L_IDX0_MASK (0x3U) +#define PUF_IDXBLK_L_IDX0_SHIFT (0U) +#define PUF_IDXBLK_L_IDX0(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX0_SHIFT)) & PUF_IDXBLK_L_IDX0_MASK) +#define PUF_IDXBLK_L_IDX1_MASK (0xCU) +#define PUF_IDXBLK_L_IDX1_SHIFT (2U) +#define PUF_IDXBLK_L_IDX1(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX1_SHIFT)) & PUF_IDXBLK_L_IDX1_MASK) +#define PUF_IDXBLK_L_IDX2_MASK (0x30U) +#define PUF_IDXBLK_L_IDX2_SHIFT (4U) +#define PUF_IDXBLK_L_IDX2(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX2_SHIFT)) & PUF_IDXBLK_L_IDX2_MASK) +#define PUF_IDXBLK_L_IDX3_MASK (0xC0U) +#define PUF_IDXBLK_L_IDX3_SHIFT (6U) +#define PUF_IDXBLK_L_IDX3(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX3_SHIFT)) & PUF_IDXBLK_L_IDX3_MASK) +#define PUF_IDXBLK_L_IDX4_MASK (0x300U) +#define PUF_IDXBLK_L_IDX4_SHIFT (8U) +#define PUF_IDXBLK_L_IDX4(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX4_SHIFT)) & PUF_IDXBLK_L_IDX4_MASK) +#define PUF_IDXBLK_L_IDX5_MASK (0xC00U) +#define PUF_IDXBLK_L_IDX5_SHIFT (10U) +#define PUF_IDXBLK_L_IDX5(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX5_SHIFT)) & PUF_IDXBLK_L_IDX5_MASK) +#define PUF_IDXBLK_L_IDX6_MASK (0x3000U) +#define PUF_IDXBLK_L_IDX6_SHIFT (12U) +#define PUF_IDXBLK_L_IDX6(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX6_SHIFT)) & PUF_IDXBLK_L_IDX6_MASK) +#define PUF_IDXBLK_L_IDX7_MASK (0xC000U) +#define PUF_IDXBLK_L_IDX7_SHIFT (14U) +#define PUF_IDXBLK_L_IDX7(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX7_SHIFT)) & PUF_IDXBLK_L_IDX7_MASK) +#define PUF_IDXBLK_L_LOCK_IDX_MASK (0xC0000000U) +#define PUF_IDXBLK_L_LOCK_IDX_SHIFT (30U) +#define PUF_IDXBLK_L_LOCK_IDX(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_LOCK_IDX_SHIFT)) & PUF_IDXBLK_L_LOCK_IDX_MASK) +/*! @} */ + +/*! @name IDXBLK_H_DP - */ +/*! @{ */ +#define PUF_IDXBLK_H_DP_IDX8_MASK (0x3U) +#define PUF_IDXBLK_H_DP_IDX8_SHIFT (0U) +#define PUF_IDXBLK_H_DP_IDX8(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX8_SHIFT)) & PUF_IDXBLK_H_DP_IDX8_MASK) +#define PUF_IDXBLK_H_DP_IDX9_MASK (0xCU) +#define PUF_IDXBLK_H_DP_IDX9_SHIFT (2U) +#define PUF_IDXBLK_H_DP_IDX9(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX9_SHIFT)) & PUF_IDXBLK_H_DP_IDX9_MASK) +#define PUF_IDXBLK_H_DP_IDX10_MASK (0x30U) +#define PUF_IDXBLK_H_DP_IDX10_SHIFT (4U) +#define PUF_IDXBLK_H_DP_IDX10(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX10_SHIFT)) & PUF_IDXBLK_H_DP_IDX10_MASK) +#define PUF_IDXBLK_H_DP_IDX11_MASK (0xC0U) +#define PUF_IDXBLK_H_DP_IDX11_SHIFT (6U) +#define PUF_IDXBLK_H_DP_IDX11(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX11_SHIFT)) & PUF_IDXBLK_H_DP_IDX11_MASK) +#define PUF_IDXBLK_H_DP_IDX12_MASK (0x300U) +#define PUF_IDXBLK_H_DP_IDX12_SHIFT (8U) +#define PUF_IDXBLK_H_DP_IDX12(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX12_SHIFT)) & PUF_IDXBLK_H_DP_IDX12_MASK) +#define PUF_IDXBLK_H_DP_IDX13_MASK (0xC00U) +#define PUF_IDXBLK_H_DP_IDX13_SHIFT (10U) +#define PUF_IDXBLK_H_DP_IDX13(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX13_SHIFT)) & PUF_IDXBLK_H_DP_IDX13_MASK) +#define PUF_IDXBLK_H_DP_IDX14_MASK (0x3000U) +#define PUF_IDXBLK_H_DP_IDX14_SHIFT (12U) +#define PUF_IDXBLK_H_DP_IDX14(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX14_SHIFT)) & PUF_IDXBLK_H_DP_IDX14_MASK) +#define PUF_IDXBLK_H_DP_IDX15_MASK (0xC000U) +#define PUF_IDXBLK_H_DP_IDX15_SHIFT (14U) +#define PUF_IDXBLK_H_DP_IDX15(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX15_SHIFT)) & PUF_IDXBLK_H_DP_IDX15_MASK) +/*! @} */ + +/*! @name KEYMASK - Only reset in case of full IC reset */ +/*! @{ */ +#define PUF_KEYMASK_KEYMASK_MASK (0xFFFFFFFFU) +#define PUF_KEYMASK_KEYMASK_SHIFT (0U) +#define PUF_KEYMASK_KEYMASK(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYMASK_KEYMASK_SHIFT)) & PUF_KEYMASK_KEYMASK_MASK) +/*! @} */ + +/* The count of PUF_KEYMASK */ +#define PUF_KEYMASK_COUNT (4U) + +/*! @name IDXBLK_H - */ +/*! @{ */ +#define PUF_IDXBLK_H_IDX8_MASK (0x3U) +#define PUF_IDXBLK_H_IDX8_SHIFT (0U) +#define PUF_IDXBLK_H_IDX8(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX8_SHIFT)) & PUF_IDXBLK_H_IDX8_MASK) +#define PUF_IDXBLK_H_IDX9_MASK (0xCU) +#define PUF_IDXBLK_H_IDX9_SHIFT (2U) +#define PUF_IDXBLK_H_IDX9(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX9_SHIFT)) & PUF_IDXBLK_H_IDX9_MASK) +#define PUF_IDXBLK_H_IDX10_MASK (0x30U) +#define PUF_IDXBLK_H_IDX10_SHIFT (4U) +#define PUF_IDXBLK_H_IDX10(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX10_SHIFT)) & PUF_IDXBLK_H_IDX10_MASK) +#define PUF_IDXBLK_H_IDX11_MASK (0xC0U) +#define PUF_IDXBLK_H_IDX11_SHIFT (6U) +#define PUF_IDXBLK_H_IDX11(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX11_SHIFT)) & PUF_IDXBLK_H_IDX11_MASK) +#define PUF_IDXBLK_H_IDX12_MASK (0x300U) +#define PUF_IDXBLK_H_IDX12_SHIFT (8U) +#define PUF_IDXBLK_H_IDX12(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX12_SHIFT)) & PUF_IDXBLK_H_IDX12_MASK) +#define PUF_IDXBLK_H_IDX13_MASK (0xC00U) +#define PUF_IDXBLK_H_IDX13_SHIFT (10U) +#define PUF_IDXBLK_H_IDX13(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX13_SHIFT)) & PUF_IDXBLK_H_IDX13_MASK) +#define PUF_IDXBLK_H_IDX14_MASK (0x3000U) +#define PUF_IDXBLK_H_IDX14_SHIFT (12U) +#define PUF_IDXBLK_H_IDX14(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX14_SHIFT)) & PUF_IDXBLK_H_IDX14_MASK) +#define PUF_IDXBLK_H_IDX15_MASK (0xC000U) +#define PUF_IDXBLK_H_IDX15_SHIFT (14U) +#define PUF_IDXBLK_H_IDX15(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX15_SHIFT)) & PUF_IDXBLK_H_IDX15_MASK) +#define PUF_IDXBLK_H_LOCK_IDX_MASK (0xC0000000U) +#define PUF_IDXBLK_H_LOCK_IDX_SHIFT (30U) +#define PUF_IDXBLK_H_LOCK_IDX(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_LOCK_IDX_SHIFT)) & PUF_IDXBLK_H_LOCK_IDX_MASK) +/*! @} */ + +/*! @name IDXBLK_L_DP - */ +/*! @{ */ +#define PUF_IDXBLK_L_DP_IDX0_MASK (0x3U) +#define PUF_IDXBLK_L_DP_IDX0_SHIFT (0U) +#define PUF_IDXBLK_L_DP_IDX0(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX0_SHIFT)) & PUF_IDXBLK_L_DP_IDX0_MASK) +#define PUF_IDXBLK_L_DP_IDX1_MASK (0xCU) +#define PUF_IDXBLK_L_DP_IDX1_SHIFT (2U) +#define PUF_IDXBLK_L_DP_IDX1(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX1_SHIFT)) & PUF_IDXBLK_L_DP_IDX1_MASK) +#define PUF_IDXBLK_L_DP_IDX2_MASK (0x30U) +#define PUF_IDXBLK_L_DP_IDX2_SHIFT (4U) +#define PUF_IDXBLK_L_DP_IDX2(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX2_SHIFT)) & PUF_IDXBLK_L_DP_IDX2_MASK) +#define PUF_IDXBLK_L_DP_IDX3_MASK (0xC0U) +#define PUF_IDXBLK_L_DP_IDX3_SHIFT (6U) +#define PUF_IDXBLK_L_DP_IDX3(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX3_SHIFT)) & PUF_IDXBLK_L_DP_IDX3_MASK) +#define PUF_IDXBLK_L_DP_IDX4_MASK (0x300U) +#define PUF_IDXBLK_L_DP_IDX4_SHIFT (8U) +#define PUF_IDXBLK_L_DP_IDX4(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX4_SHIFT)) & PUF_IDXBLK_L_DP_IDX4_MASK) +#define PUF_IDXBLK_L_DP_IDX5_MASK (0xC00U) +#define PUF_IDXBLK_L_DP_IDX5_SHIFT (10U) +#define PUF_IDXBLK_L_DP_IDX5(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX5_SHIFT)) & PUF_IDXBLK_L_DP_IDX5_MASK) +#define PUF_IDXBLK_L_DP_IDX6_MASK (0x3000U) +#define PUF_IDXBLK_L_DP_IDX6_SHIFT (12U) +#define PUF_IDXBLK_L_DP_IDX6(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX6_SHIFT)) & PUF_IDXBLK_L_DP_IDX6_MASK) +#define PUF_IDXBLK_L_DP_IDX7_MASK (0xC000U) +#define PUF_IDXBLK_L_DP_IDX7_SHIFT (14U) +#define PUF_IDXBLK_L_DP_IDX7(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX7_SHIFT)) & PUF_IDXBLK_L_DP_IDX7_MASK) +/*! @} */ + +/*! @name SHIFT_STATUS - */ +/*! @{ */ +#define PUF_SHIFT_STATUS_KEY0_MASK (0xFU) +#define PUF_SHIFT_STATUS_KEY0_SHIFT (0U) +#define PUF_SHIFT_STATUS_KEY0(x) (((uint32_t)(((uint32_t)(x)) << PUF_SHIFT_STATUS_KEY0_SHIFT)) & PUF_SHIFT_STATUS_KEY0_MASK) +#define PUF_SHIFT_STATUS_KEY1_MASK (0xF0U) +#define PUF_SHIFT_STATUS_KEY1_SHIFT (4U) +#define PUF_SHIFT_STATUS_KEY1(x) (((uint32_t)(((uint32_t)(x)) << PUF_SHIFT_STATUS_KEY1_SHIFT)) & PUF_SHIFT_STATUS_KEY1_MASK) +#define PUF_SHIFT_STATUS_KEY2_MASK (0xF00U) +#define PUF_SHIFT_STATUS_KEY2_SHIFT (8U) +#define PUF_SHIFT_STATUS_KEY2(x) (((uint32_t)(((uint32_t)(x)) << PUF_SHIFT_STATUS_KEY2_SHIFT)) & PUF_SHIFT_STATUS_KEY2_MASK) +#define PUF_SHIFT_STATUS_KEY3_MASK (0xF000U) +#define PUF_SHIFT_STATUS_KEY3_SHIFT (12U) +#define PUF_SHIFT_STATUS_KEY3(x) (((uint32_t)(((uint32_t)(x)) << PUF_SHIFT_STATUS_KEY3_SHIFT)) & PUF_SHIFT_STATUS_KEY3_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group PUF_Register_Masks */ + + +/* PUF - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral PUF base address */ + #define PUF_BASE (0x5003B000u) + /** Peripheral PUF base address */ + #define PUF_BASE_NS (0x4003B000u) + /** Peripheral PUF base pointer */ + #define PUF ((PUF_Type *)PUF_BASE) + /** Peripheral PUF base pointer */ + #define PUF_NS ((PUF_Type *)PUF_BASE_NS) + /** Array initializer of PUF peripheral base addresses */ + #define PUF_BASE_ADDRS { PUF_BASE } + /** Array initializer of PUF peripheral base pointers */ + #define PUF_BASE_PTRS { PUF } + /** Array initializer of PUF peripheral base addresses */ + #define PUF_BASE_ADDRS_NS { PUF_BASE_NS } + /** Array initializer of PUF peripheral base pointers */ + #define PUF_BASE_PTRS_NS { PUF_NS } +#else + /** Peripheral PUF base address */ + #define PUF_BASE (0x4003B000u) + /** Peripheral PUF base pointer */ + #define PUF ((PUF_Type *)PUF_BASE) + /** Array initializer of PUF peripheral base addresses */ + #define PUF_BASE_ADDRS { PUF_BASE } + /** Array initializer of PUF peripheral base pointers */ + #define PUF_BASE_PTRS { PUF } +#endif +/** Interrupt vectors for the PUF peripheral type */ +#define PUF_IRQS { PUF_IRQn } + +/*! + * @} + */ /* end of group PUF_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- RNG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RNG_Peripheral_Access_Layer RNG Peripheral Access Layer + * @{ + */ + +/** RNG - Register Layout Typedef */ +typedef struct { + __I uint32_t RANDOM_NUMBER; /**< This register contains a random 32 bit number which is computed on demand, at each time it is read, offset: 0x0 */ + __I uint32_t ENCRYPTED_NUMBER; /**< This register contains a random 32 bit number which is pre-computed, offset: 0x4 */ + __I uint32_t COUNTER_VAL; /**< , offset: 0x8 */ + __IO uint32_t COUNTER_CFG; /**< , offset: 0xC */ + __IO uint32_t ONLINE_TEST_CFG; /**< , offset: 0x10 */ + __I uint32_t ONLINE_TEST_VAL; /**< , offset: 0x14 */ + __IO uint32_t MISC_CFG; /**< , offset: 0x18 */ + uint8_t RESERVED_0[4056]; + __IO uint32_t POWERDOWN; /**< Powerdown mode (standard but certainly useless here), offset: 0xFF4 */ + uint8_t RESERVED_1[4]; + __I uint32_t MODULEID; /**< IP identifier, offset: 0xFFC */ +} RNG_Type; + +/* ---------------------------------------------------------------------------- + -- RNG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RNG_Register_Masks RNG Register Masks + * @{ + */ + +/*! @name RANDOM_NUMBER - This register contains a random 32 bit number which is computed on demand, at each time it is read */ +/*! @{ */ +#define RNG_RANDOM_NUMBER_RANDOM_NUMBER_MASK (0xFFFFFFFFU) +#define RNG_RANDOM_NUMBER_RANDOM_NUMBER_SHIFT (0U) +#define RNG_RANDOM_NUMBER_RANDOM_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << RNG_RANDOM_NUMBER_RANDOM_NUMBER_SHIFT)) & RNG_RANDOM_NUMBER_RANDOM_NUMBER_MASK) +/*! @} */ + +/*! @name ENCRYPTED_NUMBER - This register contains a random 32 bit number which is pre-computed */ +/*! @{ */ +#define RNG_ENCRYPTED_NUMBER_ENCRYPTED_NUMBER_MASK (0xFFFFFFFFU) +#define RNG_ENCRYPTED_NUMBER_ENCRYPTED_NUMBER_SHIFT (0U) +#define RNG_ENCRYPTED_NUMBER_ENCRYPTED_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << RNG_ENCRYPTED_NUMBER_ENCRYPTED_NUMBER_SHIFT)) & RNG_ENCRYPTED_NUMBER_ENCRYPTED_NUMBER_MASK) +/*! @} */ + +/*! @name COUNTER_VAL - */ +/*! @{ */ +#define RNG_COUNTER_VAL_CLK_RATIO_MASK (0xFFU) +#define RNG_COUNTER_VAL_CLK_RATIO_SHIFT (0U) +#define RNG_COUNTER_VAL_CLK_RATIO(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_VAL_CLK_RATIO_SHIFT)) & RNG_COUNTER_VAL_CLK_RATIO_MASK) +#define RNG_COUNTER_VAL_REFRESH_CNT_MASK (0x1F00U) +#define RNG_COUNTER_VAL_REFRESH_CNT_SHIFT (8U) +#define RNG_COUNTER_VAL_REFRESH_CNT(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_VAL_REFRESH_CNT_SHIFT)) & RNG_COUNTER_VAL_REFRESH_CNT_MASK) +/*! @} */ + +/*! @name COUNTER_CFG - */ +/*! @{ */ +#define RNG_COUNTER_CFG_MODE_MASK (0x3U) +#define RNG_COUNTER_CFG_MODE_SHIFT (0U) +#define RNG_COUNTER_CFG_MODE(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_CFG_MODE_SHIFT)) & RNG_COUNTER_CFG_MODE_MASK) +#define RNG_COUNTER_CFG_CLOCK_SEL_MASK (0x1CU) +#define RNG_COUNTER_CFG_CLOCK_SEL_SHIFT (2U) +#define RNG_COUNTER_CFG_CLOCK_SEL(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_CFG_CLOCK_SEL_SHIFT)) & RNG_COUNTER_CFG_CLOCK_SEL_MASK) +#define RNG_COUNTER_CFG_SHIFT4X_MASK (0xE0U) +#define RNG_COUNTER_CFG_SHIFT4X_SHIFT (5U) +#define RNG_COUNTER_CFG_SHIFT4X(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_CFG_SHIFT4X_SHIFT)) & RNG_COUNTER_CFG_SHIFT4X_MASK) +#define RNG_COUNTER_CFG_DIS_ENH_ENTR_REFILL_MASK (0x100U) +#define RNG_COUNTER_CFG_DIS_ENH_ENTR_REFILL_SHIFT (8U) +#define RNG_COUNTER_CFG_DIS_ENH_ENTR_REFILL(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_CFG_DIS_ENH_ENTR_REFILL_SHIFT)) & RNG_COUNTER_CFG_DIS_ENH_ENTR_REFILL_MASK) +#define RNG_COUNTER_CFG_FORCE_ENTR_SPREADING_MASK (0x200U) +#define RNG_COUNTER_CFG_FORCE_ENTR_SPREADING_SHIFT (9U) +#define RNG_COUNTER_CFG_FORCE_ENTR_SPREADING(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_CFG_FORCE_ENTR_SPREADING_SHIFT)) & RNG_COUNTER_CFG_FORCE_ENTR_SPREADING_MASK) +/*! @} */ + +/*! @name ONLINE_TEST_CFG - */ +/*! @{ */ +#define RNG_ONLINE_TEST_CFG_ACTIVATE_MASK (0x1U) +#define RNG_ONLINE_TEST_CFG_ACTIVATE_SHIFT (0U) +#define RNG_ONLINE_TEST_CFG_ACTIVATE(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_CFG_ACTIVATE_SHIFT)) & RNG_ONLINE_TEST_CFG_ACTIVATE_MASK) +#define RNG_ONLINE_TEST_CFG_DATA_SEL_MASK (0x6U) +#define RNG_ONLINE_TEST_CFG_DATA_SEL_SHIFT (1U) +#define RNG_ONLINE_TEST_CFG_DATA_SEL(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_CFG_DATA_SEL_SHIFT)) & RNG_ONLINE_TEST_CFG_DATA_SEL_MASK) +/*! @} */ + +/*! @name ONLINE_TEST_VAL - */ +/*! @{ */ +#define RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED_MASK (0xFU) +#define RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED_SHIFT (0U) +#define RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED_SHIFT)) & RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED_MASK) +#define RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_MASK (0xF0U) +#define RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_SHIFT (4U) +#define RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_SHIFT)) & RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_MASK) +#define RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_MASK (0xF00U) +#define RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_SHIFT (8U) +#define RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_SHIFT)) & RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_MASK) +/*! @} */ + +/*! @name MISC_CFG - */ +/*! @{ */ +#define RNG_MISC_CFG_AES_RESEED_MASK (0x1U) +#define RNG_MISC_CFG_AES_RESEED_SHIFT (0U) +#define RNG_MISC_CFG_AES_RESEED(x) (((uint32_t)(((uint32_t)(x)) << RNG_MISC_CFG_AES_RESEED_SHIFT)) & RNG_MISC_CFG_AES_RESEED_MASK) +#define RNG_MISC_CFG_AES_DT_CFG_MASK (0x2U) +#define RNG_MISC_CFG_AES_DT_CFG_SHIFT (1U) +#define RNG_MISC_CFG_AES_DT_CFG(x) (((uint32_t)(((uint32_t)(x)) << RNG_MISC_CFG_AES_DT_CFG_SHIFT)) & RNG_MISC_CFG_AES_DT_CFG_MASK) +/*! @} */ + +/*! @name POWERDOWN - Powerdown mode (standard but certainly useless here) */ +/*! @{ */ +#define RNG_POWERDOWN_SOFT_RESET_MASK (0x1U) +#define RNG_POWERDOWN_SOFT_RESET_SHIFT (0U) +#define RNG_POWERDOWN_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << RNG_POWERDOWN_SOFT_RESET_SHIFT)) & RNG_POWERDOWN_SOFT_RESET_MASK) +#define RNG_POWERDOWN_FORCE_SOFT_RESET_MASK (0x2U) +#define RNG_POWERDOWN_FORCE_SOFT_RESET_SHIFT (1U) +#define RNG_POWERDOWN_FORCE_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << RNG_POWERDOWN_FORCE_SOFT_RESET_SHIFT)) & RNG_POWERDOWN_FORCE_SOFT_RESET_MASK) +#define RNG_POWERDOWN_POWERDOWN_MASK (0x80000000U) +#define RNG_POWERDOWN_POWERDOWN_SHIFT (31U) +#define RNG_POWERDOWN_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << RNG_POWERDOWN_POWERDOWN_SHIFT)) & RNG_POWERDOWN_POWERDOWN_MASK) +/*! @} */ + +/*! @name MODULEID - IP identifier */ +/*! @{ */ +#define RNG_MODULEID_APERTURE_MASK (0xFFU) +#define RNG_MODULEID_APERTURE_SHIFT (0U) +#define RNG_MODULEID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << RNG_MODULEID_APERTURE_SHIFT)) & RNG_MODULEID_APERTURE_MASK) +#define RNG_MODULEID_MIN_REV_MASK (0xF00U) +#define RNG_MODULEID_MIN_REV_SHIFT (8U) +#define RNG_MODULEID_MIN_REV(x) (((uint32_t)(((uint32_t)(x)) << RNG_MODULEID_MIN_REV_SHIFT)) & RNG_MODULEID_MIN_REV_MASK) +#define RNG_MODULEID_MAJ_REV_MASK (0xF000U) +#define RNG_MODULEID_MAJ_REV_SHIFT (12U) +#define RNG_MODULEID_MAJ_REV(x) (((uint32_t)(((uint32_t)(x)) << RNG_MODULEID_MAJ_REV_SHIFT)) & RNG_MODULEID_MAJ_REV_MASK) +#define RNG_MODULEID_ID_MASK (0xFFFF0000U) +#define RNG_MODULEID_ID_SHIFT (16U) +#define RNG_MODULEID_ID(x) (((uint32_t)(((uint32_t)(x)) << RNG_MODULEID_ID_SHIFT)) & RNG_MODULEID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group RNG_Register_Masks */ + + +/* RNG - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral RNG base address */ + #define RNG_BASE (0x5003A000u) + /** Peripheral RNG base address */ + #define RNG_BASE_NS (0x4003A000u) + /** Peripheral RNG base pointer */ + #define RNG ((RNG_Type *)RNG_BASE) + /** Peripheral RNG base pointer */ + #define RNG_NS ((RNG_Type *)RNG_BASE_NS) + /** Array initializer of RNG peripheral base addresses */ + #define RNG_BASE_ADDRS { RNG_BASE } + /** Array initializer of RNG peripheral base pointers */ + #define RNG_BASE_PTRS { RNG } + /** Array initializer of RNG peripheral base addresses */ + #define RNG_BASE_ADDRS_NS { RNG_BASE_NS } + /** Array initializer of RNG peripheral base pointers */ + #define RNG_BASE_PTRS_NS { RNG_NS } +#else + /** Peripheral RNG base address */ + #define RNG_BASE (0x4003A000u) + /** Peripheral RNG base pointer */ + #define RNG ((RNG_Type *)RNG_BASE) + /** Array initializer of RNG peripheral base addresses */ + #define RNG_BASE_ADDRS { RNG_BASE } + /** Array initializer of RNG peripheral base pointers */ + #define RNG_BASE_PTRS { RNG } +#endif + +/*! + * @} + */ /* end of group RNG_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- RTC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer + * @{ + */ + +/** RTC - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< RTC control register, offset: 0x0 */ + __IO uint32_t MATCH; /**< RTC match register, offset: 0x4 */ + __IO uint32_t COUNT; /**< RTC counter register, offset: 0x8 */ + __IO uint32_t WAKE; /**< High-resolution/wake-up timer control register, offset: 0xC */ + __I uint32_t SUBSEC; /**< RTC Sub-second Counter register, offset: 0x10 */ + uint8_t RESERVED_0[44]; + __IO uint32_t GPREG[8]; /**< General Purpose register, array offset: 0x40, array step: 0x4 */ +} RTC_Type; + +/* ---------------------------------------------------------------------------- + -- RTC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RTC_Register_Masks RTC Register Masks + * @{ + */ + +/*! @name CTRL - RTC control register */ +/*! @{ */ +#define RTC_CTRL_SWRESET_MASK (0x1U) +#define RTC_CTRL_SWRESET_SHIFT (0U) +/*! SWRESET - Software reset control + * 0b0..Not in reset. The RTC is not held in reset. This bit must be cleared prior to configuring or initiating any operation of the RTC. + * 0b1..In reset. The RTC is held in reset. All register bits within the RTC will be forced to their reset value + * except the OFD bit. This bit must be cleared before writing to any register in the RTC - including writes + * to set any of the other bits within this register. Do not attempt to write to any bits of this register at + * the same time that the reset bit is being cleared. + */ +#define RTC_CTRL_SWRESET(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_SWRESET_SHIFT)) & RTC_CTRL_SWRESET_MASK) +#define RTC_CTRL_ALARM1HZ_MASK (0x4U) +#define RTC_CTRL_ALARM1HZ_SHIFT (2U) +/*! ALARM1HZ - RTC 1 Hz timer alarm flag status. + * 0b0..No match. No match has occurred on the 1 Hz RTC timer. Writing a 0 has no effect. + * 0b1..Match. A match condition has occurred on the 1 Hz RTC timer. This flag generates an RTC alarm interrupt + * request RTC_ALARM which can also wake up the part from any low power mode. Writing a 1 clears this bit. + */ +#define RTC_CTRL_ALARM1HZ(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARM1HZ_SHIFT)) & RTC_CTRL_ALARM1HZ_MASK) +#define RTC_CTRL_WAKE1KHZ_MASK (0x8U) +#define RTC_CTRL_WAKE1KHZ_SHIFT (3U) +/*! WAKE1KHZ - RTC 1 kHz timer wake-up flag status. + * 0b0..Run. The RTC 1 kHz timer is running. Writing a 0 has no effect. + * 0b1..Time-out. The 1 kHz high-resolution/wake-up timer has timed out. This flag generates an RTC wake-up + * interrupt request RTC-WAKE which can also wake up the part from any low power mode. Writing a 1 clears this bit. + */ +#define RTC_CTRL_WAKE1KHZ(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKE1KHZ_SHIFT)) & RTC_CTRL_WAKE1KHZ_MASK) +#define RTC_CTRL_ALARMDPD_EN_MASK (0x10U) +#define RTC_CTRL_ALARMDPD_EN_SHIFT (4U) +/*! ALARMDPD_EN - RTC 1 Hz timer alarm enable for Deep power-down. + * 0b0..Disable. A match on the 1 Hz RTC timer will not bring the part out of Deep power-down mode. + * 0b1..Enable. A match on the 1 Hz RTC timer bring the part out of Deep power-down mode. + */ +#define RTC_CTRL_ALARMDPD_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARMDPD_EN_SHIFT)) & RTC_CTRL_ALARMDPD_EN_MASK) +#define RTC_CTRL_WAKEDPD_EN_MASK (0x20U) +#define RTC_CTRL_WAKEDPD_EN_SHIFT (5U) +/*! WAKEDPD_EN - RTC 1 kHz timer wake-up enable for Deep power-down. + * 0b0..Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode. + * 0b1..Enable. A match on the 1 kHz RTC timer bring the part out of Deep power-down mode. + */ +#define RTC_CTRL_WAKEDPD_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKEDPD_EN_SHIFT)) & RTC_CTRL_WAKEDPD_EN_MASK) +#define RTC_CTRL_RTC1KHZ_EN_MASK (0x40U) +#define RTC_CTRL_RTC1KHZ_EN_SHIFT (6U) +/*! RTC1KHZ_EN - RTC 1 kHz clock enable. This bit can be set to 0 to conserve power if the 1 kHz + * timer is not used. This bit has no effect when the RTC is disabled (bit 7 of this register is 0). + * 0b0..Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode. + * 0b1..Enable. The 1 kHz RTC timer is enabled. + */ +#define RTC_CTRL_RTC1KHZ_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC1KHZ_EN_SHIFT)) & RTC_CTRL_RTC1KHZ_EN_MASK) +#define RTC_CTRL_RTC_EN_MASK (0x80U) +#define RTC_CTRL_RTC_EN_SHIFT (7U) +/*! RTC_EN - RTC enable. + * 0b0..Disable. The RTC 1 Hz and 1 kHz clocks are shut down and the RTC operation is disabled. This bit should + * be 0 when writing to load a value in the RTC counter register. + * 0b1..Enable. The 1 Hz RTC clock is running and RTC operation is enabled. This bit must be set to initiate + * operation of the RTC. The first clock to the RTC counter occurs 1 s after this bit is set. To also enable the + * high-resolution, 1 kHz clock, set bit 6 in this register. + */ +#define RTC_CTRL_RTC_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_EN_SHIFT)) & RTC_CTRL_RTC_EN_MASK) +#define RTC_CTRL_RTC_OSC_PD_MASK (0x100U) +#define RTC_CTRL_RTC_OSC_PD_SHIFT (8U) +/*! RTC_OSC_PD - RTC oscillator power-down control. + * 0b0..See RTC_OSC_BYPASS + * 0b1..RTC oscillator is powered-down. + */ +#define RTC_CTRL_RTC_OSC_PD(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_OSC_PD_SHIFT)) & RTC_CTRL_RTC_OSC_PD_MASK) +#define RTC_CTRL_RTC_OSC_BYPASS_MASK (0x200U) +#define RTC_CTRL_RTC_OSC_BYPASS_SHIFT (9U) +/*! RTC_OSC_BYPASS - RTC oscillator bypass control. + * 0b0..The RTC Oscillator operates normally as a crystal oscillator with the crystal connected between the RTC_XTALIN and RTC_XTALOUT pins. + * 0b1..The RTC Oscillator is in bypass mode. In this mode a clock can be directly input into the RTC_XTALIN pin. + */ +#define RTC_CTRL_RTC_OSC_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_OSC_BYPASS_SHIFT)) & RTC_CTRL_RTC_OSC_BYPASS_MASK) +#define RTC_CTRL_RTC_SUBSEC_ENA_MASK (0x400U) +#define RTC_CTRL_RTC_SUBSEC_ENA_SHIFT (10U) +/*! RTC_SUBSEC_ENA - RTC Sub-second counter control. + * 0b0..The sub-second counter (if implemented) is disabled. This bit is cleared by a system-level POR or BOD + * reset as well as a by the RTC_ENA bit (bit 7 in this register). On modules not equipped with a sub-second + * counter, this bit will always read-back as a '0'. + * 0b1..The 32 KHz sub-second counter is enabled (if implemented). Counting commences on the start of the first + * one-second interval after this bit is set. Note: This bit can only be set after the RTC_ENA bit (bit 7) is + * set by a previous write operation. Note: The RTC sub-second counter must be re-enabled whenever the chip + * exits deep power-down mode. + */ +#define RTC_CTRL_RTC_SUBSEC_ENA(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_SUBSEC_ENA_SHIFT)) & RTC_CTRL_RTC_SUBSEC_ENA_MASK) +/*! @} */ + +/*! @name MATCH - RTC match register */ +/*! @{ */ +#define RTC_MATCH_MATVAL_MASK (0xFFFFFFFFU) +#define RTC_MATCH_MATVAL_SHIFT (0U) +#define RTC_MATCH_MATVAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_MATCH_MATVAL_SHIFT)) & RTC_MATCH_MATVAL_MASK) +/*! @} */ + +/*! @name COUNT - RTC counter register */ +/*! @{ */ +#define RTC_COUNT_VAL_MASK (0xFFFFFFFFU) +#define RTC_COUNT_VAL_SHIFT (0U) +#define RTC_COUNT_VAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_COUNT_VAL_SHIFT)) & RTC_COUNT_VAL_MASK) +/*! @} */ + +/*! @name WAKE - High-resolution/wake-up timer control register */ +/*! @{ */ +#define RTC_WAKE_VAL_MASK (0xFFFFU) +#define RTC_WAKE_VAL_SHIFT (0U) +#define RTC_WAKE_VAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_VAL_SHIFT)) & RTC_WAKE_VAL_MASK) +/*! @} */ + +/*! @name SUBSEC - RTC Sub-second Counter register */ +/*! @{ */ +#define RTC_SUBSEC_SUBSEC_MASK (0x7FFFU) +#define RTC_SUBSEC_SUBSEC_SHIFT (0U) +#define RTC_SUBSEC_SUBSEC(x) (((uint32_t)(((uint32_t)(x)) << RTC_SUBSEC_SUBSEC_SHIFT)) & RTC_SUBSEC_SUBSEC_MASK) +/*! @} */ + +/*! @name GPREG - General Purpose register */ +/*! @{ */ +#define RTC_GPREG_GPDATA_MASK (0xFFFFFFFFU) +#define RTC_GPREG_GPDATA_SHIFT (0U) +#define RTC_GPREG_GPDATA(x) (((uint32_t)(((uint32_t)(x)) << RTC_GPREG_GPDATA_SHIFT)) & RTC_GPREG_GPDATA_MASK) +/*! @} */ + +/* The count of RTC_GPREG */ +#define RTC_GPREG_COUNT (8U) + + +/*! + * @} + */ /* end of group RTC_Register_Masks */ + + +/* RTC - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral RTC base address */ + #define RTC_BASE (0x5002C000u) + /** Peripheral RTC base address */ + #define RTC_BASE_NS (0x4002C000u) + /** Peripheral RTC base pointer */ + #define RTC ((RTC_Type *)RTC_BASE) + /** Peripheral RTC base pointer */ + #define RTC_NS ((RTC_Type *)RTC_BASE_NS) + /** Array initializer of RTC peripheral base addresses */ + #define RTC_BASE_ADDRS { RTC_BASE } + /** Array initializer of RTC peripheral base pointers */ + #define RTC_BASE_PTRS { RTC } + /** Array initializer of RTC peripheral base addresses */ + #define RTC_BASE_ADDRS_NS { RTC_BASE_NS } + /** Array initializer of RTC peripheral base pointers */ + #define RTC_BASE_PTRS_NS { RTC_NS } +#else + /** Peripheral RTC base address */ + #define RTC_BASE (0x4002C000u) + /** Peripheral RTC base pointer */ + #define RTC ((RTC_Type *)RTC_BASE) + /** Array initializer of RTC peripheral base addresses */ + #define RTC_BASE_ADDRS { RTC_BASE } + /** Array initializer of RTC peripheral base pointers */ + #define RTC_BASE_PTRS { RTC } +#endif +/** Interrupt vectors for the RTC peripheral type */ +#define RTC_IRQS { RTC_IRQn } + +/*! + * @} + */ /* end of group RTC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SCT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SCT_Peripheral_Access_Layer SCT Peripheral Access Layer + * @{ + */ + +/** SCT - Register Layout Typedef */ +typedef struct { + __IO uint32_t CONFIG; /**< SCT configuration register, offset: 0x0 */ + __IO uint32_t CTRL; /**< SCT control register, offset: 0x4 */ + __IO uint32_t LIMIT; /**< SCT limit event select register, offset: 0x8 */ + __IO uint32_t HALT; /**< SCT halt event select register, offset: 0xC */ + __IO uint32_t STOP; /**< SCT stop event select register, offset: 0x10 */ + __IO uint32_t START; /**< SCT start event select register, offset: 0x14 */ + uint8_t RESERVED_0[40]; + __IO uint32_t COUNT; /**< SCT counter register, offset: 0x40 */ + __IO uint32_t STATE; /**< SCT state register, offset: 0x44 */ + __I uint32_t INPUT; /**< SCT input register, offset: 0x48 */ + __IO uint32_t REGMODE; /**< SCT match/capture mode register, offset: 0x4C */ + __IO uint32_t OUTPUT; /**< SCT output register, offset: 0x50 */ + __IO uint32_t OUTPUTDIRCTRL; /**< SCT output counter direction control register, offset: 0x54 */ + __IO uint32_t RES; /**< SCT conflict resolution register, offset: 0x58 */ + __IO uint32_t DMA0REQUEST; /**< SCT DMA request 0 register, offset: 0x5C */ + __IO uint32_t DMA1REQUEST; /**< SCT DMA request 1 register, offset: 0x60 */ + uint8_t RESERVED_1[140]; + __IO uint32_t EVEN; /**< SCT event interrupt enable register, offset: 0xF0 */ + __IO uint32_t EVFLAG; /**< SCT event flag register, offset: 0xF4 */ + __IO uint32_t CONEN; /**< SCT conflict interrupt enable register, offset: 0xF8 */ + __IO uint32_t CONFLAG; /**< SCT conflict flag register, offset: 0xFC */ + union { /* offset: 0x100 */ + __IO uint32_t SCTCAP[16]; /**< SCT capture register of capture channel, array offset: 0x100, array step: 0x4 */ + __IO uint32_t SCTMATCH[16]; /**< SCT match value register of match channels, array offset: 0x100, array step: 0x4 */ + }; + uint8_t RESERVED_2[192]; + union { /* offset: 0x200 */ + __IO uint32_t SCTCAPCTRL[16]; /**< SCT capture control register, array offset: 0x200, array step: 0x4 */ + __IO uint32_t SCTMATCHREL[16]; /**< SCT match reload value register, array offset: 0x200, array step: 0x4 */ + }; + uint8_t RESERVED_3[192]; + struct { /* offset: 0x300, array step: 0x8 */ + __IO uint32_t STATE; /**< SCT event state register 0, array offset: 0x300, array step: 0x8 */ + __IO uint32_t CTRL; /**< SCT event control register 0, array offset: 0x304, array step: 0x8 */ + } EVENT[16]; + uint8_t RESERVED_4[384]; + struct { /* offset: 0x500, array step: 0x8 */ + __IO uint32_t SET; /**< SCT output 0 set register, array offset: 0x500, array step: 0x8 */ + __IO uint32_t CLR; /**< SCT output 0 clear register, array offset: 0x504, array step: 0x8 */ + } OUT[10]; +} SCT_Type; + +/* ---------------------------------------------------------------------------- + -- SCT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SCT_Register_Masks SCT Register Masks + * @{ + */ + +/*! @name CONFIG - SCT configuration register */ +/*! @{ */ +#define SCT_CONFIG_UNIFY_MASK (0x1U) +#define SCT_CONFIG_UNIFY_SHIFT (0U) +/*! UNIFY - SCT operation + * 0b0..The SCT operates as two 16-bit counters named COUNTER_L and COUNTER_H. + * 0b1..The SCT operates as a unified 32-bit counter. + */ +#define SCT_CONFIG_UNIFY(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_UNIFY_SHIFT)) & SCT_CONFIG_UNIFY_MASK) +#define SCT_CONFIG_CLKMODE_MASK (0x6U) +#define SCT_CONFIG_CLKMODE_SHIFT (1U) +/*! CLKMODE - SCT clock mode + * 0b00..System Clock Mode. The system clock clocks the entire SCT module including the counter(s) and counter prescalers. + * 0b01..Sampled System Clock Mode. The system clock clocks the SCT module, but the counter and prescalers are + * only enabled to count when the designated edge is detected on the input selected by the CKSEL field. The + * minimum pulse width on the selected clock-gate input is 1 bus clock period. This mode is the + * high-performance, sampled-clock mode. + * 0b10..SCT Input Clock Mode. The input/edge selected by the CKSEL field clocks the SCT module, including the + * counters and prescalers, after first being synchronized to the system clock. The minimum pulse width on the + * clock input is 1 bus clock period. This mode is the low-power, sampled-clock mode. + * 0b11..Asynchronous Mode. The entire SCT module is clocked directly by the input/edge selected by the CKSEL + * field. In this mode, the SCT outputs are switched synchronously to the SCT input clock - not the system + * clock. The input clock rate must be at least half the system clock rate and can be the same or faster than + * the system clock. + */ +#define SCT_CONFIG_CLKMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CLKMODE_SHIFT)) & SCT_CONFIG_CLKMODE_MASK) +#define SCT_CONFIG_CKSEL_MASK (0x78U) +#define SCT_CONFIG_CKSEL_SHIFT (3U) +/*! CKSEL - SCT clock select. The specific functionality of the designated input/edge is dependent + * on the CLKMODE bit selection in this register. + * 0b0000..Rising edges on input 0. + * 0b0001..Falling edges on input 0. + * 0b0010..Rising edges on input 1. + * 0b0011..Falling edges on input 1. + * 0b0100..Rising edges on input 2. + * 0b0101..Falling edges on input 2. + * 0b0110..Rising edges on input 3. + * 0b0111..Falling edges on input 3. + */ +#define SCT_CONFIG_CKSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CKSEL_SHIFT)) & SCT_CONFIG_CKSEL_MASK) +#define SCT_CONFIG_NORELAOD_L_MASK (0x80U) +#define SCT_CONFIG_NORELAOD_L_SHIFT (7U) +#define SCT_CONFIG_NORELAOD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELAOD_L_SHIFT)) & SCT_CONFIG_NORELAOD_L_MASK) +#define SCT_CONFIG_NORELOAD_H_MASK (0x100U) +#define SCT_CONFIG_NORELOAD_H_SHIFT (8U) +#define SCT_CONFIG_NORELOAD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_H_SHIFT)) & SCT_CONFIG_NORELOAD_H_MASK) +#define SCT_CONFIG_INSYNC_MASK (0x1E00U) +#define SCT_CONFIG_INSYNC_SHIFT (9U) +#define SCT_CONFIG_INSYNC(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_INSYNC_SHIFT)) & SCT_CONFIG_INSYNC_MASK) +#define SCT_CONFIG_AUTOLIMIT_L_MASK (0x20000U) +#define SCT_CONFIG_AUTOLIMIT_L_SHIFT (17U) +#define SCT_CONFIG_AUTOLIMIT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_L_SHIFT)) & SCT_CONFIG_AUTOLIMIT_L_MASK) +#define SCT_CONFIG_AUTOLIMIT_H_MASK (0x40000U) +#define SCT_CONFIG_AUTOLIMIT_H_SHIFT (18U) +#define SCT_CONFIG_AUTOLIMIT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_H_SHIFT)) & SCT_CONFIG_AUTOLIMIT_H_MASK) +/*! @} */ + +/*! @name CTRL - SCT control register */ +/*! @{ */ +#define SCT_CTRL_DOWN_L_MASK (0x1U) +#define SCT_CTRL_DOWN_L_SHIFT (0U) +#define SCT_CTRL_DOWN_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_L_SHIFT)) & SCT_CTRL_DOWN_L_MASK) +#define SCT_CTRL_STOP_L_MASK (0x2U) +#define SCT_CTRL_STOP_L_SHIFT (1U) +#define SCT_CTRL_STOP_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_L_SHIFT)) & SCT_CTRL_STOP_L_MASK) +#define SCT_CTRL_HALT_L_MASK (0x4U) +#define SCT_CTRL_HALT_L_SHIFT (2U) +#define SCT_CTRL_HALT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_L_SHIFT)) & SCT_CTRL_HALT_L_MASK) +#define SCT_CTRL_CLRCTR_L_MASK (0x8U) +#define SCT_CTRL_CLRCTR_L_SHIFT (3U) +#define SCT_CTRL_CLRCTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_L_SHIFT)) & SCT_CTRL_CLRCTR_L_MASK) +#define SCT_CTRL_BIDIR_L_MASK (0x10U) +#define SCT_CTRL_BIDIR_L_SHIFT (4U) +/*! BIDIR_L - L or unified counter direction select + * 0b0..Up. The counter counts up to a limit condition, then is cleared to zero. + * 0b1..Up-down. The counter counts up to a limit, then counts down to a limit condition or to 0. + */ +#define SCT_CTRL_BIDIR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_L_SHIFT)) & SCT_CTRL_BIDIR_L_MASK) +#define SCT_CTRL_PRE_L_MASK (0x1FE0U) +#define SCT_CTRL_PRE_L_SHIFT (5U) +#define SCT_CTRL_PRE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_L_SHIFT)) & SCT_CTRL_PRE_L_MASK) +#define SCT_CTRL_DOWN_H_MASK (0x10000U) +#define SCT_CTRL_DOWN_H_SHIFT (16U) +#define SCT_CTRL_DOWN_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_H_SHIFT)) & SCT_CTRL_DOWN_H_MASK) +#define SCT_CTRL_STOP_H_MASK (0x20000U) +#define SCT_CTRL_STOP_H_SHIFT (17U) +#define SCT_CTRL_STOP_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_H_SHIFT)) & SCT_CTRL_STOP_H_MASK) +#define SCT_CTRL_HALT_H_MASK (0x40000U) +#define SCT_CTRL_HALT_H_SHIFT (18U) +#define SCT_CTRL_HALT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_H_SHIFT)) & SCT_CTRL_HALT_H_MASK) +#define SCT_CTRL_CLRCTR_H_MASK (0x80000U) +#define SCT_CTRL_CLRCTR_H_SHIFT (19U) +#define SCT_CTRL_CLRCTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_H_SHIFT)) & SCT_CTRL_CLRCTR_H_MASK) +#define SCT_CTRL_BIDIR_H_MASK (0x100000U) +#define SCT_CTRL_BIDIR_H_SHIFT (20U) +/*! BIDIR_H - Direction select + * 0b0..The H counter counts up to its limit condition, then is cleared to zero. + * 0b1..The H counter counts up to its limit, then counts down to a limit condition or to 0. + */ +#define SCT_CTRL_BIDIR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_H_SHIFT)) & SCT_CTRL_BIDIR_H_MASK) +#define SCT_CTRL_PRE_H_MASK (0x1FE00000U) +#define SCT_CTRL_PRE_H_SHIFT (21U) +#define SCT_CTRL_PRE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_H_SHIFT)) & SCT_CTRL_PRE_H_MASK) +/*! @} */ + +/*! @name LIMIT - SCT limit event select register */ +/*! @{ */ +#define SCT_LIMIT_LIMMSK_L_MASK (0xFFFFU) +#define SCT_LIMIT_LIMMSK_L_SHIFT (0U) +#define SCT_LIMIT_LIMMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_L_SHIFT)) & SCT_LIMIT_LIMMSK_L_MASK) +#define SCT_LIMIT_LIMMSK_H_MASK (0xFFFF0000U) +#define SCT_LIMIT_LIMMSK_H_SHIFT (16U) +#define SCT_LIMIT_LIMMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_H_SHIFT)) & SCT_LIMIT_LIMMSK_H_MASK) +/*! @} */ + +/*! @name HALT - SCT halt event select register */ +/*! @{ */ +#define SCT_HALT_HALTMSK_L_MASK (0xFFFFU) +#define SCT_HALT_HALTMSK_L_SHIFT (0U) +#define SCT_HALT_HALTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_L_SHIFT)) & SCT_HALT_HALTMSK_L_MASK) +#define SCT_HALT_HALTMSK_H_MASK (0xFFFF0000U) +#define SCT_HALT_HALTMSK_H_SHIFT (16U) +#define SCT_HALT_HALTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_H_SHIFT)) & SCT_HALT_HALTMSK_H_MASK) +/*! @} */ + +/*! @name STOP - SCT stop event select register */ +/*! @{ */ +#define SCT_STOP_STOPMSK_L_MASK (0xFFFFU) +#define SCT_STOP_STOPMSK_L_SHIFT (0U) +#define SCT_STOP_STOPMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_L_SHIFT)) & SCT_STOP_STOPMSK_L_MASK) +#define SCT_STOP_STOPMSK_H_MASK (0xFFFF0000U) +#define SCT_STOP_STOPMSK_H_SHIFT (16U) +#define SCT_STOP_STOPMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_H_SHIFT)) & SCT_STOP_STOPMSK_H_MASK) +/*! @} */ + +/*! @name START - SCT start event select register */ +/*! @{ */ +#define SCT_START_STARTMSK_L_MASK (0xFFFFU) +#define SCT_START_STARTMSK_L_SHIFT (0U) +#define SCT_START_STARTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_L_SHIFT)) & SCT_START_STARTMSK_L_MASK) +#define SCT_START_STARTMSK_H_MASK (0xFFFF0000U) +#define SCT_START_STARTMSK_H_SHIFT (16U) +#define SCT_START_STARTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_H_SHIFT)) & SCT_START_STARTMSK_H_MASK) +/*! @} */ + +/*! @name COUNT - SCT counter register */ +/*! @{ */ +#define SCT_COUNT_CTR_L_MASK (0xFFFFU) +#define SCT_COUNT_CTR_L_SHIFT (0U) +#define SCT_COUNT_CTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_L_SHIFT)) & SCT_COUNT_CTR_L_MASK) +#define SCT_COUNT_CTR_H_MASK (0xFFFF0000U) +#define SCT_COUNT_CTR_H_SHIFT (16U) +#define SCT_COUNT_CTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_H_SHIFT)) & SCT_COUNT_CTR_H_MASK) +/*! @} */ + +/*! @name STATE - SCT state register */ +/*! @{ */ +#define SCT_STATE_STATE_L_MASK (0x1FU) +#define SCT_STATE_STATE_L_SHIFT (0U) +#define SCT_STATE_STATE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_L_SHIFT)) & SCT_STATE_STATE_L_MASK) +#define SCT_STATE_STATE_H_MASK (0x1F0000U) +#define SCT_STATE_STATE_H_SHIFT (16U) +#define SCT_STATE_STATE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_H_SHIFT)) & SCT_STATE_STATE_H_MASK) +/*! @} */ + +/*! @name INPUT - SCT input register */ +/*! @{ */ +#define SCT_INPUT_AIN0_MASK (0x1U) +#define SCT_INPUT_AIN0_SHIFT (0U) +#define SCT_INPUT_AIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN0_SHIFT)) & SCT_INPUT_AIN0_MASK) +#define SCT_INPUT_AIN1_MASK (0x2U) +#define SCT_INPUT_AIN1_SHIFT (1U) +#define SCT_INPUT_AIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN1_SHIFT)) & SCT_INPUT_AIN1_MASK) +#define SCT_INPUT_AIN2_MASK (0x4U) +#define SCT_INPUT_AIN2_SHIFT (2U) +#define SCT_INPUT_AIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN2_SHIFT)) & SCT_INPUT_AIN2_MASK) +#define SCT_INPUT_AIN3_MASK (0x8U) +#define SCT_INPUT_AIN3_SHIFT (3U) +#define SCT_INPUT_AIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN3_SHIFT)) & SCT_INPUT_AIN3_MASK) +#define SCT_INPUT_AIN4_MASK (0x10U) +#define SCT_INPUT_AIN4_SHIFT (4U) +#define SCT_INPUT_AIN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN4_SHIFT)) & SCT_INPUT_AIN4_MASK) +#define SCT_INPUT_AIN5_MASK (0x20U) +#define SCT_INPUT_AIN5_SHIFT (5U) +#define SCT_INPUT_AIN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN5_SHIFT)) & SCT_INPUT_AIN5_MASK) +#define SCT_INPUT_AIN6_MASK (0x40U) +#define SCT_INPUT_AIN6_SHIFT (6U) +#define SCT_INPUT_AIN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN6_SHIFT)) & SCT_INPUT_AIN6_MASK) +#define SCT_INPUT_AIN7_MASK (0x80U) +#define SCT_INPUT_AIN7_SHIFT (7U) +#define SCT_INPUT_AIN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN7_SHIFT)) & SCT_INPUT_AIN7_MASK) +#define SCT_INPUT_AIN8_MASK (0x100U) +#define SCT_INPUT_AIN8_SHIFT (8U) +#define SCT_INPUT_AIN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN8_SHIFT)) & SCT_INPUT_AIN8_MASK) +#define SCT_INPUT_AIN9_MASK (0x200U) +#define SCT_INPUT_AIN9_SHIFT (9U) +#define SCT_INPUT_AIN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN9_SHIFT)) & SCT_INPUT_AIN9_MASK) +#define SCT_INPUT_AIN10_MASK (0x400U) +#define SCT_INPUT_AIN10_SHIFT (10U) +#define SCT_INPUT_AIN10(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN10_SHIFT)) & SCT_INPUT_AIN10_MASK) +#define SCT_INPUT_AIN11_MASK (0x800U) +#define SCT_INPUT_AIN11_SHIFT (11U) +#define SCT_INPUT_AIN11(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN11_SHIFT)) & SCT_INPUT_AIN11_MASK) +#define SCT_INPUT_AIN12_MASK (0x1000U) +#define SCT_INPUT_AIN12_SHIFT (12U) +#define SCT_INPUT_AIN12(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN12_SHIFT)) & SCT_INPUT_AIN12_MASK) +#define SCT_INPUT_AIN13_MASK (0x2000U) +#define SCT_INPUT_AIN13_SHIFT (13U) +#define SCT_INPUT_AIN13(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN13_SHIFT)) & SCT_INPUT_AIN13_MASK) +#define SCT_INPUT_AIN14_MASK (0x4000U) +#define SCT_INPUT_AIN14_SHIFT (14U) +#define SCT_INPUT_AIN14(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN14_SHIFT)) & SCT_INPUT_AIN14_MASK) +#define SCT_INPUT_AIN15_MASK (0x8000U) +#define SCT_INPUT_AIN15_SHIFT (15U) +#define SCT_INPUT_AIN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN15_SHIFT)) & SCT_INPUT_AIN15_MASK) +#define SCT_INPUT_SIN0_MASK (0x10000U) +#define SCT_INPUT_SIN0_SHIFT (16U) +#define SCT_INPUT_SIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN0_SHIFT)) & SCT_INPUT_SIN0_MASK) +#define SCT_INPUT_SIN1_MASK (0x20000U) +#define SCT_INPUT_SIN1_SHIFT (17U) +#define SCT_INPUT_SIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN1_SHIFT)) & SCT_INPUT_SIN1_MASK) +#define SCT_INPUT_SIN2_MASK (0x40000U) +#define SCT_INPUT_SIN2_SHIFT (18U) +#define SCT_INPUT_SIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN2_SHIFT)) & SCT_INPUT_SIN2_MASK) +#define SCT_INPUT_SIN3_MASK (0x80000U) +#define SCT_INPUT_SIN3_SHIFT (19U) +#define SCT_INPUT_SIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN3_SHIFT)) & SCT_INPUT_SIN3_MASK) +#define SCT_INPUT_SIN4_MASK (0x100000U) +#define SCT_INPUT_SIN4_SHIFT (20U) +#define SCT_INPUT_SIN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN4_SHIFT)) & SCT_INPUT_SIN4_MASK) +#define SCT_INPUT_SIN5_MASK (0x200000U) +#define SCT_INPUT_SIN5_SHIFT (21U) +#define SCT_INPUT_SIN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN5_SHIFT)) & SCT_INPUT_SIN5_MASK) +#define SCT_INPUT_SIN6_MASK (0x400000U) +#define SCT_INPUT_SIN6_SHIFT (22U) +#define SCT_INPUT_SIN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN6_SHIFT)) & SCT_INPUT_SIN6_MASK) +#define SCT_INPUT_SIN7_MASK (0x800000U) +#define SCT_INPUT_SIN7_SHIFT (23U) +#define SCT_INPUT_SIN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN7_SHIFT)) & SCT_INPUT_SIN7_MASK) +#define SCT_INPUT_SIN8_MASK (0x1000000U) +#define SCT_INPUT_SIN8_SHIFT (24U) +#define SCT_INPUT_SIN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN8_SHIFT)) & SCT_INPUT_SIN8_MASK) +#define SCT_INPUT_SIN9_MASK (0x2000000U) +#define SCT_INPUT_SIN9_SHIFT (25U) +#define SCT_INPUT_SIN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN9_SHIFT)) & SCT_INPUT_SIN9_MASK) +#define SCT_INPUT_SIN10_MASK (0x4000000U) +#define SCT_INPUT_SIN10_SHIFT (26U) +#define SCT_INPUT_SIN10(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN10_SHIFT)) & SCT_INPUT_SIN10_MASK) +#define SCT_INPUT_SIN11_MASK (0x8000000U) +#define SCT_INPUT_SIN11_SHIFT (27U) +#define SCT_INPUT_SIN11(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN11_SHIFT)) & SCT_INPUT_SIN11_MASK) +#define SCT_INPUT_SIN12_MASK (0x10000000U) +#define SCT_INPUT_SIN12_SHIFT (28U) +#define SCT_INPUT_SIN12(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN12_SHIFT)) & SCT_INPUT_SIN12_MASK) +#define SCT_INPUT_SIN13_MASK (0x20000000U) +#define SCT_INPUT_SIN13_SHIFT (29U) +#define SCT_INPUT_SIN13(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN13_SHIFT)) & SCT_INPUT_SIN13_MASK) +#define SCT_INPUT_SIN14_MASK (0x40000000U) +#define SCT_INPUT_SIN14_SHIFT (30U) +#define SCT_INPUT_SIN14(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN14_SHIFT)) & SCT_INPUT_SIN14_MASK) +#define SCT_INPUT_SIN15_MASK (0x80000000U) +#define SCT_INPUT_SIN15_SHIFT (31U) +#define SCT_INPUT_SIN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN15_SHIFT)) & SCT_INPUT_SIN15_MASK) +/*! @} */ + +/*! @name REGMODE - SCT match/capture mode register */ +/*! @{ */ +#define SCT_REGMODE_REGMOD_L_MASK (0xFFFFU) +#define SCT_REGMODE_REGMOD_L_SHIFT (0U) +#define SCT_REGMODE_REGMOD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L_SHIFT)) & SCT_REGMODE_REGMOD_L_MASK) +#define SCT_REGMODE_REGMOD_H_MASK (0xFFFF0000U) +#define SCT_REGMODE_REGMOD_H_SHIFT (16U) +#define SCT_REGMODE_REGMOD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H_SHIFT)) & SCT_REGMODE_REGMOD_H_MASK) +/*! @} */ + +/*! @name OUTPUT - SCT output register */ +/*! @{ */ +#define SCT_OUTPUT_OUT_MASK (0xFFFFU) +#define SCT_OUTPUT_OUT_SHIFT (0U) +#define SCT_OUTPUT_OUT(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT_SHIFT)) & SCT_OUTPUT_OUT_MASK) +/*! @} */ + +/*! @name OUTPUTDIRCTRL - SCT output counter direction control register */ +/*! @{ */ +#define SCT_OUTPUTDIRCTRL_SETCLR0_MASK (0x3U) +#define SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT (0U) +/*! SETCLR0 - Set/clear operation on output 0. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR0(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR0_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR1_MASK (0xCU) +#define SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT (2U) +/*! SETCLR1 - Set/clear operation on output 1. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR1(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR1_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR2_MASK (0x30U) +#define SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT (4U) +/*! SETCLR2 - Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR2(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR2_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR3_MASK (0xC0U) +#define SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT (6U) +/*! SETCLR3 - Set/clear operation on output 3. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR3(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR3_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR4_MASK (0x300U) +#define SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT (8U) +/*! SETCLR4 - Set/clear operation on output 4. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR4(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR4_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR5_MASK (0xC00U) +#define SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT (10U) +/*! SETCLR5 - Set/clear operation on output 5. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR5(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR5_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR6_MASK (0x3000U) +#define SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT (12U) +/*! SETCLR6 - Set/clear operation on output 6. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR6(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR6_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR7_MASK (0xC000U) +#define SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT (14U) +/*! SETCLR7 - Set/clear operation on output 7. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR7(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR7_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR8_MASK (0x30000U) +#define SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT (16U) +/*! SETCLR8 - Set/clear operation on output 8. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR8(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR8_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR9_MASK (0xC0000U) +#define SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT (18U) +/*! SETCLR9 - Set/clear operation on output 9. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR9(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR9_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR10_MASK (0x300000U) +#define SCT_OUTPUTDIRCTRL_SETCLR10_SHIFT (20U) +/*! SETCLR10 - Set/clear operation on output 10. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR10(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR10_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR10_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR11_MASK (0xC00000U) +#define SCT_OUTPUTDIRCTRL_SETCLR11_SHIFT (22U) +/*! SETCLR11 - Set/clear operation on output 11. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR11(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR11_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR11_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR12_MASK (0x3000000U) +#define SCT_OUTPUTDIRCTRL_SETCLR12_SHIFT (24U) +/*! SETCLR12 - Set/clear operation on output 12. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR12(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR12_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR12_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR13_MASK (0xC000000U) +#define SCT_OUTPUTDIRCTRL_SETCLR13_SHIFT (26U) +/*! SETCLR13 - Set/clear operation on output 13. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR13(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR13_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR13_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR14_MASK (0x30000000U) +#define SCT_OUTPUTDIRCTRL_SETCLR14_SHIFT (28U) +/*! SETCLR14 - Set/clear operation on output 14. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR14(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR14_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR14_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR15_MASK (0xC0000000U) +#define SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT (30U) +/*! SETCLR15 - Set/clear operation on output 15. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR15(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR15_MASK) +/*! @} */ + +/*! @name RES - SCT conflict resolution register */ +/*! @{ */ +#define SCT_RES_O0RES_MASK (0x3U) +#define SCT_RES_O0RES_SHIFT (0U) +/*! O0RES - Effect of simultaneous set and clear on output 0. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR0 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR0 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O0RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O0RES_SHIFT)) & SCT_RES_O0RES_MASK) +#define SCT_RES_O1RES_MASK (0xCU) +#define SCT_RES_O1RES_SHIFT (2U) +/*! O1RES - Effect of simultaneous set and clear on output 1. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR1 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR1 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O1RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O1RES_SHIFT)) & SCT_RES_O1RES_MASK) +#define SCT_RES_O2RES_MASK (0x30U) +#define SCT_RES_O2RES_SHIFT (4U) +/*! O2RES - Effect of simultaneous set and clear on output 2. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR2 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output n (or set based on the SETCLR2 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O2RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O2RES_SHIFT)) & SCT_RES_O2RES_MASK) +#define SCT_RES_O3RES_MASK (0xC0U) +#define SCT_RES_O3RES_SHIFT (6U) +/*! O3RES - Effect of simultaneous set and clear on output 3. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR3 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR3 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O3RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O3RES_SHIFT)) & SCT_RES_O3RES_MASK) +#define SCT_RES_O4RES_MASK (0x300U) +#define SCT_RES_O4RES_SHIFT (8U) +/*! O4RES - Effect of simultaneous set and clear on output 4. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR4 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR4 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O4RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O4RES_SHIFT)) & SCT_RES_O4RES_MASK) +#define SCT_RES_O5RES_MASK (0xC00U) +#define SCT_RES_O5RES_SHIFT (10U) +/*! O5RES - Effect of simultaneous set and clear on output 5. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR5 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR5 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O5RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O5RES_SHIFT)) & SCT_RES_O5RES_MASK) +#define SCT_RES_O6RES_MASK (0x3000U) +#define SCT_RES_O6RES_SHIFT (12U) +/*! O6RES - Effect of simultaneous set and clear on output 6. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR6 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR6 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O6RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O6RES_SHIFT)) & SCT_RES_O6RES_MASK) +#define SCT_RES_O7RES_MASK (0xC000U) +#define SCT_RES_O7RES_SHIFT (14U) +/*! O7RES - Effect of simultaneous set and clear on output 7. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR7 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output n (or set based on the SETCLR7 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O7RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O7RES_SHIFT)) & SCT_RES_O7RES_MASK) +#define SCT_RES_O8RES_MASK (0x30000U) +#define SCT_RES_O8RES_SHIFT (16U) +/*! O8RES - Effect of simultaneous set and clear on output 8. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR8 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR8 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O8RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O8RES_SHIFT)) & SCT_RES_O8RES_MASK) +#define SCT_RES_O9RES_MASK (0xC0000U) +#define SCT_RES_O9RES_SHIFT (18U) +/*! O9RES - Effect of simultaneous set and clear on output 9. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR9 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR9 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O9RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O9RES_SHIFT)) & SCT_RES_O9RES_MASK) +#define SCT_RES_O10RES_MASK (0x300000U) +#define SCT_RES_O10RES_SHIFT (20U) +/*! O10RES - Effect of simultaneous set and clear on output 10. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR10 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR10 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O10RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O10RES_SHIFT)) & SCT_RES_O10RES_MASK) +#define SCT_RES_O11RES_MASK (0xC00000U) +#define SCT_RES_O11RES_SHIFT (22U) +/*! O11RES - Effect of simultaneous set and clear on output 11. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR11 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR11 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O11RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O11RES_SHIFT)) & SCT_RES_O11RES_MASK) +#define SCT_RES_O12RES_MASK (0x3000000U) +#define SCT_RES_O12RES_SHIFT (24U) +/*! O12RES - Effect of simultaneous set and clear on output 12. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR12 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR12 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O12RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O12RES_SHIFT)) & SCT_RES_O12RES_MASK) +#define SCT_RES_O13RES_MASK (0xC000000U) +#define SCT_RES_O13RES_SHIFT (26U) +/*! O13RES - Effect of simultaneous set and clear on output 13. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR13 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR13 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O13RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O13RES_SHIFT)) & SCT_RES_O13RES_MASK) +#define SCT_RES_O14RES_MASK (0x30000000U) +#define SCT_RES_O14RES_SHIFT (28U) +/*! O14RES - Effect of simultaneous set and clear on output 14. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR14 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR14 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O14RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O14RES_SHIFT)) & SCT_RES_O14RES_MASK) +#define SCT_RES_O15RES_MASK (0xC0000000U) +#define SCT_RES_O15RES_SHIFT (30U) +/*! O15RES - Effect of simultaneous set and clear on output 15. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR15 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR15 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O15RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O15RES_SHIFT)) & SCT_RES_O15RES_MASK) +/*! @} */ + +/*! @name DMA0REQUEST - SCT DMA request 0 register */ +/*! @{ */ +#define SCT_DMA0REQUEST_DEV_0_MASK (0xFFFFU) +#define SCT_DMA0REQUEST_DEV_0_SHIFT (0U) +#define SCT_DMA0REQUEST_DEV_0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA0REQUEST_DEV_0_SHIFT)) & SCT_DMA0REQUEST_DEV_0_MASK) +#define SCT_DMA0REQUEST_DRL0_MASK (0x40000000U) +#define SCT_DMA0REQUEST_DRL0_SHIFT (30U) +#define SCT_DMA0REQUEST_DRL0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA0REQUEST_DRL0_SHIFT)) & SCT_DMA0REQUEST_DRL0_MASK) +#define SCT_DMA0REQUEST_DRQ0_MASK (0x80000000U) +#define SCT_DMA0REQUEST_DRQ0_SHIFT (31U) +#define SCT_DMA0REQUEST_DRQ0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA0REQUEST_DRQ0_SHIFT)) & SCT_DMA0REQUEST_DRQ0_MASK) +/*! @} */ + +/*! @name DMA1REQUEST - SCT DMA request 1 register */ +/*! @{ */ +#define SCT_DMA1REQUEST_DEV_1_MASK (0xFFFFU) +#define SCT_DMA1REQUEST_DEV_1_SHIFT (0U) +#define SCT_DMA1REQUEST_DEV_1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA1REQUEST_DEV_1_SHIFT)) & SCT_DMA1REQUEST_DEV_1_MASK) +#define SCT_DMA1REQUEST_DRL1_MASK (0x40000000U) +#define SCT_DMA1REQUEST_DRL1_SHIFT (30U) +#define SCT_DMA1REQUEST_DRL1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA1REQUEST_DRL1_SHIFT)) & SCT_DMA1REQUEST_DRL1_MASK) +#define SCT_DMA1REQUEST_DRQ1_MASK (0x80000000U) +#define SCT_DMA1REQUEST_DRQ1_SHIFT (31U) +#define SCT_DMA1REQUEST_DRQ1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA1REQUEST_DRQ1_SHIFT)) & SCT_DMA1REQUEST_DRQ1_MASK) +/*! @} */ + +/*! @name EVEN - SCT event interrupt enable register */ +/*! @{ */ +#define SCT_EVEN_IEN_MASK (0xFFFFU) +#define SCT_EVEN_IEN_SHIFT (0U) +#define SCT_EVEN_IEN(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN_SHIFT)) & SCT_EVEN_IEN_MASK) +/*! @} */ + +/*! @name EVFLAG - SCT event flag register */ +/*! @{ */ +#define SCT_EVFLAG_FLAG_MASK (0xFFFFU) +#define SCT_EVFLAG_FLAG_SHIFT (0U) +#define SCT_EVFLAG_FLAG(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG_SHIFT)) & SCT_EVFLAG_FLAG_MASK) +/*! @} */ + +/*! @name CONEN - SCT conflict interrupt enable register */ +/*! @{ */ +#define SCT_CONEN_NCEN_MASK (0xFFFFU) +#define SCT_CONEN_NCEN_SHIFT (0U) +#define SCT_CONEN_NCEN(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN_SHIFT)) & SCT_CONEN_NCEN_MASK) +/*! @} */ + +/*! @name CONFLAG - SCT conflict flag register */ +/*! @{ */ +#define SCT_CONFLAG_NCFLAG_MASK (0xFFFFU) +#define SCT_CONFLAG_NCFLAG_SHIFT (0U) +#define SCT_CONFLAG_NCFLAG(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG_SHIFT)) & SCT_CONFLAG_NCFLAG_MASK) +#define SCT_CONFLAG_BUSERRL_MASK (0x40000000U) +#define SCT_CONFLAG_BUSERRL_SHIFT (30U) +#define SCT_CONFLAG_BUSERRL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRL_SHIFT)) & SCT_CONFLAG_BUSERRL_MASK) +#define SCT_CONFLAG_BUSERRH_MASK (0x80000000U) +#define SCT_CONFLAG_BUSERRH_SHIFT (31U) +#define SCT_CONFLAG_BUSERRH(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRH_SHIFT)) & SCT_CONFLAG_BUSERRH_MASK) +/*! @} */ + +/*! @name SCTCAP - SCT capture register of capture channel */ +/*! @{ */ +#define SCT_SCTCAP_CAPn_L_MASK (0xFFFFU) +#define SCT_SCTCAP_CAPn_L_SHIFT (0U) +#define SCT_SCTCAP_CAPn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAP_CAPn_L_SHIFT)) & SCT_SCTCAP_CAPn_L_MASK) +#define SCT_SCTCAP_CAPn_H_MASK (0xFFFF0000U) +#define SCT_SCTCAP_CAPn_H_SHIFT (16U) +#define SCT_SCTCAP_CAPn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAP_CAPn_H_SHIFT)) & SCT_SCTCAP_CAPn_H_MASK) +/*! @} */ + +/* The count of SCT_SCTCAP */ +#define SCT_SCTCAP_COUNT (16U) + +/*! @name SCTMATCH - SCT match value register of match channels */ +/*! @{ */ +#define SCT_SCTMATCH_MATCHn_L_MASK (0xFFFFU) +#define SCT_SCTMATCH_MATCHn_L_SHIFT (0U) +#define SCT_SCTMATCH_MATCHn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCH_MATCHn_L_SHIFT)) & SCT_SCTMATCH_MATCHn_L_MASK) +#define SCT_SCTMATCH_MATCHn_H_MASK (0xFFFF0000U) +#define SCT_SCTMATCH_MATCHn_H_SHIFT (16U) +#define SCT_SCTMATCH_MATCHn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCH_MATCHn_H_SHIFT)) & SCT_SCTMATCH_MATCHn_H_MASK) +/*! @} */ + +/* The count of SCT_SCTMATCH */ +#define SCT_SCTMATCH_COUNT (16U) + +/*! @name SCTCAPCTRL - SCT capture control register */ +/*! @{ */ +#define SCT_SCTCAPCTRL_CAPCONn_L_MASK (0xFFFFU) +#define SCT_SCTCAPCTRL_CAPCONn_L_SHIFT (0U) +#define SCT_SCTCAPCTRL_CAPCONn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAPCTRL_CAPCONn_L_SHIFT)) & SCT_SCTCAPCTRL_CAPCONn_L_MASK) +#define SCT_SCTCAPCTRL_CAPCONn_H_MASK (0xFFFF0000U) +#define SCT_SCTCAPCTRL_CAPCONn_H_SHIFT (16U) +#define SCT_SCTCAPCTRL_CAPCONn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAPCTRL_CAPCONn_H_SHIFT)) & SCT_SCTCAPCTRL_CAPCONn_H_MASK) +/*! @} */ + +/* The count of SCT_SCTCAPCTRL */ +#define SCT_SCTCAPCTRL_COUNT (16U) + +/*! @name SCTMATCHREL - SCT match reload value register */ +/*! @{ */ +#define SCT_SCTMATCHREL_RELOADn_L_MASK (0xFFFFU) +#define SCT_SCTMATCHREL_RELOADn_L_SHIFT (0U) +#define SCT_SCTMATCHREL_RELOADn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCHREL_RELOADn_L_SHIFT)) & SCT_SCTMATCHREL_RELOADn_L_MASK) +#define SCT_SCTMATCHREL_RELOADn_H_MASK (0xFFFF0000U) +#define SCT_SCTMATCHREL_RELOADn_H_SHIFT (16U) +#define SCT_SCTMATCHREL_RELOADn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCHREL_RELOADn_H_SHIFT)) & SCT_SCTMATCHREL_RELOADn_H_MASK) +/*! @} */ + +/* The count of SCT_SCTMATCHREL */ +#define SCT_SCTMATCHREL_COUNT (16U) + +/*! @name EVENT_STATE - SCT event state register 0 */ +/*! @{ */ +#define SCT_EVENT_STATE_STATEMSKn_MASK (0xFFFFU) +#define SCT_EVENT_STATE_STATEMSKn_SHIFT (0U) +#define SCT_EVENT_STATE_STATEMSKn(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_STATE_STATEMSKn_SHIFT)) & SCT_EVENT_STATE_STATEMSKn_MASK) +/*! @} */ + +/* The count of SCT_EVENT_STATE */ +#define SCT_EVENT_STATE_COUNT (16U) + +/*! @name EVENT_CTRL - SCT event control register 0 */ +/*! @{ */ +#define SCT_EVENT_CTRL_MATCHSEL_MASK (0xFU) +#define SCT_EVENT_CTRL_MATCHSEL_SHIFT (0U) +#define SCT_EVENT_CTRL_MATCHSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_MATCHSEL_SHIFT)) & SCT_EVENT_CTRL_MATCHSEL_MASK) +#define SCT_EVENT_CTRL_HEVENT_MASK (0x10U) +#define SCT_EVENT_CTRL_HEVENT_SHIFT (4U) +/*! HEVENT - Select L/H counter. Do not set this bit if UNIFY = 1. + * 0b0..Selects the L state and the L match register selected by MATCHSEL. + * 0b1..Selects the H state and the H match register selected by MATCHSEL. + */ +#define SCT_EVENT_CTRL_HEVENT(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_HEVENT_SHIFT)) & SCT_EVENT_CTRL_HEVENT_MASK) +#define SCT_EVENT_CTRL_OUTSEL_MASK (0x20U) +#define SCT_EVENT_CTRL_OUTSEL_SHIFT (5U) +/*! OUTSEL - Input/output select + * 0b0..Selects the inputs selected by IOSEL. + * 0b1..Selects the outputs selected by IOSEL. + */ +#define SCT_EVENT_CTRL_OUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_OUTSEL_SHIFT)) & SCT_EVENT_CTRL_OUTSEL_MASK) +#define SCT_EVENT_CTRL_IOSEL_MASK (0x3C0U) +#define SCT_EVENT_CTRL_IOSEL_SHIFT (6U) +#define SCT_EVENT_CTRL_IOSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_IOSEL_SHIFT)) & SCT_EVENT_CTRL_IOSEL_MASK) +#define SCT_EVENT_CTRL_IOCOND_MASK (0xC00U) +#define SCT_EVENT_CTRL_IOCOND_SHIFT (10U) +/*! IOCOND - Selects the I/O condition for event n. (The detection of edges on outputs lag the + * conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state + * detection, an input must have a minimum pulse width of at least one SCT clock period . + * 0b00..LOW + * 0b01..Rise + * 0b10..Fall + * 0b11..HIGH + */ +#define SCT_EVENT_CTRL_IOCOND(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_IOCOND_SHIFT)) & SCT_EVENT_CTRL_IOCOND_MASK) +#define SCT_EVENT_CTRL_COMBMODE_MASK (0x3000U) +#define SCT_EVENT_CTRL_COMBMODE_SHIFT (12U) +/*! COMBMODE - Selects how the specified match and I/O condition are used and combined. + * 0b00..OR. The event occurs when either the specified match or I/O condition occurs. + * 0b01..MATCH. Uses the specified match only. + * 0b10..IO. Uses the specified I/O condition only. + * 0b11..AND. The event occurs when the specified match and I/O condition occur simultaneously. + */ +#define SCT_EVENT_CTRL_COMBMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_COMBMODE_SHIFT)) & SCT_EVENT_CTRL_COMBMODE_MASK) +#define SCT_EVENT_CTRL_STATELD_MASK (0x4000U) +#define SCT_EVENT_CTRL_STATELD_SHIFT (14U) +/*! STATELD - This bit controls how the STATEV value modifies the state selected by HEVENT when this + * event is the highest-numbered event occurring for that state. + * 0b0..STATEV value is added into STATE (the carry-out is ignored). + * 0b1..STATEV value is loaded into STATE. + */ +#define SCT_EVENT_CTRL_STATELD(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_STATELD_SHIFT)) & SCT_EVENT_CTRL_STATELD_MASK) +#define SCT_EVENT_CTRL_STATEV_MASK (0xF8000U) +#define SCT_EVENT_CTRL_STATEV_SHIFT (15U) +#define SCT_EVENT_CTRL_STATEV(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_STATEV_SHIFT)) & SCT_EVENT_CTRL_STATEV_MASK) +#define SCT_EVENT_CTRL_MATCHMEM_MASK (0x100000U) +#define SCT_EVENT_CTRL_MATCHMEM_SHIFT (20U) +#define SCT_EVENT_CTRL_MATCHMEM(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_MATCHMEM_SHIFT)) & SCT_EVENT_CTRL_MATCHMEM_MASK) +#define SCT_EVENT_CTRL_DIRECTION_MASK (0x600000U) +#define SCT_EVENT_CTRL_DIRECTION_SHIFT (21U) +/*! DIRECTION - Direction qualifier for event generation. This field only applies when the counters + * are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved. + * 0b00..Direction independent. This event is triggered regardless of the count direction. + * 0b01..Counting up. This event is triggered only during up-counting when BIDIR = 1. + * 0b10..Counting down. This event is triggered only during down-counting when BIDIR = 1. + */ +#define SCT_EVENT_CTRL_DIRECTION(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_DIRECTION_SHIFT)) & SCT_EVENT_CTRL_DIRECTION_MASK) +/*! @} */ + +/* The count of SCT_EVENT_CTRL */ +#define SCT_EVENT_CTRL_COUNT (16U) + +/*! @name OUT_SET - SCT output 0 set register */ +/*! @{ */ +#define SCT_OUT_SET_SET_MASK (0xFFFFU) +#define SCT_OUT_SET_SET_SHIFT (0U) +#define SCT_OUT_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_SET_SET_SHIFT)) & SCT_OUT_SET_SET_MASK) +/*! @} */ + +/* The count of SCT_OUT_SET */ +#define SCT_OUT_SET_COUNT (10U) + +/*! @name OUT_CLR - SCT output 0 clear register */ +/*! @{ */ +#define SCT_OUT_CLR_CLR_MASK (0xFFFFU) +#define SCT_OUT_CLR_CLR_SHIFT (0U) +#define SCT_OUT_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_CLR_CLR_SHIFT)) & SCT_OUT_CLR_CLR_MASK) +/*! @} */ + +/* The count of SCT_OUT_CLR */ +#define SCT_OUT_CLR_COUNT (10U) + + +/*! + * @} + */ /* end of group SCT_Register_Masks */ + + +/* SCT - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral SCT0 base address */ + #define SCT0_BASE (0x50085000u) + /** Peripheral SCT0 base address */ + #define SCT0_BASE_NS (0x40085000u) + /** Peripheral SCT0 base pointer */ + #define SCT0 ((SCT_Type *)SCT0_BASE) + /** Peripheral SCT0 base pointer */ + #define SCT0_NS ((SCT_Type *)SCT0_BASE_NS) + /** Array initializer of SCT peripheral base addresses */ + #define SCT_BASE_ADDRS { SCT0_BASE } + /** Array initializer of SCT peripheral base pointers */ + #define SCT_BASE_PTRS { SCT0 } + /** Array initializer of SCT peripheral base addresses */ + #define SCT_BASE_ADDRS_NS { SCT0_BASE_NS } + /** Array initializer of SCT peripheral base pointers */ + #define SCT_BASE_PTRS_NS { SCT0_NS } +#else + /** Peripheral SCT0 base address */ + #define SCT0_BASE (0x40085000u) + /** Peripheral SCT0 base pointer */ + #define SCT0 ((SCT_Type *)SCT0_BASE) + /** Array initializer of SCT peripheral base addresses */ + #define SCT_BASE_ADDRS { SCT0_BASE } + /** Array initializer of SCT peripheral base pointers */ + #define SCT_BASE_PTRS { SCT0 } +#endif +/** Interrupt vectors for the SCT peripheral type */ +#define SCT_IRQS { SCT0_IRQn } + +/*! + * @} + */ /* end of group SCT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SDIF Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDIF_Peripheral_Access_Layer SDIF Peripheral Access Layer + * @{ + */ + +/** SDIF - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< Control register, offset: 0x0 */ + __IO uint32_t PWREN; /**< Power Enable register, offset: 0x4 */ + __IO uint32_t CLKDIV; /**< Clock Divider register, offset: 0x8 */ + uint8_t RESERVED_0[4]; + __IO uint32_t CLKENA; /**< Clock Enable register, offset: 0x10 */ + __IO uint32_t TMOUT; /**< Time-out register, offset: 0x14 */ + __IO uint32_t CTYPE; /**< Card Type register, offset: 0x18 */ + __IO uint32_t BLKSIZ; /**< Block Size register, offset: 0x1C */ + __IO uint32_t BYTCNT; /**< Byte Count register, offset: 0x20 */ + __IO uint32_t INTMASK; /**< Interrupt Mask register, offset: 0x24 */ + __IO uint32_t CMDARG; /**< Command Argument register, offset: 0x28 */ + __IO uint32_t CMD; /**< Command register, offset: 0x2C */ + __IO uint32_t RESP[4]; /**< Response register, array offset: 0x30, array step: 0x4 */ + __IO uint32_t MINTSTS; /**< Masked Interrupt Status register, offset: 0x40 */ + __IO uint32_t RINTSTS; /**< Raw Interrupt Status register, offset: 0x44 */ + __IO uint32_t STATUS; /**< Status register, offset: 0x48 */ + __IO uint32_t FIFOTH; /**< FIFO Threshold Watermark register, offset: 0x4C */ + __IO uint32_t CDETECT; /**< Card Detect register, offset: 0x50 */ + __IO uint32_t WRTPRT; /**< Write Protect register, offset: 0x54 */ + uint8_t RESERVED_1[4]; + __IO uint32_t TCBCNT; /**< Transferred CIU Card Byte Count register, offset: 0x5C */ + __IO uint32_t TBBCNT; /**< Transferred Host to BIU-FIFO Byte Count register, offset: 0x60 */ + __IO uint32_t DEBNCE; /**< Debounce Count register, offset: 0x64 */ + uint8_t RESERVED_2[16]; + __IO uint32_t RST_N; /**< Hardware Reset, offset: 0x78 */ + uint8_t RESERVED_3[4]; + __IO uint32_t BMOD; /**< Bus Mode register, offset: 0x80 */ + __IO uint32_t PLDMND; /**< Poll Demand register, offset: 0x84 */ + __IO uint32_t DBADDR; /**< Descriptor List Base Address register, offset: 0x88 */ + __IO uint32_t IDSTS; /**< Internal DMAC Status register, offset: 0x8C */ + __IO uint32_t IDINTEN; /**< Internal DMAC Interrupt Enable register, offset: 0x90 */ + __IO uint32_t DSCADDR; /**< Current Host Descriptor Address register, offset: 0x94 */ + __IO uint32_t BUFADDR; /**< Current Buffer Descriptor Address register, offset: 0x98 */ + uint8_t RESERVED_4[100]; + __IO uint32_t CARDTHRCTL; /**< Card Threshold Control, offset: 0x100 */ + __IO uint32_t BACKENDPWR; /**< Power control, offset: 0x104 */ + uint8_t RESERVED_5[248]; + __IO uint32_t FIFO[64]; /**< SDIF FIFO, array offset: 0x200, array step: 0x4 */ +} SDIF_Type; + +/* ---------------------------------------------------------------------------- + -- SDIF Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDIF_Register_Masks SDIF Register Masks + * @{ + */ + +/*! @name CTRL - Control register */ +/*! @{ */ +#define SDIF_CTRL_CONTROLLER_RESET_MASK (0x1U) +#define SDIF_CTRL_CONTROLLER_RESET_SHIFT (0U) +#define SDIF_CTRL_CONTROLLER_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CONTROLLER_RESET_SHIFT)) & SDIF_CTRL_CONTROLLER_RESET_MASK) +#define SDIF_CTRL_FIFO_RESET_MASK (0x2U) +#define SDIF_CTRL_FIFO_RESET_SHIFT (1U) +#define SDIF_CTRL_FIFO_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_FIFO_RESET_SHIFT)) & SDIF_CTRL_FIFO_RESET_MASK) +#define SDIF_CTRL_DMA_RESET_MASK (0x4U) +#define SDIF_CTRL_DMA_RESET_SHIFT (2U) +#define SDIF_CTRL_DMA_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_DMA_RESET_SHIFT)) & SDIF_CTRL_DMA_RESET_MASK) +#define SDIF_CTRL_INT_ENABLE_MASK (0x10U) +#define SDIF_CTRL_INT_ENABLE_SHIFT (4U) +#define SDIF_CTRL_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_INT_ENABLE_SHIFT)) & SDIF_CTRL_INT_ENABLE_MASK) +#define SDIF_CTRL_READ_WAIT_MASK (0x40U) +#define SDIF_CTRL_READ_WAIT_SHIFT (6U) +#define SDIF_CTRL_READ_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_READ_WAIT_SHIFT)) & SDIF_CTRL_READ_WAIT_MASK) +#define SDIF_CTRL_SEND_IRQ_RESPONSE_MASK (0x80U) +#define SDIF_CTRL_SEND_IRQ_RESPONSE_SHIFT (7U) +#define SDIF_CTRL_SEND_IRQ_RESPONSE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_IRQ_RESPONSE_SHIFT)) & SDIF_CTRL_SEND_IRQ_RESPONSE_MASK) +#define SDIF_CTRL_ABORT_READ_DATA_MASK (0x100U) +#define SDIF_CTRL_ABORT_READ_DATA_SHIFT (8U) +#define SDIF_CTRL_ABORT_READ_DATA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_ABORT_READ_DATA_SHIFT)) & SDIF_CTRL_ABORT_READ_DATA_MASK) +#define SDIF_CTRL_SEND_CCSD_MASK (0x200U) +#define SDIF_CTRL_SEND_CCSD_SHIFT (9U) +#define SDIF_CTRL_SEND_CCSD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_CCSD_SHIFT)) & SDIF_CTRL_SEND_CCSD_MASK) +#define SDIF_CTRL_SEND_AUTO_STOP_CCSD_MASK (0x400U) +#define SDIF_CTRL_SEND_AUTO_STOP_CCSD_SHIFT (10U) +#define SDIF_CTRL_SEND_AUTO_STOP_CCSD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_AUTO_STOP_CCSD_SHIFT)) & SDIF_CTRL_SEND_AUTO_STOP_CCSD_MASK) +#define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_MASK (0x800U) +#define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_SHIFT (11U) +#define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_SHIFT)) & SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_MASK) +#define SDIF_CTRL_CARD_VOLTAGE_A0_MASK (0x10000U) +#define SDIF_CTRL_CARD_VOLTAGE_A0_SHIFT (16U) +#define SDIF_CTRL_CARD_VOLTAGE_A0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A0_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A0_MASK) +#define SDIF_CTRL_CARD_VOLTAGE_A1_MASK (0x20000U) +#define SDIF_CTRL_CARD_VOLTAGE_A1_SHIFT (17U) +#define SDIF_CTRL_CARD_VOLTAGE_A1(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A1_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A1_MASK) +#define SDIF_CTRL_CARD_VOLTAGE_A2_MASK (0x40000U) +#define SDIF_CTRL_CARD_VOLTAGE_A2_SHIFT (18U) +#define SDIF_CTRL_CARD_VOLTAGE_A2(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A2_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A2_MASK) +#define SDIF_CTRL_USE_INTERNAL_DMAC_MASK (0x2000000U) +#define SDIF_CTRL_USE_INTERNAL_DMAC_SHIFT (25U) +#define SDIF_CTRL_USE_INTERNAL_DMAC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_USE_INTERNAL_DMAC_SHIFT)) & SDIF_CTRL_USE_INTERNAL_DMAC_MASK) +/*! @} */ + +/*! @name PWREN - Power Enable register */ +/*! @{ */ +#define SDIF_PWREN_POWER_ENABLE0_MASK (0x1U) +#define SDIF_PWREN_POWER_ENABLE0_SHIFT (0U) +#define SDIF_PWREN_POWER_ENABLE0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_PWREN_POWER_ENABLE0_SHIFT)) & SDIF_PWREN_POWER_ENABLE0_MASK) +#define SDIF_PWREN_POWER_ENABLE1_MASK (0x2U) +#define SDIF_PWREN_POWER_ENABLE1_SHIFT (1U) +#define SDIF_PWREN_POWER_ENABLE1(x) (((uint32_t)(((uint32_t)(x)) << SDIF_PWREN_POWER_ENABLE1_SHIFT)) & SDIF_PWREN_POWER_ENABLE1_MASK) +/*! @} */ + +/*! @name CLKDIV - Clock Divider register */ +/*! @{ */ +#define SDIF_CLKDIV_CLK_DIVIDER0_MASK (0xFFU) +#define SDIF_CLKDIV_CLK_DIVIDER0_SHIFT (0U) +#define SDIF_CLKDIV_CLK_DIVIDER0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKDIV_CLK_DIVIDER0_SHIFT)) & SDIF_CLKDIV_CLK_DIVIDER0_MASK) +/*! @} */ + +/*! @name CLKENA - Clock Enable register */ +/*! @{ */ +#define SDIF_CLKENA_CCLK0_ENABLE_MASK (0x1U) +#define SDIF_CLKENA_CCLK0_ENABLE_SHIFT (0U) +#define SDIF_CLKENA_CCLK0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK0_ENABLE_SHIFT)) & SDIF_CLKENA_CCLK0_ENABLE_MASK) +#define SDIF_CLKENA_CCLK1_ENABLE_MASK (0x2U) +#define SDIF_CLKENA_CCLK1_ENABLE_SHIFT (1U) +#define SDIF_CLKENA_CCLK1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK1_ENABLE_SHIFT)) & SDIF_CLKENA_CCLK1_ENABLE_MASK) +#define SDIF_CLKENA_CCLK0_LOW_POWER_MASK (0x10000U) +#define SDIF_CLKENA_CCLK0_LOW_POWER_SHIFT (16U) +#define SDIF_CLKENA_CCLK0_LOW_POWER(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK0_LOW_POWER_SHIFT)) & SDIF_CLKENA_CCLK0_LOW_POWER_MASK) +#define SDIF_CLKENA_CCLK1_LOW_POWER_MASK (0x20000U) +#define SDIF_CLKENA_CCLK1_LOW_POWER_SHIFT (17U) +#define SDIF_CLKENA_CCLK1_LOW_POWER(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK1_LOW_POWER_SHIFT)) & SDIF_CLKENA_CCLK1_LOW_POWER_MASK) +/*! @} */ + +/*! @name TMOUT - Time-out register */ +/*! @{ */ +#define SDIF_TMOUT_RESPONSE_TIMEOUT_MASK (0xFFU) +#define SDIF_TMOUT_RESPONSE_TIMEOUT_SHIFT (0U) +#define SDIF_TMOUT_RESPONSE_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TMOUT_RESPONSE_TIMEOUT_SHIFT)) & SDIF_TMOUT_RESPONSE_TIMEOUT_MASK) +#define SDIF_TMOUT_DATA_TIMEOUT_MASK (0xFFFFFF00U) +#define SDIF_TMOUT_DATA_TIMEOUT_SHIFT (8U) +#define SDIF_TMOUT_DATA_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TMOUT_DATA_TIMEOUT_SHIFT)) & SDIF_TMOUT_DATA_TIMEOUT_MASK) +/*! @} */ + +/*! @name CTYPE - Card Type register */ +/*! @{ */ +#define SDIF_CTYPE_CARD0_WIDTH0_MASK (0x1U) +#define SDIF_CTYPE_CARD0_WIDTH0_SHIFT (0U) +#define SDIF_CTYPE_CARD0_WIDTH0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD0_WIDTH0_SHIFT)) & SDIF_CTYPE_CARD0_WIDTH0_MASK) +#define SDIF_CTYPE_CARD1_WIDTH0_MASK (0x2U) +#define SDIF_CTYPE_CARD1_WIDTH0_SHIFT (1U) +#define SDIF_CTYPE_CARD1_WIDTH0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD1_WIDTH0_SHIFT)) & SDIF_CTYPE_CARD1_WIDTH0_MASK) +#define SDIF_CTYPE_CARD0_WIDTH1_MASK (0x10000U) +#define SDIF_CTYPE_CARD0_WIDTH1_SHIFT (16U) +#define SDIF_CTYPE_CARD0_WIDTH1(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD0_WIDTH1_SHIFT)) & SDIF_CTYPE_CARD0_WIDTH1_MASK) +#define SDIF_CTYPE_CARD1_WIDTH1_MASK (0x20000U) +#define SDIF_CTYPE_CARD1_WIDTH1_SHIFT (17U) +#define SDIF_CTYPE_CARD1_WIDTH1(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD1_WIDTH1_SHIFT)) & SDIF_CTYPE_CARD1_WIDTH1_MASK) +/*! @} */ + +/*! @name BLKSIZ - Block Size register */ +/*! @{ */ +#define SDIF_BLKSIZ_BLOCK_SIZE_MASK (0xFFFFU) +#define SDIF_BLKSIZ_BLOCK_SIZE_SHIFT (0U) +#define SDIF_BLKSIZ_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BLKSIZ_BLOCK_SIZE_SHIFT)) & SDIF_BLKSIZ_BLOCK_SIZE_MASK) +/*! @} */ + +/*! @name BYTCNT - Byte Count register */ +/*! @{ */ +#define SDIF_BYTCNT_BYTE_COUNT_MASK (0xFFFFFFFFU) +#define SDIF_BYTCNT_BYTE_COUNT_SHIFT (0U) +#define SDIF_BYTCNT_BYTE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BYTCNT_BYTE_COUNT_SHIFT)) & SDIF_BYTCNT_BYTE_COUNT_MASK) +/*! @} */ + +/*! @name INTMASK - Interrupt Mask register */ +/*! @{ */ +#define SDIF_INTMASK_CDET_MASK (0x1U) +#define SDIF_INTMASK_CDET_SHIFT (0U) +#define SDIF_INTMASK_CDET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_CDET_SHIFT)) & SDIF_INTMASK_CDET_MASK) +#define SDIF_INTMASK_RE_MASK (0x2U) +#define SDIF_INTMASK_RE_SHIFT (1U) +#define SDIF_INTMASK_RE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RE_SHIFT)) & SDIF_INTMASK_RE_MASK) +#define SDIF_INTMASK_CDONE_MASK (0x4U) +#define SDIF_INTMASK_CDONE_SHIFT (2U) +#define SDIF_INTMASK_CDONE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_CDONE_SHIFT)) & SDIF_INTMASK_CDONE_MASK) +#define SDIF_INTMASK_DTO_MASK (0x8U) +#define SDIF_INTMASK_DTO_SHIFT (3U) +#define SDIF_INTMASK_DTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DTO_SHIFT)) & SDIF_INTMASK_DTO_MASK) +#define SDIF_INTMASK_TXDR_MASK (0x10U) +#define SDIF_INTMASK_TXDR_SHIFT (4U) +#define SDIF_INTMASK_TXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_TXDR_SHIFT)) & SDIF_INTMASK_TXDR_MASK) +#define SDIF_INTMASK_RXDR_MASK (0x20U) +#define SDIF_INTMASK_RXDR_SHIFT (5U) +#define SDIF_INTMASK_RXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RXDR_SHIFT)) & SDIF_INTMASK_RXDR_MASK) +#define SDIF_INTMASK_RCRC_MASK (0x40U) +#define SDIF_INTMASK_RCRC_SHIFT (6U) +#define SDIF_INTMASK_RCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RCRC_SHIFT)) & SDIF_INTMASK_RCRC_MASK) +#define SDIF_INTMASK_DCRC_MASK (0x80U) +#define SDIF_INTMASK_DCRC_SHIFT (7U) +#define SDIF_INTMASK_DCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DCRC_SHIFT)) & SDIF_INTMASK_DCRC_MASK) +#define SDIF_INTMASK_RTO_MASK (0x100U) +#define SDIF_INTMASK_RTO_SHIFT (8U) +#define SDIF_INTMASK_RTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RTO_SHIFT)) & SDIF_INTMASK_RTO_MASK) +#define SDIF_INTMASK_DRTO_MASK (0x200U) +#define SDIF_INTMASK_DRTO_SHIFT (9U) +#define SDIF_INTMASK_DRTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DRTO_SHIFT)) & SDIF_INTMASK_DRTO_MASK) +#define SDIF_INTMASK_HTO_MASK (0x400U) +#define SDIF_INTMASK_HTO_SHIFT (10U) +#define SDIF_INTMASK_HTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_HTO_SHIFT)) & SDIF_INTMASK_HTO_MASK) +#define SDIF_INTMASK_FRUN_MASK (0x800U) +#define SDIF_INTMASK_FRUN_SHIFT (11U) +#define SDIF_INTMASK_FRUN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_FRUN_SHIFT)) & SDIF_INTMASK_FRUN_MASK) +#define SDIF_INTMASK_HLE_MASK (0x1000U) +#define SDIF_INTMASK_HLE_SHIFT (12U) +#define SDIF_INTMASK_HLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_HLE_SHIFT)) & SDIF_INTMASK_HLE_MASK) +#define SDIF_INTMASK_SBE_MASK (0x2000U) +#define SDIF_INTMASK_SBE_SHIFT (13U) +#define SDIF_INTMASK_SBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_SBE_SHIFT)) & SDIF_INTMASK_SBE_MASK) +#define SDIF_INTMASK_ACD_MASK (0x4000U) +#define SDIF_INTMASK_ACD_SHIFT (14U) +#define SDIF_INTMASK_ACD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_ACD_SHIFT)) & SDIF_INTMASK_ACD_MASK) +#define SDIF_INTMASK_EBE_MASK (0x8000U) +#define SDIF_INTMASK_EBE_SHIFT (15U) +#define SDIF_INTMASK_EBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_EBE_SHIFT)) & SDIF_INTMASK_EBE_MASK) +#define SDIF_INTMASK_SDIO_INT_MASK_MASK (0x10000U) +#define SDIF_INTMASK_SDIO_INT_MASK_SHIFT (16U) +#define SDIF_INTMASK_SDIO_INT_MASK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_SDIO_INT_MASK_SHIFT)) & SDIF_INTMASK_SDIO_INT_MASK_MASK) +/*! @} */ + +/*! @name CMDARG - Command Argument register */ +/*! @{ */ +#define SDIF_CMDARG_CMD_ARG_MASK (0xFFFFFFFFU) +#define SDIF_CMDARG_CMD_ARG_SHIFT (0U) +#define SDIF_CMDARG_CMD_ARG(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMDARG_CMD_ARG_SHIFT)) & SDIF_CMDARG_CMD_ARG_MASK) +/*! @} */ + +/*! @name CMD - Command register */ +/*! @{ */ +#define SDIF_CMD_CMD_INDEX_MASK (0x3FU) +#define SDIF_CMD_CMD_INDEX_SHIFT (0U) +#define SDIF_CMD_CMD_INDEX(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CMD_INDEX_SHIFT)) & SDIF_CMD_CMD_INDEX_MASK) +#define SDIF_CMD_RESPONSE_EXPECT_MASK (0x40U) +#define SDIF_CMD_RESPONSE_EXPECT_SHIFT (6U) +#define SDIF_CMD_RESPONSE_EXPECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_RESPONSE_EXPECT_SHIFT)) & SDIF_CMD_RESPONSE_EXPECT_MASK) +#define SDIF_CMD_RESPONSE_LENGTH_MASK (0x80U) +#define SDIF_CMD_RESPONSE_LENGTH_SHIFT (7U) +#define SDIF_CMD_RESPONSE_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_RESPONSE_LENGTH_SHIFT)) & SDIF_CMD_RESPONSE_LENGTH_MASK) +#define SDIF_CMD_CHECK_RESPONSE_CRC_MASK (0x100U) +#define SDIF_CMD_CHECK_RESPONSE_CRC_SHIFT (8U) +#define SDIF_CMD_CHECK_RESPONSE_CRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CHECK_RESPONSE_CRC_SHIFT)) & SDIF_CMD_CHECK_RESPONSE_CRC_MASK) +#define SDIF_CMD_DATA_EXPECTED_MASK (0x200U) +#define SDIF_CMD_DATA_EXPECTED_SHIFT (9U) +#define SDIF_CMD_DATA_EXPECTED(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_DATA_EXPECTED_SHIFT)) & SDIF_CMD_DATA_EXPECTED_MASK) +#define SDIF_CMD_READ_WRITE_MASK (0x400U) +#define SDIF_CMD_READ_WRITE_SHIFT (10U) +#define SDIF_CMD_READ_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_READ_WRITE_SHIFT)) & SDIF_CMD_READ_WRITE_MASK) +#define SDIF_CMD_TRANSFER_MODE_MASK (0x800U) +#define SDIF_CMD_TRANSFER_MODE_SHIFT (11U) +#define SDIF_CMD_TRANSFER_MODE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_TRANSFER_MODE_SHIFT)) & SDIF_CMD_TRANSFER_MODE_MASK) +#define SDIF_CMD_SEND_AUTO_STOP_MASK (0x1000U) +#define SDIF_CMD_SEND_AUTO_STOP_SHIFT (12U) +#define SDIF_CMD_SEND_AUTO_STOP(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_SEND_AUTO_STOP_SHIFT)) & SDIF_CMD_SEND_AUTO_STOP_MASK) +#define SDIF_CMD_WAIT_PRVDATA_COMPLETE_MASK (0x2000U) +#define SDIF_CMD_WAIT_PRVDATA_COMPLETE_SHIFT (13U) +#define SDIF_CMD_WAIT_PRVDATA_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_WAIT_PRVDATA_COMPLETE_SHIFT)) & SDIF_CMD_WAIT_PRVDATA_COMPLETE_MASK) +#define SDIF_CMD_STOP_ABORT_CMD_MASK (0x4000U) +#define SDIF_CMD_STOP_ABORT_CMD_SHIFT (14U) +#define SDIF_CMD_STOP_ABORT_CMD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_STOP_ABORT_CMD_SHIFT)) & SDIF_CMD_STOP_ABORT_CMD_MASK) +#define SDIF_CMD_SEND_INITIALIZATION_MASK (0x8000U) +#define SDIF_CMD_SEND_INITIALIZATION_SHIFT (15U) +#define SDIF_CMD_SEND_INITIALIZATION(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_SEND_INITIALIZATION_SHIFT)) & SDIF_CMD_SEND_INITIALIZATION_MASK) +#define SDIF_CMD_CARD_NUMBER_MASK (0x1F0000U) +#define SDIF_CMD_CARD_NUMBER_SHIFT (16U) +/*! CARD_NUMBER - Specifies the card number of SDCARD for which the current Command is being executed + * 0b00000..Command will be execute on SDCARD 0 + * 0b00001..Command will be execute on SDCARD 1 + */ +#define SDIF_CMD_CARD_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CARD_NUMBER_SHIFT)) & SDIF_CMD_CARD_NUMBER_MASK) +#define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_MASK (0x200000U) +#define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_SHIFT (21U) +#define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_SHIFT)) & SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_MASK) +#define SDIF_CMD_READ_CEATA_DEVICE_MASK (0x400000U) +#define SDIF_CMD_READ_CEATA_DEVICE_SHIFT (22U) +#define SDIF_CMD_READ_CEATA_DEVICE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_READ_CEATA_DEVICE_SHIFT)) & SDIF_CMD_READ_CEATA_DEVICE_MASK) +#define SDIF_CMD_CCS_EXPECTED_MASK (0x800000U) +#define SDIF_CMD_CCS_EXPECTED_SHIFT (23U) +#define SDIF_CMD_CCS_EXPECTED(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CCS_EXPECTED_SHIFT)) & SDIF_CMD_CCS_EXPECTED_MASK) +#define SDIF_CMD_ENABLE_BOOT_MASK (0x1000000U) +#define SDIF_CMD_ENABLE_BOOT_SHIFT (24U) +#define SDIF_CMD_ENABLE_BOOT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_ENABLE_BOOT_SHIFT)) & SDIF_CMD_ENABLE_BOOT_MASK) +#define SDIF_CMD_EXPECT_BOOT_ACK_MASK (0x2000000U) +#define SDIF_CMD_EXPECT_BOOT_ACK_SHIFT (25U) +#define SDIF_CMD_EXPECT_BOOT_ACK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_EXPECT_BOOT_ACK_SHIFT)) & SDIF_CMD_EXPECT_BOOT_ACK_MASK) +#define SDIF_CMD_DISABLE_BOOT_MASK (0x4000000U) +#define SDIF_CMD_DISABLE_BOOT_SHIFT (26U) +#define SDIF_CMD_DISABLE_BOOT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_DISABLE_BOOT_SHIFT)) & SDIF_CMD_DISABLE_BOOT_MASK) +#define SDIF_CMD_BOOT_MODE_MASK (0x8000000U) +#define SDIF_CMD_BOOT_MODE_SHIFT (27U) +#define SDIF_CMD_BOOT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_BOOT_MODE_SHIFT)) & SDIF_CMD_BOOT_MODE_MASK) +#define SDIF_CMD_VOLT_SWITCH_MASK (0x10000000U) +#define SDIF_CMD_VOLT_SWITCH_SHIFT (28U) +#define SDIF_CMD_VOLT_SWITCH(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_VOLT_SWITCH_SHIFT)) & SDIF_CMD_VOLT_SWITCH_MASK) +#define SDIF_CMD_USE_HOLD_REG_MASK (0x20000000U) +#define SDIF_CMD_USE_HOLD_REG_SHIFT (29U) +#define SDIF_CMD_USE_HOLD_REG(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_USE_HOLD_REG_SHIFT)) & SDIF_CMD_USE_HOLD_REG_MASK) +#define SDIF_CMD_START_CMD_MASK (0x80000000U) +#define SDIF_CMD_START_CMD_SHIFT (31U) +#define SDIF_CMD_START_CMD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_START_CMD_SHIFT)) & SDIF_CMD_START_CMD_MASK) +/*! @} */ + +/*! @name RESP - Response register */ +/*! @{ */ +#define SDIF_RESP_RESPONSE_MASK (0xFFFFFFFFU) +#define SDIF_RESP_RESPONSE_SHIFT (0U) +#define SDIF_RESP_RESPONSE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RESP_RESPONSE_SHIFT)) & SDIF_RESP_RESPONSE_MASK) +/*! @} */ + +/* The count of SDIF_RESP */ +#define SDIF_RESP_COUNT (4U) + +/*! @name MINTSTS - Masked Interrupt Status register */ +/*! @{ */ +#define SDIF_MINTSTS_CDET_MASK (0x1U) +#define SDIF_MINTSTS_CDET_SHIFT (0U) +#define SDIF_MINTSTS_CDET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_CDET_SHIFT)) & SDIF_MINTSTS_CDET_MASK) +#define SDIF_MINTSTS_RE_MASK (0x2U) +#define SDIF_MINTSTS_RE_SHIFT (1U) +#define SDIF_MINTSTS_RE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RE_SHIFT)) & SDIF_MINTSTS_RE_MASK) +#define SDIF_MINTSTS_CDONE_MASK (0x4U) +#define SDIF_MINTSTS_CDONE_SHIFT (2U) +#define SDIF_MINTSTS_CDONE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_CDONE_SHIFT)) & SDIF_MINTSTS_CDONE_MASK) +#define SDIF_MINTSTS_DTO_MASK (0x8U) +#define SDIF_MINTSTS_DTO_SHIFT (3U) +#define SDIF_MINTSTS_DTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DTO_SHIFT)) & SDIF_MINTSTS_DTO_MASK) +#define SDIF_MINTSTS_TXDR_MASK (0x10U) +#define SDIF_MINTSTS_TXDR_SHIFT (4U) +#define SDIF_MINTSTS_TXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_TXDR_SHIFT)) & SDIF_MINTSTS_TXDR_MASK) +#define SDIF_MINTSTS_RXDR_MASK (0x20U) +#define SDIF_MINTSTS_RXDR_SHIFT (5U) +#define SDIF_MINTSTS_RXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RXDR_SHIFT)) & SDIF_MINTSTS_RXDR_MASK) +#define SDIF_MINTSTS_RCRC_MASK (0x40U) +#define SDIF_MINTSTS_RCRC_SHIFT (6U) +#define SDIF_MINTSTS_RCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RCRC_SHIFT)) & SDIF_MINTSTS_RCRC_MASK) +#define SDIF_MINTSTS_DCRC_MASK (0x80U) +#define SDIF_MINTSTS_DCRC_SHIFT (7U) +#define SDIF_MINTSTS_DCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DCRC_SHIFT)) & SDIF_MINTSTS_DCRC_MASK) +#define SDIF_MINTSTS_RTO_MASK (0x100U) +#define SDIF_MINTSTS_RTO_SHIFT (8U) +#define SDIF_MINTSTS_RTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RTO_SHIFT)) & SDIF_MINTSTS_RTO_MASK) +#define SDIF_MINTSTS_DRTO_MASK (0x200U) +#define SDIF_MINTSTS_DRTO_SHIFT (9U) +#define SDIF_MINTSTS_DRTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DRTO_SHIFT)) & SDIF_MINTSTS_DRTO_MASK) +#define SDIF_MINTSTS_HTO_MASK (0x400U) +#define SDIF_MINTSTS_HTO_SHIFT (10U) +#define SDIF_MINTSTS_HTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_HTO_SHIFT)) & SDIF_MINTSTS_HTO_MASK) +#define SDIF_MINTSTS_FRUN_MASK (0x800U) +#define SDIF_MINTSTS_FRUN_SHIFT (11U) +#define SDIF_MINTSTS_FRUN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_FRUN_SHIFT)) & SDIF_MINTSTS_FRUN_MASK) +#define SDIF_MINTSTS_HLE_MASK (0x1000U) +#define SDIF_MINTSTS_HLE_SHIFT (12U) +#define SDIF_MINTSTS_HLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_HLE_SHIFT)) & SDIF_MINTSTS_HLE_MASK) +#define SDIF_MINTSTS_SBE_MASK (0x2000U) +#define SDIF_MINTSTS_SBE_SHIFT (13U) +#define SDIF_MINTSTS_SBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_SBE_SHIFT)) & SDIF_MINTSTS_SBE_MASK) +#define SDIF_MINTSTS_ACD_MASK (0x4000U) +#define SDIF_MINTSTS_ACD_SHIFT (14U) +#define SDIF_MINTSTS_ACD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_ACD_SHIFT)) & SDIF_MINTSTS_ACD_MASK) +#define SDIF_MINTSTS_EBE_MASK (0x8000U) +#define SDIF_MINTSTS_EBE_SHIFT (15U) +#define SDIF_MINTSTS_EBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_EBE_SHIFT)) & SDIF_MINTSTS_EBE_MASK) +#define SDIF_MINTSTS_SDIO_INTERRUPT_MASK (0x10000U) +#define SDIF_MINTSTS_SDIO_INTERRUPT_SHIFT (16U) +#define SDIF_MINTSTS_SDIO_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_SDIO_INTERRUPT_SHIFT)) & SDIF_MINTSTS_SDIO_INTERRUPT_MASK) +/*! @} */ + +/*! @name RINTSTS - Raw Interrupt Status register */ +/*! @{ */ +#define SDIF_RINTSTS_CDET_MASK (0x1U) +#define SDIF_RINTSTS_CDET_SHIFT (0U) +#define SDIF_RINTSTS_CDET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_CDET_SHIFT)) & SDIF_RINTSTS_CDET_MASK) +#define SDIF_RINTSTS_RE_MASK (0x2U) +#define SDIF_RINTSTS_RE_SHIFT (1U) +#define SDIF_RINTSTS_RE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RE_SHIFT)) & SDIF_RINTSTS_RE_MASK) +#define SDIF_RINTSTS_CDONE_MASK (0x4U) +#define SDIF_RINTSTS_CDONE_SHIFT (2U) +#define SDIF_RINTSTS_CDONE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_CDONE_SHIFT)) & SDIF_RINTSTS_CDONE_MASK) +#define SDIF_RINTSTS_DTO_MASK (0x8U) +#define SDIF_RINTSTS_DTO_SHIFT (3U) +#define SDIF_RINTSTS_DTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DTO_SHIFT)) & SDIF_RINTSTS_DTO_MASK) +#define SDIF_RINTSTS_TXDR_MASK (0x10U) +#define SDIF_RINTSTS_TXDR_SHIFT (4U) +#define SDIF_RINTSTS_TXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_TXDR_SHIFT)) & SDIF_RINTSTS_TXDR_MASK) +#define SDIF_RINTSTS_RXDR_MASK (0x20U) +#define SDIF_RINTSTS_RXDR_SHIFT (5U) +#define SDIF_RINTSTS_RXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RXDR_SHIFT)) & SDIF_RINTSTS_RXDR_MASK) +#define SDIF_RINTSTS_RCRC_MASK (0x40U) +#define SDIF_RINTSTS_RCRC_SHIFT (6U) +#define SDIF_RINTSTS_RCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RCRC_SHIFT)) & SDIF_RINTSTS_RCRC_MASK) +#define SDIF_RINTSTS_DCRC_MASK (0x80U) +#define SDIF_RINTSTS_DCRC_SHIFT (7U) +#define SDIF_RINTSTS_DCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DCRC_SHIFT)) & SDIF_RINTSTS_DCRC_MASK) +#define SDIF_RINTSTS_RTO_BAR_MASK (0x100U) +#define SDIF_RINTSTS_RTO_BAR_SHIFT (8U) +#define SDIF_RINTSTS_RTO_BAR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RTO_BAR_SHIFT)) & SDIF_RINTSTS_RTO_BAR_MASK) +#define SDIF_RINTSTS_DRTO_BDS_MASK (0x200U) +#define SDIF_RINTSTS_DRTO_BDS_SHIFT (9U) +#define SDIF_RINTSTS_DRTO_BDS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DRTO_BDS_SHIFT)) & SDIF_RINTSTS_DRTO_BDS_MASK) +#define SDIF_RINTSTS_HTO_MASK (0x400U) +#define SDIF_RINTSTS_HTO_SHIFT (10U) +#define SDIF_RINTSTS_HTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_HTO_SHIFT)) & SDIF_RINTSTS_HTO_MASK) +#define SDIF_RINTSTS_FRUN_MASK (0x800U) +#define SDIF_RINTSTS_FRUN_SHIFT (11U) +#define SDIF_RINTSTS_FRUN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_FRUN_SHIFT)) & SDIF_RINTSTS_FRUN_MASK) +#define SDIF_RINTSTS_HLE_MASK (0x1000U) +#define SDIF_RINTSTS_HLE_SHIFT (12U) +#define SDIF_RINTSTS_HLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_HLE_SHIFT)) & SDIF_RINTSTS_HLE_MASK) +#define SDIF_RINTSTS_SBE_MASK (0x2000U) +#define SDIF_RINTSTS_SBE_SHIFT (13U) +#define SDIF_RINTSTS_SBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_SBE_SHIFT)) & SDIF_RINTSTS_SBE_MASK) +#define SDIF_RINTSTS_ACD_MASK (0x4000U) +#define SDIF_RINTSTS_ACD_SHIFT (14U) +#define SDIF_RINTSTS_ACD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_ACD_SHIFT)) & SDIF_RINTSTS_ACD_MASK) +#define SDIF_RINTSTS_EBE_MASK (0x8000U) +#define SDIF_RINTSTS_EBE_SHIFT (15U) +#define SDIF_RINTSTS_EBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_EBE_SHIFT)) & SDIF_RINTSTS_EBE_MASK) +#define SDIF_RINTSTS_SDIO_INTERRUPT_MASK (0x10000U) +#define SDIF_RINTSTS_SDIO_INTERRUPT_SHIFT (16U) +#define SDIF_RINTSTS_SDIO_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_SDIO_INTERRUPT_SHIFT)) & SDIF_RINTSTS_SDIO_INTERRUPT_MASK) +/*! @} */ + +/*! @name STATUS - Status register */ +/*! @{ */ +#define SDIF_STATUS_FIFO_RX_WATERMARK_MASK (0x1U) +#define SDIF_STATUS_FIFO_RX_WATERMARK_SHIFT (0U) +#define SDIF_STATUS_FIFO_RX_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_RX_WATERMARK_SHIFT)) & SDIF_STATUS_FIFO_RX_WATERMARK_MASK) +#define SDIF_STATUS_FIFO_TX_WATERMARK_MASK (0x2U) +#define SDIF_STATUS_FIFO_TX_WATERMARK_SHIFT (1U) +#define SDIF_STATUS_FIFO_TX_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_TX_WATERMARK_SHIFT)) & SDIF_STATUS_FIFO_TX_WATERMARK_MASK) +#define SDIF_STATUS_FIFO_EMPTY_MASK (0x4U) +#define SDIF_STATUS_FIFO_EMPTY_SHIFT (2U) +#define SDIF_STATUS_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_EMPTY_SHIFT)) & SDIF_STATUS_FIFO_EMPTY_MASK) +#define SDIF_STATUS_FIFO_FULL_MASK (0x8U) +#define SDIF_STATUS_FIFO_FULL_SHIFT (3U) +#define SDIF_STATUS_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_FULL_SHIFT)) & SDIF_STATUS_FIFO_FULL_MASK) +#define SDIF_STATUS_CMDFSMSTATES_MASK (0xF0U) +#define SDIF_STATUS_CMDFSMSTATES_SHIFT (4U) +#define SDIF_STATUS_CMDFSMSTATES(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_CMDFSMSTATES_SHIFT)) & SDIF_STATUS_CMDFSMSTATES_MASK) +#define SDIF_STATUS_DATA_3_STATUS_MASK (0x100U) +#define SDIF_STATUS_DATA_3_STATUS_SHIFT (8U) +#define SDIF_STATUS_DATA_3_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_3_STATUS_SHIFT)) & SDIF_STATUS_DATA_3_STATUS_MASK) +#define SDIF_STATUS_DATA_BUSY_MASK (0x200U) +#define SDIF_STATUS_DATA_BUSY_SHIFT (9U) +#define SDIF_STATUS_DATA_BUSY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_BUSY_SHIFT)) & SDIF_STATUS_DATA_BUSY_MASK) +#define SDIF_STATUS_DATA_STATE_MC_BUSY_MASK (0x400U) +#define SDIF_STATUS_DATA_STATE_MC_BUSY_SHIFT (10U) +#define SDIF_STATUS_DATA_STATE_MC_BUSY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_STATE_MC_BUSY_SHIFT)) & SDIF_STATUS_DATA_STATE_MC_BUSY_MASK) +#define SDIF_STATUS_RESPONSE_INDEX_MASK (0x1F800U) +#define SDIF_STATUS_RESPONSE_INDEX_SHIFT (11U) +#define SDIF_STATUS_RESPONSE_INDEX(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_RESPONSE_INDEX_SHIFT)) & SDIF_STATUS_RESPONSE_INDEX_MASK) +#define SDIF_STATUS_FIFO_COUNT_MASK (0x3FFE0000U) +#define SDIF_STATUS_FIFO_COUNT_SHIFT (17U) +#define SDIF_STATUS_FIFO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_COUNT_SHIFT)) & SDIF_STATUS_FIFO_COUNT_MASK) +#define SDIF_STATUS_DMA_ACK_MASK (0x40000000U) +#define SDIF_STATUS_DMA_ACK_SHIFT (30U) +#define SDIF_STATUS_DMA_ACK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DMA_ACK_SHIFT)) & SDIF_STATUS_DMA_ACK_MASK) +#define SDIF_STATUS_DMA_REQ_MASK (0x80000000U) +#define SDIF_STATUS_DMA_REQ_SHIFT (31U) +#define SDIF_STATUS_DMA_REQ(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DMA_REQ_SHIFT)) & SDIF_STATUS_DMA_REQ_MASK) +/*! @} */ + +/*! @name FIFOTH - FIFO Threshold Watermark register */ +/*! @{ */ +#define SDIF_FIFOTH_TX_WMARK_MASK (0xFFFU) +#define SDIF_FIFOTH_TX_WMARK_SHIFT (0U) +#define SDIF_FIFOTH_TX_WMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_TX_WMARK_SHIFT)) & SDIF_FIFOTH_TX_WMARK_MASK) +#define SDIF_FIFOTH_RX_WMARK_MASK (0xFFF0000U) +#define SDIF_FIFOTH_RX_WMARK_SHIFT (16U) +#define SDIF_FIFOTH_RX_WMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_RX_WMARK_SHIFT)) & SDIF_FIFOTH_RX_WMARK_MASK) +#define SDIF_FIFOTH_DMA_MTS_MASK (0x70000000U) +#define SDIF_FIFOTH_DMA_MTS_SHIFT (28U) +#define SDIF_FIFOTH_DMA_MTS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_DMA_MTS_SHIFT)) & SDIF_FIFOTH_DMA_MTS_MASK) +/*! @} */ + +/*! @name CDETECT - Card Detect register */ +/*! @{ */ +#define SDIF_CDETECT_CARD0_DETECT_MASK (0x1U) +#define SDIF_CDETECT_CARD0_DETECT_SHIFT (0U) +#define SDIF_CDETECT_CARD0_DETECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CDETECT_CARD0_DETECT_SHIFT)) & SDIF_CDETECT_CARD0_DETECT_MASK) +#define SDIF_CDETECT_CARD1_DETECT_MASK (0x2U) +#define SDIF_CDETECT_CARD1_DETECT_SHIFT (1U) +#define SDIF_CDETECT_CARD1_DETECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CDETECT_CARD1_DETECT_SHIFT)) & SDIF_CDETECT_CARD1_DETECT_MASK) +/*! @} */ + +/*! @name WRTPRT - Write Protect register */ +/*! @{ */ +#define SDIF_WRTPRT_WRITE_PROTECT_MASK (0x1U) +#define SDIF_WRTPRT_WRITE_PROTECT_SHIFT (0U) +#define SDIF_WRTPRT_WRITE_PROTECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_WRTPRT_WRITE_PROTECT_SHIFT)) & SDIF_WRTPRT_WRITE_PROTECT_MASK) +/*! @} */ + +/*! @name TCBCNT - Transferred CIU Card Byte Count register */ +/*! @{ */ +#define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_MASK (0xFFFFFFFFU) +#define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_SHIFT (0U) +#define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_SHIFT)) & SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_MASK) +/*! @} */ + +/*! @name TBBCNT - Transferred Host to BIU-FIFO Byte Count register */ +/*! @{ */ +#define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_MASK (0xFFFFFFFFU) +#define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_SHIFT (0U) +#define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_SHIFT)) & SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_MASK) +/*! @} */ + +/*! @name DEBNCE - Debounce Count register */ +/*! @{ */ +#define SDIF_DEBNCE_DEBOUNCE_COUNT_MASK (0xFFFFFFU) +#define SDIF_DEBNCE_DEBOUNCE_COUNT_SHIFT (0U) +#define SDIF_DEBNCE_DEBOUNCE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_DEBNCE_DEBOUNCE_COUNT_SHIFT)) & SDIF_DEBNCE_DEBOUNCE_COUNT_MASK) +/*! @} */ + +/*! @name RST_N - Hardware Reset */ +/*! @{ */ +#define SDIF_RST_N_CARD_RESET_MASK (0x1U) +#define SDIF_RST_N_CARD_RESET_SHIFT (0U) +#define SDIF_RST_N_CARD_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RST_N_CARD_RESET_SHIFT)) & SDIF_RST_N_CARD_RESET_MASK) +/*! @} */ + +/*! @name BMOD - Bus Mode register */ +/*! @{ */ +#define SDIF_BMOD_SWR_MASK (0x1U) +#define SDIF_BMOD_SWR_SHIFT (0U) +#define SDIF_BMOD_SWR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_SWR_SHIFT)) & SDIF_BMOD_SWR_MASK) +#define SDIF_BMOD_FB_MASK (0x2U) +#define SDIF_BMOD_FB_SHIFT (1U) +#define SDIF_BMOD_FB(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_FB_SHIFT)) & SDIF_BMOD_FB_MASK) +#define SDIF_BMOD_DSL_MASK (0x7CU) +#define SDIF_BMOD_DSL_SHIFT (2U) +#define SDIF_BMOD_DSL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_DSL_SHIFT)) & SDIF_BMOD_DSL_MASK) +#define SDIF_BMOD_DE_MASK (0x80U) +#define SDIF_BMOD_DE_SHIFT (7U) +#define SDIF_BMOD_DE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_DE_SHIFT)) & SDIF_BMOD_DE_MASK) +#define SDIF_BMOD_PBL_MASK (0x700U) +#define SDIF_BMOD_PBL_SHIFT (8U) +#define SDIF_BMOD_PBL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_PBL_SHIFT)) & SDIF_BMOD_PBL_MASK) +/*! @} */ + +/*! @name PLDMND - Poll Demand register */ +/*! @{ */ +#define SDIF_PLDMND_PD_MASK (0xFFFFFFFFU) +#define SDIF_PLDMND_PD_SHIFT (0U) +#define SDIF_PLDMND_PD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_PLDMND_PD_SHIFT)) & SDIF_PLDMND_PD_MASK) +/*! @} */ + +/*! @name DBADDR - Descriptor List Base Address register */ +/*! @{ */ +#define SDIF_DBADDR_SDL_MASK (0xFFFFFFFFU) +#define SDIF_DBADDR_SDL_SHIFT (0U) +#define SDIF_DBADDR_SDL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_DBADDR_SDL_SHIFT)) & SDIF_DBADDR_SDL_MASK) +/*! @} */ + +/*! @name IDSTS - Internal DMAC Status register */ +/*! @{ */ +#define SDIF_IDSTS_TI_MASK (0x1U) +#define SDIF_IDSTS_TI_SHIFT (0U) +#define SDIF_IDSTS_TI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_TI_SHIFT)) & SDIF_IDSTS_TI_MASK) +#define SDIF_IDSTS_RI_MASK (0x2U) +#define SDIF_IDSTS_RI_SHIFT (1U) +#define SDIF_IDSTS_RI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_RI_SHIFT)) & SDIF_IDSTS_RI_MASK) +#define SDIF_IDSTS_FBE_MASK (0x4U) +#define SDIF_IDSTS_FBE_SHIFT (2U) +#define SDIF_IDSTS_FBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_FBE_SHIFT)) & SDIF_IDSTS_FBE_MASK) +#define SDIF_IDSTS_DU_MASK (0x10U) +#define SDIF_IDSTS_DU_SHIFT (4U) +#define SDIF_IDSTS_DU(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_DU_SHIFT)) & SDIF_IDSTS_DU_MASK) +#define SDIF_IDSTS_CES_MASK (0x20U) +#define SDIF_IDSTS_CES_SHIFT (5U) +#define SDIF_IDSTS_CES(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_CES_SHIFT)) & SDIF_IDSTS_CES_MASK) +#define SDIF_IDSTS_NIS_MASK (0x100U) +#define SDIF_IDSTS_NIS_SHIFT (8U) +#define SDIF_IDSTS_NIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_NIS_SHIFT)) & SDIF_IDSTS_NIS_MASK) +#define SDIF_IDSTS_AIS_MASK (0x200U) +#define SDIF_IDSTS_AIS_SHIFT (9U) +#define SDIF_IDSTS_AIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_AIS_SHIFT)) & SDIF_IDSTS_AIS_MASK) +#define SDIF_IDSTS_EB_MASK (0x1C00U) +#define SDIF_IDSTS_EB_SHIFT (10U) +#define SDIF_IDSTS_EB(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_EB_SHIFT)) & SDIF_IDSTS_EB_MASK) +#define SDIF_IDSTS_FSM_MASK (0x1E000U) +#define SDIF_IDSTS_FSM_SHIFT (13U) +#define SDIF_IDSTS_FSM(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_FSM_SHIFT)) & SDIF_IDSTS_FSM_MASK) +/*! @} */ + +/*! @name IDINTEN - Internal DMAC Interrupt Enable register */ +/*! @{ */ +#define SDIF_IDINTEN_TI_MASK (0x1U) +#define SDIF_IDINTEN_TI_SHIFT (0U) +#define SDIF_IDINTEN_TI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_TI_SHIFT)) & SDIF_IDINTEN_TI_MASK) +#define SDIF_IDINTEN_RI_MASK (0x2U) +#define SDIF_IDINTEN_RI_SHIFT (1U) +#define SDIF_IDINTEN_RI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_RI_SHIFT)) & SDIF_IDINTEN_RI_MASK) +#define SDIF_IDINTEN_FBE_MASK (0x4U) +#define SDIF_IDINTEN_FBE_SHIFT (2U) +#define SDIF_IDINTEN_FBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_FBE_SHIFT)) & SDIF_IDINTEN_FBE_MASK) +#define SDIF_IDINTEN_DU_MASK (0x10U) +#define SDIF_IDINTEN_DU_SHIFT (4U) +#define SDIF_IDINTEN_DU(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_DU_SHIFT)) & SDIF_IDINTEN_DU_MASK) +#define SDIF_IDINTEN_CES_MASK (0x20U) +#define SDIF_IDINTEN_CES_SHIFT (5U) +#define SDIF_IDINTEN_CES(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_CES_SHIFT)) & SDIF_IDINTEN_CES_MASK) +#define SDIF_IDINTEN_NIS_MASK (0x100U) +#define SDIF_IDINTEN_NIS_SHIFT (8U) +#define SDIF_IDINTEN_NIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_NIS_SHIFT)) & SDIF_IDINTEN_NIS_MASK) +#define SDIF_IDINTEN_AIS_MASK (0x200U) +#define SDIF_IDINTEN_AIS_SHIFT (9U) +#define SDIF_IDINTEN_AIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_AIS_SHIFT)) & SDIF_IDINTEN_AIS_MASK) +/*! @} */ + +/*! @name DSCADDR - Current Host Descriptor Address register */ +/*! @{ */ +#define SDIF_DSCADDR_HDA_MASK (0xFFFFFFFFU) +#define SDIF_DSCADDR_HDA_SHIFT (0U) +#define SDIF_DSCADDR_HDA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_DSCADDR_HDA_SHIFT)) & SDIF_DSCADDR_HDA_MASK) +/*! @} */ + +/*! @name BUFADDR - Current Buffer Descriptor Address register */ +/*! @{ */ +#define SDIF_BUFADDR_HBA_MASK (0xFFFFFFFFU) +#define SDIF_BUFADDR_HBA_SHIFT (0U) +#define SDIF_BUFADDR_HBA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BUFADDR_HBA_SHIFT)) & SDIF_BUFADDR_HBA_MASK) +/*! @} */ + +/*! @name CARDTHRCTL - Card Threshold Control */ +/*! @{ */ +#define SDIF_CARDTHRCTL_CARDRDTHREN_MASK (0x1U) +#define SDIF_CARDTHRCTL_CARDRDTHREN_SHIFT (0U) +#define SDIF_CARDTHRCTL_CARDRDTHREN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_CARDRDTHREN_SHIFT)) & SDIF_CARDTHRCTL_CARDRDTHREN_MASK) +#define SDIF_CARDTHRCTL_BSYCLRINTEN_MASK (0x2U) +#define SDIF_CARDTHRCTL_BSYCLRINTEN_SHIFT (1U) +#define SDIF_CARDTHRCTL_BSYCLRINTEN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_BSYCLRINTEN_SHIFT)) & SDIF_CARDTHRCTL_BSYCLRINTEN_MASK) +#define SDIF_CARDTHRCTL_CARDTHRESHOLD_MASK (0xFF0000U) +#define SDIF_CARDTHRCTL_CARDTHRESHOLD_SHIFT (16U) +#define SDIF_CARDTHRCTL_CARDTHRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_CARDTHRESHOLD_SHIFT)) & SDIF_CARDTHRCTL_CARDTHRESHOLD_MASK) +/*! @} */ + +/*! @name BACKENDPWR - Power control */ +/*! @{ */ +#define SDIF_BACKENDPWR_BACKENDPWR_MASK (0x1U) +#define SDIF_BACKENDPWR_BACKENDPWR_SHIFT (0U) +#define SDIF_BACKENDPWR_BACKENDPWR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BACKENDPWR_BACKENDPWR_SHIFT)) & SDIF_BACKENDPWR_BACKENDPWR_MASK) +/*! @} */ + +/*! @name FIFO - SDIF FIFO */ +/*! @{ */ +#define SDIF_FIFO_DATA_MASK (0xFFFFFFFFU) +#define SDIF_FIFO_DATA_SHIFT (0U) +#define SDIF_FIFO_DATA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFO_DATA_SHIFT)) & SDIF_FIFO_DATA_MASK) +/*! @} */ + +/* The count of SDIF_FIFO */ +#define SDIF_FIFO_COUNT (64U) + + +/*! + * @} + */ /* end of group SDIF_Register_Masks */ + + +/* SDIF - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral SDIF base address */ + #define SDIF_BASE (0x5009B000u) + /** Peripheral SDIF base address */ + #define SDIF_BASE_NS (0x4009B000u) + /** Peripheral SDIF base pointer */ + #define SDIF ((SDIF_Type *)SDIF_BASE) + /** Peripheral SDIF base pointer */ + #define SDIF_NS ((SDIF_Type *)SDIF_BASE_NS) + /** Array initializer of SDIF peripheral base addresses */ + #define SDIF_BASE_ADDRS { SDIF_BASE } + /** Array initializer of SDIF peripheral base pointers */ + #define SDIF_BASE_PTRS { SDIF } + /** Array initializer of SDIF peripheral base addresses */ + #define SDIF_BASE_ADDRS_NS { SDIF_BASE_NS } + /** Array initializer of SDIF peripheral base pointers */ + #define SDIF_BASE_PTRS_NS { SDIF_NS } +#else + /** Peripheral SDIF base address */ + #define SDIF_BASE (0x4009B000u) + /** Peripheral SDIF base pointer */ + #define SDIF ((SDIF_Type *)SDIF_BASE) + /** Array initializer of SDIF peripheral base addresses */ + #define SDIF_BASE_ADDRS { SDIF_BASE } + /** Array initializer of SDIF peripheral base pointers */ + #define SDIF_BASE_PTRS { SDIF } +#endif +/** Interrupt vectors for the SDIF peripheral type */ +#define SDIF_IRQS { SDIO_IRQn } + +/*! + * @} + */ /* end of group SDIF_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SPI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer + * @{ + */ + +/** SPI - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[1024]; + __IO uint32_t CFG; /**< SPI Configuration register, offset: 0x400 */ + __IO uint32_t DLY; /**< SPI Delay register, offset: 0x404 */ + __IO uint32_t STAT; /**< SPI Status. Some status flags can be cleared by writing a 1 to that bit position., offset: 0x408 */ + __IO uint32_t INTENSET; /**< SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set., offset: 0x40C */ + __O uint32_t INTENCLR; /**< SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared., offset: 0x410 */ + uint8_t RESERVED_1[16]; + __IO uint32_t DIV; /**< SPI clock Divider, offset: 0x424 */ + __I uint32_t INTSTAT; /**< SPI Interrupt Status, offset: 0x428 */ + uint8_t RESERVED_2[2516]; + __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */ + __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ + __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */ + uint8_t RESERVED_3[4]; + __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */ + __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */ + __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */ + uint8_t RESERVED_4[4]; + __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ + uint8_t RESERVED_5[12]; + __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */ + uint8_t RESERVED_6[12]; + __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */ + uint8_t RESERVED_7[440]; + __I uint32_t ID; /**< Peripheral identification register., offset: 0xFFC */ +} SPI_Type; + +/* ---------------------------------------------------------------------------- + -- SPI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPI_Register_Masks SPI Register Masks + * @{ + */ + +/*! @name CFG - SPI Configuration register */ +/*! @{ */ +#define SPI_CFG_ENABLE_MASK (0x1U) +#define SPI_CFG_ENABLE_SHIFT (0U) +/*! ENABLE - SPI enable. + * 0b0..Disabled. The SPI is disabled and the internal state machine and counters are reset. + * 0b1..Enabled. The SPI is enabled for operation. + */ +#define SPI_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_ENABLE_SHIFT)) & SPI_CFG_ENABLE_MASK) +#define SPI_CFG_MASTER_MASK (0x4U) +#define SPI_CFG_MASTER_SHIFT (2U) +/*! MASTER - Master mode select. + * 0b0..Slave mode. The SPI will operate in slave mode. SCK, MOSI, and the SSEL signals are inputs, MISO is an output. + * 0b1..Master mode. The SPI will operate in master mode. SCK, MOSI, and the SSEL signals are outputs, MISO is an input. + */ +#define SPI_CFG_MASTER(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_MASTER_SHIFT)) & SPI_CFG_MASTER_MASK) +#define SPI_CFG_LSBF_MASK (0x8U) +#define SPI_CFG_LSBF_SHIFT (3U) +/*! LSBF - LSB First mode enable. + * 0b0..Standard. Data is transmitted and received in standard MSB first order. + * 0b1..Reverse. Data is transmitted and received in reverse order (LSB first). + */ +#define SPI_CFG_LSBF(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LSBF_SHIFT)) & SPI_CFG_LSBF_MASK) +#define SPI_CFG_CPHA_MASK (0x10U) +#define SPI_CFG_CPHA_SHIFT (4U) +/*! CPHA - Clock Phase select. + * 0b0..Change. The SPI captures serial data on the first clock transition of the transfer (when the clock + * changes away from the rest state). Data is changed on the following edge. + * 0b1..Capture. The SPI changes serial data on the first clock transition of the transfer (when the clock + * changes away from the rest state). Data is captured on the following edge. + */ +#define SPI_CFG_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPHA_SHIFT)) & SPI_CFG_CPHA_MASK) +#define SPI_CFG_CPOL_MASK (0x20U) +#define SPI_CFG_CPOL_SHIFT (5U) +/*! CPOL - Clock Polarity select. + * 0b0..Low. The rest state of the clock (between transfers) is low. + * 0b1..High. The rest state of the clock (between transfers) is high. + */ +#define SPI_CFG_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPOL_SHIFT)) & SPI_CFG_CPOL_MASK) +#define SPI_CFG_LOOP_MASK (0x80U) +#define SPI_CFG_LOOP_SHIFT (7U) +/*! LOOP - Loopback mode enable. Loopback mode applies only to Master mode, and connects transmit + * and receive data connected together to allow simple software testing. + * 0b0..Disabled. + * 0b1..Enabled. + */ +#define SPI_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LOOP_SHIFT)) & SPI_CFG_LOOP_MASK) +#define SPI_CFG_SPOL0_MASK (0x100U) +#define SPI_CFG_SPOL0_SHIFT (8U) +/*! SPOL0 - SSEL0 Polarity select. + * 0b0..Low. The SSEL0 pin is active low. + * 0b1..High. The SSEL0 pin is active high. + */ +#define SPI_CFG_SPOL0(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL0_SHIFT)) & SPI_CFG_SPOL0_MASK) +#define SPI_CFG_SPOL1_MASK (0x200U) +#define SPI_CFG_SPOL1_SHIFT (9U) +/*! SPOL1 - SSEL1 Polarity select. + * 0b0..Low. The SSEL1 pin is active low. + * 0b1..High. The SSEL1 pin is active high. + */ +#define SPI_CFG_SPOL1(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL1_SHIFT)) & SPI_CFG_SPOL1_MASK) +#define SPI_CFG_SPOL2_MASK (0x400U) +#define SPI_CFG_SPOL2_SHIFT (10U) +/*! SPOL2 - SSEL2 Polarity select. + * 0b0..Low. The SSEL2 pin is active low. + * 0b1..High. The SSEL2 pin is active high. + */ +#define SPI_CFG_SPOL2(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL2_SHIFT)) & SPI_CFG_SPOL2_MASK) +#define SPI_CFG_SPOL3_MASK (0x800U) +#define SPI_CFG_SPOL3_SHIFT (11U) +/*! SPOL3 - SSEL3 Polarity select. + * 0b0..Low. The SSEL3 pin is active low. + * 0b1..High. The SSEL3 pin is active high. + */ +#define SPI_CFG_SPOL3(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL3_SHIFT)) & SPI_CFG_SPOL3_MASK) +/*! @} */ + +/*! @name DLY - SPI Delay register */ +/*! @{ */ +#define SPI_DLY_PRE_DELAY_MASK (0xFU) +#define SPI_DLY_PRE_DELAY_SHIFT (0U) +#define SPI_DLY_PRE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_PRE_DELAY_SHIFT)) & SPI_DLY_PRE_DELAY_MASK) +#define SPI_DLY_POST_DELAY_MASK (0xF0U) +#define SPI_DLY_POST_DELAY_SHIFT (4U) +#define SPI_DLY_POST_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_POST_DELAY_SHIFT)) & SPI_DLY_POST_DELAY_MASK) +#define SPI_DLY_FRAME_DELAY_MASK (0xF00U) +#define SPI_DLY_FRAME_DELAY_SHIFT (8U) +#define SPI_DLY_FRAME_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_FRAME_DELAY_SHIFT)) & SPI_DLY_FRAME_DELAY_MASK) +#define SPI_DLY_TRANSFER_DELAY_MASK (0xF000U) +#define SPI_DLY_TRANSFER_DELAY_SHIFT (12U) +#define SPI_DLY_TRANSFER_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_TRANSFER_DELAY_SHIFT)) & SPI_DLY_TRANSFER_DELAY_MASK) +/*! @} */ + +/*! @name STAT - SPI Status. Some status flags can be cleared by writing a 1 to that bit position. */ +/*! @{ */ +#define SPI_STAT_SSA_MASK (0x10U) +#define SPI_STAT_SSA_SHIFT (4U) +#define SPI_STAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSA_SHIFT)) & SPI_STAT_SSA_MASK) +#define SPI_STAT_SSD_MASK (0x20U) +#define SPI_STAT_SSD_SHIFT (5U) +#define SPI_STAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSD_SHIFT)) & SPI_STAT_SSD_MASK) +#define SPI_STAT_STALLED_MASK (0x40U) +#define SPI_STAT_STALLED_SHIFT (6U) +#define SPI_STAT_STALLED(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_STALLED_SHIFT)) & SPI_STAT_STALLED_MASK) +#define SPI_STAT_ENDTRANSFER_MASK (0x80U) +#define SPI_STAT_ENDTRANSFER_SHIFT (7U) +#define SPI_STAT_ENDTRANSFER(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_ENDTRANSFER_SHIFT)) & SPI_STAT_ENDTRANSFER_MASK) +#define SPI_STAT_MSTIDLE_MASK (0x100U) +#define SPI_STAT_MSTIDLE_SHIFT (8U) +#define SPI_STAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_MSTIDLE_SHIFT)) & SPI_STAT_MSTIDLE_MASK) +/*! @} */ + +/*! @name INTENSET - SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */ +/*! @{ */ +#define SPI_INTENSET_SSAEN_MASK (0x10U) +#define SPI_INTENSET_SSAEN_SHIFT (4U) +/*! SSAEN - Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted. + * 0b0..Disabled. No interrupt will be generated when any Slave Select transitions from deasserted to asserted. + * 0b1..Enabled. An interrupt will be generated when any Slave Select transitions from deasserted to asserted. + */ +#define SPI_INTENSET_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSAEN_SHIFT)) & SPI_INTENSET_SSAEN_MASK) +#define SPI_INTENSET_SSDEN_MASK (0x20U) +#define SPI_INTENSET_SSDEN_SHIFT (5U) +/*! SSDEN - Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted. + * 0b0..Disabled. No interrupt will be generated when all asserted Slave Selects transition to deasserted. + * 0b1..Enabled. An interrupt will be generated when all asserted Slave Selects transition to deasserted. + */ +#define SPI_INTENSET_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSDEN_SHIFT)) & SPI_INTENSET_SSDEN_MASK) +#define SPI_INTENSET_MSTIDLEEN_MASK (0x100U) +#define SPI_INTENSET_MSTIDLEEN_SHIFT (8U) +/*! MSTIDLEEN - Master idle interrupt enable. + * 0b0..No interrupt will be generated when the SPI master function is idle. + * 0b1..An interrupt will be generated when the SPI master function is fully idle. + */ +#define SPI_INTENSET_MSTIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_MSTIDLEEN_SHIFT)) & SPI_INTENSET_MSTIDLEEN_MASK) +/*! @} */ + +/*! @name INTENCLR - SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared. */ +/*! @{ */ +#define SPI_INTENCLR_SSAEN_MASK (0x10U) +#define SPI_INTENCLR_SSAEN_SHIFT (4U) +#define SPI_INTENCLR_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSAEN_SHIFT)) & SPI_INTENCLR_SSAEN_MASK) +#define SPI_INTENCLR_SSDEN_MASK (0x20U) +#define SPI_INTENCLR_SSDEN_SHIFT (5U) +#define SPI_INTENCLR_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSDEN_SHIFT)) & SPI_INTENCLR_SSDEN_MASK) +#define SPI_INTENCLR_MSTIDLE_MASK (0x100U) +#define SPI_INTENCLR_MSTIDLE_SHIFT (8U) +#define SPI_INTENCLR_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_MSTIDLE_SHIFT)) & SPI_INTENCLR_MSTIDLE_MASK) +/*! @} */ + +/*! @name DIV - SPI clock Divider */ +/*! @{ */ +#define SPI_DIV_DIVVAL_MASK (0xFFFFU) +#define SPI_DIV_DIVVAL_SHIFT (0U) +#define SPI_DIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << SPI_DIV_DIVVAL_SHIFT)) & SPI_DIV_DIVVAL_MASK) +/*! @} */ + +/*! @name INTSTAT - SPI Interrupt Status */ +/*! @{ */ +#define SPI_INTSTAT_SSA_MASK (0x10U) +#define SPI_INTSTAT_SSA_SHIFT (4U) +#define SPI_INTSTAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSA_SHIFT)) & SPI_INTSTAT_SSA_MASK) +#define SPI_INTSTAT_SSD_MASK (0x20U) +#define SPI_INTSTAT_SSD_SHIFT (5U) +#define SPI_INTSTAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSD_SHIFT)) & SPI_INTSTAT_SSD_MASK) +#define SPI_INTSTAT_MSTIDLE_MASK (0x100U) +#define SPI_INTSTAT_MSTIDLE_SHIFT (8U) +#define SPI_INTSTAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_MSTIDLE_SHIFT)) & SPI_INTSTAT_MSTIDLE_MASK) +/*! @} */ + +/*! @name FIFOCFG - FIFO configuration and enable register. */ +/*! @{ */ +#define SPI_FIFOCFG_ENABLETX_MASK (0x1U) +#define SPI_FIFOCFG_ENABLETX_SHIFT (0U) +/*! ENABLETX - Enable the transmit FIFO. + * 0b0..The transmit FIFO is not enabled. + * 0b1..The transmit FIFO is enabled. + */ +#define SPI_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLETX_SHIFT)) & SPI_FIFOCFG_ENABLETX_MASK) +#define SPI_FIFOCFG_ENABLERX_MASK (0x2U) +#define SPI_FIFOCFG_ENABLERX_SHIFT (1U) +/*! ENABLERX - Enable the receive FIFO. + * 0b0..The receive FIFO is not enabled. + * 0b1..The receive FIFO is enabled. + */ +#define SPI_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLERX_SHIFT)) & SPI_FIFOCFG_ENABLERX_MASK) +#define SPI_FIFOCFG_SIZE_MASK (0x30U) +#define SPI_FIFOCFG_SIZE_SHIFT (4U) +#define SPI_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_SIZE_SHIFT)) & SPI_FIFOCFG_SIZE_MASK) +#define SPI_FIFOCFG_DMATX_MASK (0x1000U) +#define SPI_FIFOCFG_DMATX_SHIFT (12U) +/*! DMATX - DMA configuration for transmit. + * 0b0..DMA is not used for the transmit function. + * 0b1..Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. + */ +#define SPI_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMATX_SHIFT)) & SPI_FIFOCFG_DMATX_MASK) +#define SPI_FIFOCFG_DMARX_MASK (0x2000U) +#define SPI_FIFOCFG_DMARX_SHIFT (13U) +/*! DMARX - DMA configuration for receive. + * 0b0..DMA is not used for the receive function. + * 0b1..Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. + */ +#define SPI_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMARX_SHIFT)) & SPI_FIFOCFG_DMARX_MASK) +#define SPI_FIFOCFG_WAKETX_MASK (0x4000U) +#define SPI_FIFOCFG_WAKETX_SHIFT (14U) +/*! WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power + * modes (up to power-down, as long as the peripheral function works in that power mode) without + * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The + * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware + * Wake-up control register. + * 0b0..Only enabled interrupts will wake up the device form reduced power modes. + * 0b1..A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in + * FIFOTRIG, even when the TXLVL interrupt is not enabled. + */ +#define SPI_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKETX_SHIFT)) & SPI_FIFOCFG_WAKETX_MASK) +#define SPI_FIFOCFG_WAKERX_MASK (0x8000U) +#define SPI_FIFOCFG_WAKERX_SHIFT (15U) +/*! WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power + * modes (up to power-down, as long as the peripheral function works in that power mode) without + * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The + * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware + * Wake-up control register. + * 0b0..Only enabled interrupts will wake up the device form reduced power modes. + * 0b1..A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in + * FIFOTRIG, even when the RXLVL interrupt is not enabled. + */ +#define SPI_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKERX_SHIFT)) & SPI_FIFOCFG_WAKERX_MASK) +#define SPI_FIFOCFG_EMPTYTX_MASK (0x10000U) +#define SPI_FIFOCFG_EMPTYTX_SHIFT (16U) +#define SPI_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYTX_SHIFT)) & SPI_FIFOCFG_EMPTYTX_MASK) +#define SPI_FIFOCFG_EMPTYRX_MASK (0x20000U) +#define SPI_FIFOCFG_EMPTYRX_SHIFT (17U) +#define SPI_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYRX_SHIFT)) & SPI_FIFOCFG_EMPTYRX_MASK) +#define SPI_FIFOCFG_POPDBG_MASK (0x40000U) +#define SPI_FIFOCFG_POPDBG_SHIFT (18U) +/*! POPDBG - Pop FIFO for debug reads. + * 0b0..Debug reads of the FIFO do not pop the FIFO. + * 0b1..A debug read will cause the FIFO to pop. + */ +#define SPI_FIFOCFG_POPDBG(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_POPDBG_SHIFT)) & SPI_FIFOCFG_POPDBG_MASK) +/*! @} */ + +/*! @name FIFOSTAT - FIFO status register. */ +/*! @{ */ +#define SPI_FIFOSTAT_TXERR_MASK (0x1U) +#define SPI_FIFOSTAT_TXERR_SHIFT (0U) +#define SPI_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXERR_SHIFT)) & SPI_FIFOSTAT_TXERR_MASK) +#define SPI_FIFOSTAT_RXERR_MASK (0x2U) +#define SPI_FIFOSTAT_RXERR_SHIFT (1U) +#define SPI_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXERR_SHIFT)) & SPI_FIFOSTAT_RXERR_MASK) +#define SPI_FIFOSTAT_PERINT_MASK (0x8U) +#define SPI_FIFOSTAT_PERINT_SHIFT (3U) +#define SPI_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_PERINT_SHIFT)) & SPI_FIFOSTAT_PERINT_MASK) +#define SPI_FIFOSTAT_TXEMPTY_MASK (0x10U) +#define SPI_FIFOSTAT_TXEMPTY_SHIFT (4U) +#define SPI_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXEMPTY_SHIFT)) & SPI_FIFOSTAT_TXEMPTY_MASK) +#define SPI_FIFOSTAT_TXNOTFULL_MASK (0x20U) +#define SPI_FIFOSTAT_TXNOTFULL_SHIFT (5U) +#define SPI_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXNOTFULL_SHIFT)) & SPI_FIFOSTAT_TXNOTFULL_MASK) +#define SPI_FIFOSTAT_RXNOTEMPTY_MASK (0x40U) +#define SPI_FIFOSTAT_RXNOTEMPTY_SHIFT (6U) +#define SPI_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXNOTEMPTY_SHIFT)) & SPI_FIFOSTAT_RXNOTEMPTY_MASK) +#define SPI_FIFOSTAT_RXFULL_MASK (0x80U) +#define SPI_FIFOSTAT_RXFULL_SHIFT (7U) +#define SPI_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXFULL_SHIFT)) & SPI_FIFOSTAT_RXFULL_MASK) +#define SPI_FIFOSTAT_TXLVL_MASK (0x1F00U) +#define SPI_FIFOSTAT_TXLVL_SHIFT (8U) +#define SPI_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXLVL_SHIFT)) & SPI_FIFOSTAT_TXLVL_MASK) +#define SPI_FIFOSTAT_RXLVL_MASK (0x1F0000U) +#define SPI_FIFOSTAT_RXLVL_SHIFT (16U) +#define SPI_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXLVL_SHIFT)) & SPI_FIFOSTAT_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */ +/*! @{ */ +#define SPI_FIFOTRIG_TXLVLENA_MASK (0x1U) +#define SPI_FIFOTRIG_TXLVLENA_SHIFT (0U) +/*! TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled + * in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set. + * 0b0..Transmit FIFO level does not generate a FIFO level trigger. + * 0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register. + */ +#define SPI_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVLENA_SHIFT)) & SPI_FIFOTRIG_TXLVLENA_MASK) +#define SPI_FIFOTRIG_RXLVLENA_MASK (0x2U) +#define SPI_FIFOTRIG_RXLVLENA_SHIFT (1U) +/*! RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled + * in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. + * 0b0..Receive FIFO level does not generate a FIFO level trigger. + * 0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. + */ +#define SPI_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVLENA_SHIFT)) & SPI_FIFOTRIG_RXLVLENA_MASK) +#define SPI_FIFOTRIG_TXLVL_MASK (0xF00U) +#define SPI_FIFOTRIG_TXLVL_SHIFT (8U) +#define SPI_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVL_SHIFT)) & SPI_FIFOTRIG_TXLVL_MASK) +#define SPI_FIFOTRIG_RXLVL_MASK (0xF0000U) +#define SPI_FIFOTRIG_RXLVL_SHIFT (16U) +#define SPI_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVL_SHIFT)) & SPI_FIFOTRIG_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */ +/*! @{ */ +#define SPI_FIFOINTENSET_TXERR_MASK (0x1U) +#define SPI_FIFOINTENSET_TXERR_SHIFT (0U) +/*! TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. + * 0b0..No interrupt will be generated for a transmit error. + * 0b1..An interrupt will be generated when a transmit error occurs. + */ +#define SPI_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXERR_SHIFT)) & SPI_FIFOINTENSET_TXERR_MASK) +#define SPI_FIFOINTENSET_RXERR_MASK (0x2U) +#define SPI_FIFOINTENSET_RXERR_SHIFT (1U) +/*! RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. + * 0b0..No interrupt will be generated for a receive error. + * 0b1..An interrupt will be generated when a receive error occurs. + */ +#define SPI_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXERR_SHIFT)) & SPI_FIFOINTENSET_RXERR_MASK) +#define SPI_FIFOINTENSET_TXLVL_MASK (0x4U) +#define SPI_FIFOINTENSET_TXLVL_SHIFT (2U) +/*! TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level + * specified by the TXLVL field in the FIFOTRIG register. + * 0b0..No interrupt will be generated based on the TX FIFO level. + * 0b1..If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases + * to the level specified by TXLVL in the FIFOTRIG register. + */ +#define SPI_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXLVL_SHIFT)) & SPI_FIFOINTENSET_TXLVL_MASK) +#define SPI_FIFOINTENSET_RXLVL_MASK (0x8U) +#define SPI_FIFOINTENSET_RXLVL_SHIFT (3U) +/*! RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level + * specified by the TXLVL field in the FIFOTRIG register. + * 0b0..No interrupt will be generated based on the RX FIFO level. + * 0b1..If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level + * increases to the level specified by RXLVL in the FIFOTRIG register. + */ +#define SPI_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXLVL_SHIFT)) & SPI_FIFOINTENSET_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */ +/*! @{ */ +#define SPI_FIFOINTENCLR_TXERR_MASK (0x1U) +#define SPI_FIFOINTENCLR_TXERR_SHIFT (0U) +#define SPI_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXERR_SHIFT)) & SPI_FIFOINTENCLR_TXERR_MASK) +#define SPI_FIFOINTENCLR_RXERR_MASK (0x2U) +#define SPI_FIFOINTENCLR_RXERR_SHIFT (1U) +#define SPI_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXERR_SHIFT)) & SPI_FIFOINTENCLR_RXERR_MASK) +#define SPI_FIFOINTENCLR_TXLVL_MASK (0x4U) +#define SPI_FIFOINTENCLR_TXLVL_SHIFT (2U) +#define SPI_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXLVL_SHIFT)) & SPI_FIFOINTENCLR_TXLVL_MASK) +#define SPI_FIFOINTENCLR_RXLVL_MASK (0x8U) +#define SPI_FIFOINTENCLR_RXLVL_SHIFT (3U) +#define SPI_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXLVL_SHIFT)) & SPI_FIFOINTENCLR_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTSTAT - FIFO interrupt status register. */ +/*! @{ */ +#define SPI_FIFOINTSTAT_TXERR_MASK (0x1U) +#define SPI_FIFOINTSTAT_TXERR_SHIFT (0U) +#define SPI_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXERR_SHIFT)) & SPI_FIFOINTSTAT_TXERR_MASK) +#define SPI_FIFOINTSTAT_RXERR_MASK (0x2U) +#define SPI_FIFOINTSTAT_RXERR_SHIFT (1U) +#define SPI_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXERR_SHIFT)) & SPI_FIFOINTSTAT_RXERR_MASK) +#define SPI_FIFOINTSTAT_TXLVL_MASK (0x4U) +#define SPI_FIFOINTSTAT_TXLVL_SHIFT (2U) +#define SPI_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXLVL_SHIFT)) & SPI_FIFOINTSTAT_TXLVL_MASK) +#define SPI_FIFOINTSTAT_RXLVL_MASK (0x8U) +#define SPI_FIFOINTSTAT_RXLVL_SHIFT (3U) +#define SPI_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXLVL_SHIFT)) & SPI_FIFOINTSTAT_RXLVL_MASK) +#define SPI_FIFOINTSTAT_PERINT_MASK (0x10U) +#define SPI_FIFOINTSTAT_PERINT_SHIFT (4U) +#define SPI_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_PERINT_SHIFT)) & SPI_FIFOINTSTAT_PERINT_MASK) +/*! @} */ + +/*! @name FIFOWR - FIFO write data. */ +/*! @{ */ +#define SPI_FIFOWR_TXDATA_MASK (0xFFFFU) +#define SPI_FIFOWR_TXDATA_SHIFT (0U) +#define SPI_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXDATA_SHIFT)) & SPI_FIFOWR_TXDATA_MASK) +#define SPI_FIFOWR_TXSSEL0_N_MASK (0x10000U) +#define SPI_FIFOWR_TXSSEL0_N_SHIFT (16U) +/*! TXSSEL0_N - Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default. + * 0b0..SSEL0 asserted. + * 0b1..SSEL0 not asserted. + */ +#define SPI_FIFOWR_TXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL0_N_SHIFT)) & SPI_FIFOWR_TXSSEL0_N_MASK) +#define SPI_FIFOWR_TXSSEL1_N_MASK (0x20000U) +#define SPI_FIFOWR_TXSSEL1_N_SHIFT (17U) +/*! TXSSEL1_N - Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default. + * 0b0..SSEL1 asserted. + * 0b1..SSEL1 not asserted. + */ +#define SPI_FIFOWR_TXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL1_N_SHIFT)) & SPI_FIFOWR_TXSSEL1_N_MASK) +#define SPI_FIFOWR_TXSSEL2_N_MASK (0x40000U) +#define SPI_FIFOWR_TXSSEL2_N_SHIFT (18U) +/*! TXSSEL2_N - Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default. + * 0b0..SSEL2 asserted. + * 0b1..SSEL2 not asserted. + */ +#define SPI_FIFOWR_TXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL2_N_SHIFT)) & SPI_FIFOWR_TXSSEL2_N_MASK) +#define SPI_FIFOWR_TXSSEL3_N_MASK (0x80000U) +#define SPI_FIFOWR_TXSSEL3_N_SHIFT (19U) +/*! TXSSEL3_N - Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default. + * 0b0..SSEL3 asserted. + * 0b1..SSEL3 not asserted. + */ +#define SPI_FIFOWR_TXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL3_N_SHIFT)) & SPI_FIFOWR_TXSSEL3_N_MASK) +#define SPI_FIFOWR_EOT_MASK (0x100000U) +#define SPI_FIFOWR_EOT_SHIFT (20U) +/*! EOT - End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain + * so far at least the time specified by the Transfer_delay value in the DLY register. + * 0b0..SSEL not deasserted. This piece of data is not treated as the end of a transfer. SSEL will not be deasserted at the end of this data. + * 0b1..SSEL deasserted. This piece of data is treated as the end of a transfer. SSEL will be deasserted at the end of this piece of data. + */ +#define SPI_FIFOWR_EOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOT_SHIFT)) & SPI_FIFOWR_EOT_MASK) +#define SPI_FIFOWR_EOF_MASK (0x200000U) +#define SPI_FIFOWR_EOF_SHIFT (21U) +/*! EOF - End of frame. Between frames, a delay may be inserted, as defined by the Frame_delay value + * in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay + * value = 0. This control can be used as part of the support for frame lengths greater than 16 + * bits. + * 0b0..Data not EOF. This piece of data transmitted is not treated as the end of a frame. + * 0b1..Data EOF. This piece of data is treated as the end of a frame, causing the Frame_delay time to be + * inserted before subsequent data is transmitted. + */ +#define SPI_FIFOWR_EOF(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOF_SHIFT)) & SPI_FIFOWR_EOF_MASK) +#define SPI_FIFOWR_RXIGNORE_MASK (0x400000U) +#define SPI_FIFOWR_RXIGNORE_SHIFT (22U) +/*! RXIGNORE - Receive Ignore. This allows data to be transmitted using the SPI without the need to + * read unneeded data from the receiver. Setting this bit simplifies the transmit process and can + * be used with the DMA. + * 0b0..Read received data. Received data must be read in order to allow transmission to progress. SPI transmit + * will halt when the receive data FIFO is full. In slave mode, an overrun error will occur if received data + * is not read before new data is received. + * 0b1..Ignore received data. Received data is ignored, allowing transmission without reading unneeded received + * data. No receiver flags are generated. + */ +#define SPI_FIFOWR_RXIGNORE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_RXIGNORE_SHIFT)) & SPI_FIFOWR_RXIGNORE_MASK) +#define SPI_FIFOWR_LEN_MASK (0xF000000U) +#define SPI_FIFOWR_LEN_SHIFT (24U) +#define SPI_FIFOWR_LEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_LEN_SHIFT)) & SPI_FIFOWR_LEN_MASK) +/*! @} */ + +/*! @name FIFORD - FIFO read data. */ +/*! @{ */ +#define SPI_FIFORD_RXDATA_MASK (0xFFFFU) +#define SPI_FIFORD_RXDATA_SHIFT (0U) +#define SPI_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXDATA_SHIFT)) & SPI_FIFORD_RXDATA_MASK) +#define SPI_FIFORD_RXSSEL0_N_MASK (0x10000U) +#define SPI_FIFORD_RXSSEL0_N_SHIFT (16U) +#define SPI_FIFORD_RXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL0_N_SHIFT)) & SPI_FIFORD_RXSSEL0_N_MASK) +#define SPI_FIFORD_RXSSEL1_N_MASK (0x20000U) +#define SPI_FIFORD_RXSSEL1_N_SHIFT (17U) +#define SPI_FIFORD_RXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL1_N_SHIFT)) & SPI_FIFORD_RXSSEL1_N_MASK) +#define SPI_FIFORD_RXSSEL2_N_MASK (0x40000U) +#define SPI_FIFORD_RXSSEL2_N_SHIFT (18U) +#define SPI_FIFORD_RXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL2_N_SHIFT)) & SPI_FIFORD_RXSSEL2_N_MASK) +#define SPI_FIFORD_RXSSEL3_N_MASK (0x80000U) +#define SPI_FIFORD_RXSSEL3_N_SHIFT (19U) +#define SPI_FIFORD_RXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL3_N_SHIFT)) & SPI_FIFORD_RXSSEL3_N_MASK) +#define SPI_FIFORD_SOT_MASK (0x100000U) +#define SPI_FIFORD_SOT_SHIFT (20U) +#define SPI_FIFORD_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_SOT_SHIFT)) & SPI_FIFORD_SOT_MASK) +/*! @} */ + +/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */ +/*! @{ */ +#define SPI_FIFORDNOPOP_RXDATA_MASK (0xFFFFU) +#define SPI_FIFORDNOPOP_RXDATA_SHIFT (0U) +#define SPI_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXDATA_SHIFT)) & SPI_FIFORDNOPOP_RXDATA_MASK) +#define SPI_FIFORDNOPOP_RXSSEL0_N_MASK (0x10000U) +#define SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT (16U) +#define SPI_FIFORDNOPOP_RXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL0_N_MASK) +#define SPI_FIFORDNOPOP_RXSSEL1_N_MASK (0x20000U) +#define SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT (17U) +#define SPI_FIFORDNOPOP_RXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL1_N_MASK) +#define SPI_FIFORDNOPOP_RXSSEL2_N_MASK (0x40000U) +#define SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT (18U) +#define SPI_FIFORDNOPOP_RXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL2_N_MASK) +#define SPI_FIFORDNOPOP_RXSSEL3_N_MASK (0x80000U) +#define SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT (19U) +#define SPI_FIFORDNOPOP_RXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL3_N_MASK) +#define SPI_FIFORDNOPOP_SOT_MASK (0x100000U) +#define SPI_FIFORDNOPOP_SOT_SHIFT (20U) +#define SPI_FIFORDNOPOP_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_SOT_SHIFT)) & SPI_FIFORDNOPOP_SOT_MASK) +/*! @} */ + +/*! @name ID - Peripheral identification register. */ +/*! @{ */ +#define SPI_ID_APERTURE_MASK (0xFFU) +#define SPI_ID_APERTURE_SHIFT (0U) +#define SPI_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_APERTURE_SHIFT)) & SPI_ID_APERTURE_MASK) +#define SPI_ID_MINOR_REV_MASK (0xF00U) +#define SPI_ID_MINOR_REV_SHIFT (8U) +#define SPI_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_MINOR_REV_SHIFT)) & SPI_ID_MINOR_REV_MASK) +#define SPI_ID_MAJOR_REV_MASK (0xF000U) +#define SPI_ID_MAJOR_REV_SHIFT (12U) +#define SPI_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_MAJOR_REV_SHIFT)) & SPI_ID_MAJOR_REV_MASK) +#define SPI_ID_ID_MASK (0xFFFF0000U) +#define SPI_ID_ID_SHIFT (16U) +#define SPI_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_ID_SHIFT)) & SPI_ID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SPI_Register_Masks */ + + +/* SPI - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral SPI0 base address */ + #define SPI0_BASE (0x50086000u) + /** Peripheral SPI0 base address */ + #define SPI0_BASE_NS (0x40086000u) + /** Peripheral SPI0 base pointer */ + #define SPI0 ((SPI_Type *)SPI0_BASE) + /** Peripheral SPI0 base pointer */ + #define SPI0_NS ((SPI_Type *)SPI0_BASE_NS) + /** Peripheral SPI1 base address */ + #define SPI1_BASE (0x50087000u) + /** Peripheral SPI1 base address */ + #define SPI1_BASE_NS (0x40087000u) + /** Peripheral SPI1 base pointer */ + #define SPI1 ((SPI_Type *)SPI1_BASE) + /** Peripheral SPI1 base pointer */ + #define SPI1_NS ((SPI_Type *)SPI1_BASE_NS) + /** Peripheral SPI2 base address */ + #define SPI2_BASE (0x50088000u) + /** Peripheral SPI2 base address */ + #define SPI2_BASE_NS (0x40088000u) + /** Peripheral SPI2 base pointer */ + #define SPI2 ((SPI_Type *)SPI2_BASE) + /** Peripheral SPI2 base pointer */ + #define SPI2_NS ((SPI_Type *)SPI2_BASE_NS) + /** Peripheral SPI3 base address */ + #define SPI3_BASE (0x50089000u) + /** Peripheral SPI3 base address */ + #define SPI3_BASE_NS (0x40089000u) + /** Peripheral SPI3 base pointer */ + #define SPI3 ((SPI_Type *)SPI3_BASE) + /** Peripheral SPI3 base pointer */ + #define SPI3_NS ((SPI_Type *)SPI3_BASE_NS) + /** Peripheral SPI4 base address */ + #define SPI4_BASE (0x5008A000u) + /** Peripheral SPI4 base address */ + #define SPI4_BASE_NS (0x4008A000u) + /** Peripheral SPI4 base pointer */ + #define SPI4 ((SPI_Type *)SPI4_BASE) + /** Peripheral SPI4 base pointer */ + #define SPI4_NS ((SPI_Type *)SPI4_BASE_NS) + /** Peripheral SPI5 base address */ + #define SPI5_BASE (0x50096000u) + /** Peripheral SPI5 base address */ + #define SPI5_BASE_NS (0x40096000u) + /** Peripheral SPI5 base pointer */ + #define SPI5 ((SPI_Type *)SPI5_BASE) + /** Peripheral SPI5 base pointer */ + #define SPI5_NS ((SPI_Type *)SPI5_BASE_NS) + /** Peripheral SPI6 base address */ + #define SPI6_BASE (0x50097000u) + /** Peripheral SPI6 base address */ + #define SPI6_BASE_NS (0x40097000u) + /** Peripheral SPI6 base pointer */ + #define SPI6 ((SPI_Type *)SPI6_BASE) + /** Peripheral SPI6 base pointer */ + #define SPI6_NS ((SPI_Type *)SPI6_BASE_NS) + /** Peripheral SPI7 base address */ + #define SPI7_BASE (0x50098000u) + /** Peripheral SPI7 base address */ + #define SPI7_BASE_NS (0x40098000u) + /** Peripheral SPI7 base pointer */ + #define SPI7 ((SPI_Type *)SPI7_BASE) + /** Peripheral SPI7 base pointer */ + #define SPI7_NS ((SPI_Type *)SPI7_BASE_NS) + /** Peripheral SPI8 base address */ + #define SPI8_BASE (0x5009F000u) + /** Peripheral SPI8 base address */ + #define SPI8_BASE_NS (0x4009F000u) + /** Peripheral SPI8 base pointer */ + #define SPI8 ((SPI_Type *)SPI8_BASE) + /** Peripheral SPI8 base pointer */ + #define SPI8_NS ((SPI_Type *)SPI8_BASE_NS) + /** Array initializer of SPI peripheral base addresses */ + #define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE, SPI2_BASE, SPI3_BASE, SPI4_BASE, SPI5_BASE, SPI6_BASE, SPI7_BASE, SPI8_BASE } + /** Array initializer of SPI peripheral base pointers */ + #define SPI_BASE_PTRS { SPI0, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SPI7, SPI8 } + /** Array initializer of SPI peripheral base addresses */ + #define SPI_BASE_ADDRS_NS { SPI0_BASE_NS, SPI1_BASE_NS, SPI2_BASE_NS, SPI3_BASE_NS, SPI4_BASE_NS, SPI5_BASE_NS, SPI6_BASE_NS, SPI7_BASE_NS, SPI8_BASE_NS } + /** Array initializer of SPI peripheral base pointers */ + #define SPI_BASE_PTRS_NS { SPI0_NS, SPI1_NS, SPI2_NS, SPI3_NS, SPI4_NS, SPI5_NS, SPI6_NS, SPI7_NS, SPI8_NS } +#else + /** Peripheral SPI0 base address */ + #define SPI0_BASE (0x40086000u) + /** Peripheral SPI0 base pointer */ + #define SPI0 ((SPI_Type *)SPI0_BASE) + /** Peripheral SPI1 base address */ + #define SPI1_BASE (0x40087000u) + /** Peripheral SPI1 base pointer */ + #define SPI1 ((SPI_Type *)SPI1_BASE) + /** Peripheral SPI2 base address */ + #define SPI2_BASE (0x40088000u) + /** Peripheral SPI2 base pointer */ + #define SPI2 ((SPI_Type *)SPI2_BASE) + /** Peripheral SPI3 base address */ + #define SPI3_BASE (0x40089000u) + /** Peripheral SPI3 base pointer */ + #define SPI3 ((SPI_Type *)SPI3_BASE) + /** Peripheral SPI4 base address */ + #define SPI4_BASE (0x4008A000u) + /** Peripheral SPI4 base pointer */ + #define SPI4 ((SPI_Type *)SPI4_BASE) + /** Peripheral SPI5 base address */ + #define SPI5_BASE (0x40096000u) + /** Peripheral SPI5 base pointer */ + #define SPI5 ((SPI_Type *)SPI5_BASE) + /** Peripheral SPI6 base address */ + #define SPI6_BASE (0x40097000u) + /** Peripheral SPI6 base pointer */ + #define SPI6 ((SPI_Type *)SPI6_BASE) + /** Peripheral SPI7 base address */ + #define SPI7_BASE (0x40098000u) + /** Peripheral SPI7 base pointer */ + #define SPI7 ((SPI_Type *)SPI7_BASE) + /** Peripheral SPI8 base address */ + #define SPI8_BASE (0x4009F000u) + /** Peripheral SPI8 base pointer */ + #define SPI8 ((SPI_Type *)SPI8_BASE) + /** Array initializer of SPI peripheral base addresses */ + #define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE, SPI2_BASE, SPI3_BASE, SPI4_BASE, SPI5_BASE, SPI6_BASE, SPI7_BASE, SPI8_BASE } + /** Array initializer of SPI peripheral base pointers */ + #define SPI_BASE_PTRS { SPI0, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SPI7, SPI8 } +#endif +/** Interrupt vectors for the SPI peripheral type */ +#define SPI_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn } + +/*! + * @} + */ /* end of group SPI_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SYSCON Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SYSCON_Peripheral_Access_Layer SYSCON Peripheral Access Layer + * @{ + */ + +/** SYSCON - Register Layout Typedef */ +typedef struct { + __IO uint32_t MEMORYREMAP; /**< Memory Remap control register, offset: 0x0 */ + uint8_t RESERVED_0[12]; + __IO uint32_t AHBMATPRIO; /**< AHB Matrix priority control register Priority values are 3 = highest, 0 = lowest, offset: 0x10 */ + uint8_t RESERVED_1[36]; + __IO uint32_t CPU0STCKCAL; /**< System tick calibration for secure part of CPU0, offset: 0x38 */ + __IO uint32_t CPU0NSTCKCAL; /**< System tick calibration for non-secure part of CPU0, offset: 0x3C */ + __IO uint32_t CPU1TCKCAL; /**< System tick calibration for CPU1, offset: 0x40 */ + uint8_t RESERVED_2[4]; + __IO uint32_t NMISRC; /**< NMI Source Select, offset: 0x48 */ + uint8_t RESERVED_3[180]; + union { /* offset: 0x100 */ + struct { /* offset: 0x100 */ + __IO uint32_t PRESETCTRL0; /**< Peripheral reset control 0, offset: 0x100 */ + __IO uint32_t PRESETCTRL1; /**< Peripheral reset control 1, offset: 0x104 */ + __IO uint32_t PRESETCTRL2; /**< Peripheral reset control 2, offset: 0x108 */ + } PRESETCTRL; + __IO uint32_t PRESETCTRLX[3]; /**< Peripheral reset control register, array offset: 0x100, array step: 0x4 */ + }; + uint8_t RESERVED_4[20]; + __IO uint32_t PRESETCTRLSET[3]; /**< Peripheral reset control set register, array offset: 0x120, array step: 0x4 */ + uint8_t RESERVED_5[20]; + __IO uint32_t PRESETCTRLCLR[3]; /**< Peripheral reset contro clearl register, array offset: 0x140, array step: 0x4 */ + uint8_t RESERVED_6[20]; + __O uint32_t SWR_RESET; /**< generate a software_reset, offset: 0x160 */ + uint8_t RESERVED_7[156]; + union { /* offset: 0x200 */ + struct { /* offset: 0x200 */ + __IO uint32_t AHBCLKCTRL0; /**< AHB Clock control 0, offset: 0x200 */ + __IO uint32_t AHBCLKCTRL1; /**< AHB Clock control 1, offset: 0x204 */ + __IO uint32_t AHBCLKCTRL2; /**< AHB Clock control 2, offset: 0x208 */ + } AHBCLKCTRL; + __IO uint32_t AHBCLKCTRLX[3]; /**< Peripheral reset control register, array offset: 0x200, array step: 0x4 */ + }; + uint8_t RESERVED_8[20]; + __IO uint32_t AHBCLKCTRLSET[3]; /**< Peripheral reset control register, array offset: 0x220, array step: 0x4 */ + uint8_t RESERVED_9[20]; + __IO uint32_t AHBCLKCTRLCLR[3]; /**< Peripheral reset control register, array offset: 0x240, array step: 0x4 */ + uint8_t RESERVED_10[20]; + union { /* offset: 0x260 */ + struct { /* offset: 0x260 */ + __IO uint32_t SYSTICKCLKSEL0; /**< System Tick Timer for CPU0 source select, offset: 0x260 */ + __IO uint32_t SYSTICKCLKSEL1; /**< System Tick Timer for CPU1 source select, offset: 0x264 */ + } SYSTICKCLKSEL; + __IO uint32_t SYSTICKCLKSELX[2]; /**< Peripheral reset control register, array offset: 0x260, array step: 0x4 */ + }; + __IO uint32_t TRACECLKSEL; /**< Trace clock source select, offset: 0x268 */ + union { /* offset: 0x26C */ + struct { /* offset: 0x26C */ + __IO uint32_t CTIMERCLKSEL0; /**< CTimer 0 clock source select, offset: 0x26C */ + __IO uint32_t CTIMERCLKSEL1; /**< CTimer 1 clock source select, offset: 0x270 */ + __IO uint32_t CTIMERCLKSEL2; /**< CTimer 2 clock source select, offset: 0x274 */ + __IO uint32_t CTIMERCLKSEL3; /**< CTimer 3 clock source select, offset: 0x278 */ + __IO uint32_t CTIMERCLKSEL4; /**< CTimer 4 clock source select, offset: 0x27C */ + } CTIMERCLKSEL; + __IO uint32_t CTIMERCLKSELX[5]; /**< Peripheral reset control register, array offset: 0x26C, array step: 0x4 */ + }; + __IO uint32_t MAINCLKSELA; /**< Main clock A source select, offset: 0x280 */ + __IO uint32_t MAINCLKSELB; /**< Main clock source select, offset: 0x284 */ + __IO uint32_t CLKOUTSEL; /**< CLKOUT clock source select, offset: 0x288 */ + uint8_t RESERVED_11[4]; + __IO uint32_t PLL0CLKSEL; /**< PLL0 clock source select, offset: 0x290 */ + __IO uint32_t PLL1CLKSEL; /**< PLL1 clock source select, offset: 0x294 */ + uint8_t RESERVED_12[12]; + __IO uint32_t ADCCLKSEL; /**< ADC clock source select, offset: 0x2A4 */ + __IO uint32_t USB0CLKSEL; /**< FS USB clock source select, offset: 0x2A8 */ + __IO uint32_t USB1CLKSEL; /**< HS USB clock source select - NOT USED, offset: 0x2AC */ + union { /* offset: 0x2B0 */ + struct { /* offset: 0x2B0 */ + __IO uint32_t FCCLKSEL0; /**< Flexcomm Interface 0 clock source select for Fractional Rate Divider, offset: 0x2B0 */ + __IO uint32_t FCCLKSEL1; /**< Flexcomm Interface 1 clock source select for Fractional Rate Divider, offset: 0x2B4 */ + __IO uint32_t FCCLKSEL2; /**< Flexcomm Interface 2 clock source select for Fractional Rate Divider, offset: 0x2B8 */ + __IO uint32_t FCCLKSEL3; /**< Flexcomm Interface 3 clock source select for Fractional Rate Divider, offset: 0x2BC */ + __IO uint32_t FCCLKSEL4; /**< Flexcomm Interface 4 clock source select for Fractional Rate Divider, offset: 0x2C0 */ + __IO uint32_t FCCLKSEL5; /**< Flexcomm Interface 5 clock source select for Fractional Rate Divider, offset: 0x2C4 */ + __IO uint32_t FCCLKSEL6; /**< Flexcomm Interface 6 clock source select for Fractional Rate Divider, offset: 0x2C8 */ + __IO uint32_t FCCLKSEL7; /**< Flexcomm Interface 7 clock source select for Fractional Rate Divider, offset: 0x2CC */ + } FCCLKSEL; + __IO uint32_t FCCLKSELX[8]; /**< Peripheral reset control register, array offset: 0x2B0, array step: 0x4 */ + }; + __IO uint32_t HSLSPICLKSEL; /**< HS LSPI clock source select, offset: 0x2D0 */ + uint8_t RESERVED_13[12]; + __IO uint32_t MCLKCLKSEL; /**< MCLK clock source select, offset: 0x2E0 */ + uint8_t RESERVED_14[12]; + __IO uint32_t SCTCLKSEL; /**< SCTimer/PWM clock source select, offset: 0x2F0 */ + uint8_t RESERVED_15[4]; + __IO uint32_t SDIOCLKSEL; /**< SDIO clock source select, offset: 0x2F8 */ + uint8_t RESERVED_16[4]; + __IO uint32_t SYSTICKCLKDIV0; /**< System Tick Timer divider for CPU0, offset: 0x300 */ + __IO uint32_t SYSTICKCLKDIV1; /**< System Tick Timer divider for CPU1, offset: 0x304 */ + __IO uint32_t TRACECLKDIV; /**< TRACE clock divider, offset: 0x308 */ + uint8_t RESERVED_17[20]; + union { /* offset: 0x320 */ + struct { /* offset: 0x320 */ + __IO uint32_t FLEXFRG0CTRL; /**< Fractional rate divider for flexcomm 0, offset: 0x320 */ + __IO uint32_t FLEXFRG1CTRL; /**< Fractional rate divider for flexcomm 1, offset: 0x324 */ + __IO uint32_t FLEXFRG2CTRL; /**< Fractional rate divider for flexcomm 2, offset: 0x328 */ + __IO uint32_t FLEXFRG3CTRL; /**< Fractional rate divider for flexcomm 3, offset: 0x32C */ + __IO uint32_t FLEXFRG4CTRL; /**< Fractional rate divider for flexcomm 4, offset: 0x330 */ + __IO uint32_t FLEXFRG5CTRL; /**< Fractional rate divider for flexcomm 5, offset: 0x334 */ + __IO uint32_t FLEXFRG6CTRL; /**< Fractional rate divider for flexcomm 6, offset: 0x338 */ + __IO uint32_t FLEXFRG7CTRL; /**< Fractional rate divider for flexcomm 7, offset: 0x33C */ + } FLEXFRGCTRL; + __IO uint32_t FLEXFRGXCTRL[8]; /**< Peripheral reset control register, array offset: 0x320, array step: 0x4 */ + }; + uint8_t RESERVED_18[64]; + __IO uint32_t AHBCLKDIV; /**< System clock divider, offset: 0x380 */ + __IO uint32_t CLKOUTDIV; /**< CLKOUT clock divider, offset: 0x384 */ + __IO uint32_t FROHFDIV; /**< FRO_HF (96MHz) clock divider, offset: 0x388 */ + __IO uint32_t WDTCLKDIV; /**< WDT clock divider, offset: 0x38C */ + uint8_t RESERVED_19[4]; + __IO uint32_t ADCCLKDIV; /**< ADC clock divider, offset: 0x394 */ + __IO uint32_t USB0CLKDIV; /**< USB0 Clock divider, offset: 0x398 */ + uint8_t RESERVED_20[16]; + __IO uint32_t MCLKDIV; /**< I2S MCLK clock divider, offset: 0x3AC */ + uint8_t RESERVED_21[4]; + __IO uint32_t SCTCLKDIV; /**< SCT/PWM clock divider, offset: 0x3B4 */ + uint8_t RESERVED_22[4]; + __IO uint32_t SDIOCLKDIV; /**< SDIO clock divider, offset: 0x3BC */ + uint8_t RESERVED_23[4]; + __IO uint32_t PLL0CLKDIV; /**< PLL0 clock divider, offset: 0x3C4 */ + uint8_t RESERVED_24[52]; + __IO uint32_t CLOCKGENUPDATELOCKOUT; /**< Control clock configuration registers access (like xxxDIV, xxxSEL), offset: 0x3FC */ + __IO uint32_t FMCCR; /**< FMC configuration register - INTERNAL USE ONLY, offset: 0x400 */ + uint8_t RESERVED_25[8]; + __IO uint32_t USB0CLKCTRL; /**< USB0 clock control, offset: 0x40C */ + __I uint32_t USB0CLKSTAT; /**< USB0 clock status, offset: 0x410 */ + uint8_t RESERVED_26[8]; + __O uint32_t FMCFLUSH; /**< FMCflush control, offset: 0x41C */ + __IO uint32_t MCLKIO; /**< MCLK control, offset: 0x420 */ + __IO uint32_t USB1CLKCTRL; /**< USB1 clock control, offset: 0x424 */ + __I uint32_t USB1CLKSTAT; /**< USB1 clock status, offset: 0x428 */ + uint8_t RESERVED_27[36]; + __IO uint32_t FLASHBANKENABLE; /**< Flash Banks control, offset: 0x450 */ + uint8_t RESERVED_28[12]; + __IO uint32_t SDIOCLKCTRL; /**< SDIO CCLKIN phase and delay control, offset: 0x460 */ + uint8_t RESERVED_29[252]; + __IO uint32_t PLL1CTRL; /**< PLL1 550m control, offset: 0x560 */ + __I uint32_t PLL1STAT; /**< PLL1 550m status, offset: 0x564 */ + __IO uint32_t PLL1NDEC; /**< PLL1 550m N divider, offset: 0x568 */ + __IO uint32_t PLL1MDEC; /**< PLL1 550m M divider, offset: 0x56C */ + __IO uint32_t PLL1PDEC; /**< PLL1 550m P divider, offset: 0x570 */ + uint8_t RESERVED_30[12]; + __IO uint32_t PLL0CTRL; /**< PLL0 550m control, offset: 0x580 */ + __I uint32_t PLL0STAT; /**< PLL0 550m status, offset: 0x584 */ + __IO uint32_t PLL0NDEC; /**< PLL0 550m N divider, offset: 0x588 */ + __IO uint32_t PLL0PDEC; /**< PLL0 550m P divider, offset: 0x58C */ + __IO uint32_t PLL0SSCG0; /**< PLL0 Spread Spectrum Wrapper control register 0, offset: 0x590 */ + __IO uint32_t PLL0SSCG1; /**< PLL0 Spread Spectrum Wrapper control register 1, offset: 0x594 */ + uint8_t RESERVED_31[52]; + __IO uint32_t EFUSECLKCTRL; /**< eFUSE controller clock enable, offset: 0x5CC */ + uint8_t RESERVED_32[176]; + __IO uint32_t STARTER[2]; /**< Start logic wake-up enable register, array offset: 0x680, array step: 0x4 */ + uint8_t RESERVED_33[24]; + __O uint32_t STARTERSET[2]; /**< Set bits in STARTER, array offset: 0x6A0, array step: 0x4 */ + uint8_t RESERVED_34[24]; + __O uint32_t STARTERCLR[2]; /**< Clear bits in STARTER, array offset: 0x6C0, array step: 0x4 */ + uint8_t RESERVED_35[184]; + __IO uint32_t HARDWARESLEEP; /**< Hardware Sleep control, offset: 0x780 */ + uint8_t RESERVED_36[124]; + __IO uint32_t CPUCTRL; /**< CPU Control for multiple processors, offset: 0x800 */ + __IO uint32_t CPBOOT; /**< Coprocessor Boot Address, offset: 0x804 */ + __IO uint32_t CPSTACK; /**< Coprocessor Stack Address, offset: 0x808 */ + __I uint32_t CPSTAT; /**< CPU Status, offset: 0x80C */ + uint8_t RESERVED_37[240]; + __IO uint32_t DICE_REG0; /**< Composite Device Identifier, offset: 0x900 */ + __IO uint32_t DICE_REG1; /**< Composite Device Identifier, offset: 0x904 */ + __IO uint32_t DICE_REG2; /**< Composite Device Identifier, offset: 0x908 */ + __IO uint32_t DICE_REG3; /**< Composite Device Identifier, offset: 0x90C */ + __IO uint32_t DICE_REG4; /**< Composite Device Identifier, offset: 0x910 */ + __IO uint32_t DICE_REG5; /**< Composite Device Identifier, offset: 0x914 */ + __IO uint32_t DICE_REG6; /**< Composite Device Identifier, offset: 0x918 */ + __IO uint32_t DICE_REG7; /**< Composite Device Identifier, offset: 0x91C */ + uint8_t RESERVED_38[248]; + __IO uint32_t CLOCK_CTRL; /**< Various system clock controls : Flash clock (48 MHz) control, clocks to Frequency Measures, offset: 0xA18 */ + uint8_t RESERVED_39[244]; + __IO uint32_t COMP_INT_CTRL; /**< Comparator Interrupt control, offset: 0xB10 */ + __I uint32_t COMP_INT_STATUS; /**< Comparator Interrupt status, offset: 0xB14 */ + uint8_t RESERVED_40[748]; + __IO uint32_t AUTOCLKGATEOVERRIDE; /**< Control automatic clock gating, offset: 0xE04 */ + __IO uint32_t GPIOPSYNC; /**< Enable bypass of the first stage of synchonization inside GPIO_INT module, offset: 0xE08 */ + uint8_t RESERVED_41[404]; + __IO uint32_t DEBUG_LOCK_EN; /**< Control write access to security registers -- FOR INTERNAl USE ONLY, offset: 0xFA0 */ + __IO uint32_t DEBUG_FEATURES; /**< Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control -- FOR INTERNAl USE ONLY, offset: 0xFA4 */ + __IO uint32_t DEBUG_FEATURES_DP; /**< Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control DUPLICATE register -- FOR INTERNAl USE ONLY, offset: 0xFA8 */ + uint8_t RESERVED_42[4]; + __O uint32_t CODESECURITYPROTTEST; /**< Security code to allow test (Design for Testability) access -- FOR INTERNAl USE ONLY, offset: 0xFB0 */ + __O uint32_t CODESECURITYPROTCPU0; /**< Security code to allow CPU0 (CM33) Debug Access Port (DAP) -- FOR INTERNAl USE ONLY, offset: 0xFB4 */ + __O uint32_t CODESECURITYPROTCPU1; /**< Security code to allow CPU1 (Micro CM33) Debug Access Port (DAP) -- FOR INTERNAl USE ONLY, offset: 0xFB8 */ + __O uint32_t KEY_BLOCK; /**< block quiddikey/PUF all index. -- FOR INTERNAL USE ONLY, offset: 0xFBC */ + __IO uint32_t DEBUG_AUTH_SCRATCH; /**< Debug authentication scratch registers -- FOR INTERNAL USE ONLY, offset: 0xFC0 */ + uint8_t RESERVED_43[16]; + __IO uint32_t CPUCFG; /**< CPUs configuration register, offset: 0xFD4 */ + uint8_t RESERVED_44[20]; + __IO uint32_t PERIPHENCFG; /**< peripheral enable configuration -- FOR INTERNAL USE ONLY, offset: 0xFEC */ + uint8_t RESERVED_45[8]; + __I uint32_t DEVICE_ID0; /**< Device ID, offset: 0xFF8 */ + __I uint32_t DIEID; /**< Chip revision ID and Number, offset: 0xFFC */ +} SYSCON_Type; + +/* ---------------------------------------------------------------------------- + -- SYSCON Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SYSCON_Register_Masks SYSCON Register Masks + * @{ + */ + +/*! @name MEMORYREMAP - Memory Remap control register */ +/*! @{ */ +#define SYSCON_MEMORYREMAP_MAP_MASK (0x3U) +#define SYSCON_MEMORYREMAP_MAP_SHIFT (0U) +/*! MAP - Select the location of the vector table :. + * 0b00..Vector Table in ROM. + * 0b01..Vector Table in RAM. + * 0b10..Vector Table in Flash. + * 0b11..Vector Table in Flash. + */ +#define SYSCON_MEMORYREMAP_MAP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MEMORYREMAP_MAP_SHIFT)) & SYSCON_MEMORYREMAP_MAP_MASK) +/*! @} */ + +/*! @name AHBMATPRIO - AHB Matrix priority control register Priority values are 3 = highest, 0 = lowest */ +/*! @{ */ +#define SYSCON_AHBMATPRIO_PRI_TEAL_CBUS_MASK (0x3U) +#define SYSCON_AHBMATPRIO_PRI_TEAL_CBUS_SHIFT (0U) +#define SYSCON_AHBMATPRIO_PRI_TEAL_CBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_TEAL_CBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_TEAL_CBUS_MASK) +#define SYSCON_AHBMATPRIO_PRI_TEAL_SBUS_MASK (0xCU) +#define SYSCON_AHBMATPRIO_PRI_TEAL_SBUS_SHIFT (2U) +#define SYSCON_AHBMATPRIO_PRI_TEAL_SBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_TEAL_SBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_TEAL_SBUS_MASK) +#define SYSCON_AHBMATPRIO_PRI_UTEAL_CBUS_MASK (0x30U) +#define SYSCON_AHBMATPRIO_PRI_UTEAL_CBUS_SHIFT (4U) +#define SYSCON_AHBMATPRIO_PRI_UTEAL_CBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_UTEAL_CBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_UTEAL_CBUS_MASK) +#define SYSCON_AHBMATPRIO_PRI_UTEAL_SBUS_MASK (0xC0U) +#define SYSCON_AHBMATPRIO_PRI_UTEAL_SBUS_SHIFT (6U) +#define SYSCON_AHBMATPRIO_PRI_UTEAL_SBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_UTEAL_SBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_UTEAL_SBUS_MASK) +#define SYSCON_AHBMATPRIO_PRI_USB_FS_MASK (0x300U) +#define SYSCON_AHBMATPRIO_PRI_USB_FS_SHIFT (8U) +#define SYSCON_AHBMATPRIO_PRI_USB_FS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USB_FS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USB_FS_MASK) +#define SYSCON_AHBMATPRIO_PRI_SDMA0_MASK (0xC00U) +#define SYSCON_AHBMATPRIO_PRI_SDMA0_SHIFT (10U) +#define SYSCON_AHBMATPRIO_PRI_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SDMA0_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SDMA0_MASK) +#define SYSCON_AHBMATPRIO_PRI_EZH_B_D_MASK (0x3000U) +#define SYSCON_AHBMATPRIO_PRI_EZH_B_D_SHIFT (12U) +#define SYSCON_AHBMATPRIO_PRI_EZH_B_D(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_EZH_B_D_SHIFT)) & SYSCON_AHBMATPRIO_PRI_EZH_B_D_MASK) +#define SYSCON_AHBMATPRIO_PRI_EZH_B_I_MASK (0xC000U) +#define SYSCON_AHBMATPRIO_PRI_EZH_B_I_SHIFT (14U) +#define SYSCON_AHBMATPRIO_PRI_EZH_B_I(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_EZH_B_I_SHIFT)) & SYSCON_AHBMATPRIO_PRI_EZH_B_I_MASK) +#define SYSCON_AHBMATPRIO_PRI_SDIO_MASK (0x30000U) +#define SYSCON_AHBMATPRIO_PRI_SDIO_SHIFT (16U) +#define SYSCON_AHBMATPRIO_PRI_SDIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SDIO_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SDIO_MASK) +#define SYSCON_AHBMATPRIO_PRI_PQ_MASK (0xC0000U) +#define SYSCON_AHBMATPRIO_PRI_PQ_SHIFT (18U) +#define SYSCON_AHBMATPRIO_PRI_PQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_PQ_SHIFT)) & SYSCON_AHBMATPRIO_PRI_PQ_MASK) +#define SYSCON_AHBMATPRIO_PRI_SHA2_MASK (0x300000U) +#define SYSCON_AHBMATPRIO_PRI_SHA2_SHIFT (20U) +#define SYSCON_AHBMATPRIO_PRI_SHA2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SHA2_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SHA2_MASK) +#define SYSCON_AHBMATPRIO_PRI_USB_HS_MASK (0xC00000U) +#define SYSCON_AHBMATPRIO_PRI_USB_HS_SHIFT (22U) +#define SYSCON_AHBMATPRIO_PRI_USB_HS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USB_HS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USB_HS_MASK) +#define SYSCON_AHBMATPRIO_PRI_SDMA1_MASK (0x3000000U) +#define SYSCON_AHBMATPRIO_PRI_SDMA1_SHIFT (24U) +#define SYSCON_AHBMATPRIO_PRI_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SDMA1_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SDMA1_MASK) +/*! @} */ + +/*! @name CPU0STCKCAL - System tick calibration for secure part of CPU0 */ +/*! @{ */ +#define SYSCON_CPU0STCKCAL_CAL_MASK (0xFFFFFFU) +#define SYSCON_CPU0STCKCAL_CAL_SHIFT (0U) +#define SYSCON_CPU0STCKCAL_CAL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0STCKCAL_CAL_SHIFT)) & SYSCON_CPU0STCKCAL_CAL_MASK) +#define SYSCON_CPU0STCKCAL_SKEW_MASK (0x1000000U) +#define SYSCON_CPU0STCKCAL_SKEW_SHIFT (24U) +#define SYSCON_CPU0STCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0STCKCAL_SKEW_SHIFT)) & SYSCON_CPU0STCKCAL_SKEW_MASK) +#define SYSCON_CPU0STCKCAL_NOREF_MASK (0x2000000U) +#define SYSCON_CPU0STCKCAL_NOREF_SHIFT (25U) +#define SYSCON_CPU0STCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0STCKCAL_NOREF_SHIFT)) & SYSCON_CPU0STCKCAL_NOREF_MASK) +/*! @} */ + +/*! @name CPU0NSTCKCAL - System tick calibration for non-secure part of CPU0 */ +/*! @{ */ +#define SYSCON_CPU0NSTCKCAL_CAL_MASK (0xFFFFFFU) +#define SYSCON_CPU0NSTCKCAL_CAL_SHIFT (0U) +#define SYSCON_CPU0NSTCKCAL_CAL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_CAL_SHIFT)) & SYSCON_CPU0NSTCKCAL_CAL_MASK) +#define SYSCON_CPU0NSTCKCAL_SKEW_MASK (0x1000000U) +#define SYSCON_CPU0NSTCKCAL_SKEW_SHIFT (24U) +#define SYSCON_CPU0NSTCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_SKEW_SHIFT)) & SYSCON_CPU0NSTCKCAL_SKEW_MASK) +#define SYSCON_CPU0NSTCKCAL_NOREF_MASK (0x2000000U) +#define SYSCON_CPU0NSTCKCAL_NOREF_SHIFT (25U) +#define SYSCON_CPU0NSTCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_NOREF_SHIFT)) & SYSCON_CPU0NSTCKCAL_NOREF_MASK) +/*! @} */ + +/*! @name CPU1TCKCAL - System tick calibration for CPU1 */ +/*! @{ */ +#define SYSCON_CPU1TCKCAL_CAL_MASK (0xFFFFFFU) +#define SYSCON_CPU1TCKCAL_CAL_SHIFT (0U) +#define SYSCON_CPU1TCKCAL_CAL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU1TCKCAL_CAL_SHIFT)) & SYSCON_CPU1TCKCAL_CAL_MASK) +#define SYSCON_CPU1TCKCAL_SKEW_MASK (0x1000000U) +#define SYSCON_CPU1TCKCAL_SKEW_SHIFT (24U) +#define SYSCON_CPU1TCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU1TCKCAL_SKEW_SHIFT)) & SYSCON_CPU1TCKCAL_SKEW_MASK) +#define SYSCON_CPU1TCKCAL_NOREF_MASK (0x2000000U) +#define SYSCON_CPU1TCKCAL_NOREF_SHIFT (25U) +#define SYSCON_CPU1TCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU1TCKCAL_NOREF_SHIFT)) & SYSCON_CPU1TCKCAL_NOREF_MASK) +/*! @} */ + +/*! @name NMISRC - NMI Source Select */ +/*! @{ */ +#define SYSCON_NMISRC_IRQCPU0_MASK (0x3FU) +#define SYSCON_NMISRC_IRQCPU0_SHIFT (0U) +#define SYSCON_NMISRC_IRQCPU0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQCPU0_SHIFT)) & SYSCON_NMISRC_IRQCPU0_MASK) +#define SYSCON_NMISRC_IRQCPU1_MASK (0x3F00U) +#define SYSCON_NMISRC_IRQCPU1_SHIFT (8U) +#define SYSCON_NMISRC_IRQCPU1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQCPU1_SHIFT)) & SYSCON_NMISRC_IRQCPU1_MASK) +#define SYSCON_NMISRC_NMIENCPU1_MASK (0x40000000U) +#define SYSCON_NMISRC_NMIENCPU1_SHIFT (30U) +#define SYSCON_NMISRC_NMIENCPU1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIENCPU1_SHIFT)) & SYSCON_NMISRC_NMIENCPU1_MASK) +#define SYSCON_NMISRC_NMIENCPU0_MASK (0x80000000U) +#define SYSCON_NMISRC_NMIENCPU0_SHIFT (31U) +#define SYSCON_NMISRC_NMIENCPU0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIENCPU0_SHIFT)) & SYSCON_NMISRC_NMIENCPU0_MASK) +/*! @} */ + +/*! @name PRESETCTRL0 - Peripheral reset control 0 */ +/*! @{ */ +#define SYSCON_PRESETCTRL0_ROM_RST_MASK (0x2U) +#define SYSCON_PRESETCTRL0_ROM_RST_SHIFT (1U) +/*! ROM_RST - ROM reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_ROM_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_ROM_RST_SHIFT)) & SYSCON_PRESETCTRL0_ROM_RST_MASK) +#define SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_MASK (0x8U) +#define SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_SHIFT (3U) +/*! SRAM_CTRL1_RST - SRAM Controller 1 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_SRAM_CTRL1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_SHIFT)) & SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_MASK) +#define SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_MASK (0x10U) +#define SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_SHIFT (4U) +/*! SRAM_CTRL2_RST - SRAM Controller 2 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_SRAM_CTRL2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_SHIFT)) & SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_MASK) +#define SYSCON_PRESETCTRL0_SRAM_CTRL3_RST_MASK (0x20U) +#define SYSCON_PRESETCTRL0_SRAM_CTRL3_RST_SHIFT (5U) +/*! SRAM_CTRL3_RST - SRAM Controller 3 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_SRAM_CTRL3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SRAM_CTRL3_RST_SHIFT)) & SYSCON_PRESETCTRL0_SRAM_CTRL3_RST_MASK) +#define SYSCON_PRESETCTRL0_SRAM_CTRL4_RST_MASK (0x40U) +#define SYSCON_PRESETCTRL0_SRAM_CTRL4_RST_SHIFT (6U) +/*! SRAM_CTRL4_RST - SRAM Controller 4 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_SRAM_CTRL4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SRAM_CTRL4_RST_SHIFT)) & SYSCON_PRESETCTRL0_SRAM_CTRL4_RST_MASK) +#define SYSCON_PRESETCTRL0_FLASH_RST_MASK (0x80U) +#define SYSCON_PRESETCTRL0_FLASH_RST_SHIFT (7U) +/*! FLASH_RST - Flash controller reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_FLASH_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_FLASH_RST_SHIFT)) & SYSCON_PRESETCTRL0_FLASH_RST_MASK) +#define SYSCON_PRESETCTRL0_FMC_RST_MASK (0x100U) +#define SYSCON_PRESETCTRL0_FMC_RST_SHIFT (8U) +/*! FMC_RST - FMC controller reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_FMC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_FMC_RST_SHIFT)) & SYSCON_PRESETCTRL0_FMC_RST_MASK) +#define SYSCON_PRESETCTRL0_MUX0_RST_MASK (0x800U) +#define SYSCON_PRESETCTRL0_MUX0_RST_SHIFT (11U) +/*! MUX0_RST - Input Mux 0 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_MUX0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_MUX0_RST_SHIFT)) & SYSCON_PRESETCTRL0_MUX0_RST_MASK) +#define SYSCON_PRESETCTRL0_IOCON_RST_MASK (0x2000U) +#define SYSCON_PRESETCTRL0_IOCON_RST_SHIFT (13U) +/*! IOCON_RST - I/O controller reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_IOCON_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_IOCON_RST_SHIFT)) & SYSCON_PRESETCTRL0_IOCON_RST_MASK) +#define SYSCON_PRESETCTRL0_GPIO0_RST_MASK (0x4000U) +#define SYSCON_PRESETCTRL0_GPIO0_RST_SHIFT (14U) +/*! GPIO0_RST - GPIO0 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_GPIO0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO0_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO0_RST_MASK) +#define SYSCON_PRESETCTRL0_GPIO1_RST_MASK (0x8000U) +#define SYSCON_PRESETCTRL0_GPIO1_RST_SHIFT (15U) +/*! GPIO1_RST - GPIO1 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_GPIO1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO1_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO1_RST_MASK) +#define SYSCON_PRESETCTRL0_GPIO2_RST_MASK (0x10000U) +#define SYSCON_PRESETCTRL0_GPIO2_RST_SHIFT (16U) +/*! GPIO2_RST - GPIO2 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_GPIO2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO2_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO2_RST_MASK) +#define SYSCON_PRESETCTRL0_GPIO3_RST_MASK (0x20000U) +#define SYSCON_PRESETCTRL0_GPIO3_RST_SHIFT (17U) +/*! GPIO3_RST - GPIO3 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_GPIO3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO3_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO3_RST_MASK) +#define SYSCON_PRESETCTRL0_PINT_RST_MASK (0x40000U) +#define SYSCON_PRESETCTRL0_PINT_RST_SHIFT (18U) +/*! PINT_RST - Pin interrupt (PINT) reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_PINT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_PINT_RST_SHIFT)) & SYSCON_PRESETCTRL0_PINT_RST_MASK) +#define SYSCON_PRESETCTRL0_GINT_RST_MASK (0x80000U) +#define SYSCON_PRESETCTRL0_GINT_RST_SHIFT (19U) +/*! GINT_RST - Group interrupt (GINT) reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_GINT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GINT_RST_SHIFT)) & SYSCON_PRESETCTRL0_GINT_RST_MASK) +#define SYSCON_PRESETCTRL0_DMA0_RST_MASK (0x100000U) +#define SYSCON_PRESETCTRL0_DMA0_RST_SHIFT (20U) +/*! DMA0_RST - DMA0 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_DMA0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_DMA0_RST_SHIFT)) & SYSCON_PRESETCTRL0_DMA0_RST_MASK) +#define SYSCON_PRESETCTRL0_CRCGEN_RST_MASK (0x200000U) +#define SYSCON_PRESETCTRL0_CRCGEN_RST_SHIFT (21U) +/*! CRCGEN_RST - CRCGEN reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_CRCGEN_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_CRCGEN_RST_SHIFT)) & SYSCON_PRESETCTRL0_CRCGEN_RST_MASK) +#define SYSCON_PRESETCTRL0_WWDT_RST_MASK (0x400000U) +#define SYSCON_PRESETCTRL0_WWDT_RST_SHIFT (22U) +/*! WWDT_RST - Watchdog Timer reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_WWDT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_WWDT_RST_SHIFT)) & SYSCON_PRESETCTRL0_WWDT_RST_MASK) +#define SYSCON_PRESETCTRL0_RTC_RST_MASK (0x800000U) +#define SYSCON_PRESETCTRL0_RTC_RST_SHIFT (23U) +/*! RTC_RST - Real Time Clock (RTC) reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_RTC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_RTC_RST_SHIFT)) & SYSCON_PRESETCTRL0_RTC_RST_MASK) +#define SYSCON_PRESETCTRL0_MAILBOX_RST_MASK (0x4000000U) +#define SYSCON_PRESETCTRL0_MAILBOX_RST_SHIFT (26U) +/*! MAILBOX_RST - Inter CPU communication Mailbox reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_MAILBOX_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_MAILBOX_RST_SHIFT)) & SYSCON_PRESETCTRL0_MAILBOX_RST_MASK) +#define SYSCON_PRESETCTRL0_ADC_RST_MASK (0x8000000U) +#define SYSCON_PRESETCTRL0_ADC_RST_SHIFT (27U) +/*! ADC_RST - ADC reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_ADC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_ADC_RST_SHIFT)) & SYSCON_PRESETCTRL0_ADC_RST_MASK) +/*! @} */ + +/*! @name PRESETCTRL1 - Peripheral reset control 1 */ +/*! @{ */ +#define SYSCON_PRESETCTRL1_MRT_RST_MASK (0x1U) +#define SYSCON_PRESETCTRL1_MRT_RST_SHIFT (0U) +/*! MRT_RST - MRT reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_MRT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_MRT_RST_SHIFT)) & SYSCON_PRESETCTRL1_MRT_RST_MASK) +#define SYSCON_PRESETCTRL1_OSTIMER0_RST_MASK (0x2U) +#define SYSCON_PRESETCTRL1_OSTIMER0_RST_SHIFT (1U) +/*! OSTIMER0_RST - OS Timer 0 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_OSTIMER0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_OSTIMER0_RST_SHIFT)) & SYSCON_PRESETCTRL1_OSTIMER0_RST_MASK) +#define SYSCON_PRESETCTRL1_SCT0_RST_MASK (0x4U) +#define SYSCON_PRESETCTRL1_SCT0_RST_SHIFT (2U) +/*! SCT0_RST - SCT0 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_SCT0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_SCT0_RST_SHIFT)) & SYSCON_PRESETCTRL1_SCT0_RST_MASK) +#define SYSCON_PRESETCTRL1_SCTIPU_RST_MASK (0x40U) +#define SYSCON_PRESETCTRL1_SCTIPU_RST_SHIFT (6U) +/*! SCTIPU_RST - SCTIPU reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_SCTIPU_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_SCTIPU_RST_SHIFT)) & SYSCON_PRESETCTRL1_SCTIPU_RST_MASK) +#define SYSCON_PRESETCTRL1_UTICK0_RST_MASK (0x400U) +#define SYSCON_PRESETCTRL1_UTICK0_RST_SHIFT (10U) +/*! UTICK0_RST - UTICK0 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_UTICK0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_UTICK0_RST_SHIFT)) & SYSCON_PRESETCTRL1_UTICK0_RST_MASK) +#define SYSCON_PRESETCTRL1_FC0_RST_MASK (0x800U) +#define SYSCON_PRESETCTRL1_FC0_RST_SHIFT (11U) +/*! FC0_RST - FC0 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_FC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC0_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC0_RST_MASK) +#define SYSCON_PRESETCTRL1_FC1_RST_MASK (0x1000U) +#define SYSCON_PRESETCTRL1_FC1_RST_SHIFT (12U) +/*! FC1_RST - FC1 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_FC1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC1_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC1_RST_MASK) +#define SYSCON_PRESETCTRL1_FC2_RST_MASK (0x2000U) +#define SYSCON_PRESETCTRL1_FC2_RST_SHIFT (13U) +/*! FC2_RST - FC2 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_FC2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC2_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC2_RST_MASK) +#define SYSCON_PRESETCTRL1_FC3_RST_MASK (0x4000U) +#define SYSCON_PRESETCTRL1_FC3_RST_SHIFT (14U) +/*! FC3_RST - FC3 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_FC3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC3_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC3_RST_MASK) +#define SYSCON_PRESETCTRL1_FC4_RST_MASK (0x8000U) +#define SYSCON_PRESETCTRL1_FC4_RST_SHIFT (15U) +/*! FC4_RST - FC4 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_FC4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC4_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC4_RST_MASK) +#define SYSCON_PRESETCTRL1_FC5_RST_MASK (0x10000U) +#define SYSCON_PRESETCTRL1_FC5_RST_SHIFT (16U) +/*! FC5_RST - FC5 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_FC5_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC5_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC5_RST_MASK) +#define SYSCON_PRESETCTRL1_FC6_RST_MASK (0x20000U) +#define SYSCON_PRESETCTRL1_FC6_RST_SHIFT (17U) +/*! FC6_RST - FC6 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_FC6_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC6_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC6_RST_MASK) +#define SYSCON_PRESETCTRL1_FC7_RST_MASK (0x40000U) +#define SYSCON_PRESETCTRL1_FC7_RST_SHIFT (18U) +/*! FC7_RST - FC7 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_FC7_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC7_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC7_RST_MASK) +#define SYSCON_PRESETCTRL1_TIMER2_RST_MASK (0x400000U) +#define SYSCON_PRESETCTRL1_TIMER2_RST_SHIFT (22U) +/*! TIMER2_RST - Timer 2 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_TIMER2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_TIMER2_RST_SHIFT)) & SYSCON_PRESETCTRL1_TIMER2_RST_MASK) +#define SYSCON_PRESETCTRL1_USB0_DEV_RST_MASK (0x2000000U) +#define SYSCON_PRESETCTRL1_USB0_DEV_RST_SHIFT (25U) +/*! USB0_DEV_RST - USB0 DEV reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_USB0_DEV_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_USB0_DEV_RST_SHIFT)) & SYSCON_PRESETCTRL1_USB0_DEV_RST_MASK) +#define SYSCON_PRESETCTRL1_TIMER0_RST_MASK (0x4000000U) +#define SYSCON_PRESETCTRL1_TIMER0_RST_SHIFT (26U) +/*! TIMER0_RST - Timer 0 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_TIMER0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_TIMER0_RST_SHIFT)) & SYSCON_PRESETCTRL1_TIMER0_RST_MASK) +#define SYSCON_PRESETCTRL1_TIMER1_RST_MASK (0x8000000U) +#define SYSCON_PRESETCTRL1_TIMER1_RST_SHIFT (27U) +/*! TIMER1_RST - Timer 1 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_TIMER1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_TIMER1_RST_SHIFT)) & SYSCON_PRESETCTRL1_TIMER1_RST_MASK) +#define SYSCON_PRESETCTRL1_PVT_RST_MASK (0x10000000U) +#define SYSCON_PRESETCTRL1_PVT_RST_SHIFT (28U) +/*! PVT_RST - PVT reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_PVT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_PVT_RST_SHIFT)) & SYSCON_PRESETCTRL1_PVT_RST_MASK) +#define SYSCON_PRESETCTRL1_EZHA_RST_MASK (0x40000000U) +#define SYSCON_PRESETCTRL1_EZHA_RST_SHIFT (30U) +/*! EZHA_RST - EZH a reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_EZHA_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_EZHA_RST_SHIFT)) & SYSCON_PRESETCTRL1_EZHA_RST_MASK) +#define SYSCON_PRESETCTRL1_EZHB_RST_MASK (0x80000000U) +#define SYSCON_PRESETCTRL1_EZHB_RST_SHIFT (31U) +/*! EZHB_RST - EZH b reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_EZHB_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_EZHB_RST_SHIFT)) & SYSCON_PRESETCTRL1_EZHB_RST_MASK) +/*! @} */ + +/*! @name PRESETCTRL2 - Peripheral reset control 2 */ +/*! @{ */ +#define SYSCON_PRESETCTRL2_DMA1_RST_MASK (0x2U) +#define SYSCON_PRESETCTRL2_DMA1_RST_SHIFT (1U) +/*! DMA1_RST - DMA1 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_DMA1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_DMA1_RST_SHIFT)) & SYSCON_PRESETCTRL2_DMA1_RST_MASK) +#define SYSCON_PRESETCTRL2_COMP_RST_MASK (0x4U) +#define SYSCON_PRESETCTRL2_COMP_RST_SHIFT (2U) +/*! COMP_RST - Comparator reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_COMP_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_COMP_RST_SHIFT)) & SYSCON_PRESETCTRL2_COMP_RST_MASK) +#define SYSCON_PRESETCTRL2_SDIO_RST_MASK (0x8U) +#define SYSCON_PRESETCTRL2_SDIO_RST_SHIFT (3U) +/*! SDIO_RST - SDIO reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_SDIO_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_SDIO_RST_SHIFT)) & SYSCON_PRESETCTRL2_SDIO_RST_MASK) +#define SYSCON_PRESETCTRL2_USB1_HOST_RST_MASK (0x10U) +#define SYSCON_PRESETCTRL2_USB1_HOST_RST_SHIFT (4U) +/*! USB1_HOST_RST - USB1 Host reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_USB1_HOST_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB1_HOST_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB1_HOST_RST_MASK) +#define SYSCON_PRESETCTRL2_USB1_DEV_RST_MASK (0x20U) +#define SYSCON_PRESETCTRL2_USB1_DEV_RST_SHIFT (5U) +/*! USB1_DEV_RST - USB1 dev reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_USB1_DEV_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB1_DEV_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB1_DEV_RST_MASK) +#define SYSCON_PRESETCTRL2_USB1_RAM_RST_MASK (0x40U) +#define SYSCON_PRESETCTRL2_USB1_RAM_RST_SHIFT (6U) +/*! USB1_RAM_RST - USB1 RAM reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_USB1_RAM_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB1_RAM_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB1_RAM_RST_MASK) +#define SYSCON_PRESETCTRL2_USB1_PHY_RST_MASK (0x80U) +#define SYSCON_PRESETCTRL2_USB1_PHY_RST_SHIFT (7U) +/*! USB1_PHY_RST - USB1 PHY reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_USB1_PHY_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB1_PHY_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB1_PHY_RST_MASK) +#define SYSCON_PRESETCTRL2_FREQME_RST_MASK (0x100U) +#define SYSCON_PRESETCTRL2_FREQME_RST_SHIFT (8U) +/*! FREQME_RST - Frequency meter reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_FREQME_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_FREQME_RST_SHIFT)) & SYSCON_PRESETCTRL2_FREQME_RST_MASK) +#define SYSCON_PRESETCTRL2_GPIO4_RST_MASK (0x200U) +#define SYSCON_PRESETCTRL2_GPIO4_RST_SHIFT (9U) +/*! GPIO4_RST - GPIO4 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_GPIO4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_GPIO4_RST_SHIFT)) & SYSCON_PRESETCTRL2_GPIO4_RST_MASK) +#define SYSCON_PRESETCTRL2_GPIO5_RST_MASK (0x400U) +#define SYSCON_PRESETCTRL2_GPIO5_RST_SHIFT (10U) +/*! GPIO5_RST - GPIO5 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_GPIO5_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_GPIO5_RST_SHIFT)) & SYSCON_PRESETCTRL2_GPIO5_RST_MASK) +#define SYSCON_PRESETCTRL2_OTP_RST_MASK (0x1000U) +#define SYSCON_PRESETCTRL2_OTP_RST_SHIFT (12U) +/*! OTP_RST - OTP reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_OTP_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_OTP_RST_SHIFT)) & SYSCON_PRESETCTRL2_OTP_RST_MASK) +#define SYSCON_PRESETCTRL2_RNG_RST_MASK (0x2000U) +#define SYSCON_PRESETCTRL2_RNG_RST_SHIFT (13U) +/*! RNG_RST - RNG reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_RNG_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_RNG_RST_SHIFT)) & SYSCON_PRESETCTRL2_RNG_RST_MASK) +#define SYSCON_PRESETCTRL2_MUX1_RST_MASK (0x4000U) +#define SYSCON_PRESETCTRL2_MUX1_RST_SHIFT (14U) +/*! MUX1_RST - Peripheral Input Mux 1 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_MUX1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_MUX1_RST_SHIFT)) & SYSCON_PRESETCTRL2_MUX1_RST_MASK) +#define SYSCON_PRESETCTRL2_USB0_HOSTM_RST_MASK (0x10000U) +#define SYSCON_PRESETCTRL2_USB0_HOSTM_RST_SHIFT (16U) +/*! USB0_HOSTM_RST - USB0 Host Master reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_USB0_HOSTM_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB0_HOSTM_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB0_HOSTM_RST_MASK) +#define SYSCON_PRESETCTRL2_USB0_HOSTS_RST_MASK (0x20000U) +#define SYSCON_PRESETCTRL2_USB0_HOSTS_RST_SHIFT (17U) +/*! USB0_HOSTS_RST - USB0 Host Slave reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_USB0_HOSTS_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB0_HOSTS_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB0_HOSTS_RST_MASK) +#define SYSCON_PRESETCTRL2_HASH0_RST_MASK (0x40000U) +#define SYSCON_PRESETCTRL2_HASH0_RST_SHIFT (18U) +/*! HASH0_RST - HASH0 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_HASH0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_HASH0_RST_SHIFT)) & SYSCON_PRESETCTRL2_HASH0_RST_MASK) +#define SYSCON_PRESETCTRL2_PQ_RST_MASK (0x80000U) +#define SYSCON_PRESETCTRL2_PQ_RST_SHIFT (19U) +/*! PQ_RST - Power Quad reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_PQ_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_PQ_RST_SHIFT)) & SYSCON_PRESETCTRL2_PQ_RST_MASK) +#define SYSCON_PRESETCTRL2_PLULUT_RST_MASK (0x100000U) +#define SYSCON_PRESETCTRL2_PLULUT_RST_SHIFT (20U) +/*! PLULUT_RST - PLU LUT reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_PLULUT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_PLULUT_RST_SHIFT)) & SYSCON_PRESETCTRL2_PLULUT_RST_MASK) +#define SYSCON_PRESETCTRL2_TIMER3_RST_MASK (0x200000U) +#define SYSCON_PRESETCTRL2_TIMER3_RST_SHIFT (21U) +/*! TIMER3_RST - Timer 3 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_TIMER3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_TIMER3_RST_SHIFT)) & SYSCON_PRESETCTRL2_TIMER3_RST_MASK) +#define SYSCON_PRESETCTRL2_TIMER4_RST_MASK (0x400000U) +#define SYSCON_PRESETCTRL2_TIMER4_RST_SHIFT (22U) +/*! TIMER4_RST - Timer 4 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_TIMER4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_TIMER4_RST_SHIFT)) & SYSCON_PRESETCTRL2_TIMER4_RST_MASK) +#define SYSCON_PRESETCTRL2_PUF_RST_MASK (0x800000U) +#define SYSCON_PRESETCTRL2_PUF_RST_SHIFT (23U) +/*! PUF_RST - PUF reset control reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_PUF_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_PUF_RST_SHIFT)) & SYSCON_PRESETCTRL2_PUF_RST_MASK) +#define SYSCON_PRESETCTRL2_CASPER_RST_MASK (0x1000000U) +#define SYSCON_PRESETCTRL2_CASPER_RST_SHIFT (24U) +/*! CASPER_RST - Casper reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_CASPER_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_CASPER_RST_SHIFT)) & SYSCON_PRESETCTRL2_CASPER_RST_MASK) +#define SYSCON_PRESETCTRL2_CAPT0_RST_MASK (0x2000000U) +#define SYSCON_PRESETCTRL2_CAPT0_RST_SHIFT (25U) +/*! CAPT0_RST - CAPT0 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_CAPT0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_CAPT0_RST_SHIFT)) & SYSCON_PRESETCTRL2_CAPT0_RST_MASK) +#define SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_MASK (0x8000000U) +#define SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_SHIFT (27U) +/*! ANALOG_CTRL_RST - analog control reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_ANALOG_CTRL_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_SHIFT)) & SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_MASK) +#define SYSCON_PRESETCTRL2_HS_LSPI_RST_MASK (0x10000000U) +#define SYSCON_PRESETCTRL2_HS_LSPI_RST_SHIFT (28U) +/*! HS_LSPI_RST - HS LSPI reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_HS_LSPI_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_HS_LSPI_RST_SHIFT)) & SYSCON_PRESETCTRL2_HS_LSPI_RST_MASK) +#define SYSCON_PRESETCTRL2_GPIO_SEC_RST_MASK (0x20000000U) +#define SYSCON_PRESETCTRL2_GPIO_SEC_RST_SHIFT (29U) +/*! GPIO_SEC_RST - GPIO secure reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_GPIO_SEC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_GPIO_SEC_RST_SHIFT)) & SYSCON_PRESETCTRL2_GPIO_SEC_RST_MASK) +#define SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST_MASK (0x40000000U) +#define SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST_SHIFT (30U) +/*! GPIO_SEC_INT_RST - GPIO secure int reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST_SHIFT)) & SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST_MASK) +/*! @} */ + +/*! @name PRESETCTRLX - Peripheral reset control register */ +/*! @{ */ +#define SYSCON_PRESETCTRLX_DATA_MASK (0xFFFFFFFFU) +#define SYSCON_PRESETCTRLX_DATA_SHIFT (0U) +#define SYSCON_PRESETCTRLX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLX_DATA_SHIFT)) & SYSCON_PRESETCTRLX_DATA_MASK) +/*! @} */ + +/* The count of SYSCON_PRESETCTRLX */ +#define SYSCON_PRESETCTRLX_COUNT (3U) + +/*! @name PRESETCTRLSET - Peripheral reset control set register */ +/*! @{ */ +#define SYSCON_PRESETCTRLSET_DATA_MASK (0xFFFFFFFFU) +#define SYSCON_PRESETCTRLSET_DATA_SHIFT (0U) +#define SYSCON_PRESETCTRLSET_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLSET_DATA_SHIFT)) & SYSCON_PRESETCTRLSET_DATA_MASK) +/*! @} */ + +/* The count of SYSCON_PRESETCTRLSET */ +#define SYSCON_PRESETCTRLSET_COUNT (3U) + +/*! @name PRESETCTRLCLR - Peripheral reset contro clearl register */ +/*! @{ */ +#define SYSCON_PRESETCTRLCLR_DATA_MASK (0xFFFFFFFFU) +#define SYSCON_PRESETCTRLCLR_DATA_SHIFT (0U) +#define SYSCON_PRESETCTRLCLR_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLCLR_DATA_SHIFT)) & SYSCON_PRESETCTRLCLR_DATA_MASK) +/*! @} */ + +/* The count of SYSCON_PRESETCTRLCLR */ +#define SYSCON_PRESETCTRLCLR_COUNT (3U) + +/*! @name SWR_RESET - generate a software_reset */ +/*! @{ */ +#define SYSCON_SWR_RESET_SWR_RESET_MASK (0xFFFFFFFFU) +#define SYSCON_SWR_RESET_SWR_RESET_SHIFT (0U) +/*! SWR_RESET - Write 0x5A00_0001 to generate a software_reset. + * 0b01011010000000000000000000000001..Generate a software reset. + * 0b00000000000000000000000000000000..Bloc is not reset. + */ +#define SYSCON_SWR_RESET_SWR_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SWR_RESET_SWR_RESET_SHIFT)) & SYSCON_SWR_RESET_SWR_RESET_MASK) +/*! @} */ + +/*! @name AHBCLKCTRL0 - AHB Clock control 0 */ +/*! @{ */ +#define SYSCON_AHBCLKCTRL0_ROM_MASK (0x2U) +#define SYSCON_AHBCLKCTRL0_ROM_SHIFT (1U) +/*! ROM - Enables the clock for the ROM. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_ROM_SHIFT)) & SYSCON_AHBCLKCTRL0_ROM_MASK) +#define SYSCON_AHBCLKCTRL0_SRAM_CTRL1_MASK (0x8U) +#define SYSCON_AHBCLKCTRL0_SRAM_CTRL1_SHIFT (3U) +/*! SRAM_CTRL1 - Enables the clock for the SRAM Controller 1. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_SRAM_CTRL1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL1_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL1_MASK) +#define SYSCON_AHBCLKCTRL0_SRAM_CTRL2_MASK (0x10U) +#define SYSCON_AHBCLKCTRL0_SRAM_CTRL2_SHIFT (4U) +/*! SRAM_CTRL2 - Enables the clock for the SRAM Controller 2. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_SRAM_CTRL2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL2_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL2_MASK) +#define SYSCON_AHBCLKCTRL0_SRAM_CTRL3_MASK (0x20U) +#define SYSCON_AHBCLKCTRL0_SRAM_CTRL3_SHIFT (5U) +/*! SRAM_CTRL3 - Enables the clock for the SRAM Controller 3. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_SRAM_CTRL3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL3_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL3_MASK) +#define SYSCON_AHBCLKCTRL0_SRAM_CTRL4_MASK (0x40U) +#define SYSCON_AHBCLKCTRL0_SRAM_CTRL4_SHIFT (6U) +/*! SRAM_CTRL4 - Enables the clock for the SRAM Controller 4. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_SRAM_CTRL4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL4_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL4_MASK) +#define SYSCON_AHBCLKCTRL0_FLASH_MASK (0x80U) +#define SYSCON_AHBCLKCTRL0_FLASH_SHIFT (7U) +/*! FLASH - Enables the clock for the Flash controller. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_FLASH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_FLASH_SHIFT)) & SYSCON_AHBCLKCTRL0_FLASH_MASK) +#define SYSCON_AHBCLKCTRL0_FMC_MASK (0x100U) +#define SYSCON_AHBCLKCTRL0_FMC_SHIFT (8U) +/*! FMC - Enables the clock for the FMC controller. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_FMC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_FMC_SHIFT)) & SYSCON_AHBCLKCTRL0_FMC_MASK) +#define SYSCON_AHBCLKCTRL0_MUX0_MASK (0x800U) +#define SYSCON_AHBCLKCTRL0_MUX0_SHIFT (11U) +/*! MUX0 - Enables the clock for the Input Mux 0. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_MUX0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_MUX0_SHIFT)) & SYSCON_AHBCLKCTRL0_MUX0_MASK) +#define SYSCON_AHBCLKCTRL0_IOCON_MASK (0x2000U) +#define SYSCON_AHBCLKCTRL0_IOCON_SHIFT (13U) +/*! IOCON - Enables the clock for the I/O controller. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_IOCON(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_IOCON_SHIFT)) & SYSCON_AHBCLKCTRL0_IOCON_MASK) +#define SYSCON_AHBCLKCTRL0_GPIO0_MASK (0x4000U) +#define SYSCON_AHBCLKCTRL0_GPIO0_SHIFT (14U) +/*! GPIO0 - Enables the clock for the GPIO0. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_GPIO0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO0_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO0_MASK) +#define SYSCON_AHBCLKCTRL0_GPIO1_MASK (0x8000U) +#define SYSCON_AHBCLKCTRL0_GPIO1_SHIFT (15U) +/*! GPIO1 - Enables the clock for the GPIO1. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_GPIO1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO1_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO1_MASK) +#define SYSCON_AHBCLKCTRL0_GPIO2_MASK (0x10000U) +#define SYSCON_AHBCLKCTRL0_GPIO2_SHIFT (16U) +/*! GPIO2 - Enables the clock for the GPIO2. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_GPIO2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO2_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO2_MASK) +#define SYSCON_AHBCLKCTRL0_GPIO3_MASK (0x20000U) +#define SYSCON_AHBCLKCTRL0_GPIO3_SHIFT (17U) +/*! GPIO3 - Enables the clock for the GPIO3. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_GPIO3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO3_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO3_MASK) +#define SYSCON_AHBCLKCTRL0_PINT_MASK (0x40000U) +#define SYSCON_AHBCLKCTRL0_PINT_SHIFT (18U) +/*! PINT - Enables the clock for the Pin interrupt (PINT). + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_PINT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_PINT_SHIFT)) & SYSCON_AHBCLKCTRL0_PINT_MASK) +#define SYSCON_AHBCLKCTRL0_GINT_MASK (0x80000U) +#define SYSCON_AHBCLKCTRL0_GINT_SHIFT (19U) +/*! GINT - Enables the clock for the Group interrupt (GINT). + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_GINT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GINT_SHIFT)) & SYSCON_AHBCLKCTRL0_GINT_MASK) +#define SYSCON_AHBCLKCTRL0_DMA0_MASK (0x100000U) +#define SYSCON_AHBCLKCTRL0_DMA0_SHIFT (20U) +/*! DMA0 - Enables the clock for the DMA0. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_DMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_DMA0_SHIFT)) & SYSCON_AHBCLKCTRL0_DMA0_MASK) +#define SYSCON_AHBCLKCTRL0_CRCGEN_MASK (0x200000U) +#define SYSCON_AHBCLKCTRL0_CRCGEN_SHIFT (21U) +/*! CRCGEN - Enables the clock for the CRCGEN. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_CRCGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_CRCGEN_SHIFT)) & SYSCON_AHBCLKCTRL0_CRCGEN_MASK) +#define SYSCON_AHBCLKCTRL0_WWDT_MASK (0x400000U) +#define SYSCON_AHBCLKCTRL0_WWDT_SHIFT (22U) +/*! WWDT - Enables the clock for the Watchdog Timer. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_WWDT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_WWDT_SHIFT)) & SYSCON_AHBCLKCTRL0_WWDT_MASK) +#define SYSCON_AHBCLKCTRL0_RTC_MASK (0x800000U) +#define SYSCON_AHBCLKCTRL0_RTC_SHIFT (23U) +/*! RTC - Enables the clock for the Real Time Clock (RTC). + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_RTC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_RTC_SHIFT)) & SYSCON_AHBCLKCTRL0_RTC_MASK) +#define SYSCON_AHBCLKCTRL0_MAILBOX_MASK (0x4000000U) +#define SYSCON_AHBCLKCTRL0_MAILBOX_SHIFT (26U) +/*! MAILBOX - Enables the clock for the Inter CPU communication Mailbox. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_MAILBOX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_MAILBOX_SHIFT)) & SYSCON_AHBCLKCTRL0_MAILBOX_MASK) +#define SYSCON_AHBCLKCTRL0_ADC_MASK (0x8000000U) +#define SYSCON_AHBCLKCTRL0_ADC_SHIFT (27U) +/*! ADC - Enables the clock for the ADC. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_ADC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_ADC_SHIFT)) & SYSCON_AHBCLKCTRL0_ADC_MASK) +/*! @} */ + +/*! @name AHBCLKCTRL1 - AHB Clock control 1 */ +/*! @{ */ +#define SYSCON_AHBCLKCTRL1_MRT_MASK (0x1U) +#define SYSCON_AHBCLKCTRL1_MRT_SHIFT (0U) +/*! MRT - Enables the clock for the MRT. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_MRT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_MRT_SHIFT)) & SYSCON_AHBCLKCTRL1_MRT_MASK) +#define SYSCON_AHBCLKCTRL1_OSTIMER0_MASK (0x2U) +#define SYSCON_AHBCLKCTRL1_OSTIMER0_SHIFT (1U) +/*! OSTIMER0 - Enables the clock for the OS Timer 0. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_OSTIMER0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_OSTIMER0_SHIFT)) & SYSCON_AHBCLKCTRL1_OSTIMER0_MASK) +#define SYSCON_AHBCLKCTRL1_SCT0_MASK (0x4U) +#define SYSCON_AHBCLKCTRL1_SCT0_SHIFT (2U) +/*! SCT0 - Enables the clock for the SCT0. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_SCT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_SCT0_SHIFT)) & SYSCON_AHBCLKCTRL1_SCT0_MASK) +#define SYSCON_AHBCLKCTRL1_SCTIPU_MASK (0x40U) +#define SYSCON_AHBCLKCTRL1_SCTIPU_SHIFT (6U) +/*! SCTIPU - Enables the clock for the SCTIPU. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_SCTIPU(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_SCTIPU_SHIFT)) & SYSCON_AHBCLKCTRL1_SCTIPU_MASK) +#define SYSCON_AHBCLKCTRL1_UTICK0_MASK (0x400U) +#define SYSCON_AHBCLKCTRL1_UTICK0_SHIFT (10U) +/*! UTICK0 - Enables the clock for the UTICK0. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_UTICK0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_UTICK0_SHIFT)) & SYSCON_AHBCLKCTRL1_UTICK0_MASK) +#define SYSCON_AHBCLKCTRL1_FC0_MASK (0x800U) +#define SYSCON_AHBCLKCTRL1_FC0_SHIFT (11U) +/*! FC0 - Enables the clock for the FC0. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_FC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC0_SHIFT)) & SYSCON_AHBCLKCTRL1_FC0_MASK) +#define SYSCON_AHBCLKCTRL1_FC1_MASK (0x1000U) +#define SYSCON_AHBCLKCTRL1_FC1_SHIFT (12U) +/*! FC1 - Enables the clock for the FC1. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_FC1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC1_SHIFT)) & SYSCON_AHBCLKCTRL1_FC1_MASK) +#define SYSCON_AHBCLKCTRL1_FC2_MASK (0x2000U) +#define SYSCON_AHBCLKCTRL1_FC2_SHIFT (13U) +/*! FC2 - Enables the clock for the FC2. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_FC2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC2_SHIFT)) & SYSCON_AHBCLKCTRL1_FC2_MASK) +#define SYSCON_AHBCLKCTRL1_FC3_MASK (0x4000U) +#define SYSCON_AHBCLKCTRL1_FC3_SHIFT (14U) +/*! FC3 - Enables the clock for the FC3. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_FC3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC3_SHIFT)) & SYSCON_AHBCLKCTRL1_FC3_MASK) +#define SYSCON_AHBCLKCTRL1_FC4_MASK (0x8000U) +#define SYSCON_AHBCLKCTRL1_FC4_SHIFT (15U) +/*! FC4 - Enables the clock for the FC4. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_FC4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC4_SHIFT)) & SYSCON_AHBCLKCTRL1_FC4_MASK) +#define SYSCON_AHBCLKCTRL1_FC5_MASK (0x10000U) +#define SYSCON_AHBCLKCTRL1_FC5_SHIFT (16U) +/*! FC5 - Enables the clock for the FC5. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_FC5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC5_SHIFT)) & SYSCON_AHBCLKCTRL1_FC5_MASK) +#define SYSCON_AHBCLKCTRL1_FC6_MASK (0x20000U) +#define SYSCON_AHBCLKCTRL1_FC6_SHIFT (17U) +/*! FC6 - Enables the clock for the FC6. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_FC6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC6_SHIFT)) & SYSCON_AHBCLKCTRL1_FC6_MASK) +#define SYSCON_AHBCLKCTRL1_FC7_MASK (0x40000U) +#define SYSCON_AHBCLKCTRL1_FC7_SHIFT (18U) +/*! FC7 - Enables the clock for the FC7. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_FC7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC7_SHIFT)) & SYSCON_AHBCLKCTRL1_FC7_MASK) +#define SYSCON_AHBCLKCTRL1_TIMER2_MASK (0x400000U) +#define SYSCON_AHBCLKCTRL1_TIMER2_SHIFT (22U) +/*! TIMER2 - Enables the clock for the Timer 2. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_TIMER2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_TIMER2_SHIFT)) & SYSCON_AHBCLKCTRL1_TIMER2_MASK) +#define SYSCON_AHBCLKCTRL1_USB0_DEV_MASK (0x2000000U) +#define SYSCON_AHBCLKCTRL1_USB0_DEV_SHIFT (25U) +/*! USB0_DEV - Enables the clock for the USB0 DEV. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_USB0_DEV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_USB0_DEV_SHIFT)) & SYSCON_AHBCLKCTRL1_USB0_DEV_MASK) +#define SYSCON_AHBCLKCTRL1_TIMER0_MASK (0x4000000U) +#define SYSCON_AHBCLKCTRL1_TIMER0_SHIFT (26U) +/*! TIMER0 - Enables the clock for the Timer 0. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_TIMER0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_TIMER0_SHIFT)) & SYSCON_AHBCLKCTRL1_TIMER0_MASK) +#define SYSCON_AHBCLKCTRL1_TIMER1_MASK (0x8000000U) +#define SYSCON_AHBCLKCTRL1_TIMER1_SHIFT (27U) +/*! TIMER1 - Enables the clock for the Timer 1. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_TIMER1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_TIMER1_SHIFT)) & SYSCON_AHBCLKCTRL1_TIMER1_MASK) +#define SYSCON_AHBCLKCTRL1_PVT_MASK (0x10000000U) +#define SYSCON_AHBCLKCTRL1_PVT_SHIFT (28U) +/*! PVT - Enables the clock for the PVT. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_PVT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_PVT_SHIFT)) & SYSCON_AHBCLKCTRL1_PVT_MASK) +#define SYSCON_AHBCLKCTRL1_EZHA_MASK (0x40000000U) +#define SYSCON_AHBCLKCTRL1_EZHA_SHIFT (30U) +/*! EZHA - Enables the clock for the EZH a. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_EZHA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_EZHA_SHIFT)) & SYSCON_AHBCLKCTRL1_EZHA_MASK) +#define SYSCON_AHBCLKCTRL1_EZHB_MASK (0x80000000U) +#define SYSCON_AHBCLKCTRL1_EZHB_SHIFT (31U) +/*! EZHB - Enables the clock for the EZH b. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_EZHB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_EZHB_SHIFT)) & SYSCON_AHBCLKCTRL1_EZHB_MASK) +/*! @} */ + +/*! @name AHBCLKCTRL2 - AHB Clock control 2 */ +/*! @{ */ +#define SYSCON_AHBCLKCTRL2_DMA1_MASK (0x2U) +#define SYSCON_AHBCLKCTRL2_DMA1_SHIFT (1U) +/*! DMA1 - Enables the clock for the DMA1. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_DMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_DMA1_SHIFT)) & SYSCON_AHBCLKCTRL2_DMA1_MASK) +#define SYSCON_AHBCLKCTRL2_COMP_MASK (0x4U) +#define SYSCON_AHBCLKCTRL2_COMP_SHIFT (2U) +/*! COMP - Enables the clock for the Comparator. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_COMP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_COMP_SHIFT)) & SYSCON_AHBCLKCTRL2_COMP_MASK) +#define SYSCON_AHBCLKCTRL2_SDIO_MASK (0x8U) +#define SYSCON_AHBCLKCTRL2_SDIO_SHIFT (3U) +/*! SDIO - Enables the clock for the SDIO. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_SDIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_SDIO_SHIFT)) & SYSCON_AHBCLKCTRL2_SDIO_MASK) +#define SYSCON_AHBCLKCTRL2_USB1_HOST_MASK (0x10U) +#define SYSCON_AHBCLKCTRL2_USB1_HOST_SHIFT (4U) +/*! USB1_HOST - Enables the clock for the USB1 Host. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_USB1_HOST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB1_HOST_SHIFT)) & SYSCON_AHBCLKCTRL2_USB1_HOST_MASK) +#define SYSCON_AHBCLKCTRL2_USB1_DEV_MASK (0x20U) +#define SYSCON_AHBCLKCTRL2_USB1_DEV_SHIFT (5U) +/*! USB1_DEV - Enables the clock for the USB1 dev. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_USB1_DEV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB1_DEV_SHIFT)) & SYSCON_AHBCLKCTRL2_USB1_DEV_MASK) +#define SYSCON_AHBCLKCTRL2_USB1_RAM_MASK (0x40U) +#define SYSCON_AHBCLKCTRL2_USB1_RAM_SHIFT (6U) +/*! USB1_RAM - Enables the clock for the USB1 RAM. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_USB1_RAM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB1_RAM_SHIFT)) & SYSCON_AHBCLKCTRL2_USB1_RAM_MASK) +#define SYSCON_AHBCLKCTRL2_USB1_PHY_MASK (0x80U) +#define SYSCON_AHBCLKCTRL2_USB1_PHY_SHIFT (7U) +/*! USB1_PHY - Enables the clock for the USB1 PHY. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_USB1_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB1_PHY_SHIFT)) & SYSCON_AHBCLKCTRL2_USB1_PHY_MASK) +#define SYSCON_AHBCLKCTRL2_FREQME_MASK (0x100U) +#define SYSCON_AHBCLKCTRL2_FREQME_SHIFT (8U) +/*! FREQME - Enables the clock for the Frequency meter. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_FREQME(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_FREQME_SHIFT)) & SYSCON_AHBCLKCTRL2_FREQME_MASK) +#define SYSCON_AHBCLKCTRL2_GPIO4_MASK (0x200U) +#define SYSCON_AHBCLKCTRL2_GPIO4_SHIFT (9U) +/*! GPIO4 - Enables the clock for the GPIO4. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_GPIO4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_GPIO4_SHIFT)) & SYSCON_AHBCLKCTRL2_GPIO4_MASK) +#define SYSCON_AHBCLKCTRL2_GPIO5_MASK (0x400U) +#define SYSCON_AHBCLKCTRL2_GPIO5_SHIFT (10U) +/*! GPIO5 - Enables the clock for the GPIO5. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_GPIO5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_GPIO5_SHIFT)) & SYSCON_AHBCLKCTRL2_GPIO5_MASK) +#define SYSCON_AHBCLKCTRL2_OTP_MASK (0x1000U) +#define SYSCON_AHBCLKCTRL2_OTP_SHIFT (12U) +/*! OTP - Enables the clock for the OTP. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_OTP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_OTP_SHIFT)) & SYSCON_AHBCLKCTRL2_OTP_MASK) +#define SYSCON_AHBCLKCTRL2_RNG_MASK (0x2000U) +#define SYSCON_AHBCLKCTRL2_RNG_SHIFT (13U) +/*! RNG - Enables the clock for the RNG. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_RNG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_RNG_SHIFT)) & SYSCON_AHBCLKCTRL2_RNG_MASK) +#define SYSCON_AHBCLKCTRL2_MUX1_MASK (0x4000U) +#define SYSCON_AHBCLKCTRL2_MUX1_SHIFT (14U) +/*! MUX1 - Enables the clock for the Peripheral Input Mux 1. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_MUX1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_MUX1_SHIFT)) & SYSCON_AHBCLKCTRL2_MUX1_MASK) +#define SYSCON_AHBCLKCTRL2_USB0_HOSTM_MASK (0x10000U) +#define SYSCON_AHBCLKCTRL2_USB0_HOSTM_SHIFT (16U) +/*! USB0_HOSTM - Enables the clock for the USB0 Host Master. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_USB0_HOSTM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB0_HOSTM_SHIFT)) & SYSCON_AHBCLKCTRL2_USB0_HOSTM_MASK) +#define SYSCON_AHBCLKCTRL2_USB0_HOSTS_MASK (0x20000U) +#define SYSCON_AHBCLKCTRL2_USB0_HOSTS_SHIFT (17U) +/*! USB0_HOSTS - Enables the clock for the USB0 Host Slave. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_USB0_HOSTS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB0_HOSTS_SHIFT)) & SYSCON_AHBCLKCTRL2_USB0_HOSTS_MASK) +#define SYSCON_AHBCLKCTRL2_HASH0_MASK (0x40000U) +#define SYSCON_AHBCLKCTRL2_HASH0_SHIFT (18U) +/*! HASH0 - Enables the clock for the HASH0. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_HASH0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_HASH0_SHIFT)) & SYSCON_AHBCLKCTRL2_HASH0_MASK) +#define SYSCON_AHBCLKCTRL2_PQ_MASK (0x80000U) +#define SYSCON_AHBCLKCTRL2_PQ_SHIFT (19U) +/*! PQ - Enables the clock for the Power Quad. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_PQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_PQ_SHIFT)) & SYSCON_AHBCLKCTRL2_PQ_MASK) +#define SYSCON_AHBCLKCTRL2_PLULUT_MASK (0x100000U) +#define SYSCON_AHBCLKCTRL2_PLULUT_SHIFT (20U) +/*! PLULUT - Enables the clock for the PLU LUT. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_PLULUT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_PLULUT_SHIFT)) & SYSCON_AHBCLKCTRL2_PLULUT_MASK) +#define SYSCON_AHBCLKCTRL2_TIMER3_MASK (0x200000U) +#define SYSCON_AHBCLKCTRL2_TIMER3_SHIFT (21U) +/*! TIMER3 - Enables the clock for the Timer 3. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_TIMER3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_TIMER3_SHIFT)) & SYSCON_AHBCLKCTRL2_TIMER3_MASK) +#define SYSCON_AHBCLKCTRL2_TIMER4_MASK (0x400000U) +#define SYSCON_AHBCLKCTRL2_TIMER4_SHIFT (22U) +/*! TIMER4 - Enables the clock for the Timer 4. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_TIMER4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_TIMER4_SHIFT)) & SYSCON_AHBCLKCTRL2_TIMER4_MASK) +#define SYSCON_AHBCLKCTRL2_PUF_MASK (0x800000U) +#define SYSCON_AHBCLKCTRL2_PUF_SHIFT (23U) +/*! PUF - Enables the clock for the PUF reset control. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_PUF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_PUF_SHIFT)) & SYSCON_AHBCLKCTRL2_PUF_MASK) +#define SYSCON_AHBCLKCTRL2_CASPER_MASK (0x1000000U) +#define SYSCON_AHBCLKCTRL2_CASPER_SHIFT (24U) +/*! CASPER - Enables the clock for the Casper. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_CASPER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_CASPER_SHIFT)) & SYSCON_AHBCLKCTRL2_CASPER_MASK) +#define SYSCON_AHBCLKCTRL2_CAPT0_MASK (0x2000000U) +#define SYSCON_AHBCLKCTRL2_CAPT0_SHIFT (25U) +/*! CAPT0 - Enables the clock for the CAPT0. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_CAPT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_CAPT0_SHIFT)) & SYSCON_AHBCLKCTRL2_CAPT0_MASK) +#define SYSCON_AHBCLKCTRL2_ANALOG_CTRL_MASK (0x8000000U) +#define SYSCON_AHBCLKCTRL2_ANALOG_CTRL_SHIFT (27U) +/*! ANALOG_CTRL - Enables the clock for the analog control. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_ANALOG_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_ANALOG_CTRL_SHIFT)) & SYSCON_AHBCLKCTRL2_ANALOG_CTRL_MASK) +#define SYSCON_AHBCLKCTRL2_HS_LSPI_MASK (0x10000000U) +#define SYSCON_AHBCLKCTRL2_HS_LSPI_SHIFT (28U) +/*! HS_LSPI - Enables the clock for the HS LSPI. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_HS_LSPI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_HS_LSPI_SHIFT)) & SYSCON_AHBCLKCTRL2_HS_LSPI_MASK) +#define SYSCON_AHBCLKCTRL2_GPIO_SEC_MASK (0x20000000U) +#define SYSCON_AHBCLKCTRL2_GPIO_SEC_SHIFT (29U) +/*! GPIO_SEC - Enables the clock for the GPIO secure. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_GPIO_SEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_GPIO_SEC_SHIFT)) & SYSCON_AHBCLKCTRL2_GPIO_SEC_MASK) +#define SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_MASK (0x40000000U) +#define SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_SHIFT (30U) +/*! GPIO_SEC_INT - Enables the clock for the GPIO secure int. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_GPIO_SEC_INT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_SHIFT)) & SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_MASK) +/*! @} */ + +/*! @name AHBCLKCTRLX - Peripheral reset control register */ +/*! @{ */ +#define SYSCON_AHBCLKCTRLX_DATA_MASK (0xFFFFFFFFU) +#define SYSCON_AHBCLKCTRLX_DATA_SHIFT (0U) +#define SYSCON_AHBCLKCTRLX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLX_DATA_SHIFT)) & SYSCON_AHBCLKCTRLX_DATA_MASK) +/*! @} */ + +/* The count of SYSCON_AHBCLKCTRLX */ +#define SYSCON_AHBCLKCTRLX_COUNT (3U) + +/*! @name AHBCLKCTRLSET - Peripheral reset control register */ +/*! @{ */ +#define SYSCON_AHBCLKCTRLSET_DATA_MASK (0xFFFFFFFFU) +#define SYSCON_AHBCLKCTRLSET_DATA_SHIFT (0U) +#define SYSCON_AHBCLKCTRLSET_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLSET_DATA_SHIFT)) & SYSCON_AHBCLKCTRLSET_DATA_MASK) +/*! @} */ + +/* The count of SYSCON_AHBCLKCTRLSET */ +#define SYSCON_AHBCLKCTRLSET_COUNT (3U) + +/*! @name AHBCLKCTRLCLR - Peripheral reset control register */ +/*! @{ */ +#define SYSCON_AHBCLKCTRLCLR_DATA_MASK (0xFFFFFFFFU) +#define SYSCON_AHBCLKCTRLCLR_DATA_SHIFT (0U) +#define SYSCON_AHBCLKCTRLCLR_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLCLR_DATA_SHIFT)) & SYSCON_AHBCLKCTRLCLR_DATA_MASK) +/*! @} */ + +/* The count of SYSCON_AHBCLKCTRLCLR */ +#define SYSCON_AHBCLKCTRLCLR_COUNT (3U) + +/*! @name SYSTICKCLKSEL0 - System Tick Timer for CPU0 source select */ +/*! @{ */ +#define SYSCON_SYSTICKCLKSEL0_SEL_MASK (0x7U) +#define SYSCON_SYSTICKCLKSEL0_SEL_SHIFT (0U) +/*! SEL - System Tick Timer for CPU0 source select. + * 0b000..System Tick 0 divided clock. + * 0b001..FRO 1MHz clock. + * 0b010..Oscillator 32 kHz clock. + * 0b011..No clock. + * 0b100..No clock. + * 0b101..No clock. + * 0b110..No clock. + * 0b111..No clock. + */ +#define SYSCON_SYSTICKCLKSEL0_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKSEL0_SEL_SHIFT)) & SYSCON_SYSTICKCLKSEL0_SEL_MASK) +/*! @} */ + +/*! @name SYSTICKCLKSEL1 - System Tick Timer for CPU1 source select */ +/*! @{ */ +#define SYSCON_SYSTICKCLKSEL1_SEL_MASK (0x7U) +#define SYSCON_SYSTICKCLKSEL1_SEL_SHIFT (0U) +/*! SEL - System Tick Timer for CPU1 source select. + * 0b000..System Tick 1 divided clock. + * 0b001..FRO 1MHz clock. + * 0b010..Oscillator 32 kHz clock. + * 0b011..No clock. + * 0b100..No clock. + * 0b101..No clock. + * 0b110..No clock. + * 0b111..No clock. + */ +#define SYSCON_SYSTICKCLKSEL1_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKSEL1_SEL_SHIFT)) & SYSCON_SYSTICKCLKSEL1_SEL_MASK) +/*! @} */ + +/*! @name SYSTICKCLKSELX - Peripheral reset control register */ +/*! @{ */ +#define SYSCON_SYSTICKCLKSELX_DATA_MASK (0xFFFFFFFFU) +#define SYSCON_SYSTICKCLKSELX_DATA_SHIFT (0U) +#define SYSCON_SYSTICKCLKSELX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKSELX_DATA_SHIFT)) & SYSCON_SYSTICKCLKSELX_DATA_MASK) +/*! @} */ + +/* The count of SYSCON_SYSTICKCLKSELX */ +#define SYSCON_SYSTICKCLKSELX_COUNT (2U) + +/*! @name TRACECLKSEL - Trace clock source select */ +/*! @{ */ +#define SYSCON_TRACECLKSEL_SEL_MASK (0x7U) +#define SYSCON_TRACECLKSEL_SEL_SHIFT (0U) +/*! SEL - Trace clock source select. + * 0b000..Trace divided clock. + * 0b001..FRO 1MHz clock. + * 0b010..Oscillator 32 kHz clock. + * 0b011..No clock. + * 0b100..No clock. + * 0b101..No clock. + * 0b110..No clock. + * 0b111..No clock. + */ +#define SYSCON_TRACECLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKSEL_SEL_SHIFT)) & SYSCON_TRACECLKSEL_SEL_MASK) +/*! @} */ + +/*! @name CTIMERCLKSEL0 - CTimer 0 clock source select */ +/*! @{ */ +#define SYSCON_CTIMERCLKSEL0_SEL_MASK (0x7U) +#define SYSCON_CTIMERCLKSEL0_SEL_SHIFT (0U) +/*! SEL - CTimer 0 clock source select. + * 0b000..Main clock. + * 0b001..PLL0 clock. + * 0b010..No clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32kHz clock. + * 0b111..No clock. + */ +#define SYSCON_CTIMERCLKSEL0_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL0_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL0_SEL_MASK) +/*! @} */ + +/*! @name CTIMERCLKSEL1 - CTimer 1 clock source select */ +/*! @{ */ +#define SYSCON_CTIMERCLKSEL1_SEL_MASK (0x7U) +#define SYSCON_CTIMERCLKSEL1_SEL_SHIFT (0U) +/*! SEL - CTimer 1 clock source select. + * 0b000..Main clock. + * 0b001..PLL0 clock. + * 0b010..No clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32kHz clock. + * 0b111..No clock. + */ +#define SYSCON_CTIMERCLKSEL1_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL1_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL1_SEL_MASK) +/*! @} */ + +/*! @name CTIMERCLKSEL2 - CTimer 2 clock source select */ +/*! @{ */ +#define SYSCON_CTIMERCLKSEL2_SEL_MASK (0x7U) +#define SYSCON_CTIMERCLKSEL2_SEL_SHIFT (0U) +/*! SEL - CTimer 2 clock source select. + * 0b000..Main clock. + * 0b001..PLL0 clock. + * 0b010..No clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32kHz clock. + * 0b111..No clock. + */ +#define SYSCON_CTIMERCLKSEL2_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL2_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL2_SEL_MASK) +/*! @} */ + +/*! @name CTIMERCLKSEL3 - CTimer 3 clock source select */ +/*! @{ */ +#define SYSCON_CTIMERCLKSEL3_SEL_MASK (0x7U) +#define SYSCON_CTIMERCLKSEL3_SEL_SHIFT (0U) +/*! SEL - CTimer 3 clock source select. + * 0b000..Main clock. + * 0b001..PLL0 clock. + * 0b010..No clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32kHz clock. + * 0b111..No clock. + */ +#define SYSCON_CTIMERCLKSEL3_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL3_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL3_SEL_MASK) +/*! @} */ + +/*! @name CTIMERCLKSEL4 - CTimer 4 clock source select */ +/*! @{ */ +#define SYSCON_CTIMERCLKSEL4_SEL_MASK (0x7U) +#define SYSCON_CTIMERCLKSEL4_SEL_SHIFT (0U) +/*! SEL - CTimer 4 clock source select. + * 0b000..Main clock. + * 0b001..PLL0 clock. + * 0b010..No clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32kHz clock. + * 0b111..No clock. + */ +#define SYSCON_CTIMERCLKSEL4_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL4_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL4_SEL_MASK) +/*! @} */ + +/*! @name CTIMERCLKSELX - Peripheral reset control register */ +/*! @{ */ +#define SYSCON_CTIMERCLKSELX_DATA_MASK (0xFFFFFFFFU) +#define SYSCON_CTIMERCLKSELX_DATA_SHIFT (0U) +#define SYSCON_CTIMERCLKSELX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSELX_DATA_SHIFT)) & SYSCON_CTIMERCLKSELX_DATA_MASK) +/*! @} */ + +/* The count of SYSCON_CTIMERCLKSELX */ +#define SYSCON_CTIMERCLKSELX_COUNT (5U) + +/*! @name MAINCLKSELA - Main clock A source select */ +/*! @{ */ +#define SYSCON_MAINCLKSELA_SEL_MASK (0x7U) +#define SYSCON_MAINCLKSELA_SEL_SHIFT (0U) +/*! SEL - Main clock A source select. + * 0b000..FRO 12 MHz clock. + * 0b001..CLKIN clock. + * 0b010..FRO 1MHz clock. + * 0b011..FRO 96 MHz clock. + * 0b100..No clock. + * 0b101..No clock. + * 0b110..No clock. + * 0b111..No clock. + */ +#define SYSCON_MAINCLKSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELA_SEL_SHIFT)) & SYSCON_MAINCLKSELA_SEL_MASK) +/*! @} */ + +/*! @name MAINCLKSELB - Main clock source select */ +/*! @{ */ +#define SYSCON_MAINCLKSELB_SEL_MASK (0x7U) +#define SYSCON_MAINCLKSELB_SEL_SHIFT (0U) +/*! SEL - Main clock source select. + * 0b000..Main Clock A. + * 0b001..PLL0 clock. + * 0b010..PLL1 clock. + * 0b011..Oscillator 32 kHz clock. + * 0b100..No clock. + * 0b101..No clock. + * 0b110..No clock. + * 0b111..No clock. + */ +#define SYSCON_MAINCLKSELB_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELB_SEL_SHIFT)) & SYSCON_MAINCLKSELB_SEL_MASK) +/*! @} */ + +/*! @name CLKOUTSEL - CLKOUT clock source select */ +/*! @{ */ +#define SYSCON_CLKOUTSEL_SEL_MASK (0x7U) +#define SYSCON_CLKOUTSEL_SEL_SHIFT (0U) +/*! SEL - CLKOUT clock source select. + * 0b000..Main clock. + * 0b001..PLL0 clock. + * 0b010..CLKIN clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..PLL1 clock. + * 0b110..Oscillator 32kHz clock. + * 0b111..No clock. + */ +#define SYSCON_CLKOUTSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTSEL_SEL_SHIFT)) & SYSCON_CLKOUTSEL_SEL_MASK) +/*! @} */ + +/*! @name PLL0CLKSEL - PLL0 clock source select */ +/*! @{ */ +#define SYSCON_PLL0CLKSEL_SEL_MASK (0x7U) +#define SYSCON_PLL0CLKSEL_SEL_SHIFT (0U) +/*! SEL - PLL0 clock source select. + * 0b000..FRO 12 MHz clock. + * 0b001..CLKIN clock. + * 0b010..FRO 1MHz clock. + * 0b011..Oscillator 32kHz clock. + * 0b100..No clock. + * 0b101..No clock. + * 0b110..No clock. + * 0b111..No clock. + */ +#define SYSCON_PLL0CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKSEL_SEL_SHIFT)) & SYSCON_PLL0CLKSEL_SEL_MASK) +/*! @} */ + +/*! @name PLL1CLKSEL - PLL1 clock source select */ +/*! @{ */ +#define SYSCON_PLL1CLKSEL_SEL_MASK (0x7U) +#define SYSCON_PLL1CLKSEL_SEL_SHIFT (0U) +/*! SEL - PLL1 clock source select. + * 0b000..FRO 12 MHz clock. + * 0b001..CLKIN clock. + * 0b010..FRO 1MHz clock. + * 0b011..Oscillator 32kHz clock. + * 0b100..No clock. + * 0b101..No clock. + * 0b110..No clock. + * 0b111..No clock. + */ +#define SYSCON_PLL1CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CLKSEL_SEL_SHIFT)) & SYSCON_PLL1CLKSEL_SEL_MASK) +/*! @} */ + +/*! @name ADCCLKSEL - ADC clock source select */ +/*! @{ */ +#define SYSCON_ADCCLKSEL_SEL_MASK (0x7U) +#define SYSCON_ADCCLKSEL_SEL_SHIFT (0U) +/*! SEL - ADC clock source select. + * 0b000..Main clock. + * 0b001..PLL0 clock. + * 0b010..FRO 96 MHz clock. + * 0b011..No clock. + * 0b100..No clock. + * 0b101..No clock. + * 0b110..No clock. + * 0b111..No clock. + */ +#define SYSCON_ADCCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKSEL_SEL_SHIFT)) & SYSCON_ADCCLKSEL_SEL_MASK) +/*! @} */ + +/*! @name USB0CLKSEL - FS USB clock source select */ +/*! @{ */ +#define SYSCON_USB0CLKSEL_SEL_MASK (0x7U) +#define SYSCON_USB0CLKSEL_SEL_SHIFT (0U) +/*! SEL - FS USB clock source select. + * 0b000..Main clock. + * 0b001..PLL0 clock. + * 0b010..No clock. + * 0b011..FRO 96 MHz clock. + * 0b100..No clock. + * 0b101..PLL1 clock. + * 0b110..No clock. + * 0b111..No clock. + */ +#define SYSCON_USB0CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKSEL_SEL_SHIFT)) & SYSCON_USB0CLKSEL_SEL_MASK) +/*! @} */ + +/*! @name USB1CLKSEL - HS USB clock source select - NOT USED */ +/*! @{ */ +#define SYSCON_USB1CLKSEL_SEL_MASK (0x7U) +#define SYSCON_USB1CLKSEL_SEL_SHIFT (0U) +/*! SEL - HS USB clock source select. + * 0b000..Main clock. + * 0b001..PLL0 clock. + * 0b010..CLKIN clock. + * 0b011..No clock. + * 0b100..No clock. + * 0b101..PLL1 clock. + * 0b110..No clock. + * 0b111..No clock. + */ +#define SYSCON_USB1CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKSEL_SEL_SHIFT)) & SYSCON_USB1CLKSEL_SEL_MASK) +/*! @} */ + +/*! @name FCCLKSEL0 - Flexcomm Interface 0 clock source select for Fractional Rate Divider */ +/*! @{ */ +#define SYSCON_FCCLKSEL0_SEL_MASK (0x7U) +#define SYSCON_FCCLKSEL0_SEL_SHIFT (0U) +/*! SEL - Flexcomm Interface 0 clock source select for Fractional Rate Divider. + * 0b000..Main clock. + * 0b001..system PLL divided clock. + * 0b010..FRO 12 MHz clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32 kHz clock. + * 0b111..No clock. + */ +#define SYSCON_FCCLKSEL0_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL0_SEL_SHIFT)) & SYSCON_FCCLKSEL0_SEL_MASK) +/*! @} */ + +/*! @name FCCLKSEL1 - Flexcomm Interface 1 clock source select for Fractional Rate Divider */ +/*! @{ */ +#define SYSCON_FCCLKSEL1_SEL_MASK (0x7U) +#define SYSCON_FCCLKSEL1_SEL_SHIFT (0U) +/*! SEL - Flexcomm Interface 1 clock source select for Fractional Rate Divider. + * 0b000..Main clock. + * 0b001..system PLL divided clock. + * 0b010..FRO 12 MHz clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32 kHz clock. + * 0b111..No clock. + */ +#define SYSCON_FCCLKSEL1_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL1_SEL_SHIFT)) & SYSCON_FCCLKSEL1_SEL_MASK) +/*! @} */ + +/*! @name FCCLKSEL2 - Flexcomm Interface 2 clock source select for Fractional Rate Divider */ +/*! @{ */ +#define SYSCON_FCCLKSEL2_SEL_MASK (0x7U) +#define SYSCON_FCCLKSEL2_SEL_SHIFT (0U) +/*! SEL - Flexcomm Interface 2 clock source select for Fractional Rate Divider. + * 0b000..Main clock. + * 0b001..system PLL divided clock. + * 0b010..FRO 12 MHz clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32 kHz clock. + * 0b111..No clock. + */ +#define SYSCON_FCCLKSEL2_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL2_SEL_SHIFT)) & SYSCON_FCCLKSEL2_SEL_MASK) +/*! @} */ + +/*! @name FCCLKSEL3 - Flexcomm Interface 3 clock source select for Fractional Rate Divider */ +/*! @{ */ +#define SYSCON_FCCLKSEL3_SEL_MASK (0x7U) +#define SYSCON_FCCLKSEL3_SEL_SHIFT (0U) +/*! SEL - Flexcomm Interface 3 clock source select for Fractional Rate Divider. + * 0b000..Main clock. + * 0b001..system PLL divided clock. + * 0b010..FRO 12 MHz clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32 kHz clock. + * 0b111..No clock. + */ +#define SYSCON_FCCLKSEL3_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL3_SEL_SHIFT)) & SYSCON_FCCLKSEL3_SEL_MASK) +/*! @} */ + +/*! @name FCCLKSEL4 - Flexcomm Interface 4 clock source select for Fractional Rate Divider */ +/*! @{ */ +#define SYSCON_FCCLKSEL4_SEL_MASK (0x7U) +#define SYSCON_FCCLKSEL4_SEL_SHIFT (0U) +/*! SEL - Flexcomm Interface 4 clock source select for Fractional Rate Divider. + * 0b000..Main clock. + * 0b001..system PLL divided clock. + * 0b010..FRO 12 MHz clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32 kHz clock. + * 0b111..No clock. + */ +#define SYSCON_FCCLKSEL4_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL4_SEL_SHIFT)) & SYSCON_FCCLKSEL4_SEL_MASK) +/*! @} */ + +/*! @name FCCLKSEL5 - Flexcomm Interface 5 clock source select for Fractional Rate Divider */ +/*! @{ */ +#define SYSCON_FCCLKSEL5_SEL_MASK (0x7U) +#define SYSCON_FCCLKSEL5_SEL_SHIFT (0U) +/*! SEL - Flexcomm Interface 5 clock source select for Fractional Rate Divider. + * 0b000..Main clock. + * 0b001..system PLL divided clock. + * 0b010..FRO 12 MHz clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32 kHz clock. + * 0b111..No clock. + */ +#define SYSCON_FCCLKSEL5_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL5_SEL_SHIFT)) & SYSCON_FCCLKSEL5_SEL_MASK) +/*! @} */ + +/*! @name FCCLKSEL6 - Flexcomm Interface 6 clock source select for Fractional Rate Divider */ +/*! @{ */ +#define SYSCON_FCCLKSEL6_SEL_MASK (0x7U) +#define SYSCON_FCCLKSEL6_SEL_SHIFT (0U) +/*! SEL - Flexcomm Interface 6 clock source select for Fractional Rate Divider. + * 0b000..Main clock. + * 0b001..system PLL divided clock. + * 0b010..FRO 12 MHz clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32 kHz clock. + * 0b111..No clock. + */ +#define SYSCON_FCCLKSEL6_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL6_SEL_SHIFT)) & SYSCON_FCCLKSEL6_SEL_MASK) +/*! @} */ + +/*! @name FCCLKSEL7 - Flexcomm Interface 7 clock source select for Fractional Rate Divider */ +/*! @{ */ +#define SYSCON_FCCLKSEL7_SEL_MASK (0x7U) +#define SYSCON_FCCLKSEL7_SEL_SHIFT (0U) +/*! SEL - Flexcomm Interface 7 clock source select for Fractional Rate Divider. + * 0b000..Main clock. + * 0b001..system PLL divided clock. + * 0b010..FRO 12 MHz clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32 kHz clock. + * 0b111..No clock. + */ +#define SYSCON_FCCLKSEL7_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL7_SEL_SHIFT)) & SYSCON_FCCLKSEL7_SEL_MASK) +/*! @} */ + +/*! @name FCCLKSELX - Peripheral reset control register */ +/*! @{ */ +#define SYSCON_FCCLKSELX_DATA_MASK (0xFFFFFFFFU) +#define SYSCON_FCCLKSELX_DATA_SHIFT (0U) +#define SYSCON_FCCLKSELX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSELX_DATA_SHIFT)) & SYSCON_FCCLKSELX_DATA_MASK) +/*! @} */ + +/* The count of SYSCON_FCCLKSELX */ +#define SYSCON_FCCLKSELX_COUNT (8U) + +/*! @name HSLSPICLKSEL - HS LSPI clock source select */ +/*! @{ */ +#define SYSCON_HSLSPICLKSEL_SEL_MASK (0x7U) +#define SYSCON_HSLSPICLKSEL_SEL_SHIFT (0U) +/*! SEL - HS LSPI clock source select. + * 0b000..Main clock. + * 0b001..system PLL divided clock. + * 0b010..FRO 12 MHz clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..No clock. + * 0b110..Oscillator 32 kHz clock. + * 0b111..No clock. + */ +#define SYSCON_HSLSPICLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HSLSPICLKSEL_SEL_SHIFT)) & SYSCON_HSLSPICLKSEL_SEL_MASK) +/*! @} */ + +/*! @name MCLKCLKSEL - MCLK clock source select */ +/*! @{ */ +#define SYSCON_MCLKCLKSEL_SEL_MASK (0x7U) +#define SYSCON_MCLKCLKSEL_SEL_SHIFT (0U) +/*! SEL - MCLK clock source select. + * 0b000..FRO 96 MHz clock. + * 0b001..PLL0 clock. + * 0b010..No clock. + * 0b011..No clock. + * 0b100..No clock. + * 0b101..No clock. + * 0b110..No clock. + * 0b111..No clock. + */ +#define SYSCON_MCLKCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKCLKSEL_SEL_SHIFT)) & SYSCON_MCLKCLKSEL_SEL_MASK) +/*! @} */ + +/*! @name SCTCLKSEL - SCTimer/PWM clock source select */ +/*! @{ */ +#define SYSCON_SCTCLKSEL_SEL_MASK (0x7U) +#define SYSCON_SCTCLKSEL_SEL_SHIFT (0U) +/*! SEL - SCTimer/PWM clock source select. + * 0b000..Main clock. + * 0b001..PLL0 clock. + * 0b010..CLKIN clock. + * 0b011..FRO 96 MHz clock. + * 0b100..No clock. + * 0b101..MCLK clock. + * 0b110..No clock. + * 0b111..No clock. + */ +#define SYSCON_SCTCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKSEL_SEL_SHIFT)) & SYSCON_SCTCLKSEL_SEL_MASK) +/*! @} */ + +/*! @name SDIOCLKSEL - SDIO clock source select */ +/*! @{ */ +#define SYSCON_SDIOCLKSEL_SEL_MASK (0x7U) +#define SYSCON_SDIOCLKSEL_SEL_SHIFT (0U) +/*! SEL - SDIO clock source select. + * 0b000..Main clock. + * 0b001..PLL0 clock. + * 0b010..No clock. + * 0b011..FRO 96 MHz clock. + * 0b100..No clock. + * 0b101..PLL1 clock. + * 0b110..No clock. + * 0b111..No clock. + */ +#define SYSCON_SDIOCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKSEL_SEL_SHIFT)) & SYSCON_SDIOCLKSEL_SEL_MASK) +/*! @} */ + +/*! @name SYSTICKCLKDIV0 - System Tick Timer divider for CPU0 */ +/*! @{ */ +#define SYSCON_SYSTICKCLKDIV0_DIV_MASK (0xFFU) +#define SYSCON_SYSTICKCLKDIV0_DIV_SHIFT (0U) +#define SYSCON_SYSTICKCLKDIV0_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV0_DIV_SHIFT)) & SYSCON_SYSTICKCLKDIV0_DIV_MASK) +#define SYSCON_SYSTICKCLKDIV0_RESET_MASK (0x20000000U) +#define SYSCON_SYSTICKCLKDIV0_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_SYSTICKCLKDIV0_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV0_RESET_SHIFT)) & SYSCON_SYSTICKCLKDIV0_RESET_MASK) +#define SYSCON_SYSTICKCLKDIV0_HALT_MASK (0x40000000U) +#define SYSCON_SYSTICKCLKDIV0_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stoped. + * 0b0..Divider clock is running. + */ +#define SYSCON_SYSTICKCLKDIV0_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV0_HALT_SHIFT)) & SYSCON_SYSTICKCLKDIV0_HALT_MASK) +#define SYSCON_SYSTICKCLKDIV0_REQFLAG_MASK (0x80000000U) +#define SYSCON_SYSTICKCLKDIV0_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_SYSTICKCLKDIV0_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV0_REQFLAG_SHIFT)) & SYSCON_SYSTICKCLKDIV0_REQFLAG_MASK) +/*! @} */ + +/*! @name SYSTICKCLKDIV1 - System Tick Timer divider for CPU1 */ +/*! @{ */ +#define SYSCON_SYSTICKCLKDIV1_DIV_MASK (0xFFU) +#define SYSCON_SYSTICKCLKDIV1_DIV_SHIFT (0U) +#define SYSCON_SYSTICKCLKDIV1_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV1_DIV_SHIFT)) & SYSCON_SYSTICKCLKDIV1_DIV_MASK) +#define SYSCON_SYSTICKCLKDIV1_RESET_MASK (0x20000000U) +#define SYSCON_SYSTICKCLKDIV1_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_SYSTICKCLKDIV1_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV1_RESET_SHIFT)) & SYSCON_SYSTICKCLKDIV1_RESET_MASK) +#define SYSCON_SYSTICKCLKDIV1_HALT_MASK (0x40000000U) +#define SYSCON_SYSTICKCLKDIV1_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stoped. + * 0b0..Divider clock is running. + */ +#define SYSCON_SYSTICKCLKDIV1_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV1_HALT_SHIFT)) & SYSCON_SYSTICKCLKDIV1_HALT_MASK) +#define SYSCON_SYSTICKCLKDIV1_REQFLAG_MASK (0x80000000U) +#define SYSCON_SYSTICKCLKDIV1_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_SYSTICKCLKDIV1_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV1_REQFLAG_SHIFT)) & SYSCON_SYSTICKCLKDIV1_REQFLAG_MASK) +/*! @} */ + +/*! @name TRACECLKDIV - TRACE clock divider */ +/*! @{ */ +#define SYSCON_TRACECLKDIV_DIV_MASK (0xFFU) +#define SYSCON_TRACECLKDIV_DIV_SHIFT (0U) +#define SYSCON_TRACECLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_DIV_SHIFT)) & SYSCON_TRACECLKDIV_DIV_MASK) +#define SYSCON_TRACECLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_TRACECLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_TRACECLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_RESET_SHIFT)) & SYSCON_TRACECLKDIV_RESET_MASK) +#define SYSCON_TRACECLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_TRACECLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stoped. + * 0b0..Divider clock is running. + */ +#define SYSCON_TRACECLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_HALT_SHIFT)) & SYSCON_TRACECLKDIV_HALT_MASK) +#define SYSCON_TRACECLKDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_TRACECLKDIV_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_TRACECLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_REQFLAG_SHIFT)) & SYSCON_TRACECLKDIV_REQFLAG_MASK) +/*! @} */ + +/*! @name FLEXFRG0CTRL - Fractional rate divider for flexcomm 0 */ +/*! @{ */ +#define SYSCON_FLEXFRG0CTRL_DIV_MASK (0xFFU) +#define SYSCON_FLEXFRG0CTRL_DIV_SHIFT (0U) +#define SYSCON_FLEXFRG0CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG0CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG0CTRL_DIV_MASK) +#define SYSCON_FLEXFRG0CTRL_MULT_MASK (0xFF00U) +#define SYSCON_FLEXFRG0CTRL_MULT_SHIFT (8U) +#define SYSCON_FLEXFRG0CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG0CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG0CTRL_MULT_MASK) +/*! @} */ + +/*! @name FLEXFRG1CTRL - Fractional rate divider for flexcomm 1 */ +/*! @{ */ +#define SYSCON_FLEXFRG1CTRL_DIV_MASK (0xFFU) +#define SYSCON_FLEXFRG1CTRL_DIV_SHIFT (0U) +#define SYSCON_FLEXFRG1CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG1CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG1CTRL_DIV_MASK) +#define SYSCON_FLEXFRG1CTRL_MULT_MASK (0xFF00U) +#define SYSCON_FLEXFRG1CTRL_MULT_SHIFT (8U) +#define SYSCON_FLEXFRG1CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG1CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG1CTRL_MULT_MASK) +/*! @} */ + +/*! @name FLEXFRG2CTRL - Fractional rate divider for flexcomm 2 */ +/*! @{ */ +#define SYSCON_FLEXFRG2CTRL_DIV_MASK (0xFFU) +#define SYSCON_FLEXFRG2CTRL_DIV_SHIFT (0U) +#define SYSCON_FLEXFRG2CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG2CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG2CTRL_DIV_MASK) +#define SYSCON_FLEXFRG2CTRL_MULT_MASK (0xFF00U) +#define SYSCON_FLEXFRG2CTRL_MULT_SHIFT (8U) +#define SYSCON_FLEXFRG2CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG2CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG2CTRL_MULT_MASK) +/*! @} */ + +/*! @name FLEXFRG3CTRL - Fractional rate divider for flexcomm 3 */ +/*! @{ */ +#define SYSCON_FLEXFRG3CTRL_DIV_MASK (0xFFU) +#define SYSCON_FLEXFRG3CTRL_DIV_SHIFT (0U) +#define SYSCON_FLEXFRG3CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG3CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG3CTRL_DIV_MASK) +#define SYSCON_FLEXFRG3CTRL_MULT_MASK (0xFF00U) +#define SYSCON_FLEXFRG3CTRL_MULT_SHIFT (8U) +#define SYSCON_FLEXFRG3CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG3CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG3CTRL_MULT_MASK) +/*! @} */ + +/*! @name FLEXFRG4CTRL - Fractional rate divider for flexcomm 4 */ +/*! @{ */ +#define SYSCON_FLEXFRG4CTRL_DIV_MASK (0xFFU) +#define SYSCON_FLEXFRG4CTRL_DIV_SHIFT (0U) +#define SYSCON_FLEXFRG4CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG4CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG4CTRL_DIV_MASK) +#define SYSCON_FLEXFRG4CTRL_MULT_MASK (0xFF00U) +#define SYSCON_FLEXFRG4CTRL_MULT_SHIFT (8U) +#define SYSCON_FLEXFRG4CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG4CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG4CTRL_MULT_MASK) +/*! @} */ + +/*! @name FLEXFRG5CTRL - Fractional rate divider for flexcomm 5 */ +/*! @{ */ +#define SYSCON_FLEXFRG5CTRL_DIV_MASK (0xFFU) +#define SYSCON_FLEXFRG5CTRL_DIV_SHIFT (0U) +#define SYSCON_FLEXFRG5CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG5CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG5CTRL_DIV_MASK) +#define SYSCON_FLEXFRG5CTRL_MULT_MASK (0xFF00U) +#define SYSCON_FLEXFRG5CTRL_MULT_SHIFT (8U) +#define SYSCON_FLEXFRG5CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG5CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG5CTRL_MULT_MASK) +/*! @} */ + +/*! @name FLEXFRG6CTRL - Fractional rate divider for flexcomm 6 */ +/*! @{ */ +#define SYSCON_FLEXFRG6CTRL_DIV_MASK (0xFFU) +#define SYSCON_FLEXFRG6CTRL_DIV_SHIFT (0U) +#define SYSCON_FLEXFRG6CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG6CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG6CTRL_DIV_MASK) +#define SYSCON_FLEXFRG6CTRL_MULT_MASK (0xFF00U) +#define SYSCON_FLEXFRG6CTRL_MULT_SHIFT (8U) +#define SYSCON_FLEXFRG6CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG6CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG6CTRL_MULT_MASK) +/*! @} */ + +/*! @name FLEXFRG7CTRL - Fractional rate divider for flexcomm 7 */ +/*! @{ */ +#define SYSCON_FLEXFRG7CTRL_DIV_MASK (0xFFU) +#define SYSCON_FLEXFRG7CTRL_DIV_SHIFT (0U) +#define SYSCON_FLEXFRG7CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG7CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG7CTRL_DIV_MASK) +#define SYSCON_FLEXFRG7CTRL_MULT_MASK (0xFF00U) +#define SYSCON_FLEXFRG7CTRL_MULT_SHIFT (8U) +#define SYSCON_FLEXFRG7CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG7CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG7CTRL_MULT_MASK) +/*! @} */ + +/*! @name FLEXFRGXCTRL - Peripheral reset control register */ +/*! @{ */ +#define SYSCON_FLEXFRGXCTRL_DATA_MASK (0xFFFFFFFFU) +#define SYSCON_FLEXFRGXCTRL_DATA_SHIFT (0U) +#define SYSCON_FLEXFRGXCTRL_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRGXCTRL_DATA_SHIFT)) & SYSCON_FLEXFRGXCTRL_DATA_MASK) +/*! @} */ + +/* The count of SYSCON_FLEXFRGXCTRL */ +#define SYSCON_FLEXFRGXCTRL_COUNT (8U) + +/*! @name AHBCLKDIV - System clock divider */ +/*! @{ */ +#define SYSCON_AHBCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_AHBCLKDIV_DIV_SHIFT (0U) +#define SYSCON_AHBCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_DIV_SHIFT)) & SYSCON_AHBCLKDIV_DIV_MASK) +#define SYSCON_AHBCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_AHBCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_AHBCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_RESET_SHIFT)) & SYSCON_AHBCLKDIV_RESET_MASK) +#define SYSCON_AHBCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_AHBCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stoped. + * 0b0..Divider clock is running. + */ +#define SYSCON_AHBCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_HALT_SHIFT)) & SYSCON_AHBCLKDIV_HALT_MASK) +#define SYSCON_AHBCLKDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_AHBCLKDIV_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_AHBCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_REQFLAG_SHIFT)) & SYSCON_AHBCLKDIV_REQFLAG_MASK) +/*! @} */ + +/*! @name CLKOUTDIV - CLKOUT clock divider */ +/*! @{ */ +#define SYSCON_CLKOUTDIV_DIV_MASK (0xFFU) +#define SYSCON_CLKOUTDIV_DIV_SHIFT (0U) +#define SYSCON_CLKOUTDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_DIV_SHIFT)) & SYSCON_CLKOUTDIV_DIV_MASK) +#define SYSCON_CLKOUTDIV_RESET_MASK (0x20000000U) +#define SYSCON_CLKOUTDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_CLKOUTDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_RESET_SHIFT)) & SYSCON_CLKOUTDIV_RESET_MASK) +#define SYSCON_CLKOUTDIV_HALT_MASK (0x40000000U) +#define SYSCON_CLKOUTDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stoped. + * 0b0..Divider clock is running. + */ +#define SYSCON_CLKOUTDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_HALT_SHIFT)) & SYSCON_CLKOUTDIV_HALT_MASK) +#define SYSCON_CLKOUTDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_CLKOUTDIV_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_CLKOUTDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_REQFLAG_SHIFT)) & SYSCON_CLKOUTDIV_REQFLAG_MASK) +/*! @} */ + +/*! @name FROHFDIV - FRO_HF (96MHz) clock divider */ +/*! @{ */ +#define SYSCON_FROHFDIV_DIV_MASK (0xFFU) +#define SYSCON_FROHFDIV_DIV_SHIFT (0U) +#define SYSCON_FROHFDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_DIV_SHIFT)) & SYSCON_FROHFDIV_DIV_MASK) +#define SYSCON_FROHFDIV_RESET_MASK (0x20000000U) +#define SYSCON_FROHFDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_FROHFDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_RESET_SHIFT)) & SYSCON_FROHFDIV_RESET_MASK) +#define SYSCON_FROHFDIV_HALT_MASK (0x40000000U) +#define SYSCON_FROHFDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stoped. + * 0b0..Divider clock is running. + */ +#define SYSCON_FROHFDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_HALT_SHIFT)) & SYSCON_FROHFDIV_HALT_MASK) +#define SYSCON_FROHFDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_FROHFDIV_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_FROHFDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_REQFLAG_SHIFT)) & SYSCON_FROHFDIV_REQFLAG_MASK) +/*! @} */ + +/*! @name WDTCLKDIV - WDT clock divider */ +/*! @{ */ +#define SYSCON_WDTCLKDIV_DIV_MASK (0x3FU) +#define SYSCON_WDTCLKDIV_DIV_SHIFT (0U) +#define SYSCON_WDTCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_DIV_SHIFT)) & SYSCON_WDTCLKDIV_DIV_MASK) +#define SYSCON_WDTCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_WDTCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_WDTCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_RESET_SHIFT)) & SYSCON_WDTCLKDIV_RESET_MASK) +#define SYSCON_WDTCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_WDTCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stoped. + * 0b0..Divider clock is running. + */ +#define SYSCON_WDTCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_HALT_SHIFT)) & SYSCON_WDTCLKDIV_HALT_MASK) +#define SYSCON_WDTCLKDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_WDTCLKDIV_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_WDTCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_REQFLAG_SHIFT)) & SYSCON_WDTCLKDIV_REQFLAG_MASK) +/*! @} */ + +/*! @name ADCCLKDIV - ADC clock divider */ +/*! @{ */ +#define SYSCON_ADCCLKDIV_DIV_MASK (0x7U) +#define SYSCON_ADCCLKDIV_DIV_SHIFT (0U) +#define SYSCON_ADCCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_DIV_SHIFT)) & SYSCON_ADCCLKDIV_DIV_MASK) +#define SYSCON_ADCCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_ADCCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_ADCCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_RESET_SHIFT)) & SYSCON_ADCCLKDIV_RESET_MASK) +#define SYSCON_ADCCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_ADCCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stoped. + * 0b0..Divider clock is running. + */ +#define SYSCON_ADCCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_HALT_SHIFT)) & SYSCON_ADCCLKDIV_HALT_MASK) +#define SYSCON_ADCCLKDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_ADCCLKDIV_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_ADCCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_REQFLAG_SHIFT)) & SYSCON_ADCCLKDIV_REQFLAG_MASK) +/*! @} */ + +/*! @name USB0CLKDIV - USB0 Clock divider */ +/*! @{ */ +#define SYSCON_USB0CLKDIV_DIV_MASK (0xFFU) +#define SYSCON_USB0CLKDIV_DIV_SHIFT (0U) +#define SYSCON_USB0CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_DIV_SHIFT)) & SYSCON_USB0CLKDIV_DIV_MASK) +#define SYSCON_USB0CLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_USB0CLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_USB0CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_RESET_SHIFT)) & SYSCON_USB0CLKDIV_RESET_MASK) +#define SYSCON_USB0CLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_USB0CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stoped. + * 0b0..Divider clock is running. + */ +#define SYSCON_USB0CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_HALT_SHIFT)) & SYSCON_USB0CLKDIV_HALT_MASK) +#define SYSCON_USB0CLKDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_USB0CLKDIV_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_USB0CLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_REQFLAG_SHIFT)) & SYSCON_USB0CLKDIV_REQFLAG_MASK) +/*! @} */ + +/*! @name MCLKDIV - I2S MCLK clock divider */ +/*! @{ */ +#define SYSCON_MCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_MCLKDIV_DIV_SHIFT (0U) +#define SYSCON_MCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_DIV_SHIFT)) & SYSCON_MCLKDIV_DIV_MASK) +#define SYSCON_MCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_MCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_MCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_RESET_SHIFT)) & SYSCON_MCLKDIV_RESET_MASK) +#define SYSCON_MCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_MCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stoped. + * 0b0..Divider clock is running. + */ +#define SYSCON_MCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_HALT_SHIFT)) & SYSCON_MCLKDIV_HALT_MASK) +#define SYSCON_MCLKDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_MCLKDIV_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_MCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_REQFLAG_SHIFT)) & SYSCON_MCLKDIV_REQFLAG_MASK) +/*! @} */ + +/*! @name SCTCLKDIV - SCT/PWM clock divider */ +/*! @{ */ +#define SYSCON_SCTCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_SCTCLKDIV_DIV_SHIFT (0U) +#define SYSCON_SCTCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_DIV_SHIFT)) & SYSCON_SCTCLKDIV_DIV_MASK) +#define SYSCON_SCTCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_SCTCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_SCTCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_RESET_SHIFT)) & SYSCON_SCTCLKDIV_RESET_MASK) +#define SYSCON_SCTCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_SCTCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stoped. + * 0b0..Divider clock is running. + */ +#define SYSCON_SCTCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_HALT_SHIFT)) & SYSCON_SCTCLKDIV_HALT_MASK) +#define SYSCON_SCTCLKDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_SCTCLKDIV_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_SCTCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_REQFLAG_SHIFT)) & SYSCON_SCTCLKDIV_REQFLAG_MASK) +/*! @} */ + +/*! @name SDIOCLKDIV - SDIO clock divider */ +/*! @{ */ +#define SYSCON_SDIOCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_SDIOCLKDIV_DIV_SHIFT (0U) +#define SYSCON_SDIOCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_DIV_SHIFT)) & SYSCON_SDIOCLKDIV_DIV_MASK) +#define SYSCON_SDIOCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_SDIOCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_SDIOCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_RESET_SHIFT)) & SYSCON_SDIOCLKDIV_RESET_MASK) +#define SYSCON_SDIOCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_SDIOCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stoped. + * 0b0..Divider clock is running. + */ +#define SYSCON_SDIOCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_HALT_SHIFT)) & SYSCON_SDIOCLKDIV_HALT_MASK) +#define SYSCON_SDIOCLKDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_SDIOCLKDIV_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_SDIOCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_REQFLAG_SHIFT)) & SYSCON_SDIOCLKDIV_REQFLAG_MASK) +/*! @} */ + +/*! @name PLL0CLKDIV - PLL0 clock divider */ +/*! @{ */ +#define SYSCON_PLL0CLKDIV_DIV_MASK (0xFFU) +#define SYSCON_PLL0CLKDIV_DIV_SHIFT (0U) +#define SYSCON_PLL0CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKDIV_DIV_SHIFT)) & SYSCON_PLL0CLKDIV_DIV_MASK) +#define SYSCON_PLL0CLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_PLL0CLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_PLL0CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKDIV_RESET_SHIFT)) & SYSCON_PLL0CLKDIV_RESET_MASK) +#define SYSCON_PLL0CLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_PLL0CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stoped. + * 0b0..Divider clock is running. + */ +#define SYSCON_PLL0CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKDIV_HALT_SHIFT)) & SYSCON_PLL0CLKDIV_HALT_MASK) +#define SYSCON_PLL0CLKDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_PLL0CLKDIV_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_PLL0CLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKDIV_REQFLAG_SHIFT)) & SYSCON_PLL0CLKDIV_REQFLAG_MASK) +/*! @} */ + +/*! @name CLOCKGENUPDATELOCKOUT - Control clock configuration registers access (like xxxDIV, xxxSEL) */ +/*! @{ */ +#define SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT_MASK (0xFFFFFFFFU) +#define SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT_SHIFT (0U) +/*! CLOCKGENUPDATELOCKOUT - Control clock configuration registers access (like xxxDIV, xxxSEL). + * 0b00000000000000000000000000000001..update all clock configuration. + * 0b00000000000000000000000000000000..all hardware clock configruration are freeze. + */ +#define SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT_SHIFT)) & SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT_MASK) +/*! @} */ + +/*! @name FMCCR - FMC configuration register - INTERNAL USE ONLY */ +/*! @{ */ +#define SYSCON_FMCCR_FLASHTIM_MASK (0xF000U) +#define SYSCON_FMCCR_FLASHTIM_SHIFT (12U) + +#define SYSCON_FMCCR_FETCHCTL_MASK (0x3U) +#define SYSCON_FMCCR_FETCHCTL_SHIFT (0U) +/*! FETCHCTL - Fetch control + * 0b00..No buffering (bypass always used) for Fetch cycles + * 0b01..One buffer is used for all Fetch cycles + * 0b10..All buffers can be used for Fetch cycles + */ +#define SYSCON_FMCCR_FETCHCTL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_FETCHCTL_SHIFT)) & SYSCON_FMCCR_FETCHCTL_MASK) +#define SYSCON_FMCCR_DATACTL_MASK (0xCU) +#define SYSCON_FMCCR_DATACTL_SHIFT (2U) +/*! DATACTL - Data control + * 0b00..No buffering (bypass always used) for Data cycles + * 0b01..One buffer is used for all Data cycles + * 0b10..All buffers can be used for Data cycles + */ +#define SYSCON_FMCCR_DATACTL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_DATACTL_SHIFT)) & SYSCON_FMCCR_DATACTL_MASK) +#define SYSCON_FMCCR_ACCEL_MASK (0x10U) +#define SYSCON_FMCCR_ACCEL_SHIFT (4U) +#define SYSCON_FMCCR_ACCEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_ACCEL_SHIFT)) & SYSCON_FMCCR_ACCEL_MASK) +#define SYSCON_FMCCR_PREFEN_MASK (0x20U) +#define SYSCON_FMCCR_PREFEN_SHIFT (5U) +#define SYSCON_FMCCR_PREFEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_PREFEN_SHIFT)) & SYSCON_FMCCR_PREFEN_MASK) +#define SYSCON_FMCCR_PREFOVR_MASK (0x40U) +#define SYSCON_FMCCR_PREFOVR_SHIFT (6U) +#define SYSCON_FMCCR_PREFOVR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_PREFOVR_SHIFT)) & SYSCON_FMCCR_PREFOVR_MASK) +#define SYSCON_FMCCR_PREFCRI_MASK (0x700U) +#define SYSCON_FMCCR_PREFCRI_SHIFT (8U) +#define SYSCON_FMCCR_PREFCRI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_PREFCRI_SHIFT)) & SYSCON_FMCCR_PREFCRI_MASK) +#define SYSCON_FMCCR_FMCTIM_MASK (0x1F000U) +#define SYSCON_FMCCR_FMCTIM_SHIFT (12U) +#define SYSCON_FMCCR_FMCTIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_FMCTIM_SHIFT)) & SYSCON_FMCCR_FMCTIM_MASK) +#define SYSCON_FMCCR_PFISLRU_MASK (0x20000U) +#define SYSCON_FMCCR_PFISLRU_SHIFT (17U) +#define SYSCON_FMCCR_PFISLRU(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_PFISLRU_SHIFT)) & SYSCON_FMCCR_PFISLRU_MASK) +#define SYSCON_FMCCR_PFADAP_MASK (0x40000U) +#define SYSCON_FMCCR_PFADAP_SHIFT (18U) +#define SYSCON_FMCCR_PFADAP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_PFADAP_SHIFT)) & SYSCON_FMCCR_PFADAP_MASK) +/*! @} */ + +/*! @name USB0CLKCTRL - USB0 clock control */ +/*! @{ */ +#define SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK_MASK (0x1U) +#define SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK_SHIFT (0U) +/*! AP_FS_DEV_CLK - USB0 Device USB0_NEEDCLK signal control:. + * 0b0..Under hardware control. + * 0b1..Forced high. + */ +#define SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK_SHIFT)) & SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK_MASK) +#define SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK_MASK (0x2U) +#define SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK_SHIFT (1U) +/*! POL_FS_DEV_CLK - USB0 Device USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt:. + * 0b0..Falling edge of device USB0_NEEDCLK triggers wake-up. + * 0b1..Rising edge of device USB0_NEEDCLK triggers wake-up. + */ +#define SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK_SHIFT)) & SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK_MASK) +#define SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK_MASK (0x4U) +#define SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK_SHIFT (2U) +/*! AP_FS_HOST_CLK - USB0 Host USB0_NEEDCLK signal control:. + * 0b0..Under hardware control. + * 0b1..Forced high. + */ +#define SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK_SHIFT)) & SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK_MASK) +#define SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK_MASK (0x8U) +#define SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK_SHIFT (3U) +/*! POL_FS_HOST_CLK - USB0 Host USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt:. + * 0b0..Falling edge of device USB0_NEEDCLK triggers wake-up. + * 0b1..Rising edge of device USB0_NEEDCLK triggers wake-up. + */ +#define SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK_SHIFT)) & SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK_MASK) +#define SYSCON_USB0CLKCTRL_PU_DISABLE_MASK (0x10U) +#define SYSCON_USB0CLKCTRL_PU_DISABLE_SHIFT (4U) +/*! PU_DISABLE - Internal pull-up disable control. + * 0b1..Internal pull-up disable. + * 0b0..Internal pull-up enable. + */ +#define SYSCON_USB0CLKCTRL_PU_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_PU_DISABLE_SHIFT)) & SYSCON_USB0CLKCTRL_PU_DISABLE_MASK) +/*! @} */ + +/*! @name USB0CLKSTAT - USB0 clock status */ +/*! @{ */ +#define SYSCON_USB0CLKSTAT_DEV_NEED_CLKST_MASK (0x1U) +#define SYSCON_USB0CLKSTAT_DEV_NEED_CLKST_SHIFT (0U) +/*! DEV_NEED_CLKST - USB0 Device USB0_NEEDCLK signal status:. + * 0b1..USB0 Device clock is high. + * 0b0..USB0 Device clock is low. + */ +#define SYSCON_USB0CLKSTAT_DEV_NEED_CLKST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKSTAT_DEV_NEED_CLKST_SHIFT)) & SYSCON_USB0CLKSTAT_DEV_NEED_CLKST_MASK) +#define SYSCON_USB0CLKSTAT_HOST_NEED_CLKST_MASK (0x2U) +#define SYSCON_USB0CLKSTAT_HOST_NEED_CLKST_SHIFT (1U) +/*! HOST_NEED_CLKST - USB0 Host USB0_NEEDCLK signal status:. + * 0b1..USB0 Host clock is high. + * 0b0..USB0 Host clock is low. + */ +#define SYSCON_USB0CLKSTAT_HOST_NEED_CLKST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKSTAT_HOST_NEED_CLKST_SHIFT)) & SYSCON_USB0CLKSTAT_HOST_NEED_CLKST_MASK) +/*! @} */ + +/*! @name FMCFLUSH - FMCflush control */ +/*! @{ */ +#define SYSCON_FMCFLUSH_FLUSH_MASK (0x1U) +#define SYSCON_FMCFLUSH_FLUSH_SHIFT (0U) +#define SYSCON_FMCFLUSH_FLUSH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCFLUSH_FLUSH_SHIFT)) & SYSCON_FMCFLUSH_FLUSH_MASK) +/*! @} */ + +/*! @name MCLKIO - MCLK control */ +/*! @{ */ +#define SYSCON_MCLKIO_MCLKIO_MASK (0xFFFFFFFFU) +#define SYSCON_MCLKIO_MCLKIO_SHIFT (0U) +/*! MCLKIO - MCLK control. + * 0b00000000000000000000000000000000..input mode. + * 0b00000000000000000000000000000001..output mode. + */ +#define SYSCON_MCLKIO_MCLKIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKIO_MCLKIO_SHIFT)) & SYSCON_MCLKIO_MCLKIO_MASK) +/*! @} */ + +/*! @name USB1CLKCTRL - USB1 clock control */ +/*! @{ */ +#define SYSCON_USB1CLKCTRL_AP_HS_DEV_CLK_MASK (0x1U) +#define SYSCON_USB1CLKCTRL_AP_HS_DEV_CLK_SHIFT (0U) +/*! AP_HS_DEV_CLK - USB1 Device need_clock signal control:. + * 0b0..Under hardware control. + * 0b1..Forced high. + */ +#define SYSCON_USB1CLKCTRL_AP_HS_DEV_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_AP_HS_DEV_CLK_SHIFT)) & SYSCON_USB1CLKCTRL_AP_HS_DEV_CLK_MASK) +#define SYSCON_USB1CLKCTRL_POL_HS_DEV_CLK_MASK (0x2U) +#define SYSCON_USB1CLKCTRL_POL_HS_DEV_CLK_SHIFT (1U) +/*! POL_HS_DEV_CLK - USB1 Device need_clock polarity for triggering the USB1 wake-up interrupt:. + * 0b0..Falling edge of device need_clock triggers wake-up. + * 0b1..Rising edge of device need_clock triggers wake-up. + */ +#define SYSCON_USB1CLKCTRL_POL_HS_DEV_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_POL_HS_DEV_CLK_SHIFT)) & SYSCON_USB1CLKCTRL_POL_HS_DEV_CLK_MASK) +#define SYSCON_USB1CLKCTRL_AP_HS_HOST_CLK_MASK (0x4U) +#define SYSCON_USB1CLKCTRL_AP_HS_HOST_CLK_SHIFT (2U) +/*! AP_HS_HOST_CLK - USB1 Host need_clock signal control:. + * 0b0..Under hardware control. + * 0b1..Forced high. + */ +#define SYSCON_USB1CLKCTRL_AP_HS_HOST_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_AP_HS_HOST_CLK_SHIFT)) & SYSCON_USB1CLKCTRL_AP_HS_HOST_CLK_MASK) +#define SYSCON_USB1CLKCTRL_POL_HS_HOST_CLK_MASK (0x8U) +#define SYSCON_USB1CLKCTRL_POL_HS_HOST_CLK_SHIFT (3U) +/*! POL_HS_HOST_CLK - USB1 Host need_clock polarity for triggering the USB1 wake-up interrupt: 0 + * Falling edge of device need_clock triggers wake-up. + * 0b0..Falling edge of device need_clock triggers wake-up. + * 0b1..Rising edge of device need_clock triggers wake-up. + */ +#define SYSCON_USB1CLKCTRL_POL_HS_HOST_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_POL_HS_HOST_CLK_SHIFT)) & SYSCON_USB1CLKCTRL_POL_HS_HOST_CLK_MASK) +#define SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N_MASK (0x10U) +#define SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N_SHIFT (4U) +/*! HS_DEV_WAKEUP_N - External user wake-up signal for device mode; asserting this signal (active + * low) will result in exiting the low power mode; input to synchronous control logic:. + * 0b0..Forces USB1 PHY to wake-up. + * 0b1..Normal USB1 PHY behavior. + */ +#define SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N_SHIFT)) & SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N_MASK) +/*! @} */ + +/*! @name USB1CLKSTAT - USB1 clock status */ +/*! @{ */ +#define SYSCON_USB1CLKSTAT_DEV_NEED_CLKST_MASK (0x1U) +#define SYSCON_USB1CLKSTAT_DEV_NEED_CLKST_SHIFT (0U) +/*! DEV_NEED_CLKST - USB1 Device need_clock signal status:. + * 0b1..USB1 Device clock is high. + * 0b0..USB1 Device clock is low. + */ +#define SYSCON_USB1CLKSTAT_DEV_NEED_CLKST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKSTAT_DEV_NEED_CLKST_SHIFT)) & SYSCON_USB1CLKSTAT_DEV_NEED_CLKST_MASK) +#define SYSCON_USB1CLKSTAT_HOST_NEED_CLKST_MASK (0x2U) +#define SYSCON_USB1CLKSTAT_HOST_NEED_CLKST_SHIFT (1U) +/*! HOST_NEED_CLKST - USB1 Host need_clock signal status:. + * 0b1..USB1 Host clock is high. + * 0b0..USB1 Host clock is low. + */ +#define SYSCON_USB1CLKSTAT_HOST_NEED_CLKST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKSTAT_HOST_NEED_CLKST_SHIFT)) & SYSCON_USB1CLKSTAT_HOST_NEED_CLKST_MASK) +/*! @} */ + +/*! @name FLASHBANKENABLE - Flash Banks control */ +/*! @{ */ +#define SYSCON_FLASHBANKENABLE_BANK0_MASK (0xFU) +#define SYSCON_FLASHBANKENABLE_BANK0_SHIFT (0U) +/*! BANK0 - Flash Bank0 control. + * 0b0000..Flash BANK0 checker is enabled (all Flash pages inside this bank cannot be erased nor programmed). + * 0b1010..1010: Flash BANK0 checker is disabled (all Flash pages inside this bank can be erased and programmed). + */ +#define SYSCON_FLASHBANKENABLE_BANK0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHBANKENABLE_BANK0_SHIFT)) & SYSCON_FLASHBANKENABLE_BANK0_MASK) +#define SYSCON_FLASHBANKENABLE_BANK1_MASK (0xF0U) +#define SYSCON_FLASHBANKENABLE_BANK1_SHIFT (4U) +/*! BANK1 - Flash Bank1 control. + * 0b0000..Flash BANK1 checker is enabled (all Flash pages inside this bank cannot be erased nor programmed). + * 0b1010..1010: Flash BANK1 checker is disabled (all Flash pages inside this bank can be erased and programmed). + */ +#define SYSCON_FLASHBANKENABLE_BANK1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHBANKENABLE_BANK1_SHIFT)) & SYSCON_FLASHBANKENABLE_BANK1_MASK) +#define SYSCON_FLASHBANKENABLE_BANK2_MASK (0xF00U) +#define SYSCON_FLASHBANKENABLE_BANK2_SHIFT (8U) +/*! BANK2 - Flash Bank2 control. + * 0b0000..Flash BANK2 checker is enabled (all Flash pages inside this bank cannot be erased nor programmed). + * 0b1010..1010: Flash BANK2 checker is disabled (all Flash pages inside this bank can be erased and programmed). + */ +#define SYSCON_FLASHBANKENABLE_BANK2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHBANKENABLE_BANK2_SHIFT)) & SYSCON_FLASHBANKENABLE_BANK2_MASK) +/*! @} */ + +/*! @name SDIOCLKCTRL - SDIO CCLKIN phase and delay control */ +/*! @{ */ +#define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK (0x3U) +#define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_SHIFT (0U) +/*! CCLK_DRV_PHASE - Programmable delay value by which cclk_in_drv is phase-shifted with regard to cclk_in. + * 0b00..0 degree shift. + * 0b01..90 degree shift. + * 0b10..180 degree shift. + * 0b11..270 degree shift. + */ +#define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK) +#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK (0xCU) +#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_SHIFT (2U) +/*! CCLK_SAMPLE_PHASE - Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in. + * 0b00..0 degree shift. + * 0b01..90 degree shift. + * 0b10..180 degree shift. + * 0b11..270 degree shift. + */ +#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK) +#define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK (0x80U) +#define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_SHIFT (7U) +/*! PHASE_ACTIVE - Enables the delays CCLK_DRV_PHASE and CCLK_SAMPLE_PHASE. + * 0b0..Bypassed. + * 0b1..Activates phase shift logic. When active, the clock divider is active and phase delays are enabled. + */ +#define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK) +#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_MASK (0x1F0000U) +#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_SHIFT (16U) +#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_MASK) +#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK (0x800000U) +#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_SHIFT (23U) +/*! CCLK_DRV_DELAY_ACTIVE - Enables drive delay, as controlled by the CCLK_DRV_DELAY field. + * 0b1..Enable drive delay. + * 0b0..Disable drive delay. + */ +#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK) +#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_MASK (0x1F000000U) +#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_SHIFT (24U) +#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_MASK) +#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK (0x80000000U) +#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_SHIFT (31U) +/*! CCLK_SAMPLE_DELAY_ACTIVE - Enables sample delay, as controlled by the CCLK_SAMPLE_DELAY field. + * 0b1..Enables sample delay. + * 0b0..Disables sample delay. + */ +#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK) +/*! @} */ + +/*! @name PLL1CTRL - PLL1 550m control */ +/*! @{ */ +#define SYSCON_PLL1CTRL_SELR_MASK (0xFU) +#define SYSCON_PLL1CTRL_SELR_SHIFT (0U) +#define SYSCON_PLL1CTRL_SELR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SELR_SHIFT)) & SYSCON_PLL1CTRL_SELR_MASK) +#define SYSCON_PLL1CTRL_SELI_MASK (0x3F0U) +#define SYSCON_PLL1CTRL_SELI_SHIFT (4U) +#define SYSCON_PLL1CTRL_SELI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SELI_SHIFT)) & SYSCON_PLL1CTRL_SELI_MASK) +#define SYSCON_PLL1CTRL_SELP_MASK (0x7C00U) +#define SYSCON_PLL1CTRL_SELP_SHIFT (10U) +#define SYSCON_PLL1CTRL_SELP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SELP_SHIFT)) & SYSCON_PLL1CTRL_SELP_MASK) +#define SYSCON_PLL1CTRL_BYPASSPLL_MASK (0x8000U) +#define SYSCON_PLL1CTRL_BYPASSPLL_SHIFT (15U) +/*! BYPASSPLL - Bypass PLL input clock is sent directly to the PLL output (default). + * 0b1..PLL input clock is sent directly to the PLL output. + * 0b0..use PLL. + */ +#define SYSCON_PLL1CTRL_BYPASSPLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPLL_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPLL_MASK) +#define SYSCON_PLL1CTRL_BYPASSPOSTDIV2_MASK (0x10000U) +#define SYSCON_PLL1CTRL_BYPASSPOSTDIV2_SHIFT (16U) +/*! BYPASSPOSTDIV2 - bypass of the divide-by-2 divider in the post-divider. + * 0b1..bypass of the divide-by-2 divider in the post-divider. + * 0b0..use the divide-by-2 divider in the post-divider. + */ +#define SYSCON_PLL1CTRL_BYPASSPOSTDIV2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPOSTDIV2_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPOSTDIV2_MASK) +#define SYSCON_PLL1CTRL_LIMUPOFF_MASK (0x20000U) +#define SYSCON_PLL1CTRL_LIMUPOFF_SHIFT (17U) +#define SYSCON_PLL1CTRL_LIMUPOFF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_LIMUPOFF_SHIFT)) & SYSCON_PLL1CTRL_LIMUPOFF_MASK) +#define SYSCON_PLL1CTRL_BWDIRECT_MASK (0x40000U) +#define SYSCON_PLL1CTRL_BWDIRECT_SHIFT (18U) +/*! BWDIRECT - control of the bandwidth of the PLL. + * 0b1..modify the bandwidth of the PLL directly. + * 0b0..the bandwidth is changed synchronously with the feedback-divider. + */ +#define SYSCON_PLL1CTRL_BWDIRECT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BWDIRECT_SHIFT)) & SYSCON_PLL1CTRL_BWDIRECT_MASK) +#define SYSCON_PLL1CTRL_BYPASSPREDIV_MASK (0x80000U) +#define SYSCON_PLL1CTRL_BYPASSPREDIV_SHIFT (19U) +/*! BYPASSPREDIV - bypass of the pre-divider. + * 0b1..bypass of the pre-divider. + * 0b0..use the pre-divider. + */ +#define SYSCON_PLL1CTRL_BYPASSPREDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPREDIV_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPREDIV_MASK) +#define SYSCON_PLL1CTRL_BYPASSPOSTDIV_MASK (0x100000U) +#define SYSCON_PLL1CTRL_BYPASSPOSTDIV_SHIFT (20U) +/*! BYPASSPOSTDIV - bypass of the post-divider. + * 0b1..bypass of the post-divider. + * 0b0..use the post-divider. + */ +#define SYSCON_PLL1CTRL_BYPASSPOSTDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPOSTDIV_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPOSTDIV_MASK) +#define SYSCON_PLL1CTRL_CLKEN_MASK (0x200000U) +#define SYSCON_PLL1CTRL_CLKEN_SHIFT (21U) +/*! CLKEN - enable the output clock. + * 0b1..Enable the output clock. + * 0b0..Disable the output clock. + */ +#define SYSCON_PLL1CTRL_CLKEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_CLKEN_SHIFT)) & SYSCON_PLL1CTRL_CLKEN_MASK) +#define SYSCON_PLL1CTRL_FRMEN_MASK (0x400000U) +#define SYSCON_PLL1CTRL_FRMEN_SHIFT (22U) +#define SYSCON_PLL1CTRL_FRMEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_FRMEN_SHIFT)) & SYSCON_PLL1CTRL_FRMEN_MASK) +#define SYSCON_PLL1CTRL_FRMCLKSTABLE_MASK (0x800000U) +#define SYSCON_PLL1CTRL_FRMCLKSTABLE_SHIFT (23U) +#define SYSCON_PLL1CTRL_FRMCLKSTABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_FRMCLKSTABLE_SHIFT)) & SYSCON_PLL1CTRL_FRMCLKSTABLE_MASK) +#define SYSCON_PLL1CTRL_SKEWEN_MASK (0x1000000U) +#define SYSCON_PLL1CTRL_SKEWEN_SHIFT (24U) +/*! SKEWEN - Skew mode. + * 0b1..skewmode is enable. + * 0b0..skewmode is disable. + */ +#define SYSCON_PLL1CTRL_SKEWEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SKEWEN_SHIFT)) & SYSCON_PLL1CTRL_SKEWEN_MASK) +/*! @} */ + +/*! @name PLL1STAT - PLL1 550m status */ +/*! @{ */ +#define SYSCON_PLL1STAT_LOCK_MASK (0x1U) +#define SYSCON_PLL1STAT_LOCK_SHIFT (0U) +#define SYSCON_PLL1STAT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_LOCK_SHIFT)) & SYSCON_PLL1STAT_LOCK_MASK) +#define SYSCON_PLL1STAT_PREDIVACK_MASK (0x2U) +#define SYSCON_PLL1STAT_PREDIVACK_SHIFT (1U) +#define SYSCON_PLL1STAT_PREDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_PREDIVACK_SHIFT)) & SYSCON_PLL1STAT_PREDIVACK_MASK) +#define SYSCON_PLL1STAT_FEEDDIVACK_MASK (0x4U) +#define SYSCON_PLL1STAT_FEEDDIVACK_SHIFT (2U) +#define SYSCON_PLL1STAT_FEEDDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_FEEDDIVACK_SHIFT)) & SYSCON_PLL1STAT_FEEDDIVACK_MASK) +#define SYSCON_PLL1STAT_POSTDIVACK_MASK (0x8U) +#define SYSCON_PLL1STAT_POSTDIVACK_SHIFT (3U) +#define SYSCON_PLL1STAT_POSTDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_POSTDIVACK_SHIFT)) & SYSCON_PLL1STAT_POSTDIVACK_MASK) +#define SYSCON_PLL1STAT_FRMDET_MASK (0x10U) +#define SYSCON_PLL1STAT_FRMDET_SHIFT (4U) +#define SYSCON_PLL1STAT_FRMDET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_FRMDET_SHIFT)) & SYSCON_PLL1STAT_FRMDET_MASK) +/*! @} */ + +/*! @name PLL1NDEC - PLL1 550m N divider */ +/*! @{ */ +#define SYSCON_PLL1NDEC_NDIV_MASK (0xFFU) +#define SYSCON_PLL1NDEC_NDIV_SHIFT (0U) +#define SYSCON_PLL1NDEC_NDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1NDEC_NDIV_SHIFT)) & SYSCON_PLL1NDEC_NDIV_MASK) +#define SYSCON_PLL1NDEC_NREQ_MASK (0x100U) +#define SYSCON_PLL1NDEC_NREQ_SHIFT (8U) +#define SYSCON_PLL1NDEC_NREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1NDEC_NREQ_SHIFT)) & SYSCON_PLL1NDEC_NREQ_MASK) +/*! @} */ + +/*! @name PLL1MDEC - PLL1 550m M divider */ +/*! @{ */ +#define SYSCON_PLL1MDEC_MDIV_MASK (0xFFFFU) +#define SYSCON_PLL1MDEC_MDIV_SHIFT (0U) +#define SYSCON_PLL1MDEC_MDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1MDEC_MDIV_SHIFT)) & SYSCON_PLL1MDEC_MDIV_MASK) +#define SYSCON_PLL1MDEC_MREQ_MASK (0x10000U) +#define SYSCON_PLL1MDEC_MREQ_SHIFT (16U) +#define SYSCON_PLL1MDEC_MREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1MDEC_MREQ_SHIFT)) & SYSCON_PLL1MDEC_MREQ_MASK) +/*! @} */ + +/*! @name PLL1PDEC - PLL1 550m P divider */ +/*! @{ */ +#define SYSCON_PLL1PDEC_PDIV_MASK (0x1FU) +#define SYSCON_PLL1PDEC_PDIV_SHIFT (0U) +#define SYSCON_PLL1PDEC_PDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1PDEC_PDIV_SHIFT)) & SYSCON_PLL1PDEC_PDIV_MASK) +#define SYSCON_PLL1PDEC_PREQ_MASK (0x20U) +#define SYSCON_PLL1PDEC_PREQ_SHIFT (5U) +#define SYSCON_PLL1PDEC_PREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1PDEC_PREQ_SHIFT)) & SYSCON_PLL1PDEC_PREQ_MASK) +/*! @} */ + +/*! @name PLL0CTRL - PLL0 550m control */ +/*! @{ */ +#define SYSCON_PLL0CTRL_SELR_MASK (0xFU) +#define SYSCON_PLL0CTRL_SELR_SHIFT (0U) +#define SYSCON_PLL0CTRL_SELR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SELR_SHIFT)) & SYSCON_PLL0CTRL_SELR_MASK) +#define SYSCON_PLL0CTRL_SELI_MASK (0x3F0U) +#define SYSCON_PLL0CTRL_SELI_SHIFT (4U) +#define SYSCON_PLL0CTRL_SELI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SELI_SHIFT)) & SYSCON_PLL0CTRL_SELI_MASK) +#define SYSCON_PLL0CTRL_SELP_MASK (0x7C00U) +#define SYSCON_PLL0CTRL_SELP_SHIFT (10U) +#define SYSCON_PLL0CTRL_SELP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SELP_SHIFT)) & SYSCON_PLL0CTRL_SELP_MASK) +#define SYSCON_PLL0CTRL_BYPASSPLL_MASK (0x8000U) +#define SYSCON_PLL0CTRL_BYPASSPLL_SHIFT (15U) +/*! BYPASSPLL - Bypass PLL input clock is sent directly to the PLL output (default). + * 0b1..Bypass PLL input clock is sent directly to the PLL output. + * 0b0..use PLL. + */ +#define SYSCON_PLL0CTRL_BYPASSPLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPLL_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPLL_MASK) +#define SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK (0x10000U) +#define SYSCON_PLL0CTRL_BYPASSPOSTDIV2_SHIFT (16U) +/*! BYPASSPOSTDIV2 - bypass of the divide-by-2 divider in the post-divider. + * 0b1..bypass of the divide-by-2 divider in the post-divider. + * 0b0..use the divide-by-2 divider in the post-divider. + */ +#define SYSCON_PLL0CTRL_BYPASSPOSTDIV2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPOSTDIV2_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK) +#define SYSCON_PLL0CTRL_LIMUPOFF_MASK (0x20000U) +#define SYSCON_PLL0CTRL_LIMUPOFF_SHIFT (17U) +#define SYSCON_PLL0CTRL_LIMUPOFF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_LIMUPOFF_SHIFT)) & SYSCON_PLL0CTRL_LIMUPOFF_MASK) +#define SYSCON_PLL0CTRL_BWDIRECT_MASK (0x40000U) +#define SYSCON_PLL0CTRL_BWDIRECT_SHIFT (18U) +/*! BWDIRECT - Control of the bandwidth of the PLL. + * 0b1..modify the bandwidth of the PLL directly. + * 0b0..the bandwidth is changed synchronously with the feedback-divider. + */ +#define SYSCON_PLL0CTRL_BWDIRECT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BWDIRECT_SHIFT)) & SYSCON_PLL0CTRL_BWDIRECT_MASK) +#define SYSCON_PLL0CTRL_BYPASSPREDIV_MASK (0x80000U) +#define SYSCON_PLL0CTRL_BYPASSPREDIV_SHIFT (19U) +/*! BYPASSPREDIV - bypass of the pre-divider. + * 0b1..bypass of the pre-divider. + * 0b0..use the pre-divider. + */ +#define SYSCON_PLL0CTRL_BYPASSPREDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPREDIV_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPREDIV_MASK) +#define SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK (0x100000U) +#define SYSCON_PLL0CTRL_BYPASSPOSTDIV_SHIFT (20U) +/*! BYPASSPOSTDIV - bypass of the post-divider. + * 0b1..bypass of the post-divider. + * 0b0..use the post-divider. + */ +#define SYSCON_PLL0CTRL_BYPASSPOSTDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPOSTDIV_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK) +#define SYSCON_PLL0CTRL_CLKEN_MASK (0x200000U) +#define SYSCON_PLL0CTRL_CLKEN_SHIFT (21U) +/*! CLKEN - enable the output clock. + * 0b1..enable the output clock. + * 0b0..disable the output clock. + */ +#define SYSCON_PLL0CTRL_CLKEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_CLKEN_SHIFT)) & SYSCON_PLL0CTRL_CLKEN_MASK) +#define SYSCON_PLL0CTRL_FRMEN_MASK (0x400000U) +#define SYSCON_PLL0CTRL_FRMEN_SHIFT (22U) +/*! FRMEN - free running mode. + * 0b1..free running mode is enable. + * 0b0..free running mode is disable. + */ +#define SYSCON_PLL0CTRL_FRMEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_FRMEN_SHIFT)) & SYSCON_PLL0CTRL_FRMEN_MASK) +#define SYSCON_PLL0CTRL_FRMCLKSTABLE_MASK (0x800000U) +#define SYSCON_PLL0CTRL_FRMCLKSTABLE_SHIFT (23U) +#define SYSCON_PLL0CTRL_FRMCLKSTABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_FRMCLKSTABLE_SHIFT)) & SYSCON_PLL0CTRL_FRMCLKSTABLE_MASK) +#define SYSCON_PLL0CTRL_SKEWEN_MASK (0x1000000U) +#define SYSCON_PLL0CTRL_SKEWEN_SHIFT (24U) +/*! SKEWEN - skew mode. + * 0b1..skew mode is enable. + * 0b0..skew mode is disable. + */ +#define SYSCON_PLL0CTRL_SKEWEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SKEWEN_SHIFT)) & SYSCON_PLL0CTRL_SKEWEN_MASK) +/*! @} */ + +/*! @name PLL0STAT - PLL0 550m status */ +/*! @{ */ +#define SYSCON_PLL0STAT_LOCK_MASK (0x1U) +#define SYSCON_PLL0STAT_LOCK_SHIFT (0U) +#define SYSCON_PLL0STAT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_LOCK_SHIFT)) & SYSCON_PLL0STAT_LOCK_MASK) +#define SYSCON_PLL0STAT_PREDIVACK_MASK (0x2U) +#define SYSCON_PLL0STAT_PREDIVACK_SHIFT (1U) +#define SYSCON_PLL0STAT_PREDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_PREDIVACK_SHIFT)) & SYSCON_PLL0STAT_PREDIVACK_MASK) +#define SYSCON_PLL0STAT_FEEDDIVACK_MASK (0x4U) +#define SYSCON_PLL0STAT_FEEDDIVACK_SHIFT (2U) +#define SYSCON_PLL0STAT_FEEDDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_FEEDDIVACK_SHIFT)) & SYSCON_PLL0STAT_FEEDDIVACK_MASK) +#define SYSCON_PLL0STAT_POSTDIVACK_MASK (0x8U) +#define SYSCON_PLL0STAT_POSTDIVACK_SHIFT (3U) +#define SYSCON_PLL0STAT_POSTDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_POSTDIVACK_SHIFT)) & SYSCON_PLL0STAT_POSTDIVACK_MASK) +#define SYSCON_PLL0STAT_FRMDET_MASK (0x10U) +#define SYSCON_PLL0STAT_FRMDET_SHIFT (4U) +#define SYSCON_PLL0STAT_FRMDET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_FRMDET_SHIFT)) & SYSCON_PLL0STAT_FRMDET_MASK) +/*! @} */ + +/*! @name PLL0NDEC - PLL0 550m N divider */ +/*! @{ */ +#define SYSCON_PLL0NDEC_NDIV_MASK (0xFFU) +#define SYSCON_PLL0NDEC_NDIV_SHIFT (0U) +#define SYSCON_PLL0NDEC_NDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0NDEC_NDIV_SHIFT)) & SYSCON_PLL0NDEC_NDIV_MASK) +#define SYSCON_PLL0NDEC_NREQ_MASK (0x100U) +#define SYSCON_PLL0NDEC_NREQ_SHIFT (8U) +#define SYSCON_PLL0NDEC_NREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0NDEC_NREQ_SHIFT)) & SYSCON_PLL0NDEC_NREQ_MASK) +/*! @} */ + +/*! @name PLL0PDEC - PLL0 550m P divider */ +/*! @{ */ +#define SYSCON_PLL0PDEC_PDIV_MASK (0x1FU) +#define SYSCON_PLL0PDEC_PDIV_SHIFT (0U) +#define SYSCON_PLL0PDEC_PDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0PDEC_PDIV_SHIFT)) & SYSCON_PLL0PDEC_PDIV_MASK) +#define SYSCON_PLL0PDEC_PREQ_MASK (0x20U) +#define SYSCON_PLL0PDEC_PREQ_SHIFT (5U) +#define SYSCON_PLL0PDEC_PREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0PDEC_PREQ_SHIFT)) & SYSCON_PLL0PDEC_PREQ_MASK) +/*! @} */ + +/*! @name PLL0SSCG0 - PLL0 Spread Spectrum Wrapper control register 0 */ +/*! @{ */ +#define SYSCON_PLL0SSCG0_MD_LBS_MASK (0xFFFFFFFFU) +#define SYSCON_PLL0SSCG0_MD_LBS_SHIFT (0U) +#define SYSCON_PLL0SSCG0_MD_LBS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG0_MD_LBS_SHIFT)) & SYSCON_PLL0SSCG0_MD_LBS_MASK) +/*! @} */ + +/*! @name PLL0SSCG1 - PLL0 Spread Spectrum Wrapper control register 1 */ +/*! @{ */ +#define SYSCON_PLL0SSCG1_MD_MBS_MASK (0x1U) +#define SYSCON_PLL0SSCG1_MD_MBS_SHIFT (0U) +#define SYSCON_PLL0SSCG1_MD_MBS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MD_MBS_SHIFT)) & SYSCON_PLL0SSCG1_MD_MBS_MASK) +#define SYSCON_PLL0SSCG1_MD_REQ_MASK (0x2U) +#define SYSCON_PLL0SSCG1_MD_REQ_SHIFT (1U) +#define SYSCON_PLL0SSCG1_MD_REQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MD_REQ_SHIFT)) & SYSCON_PLL0SSCG1_MD_REQ_MASK) +#define SYSCON_PLL0SSCG1_MF_MASK (0x1CU) +#define SYSCON_PLL0SSCG1_MF_SHIFT (2U) +#define SYSCON_PLL0SSCG1_MF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MF_SHIFT)) & SYSCON_PLL0SSCG1_MF_MASK) +#define SYSCON_PLL0SSCG1_MR_MASK (0xE0U) +#define SYSCON_PLL0SSCG1_MR_SHIFT (5U) +#define SYSCON_PLL0SSCG1_MR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MR_SHIFT)) & SYSCON_PLL0SSCG1_MR_MASK) +#define SYSCON_PLL0SSCG1_MC_MASK (0x300U) +#define SYSCON_PLL0SSCG1_MC_SHIFT (8U) +#define SYSCON_PLL0SSCG1_MC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MC_SHIFT)) & SYSCON_PLL0SSCG1_MC_MASK) +#define SYSCON_PLL0SSCG1_MDIV_EXT_MASK (0x3FFFC00U) +#define SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT (10U) +#define SYSCON_PLL0SSCG1_MDIV_EXT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT)) & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) +#define SYSCON_PLL0SSCG1_MREQ_MASK (0x4000000U) +#define SYSCON_PLL0SSCG1_MREQ_SHIFT (26U) +#define SYSCON_PLL0SSCG1_MREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MREQ_SHIFT)) & SYSCON_PLL0SSCG1_MREQ_MASK) +#define SYSCON_PLL0SSCG1_DITHER_MASK (0x8000000U) +#define SYSCON_PLL0SSCG1_DITHER_SHIFT (27U) +#define SYSCON_PLL0SSCG1_DITHER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_DITHER_SHIFT)) & SYSCON_PLL0SSCG1_DITHER_MASK) +#define SYSCON_PLL0SSCG1_SEL_EXT_MASK (0x10000000U) +#define SYSCON_PLL0SSCG1_SEL_EXT_SHIFT (28U) +#define SYSCON_PLL0SSCG1_SEL_EXT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_SEL_EXT_SHIFT)) & SYSCON_PLL0SSCG1_SEL_EXT_MASK) +/*! @} */ + +/*! @name EFUSECLKCTRL - eFUSE controller clock enable */ +/*! @{ */ +#define SYSCON_EFUSECLKCTRL_EFUSECLKENA_MASK (0x1U) +#define SYSCON_EFUSECLKCTRL_EFUSECLKENA_SHIFT (0U) +#define SYSCON_EFUSECLKCTRL_EFUSECLKENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EFUSECLKCTRL_EFUSECLKENA_SHIFT)) & SYSCON_EFUSECLKCTRL_EFUSECLKENA_MASK) +/*! @} */ + +/*! @name STARTER - Start logic wake-up enable register */ +/*! @{ */ +#define SYSCON_STARTER_GPIO_INT04_MASK (0x1U) +#define SYSCON_STARTER_GPIO_INT04_SHIFT (0U) +/*! GPIO_INT04 - GPIO_INT04 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_GPIO_INT04(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GPIO_INT04_SHIFT)) & SYSCON_STARTER_GPIO_INT04_MASK) +#define SYSCON_STARTER_SYS_MASK (0x1U) +#define SYSCON_STARTER_SYS_SHIFT (0U) +/*! SYS - SYS interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_SYS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SYS_SHIFT)) & SYSCON_STARTER_SYS_MASK) +#define SYSCON_STARTER_GPIO_INT05_MASK (0x2U) +#define SYSCON_STARTER_GPIO_INT05_SHIFT (1U) +/*! GPIO_INT05 - GPIO_INT05 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_GPIO_INT05(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GPIO_INT05_SHIFT)) & SYSCON_STARTER_GPIO_INT05_MASK) +#define SYSCON_STARTER_SDMA0_MASK (0x2U) +#define SYSCON_STARTER_SDMA0_SHIFT (1U) +/*! SDMA0 - SDMA0 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SDMA0_SHIFT)) & SYSCON_STARTER_SDMA0_MASK) +#define SYSCON_STARTER_GINT0_MASK (0x4U) +#define SYSCON_STARTER_GINT0_SHIFT (2U) +/*! GINT0 - GINT0 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_GINT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GINT0_SHIFT)) & SYSCON_STARTER_GINT0_MASK) +#define SYSCON_STARTER_GPIO_INT06_MASK (0x4U) +#define SYSCON_STARTER_GPIO_INT06_SHIFT (2U) +/*! GPIO_INT06 - GPIO_INT06 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_GPIO_INT06(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GPIO_INT06_SHIFT)) & SYSCON_STARTER_GPIO_INT06_MASK) +#define SYSCON_STARTER_GINT1_MASK (0x8U) +#define SYSCON_STARTER_GINT1_SHIFT (3U) +/*! GINT1 - GINT1 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_GINT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GINT1_SHIFT)) & SYSCON_STARTER_GINT1_MASK) +#define SYSCON_STARTER_GPIO_INT07_MASK (0x8U) +#define SYSCON_STARTER_GPIO_INT07_SHIFT (3U) +/*! GPIO_INT07 - GPIO_INT07 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_GPIO_INT07(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GPIO_INT07_SHIFT)) & SYSCON_STARTER_GPIO_INT07_MASK) +#define SYSCON_STARTER_CTIMER2_MASK (0x10U) +#define SYSCON_STARTER_CTIMER2_SHIFT (4U) +/*! CTIMER2 - CTIMER2 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_CTIMER2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER2_SHIFT)) & SYSCON_STARTER_CTIMER2_MASK) +#define SYSCON_STARTER_PIO_INT0_MASK (0x10U) +#define SYSCON_STARTER_PIO_INT0_SHIFT (4U) +/*! PIO_INT0 - PIO_INT0 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_PIO_INT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIO_INT0_SHIFT)) & SYSCON_STARTER_PIO_INT0_MASK) +#define SYSCON_STARTER_CTIMER4_MASK (0x20U) +#define SYSCON_STARTER_CTIMER4_SHIFT (5U) +/*! CTIMER4 - CTIMER4 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER4_SHIFT)) & SYSCON_STARTER_CTIMER4_MASK) +#define SYSCON_STARTER_PIO_INT1_MASK (0x20U) +#define SYSCON_STARTER_PIO_INT1_SHIFT (5U) +/*! PIO_INT1 - PIO_INT1 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_PIO_INT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIO_INT1_SHIFT)) & SYSCON_STARTER_PIO_INT1_MASK) +#define SYSCON_STARTER_OS_EVENT_MASK (0x40U) +#define SYSCON_STARTER_OS_EVENT_SHIFT (6U) +/*! OS_EVENT - OS_EVENT interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_OS_EVENT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_OS_EVENT_SHIFT)) & SYSCON_STARTER_OS_EVENT_MASK) +#define SYSCON_STARTER_PIO_INT2_MASK (0x40U) +#define SYSCON_STARTER_PIO_INT2_SHIFT (6U) +/*! PIO_INT2 - PIO_INT2 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_PIO_INT2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIO_INT2_SHIFT)) & SYSCON_STARTER_PIO_INT2_MASK) +#define SYSCON_STARTER_PIO_INT3_MASK (0x80U) +#define SYSCON_STARTER_PIO_INT3_SHIFT (7U) +/*! PIO_INT3 - PIO_INT3 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_PIO_INT3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIO_INT3_SHIFT)) & SYSCON_STARTER_PIO_INT3_MASK) +#define SYSCON_STARTER_UTICK0_MASK (0x100U) +#define SYSCON_STARTER_UTICK0_SHIFT (8U) +/*! UTICK0 - UTICK0 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_UTICK0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_UTICK0_SHIFT)) & SYSCON_STARTER_UTICK0_MASK) +#define SYSCON_STARTER_MRT0_MASK (0x200U) +#define SYSCON_STARTER_MRT0_SHIFT (9U) +/*! MRT0 - MRT0 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_MRT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_MRT0_SHIFT)) & SYSCON_STARTER_MRT0_MASK) +#define SYSCON_STARTER_CTIMER0_MASK (0x400U) +#define SYSCON_STARTER_CTIMER0_SHIFT (10U) +/*! CTIMER0 - CTIMER0 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_CTIMER0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER0_SHIFT)) & SYSCON_STARTER_CTIMER0_MASK) +#define SYSCON_STARTER_SDIO_MASK (0x400U) +#define SYSCON_STARTER_SDIO_SHIFT (10U) +/*! SDIO - SDIO interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_SDIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SDIO_SHIFT)) & SYSCON_STARTER_SDIO_MASK) +#define SYSCON_STARTER_CTIMER1_MASK (0x800U) +#define SYSCON_STARTER_CTIMER1_SHIFT (11U) +/*! CTIMER1 - CTIMER1 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_CTIMER1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER1_SHIFT)) & SYSCON_STARTER_CTIMER1_MASK) +#define SYSCON_STARTER_SCT0_MASK (0x1000U) +#define SYSCON_STARTER_SCT0_SHIFT (12U) +/*! SCT0 - SCT0 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_SCT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SCT0_SHIFT)) & SYSCON_STARTER_SCT0_MASK) +#define SYSCON_STARTER_CTIMER3_MASK (0x2000U) +#define SYSCON_STARTER_CTIMER3_SHIFT (13U) +/*! CTIMER3 - CTIMER3 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER3_SHIFT)) & SYSCON_STARTER_CTIMER3_MASK) +#define SYSCON_STARTER_FLEXINT0_MASK (0x4000U) +#define SYSCON_STARTER_FLEXINT0_SHIFT (14U) +/*! FLEXINT0 - FLEXINT0 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_FLEXINT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXINT0_SHIFT)) & SYSCON_STARTER_FLEXINT0_MASK) +#define SYSCON_STARTER_FLEXINT1_MASK (0x8000U) +#define SYSCON_STARTER_FLEXINT1_SHIFT (15U) +/*! FLEXINT1 - FLEXINT1 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_FLEXINT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXINT1_SHIFT)) & SYSCON_STARTER_FLEXINT1_MASK) +#define SYSCON_STARTER_USB1_MASK (0x8000U) +#define SYSCON_STARTER_USB1_SHIFT (15U) +/*! USB1 - USB1 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_USB1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB1_SHIFT)) & SYSCON_STARTER_USB1_MASK) +#define SYSCON_STARTER_FLEXINT2_MASK (0x10000U) +#define SYSCON_STARTER_FLEXINT2_SHIFT (16U) +/*! FLEXINT2 - FLEXINT2 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_FLEXINT2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXINT2_SHIFT)) & SYSCON_STARTER_FLEXINT2_MASK) +#define SYSCON_STARTER_USB1_NEEDCLK_MASK (0x10000U) +#define SYSCON_STARTER_USB1_NEEDCLK_SHIFT (16U) +/*! USB1_NEEDCLK - USB1_NEEDCLK interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_USB1_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB1_NEEDCLK_SHIFT)) & SYSCON_STARTER_USB1_NEEDCLK_MASK) +#define SYSCON_STARTER_FLEXINT3_MASK (0x20000U) +#define SYSCON_STARTER_FLEXINT3_SHIFT (17U) +/*! FLEXINT3 - FLEXINT3 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_FLEXINT3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXINT3_SHIFT)) & SYSCON_STARTER_FLEXINT3_MASK) +#define SYSCON_STARTER_SEC_HYPERVISOR_CALL_MASK (0x20000U) +#define SYSCON_STARTER_SEC_HYPERVISOR_CALL_SHIFT (17U) +/*! SEC_HYPERVISOR_CALL - SEC_HYPERVISOR_CALL interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_SEC_HYPERVISOR_CALL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SEC_HYPERVISOR_CALL_SHIFT)) & SYSCON_STARTER_SEC_HYPERVISOR_CALL_MASK) +#define SYSCON_STARTER_FLEXINT4_MASK (0x40000U) +#define SYSCON_STARTER_FLEXINT4_SHIFT (18U) +/*! FLEXINT4 - FLEXINT4 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_FLEXINT4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXINT4_SHIFT)) & SYSCON_STARTER_FLEXINT4_MASK) +#define SYSCON_STARTER_SEC_GPIO_INT00_MASK (0x40000U) +#define SYSCON_STARTER_SEC_GPIO_INT00_SHIFT (18U) +/*! SEC_GPIO_INT00 - SEC_GPIO_INT00 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_SEC_GPIO_INT00(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SEC_GPIO_INT00_SHIFT)) & SYSCON_STARTER_SEC_GPIO_INT00_MASK) +#define SYSCON_STARTER_FLEXINT5_MASK (0x80000U) +#define SYSCON_STARTER_FLEXINT5_SHIFT (19U) +/*! FLEXINT5 - FLEXINT5 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_FLEXINT5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXINT5_SHIFT)) & SYSCON_STARTER_FLEXINT5_MASK) +#define SYSCON_STARTER_SEC_GPIO_INT01_MASK (0x80000U) +#define SYSCON_STARTER_SEC_GPIO_INT01_SHIFT (19U) +/*! SEC_GPIO_INT01 - SEC_GPIO_INT01 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_SEC_GPIO_INT01(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SEC_GPIO_INT01_SHIFT)) & SYSCON_STARTER_SEC_GPIO_INT01_MASK) +#define SYSCON_STARTER_FLEXINT6_MASK (0x100000U) +#define SYSCON_STARTER_FLEXINT6_SHIFT (20U) +/*! FLEXINT6 - FLEXINT6 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_FLEXINT6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXINT6_SHIFT)) & SYSCON_STARTER_FLEXINT6_MASK) +#define SYSCON_STARTER_PLU_MASK (0x100000U) +#define SYSCON_STARTER_PLU_SHIFT (20U) +/*! PLU - PLU interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_PLU(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PLU_SHIFT)) & SYSCON_STARTER_PLU_MASK) +#define SYSCON_STARTER_FLEXINT7_MASK (0x200000U) +#define SYSCON_STARTER_FLEXINT7_SHIFT (21U) +/*! FLEXINT7 - FLEXINT7 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_FLEXINT7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXINT7_SHIFT)) & SYSCON_STARTER_FLEXINT7_MASK) +#define SYSCON_STARTER_SEC_VIO_MASK (0x200000U) +#define SYSCON_STARTER_SEC_VIO_SHIFT (21U) +/*! SEC_VIO - SEC_VIO interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_SEC_VIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SEC_VIO_SHIFT)) & SYSCON_STARTER_SEC_VIO_MASK) +#define SYSCON_STARTER_ADC0_MASK (0x400000U) +#define SYSCON_STARTER_ADC0_SHIFT (22U) +/*! ADC0 - ADC0 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ADC0_SHIFT)) & SYSCON_STARTER_ADC0_MASK) +#define SYSCON_STARTER_SHA_MASK (0x400000U) +#define SYSCON_STARTER_SHA_SHIFT (22U) +/*! SHA - SHA interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_SHA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SHA_SHIFT)) & SYSCON_STARTER_SHA_MASK) +#define SYSCON_STARTER_CASER_MASK (0x800000U) +#define SYSCON_STARTER_CASER_SHIFT (23U) +/*! CASER - CASER interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_CASER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CASER_SHIFT)) & SYSCON_STARTER_CASER_MASK) +#define SYSCON_STARTER_ADC0_THCMP_OVR_MASK (0x1000000U) +#define SYSCON_STARTER_ADC0_THCMP_OVR_SHIFT (24U) +/*! ADC0_THCMP_OVR - ADC0_THCMP_OVR interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_ADC0_THCMP_OVR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ADC0_THCMP_OVR_SHIFT)) & SYSCON_STARTER_ADC0_THCMP_OVR_MASK) +#define SYSCON_STARTER_QDDKEY_MASK (0x1000000U) +#define SYSCON_STARTER_QDDKEY_SHIFT (24U) +/*! QDDKEY - QDDKEY interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_QDDKEY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_QDDKEY_SHIFT)) & SYSCON_STARTER_QDDKEY_MASK) +#define SYSCON_STARTER_PQ_MASK (0x2000000U) +#define SYSCON_STARTER_PQ_SHIFT (25U) +/*! PQ - PQ interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_PQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PQ_SHIFT)) & SYSCON_STARTER_PQ_MASK) +#define SYSCON_STARTER_SDMA1_MASK (0x4000000U) +#define SYSCON_STARTER_SDMA1_SHIFT (26U) +/*! SDMA1 - SDMA1 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SDMA1_SHIFT)) & SYSCON_STARTER_SDMA1_MASK) +#define SYSCON_STARTER_LSPI_HS_MASK (0x8000000U) +#define SYSCON_STARTER_LSPI_HS_SHIFT (27U) +/*! LSPI_HS - LSPI_HS interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_LSPI_HS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_LSPI_HS_SHIFT)) & SYSCON_STARTER_LSPI_HS_MASK) +#define SYSCON_STARTER_USB0_NEEDCLK_MASK (0x8000000U) +#define SYSCON_STARTER_USB0_NEEDCLK_SHIFT (27U) +/*! USB0_NEEDCLK - USB0_NEEDCLK interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_USB0_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB0_NEEDCLK_SHIFT)) & SYSCON_STARTER_USB0_NEEDCLK_MASK) +#define SYSCON_STARTER_USB0_MASK (0x10000000U) +#define SYSCON_STARTER_USB0_SHIFT (28U) +/*! USB0 - USB0 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_USB0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB0_SHIFT)) & SYSCON_STARTER_USB0_MASK) +#define SYSCON_STARTER_RTC_LITE0_MASK (0x20000000U) +#define SYSCON_STARTER_RTC_LITE0_SHIFT (29U) +/*! RTC_LITE0 - RTC_LITE0 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_RTC_LITE0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_RTC_LITE0_SHIFT)) & SYSCON_STARTER_RTC_LITE0_MASK) +#define SYSCON_STARTER_EZH_ARCH_B0_MASK (0x40000000U) +#define SYSCON_STARTER_EZH_ARCH_B0_SHIFT (30U) +/*! EZH_ARCH_B0 - EZH_ARCH_B0 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_EZH_ARCH_B0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_EZH_ARCH_B0_SHIFT)) & SYSCON_STARTER_EZH_ARCH_B0_MASK) +#define SYSCON_STARTER_WAKEUPPADS_MASK (0x80000000U) +#define SYSCON_STARTER_WAKEUPPADS_SHIFT (31U) +#define SYSCON_STARTER_WAKEUPPADS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_WAKEUPPADS_SHIFT)) & SYSCON_STARTER_WAKEUPPADS_MASK) +#define SYSCON_STARTER_WAKEUP_MAILBOX0_MASK (0x80000000U) +#define SYSCON_STARTER_WAKEUP_MAILBOX0_SHIFT (31U) +/*! WAKEUP_MAILBOX0 - WAKEUP_MAILBOX0 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_WAKEUP_MAILBOX0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_WAKEUP_MAILBOX0_SHIFT)) & SYSCON_STARTER_WAKEUP_MAILBOX0_MASK) +/*! @} */ + +/* The count of SYSCON_STARTER */ +#define SYSCON_STARTER_COUNT (2U) + +/*! @name STARTERSET - Set bits in STARTER */ +/*! @{ */ +#define SYSCON_STARTERSET_GPIO_INT04_SET_MASK (0x1U) +#define SYSCON_STARTERSET_GPIO_INT04_SET_SHIFT (0U) +#define SYSCON_STARTERSET_GPIO_INT04_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_INT04_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_INT04_SET_MASK) +#define SYSCON_STARTERSET_SYS_SET_MASK (0x1U) +#define SYSCON_STARTERSET_SYS_SET_SHIFT (0U) +#define SYSCON_STARTERSET_SYS_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SYS_SET_SHIFT)) & SYSCON_STARTERSET_SYS_SET_MASK) +#define SYSCON_STARTERSET_GPIO_INT05_SET_MASK (0x2U) +#define SYSCON_STARTERSET_GPIO_INT05_SET_SHIFT (1U) +#define SYSCON_STARTERSET_GPIO_INT05_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_INT05_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_INT05_SET_MASK) +#define SYSCON_STARTERSET_SDMA0_SET_MASK (0x2U) +#define SYSCON_STARTERSET_SDMA0_SET_SHIFT (1U) +#define SYSCON_STARTERSET_SDMA0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SDMA0_SET_SHIFT)) & SYSCON_STARTERSET_SDMA0_SET_MASK) +#define SYSCON_STARTERSET_GPIO_GLOBALINT0_SET_MASK (0x4U) +#define SYSCON_STARTERSET_GPIO_GLOBALINT0_SET_SHIFT (2U) +#define SYSCON_STARTERSET_GPIO_GLOBALINT0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_GLOBALINT0_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_GLOBALINT0_SET_MASK) +#define SYSCON_STARTERSET_GPIO_INT06_SET_MASK (0x4U) +#define SYSCON_STARTERSET_GPIO_INT06_SET_SHIFT (2U) +#define SYSCON_STARTERSET_GPIO_INT06_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_INT06_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_INT06_SET_MASK) +#define SYSCON_STARTERSET_GPIO_GLOBALINT1_SET_MASK (0x8U) +#define SYSCON_STARTERSET_GPIO_GLOBALINT1_SET_SHIFT (3U) +#define SYSCON_STARTERSET_GPIO_GLOBALINT1_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_GLOBALINT1_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_GLOBALINT1_SET_MASK) +#define SYSCON_STARTERSET_GPIO_INT07_SET_MASK (0x8U) +#define SYSCON_STARTERSET_GPIO_INT07_SET_SHIFT (3U) +#define SYSCON_STARTERSET_GPIO_INT07_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_INT07_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_INT07_SET_MASK) +#define SYSCON_STARTERSET_CTIMER2_SET_MASK (0x10U) +#define SYSCON_STARTERSET_CTIMER2_SET_SHIFT (4U) +#define SYSCON_STARTERSET_CTIMER2_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_CTIMER2_SET_SHIFT)) & SYSCON_STARTERSET_CTIMER2_SET_MASK) +#define SYSCON_STARTERSET_GPIO_INT00_SET_MASK (0x10U) +#define SYSCON_STARTERSET_GPIO_INT00_SET_SHIFT (4U) +#define SYSCON_STARTERSET_GPIO_INT00_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_INT00_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_INT00_SET_MASK) +#define SYSCON_STARTERSET_CTIMER4_SET_MASK (0x20U) +#define SYSCON_STARTERSET_CTIMER4_SET_SHIFT (5U) +#define SYSCON_STARTERSET_CTIMER4_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_CTIMER4_SET_SHIFT)) & SYSCON_STARTERSET_CTIMER4_SET_MASK) +#define SYSCON_STARTERSET_GPIO_INT01_SET_MASK (0x20U) +#define SYSCON_STARTERSET_GPIO_INT01_SET_SHIFT (5U) +#define SYSCON_STARTERSET_GPIO_INT01_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_INT01_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_INT01_SET_MASK) +#define SYSCON_STARTERSET_GPIO_INT02_SET_MASK (0x40U) +#define SYSCON_STARTERSET_GPIO_INT02_SET_SHIFT (6U) +#define SYSCON_STARTERSET_GPIO_INT02_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_INT02_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_INT02_SET_MASK) +#define SYSCON_STARTERSET_OS_EVENT_SET_MASK (0x40U) +#define SYSCON_STARTERSET_OS_EVENT_SET_SHIFT (6U) +#define SYSCON_STARTERSET_OS_EVENT_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_OS_EVENT_SET_SHIFT)) & SYSCON_STARTERSET_OS_EVENT_SET_MASK) +#define SYSCON_STARTERSET_GPIO_INT03_SET_MASK (0x80U) +#define SYSCON_STARTERSET_GPIO_INT03_SET_SHIFT (7U) +#define SYSCON_STARTERSET_GPIO_INT03_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_INT03_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_INT03_SET_MASK) +#define SYSCON_STARTERSET_UTICK0_SET_MASK (0x100U) +#define SYSCON_STARTERSET_UTICK0_SET_SHIFT (8U) +#define SYSCON_STARTERSET_UTICK0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_UTICK0_SET_SHIFT)) & SYSCON_STARTERSET_UTICK0_SET_MASK) +#define SYSCON_STARTERSET_MRT0_SET_MASK (0x200U) +#define SYSCON_STARTERSET_MRT0_SET_SHIFT (9U) +#define SYSCON_STARTERSET_MRT0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_MRT0_SET_SHIFT)) & SYSCON_STARTERSET_MRT0_SET_MASK) +#define SYSCON_STARTERSET_CTIMER0_SET_MASK (0x400U) +#define SYSCON_STARTERSET_CTIMER0_SET_SHIFT (10U) +#define SYSCON_STARTERSET_CTIMER0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_CTIMER0_SET_SHIFT)) & SYSCON_STARTERSET_CTIMER0_SET_MASK) +#define SYSCON_STARTERSET_SDIO_SET_MASK (0x400U) +#define SYSCON_STARTERSET_SDIO_SET_SHIFT (10U) +#define SYSCON_STARTERSET_SDIO_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SDIO_SET_SHIFT)) & SYSCON_STARTERSET_SDIO_SET_MASK) +#define SYSCON_STARTERSET_CTIMER1_SET_MASK (0x800U) +#define SYSCON_STARTERSET_CTIMER1_SET_SHIFT (11U) +#define SYSCON_STARTERSET_CTIMER1_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_CTIMER1_SET_SHIFT)) & SYSCON_STARTERSET_CTIMER1_SET_MASK) +#define SYSCON_STARTERSET_SCT0_SET_MASK (0x1000U) +#define SYSCON_STARTERSET_SCT0_SET_SHIFT (12U) +#define SYSCON_STARTERSET_SCT0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SCT0_SET_SHIFT)) & SYSCON_STARTERSET_SCT0_SET_MASK) +#define SYSCON_STARTERSET_CTIMER3_SET_MASK (0x2000U) +#define SYSCON_STARTERSET_CTIMER3_SET_SHIFT (13U) +#define SYSCON_STARTERSET_CTIMER3_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_CTIMER3_SET_SHIFT)) & SYSCON_STARTERSET_CTIMER3_SET_MASK) +#define SYSCON_STARTERSET_FLEXINT0_SET_MASK (0x4000U) +#define SYSCON_STARTERSET_FLEXINT0_SET_SHIFT (14U) +#define SYSCON_STARTERSET_FLEXINT0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXINT0_SET_SHIFT)) & SYSCON_STARTERSET_FLEXINT0_SET_MASK) +#define SYSCON_STARTERSET_FLEXINT1_SET_MASK (0x8000U) +#define SYSCON_STARTERSET_FLEXINT1_SET_SHIFT (15U) +#define SYSCON_STARTERSET_FLEXINT1_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXINT1_SET_SHIFT)) & SYSCON_STARTERSET_FLEXINT1_SET_MASK) +#define SYSCON_STARTERSET_USB1_SET_MASK (0x8000U) +#define SYSCON_STARTERSET_USB1_SET_SHIFT (15U) +#define SYSCON_STARTERSET_USB1_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_USB1_SET_SHIFT)) & SYSCON_STARTERSET_USB1_SET_MASK) +#define SYSCON_STARTERSET_FLEXINT2_SET_MASK (0x10000U) +#define SYSCON_STARTERSET_FLEXINT2_SET_SHIFT (16U) +#define SYSCON_STARTERSET_FLEXINT2_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXINT2_SET_SHIFT)) & SYSCON_STARTERSET_FLEXINT2_SET_MASK) +#define SYSCON_STARTERSET_USB1_NEEDCLK_SET_MASK (0x10000U) +#define SYSCON_STARTERSET_USB1_NEEDCLK_SET_SHIFT (16U) +#define SYSCON_STARTERSET_USB1_NEEDCLK_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_USB1_NEEDCLK_SET_SHIFT)) & SYSCON_STARTERSET_USB1_NEEDCLK_SET_MASK) +#define SYSCON_STARTERSET_FLEXINT3_SET_MASK (0x20000U) +#define SYSCON_STARTERSET_FLEXINT3_SET_SHIFT (17U) +#define SYSCON_STARTERSET_FLEXINT3_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXINT3_SET_SHIFT)) & SYSCON_STARTERSET_FLEXINT3_SET_MASK) +#define SYSCON_STARTERSET_SEC_HYPERVISOR_CALL_SET_MASK (0x20000U) +#define SYSCON_STARTERSET_SEC_HYPERVISOR_CALL_SET_SHIFT (17U) +#define SYSCON_STARTERSET_SEC_HYPERVISOR_CALL_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SEC_HYPERVISOR_CALL_SET_SHIFT)) & SYSCON_STARTERSET_SEC_HYPERVISOR_CALL_SET_MASK) +#define SYSCON_STARTERSET_FLEXINT4_SET_MASK (0x40000U) +#define SYSCON_STARTERSET_FLEXINT4_SET_SHIFT (18U) +#define SYSCON_STARTERSET_FLEXINT4_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXINT4_SET_SHIFT)) & SYSCON_STARTERSET_FLEXINT4_SET_MASK) +#define SYSCON_STARTERSET_SEC_GPIO_INT00_SET_MASK (0x40000U) +#define SYSCON_STARTERSET_SEC_GPIO_INT00_SET_SHIFT (18U) +#define SYSCON_STARTERSET_SEC_GPIO_INT00_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SEC_GPIO_INT00_SET_SHIFT)) & SYSCON_STARTERSET_SEC_GPIO_INT00_SET_MASK) +#define SYSCON_STARTERSET_FLEXINT5_SET_MASK (0x80000U) +#define SYSCON_STARTERSET_FLEXINT5_SET_SHIFT (19U) +#define SYSCON_STARTERSET_FLEXINT5_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXINT5_SET_SHIFT)) & SYSCON_STARTERSET_FLEXINT5_SET_MASK) +#define SYSCON_STARTERSET_SEC_GPIO_INT01_SET_MASK (0x80000U) +#define SYSCON_STARTERSET_SEC_GPIO_INT01_SET_SHIFT (19U) +#define SYSCON_STARTERSET_SEC_GPIO_INT01_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SEC_GPIO_INT01_SET_SHIFT)) & SYSCON_STARTERSET_SEC_GPIO_INT01_SET_MASK) +#define SYSCON_STARTERSET_FLEXINT6_SET_MASK (0x100000U) +#define SYSCON_STARTERSET_FLEXINT6_SET_SHIFT (20U) +#define SYSCON_STARTERSET_FLEXINT6_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXINT6_SET_SHIFT)) & SYSCON_STARTERSET_FLEXINT6_SET_MASK) +#define SYSCON_STARTERSET_PLU_SET_MASK (0x100000U) +#define SYSCON_STARTERSET_PLU_SET_SHIFT (20U) +#define SYSCON_STARTERSET_PLU_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_PLU_SET_SHIFT)) & SYSCON_STARTERSET_PLU_SET_MASK) +#define SYSCON_STARTERSET_FLEXINT7_SET_MASK (0x200000U) +#define SYSCON_STARTERSET_FLEXINT7_SET_SHIFT (21U) +#define SYSCON_STARTERSET_FLEXINT7_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXINT7_SET_SHIFT)) & SYSCON_STARTERSET_FLEXINT7_SET_MASK) +#define SYSCON_STARTERSET_SEC_VIO_SET_MASK (0x200000U) +#define SYSCON_STARTERSET_SEC_VIO_SET_SHIFT (21U) +#define SYSCON_STARTERSET_SEC_VIO_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SEC_VIO_SET_SHIFT)) & SYSCON_STARTERSET_SEC_VIO_SET_MASK) +#define SYSCON_STARTERSET_ADC0_SET_MASK (0x400000U) +#define SYSCON_STARTERSET_ADC0_SET_SHIFT (22U) +#define SYSCON_STARTERSET_ADC0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_ADC0_SET_SHIFT)) & SYSCON_STARTERSET_ADC0_SET_MASK) +#define SYSCON_STARTERSET_SHA_SET_MASK (0x400000U) +#define SYSCON_STARTERSET_SHA_SET_SHIFT (22U) +#define SYSCON_STARTERSET_SHA_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SHA_SET_SHIFT)) & SYSCON_STARTERSET_SHA_SET_MASK) +#define SYSCON_STARTERSET_CASER_SET_MASK (0x800000U) +#define SYSCON_STARTERSET_CASER_SET_SHIFT (23U) +#define SYSCON_STARTERSET_CASER_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_CASER_SET_SHIFT)) & SYSCON_STARTERSET_CASER_SET_MASK) +#define SYSCON_STARTERSET_ADC0_THCMP_OVR_SET_MASK (0x1000000U) +#define SYSCON_STARTERSET_ADC0_THCMP_OVR_SET_SHIFT (24U) +#define SYSCON_STARTERSET_ADC0_THCMP_OVR_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_ADC0_THCMP_OVR_SET_SHIFT)) & SYSCON_STARTERSET_ADC0_THCMP_OVR_SET_MASK) +#define SYSCON_STARTERSET_QDDKEY_SET_MASK (0x1000000U) +#define SYSCON_STARTERSET_QDDKEY_SET_SHIFT (24U) +#define SYSCON_STARTERSET_QDDKEY_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_QDDKEY_SET_SHIFT)) & SYSCON_STARTERSET_QDDKEY_SET_MASK) +#define SYSCON_STARTERSET_PQ_SET_MASK (0x2000000U) +#define SYSCON_STARTERSET_PQ_SET_SHIFT (25U) +#define SYSCON_STARTERSET_PQ_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_PQ_SET_SHIFT)) & SYSCON_STARTERSET_PQ_SET_MASK) +#define SYSCON_STARTERSET_SDMA1_SET_MASK (0x4000000U) +#define SYSCON_STARTERSET_SDMA1_SET_SHIFT (26U) +#define SYSCON_STARTERSET_SDMA1_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SDMA1_SET_SHIFT)) & SYSCON_STARTERSET_SDMA1_SET_MASK) +#define SYSCON_STARTERSET_LSPI_HS_SET_MASK (0x8000000U) +#define SYSCON_STARTERSET_LSPI_HS_SET_SHIFT (27U) +#define SYSCON_STARTERSET_LSPI_HS_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_LSPI_HS_SET_SHIFT)) & SYSCON_STARTERSET_LSPI_HS_SET_MASK) +#define SYSCON_STARTERSET_USB0_NEEDCLK_SET_MASK (0x8000000U) +#define SYSCON_STARTERSET_USB0_NEEDCLK_SET_SHIFT (27U) +#define SYSCON_STARTERSET_USB0_NEEDCLK_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_USB0_NEEDCLK_SET_SHIFT)) & SYSCON_STARTERSET_USB0_NEEDCLK_SET_MASK) +#define SYSCON_STARTERSET_USB0_SET_MASK (0x10000000U) +#define SYSCON_STARTERSET_USB0_SET_SHIFT (28U) +#define SYSCON_STARTERSET_USB0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_USB0_SET_SHIFT)) & SYSCON_STARTERSET_USB0_SET_MASK) +#define SYSCON_STARTERSET_RTC_LITE0_SET_MASK (0x20000000U) +#define SYSCON_STARTERSET_RTC_LITE0_SET_SHIFT (29U) +#define SYSCON_STARTERSET_RTC_LITE0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_RTC_LITE0_SET_SHIFT)) & SYSCON_STARTERSET_RTC_LITE0_SET_MASK) +#define SYSCON_STARTERSET_EZH_ARCH_B0_SET_MASK (0x40000000U) +#define SYSCON_STARTERSET_EZH_ARCH_B0_SET_SHIFT (30U) +#define SYSCON_STARTERSET_EZH_ARCH_B0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_EZH_ARCH_B0_SET_SHIFT)) & SYSCON_STARTERSET_EZH_ARCH_B0_SET_MASK) +#define SYSCON_STARTERSET_WAKEUPPADS_SET_MASK (0x80000000U) +#define SYSCON_STARTERSET_WAKEUPPADS_SET_SHIFT (31U) +#define SYSCON_STARTERSET_WAKEUPPADS_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_WAKEUPPADS_SET_SHIFT)) & SYSCON_STARTERSET_WAKEUPPADS_SET_MASK) +#define SYSCON_STARTERSET_WAKEUP_MAILBOX0_SET_MASK (0x80000000U) +#define SYSCON_STARTERSET_WAKEUP_MAILBOX0_SET_SHIFT (31U) +#define SYSCON_STARTERSET_WAKEUP_MAILBOX0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_WAKEUP_MAILBOX0_SET_SHIFT)) & SYSCON_STARTERSET_WAKEUP_MAILBOX0_SET_MASK) +/*! @} */ + +/* The count of SYSCON_STARTERSET */ +#define SYSCON_STARTERSET_COUNT (2U) + +/*! @name STARTERCLR - Clear bits in STARTER */ +/*! @{ */ +#define SYSCON_STARTERCLR_GPIO_INT04_CLR_MASK (0x1U) +#define SYSCON_STARTERCLR_GPIO_INT04_CLR_SHIFT (0U) +#define SYSCON_STARTERCLR_GPIO_INT04_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_INT04_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_INT04_CLR_MASK) +#define SYSCON_STARTERCLR_SYS_CLR_MASK (0x1U) +#define SYSCON_STARTERCLR_SYS_CLR_SHIFT (0U) +#define SYSCON_STARTERCLR_SYS_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SYS_CLR_SHIFT)) & SYSCON_STARTERCLR_SYS_CLR_MASK) +#define SYSCON_STARTERCLR_GPIO_INT05_CLR_MASK (0x2U) +#define SYSCON_STARTERCLR_GPIO_INT05_CLR_SHIFT (1U) +#define SYSCON_STARTERCLR_GPIO_INT05_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_INT05_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_INT05_CLR_MASK) +#define SYSCON_STARTERCLR_SDMA0_CLR_MASK (0x2U) +#define SYSCON_STARTERCLR_SDMA0_CLR_SHIFT (1U) +#define SYSCON_STARTERCLR_SDMA0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SDMA0_CLR_SHIFT)) & SYSCON_STARTERCLR_SDMA0_CLR_MASK) +#define SYSCON_STARTERCLR_GPIO_GLOBALINT0_CLR_MASK (0x4U) +#define SYSCON_STARTERCLR_GPIO_GLOBALINT0_CLR_SHIFT (2U) +#define SYSCON_STARTERCLR_GPIO_GLOBALINT0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_GLOBALINT0_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_GLOBALINT0_CLR_MASK) +#define SYSCON_STARTERCLR_GPIO_INT06_CLR_MASK (0x4U) +#define SYSCON_STARTERCLR_GPIO_INT06_CLR_SHIFT (2U) +#define SYSCON_STARTERCLR_GPIO_INT06_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_INT06_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_INT06_CLR_MASK) +#define SYSCON_STARTERCLR_GPIO_GLOBALINT1_CLR_MASK (0x8U) +#define SYSCON_STARTERCLR_GPIO_GLOBALINT1_CLR_SHIFT (3U) +#define SYSCON_STARTERCLR_GPIO_GLOBALINT1_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_GLOBALINT1_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_GLOBALINT1_CLR_MASK) +#define SYSCON_STARTERCLR_GPIO_INT07_CLR_MASK (0x8U) +#define SYSCON_STARTERCLR_GPIO_INT07_CLR_SHIFT (3U) +#define SYSCON_STARTERCLR_GPIO_INT07_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_INT07_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_INT07_CLR_MASK) +#define SYSCON_STARTERCLR_CTIMER2_CLR_MASK (0x10U) +#define SYSCON_STARTERCLR_CTIMER2_CLR_SHIFT (4U) +#define SYSCON_STARTERCLR_CTIMER2_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_CTIMER2_CLR_SHIFT)) & SYSCON_STARTERCLR_CTIMER2_CLR_MASK) +#define SYSCON_STARTERCLR_GPIO_INT00_CLR_MASK (0x10U) +#define SYSCON_STARTERCLR_GPIO_INT00_CLR_SHIFT (4U) +#define SYSCON_STARTERCLR_GPIO_INT00_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_INT00_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_INT00_CLR_MASK) +#define SYSCON_STARTERCLR_CTIMER4_CLR_MASK (0x20U) +#define SYSCON_STARTERCLR_CTIMER4_CLR_SHIFT (5U) +#define SYSCON_STARTERCLR_CTIMER4_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_CTIMER4_CLR_SHIFT)) & SYSCON_STARTERCLR_CTIMER4_CLR_MASK) +#define SYSCON_STARTERCLR_GPIO_INT01_CLR_MASK (0x20U) +#define SYSCON_STARTERCLR_GPIO_INT01_CLR_SHIFT (5U) +#define SYSCON_STARTERCLR_GPIO_INT01_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_INT01_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_INT01_CLR_MASK) +#define SYSCON_STARTERCLR_GPIO_INT02_CLR_MASK (0x40U) +#define SYSCON_STARTERCLR_GPIO_INT02_CLR_SHIFT (6U) +#define SYSCON_STARTERCLR_GPIO_INT02_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_INT02_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_INT02_CLR_MASK) +#define SYSCON_STARTERCLR_OS_EVENT_CLR_MASK (0x40U) +#define SYSCON_STARTERCLR_OS_EVENT_CLR_SHIFT (6U) +#define SYSCON_STARTERCLR_OS_EVENT_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_OS_EVENT_CLR_SHIFT)) & SYSCON_STARTERCLR_OS_EVENT_CLR_MASK) +#define SYSCON_STARTERCLR_GPIO_INT03_CLR_MASK (0x80U) +#define SYSCON_STARTERCLR_GPIO_INT03_CLR_SHIFT (7U) +#define SYSCON_STARTERCLR_GPIO_INT03_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_INT03_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_INT03_CLR_MASK) +#define SYSCON_STARTERCLR_UTICK0_CLR_MASK (0x100U) +#define SYSCON_STARTERCLR_UTICK0_CLR_SHIFT (8U) +#define SYSCON_STARTERCLR_UTICK0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_UTICK0_CLR_SHIFT)) & SYSCON_STARTERCLR_UTICK0_CLR_MASK) +#define SYSCON_STARTERCLR_MRT0_CLR_MASK (0x200U) +#define SYSCON_STARTERCLR_MRT0_CLR_SHIFT (9U) +#define SYSCON_STARTERCLR_MRT0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_MRT0_CLR_SHIFT)) & SYSCON_STARTERCLR_MRT0_CLR_MASK) +#define SYSCON_STARTERCLR_CTIMER0_CLR_MASK (0x400U) +#define SYSCON_STARTERCLR_CTIMER0_CLR_SHIFT (10U) +#define SYSCON_STARTERCLR_CTIMER0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_CTIMER0_CLR_SHIFT)) & SYSCON_STARTERCLR_CTIMER0_CLR_MASK) +#define SYSCON_STARTERCLR_SDIO_CLR_MASK (0x400U) +#define SYSCON_STARTERCLR_SDIO_CLR_SHIFT (10U) +#define SYSCON_STARTERCLR_SDIO_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SDIO_CLR_SHIFT)) & SYSCON_STARTERCLR_SDIO_CLR_MASK) +#define SYSCON_STARTERCLR_CTIMER1_CLR_MASK (0x800U) +#define SYSCON_STARTERCLR_CTIMER1_CLR_SHIFT (11U) +#define SYSCON_STARTERCLR_CTIMER1_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_CTIMER1_CLR_SHIFT)) & SYSCON_STARTERCLR_CTIMER1_CLR_MASK) +#define SYSCON_STARTERCLR_SCT0_CLR_MASK (0x1000U) +#define SYSCON_STARTERCLR_SCT0_CLR_SHIFT (12U) +#define SYSCON_STARTERCLR_SCT0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SCT0_CLR_SHIFT)) & SYSCON_STARTERCLR_SCT0_CLR_MASK) +#define SYSCON_STARTERCLR_CTIMER3_CLR_MASK (0x2000U) +#define SYSCON_STARTERCLR_CTIMER3_CLR_SHIFT (13U) +#define SYSCON_STARTERCLR_CTIMER3_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_CTIMER3_CLR_SHIFT)) & SYSCON_STARTERCLR_CTIMER3_CLR_MASK) +#define SYSCON_STARTERCLR_FLEXINT0_CLR_MASK (0x4000U) +#define SYSCON_STARTERCLR_FLEXINT0_CLR_SHIFT (14U) +#define SYSCON_STARTERCLR_FLEXINT0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_FLEXINT0_CLR_SHIFT)) & SYSCON_STARTERCLR_FLEXINT0_CLR_MASK) +#define SYSCON_STARTERCLR_FLEXINT1_CLR_MASK (0x8000U) +#define SYSCON_STARTERCLR_FLEXINT1_CLR_SHIFT (15U) +#define SYSCON_STARTERCLR_FLEXINT1_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_FLEXINT1_CLR_SHIFT)) & SYSCON_STARTERCLR_FLEXINT1_CLR_MASK) +#define SYSCON_STARTERCLR_USB1_CLR_MASK (0x8000U) +#define SYSCON_STARTERCLR_USB1_CLR_SHIFT (15U) +#define SYSCON_STARTERCLR_USB1_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_USB1_CLR_SHIFT)) & SYSCON_STARTERCLR_USB1_CLR_MASK) +#define SYSCON_STARTERCLR_FLEXINT2_CLR_MASK (0x10000U) +#define SYSCON_STARTERCLR_FLEXINT2_CLR_SHIFT (16U) +#define SYSCON_STARTERCLR_FLEXINT2_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_FLEXINT2_CLR_SHIFT)) & SYSCON_STARTERCLR_FLEXINT2_CLR_MASK) +#define SYSCON_STARTERCLR_USB1_NEEDCLK_CLR_MASK (0x10000U) +#define SYSCON_STARTERCLR_USB1_NEEDCLK_CLR_SHIFT (16U) +#define SYSCON_STARTERCLR_USB1_NEEDCLK_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_USB1_NEEDCLK_CLR_SHIFT)) & SYSCON_STARTERCLR_USB1_NEEDCLK_CLR_MASK) +#define SYSCON_STARTERCLR_FLEXINT3_CLR_MASK (0x20000U) +#define SYSCON_STARTERCLR_FLEXINT3_CLR_SHIFT (17U) +#define SYSCON_STARTERCLR_FLEXINT3_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_FLEXINT3_CLR_SHIFT)) & SYSCON_STARTERCLR_FLEXINT3_CLR_MASK) +#define SYSCON_STARTERCLR_SEC_HYPERVISOR_CALL_CLR_MASK (0x20000U) +#define SYSCON_STARTERCLR_SEC_HYPERVISOR_CALL_CLR_SHIFT (17U) +#define SYSCON_STARTERCLR_SEC_HYPERVISOR_CALL_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SEC_HYPERVISOR_CALL_CLR_SHIFT)) & SYSCON_STARTERCLR_SEC_HYPERVISOR_CALL_CLR_MASK) +#define SYSCON_STARTERCLR_FLEXINT4_CLR_MASK (0x40000U) +#define SYSCON_STARTERCLR_FLEXINT4_CLR_SHIFT (18U) +#define SYSCON_STARTERCLR_FLEXINT4_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_FLEXINT4_CLR_SHIFT)) & SYSCON_STARTERCLR_FLEXINT4_CLR_MASK) +#define SYSCON_STARTERCLR_SEC_GPIO_INT00_CLR_MASK (0x40000U) +#define SYSCON_STARTERCLR_SEC_GPIO_INT00_CLR_SHIFT (18U) +#define SYSCON_STARTERCLR_SEC_GPIO_INT00_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SEC_GPIO_INT00_CLR_SHIFT)) & SYSCON_STARTERCLR_SEC_GPIO_INT00_CLR_MASK) +#define SYSCON_STARTERCLR_FLEXINT5_CLR_MASK (0x80000U) +#define SYSCON_STARTERCLR_FLEXINT5_CLR_SHIFT (19U) +#define SYSCON_STARTERCLR_FLEXINT5_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_FLEXINT5_CLR_SHIFT)) & SYSCON_STARTERCLR_FLEXINT5_CLR_MASK) +#define SYSCON_STARTERCLR_SEC_GPIO_INT01_CLR_MASK (0x80000U) +#define SYSCON_STARTERCLR_SEC_GPIO_INT01_CLR_SHIFT (19U) +#define SYSCON_STARTERCLR_SEC_GPIO_INT01_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SEC_GPIO_INT01_CLR_SHIFT)) & SYSCON_STARTERCLR_SEC_GPIO_INT01_CLR_MASK) +#define SYSCON_STARTERCLR_FLEXINT6_CLR_MASK (0x100000U) +#define SYSCON_STARTERCLR_FLEXINT6_CLR_SHIFT (20U) +#define SYSCON_STARTERCLR_FLEXINT6_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_FLEXINT6_CLR_SHIFT)) & SYSCON_STARTERCLR_FLEXINT6_CLR_MASK) +#define SYSCON_STARTERCLR_PLU_CLR_MASK (0x100000U) +#define SYSCON_STARTERCLR_PLU_CLR_SHIFT (20U) +#define SYSCON_STARTERCLR_PLU_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_PLU_CLR_SHIFT)) & SYSCON_STARTERCLR_PLU_CLR_MASK) +#define SYSCON_STARTERCLR_FLEXINT7_CLR_MASK (0x200000U) +#define SYSCON_STARTERCLR_FLEXINT7_CLR_SHIFT (21U) +#define SYSCON_STARTERCLR_FLEXINT7_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_FLEXINT7_CLR_SHIFT)) & SYSCON_STARTERCLR_FLEXINT7_CLR_MASK) +#define SYSCON_STARTERCLR_SEC_VIO_CLR_MASK (0x200000U) +#define SYSCON_STARTERCLR_SEC_VIO_CLR_SHIFT (21U) +#define SYSCON_STARTERCLR_SEC_VIO_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SEC_VIO_CLR_SHIFT)) & SYSCON_STARTERCLR_SEC_VIO_CLR_MASK) +#define SYSCON_STARTERCLR_ADC0_CLR_MASK (0x400000U) +#define SYSCON_STARTERCLR_ADC0_CLR_SHIFT (22U) +#define SYSCON_STARTERCLR_ADC0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_ADC0_CLR_SHIFT)) & SYSCON_STARTERCLR_ADC0_CLR_MASK) +#define SYSCON_STARTERCLR_SHA_CLR_MASK (0x400000U) +#define SYSCON_STARTERCLR_SHA_CLR_SHIFT (22U) +#define SYSCON_STARTERCLR_SHA_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SHA_CLR_SHIFT)) & SYSCON_STARTERCLR_SHA_CLR_MASK) +#define SYSCON_STARTERCLR_CASER_CLR_MASK (0x800000U) +#define SYSCON_STARTERCLR_CASER_CLR_SHIFT (23U) +#define SYSCON_STARTERCLR_CASER_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_CASER_CLR_SHIFT)) & SYSCON_STARTERCLR_CASER_CLR_MASK) +#define SYSCON_STARTERCLR_ADC0_THCMP_OVR_CLR_MASK (0x1000000U) +#define SYSCON_STARTERCLR_ADC0_THCMP_OVR_CLR_SHIFT (24U) +#define SYSCON_STARTERCLR_ADC0_THCMP_OVR_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_ADC0_THCMP_OVR_CLR_SHIFT)) & SYSCON_STARTERCLR_ADC0_THCMP_OVR_CLR_MASK) +#define SYSCON_STARTERCLR_QDDKEY_CLR_MASK (0x1000000U) +#define SYSCON_STARTERCLR_QDDKEY_CLR_SHIFT (24U) +#define SYSCON_STARTERCLR_QDDKEY_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_QDDKEY_CLR_SHIFT)) & SYSCON_STARTERCLR_QDDKEY_CLR_MASK) +#define SYSCON_STARTERCLR_PQ_CLR_MASK (0x2000000U) +#define SYSCON_STARTERCLR_PQ_CLR_SHIFT (25U) +#define SYSCON_STARTERCLR_PQ_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_PQ_CLR_SHIFT)) & SYSCON_STARTERCLR_PQ_CLR_MASK) +#define SYSCON_STARTERCLR_SDMA1_CLR_MASK (0x4000000U) +#define SYSCON_STARTERCLR_SDMA1_CLR_SHIFT (26U) +#define SYSCON_STARTERCLR_SDMA1_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SDMA1_CLR_SHIFT)) & SYSCON_STARTERCLR_SDMA1_CLR_MASK) +#define SYSCON_STARTERCLR_LSPI_HS_CLR_MASK (0x8000000U) +#define SYSCON_STARTERCLR_LSPI_HS_CLR_SHIFT (27U) +#define SYSCON_STARTERCLR_LSPI_HS_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_LSPI_HS_CLR_SHIFT)) & SYSCON_STARTERCLR_LSPI_HS_CLR_MASK) +#define SYSCON_STARTERCLR_USB0_NEEDCLK_CLR_MASK (0x8000000U) +#define SYSCON_STARTERCLR_USB0_NEEDCLK_CLR_SHIFT (27U) +#define SYSCON_STARTERCLR_USB0_NEEDCLK_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_USB0_NEEDCLK_CLR_SHIFT)) & SYSCON_STARTERCLR_USB0_NEEDCLK_CLR_MASK) +#define SYSCON_STARTERCLR_USB0_CLR_MASK (0x10000000U) +#define SYSCON_STARTERCLR_USB0_CLR_SHIFT (28U) +#define SYSCON_STARTERCLR_USB0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_USB0_CLR_SHIFT)) & SYSCON_STARTERCLR_USB0_CLR_MASK) +#define SYSCON_STARTERCLR_RTC_LITE0_CLR_MASK (0x20000000U) +#define SYSCON_STARTERCLR_RTC_LITE0_CLR_SHIFT (29U) +#define SYSCON_STARTERCLR_RTC_LITE0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_RTC_LITE0_CLR_SHIFT)) & SYSCON_STARTERCLR_RTC_LITE0_CLR_MASK) +#define SYSCON_STARTERCLR_EZH_ARCH_B0_CLR_MASK (0x40000000U) +#define SYSCON_STARTERCLR_EZH_ARCH_B0_CLR_SHIFT (30U) +#define SYSCON_STARTERCLR_EZH_ARCH_B0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_EZH_ARCH_B0_CLR_SHIFT)) & SYSCON_STARTERCLR_EZH_ARCH_B0_CLR_MASK) +#define SYSCON_STARTERCLR_WAKEUPPADS_CLR_MASK (0x80000000U) +#define SYSCON_STARTERCLR_WAKEUPPADS_CLR_SHIFT (31U) +#define SYSCON_STARTERCLR_WAKEUPPADS_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_WAKEUPPADS_CLR_SHIFT)) & SYSCON_STARTERCLR_WAKEUPPADS_CLR_MASK) +#define SYSCON_STARTERCLR_WAKEUP_MAILBOX0_CLR_MASK (0x80000000U) +#define SYSCON_STARTERCLR_WAKEUP_MAILBOX0_CLR_SHIFT (31U) +#define SYSCON_STARTERCLR_WAKEUP_MAILBOX0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_WAKEUP_MAILBOX0_CLR_SHIFT)) & SYSCON_STARTERCLR_WAKEUP_MAILBOX0_CLR_MASK) +/*! @} */ + +/* The count of SYSCON_STARTERCLR */ +#define SYSCON_STARTERCLR_COUNT (2U) + +/*! @name HARDWARESLEEP - Hardware Sleep control */ +/*! @{ */ +#define SYSCON_HARDWARESLEEP_FORCED_MASK (0x1U) +#define SYSCON_HARDWARESLEEP_FORCED_SHIFT (0U) +#define SYSCON_HARDWARESLEEP_FORCED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HARDWARESLEEP_FORCED_SHIFT)) & SYSCON_HARDWARESLEEP_FORCED_MASK) +#define SYSCON_HARDWARESLEEP_PERIPHERALS_MASK (0x2U) +#define SYSCON_HARDWARESLEEP_PERIPHERALS_SHIFT (1U) +#define SYSCON_HARDWARESLEEP_PERIPHERALS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HARDWARESLEEP_PERIPHERALS_SHIFT)) & SYSCON_HARDWARESLEEP_PERIPHERALS_MASK) +#define SYSCON_HARDWARESLEEP_SDMA0_MASK (0x8U) +#define SYSCON_HARDWARESLEEP_SDMA0_SHIFT (3U) +#define SYSCON_HARDWARESLEEP_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HARDWARESLEEP_SDMA0_SHIFT)) & SYSCON_HARDWARESLEEP_SDMA0_MASK) +#define SYSCON_HARDWARESLEEP_SDMA1_MASK (0x20U) +#define SYSCON_HARDWARESLEEP_SDMA1_SHIFT (5U) +#define SYSCON_HARDWARESLEEP_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HARDWARESLEEP_SDMA1_SHIFT)) & SYSCON_HARDWARESLEEP_SDMA1_MASK) +/*! @} */ + +/*! @name CPUCTRL - CPU Control for multiple processors */ +/*! @{ */ +#define SYSCON_CPUCTRL_CPU1CLKEN_MASK (0x8U) +#define SYSCON_CPUCTRL_CPU1CLKEN_SHIFT (3U) +/*! CPU1CLKEN - CPU1 clock enable. + * 0b1..The CPU1 clock is enabled. + * 0b0..The CPU1 clock is not enabled. + */ +#define SYSCON_CPUCTRL_CPU1CLKEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCTRL_CPU1CLKEN_SHIFT)) & SYSCON_CPUCTRL_CPU1CLKEN_MASK) +#define SYSCON_CPUCTRL_CPU1RSTEN_MASK (0x20U) +#define SYSCON_CPUCTRL_CPU1RSTEN_SHIFT (5U) +/*! CPU1RSTEN - CPU1 reset. + * 0b1..The CPU1 is being reset. + * 0b0..The CPU1 is not being reset. + */ +#define SYSCON_CPUCTRL_CPU1RSTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCTRL_CPU1RSTEN_SHIFT)) & SYSCON_CPUCTRL_CPU1RSTEN_MASK) +/*! @} */ + +/*! @name CPBOOT - Coprocessor Boot Address */ +/*! @{ */ +#define SYSCON_CPBOOT_CPBOOT_MASK (0xFFFFFFFFU) +#define SYSCON_CPBOOT_CPBOOT_SHIFT (0U) +#define SYSCON_CPBOOT_CPBOOT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPBOOT_CPBOOT_SHIFT)) & SYSCON_CPBOOT_CPBOOT_MASK) +/*! @} */ + +/*! @name CPSTACK - Coprocessor Stack Address */ +/*! @{ */ +#define SYSCON_CPSTACK_CPSTACK_MASK (0xFFFFFFFFU) +#define SYSCON_CPSTACK_CPSTACK_SHIFT (0U) +#define SYSCON_CPSTACK_CPSTACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTACK_CPSTACK_SHIFT)) & SYSCON_CPSTACK_CPSTACK_MASK) +/*! @} */ + +/*! @name CPSTAT - CPU Status */ +/*! @{ */ +#define SYSCON_CPSTAT_CPU0SLEEPING_MASK (0x1U) +#define SYSCON_CPSTAT_CPU0SLEEPING_SHIFT (0U) +/*! CPU0SLEEPING - The CPU0 sleeping state. + * 0b1..the CPU is sleeping. + * 0b0..the CPU is not sleeping. + */ +#define SYSCON_CPSTAT_CPU0SLEEPING(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CPU0SLEEPING_SHIFT)) & SYSCON_CPSTAT_CPU0SLEEPING_MASK) +#define SYSCON_CPSTAT_CPU1SLEEPING_MASK (0x2U) +#define SYSCON_CPSTAT_CPU1SLEEPING_SHIFT (1U) +/*! CPU1SLEEPING - The CPU1 sleeping state. + * 0b1..the CPU is sleeping. + * 0b0..the CPU is not sleeping. + */ +#define SYSCON_CPSTAT_CPU1SLEEPING(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CPU1SLEEPING_SHIFT)) & SYSCON_CPSTAT_CPU1SLEEPING_MASK) +#define SYSCON_CPSTAT_CPU0LOCKUP_MASK (0x4U) +#define SYSCON_CPSTAT_CPU0LOCKUP_SHIFT (2U) +/*! CPU0LOCKUP - The CPU0 lockup state. + * 0b1..the CPU is in lockup. + * 0b0..the CPU is not in lockup. + */ +#define SYSCON_CPSTAT_CPU0LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CPU0LOCKUP_SHIFT)) & SYSCON_CPSTAT_CPU0LOCKUP_MASK) +#define SYSCON_CPSTAT_CPU1LOCKUP_MASK (0x8U) +#define SYSCON_CPSTAT_CPU1LOCKUP_SHIFT (3U) +/*! CPU1LOCKUP - The CPU1 lockup state. + * 0b1..the CPU is in lockup. + * 0b0..the CPU is not in lockup. + */ +#define SYSCON_CPSTAT_CPU1LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CPU1LOCKUP_SHIFT)) & SYSCON_CPSTAT_CPU1LOCKUP_MASK) +/*! @} */ + +/*! @name DICE_REG0 - Composite Device Identifier */ +/*! @{ */ +#define SYSCON_DICE_REG0_DICE_REG0_MASK (0xFFFFFFFFU) +#define SYSCON_DICE_REG0_DICE_REG0_SHIFT (0U) +#define SYSCON_DICE_REG0_DICE_REG0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DICE_REG0_DICE_REG0_SHIFT)) & SYSCON_DICE_REG0_DICE_REG0_MASK) +/*! @} */ + +/*! @name DICE_REG1 - Composite Device Identifier */ +/*! @{ */ +#define SYSCON_DICE_REG1_DICE_REG1_MASK (0xFFFFFFFFU) +#define SYSCON_DICE_REG1_DICE_REG1_SHIFT (0U) +#define SYSCON_DICE_REG1_DICE_REG1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DICE_REG1_DICE_REG1_SHIFT)) & SYSCON_DICE_REG1_DICE_REG1_MASK) +/*! @} */ + +/*! @name DICE_REG2 - Composite Device Identifier */ +/*! @{ */ +#define SYSCON_DICE_REG2_DICE_REG2_MASK (0xFFFFFFFFU) +#define SYSCON_DICE_REG2_DICE_REG2_SHIFT (0U) +#define SYSCON_DICE_REG2_DICE_REG2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DICE_REG2_DICE_REG2_SHIFT)) & SYSCON_DICE_REG2_DICE_REG2_MASK) +/*! @} */ + +/*! @name DICE_REG3 - Composite Device Identifier */ +/*! @{ */ +#define SYSCON_DICE_REG3_DICE_REG3_MASK (0xFFFFFFFFU) +#define SYSCON_DICE_REG3_DICE_REG3_SHIFT (0U) +#define SYSCON_DICE_REG3_DICE_REG3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DICE_REG3_DICE_REG3_SHIFT)) & SYSCON_DICE_REG3_DICE_REG3_MASK) +/*! @} */ + +/*! @name DICE_REG4 - Composite Device Identifier */ +/*! @{ */ +#define SYSCON_DICE_REG4_DICE_REG4_MASK (0xFFFFFFFFU) +#define SYSCON_DICE_REG4_DICE_REG4_SHIFT (0U) +#define SYSCON_DICE_REG4_DICE_REG4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DICE_REG4_DICE_REG4_SHIFT)) & SYSCON_DICE_REG4_DICE_REG4_MASK) +/*! @} */ + +/*! @name DICE_REG5 - Composite Device Identifier */ +/*! @{ */ +#define SYSCON_DICE_REG5_DICE_REG5_MASK (0xFFFFFFFFU) +#define SYSCON_DICE_REG5_DICE_REG5_SHIFT (0U) +#define SYSCON_DICE_REG5_DICE_REG5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DICE_REG5_DICE_REG5_SHIFT)) & SYSCON_DICE_REG5_DICE_REG5_MASK) +/*! @} */ + +/*! @name DICE_REG6 - Composite Device Identifier */ +/*! @{ */ +#define SYSCON_DICE_REG6_DICE_REG6_MASK (0xFFFFFFFFU) +#define SYSCON_DICE_REG6_DICE_REG6_SHIFT (0U) +#define SYSCON_DICE_REG6_DICE_REG6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DICE_REG6_DICE_REG6_SHIFT)) & SYSCON_DICE_REG6_DICE_REG6_MASK) +/*! @} */ + +/*! @name DICE_REG7 - Composite Device Identifier */ +/*! @{ */ +#define SYSCON_DICE_REG7_DICE_REG7_MASK (0xFFFFFFFFU) +#define SYSCON_DICE_REG7_DICE_REG7_SHIFT (0U) +#define SYSCON_DICE_REG7_DICE_REG7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DICE_REG7_DICE_REG7_SHIFT)) & SYSCON_DICE_REG7_DICE_REG7_MASK) +/*! @} */ + +/*! @name CLOCK_CTRL - Various system clock controls : Flash clock (48 MHz) control, clocks to Frequency Measures */ +/*! @{ */ +#define SYSCON_CLOCK_CTRL_FLASH48MHZ_ENA_MASK (0x1U) +#define SYSCON_CLOCK_CTRL_FLASH48MHZ_ENA_SHIFT (0U) +/*! FLASH48MHZ_ENA - Enable Flash 48 MHz clock. + * 0b1..The clock is enabled. + * 0b0..The clock is not enabled. + */ +#define SYSCON_CLOCK_CTRL_FLASH48MHZ_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FLASH48MHZ_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FLASH48MHZ_ENA_MASK) +#define SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_MASK (0x2U) +#define SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_SHIFT (1U) +/*! XTAL32MHZ_FREQM_ENA - Enable XTAL32MHz clock for Frequency Measure module. + * 0b1..The clock is enabled. + * 0b0..The clock is not enabled. + */ +#define SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_MASK) +#define SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_MASK (0x4U) +#define SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_SHIFT (2U) +/*! FRO1MHZ_UTICK_ENA - Enable FRO 1MHz clock for Frequency Measure module and for UTICK. + * 0b1..The clock is enabled. + * 0b0..The clock is not enabled. + */ +#define SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_MASK) +#define SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_MASK (0x8U) +#define SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_SHIFT (3U) +/*! FRO12MHZ_FREQM_ENA - Enable FRO 12MHz clock for Frequency Measure module. + * 0b1..The clock is enabled. + * 0b0..The clock is not enabled. + */ +#define SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_MASK) +#define SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_MASK (0x10U) +#define SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_SHIFT (4U) +/*! FRO_HF_FREQM_ENA - Enable FRO 96MHz clock for Frequency Measure module. + * 0b1..The clock is enabled. + * 0b0..The clock is not enabled. + */ +#define SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_MASK) +#define SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK (0x20U) +#define SYSCON_CLOCK_CTRL_CLKIN_ENA_SHIFT (5U) +/*! CLKIN_ENA - Enable clock_in clock for clock module. + * 0b1..The clock is enabled. + * 0b0..The clock is not enabled. + */ +#define SYSCON_CLOCK_CTRL_CLKIN_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_CLKIN_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK) +#define SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK (0x40U) +#define SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_SHIFT (6U) +/*! FRO1MHZ_CLK_ENA - Enable FRO 1MHz clock for clock muxing in clock gen. + * 0b1..The clock is enabled. + * 0b0..The clock is not enabled. + */ +#define SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK) +#define SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_MASK (0x80U) +#define SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_SHIFT (7U) +/*! ANA_FRO12M_CLK_ENA - Enable FRO 12MHz clock for analog control of the FRO 192MHz. + * 0b1..The clock is enabled. + * 0b0..The clock is not enabled. + */ +#define SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_MASK) +#define SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_MASK (0x100U) +#define SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_SHIFT (8U) +/*! XO_CAL_CLK_ENA - Enable clock for cristal oscilator calibration. + * 0b1..The clock is enabled. + * 0b0..The clock is not enabled. + */ +#define SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_MASK) +#define SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA_MASK (0x200U) +#define SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA_SHIFT (9U) +/*! PLU_DEGLITCH_CLK_ENA - Enable clocks FRO_1MHz and FRO_12MHz for PLU deglitching. + * 0b1..The clock is enabled. + * 0b0..The clock is not enabled. + */ +#define SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA_MASK) +/*! @} */ + +/*! @name COMP_INT_CTRL - Comparator Interrupt control */ +/*! @{ */ +#define SYSCON_COMP_INT_CTRL_INT_ENABLE_MASK (0x1U) +#define SYSCON_COMP_INT_CTRL_INT_ENABLE_SHIFT (0U) +/*! INT_ENABLE - Analog Comparator interrupt enable control:. + * 0b1..interrupt enable. + * 0b0..interrupt disable. + */ +#define SYSCON_COMP_INT_CTRL_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_ENABLE_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_ENABLE_MASK) +#define SYSCON_COMP_INT_CTRL_INT_CLEAR_MASK (0x2U) +#define SYSCON_COMP_INT_CTRL_INT_CLEAR_SHIFT (1U) +/*! INT_CLEAR - Analog Comparator interrupt clear. + * 0b0..No effect. + * 0b1..Clear the interrupt. Self-cleared bit. + */ +#define SYSCON_COMP_INT_CTRL_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_CLEAR_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_CLEAR_MASK) +#define SYSCON_COMP_INT_CTRL_INT_CTRL_MASK (0x1CU) +#define SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT (2U) +/*! INT_CTRL - Comparator interrupt type selector:. + * 0b000..The analog comparator interrupt edge sensitive is disabled. + * 0b010..analog comparator interrupt is rising edge sensitive. + * 0b100..analog comparator interrupt is falling edge sensitive. + * 0b110..analog comparator interrupt is rising and falling edge sensitive. + * 0b001..The analog comparator interrupt level sensitive is disabled. + * 0b011..Analog Comparator interrupt is high level sensitive. + * 0b101..Analog Comparator interrupt is low level sensitive. + * 0b111..The analog comparator interrupt level sensitive is disabled. + */ +#define SYSCON_COMP_INT_CTRL_INT_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_CTRL_MASK) +#define SYSCON_COMP_INT_CTRL_INT_SOURCE_MASK (0x20U) +#define SYSCON_COMP_INT_CTRL_INT_SOURCE_SHIFT (5U) +/*! INT_SOURCE - Select which Analog comparator output (filtered our un-filtered) is used for interrupt detection. + * 0b0..Select Analog Comparator filtered output as input for interrupt detection. + * 0b1..Select Analog Comparator raw output (unfiltered) as input for interrupt detection. Must be used when + * Analog comparator is used as wake up source in Power down mode. + */ +#define SYSCON_COMP_INT_CTRL_INT_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_SOURCE_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_SOURCE_MASK) +/*! @} */ + +/*! @name COMP_INT_STATUS - Comparator Interrupt status */ +/*! @{ */ +#define SYSCON_COMP_INT_STATUS_STATUS_MASK (0x1U) +#define SYSCON_COMP_INT_STATUS_STATUS_SHIFT (0U) +/*! STATUS - Interrupt status BEFORE Interrupt Enable. + * 0b0..no interrupt pending. + * 0b1..interrupt pending. + */ +#define SYSCON_COMP_INT_STATUS_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_STATUS_STATUS_SHIFT)) & SYSCON_COMP_INT_STATUS_STATUS_MASK) +#define SYSCON_COMP_INT_STATUS_INT_STATUS_MASK (0x2U) +#define SYSCON_COMP_INT_STATUS_INT_STATUS_SHIFT (1U) +/*! INT_STATUS - Interrupt status AFTER Interrupt Enable. + * 0b0..no interrupt pending. + * 0b1..interrupt pending. + */ +#define SYSCON_COMP_INT_STATUS_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_STATUS_INT_STATUS_SHIFT)) & SYSCON_COMP_INT_STATUS_INT_STATUS_MASK) +#define SYSCON_COMP_INT_STATUS_VAL_MASK (0x4U) +#define SYSCON_COMP_INT_STATUS_VAL_SHIFT (2U) +/*! VAL - comparator analog output. + * 0b1..P+ is greater than P-. + * 0b0..P+ is smaller than P-. + */ +#define SYSCON_COMP_INT_STATUS_VAL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_STATUS_VAL_SHIFT)) & SYSCON_COMP_INT_STATUS_VAL_MASK) +/*! @} */ + +/*! @name AUTOCLKGATEOVERRIDE - Control automatic clock gating */ +/*! @{ */ +#define SYSCON_AUTOCLKGATEOVERRIDE_ROM_MASK (0x1U) +#define SYSCON_AUTOCLKGATEOVERRIDE_ROM_SHIFT (0U) +/*! ROM - Control automatic clock gating of ROM controller. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_ROM_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_ROM_MASK) +#define SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL_MASK (0x2U) +#define SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL_SHIFT (1U) +/*! RAMX_CTRL - Control automatic clock gating of RAMX controller. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL_MASK) +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL_MASK (0x4U) +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL_SHIFT (2U) +/*! RAM0_CTRL - Control automatic clock gating of RAM0 controller. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL_MASK) +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL_MASK (0x8U) +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL_SHIFT (3U) +/*! RAM1_CTRL - Control automatic clock gating of RAM1 controller. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL_MASK) +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL_MASK (0x10U) +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL_SHIFT (4U) +/*! RAM2_CTRL - Control automatic clock gating of RAM2 controller. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL_MASK) +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM3_CTRL_MASK (0x20U) +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM3_CTRL_SHIFT (5U) +/*! RAM3_CTRL - Control automatic clock gating of RAM3 controller. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM3_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM3_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM3_CTRL_MASK) +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM4_CTRL_MASK (0x40U) +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM4_CTRL_SHIFT (6U) +/*! RAM4_CTRL - Control automatic clock gating of RAM4 controller. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM4_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM4_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM4_CTRL_MASK) +#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_MASK (0x80U) +#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_SHIFT (7U) +/*! SYNC0_APB - Control automatic clock gating of synchronous bridge controller 0. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_MASK) +#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_MASK (0x100U) +#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_SHIFT (8U) +/*! SYNC1_APB - Control automatic clock gating of synchronous bridge controller 1. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_MASK) +#define SYSCON_AUTOCLKGATEOVERRIDE_FLASH_MASK (0x200U) +#define SYSCON_AUTOCLKGATEOVERRIDE_FLASH_SHIFT (9U) +/*! FLASH - Control automatic clock gating of FLASH controller. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_FLASH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_FLASH_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_FLASH_MASK) +#define SYSCON_AUTOCLKGATEOVERRIDE_FMC_MASK (0x400U) +#define SYSCON_AUTOCLKGATEOVERRIDE_FMC_SHIFT (10U) +/*! FMC - Control automatic clock gating of FMC controller. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_FMC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_FMC_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_FMC_MASK) +#define SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_MASK (0x800U) +#define SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_SHIFT (11U) +/*! CRCGEN - Control automatic clock gating of CRCGEN controller. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_MASK) +#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_MASK (0x1000U) +#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_SHIFT (12U) +/*! SDMA0 - Control automatic clock gating of DMA0 controller. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_MASK) +#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_MASK (0x2000U) +#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_SHIFT (13U) +/*! SDMA1 - Control automatic clock gating of DMA1 controller. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_MASK) +#define SYSCON_AUTOCLKGATEOVERRIDE_USB_MASK (0x4000U) +#define SYSCON_AUTOCLKGATEOVERRIDE_USB_SHIFT (14U) +/*! USB - Control automatic clock gating of USB controller. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_USB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_USB_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_USB_MASK) +#define SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_MASK (0x8000U) +#define SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_SHIFT (15U) +/*! SYSCON - Control automatic clock gating of synchronous system controller registers bank. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_SYSCON(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_MASK) +#define SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_MASK (0xFFFF0000U) +#define SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_SHIFT (16U) +/*! ENABLEUPDATE - The value 0xC0DE must be written for AUTOCLKGATEOVERRIDE registers fields updates to have effect. + * 0b1100000011011110..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0000000000000000..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_MASK) +/*! @} */ + +/*! @name GPIOPSYNC - Enable bypass of the first stage of synchonization inside GPIO_INT module */ +/*! @{ */ +#define SYSCON_GPIOPSYNC_PSYNC_MASK (0x1U) +#define SYSCON_GPIOPSYNC_PSYNC_SHIFT (0U) +/*! PSYNC - Enable bypass of the first stage of synchonization inside GPIO_INT module. + * 0b1..bypass of the first stage of synchonization inside GPIO_INT module. + * 0b0..use the first stage of synchonization inside GPIO_INT module. + */ +#define SYSCON_GPIOPSYNC_PSYNC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_GPIOPSYNC_PSYNC_SHIFT)) & SYSCON_GPIOPSYNC_PSYNC_MASK) +/*! @} */ + +/*! @name DEBUG_LOCK_EN - Control write access to security registers -- FOR INTERNAl USE ONLY */ +/*! @{ */ +#define SYSCON_DEBUG_LOCK_EN_LOCK_ALL_MASK (0xFU) +#define SYSCON_DEBUG_LOCK_EN_LOCK_ALL_SHIFT (0U) +/*! LOCK_ALL - Control write access to CODESECURITYPROTTEST, CODESECURITYPROTCPU0, + * CODESECURITYPROTCPU1, CM33_DEBUG_FEATURES, MCM33_DEBUG_FEATURES and DBG_AUTH_SCRATCH registers. + * 0b1010..1010: Enable write access to all 6 registers. + * 0b0000..Any other value than b1010: disable write access to all 6 registers. + */ +#define SYSCON_DEBUG_LOCK_EN_LOCK_ALL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_LOCK_EN_LOCK_ALL_SHIFT)) & SYSCON_DEBUG_LOCK_EN_LOCK_ALL_MASK) +/*! @} */ + +/*! @name DEBUG_FEATURES - Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control -- FOR INTERNAl USE ONLY */ +/*! @{ */ +#define SYSCON_DEBUG_FEATURES_CM33_DBGEN_MASK (0x3U) +#define SYSCON_DEBUG_FEATURES_CM33_DBGEN_SHIFT (0U) +/*! CM33_DBGEN - CM33 (CPU0) Invasive debug control:. + * 0b10..10: Invasive debug is enabled. + * 0b01..Any other value than b10: invasive debug is disable. + */ +#define SYSCON_DEBUG_FEATURES_CM33_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CM33_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CM33_DBGEN_MASK) +#define SYSCON_DEBUG_FEATURES_CM33_NIDEN_MASK (0xCU) +#define SYSCON_DEBUG_FEATURES_CM33_NIDEN_SHIFT (2U) +/*! CM33_NIDEN - CM33 (CPU0) Non Invasive debug control:. + * 0b10..10: Invasive debug is enabled. + * 0b01..Any other value than b10: invasive debug is disable. + */ +#define SYSCON_DEBUG_FEATURES_CM33_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CM33_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CM33_NIDEN_MASK) +#define SYSCON_DEBUG_FEATURES_CM33_SPIDEN_MASK (0x30U) +#define SYSCON_DEBUG_FEATURES_CM33_SPIDEN_SHIFT (4U) +/*! CM33_SPIDEN - CM33 (CPU0) Secure Invasive debug control:. + * 0b10..10: Invasive debug is enabled. + * 0b01..Any other value than b10: invasive debug is disable. + */ +#define SYSCON_DEBUG_FEATURES_CM33_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CM33_SPIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CM33_SPIDEN_MASK) +#define SYSCON_DEBUG_FEATURES_CM33_SPNIDEN_MASK (0xC0U) +#define SYSCON_DEBUG_FEATURES_CM33_SPNIDEN_SHIFT (6U) +/*! CM33_SPNIDEN - CM33 (CPU0) Secure Non Invasive debug control:. + * 0b10..10: Invasive debug is enabled. + * 0b01..Any other value than b10: invasive debug is disable. + */ +#define SYSCON_DEBUG_FEATURES_CM33_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CM33_SPNIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CM33_SPNIDEN_MASK) +#define SYSCON_DEBUG_FEATURES_MCM33_DBGEN_MASK (0x300U) +#define SYSCON_DEBUG_FEATURES_MCM33_DBGEN_SHIFT (8U) +/*! MCM33_DBGEN - Micro-CM33 (CPU1) Invasive debug control:. + * 0b10..10: Invasive debug is enabled. + * 0b01..Any other value than b10: invasive debug is disable. + */ +#define SYSCON_DEBUG_FEATURES_MCM33_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_MCM33_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_MCM33_DBGEN_MASK) +#define SYSCON_DEBUG_FEATURES_MCM33_NIDEN_MASK (0xC00U) +#define SYSCON_DEBUG_FEATURES_MCM33_NIDEN_SHIFT (10U) +/*! MCM33_NIDEN - Micro-CM33 (CPU1) Non Invasive debug control:. + * 0b10..10: Invasive debug is enabled. + * 0b01..Any other value than b10: invasive debug is disable. + */ +#define SYSCON_DEBUG_FEATURES_MCM33_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_MCM33_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_MCM33_NIDEN_MASK) +/*! @} */ + +/*! @name DEBUG_FEATURES_DP - Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control DUPLICATE register -- FOR INTERNAl USE ONLY */ +/*! @{ */ +#define SYSCON_DEBUG_FEATURES_DP_CM33_DBGEN_MASK (0x3U) +#define SYSCON_DEBUG_FEATURES_DP_CM33_DBGEN_SHIFT (0U) +/*! CM33_DBGEN - CM33 (CPU0) Invasive debug control:. + * 0b10..10: Invasive debug is enabled. + * 0b01..Any other value than b10: invasive debug is disable. + */ +#define SYSCON_DEBUG_FEATURES_DP_CM33_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CM33_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CM33_DBGEN_MASK) +#define SYSCON_DEBUG_FEATURES_DP_CM33_NIDEN_MASK (0xCU) +#define SYSCON_DEBUG_FEATURES_DP_CM33_NIDEN_SHIFT (2U) +/*! CM33_NIDEN - CM33 (CPU0) Non Invasive debug control:. + * 0b10..10: Invasive debug is enabled. + * 0b01..Any other value than b10: invasive debug is disable. + */ +#define SYSCON_DEBUG_FEATURES_DP_CM33_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CM33_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CM33_NIDEN_MASK) +#define SYSCON_DEBUG_FEATURES_DP_CM33_SPIDEN_MASK (0x30U) +#define SYSCON_DEBUG_FEATURES_DP_CM33_SPIDEN_SHIFT (4U) +/*! CM33_SPIDEN - CM33 (CPU0) Secure Invasive debug control:. + * 0b10..10: Invasive debug is enabled. + * 0b01..Any other value than b10: invasive debug is disable. + */ +#define SYSCON_DEBUG_FEATURES_DP_CM33_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CM33_SPIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CM33_SPIDEN_MASK) +#define SYSCON_DEBUG_FEATURES_DP_CM33_SPNIDEN_MASK (0xC0U) +#define SYSCON_DEBUG_FEATURES_DP_CM33_SPNIDEN_SHIFT (6U) +/*! CM33_SPNIDEN - CM33 (CPU0) Secure Non Invasive debug control:. + * 0b10..10: Invasive debug is enabled. + * 0b01..Any other value than b10: invasive debug is disable. + */ +#define SYSCON_DEBUG_FEATURES_DP_CM33_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CM33_SPNIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CM33_SPNIDEN_MASK) +#define SYSCON_DEBUG_FEATURES_DP_MCM33_DBGEN_MASK (0x300U) +#define SYSCON_DEBUG_FEATURES_DP_MCM33_DBGEN_SHIFT (8U) +/*! MCM33_DBGEN - Micro-CM33 (CPU1) Invasive debug control:. + * 0b10..10: Invasive debug is enabled. + * 0b01..Any other value than b10: invasive debug is disable. + */ +#define SYSCON_DEBUG_FEATURES_DP_MCM33_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_MCM33_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_MCM33_DBGEN_MASK) +#define SYSCON_DEBUG_FEATURES_DP_MCM33_NIDEN_MASK (0xC00U) +#define SYSCON_DEBUG_FEATURES_DP_MCM33_NIDEN_SHIFT (10U) +/*! MCM33_NIDEN - Micro-CM33 (CPU1) Non Invasive debug control:. + * 0b10..10: Invasive debug is enabled. + * 0b01..Any other value than b10: invasive debug is disable. + */ +#define SYSCON_DEBUG_FEATURES_DP_MCM33_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_MCM33_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_MCM33_NIDEN_MASK) +/*! @} */ + +/*! @name CODESECURITYPROTTEST - Security code to allow test (Design for Testability) access -- FOR INTERNAl USE ONLY */ +/*! @{ */ +#define SYSCON_CODESECURITYPROTTEST_SEC_CODE_MASK (0xFFFFFFFFU) +#define SYSCON_CODESECURITYPROTTEST_SEC_CODE_SHIFT (0U) +/*! SEC_CODE - Security code to allow test access : 0x12345678. + * 0b00010010001101000101011001111000..Security code to allow test access. + * 0b00000000000000000000000000000000..test access is not allowed. + */ +#define SYSCON_CODESECURITYPROTTEST_SEC_CODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CODESECURITYPROTTEST_SEC_CODE_SHIFT)) & SYSCON_CODESECURITYPROTTEST_SEC_CODE_MASK) +/*! @} */ + +/*! @name CODESECURITYPROTCPU0 - Security code to allow CPU0 (CM33) Debug Access Port (DAP) -- FOR INTERNAl USE ONLY */ +/*! @{ */ +#define SYSCON_CODESECURITYPROTCPU0_SEC_CODE_MASK (0xFFFFFFFFU) +#define SYSCON_CODESECURITYPROTCPU0_SEC_CODE_SHIFT (0U) +/*! SEC_CODE - Security code to allow CPU0 DAP: 0x12345678. + * 0b00010010001101000101011001111000..Security code to allow CPU0 DAP. + * 0b00000000000000000000000000000000..CPU0 DAP is not allowed. + */ +#define SYSCON_CODESECURITYPROTCPU0_SEC_CODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CODESECURITYPROTCPU0_SEC_CODE_SHIFT)) & SYSCON_CODESECURITYPROTCPU0_SEC_CODE_MASK) +/*! @} */ + +/*! @name CODESECURITYPROTCPU1 - Security code to allow CPU1 (Micro CM33) Debug Access Port (DAP) -- FOR INTERNAl USE ONLY */ +/*! @{ */ +#define SYSCON_CODESECURITYPROTCPU1_SEC_CODE_MASK (0xFFFFFFFFU) +#define SYSCON_CODESECURITYPROTCPU1_SEC_CODE_SHIFT (0U) +/*! SEC_CODE - Security code to allow CPU1 DAP: 0x12345678. + * 0b00010010001101000101011001111000..Security code to allow CPU1 DAP. + * 0b00000000000000000000000000000000..CPU1 DAP is not allowed. + */ +#define SYSCON_CODESECURITYPROTCPU1_SEC_CODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CODESECURITYPROTCPU1_SEC_CODE_SHIFT)) & SYSCON_CODESECURITYPROTCPU1_SEC_CODE_MASK) +/*! @} */ + +/*! @name KEY_BLOCK - block quiddikey/PUF all index. -- FOR INTERNAL USE ONLY */ +/*! @{ */ +#define SYSCON_KEY_BLOCK_KEY_BLOCK_MASK (0xFFFFFFFFU) +#define SYSCON_KEY_BLOCK_KEY_BLOCK_SHIFT (0U) +#define SYSCON_KEY_BLOCK_KEY_BLOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_KEY_BLOCK_KEY_BLOCK_SHIFT)) & SYSCON_KEY_BLOCK_KEY_BLOCK_MASK) +/*! @} */ + +/*! @name DEBUG_AUTH_SCRATCH - Debug authentication scratch registers -- FOR INTERNAL USE ONLY */ +/*! @{ */ +#define SYSCON_DEBUG_AUTH_SCRATCH_SCRATCH_MASK (0xFFFFFFFFU) +#define SYSCON_DEBUG_AUTH_SCRATCH_SCRATCH_SHIFT (0U) +#define SYSCON_DEBUG_AUTH_SCRATCH_SCRATCH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_AUTH_SCRATCH_SCRATCH_SHIFT)) & SYSCON_DEBUG_AUTH_SCRATCH_SCRATCH_MASK) +/*! @} */ + +/*! @name CPUCFG - CPUs configuration register */ +/*! @{ */ +#define SYSCON_CPUCFG_CPU1ENABLE_MASK (0x4U) +#define SYSCON_CPUCFG_CPU1ENABLE_SHIFT (2U) +/*! CPU1ENABLE - Enable CPU1. + * 0b0..CPU1 is disable (Processor in reset). + * 0b1..CPU1 is enable. + */ +#define SYSCON_CPUCFG_CPU1ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCFG_CPU1ENABLE_SHIFT)) & SYSCON_CPUCFG_CPU1ENABLE_MASK) +/*! @} */ + +/*! @name PERIPHENCFG - peripheral enable configuration -- FOR INTERNAL USE ONLY */ +/*! @{ */ +#define SYSCON_PERIPHENCFG_SCTEN_MASK (0x1U) +#define SYSCON_PERIPHENCFG_SCTEN_SHIFT (0U) +/*! SCTEN - SCT enable. + * 0b1..peripheral is enable. + * 0b0..peripheral is disable. + */ +#define SYSCON_PERIPHENCFG_SCTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PERIPHENCFG_SCTEN_SHIFT)) & SYSCON_PERIPHENCFG_SCTEN_MASK) +#define SYSCON_PERIPHENCFG_ADCEN_MASK (0x2U) +#define SYSCON_PERIPHENCFG_ADCEN_SHIFT (1U) +/*! ADCEN - ADC enable. + * 0b1..peripheral is enable. + * 0b0..peripheral is disable. + */ +#define SYSCON_PERIPHENCFG_ADCEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PERIPHENCFG_ADCEN_SHIFT)) & SYSCON_PERIPHENCFG_ADCEN_MASK) +#define SYSCON_PERIPHENCFG_USB0EN_MASK (0x4U) +#define SYSCON_PERIPHENCFG_USB0EN_SHIFT (2U) +/*! USB0EN - USB0 enable. + * 0b1..peripheral is enable. + * 0b0..peripheral is disable. + */ +#define SYSCON_PERIPHENCFG_USB0EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PERIPHENCFG_USB0EN_SHIFT)) & SYSCON_PERIPHENCFG_USB0EN_MASK) +#define SYSCON_PERIPHENCFG_PUFFEN_MASK (0x40U) +#define SYSCON_PERIPHENCFG_PUFFEN_SHIFT (6U) +/*! PUFFEN - Puff enable. + * 0b1..peripheral is enable. + * 0b0..peripheral is disable. + */ +#define SYSCON_PERIPHENCFG_PUFFEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PERIPHENCFG_PUFFEN_SHIFT)) & SYSCON_PERIPHENCFG_PUFFEN_MASK) +#define SYSCON_PERIPHENCFG_USB1EN_MASK (0x400U) +#define SYSCON_PERIPHENCFG_USB1EN_SHIFT (10U) +/*! USB1EN - USB1 enable. + * 0b1..peripheral is enable. + * 0b0..peripheral is disable. + */ +#define SYSCON_PERIPHENCFG_USB1EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PERIPHENCFG_USB1EN_SHIFT)) & SYSCON_PERIPHENCFG_USB1EN_MASK) +#define SYSCON_PERIPHENCFG_SDIOEN_MASK (0x800U) +#define SYSCON_PERIPHENCFG_SDIOEN_SHIFT (11U) +/*! SDIOEN - SDIO enable. + * 0b1..peripheral is enable. + * 0b0..peripheral is disable. + */ +#define SYSCON_PERIPHENCFG_SDIOEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PERIPHENCFG_SDIOEN_SHIFT)) & SYSCON_PERIPHENCFG_SDIOEN_MASK) +#define SYSCON_PERIPHENCFG_HASHEN_MASK (0x1000U) +#define SYSCON_PERIPHENCFG_HASHEN_SHIFT (12U) +/*! HASHEN - HASH enable. + * 0b1..peripheral is enable. + * 0b0..peripheral is disable. + */ +#define SYSCON_PERIPHENCFG_HASHEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PERIPHENCFG_HASHEN_SHIFT)) & SYSCON_PERIPHENCFG_HASHEN_MASK) +#define SYSCON_PERIPHENCFG_PRINCEEN_MASK (0x4000U) +#define SYSCON_PERIPHENCFG_PRINCEEN_SHIFT (14U) +/*! PRINCEEN - PRINCE enable. + * 0b1..peripheral is enable. + * 0b0..peripheral is disable. + */ +#define SYSCON_PERIPHENCFG_PRINCEEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PERIPHENCFG_PRINCEEN_SHIFT)) & SYSCON_PERIPHENCFG_PRINCEEN_MASK) +/*! @} */ + +/*! @name DEVICE_ID0 - Device ID */ +/*! @{ */ +#define SYSCON_DEVICE_ID0_PARTCONFIG_MASK (0xFFU) +#define SYSCON_DEVICE_ID0_PARTCONFIG_SHIFT (0U) +#define SYSCON_DEVICE_ID0_PARTCONFIG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_PARTCONFIG_SHIFT)) & SYSCON_DEVICE_ID0_PARTCONFIG_MASK) +#define SYSCON_DEVICE_ID0_SRAM_SIZE_MASK (0xF00U) +#define SYSCON_DEVICE_ID0_SRAM_SIZE_SHIFT (8U) +#define SYSCON_DEVICE_ID0_SRAM_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_SRAM_SIZE_SHIFT)) & SYSCON_DEVICE_ID0_SRAM_SIZE_MASK) +#define SYSCON_DEVICE_ID0_FLASH_SIZE_MASK (0x7000U) +#define SYSCON_DEVICE_ID0_FLASH_SIZE_SHIFT (12U) +#define SYSCON_DEVICE_ID0_FLASH_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_FLASH_SIZE_SHIFT)) & SYSCON_DEVICE_ID0_FLASH_SIZE_MASK) +#define SYSCON_DEVICE_ID0_ROM_REV_MINOR_MASK (0xF00000U) +#define SYSCON_DEVICE_ID0_ROM_REV_MINOR_SHIFT (20U) +#define SYSCON_DEVICE_ID0_ROM_REV_MINOR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_ROM_REV_MINOR_SHIFT)) & SYSCON_DEVICE_ID0_ROM_REV_MINOR_MASK) +#define SYSCON_DEVICE_ID0_MODELNUM_EXTENTION_MASK (0x7000000U) +#define SYSCON_DEVICE_ID0_MODELNUM_EXTENTION_SHIFT (24U) +#define SYSCON_DEVICE_ID0_MODELNUM_EXTENTION(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_MODELNUM_EXTENTION_SHIFT)) & SYSCON_DEVICE_ID0_MODELNUM_EXTENTION_MASK) +/*! @} */ + +/*! @name DIEID - Chip revision ID and Number */ +/*! @{ */ +#define SYSCON_DIEID_REV_ID_MASK (0xFU) +#define SYSCON_DIEID_REV_ID_SHIFT (0U) +#define SYSCON_DIEID_REV_ID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DIEID_REV_ID_SHIFT)) & SYSCON_DIEID_REV_ID_MASK) +#define SYSCON_DIEID_MCO_NUM_IN_DIE_ID_MASK (0xFFFFF0U) +#define SYSCON_DIEID_MCO_NUM_IN_DIE_ID_SHIFT (4U) +#define SYSCON_DIEID_MCO_NUM_IN_DIE_ID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DIEID_MCO_NUM_IN_DIE_ID_SHIFT)) & SYSCON_DIEID_MCO_NUM_IN_DIE_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SYSCON_Register_Masks */ + + +/* SYSCON - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral SYSCON base address */ + #define SYSCON_BASE (0x50000000u) + /** Peripheral SYSCON base address */ + #define SYSCON_BASE_NS (0x40000000u) + /** Peripheral SYSCON base pointer */ + #define SYSCON ((SYSCON_Type *)SYSCON_BASE) + /** Peripheral SYSCON base pointer */ + #define SYSCON_NS ((SYSCON_Type *)SYSCON_BASE_NS) + /** Array initializer of SYSCON peripheral base addresses */ + #define SYSCON_BASE_ADDRS { SYSCON_BASE } + /** Array initializer of SYSCON peripheral base pointers */ + #define SYSCON_BASE_PTRS { SYSCON } + /** Array initializer of SYSCON peripheral base addresses */ + #define SYSCON_BASE_ADDRS_NS { SYSCON_BASE_NS } + /** Array initializer of SYSCON peripheral base pointers */ + #define SYSCON_BASE_PTRS_NS { SYSCON_NS } +#else + /** Peripheral SYSCON base address */ + #define SYSCON_BASE (0x40000000u) + /** Peripheral SYSCON base pointer */ + #define SYSCON ((SYSCON_Type *)SYSCON_BASE) + /** Array initializer of SYSCON peripheral base addresses */ + #define SYSCON_BASE_ADDRS { SYSCON_BASE } + /** Array initializer of SYSCON peripheral base pointers */ + #define SYSCON_BASE_PTRS { SYSCON } +#endif + +/*! + * @} + */ /* end of group SYSCON_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SYSCTL Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SYSCTL_Peripheral_Access_Layer SYSCTL Peripheral Access Layer + * @{ + */ + +/** SYSCTL - Register Layout Typedef */ +typedef struct { + __IO uint32_t UPDATELCKOUT; /**< update lock out control, offset: 0x0 */ + uint8_t RESERVED_0[60]; + __IO uint32_t FCCTRLSEL[8]; /**< Selects the source for SCK going into Flexcomm 0..Selects the source for SCK going into Flexcomm 7, array offset: 0x40, array step: 0x4 */ + uint8_t RESERVED_1[32]; + __IO uint32_t SHAREDCTRLSET[2]; /**< Selects sources and data combinations for shared signal set 0...Selects sources and data combinations for shared signal set 1., array offset: 0x80, array step: 0x4 */ + uint8_t RESERVED_2[120]; + __I uint32_t USB_HS_STATUS; /**< Status register for USB HS, offset: 0x100 */ +} SYSCTL_Type; + +/* ---------------------------------------------------------------------------- + -- SYSCTL Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SYSCTL_Register_Masks SYSCTL Register Masks + * @{ + */ + +/*! @name UPDATELCKOUT - update lock out control */ +/*! @{ */ +#define SYSCTL_UPDATELCKOUT_UPDATELCKOUT_MASK (0x1U) +#define SYSCTL_UPDATELCKOUT_UPDATELCKOUT_SHIFT (0U) +/*! UPDATELCKOUT - All Registers + * 0b0..Normal Mode. Can be written to. + * 0b1..Protected Mode. Cannot be written to. + */ +#define SYSCTL_UPDATELCKOUT_UPDATELCKOUT(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_UPDATELCKOUT_UPDATELCKOUT_SHIFT)) & SYSCTL_UPDATELCKOUT_UPDATELCKOUT_MASK) +/*! @} */ + +/*! @name FCCTRLSEL - Selects the source for SCK going into Flexcomm 0..Selects the source for SCK going into Flexcomm 7 */ +/*! @{ */ +#define SYSCTL_FCCTRLSEL_SCKINSEL_MASK (0x3U) +#define SYSCTL_FCCTRLSEL_SCKINSEL_SHIFT (0U) +/*! SCKINSEL - Selects the source for SCK going into this Flexcomm. + * 0b00..Selects the dedicated FCn_SCK function for this Flexcomm. + * 0b01..SCK is taken from shared signal set 0 (defined by SHAREDCTRLSET0). + * 0b10..SCK is taken from shared signal set 1 (defined by SHAREDCTRLSET1). + * 0b11..Reserved. + */ +#define SYSCTL_FCCTRLSEL_SCKINSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_SCKINSEL_SHIFT)) & SYSCTL_FCCTRLSEL_SCKINSEL_MASK) +#define SYSCTL_FCCTRLSEL_WSINSEL_MASK (0x300U) +#define SYSCTL_FCCTRLSEL_WSINSEL_SHIFT (8U) +/*! WSINSEL - Selects the source for WS going into this Flexcomm. + * 0b00..Selects the dedicated (FCn_TXD_SCL_MISO_WS) function for this Flexcomm. + * 0b01..WS is taken from shared signal set 0 (defined by SHAREDCTRLSET0). + * 0b10..WS is taken from shared signal set 1 (defined by SHAREDCTRLSET1). + * 0b11..Reserved. + */ +#define SYSCTL_FCCTRLSEL_WSINSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_WSINSEL_SHIFT)) & SYSCTL_FCCTRLSEL_WSINSEL_MASK) +#define SYSCTL_FCCTRLSEL_DATAINSEL_MASK (0x30000U) +#define SYSCTL_FCCTRLSEL_DATAINSEL_SHIFT (16U) +/*! DATAINSEL - Selects the source for DATA input to this Flexcomm. + * 0b00..Selects the dedicated FCn_RXD_SDA_MOSI_DATA input for this Flexcomm. + * 0b01..Input data is taken from shared signal set 0 (defined by SHAREDCTRLSET0). + * 0b10..Input data is taken from shared signal set 1 (defined by SHAREDCTRLSET1). + * 0b11..Reserved. + */ +#define SYSCTL_FCCTRLSEL_DATAINSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_DATAINSEL_SHIFT)) & SYSCTL_FCCTRLSEL_DATAINSEL_MASK) +#define SYSCTL_FCCTRLSEL_DATAOUTSEL_MASK (0x3000000U) +#define SYSCTL_FCCTRLSEL_DATAOUTSEL_SHIFT (24U) +/*! DATAOUTSEL - Selects the source for DATA output from this Flexcomm. + * 0b00..Selects the dedicated FCn_RXD_SDA_MOSI_DATA output from this Flexcomm. + * 0b01..Output data is taken from shared signal set 0 (defined by SHAREDCTRLSET0). + * 0b10..Output data is taken from shared signal set 1 (defined by SHAREDCTRLSET1). + * 0b11..Reserved. + */ +#define SYSCTL_FCCTRLSEL_DATAOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_DATAOUTSEL_SHIFT)) & SYSCTL_FCCTRLSEL_DATAOUTSEL_MASK) +/*! @} */ + +/* The count of SYSCTL_FCCTRLSEL */ +#define SYSCTL_FCCTRLSEL_COUNT (8U) + +/*! @name SHARECTRLSET_SHAREDCTRLSET - Selects sources and data combinations for shared signal set 0...Selects sources and data combinations for shared signal set 1. */ +/*! @{ */ +#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDSCKSEL_MASK (0x7U) +#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDSCKSEL_SHIFT (0U) +/*! SHAREDSCKSEL - Selects the source for SCK of this shared signal set. + * 0b000..SCK for this shared signal set comes from Flexcomm 0. + * 0b001..SCK for this shared signal set comes from Flexcomm 1. + * 0b010..SCK for this shared signal set comes from Flexcomm 2. + * 0b011..SCK for this shared signal set comes from Flexcomm 3. + * 0b100..SCK for this shared signal set comes from Flexcomm 4. + * 0b101..SCK for this shared signal set comes from Flexcomm 5. + * 0b110..SCK for this shared signal set comes from Flexcomm 6. + * 0b111..SCK for this shared signal set comes from Flexcomm 7. + */ +#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDSCKSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDSCKSEL_SHIFT)) & SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDSCKSEL_MASK) +#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDWSSEL_MASK (0x70U) +#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDWSSEL_SHIFT (4U) +/*! SHAREDWSSEL - Selects the source for WS of this shared signal set. + * 0b000..WS for this shared signal set comes from Flexcomm 0. + * 0b001..WS for this shared signal set comes from Flexcomm 1. + * 0b010..WS for this shared signal set comes from Flexcomm 2. + * 0b011..WS for this shared signal set comes from Flexcomm 3. + * 0b100..WS for this shared signal set comes from Flexcomm 4. + * 0b101..WS for this shared signal set comes from Flexcomm 5. + * 0b110..WS for this shared signal set comes from Flexcomm 6. + * 0b111..WS for this shared signal set comes from Flexcomm 7. + */ +#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDWSSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDWSSEL_SHIFT)) & SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDWSSEL_MASK) +#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDDATASEL_MASK (0x700U) +#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDDATASEL_SHIFT (8U) +/*! SHAREDDATASEL - Selects the source for DATA input for this shared signal set. + * 0b000..DATA input for this shared signal set comes from Flexcomm 0. + * 0b001..DATA input for this shared signal set comes from Flexcomm 1. + * 0b010..DATA input for this shared signal set comes from Flexcomm 2. + * 0b011..DATA input for this shared signal set comes from Flexcomm 3. + * 0b100..DATA input for this shared signal set comes from Flexcomm 4. + * 0b101..DATA input for this shared signal set comes from Flexcomm 5. + * 0b110..DATA input for this shared signal set comes from Flexcomm 6. + * 0b111..DATA input for this shared signal set comes from Flexcomm 7. + */ +#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDDATASEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDDATASEL_SHIFT)) & SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDDATASEL_MASK) +#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC0DATAOUTEN_MASK (0x10000U) +#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC0DATAOUTEN_SHIFT (16U) +/*! FC0DATAOUTEN - Controls FC0 contribution to SHAREDDATAOUT for this shared set. + * 0b0..Data output from FC0 does not contribute to this shared set. + * 0b1..Data output from FC0 does contribute to this shared set. + */ +#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC0DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC0DATAOUTEN_SHIFT)) & SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC0DATAOUTEN_MASK) +#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC1DATAOUTEN_MASK (0x20000U) +#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC1DATAOUTEN_SHIFT (17U) +/*! FC1DATAOUTEN - Controls FC1 contribution to SHAREDDATAOUT for this shared set. + * 0b0..Data output from FC1 does not contribute to this shared set. + * 0b1..Data output from FC1 does contribute to this shared set. + */ +#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC1DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC1DATAOUTEN_SHIFT)) & SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC1DATAOUTEN_MASK) +#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_F20DATAOUTEN_MASK (0x40000U) +#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_F20DATAOUTEN_SHIFT (18U) +/*! F20DATAOUTEN - Controls FC2 contribution to SHAREDDATAOUT for this shared set. + * 0b0..Data output from FC2 does not contribute to this shared set. + * 0b1..Data output from FC2 does contribute to this shared set. + */ +#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_F20DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHARECTRLSET_SHAREDCTRLSET_F20DATAOUTEN_SHIFT)) & SYSCTL_SHARECTRLSET_SHAREDCTRLSET_F20DATAOUTEN_MASK) +#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC3DATAOUTEN_MASK (0x80000U) +#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC3DATAOUTEN_SHIFT (19U) +/*! FC3DATAOUTEN - Controls FC3 contribution to SHAREDDATAOUT for this shared set. + * 0b0..Data output from FC3 does not contribute to this shared set. + * 0b1..Data output from FC3 does contribute to this shared set. + */ +#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC3DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC3DATAOUTEN_SHIFT)) & SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC3DATAOUTEN_MASK) +#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC4DATAOUTEN_MASK (0x100000U) +#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC4DATAOUTEN_SHIFT (20U) +/*! FC4DATAOUTEN - Controls FC4 contribution to SHAREDDATAOUT for this shared set. + * 0b0..Data output from FC4 does not contribute to this shared set. + * 0b1..Data output from FC4 does contribute to this shared set. + */ +#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC4DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC4DATAOUTEN_SHIFT)) & SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC4DATAOUTEN_MASK) +#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC5DATAOUTEN_MASK (0x200000U) +#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC5DATAOUTEN_SHIFT (21U) +/*! FC5DATAOUTEN - Controls FC5 contribution to SHAREDDATAOUT for this shared set. + * 0b0..Data output from FC5 does not contribute to this shared set. + * 0b1..Data output from FC5 does contribute to this shared set. + */ +#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC5DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC5DATAOUTEN_SHIFT)) & SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC5DATAOUTEN_MASK) +#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC6DATAOUTEN_MASK (0x400000U) +#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC6DATAOUTEN_SHIFT (22U) +/*! FC6DATAOUTEN - Controls FC6 contribution to SHAREDDATAOUT for this shared set. + * 0b0..Data output from FC6 does not contribute to this shared set. + * 0b1..Data output from FC6 does contribute to this shared set. + */ +#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC6DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC6DATAOUTEN_SHIFT)) & SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC6DATAOUTEN_MASK) +#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC7DATAOUTEN_MASK (0x800000U) +#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC7DATAOUTEN_SHIFT (23U) +/*! FC7DATAOUTEN - Controls FC7 contribution to SHAREDDATAOUT for this shared set. + * 0b0..Data output from FC7 does not contribute to this shared set. + * 0b1..Data output from FC7 does contribute to this shared set. + */ +#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC7DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC7DATAOUTEN_SHIFT)) & SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC7DATAOUTEN_MASK) +/*! @} */ + +/* The count of SYSCTL_SHARECTRLSET_SHAREDCTRLSET */ +#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_COUNT (2U) + +/*! @name USB_HS_STATUS - Status register for USB HS */ +/*! @{ */ +#define SYSCTL_USB_HS_STATUS_USBHS_3V_NOK_MASK (0x1U) +#define SYSCTL_USB_HS_STATUS_USBHS_3V_NOK_SHIFT (0U) +/*! USBHS_3V_NOK - USB_HS: Low voltage detection on 3.3V supply. + * 0b0..3v3 supply is good. + * 0b1..3v3 supply is too low. + */ +#define SYSCTL_USB_HS_STATUS_USBHS_3V_NOK(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_USB_HS_STATUS_USBHS_3V_NOK_SHIFT)) & SYSCTL_USB_HS_STATUS_USBHS_3V_NOK_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SYSCTL_Register_Masks */ + + +/* SYSCTL - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral SYSCTL base address */ + #define SYSCTL_BASE (0x50023000u) + /** Peripheral SYSCTL base address */ + #define SYSCTL_BASE_NS (0x40023000u) + /** Peripheral SYSCTL base pointer */ + #define SYSCTL ((SYSCTL_Type *)SYSCTL_BASE) + /** Peripheral SYSCTL base pointer */ + #define SYSCTL_NS ((SYSCTL_Type *)SYSCTL_BASE_NS) + /** Array initializer of SYSCTL peripheral base addresses */ + #define SYSCTL_BASE_ADDRS { SYSCTL_BASE } + /** Array initializer of SYSCTL peripheral base pointers */ + #define SYSCTL_BASE_PTRS { SYSCTL } + /** Array initializer of SYSCTL peripheral base addresses */ + #define SYSCTL_BASE_ADDRS_NS { SYSCTL_BASE_NS } + /** Array initializer of SYSCTL peripheral base pointers */ + #define SYSCTL_BASE_PTRS_NS { SYSCTL_NS } +#else + /** Peripheral SYSCTL base address */ + #define SYSCTL_BASE (0x40023000u) + /** Peripheral SYSCTL base pointer */ + #define SYSCTL ((SYSCTL_Type *)SYSCTL_BASE) + /** Array initializer of SYSCTL peripheral base addresses */ + #define SYSCTL_BASE_ADDRS { SYSCTL_BASE } + /** Array initializer of SYSCTL peripheral base pointers */ + #define SYSCTL_BASE_PTRS { SYSCTL } +#endif + +/*! + * @} + */ /* end of group SYSCTL_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USART Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USART_Peripheral_Access_Layer USART Peripheral Access Layer + * @{ + */ + +/** USART - Register Layout Typedef */ +typedef struct { + __IO uint32_t CFG; /**< USART Configuration register. Basic USART configuration settings that typically are not changed during operation., offset: 0x0 */ + __IO uint32_t CTL; /**< USART Control register. USART control settings that are more likely to change during operation., offset: 0x4 */ + __IO uint32_t STAT; /**< USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them., offset: 0x8 */ + __IO uint32_t INTENSET; /**< Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set., offset: 0xC */ + __O uint32_t INTENCLR; /**< Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared., offset: 0x10 */ + uint8_t RESERVED_0[12]; + __IO uint32_t BRG; /**< Baud Rate Generator register. 16-bit integer baud rate divisor value., offset: 0x20 */ + __I uint32_t INTSTAT; /**< Interrupt status register. Reflects interrupts that are currently enabled., offset: 0x24 */ + __IO uint32_t OSR; /**< Oversample selection register for asynchronous communication., offset: 0x28 */ + __IO uint32_t ADDR; /**< Address register for automatic address matching., offset: 0x2C */ + uint8_t RESERVED_1[3536]; + __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */ + __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ + __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */ + uint8_t RESERVED_2[4]; + __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */ + __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */ + __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */ + uint8_t RESERVED_3[4]; + __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ + uint8_t RESERVED_4[12]; + __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */ + uint8_t RESERVED_5[12]; + __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */ + uint8_t RESERVED_6[440]; + __I uint32_t ID; /**< Peripheral identification register., offset: 0xFFC */ +} USART_Type; + +/* ---------------------------------------------------------------------------- + -- USART Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USART_Register_Masks USART Register Masks + * @{ + */ + +/*! @name CFG - USART Configuration register. Basic USART configuration settings that typically are not changed during operation. */ +/*! @{ */ +#define USART_CFG_ENABLE_MASK (0x1U) +#define USART_CFG_ENABLE_SHIFT (0U) +/*! ENABLE - USART Enable. + * 0b0..Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0, + * all USART interrupts and DMA transfers are disabled. When Enable is set again, CFG and most other control + * bits remain unchanged. When re-enabled, the USART will immediately be ready to transmit because the + * transmitter has been reset and is therefore available. + * 0b1..Enabled. The USART is enabled for operation. + */ +#define USART_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_ENABLE_SHIFT)) & USART_CFG_ENABLE_MASK) +#define USART_CFG_DATALEN_MASK (0xCU) +#define USART_CFG_DATALEN_SHIFT (2U) +/*! DATALEN - Selects the data size for the USART. + * 0b00..7 bit Data length. + * 0b01..8 bit Data length. + * 0b10..9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET bit in the CTL register. + * 0b11..Reserved. + */ +#define USART_CFG_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_DATALEN_SHIFT)) & USART_CFG_DATALEN_MASK) +#define USART_CFG_PARITYSEL_MASK (0x30U) +#define USART_CFG_PARITYSEL_SHIFT (4U) +/*! PARITYSEL - Selects what type of parity is used by the USART. + * 0b00..No parity. + * 0b01..Reserved. + * 0b10..Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even, + * and the number of 1s in a received character is expected to be even. + * 0b11..Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd, + * and the number of 1s in a received character is expected to be odd. + */ +#define USART_CFG_PARITYSEL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_PARITYSEL_SHIFT)) & USART_CFG_PARITYSEL_MASK) +#define USART_CFG_STOPLEN_MASK (0x40U) +#define USART_CFG_STOPLEN_SHIFT (6U) +/*! STOPLEN - Number of stop bits appended to transmitted data. Only a single stop bit is required for received data. + * 0b0..1 stop bit. + * 0b1..2 stop bits. This setting should only be used for asynchronous communication. + */ +#define USART_CFG_STOPLEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_STOPLEN_SHIFT)) & USART_CFG_STOPLEN_MASK) +#define USART_CFG_MODE32K_MASK (0x80U) +#define USART_CFG_MODE32K_SHIFT (7U) +/*! MODE32K - Selects standard or 32 kHz clocking mode. + * 0b0..Disabled. USART uses standard clocking. + * 0b1..Enabled. USART uses the 32 kHz clock from the RTC oscillator as the clock source to the BRG, and uses a special bit clocking scheme. + */ +#define USART_CFG_MODE32K(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_MODE32K_SHIFT)) & USART_CFG_MODE32K_MASK) +#define USART_CFG_LINMODE_MASK (0x100U) +#define USART_CFG_LINMODE_SHIFT (8U) +/*! LINMODE - LIN break mode enable. + * 0b0..Disabled. Break detect and generate is configured for normal operation. + * 0b1..Enabled. Break detect and generate is configured for LIN bus operation. + */ +#define USART_CFG_LINMODE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_LINMODE_SHIFT)) & USART_CFG_LINMODE_MASK) +#define USART_CFG_CTSEN_MASK (0x200U) +#define USART_CFG_CTSEN_SHIFT (9U) +/*! CTSEN - CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input + * pin, or from the USART's own RTS if loopback mode is enabled. + * 0b0..No flow control. The transmitter does not receive any automatic flow control signal. + * 0b1..Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes. + */ +#define USART_CFG_CTSEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_CTSEN_SHIFT)) & USART_CFG_CTSEN_MASK) +#define USART_CFG_SYNCEN_MASK (0x800U) +#define USART_CFG_SYNCEN_SHIFT (11U) +/*! SYNCEN - Selects synchronous or asynchronous operation. + * 0b0..Asynchronous mode. + * 0b1..Synchronous mode. + */ +#define USART_CFG_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCEN_SHIFT)) & USART_CFG_SYNCEN_MASK) +#define USART_CFG_CLKPOL_MASK (0x1000U) +#define USART_CFG_CLKPOL_SHIFT (12U) +/*! CLKPOL - Selects the clock polarity and sampling edge of received data in synchronous mode. + * 0b0..Falling edge. Un_RXD is sampled on the falling edge of SCLK. + * 0b1..Rising edge. Un_RXD is sampled on the rising edge of SCLK. + */ +#define USART_CFG_CLKPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_CLKPOL_SHIFT)) & USART_CFG_CLKPOL_MASK) +#define USART_CFG_SYNCMST_MASK (0x4000U) +#define USART_CFG_SYNCMST_SHIFT (14U) +/*! SYNCMST - Synchronous mode Master select. + * 0b0..Slave. When synchronous mode is enabled, the USART is a slave. + * 0b1..Master. When synchronous mode is enabled, the USART is a master. + */ +#define USART_CFG_SYNCMST(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCMST_SHIFT)) & USART_CFG_SYNCMST_MASK) +#define USART_CFG_LOOP_MASK (0x8000U) +#define USART_CFG_LOOP_SHIFT (15U) +/*! LOOP - Selects data loopback mode. + * 0b0..Normal operation. + * 0b1..Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial + * data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD + * and Un_RTS activity will also appear on external pins if these functions are configured to appear on device + * pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN. + */ +#define USART_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_LOOP_SHIFT)) & USART_CFG_LOOP_MASK) +#define USART_CFG_OETA_MASK (0x40000U) +#define USART_CFG_OETA_SHIFT (18U) +/*! OETA - Output Enable Turnaround time enable for RS-485 operation. + * 0b0..Disabled. If selected by OESEL, the Output Enable signal deasserted at the end of the last stop bit of a transmission. + * 0b1..Enabled. If selected by OESEL, the Output Enable signal remains asserted for one character time after the + * end of the last stop bit of a transmission. OE will also remain asserted if another transmit begins + * before it is deasserted. + */ +#define USART_CFG_OETA(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OETA_SHIFT)) & USART_CFG_OETA_MASK) +#define USART_CFG_AUTOADDR_MASK (0x80000U) +#define USART_CFG_AUTOADDR_SHIFT (19U) +/*! AUTOADDR - Automatic Address matching enable. + * 0b0..Disabled. When addressing is enabled by ADDRDET, address matching is done by software. This provides the + * possibility of versatile addressing (e.g. respond to more than one address). + * 0b1..Enabled. When addressing is enabled by ADDRDET, address matching is done by hardware, using the value in + * the ADDR register as the address to match. + */ +#define USART_CFG_AUTOADDR(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_AUTOADDR_SHIFT)) & USART_CFG_AUTOADDR_MASK) +#define USART_CFG_OESEL_MASK (0x100000U) +#define USART_CFG_OESEL_SHIFT (20U) +/*! OESEL - Output Enable Select. + * 0b0..Standard. The RTS signal is used as the standard flow control function. + * 0b1..RS-485. The RTS signal configured to provide an output enable signal to control an RS-485 transceiver. + */ +#define USART_CFG_OESEL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OESEL_SHIFT)) & USART_CFG_OESEL_MASK) +#define USART_CFG_OEPOL_MASK (0x200000U) +#define USART_CFG_OEPOL_SHIFT (21U) +/*! OEPOL - Output Enable Polarity. + * 0b0..Low. If selected by OESEL, the output enable is active low. + * 0b1..High. If selected by OESEL, the output enable is active high. + */ +#define USART_CFG_OEPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OEPOL_SHIFT)) & USART_CFG_OEPOL_MASK) +#define USART_CFG_RXPOL_MASK (0x400000U) +#define USART_CFG_RXPOL_SHIFT (22U) +/*! RXPOL - Receive data polarity. + * 0b0..Standard. The RX signal is used as it arrives from the pin. This means that the RX rest value is 1, start + * bit is 0, data is not inverted, and the stop bit is 1. + * 0b1..Inverted. The RX signal is inverted before being used by the USART. This means that the RX rest value is + * 0, start bit is 1, data is inverted, and the stop bit is 0. + */ +#define USART_CFG_RXPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_RXPOL_SHIFT)) & USART_CFG_RXPOL_MASK) +#define USART_CFG_TXPOL_MASK (0x800000U) +#define USART_CFG_TXPOL_SHIFT (23U) +/*! TXPOL - Transmit data polarity. + * 0b0..Standard. The TX signal is sent out without change. This means that the TX rest value is 1, start bit is + * 0, data is not inverted, and the stop bit is 1. + * 0b1..Inverted. The TX signal is inverted by the USART before being sent out. This means that the TX rest value + * is 0, start bit is 1, data is inverted, and the stop bit is 0. + */ +#define USART_CFG_TXPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_TXPOL_SHIFT)) & USART_CFG_TXPOL_MASK) +/*! @} */ + +/*! @name CTL - USART Control register. USART control settings that are more likely to change during operation. */ +/*! @{ */ +#define USART_CTL_TXBRKEN_MASK (0x2U) +#define USART_CTL_TXBRKEN_SHIFT (1U) +/*! TXBRKEN - Break Enable. + * 0b0..Normal operation. + * 0b1..Continuous break. Continuous break is sent immediately when this bit is set, and remains until this bit + * is cleared. A break may be sent without danger of corrupting any currently transmitting character if the + * transmitter is first disabled (TXDIS in CTL is set) and then waiting for the transmitter to be disabled + * (TXDISINT in STAT = 1) before writing 1 to TXBRKEN. + */ +#define USART_CTL_TXBRKEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXBRKEN_SHIFT)) & USART_CTL_TXBRKEN_MASK) +#define USART_CTL_ADDRDET_MASK (0x4U) +#define USART_CTL_ADDRDET_SHIFT (2U) +/*! ADDRDET - Enable address detect mode. + * 0b0..Disabled. The USART presents all incoming data. + * 0b1..Enabled. The USART receiver ignores incoming data that does not have the most significant bit of the data + * (typically the 9th bit) = 1. When the data MSB bit = 1, the receiver treats the incoming data normally, + * generating a received data interrupt. Software can then check the data to see if this is an address that + * should be handled. If it is, the ADDRDET bit is cleared by software and further incoming data is handled + * normally. + */ +#define USART_CTL_ADDRDET(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_ADDRDET_SHIFT)) & USART_CTL_ADDRDET_MASK) +#define USART_CTL_TXDIS_MASK (0x40U) +#define USART_CTL_TXDIS_SHIFT (6U) +/*! TXDIS - Transmit Disable. + * 0b0..Not disabled. USART transmitter is not disabled. + * 0b1..Disabled. USART transmitter is disabled after any character currently being transmitted is complete. This + * feature can be used to facilitate software flow control. + */ +#define USART_CTL_TXDIS(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXDIS_SHIFT)) & USART_CTL_TXDIS_MASK) +#define USART_CTL_CC_MASK (0x100U) +#define USART_CTL_CC_SHIFT (8U) +/*! CC - Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode. + * 0b0..Clock on character. In synchronous mode, SCLK cycles only when characters are being sent on Un_TXD or to + * complete a character that is being received. + * 0b1..Continuous clock. SCLK runs continuously in synchronous mode, allowing characters to be received on + * Un_RxD independently from transmission on Un_TXD). + */ +#define USART_CTL_CC(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_CC_SHIFT)) & USART_CTL_CC_MASK) +#define USART_CTL_CLRCCONRX_MASK (0x200U) +#define USART_CTL_CLRCCONRX_SHIFT (9U) +/*! CLRCCONRX - Clear Continuous Clock. + * 0b0..No effect. No effect on the CC bit. + * 0b1..Auto-clear. The CC bit is automatically cleared when a complete character has been received. This bit is cleared at the same time. + */ +#define USART_CTL_CLRCCONRX(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_CLRCCONRX_SHIFT)) & USART_CTL_CLRCCONRX_MASK) +#define USART_CTL_AUTOBAUD_MASK (0x10000U) +#define USART_CTL_AUTOBAUD_SHIFT (16U) +/*! AUTOBAUD - Autobaud enable. + * 0b0..Disabled. USART is in normal operating mode. + * 0b1..Enabled. USART is in autobaud mode. This bit should only be set when the USART receiver is idle. The + * first start bit of RX is measured and used the update the BRG register to match the received data rate. + * AUTOBAUD is cleared once this process is complete, or if there is an AERR. + */ +#define USART_CTL_AUTOBAUD(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_AUTOBAUD_SHIFT)) & USART_CTL_AUTOBAUD_MASK) +/*! @} */ + +/*! @name STAT - USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them. */ +/*! @{ */ +#define USART_STAT_RXIDLE_MASK (0x2U) +#define USART_STAT_RXIDLE_SHIFT (1U) +#define USART_STAT_RXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXIDLE_SHIFT)) & USART_STAT_RXIDLE_MASK) +#define USART_STAT_TXIDLE_MASK (0x8U) +#define USART_STAT_TXIDLE_SHIFT (3U) +#define USART_STAT_TXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXIDLE_SHIFT)) & USART_STAT_TXIDLE_MASK) +#define USART_STAT_CTS_MASK (0x10U) +#define USART_STAT_CTS_SHIFT (4U) +#define USART_STAT_CTS(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_CTS_SHIFT)) & USART_STAT_CTS_MASK) +#define USART_STAT_DELTACTS_MASK (0x20U) +#define USART_STAT_DELTACTS_SHIFT (5U) +#define USART_STAT_DELTACTS(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTACTS_SHIFT)) & USART_STAT_DELTACTS_MASK) +#define USART_STAT_TXDISSTAT_MASK (0x40U) +#define USART_STAT_TXDISSTAT_SHIFT (6U) +#define USART_STAT_TXDISSTAT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXDISSTAT_SHIFT)) & USART_STAT_TXDISSTAT_MASK) +#define USART_STAT_RXBRK_MASK (0x400U) +#define USART_STAT_RXBRK_SHIFT (10U) +#define USART_STAT_RXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXBRK_SHIFT)) & USART_STAT_RXBRK_MASK) +#define USART_STAT_DELTARXBRK_MASK (0x800U) +#define USART_STAT_DELTARXBRK_SHIFT (11U) +#define USART_STAT_DELTARXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTARXBRK_SHIFT)) & USART_STAT_DELTARXBRK_MASK) +#define USART_STAT_START_MASK (0x1000U) +#define USART_STAT_START_SHIFT (12U) +#define USART_STAT_START(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_START_SHIFT)) & USART_STAT_START_MASK) +#define USART_STAT_FRAMERRINT_MASK (0x2000U) +#define USART_STAT_FRAMERRINT_SHIFT (13U) +#define USART_STAT_FRAMERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_FRAMERRINT_SHIFT)) & USART_STAT_FRAMERRINT_MASK) +#define USART_STAT_PARITYERRINT_MASK (0x4000U) +#define USART_STAT_PARITYERRINT_SHIFT (14U) +#define USART_STAT_PARITYERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_PARITYERRINT_SHIFT)) & USART_STAT_PARITYERRINT_MASK) +#define USART_STAT_RXNOISEINT_MASK (0x8000U) +#define USART_STAT_RXNOISEINT_SHIFT (15U) +#define USART_STAT_RXNOISEINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXNOISEINT_SHIFT)) & USART_STAT_RXNOISEINT_MASK) +#define USART_STAT_ABERR_MASK (0x10000U) +#define USART_STAT_ABERR_SHIFT (16U) +#define USART_STAT_ABERR(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_ABERR_SHIFT)) & USART_STAT_ABERR_MASK) +/*! @} */ + +/*! @name INTENSET - Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */ +/*! @{ */ +#define USART_INTENSET_TXIDLEEN_MASK (0x8U) +#define USART_INTENSET_TXIDLEEN_SHIFT (3U) +#define USART_INTENSET_TXIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXIDLEEN_SHIFT)) & USART_INTENSET_TXIDLEEN_MASK) +#define USART_INTENSET_DELTACTSEN_MASK (0x20U) +#define USART_INTENSET_DELTACTSEN_SHIFT (5U) +#define USART_INTENSET_DELTACTSEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTACTSEN_SHIFT)) & USART_INTENSET_DELTACTSEN_MASK) +#define USART_INTENSET_TXDISEN_MASK (0x40U) +#define USART_INTENSET_TXDISEN_SHIFT (6U) +#define USART_INTENSET_TXDISEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXDISEN_SHIFT)) & USART_INTENSET_TXDISEN_MASK) +#define USART_INTENSET_DELTARXBRKEN_MASK (0x800U) +#define USART_INTENSET_DELTARXBRKEN_SHIFT (11U) +#define USART_INTENSET_DELTARXBRKEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTARXBRKEN_SHIFT)) & USART_INTENSET_DELTARXBRKEN_MASK) +#define USART_INTENSET_STARTEN_MASK (0x1000U) +#define USART_INTENSET_STARTEN_SHIFT (12U) +#define USART_INTENSET_STARTEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_STARTEN_SHIFT)) & USART_INTENSET_STARTEN_MASK) +#define USART_INTENSET_FRAMERREN_MASK (0x2000U) +#define USART_INTENSET_FRAMERREN_SHIFT (13U) +#define USART_INTENSET_FRAMERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_FRAMERREN_SHIFT)) & USART_INTENSET_FRAMERREN_MASK) +#define USART_INTENSET_PARITYERREN_MASK (0x4000U) +#define USART_INTENSET_PARITYERREN_SHIFT (14U) +#define USART_INTENSET_PARITYERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_PARITYERREN_SHIFT)) & USART_INTENSET_PARITYERREN_MASK) +#define USART_INTENSET_RXNOISEEN_MASK (0x8000U) +#define USART_INTENSET_RXNOISEEN_SHIFT (15U) +#define USART_INTENSET_RXNOISEEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_RXNOISEEN_SHIFT)) & USART_INTENSET_RXNOISEEN_MASK) +#define USART_INTENSET_ABERREN_MASK (0x10000U) +#define USART_INTENSET_ABERREN_SHIFT (16U) +#define USART_INTENSET_ABERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_ABERREN_SHIFT)) & USART_INTENSET_ABERREN_MASK) +/*! @} */ + +/*! @name INTENCLR - Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared. */ +/*! @{ */ +#define USART_INTENCLR_TXIDLECLR_MASK (0x8U) +#define USART_INTENCLR_TXIDLECLR_SHIFT (3U) +#define USART_INTENCLR_TXIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXIDLECLR_SHIFT)) & USART_INTENCLR_TXIDLECLR_MASK) +#define USART_INTENCLR_DELTACTSCLR_MASK (0x20U) +#define USART_INTENCLR_DELTACTSCLR_SHIFT (5U) +#define USART_INTENCLR_DELTACTSCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTACTSCLR_SHIFT)) & USART_INTENCLR_DELTACTSCLR_MASK) +#define USART_INTENCLR_TXDISCLR_MASK (0x40U) +#define USART_INTENCLR_TXDISCLR_SHIFT (6U) +#define USART_INTENCLR_TXDISCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXDISCLR_SHIFT)) & USART_INTENCLR_TXDISCLR_MASK) +#define USART_INTENCLR_DELTARXBRKCLR_MASK (0x800U) +#define USART_INTENCLR_DELTARXBRKCLR_SHIFT (11U) +#define USART_INTENCLR_DELTARXBRKCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTARXBRKCLR_SHIFT)) & USART_INTENCLR_DELTARXBRKCLR_MASK) +#define USART_INTENCLR_STARTCLR_MASK (0x1000U) +#define USART_INTENCLR_STARTCLR_SHIFT (12U) +#define USART_INTENCLR_STARTCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_STARTCLR_SHIFT)) & USART_INTENCLR_STARTCLR_MASK) +#define USART_INTENCLR_FRAMERRCLR_MASK (0x2000U) +#define USART_INTENCLR_FRAMERRCLR_SHIFT (13U) +#define USART_INTENCLR_FRAMERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_FRAMERRCLR_SHIFT)) & USART_INTENCLR_FRAMERRCLR_MASK) +#define USART_INTENCLR_PARITYERRCLR_MASK (0x4000U) +#define USART_INTENCLR_PARITYERRCLR_SHIFT (14U) +#define USART_INTENCLR_PARITYERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_PARITYERRCLR_SHIFT)) & USART_INTENCLR_PARITYERRCLR_MASK) +#define USART_INTENCLR_RXNOISECLR_MASK (0x8000U) +#define USART_INTENCLR_RXNOISECLR_SHIFT (15U) +#define USART_INTENCLR_RXNOISECLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_RXNOISECLR_SHIFT)) & USART_INTENCLR_RXNOISECLR_MASK) +#define USART_INTENCLR_ABERRCLR_MASK (0x10000U) +#define USART_INTENCLR_ABERRCLR_SHIFT (16U) +#define USART_INTENCLR_ABERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_ABERRCLR_SHIFT)) & USART_INTENCLR_ABERRCLR_MASK) +/*! @} */ + +/*! @name BRG - Baud Rate Generator register. 16-bit integer baud rate divisor value. */ +/*! @{ */ +#define USART_BRG_BRGVAL_MASK (0xFFFFU) +#define USART_BRG_BRGVAL_SHIFT (0U) +#define USART_BRG_BRGVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_BRG_BRGVAL_SHIFT)) & USART_BRG_BRGVAL_MASK) +/*! @} */ + +/*! @name INTSTAT - Interrupt status register. Reflects interrupts that are currently enabled. */ +/*! @{ */ +#define USART_INTSTAT_TXIDLE_MASK (0x8U) +#define USART_INTSTAT_TXIDLE_SHIFT (3U) +#define USART_INTSTAT_TXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXIDLE_SHIFT)) & USART_INTSTAT_TXIDLE_MASK) +#define USART_INTSTAT_DELTACTS_MASK (0x20U) +#define USART_INTSTAT_DELTACTS_SHIFT (5U) +#define USART_INTSTAT_DELTACTS(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTACTS_SHIFT)) & USART_INTSTAT_DELTACTS_MASK) +#define USART_INTSTAT_TXDISINT_MASK (0x40U) +#define USART_INTSTAT_TXDISINT_SHIFT (6U) +#define USART_INTSTAT_TXDISINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXDISINT_SHIFT)) & USART_INTSTAT_TXDISINT_MASK) +#define USART_INTSTAT_DELTARXBRK_MASK (0x800U) +#define USART_INTSTAT_DELTARXBRK_SHIFT (11U) +#define USART_INTSTAT_DELTARXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTARXBRK_SHIFT)) & USART_INTSTAT_DELTARXBRK_MASK) +#define USART_INTSTAT_START_MASK (0x1000U) +#define USART_INTSTAT_START_SHIFT (12U) +#define USART_INTSTAT_START(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_START_SHIFT)) & USART_INTSTAT_START_MASK) +#define USART_INTSTAT_FRAMERRINT_MASK (0x2000U) +#define USART_INTSTAT_FRAMERRINT_SHIFT (13U) +#define USART_INTSTAT_FRAMERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_FRAMERRINT_SHIFT)) & USART_INTSTAT_FRAMERRINT_MASK) +#define USART_INTSTAT_PARITYERRINT_MASK (0x4000U) +#define USART_INTSTAT_PARITYERRINT_SHIFT (14U) +#define USART_INTSTAT_PARITYERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_PARITYERRINT_SHIFT)) & USART_INTSTAT_PARITYERRINT_MASK) +#define USART_INTSTAT_RXNOISEINT_MASK (0x8000U) +#define USART_INTSTAT_RXNOISEINT_SHIFT (15U) +#define USART_INTSTAT_RXNOISEINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_RXNOISEINT_SHIFT)) & USART_INTSTAT_RXNOISEINT_MASK) +#define USART_INTSTAT_ABERRINT_MASK (0x10000U) +#define USART_INTSTAT_ABERRINT_SHIFT (16U) +#define USART_INTSTAT_ABERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_ABERRINT_SHIFT)) & USART_INTSTAT_ABERRINT_MASK) +/*! @} */ + +/*! @name OSR - Oversample selection register for asynchronous communication. */ +/*! @{ */ +#define USART_OSR_OSRVAL_MASK (0xFU) +#define USART_OSR_OSRVAL_SHIFT (0U) +#define USART_OSR_OSRVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_OSR_OSRVAL_SHIFT)) & USART_OSR_OSRVAL_MASK) +/*! @} */ + +/*! @name ADDR - Address register for automatic address matching. */ +/*! @{ */ +#define USART_ADDR_ADDRESS_MASK (0xFFU) +#define USART_ADDR_ADDRESS_SHIFT (0U) +#define USART_ADDR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << USART_ADDR_ADDRESS_SHIFT)) & USART_ADDR_ADDRESS_MASK) +/*! @} */ + +/*! @name FIFOCFG - FIFO configuration and enable register. */ +/*! @{ */ +#define USART_FIFOCFG_ENABLETX_MASK (0x1U) +#define USART_FIFOCFG_ENABLETX_SHIFT (0U) +/*! ENABLETX - Enable the transmit FIFO. + * 0b0..The transmit FIFO is not enabled. + * 0b1..The transmit FIFO is enabled. + */ +#define USART_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLETX_SHIFT)) & USART_FIFOCFG_ENABLETX_MASK) +#define USART_FIFOCFG_ENABLERX_MASK (0x2U) +#define USART_FIFOCFG_ENABLERX_SHIFT (1U) +/*! ENABLERX - Enable the receive FIFO. + * 0b0..The receive FIFO is not enabled. + * 0b1..The receive FIFO is enabled. + */ +#define USART_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLERX_SHIFT)) & USART_FIFOCFG_ENABLERX_MASK) +#define USART_FIFOCFG_SIZE_MASK (0x30U) +#define USART_FIFOCFG_SIZE_SHIFT (4U) +#define USART_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_SIZE_SHIFT)) & USART_FIFOCFG_SIZE_MASK) +#define USART_FIFOCFG_DMATX_MASK (0x1000U) +#define USART_FIFOCFG_DMATX_SHIFT (12U) +/*! DMATX - DMA configuration for transmit. + * 0b0..DMA is not used for the transmit function. + * 0b1..Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. + */ +#define USART_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMATX_SHIFT)) & USART_FIFOCFG_DMATX_MASK) +#define USART_FIFOCFG_DMARX_MASK (0x2000U) +#define USART_FIFOCFG_DMARX_SHIFT (13U) +/*! DMARX - DMA configuration for receive. + * 0b0..DMA is not used for the receive function. + * 0b1..Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. + */ +#define USART_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMARX_SHIFT)) & USART_FIFOCFG_DMARX_MASK) +#define USART_FIFOCFG_WAKETX_MASK (0x4000U) +#define USART_FIFOCFG_WAKETX_SHIFT (14U) +/*! WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power + * modes (up to power-down, as long as the peripheral function works in that power mode) without + * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The + * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware + * Wake-up control register. + * 0b0..Only enabled interrupts will wake up the device form reduced power modes. + * 0b1..A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in + * FIFOTRIG, even when the TXLVL interrupt is not enabled. + */ +#define USART_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKETX_SHIFT)) & USART_FIFOCFG_WAKETX_MASK) +#define USART_FIFOCFG_WAKERX_MASK (0x8000U) +#define USART_FIFOCFG_WAKERX_SHIFT (15U) +/*! WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power + * modes (up to power-down, as long as the peripheral function works in that power mode) without + * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The + * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware + * Wake-up control register. + * 0b0..Only enabled interrupts will wake up the device form reduced power modes. + * 0b1..A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in + * FIFOTRIG, even when the RXLVL interrupt is not enabled. + */ +#define USART_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKERX_SHIFT)) & USART_FIFOCFG_WAKERX_MASK) +#define USART_FIFOCFG_EMPTYTX_MASK (0x10000U) +#define USART_FIFOCFG_EMPTYTX_SHIFT (16U) +#define USART_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYTX_SHIFT)) & USART_FIFOCFG_EMPTYTX_MASK) +#define USART_FIFOCFG_EMPTYRX_MASK (0x20000U) +#define USART_FIFOCFG_EMPTYRX_SHIFT (17U) +#define USART_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYRX_SHIFT)) & USART_FIFOCFG_EMPTYRX_MASK) +#define USART_FIFOCFG_POPDBG_MASK (0x40000U) +#define USART_FIFOCFG_POPDBG_SHIFT (18U) +/*! POPDBG - Pop FIFO for debug reads. + * 0b0..Debug reads of the FIFO do not pop the FIFO. + * 0b1..A debug read will cause the FIFO to pop. + */ +#define USART_FIFOCFG_POPDBG(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_POPDBG_SHIFT)) & USART_FIFOCFG_POPDBG_MASK) +/*! @} */ + +/*! @name FIFOSTAT - FIFO status register. */ +/*! @{ */ +#define USART_FIFOSTAT_TXERR_MASK (0x1U) +#define USART_FIFOSTAT_TXERR_SHIFT (0U) +#define USART_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXERR_SHIFT)) & USART_FIFOSTAT_TXERR_MASK) +#define USART_FIFOSTAT_RXERR_MASK (0x2U) +#define USART_FIFOSTAT_RXERR_SHIFT (1U) +#define USART_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXERR_SHIFT)) & USART_FIFOSTAT_RXERR_MASK) +#define USART_FIFOSTAT_PERINT_MASK (0x8U) +#define USART_FIFOSTAT_PERINT_SHIFT (3U) +#define USART_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_PERINT_SHIFT)) & USART_FIFOSTAT_PERINT_MASK) +#define USART_FIFOSTAT_TXEMPTY_MASK (0x10U) +#define USART_FIFOSTAT_TXEMPTY_SHIFT (4U) +#define USART_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXEMPTY_SHIFT)) & USART_FIFOSTAT_TXEMPTY_MASK) +#define USART_FIFOSTAT_TXNOTFULL_MASK (0x20U) +#define USART_FIFOSTAT_TXNOTFULL_SHIFT (5U) +#define USART_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXNOTFULL_SHIFT)) & USART_FIFOSTAT_TXNOTFULL_MASK) +#define USART_FIFOSTAT_RXNOTEMPTY_MASK (0x40U) +#define USART_FIFOSTAT_RXNOTEMPTY_SHIFT (6U) +#define USART_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXNOTEMPTY_SHIFT)) & USART_FIFOSTAT_RXNOTEMPTY_MASK) +#define USART_FIFOSTAT_RXFULL_MASK (0x80U) +#define USART_FIFOSTAT_RXFULL_SHIFT (7U) +#define USART_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXFULL_SHIFT)) & USART_FIFOSTAT_RXFULL_MASK) +#define USART_FIFOSTAT_TXLVL_MASK (0x1F00U) +#define USART_FIFOSTAT_TXLVL_SHIFT (8U) +#define USART_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXLVL_SHIFT)) & USART_FIFOSTAT_TXLVL_MASK) +#define USART_FIFOSTAT_RXLVL_MASK (0x1F0000U) +#define USART_FIFOSTAT_RXLVL_SHIFT (16U) +#define USART_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXLVL_SHIFT)) & USART_FIFOSTAT_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */ +/*! @{ */ +#define USART_FIFOTRIG_TXLVLENA_MASK (0x1U) +#define USART_FIFOTRIG_TXLVLENA_SHIFT (0U) +/*! TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled + * in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set. + * 0b0..Transmit FIFO level does not generate a FIFO level trigger. + * 0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register. + */ +#define USART_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVLENA_SHIFT)) & USART_FIFOTRIG_TXLVLENA_MASK) +#define USART_FIFOTRIG_RXLVLENA_MASK (0x2U) +#define USART_FIFOTRIG_RXLVLENA_SHIFT (1U) +/*! RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled + * in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. + * 0b0..Receive FIFO level does not generate a FIFO level trigger. + * 0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. + */ +#define USART_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVLENA_SHIFT)) & USART_FIFOTRIG_RXLVLENA_MASK) +#define USART_FIFOTRIG_TXLVL_MASK (0xF00U) +#define USART_FIFOTRIG_TXLVL_SHIFT (8U) +#define USART_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVL_SHIFT)) & USART_FIFOTRIG_TXLVL_MASK) +#define USART_FIFOTRIG_RXLVL_MASK (0xF0000U) +#define USART_FIFOTRIG_RXLVL_SHIFT (16U) +#define USART_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVL_SHIFT)) & USART_FIFOTRIG_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */ +/*! @{ */ +#define USART_FIFOINTENSET_TXERR_MASK (0x1U) +#define USART_FIFOINTENSET_TXERR_SHIFT (0U) +/*! TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. + * 0b0..No interrupt will be generated for a transmit error. + * 0b1..An interrupt will be generated when a transmit error occurs. + */ +#define USART_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXERR_SHIFT)) & USART_FIFOINTENSET_TXERR_MASK) +#define USART_FIFOINTENSET_RXERR_MASK (0x2U) +#define USART_FIFOINTENSET_RXERR_SHIFT (1U) +/*! RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. + * 0b0..No interrupt will be generated for a receive error. + * 0b1..An interrupt will be generated when a receive error occurs. + */ +#define USART_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXERR_SHIFT)) & USART_FIFOINTENSET_RXERR_MASK) +#define USART_FIFOINTENSET_TXLVL_MASK (0x4U) +#define USART_FIFOINTENSET_TXLVL_SHIFT (2U) +/*! TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level + * specified by the TXLVL field in the FIFOTRIG register. + * 0b0..No interrupt will be generated based on the TX FIFO level. + * 0b1..If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases + * to the level specified by TXLVL in the FIFOTRIG register. + */ +#define USART_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXLVL_SHIFT)) & USART_FIFOINTENSET_TXLVL_MASK) +#define USART_FIFOINTENSET_RXLVL_MASK (0x8U) +#define USART_FIFOINTENSET_RXLVL_SHIFT (3U) +/*! RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level + * specified by the TXLVL field in the FIFOTRIG register. + * 0b0..No interrupt will be generated based on the RX FIFO level. + * 0b1..If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level + * increases to the level specified by RXLVL in the FIFOTRIG register. + */ +#define USART_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXLVL_SHIFT)) & USART_FIFOINTENSET_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */ +/*! @{ */ +#define USART_FIFOINTENCLR_TXERR_MASK (0x1U) +#define USART_FIFOINTENCLR_TXERR_SHIFT (0U) +#define USART_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXERR_SHIFT)) & USART_FIFOINTENCLR_TXERR_MASK) +#define USART_FIFOINTENCLR_RXERR_MASK (0x2U) +#define USART_FIFOINTENCLR_RXERR_SHIFT (1U) +#define USART_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXERR_SHIFT)) & USART_FIFOINTENCLR_RXERR_MASK) +#define USART_FIFOINTENCLR_TXLVL_MASK (0x4U) +#define USART_FIFOINTENCLR_TXLVL_SHIFT (2U) +#define USART_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXLVL_SHIFT)) & USART_FIFOINTENCLR_TXLVL_MASK) +#define USART_FIFOINTENCLR_RXLVL_MASK (0x8U) +#define USART_FIFOINTENCLR_RXLVL_SHIFT (3U) +#define USART_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXLVL_SHIFT)) & USART_FIFOINTENCLR_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTSTAT - FIFO interrupt status register. */ +/*! @{ */ +#define USART_FIFOINTSTAT_TXERR_MASK (0x1U) +#define USART_FIFOINTSTAT_TXERR_SHIFT (0U) +#define USART_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXERR_SHIFT)) & USART_FIFOINTSTAT_TXERR_MASK) +#define USART_FIFOINTSTAT_RXERR_MASK (0x2U) +#define USART_FIFOINTSTAT_RXERR_SHIFT (1U) +#define USART_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXERR_SHIFT)) & USART_FIFOINTSTAT_RXERR_MASK) +#define USART_FIFOINTSTAT_TXLVL_MASK (0x4U) +#define USART_FIFOINTSTAT_TXLVL_SHIFT (2U) +#define USART_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXLVL_SHIFT)) & USART_FIFOINTSTAT_TXLVL_MASK) +#define USART_FIFOINTSTAT_RXLVL_MASK (0x8U) +#define USART_FIFOINTSTAT_RXLVL_SHIFT (3U) +#define USART_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXLVL_SHIFT)) & USART_FIFOINTSTAT_RXLVL_MASK) +#define USART_FIFOINTSTAT_PERINT_MASK (0x10U) +#define USART_FIFOINTSTAT_PERINT_SHIFT (4U) +#define USART_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_PERINT_SHIFT)) & USART_FIFOINTSTAT_PERINT_MASK) +/*! @} */ + +/*! @name FIFOWR - FIFO write data. */ +/*! @{ */ +#define USART_FIFOWR_TXDATA_MASK (0x1FFU) +#define USART_FIFOWR_TXDATA_SHIFT (0U) +#define USART_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOWR_TXDATA_SHIFT)) & USART_FIFOWR_TXDATA_MASK) +/*! @} */ + +/*! @name FIFORD - FIFO read data. */ +/*! @{ */ +#define USART_FIFORD_RXDATA_MASK (0x1FFU) +#define USART_FIFORD_RXDATA_SHIFT (0U) +#define USART_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXDATA_SHIFT)) & USART_FIFORD_RXDATA_MASK) +#define USART_FIFORD_FRAMERR_MASK (0x2000U) +#define USART_FIFORD_FRAMERR_SHIFT (13U) +#define USART_FIFORD_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_FRAMERR_SHIFT)) & USART_FIFORD_FRAMERR_MASK) +#define USART_FIFORD_PARITYERR_MASK (0x4000U) +#define USART_FIFORD_PARITYERR_SHIFT (14U) +#define USART_FIFORD_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_PARITYERR_SHIFT)) & USART_FIFORD_PARITYERR_MASK) +#define USART_FIFORD_RXNOISE_MASK (0x8000U) +#define USART_FIFORD_RXNOISE_SHIFT (15U) +#define USART_FIFORD_RXNOISE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXNOISE_SHIFT)) & USART_FIFORD_RXNOISE_MASK) +/*! @} */ + +/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */ +/*! @{ */ +#define USART_FIFORDNOPOP_RXDATA_MASK (0x1FFU) +#define USART_FIFORDNOPOP_RXDATA_SHIFT (0U) +#define USART_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXDATA_SHIFT)) & USART_FIFORDNOPOP_RXDATA_MASK) +#define USART_FIFORDNOPOP_FRAMERR_MASK (0x2000U) +#define USART_FIFORDNOPOP_FRAMERR_SHIFT (13U) +#define USART_FIFORDNOPOP_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_FRAMERR_SHIFT)) & USART_FIFORDNOPOP_FRAMERR_MASK) +#define USART_FIFORDNOPOP_PARITYERR_MASK (0x4000U) +#define USART_FIFORDNOPOP_PARITYERR_SHIFT (14U) +#define USART_FIFORDNOPOP_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_PARITYERR_SHIFT)) & USART_FIFORDNOPOP_PARITYERR_MASK) +#define USART_FIFORDNOPOP_RXNOISE_MASK (0x8000U) +#define USART_FIFORDNOPOP_RXNOISE_SHIFT (15U) +#define USART_FIFORDNOPOP_RXNOISE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXNOISE_SHIFT)) & USART_FIFORDNOPOP_RXNOISE_MASK) +/*! @} */ + +/*! @name ID - Peripheral identification register. */ +/*! @{ */ +#define USART_ID_APERTURE_MASK (0xFFU) +#define USART_ID_APERTURE_SHIFT (0U) +#define USART_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_APERTURE_SHIFT)) & USART_ID_APERTURE_MASK) +#define USART_ID_MINOR_REV_MASK (0xF00U) +#define USART_ID_MINOR_REV_SHIFT (8U) +#define USART_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_MINOR_REV_SHIFT)) & USART_ID_MINOR_REV_MASK) +#define USART_ID_MAJOR_REV_MASK (0xF000U) +#define USART_ID_MAJOR_REV_SHIFT (12U) +#define USART_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_MAJOR_REV_SHIFT)) & USART_ID_MAJOR_REV_MASK) +#define USART_ID_ID_MASK (0xFFFF0000U) +#define USART_ID_ID_SHIFT (16U) +#define USART_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_ID_SHIFT)) & USART_ID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group USART_Register_Masks */ + + +/* USART - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral USART0 base address */ + #define USART0_BASE (0x50086000u) + /** Peripheral USART0 base address */ + #define USART0_BASE_NS (0x40086000u) + /** Peripheral USART0 base pointer */ + #define USART0 ((USART_Type *)USART0_BASE) + /** Peripheral USART0 base pointer */ + #define USART0_NS ((USART_Type *)USART0_BASE_NS) + /** Peripheral USART1 base address */ + #define USART1_BASE (0x50087000u) + /** Peripheral USART1 base address */ + #define USART1_BASE_NS (0x40087000u) + /** Peripheral USART1 base pointer */ + #define USART1 ((USART_Type *)USART1_BASE) + /** Peripheral USART1 base pointer */ + #define USART1_NS ((USART_Type *)USART1_BASE_NS) + /** Peripheral USART2 base address */ + #define USART2_BASE (0x50088000u) + /** Peripheral USART2 base address */ + #define USART2_BASE_NS (0x40088000u) + /** Peripheral USART2 base pointer */ + #define USART2 ((USART_Type *)USART2_BASE) + /** Peripheral USART2 base pointer */ + #define USART2_NS ((USART_Type *)USART2_BASE_NS) + /** Peripheral USART3 base address */ + #define USART3_BASE (0x50089000u) + /** Peripheral USART3 base address */ + #define USART3_BASE_NS (0x40089000u) + /** Peripheral USART3 base pointer */ + #define USART3 ((USART_Type *)USART3_BASE) + /** Peripheral USART3 base pointer */ + #define USART3_NS ((USART_Type *)USART3_BASE_NS) + /** Peripheral USART4 base address */ + #define USART4_BASE (0x5008A000u) + /** Peripheral USART4 base address */ + #define USART4_BASE_NS (0x4008A000u) + /** Peripheral USART4 base pointer */ + #define USART4 ((USART_Type *)USART4_BASE) + /** Peripheral USART4 base pointer */ + #define USART4_NS ((USART_Type *)USART4_BASE_NS) + /** Peripheral USART5 base address */ + #define USART5_BASE (0x50096000u) + /** Peripheral USART5 base address */ + #define USART5_BASE_NS (0x40096000u) + /** Peripheral USART5 base pointer */ + #define USART5 ((USART_Type *)USART5_BASE) + /** Peripheral USART5 base pointer */ + #define USART5_NS ((USART_Type *)USART5_BASE_NS) + /** Peripheral USART6 base address */ + #define USART6_BASE (0x50097000u) + /** Peripheral USART6 base address */ + #define USART6_BASE_NS (0x40097000u) + /** Peripheral USART6 base pointer */ + #define USART6 ((USART_Type *)USART6_BASE) + /** Peripheral USART6 base pointer */ + #define USART6_NS ((USART_Type *)USART6_BASE_NS) + /** Peripheral USART7 base address */ + #define USART7_BASE (0x50098000u) + /** Peripheral USART7 base address */ + #define USART7_BASE_NS (0x40098000u) + /** Peripheral USART7 base pointer */ + #define USART7 ((USART_Type *)USART7_BASE) + /** Peripheral USART7 base pointer */ + #define USART7_NS ((USART_Type *)USART7_BASE_NS) + /** Array initializer of USART peripheral base addresses */ + #define USART_BASE_ADDRS { USART0_BASE, USART1_BASE, USART2_BASE, USART3_BASE, USART4_BASE, USART5_BASE, USART6_BASE, USART7_BASE } + /** Array initializer of USART peripheral base pointers */ + #define USART_BASE_PTRS { USART0, USART1, USART2, USART3, USART4, USART5, USART6, USART7 } + /** Array initializer of USART peripheral base addresses */ + #define USART_BASE_ADDRS_NS { USART0_BASE_NS, USART1_BASE_NS, USART2_BASE_NS, USART3_BASE_NS, USART4_BASE_NS, USART5_BASE_NS, USART6_BASE_NS, USART7_BASE_NS } + /** Array initializer of USART peripheral base pointers */ + #define USART_BASE_PTRS_NS { USART0_NS, USART1_NS, USART2_NS, USART3_NS, USART4_NS, USART5_NS, USART6_NS, USART7_NS } +#else + /** Peripheral USART0 base address */ + #define USART0_BASE (0x40086000u) + /** Peripheral USART0 base pointer */ + #define USART0 ((USART_Type *)USART0_BASE) + /** Peripheral USART1 base address */ + #define USART1_BASE (0x40087000u) + /** Peripheral USART1 base pointer */ + #define USART1 ((USART_Type *)USART1_BASE) + /** Peripheral USART2 base address */ + #define USART2_BASE (0x40088000u) + /** Peripheral USART2 base pointer */ + #define USART2 ((USART_Type *)USART2_BASE) + /** Peripheral USART3 base address */ + #define USART3_BASE (0x40089000u) + /** Peripheral USART3 base pointer */ + #define USART3 ((USART_Type *)USART3_BASE) + /** Peripheral USART4 base address */ + #define USART4_BASE (0x4008A000u) + /** Peripheral USART4 base pointer */ + #define USART4 ((USART_Type *)USART4_BASE) + /** Peripheral USART5 base address */ + #define USART5_BASE (0x40096000u) + /** Peripheral USART5 base pointer */ + #define USART5 ((USART_Type *)USART5_BASE) + /** Peripheral USART6 base address */ + #define USART6_BASE (0x40097000u) + /** Peripheral USART6 base pointer */ + #define USART6 ((USART_Type *)USART6_BASE) + /** Peripheral USART7 base address */ + #define USART7_BASE (0x40098000u) + /** Peripheral USART7 base pointer */ + #define USART7 ((USART_Type *)USART7_BASE) + /** Array initializer of USART peripheral base addresses */ + #define USART_BASE_ADDRS { USART0_BASE, USART1_BASE, USART2_BASE, USART3_BASE, USART4_BASE, USART5_BASE, USART6_BASE, USART7_BASE } + /** Array initializer of USART peripheral base pointers */ + #define USART_BASE_PTRS { USART0, USART1, USART2, USART3, USART4, USART5, USART6, USART7 } +#endif +/** Interrupt vectors for the USART peripheral type */ +#define USART_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } + +/*! + * @} + */ /* end of group USART_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USB Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer + * @{ + */ + +/** USB - Register Layout Typedef */ +typedef struct { + __IO uint32_t DEVCMDSTAT; /**< USB Device Command/Status register, offset: 0x0 */ + __IO uint32_t INFO; /**< USB Info register, offset: 0x4 */ + __IO uint32_t EPLISTSTART; /**< USB EP Command/Status List start address, offset: 0x8 */ + __IO uint32_t DATABUFSTART; /**< USB Data buffer start address, offset: 0xC */ + __IO uint32_t LPM; /**< USB Link Power Management register, offset: 0x10 */ + __IO uint32_t EPSKIP; /**< USB Endpoint skip, offset: 0x14 */ + __IO uint32_t EPINUSE; /**< USB Endpoint Buffer in use, offset: 0x18 */ + __IO uint32_t EPBUFCFG; /**< USB Endpoint Buffer Configuration register, offset: 0x1C */ + __IO uint32_t INTSTAT; /**< USB interrupt status register, offset: 0x20 */ + __IO uint32_t INTEN; /**< USB interrupt enable register, offset: 0x24 */ + __IO uint32_t INTSETSTAT; /**< USB set interrupt status register, offset: 0x28 */ + uint8_t RESERVED_0[8]; + __IO uint32_t EPTOGGLE; /**< USB Endpoint toggle register, offset: 0x34 */ +} USB_Type; + +/* ---------------------------------------------------------------------------- + -- USB Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_Register_Masks USB Register Masks + * @{ + */ + +/*! @name DEVCMDSTAT - USB Device Command/Status register */ +/*! @{ */ +#define USB_DEVCMDSTAT_DEV_ADDR_MASK (0x7FU) +#define USB_DEVCMDSTAT_DEV_ADDR_SHIFT (0U) +#define USB_DEVCMDSTAT_DEV_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_ADDR_SHIFT)) & USB_DEVCMDSTAT_DEV_ADDR_MASK) +#define USB_DEVCMDSTAT_DEV_EN_MASK (0x80U) +#define USB_DEVCMDSTAT_DEV_EN_SHIFT (7U) +#define USB_DEVCMDSTAT_DEV_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_EN_SHIFT)) & USB_DEVCMDSTAT_DEV_EN_MASK) +#define USB_DEVCMDSTAT_SETUP_MASK (0x100U) +#define USB_DEVCMDSTAT_SETUP_SHIFT (8U) +#define USB_DEVCMDSTAT_SETUP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_SETUP_SHIFT)) & USB_DEVCMDSTAT_SETUP_MASK) +#define USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK (0x200U) +#define USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT (9U) +/*! FORCE_NEEDCLK - Forces the NEEDCLK output to always be on: + * 0b0..USB_NEEDCLK has normal function. + * 0b1..USB_NEEDCLK always 1. Clock will not be stopped in case of suspend. + */ +#define USB_DEVCMDSTAT_FORCE_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT)) & USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK) +#define USB_DEVCMDSTAT_LPM_SUP_MASK (0x800U) +#define USB_DEVCMDSTAT_LPM_SUP_SHIFT (11U) +/*! LPM_SUP - LPM Supported: + * 0b0..LPM not supported. + * 0b1..LPM supported. + */ +#define USB_DEVCMDSTAT_LPM_SUP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUP_SHIFT)) & USB_DEVCMDSTAT_LPM_SUP_MASK) +#define USB_DEVCMDSTAT_INTONNAK_AO_MASK (0x1000U) +#define USB_DEVCMDSTAT_INTONNAK_AO_SHIFT (12U) +/*! INTONNAK_AO - Interrupt on NAK for interrupt and bulk OUT EP + * 0b0..Only acknowledged packets generate an interrupt + * 0b1..Both acknowledged and NAKed packets generate interrupts. + */ +#define USB_DEVCMDSTAT_INTONNAK_AO(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AO_MASK) +#define USB_DEVCMDSTAT_INTONNAK_AI_MASK (0x2000U) +#define USB_DEVCMDSTAT_INTONNAK_AI_SHIFT (13U) +/*! INTONNAK_AI - Interrupt on NAK for interrupt and bulk IN EP + * 0b0..Only acknowledged packets generate an interrupt + * 0b1..Both acknowledged and NAKed packets generate interrupts. + */ +#define USB_DEVCMDSTAT_INTONNAK_AI(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AI_MASK) +#define USB_DEVCMDSTAT_INTONNAK_CO_MASK (0x4000U) +#define USB_DEVCMDSTAT_INTONNAK_CO_SHIFT (14U) +/*! INTONNAK_CO - Interrupt on NAK for control OUT EP + * 0b0..Only acknowledged packets generate an interrupt + * 0b1..Both acknowledged and NAKed packets generate interrupts. + */ +#define USB_DEVCMDSTAT_INTONNAK_CO(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CO_MASK) +#define USB_DEVCMDSTAT_INTONNAK_CI_MASK (0x8000U) +#define USB_DEVCMDSTAT_INTONNAK_CI_SHIFT (15U) +/*! INTONNAK_CI - Interrupt on NAK for control IN EP + * 0b0..Only acknowledged packets generate an interrupt + * 0b1..Both acknowledged and NAKed packets generate interrupts. + */ +#define USB_DEVCMDSTAT_INTONNAK_CI(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CI_MASK) +#define USB_DEVCMDSTAT_DCON_MASK (0x10000U) +#define USB_DEVCMDSTAT_DCON_SHIFT (16U) +#define USB_DEVCMDSTAT_DCON(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_SHIFT)) & USB_DEVCMDSTAT_DCON_MASK) +#define USB_DEVCMDSTAT_DSUS_MASK (0x20000U) +#define USB_DEVCMDSTAT_DSUS_SHIFT (17U) +#define USB_DEVCMDSTAT_DSUS(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_SHIFT)) & USB_DEVCMDSTAT_DSUS_MASK) +#define USB_DEVCMDSTAT_LPM_SUS_MASK (0x80000U) +#define USB_DEVCMDSTAT_LPM_SUS_SHIFT (19U) +#define USB_DEVCMDSTAT_LPM_SUS(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUS_SHIFT)) & USB_DEVCMDSTAT_LPM_SUS_MASK) +#define USB_DEVCMDSTAT_LPM_REWP_MASK (0x100000U) +#define USB_DEVCMDSTAT_LPM_REWP_SHIFT (20U) +#define USB_DEVCMDSTAT_LPM_REWP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_REWP_SHIFT)) & USB_DEVCMDSTAT_LPM_REWP_MASK) +#define USB_DEVCMDSTAT_DCON_C_MASK (0x1000000U) +#define USB_DEVCMDSTAT_DCON_C_SHIFT (24U) +#define USB_DEVCMDSTAT_DCON_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_C_SHIFT)) & USB_DEVCMDSTAT_DCON_C_MASK) +#define USB_DEVCMDSTAT_DSUS_C_MASK (0x2000000U) +#define USB_DEVCMDSTAT_DSUS_C_SHIFT (25U) +#define USB_DEVCMDSTAT_DSUS_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_C_SHIFT)) & USB_DEVCMDSTAT_DSUS_C_MASK) +#define USB_DEVCMDSTAT_DRES_C_MASK (0x4000000U) +#define USB_DEVCMDSTAT_DRES_C_SHIFT (26U) +#define USB_DEVCMDSTAT_DRES_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DRES_C_SHIFT)) & USB_DEVCMDSTAT_DRES_C_MASK) +#define USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK (0x10000000U) +#define USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT (28U) +#define USB_DEVCMDSTAT_VBUSDEBOUNCED(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT)) & USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK) +/*! @} */ + +/*! @name INFO - USB Info register */ +/*! @{ */ +#define USB_INFO_FRAME_NR_MASK (0x7FFU) +#define USB_INFO_FRAME_NR_SHIFT (0U) +#define USB_INFO_FRAME_NR(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_FRAME_NR_SHIFT)) & USB_INFO_FRAME_NR_MASK) +#define USB_INFO_ERR_CODE_MASK (0x7800U) +#define USB_INFO_ERR_CODE_SHIFT (11U) +/*! ERR_CODE - The error code which last occurred: + * 0b0000..No error + * 0b0001..PID encoding error + * 0b0010..PID unknown + * 0b0011..Packet unexpected + * 0b0100..Token CRC error + * 0b0101..Data CRC error + * 0b0110..Time out + * 0b0111..Babble + * 0b1000..Truncated EOP + * 0b1001..Sent/Received NAK + * 0b1010..Sent Stall + * 0b1011..Overrun + * 0b1100..Sent empty packet + * 0b1101..Bitstuff error + * 0b1110..Sync error + * 0b1111..Wrong data toggle + */ +#define USB_INFO_ERR_CODE(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_ERR_CODE_SHIFT)) & USB_INFO_ERR_CODE_MASK) +#define USB_INFO_MINREV_MASK (0xFF0000U) +#define USB_INFO_MINREV_SHIFT (16U) +#define USB_INFO_MINREV(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_MINREV_SHIFT)) & USB_INFO_MINREV_MASK) +#define USB_INFO_MAJREV_MASK (0xFF000000U) +#define USB_INFO_MAJREV_SHIFT (24U) +#define USB_INFO_MAJREV(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_MAJREV_SHIFT)) & USB_INFO_MAJREV_MASK) +/*! @} */ + +/*! @name EPLISTSTART - USB EP Command/Status List start address */ +/*! @{ */ +#define USB_EPLISTSTART_EP_LIST_MASK (0xFFFFFF00U) +#define USB_EPLISTSTART_EP_LIST_SHIFT (8U) +#define USB_EPLISTSTART_EP_LIST(x) (((uint32_t)(((uint32_t)(x)) << USB_EPLISTSTART_EP_LIST_SHIFT)) & USB_EPLISTSTART_EP_LIST_MASK) +/*! @} */ + +/*! @name DATABUFSTART - USB Data buffer start address */ +/*! @{ */ +#define USB_DATABUFSTART_DA_BUF_MASK (0xFFC00000U) +#define USB_DATABUFSTART_DA_BUF_SHIFT (22U) +#define USB_DATABUFSTART_DA_BUF(x) (((uint32_t)(((uint32_t)(x)) << USB_DATABUFSTART_DA_BUF_SHIFT)) & USB_DATABUFSTART_DA_BUF_MASK) +/*! @} */ + +/*! @name LPM - USB Link Power Management register */ +/*! @{ */ +#define USB_LPM_HIRD_HW_MASK (0xFU) +#define USB_LPM_HIRD_HW_SHIFT (0U) +#define USB_LPM_HIRD_HW(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_HW_SHIFT)) & USB_LPM_HIRD_HW_MASK) +#define USB_LPM_HIRD_SW_MASK (0xF0U) +#define USB_LPM_HIRD_SW_SHIFT (4U) +#define USB_LPM_HIRD_SW(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_SW_SHIFT)) & USB_LPM_HIRD_SW_MASK) +#define USB_LPM_DATA_PENDING_MASK (0x100U) +#define USB_LPM_DATA_PENDING_SHIFT (8U) +#define USB_LPM_DATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_DATA_PENDING_SHIFT)) & USB_LPM_DATA_PENDING_MASK) +/*! @} */ + +/*! @name EPSKIP - USB Endpoint skip */ +/*! @{ */ +#define USB_EPSKIP_SKIP_MASK (0x3FFU) +#define USB_EPSKIP_SKIP_SHIFT (0U) +#define USB_EPSKIP_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USB_EPSKIP_SKIP_SHIFT)) & USB_EPSKIP_SKIP_MASK) +/*! @} */ + +/*! @name EPINUSE - USB Endpoint Buffer in use */ +/*! @{ */ +#define USB_EPINUSE_BUF_MASK (0x3FCU) +#define USB_EPINUSE_BUF_SHIFT (2U) +#define USB_EPINUSE_BUF(x) (((uint32_t)(((uint32_t)(x)) << USB_EPINUSE_BUF_SHIFT)) & USB_EPINUSE_BUF_MASK) +/*! @} */ + +/*! @name EPBUFCFG - USB Endpoint Buffer Configuration register */ +/*! @{ */ +#define USB_EPBUFCFG_BUF_SB_MASK (0x3FCU) +#define USB_EPBUFCFG_BUF_SB_SHIFT (2U) +#define USB_EPBUFCFG_BUF_SB(x) (((uint32_t)(((uint32_t)(x)) << USB_EPBUFCFG_BUF_SB_SHIFT)) & USB_EPBUFCFG_BUF_SB_MASK) +/*! @} */ + +/*! @name INTSTAT - USB interrupt status register */ +/*! @{ */ +#define USB_INTSTAT_EP0OUT_MASK (0x1U) +#define USB_INTSTAT_EP0OUT_SHIFT (0U) +#define USB_INTSTAT_EP0OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0OUT_SHIFT)) & USB_INTSTAT_EP0OUT_MASK) +#define USB_INTSTAT_EP0IN_MASK (0x2U) +#define USB_INTSTAT_EP0IN_SHIFT (1U) +#define USB_INTSTAT_EP0IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0IN_SHIFT)) & USB_INTSTAT_EP0IN_MASK) +#define USB_INTSTAT_EP1OUT_MASK (0x4U) +#define USB_INTSTAT_EP1OUT_SHIFT (2U) +#define USB_INTSTAT_EP1OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1OUT_SHIFT)) & USB_INTSTAT_EP1OUT_MASK) +#define USB_INTSTAT_EP1IN_MASK (0x8U) +#define USB_INTSTAT_EP1IN_SHIFT (3U) +#define USB_INTSTAT_EP1IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1IN_SHIFT)) & USB_INTSTAT_EP1IN_MASK) +#define USB_INTSTAT_EP2OUT_MASK (0x10U) +#define USB_INTSTAT_EP2OUT_SHIFT (4U) +#define USB_INTSTAT_EP2OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2OUT_SHIFT)) & USB_INTSTAT_EP2OUT_MASK) +#define USB_INTSTAT_EP2IN_MASK (0x20U) +#define USB_INTSTAT_EP2IN_SHIFT (5U) +#define USB_INTSTAT_EP2IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2IN_SHIFT)) & USB_INTSTAT_EP2IN_MASK) +#define USB_INTSTAT_EP3OUT_MASK (0x40U) +#define USB_INTSTAT_EP3OUT_SHIFT (6U) +#define USB_INTSTAT_EP3OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3OUT_SHIFT)) & USB_INTSTAT_EP3OUT_MASK) +#define USB_INTSTAT_EP3IN_MASK (0x80U) +#define USB_INTSTAT_EP3IN_SHIFT (7U) +#define USB_INTSTAT_EP3IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3IN_SHIFT)) & USB_INTSTAT_EP3IN_MASK) +#define USB_INTSTAT_EP4OUT_MASK (0x100U) +#define USB_INTSTAT_EP4OUT_SHIFT (8U) +#define USB_INTSTAT_EP4OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4OUT_SHIFT)) & USB_INTSTAT_EP4OUT_MASK) +#define USB_INTSTAT_EP4IN_MASK (0x200U) +#define USB_INTSTAT_EP4IN_SHIFT (9U) +#define USB_INTSTAT_EP4IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4IN_SHIFT)) & USB_INTSTAT_EP4IN_MASK) +#define USB_INTSTAT_FRAME_INT_MASK (0x40000000U) +#define USB_INTSTAT_FRAME_INT_SHIFT (30U) +#define USB_INTSTAT_FRAME_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_FRAME_INT_SHIFT)) & USB_INTSTAT_FRAME_INT_MASK) +#define USB_INTSTAT_DEV_INT_MASK (0x80000000U) +#define USB_INTSTAT_DEV_INT_SHIFT (31U) +#define USB_INTSTAT_DEV_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_DEV_INT_SHIFT)) & USB_INTSTAT_DEV_INT_MASK) +/*! @} */ + +/*! @name INTEN - USB interrupt enable register */ +/*! @{ */ +#define USB_INTEN_EP_INT_EN_MASK (0x3FFU) +#define USB_INTEN_EP_INT_EN_SHIFT (0U) +#define USB_INTEN_EP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_EP_INT_EN_SHIFT)) & USB_INTEN_EP_INT_EN_MASK) +#define USB_INTEN_FRAME_INT_EN_MASK (0x40000000U) +#define USB_INTEN_FRAME_INT_EN_SHIFT (30U) +#define USB_INTEN_FRAME_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_FRAME_INT_EN_SHIFT)) & USB_INTEN_FRAME_INT_EN_MASK) +#define USB_INTEN_DEV_INT_EN_MASK (0x80000000U) +#define USB_INTEN_DEV_INT_EN_SHIFT (31U) +#define USB_INTEN_DEV_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_DEV_INT_EN_SHIFT)) & USB_INTEN_DEV_INT_EN_MASK) +/*! @} */ + +/*! @name INTSETSTAT - USB set interrupt status register */ +/*! @{ */ +#define USB_INTSETSTAT_EP_SET_INT_MASK (0x3FFU) +#define USB_INTSETSTAT_EP_SET_INT_SHIFT (0U) +#define USB_INTSETSTAT_EP_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_EP_SET_INT_SHIFT)) & USB_INTSETSTAT_EP_SET_INT_MASK) +#define USB_INTSETSTAT_FRAME_SET_INT_MASK (0x40000000U) +#define USB_INTSETSTAT_FRAME_SET_INT_SHIFT (30U) +#define USB_INTSETSTAT_FRAME_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_FRAME_SET_INT_SHIFT)) & USB_INTSETSTAT_FRAME_SET_INT_MASK) +#define USB_INTSETSTAT_DEV_SET_INT_MASK (0x80000000U) +#define USB_INTSETSTAT_DEV_SET_INT_SHIFT (31U) +#define USB_INTSETSTAT_DEV_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_DEV_SET_INT_SHIFT)) & USB_INTSETSTAT_DEV_SET_INT_MASK) +/*! @} */ + +/*! @name EPTOGGLE - USB Endpoint toggle register */ +/*! @{ */ +#define USB_EPTOGGLE_TOGGLE_MASK (0x3FFU) +#define USB_EPTOGGLE_TOGGLE_SHIFT (0U) +#define USB_EPTOGGLE_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << USB_EPTOGGLE_TOGGLE_SHIFT)) & USB_EPTOGGLE_TOGGLE_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group USB_Register_Masks */ + + +/* USB - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral USB0 base address */ + #define USB0_BASE (0x50084000u) + /** Peripheral USB0 base address */ + #define USB0_BASE_NS (0x40084000u) + /** Peripheral USB0 base pointer */ + #define USB0 ((USB_Type *)USB0_BASE) + /** Peripheral USB0 base pointer */ + #define USB0_NS ((USB_Type *)USB0_BASE_NS) + /** Array initializer of USB peripheral base addresses */ + #define USB_BASE_ADDRS { USB0_BASE } + /** Array initializer of USB peripheral base pointers */ + #define USB_BASE_PTRS { USB0 } + /** Array initializer of USB peripheral base addresses */ + #define USB_BASE_ADDRS_NS { USB0_BASE_NS } + /** Array initializer of USB peripheral base pointers */ + #define USB_BASE_PTRS_NS { USB0_NS } +#else + /** Peripheral USB0 base address */ + #define USB0_BASE (0x40084000u) + /** Peripheral USB0 base pointer */ + #define USB0 ((USB_Type *)USB0_BASE) + /** Array initializer of USB peripheral base addresses */ + #define USB_BASE_ADDRS { USB0_BASE } + /** Array initializer of USB peripheral base pointers */ + #define USB_BASE_PTRS { USB0 } +#endif +/** Interrupt vectors for the USB peripheral type */ +#define USB_IRQS { USB0_IRQn } +#define USB_NEEDCLK_IRQS { USB0_NEEDCLK_IRQn } + +/*! + * @} + */ /* end of group USB_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USBFSH Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBFSH_Peripheral_Access_Layer USBFSH Peripheral Access Layer + * @{ + */ + +/** USBFSH - Register Layout Typedef */ +typedef struct { + __I uint32_t HCREVISION; /**< BCD representation of the version of the HCI specification that is implemented by the Host Controller (HC), offset: 0x0 */ + __IO uint32_t HCCONTROL; /**< Defines the operating modes of the HC, offset: 0x4 */ + __IO uint32_t HCCOMMANDSTATUS; /**< This register is used to receive the commands from the Host Controller Driver (HCD), offset: 0x8 */ + __IO uint32_t HCINTERRUPTSTATUS; /**< Indicates the status on various events that cause hardware interrupts by setting the appropriate bits, offset: 0xC */ + __IO uint32_t HCINTERRUPTENABLE; /**< Controls the bits in the HcInterruptStatus register and indicates which events will generate a hardware interrupt, offset: 0x10 */ + __IO uint32_t HCINTERRUPTDISABLE; /**< The bits in this register are used to disable corresponding bits in the HCInterruptStatus register and in turn disable that event leading to hardware interrupt, offset: 0x14 */ + __IO uint32_t HCHCCA; /**< Contains the physical address of the host controller communication area, offset: 0x18 */ + __IO uint32_t HCPERIODCURRENTED; /**< Contains the physical address of the current isochronous or interrupt endpoint descriptor, offset: 0x1C */ + __IO uint32_t HCCONTROLHEADED; /**< Contains the physical address of the first endpoint descriptor of the control list, offset: 0x20 */ + __IO uint32_t HCCONTROLCURRENTED; /**< Contains the physical address of the current endpoint descriptor of the control list, offset: 0x24 */ + __IO uint32_t HCBULKHEADED; /**< Contains the physical address of the first endpoint descriptor of the bulk list, offset: 0x28 */ + __IO uint32_t HCBULKCURRENTED; /**< Contains the physical address of the current endpoint descriptor of the bulk list, offset: 0x2C */ + __IO uint32_t HCDONEHEAD; /**< Contains the physical address of the last transfer descriptor added to the 'Done' queue, offset: 0x30 */ + __IO uint32_t HCFMINTERVAL; /**< Defines the bit time interval in a frame and the full speed maximum packet size which would not cause an overrun, offset: 0x34 */ + __IO uint32_t HCFMREMAINING; /**< A 14-bit counter showing the bit time remaining in the current frame, offset: 0x38 */ + __IO uint32_t HCFMNUMBER; /**< Contains a 16-bit counter and provides the timing reference among events happening in the HC and the HCD, offset: 0x3C */ + __IO uint32_t HCPERIODICSTART; /**< Contains a programmable 14-bit value which determines the earliest time HC should start processing a periodic list, offset: 0x40 */ + __IO uint32_t HCLSTHRESHOLD; /**< Contains 11-bit value which is used by the HC to determine whether to commit to transfer a maximum of 8-byte LS packet before EOF, offset: 0x44 */ + __IO uint32_t HCRHDESCRIPTORA; /**< First of the two registers which describes the characteristics of the root hub, offset: 0x48 */ + __IO uint32_t HCRHDESCRIPTORB; /**< Second of the two registers which describes the characteristics of the Root Hub, offset: 0x4C */ + __IO uint32_t HCRHSTATUS; /**< This register is divided into two parts, offset: 0x50 */ + __IO uint32_t HCRHPORTSTATUS; /**< Controls and reports the port events on a per-port basis, offset: 0x54 */ + uint8_t RESERVED_0[4]; + __IO uint32_t PORTMODE; /**< Controls the port if it is attached to the host block or the device block, offset: 0x5C */ +} USBFSH_Type; + +/* ---------------------------------------------------------------------------- + -- USBFSH Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBFSH_Register_Masks USBFSH Register Masks + * @{ + */ + +/*! @name HCREVISION - BCD representation of the version of the HCI specification that is implemented by the Host Controller (HC) */ +/*! @{ */ +#define USBFSH_HCREVISION_REV_MASK (0xFFU) +#define USBFSH_HCREVISION_REV_SHIFT (0U) +#define USBFSH_HCREVISION_REV(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCREVISION_REV_SHIFT)) & USBFSH_HCREVISION_REV_MASK) +/*! @} */ + +/*! @name HCCONTROL - Defines the operating modes of the HC */ +/*! @{ */ +#define USBFSH_HCCONTROL_CBSR_MASK (0x3U) +#define USBFSH_HCCONTROL_CBSR_SHIFT (0U) +#define USBFSH_HCCONTROL_CBSR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_CBSR_SHIFT)) & USBFSH_HCCONTROL_CBSR_MASK) +#define USBFSH_HCCONTROL_PLE_MASK (0x4U) +#define USBFSH_HCCONTROL_PLE_SHIFT (2U) +#define USBFSH_HCCONTROL_PLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_PLE_SHIFT)) & USBFSH_HCCONTROL_PLE_MASK) +#define USBFSH_HCCONTROL_IE_MASK (0x8U) +#define USBFSH_HCCONTROL_IE_SHIFT (3U) +#define USBFSH_HCCONTROL_IE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_IE_SHIFT)) & USBFSH_HCCONTROL_IE_MASK) +#define USBFSH_HCCONTROL_CLE_MASK (0x10U) +#define USBFSH_HCCONTROL_CLE_SHIFT (4U) +#define USBFSH_HCCONTROL_CLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_CLE_SHIFT)) & USBFSH_HCCONTROL_CLE_MASK) +#define USBFSH_HCCONTROL_BLE_MASK (0x20U) +#define USBFSH_HCCONTROL_BLE_SHIFT (5U) +#define USBFSH_HCCONTROL_BLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_BLE_SHIFT)) & USBFSH_HCCONTROL_BLE_MASK) +#define USBFSH_HCCONTROL_HCFS_MASK (0xC0U) +#define USBFSH_HCCONTROL_HCFS_SHIFT (6U) +#define USBFSH_HCCONTROL_HCFS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_HCFS_SHIFT)) & USBFSH_HCCONTROL_HCFS_MASK) +#define USBFSH_HCCONTROL_IR_MASK (0x100U) +#define USBFSH_HCCONTROL_IR_SHIFT (8U) +#define USBFSH_HCCONTROL_IR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_IR_SHIFT)) & USBFSH_HCCONTROL_IR_MASK) +#define USBFSH_HCCONTROL_RWC_MASK (0x200U) +#define USBFSH_HCCONTROL_RWC_SHIFT (9U) +#define USBFSH_HCCONTROL_RWC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_RWC_SHIFT)) & USBFSH_HCCONTROL_RWC_MASK) +#define USBFSH_HCCONTROL_RWE_MASK (0x400U) +#define USBFSH_HCCONTROL_RWE_SHIFT (10U) +#define USBFSH_HCCONTROL_RWE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_RWE_SHIFT)) & USBFSH_HCCONTROL_RWE_MASK) +/*! @} */ + +/*! @name HCCOMMANDSTATUS - This register is used to receive the commands from the Host Controller Driver (HCD) */ +/*! @{ */ +#define USBFSH_HCCOMMANDSTATUS_HCR_MASK (0x1U) +#define USBFSH_HCCOMMANDSTATUS_HCR_SHIFT (0U) +#define USBFSH_HCCOMMANDSTATUS_HCR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_HCR_SHIFT)) & USBFSH_HCCOMMANDSTATUS_HCR_MASK) +#define USBFSH_HCCOMMANDSTATUS_CLF_MASK (0x2U) +#define USBFSH_HCCOMMANDSTATUS_CLF_SHIFT (1U) +#define USBFSH_HCCOMMANDSTATUS_CLF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_CLF_SHIFT)) & USBFSH_HCCOMMANDSTATUS_CLF_MASK) +#define USBFSH_HCCOMMANDSTATUS_BLF_MASK (0x4U) +#define USBFSH_HCCOMMANDSTATUS_BLF_SHIFT (2U) +#define USBFSH_HCCOMMANDSTATUS_BLF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_BLF_SHIFT)) & USBFSH_HCCOMMANDSTATUS_BLF_MASK) +#define USBFSH_HCCOMMANDSTATUS_OCR_MASK (0x8U) +#define USBFSH_HCCOMMANDSTATUS_OCR_SHIFT (3U) +#define USBFSH_HCCOMMANDSTATUS_OCR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_OCR_SHIFT)) & USBFSH_HCCOMMANDSTATUS_OCR_MASK) +#define USBFSH_HCCOMMANDSTATUS_SOC_MASK (0xC0U) +#define USBFSH_HCCOMMANDSTATUS_SOC_SHIFT (6U) +#define USBFSH_HCCOMMANDSTATUS_SOC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_SOC_SHIFT)) & USBFSH_HCCOMMANDSTATUS_SOC_MASK) +/*! @} */ + +/*! @name HCINTERRUPTSTATUS - Indicates the status on various events that cause hardware interrupts by setting the appropriate bits */ +/*! @{ */ +#define USBFSH_HCINTERRUPTSTATUS_SO_MASK (0x1U) +#define USBFSH_HCINTERRUPTSTATUS_SO_SHIFT (0U) +#define USBFSH_HCINTERRUPTSTATUS_SO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_SO_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_SO_MASK) +#define USBFSH_HCINTERRUPTSTATUS_WDH_MASK (0x2U) +#define USBFSH_HCINTERRUPTSTATUS_WDH_SHIFT (1U) +#define USBFSH_HCINTERRUPTSTATUS_WDH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_WDH_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_WDH_MASK) +#define USBFSH_HCINTERRUPTSTATUS_SF_MASK (0x4U) +#define USBFSH_HCINTERRUPTSTATUS_SF_SHIFT (2U) +#define USBFSH_HCINTERRUPTSTATUS_SF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_SF_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_SF_MASK) +#define USBFSH_HCINTERRUPTSTATUS_RD_MASK (0x8U) +#define USBFSH_HCINTERRUPTSTATUS_RD_SHIFT (3U) +#define USBFSH_HCINTERRUPTSTATUS_RD(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_RD_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_RD_MASK) +#define USBFSH_HCINTERRUPTSTATUS_UE_MASK (0x10U) +#define USBFSH_HCINTERRUPTSTATUS_UE_SHIFT (4U) +#define USBFSH_HCINTERRUPTSTATUS_UE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_UE_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_UE_MASK) +#define USBFSH_HCINTERRUPTSTATUS_FNO_MASK (0x20U) +#define USBFSH_HCINTERRUPTSTATUS_FNO_SHIFT (5U) +#define USBFSH_HCINTERRUPTSTATUS_FNO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_FNO_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_FNO_MASK) +#define USBFSH_HCINTERRUPTSTATUS_RHSC_MASK (0x40U) +#define USBFSH_HCINTERRUPTSTATUS_RHSC_SHIFT (6U) +#define USBFSH_HCINTERRUPTSTATUS_RHSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_RHSC_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_RHSC_MASK) +#define USBFSH_HCINTERRUPTSTATUS_OC_MASK (0xFFFFFC00U) +#define USBFSH_HCINTERRUPTSTATUS_OC_SHIFT (10U) +#define USBFSH_HCINTERRUPTSTATUS_OC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_OC_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_OC_MASK) +/*! @} */ + +/*! @name HCINTERRUPTENABLE - Controls the bits in the HcInterruptStatus register and indicates which events will generate a hardware interrupt */ +/*! @{ */ +#define USBFSH_HCINTERRUPTENABLE_SO_MASK (0x1U) +#define USBFSH_HCINTERRUPTENABLE_SO_SHIFT (0U) +#define USBFSH_HCINTERRUPTENABLE_SO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_SO_SHIFT)) & USBFSH_HCINTERRUPTENABLE_SO_MASK) +#define USBFSH_HCINTERRUPTENABLE_WDH_MASK (0x2U) +#define USBFSH_HCINTERRUPTENABLE_WDH_SHIFT (1U) +#define USBFSH_HCINTERRUPTENABLE_WDH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_WDH_SHIFT)) & USBFSH_HCINTERRUPTENABLE_WDH_MASK) +#define USBFSH_HCINTERRUPTENABLE_SF_MASK (0x4U) +#define USBFSH_HCINTERRUPTENABLE_SF_SHIFT (2U) +#define USBFSH_HCINTERRUPTENABLE_SF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_SF_SHIFT)) & USBFSH_HCINTERRUPTENABLE_SF_MASK) +#define USBFSH_HCINTERRUPTENABLE_RD_MASK (0x8U) +#define USBFSH_HCINTERRUPTENABLE_RD_SHIFT (3U) +#define USBFSH_HCINTERRUPTENABLE_RD(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_RD_SHIFT)) & USBFSH_HCINTERRUPTENABLE_RD_MASK) +#define USBFSH_HCINTERRUPTENABLE_UE_MASK (0x10U) +#define USBFSH_HCINTERRUPTENABLE_UE_SHIFT (4U) +#define USBFSH_HCINTERRUPTENABLE_UE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_UE_SHIFT)) & USBFSH_HCINTERRUPTENABLE_UE_MASK) +#define USBFSH_HCINTERRUPTENABLE_FNO_MASK (0x20U) +#define USBFSH_HCINTERRUPTENABLE_FNO_SHIFT (5U) +#define USBFSH_HCINTERRUPTENABLE_FNO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_FNO_SHIFT)) & USBFSH_HCINTERRUPTENABLE_FNO_MASK) +#define USBFSH_HCINTERRUPTENABLE_RHSC_MASK (0x40U) +#define USBFSH_HCINTERRUPTENABLE_RHSC_SHIFT (6U) +#define USBFSH_HCINTERRUPTENABLE_RHSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_RHSC_SHIFT)) & USBFSH_HCINTERRUPTENABLE_RHSC_MASK) +#define USBFSH_HCINTERRUPTENABLE_OC_MASK (0x40000000U) +#define USBFSH_HCINTERRUPTENABLE_OC_SHIFT (30U) +#define USBFSH_HCINTERRUPTENABLE_OC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_OC_SHIFT)) & USBFSH_HCINTERRUPTENABLE_OC_MASK) +#define USBFSH_HCINTERRUPTENABLE_MIE_MASK (0x80000000U) +#define USBFSH_HCINTERRUPTENABLE_MIE_SHIFT (31U) +#define USBFSH_HCINTERRUPTENABLE_MIE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_MIE_SHIFT)) & USBFSH_HCINTERRUPTENABLE_MIE_MASK) +/*! @} */ + +/*! @name HCINTERRUPTDISABLE - The bits in this register are used to disable corresponding bits in the HCInterruptStatus register and in turn disable that event leading to hardware interrupt */ +/*! @{ */ +#define USBFSH_HCINTERRUPTDISABLE_SO_MASK (0x1U) +#define USBFSH_HCINTERRUPTDISABLE_SO_SHIFT (0U) +#define USBFSH_HCINTERRUPTDISABLE_SO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_SO_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_SO_MASK) +#define USBFSH_HCINTERRUPTDISABLE_WDH_MASK (0x2U) +#define USBFSH_HCINTERRUPTDISABLE_WDH_SHIFT (1U) +#define USBFSH_HCINTERRUPTDISABLE_WDH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_WDH_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_WDH_MASK) +#define USBFSH_HCINTERRUPTDISABLE_SF_MASK (0x4U) +#define USBFSH_HCINTERRUPTDISABLE_SF_SHIFT (2U) +#define USBFSH_HCINTERRUPTDISABLE_SF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_SF_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_SF_MASK) +#define USBFSH_HCINTERRUPTDISABLE_RD_MASK (0x8U) +#define USBFSH_HCINTERRUPTDISABLE_RD_SHIFT (3U) +#define USBFSH_HCINTERRUPTDISABLE_RD(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_RD_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_RD_MASK) +#define USBFSH_HCINTERRUPTDISABLE_UE_MASK (0x10U) +#define USBFSH_HCINTERRUPTDISABLE_UE_SHIFT (4U) +#define USBFSH_HCINTERRUPTDISABLE_UE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_UE_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_UE_MASK) +#define USBFSH_HCINTERRUPTDISABLE_FNO_MASK (0x20U) +#define USBFSH_HCINTERRUPTDISABLE_FNO_SHIFT (5U) +#define USBFSH_HCINTERRUPTDISABLE_FNO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_FNO_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_FNO_MASK) +#define USBFSH_HCINTERRUPTDISABLE_RHSC_MASK (0x40U) +#define USBFSH_HCINTERRUPTDISABLE_RHSC_SHIFT (6U) +#define USBFSH_HCINTERRUPTDISABLE_RHSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_RHSC_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_RHSC_MASK) +#define USBFSH_HCINTERRUPTDISABLE_OC_MASK (0x40000000U) +#define USBFSH_HCINTERRUPTDISABLE_OC_SHIFT (30U) +#define USBFSH_HCINTERRUPTDISABLE_OC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_OC_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_OC_MASK) +#define USBFSH_HCINTERRUPTDISABLE_MIE_MASK (0x80000000U) +#define USBFSH_HCINTERRUPTDISABLE_MIE_SHIFT (31U) +#define USBFSH_HCINTERRUPTDISABLE_MIE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_MIE_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_MIE_MASK) +/*! @} */ + +/*! @name HCHCCA - Contains the physical address of the host controller communication area */ +/*! @{ */ +#define USBFSH_HCHCCA_HCCA_MASK (0xFFFFFF00U) +#define USBFSH_HCHCCA_HCCA_SHIFT (8U) +#define USBFSH_HCHCCA_HCCA(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCHCCA_HCCA_SHIFT)) & USBFSH_HCHCCA_HCCA_MASK) +/*! @} */ + +/*! @name HCPERIODCURRENTED - Contains the physical address of the current isochronous or interrupt endpoint descriptor */ +/*! @{ */ +#define USBFSH_HCPERIODCURRENTED_PCED_MASK (0xFFFFFFF0U) +#define USBFSH_HCPERIODCURRENTED_PCED_SHIFT (4U) +#define USBFSH_HCPERIODCURRENTED_PCED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCPERIODCURRENTED_PCED_SHIFT)) & USBFSH_HCPERIODCURRENTED_PCED_MASK) +/*! @} */ + +/*! @name HCCONTROLHEADED - Contains the physical address of the first endpoint descriptor of the control list */ +/*! @{ */ +#define USBFSH_HCCONTROLHEADED_CHED_MASK (0xFFFFFFF0U) +#define USBFSH_HCCONTROLHEADED_CHED_SHIFT (4U) +#define USBFSH_HCCONTROLHEADED_CHED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROLHEADED_CHED_SHIFT)) & USBFSH_HCCONTROLHEADED_CHED_MASK) +/*! @} */ + +/*! @name HCCONTROLCURRENTED - Contains the physical address of the current endpoint descriptor of the control list */ +/*! @{ */ +#define USBFSH_HCCONTROLCURRENTED_CCED_MASK (0xFFFFFFF0U) +#define USBFSH_HCCONTROLCURRENTED_CCED_SHIFT (4U) +#define USBFSH_HCCONTROLCURRENTED_CCED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROLCURRENTED_CCED_SHIFT)) & USBFSH_HCCONTROLCURRENTED_CCED_MASK) +/*! @} */ + +/*! @name HCBULKHEADED - Contains the physical address of the first endpoint descriptor of the bulk list */ +/*! @{ */ +#define USBFSH_HCBULKHEADED_BHED_MASK (0xFFFFFFF0U) +#define USBFSH_HCBULKHEADED_BHED_SHIFT (4U) +#define USBFSH_HCBULKHEADED_BHED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCBULKHEADED_BHED_SHIFT)) & USBFSH_HCBULKHEADED_BHED_MASK) +/*! @} */ + +/*! @name HCBULKCURRENTED - Contains the physical address of the current endpoint descriptor of the bulk list */ +/*! @{ */ +#define USBFSH_HCBULKCURRENTED_BCED_MASK (0xFFFFFFF0U) +#define USBFSH_HCBULKCURRENTED_BCED_SHIFT (4U) +#define USBFSH_HCBULKCURRENTED_BCED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCBULKCURRENTED_BCED_SHIFT)) & USBFSH_HCBULKCURRENTED_BCED_MASK) +/*! @} */ + +/*! @name HCDONEHEAD - Contains the physical address of the last transfer descriptor added to the 'Done' queue */ +/*! @{ */ +#define USBFSH_HCDONEHEAD_DH_MASK (0xFFFFFFF0U) +#define USBFSH_HCDONEHEAD_DH_SHIFT (4U) +#define USBFSH_HCDONEHEAD_DH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCDONEHEAD_DH_SHIFT)) & USBFSH_HCDONEHEAD_DH_MASK) +/*! @} */ + +/*! @name HCFMINTERVAL - Defines the bit time interval in a frame and the full speed maximum packet size which would not cause an overrun */ +/*! @{ */ +#define USBFSH_HCFMINTERVAL_FI_MASK (0x3FFFU) +#define USBFSH_HCFMINTERVAL_FI_SHIFT (0U) +#define USBFSH_HCFMINTERVAL_FI(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FI_SHIFT)) & USBFSH_HCFMINTERVAL_FI_MASK) +#define USBFSH_HCFMINTERVAL_FSMPS_MASK (0x7FFF0000U) +#define USBFSH_HCFMINTERVAL_FSMPS_SHIFT (16U) +#define USBFSH_HCFMINTERVAL_FSMPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FSMPS_SHIFT)) & USBFSH_HCFMINTERVAL_FSMPS_MASK) +#define USBFSH_HCFMINTERVAL_FIT_MASK (0x80000000U) +#define USBFSH_HCFMINTERVAL_FIT_SHIFT (31U) +#define USBFSH_HCFMINTERVAL_FIT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FIT_SHIFT)) & USBFSH_HCFMINTERVAL_FIT_MASK) +/*! @} */ + +/*! @name HCFMREMAINING - A 14-bit counter showing the bit time remaining in the current frame */ +/*! @{ */ +#define USBFSH_HCFMREMAINING_FR_MASK (0x3FFFU) +#define USBFSH_HCFMREMAINING_FR_SHIFT (0U) +#define USBFSH_HCFMREMAINING_FR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMREMAINING_FR_SHIFT)) & USBFSH_HCFMREMAINING_FR_MASK) +#define USBFSH_HCFMREMAINING_FRT_MASK (0x80000000U) +#define USBFSH_HCFMREMAINING_FRT_SHIFT (31U) +#define USBFSH_HCFMREMAINING_FRT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMREMAINING_FRT_SHIFT)) & USBFSH_HCFMREMAINING_FRT_MASK) +/*! @} */ + +/*! @name HCFMNUMBER - Contains a 16-bit counter and provides the timing reference among events happening in the HC and the HCD */ +/*! @{ */ +#define USBFSH_HCFMNUMBER_FN_MASK (0xFFFFU) +#define USBFSH_HCFMNUMBER_FN_SHIFT (0U) +#define USBFSH_HCFMNUMBER_FN(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMNUMBER_FN_SHIFT)) & USBFSH_HCFMNUMBER_FN_MASK) +/*! @} */ + +/*! @name HCPERIODICSTART - Contains a programmable 14-bit value which determines the earliest time HC should start processing a periodic list */ +/*! @{ */ +#define USBFSH_HCPERIODICSTART_PS_MASK (0x3FFFU) +#define USBFSH_HCPERIODICSTART_PS_SHIFT (0U) +#define USBFSH_HCPERIODICSTART_PS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCPERIODICSTART_PS_SHIFT)) & USBFSH_HCPERIODICSTART_PS_MASK) +/*! @} */ + +/*! @name HCLSTHRESHOLD - Contains 11-bit value which is used by the HC to determine whether to commit to transfer a maximum of 8-byte LS packet before EOF */ +/*! @{ */ +#define USBFSH_HCLSTHRESHOLD_LST_MASK (0xFFFU) +#define USBFSH_HCLSTHRESHOLD_LST_SHIFT (0U) +#define USBFSH_HCLSTHRESHOLD_LST(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCLSTHRESHOLD_LST_SHIFT)) & USBFSH_HCLSTHRESHOLD_LST_MASK) +/*! @} */ + +/*! @name HCRHDESCRIPTORA - First of the two registers which describes the characteristics of the root hub */ +/*! @{ */ +#define USBFSH_HCRHDESCRIPTORA_NDP_MASK (0xFFU) +#define USBFSH_HCRHDESCRIPTORA_NDP_SHIFT (0U) +#define USBFSH_HCRHDESCRIPTORA_NDP(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NDP_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NDP_MASK) +#define USBFSH_HCRHDESCRIPTORA_PSM_MASK (0x100U) +#define USBFSH_HCRHDESCRIPTORA_PSM_SHIFT (8U) +#define USBFSH_HCRHDESCRIPTORA_PSM(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_PSM_SHIFT)) & USBFSH_HCRHDESCRIPTORA_PSM_MASK) +#define USBFSH_HCRHDESCRIPTORA_NPS_MASK (0x200U) +#define USBFSH_HCRHDESCRIPTORA_NPS_SHIFT (9U) +#define USBFSH_HCRHDESCRIPTORA_NPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NPS_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NPS_MASK) +#define USBFSH_HCRHDESCRIPTORA_DT_MASK (0x400U) +#define USBFSH_HCRHDESCRIPTORA_DT_SHIFT (10U) +#define USBFSH_HCRHDESCRIPTORA_DT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_DT_SHIFT)) & USBFSH_HCRHDESCRIPTORA_DT_MASK) +#define USBFSH_HCRHDESCRIPTORA_OCPM_MASK (0x800U) +#define USBFSH_HCRHDESCRIPTORA_OCPM_SHIFT (11U) +#define USBFSH_HCRHDESCRIPTORA_OCPM(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_OCPM_SHIFT)) & USBFSH_HCRHDESCRIPTORA_OCPM_MASK) +#define USBFSH_HCRHDESCRIPTORA_NOCP_MASK (0x1000U) +#define USBFSH_HCRHDESCRIPTORA_NOCP_SHIFT (12U) +#define USBFSH_HCRHDESCRIPTORA_NOCP(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NOCP_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NOCP_MASK) +#define USBFSH_HCRHDESCRIPTORA_POTPGT_MASK (0xFF000000U) +#define USBFSH_HCRHDESCRIPTORA_POTPGT_SHIFT (24U) +#define USBFSH_HCRHDESCRIPTORA_POTPGT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_POTPGT_SHIFT)) & USBFSH_HCRHDESCRIPTORA_POTPGT_MASK) +/*! @} */ + +/*! @name HCRHDESCRIPTORB - Second of the two registers which describes the characteristics of the Root Hub */ +/*! @{ */ +#define USBFSH_HCRHDESCRIPTORB_DR_MASK (0xFFFFU) +#define USBFSH_HCRHDESCRIPTORB_DR_SHIFT (0U) +#define USBFSH_HCRHDESCRIPTORB_DR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORB_DR_SHIFT)) & USBFSH_HCRHDESCRIPTORB_DR_MASK) +#define USBFSH_HCRHDESCRIPTORB_PPCM_MASK (0xFFFF0000U) +#define USBFSH_HCRHDESCRIPTORB_PPCM_SHIFT (16U) +#define USBFSH_HCRHDESCRIPTORB_PPCM(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORB_PPCM_SHIFT)) & USBFSH_HCRHDESCRIPTORB_PPCM_MASK) +/*! @} */ + +/*! @name HCRHSTATUS - This register is divided into two parts */ +/*! @{ */ +#define USBFSH_HCRHSTATUS_LPS_MASK (0x1U) +#define USBFSH_HCRHSTATUS_LPS_SHIFT (0U) +#define USBFSH_HCRHSTATUS_LPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_LPS_SHIFT)) & USBFSH_HCRHSTATUS_LPS_MASK) +#define USBFSH_HCRHSTATUS_OCI_MASK (0x2U) +#define USBFSH_HCRHSTATUS_OCI_SHIFT (1U) +#define USBFSH_HCRHSTATUS_OCI(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_OCI_SHIFT)) & USBFSH_HCRHSTATUS_OCI_MASK) +#define USBFSH_HCRHSTATUS_DRWE_MASK (0x8000U) +#define USBFSH_HCRHSTATUS_DRWE_SHIFT (15U) +#define USBFSH_HCRHSTATUS_DRWE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_DRWE_SHIFT)) & USBFSH_HCRHSTATUS_DRWE_MASK) +#define USBFSH_HCRHSTATUS_LPSC_MASK (0x10000U) +#define USBFSH_HCRHSTATUS_LPSC_SHIFT (16U) +#define USBFSH_HCRHSTATUS_LPSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_LPSC_SHIFT)) & USBFSH_HCRHSTATUS_LPSC_MASK) +#define USBFSH_HCRHSTATUS_OCIC_MASK (0x20000U) +#define USBFSH_HCRHSTATUS_OCIC_SHIFT (17U) +#define USBFSH_HCRHSTATUS_OCIC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_OCIC_SHIFT)) & USBFSH_HCRHSTATUS_OCIC_MASK) +#define USBFSH_HCRHSTATUS_CRWE_MASK (0x80000000U) +#define USBFSH_HCRHSTATUS_CRWE_SHIFT (31U) +#define USBFSH_HCRHSTATUS_CRWE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_CRWE_SHIFT)) & USBFSH_HCRHSTATUS_CRWE_MASK) +/*! @} */ + +/*! @name HCRHPORTSTATUS - Controls and reports the port events on a per-port basis */ +/*! @{ */ +#define USBFSH_HCRHPORTSTATUS_CCS_MASK (0x1U) +#define USBFSH_HCRHPORTSTATUS_CCS_SHIFT (0U) +#define USBFSH_HCRHPORTSTATUS_CCS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_CCS_SHIFT)) & USBFSH_HCRHPORTSTATUS_CCS_MASK) +#define USBFSH_HCRHPORTSTATUS_PES_MASK (0x2U) +#define USBFSH_HCRHPORTSTATUS_PES_SHIFT (1U) +#define USBFSH_HCRHPORTSTATUS_PES(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PES_SHIFT)) & USBFSH_HCRHPORTSTATUS_PES_MASK) +#define USBFSH_HCRHPORTSTATUS_PSS_MASK (0x4U) +#define USBFSH_HCRHPORTSTATUS_PSS_SHIFT (2U) +#define USBFSH_HCRHPORTSTATUS_PSS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PSS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PSS_MASK) +#define USBFSH_HCRHPORTSTATUS_POCI_MASK (0x8U) +#define USBFSH_HCRHPORTSTATUS_POCI_SHIFT (3U) +#define USBFSH_HCRHPORTSTATUS_POCI(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_POCI_SHIFT)) & USBFSH_HCRHPORTSTATUS_POCI_MASK) +#define USBFSH_HCRHPORTSTATUS_PRS_MASK (0x10U) +#define USBFSH_HCRHPORTSTATUS_PRS_SHIFT (4U) +#define USBFSH_HCRHPORTSTATUS_PRS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PRS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PRS_MASK) +#define USBFSH_HCRHPORTSTATUS_PPS_MASK (0x100U) +#define USBFSH_HCRHPORTSTATUS_PPS_SHIFT (8U) +#define USBFSH_HCRHPORTSTATUS_PPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PPS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PPS_MASK) +#define USBFSH_HCRHPORTSTATUS_LSDA_MASK (0x200U) +#define USBFSH_HCRHPORTSTATUS_LSDA_SHIFT (9U) +#define USBFSH_HCRHPORTSTATUS_LSDA(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_LSDA_SHIFT)) & USBFSH_HCRHPORTSTATUS_LSDA_MASK) +#define USBFSH_HCRHPORTSTATUS_CSC_MASK (0x10000U) +#define USBFSH_HCRHPORTSTATUS_CSC_SHIFT (16U) +#define USBFSH_HCRHPORTSTATUS_CSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_CSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_CSC_MASK) +#define USBFSH_HCRHPORTSTATUS_PESC_MASK (0x20000U) +#define USBFSH_HCRHPORTSTATUS_PESC_SHIFT (17U) +#define USBFSH_HCRHPORTSTATUS_PESC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PESC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PESC_MASK) +#define USBFSH_HCRHPORTSTATUS_PSSC_MASK (0x40000U) +#define USBFSH_HCRHPORTSTATUS_PSSC_SHIFT (18U) +#define USBFSH_HCRHPORTSTATUS_PSSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PSSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PSSC_MASK) +#define USBFSH_HCRHPORTSTATUS_OCIC_MASK (0x80000U) +#define USBFSH_HCRHPORTSTATUS_OCIC_SHIFT (19U) +#define USBFSH_HCRHPORTSTATUS_OCIC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_OCIC_SHIFT)) & USBFSH_HCRHPORTSTATUS_OCIC_MASK) +#define USBFSH_HCRHPORTSTATUS_PRSC_MASK (0x100000U) +#define USBFSH_HCRHPORTSTATUS_PRSC_SHIFT (20U) +#define USBFSH_HCRHPORTSTATUS_PRSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PRSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PRSC_MASK) +/*! @} */ + +/*! @name PORTMODE - Controls the port if it is attached to the host block or the device block */ +/*! @{ */ +#define USBFSH_PORTMODE_ID_MASK (0x1U) +#define USBFSH_PORTMODE_ID_SHIFT (0U) +#define USBFSH_PORTMODE_ID(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_ID_SHIFT)) & USBFSH_PORTMODE_ID_MASK) +#define USBFSH_PORTMODE_ID_EN_MASK (0x100U) +#define USBFSH_PORTMODE_ID_EN_SHIFT (8U) +#define USBFSH_PORTMODE_ID_EN(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_ID_EN_SHIFT)) & USBFSH_PORTMODE_ID_EN_MASK) +#define USBFSH_PORTMODE_DEV_ENABLE_MASK (0x10000U) +#define USBFSH_PORTMODE_DEV_ENABLE_SHIFT (16U) +#define USBFSH_PORTMODE_DEV_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_DEV_ENABLE_SHIFT)) & USBFSH_PORTMODE_DEV_ENABLE_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group USBFSH_Register_Masks */ + + +/* USBFSH - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral USBFSH base address */ + #define USBFSH_BASE (0x500A2000u) + /** Peripheral USBFSH base address */ + #define USBFSH_BASE_NS (0x400A2000u) + /** Peripheral USBFSH base pointer */ + #define USBFSH ((USBFSH_Type *)USBFSH_BASE) + /** Peripheral USBFSH base pointer */ + #define USBFSH_NS ((USBFSH_Type *)USBFSH_BASE_NS) + /** Array initializer of USBFSH peripheral base addresses */ + #define USBFSH_BASE_ADDRS { USBFSH_BASE } + /** Array initializer of USBFSH peripheral base pointers */ + #define USBFSH_BASE_PTRS { USBFSH } + /** Array initializer of USBFSH peripheral base addresses */ + #define USBFSH_BASE_ADDRS_NS { USBFSH_BASE_NS } + /** Array initializer of USBFSH peripheral base pointers */ + #define USBFSH_BASE_PTRS_NS { USBFSH_NS } +#else + /** Peripheral USBFSH base address */ + #define USBFSH_BASE (0x400A2000u) + /** Peripheral USBFSH base pointer */ + #define USBFSH ((USBFSH_Type *)USBFSH_BASE) + /** Array initializer of USBFSH peripheral base addresses */ + #define USBFSH_BASE_ADDRS { USBFSH_BASE } + /** Array initializer of USBFSH peripheral base pointers */ + #define USBFSH_BASE_PTRS { USBFSH } +#endif +/** Interrupt vectors for the USBFSH peripheral type */ +#define USBFSH_IRQS { USB0_IRQn } +#define USBFSH_NEEDCLK_IRQS { USB0_NEEDCLK_IRQn } + +/*! + * @} + */ /* end of group USBFSH_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USBHSD Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBHSD_Peripheral_Access_Layer USBHSD Peripheral Access Layer + * @{ + */ + +/** USBHSD - Register Layout Typedef */ +typedef struct { + __IO uint32_t DEVCMDSTAT; /**< USB Device Command/Status register, offset: 0x0 */ + __I uint32_t INFO; /**< USB Info register, offset: 0x4 */ + __IO uint32_t EPLISTSTART; /**< USB EP Command/Status List start address, offset: 0x8 */ + __IO uint32_t DATABUFSTART; /**< USB Data buffer start address, offset: 0xC */ + __IO uint32_t LPM; /**< USB Link Power Management register, offset: 0x10 */ + __IO uint32_t EPSKIP; /**< USB Endpoint skip, offset: 0x14 */ + __IO uint32_t EPINUSE; /**< USB Endpoint Buffer in use, offset: 0x18 */ + __IO uint32_t EPBUFCFG; /**< USB Endpoint Buffer Configuration register, offset: 0x1C */ + __IO uint32_t INTSTAT; /**< USB interrupt status register, offset: 0x20 */ + __IO uint32_t INTEN; /**< USB interrupt enable register, offset: 0x24 */ + __IO uint32_t INTSETSTAT; /**< USB set interrupt status register, offset: 0x28 */ + uint8_t RESERVED_0[8]; + __I uint32_t EPTOGGLE; /**< USB Endpoint toggle register, offset: 0x34 */ + uint8_t RESERVED_1[4]; + __IO uint32_t ULPIDEBUG; /**< UTMI/ULPI debug register, offset: 0x3C */ +} USBHSD_Type; + +/* ---------------------------------------------------------------------------- + -- USBHSD Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBHSD_Register_Masks USBHSD Register Masks + * @{ + */ + +/*! @name DEVCMDSTAT - USB Device Command/Status register */ +/*! @{ */ +#define USBHSD_DEVCMDSTAT_DEV_ADDR_MASK (0x7FU) +#define USBHSD_DEVCMDSTAT_DEV_ADDR_SHIFT (0U) +#define USBHSD_DEVCMDSTAT_DEV_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DEV_ADDR_SHIFT)) & USBHSD_DEVCMDSTAT_DEV_ADDR_MASK) +#define USBHSD_DEVCMDSTAT_DEV_EN_MASK (0x80U) +#define USBHSD_DEVCMDSTAT_DEV_EN_SHIFT (7U) +#define USBHSD_DEVCMDSTAT_DEV_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DEV_EN_SHIFT)) & USBHSD_DEVCMDSTAT_DEV_EN_MASK) +#define USBHSD_DEVCMDSTAT_SETUP_MASK (0x100U) +#define USBHSD_DEVCMDSTAT_SETUP_SHIFT (8U) +#define USBHSD_DEVCMDSTAT_SETUP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_SETUP_SHIFT)) & USBHSD_DEVCMDSTAT_SETUP_MASK) +#define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_MASK (0x200U) +#define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT (9U) +#define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT)) & USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_MASK) +#define USBHSD_DEVCMDSTAT_FORCE_VBUS_MASK (0x400U) +#define USBHSD_DEVCMDSTAT_FORCE_VBUS_SHIFT (10U) +#define USBHSD_DEVCMDSTAT_FORCE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_FORCE_VBUS_SHIFT)) & USBHSD_DEVCMDSTAT_FORCE_VBUS_MASK) +#define USBHSD_DEVCMDSTAT_LPM_SUP_MASK (0x800U) +#define USBHSD_DEVCMDSTAT_LPM_SUP_SHIFT (11U) +#define USBHSD_DEVCMDSTAT_LPM_SUP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_SUP_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_SUP_MASK) +#define USBHSD_DEVCMDSTAT_INTONNAK_AO_MASK (0x1000U) +#define USBHSD_DEVCMDSTAT_INTONNAK_AO_SHIFT (12U) +#define USBHSD_DEVCMDSTAT_INTONNAK_AO(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_AO_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_AO_MASK) +#define USBHSD_DEVCMDSTAT_INTONNAK_AI_MASK (0x2000U) +#define USBHSD_DEVCMDSTAT_INTONNAK_AI_SHIFT (13U) +#define USBHSD_DEVCMDSTAT_INTONNAK_AI(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_AI_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_AI_MASK) +#define USBHSD_DEVCMDSTAT_INTONNAK_CO_MASK (0x4000U) +#define USBHSD_DEVCMDSTAT_INTONNAK_CO_SHIFT (14U) +#define USBHSD_DEVCMDSTAT_INTONNAK_CO(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_CO_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_CO_MASK) +#define USBHSD_DEVCMDSTAT_INTONNAK_CI_MASK (0x8000U) +#define USBHSD_DEVCMDSTAT_INTONNAK_CI_SHIFT (15U) +#define USBHSD_DEVCMDSTAT_INTONNAK_CI(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_CI_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_CI_MASK) +#define USBHSD_DEVCMDSTAT_DCON_MASK (0x10000U) +#define USBHSD_DEVCMDSTAT_DCON_SHIFT (16U) +#define USBHSD_DEVCMDSTAT_DCON(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DCON_SHIFT)) & USBHSD_DEVCMDSTAT_DCON_MASK) +#define USBHSD_DEVCMDSTAT_DSUS_MASK (0x20000U) +#define USBHSD_DEVCMDSTAT_DSUS_SHIFT (17U) +#define USBHSD_DEVCMDSTAT_DSUS(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DSUS_SHIFT)) & USBHSD_DEVCMDSTAT_DSUS_MASK) +#define USBHSD_DEVCMDSTAT_LPM_SUS_MASK (0x80000U) +#define USBHSD_DEVCMDSTAT_LPM_SUS_SHIFT (19U) +#define USBHSD_DEVCMDSTAT_LPM_SUS(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_SUS_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_SUS_MASK) +#define USBHSD_DEVCMDSTAT_LPM_REWP_MASK (0x100000U) +#define USBHSD_DEVCMDSTAT_LPM_REWP_SHIFT (20U) +#define USBHSD_DEVCMDSTAT_LPM_REWP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_REWP_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_REWP_MASK) +#define USBHSD_DEVCMDSTAT_Speed_MASK (0xC00000U) +#define USBHSD_DEVCMDSTAT_Speed_SHIFT (22U) +#define USBHSD_DEVCMDSTAT_Speed(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_Speed_SHIFT)) & USBHSD_DEVCMDSTAT_Speed_MASK) +#define USBHSD_DEVCMDSTAT_DCON_C_MASK (0x1000000U) +#define USBHSD_DEVCMDSTAT_DCON_C_SHIFT (24U) +#define USBHSD_DEVCMDSTAT_DCON_C(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DCON_C_SHIFT)) & USBHSD_DEVCMDSTAT_DCON_C_MASK) +#define USBHSD_DEVCMDSTAT_DSUS_C_MASK (0x2000000U) +#define USBHSD_DEVCMDSTAT_DSUS_C_SHIFT (25U) +#define USBHSD_DEVCMDSTAT_DSUS_C(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DSUS_C_SHIFT)) & USBHSD_DEVCMDSTAT_DSUS_C_MASK) +#define USBHSD_DEVCMDSTAT_DRES_C_MASK (0x4000000U) +#define USBHSD_DEVCMDSTAT_DRES_C_SHIFT (26U) +#define USBHSD_DEVCMDSTAT_DRES_C(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DRES_C_SHIFT)) & USBHSD_DEVCMDSTAT_DRES_C_MASK) +#define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_MASK (0x10000000U) +#define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_SHIFT (28U) +#define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_SHIFT)) & USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_MASK) +#define USBHSD_DEVCMDSTAT_PHY_TEST_MODE_MASK (0xE0000000U) +#define USBHSD_DEVCMDSTAT_PHY_TEST_MODE_SHIFT (29U) +#define USBHSD_DEVCMDSTAT_PHY_TEST_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_PHY_TEST_MODE_SHIFT)) & USBHSD_DEVCMDSTAT_PHY_TEST_MODE_MASK) +/*! @} */ + +/*! @name INFO - USB Info register */ +/*! @{ */ +#define USBHSD_INFO_FRAME_NR_MASK (0x7FFU) +#define USBHSD_INFO_FRAME_NR_SHIFT (0U) +#define USBHSD_INFO_FRAME_NR(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_FRAME_NR_SHIFT)) & USBHSD_INFO_FRAME_NR_MASK) +#define USBHSD_INFO_ERR_CODE_MASK (0x7800U) +#define USBHSD_INFO_ERR_CODE_SHIFT (11U) +#define USBHSD_INFO_ERR_CODE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_ERR_CODE_SHIFT)) & USBHSD_INFO_ERR_CODE_MASK) +#define USBHSD_INFO_Minrev_MASK (0xFF0000U) +#define USBHSD_INFO_Minrev_SHIFT (16U) +#define USBHSD_INFO_Minrev(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_Minrev_SHIFT)) & USBHSD_INFO_Minrev_MASK) +#define USBHSD_INFO_Majrev_MASK (0xFF000000U) +#define USBHSD_INFO_Majrev_SHIFT (24U) +#define USBHSD_INFO_Majrev(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_Majrev_SHIFT)) & USBHSD_INFO_Majrev_MASK) +/*! @} */ + +/*! @name EPLISTSTART - USB EP Command/Status List start address */ +/*! @{ */ +#define USBHSD_EPLISTSTART_EP_LIST_PRG_MASK (0xFFF00U) +#define USBHSD_EPLISTSTART_EP_LIST_PRG_SHIFT (8U) +#define USBHSD_EPLISTSTART_EP_LIST_PRG(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPLISTSTART_EP_LIST_PRG_SHIFT)) & USBHSD_EPLISTSTART_EP_LIST_PRG_MASK) +#define USBHSD_EPLISTSTART_EP_LIST_FIXED_MASK (0xFFF00000U) +#define USBHSD_EPLISTSTART_EP_LIST_FIXED_SHIFT (20U) +#define USBHSD_EPLISTSTART_EP_LIST_FIXED(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPLISTSTART_EP_LIST_FIXED_SHIFT)) & USBHSD_EPLISTSTART_EP_LIST_FIXED_MASK) +/*! @} */ + +/*! @name DATABUFSTART - USB Data buffer start address */ +/*! @{ */ +#define USBHSD_DATABUFSTART_DA_BUF_MASK (0xFFFFFFFFU) +#define USBHSD_DATABUFSTART_DA_BUF_SHIFT (0U) +#define USBHSD_DATABUFSTART_DA_BUF(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DATABUFSTART_DA_BUF_SHIFT)) & USBHSD_DATABUFSTART_DA_BUF_MASK) +/*! @} */ + +/*! @name LPM - USB Link Power Management register */ +/*! @{ */ +#define USBHSD_LPM_HIRD_HW_MASK (0xFU) +#define USBHSD_LPM_HIRD_HW_SHIFT (0U) +#define USBHSD_LPM_HIRD_HW(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_HIRD_HW_SHIFT)) & USBHSD_LPM_HIRD_HW_MASK) +#define USBHSD_LPM_HIRD_SW_MASK (0xF0U) +#define USBHSD_LPM_HIRD_SW_SHIFT (4U) +#define USBHSD_LPM_HIRD_SW(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_HIRD_SW_SHIFT)) & USBHSD_LPM_HIRD_SW_MASK) +#define USBHSD_LPM_DATA_PENDING_MASK (0x100U) +#define USBHSD_LPM_DATA_PENDING_SHIFT (8U) +#define USBHSD_LPM_DATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_DATA_PENDING_SHIFT)) & USBHSD_LPM_DATA_PENDING_MASK) +/*! @} */ + +/*! @name EPSKIP - USB Endpoint skip */ +/*! @{ */ +#define USBHSD_EPSKIP_SKIP_MASK (0xFFFU) +#define USBHSD_EPSKIP_SKIP_SHIFT (0U) +#define USBHSD_EPSKIP_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPSKIP_SKIP_SHIFT)) & USBHSD_EPSKIP_SKIP_MASK) +/*! @} */ + +/*! @name EPINUSE - USB Endpoint Buffer in use */ +/*! @{ */ +#define USBHSD_EPINUSE_BUF_MASK (0xFFCU) +#define USBHSD_EPINUSE_BUF_SHIFT (2U) +#define USBHSD_EPINUSE_BUF(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPINUSE_BUF_SHIFT)) & USBHSD_EPINUSE_BUF_MASK) +/*! @} */ + +/*! @name EPBUFCFG - USB Endpoint Buffer Configuration register */ +/*! @{ */ +#define USBHSD_EPBUFCFG_BUF_SB_MASK (0xFFCU) +#define USBHSD_EPBUFCFG_BUF_SB_SHIFT (2U) +#define USBHSD_EPBUFCFG_BUF_SB(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPBUFCFG_BUF_SB_SHIFT)) & USBHSD_EPBUFCFG_BUF_SB_MASK) +/*! @} */ + +/*! @name INTSTAT - USB interrupt status register */ +/*! @{ */ +#define USBHSD_INTSTAT_EP0OUT_MASK (0x1U) +#define USBHSD_INTSTAT_EP0OUT_SHIFT (0U) +#define USBHSD_INTSTAT_EP0OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP0OUT_SHIFT)) & USBHSD_INTSTAT_EP0OUT_MASK) +#define USBHSD_INTSTAT_EP0IN_MASK (0x2U) +#define USBHSD_INTSTAT_EP0IN_SHIFT (1U) +#define USBHSD_INTSTAT_EP0IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP0IN_SHIFT)) & USBHSD_INTSTAT_EP0IN_MASK) +#define USBHSD_INTSTAT_EP1OUT_MASK (0x4U) +#define USBHSD_INTSTAT_EP1OUT_SHIFT (2U) +#define USBHSD_INTSTAT_EP1OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP1OUT_SHIFT)) & USBHSD_INTSTAT_EP1OUT_MASK) +#define USBHSD_INTSTAT_EP1IN_MASK (0x8U) +#define USBHSD_INTSTAT_EP1IN_SHIFT (3U) +#define USBHSD_INTSTAT_EP1IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP1IN_SHIFT)) & USBHSD_INTSTAT_EP1IN_MASK) +#define USBHSD_INTSTAT_EP2OUT_MASK (0x10U) +#define USBHSD_INTSTAT_EP2OUT_SHIFT (4U) +#define USBHSD_INTSTAT_EP2OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP2OUT_SHIFT)) & USBHSD_INTSTAT_EP2OUT_MASK) +#define USBHSD_INTSTAT_EP2IN_MASK (0x20U) +#define USBHSD_INTSTAT_EP2IN_SHIFT (5U) +#define USBHSD_INTSTAT_EP2IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP2IN_SHIFT)) & USBHSD_INTSTAT_EP2IN_MASK) +#define USBHSD_INTSTAT_EP3OUT_MASK (0x40U) +#define USBHSD_INTSTAT_EP3OUT_SHIFT (6U) +#define USBHSD_INTSTAT_EP3OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP3OUT_SHIFT)) & USBHSD_INTSTAT_EP3OUT_MASK) +#define USBHSD_INTSTAT_EP3IN_MASK (0x80U) +#define USBHSD_INTSTAT_EP3IN_SHIFT (7U) +#define USBHSD_INTSTAT_EP3IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP3IN_SHIFT)) & USBHSD_INTSTAT_EP3IN_MASK) +#define USBHSD_INTSTAT_EP4OUT_MASK (0x100U) +#define USBHSD_INTSTAT_EP4OUT_SHIFT (8U) +#define USBHSD_INTSTAT_EP4OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP4OUT_SHIFT)) & USBHSD_INTSTAT_EP4OUT_MASK) +#define USBHSD_INTSTAT_EP4IN_MASK (0x200U) +#define USBHSD_INTSTAT_EP4IN_SHIFT (9U) +#define USBHSD_INTSTAT_EP4IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP4IN_SHIFT)) & USBHSD_INTSTAT_EP4IN_MASK) +#define USBHSD_INTSTAT_EP5OUT_MASK (0x400U) +#define USBHSD_INTSTAT_EP5OUT_SHIFT (10U) +#define USBHSD_INTSTAT_EP5OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP5OUT_SHIFT)) & USBHSD_INTSTAT_EP5OUT_MASK) +#define USBHSD_INTSTAT_EP5IN_MASK (0x800U) +#define USBHSD_INTSTAT_EP5IN_SHIFT (11U) +#define USBHSD_INTSTAT_EP5IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP5IN_SHIFT)) & USBHSD_INTSTAT_EP5IN_MASK) +#define USBHSD_INTSTAT_FRAME_INT_MASK (0x40000000U) +#define USBHSD_INTSTAT_FRAME_INT_SHIFT (30U) +#define USBHSD_INTSTAT_FRAME_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_FRAME_INT_SHIFT)) & USBHSD_INTSTAT_FRAME_INT_MASK) +#define USBHSD_INTSTAT_DEV_INT_MASK (0x80000000U) +#define USBHSD_INTSTAT_DEV_INT_SHIFT (31U) +#define USBHSD_INTSTAT_DEV_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_DEV_INT_SHIFT)) & USBHSD_INTSTAT_DEV_INT_MASK) +/*! @} */ + +/*! @name INTEN - USB interrupt enable register */ +/*! @{ */ +#define USBHSD_INTEN_EP_INT_EN_MASK (0xFFFU) +#define USBHSD_INTEN_EP_INT_EN_SHIFT (0U) +#define USBHSD_INTEN_EP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_EP_INT_EN_SHIFT)) & USBHSD_INTEN_EP_INT_EN_MASK) +#define USBHSD_INTEN_FRAME_INT_EN_MASK (0x40000000U) +#define USBHSD_INTEN_FRAME_INT_EN_SHIFT (30U) +#define USBHSD_INTEN_FRAME_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_FRAME_INT_EN_SHIFT)) & USBHSD_INTEN_FRAME_INT_EN_MASK) +#define USBHSD_INTEN_DEV_INT_EN_MASK (0x80000000U) +#define USBHSD_INTEN_DEV_INT_EN_SHIFT (31U) +#define USBHSD_INTEN_DEV_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_DEV_INT_EN_SHIFT)) & USBHSD_INTEN_DEV_INT_EN_MASK) +/*! @} */ + +/*! @name INTSETSTAT - USB set interrupt status register */ +/*! @{ */ +#define USBHSD_INTSETSTAT_EP_SET_INT_MASK (0xFFFU) +#define USBHSD_INTSETSTAT_EP_SET_INT_SHIFT (0U) +#define USBHSD_INTSETSTAT_EP_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_EP_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_EP_SET_INT_MASK) +#define USBHSD_INTSETSTAT_FRAME_SET_INT_MASK (0x40000000U) +#define USBHSD_INTSETSTAT_FRAME_SET_INT_SHIFT (30U) +#define USBHSD_INTSETSTAT_FRAME_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_FRAME_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_FRAME_SET_INT_MASK) +#define USBHSD_INTSETSTAT_DEV_SET_INT_MASK (0x80000000U) +#define USBHSD_INTSETSTAT_DEV_SET_INT_SHIFT (31U) +#define USBHSD_INTSETSTAT_DEV_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_DEV_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_DEV_SET_INT_MASK) +/*! @} */ + +/*! @name EPTOGGLE - USB Endpoint toggle register */ +/*! @{ */ +#define USBHSD_EPTOGGLE_TOGGLE_MASK (0x3FFFFFFFU) +#define USBHSD_EPTOGGLE_TOGGLE_SHIFT (0U) +#define USBHSD_EPTOGGLE_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPTOGGLE_TOGGLE_SHIFT)) & USBHSD_EPTOGGLE_TOGGLE_MASK) +/*! @} */ + +/*! @name ULPIDEBUG - UTMI/ULPI debug register */ +/*! @{ */ +#define USBHSD_ULPIDEBUG_PHY_ADDR_MASK (0xFFU) +#define USBHSD_ULPIDEBUG_PHY_ADDR_SHIFT (0U) +#define USBHSD_ULPIDEBUG_PHY_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_ADDR_SHIFT)) & USBHSD_ULPIDEBUG_PHY_ADDR_MASK) +#define USBHSD_ULPIDEBUG_PHY_WDATA_MASK (0xFF00U) +#define USBHSD_ULPIDEBUG_PHY_WDATA_SHIFT (8U) +#define USBHSD_ULPIDEBUG_PHY_WDATA(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_WDATA_SHIFT)) & USBHSD_ULPIDEBUG_PHY_WDATA_MASK) +#define USBHSD_ULPIDEBUG_PHY_RDATA_MASK (0xFF0000U) +#define USBHSD_ULPIDEBUG_PHY_RDATA_SHIFT (16U) +#define USBHSD_ULPIDEBUG_PHY_RDATA(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_RDATA_SHIFT)) & USBHSD_ULPIDEBUG_PHY_RDATA_MASK) +#define USBHSD_ULPIDEBUG_PHY_RW_MASK (0x1000000U) +#define USBHSD_ULPIDEBUG_PHY_RW_SHIFT (24U) +#define USBHSD_ULPIDEBUG_PHY_RW(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_RW_SHIFT)) & USBHSD_ULPIDEBUG_PHY_RW_MASK) +#define USBHSD_ULPIDEBUG_PHY_ACCESS_MASK (0x2000000U) +#define USBHSD_ULPIDEBUG_PHY_ACCESS_SHIFT (25U) +#define USBHSD_ULPIDEBUG_PHY_ACCESS(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_ACCESS_SHIFT)) & USBHSD_ULPIDEBUG_PHY_ACCESS_MASK) +#define USBHSD_ULPIDEBUG_PHY_MODE_MASK (0x80000000U) +#define USBHSD_ULPIDEBUG_PHY_MODE_SHIFT (31U) +#define USBHSD_ULPIDEBUG_PHY_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_MODE_SHIFT)) & USBHSD_ULPIDEBUG_PHY_MODE_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group USBHSD_Register_Masks */ + + +/* USBHSD - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral USBHSD base address */ + #define USBHSD_BASE (0x50094000u) + /** Peripheral USBHSD base address */ + #define USBHSD_BASE_NS (0x40094000u) + /** Peripheral USBHSD base pointer */ + #define USBHSD ((USBHSD_Type *)USBHSD_BASE) + /** Peripheral USBHSD base pointer */ + #define USBHSD_NS ((USBHSD_Type *)USBHSD_BASE_NS) + /** Array initializer of USBHSD peripheral base addresses */ + #define USBHSD_BASE_ADDRS { USBHSD_BASE } + /** Array initializer of USBHSD peripheral base pointers */ + #define USBHSD_BASE_PTRS { USBHSD } + /** Array initializer of USBHSD peripheral base addresses */ + #define USBHSD_BASE_ADDRS_NS { USBHSD_BASE_NS } + /** Array initializer of USBHSD peripheral base pointers */ + #define USBHSD_BASE_PTRS_NS { USBHSD_NS } +#else + /** Peripheral USBHSD base address */ + #define USBHSD_BASE (0x40094000u) + /** Peripheral USBHSD base pointer */ + #define USBHSD ((USBHSD_Type *)USBHSD_BASE) + /** Array initializer of USBHSD peripheral base addresses */ + #define USBHSD_BASE_ADDRS { USBHSD_BASE } + /** Array initializer of USBHSD peripheral base pointers */ + #define USBHSD_BASE_PTRS { USBHSD } +#endif +/** Interrupt vectors for the USBHSD peripheral type */ +#define USBHSD_IRQS { USB1_IRQn } +#define USBHSD_NEEDCLK_IRQS { USB1_NEEDCLK_IRQn } + +/*! + * @} + */ /* end of group USBHSD_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USBHSH Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBHSH_Peripheral_Access_Layer USBHSH Peripheral Access Layer + * @{ + */ + +/** USBHSH - Register Layout Typedef */ +typedef struct { + __I uint32_t CAPLENGTH_CHIPID; /**< This register contains the offset value towards the start of the operational register space and the version number of the IP block, offset: 0x0 */ + __I uint32_t HCSPARAMS; /**< Host Controller Structural Parameters, offset: 0x4 */ + __I uint32_t HCCPARAMS; /**< Host Controller Capability Parameters, offset: 0x8 */ + __IO uint32_t FLADJ_FRINDEX; /**< Frame Length Adjustment, offset: 0xC */ + __IO uint32_t ATL_PTD_BASE_ADDR; /**< Memory base address where ATL PTD0 is stored, offset: 0x10 */ + __IO uint32_t ISO_PTD_BASE_ADDR; /**< Memory base address where ISO PTD0 is stored, offset: 0x14 */ + __IO uint32_t INT_PTD_BASE_ADDR; /**< Memory base address where INT PTD0 is stored, offset: 0x18 */ + __IO uint32_t DATA_PAYLOAD_BASE_ADDR; /**< Memory base address that indicates the start of the data payload buffers, offset: 0x1C */ + __IO uint32_t USBCMD; /**< USB Command register, offset: 0x20 */ + __IO uint32_t USBSTS; /**< USB Interrupt Status register, offset: 0x24 */ + __IO uint32_t USBINTR; /**< USB Interrupt Enable register, offset: 0x28 */ + __IO uint32_t PORTSC1; /**< Port Status and Control register, offset: 0x2C */ + __IO uint32_t ATL_PTD_DONE_MAP; /**< Done map for each ATL PTD, offset: 0x30 */ + __IO uint32_t ATL_PTD_SKIP_MAP; /**< Skip map for each ATL PTD, offset: 0x34 */ + __IO uint32_t ISO_PTD_DONE_MAP; /**< Done map for each ISO PTD, offset: 0x38 */ + __IO uint32_t ISO_PTD_SKIP_MAP; /**< Skip map for each ISO PTD, offset: 0x3C */ + __IO uint32_t INT_PTD_DONE_MAP; /**< Done map for each INT PTD, offset: 0x40 */ + __IO uint32_t INT_PTD_SKIP_MAP; /**< Skip map for each INT PTD, offset: 0x44 */ + __IO uint32_t LAST_PTD_INUSE; /**< Marks the last PTD in the list for ISO, INT and ATL, offset: 0x48 */ + __IO uint32_t UTMIPLUS_ULPI_DEBUG; /**< Register to read/write registers in the attached USB PHY, offset: 0x4C */ + __IO uint32_t PORTMODE; /**< Controls the port if it is attached to the host block or the device block, offset: 0x50 */ +} USBHSH_Type; + +/* ---------------------------------------------------------------------------- + -- USBHSH Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBHSH_Register_Masks USBHSH Register Masks + * @{ + */ + +/*! @name CAPLENGTH_CHIPID - This register contains the offset value towards the start of the operational register space and the version number of the IP block */ +/*! @{ */ +#define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_MASK (0xFFU) +#define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_SHIFT (0U) +#define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_SHIFT)) & USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_MASK) +#define USBHSH_CAPLENGTH_CHIPID_CHIPID_MASK (0xFFFF0000U) +#define USBHSH_CAPLENGTH_CHIPID_CHIPID_SHIFT (16U) +#define USBHSH_CAPLENGTH_CHIPID_CHIPID(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_CAPLENGTH_CHIPID_CHIPID_SHIFT)) & USBHSH_CAPLENGTH_CHIPID_CHIPID_MASK) +/*! @} */ + +/*! @name HCSPARAMS - Host Controller Structural Parameters */ +/*! @{ */ +#define USBHSH_HCSPARAMS_N_PORTS_MASK (0xFU) +#define USBHSH_HCSPARAMS_N_PORTS_SHIFT (0U) +#define USBHSH_HCSPARAMS_N_PORTS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_N_PORTS_SHIFT)) & USBHSH_HCSPARAMS_N_PORTS_MASK) +#define USBHSH_HCSPARAMS_PPC_MASK (0x10U) +#define USBHSH_HCSPARAMS_PPC_SHIFT (4U) +#define USBHSH_HCSPARAMS_PPC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_PPC_SHIFT)) & USBHSH_HCSPARAMS_PPC_MASK) +#define USBHSH_HCSPARAMS_P_INDICATOR_MASK (0x10000U) +#define USBHSH_HCSPARAMS_P_INDICATOR_SHIFT (16U) +#define USBHSH_HCSPARAMS_P_INDICATOR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_P_INDICATOR_SHIFT)) & USBHSH_HCSPARAMS_P_INDICATOR_MASK) +/*! @} */ + +/*! @name HCCPARAMS - Host Controller Capability Parameters */ +/*! @{ */ +#define USBHSH_HCCPARAMS_LPMC_MASK (0x20000U) +#define USBHSH_HCCPARAMS_LPMC_SHIFT (17U) +#define USBHSH_HCCPARAMS_LPMC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCCPARAMS_LPMC_SHIFT)) & USBHSH_HCCPARAMS_LPMC_MASK) +/*! @} */ + +/*! @name FLADJ_FRINDEX - Frame Length Adjustment */ +/*! @{ */ +#define USBHSH_FLADJ_FRINDEX_FLADJ_MASK (0x3FU) +#define USBHSH_FLADJ_FRINDEX_FLADJ_SHIFT (0U) +#define USBHSH_FLADJ_FRINDEX_FLADJ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_FLADJ_FRINDEX_FLADJ_SHIFT)) & USBHSH_FLADJ_FRINDEX_FLADJ_MASK) +#define USBHSH_FLADJ_FRINDEX_FRINDEX_MASK (0x3FFF0000U) +#define USBHSH_FLADJ_FRINDEX_FRINDEX_SHIFT (16U) +#define USBHSH_FLADJ_FRINDEX_FRINDEX(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_FLADJ_FRINDEX_FRINDEX_SHIFT)) & USBHSH_FLADJ_FRINDEX_FRINDEX_MASK) +/*! @} */ + +/*! @name ATL_PTD_BASE_ADDR - Memory base address where ATL PTD0 is stored */ +/*! @{ */ +#define USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR_MASK (0x1F0U) +#define USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR_SHIFT (4U) +#define USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR_SHIFT)) & USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR_MASK) +#define USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE_MASK (0xFFFFFE00U) +#define USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE_SHIFT (9U) +#define USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE_SHIFT)) & USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE_MASK) +/*! @} */ + +/*! @name ISO_PTD_BASE_ADDR - Memory base address where ISO PTD0 is stored */ +/*! @{ */ +#define USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST_MASK (0x3E0U) +#define USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST_SHIFT (5U) +#define USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST_SHIFT)) & USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST_MASK) +#define USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE_MASK (0xFFFFFC00U) +#define USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE_SHIFT (10U) +#define USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE_SHIFT)) & USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE_MASK) +/*! @} */ + +/*! @name INT_PTD_BASE_ADDR - Memory base address where INT PTD0 is stored */ +/*! @{ */ +#define USBHSH_INT_PTD_BASE_ADDR_INT_FIRST_MASK (0x3E0U) +#define USBHSH_INT_PTD_BASE_ADDR_INT_FIRST_SHIFT (5U) +#define USBHSH_INT_PTD_BASE_ADDR_INT_FIRST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INT_PTD_BASE_ADDR_INT_FIRST_SHIFT)) & USBHSH_INT_PTD_BASE_ADDR_INT_FIRST_MASK) +#define USBHSH_INT_PTD_BASE_ADDR_INT_BASE_MASK (0xFFFFFC00U) +#define USBHSH_INT_PTD_BASE_ADDR_INT_BASE_SHIFT (10U) +#define USBHSH_INT_PTD_BASE_ADDR_INT_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INT_PTD_BASE_ADDR_INT_BASE_SHIFT)) & USBHSH_INT_PTD_BASE_ADDR_INT_BASE_MASK) +/*! @} */ + +/*! @name DATA_PAYLOAD_BASE_ADDR - Memory base address that indicates the start of the data payload buffers */ +/*! @{ */ +#define USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE_MASK (0xFFFF0000U) +#define USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE_SHIFT (16U) +#define USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE_SHIFT)) & USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE_MASK) +/*! @} */ + +/*! @name USBCMD - USB Command register */ +/*! @{ */ +#define USBHSH_USBCMD_RS_MASK (0x1U) +#define USBHSH_USBCMD_RS_SHIFT (0U) +#define USBHSH_USBCMD_RS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_RS_SHIFT)) & USBHSH_USBCMD_RS_MASK) +#define USBHSH_USBCMD_HCRESET_MASK (0x2U) +#define USBHSH_USBCMD_HCRESET_SHIFT (1U) +#define USBHSH_USBCMD_HCRESET(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_HCRESET_SHIFT)) & USBHSH_USBCMD_HCRESET_MASK) +#define USBHSH_USBCMD_FLS_MASK (0xCU) +#define USBHSH_USBCMD_FLS_SHIFT (2U) +#define USBHSH_USBCMD_FLS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_FLS_SHIFT)) & USBHSH_USBCMD_FLS_MASK) +#define USBHSH_USBCMD_LHCR_MASK (0x80U) +#define USBHSH_USBCMD_LHCR_SHIFT (7U) +#define USBHSH_USBCMD_LHCR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_LHCR_SHIFT)) & USBHSH_USBCMD_LHCR_MASK) +#define USBHSH_USBCMD_ATL_EN_MASK (0x100U) +#define USBHSH_USBCMD_ATL_EN_SHIFT (8U) +#define USBHSH_USBCMD_ATL_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_ATL_EN_SHIFT)) & USBHSH_USBCMD_ATL_EN_MASK) +#define USBHSH_USBCMD_ISO_EN_MASK (0x200U) +#define USBHSH_USBCMD_ISO_EN_SHIFT (9U) +#define USBHSH_USBCMD_ISO_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_ISO_EN_SHIFT)) & USBHSH_USBCMD_ISO_EN_MASK) +#define USBHSH_USBCMD_INT_EN_MASK (0x400U) +#define USBHSH_USBCMD_INT_EN_SHIFT (10U) +#define USBHSH_USBCMD_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_INT_EN_SHIFT)) & USBHSH_USBCMD_INT_EN_MASK) +#define USBHSH_USBCMD_HIRD_MASK (0xF000000U) +#define USBHSH_USBCMD_HIRD_SHIFT (24U) +#define USBHSH_USBCMD_HIRD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_HIRD_SHIFT)) & USBHSH_USBCMD_HIRD_MASK) +#define USBHSH_USBCMD_LPM_RWU_MASK (0x10000000U) +#define USBHSH_USBCMD_LPM_RWU_SHIFT (28U) +#define USBHSH_USBCMD_LPM_RWU(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_LPM_RWU_SHIFT)) & USBHSH_USBCMD_LPM_RWU_MASK) +/*! @} */ + +/*! @name USBSTS - USB Interrupt Status register */ +/*! @{ */ +#define USBHSH_USBSTS_PCD_MASK (0x4U) +#define USBHSH_USBSTS_PCD_SHIFT (2U) +#define USBHSH_USBSTS_PCD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_PCD_SHIFT)) & USBHSH_USBSTS_PCD_MASK) +#define USBHSH_USBSTS_FLR_MASK (0x8U) +#define USBHSH_USBSTS_FLR_SHIFT (3U) +#define USBHSH_USBSTS_FLR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_FLR_SHIFT)) & USBHSH_USBSTS_FLR_MASK) +#define USBHSH_USBSTS_ATL_IRQ_MASK (0x10000U) +#define USBHSH_USBSTS_ATL_IRQ_SHIFT (16U) +#define USBHSH_USBSTS_ATL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_ATL_IRQ_SHIFT)) & USBHSH_USBSTS_ATL_IRQ_MASK) +#define USBHSH_USBSTS_ISO_IRQ_MASK (0x20000U) +#define USBHSH_USBSTS_ISO_IRQ_SHIFT (17U) +#define USBHSH_USBSTS_ISO_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_ISO_IRQ_SHIFT)) & USBHSH_USBSTS_ISO_IRQ_MASK) +#define USBHSH_USBSTS_INT_IRQ_MASK (0x40000U) +#define USBHSH_USBSTS_INT_IRQ_SHIFT (18U) +#define USBHSH_USBSTS_INT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_INT_IRQ_SHIFT)) & USBHSH_USBSTS_INT_IRQ_MASK) +#define USBHSH_USBSTS_SOF_IRQ_MASK (0x80000U) +#define USBHSH_USBSTS_SOF_IRQ_SHIFT (19U) +#define USBHSH_USBSTS_SOF_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_SOF_IRQ_SHIFT)) & USBHSH_USBSTS_SOF_IRQ_MASK) +/*! @} */ + +/*! @name USBINTR - USB Interrupt Enable register */ +/*! @{ */ +#define USBHSH_USBINTR_PCDE_MASK (0x4U) +#define USBHSH_USBINTR_PCDE_SHIFT (2U) +#define USBHSH_USBINTR_PCDE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_PCDE_SHIFT)) & USBHSH_USBINTR_PCDE_MASK) +#define USBHSH_USBINTR_FLRE_MASK (0x8U) +#define USBHSH_USBINTR_FLRE_SHIFT (3U) +#define USBHSH_USBINTR_FLRE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_FLRE_SHIFT)) & USBHSH_USBINTR_FLRE_MASK) +#define USBHSH_USBINTR_ATL_IRQ_E_MASK (0x10000U) +#define USBHSH_USBINTR_ATL_IRQ_E_SHIFT (16U) +#define USBHSH_USBINTR_ATL_IRQ_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_ATL_IRQ_E_SHIFT)) & USBHSH_USBINTR_ATL_IRQ_E_MASK) +#define USBHSH_USBINTR_ISO_IRQ_E_MASK (0x20000U) +#define USBHSH_USBINTR_ISO_IRQ_E_SHIFT (17U) +#define USBHSH_USBINTR_ISO_IRQ_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_ISO_IRQ_E_SHIFT)) & USBHSH_USBINTR_ISO_IRQ_E_MASK) +#define USBHSH_USBINTR_INT_IRQ_E_MASK (0x40000U) +#define USBHSH_USBINTR_INT_IRQ_E_SHIFT (18U) +#define USBHSH_USBINTR_INT_IRQ_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_INT_IRQ_E_SHIFT)) & USBHSH_USBINTR_INT_IRQ_E_MASK) +#define USBHSH_USBINTR_SOF_E_MASK (0x80000U) +#define USBHSH_USBINTR_SOF_E_SHIFT (19U) +#define USBHSH_USBINTR_SOF_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_SOF_E_SHIFT)) & USBHSH_USBINTR_SOF_E_MASK) +/*! @} */ + +/*! @name PORTSC1 - Port Status and Control register */ +/*! @{ */ +#define USBHSH_PORTSC1_CCS_MASK (0x1U) +#define USBHSH_PORTSC1_CCS_SHIFT (0U) +#define USBHSH_PORTSC1_CCS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_CCS_SHIFT)) & USBHSH_PORTSC1_CCS_MASK) +#define USBHSH_PORTSC1_CSC_MASK (0x2U) +#define USBHSH_PORTSC1_CSC_SHIFT (1U) +#define USBHSH_PORTSC1_CSC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_CSC_SHIFT)) & USBHSH_PORTSC1_CSC_MASK) +#define USBHSH_PORTSC1_PED_MASK (0x4U) +#define USBHSH_PORTSC1_PED_SHIFT (2U) +#define USBHSH_PORTSC1_PED(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PED_SHIFT)) & USBHSH_PORTSC1_PED_MASK) +#define USBHSH_PORTSC1_PEDC_MASK (0x8U) +#define USBHSH_PORTSC1_PEDC_SHIFT (3U) +#define USBHSH_PORTSC1_PEDC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PEDC_SHIFT)) & USBHSH_PORTSC1_PEDC_MASK) +#define USBHSH_PORTSC1_OCA_MASK (0x10U) +#define USBHSH_PORTSC1_OCA_SHIFT (4U) +#define USBHSH_PORTSC1_OCA(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_OCA_SHIFT)) & USBHSH_PORTSC1_OCA_MASK) +#define USBHSH_PORTSC1_OCC_MASK (0x20U) +#define USBHSH_PORTSC1_OCC_SHIFT (5U) +#define USBHSH_PORTSC1_OCC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_OCC_SHIFT)) & USBHSH_PORTSC1_OCC_MASK) +#define USBHSH_PORTSC1_FPR_MASK (0x40U) +#define USBHSH_PORTSC1_FPR_SHIFT (6U) +#define USBHSH_PORTSC1_FPR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_FPR_SHIFT)) & USBHSH_PORTSC1_FPR_MASK) +#define USBHSH_PORTSC1_SUSP_MASK (0x80U) +#define USBHSH_PORTSC1_SUSP_SHIFT (7U) +#define USBHSH_PORTSC1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_SUSP_SHIFT)) & USBHSH_PORTSC1_SUSP_MASK) +#define USBHSH_PORTSC1_PR_MASK (0x100U) +#define USBHSH_PORTSC1_PR_SHIFT (8U) +#define USBHSH_PORTSC1_PR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PR_SHIFT)) & USBHSH_PORTSC1_PR_MASK) +#define USBHSH_PORTSC1_SUS_L1_MASK (0x200U) +#define USBHSH_PORTSC1_SUS_L1_SHIFT (9U) +#define USBHSH_PORTSC1_SUS_L1(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_SUS_L1_SHIFT)) & USBHSH_PORTSC1_SUS_L1_MASK) +#define USBHSH_PORTSC1_LS_MASK (0xC00U) +#define USBHSH_PORTSC1_LS_SHIFT (10U) +#define USBHSH_PORTSC1_LS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_LS_SHIFT)) & USBHSH_PORTSC1_LS_MASK) +#define USBHSH_PORTSC1_PP_MASK (0x1000U) +#define USBHSH_PORTSC1_PP_SHIFT (12U) +#define USBHSH_PORTSC1_PP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PP_SHIFT)) & USBHSH_PORTSC1_PP_MASK) +#define USBHSH_PORTSC1_PIC_MASK (0xC000U) +#define USBHSH_PORTSC1_PIC_SHIFT (14U) +#define USBHSH_PORTSC1_PIC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PIC_SHIFT)) & USBHSH_PORTSC1_PIC_MASK) +#define USBHSH_PORTSC1_PTC_MASK (0xF0000U) +#define USBHSH_PORTSC1_PTC_SHIFT (16U) +#define USBHSH_PORTSC1_PTC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PTC_SHIFT)) & USBHSH_PORTSC1_PTC_MASK) +#define USBHSH_PORTSC1_PSPD_MASK (0x300000U) +#define USBHSH_PORTSC1_PSPD_SHIFT (20U) +#define USBHSH_PORTSC1_PSPD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PSPD_SHIFT)) & USBHSH_PORTSC1_PSPD_MASK) +#define USBHSH_PORTSC1_WOO_MASK (0x400000U) +#define USBHSH_PORTSC1_WOO_SHIFT (22U) +#define USBHSH_PORTSC1_WOO(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_WOO_SHIFT)) & USBHSH_PORTSC1_WOO_MASK) +#define USBHSH_PORTSC1_SUS_STAT_MASK (0x1800000U) +#define USBHSH_PORTSC1_SUS_STAT_SHIFT (23U) +#define USBHSH_PORTSC1_SUS_STAT(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_SUS_STAT_SHIFT)) & USBHSH_PORTSC1_SUS_STAT_MASK) +#define USBHSH_PORTSC1_DEV_ADD_MASK (0xFE000000U) +#define USBHSH_PORTSC1_DEV_ADD_SHIFT (25U) +#define USBHSH_PORTSC1_DEV_ADD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_DEV_ADD_SHIFT)) & USBHSH_PORTSC1_DEV_ADD_MASK) +/*! @} */ + +/*! @name ATL_PTD_DONE_MAP - Done map for each ATL PTD */ +/*! @{ */ +#define USBHSH_ATL_PTD_DONE_MAP_ATL_DONE_MASK (0xFFFFFFFFU) +#define USBHSH_ATL_PTD_DONE_MAP_ATL_DONE_SHIFT (0U) +#define USBHSH_ATL_PTD_DONE_MAP_ATL_DONE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATL_PTD_DONE_MAP_ATL_DONE_SHIFT)) & USBHSH_ATL_PTD_DONE_MAP_ATL_DONE_MASK) +/*! @} */ + +/*! @name ATL_PTD_SKIP_MAP - Skip map for each ATL PTD */ +/*! @{ */ +#define USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP_MASK (0xFFFFFFFFU) +#define USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP_SHIFT (0U) +#define USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP_SHIFT)) & USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP_MASK) +/*! @} */ + +/*! @name ISO_PTD_DONE_MAP - Done map for each ISO PTD */ +/*! @{ */ +#define USBHSH_ISO_PTD_DONE_MAP_ISO_DONE_MASK (0xFFFFFFFFU) +#define USBHSH_ISO_PTD_DONE_MAP_ISO_DONE_SHIFT (0U) +#define USBHSH_ISO_PTD_DONE_MAP_ISO_DONE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISO_PTD_DONE_MAP_ISO_DONE_SHIFT)) & USBHSH_ISO_PTD_DONE_MAP_ISO_DONE_MASK) +/*! @} */ + +/*! @name ISO_PTD_SKIP_MAP - Skip map for each ISO PTD */ +/*! @{ */ +#define USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP_MASK (0xFFFFFFFFU) +#define USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP_SHIFT (0U) +#define USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP_SHIFT)) & USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP_MASK) +/*! @} */ + +/*! @name INT_PTD_DONE_MAP - Done map for each INT PTD */ +/*! @{ */ +#define USBHSH_INT_PTD_DONE_MAP_INT_DONE_MASK (0xFFFFFFFFU) +#define USBHSH_INT_PTD_DONE_MAP_INT_DONE_SHIFT (0U) +#define USBHSH_INT_PTD_DONE_MAP_INT_DONE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INT_PTD_DONE_MAP_INT_DONE_SHIFT)) & USBHSH_INT_PTD_DONE_MAP_INT_DONE_MASK) +/*! @} */ + +/*! @name INT_PTD_SKIP_MAP - Skip map for each INT PTD */ +/*! @{ */ +#define USBHSH_INT_PTD_SKIP_MAP_INT_SKIP_MASK (0xFFFFFFFFU) +#define USBHSH_INT_PTD_SKIP_MAP_INT_SKIP_SHIFT (0U) +#define USBHSH_INT_PTD_SKIP_MAP_INT_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INT_PTD_SKIP_MAP_INT_SKIP_SHIFT)) & USBHSH_INT_PTD_SKIP_MAP_INT_SKIP_MASK) +/*! @} */ + +/*! @name LAST_PTD_INUSE - Marks the last PTD in the list for ISO, INT and ATL */ +/*! @{ */ +#define USBHSH_LAST_PTD_INUSE_ATL_LAST_MASK (0x1FU) +#define USBHSH_LAST_PTD_INUSE_ATL_LAST_SHIFT (0U) +#define USBHSH_LAST_PTD_INUSE_ATL_LAST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_LAST_PTD_INUSE_ATL_LAST_SHIFT)) & USBHSH_LAST_PTD_INUSE_ATL_LAST_MASK) +#define USBHSH_LAST_PTD_INUSE_ISO_LAST_MASK (0x1F00U) +#define USBHSH_LAST_PTD_INUSE_ISO_LAST_SHIFT (8U) +#define USBHSH_LAST_PTD_INUSE_ISO_LAST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_LAST_PTD_INUSE_ISO_LAST_SHIFT)) & USBHSH_LAST_PTD_INUSE_ISO_LAST_MASK) +#define USBHSH_LAST_PTD_INUSE_INT_LAST_MASK (0x1F0000U) +#define USBHSH_LAST_PTD_INUSE_INT_LAST_SHIFT (16U) +#define USBHSH_LAST_PTD_INUSE_INT_LAST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_LAST_PTD_INUSE_INT_LAST_SHIFT)) & USBHSH_LAST_PTD_INUSE_INT_LAST_MASK) +/*! @} */ + +/*! @name UTMIPLUS_ULPI_DEBUG - Register to read/write registers in the attached USB PHY */ +/*! @{ */ +#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ADDR_MASK (0xFFU) +#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ADDR_SHIFT (0U) +#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ADDR_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ADDR_MASK) +#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_WDATA_MASK (0xFF00U) +#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_WDATA_SHIFT (8U) +#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_WDATA(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_WDATA_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_WDATA_MASK) +#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RDATA_MASK (0xFF0000U) +#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RDATA_SHIFT (16U) +#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RDATA(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RDATA_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RDATA_MASK) +#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RW_MASK (0x1000000U) +#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RW_SHIFT (24U) +#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RW(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RW_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RW_MASK) +#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ACCESS_MASK (0x2000000U) +#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ACCESS_SHIFT (25U) +#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ACCESS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ACCESS_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ACCESS_MASK) +#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_MODE_MASK (0x80000000U) +#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_MODE_SHIFT (31U) +#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_MODE_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_MODE_MASK) +/*! @} */ + +/*! @name PORTMODE - Controls the port if it is attached to the host block or the device block */ +/*! @{ */ +#define USBHSH_PORTMODE_ID0_MASK (0x1U) +#define USBHSH_PORTMODE_ID0_SHIFT (0U) +#define USBHSH_PORTMODE_ID0(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_ID0_SHIFT)) & USBHSH_PORTMODE_ID0_MASK) +#define USBHSH_PORTMODE_ID0_EN_MASK (0x100U) +#define USBHSH_PORTMODE_ID0_EN_SHIFT (8U) +#define USBHSH_PORTMODE_ID0_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_ID0_EN_SHIFT)) & USBHSH_PORTMODE_ID0_EN_MASK) +#define USBHSH_PORTMODE_DEV_ENABLE_MASK (0x10000U) +#define USBHSH_PORTMODE_DEV_ENABLE_SHIFT (16U) +#define USBHSH_PORTMODE_DEV_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_DEV_ENABLE_SHIFT)) & USBHSH_PORTMODE_DEV_ENABLE_MASK) +#define USBHSH_PORTMODE_SW_CTRL_PDCOM_MASK (0x40000U) +#define USBHSH_PORTMODE_SW_CTRL_PDCOM_SHIFT (18U) +#define USBHSH_PORTMODE_SW_CTRL_PDCOM(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_SW_CTRL_PDCOM_SHIFT)) & USBHSH_PORTMODE_SW_CTRL_PDCOM_MASK) +#define USBHSH_PORTMODE_SW_PDCOM_MASK (0x80000U) +#define USBHSH_PORTMODE_SW_PDCOM_SHIFT (19U) +#define USBHSH_PORTMODE_SW_PDCOM(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_SW_PDCOM_SHIFT)) & USBHSH_PORTMODE_SW_PDCOM_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group USBHSH_Register_Masks */ + + +/* USBHSH - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral USBHSH base address */ + #define USBHSH_BASE (0x500A3000u) + /** Peripheral USBHSH base address */ + #define USBHSH_BASE_NS (0x400A3000u) + /** Peripheral USBHSH base pointer */ + #define USBHSH ((USBHSH_Type *)USBHSH_BASE) + /** Peripheral USBHSH base pointer */ + #define USBHSH_NS ((USBHSH_Type *)USBHSH_BASE_NS) + /** Array initializer of USBHSH peripheral base addresses */ + #define USBHSH_BASE_ADDRS { USBHSH_BASE } + /** Array initializer of USBHSH peripheral base pointers */ + #define USBHSH_BASE_PTRS { USBHSH } + /** Array initializer of USBHSH peripheral base addresses */ + #define USBHSH_BASE_ADDRS_NS { USBHSH_BASE_NS } + /** Array initializer of USBHSH peripheral base pointers */ + #define USBHSH_BASE_PTRS_NS { USBHSH_NS } +#else + /** Peripheral USBHSH base address */ + #define USBHSH_BASE (0x400A3000u) + /** Peripheral USBHSH base pointer */ + #define USBHSH ((USBHSH_Type *)USBHSH_BASE) + /** Array initializer of USBHSH peripheral base addresses */ + #define USBHSH_BASE_ADDRS { USBHSH_BASE } + /** Array initializer of USBHSH peripheral base pointers */ + #define USBHSH_BASE_PTRS { USBHSH } +#endif +/** Interrupt vectors for the USBHSH peripheral type */ +#define USBHSH_IRQS { USB1_IRQn } +#define USBHSH_NEEDCLK_IRQS { USB1_NEEDCLK_IRQn } + +/*! + * @} + */ /* end of group USBHSH_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USBPHY Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBPHY_Peripheral_Access_Layer USBPHY Peripheral Access Layer + * @{ + */ + +/** USBPHY - Register Layout Typedef */ +typedef struct { + __IO uint32_t PWD; /**< USB PHY Power-Down Register, offset: 0x0 */ + __IO uint32_t PWD_SET; /**< USB PHY Power-Down Register, offset: 0x4 */ + __IO uint32_t PWD_CLR; /**< USB PHY Power-Down Register, offset: 0x8 */ + __IO uint32_t PWD_TOG; /**< USB PHY Power-Down Register, offset: 0xC */ + __IO uint32_t TX; /**< USB PHY Transmitter Control Register, offset: 0x10 */ + __IO uint32_t TX_SET; /**< USB PHY Transmitter Control Register, offset: 0x14 */ + __IO uint32_t TX_CLR; /**< USB PHY Transmitter Control Register, offset: 0x18 */ + __IO uint32_t TX_TOG; /**< USB PHY Transmitter Control Register, offset: 0x1C */ + __IO uint32_t RX; /**< USB PHY Receiver Control Register, offset: 0x20 */ + __IO uint32_t RX_SET; /**< USB PHY Receiver Control Register, offset: 0x24 */ + __IO uint32_t RX_CLR; /**< USB PHY Receiver Control Register, offset: 0x28 */ + __IO uint32_t RX_TOG; /**< USB PHY Receiver Control Register, offset: 0x2C */ + __IO uint32_t CTRL; /**< USB PHY General Control Register, offset: 0x30 */ + __IO uint32_t CTRL_SET; /**< USB PHY General Control Register, offset: 0x34 */ + __IO uint32_t CTRL_CLR; /**< USB PHY General Control Register, offset: 0x38 */ + __IO uint32_t CTRL_TOG; /**< USB PHY General Control Register, offset: 0x3C */ + __IO uint32_t STATUS; /**< USB PHY Status Register, offset: 0x40 */ + uint8_t RESERVED_0[12]; + __IO uint32_t DEBUG0; /**< USB PHY Debug Register 0, offset: 0x50 */ + __IO uint32_t DEBUG0_SET; /**< USB PHY Debug Register 0, offset: 0x54 */ + __IO uint32_t DEBUG0_CLR; /**< USB PHY Debug Register 0, offset: 0x58 */ + __IO uint32_t DEBUG0_TOG; /**< USB PHY Debug Register 0, offset: 0x5C */ + uint8_t RESERVED_1[16]; + __IO uint32_t DEBUG1; /**< UTMI Debug Status Register 1, offset: 0x70 */ + __IO uint32_t DEBUG1_SET; /**< UTMI Debug Status Register 1, offset: 0x74 */ + __IO uint32_t DEBUG1_CLR; /**< UTMI Debug Status Register 1, offset: 0x78 */ + __IO uint32_t DEBUG1_TOG; /**< UTMI Debug Status Register 1, offset: 0x7C */ + __I uint32_t VERSION; /**< UTMI RTL Version, offset: 0x80 */ + uint8_t RESERVED_2[28]; + __IO uint32_t PLL_SIC; /**< USB PHY PLL Control/Status Register, offset: 0xA0 */ + __IO uint32_t PLL_SIC_SET; /**< USB PHY PLL Control/Status Register, offset: 0xA4 */ + __IO uint32_t PLL_SIC_CLR; /**< USB PHY PLL Control/Status Register, offset: 0xA8 */ + __IO uint32_t PLL_SIC_TOG; /**< USB PHY PLL Control/Status Register, offset: 0xAC */ + uint8_t RESERVED_3[16]; + __IO uint32_t USB1_VBUS_DETECT; /**< USB PHY VBUS Detect Control Register, offset: 0xC0 */ + __IO uint32_t USB1_VBUS_DETECT_SET; /**< USB PHY VBUS Detect Control Register, offset: 0xC4 */ + __IO uint32_t USB1_VBUS_DETECT_CLR; /**< USB PHY VBUS Detect Control Register, offset: 0xC8 */ + __IO uint32_t USB1_VBUS_DETECT_TOG; /**< USB PHY VBUS Detect Control Register, offset: 0xCC */ + __I uint32_t USB1_VBUS_DET_STAT; /**< USB PHY VBUS Detector Status Register, offset: 0xD0 */ + uint8_t RESERVED_4[12]; + __IO uint32_t USB1_CHRG_DETECT; /**< USB PHY Charger Detect Control Register, offset: 0xE0 */ + __IO uint32_t USB1_CHRG_DETECT_SET; /**< USB PHY Charger Detect Control Register, offset: 0xE4 */ + __IO uint32_t USB1_CHRG_DETECT_CLR; /**< USB PHY Charger Detect Control Register, offset: 0xE8 */ + __IO uint32_t USB1_CHRG_DETECT_TOG; /**< USB PHY Charger Detect Control Register, offset: 0xEC */ + __I uint32_t USB1_CHRG_DET_STAT; /**< USB PHY Charger Detect Status Register, offset: 0xF0 */ + uint8_t RESERVED_5[12]; + __IO uint32_t ANACTRLr; /**< USB PHY Analog Control Register, offset: 0x100 */ + __IO uint32_t ANACTRL_SET; /**< USB PHY Analog Control Register, offset: 0x104 */ + __IO uint32_t ANACTRL_CLR; /**< USB PHY Analog Control Register, offset: 0x108 */ + __IO uint32_t ANACTRL_TOG; /**< USB PHY Analog Control Register, offset: 0x10C */ +} USBPHY_Type; + +/* ---------------------------------------------------------------------------- + -- USBPHY Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBPHY_Register_Masks USBPHY Register Masks + * @{ + */ + +/*! @name PWD - USB PHY Power-Down Register */ +/*! @{ */ +#define USBPHY_PWD_TXPWDFS_MASK (0x400U) +#define USBPHY_PWD_TXPWDFS_SHIFT (10U) +/*! TXPWDFS + * 0b0..Normal operation. + * 0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the + */ +#define USBPHY_PWD_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDFS_SHIFT)) & USBPHY_PWD_TXPWDFS_MASK) +#define USBPHY_PWD_TXPWDIBIAS_MASK (0x800U) +#define USBPHY_PWD_TXPWDIBIAS_SHIFT (11U) +/*! TXPWDIBIAS + * 0b0..Normal operation. + * 0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the + */ +#define USBPHY_PWD_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TXPWDIBIAS_MASK) +#define USBPHY_PWD_TXPWDV2I_MASK (0x1000U) +#define USBPHY_PWD_TXPWDV2I_SHIFT (12U) +/*! TXPWDV2I + * 0b0..Normal operation. + * 0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror + */ +#define USBPHY_PWD_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDV2I_SHIFT)) & USBPHY_PWD_TXPWDV2I_MASK) +#define USBPHY_PWD_RXPWDENV_MASK (0x20000U) +#define USBPHY_PWD_RXPWDENV_SHIFT (17U) +/*! RXPWDENV + * 0b0..Normal operation. + * 0b1..Power-down the USB high-speed receiver envelope detector (squelch signal) + */ +#define USBPHY_PWD_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDENV_SHIFT)) & USBPHY_PWD_RXPWDENV_MASK) +#define USBPHY_PWD_RXPWD1PT1_MASK (0x40000U) +#define USBPHY_PWD_RXPWD1PT1_SHIFT (18U) +/*! RXPWD1PT1 + * 0b0..Normal operation. + * 0b1..Power-down the USB full-speed differential receiver. + */ +#define USBPHY_PWD_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWD1PT1_SHIFT)) & USBPHY_PWD_RXPWD1PT1_MASK) +#define USBPHY_PWD_RXPWDDIFF_MASK (0x80000U) +#define USBPHY_PWD_RXPWDDIFF_SHIFT (19U) +/*! RXPWDDIFF + * 0b0..Normal operation. + * 0b1..Power-down the USB high-speed differential receive + */ +#define USBPHY_PWD_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDDIFF_SHIFT)) & USBPHY_PWD_RXPWDDIFF_MASK) +#define USBPHY_PWD_RXPWDRX_MASK (0x100000U) +#define USBPHY_PWD_RXPWDRX_SHIFT (20U) +/*! RXPWDRX + * 0b0..Normal operation. + * 0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver + */ +#define USBPHY_PWD_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDRX_SHIFT)) & USBPHY_PWD_RXPWDRX_MASK) +/*! @} */ + +/*! @name PWD_SET - USB PHY Power-Down Register */ +/*! @{ */ +#define USBPHY_PWD_SET_TXPWDFS_MASK (0x400U) +#define USBPHY_PWD_SET_TXPWDFS_SHIFT (10U) +/*! TXPWDFS + * 0b0..Normal operation. + * 0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the + */ +#define USBPHY_PWD_SET_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDFS_SHIFT)) & USBPHY_PWD_SET_TXPWDFS_MASK) +#define USBPHY_PWD_SET_TXPWDIBIAS_MASK (0x800U) +#define USBPHY_PWD_SET_TXPWDIBIAS_SHIFT (11U) +/*! TXPWDIBIAS + * 0b0..Normal operation. + * 0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the + */ +#define USBPHY_PWD_SET_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_SET_TXPWDIBIAS_MASK) +#define USBPHY_PWD_SET_TXPWDV2I_MASK (0x1000U) +#define USBPHY_PWD_SET_TXPWDV2I_SHIFT (12U) +/*! TXPWDV2I + * 0b0..Normal operation. + * 0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror + */ +#define USBPHY_PWD_SET_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDV2I_SHIFT)) & USBPHY_PWD_SET_TXPWDV2I_MASK) +#define USBPHY_PWD_SET_RXPWDENV_MASK (0x20000U) +#define USBPHY_PWD_SET_RXPWDENV_SHIFT (17U) +/*! RXPWDENV + * 0b0..Normal operation. + * 0b1..Power-down the USB high-speed receiver envelope detector (squelch signal) + */ +#define USBPHY_PWD_SET_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDENV_SHIFT)) & USBPHY_PWD_SET_RXPWDENV_MASK) +#define USBPHY_PWD_SET_RXPWD1PT1_MASK (0x40000U) +#define USBPHY_PWD_SET_RXPWD1PT1_SHIFT (18U) +/*! RXPWD1PT1 + * 0b0..Normal operation. + * 0b1..Power-down the USB full-speed differential receiver. + */ +#define USBPHY_PWD_SET_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWD1PT1_SHIFT)) & USBPHY_PWD_SET_RXPWD1PT1_MASK) +#define USBPHY_PWD_SET_RXPWDDIFF_MASK (0x80000U) +#define USBPHY_PWD_SET_RXPWDDIFF_SHIFT (19U) +/*! RXPWDDIFF + * 0b0..Normal operation. + * 0b1..Power-down the USB high-speed differential receive + */ +#define USBPHY_PWD_SET_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDDIFF_SHIFT)) & USBPHY_PWD_SET_RXPWDDIFF_MASK) +#define USBPHY_PWD_SET_RXPWDRX_MASK (0x100000U) +#define USBPHY_PWD_SET_RXPWDRX_SHIFT (20U) +/*! RXPWDRX + * 0b0..Normal operation. + * 0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver + */ +#define USBPHY_PWD_SET_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDRX_SHIFT)) & USBPHY_PWD_SET_RXPWDRX_MASK) +/*! @} */ + +/*! @name PWD_CLR - USB PHY Power-Down Register */ +/*! @{ */ +#define USBPHY_PWD_CLR_TXPWDFS_MASK (0x400U) +#define USBPHY_PWD_CLR_TXPWDFS_SHIFT (10U) +/*! TXPWDFS + * 0b0..Normal operation. + * 0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the + */ +#define USBPHY_PWD_CLR_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDFS_SHIFT)) & USBPHY_PWD_CLR_TXPWDFS_MASK) +#define USBPHY_PWD_CLR_TXPWDIBIAS_MASK (0x800U) +#define USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT (11U) +/*! TXPWDIBIAS + * 0b0..Normal operation. + * 0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the + */ +#define USBPHY_PWD_CLR_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_CLR_TXPWDIBIAS_MASK) +#define USBPHY_PWD_CLR_TXPWDV2I_MASK (0x1000U) +#define USBPHY_PWD_CLR_TXPWDV2I_SHIFT (12U) +/*! TXPWDV2I + * 0b0..Normal operation. + * 0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror + */ +#define USBPHY_PWD_CLR_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDV2I_SHIFT)) & USBPHY_PWD_CLR_TXPWDV2I_MASK) +#define USBPHY_PWD_CLR_RXPWDENV_MASK (0x20000U) +#define USBPHY_PWD_CLR_RXPWDENV_SHIFT (17U) +/*! RXPWDENV + * 0b0..Normal operation. + * 0b1..Power-down the USB high-speed receiver envelope detector (squelch signal) + */ +#define USBPHY_PWD_CLR_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDENV_SHIFT)) & USBPHY_PWD_CLR_RXPWDENV_MASK) +#define USBPHY_PWD_CLR_RXPWD1PT1_MASK (0x40000U) +#define USBPHY_PWD_CLR_RXPWD1PT1_SHIFT (18U) +/*! RXPWD1PT1 + * 0b0..Normal operation. + * 0b1..Power-down the USB full-speed differential receiver. + */ +#define USBPHY_PWD_CLR_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWD1PT1_SHIFT)) & USBPHY_PWD_CLR_RXPWD1PT1_MASK) +#define USBPHY_PWD_CLR_RXPWDDIFF_MASK (0x80000U) +#define USBPHY_PWD_CLR_RXPWDDIFF_SHIFT (19U) +/*! RXPWDDIFF + * 0b0..Normal operation. + * 0b1..Power-down the USB high-speed differential receive + */ +#define USBPHY_PWD_CLR_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDDIFF_SHIFT)) & USBPHY_PWD_CLR_RXPWDDIFF_MASK) +#define USBPHY_PWD_CLR_RXPWDRX_MASK (0x100000U) +#define USBPHY_PWD_CLR_RXPWDRX_SHIFT (20U) +/*! RXPWDRX + * 0b0..Normal operation. + * 0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver + */ +#define USBPHY_PWD_CLR_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDRX_SHIFT)) & USBPHY_PWD_CLR_RXPWDRX_MASK) +/*! @} */ + +/*! @name PWD_TOG - USB PHY Power-Down Register */ +/*! @{ */ +#define USBPHY_PWD_TOG_TXPWDFS_MASK (0x400U) +#define USBPHY_PWD_TOG_TXPWDFS_SHIFT (10U) +/*! TXPWDFS + * 0b0..Normal operation. + * 0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the + */ +#define USBPHY_PWD_TOG_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDFS_SHIFT)) & USBPHY_PWD_TOG_TXPWDFS_MASK) +#define USBPHY_PWD_TOG_TXPWDIBIAS_MASK (0x800U) +#define USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT (11U) +/*! TXPWDIBIAS + * 0b0..Normal operation. + * 0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the + */ +#define USBPHY_PWD_TOG_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TOG_TXPWDIBIAS_MASK) +#define USBPHY_PWD_TOG_TXPWDV2I_MASK (0x1000U) +#define USBPHY_PWD_TOG_TXPWDV2I_SHIFT (12U) +/*! TXPWDV2I + * 0b0..Normal operation. + * 0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror + */ +#define USBPHY_PWD_TOG_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDV2I_SHIFT)) & USBPHY_PWD_TOG_TXPWDV2I_MASK) +#define USBPHY_PWD_TOG_RXPWDENV_MASK (0x20000U) +#define USBPHY_PWD_TOG_RXPWDENV_SHIFT (17U) +/*! RXPWDENV + * 0b0..Normal operation. + * 0b1..Power-down the USB high-speed receiver envelope detector (squelch signal) + */ +#define USBPHY_PWD_TOG_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDENV_SHIFT)) & USBPHY_PWD_TOG_RXPWDENV_MASK) +#define USBPHY_PWD_TOG_RXPWD1PT1_MASK (0x40000U) +#define USBPHY_PWD_TOG_RXPWD1PT1_SHIFT (18U) +/*! RXPWD1PT1 + * 0b0..Normal operation. + * 0b1..Power-down the USB full-speed differential receiver. + */ +#define USBPHY_PWD_TOG_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWD1PT1_SHIFT)) & USBPHY_PWD_TOG_RXPWD1PT1_MASK) +#define USBPHY_PWD_TOG_RXPWDDIFF_MASK (0x80000U) +#define USBPHY_PWD_TOG_RXPWDDIFF_SHIFT (19U) +/*! RXPWDDIFF + * 0b0..Normal operation. + * 0b1..Power-down the USB high-speed differential receive + */ +#define USBPHY_PWD_TOG_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDDIFF_SHIFT)) & USBPHY_PWD_TOG_RXPWDDIFF_MASK) +#define USBPHY_PWD_TOG_RXPWDRX_MASK (0x100000U) +#define USBPHY_PWD_TOG_RXPWDRX_SHIFT (20U) +/*! RXPWDRX + * 0b0..Normal operation. + * 0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver + */ +#define USBPHY_PWD_TOG_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDRX_SHIFT)) & USBPHY_PWD_TOG_RXPWDRX_MASK) +/*! @} */ + +/*! @name TX - USB PHY Transmitter Control Register */ +/*! @{ */ +#define USBPHY_TX_D_CAL_MASK (0xFU) +#define USBPHY_TX_D_CAL_SHIFT (0U) +/*! D_CAL + * 0b0000..Maximum current, approximately 19% above nominal. + * 0b0111..Nominal + * 0b1111..Minimum current, approximately 19% below nominal. + */ +#define USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TX_D_CAL_MASK) +#define USBPHY_TX_TXCAL45DM_MASK (0xF00U) +#define USBPHY_TX_TXCAL45DM_SHIFT (8U) +#define USBPHY_TX_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DM_SHIFT)) & USBPHY_TX_TXCAL45DM_MASK) +#define USBPHY_TX_TXENCAL45DN_MASK (0x2000U) +#define USBPHY_TX_TXENCAL45DN_SHIFT (13U) +#define USBPHY_TX_TXENCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXENCAL45DN_SHIFT)) & USBPHY_TX_TXENCAL45DN_MASK) +#define USBPHY_TX_TXCAL45DP_MASK (0xF0000U) +#define USBPHY_TX_TXCAL45DP_SHIFT (16U) +#define USBPHY_TX_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DP_SHIFT)) & USBPHY_TX_TXCAL45DP_MASK) +#define USBPHY_TX_TXENCAL45DP_MASK (0x200000U) +#define USBPHY_TX_TXENCAL45DP_SHIFT (21U) +#define USBPHY_TX_TXENCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXENCAL45DP_SHIFT)) & USBPHY_TX_TXENCAL45DP_MASK) +/*! @} */ + +/*! @name TX_SET - USB PHY Transmitter Control Register */ +/*! @{ */ +#define USBPHY_TX_SET_D_CAL_MASK (0xFU) +#define USBPHY_TX_SET_D_CAL_SHIFT (0U) +/*! D_CAL + * 0b0000..Maximum current, approximately 19% above nominal. + * 0b0111..Nominal + * 0b1111..Minimum current, approximately 19% below nominal. + */ +#define USBPHY_TX_SET_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_D_CAL_SHIFT)) & USBPHY_TX_SET_D_CAL_MASK) +#define USBPHY_TX_SET_TXCAL45DM_MASK (0xF00U) +#define USBPHY_TX_SET_TXCAL45DM_SHIFT (8U) +#define USBPHY_TX_SET_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DM_SHIFT)) & USBPHY_TX_SET_TXCAL45DM_MASK) +#define USBPHY_TX_SET_TXENCAL45DN_MASK (0x2000U) +#define USBPHY_TX_SET_TXENCAL45DN_SHIFT (13U) +#define USBPHY_TX_SET_TXENCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXENCAL45DN_SHIFT)) & USBPHY_TX_SET_TXENCAL45DN_MASK) +#define USBPHY_TX_SET_TXCAL45DP_MASK (0xF0000U) +#define USBPHY_TX_SET_TXCAL45DP_SHIFT (16U) +#define USBPHY_TX_SET_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DP_SHIFT)) & USBPHY_TX_SET_TXCAL45DP_MASK) +#define USBPHY_TX_SET_TXENCAL45DP_MASK (0x200000U) +#define USBPHY_TX_SET_TXENCAL45DP_SHIFT (21U) +#define USBPHY_TX_SET_TXENCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXENCAL45DP_SHIFT)) & USBPHY_TX_SET_TXENCAL45DP_MASK) +/*! @} */ + +/*! @name TX_CLR - USB PHY Transmitter Control Register */ +/*! @{ */ +#define USBPHY_TX_CLR_D_CAL_MASK (0xFU) +#define USBPHY_TX_CLR_D_CAL_SHIFT (0U) +/*! D_CAL + * 0b0000..Maximum current, approximately 19% above nominal. + * 0b0111..Nominal + * 0b1111..Minimum current, approximately 19% below nominal. + */ +#define USBPHY_TX_CLR_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_D_CAL_SHIFT)) & USBPHY_TX_CLR_D_CAL_MASK) +#define USBPHY_TX_CLR_TXCAL45DM_MASK (0xF00U) +#define USBPHY_TX_CLR_TXCAL45DM_SHIFT (8U) +#define USBPHY_TX_CLR_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DM_SHIFT)) & USBPHY_TX_CLR_TXCAL45DM_MASK) +#define USBPHY_TX_CLR_TXENCAL45DN_MASK (0x2000U) +#define USBPHY_TX_CLR_TXENCAL45DN_SHIFT (13U) +#define USBPHY_TX_CLR_TXENCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXENCAL45DN_SHIFT)) & USBPHY_TX_CLR_TXENCAL45DN_MASK) +#define USBPHY_TX_CLR_TXCAL45DP_MASK (0xF0000U) +#define USBPHY_TX_CLR_TXCAL45DP_SHIFT (16U) +#define USBPHY_TX_CLR_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXCAL45DP_MASK) +#define USBPHY_TX_CLR_TXENCAL45DP_MASK (0x200000U) +#define USBPHY_TX_CLR_TXENCAL45DP_SHIFT (21U) +#define USBPHY_TX_CLR_TXENCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXENCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXENCAL45DP_MASK) +/*! @} */ + +/*! @name TX_TOG - USB PHY Transmitter Control Register */ +/*! @{ */ +#define USBPHY_TX_TOG_D_CAL_MASK (0xFU) +#define USBPHY_TX_TOG_D_CAL_SHIFT (0U) +/*! D_CAL + * 0b0000..Maximum current, approximately 19% above nominal. + * 0b0111..Nominal + * 0b1111..Minimum current, approximately 19% below nominal. + */ +#define USBPHY_TX_TOG_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_D_CAL_SHIFT)) & USBPHY_TX_TOG_D_CAL_MASK) +#define USBPHY_TX_TOG_TXCAL45DM_MASK (0xF00U) +#define USBPHY_TX_TOG_TXCAL45DM_SHIFT (8U) +#define USBPHY_TX_TOG_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DM_SHIFT)) & USBPHY_TX_TOG_TXCAL45DM_MASK) +#define USBPHY_TX_TOG_TXENCAL45DN_MASK (0x2000U) +#define USBPHY_TX_TOG_TXENCAL45DN_SHIFT (13U) +#define USBPHY_TX_TOG_TXENCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXENCAL45DN_SHIFT)) & USBPHY_TX_TOG_TXENCAL45DN_MASK) +#define USBPHY_TX_TOG_TXCAL45DP_MASK (0xF0000U) +#define USBPHY_TX_TOG_TXCAL45DP_SHIFT (16U) +#define USBPHY_TX_TOG_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXCAL45DP_MASK) +#define USBPHY_TX_TOG_TXENCAL45DP_MASK (0x200000U) +#define USBPHY_TX_TOG_TXENCAL45DP_SHIFT (21U) +#define USBPHY_TX_TOG_TXENCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXENCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXENCAL45DP_MASK) +/*! @} */ + +/*! @name RX - USB PHY Receiver Control Register */ +/*! @{ */ +#define USBPHY_RX_ENVADJ_MASK (0x7U) +#define USBPHY_RX_ENVADJ_SHIFT (0U) +/*! ENVADJ + * 0b000..Trip-Level Voltage is 0.1000 V + * 0b001..Trip-Level Voltage is 0.1125 V + * 0b010..Trip-Level Voltage is 0.1250 V + * 0b011..Trip-Level Voltage is 0.0875 V + * 0b100..reserved + * 0b101..reserved + * 0b110..reserved + * 0b111..reserved + */ +#define USBPHY_RX_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_ENVADJ_SHIFT)) & USBPHY_RX_ENVADJ_MASK) +#define USBPHY_RX_DISCONADJ_MASK (0x70U) +#define USBPHY_RX_DISCONADJ_SHIFT (4U) +/*! DISCONADJ + * 0b000..Trip-Level Voltage is 0.56875 V + * 0b001..Trip-Level Voltage is 0.55000 V + * 0b010..Trip-Level Voltage is 0.58125 V + * 0b011..Trip-Level Voltage is 0.60000 V + * 0b100..reserved + * 0b101..reserved + * 0b110..reserved + * 0b111..reserved + */ +#define USBPHY_RX_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_DISCONADJ_SHIFT)) & USBPHY_RX_DISCONADJ_MASK) +#define USBPHY_RX_RXDBYPASS_MASK (0x400000U) +#define USBPHY_RX_RXDBYPASS_SHIFT (22U) +/*! RXDBYPASS + * 0b0..Normal operation. + * 0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver + */ +#define USBPHY_RX_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RXDBYPASS_SHIFT)) & USBPHY_RX_RXDBYPASS_MASK) +/*! @} */ + +/*! @name RX_SET - USB PHY Receiver Control Register */ +/*! @{ */ +#define USBPHY_RX_SET_ENVADJ_MASK (0x7U) +#define USBPHY_RX_SET_ENVADJ_SHIFT (0U) +/*! ENVADJ + * 0b000..Trip-Level Voltage is 0.1000 V + * 0b001..Trip-Level Voltage is 0.1125 V + * 0b010..Trip-Level Voltage is 0.1250 V + * 0b011..Trip-Level Voltage is 0.0875 V + * 0b100..reserved + * 0b101..reserved + * 0b110..reserved + * 0b111..reserved + */ +#define USBPHY_RX_SET_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_ENVADJ_SHIFT)) & USBPHY_RX_SET_ENVADJ_MASK) +#define USBPHY_RX_SET_DISCONADJ_MASK (0x70U) +#define USBPHY_RX_SET_DISCONADJ_SHIFT (4U) +/*! DISCONADJ + * 0b000..Trip-Level Voltage is 0.56875 V + * 0b001..Trip-Level Voltage is 0.55000 V + * 0b010..Trip-Level Voltage is 0.58125 V + * 0b011..Trip-Level Voltage is 0.60000 V + * 0b100..reserved + * 0b101..reserved + * 0b110..reserved + * 0b111..reserved + */ +#define USBPHY_RX_SET_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_DISCONADJ_SHIFT)) & USBPHY_RX_SET_DISCONADJ_MASK) +#define USBPHY_RX_SET_RXDBYPASS_MASK (0x400000U) +#define USBPHY_RX_SET_RXDBYPASS_SHIFT (22U) +/*! RXDBYPASS + * 0b0..Normal operation. + * 0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver + */ +#define USBPHY_RX_SET_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RXDBYPASS_SHIFT)) & USBPHY_RX_SET_RXDBYPASS_MASK) +/*! @} */ + +/*! @name RX_CLR - USB PHY Receiver Control Register */ +/*! @{ */ +#define USBPHY_RX_CLR_ENVADJ_MASK (0x7U) +#define USBPHY_RX_CLR_ENVADJ_SHIFT (0U) +/*! ENVADJ + * 0b000..Trip-Level Voltage is 0.1000 V + * 0b001..Trip-Level Voltage is 0.1125 V + * 0b010..Trip-Level Voltage is 0.1250 V + * 0b011..Trip-Level Voltage is 0.0875 V + * 0b100..reserved + * 0b101..reserved + * 0b110..reserved + * 0b111..reserved + */ +#define USBPHY_RX_CLR_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_ENVADJ_SHIFT)) & USBPHY_RX_CLR_ENVADJ_MASK) +#define USBPHY_RX_CLR_DISCONADJ_MASK (0x70U) +#define USBPHY_RX_CLR_DISCONADJ_SHIFT (4U) +/*! DISCONADJ + * 0b000..Trip-Level Voltage is 0.56875 V + * 0b001..Trip-Level Voltage is 0.55000 V + * 0b010..Trip-Level Voltage is 0.58125 V + * 0b011..Trip-Level Voltage is 0.60000 V + * 0b100..reserved + * 0b101..reserved + * 0b110..reserved + * 0b111..reserved + */ +#define USBPHY_RX_CLR_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_DISCONADJ_SHIFT)) & USBPHY_RX_CLR_DISCONADJ_MASK) +#define USBPHY_RX_CLR_RXDBYPASS_MASK (0x400000U) +#define USBPHY_RX_CLR_RXDBYPASS_SHIFT (22U) +/*! RXDBYPASS + * 0b0..Normal operation. + * 0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver + */ +#define USBPHY_RX_CLR_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RXDBYPASS_SHIFT)) & USBPHY_RX_CLR_RXDBYPASS_MASK) +/*! @} */ + +/*! @name RX_TOG - USB PHY Receiver Control Register */ +/*! @{ */ +#define USBPHY_RX_TOG_ENVADJ_MASK (0x7U) +#define USBPHY_RX_TOG_ENVADJ_SHIFT (0U) +/*! ENVADJ + * 0b000..Trip-Level Voltage is 0.1000 V + * 0b001..Trip-Level Voltage is 0.1125 V + * 0b010..Trip-Level Voltage is 0.1250 V + * 0b011..Trip-Level Voltage is 0.0875 V + * 0b100..reserved + * 0b101..reserved + * 0b110..reserved + * 0b111..reserved + */ +#define USBPHY_RX_TOG_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_ENVADJ_SHIFT)) & USBPHY_RX_TOG_ENVADJ_MASK) +#define USBPHY_RX_TOG_DISCONADJ_MASK (0x70U) +#define USBPHY_RX_TOG_DISCONADJ_SHIFT (4U) +/*! DISCONADJ + * 0b000..Trip-Level Voltage is 0.56875 V + * 0b001..Trip-Level Voltage is 0.55000 V + * 0b010..Trip-Level Voltage is 0.58125 V + * 0b011..Trip-Level Voltage is 0.60000 V + * 0b100..reserved + * 0b101..reserved + * 0b110..reserved + * 0b111..reserved + */ +#define USBPHY_RX_TOG_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_DISCONADJ_SHIFT)) & USBPHY_RX_TOG_DISCONADJ_MASK) +#define USBPHY_RX_TOG_RXDBYPASS_MASK (0x400000U) +#define USBPHY_RX_TOG_RXDBYPASS_SHIFT (22U) +/*! RXDBYPASS + * 0b0..Normal operation. + * 0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver + */ +#define USBPHY_RX_TOG_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RXDBYPASS_SHIFT)) & USBPHY_RX_TOG_RXDBYPASS_MASK) +/*! @} */ + +/*! @name CTRL - USB PHY General Control Register */ +/*! @{ */ +#define USBPHY_CTRL_ENHOSTDISCONDETECT_MASK (0x2U) +#define USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT (1U) +#define USBPHY_CTRL_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_ENHOSTDISCONDETECT_MASK) +#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK (0x8U) +#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT (3U) +#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK) +#define USBPHY_CTRL_ENDEVPLUGINDET_MASK (0x10U) +#define USBPHY_CTRL_ENDEVPLUGINDET_SHIFT (4U) +/*! ENDEVPLUGINDET + * 0b0..Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) + * 0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins + */ +#define USBPHY_CTRL_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_ENDEVPLUGINDET_MASK) +#define USBPHY_CTRL_DEVPLUGIN_IRQ_MASK (0x1000U) +#define USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT (12U) +#define USBPHY_CTRL_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_IRQ_MASK) +#define USBPHY_CTRL_DATA_ON_LRADC_MASK (0x2000U) +#define USBPHY_CTRL_DATA_ON_LRADC_SHIFT (13U) +#define USBPHY_CTRL_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_DATA_ON_LRADC_MASK) +#define USBPHY_CTRL_ENUTMILEVEL2_MASK (0x4000U) +#define USBPHY_CTRL_ENUTMILEVEL2_SHIFT (14U) +#define USBPHY_CTRL_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL2_MASK) +#define USBPHY_CTRL_ENUTMILEVEL3_MASK (0x8000U) +#define USBPHY_CTRL_ENUTMILEVEL3_SHIFT (15U) +#define USBPHY_CTRL_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL3_MASK) +#define USBPHY_CTRL_AUTORESUME_EN_MASK (0x40000U) +#define USBPHY_CTRL_AUTORESUME_EN_SHIFT (18U) +#define USBPHY_CTRL_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_AUTORESUME_EN_MASK) +#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK (0x80000U) +#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT (19U) +#define USBPHY_CTRL_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK) +#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK (0x100000U) +#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT (20U) +#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK) +#define USBPHY_CTRL_FSDLL_RST_EN_MASK (0x1000000U) +#define USBPHY_CTRL_FSDLL_RST_EN_SHIFT (24U) +#define USBPHY_CTRL_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_FSDLL_RST_EN_MASK) +#define USBPHY_CTRL_OTG_ID_VALUE_MASK (0x8000000U) +#define USBPHY_CTRL_OTG_ID_VALUE_SHIFT (27U) +#define USBPHY_CTRL_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_OTG_ID_VALUE_MASK) +#define USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK (0x10000000U) +#define USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT (28U) +#define USBPHY_CTRL_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK) +#define USBPHY_CTRL_UTMI_SUSPENDM_MASK (0x20000000U) +#define USBPHY_CTRL_UTMI_SUSPENDM_SHIFT (29U) +#define USBPHY_CTRL_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_UTMI_SUSPENDM_MASK) +#define USBPHY_CTRL_CLKGATE_MASK (0x40000000U) +#define USBPHY_CTRL_CLKGATE_SHIFT (30U) +#define USBPHY_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLKGATE_SHIFT)) & USBPHY_CTRL_CLKGATE_MASK) +#define USBPHY_CTRL_SFTRST_MASK (0x80000000U) +#define USBPHY_CTRL_SFTRST_SHIFT (31U) +#define USBPHY_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SFTRST_SHIFT)) & USBPHY_CTRL_SFTRST_MASK) +/*! @} */ + +/*! @name CTRL_SET - USB PHY General Control Register */ +/*! @{ */ +#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK (0x2U) +#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT (1U) +#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK) +#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK (0x8U) +#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT (3U) +#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK) +#define USBPHY_CTRL_SET_ENDEVPLUGINDET_MASK (0x10U) +#define USBPHY_CTRL_SET_ENDEVPLUGINDET_SHIFT (4U) +/*! ENDEVPLUGINDET + * 0b0..Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) + * 0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins + */ +#define USBPHY_CTRL_SET_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_SET_ENDEVPLUGINDET_MASK) +#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK (0x1000U) +#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT (12U) +#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK) +#define USBPHY_CTRL_SET_ENUTMILEVEL2_MASK (0x4000U) +#define USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT (14U) +#define USBPHY_CTRL_SET_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL2_MASK) +#define USBPHY_CTRL_SET_ENUTMILEVEL3_MASK (0x8000U) +#define USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT (15U) +#define USBPHY_CTRL_SET_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL3_MASK) +#define USBPHY_CTRL_SET_AUTORESUME_EN_MASK (0x40000U) +#define USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT (18U) +#define USBPHY_CTRL_SET_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_SET_AUTORESUME_EN_MASK) +#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK (0x80000U) +#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT (19U) +#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK) +#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK (0x100000U) +#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT (20U) +#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK) +#define USBPHY_CTRL_SET_FSDLL_RST_EN_MASK (0x1000000U) +#define USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT (24U) +#define USBPHY_CTRL_SET_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_SET_FSDLL_RST_EN_MASK) +#define USBPHY_CTRL_SET_OTG_ID_VALUE_MASK (0x8000000U) +#define USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT (27U) +#define USBPHY_CTRL_SET_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_VALUE_MASK) +#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK (0x10000000U) +#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT (28U) +#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK) +#define USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK (0x20000000U) +#define USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT (29U) +#define USBPHY_CTRL_SET_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK) +#define USBPHY_CTRL_SET_CLKGATE_MASK (0x40000000U) +#define USBPHY_CTRL_SET_CLKGATE_SHIFT (30U) +#define USBPHY_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_CLKGATE_MASK) +#define USBPHY_CTRL_SET_SFTRST_MASK (0x80000000U) +#define USBPHY_CTRL_SET_SFTRST_SHIFT (31U) +#define USBPHY_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_SFTRST_SHIFT)) & USBPHY_CTRL_SET_SFTRST_MASK) +/*! @} */ + +/*! @name CTRL_CLR - USB PHY General Control Register */ +/*! @{ */ +#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK (0x2U) +#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT (1U) +#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK) +#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK (0x8U) +#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT (3U) +#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK) +#define USBPHY_CTRL_CLR_ENDEVPLUGINDET_MASK (0x10U) +#define USBPHY_CTRL_CLR_ENDEVPLUGINDET_SHIFT (4U) +/*! ENDEVPLUGINDET + * 0b0..Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) + * 0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins + */ +#define USBPHY_CTRL_CLR_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_CLR_ENDEVPLUGINDET_MASK) +#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK (0x1000U) +#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT (12U) +#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK) +#define USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK (0x4000U) +#define USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT (14U) +#define USBPHY_CTRL_CLR_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK) +#define USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK (0x8000U) +#define USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT (15U) +#define USBPHY_CTRL_CLR_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK) +#define USBPHY_CTRL_CLR_AUTORESUME_EN_MASK (0x40000U) +#define USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT (18U) +#define USBPHY_CTRL_CLR_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_CLR_AUTORESUME_EN_MASK) +#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK (0x80000U) +#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT (19U) +#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK) +#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK (0x100000U) +#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT (20U) +#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK) +#define USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK (0x1000000U) +#define USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT (24U) +#define USBPHY_CTRL_CLR_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK) +#define USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK (0x8000000U) +#define USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT (27U) +#define USBPHY_CTRL_CLR_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK) +#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK (0x10000000U) +#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT (28U) +#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK) +#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK (0x20000000U) +#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT (29U) +#define USBPHY_CTRL_CLR_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK) +#define USBPHY_CTRL_CLR_CLKGATE_MASK (0x40000000U) +#define USBPHY_CTRL_CLR_CLKGATE_SHIFT (30U) +#define USBPHY_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_CLKGATE_MASK) +#define USBPHY_CTRL_CLR_SFTRST_MASK (0x80000000U) +#define USBPHY_CTRL_CLR_SFTRST_SHIFT (31U) +#define USBPHY_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_SFTRST_SHIFT)) & USBPHY_CTRL_CLR_SFTRST_MASK) +/*! @} */ + +/*! @name CTRL_TOG - USB PHY General Control Register */ +/*! @{ */ +#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK (0x2U) +#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT (1U) +#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK) +#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK (0x8U) +#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT (3U) +#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK) +#define USBPHY_CTRL_TOG_ENDEVPLUGINDET_MASK (0x10U) +#define USBPHY_CTRL_TOG_ENDEVPLUGINDET_SHIFT (4U) +/*! ENDEVPLUGINDET + * 0b0..Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) + * 0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins + */ +#define USBPHY_CTRL_TOG_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_TOG_ENDEVPLUGINDET_MASK) +#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK (0x1000U) +#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT (12U) +#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK) +#define USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK (0x4000U) +#define USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT (14U) +#define USBPHY_CTRL_TOG_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK) +#define USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK (0x8000U) +#define USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT (15U) +#define USBPHY_CTRL_TOG_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK) +#define USBPHY_CTRL_TOG_AUTORESUME_EN_MASK (0x40000U) +#define USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT (18U) +#define USBPHY_CTRL_TOG_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_TOG_AUTORESUME_EN_MASK) +#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK (0x80000U) +#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT (19U) +#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK) +#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK (0x100000U) +#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT (20U) +#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK) +#define USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK (0x1000000U) +#define USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT (24U) +#define USBPHY_CTRL_TOG_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK) +#define USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK (0x8000000U) +#define USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT (27U) +#define USBPHY_CTRL_TOG_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK) +#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK (0x10000000U) +#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT (28U) +#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK) +#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK (0x20000000U) +#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT (29U) +#define USBPHY_CTRL_TOG_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK) +#define USBPHY_CTRL_TOG_CLKGATE_MASK (0x40000000U) +#define USBPHY_CTRL_TOG_CLKGATE_SHIFT (30U) +#define USBPHY_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_CLKGATE_MASK) +#define USBPHY_CTRL_TOG_SFTRST_MASK (0x80000000U) +#define USBPHY_CTRL_TOG_SFTRST_SHIFT (31U) +#define USBPHY_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_SFTRST_SHIFT)) & USBPHY_CTRL_TOG_SFTRST_MASK) +/*! @} */ + +/*! @name STATUS - USB PHY Status Register */ +/*! @{ */ +#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK (0x8U) +#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT (3U) +/*! HOSTDISCONDETECT_STATUS + * 0b0..USB cable disconnect has not been detected at the local host + * 0b1..USB cable disconnect has been detected at the local host + */ +#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT)) & USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK) +#define USBPHY_STATUS_DEVPLUGIN_STATUS_MASK (0x40U) +#define USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT (6U) +/*! DEVPLUGIN_STATUS + * 0b0..No attachment to a USB host is detected + * 0b1..Cable attachment to a USB host is detected + */ +#define USBPHY_STATUS_DEVPLUGIN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT)) & USBPHY_STATUS_DEVPLUGIN_STATUS_MASK) +#define USBPHY_STATUS_OTGID_STATUS_MASK (0x100U) +#define USBPHY_STATUS_OTGID_STATUS_SHIFT (8U) +#define USBPHY_STATUS_OTGID_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_OTGID_STATUS_SHIFT)) & USBPHY_STATUS_OTGID_STATUS_MASK) +#define USBPHY_STATUS_RESUME_STATUS_MASK (0x400U) +#define USBPHY_STATUS_RESUME_STATUS_SHIFT (10U) +#define USBPHY_STATUS_RESUME_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RESUME_STATUS_SHIFT)) & USBPHY_STATUS_RESUME_STATUS_MASK) +/*! @} */ + +/*! @name DEBUG0 - USB PHY Debug Register 0 */ +/*! @{ */ +#define USBPHY_DEBUG0_OTGIDPIOLOCK_MASK (0x1U) +#define USBPHY_DEBUG0_OTGIDPIOLOCK_SHIFT (0U) +#define USBPHY_DEBUG0_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG0_OTGIDPIOLOCK_MASK) +#define USBPHY_DEBUG0_DEBUG_INTERFACE_HOLD_MASK (0x2U) +#define USBPHY_DEBUG0_DEBUG_INTERFACE_HOLD_SHIFT (1U) +#define USBPHY_DEBUG0_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG0_DEBUG_INTERFACE_HOLD_MASK) +#define USBPHY_DEBUG0_HSTPULLDOWN_MASK (0xCU) +#define USBPHY_DEBUG0_HSTPULLDOWN_SHIFT (2U) +#define USBPHY_DEBUG0_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_HSTPULLDOWN_MASK) +#define USBPHY_DEBUG0_ENHSTPULLDOWN_MASK (0x30U) +#define USBPHY_DEBUG0_ENHSTPULLDOWN_SHIFT (4U) +#define USBPHY_DEBUG0_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_ENHSTPULLDOWN_MASK) +#define USBPHY_DEBUG0_TX2RXCOUNT_MASK (0xF00U) +#define USBPHY_DEBUG0_TX2RXCOUNT_SHIFT (8U) +#define USBPHY_DEBUG0_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_TX2RXCOUNT_MASK) +#define USBPHY_DEBUG0_ENTX2RXCOUNT_MASK (0x1000U) +#define USBPHY_DEBUG0_ENTX2RXCOUNT_SHIFT (12U) +#define USBPHY_DEBUG0_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_ENTX2RXCOUNT_MASK) +#define USBPHY_DEBUG0_SQUELCHRESETCOUNT_MASK (0x1F0000U) +#define USBPHY_DEBUG0_SQUELCHRESETCOUNT_SHIFT (16U) +#define USBPHY_DEBUG0_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG0_SQUELCHRESETCOUNT_MASK) +#define USBPHY_DEBUG0_ENSQUELCHRESET_MASK (0x1000000U) +#define USBPHY_DEBUG0_ENSQUELCHRESET_SHIFT (24U) +#define USBPHY_DEBUG0_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG0_ENSQUELCHRESET_MASK) +#define USBPHY_DEBUG0_SQUELCHRESETLENGTH_MASK (0x1E000000U) +#define USBPHY_DEBUG0_SQUELCHRESETLENGTH_SHIFT (25U) +#define USBPHY_DEBUG0_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG0_SQUELCHRESETLENGTH_MASK) +#define USBPHY_DEBUG0_HOST_RESUME_DEBUG_MASK (0x20000000U) +#define USBPHY_DEBUG0_HOST_RESUME_DEBUG_SHIFT (29U) +#define USBPHY_DEBUG0_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG0_HOST_RESUME_DEBUG_MASK) +#define USBPHY_DEBUG0_CLKGATE_MASK (0x40000000U) +#define USBPHY_DEBUG0_CLKGATE_SHIFT (30U) +#define USBPHY_DEBUG0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLKGATE_SHIFT)) & USBPHY_DEBUG0_CLKGATE_MASK) +/*! @} */ + +/*! @name DEBUG0_SET - USB PHY Debug Register 0 */ +/*! @{ */ +#define USBPHY_DEBUG0_SET_OTGIDPIOLOCK_MASK (0x1U) +#define USBPHY_DEBUG0_SET_OTGIDPIOLOCK_SHIFT (0U) +#define USBPHY_DEBUG0_SET_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG0_SET_OTGIDPIOLOCK_MASK) +#define USBPHY_DEBUG0_SET_DEBUG_INTERFACE_HOLD_MASK (0x2U) +#define USBPHY_DEBUG0_SET_DEBUG_INTERFACE_HOLD_SHIFT (1U) +#define USBPHY_DEBUG0_SET_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG0_SET_DEBUG_INTERFACE_HOLD_MASK) +#define USBPHY_DEBUG0_SET_HSTPULLDOWN_MASK (0xCU) +#define USBPHY_DEBUG0_SET_HSTPULLDOWN_SHIFT (2U) +#define USBPHY_DEBUG0_SET_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_SET_HSTPULLDOWN_MASK) +#define USBPHY_DEBUG0_SET_ENHSTPULLDOWN_MASK (0x30U) +#define USBPHY_DEBUG0_SET_ENHSTPULLDOWN_SHIFT (4U) +#define USBPHY_DEBUG0_SET_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_SET_ENHSTPULLDOWN_MASK) +#define USBPHY_DEBUG0_SET_TX2RXCOUNT_MASK (0xF00U) +#define USBPHY_DEBUG0_SET_TX2RXCOUNT_SHIFT (8U) +#define USBPHY_DEBUG0_SET_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_SET_TX2RXCOUNT_MASK) +#define USBPHY_DEBUG0_SET_ENTX2RXCOUNT_MASK (0x1000U) +#define USBPHY_DEBUG0_SET_ENTX2RXCOUNT_SHIFT (12U) +#define USBPHY_DEBUG0_SET_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_SET_ENTX2RXCOUNT_MASK) +#define USBPHY_DEBUG0_SET_SQUELCHRESETCOUNT_MASK (0x1F0000U) +#define USBPHY_DEBUG0_SET_SQUELCHRESETCOUNT_SHIFT (16U) +#define USBPHY_DEBUG0_SET_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG0_SET_SQUELCHRESETCOUNT_MASK) +#define USBPHY_DEBUG0_SET_ENSQUELCHRESET_MASK (0x1000000U) +#define USBPHY_DEBUG0_SET_ENSQUELCHRESET_SHIFT (24U) +#define USBPHY_DEBUG0_SET_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG0_SET_ENSQUELCHRESET_MASK) +#define USBPHY_DEBUG0_SET_SQUELCHRESETLENGTH_MASK (0x1E000000U) +#define USBPHY_DEBUG0_SET_SQUELCHRESETLENGTH_SHIFT (25U) +#define USBPHY_DEBUG0_SET_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG0_SET_SQUELCHRESETLENGTH_MASK) +#define USBPHY_DEBUG0_SET_HOST_RESUME_DEBUG_MASK (0x20000000U) +#define USBPHY_DEBUG0_SET_HOST_RESUME_DEBUG_SHIFT (29U) +#define USBPHY_DEBUG0_SET_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG0_SET_HOST_RESUME_DEBUG_MASK) +#define USBPHY_DEBUG0_SET_CLKGATE_MASK (0x40000000U) +#define USBPHY_DEBUG0_SET_CLKGATE_SHIFT (30U) +#define USBPHY_DEBUG0_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_CLKGATE_SHIFT)) & USBPHY_DEBUG0_SET_CLKGATE_MASK) +/*! @} */ + +/*! @name DEBUG0_CLR - USB PHY Debug Register 0 */ +/*! @{ */ +#define USBPHY_DEBUG0_CLR_OTGIDPIOLOCK_MASK (0x1U) +#define USBPHY_DEBUG0_CLR_OTGIDPIOLOCK_SHIFT (0U) +#define USBPHY_DEBUG0_CLR_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG0_CLR_OTGIDPIOLOCK_MASK) +#define USBPHY_DEBUG0_CLR_DEBUG_INTERFACE_HOLD_MASK (0x2U) +#define USBPHY_DEBUG0_CLR_DEBUG_INTERFACE_HOLD_SHIFT (1U) +#define USBPHY_DEBUG0_CLR_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG0_CLR_DEBUG_INTERFACE_HOLD_MASK) +#define USBPHY_DEBUG0_CLR_HSTPULLDOWN_MASK (0xCU) +#define USBPHY_DEBUG0_CLR_HSTPULLDOWN_SHIFT (2U) +#define USBPHY_DEBUG0_CLR_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_CLR_HSTPULLDOWN_MASK) +#define USBPHY_DEBUG0_CLR_ENHSTPULLDOWN_MASK (0x30U) +#define USBPHY_DEBUG0_CLR_ENHSTPULLDOWN_SHIFT (4U) +#define USBPHY_DEBUG0_CLR_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_CLR_ENHSTPULLDOWN_MASK) +#define USBPHY_DEBUG0_CLR_TX2RXCOUNT_MASK (0xF00U) +#define USBPHY_DEBUG0_CLR_TX2RXCOUNT_SHIFT (8U) +#define USBPHY_DEBUG0_CLR_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_CLR_TX2RXCOUNT_MASK) +#define USBPHY_DEBUG0_CLR_ENTX2RXCOUNT_MASK (0x1000U) +#define USBPHY_DEBUG0_CLR_ENTX2RXCOUNT_SHIFT (12U) +#define USBPHY_DEBUG0_CLR_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_CLR_ENTX2RXCOUNT_MASK) +#define USBPHY_DEBUG0_CLR_SQUELCHRESETCOUNT_MASK (0x1F0000U) +#define USBPHY_DEBUG0_CLR_SQUELCHRESETCOUNT_SHIFT (16U) +#define USBPHY_DEBUG0_CLR_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG0_CLR_SQUELCHRESETCOUNT_MASK) +#define USBPHY_DEBUG0_CLR_ENSQUELCHRESET_MASK (0x1000000U) +#define USBPHY_DEBUG0_CLR_ENSQUELCHRESET_SHIFT (24U) +#define USBPHY_DEBUG0_CLR_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG0_CLR_ENSQUELCHRESET_MASK) +#define USBPHY_DEBUG0_CLR_SQUELCHRESETLENGTH_MASK (0x1E000000U) +#define USBPHY_DEBUG0_CLR_SQUELCHRESETLENGTH_SHIFT (25U) +#define USBPHY_DEBUG0_CLR_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG0_CLR_SQUELCHRESETLENGTH_MASK) +#define USBPHY_DEBUG0_CLR_HOST_RESUME_DEBUG_MASK (0x20000000U) +#define USBPHY_DEBUG0_CLR_HOST_RESUME_DEBUG_SHIFT (29U) +#define USBPHY_DEBUG0_CLR_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG0_CLR_HOST_RESUME_DEBUG_MASK) +#define USBPHY_DEBUG0_CLR_CLKGATE_MASK (0x40000000U) +#define USBPHY_DEBUG0_CLR_CLKGATE_SHIFT (30U) +#define USBPHY_DEBUG0_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_CLKGATE_SHIFT)) & USBPHY_DEBUG0_CLR_CLKGATE_MASK) +/*! @} */ + +/*! @name DEBUG0_TOG - USB PHY Debug Register 0 */ +/*! @{ */ +#define USBPHY_DEBUG0_TOG_OTGIDPIOLOCK_MASK (0x1U) +#define USBPHY_DEBUG0_TOG_OTGIDPIOLOCK_SHIFT (0U) +#define USBPHY_DEBUG0_TOG_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG0_TOG_OTGIDPIOLOCK_MASK) +#define USBPHY_DEBUG0_TOG_DEBUG_INTERFACE_HOLD_MASK (0x2U) +#define USBPHY_DEBUG0_TOG_DEBUG_INTERFACE_HOLD_SHIFT (1U) +#define USBPHY_DEBUG0_TOG_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG0_TOG_DEBUG_INTERFACE_HOLD_MASK) +#define USBPHY_DEBUG0_TOG_HSTPULLDOWN_MASK (0xCU) +#define USBPHY_DEBUG0_TOG_HSTPULLDOWN_SHIFT (2U) +#define USBPHY_DEBUG0_TOG_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_TOG_HSTPULLDOWN_MASK) +#define USBPHY_DEBUG0_TOG_ENHSTPULLDOWN_MASK (0x30U) +#define USBPHY_DEBUG0_TOG_ENHSTPULLDOWN_SHIFT (4U) +#define USBPHY_DEBUG0_TOG_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_TOG_ENHSTPULLDOWN_MASK) +#define USBPHY_DEBUG0_TOG_TX2RXCOUNT_MASK (0xF00U) +#define USBPHY_DEBUG0_TOG_TX2RXCOUNT_SHIFT (8U) +#define USBPHY_DEBUG0_TOG_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_TOG_TX2RXCOUNT_MASK) +#define USBPHY_DEBUG0_TOG_ENTX2RXCOUNT_MASK (0x1000U) +#define USBPHY_DEBUG0_TOG_ENTX2RXCOUNT_SHIFT (12U) +#define USBPHY_DEBUG0_TOG_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_TOG_ENTX2RXCOUNT_MASK) +#define USBPHY_DEBUG0_TOG_SQUELCHRESETCOUNT_MASK (0x1F0000U) +#define USBPHY_DEBUG0_TOG_SQUELCHRESETCOUNT_SHIFT (16U) +#define USBPHY_DEBUG0_TOG_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG0_TOG_SQUELCHRESETCOUNT_MASK) +#define USBPHY_DEBUG0_TOG_ENSQUELCHRESET_MASK (0x1000000U) +#define USBPHY_DEBUG0_TOG_ENSQUELCHRESET_SHIFT (24U) +#define USBPHY_DEBUG0_TOG_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG0_TOG_ENSQUELCHRESET_MASK) +#define USBPHY_DEBUG0_TOG_SQUELCHRESETLENGTH_MASK (0x1E000000U) +#define USBPHY_DEBUG0_TOG_SQUELCHRESETLENGTH_SHIFT (25U) +#define USBPHY_DEBUG0_TOG_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG0_TOG_SQUELCHRESETLENGTH_MASK) +#define USBPHY_DEBUG0_TOG_HOST_RESUME_DEBUG_MASK (0x20000000U) +#define USBPHY_DEBUG0_TOG_HOST_RESUME_DEBUG_SHIFT (29U) +#define USBPHY_DEBUG0_TOG_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG0_TOG_HOST_RESUME_DEBUG_MASK) +#define USBPHY_DEBUG0_TOG_CLKGATE_MASK (0x40000000U) +#define USBPHY_DEBUG0_TOG_CLKGATE_SHIFT (30U) +#define USBPHY_DEBUG0_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_CLKGATE_SHIFT)) & USBPHY_DEBUG0_TOG_CLKGATE_MASK) +/*! @} */ + +/*! @name DEBUG1 - UTMI Debug Status Register 1 */ +/*! @{ */ +#define USBPHY_DEBUG1_ENTAILADJVD_MASK (0x6000U) +#define USBPHY_DEBUG1_ENTAILADJVD_SHIFT (13U) +/*! ENTAILADJVD + * 0b00..Delay is nominal + * 0b01..Delay is +20% + * 0b10..Delay is -20% + * 0b11..Delay is -40% + */ +#define USBPHY_DEBUG1_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_ENTAILADJVD_MASK) +#define USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ_MASK (0x1C0000U) +#define USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ_SHIFT (18U) +#define USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ_MASK) +#define USBPHY_DEBUG1_USB2_REFBIAS_TST_MASK (0x600000U) +#define USBPHY_DEBUG1_USB2_REFBIAS_TST_SHIFT (21U) +#define USBPHY_DEBUG1_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_USB2_REFBIAS_TST_SHIFT)) & USBPHY_DEBUG1_USB2_REFBIAS_TST_MASK) +/*! @} */ + +/*! @name DEBUG1_SET - UTMI Debug Status Register 1 */ +/*! @{ */ +#define USBPHY_DEBUG1_SET_ENTAILADJVD_MASK (0x6000U) +#define USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT (13U) +/*! ENTAILADJVD + * 0b00..Delay is nominal + * 0b01..Delay is +20% + * 0b10..Delay is -20% + * 0b11..Delay is -40% + */ +#define USBPHY_DEBUG1_SET_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_SET_ENTAILADJVD_MASK) +#define USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ_MASK (0x1C0000U) +#define USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ_SHIFT (18U) +#define USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ_MASK) +#define USBPHY_DEBUG1_SET_USB2_REFBIAS_TST_MASK (0x600000U) +#define USBPHY_DEBUG1_SET_USB2_REFBIAS_TST_SHIFT (21U) +#define USBPHY_DEBUG1_SET_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_USB2_REFBIAS_TST_SHIFT)) & USBPHY_DEBUG1_SET_USB2_REFBIAS_TST_MASK) +/*! @} */ + +/*! @name DEBUG1_CLR - UTMI Debug Status Register 1 */ +/*! @{ */ +#define USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK (0x6000U) +#define USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT (13U) +/*! ENTAILADJVD + * 0b00..Delay is nominal + * 0b01..Delay is +20% + * 0b10..Delay is -20% + * 0b11..Delay is -40% + */ +#define USBPHY_DEBUG1_CLR_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK) +#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ_MASK (0x1C0000U) +#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ_SHIFT (18U) +#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ_MASK) +#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST_MASK (0x600000U) +#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST_SHIFT (21U) +#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST_SHIFT)) & USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST_MASK) +/*! @} */ + +/*! @name DEBUG1_TOG - UTMI Debug Status Register 1 */ +/*! @{ */ +#define USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK (0x6000U) +#define USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT (13U) +/*! ENTAILADJVD + * 0b00..Delay is nominal + * 0b01..Delay is +20% + * 0b10..Delay is -20% + * 0b11..Delay is -40% + */ +#define USBPHY_DEBUG1_TOG_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK) +#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ_MASK (0x1C0000U) +#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ_SHIFT (18U) +#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ_MASK) +#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST_MASK (0x600000U) +#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST_SHIFT (21U) +#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST_SHIFT)) & USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST_MASK) +/*! @} */ + +/*! @name VERSION - UTMI RTL Version */ +/*! @{ */ +#define USBPHY_VERSION_STEP_MASK (0xFFFFU) +#define USBPHY_VERSION_STEP_SHIFT (0U) +#define USBPHY_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_STEP_SHIFT)) & USBPHY_VERSION_STEP_MASK) +#define USBPHY_VERSION_MINOR_MASK (0xFF0000U) +#define USBPHY_VERSION_MINOR_SHIFT (16U) +#define USBPHY_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MINOR_SHIFT)) & USBPHY_VERSION_MINOR_MASK) +#define USBPHY_VERSION_MAJOR_MASK (0xFF000000U) +#define USBPHY_VERSION_MAJOR_SHIFT (24U) +#define USBPHY_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MAJOR_SHIFT)) & USBPHY_VERSION_MAJOR_MASK) +/*! @} */ + +/*! @name PLL_SIC - USB PHY PLL Control/Status Register */ +/*! @{ */ +#define USBPHY_PLL_SIC_MISC2_CONTROL0_MASK (0x20U) +#define USBPHY_PLL_SIC_MISC2_CONTROL0_SHIFT (5U) +#define USBPHY_PLL_SIC_MISC2_CONTROL0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_MISC2_CONTROL0_SHIFT)) & USBPHY_PLL_SIC_MISC2_CONTROL0_MASK) +#define USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK (0x40U) +#define USBPHY_PLL_SIC_PLL_EN_USB_CLKS_SHIFT (6U) +#define USBPHY_PLL_SIC_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK) +#define USBPHY_PLL_SIC_PLL_POWER_MASK (0x1000U) +#define USBPHY_PLL_SIC_PLL_POWER_SHIFT (12U) +#define USBPHY_PLL_SIC_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_PLL_POWER_MASK) +#define USBPHY_PLL_SIC_PLL_ENABLE_MASK (0x2000U) +#define USBPHY_PLL_SIC_PLL_ENABLE_SHIFT (13U) +#define USBPHY_PLL_SIC_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_PLL_ENABLE_MASK) +#define USBPHY_PLL_SIC_PLL_BYPASS_MASK (0x10000U) +#define USBPHY_PLL_SIC_PLL_BYPASS_SHIFT (16U) +#define USBPHY_PLL_SIC_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_PLL_BYPASS_MASK) +#define USBPHY_PLL_SIC_REFBIAS_PWD_SEL_MASK (0x80000U) +#define USBPHY_PLL_SIC_REFBIAS_PWD_SEL_SHIFT (19U) +/*! REFBIAS_PWD_SEL + * 0b0..Selects PLL_POWER to control the reference bias + * 0b1..Selects REFBIAS_PWD to control the reference bias + */ +#define USBPHY_PLL_SIC_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_REFBIAS_PWD_SEL_MASK) +#define USBPHY_PLL_SIC_REFBIAS_PWD_MASK (0x100000U) +#define USBPHY_PLL_SIC_REFBIAS_PWD_SHIFT (20U) +#define USBPHY_PLL_SIC_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_REFBIAS_PWD_MASK) +#define USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK (0x200000U) +#define USBPHY_PLL_SIC_PLL_REG_ENABLE_SHIFT (21U) +#define USBPHY_PLL_SIC_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK) +#define USBPHY_PLL_SIC_PLL_DIV_SEL_MASK (0x1C00000U) +#define USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT (22U) +/*! PLL_DIV_SEL + * 0b000..Divide by 13 + * 0b001..Divide by 15 + * 0b010..Divide by 16 + * 0b011..Divide by 20 + * 0b100..Divide by 22 + * 0b101..Divide by 25 + * 0b110..Divide by 30 + * 0b111..Divide by 240 + */ +#define USBPHY_PLL_SIC_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_PLL_DIV_SEL_MASK) +#define USBPHY_PLL_SIC_PLL_LOCK_MASK (0x80000000U) +#define USBPHY_PLL_SIC_PLL_LOCK_SHIFT (31U) +/*! PLL_LOCK + * 0b0..PLL is not currently locked + * 0b1..PLL is currently locked + */ +#define USBPHY_PLL_SIC_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_PLL_LOCK_MASK) +/*! @} */ + +/*! @name PLL_SIC_SET - USB PHY PLL Control/Status Register */ +/*! @{ */ +#define USBPHY_PLL_SIC_SET_MISC2_CONTROL0_MASK (0x20U) +#define USBPHY_PLL_SIC_SET_MISC2_CONTROL0_SHIFT (5U) +#define USBPHY_PLL_SIC_SET_MISC2_CONTROL0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_MISC2_CONTROL0_SHIFT)) & USBPHY_PLL_SIC_SET_MISC2_CONTROL0_MASK) +#define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK (0x40U) +#define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_SHIFT (6U) +#define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK) +#define USBPHY_PLL_SIC_SET_PLL_POWER_MASK (0x1000U) +#define USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT (12U) +#define USBPHY_PLL_SIC_SET_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_POWER_MASK) +#define USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK (0x2000U) +#define USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT (13U) +#define USBPHY_PLL_SIC_SET_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK) +#define USBPHY_PLL_SIC_SET_PLL_BYPASS_MASK (0x10000U) +#define USBPHY_PLL_SIC_SET_PLL_BYPASS_SHIFT (16U) +#define USBPHY_PLL_SIC_SET_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_BYPASS_MASK) +#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_MASK (0x80000U) +#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_SHIFT (19U) +/*! REFBIAS_PWD_SEL + * 0b0..Selects PLL_POWER to control the reference bias + * 0b1..Selects REFBIAS_PWD to control the reference bias + */ +#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_MASK) +#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_MASK (0x100000U) +#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SHIFT (20U) +#define USBPHY_PLL_SIC_SET_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_SET_REFBIAS_PWD_MASK) +#define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK (0x200000U) +#define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_SHIFT (21U) +#define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK) +#define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK (0x1C00000U) +#define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT (22U) +/*! PLL_DIV_SEL + * 0b000..Divide by 13 + * 0b001..Divide by 15 + * 0b010..Divide by 16 + * 0b011..Divide by 20 + * 0b100..Divide by 22 + * 0b101..Divide by 25 + * 0b110..Divide by 30 + * 0b111..Divide by 240 + */ +#define USBPHY_PLL_SIC_SET_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK) +#define USBPHY_PLL_SIC_SET_PLL_LOCK_MASK (0x80000000U) +#define USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT (31U) +/*! PLL_LOCK + * 0b0..PLL is not currently locked + * 0b1..PLL is currently locked + */ +#define USBPHY_PLL_SIC_SET_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_LOCK_MASK) +/*! @} */ + +/*! @name PLL_SIC_CLR - USB PHY PLL Control/Status Register */ +/*! @{ */ +#define USBPHY_PLL_SIC_CLR_MISC2_CONTROL0_MASK (0x20U) +#define USBPHY_PLL_SIC_CLR_MISC2_CONTROL0_SHIFT (5U) +#define USBPHY_PLL_SIC_CLR_MISC2_CONTROL0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_MISC2_CONTROL0_SHIFT)) & USBPHY_PLL_SIC_CLR_MISC2_CONTROL0_MASK) +#define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_MASK (0x40U) +#define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_SHIFT (6U) +#define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_MASK) +#define USBPHY_PLL_SIC_CLR_PLL_POWER_MASK (0x1000U) +#define USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT (12U) +#define USBPHY_PLL_SIC_CLR_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_POWER_MASK) +#define USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK (0x2000U) +#define USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT (13U) +#define USBPHY_PLL_SIC_CLR_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK) +#define USBPHY_PLL_SIC_CLR_PLL_BYPASS_MASK (0x10000U) +#define USBPHY_PLL_SIC_CLR_PLL_BYPASS_SHIFT (16U) +#define USBPHY_PLL_SIC_CLR_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_BYPASS_MASK) +#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_MASK (0x80000U) +#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_SHIFT (19U) +/*! REFBIAS_PWD_SEL + * 0b0..Selects PLL_POWER to control the reference bias + * 0b1..Selects REFBIAS_PWD to control the reference bias + */ +#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_MASK) +#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_MASK (0x100000U) +#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SHIFT (20U) +#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_CLR_REFBIAS_PWD_MASK) +#define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_MASK (0x200000U) +#define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_SHIFT (21U) +#define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_MASK) +#define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK (0x1C00000U) +#define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT (22U) +/*! PLL_DIV_SEL + * 0b000..Divide by 13 + * 0b001..Divide by 15 + * 0b010..Divide by 16 + * 0b011..Divide by 20 + * 0b100..Divide by 22 + * 0b101..Divide by 25 + * 0b110..Divide by 30 + * 0b111..Divide by 240 + */ +#define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK) +#define USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK (0x80000000U) +#define USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT (31U) +/*! PLL_LOCK + * 0b0..PLL is not currently locked + * 0b1..PLL is currently locked + */ +#define USBPHY_PLL_SIC_CLR_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK) +/*! @} */ + +/*! @name PLL_SIC_TOG - USB PHY PLL Control/Status Register */ +/*! @{ */ +#define USBPHY_PLL_SIC_TOG_MISC2_CONTROL0_MASK (0x20U) +#define USBPHY_PLL_SIC_TOG_MISC2_CONTROL0_SHIFT (5U) +#define USBPHY_PLL_SIC_TOG_MISC2_CONTROL0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_MISC2_CONTROL0_SHIFT)) & USBPHY_PLL_SIC_TOG_MISC2_CONTROL0_MASK) +#define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_MASK (0x40U) +#define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_SHIFT (6U) +#define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_MASK) +#define USBPHY_PLL_SIC_TOG_PLL_POWER_MASK (0x1000U) +#define USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT (12U) +#define USBPHY_PLL_SIC_TOG_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_POWER_MASK) +#define USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK (0x2000U) +#define USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT (13U) +#define USBPHY_PLL_SIC_TOG_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK) +#define USBPHY_PLL_SIC_TOG_PLL_BYPASS_MASK (0x10000U) +#define USBPHY_PLL_SIC_TOG_PLL_BYPASS_SHIFT (16U) +#define USBPHY_PLL_SIC_TOG_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_BYPASS_MASK) +#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_MASK (0x80000U) +#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_SHIFT (19U) +/*! REFBIAS_PWD_SEL + * 0b0..Selects PLL_POWER to control the reference bias + * 0b1..Selects REFBIAS_PWD to control the reference bias + */ +#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_MASK) +#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_MASK (0x100000U) +#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SHIFT (20U) +#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_TOG_REFBIAS_PWD_MASK) +#define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_MASK (0x200000U) +#define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_SHIFT (21U) +#define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_MASK) +#define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK (0x1C00000U) +#define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT (22U) +/*! PLL_DIV_SEL + * 0b000..Divide by 13 + * 0b001..Divide by 15 + * 0b010..Divide by 16 + * 0b011..Divide by 20 + * 0b100..Divide by 22 + * 0b101..Divide by 25 + * 0b110..Divide by 30 + * 0b111..Divide by 240 + */ +#define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK) +#define USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK (0x80000000U) +#define USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT (31U) +/*! PLL_LOCK + * 0b0..PLL is not currently locked + * 0b1..PLL is currently locked + */ +#define USBPHY_PLL_SIC_TOG_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK) +/*! @} */ + +/*! @name USB1_VBUS_DETECT - USB PHY VBUS Detect Control Register */ +/*! @{ */ +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK (0x7U) +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT (0U) +/*! VBUSVALID_THRESH + * 0b000..4.0V + * 0b001..4.1V + * 0b010..4.2V + * 0b011..4.3V + * 0b100..4.4V(Default) + * 0b101..4.5V + * 0b110..4.6V + * 0b111..4.7V + */ +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK) +#define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK (0x8U) +#define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT (3U) +/*! VBUS_OVERRIDE_EN + * 0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) + * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND + */ +#define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK) +#define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK (0x10U) +#define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT (4U) +#define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK) +#define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK (0x20U) +#define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT (5U) +#define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK) +#define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK (0x40U) +#define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT (6U) +#define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK) +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK (0x80U) +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT (7U) +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK) +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_MASK (0x100U) +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_SHIFT (8U) +/*! VBUSVALID_SEL + * 0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) + * 0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller + */ +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_MASK) +#define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_MASK (0x600U) +#define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_SHIFT (9U) +/*! VBUS_SOURCE_SEL + * 0b00..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) + * 0b01..Use the Session Valid comparator results for signal reported to the USB controller + * 0b10..Use the Session Valid comparator results for signal reported to the USB controller + * 0b11..Reserved, do not use + */ +#define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_MASK) +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_MASK (0x40000U) +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_SHIFT (18U) +/*! VBUSVALID_TO_SESSVALID + * 0b0..Use the VBUS_VALID comparator for VBUS_VALID results + * 0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. + */ +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_MASK) +#define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_MASK (0x100000U) +#define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_SHIFT (20U) +/*! PWRUP_CMPS + * 0b0..Powers down the VBUS_VALID comparator + * 0b1..Enables the VBUS_VALID comparator (default) + */ +#define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_MASK) +#define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK (0x4000000U) +#define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT (26U) +/*! DISCHARGE_VBUS + * 0b0..VBUS discharge resistor is disabled (Default) + * 0b1..VBUS discharge resistor is enabled + */ +#define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK) +#define USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_MASK (0x80000000U) +#define USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_SHIFT (31U) +/*! EN_CHARGER_RESISTOR + * 0b0..Disable resistive charger detection resistors on USB_DP and USB_DP + * 0b1..Enable resistive charger detection resistors on USB_DP and USB_DP + */ +#define USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_MASK) +/*! @} */ + +/*! @name USB1_VBUS_DETECT_SET - USB PHY VBUS Detect Control Register */ +/*! @{ */ +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK (0x7U) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT (0U) +/*! VBUSVALID_THRESH + * 0b000..4.0V + * 0b001..4.1V + * 0b010..4.2V + * 0b011..4.3V + * 0b100..4.4V(Default) + * 0b101..4.5V + * 0b110..4.6V + * 0b111..4.7V + */ +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK (0x8U) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_SHIFT (3U) +/*! VBUS_OVERRIDE_EN + * 0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) + * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND + */ +#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK) +#define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_MASK (0x10U) +#define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_SHIFT (4U) +#define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_MASK) +#define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK (0x20U) +#define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_SHIFT (5U) +#define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK) +#define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK (0x40U) +#define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_SHIFT (6U) +#define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK (0x80U) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_SHIFT (7U) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_MASK (0x100U) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_SHIFT (8U) +/*! VBUSVALID_SEL + * 0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) + * 0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller + */ +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_MASK) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_MASK (0x600U) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_SHIFT (9U) +/*! VBUS_SOURCE_SEL + * 0b00..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) + * 0b01..Use the Session Valid comparator results for signal reported to the USB controller + * 0b10..Use the Session Valid comparator results for signal reported to the USB controller + * 0b11..Reserved, do not use + */ +#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_MASK) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_MASK (0x40000U) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_SHIFT (18U) +/*! VBUSVALID_TO_SESSVALID + * 0b0..Use the VBUS_VALID comparator for VBUS_VALID results + * 0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. + */ +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_MASK) +#define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_MASK (0x100000U) +#define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_SHIFT (20U) +/*! PWRUP_CMPS + * 0b0..Powers down the VBUS_VALID comparator + * 0b1..Enables the VBUS_VALID comparator (default) + */ +#define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_MASK) +#define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK (0x4000000U) +#define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT (26U) +/*! DISCHARGE_VBUS + * 0b0..VBUS discharge resistor is disabled (Default) + * 0b1..VBUS discharge resistor is enabled + */ +#define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK) +#define USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_MASK (0x80000000U) +#define USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_SHIFT (31U) +/*! EN_CHARGER_RESISTOR + * 0b0..Disable resistive charger detection resistors on USB_DP and USB_DP + * 0b1..Enable resistive charger detection resistors on USB_DP and USB_DP + */ +#define USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_MASK) +/*! @} */ + +/*! @name USB1_VBUS_DETECT_CLR - USB PHY VBUS Detect Control Register */ +/*! @{ */ +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK (0x7U) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT (0U) +/*! VBUSVALID_THRESH + * 0b000..4.0V + * 0b001..4.1V + * 0b010..4.2V + * 0b011..4.3V + * 0b100..4.4V(Default) + * 0b101..4.5V + * 0b110..4.6V + * 0b111..4.7V + */ +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_MASK (0x8U) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_SHIFT (3U) +/*! VBUS_OVERRIDE_EN + * 0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) + * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND + */ +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_MASK) +#define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_MASK (0x10U) +#define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_SHIFT (4U) +#define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_MASK) +#define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_MASK (0x20U) +#define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_SHIFT (5U) +#define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_MASK) +#define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_MASK (0x40U) +#define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_SHIFT (6U) +#define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_MASK) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_MASK (0x80U) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_SHIFT (7U) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_MASK) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_MASK (0x100U) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_SHIFT (8U) +/*! VBUSVALID_SEL + * 0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) + * 0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller + */ +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_MASK) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_MASK (0x600U) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_SHIFT (9U) +/*! VBUS_SOURCE_SEL + * 0b00..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) + * 0b01..Use the Session Valid comparator results for signal reported to the USB controller + * 0b10..Use the Session Valid comparator results for signal reported to the USB controller + * 0b11..Reserved, do not use + */ +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_MASK) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_MASK (0x40000U) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_SHIFT (18U) +/*! VBUSVALID_TO_SESSVALID + * 0b0..Use the VBUS_VALID comparator for VBUS_VALID results + * 0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. + */ +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_MASK) +#define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_MASK (0x100000U) +#define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_SHIFT (20U) +/*! PWRUP_CMPS + * 0b0..Powers down the VBUS_VALID comparator + * 0b1..Enables the VBUS_VALID comparator (default) + */ +#define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_MASK) +#define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK (0x4000000U) +#define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT (26U) +/*! DISCHARGE_VBUS + * 0b0..VBUS discharge resistor is disabled (Default) + * 0b1..VBUS discharge resistor is enabled + */ +#define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK) +#define USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_MASK (0x80000000U) +#define USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_SHIFT (31U) +/*! EN_CHARGER_RESISTOR + * 0b0..Disable resistive charger detection resistors on USB_DP and USB_DP + * 0b1..Enable resistive charger detection resistors on USB_DP and USB_DP + */ +#define USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_MASK) +/*! @} */ + +/*! @name USB1_VBUS_DETECT_TOG - USB PHY VBUS Detect Control Register */ +/*! @{ */ +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK (0x7U) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT (0U) +/*! VBUSVALID_THRESH + * 0b000..4.0V + * 0b001..4.1V + * 0b010..4.2V + * 0b011..4.3V + * 0b100..4.4V(Default) + * 0b101..4.5V + * 0b110..4.6V + * 0b111..4.7V + */ +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_MASK (0x8U) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_SHIFT (3U) +/*! VBUS_OVERRIDE_EN + * 0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) + * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND + */ +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_MASK) +#define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_MASK (0x10U) +#define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_SHIFT (4U) +#define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_MASK) +#define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_MASK (0x20U) +#define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_SHIFT (5U) +#define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_MASK) +#define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_MASK (0x40U) +#define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_SHIFT (6U) +#define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_MASK) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_MASK (0x80U) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_SHIFT (7U) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_MASK) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_MASK (0x100U) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_SHIFT (8U) +/*! VBUSVALID_SEL + * 0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) + * 0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller + */ +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_MASK) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_MASK (0x600U) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_SHIFT (9U) +/*! VBUS_SOURCE_SEL + * 0b00..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) + * 0b01..Use the Session Valid comparator results for signal reported to the USB controller + * 0b10..Use the Session Valid comparator results for signal reported to the USB controller + * 0b11..Reserved, do not use + */ +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_MASK) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_MASK (0x40000U) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_SHIFT (18U) +/*! VBUSVALID_TO_SESSVALID + * 0b0..Use the VBUS_VALID comparator for VBUS_VALID results + * 0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. + */ +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_MASK) +#define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_MASK (0x100000U) +#define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_SHIFT (20U) +/*! PWRUP_CMPS + * 0b0..Powers down the VBUS_VALID comparator + * 0b1..Enables the VBUS_VALID comparator (default) + */ +#define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_MASK) +#define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK (0x4000000U) +#define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT (26U) +/*! DISCHARGE_VBUS + * 0b0..VBUS discharge resistor is disabled (Default) + * 0b1..VBUS discharge resistor is enabled + */ +#define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK) +#define USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_MASK (0x80000000U) +#define USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_SHIFT (31U) +/*! EN_CHARGER_RESISTOR + * 0b0..Disable resistive charger detection resistors on USB_DP and USB_DP + * 0b1..Enable resistive charger detection resistors on USB_DP and USB_DP + */ +#define USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_MASK) +/*! @} */ + +/*! @name USB1_VBUS_DET_STAT - USB PHY VBUS Detector Status Register */ +/*! @{ */ +#define USBPHY_USB1_VBUS_DET_STAT_SESSEND_MASK (0x1U) +#define USBPHY_USB1_VBUS_DET_STAT_SESSEND_SHIFT (0U) +/*! SESSEND + * 0b0..The VBUS voltage is above the Session Valid threshold + * 0b1..The VBUS voltage is below the Session Valid threshold + */ +#define USBPHY_USB1_VBUS_DET_STAT_SESSEND(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_SESSEND_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_SESSEND_MASK) +#define USBPHY_USB1_VBUS_DET_STAT_BVALID_MASK (0x2U) +#define USBPHY_USB1_VBUS_DET_STAT_BVALID_SHIFT (1U) +/*! BVALID + * 0b0..The VBUS voltage is below the Session Valid threshold + * 0b1..The VBUS voltage is above the Session Valid threshold + */ +#define USBPHY_USB1_VBUS_DET_STAT_BVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_BVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_BVALID_MASK) +#define USBPHY_USB1_VBUS_DET_STAT_AVALID_MASK (0x4U) +#define USBPHY_USB1_VBUS_DET_STAT_AVALID_SHIFT (2U) +/*! AVALID + * 0b0..The VBUS voltage is below the Session Valid threshold + * 0b1..The VBUS voltage is above the Session Valid threshold + */ +#define USBPHY_USB1_VBUS_DET_STAT_AVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_AVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_AVALID_MASK) +#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_MASK (0x8U) +#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_SHIFT (3U) +/*! VBUS_VALID + * 0b0..VBUS is below the comparator threshold + * 0b1..VBUS is above the comparator threshold + */ +#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_MASK) +#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_MASK (0x10U) +#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_SHIFT (4U) +/*! VBUS_VALID_3V + * 0b0..VBUS voltage is below VBUS_VALID_3V threshold + * 0b1..VBUS voltage is above VBUS_VALID_3V threshold + */ +#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_MASK) +/*! @} */ + +/*! @name USB1_CHRG_DETECT - USB PHY Charger Detect Control Register */ +/*! @{ */ +#define USBPHY_USB1_CHRG_DETECT_PULLUP_DP_MASK (0x4U) +#define USBPHY_USB1_CHRG_DETECT_PULLUP_DP_SHIFT (2U) +#define USBPHY_USB1_CHRG_DETECT_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_PULLUP_DP_MASK) +#define USBPHY_USB1_CHRG_DETECT_BGR_IBIAS_MASK (0x800000U) +#define USBPHY_USB1_CHRG_DETECT_BGR_IBIAS_SHIFT (23U) +/*! BGR_IBIAS + * 0b0..Bias current is derived from the USB PHY internal current generator. + * 0b1..Bias current is derived from the reference generator of the bandgap. + */ +#define USBPHY_USB1_CHRG_DETECT_BGR_IBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_BGR_IBIAS_SHIFT)) & USBPHY_USB1_CHRG_DETECT_BGR_IBIAS_MASK) +/*! @} */ + +/*! @name USB1_CHRG_DETECT_SET - USB PHY Charger Detect Control Register */ +/*! @{ */ +#define USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_MASK (0x4U) +#define USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_SHIFT (2U) +#define USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_MASK) +#define USBPHY_USB1_CHRG_DETECT_SET_BGR_IBIAS_MASK (0x800000U) +#define USBPHY_USB1_CHRG_DETECT_SET_BGR_IBIAS_SHIFT (23U) +/*! BGR_IBIAS + * 0b0..Bias current is derived from the USB PHY internal current generator. + * 0b1..Bias current is derived from the reference generator of the bandgap. + */ +#define USBPHY_USB1_CHRG_DETECT_SET_BGR_IBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_BGR_IBIAS_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_BGR_IBIAS_MASK) +/*! @} */ + +/*! @name USB1_CHRG_DETECT_CLR - USB PHY Charger Detect Control Register */ +/*! @{ */ +#define USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_MASK (0x4U) +#define USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_SHIFT (2U) +#define USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_MASK) +#define USBPHY_USB1_CHRG_DETECT_CLR_BGR_IBIAS_MASK (0x800000U) +#define USBPHY_USB1_CHRG_DETECT_CLR_BGR_IBIAS_SHIFT (23U) +/*! BGR_IBIAS + * 0b0..Bias current is derived from the USB PHY internal current generator. + * 0b1..Bias current is derived from the reference generator of the bandgap. + */ +#define USBPHY_USB1_CHRG_DETECT_CLR_BGR_IBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_BGR_IBIAS_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_BGR_IBIAS_MASK) +/*! @} */ + +/*! @name USB1_CHRG_DETECT_TOG - USB PHY Charger Detect Control Register */ +/*! @{ */ +#define USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_MASK (0x4U) +#define USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_SHIFT (2U) +#define USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_MASK) +#define USBPHY_USB1_CHRG_DETECT_TOG_BGR_IBIAS_MASK (0x800000U) +#define USBPHY_USB1_CHRG_DETECT_TOG_BGR_IBIAS_SHIFT (23U) +/*! BGR_IBIAS + * 0b0..Bias current is derived from the USB PHY internal current generator. + * 0b1..Bias current is derived from the reference generator of the bandgap. + */ +#define USBPHY_USB1_CHRG_DETECT_TOG_BGR_IBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_BGR_IBIAS_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_BGR_IBIAS_MASK) +/*! @} */ + +/*! @name USB1_CHRG_DET_STAT - USB PHY Charger Detect Status Register */ +/*! @{ */ +#define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_MASK (0x1U) +#define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_SHIFT (0U) +/*! PLUG_CONTACT + * 0b0..No USB cable attachment has been detected + * 0b1..A USB cable attachment between the device and host has been detected + */ +#define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_MASK) +#define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_MASK (0x2U) +#define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_SHIFT (1U) +/*! CHRG_DETECTED + * 0b0..Standard Downstream Port (SDP) has been detected + * 0b1..Charging Port has been detected + */ +#define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_MASK) +#define USBPHY_USB1_CHRG_DET_STAT_DM_STATE_MASK (0x4U) +#define USBPHY_USB1_CHRG_DET_STAT_DM_STATE_SHIFT (2U) +/*! DM_STATE + * 0b0..USB_DM pin voltage is < 0.8V + * 0b1..USB_DM pin voltage is > 2.0V + */ +#define USBPHY_USB1_CHRG_DET_STAT_DM_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_DM_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_DM_STATE_MASK) +#define USBPHY_USB1_CHRG_DET_STAT_DP_STATE_MASK (0x8U) +#define USBPHY_USB1_CHRG_DET_STAT_DP_STATE_SHIFT (3U) +/*! DP_STATE + * 0b0..USB_DP pin voltage is < 0.8V + * 0b1..USB_DP pin voltage is > 2.0V + */ +#define USBPHY_USB1_CHRG_DET_STAT_DP_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_DP_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_DP_STATE_MASK) +#define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_MASK (0x10U) +#define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_SHIFT (4U) +/*! SECDET_DCP + * 0b0..Charging Downstream Port (CDP) has been detected + * 0b1..Downstream Charging Port (DCP) has been detected + */ +#define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_MASK) +/*! @} */ + +/*! @name ANACTRL - USB PHY Analog Control Register */ +/*! @{ */ +#define USBPHY_ANACTRL_DEV_PULLDOWN_MASK (0x400U) +#define USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT (10U) +/*! DEV_PULLDOWN + * 0b0..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. + * 0b1..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. + */ +#define USBPHY_ANACTRL_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_DEV_PULLDOWN_MASK) +/*! @} */ + +/*! @name ANACTRL_SET - USB PHY Analog Control Register */ +/*! @{ */ +#define USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK (0x400U) +#define USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT (10U) +/*! DEV_PULLDOWN + * 0b0..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. + * 0b1..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. + */ +#define USBPHY_ANACTRL_SET_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK) +/*! @} */ + +/*! @name ANACTRL_CLR - USB PHY Analog Control Register */ +/*! @{ */ +#define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK (0x400U) +#define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT (10U) +/*! DEV_PULLDOWN + * 0b0..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. + * 0b1..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. + */ +#define USBPHY_ANACTRL_CLR_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK) +/*! @} */ + +/*! @name ANACTRL_TOG - USB PHY Analog Control Register */ +/*! @{ */ +#define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK (0x400U) +#define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT (10U) +/*! DEV_PULLDOWN + * 0b0..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. + * 0b1..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. + */ +#define USBPHY_ANACTRL_TOG_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group USBPHY_Register_Masks */ + + +/* USBPHY - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral USBPHY base address */ + #define USBPHY_BASE (0x50038000u) + /** Peripheral USBPHY base address */ + #define USBPHY_BASE_NS (0x40038000u) + /** Peripheral USBPHY base pointer */ + #define USBPHY ((USBPHY_Type *)USBPHY_BASE) + /** Peripheral USBPHY base pointer */ + #define USBPHY_NS ((USBPHY_Type *)USBPHY_BASE_NS) + /** Array initializer of USBPHY peripheral base addresses */ + #define USBPHY_BASE_ADDRS { USBPHY_BASE } + /** Array initializer of USBPHY peripheral base pointers */ + #define USBPHY_BASE_PTRS { USBPHY } + /** Array initializer of USBPHY peripheral base addresses */ + #define USBPHY_BASE_ADDRS_NS { USBPHY_BASE_NS } + /** Array initializer of USBPHY peripheral base pointers */ + #define USBPHY_BASE_PTRS_NS { USBPHY_NS } +#else + /** Peripheral USBPHY base address */ + #define USBPHY_BASE (0x40038000u) + /** Peripheral USBPHY base pointer */ + #define USBPHY ((USBPHY_Type *)USBPHY_BASE) + /** Array initializer of USBPHY peripheral base addresses */ + #define USBPHY_BASE_ADDRS { USBPHY_BASE } + /** Array initializer of USBPHY peripheral base pointers */ + #define USBPHY_BASE_PTRS { USBPHY } +#endif + +/*! + * @} + */ /* end of group USBPHY_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- UTICK Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup UTICK_Peripheral_Access_Layer UTICK Peripheral Access Layer + * @{ + */ + +/** UTICK - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< Control register., offset: 0x0 */ + __IO uint32_t STAT; /**< Status register., offset: 0x4 */ + __IO uint32_t CFG; /**< Capture configuration register., offset: 0x8 */ + __O uint32_t CAPCLR; /**< Capture clear register., offset: 0xC */ + __I uint32_t CAP[4]; /**< Capture register ., array offset: 0x10, array step: 0x4 */ +} UTICK_Type; + +/* ---------------------------------------------------------------------------- + -- UTICK Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup UTICK_Register_Masks UTICK Register Masks + * @{ + */ + +/*! @name CTRL - Control register. */ +/*! @{ */ +#define UTICK_CTRL_DELAYVAL_MASK (0x7FFFFFFFU) +#define UTICK_CTRL_DELAYVAL_SHIFT (0U) +#define UTICK_CTRL_DELAYVAL(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_DELAYVAL_SHIFT)) & UTICK_CTRL_DELAYVAL_MASK) +#define UTICK_CTRL_REPEAT_MASK (0x80000000U) +#define UTICK_CTRL_REPEAT_SHIFT (31U) +#define UTICK_CTRL_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_REPEAT_SHIFT)) & UTICK_CTRL_REPEAT_MASK) +/*! @} */ + +/*! @name STAT - Status register. */ +/*! @{ */ +#define UTICK_STAT_INTR_MASK (0x1U) +#define UTICK_STAT_INTR_SHIFT (0U) +#define UTICK_STAT_INTR(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_INTR_SHIFT)) & UTICK_STAT_INTR_MASK) +#define UTICK_STAT_ACTIVE_MASK (0x2U) +#define UTICK_STAT_ACTIVE_SHIFT (1U) +#define UTICK_STAT_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_ACTIVE_SHIFT)) & UTICK_STAT_ACTIVE_MASK) +/*! @} */ + +/*! @name CFG - Capture configuration register. */ +/*! @{ */ +#define UTICK_CFG_CAPEN0_MASK (0x1U) +#define UTICK_CFG_CAPEN0_SHIFT (0U) +#define UTICK_CFG_CAPEN0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN0_SHIFT)) & UTICK_CFG_CAPEN0_MASK) +#define UTICK_CFG_CAPEN1_MASK (0x2U) +#define UTICK_CFG_CAPEN1_SHIFT (1U) +#define UTICK_CFG_CAPEN1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN1_SHIFT)) & UTICK_CFG_CAPEN1_MASK) +#define UTICK_CFG_CAPEN2_MASK (0x4U) +#define UTICK_CFG_CAPEN2_SHIFT (2U) +#define UTICK_CFG_CAPEN2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN2_SHIFT)) & UTICK_CFG_CAPEN2_MASK) +#define UTICK_CFG_CAPEN3_MASK (0x8U) +#define UTICK_CFG_CAPEN3_SHIFT (3U) +#define UTICK_CFG_CAPEN3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN3_SHIFT)) & UTICK_CFG_CAPEN3_MASK) +#define UTICK_CFG_CAPPOL0_MASK (0x100U) +#define UTICK_CFG_CAPPOL0_SHIFT (8U) +#define UTICK_CFG_CAPPOL0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL0_SHIFT)) & UTICK_CFG_CAPPOL0_MASK) +#define UTICK_CFG_CAPPOL1_MASK (0x200U) +#define UTICK_CFG_CAPPOL1_SHIFT (9U) +#define UTICK_CFG_CAPPOL1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL1_SHIFT)) & UTICK_CFG_CAPPOL1_MASK) +#define UTICK_CFG_CAPPOL2_MASK (0x400U) +#define UTICK_CFG_CAPPOL2_SHIFT (10U) +#define UTICK_CFG_CAPPOL2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL2_SHIFT)) & UTICK_CFG_CAPPOL2_MASK) +#define UTICK_CFG_CAPPOL3_MASK (0x800U) +#define UTICK_CFG_CAPPOL3_SHIFT (11U) +#define UTICK_CFG_CAPPOL3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL3_SHIFT)) & UTICK_CFG_CAPPOL3_MASK) +/*! @} */ + +/*! @name CAPCLR - Capture clear register. */ +/*! @{ */ +#define UTICK_CAPCLR_CAPCLR0_MASK (0x1U) +#define UTICK_CAPCLR_CAPCLR0_SHIFT (0U) +#define UTICK_CAPCLR_CAPCLR0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR0_SHIFT)) & UTICK_CAPCLR_CAPCLR0_MASK) +#define UTICK_CAPCLR_CAPCLR1_MASK (0x2U) +#define UTICK_CAPCLR_CAPCLR1_SHIFT (1U) +#define UTICK_CAPCLR_CAPCLR1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR1_SHIFT)) & UTICK_CAPCLR_CAPCLR1_MASK) +#define UTICK_CAPCLR_CAPCLR2_MASK (0x4U) +#define UTICK_CAPCLR_CAPCLR2_SHIFT (2U) +#define UTICK_CAPCLR_CAPCLR2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR2_SHIFT)) & UTICK_CAPCLR_CAPCLR2_MASK) +#define UTICK_CAPCLR_CAPCLR3_MASK (0x8U) +#define UTICK_CAPCLR_CAPCLR3_SHIFT (3U) +#define UTICK_CAPCLR_CAPCLR3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR3_SHIFT)) & UTICK_CAPCLR_CAPCLR3_MASK) +/*! @} */ + +/*! @name CAP - Capture register . */ +/*! @{ */ +#define UTICK_CAP_CAP_VALUE_MASK (0x7FFFFFFFU) +#define UTICK_CAP_CAP_VALUE_SHIFT (0U) +#define UTICK_CAP_CAP_VALUE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_CAP_VALUE_SHIFT)) & UTICK_CAP_CAP_VALUE_MASK) +#define UTICK_CAP_VALID_MASK (0x80000000U) +#define UTICK_CAP_VALID_SHIFT (31U) +#define UTICK_CAP_VALID(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_VALID_SHIFT)) & UTICK_CAP_VALID_MASK) +/*! @} */ + +/* The count of UTICK_CAP */ +#define UTICK_CAP_COUNT (4U) + + +/*! + * @} + */ /* end of group UTICK_Register_Masks */ + + +/* UTICK - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral UTICK0 base address */ + #define UTICK0_BASE (0x5000E000u) + /** Peripheral UTICK0 base address */ + #define UTICK0_BASE_NS (0x4000E000u) + /** Peripheral UTICK0 base pointer */ + #define UTICK0 ((UTICK_Type *)UTICK0_BASE) + /** Peripheral UTICK0 base pointer */ + #define UTICK0_NS ((UTICK_Type *)UTICK0_BASE_NS) + /** Array initializer of UTICK peripheral base addresses */ + #define UTICK_BASE_ADDRS { UTICK0_BASE } + /** Array initializer of UTICK peripheral base pointers */ + #define UTICK_BASE_PTRS { UTICK0 } + /** Array initializer of UTICK peripheral base addresses */ + #define UTICK_BASE_ADDRS_NS { UTICK0_BASE_NS } + /** Array initializer of UTICK peripheral base pointers */ + #define UTICK_BASE_PTRS_NS { UTICK0_NS } +#else + /** Peripheral UTICK0 base address */ + #define UTICK0_BASE (0x4000E000u) + /** Peripheral UTICK0 base pointer */ + #define UTICK0 ((UTICK_Type *)UTICK0_BASE) + /** Array initializer of UTICK peripheral base addresses */ + #define UTICK_BASE_ADDRS { UTICK0_BASE } + /** Array initializer of UTICK peripheral base pointers */ + #define UTICK_BASE_PTRS { UTICK0 } +#endif +/** Interrupt vectors for the UTICK peripheral type */ +#define UTICK_IRQS { UTICK0_IRQn } + +/*! + * @} + */ /* end of group UTICK_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- WWDT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WWDT_Peripheral_Access_Layer WWDT Peripheral Access Layer + * @{ + */ + +/** WWDT - Register Layout Typedef */ +typedef struct { + __IO uint32_t MOD; /**< Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer., offset: 0x0 */ + __IO uint32_t TC; /**< Watchdog timer constant register. This 24-bit register determines the time-out value., offset: 0x4 */ + __O uint32_t FEED; /**< Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC., offset: 0x8 */ + __I uint32_t TV; /**< Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer., offset: 0xC */ + uint8_t RESERVED_0[4]; + __IO uint32_t WARNINT; /**< Watchdog Warning Interrupt compare value., offset: 0x14 */ + __IO uint32_t WINDOW; /**< Watchdog Window compare value., offset: 0x18 */ +} WWDT_Type; + +/* ---------------------------------------------------------------------------- + -- WWDT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WWDT_Register_Masks WWDT Register Masks + * @{ + */ + +/*! @name MOD - Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */ +/*! @{ */ +#define WWDT_MOD_WDEN_MASK (0x1U) +#define WWDT_MOD_WDEN_SHIFT (0U) +/*! WDEN - Watchdog enable bit. Once this bit is set to one and a watchdog feed is performed, the + * watchdog timer will run permanently. + * 0b0..Stop. The watchdog timer is stopped. + * 0b1..Run. The watchdog timer is running. + */ +#define WWDT_MOD_WDEN(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDEN_SHIFT)) & WWDT_MOD_WDEN_MASK) +#define WWDT_MOD_WDRESET_MASK (0x2U) +#define WWDT_MOD_WDRESET_SHIFT (1U) +/*! WDRESET - Watchdog reset enable bit. Once this bit has been written with a 1 it cannot be re-written with a 0. + * 0b0..Interrupt. A watchdog time-out will not cause a chip reset. + * 0b1..Reset. A watchdog time-out will cause a chip reset. + */ +#define WWDT_MOD_WDRESET(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDRESET_SHIFT)) & WWDT_MOD_WDRESET_MASK) +#define WWDT_MOD_WDTOF_MASK (0x4U) +#define WWDT_MOD_WDTOF_SHIFT (2U) +#define WWDT_MOD_WDTOF(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDTOF_SHIFT)) & WWDT_MOD_WDTOF_MASK) +#define WWDT_MOD_WDINT_MASK (0x8U) +#define WWDT_MOD_WDINT_SHIFT (3U) +#define WWDT_MOD_WDINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDINT_SHIFT)) & WWDT_MOD_WDINT_MASK) +#define WWDT_MOD_WDPROTECT_MASK (0x10U) +#define WWDT_MOD_WDPROTECT_SHIFT (4U) +/*! WDPROTECT - Watchdog update mode. This bit can be set once by software and is only cleared by a reset. + * 0b0..Flexible. The watchdog time-out value (TC) can be changed at any time. + * 0b1..Threshold. The watchdog time-out value (TC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW. + */ +#define WWDT_MOD_WDPROTECT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDPROTECT_SHIFT)) & WWDT_MOD_WDPROTECT_MASK) +/*! @} */ + +/*! @name TC - Watchdog timer constant register. This 24-bit register determines the time-out value. */ +/*! @{ */ +#define WWDT_TC_COUNT_MASK (0xFFFFFFU) +#define WWDT_TC_COUNT_SHIFT (0U) +#define WWDT_TC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TC_COUNT_SHIFT)) & WWDT_TC_COUNT_MASK) +/*! @} */ + +/*! @name FEED - Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC. */ +/*! @{ */ +#define WWDT_FEED_FEED_MASK (0xFFU) +#define WWDT_FEED_FEED_SHIFT (0U) +#define WWDT_FEED_FEED(x) (((uint32_t)(((uint32_t)(x)) << WWDT_FEED_FEED_SHIFT)) & WWDT_FEED_FEED_MASK) +/*! @} */ + +/*! @name TV - Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer. */ +/*! @{ */ +#define WWDT_TV_COUNT_MASK (0xFFFFFFU) +#define WWDT_TV_COUNT_SHIFT (0U) +#define WWDT_TV_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TV_COUNT_SHIFT)) & WWDT_TV_COUNT_MASK) +/*! @} */ + +/*! @name WARNINT - Watchdog Warning Interrupt compare value. */ +/*! @{ */ +#define WWDT_WARNINT_WARNINT_MASK (0x3FFU) +#define WWDT_WARNINT_WARNINT_SHIFT (0U) +#define WWDT_WARNINT_WARNINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WARNINT_WARNINT_SHIFT)) & WWDT_WARNINT_WARNINT_MASK) +/*! @} */ + +/*! @name WINDOW - Watchdog Window compare value. */ +/*! @{ */ +#define WWDT_WINDOW_WINDOW_MASK (0xFFFFFFU) +#define WWDT_WINDOW_WINDOW_SHIFT (0U) +#define WWDT_WINDOW_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WINDOW_WINDOW_SHIFT)) & WWDT_WINDOW_WINDOW_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group WWDT_Register_Masks */ + + +/* WWDT - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral WWDT base address */ + #define WWDT_BASE (0x5000C000u) + /** Peripheral WWDT base address */ + #define WWDT_BASE_NS (0x4000C000u) + /** Peripheral WWDT base pointer */ + #define WWDT ((WWDT_Type *)WWDT_BASE) + /** Peripheral WWDT base pointer */ + #define WWDT_NS ((WWDT_Type *)WWDT_BASE_NS) + /** Array initializer of WWDT peripheral base addresses */ + #define WWDT_BASE_ADDRS { WWDT_BASE } + /** Array initializer of WWDT peripheral base pointers */ + #define WWDT_BASE_PTRS { WWDT } + /** Array initializer of WWDT peripheral base addresses */ + #define WWDT_BASE_ADDRS_NS { WWDT_BASE_NS } + /** Array initializer of WWDT peripheral base pointers */ + #define WWDT_BASE_PTRS_NS { WWDT_NS } +#else + /** Peripheral WWDT base address */ + #define WWDT_BASE (0x4000C000u) + /** Peripheral WWDT base pointer */ + #define WWDT ((WWDT_Type *)WWDT_BASE) + /** Array initializer of WWDT peripheral base addresses */ + #define WWDT_BASE_ADDRS { WWDT_BASE } + /** Array initializer of WWDT peripheral base pointers */ + #define WWDT_BASE_PTRS { WWDT } +#endif +/** Interrupt vectors for the WWDT peripheral type */ +#define WWDT_IRQS { WDT_BOD_IRQn } + +/*! + * @} + */ /* end of group WWDT_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +/* ---------------------------------------------------------------------------- + -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + * @{ + */ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang system_header + #endif +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma system_include +#endif + +/** + * @brief Mask and left-shift a bit field value for use in a register bit range. + * @param field Name of the register bit field. + * @param value Value of the bit field. + * @return Masked and shifted value. + */ +#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) +/** + * @brief Mask and right-shift a register value to extract a bit field value. + * @param field Name of the register bit field. + * @param value Value of the register. + * @return Masked and shifted bit field value. + */ +#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) + +/*! + * @} + */ /* end of group Bit_Field_Generic_Macros */ + + +/* ---------------------------------------------------------------------------- + -- SDK Compatibility + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDK_Compatibility_Symbols SDK Compatibility + * @{ + */ + +/** High Speed SPI (Flexcomm 8) interrupt name */ +#define LSPI_HS_IRQn FLEXCOMM8_IRQn + +/** EMC CS base address */ +#define EMC_CS0_BASE (0x80000000u) +#define EMC_CS1_BASE (0x90000000u) +#define EMC_CS2_BASE (0x98000000u) +#define EMC_CS3_BASE (0x9C000000u) +#define EMC_DYCS0_BASE (0xA0000000u) +#define EMC_DYCS1_BASE (0xB0000000u) +#define EMC_DYCS2_BASE (0xC0000000u) +#define EMC_DYCS3_BASE (0xD0000000u) +#define EMC_CS_ADDRESS {EMC_CS0_BASE, EMC_CS1_BASE, EMC_CS2_BASE, EMC_CS3_BASE} +#define EMC_DYCS_ADDRESS {EMC_DYCS0_BASE, EMC_DYCS1_BASE, EMC_DYCS2_BASE, EMC_DYCS3_BASE} + +/** OTP API */ +typedef struct { + uint32_t (*otpInit)(void); /** Initializes OTP controller */ + uint32_t (*otpEnableBankWriteMask)(uint32_t bankMask); /** Unlock one or more OTP banks for write access */ + uint32_t (*otpDisableBankWriteMask)(uint32_t bankMask); /** Lock one or more OTP banks for write access */ + uint32_t (*otpEnableBankWriteLock)(uint32_t bankIndex, uint32_t regEnableMask, uint32_t regDisableMask, + uint32_t lockWrite); /** Locks or unlocks write access to a register of an OTP bank and the write lock */ + uint32_t (*otpEnableBankReadLock)(uint32_t bankIndex, uint32_t regEnableMask, uint32_t regDisableMask, + uint32_t lockWrite); /** Locks or unlocks read access to a register of an OTP bank and the write lock */ + uint32_t (*otpProgramReg)(uint32_t bankIndex, uint32_t regIndex, uint32_t value); /** Program a single register in an OTP bank */ + uint32_t RESERVED_0[5]; + uint32_t (*rngRead)(void); /** Returns 32-bit number from hardware random number generator */ + uint32_t (*otpGetDriverVersion)(void); /** Returns the version of the OTP driver in ROM */ +} OTP_API_Type; + +/** ROM API */ +typedef struct { + __I uint32_t usbdApiBase; /** USB API Base */ + uint32_t RESERVED_0[13]; + __I OTP_API_Type *otpApiBase; /** OTP API Base */ + __I uint32_t aesApiBase; /** AES API Base */ + __I uint32_t secureApiBase; /** Secure API Base */ +} ROM_API_Type; + +/** ROM API base address */ +#define ROM_API_BASE (0x03000200u) +/** ROM API base pointer */ +#define ROM_API (*(ROM_API_Type**) ROM_API_BASE) +/** OTP API base pointer */ +#define OTP_API (ROM_API->otpApiBase) + +/*! + * @} + */ /* end of group SDK_Compatibility_Symbols */ + + +#endif /* _LPC55S69_CM33_CORE0_H_ */ + diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/LPC55S69_cm33_core0.xml b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/LPC55S69_cm33_core0.xml new file mode 100644 index 000000000..0d7fea3b1 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/LPC55S69_cm33_core0.xml @@ -0,0 +1,87406 @@ + + + nxp.com + LPC55S69_cm33_core0 + 1.0 + LPC55S69JBD100,LPC55S69JBD64,LPC55S69JET98 + +Copyright 2016-2019 NXP +All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + + + CM33 + r2p0 + little + true + true + true + 3 + false + + 8 + 32 + + + FLASH_CFPA0 + FLASH_CFPA + FLASH_CFPA + FLASH_CFPA + 0x9E000 + + 0 + 0x200 + registers + + + + HEADER + . + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + VERSION + . + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + S_FW_Version + Secure firmware version (Monotonic counter) + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + NS_FW_Version + Non-Secure firmware version (Monotonic counter) + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + IMAGE_KEY_REVOKE + Image key revocation ID (Monotonic counter) + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + ROTKH_REVOKE + . + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + RoTK0_EN + RoT Key 0 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked + 0 + 2 + read-write + + + RoTK1_EN + RoT Key 1 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked + 2 + 2 + read-write + + + RoTK2_EN + RoT Key 2 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked + 4 + 2 + read-write + + + + + VENDOR_USAGE + . + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + DBG_VENDOR_USAGE + DBG_VENDOR_USAGE. + 0 + 16 + read-write + + + INVERSE_VALUE + inverse value of bits [15:0] + 16 + 16 + read-write + + + + + DCFG_CC_SOCU_PIN + With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access. + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + NIDEN + Non Secure non-invasive debug enable + 0 + 1 + read-write + + + VALUE_0 + Use DAP to enable + 0 + + + VALUE_1 + Fixed state + 0x1 + + + + + DBGEN + Non Secure debug enable + 1 + 1 + read-write + + + VALUE_0 + Use DAP to enable + 0 + + + VALUE_1 + Fixed state + 0x1 + + + + + SPNIDEN + Secure non-invasive debug enable + 2 + 1 + read-write + + + VALUE_0 + Use DAP to enable + 0 + + + VALUE_1 + Fixed state + 0x1 + + + + + SPIDEN + Secure invasive debug enable + 3 + 1 + read-write + + + VALUE_0 + Use DAP to enable + 0 + + + VALUE_1 + Fixed state + 0x1 + + + + + TAPEN + JTAG TAP enable + 4 + 1 + read-write + + + VALUE_0 + Use DAP to enable + 0 + + + VALUE_1 + Fixed state + 0x1 + + + + + MCM33_DBGEN + Micro CM33 invasive debug enable + 5 + 1 + read-write + + + VALUE_0 + Use DAP to enable + 0 + + + VALUE_1 + Fixed state + 0x1 + + + + + ISP_CMD_EN + ISP Boot Command enable + 6 + 1 + read-write + + + VALUE_0 + Use DAP to enable + 0 + + + VALUE_1 + Fixed state + 0x1 + + + + + FA_CMD_EN + FA Command enable + 7 + 1 + read-write + + + VALUE_0 + Use DAP to enable + 0 + + + VALUE_1 + Fixed state + 0x1 + + + + + ME_CMD_EN + Flash Mass Erase Command enable + 8 + 1 + read-write + + + VALUE_0 + Use DAP to enable + 0 + + + VALUE_1 + Fixed state + 0x1 + + + + + MCM33_NIDEN + Micro CM33 non-invasive debug enable + 9 + 1 + read-write + + + VALUE_0 + Use DAP to enable + 0 + + + VALUE_1 + Fixed state + 0x1 + + + + + UUID_CHECK + Enforce UUID match during Debug authentication. + 15 + 1 + read-write + + + INVERSE_VALUE + inverse value of bits [15:0] + 16 + 16 + read-write + + + + + DCFG_CC_SOCU_DFLT + With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access. + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + NIDEN + Non Secure non-invasive debug fixed state + 0 + 1 + read-write + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + DBGEN + Non Secure debug fixed state + 1 + 1 + read-write + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + SPNIDEN + Secure non-invasive debug fixed state + 2 + 1 + read-write + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + SPIDEN + Secure invasive debug fixed state + 3 + 1 + read-write + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + TAPEN + JTAG TAP fixed state + 4 + 1 + read-write + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + MCM33_DBGEN + Micro CM33 invasive debug fixed state + 5 + 1 + read-write + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + ISP_CMD_EN + ISP Boot Command fixed state + 6 + 1 + read-write + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + FA_CMD_EN + FA Command fixed state + 7 + 1 + read-write + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + ME_CMD_EN + Flash Mass Erase Command fixed state + 8 + 1 + read-write + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + MCM33_NIDEN + Micro CM33 non-invasive debug fixed state + 9 + 1 + read-write + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + INVERSE_VALUE + inverse value of bits [15:0] + 16 + 16 + read-write + + + + + ENABLE_FA_MODE + Enable FA mode. SET_FA_MODE Command should write 0xC33CA55A to this word to indicate boot ROM to enter FA mode. + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + CMPA_PROG_IN_PROGRESS + CMPA Page programming on going. This field shall be set to 0x5CC55AA5 in the active CFPA page each time CMPA page programming is going on. It shall always be set to 0x00000000 in the CFPA scratch area. + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_IV_CODE0 + . + PRINCE_REGION0_IV_CODE + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_IV_HEADER0 + . + PRINCE_REGION0_IV_CODE + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_IV_CODE1 + . + PRINCE_REGION0_IV_CODE + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_IV_HEADER1 + . + PRINCE_REGION0_IV_CODE + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + TYPE + . + 0 + 2 + read-write + + + INDEX + . + 8 + 4 + read-write + + + SIZE + . + 24 + 6 + read-write + + + + + PRINCE_REGION0_IV_BODY0 + . + PRINCE_REGION0_IV_CODE + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_IV_CODE2 + . + PRINCE_REGION0_IV_CODE + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_IV_BODY1 + . + PRINCE_REGION0_IV_CODE + 0x3C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_IV_CODE3 + . + PRINCE_REGION0_IV_CODE + 0x3C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_IV_BODY2 + . + PRINCE_REGION0_IV_CODE + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_IV_CODE4 + . + PRINCE_REGION0_IV_CODE + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_IV_BODY3 + . + PRINCE_REGION0_IV_CODE + 0x44 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_IV_CODE5 + . + PRINCE_REGION0_IV_CODE + 0x44 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_IV_BODY4 + . + PRINCE_REGION0_IV_CODE + 0x48 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_IV_CODE6 + . + PRINCE_REGION0_IV_CODE + 0x48 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_IV_BODY5 + . + PRINCE_REGION0_IV_CODE + 0x4C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_IV_CODE7 + . + PRINCE_REGION0_IV_CODE + 0x4C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_IV_BODY6 + . + PRINCE_REGION0_IV_CODE + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_IV_CODE8 + . + PRINCE_REGION0_IV_CODE + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_IV_BODY7 + . + PRINCE_REGION0_IV_CODE + 0x54 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_IV_CODE9 + . + PRINCE_REGION0_IV_CODE + 0x54 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_IV_BODY8 + . + PRINCE_REGION0_IV_CODE + 0x58 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_IV_CODE10 + . + PRINCE_REGION0_IV_CODE + 0x58 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_IV_BODY9 + . + PRINCE_REGION0_IV_CODE + 0x5C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_IV_CODE11 + . + PRINCE_REGION0_IV_CODE + 0x5C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_IV_BODY10 + . + PRINCE_REGION0_IV_CODE + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_IV_CODE12 + . + PRINCE_REGION0_IV_CODE + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_IV_BODY11 + . + PRINCE_REGION0_IV_CODE + 0x64 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_IV_CODE13 + . + PRINCE_REGION0_IV_CODE + 0x64 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_IV_CODE0 + . + PRINCE_REGION1_IV_CODE + 0x68 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_IV_HEADER0 + . + PRINCE_REGION1_IV_CODE + 0x68 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_IV_CODE1 + . + PRINCE_REGION1_IV_CODE + 0x6C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_IV_HEADER1 + . + PRINCE_REGION1_IV_CODE + 0x6C + 32 + read-write + 0 + 0xFFFFFFFF + + + TYPE + . + 0 + 2 + read-write + + + INDEX + . + 8 + 4 + read-write + + + SIZE + . + 24 + 6 + read-write + + + + + PRINCE_REGION1_IV_BODY0 + . + PRINCE_REGION1_IV_CODE + 0x70 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_IV_CODE2 + . + PRINCE_REGION1_IV_CODE + 0x70 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_IV_BODY1 + . + PRINCE_REGION1_IV_CODE + 0x74 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_IV_CODE3 + . + PRINCE_REGION1_IV_CODE + 0x74 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_IV_BODY2 + . + PRINCE_REGION1_IV_CODE + 0x78 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_IV_CODE4 + . + PRINCE_REGION1_IV_CODE + 0x78 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_IV_BODY3 + . + PRINCE_REGION1_IV_CODE + 0x7C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_IV_CODE5 + . + PRINCE_REGION1_IV_CODE + 0x7C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_IV_BODY4 + . + PRINCE_REGION1_IV_CODE + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_IV_CODE6 + . + PRINCE_REGION1_IV_CODE + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_IV_BODY5 + . + PRINCE_REGION1_IV_CODE + 0x84 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_IV_CODE7 + . + PRINCE_REGION1_IV_CODE + 0x84 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_IV_BODY6 + . + PRINCE_REGION1_IV_CODE + 0x88 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_IV_CODE8 + . + PRINCE_REGION1_IV_CODE + 0x88 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_IV_BODY7 + . + PRINCE_REGION1_IV_CODE + 0x8C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_IV_CODE9 + . + PRINCE_REGION1_IV_CODE + 0x8C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_IV_BODY8 + . + PRINCE_REGION1_IV_CODE + 0x90 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_IV_CODE10 + . + PRINCE_REGION1_IV_CODE + 0x90 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_IV_BODY9 + . + PRINCE_REGION1_IV_CODE + 0x94 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_IV_CODE11 + . + PRINCE_REGION1_IV_CODE + 0x94 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_IV_BODY10 + . + PRINCE_REGION1_IV_CODE + 0x98 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_IV_CODE12 + . + PRINCE_REGION1_IV_CODE + 0x98 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_IV_BODY11 + . + PRINCE_REGION1_IV_CODE + 0x9C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_IV_CODE13 + . + PRINCE_REGION1_IV_CODE + 0x9C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_IV_CODE0 + . + PRINCE_REGION2_IV_CODE + 0xA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_IV_HEADER0 + . + PRINCE_REGION2_IV_CODE + 0xA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_IV_CODE1 + . + PRINCE_REGION2_IV_CODE + 0xA4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_IV_HEADER1 + . + PRINCE_REGION2_IV_CODE + 0xA4 + 32 + read-write + 0 + 0xFFFFFFFF + + + TYPE + . + 0 + 2 + read-write + + + INDEX + . + 8 + 4 + read-write + + + SIZE + . + 24 + 6 + read-write + + + + + PRINCE_REGION2_IV_BODY0 + . + PRINCE_REGION2_IV_CODE + 0xA8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_IV_CODE2 + . + PRINCE_REGION2_IV_CODE + 0xA8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_IV_BODY1 + . + PRINCE_REGION2_IV_CODE + 0xAC + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_IV_CODE3 + . + PRINCE_REGION2_IV_CODE + 0xAC + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_IV_BODY2 + . + PRINCE_REGION2_IV_CODE + 0xB0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_IV_CODE4 + . + PRINCE_REGION2_IV_CODE + 0xB0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_IV_BODY3 + . + PRINCE_REGION2_IV_CODE + 0xB4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_IV_CODE5 + . + PRINCE_REGION2_IV_CODE + 0xB4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_IV_BODY4 + . + PRINCE_REGION2_IV_CODE + 0xB8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_IV_CODE6 + . + PRINCE_REGION2_IV_CODE + 0xB8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_IV_BODY5 + . + PRINCE_REGION2_IV_CODE + 0xBC + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_IV_CODE7 + . + PRINCE_REGION2_IV_CODE + 0xBC + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_IV_BODY6 + . + PRINCE_REGION2_IV_CODE + 0xC0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_IV_CODE8 + . + PRINCE_REGION2_IV_CODE + 0xC0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_IV_BODY7 + . + PRINCE_REGION2_IV_CODE + 0xC4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_IV_CODE9 + . + PRINCE_REGION2_IV_CODE + 0xC4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_IV_BODY8 + . + PRINCE_REGION2_IV_CODE + 0xC8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_IV_CODE10 + . + PRINCE_REGION2_IV_CODE + 0xC8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_IV_BODY9 + . + PRINCE_REGION2_IV_CODE + 0xCC + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_IV_CODE11 + . + PRINCE_REGION2_IV_CODE + 0xCC + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_IV_BODY10 + . + PRINCE_REGION2_IV_CODE + 0xD0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_IV_CODE12 + . + PRINCE_REGION2_IV_CODE + 0xD0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_IV_BODY11 + . + PRINCE_REGION2_IV_CODE + 0xD4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_IV_CODE13 + . + PRINCE_REGION2_IV_CODE + 0xD4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + 56 + 0x4 + CUSTOMER_DEFINED[%s] + Customer Defined (Programable through ROM API) + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + 8 + 0x4 + SHA256_DIGEST[%s] + SHA256_DIGEST0 for DIGEST[31:0] SHA256_DIGEST1 for DIGEST[63:32] SHA256_DIGEST2 for DIGEST[95:64] SHA256_DIGEST3 for DIGEST[127:96] SHA256_DIGEST4 for DIGEST[159:128] SHA256_DIGEST5 for DIGEST[191:160] SHA256_DIGEST6 for DIGEST[223:192] SHA256_DIGEST7 for DIGEST[255:224] + 0x1E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + + + FLASH_CFPA_SCRATCH + FLASH_CFPA + FLASH_CFPA + 0x9DE00 + + 0 + 0x200 + registers + + + + FLASH_CFPA1 + FLASH_CFPA + FLASH_CFPA + 0x9E200 + + 0 + 0x200 + registers + + + + FLASH_CMPA + FLASH_CMPA + FLASH_CMPA + 0x9E400 + + 0 + 0x200 + registers + + + + BOOT_CFG + . + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DEFAULT_ISP_MODE + Default ISP mode: + 4 + 3 + read-write + + + VALUE_0 + Auto ISP + 0 + + + VALUE_1 + USB_HID_MSC + 0x1 + + + VALUE_2 + SPI Slave ISP + 0x2 + + + VALUE_3 + I2C Slave ISP + 0x3 + + + VALUE_7 + Disable ISP fall through + 0x7 + + + + + BOOT_SPEED + Core clock: + 7 + 2 + read-write + + + VALUE_0 + Defined by NMPA.SYSTEM_SPEED_CODE + 0 + + + VALUE_1 + 48MHz FRO + 0x1 + + + VALUE_2 + 96MHz FRO + 0x2 + + + + + BOOT_FAILURE_PIN + GPIO port and pin number to use for indicating failure reason. The toggle rate of the pin is used to decode the error type. [2:0] - Defines GPIO port [7:3] - Defines GPIO pin + 24 + 8 + read-write + + + + + SPI_FLASH_CFG + . + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + USB_ID + . + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + USB_VENDOR_ID + . + 0 + 16 + read-write + + + USB_PRODUCT_ID + . + 16 + 16 + read-write + + + + + SDIO_CFG + . + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + DCFG_CC_SOCU_PIN + . + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + NIDEN + Non Secure non-invasive debug enable + 0 + 1 + read-write + + + VALUE_0 + Use DAP to enable + 0 + + + VALUE_1 + Fixed state + 0x1 + + + + + DBGEN + Non Secure debug enable + 1 + 1 + read-write + + + VALUE_0 + Use DAP to enable + 0 + + + VALUE_1 + Fixed state + 0x1 + + + + + SPNIDEN + Secure non-invasive debug enable + 2 + 1 + read-write + + + VALUE_0 + Use DAP to enable + 0 + + + VALUE_1 + Fixed state + 0x1 + + + + + SPIDEN + Secure invasive debug enable + 3 + 1 + read-write + + + VALUE_0 + Use DAP to enable + 0 + + + VALUE_1 + Fixed state + 0x1 + + + + + TAPEN + JTAG TAP enable + 4 + 1 + read-write + + + VALUE_0 + Use DAP to enable + 0 + + + VALUE_1 + Fixed state + 0x1 + + + + + MCM33_DBGEN + Micro CM33 invasive debug enable + 5 + 1 + read-write + + + VALUE_0 + Use DAP to enable + 0 + + + VALUE_1 + Fixed state + 0x1 + + + + + ISP_CMD_EN + ISP Boot Command enable + 6 + 1 + read-write + + + VALUE_0 + Use DAP to enable + 0 + + + VALUE_1 + Fixed state + 0x1 + + + + + FA_CMD_EN + FA Command enable + 7 + 1 + read-write + + + VALUE_0 + Use DAP to enable + 0 + + + VALUE_1 + Fixed state + 0x1 + + + + + ME_CMD_EN + Flash Mass Erase Command enable + 8 + 1 + read-write + + + VALUE_0 + Use DAP to enable + 0 + + + VALUE_1 + Fixed state + 0x1 + + + + + MCM33_NIDEN + Micro CM33 non-invasive debug enable + 9 + 1 + read-write + + + VALUE_0 + Use DAP to enable + 0 + + + VALUE_1 + Fixed state + 0x1 + + + + + UUID_CHECK + Enforce UUID match during Debug authentication. + 15 + 1 + read-write + + + INVERSE_VALUE + inverse value of bits [15:0] + 16 + 16 + read-write + + + + + DCFG_CC_SOCU_DFLT + . + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + NIDEN + Non Secure non-invasive debug fixed state + 0 + 1 + read-write + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + DBGEN + Non Secure debug fixed state + 1 + 1 + read-write + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + SPNIDEN + Secure non-invasive debug fixed state + 2 + 1 + read-write + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + SPIDEN + Secure invasive debug fixed state + 3 + 1 + read-write + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + TAPEN + JTAG TAP fixed state + 4 + 1 + read-write + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + MCM33_DBGEN + Micro CM33 invasive debug fixed state + 5 + 1 + read-write + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + ISP_CMD_EN + ISP Boot Command fixed state + 6 + 1 + read-write + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + FA_CMD_EN + FA Command fixed state + 7 + 1 + read-write + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + ME_CMD_EN + Flash Mass Erase Command fixed state + 8 + 1 + read-write + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + MCM33_NIDEN + Micro CM33 non-invasive debug fixed state + 9 + 1 + read-write + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + INVERSE_VALUE + inverse value of bits [15:0] + 16 + 16 + read-write + + + + + DAP_VENDOR_USAGE_FIXED + . + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + VENDOR_USAGE + Upper 16 bits of vendor usage field defined in DAP. Lower 16-bits come from customer field area. + 16 + 16 + read-write + + + + + SECURE_BOOT_CFG + . + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + RSA4K + Use RSA4096 keys only. 00- RSA2048 keys 01, 10, 11 - RSA4096 keys + 0 + 2 + read-write + + + DICE_ENC_NXP_CFG + Include NXP area in DICE computation. 00 - not included 01, 10, 11 - included + 2 + 2 + read-write + + + DICE_CUST_CFG + Include Customer factory area (including keys) in DICE computation. 00 - not included 01, 10, 11 - included + 4 + 2 + read-write + + + SKIP_DICE + Skip DICE computation. 00 - Enable DICE 01,10,11 - Disable DICE + 6 + 2 + read-write + + + TZM_IMAGE_TYPE + TrustZone-M mode. 00 - TZM mode in image header. 01 - Disable TZ-M. Boots to NonSecure. 10 - TZ-M enable boots to secure mode. 11 - Preset TZM checker from image header. + 8 + 2 + read-write + + + BLOCK_SET_KEY + Block PUF key code generation. 00 - Enable Key code generation 01, 10, 11 - Disable key code generation + 10 + 2 + read-write + + + BLOCK_ENROLL + Block PUF enrollement. 00 - Enable enrollment mode 01, 10, 11 - Disable further enrollmnet + 12 + 2 + read-write + + + SEC_BOOT_EN + Secure boot enable. 00 - Plain image (internal flash with or without CRC) 01, 10, 11 - Boot signed images. (internal flash, RSA signed) + 30 + 2 + read-write + + + + + PRINCE_BASE_ADDR + . + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR0_PRG + Programmable portion of the base address of region 0. + 0 + 4 + read-write + + + ADDR1_PRG + Programmable portion of the base address of region 1. + 4 + 4 + read-write + + + ADDR2_PRG + Programmable portion of the base address of region 2. + 8 + 4 + read-write + + + LOCK_REG0 + Lock PRINCE region0 settings. 00 - Region is not locked. 01, 10, 11 - Region is locked. + 16 + 2 + read-write + + + LOCK_REG1 + Lock PRINCE region1 settings. 00 - Region is not locked. 01, 10, 11 - Region is locked. + 18 + 2 + read-write + + + LOCK_REG2 + Lock PRINCE region2 settings. 00 - Region is not locked. 01, 10, 11 - Region is locked. + 20 + 2 + read-write + + + REG0_ERASE_CHECK_EN + For PRINCE region0 enable checking whether all encrypted pages are erased together. 00 - Check is disabled. 01, 10, 11 - Check is enabled. + 24 + 2 + read-write + + + REG1_ERASE_CHECK_EN + For PRINCE region1 enable checking whether all encrypted pages are erased together. 00 - Check is disabled. 01, 10, 11 - Check is enabled. + 26 + 2 + read-write + + + REG2_ERASE_CHECK_EN + For PRINCE region2 enable checking whether all encrypted pages are erased together. 00 - Check is disabled. 01, 10, 11 - Check is enabled. + 28 + 2 + read-write + + + + + PRINCE_SR_0 + Region 0, sub-region enable + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_SR_1 + Region 1, sub-region enable + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_SR_2 + Region 2, sub-region enable + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + 8 + 0x4 + ROTKH[%s] + ROTKH0 for Root of Trust Keys Table hash[255:224] ROTKH1 for Root of Trust Keys Table hash[223:192] ROTKH2 for Root of Trust Keys Table hash[191:160] ROTKH3 for Root of Trust Keys Table hash[159:128] ROTKH4 for Root of Trust Keys Table hash[127:96] ROTKH5 for Root of Trust Keys Table hash[95:64] ROTKH6 for Root of Trust Keys Table hash[63:32] ROTKH7 for Root of Trust Keys Table hash[31:0] + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + 56 + 0x4 + CUSTOMER_DEFINED[%s] + Customer Defined (Programable through ROM API) + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + 8 + 0x4 + SHA256_DIGEST[%s] + SHA256_DIGEST0 for DIGEST[31:0] SHA256_DIGEST1 for DIGEST[63:32] SHA256_DIGEST2 for DIGEST[95:64] SHA256_DIGEST3 for DIGEST[127:96] SHA256_DIGEST4 for DIGEST[159:128] SHA256_DIGEST5 for DIGEST[191:160] SHA256_DIGEST6 for DIGEST[223:192] SHA256_DIGEST7 for DIGEST[255:224] + 0x1E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + + + FLASH_KEY_STORE + FLASH_KEY_STORE + FLASH_KEY_STORE + 0x9E600 + + 0 + 0x600 + registers + + + + HEADER + Valid Key Sore Header : 0x95959595 + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + puf_discharge_time_in_ms + puf discharge time in ms. + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + 298 + 0x4 + ACTIVATION_CODE[%s] + . + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + SBKEY_HEADER0 + . + SBKEY_KEY_CODE + 0x4B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + SBKEY_KEY_CODE0 + . + SBKEY_KEY_CODE + 0x4B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + SBKEY_HEADER1 + . + SBKEY_KEY_CODE + 0x4B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + TYPE + . + 0 + 2 + read-write + + + INDEX + . + 8 + 4 + read-write + + + SIZE + . + 24 + 6 + read-write + + + + + SBKEY_KEY_CODE1 + . + SBKEY_KEY_CODE + 0x4B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + SBKEY_BODY0 + . + SBKEY_KEY_CODE + 0x4B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + SBKEY_KEY_CODE2 + . + SBKEY_KEY_CODE + 0x4B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + SBKEY_BODY1 + . + SBKEY_KEY_CODE + 0x4BC + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + SBKEY_KEY_CODE3 + . + SBKEY_KEY_CODE + 0x4BC + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + SBKEY_BODY2 + . + SBKEY_KEY_CODE + 0x4C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + SBKEY_KEY_CODE4 + . + SBKEY_KEY_CODE + 0x4C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + SBKEY_BODY3 + . + SBKEY_KEY_CODE + 0x4C4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + SBKEY_KEY_CODE5 + . + SBKEY_KEY_CODE + 0x4C4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + SBKEY_BODY4 + . + SBKEY_KEY_CODE + 0x4C8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + SBKEY_KEY_CODE6 + . + SBKEY_KEY_CODE + 0x4C8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + SBKEY_BODY5 + . + SBKEY_KEY_CODE + 0x4CC + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + SBKEY_KEY_CODE7 + . + SBKEY_KEY_CODE + 0x4CC + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + SBKEY_BODY6 + . + SBKEY_KEY_CODE + 0x4D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + SBKEY_KEY_CODE8 + . + SBKEY_KEY_CODE + 0x4D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + SBKEY_BODY7 + . + SBKEY_KEY_CODE + 0x4D4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + SBKEY_KEY_CODE9 + . + SBKEY_KEY_CODE + 0x4D4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + SBKEY_BODY8 + . + SBKEY_KEY_CODE + 0x4D8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + SBKEY_KEY_CODE10 + . + SBKEY_KEY_CODE + 0x4D8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + SBKEY_BODY9 + . + SBKEY_KEY_CODE + 0x4DC + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + SBKEY_KEY_CODE11 + . + SBKEY_KEY_CODE + 0x4DC + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + SBKEY_BODY10 + . + SBKEY_KEY_CODE + 0x4E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + SBKEY_KEY_CODE12 + . + SBKEY_KEY_CODE + 0x4E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + SBKEY_BODY11 + . + SBKEY_KEY_CODE + 0x4E4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + SBKEY_KEY_CODE13 + . + SBKEY_KEY_CODE + 0x4E4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + USER_KEK_HEADER0 + . + USER_KEK_KEY_CODE + 0x4E8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + USER_KEK_KEY_CODE0 + . + USER_KEK_KEY_CODE + 0x4E8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + USER_KEK_HEADER1 + . + USER_KEK_KEY_CODE + 0x4EC + 32 + read-write + 0 + 0xFFFFFFFF + + + TYPE + . + 0 + 2 + read-write + + + INDEX + . + 8 + 4 + read-write + + + SIZE + . + 24 + 6 + read-write + + + + + USER_KEK_KEY_CODE1 + . + USER_KEK_KEY_CODE + 0x4EC + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + USER_KEK_BODY0 + . + USER_KEK_KEY_CODE + 0x4F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + USER_KEK_KEY_CODE2 + . + USER_KEK_KEY_CODE + 0x4F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + USER_KEK_BODY1 + . + USER_KEK_KEY_CODE + 0x4F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + USER_KEK_KEY_CODE3 + . + USER_KEK_KEY_CODE + 0x4F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + USER_KEK_BODY2 + . + USER_KEK_KEY_CODE + 0x4F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + USER_KEK_KEY_CODE4 + . + USER_KEK_KEY_CODE + 0x4F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + USER_KEK_BODY3 + . + USER_KEK_KEY_CODE + 0x4FC + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + USER_KEK_KEY_CODE5 + . + USER_KEK_KEY_CODE + 0x4FC + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + USER_KEK_BODY4 + . + USER_KEK_KEY_CODE + 0x500 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + USER_KEK_KEY_CODE6 + . + USER_KEK_KEY_CODE + 0x500 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + USER_KEK_BODY5 + . + USER_KEK_KEY_CODE + 0x504 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + USER_KEK_KEY_CODE7 + . + USER_KEK_KEY_CODE + 0x504 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + USER_KEK_BODY6 + . + USER_KEK_KEY_CODE + 0x508 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + USER_KEK_KEY_CODE8 + . + USER_KEK_KEY_CODE + 0x508 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + USER_KEK_BODY7 + . + USER_KEK_KEY_CODE + 0x50C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + USER_KEK_KEY_CODE9 + . + USER_KEK_KEY_CODE + 0x50C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + USER_KEK_BODY8 + . + USER_KEK_KEY_CODE + 0x510 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + USER_KEK_KEY_CODE10 + . + USER_KEK_KEY_CODE + 0x510 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + USER_KEK_BODY9 + . + USER_KEK_KEY_CODE + 0x514 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + USER_KEK_KEY_CODE11 + . + USER_KEK_KEY_CODE + 0x514 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + USER_KEK_BODY10 + . + USER_KEK_KEY_CODE + 0x518 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + USER_KEK_KEY_CODE12 + . + USER_KEK_KEY_CODE + 0x518 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + USER_KEK_BODY11 + . + USER_KEK_KEY_CODE + 0x51C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + USER_KEK_KEY_CODE13 + . + USER_KEK_KEY_CODE + 0x51C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + UDS_HEADER0 + . + UDS_KEY_CODE + 0x520 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + UDS_KEY_CODE0 + . + UDS_KEY_CODE + 0x520 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + UDS_HEADER1 + . + UDS_KEY_CODE + 0x524 + 32 + read-write + 0 + 0xFFFFFFFF + + + TYPE + . + 0 + 2 + read-write + + + INDEX + . + 8 + 4 + read-write + + + SIZE + . + 24 + 6 + read-write + + + + + UDS_KEY_CODE1 + . + UDS_KEY_CODE + 0x524 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + UDS_BODY0 + . + UDS_KEY_CODE + 0x528 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + UDS_KEY_CODE2 + . + UDS_KEY_CODE + 0x528 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + UDS_BODY1 + . + UDS_KEY_CODE + 0x52C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + UDS_KEY_CODE3 + . + UDS_KEY_CODE + 0x52C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + UDS_BODY2 + . + UDS_KEY_CODE + 0x530 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + UDS_KEY_CODE4 + . + UDS_KEY_CODE + 0x530 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + UDS_BODY3 + . + UDS_KEY_CODE + 0x534 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + UDS_KEY_CODE5 + . + UDS_KEY_CODE + 0x534 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + UDS_BODY4 + . + UDS_KEY_CODE + 0x538 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + UDS_KEY_CODE6 + . + UDS_KEY_CODE + 0x538 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + UDS_BODY5 + . + UDS_KEY_CODE + 0x53C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + UDS_KEY_CODE7 + . + UDS_KEY_CODE + 0x53C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + UDS_BODY6 + . + UDS_KEY_CODE + 0x540 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + UDS_KEY_CODE8 + . + UDS_KEY_CODE + 0x540 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + UDS_BODY7 + . + UDS_KEY_CODE + 0x544 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + UDS_KEY_CODE9 + . + UDS_KEY_CODE + 0x544 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + UDS_BODY8 + . + UDS_KEY_CODE + 0x548 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + UDS_KEY_CODE10 + . + UDS_KEY_CODE + 0x548 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + UDS_BODY9 + . + UDS_KEY_CODE + 0x54C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + UDS_KEY_CODE11 + . + UDS_KEY_CODE + 0x54C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + UDS_BODY10 + . + UDS_KEY_CODE + 0x550 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + UDS_KEY_CODE12 + . + UDS_KEY_CODE + 0x550 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + UDS_BODY11 + . + UDS_KEY_CODE + 0x554 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + UDS_KEY_CODE13 + . + UDS_KEY_CODE + 0x554 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_HEADER0 + . + PRINCE_REGION0_KEY_CODE + 0x558 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_KEY_CODE0 + . + PRINCE_REGION0_KEY_CODE + 0x558 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_HEADER1 + . + PRINCE_REGION0_KEY_CODE + 0x55C + 32 + read-write + 0 + 0xFFFFFFFF + + + TYPE + . + 0 + 2 + read-write + + + INDEX + . + 8 + 4 + read-write + + + SIZE + . + 24 + 6 + read-write + + + + + PRINCE_REGION0_KEY_CODE1 + . + PRINCE_REGION0_KEY_CODE + 0x55C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_BODY0 + . + PRINCE_REGION0_KEY_CODE + 0x560 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_KEY_CODE2 + . + PRINCE_REGION0_KEY_CODE + 0x560 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_BODY1 + . + PRINCE_REGION0_KEY_CODE + 0x564 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_KEY_CODE3 + . + PRINCE_REGION0_KEY_CODE + 0x564 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_BODY2 + . + PRINCE_REGION0_KEY_CODE + 0x568 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_KEY_CODE4 + . + PRINCE_REGION0_KEY_CODE + 0x568 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_BODY3 + . + PRINCE_REGION0_KEY_CODE + 0x56C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_KEY_CODE5 + . + PRINCE_REGION0_KEY_CODE + 0x56C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_BODY4 + . + PRINCE_REGION0_KEY_CODE + 0x570 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_KEY_CODE6 + . + PRINCE_REGION0_KEY_CODE + 0x570 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_BODY5 + . + PRINCE_REGION0_KEY_CODE + 0x574 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_KEY_CODE7 + . + PRINCE_REGION0_KEY_CODE + 0x574 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_BODY6 + . + PRINCE_REGION0_KEY_CODE + 0x578 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_KEY_CODE8 + . + PRINCE_REGION0_KEY_CODE + 0x578 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_BODY7 + . + PRINCE_REGION0_KEY_CODE + 0x57C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_KEY_CODE9 + . + PRINCE_REGION0_KEY_CODE + 0x57C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_BODY8 + . + PRINCE_REGION0_KEY_CODE + 0x580 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_KEY_CODE10 + . + PRINCE_REGION0_KEY_CODE + 0x580 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_BODY9 + . + PRINCE_REGION0_KEY_CODE + 0x584 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_KEY_CODE11 + . + PRINCE_REGION0_KEY_CODE + 0x584 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_BODY10 + . + PRINCE_REGION0_KEY_CODE + 0x588 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_KEY_CODE12 + . + PRINCE_REGION0_KEY_CODE + 0x588 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_BODY11 + . + PRINCE_REGION0_KEY_CODE + 0x58C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_KEY_CODE13 + . + PRINCE_REGION0_KEY_CODE + 0x58C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_HEADER0 + . + PRINCE_REGION1_KEY_CODE + 0x590 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_KEY_CODE0 + . + PRINCE_REGION1_KEY_CODE + 0x590 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_HEADER1 + . + PRINCE_REGION1_KEY_CODE + 0x594 + 32 + read-write + 0 + 0xFFFFFFFF + + + TYPE + . + 0 + 2 + read-write + + + INDEX + . + 8 + 4 + read-write + + + SIZE + . + 24 + 6 + read-write + + + + + PRINCE_REGION1_KEY_CODE1 + . + PRINCE_REGION1_KEY_CODE + 0x594 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_BODY0 + . + PRINCE_REGION1_KEY_CODE + 0x598 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_KEY_CODE2 + . + PRINCE_REGION1_KEY_CODE + 0x598 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_BODY1 + . + PRINCE_REGION1_KEY_CODE + 0x59C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_KEY_CODE3 + . + PRINCE_REGION1_KEY_CODE + 0x59C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_BODY2 + . + PRINCE_REGION1_KEY_CODE + 0x5A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_KEY_CODE4 + . + PRINCE_REGION1_KEY_CODE + 0x5A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_BODY3 + . + PRINCE_REGION1_KEY_CODE + 0x5A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_KEY_CODE5 + . + PRINCE_REGION1_KEY_CODE + 0x5A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_BODY4 + . + PRINCE_REGION1_KEY_CODE + 0x5A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_KEY_CODE6 + . + PRINCE_REGION1_KEY_CODE + 0x5A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_BODY5 + . + PRINCE_REGION1_KEY_CODE + 0x5AC + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_KEY_CODE7 + . + PRINCE_REGION1_KEY_CODE + 0x5AC + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_BODY6 + . + PRINCE_REGION1_KEY_CODE + 0x5B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_KEY_CODE8 + . + PRINCE_REGION1_KEY_CODE + 0x5B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_BODY7 + . + PRINCE_REGION1_KEY_CODE + 0x5B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_KEY_CODE9 + . + PRINCE_REGION1_KEY_CODE + 0x5B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_BODY8 + . + PRINCE_REGION1_KEY_CODE + 0x5B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_KEY_CODE10 + . + PRINCE_REGION1_KEY_CODE + 0x5B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_BODY9 + . + PRINCE_REGION1_KEY_CODE + 0x5BC + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_KEY_CODE11 + . + PRINCE_REGION1_KEY_CODE + 0x5BC + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_BODY10 + . + PRINCE_REGION1_KEY_CODE + 0x5C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_KEY_CODE12 + . + PRINCE_REGION1_KEY_CODE + 0x5C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_BODY11 + . + PRINCE_REGION1_KEY_CODE + 0x5C4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_KEY_CODE13 + . + PRINCE_REGION1_KEY_CODE + 0x5C4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_HEADER0 + . + PRINCE_REGION2_KEY_CODE + 0x5C8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_KEY_CODE0 + . + PRINCE_REGION2_KEY_CODE + 0x5C8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_HEADER1 + . + PRINCE_REGION2_KEY_CODE + 0x5CC + 32 + read-write + 0 + 0xFFFFFFFF + + + TYPE + . + 0 + 2 + read-write + + + INDEX + . + 8 + 4 + read-write + + + SIZE + . + 24 + 6 + read-write + + + + + PRINCE_REGION2_KEY_CODE1 + . + PRINCE_REGION2_KEY_CODE + 0x5CC + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_BODY0 + . + PRINCE_REGION2_KEY_CODE + 0x5D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_KEY_CODE2 + . + PRINCE_REGION2_KEY_CODE + 0x5D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_BODY1 + . + PRINCE_REGION2_KEY_CODE + 0x5D4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_KEY_CODE3 + . + PRINCE_REGION2_KEY_CODE + 0x5D4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_BODY2 + . + PRINCE_REGION2_KEY_CODE + 0x5D8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_KEY_CODE4 + . + PRINCE_REGION2_KEY_CODE + 0x5D8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_BODY3 + . + PRINCE_REGION2_KEY_CODE + 0x5DC + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_KEY_CODE5 + . + PRINCE_REGION2_KEY_CODE + 0x5DC + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_BODY4 + . + PRINCE_REGION2_KEY_CODE + 0x5E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_KEY_CODE6 + . + PRINCE_REGION2_KEY_CODE + 0x5E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_BODY5 + . + PRINCE_REGION2_KEY_CODE + 0x5E4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_KEY_CODE7 + . + PRINCE_REGION2_KEY_CODE + 0x5E4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_BODY6 + . + PRINCE_REGION2_KEY_CODE + 0x5E8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_KEY_CODE8 + . + PRINCE_REGION2_KEY_CODE + 0x5E8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_BODY7 + . + PRINCE_REGION2_KEY_CODE + 0x5EC + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_KEY_CODE9 + . + PRINCE_REGION2_KEY_CODE + 0x5EC + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_BODY8 + . + PRINCE_REGION2_KEY_CODE + 0x5F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_KEY_CODE10 + . + PRINCE_REGION2_KEY_CODE + 0x5F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_BODY9 + . + PRINCE_REGION2_KEY_CODE + 0x5F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_KEY_CODE11 + . + PRINCE_REGION2_KEY_CODE + 0x5F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_BODY10 + . + PRINCE_REGION2_KEY_CODE + 0x5F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_KEY_CODE12 + . + PRINCE_REGION2_KEY_CODE + 0x5F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_BODY11 + . + PRINCE_REGION2_KEY_CODE + 0x5FC + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_KEY_CODE13 + . + PRINCE_REGION2_KEY_CODE + 0x5FC + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + + + SYSCON + SYSCON + SYSCON + 0x40000000 + + 0 + 0x1000 + registers + + + + MEMORYREMAP + Memory Remap control register + 0 + 32 + read-write + 0 + 0x3 + + + MAP + Select the location of the vector table :. + 0 + 2 + read-write + + + ROM0 + Vector Table in ROM. + 0 + + + RAM1 + Vector Table in RAM. + 0x1 + + + FLASH0 + Vector Table in Flash. + 0x2 + + + FLASH1 + Vector Table in Flash. + 0x3 + + + + + + + AHBMATPRIO + AHB Matrix priority control register Priority values are 3 = highest, 0 = lowest + 0x10 + 32 + read-write + 0 + 0x3FFFFFF + + + PRI_TEAL_CBUS + Teal C-AHB bus. + 0 + 2 + read-write + + + PRI_TEAL_SBUS + Teal S-AHB bus. + 2 + 2 + read-write + + + PRI_UTEAL_CBUS + Micro Teal C-AHB bus. + 4 + 2 + read-write + + + PRI_UTEAL_SBUS + Micro Teal S-AHB bus. + 6 + 2 + read-write + + + PRI_USB_FS + USB-FS.(USB0) + 8 + 2 + read-write + + + PRI_SDMA0 + DMA0 controller priority. + 10 + 2 + read-write + + + PRI_EZH_B_D + EZH B data bus. + 12 + 2 + read-write + + + PRI_EZH_B_I + EZH B instruction bus. + 14 + 2 + read-write + + + PRI_SDIO + SDIO. + 16 + 2 + read-write + + + PRI_PQ + PQ (Teal HW Accelerator). + 18 + 2 + read-write + + + PRI_SHA2 + SHA-2. + 20 + 2 + read-write + + + PRI_USB_HS + USB-HS.(USB1) + 22 + 2 + read-write + + + PRI_SDMA1 + DMA1 controller priority. + 24 + 2 + read-write + + + + + CPU0STCKCAL + System tick calibration for secure part of CPU0 + 0x38 + 32 + read-write + 0 + 0x3FFFFFF + + + CAL + System tick timer calibration value. + 0 + 24 + read-write + + + SKEW + Initial value for the Systick timer. + 24 + 1 + read-write + + + NOREF + Initial value for the Systick timer. + 25 + 1 + read-write + + + + + CPU0NSTCKCAL + System tick calibration for non-secure part of CPU0 + 0x3C + 32 + read-write + 0 + 0x3FFFFFF + + + CAL + System tick timer calibration value. + 0 + 24 + read-write + + + SKEW + Initial value for the Systick timer. + 24 + 1 + read-write + + + NOREF + Initial value for the Systick timer. + 25 + 1 + read-write + + + + + CPU1TCKCAL + System tick calibration for CPU1 + 0x40 + 32 + read-write + 0 + 0x3FFFFFF + + + CAL + System tick timer calibration value. + 0 + 24 + read-write + + + SKEW + Initial value for the Systick timer. + 24 + 1 + read-write + + + NOREF + Initial value for the Systick timer. + 25 + 1 + read-write + + + + + NMISRC + NMI Source Select + 0x48 + 32 + read-write + 0 + 0xC0003F3F + + + IRQCPU0 + The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for the CPU0, if enabled by NMIENCPU0. + 0 + 6 + read-write + + + IRQCPU1 + The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for the CPU1, if enabled by NMIENCPU1. + 8 + 6 + read-write + + + NMIENCPU1 + Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by IRQCPU1. + 30 + 1 + read-write + + + NMIENCPU0 + Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by IRQCPU0. + 31 + 1 + read-write + + + + + PRESETCTRL0 + Peripheral reset control 0 + PRESETCTRL + 0x100 + 32 + read-write + 0 + 0xCFFE9FA + + + ROM_RST + ROM reset control. + 1 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + SRAM_CTRL1_RST + SRAM Controller 1 reset control. + 3 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + SRAM_CTRL2_RST + SRAM Controller 2 reset control. + 4 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + SRAM_CTRL3_RST + SRAM Controller 3 reset control. + 5 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + SRAM_CTRL4_RST + SRAM Controller 4 reset control. + 6 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + FLASH_RST + Flash controller reset control. + 7 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + FMC_RST + FMC controller reset control. + 8 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + MUX0_RST + Input Mux 0 reset control. + 11 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + IOCON_RST + I/O controller reset control. + 13 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + GPIO0_RST + GPIO0 reset control. + 14 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + GPIO1_RST + GPIO1 reset control. + 15 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + GPIO2_RST + GPIO2 reset control. + 16 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + GPIO3_RST + GPIO3 reset control. + 17 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + PINT_RST + Pin interrupt (PINT) reset control. + 18 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + GINT_RST + Group interrupt (GINT) reset control. + 19 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + DMA0_RST + DMA0 reset control. + 20 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + CRCGEN_RST + CRCGEN reset control. + 21 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + WWDT_RST + Watchdog Timer reset control. + 22 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + RTC_RST + Real Time Clock (RTC) reset control. + 23 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + MAILBOX_RST + Inter CPU communication Mailbox reset control. + 26 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + ADC_RST + ADC reset control. + 27 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + + + PRESETCTRLX0 + Peripheral reset control register + PRESETCTRL + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + PRESETCTRL1 + Peripheral reset control 1 + PRESETCTRL + 0x104 + 32 + read-write + 0 + 0xDE57FC47 + + + MRT_RST + MRT reset control. + 0 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + OSTIMER0_RST + OS Timer 0 reset control. + 1 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + SCT0_RST + SCT0 reset control. + 2 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + SCTIPU_RST + SCTIPU reset control. + 6 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + UTICK0_RST + UTICK0 reset control. + 10 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + FC0_RST + FC0 reset control. + 11 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + FC1_RST + FC1 reset control. + 12 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + FC2_RST + FC2 reset control. + 13 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + FC3_RST + FC3 reset control. + 14 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + FC4_RST + FC4 reset control. + 15 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + FC5_RST + FC5 reset control. + 16 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + FC6_RST + FC6 reset control. + 17 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + FC7_RST + FC7 reset control. + 18 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + TIMER2_RST + Timer 2 reset control. + 22 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + USB0_DEV_RST + USB0 DEV reset control. + 25 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + TIMER0_RST + Timer 0 reset control. + 26 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + TIMER1_RST + Timer 1 reset control. + 27 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + PVT_RST + PVT reset control. + 28 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + EZHA_RST + EZH a reset control. + 30 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + EZHB_RST + EZH b reset control. + 31 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + + + PRESETCTRLX1 + Peripheral reset control register + PRESETCTRL + 0x104 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + PRESETCTRL2 + Peripheral reset control 2 + PRESETCTRL + 0x108 + 32 + read-write + 0 + 0x7FFF77FE + + + DMA1_RST + DMA1 reset control. + 1 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + COMP_RST + Comparator reset control. + 2 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + SDIO_RST + SDIO reset control. + 3 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + USB1_HOST_RST + USB1 Host reset control. + 4 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + USB1_DEV_RST + USB1 dev reset control. + 5 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + USB1_RAM_RST + USB1 RAM reset control. + 6 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + USB1_PHY_RST + USB1 PHY reset control. + 7 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + FREQME_RST + Frequency meter reset control. + 8 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + GPIO4_RST + GPIO4 reset control. + 9 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + GPIO5_RST + GPIO5 reset control. + 10 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + OTP_RST + OTP reset control. + 12 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + RNG_RST + RNG reset control. + 13 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + MUX1_RST + Peripheral Input Mux 1 reset control. + 14 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + USB0_HOSTM_RST + USB0 Host Master reset control. + 16 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + USB0_HOSTS_RST + USB0 Host Slave reset control. + 17 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + HASH0_RST + HASH0 reset control. + 18 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + PQ_RST + Power Quad reset control. + 19 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + PLULUT_RST + PLU LUT reset control. + 20 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + TIMER3_RST + Timer 3 reset control. + 21 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + TIMER4_RST + Timer 4 reset control. + 22 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + PUF_RST + PUF reset control reset control. + 23 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + CASPER_RST + Casper reset control. + 24 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + CAPT0_RST + CAPT0 reset control. + 25 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + ANALOG_CTRL_RST + analog control reset control. + 27 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + HS_LSPI_RST + HS LSPI reset control. + 28 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + GPIO_SEC_RST + GPIO secure reset control. + 29 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + GPIO_SEC_INT_RST + GPIO secure int reset control. + 30 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + + + PRESETCTRLX2 + Peripheral reset control register + PRESETCTRL + 0x108 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + 3 + 0x4 + PRESETCTRLSET[%s] + Peripheral reset control set register + 0x120 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + 3 + 0x4 + PRESETCTRLCLR[%s] + Peripheral reset contro clearl register + 0x140 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + SWR_RESET + generate a software_reset + 0x160 + 32 + write-only + 0 + 0xFFFFFFFF + + + SWR_RESET + Write 0x5A00_0001 to generate a software_reset. + 0 + 32 + write-only + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Generate a software reset. + 0x5A000001 + + + + + + + AHBCLKCTRL0 + AHB Clock control 0 + AHBCLKCTRL + 0x200 + 32 + read-write + 0x180 + 0xCFFE9FA + + + ROM + Enables the clock for the ROM. + 1 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + SRAM_CTRL1 + Enables the clock for the SRAM Controller 1. + 3 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + SRAM_CTRL2 + Enables the clock for the SRAM Controller 2. + 4 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + SRAM_CTRL3 + Enables the clock for the SRAM Controller 3. + 5 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + SRAM_CTRL4 + Enables the clock for the SRAM Controller 4. + 6 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + FLASH + Enables the clock for the Flash controller. + 7 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + FMC + Enables the clock for the FMC controller. + 8 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + MUX0 + Enables the clock for the Input Mux 0. + 11 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + IOCON + Enables the clock for the I/O controller. + 13 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + GPIO0 + Enables the clock for the GPIO0. + 14 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + GPIO1 + Enables the clock for the GPIO1. + 15 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + GPIO2 + Enables the clock for the GPIO2. + 16 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + GPIO3 + Enables the clock for the GPIO3. + 17 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + PINT + Enables the clock for the Pin interrupt (PINT). + 18 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + GINT + Enables the clock for the Group interrupt (GINT). + 19 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + DMA0 + Enables the clock for the DMA0. + 20 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + CRCGEN + Enables the clock for the CRCGEN. + 21 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + WWDT + Enables the clock for the Watchdog Timer. + 22 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + RTC + Enables the clock for the Real Time Clock (RTC). + 23 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + MAILBOX + Enables the clock for the Inter CPU communication Mailbox. + 26 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + ADC + Enables the clock for the ADC. + 27 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + + + AHBCLKCTRLX0 + Peripheral reset control register + AHBCLKCTRL + 0x200 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + AHBCLKCTRL1 + AHB Clock control 1 + AHBCLKCTRL + 0x204 + 32 + read-write + 0 + 0xDE57FC47 + + + MRT + Enables the clock for the MRT. + 0 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + OSTIMER0 + Enables the clock for the OS Timer 0. + 1 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + SCT0 + Enables the clock for the SCT0. + 2 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + SCTIPU + Enables the clock for the SCTIPU. + 6 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + UTICK0 + Enables the clock for the UTICK0. + 10 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + FC0 + Enables the clock for the FC0. + 11 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + FC1 + Enables the clock for the FC1. + 12 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + FC2 + Enables the clock for the FC2. + 13 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + FC3 + Enables the clock for the FC3. + 14 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + FC4 + Enables the clock for the FC4. + 15 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + FC5 + Enables the clock for the FC5. + 16 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + FC6 + Enables the clock for the FC6. + 17 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + FC7 + Enables the clock for the FC7. + 18 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + TIMER2 + Enables the clock for the Timer 2. + 22 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + USB0_DEV + Enables the clock for the USB0 DEV. + 25 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + TIMER0 + Enables the clock for the Timer 0. + 26 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + TIMER1 + Enables the clock for the Timer 1. + 27 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + PVT + Enables the clock for the PVT. + 28 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + EZHA + Enables the clock for the EZH a. + 30 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + EZHB + Enables the clock for the EZH b. + 31 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + + + AHBCLKCTRLX1 + Peripheral reset control register + AHBCLKCTRL + 0x204 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + AHBCLKCTRL2 + AHB Clock control 2 + AHBCLKCTRL + 0x208 + 32 + read-write + 0 + 0x7FFF77FE + + + DMA1 + Enables the clock for the DMA1. + 1 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + COMP + Enables the clock for the Comparator. + 2 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + SDIO + Enables the clock for the SDIO. + 3 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + USB1_HOST + Enables the clock for the USB1 Host. + 4 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + USB1_DEV + Enables the clock for the USB1 dev. + 5 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + USB1_RAM + Enables the clock for the USB1 RAM. + 6 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + USB1_PHY + Enables the clock for the USB1 PHY. + 7 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + FREQME + Enables the clock for the Frequency meter. + 8 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + GPIO4 + Enables the clock for the GPIO4. + 9 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + GPIO5 + Enables the clock for the GPIO5. + 10 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + OTP + Enables the clock for the OTP. + 12 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + RNG + Enables the clock for the RNG. + 13 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + MUX1 + Enables the clock for the Peripheral Input Mux 1. + 14 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + USB0_HOSTM + Enables the clock for the USB0 Host Master. + 16 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + USB0_HOSTS + Enables the clock for the USB0 Host Slave. + 17 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + HASH0 + Enables the clock for the HASH0. + 18 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + PQ + Enables the clock for the Power Quad. + 19 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + PLULUT + Enables the clock for the PLU LUT. + 20 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + TIMER3 + Enables the clock for the Timer 3. + 21 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + TIMER4 + Enables the clock for the Timer 4. + 22 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + PUF + Enables the clock for the PUF reset control. + 23 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + CASPER + Enables the clock for the Casper. + 24 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + CAPT0 + Enables the clock for the CAPT0. + 25 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + ANALOG_CTRL + Enables the clock for the analog control. + 27 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + HS_LSPI + Enables the clock for the HS LSPI. + 28 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + GPIO_SEC + Enables the clock for the GPIO secure. + 29 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + GPIO_SEC_INT + Enables the clock for the GPIO secure int. + 30 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + + + AHBCLKCTRLX2 + Peripheral reset control register + AHBCLKCTRL + 0x208 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + 3 + 0x4 + AHBCLKCTRLSET[%s] + Peripheral reset control register + 0x220 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + 3 + 0x4 + AHBCLKCTRLCLR[%s] + Peripheral reset control register + 0x240 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + SYSTICKCLKSEL0 + System Tick Timer for CPU0 source select + SYSTICKCLKSEL + 0x260 + 32 + read-write + 0x7 + 0x7 + + + SEL + System Tick Timer for CPU0 source select. + 0 + 3 + read-write + + + ENUM_0x0 + System Tick 0 divided clock. + 0 + + + ENUM_0x1 + FRO 1MHz clock. + 0x1 + + + ENUM_0x2 + Oscillator 32 kHz clock. + 0x2 + + + ENUM_0x3 + No clock. + 0x3 + + + ENUM_0x4 + No clock. + 0x4 + + + ENUM_0x5 + No clock. + 0x5 + + + ENUM_0x6 + No clock. + 0x6 + + + ENUM_0x7 + No clock. + 0x7 + + + + + + + SYSTICKCLKSELX0 + Peripheral reset control register + SYSTICKCLKSEL + 0x260 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + SYSTICKCLKSEL1 + System Tick Timer for CPU1 source select + SYSTICKCLKSEL + 0x264 + 32 + read-write + 0x7 + 0x7 + + + SEL + System Tick Timer for CPU1 source select. + 0 + 3 + read-write + + + ENUM_0x0 + System Tick 1 divided clock. + 0 + + + ENUM_0x1 + FRO 1MHz clock. + 0x1 + + + ENUM_0x2 + Oscillator 32 kHz clock. + 0x2 + + + ENUM_0x3 + No clock. + 0x3 + + + ENUM_0x4 + No clock. + 0x4 + + + ENUM_0x5 + No clock. + 0x5 + + + ENUM_0x6 + No clock. + 0x6 + + + ENUM_0x7 + No clock. + 0x7 + + + + + + + SYSTICKCLKSELX1 + Peripheral reset control register + SYSTICKCLKSEL + 0x264 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + TRACECLKSEL + Trace clock source select + 0x268 + 32 + read-write + 0x7 + 0x7 + + + SEL + Trace clock source select. + 0 + 3 + read-write + + + ENUM_0x0 + Trace divided clock. + 0 + + + ENUM_0x1 + FRO 1MHz clock. + 0x1 + + + ENUM_0x2 + Oscillator 32 kHz clock. + 0x2 + + + ENUM_0x3 + No clock. + 0x3 + + + ENUM_0x4 + No clock. + 0x4 + + + ENUM_0x5 + No clock. + 0x5 + + + ENUM_0x6 + No clock. + 0x6 + + + ENUM_0x7 + No clock. + 0x7 + + + + + + + CTIMERCLKSEL0 + CTimer 0 clock source select + CTIMERCLKSEL + 0x26C + 32 + read-write + 0x7 + 0x7 + + + SEL + CTimer 0 clock source select. + 0 + 3 + read-write + + + ENUM_0x0 + Main clock. + 0 + + + ENUM_0x1 + PLL0 clock. + 0x1 + + + ENUM_0x2 + No clock. + 0x2 + + + ENUM_0x3 + FRO 96 MHz clock. + 0x3 + + + ENUM_0x4 + FRO 1MHz clock. + 0x4 + + + ENUM_0x5 + MCLK clock. + 0x5 + + + ENUM_0x6 + Oscillator 32kHz clock. + 0x6 + + + ENUM_0x7 + No clock. + 0x7 + + + + + + + CTIMERCLKSELX0 + Peripheral reset control register + CTIMERCLKSEL + 0x26C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + CTIMERCLKSEL1 + CTimer 1 clock source select + CTIMERCLKSEL + 0x270 + 32 + read-write + 0x7 + 0x7 + + + SEL + CTimer 1 clock source select. + 0 + 3 + read-write + + + ENUM_0x0 + Main clock. + 0 + + + ENUM_0x1 + PLL0 clock. + 0x1 + + + ENUM_0x2 + No clock. + 0x2 + + + ENUM_0x3 + FRO 96 MHz clock. + 0x3 + + + ENUM_0x4 + FRO 1MHz clock. + 0x4 + + + ENUM_0x5 + MCLK clock. + 0x5 + + + ENUM_0x6 + Oscillator 32kHz clock. + 0x6 + + + ENUM_0x7 + No clock. + 0x7 + + + + + + + CTIMERCLKSELX1 + Peripheral reset control register + CTIMERCLKSEL + 0x270 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + CTIMERCLKSEL2 + CTimer 2 clock source select + CTIMERCLKSEL + 0x274 + 32 + read-write + 0x7 + 0x7 + + + SEL + CTimer 2 clock source select. + 0 + 3 + read-write + + + ENUM_0x0 + Main clock. + 0 + + + ENUM_0x1 + PLL0 clock. + 0x1 + + + ENUM_0x2 + No clock. + 0x2 + + + ENUM_0x3 + FRO 96 MHz clock. + 0x3 + + + ENUM_0x4 + FRO 1MHz clock. + 0x4 + + + ENUM_0x5 + MCLK clock. + 0x5 + + + ENUM_0x6 + Oscillator 32kHz clock. + 0x6 + + + ENUM_0x7 + No clock. + 0x7 + + + + + + + CTIMERCLKSELX2 + Peripheral reset control register + CTIMERCLKSEL + 0x274 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + CTIMERCLKSEL3 + CTimer 3 clock source select + CTIMERCLKSEL + 0x278 + 32 + read-write + 0x7 + 0x7 + + + SEL + CTimer 3 clock source select. + 0 + 3 + read-write + + + ENUM_0x0 + Main clock. + 0 + + + ENUM_0x1 + PLL0 clock. + 0x1 + + + ENUM_0x2 + No clock. + 0x2 + + + ENUM_0x3 + FRO 96 MHz clock. + 0x3 + + + ENUM_0x4 + FRO 1MHz clock. + 0x4 + + + ENUM_0x5 + MCLK clock. + 0x5 + + + ENUM_0x6 + Oscillator 32kHz clock. + 0x6 + + + ENUM_0x7 + No clock. + 0x7 + + + + + + + CTIMERCLKSELX3 + Peripheral reset control register + CTIMERCLKSEL + 0x278 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + CTIMERCLKSEL4 + CTimer 4 clock source select + CTIMERCLKSEL + 0x27C + 32 + read-write + 0x7 + 0x7 + + + SEL + CTimer 4 clock source select. + 0 + 3 + read-write + + + ENUM_0x0 + Main clock. + 0 + + + ENUM_0x1 + PLL0 clock. + 0x1 + + + ENUM_0x2 + No clock. + 0x2 + + + ENUM_0x3 + FRO 96 MHz clock. + 0x3 + + + ENUM_0x4 + FRO 1MHz clock. + 0x4 + + + ENUM_0x5 + MCLK clock. + 0x5 + + + ENUM_0x6 + Oscillator 32kHz clock. + 0x6 + + + ENUM_0x7 + No clock. + 0x7 + + + + + + + CTIMERCLKSELX4 + Peripheral reset control register + CTIMERCLKSEL + 0x27C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + MAINCLKSELA + Main clock A source select + 0x280 + 32 + read-write + 0 + 0x7 + + + SEL + Main clock A source select. + 0 + 3 + read-write + + + ENUM_0x0 + FRO 12 MHz clock. + 0 + + + ENUM_0x1 + CLKIN clock. + 0x1 + + + ENUM_0x2 + FRO 1MHz clock. + 0x2 + + + ENUM_0x3 + FRO 96 MHz clock. + 0x3 + + + ENUM_0x4 + No clock. + 0x4 + + + ENUM_0x5 + No clock. + 0x5 + + + ENUM_0x6 + No clock. + 0x6 + + + ENUM_0x7 + No clock. + 0x7 + + + + + + + MAINCLKSELB + Main clock source select + 0x284 + 32 + read-write + 0 + 0x7 + + + SEL + Main clock source select. + 0 + 3 + read-write + + + ENUM_0x0 + Main Clock A. + 0 + + + ENUM_0x1 + PLL0 clock. + 0x1 + + + ENUM_0x2 + PLL1 clock. + 0x2 + + + ENUM_0x3 + Oscillator 32 kHz clock. + 0x3 + + + ENUM_0x4 + No clock. + 0x4 + + + ENUM_0x5 + No clock. + 0x5 + + + ENUM_0x6 + No clock. + 0x6 + + + ENUM_0x7 + No clock. + 0x7 + + + + + + + CLKOUTSEL + CLKOUT clock source select + 0x288 + 32 + read-write + 0x7 + 0x7 + + + SEL + CLKOUT clock source select. + 0 + 3 + read-write + + + ENUM_0x0 + Main clock. + 0 + + + ENUM_0x1 + PLL0 clock. + 0x1 + + + ENUM_0x2 + CLKIN clock. + 0x2 + + + ENUM_0x3 + FRO 96 MHz clock. + 0x3 + + + ENUM_0x4 + FRO 1MHz clock. + 0x4 + + + ENUM_0x5 + PLL1 clock. + 0x5 + + + ENUM_0x6 + Oscillator 32kHz clock. + 0x6 + + + ENUM_0x7 + No clock. + 0x7 + + + + + + + PLL0CLKSEL + PLL0 clock source select + 0x290 + 32 + read-write + 0x7 + 0x7 + + + SEL + PLL0 clock source select. + 0 + 3 + read-write + + + ENUM_0x0 + FRO 12 MHz clock. + 0 + + + ENUM_0x1 + CLKIN clock. + 0x1 + + + ENUM_0x2 + FRO 1MHz clock. + 0x2 + + + ENUM_0x3 + Oscillator 32kHz clock. + 0x3 + + + ENUM_0x4 + No clock. + 0x4 + + + ENUM_0x5 + No clock. + 0x5 + + + ENUM_0x6 + No clock. + 0x6 + + + ENUM_0x7 + No clock. + 0x7 + + + + + + + PLL1CLKSEL + PLL1 clock source select + 0x294 + 32 + read-write + 0x7 + 0x7 + + + SEL + PLL1 clock source select. + 0 + 3 + read-write + + + ENUM_0x0 + FRO 12 MHz clock. + 0 + + + ENUM_0x1 + CLKIN clock. + 0x1 + + + ENUM_0x2 + FRO 1MHz clock. + 0x2 + + + ENUM_0x3 + Oscillator 32kHz clock. + 0x3 + + + ENUM_0x4 + No clock. + 0x4 + + + ENUM_0x5 + No clock. + 0x5 + + + ENUM_0x6 + No clock. + 0x6 + + + ENUM_0x7 + No clock. + 0x7 + + + + + + + ADCCLKSEL + ADC clock source select + 0x2A4 + 32 + read-write + 0x7 + 0x7 + + + SEL + ADC clock source select. + 0 + 3 + read-write + + + ENUM_0x0 + Main clock. + 0 + + + ENUM_0x1 + PLL0 clock. + 0x1 + + + ENUM_0x2 + FRO 96 MHz clock. + 0x2 + + + ENUM_0x3 + No clock. + 0x3 + + + ENUM_0x4 + No clock. + 0x4 + + + ENUM_0x5 + No clock. + 0x5 + + + ENUM_0x6 + No clock. + 0x6 + + + ENUM_0x7 + No clock. + 0x7 + + + + + + + USB0CLKSEL + FS USB clock source select + 0x2A8 + 32 + read-write + 0x7 + 0x7 + + + SEL + FS USB clock source select. + 0 + 3 + read-write + + + ENUM_0x0 + Main clock. + 0 + + + ENUM_0x1 + PLL0 clock. + 0x1 + + + ENUM_0x2 + No clock. + 0x2 + + + ENUM_0x3 + FRO 96 MHz clock. + 0x3 + + + ENUM_0x4 + No clock. + 0x4 + + + ENUM_0x5 + PLL1 clock. + 0x5 + + + ENUM_0x6 + No clock. + 0x6 + + + ENUM_0x7 + No clock. + 0x7 + + + + + + + USB1CLKSEL + HS USB clock source select - NOT USED + 0x2AC + 32 + read-write + 0x7 + 0x7 + + + SEL + HS USB clock source select. + 0 + 3 + read-write + + + ENUM_0x0 + Main clock. + 0 + + + ENUM_0x1 + PLL0 clock. + 0x1 + + + ENUM_0x2 + CLKIN clock. + 0x2 + + + ENUM_0x3 + No clock. + 0x3 + + + ENUM_0x4 + No clock. + 0x4 + + + ENUM_0x5 + PLL1 clock. + 0x5 + + + ENUM_0x6 + No clock. + 0x6 + + + ENUM_0x7 + No clock. + 0x7 + + + + + + + FCCLKSEL0 + Flexcomm Interface 0 clock source select for Fractional Rate Divider + FCCLKSEL + 0x2B0 + 32 + read-write + 0x7 + 0x7 + + + SEL + Flexcomm Interface 0 clock source select for Fractional Rate Divider. + 0 + 3 + read-write + + + ENUM_0x0 + Main clock. + 0 + + + ENUM_0x1 + system PLL divided clock. + 0x1 + + + ENUM_0x2 + FRO 12 MHz clock. + 0x2 + + + ENUM_0x3 + FRO 96 MHz clock. + 0x3 + + + ENUM_0x4 + FRO 1MHz clock. + 0x4 + + + ENUM_0x5 + MCLK clock. + 0x5 + + + ENUM_0x6 + Oscillator 32 kHz clock. + 0x6 + + + ENUM_0x7 + No clock. + 0x7 + + + + + + + FCCLKSELX0 + Peripheral reset control register + FCCLKSEL + 0x2B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + FCCLKSEL1 + Flexcomm Interface 1 clock source select for Fractional Rate Divider + FCCLKSEL + 0x2B4 + 32 + read-write + 0x7 + 0x7 + + + SEL + Flexcomm Interface 1 clock source select for Fractional Rate Divider. + 0 + 3 + read-write + + + ENUM_0x0 + Main clock. + 0 + + + ENUM_0x1 + system PLL divided clock. + 0x1 + + + ENUM_0x2 + FRO 12 MHz clock. + 0x2 + + + ENUM_0x3 + FRO 96 MHz clock. + 0x3 + + + ENUM_0x4 + FRO 1MHz clock. + 0x4 + + + ENUM_0x5 + MCLK clock. + 0x5 + + + ENUM_0x6 + Oscillator 32 kHz clock. + 0x6 + + + ENUM_0x7 + No clock. + 0x7 + + + + + + + FCCLKSELX1 + Peripheral reset control register + FCCLKSEL + 0x2B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + FCCLKSEL2 + Flexcomm Interface 2 clock source select for Fractional Rate Divider + FCCLKSEL + 0x2B8 + 32 + read-write + 0x7 + 0x7 + + + SEL + Flexcomm Interface 2 clock source select for Fractional Rate Divider. + 0 + 3 + read-write + + + ENUM_0x0 + Main clock. + 0 + + + ENUM_0x1 + system PLL divided clock. + 0x1 + + + ENUM_0x2 + FRO 12 MHz clock. + 0x2 + + + ENUM_0x3 + FRO 96 MHz clock. + 0x3 + + + ENUM_0x4 + FRO 1MHz clock. + 0x4 + + + ENUM_0x5 + MCLK clock. + 0x5 + + + ENUM_0x6 + Oscillator 32 kHz clock. + 0x6 + + + ENUM_0x7 + No clock. + 0x7 + + + + + + + FCCLKSELX2 + Peripheral reset control register + FCCLKSEL + 0x2B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + FCCLKSEL3 + Flexcomm Interface 3 clock source select for Fractional Rate Divider + FCCLKSEL + 0x2BC + 32 + read-write + 0x7 + 0x7 + + + SEL + Flexcomm Interface 3 clock source select for Fractional Rate Divider. + 0 + 3 + read-write + + + ENUM_0x0 + Main clock. + 0 + + + ENUM_0x1 + system PLL divided clock. + 0x1 + + + ENUM_0x2 + FRO 12 MHz clock. + 0x2 + + + ENUM_0x3 + FRO 96 MHz clock. + 0x3 + + + ENUM_0x4 + FRO 1MHz clock. + 0x4 + + + ENUM_0x5 + MCLK clock. + 0x5 + + + ENUM_0x6 + Oscillator 32 kHz clock. + 0x6 + + + ENUM_0x7 + No clock. + 0x7 + + + + + + + FCCLKSELX3 + Peripheral reset control register + FCCLKSEL + 0x2BC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + FCCLKSEL4 + Flexcomm Interface 4 clock source select for Fractional Rate Divider + FCCLKSEL + 0x2C0 + 32 + read-write + 0x7 + 0x7 + + + SEL + Flexcomm Interface 4 clock source select for Fractional Rate Divider. + 0 + 3 + read-write + + + ENUM_0x0 + Main clock. + 0 + + + ENUM_0x1 + system PLL divided clock. + 0x1 + + + ENUM_0x2 + FRO 12 MHz clock. + 0x2 + + + ENUM_0x3 + FRO 96 MHz clock. + 0x3 + + + ENUM_0x4 + FRO 1MHz clock. + 0x4 + + + ENUM_0x5 + MCLK clock. + 0x5 + + + ENUM_0x6 + Oscillator 32 kHz clock. + 0x6 + + + ENUM_0x7 + No clock. + 0x7 + + + + + + + FCCLKSELX4 + Peripheral reset control register + FCCLKSEL + 0x2C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + FCCLKSEL5 + Flexcomm Interface 5 clock source select for Fractional Rate Divider + FCCLKSEL + 0x2C4 + 32 + read-write + 0x7 + 0x7 + + + SEL + Flexcomm Interface 5 clock source select for Fractional Rate Divider. + 0 + 3 + read-write + + + ENUM_0x0 + Main clock. + 0 + + + ENUM_0x1 + system PLL divided clock. + 0x1 + + + ENUM_0x2 + FRO 12 MHz clock. + 0x2 + + + ENUM_0x3 + FRO 96 MHz clock. + 0x3 + + + ENUM_0x4 + FRO 1MHz clock. + 0x4 + + + ENUM_0x5 + MCLK clock. + 0x5 + + + ENUM_0x6 + Oscillator 32 kHz clock. + 0x6 + + + ENUM_0x7 + No clock. + 0x7 + + + + + + + FCCLKSELX5 + Peripheral reset control register + FCCLKSEL + 0x2C4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + FCCLKSEL6 + Flexcomm Interface 6 clock source select for Fractional Rate Divider + FCCLKSEL + 0x2C8 + 32 + read-write + 0x7 + 0x7 + + + SEL + Flexcomm Interface 6 clock source select for Fractional Rate Divider. + 0 + 3 + read-write + + + ENUM_0x0 + Main clock. + 0 + + + ENUM_0x1 + system PLL divided clock. + 0x1 + + + ENUM_0x2 + FRO 12 MHz clock. + 0x2 + + + ENUM_0x3 + FRO 96 MHz clock. + 0x3 + + + ENUM_0x4 + FRO 1MHz clock. + 0x4 + + + ENUM_0x5 + MCLK clock. + 0x5 + + + ENUM_0x6 + Oscillator 32 kHz clock. + 0x6 + + + ENUM_0x7 + No clock. + 0x7 + + + + + + + FCCLKSELX6 + Peripheral reset control register + FCCLKSEL + 0x2C8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + FCCLKSEL7 + Flexcomm Interface 7 clock source select for Fractional Rate Divider + FCCLKSEL + 0x2CC + 32 + read-write + 0x7 + 0x7 + + + SEL + Flexcomm Interface 7 clock source select for Fractional Rate Divider. + 0 + 3 + read-write + + + ENUM_0x0 + Main clock. + 0 + + + ENUM_0x1 + system PLL divided clock. + 0x1 + + + ENUM_0x2 + FRO 12 MHz clock. + 0x2 + + + ENUM_0x3 + FRO 96 MHz clock. + 0x3 + + + ENUM_0x4 + FRO 1MHz clock. + 0x4 + + + ENUM_0x5 + MCLK clock. + 0x5 + + + ENUM_0x6 + Oscillator 32 kHz clock. + 0x6 + + + ENUM_0x7 + No clock. + 0x7 + + + + + + + FCCLKSELX7 + Peripheral reset control register + FCCLKSEL + 0x2CC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + HSLSPICLKSEL + HS LSPI clock source select + 0x2D0 + 32 + read-write + 0x7 + 0x7 + + + SEL + HS LSPI clock source select. + 0 + 3 + read-write + + + ENUM_0x0 + Main clock. + 0 + + + ENUM_0x1 + system PLL divided clock. + 0x1 + + + ENUM_0x2 + FRO 12 MHz clock. + 0x2 + + + ENUM_0x3 + FRO 96 MHz clock. + 0x3 + + + ENUM_0x4 + FRO 1MHz clock. + 0x4 + + + ENUM_0x5 + No clock. + 0x5 + + + ENUM_0x6 + Oscillator 32 kHz clock. + 0x6 + + + ENUM_0x7 + No clock. + 0x7 + + + + + + + MCLKCLKSEL + MCLK clock source select + 0x2E0 + 32 + read-write + 0x7 + 0x7 + + + SEL + MCLK clock source select. + 0 + 3 + read-write + + + ENUM_0x0 + FRO 96 MHz clock. + 0 + + + ENUM_0x1 + PLL0 clock. + 0x1 + + + ENUM_0x2 + No clock. + 0x2 + + + ENUM_0x3 + No clock. + 0x3 + + + ENUM_0x4 + No clock. + 0x4 + + + ENUM_0x5 + No clock. + 0x5 + + + ENUM_0x6 + No clock. + 0x6 + + + ENUM_0x7 + No clock. + 0x7 + + + + + + + SCTCLKSEL + SCTimer/PWM clock source select + 0x2F0 + 32 + read-write + 0x7 + 0x7 + + + SEL + SCTimer/PWM clock source select. + 0 + 3 + read-write + + + ENUM_0x0 + Main clock. + 0 + + + ENUM_0x1 + PLL0 clock. + 0x1 + + + ENUM_0x2 + CLKIN clock. + 0x2 + + + ENUM_0x3 + FRO 96 MHz clock. + 0x3 + + + ENUM_0x4 + No clock. + 0x4 + + + ENUM_0x5 + MCLK clock. + 0x5 + + + ENUM_0x6 + No clock. + 0x6 + + + ENUM_0x7 + No clock. + 0x7 + + + + + + + SDIOCLKSEL + SDIO clock source select + 0x2F8 + 32 + read-write + 0x7 + 0x7 + + + SEL + SDIO clock source select. + 0 + 3 + read-write + + + ENUM_0x0 + Main clock. + 0 + + + ENUM_0x1 + PLL0 clock. + 0x1 + + + ENUM_0x2 + No clock. + 0x2 + + + ENUM_0x3 + FRO 96 MHz clock. + 0x3 + + + ENUM_0x4 + No clock. + 0x4 + + + ENUM_0x5 + PLL1 clock. + 0x5 + + + ENUM_0x6 + No clock. + 0x6 + + + ENUM_0x7 + No clock. + 0x7 + + + + + + + SYSTICKCLKDIV0 + System Tick Timer divider for CPU0 + 0x300 + 32 + read-write + 0x40000000 + 0xE00000FF + + + DIV + Clock divider value. + 0 + 8 + read-write + + + RESET + Resets the divider counter. + 29 + 1 + write-only + + + RELEASED + Divider is not reset. + 0 + + + ASSERTED + Divider is reset. + 0x1 + + + + + HALT + Halts the divider counter. + 30 + 1 + read-write + + + RUN + Divider clock is running. + 0 + + + HALT + Divider clock is stoped. + 0x1 + + + + + REQFLAG + Divider status flag. + 31 + 1 + read-only + + + STABLE + Divider clock is stable. + 0 + + + ONGOING + Clock frequency is not stable. + 0x1 + + + + + + + SYSTICKCLKDIV1 + System Tick Timer divider for CPU1 + 0x304 + 32 + read-write + 0x40000000 + 0xE00000FF + + + DIV + Clock divider value. + 0 + 8 + read-write + + + RESET + Resets the divider counter. + 29 + 1 + write-only + + + RELEASED + Divider is not reset. + 0 + + + ASSERTED + Divider is reset. + 0x1 + + + + + HALT + Halts the divider counter. + 30 + 1 + read-write + + + RUN + Divider clock is running. + 0 + + + HALT + Divider clock is stoped. + 0x1 + + + + + REQFLAG + Divider status flag. + 31 + 1 + read-only + + + STABLE + Divider clock is stable. + 0 + + + ONGOING + Clock frequency is not stable. + 0x1 + + + + + + + TRACECLKDIV + TRACE clock divider + 0x308 + 32 + read-write + 0x40000000 + 0xE00000FF + + + DIV + Clock divider value. + 0 + 8 + read-write + + + RESET + Resets the divider counter. + 29 + 1 + write-only + + + RELEASED + Divider is not reset. + 0 + + + ASSERTED + Divider is reset. + 0x1 + + + + + HALT + Halts the divider counter. + 30 + 1 + read-write + + + RUN + Divider clock is running. + 0 + + + HALT + Divider clock is stoped. + 0x1 + + + + + REQFLAG + Divider status flag. + 31 + 1 + read-only + + + STABLE + Divider clock is stable. + 0 + + + ONGOING + Clock frequency is not stable. + 0x1 + + + + + + + FLEXFRG0CTRL + Fractional rate divider for flexcomm 0 + FLEXFRGCTRL + 0x320 + 32 + read-write + 0xFF + 0xFFFF + + + DIV + Denominator of the fractional rate divider. + 0 + 8 + read-write + + + MULT + Numerator of the fractional rate divider. + 8 + 8 + read-write + + + + + FLEXFRGXCTRL0 + Peripheral reset control register + FLEXFRGCTRL + 0x320 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + FLEXFRG1CTRL + Fractional rate divider for flexcomm 1 + FLEXFRGCTRL + 0x324 + 32 + read-write + 0xFF + 0xFFFF + + + DIV + Denominator of the fractional rate divider. + 0 + 8 + read-write + + + MULT + Numerator of the fractional rate divider. + 8 + 8 + read-write + + + + + FLEXFRGXCTRL1 + Peripheral reset control register + FLEXFRGCTRL + 0x324 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + FLEXFRG2CTRL + Fractional rate divider for flexcomm 2 + FLEXFRGCTRL + 0x328 + 32 + read-write + 0xFF + 0xFFFF + + + DIV + Denominator of the fractional rate divider. + 0 + 8 + read-write + + + MULT + Numerator of the fractional rate divider. + 8 + 8 + read-write + + + + + FLEXFRGXCTRL2 + Peripheral reset control register + FLEXFRGCTRL + 0x328 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + FLEXFRG3CTRL + Fractional rate divider for flexcomm 3 + FLEXFRGCTRL + 0x32C + 32 + read-write + 0xFF + 0xFFFF + + + DIV + Denominator of the fractional rate divider. + 0 + 8 + read-write + + + MULT + Numerator of the fractional rate divider. + 8 + 8 + read-write + + + + + FLEXFRGXCTRL3 + Peripheral reset control register + FLEXFRGCTRL + 0x32C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + FLEXFRG4CTRL + Fractional rate divider for flexcomm 4 + FLEXFRGCTRL + 0x330 + 32 + read-write + 0xFF + 0xFFFF + + + DIV + Denominator of the fractional rate divider. + 0 + 8 + read-write + + + MULT + Numerator of the fractional rate divider. + 8 + 8 + read-write + + + + + FLEXFRGXCTRL4 + Peripheral reset control register + FLEXFRGCTRL + 0x330 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + FLEXFRG5CTRL + Fractional rate divider for flexcomm 5 + FLEXFRGCTRL + 0x334 + 32 + read-write + 0xFF + 0xFFFF + + + DIV + Denominator of the fractional rate divider. + 0 + 8 + read-write + + + MULT + Numerator of the fractional rate divider. + 8 + 8 + read-write + + + + + FLEXFRGXCTRL5 + Peripheral reset control register + FLEXFRGCTRL + 0x334 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + FLEXFRG6CTRL + Fractional rate divider for flexcomm 6 + FLEXFRGCTRL + 0x338 + 32 + read-write + 0xFF + 0xFFFF + + + DIV + Denominator of the fractional rate divider. + 0 + 8 + read-write + + + MULT + Numerator of the fractional rate divider. + 8 + 8 + read-write + + + + + FLEXFRGXCTRL6 + Peripheral reset control register + FLEXFRGCTRL + 0x338 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + FLEXFRG7CTRL + Fractional rate divider for flexcomm 7 + FLEXFRGCTRL + 0x33C + 32 + read-write + 0xFF + 0xFFFF + + + DIV + Denominator of the fractional rate divider. + 0 + 8 + read-write + + + MULT + Numerator of the fractional rate divider. + 8 + 8 + read-write + + + + + FLEXFRGXCTRL7 + Peripheral reset control register + FLEXFRGCTRL + 0x33C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + AHBCLKDIV + System clock divider + 0x380 + 32 + read-write + 0 + 0xE00000FF + + + DIV + Clock divider value. + 0 + 8 + read-write + + + RESET + Resets the divider counter. + 29 + 1 + write-only + + + RELEASED + Divider is not reset. + 0 + + + ASSERTED + Divider is reset. + 0x1 + + + + + HALT + Halts the divider counter. + 30 + 1 + read-write + + + RUN + Divider clock is running. + 0 + + + HALT + Divider clock is stoped. + 0x1 + + + + + REQFLAG + Divider status flag. + 31 + 1 + read-only + + + STABLE + Divider clock is stable. + 0 + + + ONGOING + Clock frequency is not stable. + 0x1 + + + + + + + CLKOUTDIV + CLKOUT clock divider + 0x384 + 32 + read-write + 0x40000000 + 0xE00000FF + + + DIV + Clock divider value. + 0 + 8 + read-write + + + RESET + Resets the divider counter. + 29 + 1 + write-only + + + RELEASED + Divider is not reset. + 0 + + + ASSERTED + Divider is reset. + 0x1 + + + + + HALT + Halts the divider counter. + 30 + 1 + read-write + + + RUN + Divider clock is running. + 0 + + + HALT + Divider clock is stoped. + 0x1 + + + + + REQFLAG + Divider status flag. + 31 + 1 + read-only + + + STABLE + Divider clock is stable. + 0 + + + ONGOING + Clock frequency is not stable. + 0x1 + + + + + + + FROHFDIV + FRO_HF (96MHz) clock divider + 0x388 + 32 + read-write + 0x40000000 + 0xE00000FF + + + DIV + Clock divider value. + 0 + 8 + read-write + + + RESET + Resets the divider counter. + 29 + 1 + write-only + + + RELEASED + Divider is not reset. + 0 + + + ASSERTED + Divider is reset. + 0x1 + + + + + HALT + Halts the divider counter. + 30 + 1 + read-write + + + RUN + Divider clock is running. + 0 + + + HALT + Divider clock is stoped. + 0x1 + + + + + REQFLAG + Divider status flag. + 31 + 1 + read-only + + + STABLE + Divider clock is stable. + 0 + + + ONGOING + Clock frequency is not stable. + 0x1 + + + + + + + WDTCLKDIV + WDT clock divider + 0x38C + 32 + read-write + 0x40000000 + 0xE000003F + + + DIV + Clock divider value. + 0 + 6 + read-write + + + RESET + Resets the divider counter. + 29 + 1 + write-only + + + RELEASED + Divider is not reset. + 0 + + + ASSERTED + Divider is reset. + 0x1 + + + + + HALT + Halts the divider counter. + 30 + 1 + read-write + + + RUN + Divider clock is running. + 0 + + + HALT + Divider clock is stoped. + 0x1 + + + + + REQFLAG + Divider status flag. + 31 + 1 + read-only + + + STABLE + Divider clock is stable. + 0 + + + ONGOING + Clock frequency is not stable. + 0x1 + + + + + + + ADCCLKDIV + ADC clock divider + 0x394 + 32 + read-write + 0x40000000 + 0xE0000007 + + + DIV + Clock divider value. + 0 + 3 + read-write + + + RESET + Resets the divider counter. + 29 + 1 + write-only + + + RELEASED + Divider is not reset. + 0 + + + ASSERTED + Divider is reset. + 0x1 + + + + + HALT + Halts the divider counter. + 30 + 1 + read-write + + + RUN + Divider clock is running. + 0 + + + HALT + Divider clock is stoped. + 0x1 + + + + + REQFLAG + Divider status flag. + 31 + 1 + read-only + + + STABLE + Divider clock is stable. + 0 + + + ONGOING + Clock frequency is not stable. + 0x1 + + + + + + + USB0CLKDIV + USB0 Clock divider + 0x398 + 32 + read-write + 0x40000000 + 0xE00000FF + + + DIV + Clock divider value. + 0 + 8 + read-write + + + RESET + Resets the divider counter. + 29 + 1 + write-only + + + RELEASED + Divider is not reset. + 0 + + + ASSERTED + Divider is reset. + 0x1 + + + + + HALT + Halts the divider counter. + 30 + 1 + read-write + + + RUN + Divider clock is running. + 0 + + + HALT + Divider clock is stoped. + 0x1 + + + + + REQFLAG + Divider status flag. + 31 + 1 + read-only + + + STABLE + Divider clock is stable. + 0 + + + ONGOING + Clock frequency is not stable. + 0x1 + + + + + + + MCLKDIV + I2S MCLK clock divider + 0x3AC + 32 + read-write + 0x40000000 + 0xE00000FF + + + DIV + Clock divider value. + 0 + 8 + read-write + + + RESET + Resets the divider counter. + 29 + 1 + write-only + + + RELEASED + Divider is not reset. + 0 + + + ASSERTED + Divider is reset. + 0x1 + + + + + HALT + Halts the divider counter. + 30 + 1 + read-write + + + RUN + Divider clock is running. + 0 + + + HALT + Divider clock is stoped. + 0x1 + + + + + REQFLAG + Divider status flag. + 31 + 1 + read-only + + + STABLE + Divider clock is stable. + 0 + + + ONGOING + Clock frequency is not stable. + 0x1 + + + + + + + SCTCLKDIV + SCT/PWM clock divider + 0x3B4 + 32 + read-write + 0x40000000 + 0xE00000FF + + + DIV + Clock divider value. + 0 + 8 + read-write + + + RESET + Resets the divider counter. + 29 + 1 + write-only + + + RELEASED + Divider is not reset. + 0 + + + ASSERTED + Divider is reset. + 0x1 + + + + + HALT + Halts the divider counter. + 30 + 1 + read-write + + + RUN + Divider clock is running. + 0 + + + HALT + Divider clock is stoped. + 0x1 + + + + + REQFLAG + Divider status flag. + 31 + 1 + read-only + + + STABLE + Divider clock is stable. + 0 + + + ONGOING + Clock frequency is not stable. + 0x1 + + + + + + + SDIOCLKDIV + SDIO clock divider + 0x3BC + 32 + read-write + 0x40000000 + 0xE00000FF + + + DIV + Clock divider value. + 0 + 8 + read-write + + + RESET + Resets the divider counter. + 29 + 1 + write-only + + + RELEASED + Divider is not reset. + 0 + + + ASSERTED + Divider is reset. + 0x1 + + + + + HALT + Halts the divider counter. + 30 + 1 + read-write + + + RUN + Divider clock is running. + 0 + + + HALT + Divider clock is stoped. + 0x1 + + + + + REQFLAG + Divider status flag. + 31 + 1 + read-only + + + STABLE + Divider clock is stable. + 0 + + + ONGOING + Clock frequency is not stable. + 0x1 + + + + + + + PLL0CLKDIV + PLL0 clock divider + 0x3C4 + 32 + read-write + 0x40000000 + 0xE00000FF + + + DIV + Clock divider value. + 0 + 8 + read-write + + + RESET + Resets the divider counter. + 29 + 1 + write-only + + + RELEASED + Divider is not reset. + 0 + + + ASSERTED + Divider is reset. + 0x1 + + + + + HALT + Halts the divider counter. + 30 + 1 + read-write + + + RUN + Divider clock is running. + 0 + + + HALT + Divider clock is stoped. + 0x1 + + + + + REQFLAG + Divider status flag. + 31 + 1 + read-only + + + STABLE + Divider clock is stable. + 0 + + + ONGOING + Clock frequency is not stable. + 0x1 + + + + + + + CLOCKGENUPDATELOCKOUT + Control clock configuration registers access (like xxxDIV, xxxSEL) + 0x3FC + 32 + read-write + 0 + 0xFFFFFFFF + + + CLOCKGENUPDATELOCKOUT + Control clock configuration registers access (like xxxDIV, xxxSEL). + 0 + 32 + read-write + + + FREEZE + all hardware clock configruration are freeze. + 0 + + + ENABLE + update all clock configuration. + 0x1 + + + + + + + FMCCR + FMC configuration register - INTERNAL USE ONLY + 0x400 + 32 + read-write + 0x3000 + 0xFFFFFFFF + + + FETCHCTL + Fetch control + 0 + 2 + read-write + + + NOBUF + No buffering (bypass always used) for Fetch cycles + 0 + + + ONEBUF + One buffer is used for all Fetch cycles + 0x1 + + + ALLBUF + All buffers can be used for Fetch cycles + 0x2 + + + + + DATACTL + Data control + 2 + 2 + read-write + + + NOBUF + No buffering (bypass always used) for Data cycles + 0 + + + ONEBUF + One buffer is used for all Data cycles + 0x1 + + + ALLBUF + All buffers can be used for Data cycles + 0x2 + + + + + ACCEL + ACCEL + 4 + 1 + read-write + + + PREFEN + Pref enable + 5 + 1 + read-write + + + PREFOVR + Pref ovr + 6 + 1 + read-write + + + PREFCRI + Pref CRI + 8 + 3 + read-write + + + FMCTIM + TMC time + 12 + 5 + read-write + + + PFISLRU + When set, prefetch uses LRU buffer replacement policy + 17 + 1 + read-write + + + PFADAP + When set, prefetch will adaptively select between parent and LRU buffer replacement policies. + 18 + 1 + read-write + + + + + USB0CLKCTRL + USB0 clock control + 0x40C + 32 + read-write + 0 + 0x1F + + + AP_FS_DEV_CLK + USB0 Device USB0_NEEDCLK signal control:. + 0 + 1 + read-write + + + HW_CTRL + Under hardware control. + 0 + + + FORCED + Forced high. + 0x1 + + + + + POL_FS_DEV_CLK + USB0 Device USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt:. + 1 + 1 + read-write + + + FALLING + Falling edge of device USB0_NEEDCLK triggers wake-up. + 0 + + + RISING + Rising edge of device USB0_NEEDCLK triggers wake-up. + 0x1 + + + + + AP_FS_HOST_CLK + USB0 Host USB0_NEEDCLK signal control:. + 2 + 1 + read-write + + + HW_CTRL + Under hardware control. + 0 + + + FORCED + Forced high. + 0x1 + + + + + POL_FS_HOST_CLK + USB0 Host USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt:. + 3 + 1 + read-write + + + FALLING + Falling edge of device USB0_NEEDCLK triggers wake-up. + 0 + + + RISING + Rising edge of device USB0_NEEDCLK triggers wake-up. + 0x1 + + + + + PU_DISABLE + Internal pull-up disable control. + 4 + 1 + read-write + + + ENABLE + Internal pull-up enable. + 0 + + + DISABLE + Internal pull-up disable. + 0x1 + + + + + + + USB0CLKSTAT + USB0 clock status + 0x410 + 32 + read-write + 0 + 0x3 + + + DEV_NEED_CLKST + USB0 Device USB0_NEEDCLK signal status:. + 0 + 1 + read-only + + + LOW + USB0 Device clock is low. + 0 + + + HIGH + USB0 Device clock is high. + 0x1 + + + + + HOST_NEED_CLKST + USB0 Host USB0_NEEDCLK signal status:. + 1 + 1 + read-only + + + LOW + USB0 Host clock is low. + 0 + + + HIGH + USB0 Host clock is high. + 0x1 + + + + + + + FMCFLUSH + FMCflush control + 0x41C + 32 + write-only + 0 + 0xFFFFFFFF + + + FLUSH + no description available + 0 + 1 + write-only + + + + + MCLKIO + MCLK control + 0x420 + 32 + read-write + 0 + 0xFFFFFFFF + + + MCLKIO + MCLK control. + 0 + 32 + read-write + + + INPUT + input mode. + 0 + + + OUTPUT + output mode. + 0x1 + + + + + + + USB1CLKCTRL + USB1 clock control + 0x424 + 32 + read-write + 0x10 + 0x1F + + + AP_HS_DEV_CLK + USB1 Device need_clock signal control:. + 0 + 1 + read-write + + + HW_CTRL + Under hardware control. + 0 + + + FORCED + Forced high. + 0x1 + + + + + POL_HS_DEV_CLK + USB1 Device need_clock polarity for triggering the USB1 wake-up interrupt:. + 1 + 1 + read-write + + + FALLING + Falling edge of device need_clock triggers wake-up. + 0 + + + RISING + Rising edge of device need_clock triggers wake-up. + 0x1 + + + + + AP_HS_HOST_CLK + USB1 Host need_clock signal control:. + 2 + 1 + read-write + + + HW_CTRL + Under hardware control. + 0 + + + FORCED + Forced high. + 0x1 + + + + + POL_HS_HOST_CLK + USB1 Host need_clock polarity for triggering the USB1 wake-up interrupt: 0 Falling edge of device need_clock triggers wake-up. + 3 + 1 + read-write + + + FALLING + Falling edge of device need_clock triggers wake-up. + 0 + + + RISING + Rising edge of device need_clock triggers wake-up. + 0x1 + + + + + HS_DEV_WAKEUP_N + External user wake-up signal for device mode; asserting this signal (active low) will result in exiting the low power mode; input to synchronous control logic:. + 4 + 1 + read-write + + + FORCE_WUP + Forces USB1 PHY to wake-up. + 0 + + + NORMAL_WUP + Normal USB1 PHY behavior. + 0x1 + + + + + + + USB1CLKSTAT + USB1 clock status + 0x428 + 32 + read-write + 0 + 0x3 + + + DEV_NEED_CLKST + USB1 Device need_clock signal status:. + 0 + 1 + read-only + + + LOW + USB1 Device clock is low. + 0 + + + HIGH + USB1 Device clock is high. + 0x1 + + + + + HOST_NEED_CLKST + USB1 Host need_clock signal status:. + 1 + 1 + read-only + + + LOW + USB1 Host clock is low. + 0 + + + HIGH + USB1 Host clock is high. + 0x1 + + + + + + + FLASHBANKENABLE + Flash Banks control + 0x450 + 32 + read-write + 0 + 0xFFF + + + BANK0 + Flash Bank0 control. + 0 + 4 + read-write + + + ENABLE + Flash BANK0 checker is enabled (all Flash pages inside this bank cannot be erased nor programmed). + 0 + + + DISABLE + 1010: Flash BANK0 checker is disabled (all Flash pages inside this bank can be erased and programmed). + 0xA + + + + + BANK1 + Flash Bank1 control. + 4 + 4 + read-write + + + ENABLE + Flash BANK1 checker is enabled (all Flash pages inside this bank cannot be erased nor programmed). + 0 + + + DISABLE + 1010: Flash BANK1 checker is disabled (all Flash pages inside this bank can be erased and programmed). + 0xA + + + + + BANK2 + Flash Bank2 control. + 8 + 4 + read-write + + + ENABLE + Flash BANK2 checker is enabled (all Flash pages inside this bank cannot be erased nor programmed). + 0 + + + DISABLE + 1010: Flash BANK2 checker is disabled (all Flash pages inside this bank can be erased and programmed). + 0xA + + + + + + + SDIOCLKCTRL + SDIO CCLKIN phase and delay control + 0x460 + 32 + read-write + 0 + 0x9F9F008F + + + CCLK_DRV_PHASE + Programmable delay value by which cclk_in_drv is phase-shifted with regard to cclk_in. + 0 + 2 + read-write + + + ENUM_0_DEG + 0 degree shift. + 0 + + + ENUM_90_DEG + 90 degree shift. + 0x1 + + + ENUM_180_DEG + 180 degree shift. + 0x2 + + + ENUM_270_DEG + 270 degree shift. + 0x3 + + + + + CCLK_SAMPLE_PHASE + Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in. + 2 + 2 + read-write + + + ENUM_0_DEG + 0 degree shift. + 0 + + + ENUM_90_DEG + 90 degree shift. + 0x1 + + + ENUM_180_DEG + 180 degree shift. + 0x2 + + + ENUM_270_DEG + 270 degree shift. + 0x3 + + + + + PHASE_ACTIVE + Enables the delays CCLK_DRV_PHASE and CCLK_SAMPLE_PHASE. + 7 + 1 + read-write + + + BYPASSED + Bypassed. + 0 + + + PH_SHIFT + Activates phase shift logic. When active, the clock divider is active and phase delays are enabled. + 0x1 + + + + + CCLK_DRV_DELAY + Programmable delay value by which cclk_in_drv is delayed with regard to cclk_in. + 16 + 5 + read-write + + + CCLK_DRV_DELAY_ACTIVE + Enables drive delay, as controlled by the CCLK_DRV_DELAY field. + 23 + 1 + read-write + + + DISABLE + Disable drive delay. + 0 + + + ENABLE + Enable drive delay. + 0x1 + + + + + CCLK_SAMPLE_DELAY + Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in. + 24 + 5 + read-write + + + CCLK_SAMPLE_DELAY_ACTIVE + Enables sample delay, as controlled by the CCLK_SAMPLE_DELAY field. + 31 + 1 + read-write + + + DISABLE + Disables sample delay. + 0 + + + ENABLE + Enables sample delay. + 0x1 + + + + + + + PLL1CTRL + PLL1 550m control + 0x560 + 32 + read-write + 0 + 0x1FFFFFF + + + SELR + Bandwidth select R value. + 0 + 4 + read-write + + + SELI + Bandwidth select I value. + 4 + 6 + read-write + + + SELP + Bandwidth select P value. + 10 + 5 + read-write + + + BYPASSPLL + Bypass PLL input clock is sent directly to the PLL output (default). + 15 + 1 + read-write + + + USED + use PLL. + 0 + + + BYPASSED + PLL input clock is sent directly to the PLL output. + 0x1 + + + + + BYPASSPOSTDIV2 + bypass of the divide-by-2 divider in the post-divider. + 16 + 1 + read-write + + + USED + use the divide-by-2 divider in the post-divider. + 0 + + + BYPASSED + bypass of the divide-by-2 divider in the post-divider. + 0x1 + + + + + LIMUPOFF + limup_off = 1 in spread spectrum and fractional PLL applications. + 17 + 1 + read-write + + + BWDIRECT + control of the bandwidth of the PLL. + 18 + 1 + read-write + + + SYNC + the bandwidth is changed synchronously with the feedback-divider. + 0 + + + DIRECT + modify the bandwidth of the PLL directly. + 0x1 + + + + + BYPASSPREDIV + bypass of the pre-divider. + 19 + 1 + read-write + + + USED + use the pre-divider. + 0 + + + BYPASSED + bypass of the pre-divider. + 0x1 + + + + + BYPASSPOSTDIV + bypass of the post-divider. + 20 + 1 + read-write + + + USED + use the post-divider. + 0 + + + BYPASSED + bypass of the post-divider. + 0x1 + + + + + CLKEN + enable the output clock. + 21 + 1 + read-write + + + DISABLE + Disable the output clock. + 0 + + + ENABLE + Enable the output clock. + 0x1 + + + + + FRMEN + 1: free running mode. + 22 + 1 + read-write + + + FRMCLKSTABLE + free running mode clockstable: Warning: Only make frm_clockstable = 1 after the PLL output frequency is stable. + 23 + 1 + read-write + + + SKEWEN + Skew mode. + 24 + 1 + read-write + + + DISABLE + skewmode is disable. + 0 + + + ENABLE + skewmode is enable. + 0x1 + + + + + + + PLL1STAT + PLL1 550m status + 0x564 + 32 + read-write + 0 + 0x1F + + + LOCK + lock detector output (active high) Warning: The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. + 0 + 1 + read-only + + + PREDIVACK + pre-divider ratio change acknowledge. + 1 + 1 + read-only + + + FEEDDIVACK + feedback divider ratio change acknowledge. + 2 + 1 + read-only + + + POSTDIVACK + post-divider ratio change acknowledge. + 3 + 1 + read-only + + + FRMDET + free running detector output (active high). + 4 + 1 + read-only + + + + + PLL1NDEC + PLL1 550m N divider + 0x568 + 32 + read-write + 0 + 0x1FF + + + NDIV + pre-divider divider ratio (N-divider). + 0 + 8 + read-write + + + NREQ + pre-divider ratio change request. + 8 + 1 + read-write + + + + + PLL1MDEC + PLL1 550m M divider + 0x56C + 32 + read-write + 0 + 0x1FFFF + + + MDIV + feedback divider divider ratio (M-divider). + 0 + 16 + read-write + + + MREQ + feedback ratio change request. + 16 + 1 + read-write + + + + + PLL1PDEC + PLL1 550m P divider + 0x570 + 32 + read-write + 0 + 0x3F + + + PDIV + post-divider divider ratio (P-divider) + 0 + 5 + read-write + + + PREQ + feedback ratio change request. + 5 + 1 + read-write + + + + + PLL0CTRL + PLL0 550m control + 0x580 + 32 + read-write + 0 + 0x1FFFFFF + + + SELR + Bandwidth select R value. + 0 + 4 + read-write + + + SELI + Bandwidth select I value. + 4 + 6 + read-write + + + SELP + Bandwidth select P value. + 10 + 5 + read-write + + + BYPASSPLL + Bypass PLL input clock is sent directly to the PLL output (default). + 15 + 1 + read-write + + + USED + use PLL. + 0 + + + BYPASSED + Bypass PLL input clock is sent directly to the PLL output. + 0x1 + + + + + BYPASSPOSTDIV2 + bypass of the divide-by-2 divider in the post-divider. + 16 + 1 + read-write + + + USED + use the divide-by-2 divider in the post-divider. + 0 + + + BYPASSED + bypass of the divide-by-2 divider in the post-divider. + 0x1 + + + + + LIMUPOFF + limup_off = 1 in spread spectrum and fractional PLL applications. + 17 + 1 + read-write + + + BWDIRECT + Control of the bandwidth of the PLL. + 18 + 1 + read-write + + + SYNC + the bandwidth is changed synchronously with the feedback-divider. + 0 + + + DIRECT + modify the bandwidth of the PLL directly. + 0x1 + + + + + BYPASSPREDIV + bypass of the pre-divider. + 19 + 1 + read-write + + + USED + use the pre-divider. + 0 + + + BYPASSED + bypass of the pre-divider. + 0x1 + + + + + BYPASSPOSTDIV + bypass of the post-divider. + 20 + 1 + read-write + + + USED + use the post-divider. + 0 + + + BYPASSED + bypass of the post-divider. + 0x1 + + + + + CLKEN + enable the output clock. + 21 + 1 + read-write + + + DISABLE + disable the output clock. + 0 + + + ENABLE + enable the output clock. + 0x1 + + + + + FRMEN + free running mode. + 22 + 1 + read-write + + + DISABLE + free running mode is disable. + 0 + + + ENABLE + free running mode is enable. + 0x1 + + + + + FRMCLKSTABLE + free running mode clockstable: Warning: Only make frm_clockstable =1 after the PLL output frequency is stable. + 23 + 1 + read-write + + + SKEWEN + skew mode. + 24 + 1 + read-write + + + DISABLE + skew mode is disable. + 0 + + + ENABLE + skew mode is enable. + 0x1 + + + + + + + PLL0STAT + PLL0 550m status + 0x584 + 32 + read-write + 0 + 0x1F + + + LOCK + lock detector output (active high) Warning: The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. + 0 + 1 + read-only + + + PREDIVACK + pre-divider ratio change acknowledge. + 1 + 1 + read-only + + + FEEDDIVACK + feedback divider ratio change acknowledge. + 2 + 1 + read-only + + + POSTDIVACK + post-divider ratio change acknowledge. + 3 + 1 + read-only + + + FRMDET + free running detector output (active high). + 4 + 1 + read-only + + + + + PLL0NDEC + PLL0 550m N divider + 0x588 + 32 + read-write + 0 + 0x1FF + + + NDIV + pre-divider divider ratio (N-divider). + 0 + 8 + read-write + + + NREQ + pre-divider ratio change request. + 8 + 1 + read-write + + + + + PLL0PDEC + PLL0 550m P divider + 0x58C + 32 + read-write + 0 + 0x3F + + + PDIV + post-divider divider ratio (P-divider) + 0 + 5 + read-write + + + PREQ + feedback ratio change request. + 5 + 1 + read-write + + + + + PLL0SSCG0 + PLL0 Spread Spectrum Wrapper control register 0 + 0x590 + 32 + read-write + 0 + 0xFFFFFFFF + + + MD_LBS + input word of the wrapper bit 31 to 0. + 0 + 32 + read-write + + + + + PLL0SSCG1 + PLL0 Spread Spectrum Wrapper control register 1 + 0x594 + 32 + read-write + 0 + 0x1FFFFFFF + + + MD_MBS + input word of the wrapper bit 32. + 0 + 1 + read-write + + + MD_REQ + md change request. + 1 + 1 + read-write + + + MF + programmable modulation frequency fm = Fref/Nss mf[2:0] = 000 => Nss=512 (fm ~ 3. + 2 + 3 + read-write + + + MR + programmable frequency modulation depth Dfmodpk-pk = Fref*kss/Fcco = kss/(2*md[32:25]dec) mr[2:0] = 000 => kss = 0 (no spread spectrum) mr[2:0] = 001 => kss ~ 1 mr[2:0] = 010 => kss ~ 1. + 5 + 3 + read-write + + + MC + modulation waveform control Compensation for low pass filtering of the PLL to get a triangular modulation at the output of the PLL, giving a flat frequency spectrum. + 8 + 2 + read-write + + + MDIV_EXT + to select an external mdiv value. + 10 + 16 + read-write + + + MREQ + to select an external mreq value. + 26 + 1 + read-write + + + DITHER + dithering between two modulation frequencies in a random way or in a pseudo random way (white noise), in order to decrease the probability that the modulated waveform will occur with the same phase on a particular point on the screen. + 27 + 1 + read-write + + + SEL_EXT + to select mdiv_ext and mreq_ext sel_ext = 0: mdiv ~ md[32:0], mreq = 1 sel_ext = 1 : mdiv = mdiv_ext, mreq = mreq_ext. + 28 + 1 + read-write + + + + + EFUSECLKCTRL + eFUSE controller clock enable + 0x5CC + 32 + read-write + 0x1 + 0xFFFFFFFF + + + EFUSECLKENA + eFUSE controller clock enable. + 0 + 1 + read-write + + + + + STARTER0 + Start logic wake-up enable register + 0x680 + 32 + read-write + 0 + 0xF97FFFFF + + + SYS + SYS interrupt wake-up. + 0 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + SDMA0 + SDMA0 interrupt wake-up. + 1 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + GINT0 + GINT0 interrupt wake-up. + 2 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + GINT1 + GINT1 interrupt wake-up. + 3 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + PIO_INT0 + PIO_INT0 interrupt wake-up. + 4 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + PIO_INT1 + PIO_INT1 interrupt wake-up. + 5 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + PIO_INT2 + PIO_INT2 interrupt wake-up. + 6 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + PIO_INT3 + PIO_INT3 interrupt wake-up. + 7 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + UTICK0 + UTICK0 interrupt wake-up. + 8 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + MRT0 + MRT0 interrupt wake-up. + 9 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + CTIMER0 + CTIMER0 interrupt wake-up. + 10 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + CTIMER1 + CTIMER1 interrupt wake-up. + 11 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + SCT0 + SCT0 interrupt wake-up. + 12 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + CTIMER3 + CTIMER3 interrupt wake-up. + 13 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + FLEXINT0 + FLEXINT0 interrupt wake-up. + 14 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + FLEXINT1 + FLEXINT1 interrupt wake-up. + 15 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + FLEXINT2 + FLEXINT2 interrupt wake-up. + 16 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + FLEXINT3 + FLEXINT3 interrupt wake-up. + 17 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + FLEXINT4 + FLEXINT4 interrupt wake-up. + 18 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + FLEXINT5 + FLEXINT5 interrupt wake-up. + 19 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + FLEXINT6 + FLEXINT6 interrupt wake-up. + 20 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + FLEXINT7 + FLEXINT7 interrupt wake-up. + 21 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + ADC0 + ADC0 interrupt wake-up. + 22 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + ADC0_THCMP_OVR + ADC0_THCMP_OVR interrupt wake-up. + 24 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + USB0_NEEDCLK + USB0_NEEDCLK interrupt wake-up. + 27 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + USB0 + USB0 interrupt wake-up. + 28 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + RTC_LITE0 + RTC_LITE0 interrupt wake-up. + 29 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + EZH_ARCH_B0 + EZH_ARCH_B0 interrupt wake-up. + 30 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + WAKEUP_MAILBOX0 + WAKEUP_MAILBOX0 interrupt wake-up. + 31 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + + + STARTER1 + Start logic wake-up enable register + 0x684 + 32 + read-write + 0 + 0xFFFF847F + + + GPIO_INT04 + GPIO_INT04 interrupt wake-up. + 0 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + GPIO_INT05 + GPIO_INT05 interrupt wake-up. + 1 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + GPIO_INT06 + GPIO_INT06 interrupt wake-up. + 2 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + GPIO_INT07 + GPIO_INT07 interrupt wake-up. + 3 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + CTIMER2 + CTIMER2 interrupt wake-up. + 4 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + CTIMER4 + CTIMER4 interrupt wake-up. + 5 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + OS_EVENT + OS_EVENT interrupt wake-up. + 6 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + SDIO + SDIO interrupt wake-up. + 10 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + USB1 + USB1 interrupt wake-up. + 15 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + USB1_NEEDCLK + USB1_NEEDCLK interrupt wake-up. + 16 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + SEC_HYPERVISOR_CALL + SEC_HYPERVISOR_CALL interrupt wake-up. + 17 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + SEC_GPIO_INT00 + SEC_GPIO_INT00 interrupt wake-up. + 18 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + SEC_GPIO_INT01 + SEC_GPIO_INT01 interrupt wake-up. + 19 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + PLU + PLU interrupt wake-up. + 20 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + SEC_VIO + SEC_VIO interrupt wake-up. + 21 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + SHA + SHA interrupt wake-up. + 22 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + CASER + CASER interrupt wake-up. + 23 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + QDDKEY + QDDKEY interrupt wake-up. + 24 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + PQ + PQ interrupt wake-up. + 25 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + SDMA1 + SDMA1 interrupt wake-up. + 26 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + LSPI_HS + LSPI_HS interrupt wake-up. + 27 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + WAKEUPPADS + WAKEUPPADS interrupt wake-up. + 31 + 1 + read-write + + + + + STARTERSET0 + Set bits in STARTER + 0x6A0 + 32 + write-only + 0 + 0xF97FFFFF + + + SYS_SET + Writing ones to this register sets the corresponding bit in the STARTER0 register. + 0 + 1 + write-only + + + SDMA0_SET + Writing ones to this register sets the corresponding bit in the STARTER0 register. + 1 + 1 + write-only + + + GPIO_GLOBALINT0_SET + Writing ones to this register sets the corresponding bit in the STARTER0 register. + 2 + 1 + write-only + + + GPIO_GLOBALINT1_SET + Writing ones to this register sets the corresponding bit in the STARTER0 register. + 3 + 1 + write-only + + + GPIO_INT00_SET + Writing ones to this register sets the corresponding bit in the STARTER0 register. + 4 + 1 + write-only + + + GPIO_INT01_SET + Writing ones to this register sets the corresponding bit in the STARTER0 register. + 5 + 1 + write-only + + + GPIO_INT02_SET + Writing ones to this register sets the corresponding bit in the STARTER0 register. + 6 + 1 + write-only + + + GPIO_INT03_SET + Writing ones to this register sets the corresponding bit in the STARTER0 register. + 7 + 1 + write-only + + + UTICK0_SET + Writing ones to this register sets the corresponding bit in the STARTER0 register. + 8 + 1 + write-only + + + MRT0_SET + Writing ones to this register sets the corresponding bit in the STARTER0 register. + 9 + 1 + write-only + + + CTIMER0_SET + Writing ones to this register sets the corresponding bit in the STARTER0 register. + 10 + 1 + write-only + + + CTIMER1_SET + Writing ones to this register sets the corresponding bit in the STARTER0 register. + 11 + 1 + write-only + + + SCT0_SET + Writing ones to this register sets the corresponding bit in the STARTER0 register. + 12 + 1 + write-only + + + CTIMER3_SET + Writing ones to this register sets the corresponding bit in the STARTER0 register. + 13 + 1 + write-only + + + FLEXINT0_SET + Writing ones to this register sets the corresponding bit in the STARTER0 register. + 14 + 1 + write-only + + + FLEXINT1_SET + Writing ones to this register sets the corresponding bit in the STARTER0 register. + 15 + 1 + write-only + + + FLEXINT2_SET + Writing ones to this register sets the corresponding bit in the STARTER0 register. + 16 + 1 + write-only + + + FLEXINT3_SET + Writing ones to this register sets the corresponding bit in the STARTER0 register. + 17 + 1 + write-only + + + FLEXINT4_SET + Writing ones to this register sets the corresponding bit in the STARTER0 register. + 18 + 1 + write-only + + + FLEXINT5_SET + Writing ones to this register sets the corresponding bit in the STARTER0 register. + 19 + 1 + write-only + + + FLEXINT6_SET + Writing ones to this register sets the corresponding bit in the STARTER0 register. + 20 + 1 + write-only + + + FLEXINT7_SET + Writing ones to this register sets the corresponding bit in the STARTER0 register. + 21 + 1 + write-only + + + ADC0_SET + Writing ones to this register sets the corresponding bit in the STARTER0 register. + 22 + 1 + write-only + + + ADC0_THCMP_OVR_SET + Writing ones to this register sets the corresponding bit in the STARTER0 register. + 24 + 1 + write-only + + + USB0_NEEDCLK_SET + Writing ones to this register sets the corresponding bit in the STARTER0 register. + 27 + 1 + write-only + + + USB0_SET + Writing ones to this register sets the corresponding bit in the STARTER0 register. + 28 + 1 + write-only + + + RTC_LITE0_SET + Writing ones to this register sets the corresponding bit in the STARTER0 register. + 29 + 1 + write-only + + + EZH_ARCH_B0_SET + Writing ones to this register sets the corresponding bit in the STARTER0 register. + 30 + 1 + write-only + + + WAKEUP_MAILBOX0_SET + Writing ones to this register sets the corresponding bit in the STARTER0 register. + 31 + 1 + write-only + + + + + STARTERSET1 + Set bits in STARTER + 0x6A4 + 32 + write-only + 0 + 0x8FFF847F + + + GPIO_INT04_SET + Writing ones to this register sets the corresponding bit in the STARTER1 register. + 0 + 1 + write-only + + + GPIO_INT05_SET + Writing ones to this register sets the corresponding bit in the STARTER1 register. + 1 + 1 + write-only + + + GPIO_INT06_SET + Writing ones to this register sets the corresponding bit in the STARTER1 register. + 2 + 1 + write-only + + + GPIO_INT07_SET + Writing ones to this register sets the corresponding bit in the STARTER1 register. + 3 + 1 + write-only + + + CTIMER2_SET + Writing ones to this register sets the corresponding bit in the STARTER1 register. + 4 + 1 + write-only + + + CTIMER4_SET + Writing ones to this register sets the corresponding bit in the STARTER1 register. + 5 + 1 + write-only + + + OS_EVENT_SET + Writing ones to this register sets the corresponding bit in the STARTER1 register. + 6 + 1 + write-only + + + SDIO_SET + Writing ones to this register sets the corresponding bit in the STARTER1 register. + 10 + 1 + write-only + + + USB1_SET + Writing ones to this register sets the corresponding bit in the STARTER1 register. + 15 + 1 + write-only + + + USB1_NEEDCLK_SET + Writing ones to this register sets the corresponding bit in the STARTER1 register. + 16 + 1 + write-only + + + SEC_HYPERVISOR_CALL_SET + Writing ones to this register sets the corresponding bit in the STARTER1 register. + 17 + 1 + write-only + + + SEC_GPIO_INT00_SET + Writing ones to this register sets the corresponding bit in the STARTER1 register. + 18 + 1 + write-only + + + SEC_GPIO_INT01_SET + Writing ones to this register sets the corresponding bit in the STARTER1 register. + 19 + 1 + write-only + + + PLU_SET + Writing ones to this register sets the corresponding bit in the STARTER1 register. + 20 + 1 + write-only + + + SEC_VIO_SET + Writing ones to this register sets the corresponding bit in the STARTER1 register. + 21 + 1 + write-only + + + SHA_SET + Writing ones to this register sets the corresponding bit in the STARTER1 register. + 22 + 1 + write-only + + + CASER_SET + Writing ones to this register sets the corresponding bit in the STARTER1 register. + 23 + 1 + write-only + + + QDDKEY_SET + Writing ones to this register sets the corresponding bit in the STARTER1 register. + 24 + 1 + write-only + + + PQ_SET + Writing ones to this register sets the corresponding bit in the STARTER1 register. + 25 + 1 + write-only + + + SDMA1_SET + Writing ones to this register sets the corresponding bit in the STARTER1 register. + 26 + 1 + write-only + + + LSPI_HS_SET + Writing ones to this register sets the corresponding bit in the STARTER1 register. + 27 + 1 + write-only + + + WAKEUPPADS_SET + Writing ones to this register sets the corresponding bit in the STARTER1 register. + 31 + 1 + write-only + + + + + STARTERCLR0 + Clear bits in STARTER + 0x6C0 + 32 + write-only + 0 + 0xF97FFFFF + + + SYS_CLR + Writing ones to this register clears the corresponding bit in the STARTER0 register. + 0 + 1 + write-only + + + SDMA0_CLR + Writing ones to this register clears the corresponding bit in the STARTER0 register. + 1 + 1 + write-only + + + GPIO_GLOBALINT0_CLR + Writing ones to this register clears the corresponding bit in the STARTER0 register. + 2 + 1 + write-only + + + GPIO_GLOBALINT1_CLR + Writing ones to this register clears the corresponding bit in the STARTER0 register. + 3 + 1 + write-only + + + GPIO_INT00_CLR + Writing ones to this register clears the corresponding bit in the STARTER0 register. + 4 + 1 + write-only + + + GPIO_INT01_CLR + Writing ones to this register clears the corresponding bit in the STARTER0 register. + 5 + 1 + write-only + + + GPIO_INT02_CLR + Writing ones to this register clears the corresponding bit in the STARTER0 register. + 6 + 1 + write-only + + + GPIO_INT03_CLR + Writing ones to this register clears the corresponding bit in the STARTER0 register. + 7 + 1 + write-only + + + UTICK0_CLR + Writing ones to this register clears the corresponding bit in the STARTER0 register. + 8 + 1 + write-only + + + MRT0_CLR + Writing ones to this register clears the corresponding bit in the STARTER0 register. + 9 + 1 + write-only + + + CTIMER0_CLR + Writing ones to this register clears the corresponding bit in the STARTER0 register. + 10 + 1 + write-only + + + CTIMER1_CLR + Writing ones to this register clears the corresponding bit in the STARTER0 register. + 11 + 1 + write-only + + + SCT0_CLR + Writing ones to this register clears the corresponding bit in the STARTER0 register. + 12 + 1 + write-only + + + CTIMER3_CLR + Writing ones to this register clears the corresponding bit in the STARTER0 register. + 13 + 1 + write-only + + + FLEXINT0_CLR + Writing ones to this register clears the corresponding bit in the STARTER0 register. + 14 + 1 + write-only + + + FLEXINT1_CLR + Writing ones to this register clears the corresponding bit in the STARTER0 register. + 15 + 1 + write-only + + + FLEXINT2_CLR + Writing ones to this register clears the corresponding bit in the STARTER0 register. + 16 + 1 + write-only + + + FLEXINT3_CLR + Writing ones to this register clears the corresponding bit in the STARTER0 register. + 17 + 1 + write-only + + + FLEXINT4_CLR + Writing ones to this register clears the corresponding bit in the STARTER0 register. + 18 + 1 + write-only + + + FLEXINT5_CLR + Writing ones to this register clears the corresponding bit in the STARTER0 register. + 19 + 1 + write-only + + + FLEXINT6_CLR + Writing ones to this register clears the corresponding bit in the STARTER0 register. + 20 + 1 + write-only + + + FLEXINT7_CLR + Writing ones to this register clears the corresponding bit in the STARTER0 register. + 21 + 1 + write-only + + + ADC0_CLR + Writing ones to this register clears the corresponding bit in the STARTER0 register. + 22 + 1 + write-only + + + ADC0_THCMP_OVR_CLR + Writing ones to this register clears the corresponding bit in the STARTER0 register. + 24 + 1 + write-only + + + USB0_NEEDCLK_CLR + Writing ones to this register clears the corresponding bit in the STARTER0 register. + 27 + 1 + write-only + + + USB0_CLR + Writing ones to this register clears the corresponding bit in the STARTER0 register. + 28 + 1 + write-only + + + RTC_LITE0_CLR + Writing ones to this register clears the corresponding bit in the STARTER0 register. + 29 + 1 + write-only + + + EZH_ARCH_B0_CLR + Writing ones to this register clears the corresponding bit in the STARTER0 register. + 30 + 1 + write-only + + + WAKEUP_MAILBOX0_CLR + Writing ones to this register clears the corresponding bit in the STARTER0 register. + 31 + 1 + write-only + + + + + STARTERCLR1 + Clear bits in STARTER + 0x6C4 + 32 + write-only + 0 + 0x8FFF847F + + + GPIO_INT04_CLR + Writing ones to this register clears the corresponding bit in the STARTER1 register. + 0 + 1 + write-only + + + GPIO_INT05_CLR + Writing ones to this register clears the corresponding bit in the STARTER1 register. + 1 + 1 + write-only + + + GPIO_INT06_CLR + Writing ones to this register clears the corresponding bit in the STARTER1 register. + 2 + 1 + write-only + + + GPIO_INT07_CLR + Writing ones to this register clears the corresponding bit in the STARTER1 register. + 3 + 1 + write-only + + + CTIMER2_CLR + Writing ones to this register clears the corresponding bit in the STARTER1 register. + 4 + 1 + write-only + + + CTIMER4_CLR + Writing ones to this register clears the corresponding bit in the STARTER1 register. + 5 + 1 + write-only + + + OS_EVENT_CLR + Writing ones to this register clears the corresponding bit in the STARTER1 register. + 6 + 1 + write-only + + + SDIO_CLR + Writing ones to this register clears the corresponding bit in the STARTER1 register. + 10 + 1 + write-only + + + USB1_CLR + Writing ones to this register clears the corresponding bit in the STARTER1 register. + 15 + 1 + write-only + + + USB1_NEEDCLK_CLR + Writing ones to this register clears the corresponding bit in the STARTER1 register. + 16 + 1 + write-only + + + SEC_HYPERVISOR_CALL_CLR + Writing ones to this register clears the corresponding bit in the STARTER1 register. + 17 + 1 + write-only + + + SEC_GPIO_INT00_CLR + Writing ones to this register clears the corresponding bit in the STARTER1 register. + 18 + 1 + write-only + + + SEC_GPIO_INT01_CLR + Writing ones to this register clears the corresponding bit in the STARTER1 register. + 19 + 1 + write-only + + + PLU_CLR + Writing ones to this register clears the corresponding bit in the STARTER1 register. + 20 + 1 + write-only + + + SEC_VIO_CLR + Writing ones to this register clears the corresponding bit in the STARTER1 register. + 21 + 1 + write-only + + + SHA_CLR + Writing ones to this register clears the corresponding bit in the STARTER1 register. + 22 + 1 + write-only + + + CASER_CLR + Writing ones to this register clears the corresponding bit in the STARTER1 register. + 23 + 1 + write-only + + + QDDKEY_CLR + Writing ones to this register clears the corresponding bit in the STARTER1 register. + 24 + 1 + write-only + + + PQ_CLR + Writing ones to this register clears the corresponding bit in the STARTER1 register. + 25 + 1 + write-only + + + SDMA1_CLR + Writing ones to this register clears the corresponding bit in the STARTER1 register. + 26 + 1 + write-only + + + LSPI_HS_CLR + Writing ones to this register clears the corresponding bit in the STARTER1 register. + 27 + 1 + write-only + + + WAKEUPPADS_CLR + Writing ones to this register clears the corresponding bit in the STARTER1 register. + 31 + 1 + write-only + + + + + HARDWARESLEEP + Hardware Sleep control + 0x780 + 32 + read-write + 0 + 0x2B + + + FORCED + Force peripheral clocking to stay on during Deep Sleep and Power-down modes. + 0 + 1 + read-write + + + PERIPHERALS + Wake for Flexcomms. + 1 + 1 + read-write + + + SDMA0 + Wake for DMA0. + 3 + 1 + read-write + + + SDMA1 + Wake for DMA1. + 5 + 1 + read-write + + + + + CPUCTRL + CPU Control for multiple processors + 0x800 + 32 + read-write + 0x2C + 0x3D + + + CPU1CLKEN + CPU1 clock enable. + 3 + 1 + read-write + + + DISABLE + The CPU1 clock is not enabled. + 0 + + + ENABLE + The CPU1 clock is enabled. + 0x1 + + + + + CPU1RSTEN + CPU1 reset. + 5 + 1 + read-write + + + RELEASED + The CPU1 is not being reset. + 0 + + + ASSERTED + The CPU1 is being reset. + 0x1 + + + + + + + CPBOOT + Coprocessor Boot Address + 0x804 + 32 + read-write + 0 + 0xFFFFFFFF + + + CPBOOT + Coprocessor Boot Address for CPU1. + 0 + 32 + read-write + + + + + CPSTACK + Coprocessor Stack Address + 0x808 + 32 + read-write + 0 + 0xFFFFFFFF + + + CPSTACK + Coprocessor Stack Address. -- NOT USED + 0 + 32 + read-write + + + + + CPSTAT + CPU Status + 0x80C + 32 + read-write + 0 + 0xF + + + CPU0SLEEPING + The CPU0 sleeping state. + 0 + 1 + read-only + + + AWAKE + the CPU is not sleeping. + 0 + + + SLEEPING + the CPU is sleeping. + 0x1 + + + + + CPU1SLEEPING + The CPU1 sleeping state. + 1 + 1 + read-only + + + AWAKE + the CPU is not sleeping. + 0 + + + SLEEPING + the CPU is sleeping. + 0x1 + + + + + CPU0LOCKUP + The CPU0 lockup state. + 2 + 1 + read-only + + + AWAKE + the CPU is not in lockup. + 0 + + + SLEEPING + the CPU is in lockup. + 0x1 + + + + + CPU1LOCKUP + The CPU1 lockup state. + 3 + 1 + read-only + + + AWAKE + the CPU is not in lockup. + 0 + + + SLEEPING + the CPU is in lockup. + 0x1 + + + + + + + DICE_REG0 + Composite Device Identifier + 0x900 + 32 + read-write + 0 + 0xFFFFFFFF + + + DICE_REG0 + no description available + 0 + 32 + read-write + + + + + DICE_REG1 + Composite Device Identifier + 0x904 + 32 + read-write + 0 + 0xFFFFFFFF + + + DICE_REG1 + no description available + 0 + 32 + read-write + + + + + DICE_REG2 + Composite Device Identifier + 0x908 + 32 + read-write + 0 + 0xFFFFFFFF + + + DICE_REG2 + no description available + 0 + 32 + read-write + + + + + DICE_REG3 + Composite Device Identifier + 0x90C + 32 + read-write + 0 + 0xFFFFFFFF + + + DICE_REG3 + no description available + 0 + 32 + read-write + + + + + DICE_REG4 + Composite Device Identifier + 0x910 + 32 + read-write + 0 + 0xFFFFFFFF + + + DICE_REG4 + no description available + 0 + 32 + read-write + + + + + DICE_REG5 + Composite Device Identifier + 0x914 + 32 + read-write + 0 + 0xFFFFFFFF + + + DICE_REG5 + no description available + 0 + 32 + read-write + + + + + DICE_REG6 + Composite Device Identifier + 0x918 + 32 + read-write + 0 + 0xFFFFFFFF + + + DICE_REG6 + no description available + 0 + 32 + read-write + + + + + DICE_REG7 + Composite Device Identifier + 0x91C + 32 + read-write + 0 + 0xFFFFFFFF + + + DICE_REG7 + no description available + 0 + 32 + read-write + + + + + CLOCK_CTRL + Various system clock controls : Flash clock (48 MHz) control, clocks to Frequency Measures + 0xA18 + 32 + read-write + 0x1 + 0x7F + + + FLASH48MHZ_ENA + Enable Flash 48 MHz clock. + 0 + 1 + read-write + + + DISABLE + The clock is not enabled. + 0 + + + ENABLE + The clock is enabled. + 0x1 + + + + + XTAL32MHZ_FREQM_ENA + Enable XTAL32MHz clock for Frequency Measure module. + 1 + 1 + read-write + + + DISABLE + The clock is not enabled. + 0 + + + ENABLE + The clock is enabled. + 0x1 + + + + + FRO1MHZ_UTICK_ENA + Enable FRO 1MHz clock for Frequency Measure module and for UTICK. + 2 + 1 + read-write + + + DISABLE + The clock is not enabled. + 0 + + + ENABLE + The clock is enabled. + 0x1 + + + + + FRO12MHZ_FREQM_ENA + Enable FRO 12MHz clock for Frequency Measure module. + 3 + 1 + read-write + + + DISABLE + The clock is not enabled. + 0 + + + ENABLE + The clock is enabled. + 0x1 + + + + + FRO_HF_FREQM_ENA + Enable FRO 96MHz clock for Frequency Measure module. + 4 + 1 + read-write + + + DISABLE + The clock is not enabled. + 0 + + + ENABLE + The clock is enabled. + 0x1 + + + + + CLKIN_ENA + Enable clock_in clock for clock module. + 5 + 1 + read-write + + + DISABLE + The clock is not enabled. + 0 + + + ENABLE + The clock is enabled. + 0x1 + + + + + FRO1MHZ_CLK_ENA + Enable FRO 1MHz clock for clock muxing in clock gen. + 6 + 1 + read-write + + + DISABLE + The clock is not enabled. + 0 + + + ENABLE + The clock is enabled. + 0x1 + + + + + ANA_FRO12M_CLK_ENA + Enable FRO 12MHz clock for analog control of the FRO 192MHz. + 7 + 1 + read-write + + + DISABLE + The clock is not enabled. + 0 + + + ENABLE + The clock is enabled. + 0x1 + + + + + XO_CAL_CLK_ENA + Enable clock for cristal oscilator calibration. + 8 + 1 + read-write + + + DISABLE + The clock is not enabled. + 0 + + + ENABLE + The clock is enabled. + 0x1 + + + + + PLU_DEGLITCH_CLK_ENA + Enable clocks FRO_1MHz and FRO_12MHz for PLU deglitching. + 9 + 1 + read-write + + + DISABLE + The clock is not enabled. + 0 + + + ENABLE + The clock is enabled. + 0x1 + + + + + + + COMP_INT_CTRL + Comparator Interrupt control + 0xB10 + 32 + read-write + 0 + 0x3F + + + INT_ENABLE + Analog Comparator interrupt enable control:. + 0 + 1 + read-write + + + INT_DISABLE + interrupt disable. + 0 + + + INT_ENABLE + interrupt enable. + 0x1 + + + + + INT_CLEAR + Analog Comparator interrupt clear. + 1 + 1 + read-write + + + NONE + No effect. + 0 + + + CLEAR + Clear the interrupt. Self-cleared bit. + 0x1 + + + + + INT_CTRL + Comparator interrupt type selector:. + 2 + 3 + read-write + + + EDGE_DISABLE + The analog comparator interrupt edge sensitive is disabled. + 0 + + + LVL_DISABLE + The analog comparator interrupt level sensitive is disabled. + 0x1 + + + EDGE_RISING + analog comparator interrupt is rising edge sensitive. + 0x2 + + + LVL_HIGH + Analog Comparator interrupt is high level sensitive. + 0x3 + + + EDGE_FALLING + analog comparator interrupt is falling edge sensitive. + 0x4 + + + LVL_LOW + Analog Comparator interrupt is low level sensitive. + 0x5 + + + EDGE_BOTH + analog comparator interrupt is rising and falling edge sensitive. + 0x6 + + + LVL_DIS2 + The analog comparator interrupt level sensitive is disabled. + 0x7 + + + + + INT_SOURCE + Select which Analog comparator output (filtered our un-filtered) is used for interrupt detection. + 5 + 1 + read-write + + + FILTER_INT + Select Analog Comparator filtered output as input for interrupt detection. + 0 + + + RAW_INT + Select Analog Comparator raw output (unfiltered) as input for interrupt detection. Must be used when Analog comparator is used as wake up source in Power down mode. + 0x1 + + + + + + + COMP_INT_STATUS + Comparator Interrupt status + 0xB14 + 32 + read-write + 0 + 0x7 + + + STATUS + Interrupt status BEFORE Interrupt Enable. + 0 + 1 + read-only + + + NO_INT + no interrupt pending. + 0 + + + PENDING + interrupt pending. + 0x1 + + + + + INT_STATUS + Interrupt status AFTER Interrupt Enable. + 1 + 1 + read-only + + + NO_INT + no interrupt pending. + 0 + + + PENDING + interrupt pending. + 0x1 + + + + + VAL + comparator analog output. + 2 + 1 + read-only + + + SMALLER + P+ is smaller than P-. + 0 + + + GREATER + P+ is greater than P-. + 0x1 + + + + + + + AUTOCLKGATEOVERRIDE + Control automatic clock gating + 0xE04 + 32 + read-write + 0xFFFF + 0xFFFFFFFF + + + ROM + Control automatic clock gating of ROM controller. + 0 + 1 + read-write + + + DISABLE + Automatic clock gating is not overridden. + 0 + + + ENABLE + Automatic clock gating is overridden (Clock gating is disabled). + 0x1 + + + + + RAMX_CTRL + Control automatic clock gating of RAMX controller. + 1 + 1 + read-write + + + DISABLE + Automatic clock gating is not overridden. + 0 + + + ENABLE + Automatic clock gating is overridden (Clock gating is disabled). + 0x1 + + + + + RAM0_CTRL + Control automatic clock gating of RAM0 controller. + 2 + 1 + read-write + + + DISABLE + Automatic clock gating is not overridden. + 0 + + + ENABLE + Automatic clock gating is overridden (Clock gating is disabled). + 0x1 + + + + + RAM1_CTRL + Control automatic clock gating of RAM1 controller. + 3 + 1 + read-write + + + DISABLE + Automatic clock gating is not overridden. + 0 + + + ENABLE + Automatic clock gating is overridden (Clock gating is disabled). + 0x1 + + + + + RAM2_CTRL + Control automatic clock gating of RAM2 controller. + 4 + 1 + read-write + + + DISABLE + Automatic clock gating is not overridden. + 0 + + + ENABLE + Automatic clock gating is overridden (Clock gating is disabled). + 0x1 + + + + + RAM3_CTRL + Control automatic clock gating of RAM3 controller. + 5 + 1 + read-write + + + DISABLE + Automatic clock gating is not overridden. + 0 + + + ENABLE + Automatic clock gating is overridden (Clock gating is disabled). + 0x1 + + + + + RAM4_CTRL + Control automatic clock gating of RAM4 controller. + 6 + 1 + read-write + + + DISABLE + Automatic clock gating is not overridden. + 0 + + + ENABLE + Automatic clock gating is overridden (Clock gating is disabled). + 0x1 + + + + + SYNC0_APB + Control automatic clock gating of synchronous bridge controller 0. + 7 + 1 + read-write + + + DISABLE + Automatic clock gating is not overridden. + 0 + + + ENABLE + Automatic clock gating is overridden (Clock gating is disabled). + 0x1 + + + + + SYNC1_APB + Control automatic clock gating of synchronous bridge controller 1. + 8 + 1 + read-write + + + DISABLE + Automatic clock gating is not overridden. + 0 + + + ENABLE + Automatic clock gating is overridden (Clock gating is disabled). + 0x1 + + + + + FLASH + Control automatic clock gating of FLASH controller. + 9 + 1 + read-write + + + DISABLE + Automatic clock gating is not overridden. + 0 + + + ENABLE + Automatic clock gating is overridden (Clock gating is disabled). + 0x1 + + + + + FMC + Control automatic clock gating of FMC controller. + 10 + 1 + read-write + + + DISABLE + Automatic clock gating is not overridden. + 0 + + + ENABLE + Automatic clock gating is overridden (Clock gating is disabled). + 0x1 + + + + + CRCGEN + Control automatic clock gating of CRCGEN controller. + 11 + 1 + read-write + + + DISABLE + Automatic clock gating is not overridden. + 0 + + + ENABLE + Automatic clock gating is overridden (Clock gating is disabled). + 0x1 + + + + + SDMA0 + Control automatic clock gating of DMA0 controller. + 12 + 1 + read-write + + + DISABLE + Automatic clock gating is not overridden. + 0 + + + ENABLE + Automatic clock gating is overridden (Clock gating is disabled). + 0x1 + + + + + SDMA1 + Control automatic clock gating of DMA1 controller. + 13 + 1 + read-write + + + DISABLE + Automatic clock gating is not overridden. + 0 + + + ENABLE + Automatic clock gating is overridden (Clock gating is disabled). + 0x1 + + + + + USB + Control automatic clock gating of USB controller. + 14 + 1 + read-write + + + DISABLE + Automatic clock gating is not overridden. + 0 + + + ENABLE + Automatic clock gating is overridden (Clock gating is disabled). + 0x1 + + + + + SYSCON + Control automatic clock gating of synchronous system controller registers bank. + 15 + 1 + read-write + + + DISABLE + Automatic clock gating is not overridden. + 0 + + + ENABLE + Automatic clock gating is overridden (Clock gating is disabled). + 0x1 + + + + + ENABLEUPDATE + The value 0xC0DE must be written for AUTOCLKGATEOVERRIDE registers fields updates to have effect. + 16 + 16 + write-only + + + DISABLE + Automatic clock gating is not overridden. + 0 + + + ENABLE + Automatic clock gating is overridden (Clock gating is disabled). + 0xC0DE + + + + + + + GPIOPSYNC + Enable bypass of the first stage of synchonization inside GPIO_INT module + 0xE08 + 32 + read-write + 0 + 0x1 + + + PSYNC + Enable bypass of the first stage of synchonization inside GPIO_INT module. + 0 + 1 + read-write + + + USED + use the first stage of synchonization inside GPIO_INT module. + 0 + + + BYPASS + bypass of the first stage of synchonization inside GPIO_INT module. + 0x1 + + + + + + + DEBUG_LOCK_EN + Control write access to security registers -- FOR INTERNAl USE ONLY + 0xFA0 + 32 + read-write + 0x5 + 0xF + + + LOCK_ALL + Control write access to CODESECURITYPROTTEST, CODESECURITYPROTCPU0, CODESECURITYPROTCPU1, CM33_DEBUG_FEATURES, MCM33_DEBUG_FEATURES and DBG_AUTH_SCRATCH registers. + 0 + 4 + read-write + + + DISABLE + Any other value than b1010: disable write access to all 6 registers. + 0 + + + ENABLE + 1010: Enable write access to all 6 registers. + 0xA + + + + + + + DEBUG_FEATURES + Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control -- FOR INTERNAl USE ONLY + 0xFA4 + 32 + read-write + 0 + 0xFFF + + + CM33_DBGEN + CM33 (CPU0) Invasive debug control:. + 0 + 2 + read-write + + + DISABLE + Any other value than b10: invasive debug is disable. + 0x1 + + + ENABLE + 10: Invasive debug is enabled. + 0x2 + + + + + CM33_NIDEN + CM33 (CPU0) Non Invasive debug control:. + 2 + 2 + read-write + + + DISABLE + Any other value than b10: invasive debug is disable. + 0x1 + + + ENABLE + 10: Invasive debug is enabled. + 0x2 + + + + + CM33_SPIDEN + CM33 (CPU0) Secure Invasive debug control:. + 4 + 2 + read-write + + + DISABLE + Any other value than b10: invasive debug is disable. + 0x1 + + + ENABLE + 10: Invasive debug is enabled. + 0x2 + + + + + CM33_SPNIDEN + CM33 (CPU0) Secure Non Invasive debug control:. + 6 + 2 + read-write + + + DISABLE + Any other value than b10: invasive debug is disable. + 0x1 + + + ENABLE + 10: Invasive debug is enabled. + 0x2 + + + + + MCM33_DBGEN + Micro-CM33 (CPU1) Invasive debug control:. + 8 + 2 + read-write + + + DISABLE + Any other value than b10: invasive debug is disable. + 0x1 + + + ENABLE + 10: Invasive debug is enabled. + 0x2 + + + + + MCM33_NIDEN + Micro-CM33 (CPU1) Non Invasive debug control:. + 10 + 2 + read-write + + + DISABLE + Any other value than b10: invasive debug is disable. + 0x1 + + + ENABLE + 10: Invasive debug is enabled. + 0x2 + + + + + + + DEBUG_FEATURES_DP + Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control DUPLICATE register -- FOR INTERNAl USE ONLY + 0xFA8 + 32 + read-write + 0x555 + 0xFFF + + + CM33_DBGEN + CM33 (CPU0) Invasive debug control:. + 0 + 2 + read-write + + + DISABLE + Any other value than b10: invasive debug is disable. + 0x1 + + + ENABLE + 10: Invasive debug is enabled. + 0x2 + + + + + CM33_NIDEN + CM33 (CPU0) Non Invasive debug control:. + 2 + 2 + read-write + + + DISABLE + Any other value than b10: invasive debug is disable. + 0x1 + + + ENABLE + 10: Invasive debug is enabled. + 0x2 + + + + + CM33_SPIDEN + CM33 (CPU0) Secure Invasive debug control:. + 4 + 2 + read-write + + + DISABLE + Any other value than b10: invasive debug is disable. + 0x1 + + + ENABLE + 10: Invasive debug is enabled. + 0x2 + + + + + CM33_SPNIDEN + CM33 (CPU0) Secure Non Invasive debug control:. + 6 + 2 + read-write + + + DISABLE + Any other value than b10: invasive debug is disable. + 0x1 + + + ENABLE + 10: Invasive debug is enabled. + 0x2 + + + + + MCM33_DBGEN + Micro-CM33 (CPU1) Invasive debug control:. + 8 + 2 + read-write + + + DISABLE + Any other value than b10: invasive debug is disable. + 0x1 + + + ENABLE + 10: Invasive debug is enabled. + 0x2 + + + + + MCM33_NIDEN + Micro-CM33 (CPU1) Non Invasive debug control:. + 10 + 2 + read-write + + + DISABLE + Any other value than b10: invasive debug is disable. + 0x1 + + + ENABLE + 10: Invasive debug is enabled. + 0x2 + + + + + + + CODESECURITYPROTTEST + Security code to allow test (Design for Testability) access -- FOR INTERNAl USE ONLY + 0xFB0 + 32 + write-only + 0 + 0xFFFFFFFF + + + SEC_CODE + Security code to allow test access : 0x12345678. + 0 + 32 + write-only + + + DISABLE + test access is not allowed. + 0 + + + ENABLE + Security code to allow test access. + 0x12345678 + + + + + + + CODESECURITYPROTCPU0 + Security code to allow CPU0 (CM33) Debug Access Port (DAP) -- FOR INTERNAl USE ONLY + 0xFB4 + 32 + write-only + 0 + 0xFFFFFFFF + + + SEC_CODE + Security code to allow CPU0 DAP: 0x12345678. + 0 + 32 + write-only + + + DISABLE + CPU0 DAP is not allowed. + 0 + + + ENABLE + Security code to allow CPU0 DAP. + 0x12345678 + + + + + + + CODESECURITYPROTCPU1 + Security code to allow CPU1 (Micro CM33) Debug Access Port (DAP) -- FOR INTERNAl USE ONLY + 0xFB8 + 32 + write-only + 0 + 0xFFFFFFFF + + + SEC_CODE + Security code to allow CPU1 DAP: 0x12345678. + 0 + 32 + write-only + + + DISABLE + CPU1 DAP is not allowed. + 0 + + + ENABLE + Security code to allow CPU1 DAP. + 0x12345678 + + + + + + + KEY_BLOCK + block quiddikey/PUF all index. -- FOR INTERNAL USE ONLY + 0xFBC + 32 + write-only + 0x3CC35AA5 + 0xFFFFFFFF + + + KEY_BLOCK + Write a value to block quiddikey/PUF all index. + 0 + 32 + write-only + + + + + DEBUG_AUTH_SCRATCH + Debug authentication scratch registers -- FOR INTERNAL USE ONLY + 0xFC0 + 32 + read-write + 0 + 0xFFFFFFFF + + + SCRATCH + Set by the debug authentication code in ROM to pass the debug beacons (Credential Beacon and Authentication Beacon) to application code. + 0 + 32 + read-write + + + + + CPUCFG + CPUs configuration register + 0xFD4 + 32 + read-write + 0x2 + 0x7 + + + CPU1ENABLE + Enable CPU1. + 2 + 1 + read-write + + + DISABLE + CPU1 is disable (Processor in reset). + 0 + + + ENABLE + CPU1 is enable. + 0x1 + + + + + + + PERIPHENCFG + peripheral enable configuration -- FOR INTERNAL USE ONLY + 0xFEC + 32 + read-write + 0x5C47 + 0x5C47 + + + SCTEN + SCT enable. + 0 + 1 + read-write + + + DISABLE + peripheral is disable. + 0 + + + ENABLE + peripheral is enable. + 0x1 + + + + + ADCEN + ADC enable. + 1 + 1 + read-write + + + DISABLE + peripheral is disable. + 0 + + + ENABLE + peripheral is enable. + 0x1 + + + + + USB0EN + USB0 enable. + 2 + 1 + read-write + + + DISABLE + peripheral is disable. + 0 + + + ENABLE + peripheral is enable. + 0x1 + + + + + PUFFEN + Puff enable. + 6 + 1 + read-write + + + DISABLE + peripheral is disable. + 0 + + + ENABLE + peripheral is enable. + 0x1 + + + + + USB1EN + USB1 enable. + 10 + 1 + read-write + + + DISABLE + peripheral is disable. + 0 + + + ENABLE + peripheral is enable. + 0x1 + + + + + SDIOEN + SDIO enable. + 11 + 1 + read-write + + + DISABLE + peripheral is disable. + 0 + + + ENABLE + peripheral is enable. + 0x1 + + + + + HASHEN + HASH enable. + 12 + 1 + read-write + + + DISABLE + peripheral is disable. + 0 + + + ENABLE + peripheral is enable. + 0x1 + + + + + PRINCEEN + PRINCE enable. + 14 + 1 + read-write + + + DISABLE + peripheral is disable. + 0 + + + ENABLE + peripheral is enable. + 0x1 + + + + + + + DEVICE_ID0 + Device ID + 0xFF8 + 32 + read-only + 0 + 0xFFFFFFFF + + + PARTCONFIG + no description available + 0 + 8 + read-only + + + SRAM_SIZE + no description available + 8 + 4 + read-only + + + FLASH_SIZE + no description available + 12 + 3 + read-only + + + ROM_REV_MINOR + no description available + 20 + 4 + read-only + + + MODELNUM_EXTENTION + no description available + 24 + 3 + read-only + + + + + DIEID + Chip revision ID and Number + 0xFFC + 32 + read-only + 0x426B0 + 0xFFFFFF + + + REV_ID + Chip Metal Revision ID. + 0 + 4 + read-only + + + MCO_NUM_IN_DIE_ID + Chip Number. + 4 + 20 + read-only + + + + + + + IOCON + I/O pin configuration (IOCON) + IOCON + 0x40001000 + + 0 + 0x100 + registers + + + + PIO0_0 + Digital I/O control for port 0 pins PIO0_0 + 0 + 32 + read-write + 0 + 0x7FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + ASW + Analog switch input control. Usable only if DIGIMODE = 0b0 + 10 + 1 + read-write + + + DISABLE + Analog switch is open. + 0 + + + ENABLE + Analog switch is closed. + 0x1 + + + + + + + PIO0_1 + Digital I/O control for port 0 pins PIO0_1 + 0x4 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO0_2 + Digital I/O control for port 0 pins PIO0_2 + 0x8 + 32 + read-write + 0x110 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO0_3 + Digital I/O control for port 0 pins PIO0_3 + 0xC + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO0_4 + Digital I/O control for port 0 pins PIO0_4 + 0x10 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO0_5 + Digital I/O control for port 0 pins PIO0_5 + 0x14 + 32 + read-write + 0x120 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO0_6 + Digital I/O control for port 0 pins PIO0_6 + 0x18 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO0_7 + Digital I/O control for port 0 pins PIO0_7 + 0x1C + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO0_8 + Digital I/O control for port 0 pins PIO0_8 + 0x20 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO0_9 + Digital I/O control for port 0 pins PIO0_9 + 0x24 + 32 + read-write + 0 + 0x7FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + ASW + Analog switch input control. Usable only if DIGIMODE = 0b0 + 10 + 1 + read-write + + + DISABLE + Analog switch is open. + 0 + + + ENABLE + Analog switch is closed. + 0x1 + + + + + + + PIO0_10 + Digital I/O control for port 0 pins PIO0_10 + 0x28 + 32 + read-write + 0 + 0x7FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + ASW + Analog switch input control. Usable only if DIGIMODE = 0b0 + 10 + 1 + read-write + + + DISABLE + Analog switch is open. + 0 + + + ENABLE + Analog switch is closed. + 0x1 + + + + + + + PIO0_11 + Digital I/O control for port 0 pins PIO0_11 + 0x2C + 32 + read-write + 0x116 + 0x7FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + ASW + Analog switch input control. Usable only if DIGIMODE = 0b0 + 10 + 1 + read-write + + + DISABLE + Analog switch is open. + 0 + + + ENABLE + Analog switch is closed. + 0x1 + + + + + + + PIO0_12 + Digital I/O control for port 0 pins PIO0_12 + 0x30 + 32 + read-write + 0x126 + 0x7FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + ASW + Analog switch input control. Usable only if DIGIMODE = 0b0 + 10 + 1 + read-write + + + DISABLE + Analog switch is open. + 0 + + + ENABLE + Analog switch is closed. + 0x1 + + + + + + + PIO0_13 + Digital I/O control for port 0 pins PIO0_13 + 0x34 + 32 + read-write + 0x5000 + 0xFFFF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + SSEL + Supply Selection bit. + 11 + 1 + read-write + + + SEL3V3 + 3V3 Signaling in I2C Mode. + 0 + + + SEL1V8 + 1V8 Signaling in I2C Mode. + 0x1 + + + + + FILTEROFF + Controls input glitch filter. + 12 + 1 + read-write + + + ENABLED + Filter enabled. Noise pulses below approximately 10 ns are filtered out. + 0 + + + DISABLED + Filter disabled. No input filtering is done. + 0x1 + + + + + ECS + Pull-up current source enable in IIC mode. + 13 + 1 + read-write + + + DISABLED + Disabled. IO is in open drain. + 0 + + + ENABLED + Enabled. Pull resistor is conencted. + 0x1 + + + + + EGP + Controls slew rate of I2C pad. + 14 + 1 + read-write + + + I2C_MODE + I2C mode. + 0 + + + GPIO_MODE + GPIO mode. + 0x1 + + + + + I2CFILTER + Configures I2C features for standard mode, fast mode, and Fast Mode Plus operation. + 15 + 1 + read-write + + + FAST_MODE + I2C 50 ns glitch filter enabled. Typically used for Fast-mode and Fast-mode Plus I2C. + 0 + + + STANDARD_MODE + I2C 10 ns glitch filter enabled. Typically used for Standard-mode I2C. + 0x1 + + + + + + + PIO0_14 + Digital I/O control for port 0 pins PIO0_14 + 0x38 + 32 + read-write + 0x5000 + 0xFFFF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + SSEL + Supply Selection bit. + 11 + 1 + read-write + + + SEL3V3 + 3V3 Signaling in I2C Mode. + 0 + + + SEL1V8 + 1V8 Signaling in I2C Mode. + 0x1 + + + + + FILTEROFF + Controls input glitch filter. + 12 + 1 + read-write + + + ENABLED + Filter enabled. Noise pulses below approximately 10 ns are filtered out. + 0 + + + DISABLED + Filter disabled. No input filtering is done. + 0x1 + + + + + ECS + Pull-up current source enable in IIC mode. + 13 + 1 + read-write + + + DISABLED + Disabled. IO is in open drain. + 0 + + + ENABLED + Enabled. Pull resistor is conencted. + 0x1 + + + + + EGP + Controls slew rate of I2C pad. + 14 + 1 + read-write + + + I2C_MODE + I2C mode. + 0 + + + GPIO_MODE + GPIO mode. + 0x1 + + + + + I2CFILTER + Configures I2C features for standard mode, fast mode, and Fast Mode Plus operation. + 15 + 1 + read-write + + + FAST_MODE + I2C 50 ns glitch filter enabled. Typically used for Fast-mode and Fast-mode Plus I2C. + 0 + + + STANDARD_MODE + I2C 10 ns glitch filter enabled. Typically used for Standard-mode I2C. + 0x1 + + + + + + + PIO0_15 + Digital I/O control for port 0 pins PIO0_15 + 0x3C + 32 + read-write + 0 + 0x7FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + ASW + Analog switch input control. Usable only if DIGIMODE = 0b0 + 10 + 1 + read-write + + + DISABLE + Analog switch is open. + 0 + + + ENABLE + Analog switch is closed. + 0x1 + + + + + + + PIO0_16 + Digital I/O control for port 0 pins PIO0_16 + 0x40 + 32 + read-write + 0 + 0x7FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + ASW + Analog switch input control. Usable only if DIGIMODE = 0b0 + 10 + 1 + read-write + + + DISABLE + Analog switch is open. + 0 + + + ENABLE + Analog switch is closed. + 0x1 + + + + + + + PIO0_17 + Digital I/O control for port 0 pins PIO0_17 + 0x44 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO0_18 + Digital I/O control for port 0 pins PIO0_18 + 0x48 + 32 + read-write + 0 + 0x7FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + ASW + Analog switch input control. Usable only if DIGIMODE = 0b0 + 10 + 1 + read-write + + + DISABLE + Analog switch is open. + 0 + + + ENABLE + Analog switch is closed. + 0x1 + + + + + + + PIO0_19 + Digital I/O control for port 0 pins PIO0_19 + 0x4C + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO0_20 + Digital I/O control for port 0 pins PIO0_20 + 0x50 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO0_21 + Digital I/O control for port 0 pins PIO0_21 + 0x54 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO0_22 + Digital I/O control for port 0 pins PIO0_22 + 0x58 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO0_23 + Digital I/O control for port 0 pins PIO0_23 + 0x5C + 32 + read-write + 0 + 0x7FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + ASW + Analog switch input control. Usable only if DIGIMODE = 0b0 + 10 + 1 + read-write + + + DISABLE + Analog switch is open. + 0 + + + ENABLE + Analog switch is closed. + 0x1 + + + + + + + PIO0_24 + Digital I/O control for port 0 pins PIO0_24 + 0x60 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO0_25 + Digital I/O control for port 0 pins PIO0_25 + 0x64 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO0_26 + Digital I/O control for port 0 pins PIO0_26 + 0x68 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO0_27 + Digital I/O control for port 0 pins PIO0_27 + 0x6C + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO0_28 + Digital I/O control for port 0 pins PIO0_28 + 0x70 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO0_29 + Digital I/O control for port 0 pins PIO0_29 + 0x74 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO0_30 + Digital I/O control for port 0 pins PIO0_30 + 0x78 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO0_31 + Digital I/O control for port 0 pins PIO0_31 + 0x7C + 32 + read-write + 0 + 0x7FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + ASW + Analog switch input control. Usable only if DIGIMODE = 0b0 + 10 + 1 + read-write + + + DISABLE + Analog switch is open. + 0 + + + ENABLE + Analog switch is closed. + 0x1 + + + + + + + PIO1_0 + Digital I/O control for port 1 pins PIO1_0 + 0x80 + 32 + read-write + 0 + 0x7FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + ASW + Analog switch input control. Usable only if DIGIMODE = 0b0 + 10 + 1 + read-write + + + DISABLE + Analog switch is open. + 0 + + + ENABLE + Analog switch is closed. + 0x1 + + + + + + + PIO1_1 + Digital I/O control for port 1 pins PIO1_1 + 0x84 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO1_2 + Digital I/O control for port 1 pins PIO1_2 + 0x88 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO1_3 + Digital I/O control for port 1 pins PIO1_3 + 0x8C + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO1_4 + Digital I/O control for port 1 pins PIO1_4 + 0x90 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO1_5 + Digital I/O control for port 1 pins PIO1_5 + 0x94 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO1_6 + Digital I/O control for port 1 pins PIO1_6 + 0x98 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO1_7 + Digital I/O control for port 1 pins PIO1_7 + 0x9C + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO1_8 + Digital I/O control for port 1 pins PIO1_8 + 0xA0 + 32 + read-write + 0 + 0x7FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + ASW + Analog switch input control. Usable only if DIGIMODE = 0b0 + 10 + 1 + read-write + + + DISABLE + Analog switch is open. + 0 + + + ENABLE + Analog switch is closed. + 0x1 + + + + + + + PIO1_9 + Digital I/O control for port 1 pins PIO1_9 + 0xA4 + 32 + read-write + 0 + 0x7FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + ASW + Analog switch input control. Usable only if DIGIMODE = 0b0 + 10 + 1 + read-write + + + DISABLE + Analog switch is open. + 0 + + + ENABLE + Analog switch is closed. + 0x1 + + + + + + + PIO1_10 + Digital I/O control for port 1 pins PIO1_10 + 0xA8 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO1_11 + Digital I/O control for port 1 pins PIO1_11 + 0xAC + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO1_12 + Digital I/O control for port 1 pins PIO1_12 + 0xB0 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO1_13 + Digital I/O control for port 1 pins PIO1_13 + 0xB4 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO1_14 + Digital I/O control for port 1 pins PIO1_14 + 0xB8 + 32 + read-write + 0 + 0x7FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + ASW + Analog switch input control. Usable only if DIGIMODE = 0b0 + 10 + 1 + read-write + + + DISABLE + Analog switch is open. + 0 + + + ENABLE + Analog switch is closed. + 0x1 + + + + + + + PIO1_15 + Digital I/O control for port 1 pins PIO1_15 + 0xBC + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO1_16 + Digital I/O control for port 1 pins PIO1_16 + 0xC0 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO1_17 + Digital I/O control for port 1 pins PIO1_17 + 0xC4 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO1_18 + Digital I/O control for port 1 pins PIO1_18 + 0xC8 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO1_19 + Digital I/O control for port 1 pins PIO1_19 + 0xCC + 32 + read-write + 0 + 0x7FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + ASW + Analog switch input control. Usable only if DIGIMODE = 0b0 + 10 + 1 + read-write + + + DISABLE + Analog switch is open. + 0 + + + ENABLE + Analog switch is closed. + 0x1 + + + + + + + PIO1_20 + Digital I/O control for port 1 pins PIO1_20 + 0xD0 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO1_21 + Digital I/O control for port 1 pins PIO1_21 + 0xD4 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO1_22 + Digital I/O control for port 1 pins PIO1_22 + 0xD8 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO1_23 + Digital I/O control for port 1 pins PIO1_23 + 0xDC + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO1_24 + Digital I/O control for port 1 pins PIO1_24 + 0xE0 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO1_25 + Digital I/O control for port 1 pins PIO1_25 + 0xE4 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO1_26 + Digital I/O control for port 1 pins PIO1_26 + 0xE8 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO1_27 + Digital I/O control for port 1 pins PIO1_27 + 0xEC + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO1_28 + Digital I/O control for port 1 pins PIO1_28 + 0xF0 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO1_29 + Digital I/O control for port 1 pins PIO1_29 + 0xF4 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO1_30 + Digital I/O control for port 1 pins PIO1_30 + 0xF8 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO1_31 + Digital I/O control for port 1 pins PIO1_31 + 0xFC + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + + + GINT0 + Group GPIO input interrupt (GINT0/1) + GINT + GINT + 0x40002000 + + 0 + 0x48 + registers + + + GINT0 + 2 + + + + CTRL + GPIO grouped interrupt control register + 0 + 32 + read-write + 0 + 0x7 + + + INT + Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect. + 0 + 1 + read-write + + + NO_REQUEST + No request. No interrupt request is pending. + 0 + + + REQUEST_ACTIVE + Request active. Interrupt request is active. + 0x1 + + + + + COMB + Combine enabled inputs for group interrupt + 1 + 1 + read-write + + + OR + Or. OR functionality: A grouped interrupt is generated when any one of the enabled inputs is active (based on its programmed polarity). + 0 + + + AND + And. AND functionality: An interrupt is generated when all enabled bits are active (based on their programmed polarity). + 0x1 + + + + + TRIG + Group interrupt trigger + 2 + 1 + read-write + + + EDGE_TRIGGERED + Edge-triggered. + 0 + + + LEVEL_TRIGGERED + Level-triggered. + 0x1 + + + + + + + 2 + 0x4 + PORT_POL[%s] + GPIO grouped interrupt port 0 polarity register + 0x20 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + POL + Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. + 0 + 32 + read-write + + + + + 2 + 0x4 + PORT_ENA[%s] + GPIO grouped interrupt port 0 enable register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENA + Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt. + 0 + 32 + read-write + + + + + + + GINT1 + Group GPIO input interrupt (GINT0/1) + GINT + 0x40003000 + + 0 + 0x48 + registers + + + GINT1 + 3 + + + + PINT + Pin interrupt and pattern match (PINT) + PINT + PINT + 0x40004000 + + 0 + 0x34 + registers + + + PIN_INT0 + 4 + + + PIN_INT1 + 5 + + + PIN_INT2 + 6 + + + PIN_INT3 + 7 + + + PIN_INT4 + 32 + + + PIN_INT5 + 33 + + + PIN_INT6 + 34 + + + PIN_INT7 + 35 + + + + ISEL + Pin Interrupt Mode register + 0 + 32 + read-write + 0 + 0xFF + + + PMODE + Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive + 0 + 8 + read-write + + + + + IENR + Pin interrupt level or rising edge interrupt enable register + 0x4 + 32 + read-write + 0 + 0xFF + + + ENRL + Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt. + 0 + 8 + read-write + + + + + SIENR + Pin interrupt level or rising edge interrupt set register + 0x8 + 32 + write-only + 0 + 0 + + + SETENRL + Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt. + 0 + 8 + write-only + + + + + CIENR + Pin interrupt level (rising edge interrupt) clear register + 0xC + 32 + write-only + 0 + 0 + + + CENRL + Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt. + 0 + 8 + write-only + + + + + IENF + Pin interrupt active level or falling edge interrupt enable register + 0x10 + 32 + read-write + 0 + 0xFF + + + ENAF + Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH. + 0 + 8 + read-write + + + + + SIENF + Pin interrupt active level or falling edge interrupt set register + 0x14 + 32 + write-only + 0 + 0 + + + SETENAF + Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt. + 0 + 8 + write-only + + + + + CIENF + Pin interrupt active level or falling edge interrupt clear register + 0x18 + 32 + write-only + 0 + 0 + + + CENAF + Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled. + 0 + 8 + write-only + + + + + RISE + Pin interrupt rising edge register + 0x1C + 32 + read-write + 0 + 0xFF + + + RDET + Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin. + 0 + 8 + read-write + + + + + FALL + Pin interrupt falling edge register + 0x20 + 32 + read-write + 0 + 0xFF + + + FDET + Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin. + 0 + 8 + read-write + + + + + IST + Pin interrupt status register + 0x24 + 32 + read-write + 0 + 0xFF + + + PSTAT + Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the IENF register). + 0 + 8 + read-write + + + + + PMCTRL + Pattern match interrupt control register + 0x28 + 32 + read-write + 0 + 0xFF000003 + + + SEL_PMATCH + Specifies whether the 8 pin interrupts are controlled by the pin interrupt function or by the pattern match function. + 0 + 1 + read-write + + + PIN_INTERRUPT + Pin interrupt. Interrupts are driven in response to the standard pin interrupt function. + 0 + + + PATTERN_MATCH + Pattern match. Interrupts are driven in response to pattern matches. + 0x1 + + + + + ENA_RXEV + Enables the RXEV output to the CPU and/or to a GPIO output when the specified boolean expression evaluates to true. + 1 + 1 + read-write + + + DISABLED + Disabled. RXEV output to the CPU is disabled. + 0 + + + ENABLED + Enabled. RXEV output to the CPU is enabled. + 0x1 + + + + + PMAT + This field displays the current state of pattern matches. A 1 in any bit of this field indicates that the corresponding product term is matched by the current state of the appropriate inputs. + 24 + 8 + read-write + + + + + PMSRC + Pattern match interrupt bit-slice source register + 0x2C + 32 + read-write + 0 + 0xFFFFFF00 + + + SRC0 + Selects the input source for bit slice 0 + 8 + 3 + read-write + + + INPUT0 + Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 0. + 0 + + + INPUT1 + Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 0. + 0x1 + + + INPUT2 + Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 0. + 0x2 + + + INPUT3 + Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 0. + 0x3 + + + INPUT4 + Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 0. + 0x4 + + + INPUT5 + Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 0. + 0x5 + + + INPUT6 + Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 0. + 0x6 + + + INPUT7 + Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 0. + 0x7 + + + + + SRC1 + Selects the input source for bit slice 1 + 11 + 3 + read-write + + + INPUT0 + Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 1. + 0 + + + INPUT1 + Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 1. + 0x1 + + + INPUT2 + Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 1. + 0x2 + + + INPUT3 + Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 1. + 0x3 + + + INPUT4 + Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 1. + 0x4 + + + INPUT5 + Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 1. + 0x5 + + + INPUT6 + Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 1. + 0x6 + + + INPUT7 + Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 1. + 0x7 + + + + + SRC2 + Selects the input source for bit slice 2 + 14 + 3 + read-write + + + INPUT0 + Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 2. + 0 + + + INPUT1 + Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 2. + 0x1 + + + INPUT2 + Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 2. + 0x2 + + + INPUT3 + Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 2. + 0x3 + + + INPUT4 + Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 2. + 0x4 + + + INPUT5 + Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 2. + 0x5 + + + INPUT6 + Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 2. + 0x6 + + + INPUT7 + Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 2. + 0x7 + + + + + SRC3 + Selects the input source for bit slice 3 + 17 + 3 + read-write + + + INPUT0 + Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 3. + 0 + + + INPUT1 + Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 3. + 0x1 + + + INPUT2 + Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 3. + 0x2 + + + INPUT3 + Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 3. + 0x3 + + + INPUT4 + Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 3. + 0x4 + + + INPUT5 + Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 3. + 0x5 + + + INPUT6 + Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 3. + 0x6 + + + INPUT7 + Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 3. + 0x7 + + + + + SRC4 + Selects the input source for bit slice 4 + 20 + 3 + read-write + + + INPUT0 + Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 4. + 0 + + + INPUT1 + Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 4. + 0x1 + + + INPUT2 + Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 4. + 0x2 + + + INPUT3 + Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 4. + 0x3 + + + INPUT4 + Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 4. + 0x4 + + + INPUT5 + Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 4. + 0x5 + + + INPUT6 + Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 4. + 0x6 + + + INPUT7 + Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 4. + 0x7 + + + + + SRC5 + Selects the input source for bit slice 5 + 23 + 3 + read-write + + + INPUT0 + Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 5. + 0 + + + INPUT1 + Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 5. + 0x1 + + + INPUT2 + Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 5. + 0x2 + + + INPUT3 + Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 5. + 0x3 + + + INPUT4 + Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 5. + 0x4 + + + INPUT5 + Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 5. + 0x5 + + + INPUT6 + Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 5. + 0x6 + + + INPUT7 + Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 5. + 0x7 + + + + + SRC6 + Selects the input source for bit slice 6 + 26 + 3 + read-write + + + INPUT0 + Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 6. + 0 + + + INPUT1 + Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 6. + 0x1 + + + INPUT2 + Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 6. + 0x2 + + + INPUT3 + Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 6. + 0x3 + + + INPUT4 + Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 6. + 0x4 + + + INPUT5 + Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 6. + 0x5 + + + INPUT6 + Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 6. + 0x6 + + + INPUT7 + Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 6. + 0x7 + + + + + SRC7 + Selects the input source for bit slice 7 + 29 + 3 + read-write + + + INPUT0 + Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 7. + 0 + + + INPUT1 + Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 7. + 0x1 + + + INPUT2 + Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 7. + 0x2 + + + INPUT3 + Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 7. + 0x3 + + + INPUT4 + Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 7. + 0x4 + + + INPUT5 + Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 7. + 0x5 + + + INPUT6 + Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 7. + 0x6 + + + INPUT7 + Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 7. + 0x7 + + + + + + + PMCFG + Pattern match interrupt bit slice configuration register + 0x30 + 32 + read-write + 0 + 0xFFFFFF7F + + + PROD_ENDPTS0 + Determines whether slice 0 is an endpoint. + 0 + 1 + read-write + + + NO_EFFECT + No effect. Slice 0 is not an endpoint. + 0 + + + ENDPOINT + endpoint. Slice 0 is the endpoint of a product term (minterm). Pin interrupt 0 in the NVIC is raised if the minterm evaluates as true. + 0x1 + + + + + PROD_ENDPTS1 + Determines whether slice 1 is an endpoint. + 1 + 1 + read-write + + + NO_EFFECT + No effect. Slice 1 is not an endpoint. + 0 + + + ENDPOINT + endpoint. Slice 1 is the endpoint of a product term (minterm). Pin interrupt 1 in the NVIC is raised if the minterm evaluates as true. + 0x1 + + + + + PROD_ENDPTS2 + Determines whether slice 2 is an endpoint. + 2 + 1 + read-write + + + NO_EFFECT + No effect. Slice 2 is not an endpoint. + 0 + + + ENDPOINT + endpoint. Slice 2 is the endpoint of a product term (minterm). Pin interrupt 2 in the NVIC is raised if the minterm evaluates as true. + 0x1 + + + + + PROD_ENDPTS3 + Determines whether slice 3 is an endpoint. + 3 + 1 + read-write + + + NO_EFFECT + No effect. Slice 3 is not an endpoint. + 0 + + + ENDPOINT + endpoint. Slice 3 is the endpoint of a product term (minterm). Pin interrupt 3 in the NVIC is raised if the minterm evaluates as true. + 0x1 + + + + + PROD_ENDPTS4 + Determines whether slice 4 is an endpoint. + 4 + 1 + read-write + + + NO_EFFECT + No effect. Slice 4 is not an endpoint. + 0 + + + ENDPOINT + endpoint. Slice 4 is the endpoint of a product term (minterm). Pin interrupt 4 in the NVIC is raised if the minterm evaluates as true. + 0x1 + + + + + PROD_ENDPTS5 + Determines whether slice 5 is an endpoint. + 5 + 1 + read-write + + + NO_EFFECT + No effect. Slice 5 is not an endpoint. + 0 + + + ENDPOINT + endpoint. Slice 5 is the endpoint of a product term (minterm). Pin interrupt 5 in the NVIC is raised if the minterm evaluates as true. + 0x1 + + + + + PROD_ENDPTS6 + Determines whether slice 6 is an endpoint. + 6 + 1 + read-write + + + NO_EFFECT + No effect. Slice 6 is not an endpoint. + 0 + + + ENDPOINT + endpoint. Slice 6 is the endpoint of a product term (minterm). Pin interrupt 6 in the NVIC is raised if the minterm evaluates as true. + 0x1 + + + + + CFG0 + Specifies the match contribution condition for bit slice 0. + 8 + 3 + read-write + + + CONSTANT_HIGH + Constant HIGH. This bit slice always contributes to a product term match. + 0 + + + STICKY_RISING_EDGE + Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + 0x1 + + + STICKY_FALLING_EDGE + Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + 0x2 + + + STICKY_RISING_FALLING_EDGE + Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + 0x3 + + + HIGH_LEVEL + High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + 0x4 + + + LOW_LEVEL + Low level. Match occurs when there is a low level on the specified input. + 0x5 + + + CONSTANT_ZERO + Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + 0x6 + + + EVENT + Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. + 0x7 + + + + + CFG1 + Specifies the match contribution condition for bit slice 1. + 11 + 3 + read-write + + + CONSTANT_HIGH + Constant HIGH. This bit slice always contributes to a product term match. + 0 + + + STICKY_RISING_EDGE + Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + 0x1 + + + STICKY_FALLING_EDGE + Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + 0x2 + + + STICKY_RISING_FALLING_EDGE + Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + 0x3 + + + HIGH_LEVEL + High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + 0x4 + + + LOW_LEVEL + Low level. Match occurs when there is a low level on the specified input. + 0x5 + + + CONSTANT_ZERO + Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + 0x6 + + + EVENT + Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. + 0x7 + + + + + CFG2 + Specifies the match contribution condition for bit slice 2. + 14 + 3 + read-write + + + CONSTANT_HIGH + Constant HIGH. This bit slice always contributes to a product term match. + 0 + + + STICKY_RISING_EDGE + Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + 0x1 + + + STICKY_FALLING_EDGE + Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + 0x2 + + + STICKY_RISING_FALLING_EDGE + Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + 0x3 + + + HIGH_LEVEL + High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + 0x4 + + + LOW_LEVEL + Low level. Match occurs when there is a low level on the specified input. + 0x5 + + + CONSTANT_ZERO + Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + 0x6 + + + EVENT + Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. + 0x7 + + + + + CFG3 + Specifies the match contribution condition for bit slice 3. + 17 + 3 + read-write + + + CONSTANT_HIGH + Constant HIGH. This bit slice always contributes to a product term match. + 0 + + + STICKY_RISING_EDGE + Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + 0x1 + + + STICKY_FALLING_EDGE + Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + 0x2 + + + STICKY_RISING_FALLING_EDGE + Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + 0x3 + + + HIGH_LEVEL + High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + 0x4 + + + LOW_LEVEL + Low level. Match occurs when there is a low level on the specified input. + 0x5 + + + CONSTANT_ZERO + Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + 0x6 + + + EVENT + Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. + 0x7 + + + + + CFG4 + Specifies the match contribution condition for bit slice 4. + 20 + 3 + read-write + + + CONSTANT_HIGH + Constant HIGH. This bit slice always contributes to a product term match. + 0 + + + STICKY_RISING_EDGE + Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + 0x1 + + + STICKY_FALLING_EDGE + Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + 0x2 + + + STICKY_RISING_FALLING_EDGE + Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + 0x3 + + + HIGH_LEVEL + High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + 0x4 + + + LOW_LEVEL + Low level. Match occurs when there is a low level on the specified input. + 0x5 + + + CONSTANT_ZERO + Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + 0x6 + + + EVENT + Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. + 0x7 + + + + + CFG5 + Specifies the match contribution condition for bit slice 5. + 23 + 3 + read-write + + + CONSTANT_HIGH + Constant HIGH. This bit slice always contributes to a product term match. + 0 + + + STICKY_RISING_EDGE + Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + 0x1 + + + STICKY_FALLING_EDGE + Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + 0x2 + + + STICKY_RISING_FALLING_EDGE + Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + 0x3 + + + HIGH_LEVEL + High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + 0x4 + + + LOW_LEVEL + Low level. Match occurs when there is a low level on the specified input. + 0x5 + + + CONSTANT_ZERO + Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + 0x6 + + + EVENT + Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. + 0x7 + + + + + CFG6 + Specifies the match contribution condition for bit slice 6. + 26 + 3 + read-write + + + CONSTANT_HIGH + Constant HIGH. This bit slice always contributes to a product term match. + 0 + + + STICKY_RISING_EDGE + Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + 0x1 + + + STICKY_FALLING_EDGE + Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + 0x2 + + + STICKY_RISING_FALLING_EDGE + Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + 0x3 + + + HIGH_LEVEL + High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + 0x4 + + + LOW_LEVEL + Low level. Match occurs when there is a low level on the specified input. + 0x5 + + + CONSTANT_ZERO + Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + 0x6 + + + EVENT + Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. + 0x7 + + + + + CFG7 + Specifies the match contribution condition for bit slice 7. + 29 + 3 + read-write + + + CONSTANT_HIGH + Constant HIGH. This bit slice always contributes to a product term match. + 0 + + + STICKY_RISING_EDGE + Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + 0x1 + + + STICKY_FALLING_EDGE + Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + 0x2 + + + STICKY_RISING_FALLING_EDGE + Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + 0x3 + + + HIGH_LEVEL + High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + 0x4 + + + LOW_LEVEL + Low level. Match occurs when there is a low level on the specified input. + 0x5 + + + CONSTANT_ZERO + Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + 0x6 + + + EVENT + Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. + 0x7 + + + + + + + + + SECPINT + Pin interrupt and pattern match (PINT) + PINT + 0x40005000 + + 0 + 0x34 + registers + + + SEC_GPIO_INT0_IRQ0 + 50 + + + SEC_GPIO_INT0_IRQ1 + 51 + + + + INPUTMUX + Input multiplexing (INPUT MUX) + INPUTMUX + 0x40006000 + + 0 + 0x7B4 + registers + + + + 7 + 0x4 + SCT0_INMUX[%s] + Input mux register for SCT0 input + 0 + 32 + read-write + 0x1F + 0x1F + + + INP_N + Input number to SCT0 inputs 0 to 6.. + 0 + 5 + read-write + + + val0 + SCT_GPI0 function selected from IOCON register + 0 + + + val1 + SCT_GPI1 function selected from IOCON register + 0x1 + + + val2 + SCT_GPI2 function selected from IOCON register + 0x2 + + + val3 + SCT_GPI3 function selected from IOCON register + 0x3 + + + val4 + SCT_GPI4 function selected from IOCON register + 0x4 + + + val5 + SCT_GPI5 function selected from IOCON register + 0x5 + + + val6 + SCT_GPI6 function selected from IOCON register + 0x6 + + + val7 + SCT_GPI7 function selected from IOCON register + 0x7 + + + val8 + T0_OUT0 ctimer 0 match[0] output + 0x8 + + + val9 + T1_OUT0 ctimer 1 match[0] output + 0x9 + + + val10 + T2_OUT0 ctimer 2 match[0] output + 0xA + + + val11 + T3_OUT0 ctimer 3 match[0] output + 0xB + + + val12 + T4_OUT0 ctimer 4 match[0] output + 0xC + + + val13 + ADC_IRQ interrupt request from ADC + 0xD + + + val14 + GPIOINT_BMATCH + 0xE + + + val15 + USB0_FRAME_TOGGLE + 0xF + + + val16 + USB1_FRAME_TOGGLE + 0x10 + + + val17 + COMP_OUTPUT output from analog comparator + 0x11 + + + val18 + I2S_SHARED_SCK[0] output from I2S pin sharing + 0x12 + + + val19 + I2S_SHARED_SCK[1] output from I2S pin sharing + 0x13 + + + val20 + I2S_SHARED_WS[0] output from I2S pin sharing + 0x14 + + + val21 + I2S_SHARED_WS[1] output from I2S pin sharing + 0x15 + + + val22 + ARM_TXEV interrupt event from cpu0 or cpu1 + 0x16 + + + val23 + DEBUG_HALTED from cpu0 or cpu1 + 0x17 + + + val24 + None + 0x18 + + + val24 + None + 0x19 + + + val24 + None + 0x1A + + + val24 + None + 0x1B + + + val24 + None + 0x1C + + + val24 + None + 0x1D + + + val24 + None + 0x1E + + + val24 + None + 0x1F + + + + + + + 4 + 0x4 + TIMER0CAPTSEL[%s] + Capture select registers for TIMER0 inputs + 0x20 + 32 + read-write + 0x1F + 0x1F + + + CAPTSEL + Input number to TIMER0 capture inputs 0 to 4 + 0 + 5 + read-write + + + val0 + CT_INP0 function selected from IOCON register + 0 + + + val1 + CT_INP1 function selected from IOCON register + 0x1 + + + val2 + CT_INP2 function selected from IOCON register + 0x2 + + + val3 + CT_INP3 function selected from IOCON register + 0x3 + + + val4 + CT_INP4 function selected from IOCON register + 0x4 + + + val5 + CT_INP5 function selected from IOCON register + 0x5 + + + val6 + CT_INP6 function selected from IOCON register + 0x6 + + + val7 + CT_INP7 function selected from IOCON register + 0x7 + + + val8 + CT_INP8 function selected from IOCON register + 0x8 + + + val9 + CT_INP9 function selected from IOCON register + 0x9 + + + val10 + CT_INP10 function selected from IOCON register + 0xA + + + val11 + CT_INP11 function selected from IOCON register + 0xB + + + val12 + CT_INP12 function selected from IOCON register + 0xC + + + val13 + CT_INP13 function selected from IOCON register + 0xD + + + val14 + CT_INP14 function selected from IOCON register + 0xE + + + val15 + CT_INP15 function selected from IOCON register + 0xF + + + val16 + CT_INP16 function selected from IOCON register + 0x10 + + + val17 + CT_INP17 function selected from IOCON register + 0x11 + + + val18 + CT_INP18 function selected from IOCON register + 0x12 + + + val19 + CT_INP19 function selected from IOCON register + 0x13 + + + val20 + USB0_FRAME_TOGGLE + 0x14 + + + val21 + USB1_FRAME_TOGGLE + 0x15 + + + val22 + COMP_OUTPUT output from analog comparator + 0x16 + + + val23 + I2S_SHARED_WS[0] output from I2S pin sharing + 0x17 + + + val24 + I2S_SHARED_WS[1] output from I2S pin sharing + 0x18 + + + val25 + None + 0x19 + + + val25 + None + 0x1A + + + val25 + None + 0x1B + + + val25 + None + 0x1C + + + val25 + None + 0x1D + + + val25 + None + 0x1E + + + val25 + None + 0x1F + + + + + + + 4 + 0x4 + TIMER1CAPTSEL[%s] + Capture select registers for TIMER1 inputs + 0x40 + 32 + read-write + 0x1F + 0x1F + + + CAPTSEL + Input number to TIMER1 capture inputs 0 to 4 + 0 + 5 + read-write + + + val0 + CT_INP0 function selected from IOCON register + 0 + + + val1 + CT_INP1 function selected from IOCON register + 0x1 + + + val2 + CT_INP2 function selected from IOCON register + 0x2 + + + val3 + CT_INP3 function selected from IOCON register + 0x3 + + + val4 + CT_INP4 function selected from IOCON register + 0x4 + + + val5 + CT_INP5 function selected from IOCON register + 0x5 + + + val6 + CT_INP6 function selected from IOCON register + 0x6 + + + val7 + CT_INP7 function selected from IOCON register + 0x7 + + + val8 + CT_INP8 function selected from IOCON register + 0x8 + + + val9 + CT_INP9 function selected from IOCON register + 0x9 + + + val10 + CT_INP10 function selected from IOCON register + 0xA + + + val11 + CT_INP11 function selected from IOCON register + 0xB + + + val12 + CT_INP12 function selected from IOCON register + 0xC + + + val13 + CT_INP13 function selected from IOCON register + 0xD + + + val14 + CT_INP14 function selected from IOCON register + 0xE + + + val15 + CT_INP15 function selected from IOCON register + 0xF + + + val16 + CT_INP16 function selected from IOCON register + 0x10 + + + val17 + CT_INP17 function selected from IOCON register + 0x11 + + + val18 + CT_INP18 function selected from IOCON register + 0x12 + + + val19 + CT_INP19 function selected from IOCON register + 0x13 + + + val20 + USB0_FRAME_TOGGLE + 0x14 + + + val21 + USB1_FRAME_TOGGLE + 0x15 + + + val22 + COMP_OUTPUT output from analog comparator + 0x16 + + + val23 + I2S_SHARED_WS[0] output from I2S pin sharing + 0x17 + + + val24 + I2S_SHARED_WS[1] output from I2S pin sharing + 0x18 + + + val25 + None + 0x19 + + + val25 + None + 0x1A + + + val25 + None + 0x1B + + + val25 + None + 0x1C + + + val25 + None + 0x1D + + + val25 + None + 0x1E + + + val25 + None + 0x1F + + + + + + + 4 + 0x4 + TIMER2CAPTSEL[%s] + Capture select registers for TIMER2 inputs + 0x60 + 32 + read-write + 0x1F + 0x1F + + + CAPTSEL + Input number to TIMER2 capture inputs 0 to 4 + 0 + 5 + read-write + + + val0 + CT_INP0 function selected from IOCON register + 0 + + + val1 + CT_INP1 function selected from IOCON register + 0x1 + + + val2 + CT_INP2 function selected from IOCON register + 0x2 + + + val3 + CT_INP3 function selected from IOCON register + 0x3 + + + val4 + CT_INP4 function selected from IOCON register + 0x4 + + + val5 + CT_INP5 function selected from IOCON register + 0x5 + + + val6 + CT_INP6 function selected from IOCON register + 0x6 + + + val7 + CT_INP7 function selected from IOCON register + 0x7 + + + val8 + CT_INP8 function selected from IOCON register + 0x8 + + + val9 + CT_INP9 function selected from IOCON register + 0x9 + + + val10 + CT_INP10 function selected from IOCON register + 0xA + + + val11 + CT_INP11 function selected from IOCON register + 0xB + + + val12 + CT_INP12 function selected from IOCON register + 0xC + + + val13 + CT_INP13 function selected from IOCON register + 0xD + + + val14 + CT_INP14 function selected from IOCON register + 0xE + + + val15 + CT_INP15 function selected from IOCON register + 0xF + + + val16 + CT_INP16 function selected from IOCON register + 0x10 + + + val17 + CT_INP17 function selected from IOCON register + 0x11 + + + val18 + CT_INP18 function selected from IOCON register + 0x12 + + + val19 + CT_INP19 function selected from IOCON register + 0x13 + + + val20 + USB0_FRAME_TOGGLE + 0x14 + + + val21 + USB1_FRAME_TOGGLE + 0x15 + + + val22 + COMP_OUTPUT output from analog comparator + 0x16 + + + val23 + I2S_SHARED_WS[0] output from I2S pin sharing + 0x17 + + + val24 + I2S_SHARED_WS[1] output from I2S pin sharing + 0x18 + + + val25 + None + 0x19 + + + val25 + None + 0x1A + + + val25 + None + 0x1B + + + val25 + None + 0x1C + + + val25 + None + 0x1D + + + val25 + None + 0x1E + + + val25 + None + 0x1F + + + + + + + 8 + 0x4 + PINTSEL[%s] + Pin interrupt select register + 0xC0 + 32 + read-write + 0x7F + 0x7F + + + INTPIN + Pin number select for pin interrupt or pattern match engine input. For PIOx_y: INTPIN = (x * 32) + y. PIO0_0 to PIO1_31 correspond to numbers 0 to 63. + 0 + 7 + read-write + + + + + 23 + 0x4 + DMA0_ITRIG_INMUX[%s] + Trigger select register for DMA0 channel + 0xE0 + 32 + read-write + 0x1F + 0x1F + + + INP + Trigger input number (decimal value) for DMA channel n (n = 0 to 22). + 0 + 5 + read-write + + + val0 + Pin interrupt 0 + 0 + + + val1 + Pin interrupt 1 + 0x1 + + + val2 + Pin interrupt 2 + 0x2 + + + val3 + Pin interrupt 3 + 0x3 + + + val4 + Timer CTIMER0 Match 0 + 0x4 + + + val5 + Timer CTIMER0 Match 1 + 0x5 + + + val6 + Timer CTIMER1 Match 0 + 0x6 + + + val7 + Timer CTIMER1 Match 1 + 0x7 + + + val8 + Timer CTIMER2 Match 0 + 0x8 + + + val9 + Timer CTIMER2 Match 1 + 0x9 + + + val10 + Timer CTIMER3 Match 0 + 0xA + + + val11 + Timer CTIMER3 Match 1 + 0xB + + + val12 + Timer CTIMER4 Match 0 + 0xC + + + val13 + Timer CTIMER4 Match 1 + 0xD + + + val14 + COMP_OUTPUT + 0xE + + + val15 + DMA0 output trigger mux 0 + 0xF + + + val16 + DMA0 output trigger mux 1 + 0x10 + + + val17 + DMA0 output trigger mux 1 + 0x11 + + + val18 + DMA0 output trigger mux 3 + 0x12 + + + val19 + SCT0 DMA request 0 + 0x13 + + + val20 + SCT0 DMA request 1 + 0x14 + + + val21 + HASH DMA RX trigger + 0x15 + + + val22 + None + 0x16 + + + val22 + None + 0x17 + + + val22 + None + 0x18 + + + val22 + None + 0x19 + + + val22 + None + 0x1A + + + val22 + None + 0x1B + + + val22 + None + 0x1C + + + val22 + None + 0x1D + + + val22 + None + 0x1E + + + val22 + None + 0x1F + + + + + + + 4 + 0x4 + DMA0_OTRIG_INMUX[%s] + DMA0 output trigger selection to become DMA0 trigger + 0x160 + 32 + read-write + 0x1F + 0x1F + + + INP + DMA trigger output number (decimal value) for DMA channel n (n = 0 to 22). + 0 + 5 + read-write + + + + + FREQMEAS_REF + Selection for frequency measurement reference clock + 0x180 + 32 + read-write + 0x1F + 0x1F + + + CLKIN + Clock source number (decimal value) for frequency measure function target clock: 0 = CLK_IN 1 = FRO 12 MHz oscillator 2 = Watchdog oscillator 3 = 32 kHz RTC oscillator 4 = Main clock (see Section 4.5.23) 5 = PIO0_4 6 = PIO0_20 7 = PIO0_24 8 = PIO1_4 + 0 + 5 + read-write + + + + + FREQMEAS_TARGET + Selection for frequency measurement target clock + 0x184 + 32 + read-write + 0x1F + 0x1F + + + CLKIN + Clock source number (decimal value) for frequency measure function target clock: 0 = CLK_IN 1 = FRO 12 MHz oscillator 2 = Watchdog oscillator 3 = 32 kHz RTC oscillator 4 = Main clock (see Section 4.5.23) 5 = PIO0_4 6 = PIO0_20 7 = PIO0_24 8 = PIO1_4 + 0 + 5 + read-write + + + + + 4 + 0x4 + TIMER3CAPTSEL[%s] + Capture select registers for TIMER3 inputs + 0x1A0 + 32 + read-write + 0x1F + 0x1F + + + CAPTSEL + Input number to TIMER3 capture inputs 0 to 4 + 0 + 5 + read-write + + + val0 + CT_INP0 function selected from IOCON register + 0 + + + val1 + CT_INP1 function selected from IOCON register + 0x1 + + + val2 + CT_INP2 function selected from IOCON register + 0x2 + + + val3 + CT_INP3 function selected from IOCON register + 0x3 + + + val4 + CT_INP4 function selected from IOCON register + 0x4 + + + val5 + CT_INP5 function selected from IOCON register + 0x5 + + + val6 + CT_INP6 function selected from IOCON register + 0x6 + + + val7 + CT_INP7 function selected from IOCON register + 0x7 + + + val8 + CT_INP8 function selected from IOCON register + 0x8 + + + val9 + CT_INP9 function selected from IOCON register + 0x9 + + + val10 + CT_INP10 function selected from IOCON register + 0xA + + + val11 + CT_INP11 function selected from IOCON register + 0xB + + + val12 + CT_INP12 function selected from IOCON register + 0xC + + + val13 + CT_INP13 function selected from IOCON register + 0xD + + + val14 + CT_INP14 function selected from IOCON register + 0xE + + + val15 + CT_INP15 function selected from IOCON register + 0xF + + + val16 + CT_INP16 function selected from IOCON register + 0x10 + + + val17 + CT_INP17 function selected from IOCON register + 0x11 + + + val18 + CT_INP18 function selected from IOCON register + 0x12 + + + val19 + CT_INP19 function selected from IOCON register + 0x13 + + + val20 + USB0_FRAME_TOGGLE + 0x14 + + + val21 + USB1_FRAME_TOGGLE + 0x15 + + + val22 + COMP_OUTPUT output from analog comparator + 0x16 + + + val23 + I2S_SHARED_WS[0] output from I2S pin sharing + 0x17 + + + val24 + I2S_SHARED_WS[1] output from I2S pin sharing + 0x18 + + + val25 + None + 0x19 + + + val25 + None + 0x1A + + + val25 + None + 0x1B + + + val25 + None + 0x1C + + + val25 + None + 0x1D + + + val25 + None + 0x1E + + + val25 + None + 0x1F + + + + + + + 4 + 0x4 + TIMER4CAPTSEL[%s] + Capture select registers for TIMER4 inputs + 0x1C0 + 32 + read-write + 0x1F + 0x1F + + + CAPTSEL + Input number to TIMER4 capture inputs 0 to 4 + 0 + 5 + read-write + + + val0 + CT_INP0 function selected from IOCON register + 0 + + + val1 + CT_INP1 function selected from IOCON register + 0x1 + + + val2 + CT_INP2 function selected from IOCON register + 0x2 + + + val3 + CT_INP3 function selected from IOCON register + 0x3 + + + val4 + CT_INP4 function selected from IOCON register + 0x4 + + + val5 + CT_INP5 function selected from IOCON register + 0x5 + + + val6 + CT_INP6 function selected from IOCON register + 0x6 + + + val7 + CT_INP7 function selected from IOCON register + 0x7 + + + val8 + CT_INP8 function selected from IOCON register + 0x8 + + + val9 + CT_INP9 function selected from IOCON register + 0x9 + + + val10 + CT_INP10 function selected from IOCON register + 0xA + + + val11 + CT_INP11 function selected from IOCON register + 0xB + + + val12 + CT_INP12 function selected from IOCON register + 0xC + + + val13 + CT_INP13 function selected from IOCON register + 0xD + + + val14 + CT_INP14 function selected from IOCON register + 0xE + + + val15 + CT_INP15 function selected from IOCON register + 0xF + + + val16 + CT_INP16 function selected from IOCON register + 0x10 + + + val17 + CT_INP17 function selected from IOCON register + 0x11 + + + val18 + CT_INP18 function selected from IOCON register + 0x12 + + + val19 + CT_INP19 function selected from IOCON register + 0x13 + + + val20 + USB0_FRAME_TOGGLE + 0x14 + + + val21 + USB1_FRAME_TOGGLE + 0x15 + + + val22 + COMP_OUTPUT output from analog comparator + 0x16 + + + val23 + I2S_SHARED_WS[0] output from I2S pin sharing + 0x17 + + + val24 + I2S_SHARED_WS[1] output from I2S pin sharing + 0x18 + + + val25 + None + 0x19 + + + val25 + None + 0x1A + + + val25 + None + 0x1B + + + val25 + None + 0x1C + + + val25 + None + 0x1D + + + val25 + None + 0x1E + + + val25 + None + 0x1F + + + + + + + 2 + 0x4 + PINTSECSEL[%s] + Pin interrupt secure select register + 0x1E0 + 32 + read-write + 0x3F + 0x3F + + + INTPIN + Pin number select for pin interrupt secure or pattern match engine input. For PIO0_x: INTPIN = x. PIO0_0 to PIO0_31 correspond to numbers 0 to 31. + 0 + 6 + read-write + + + + + 10 + 0x4 + DMA1_ITRIG_INMUX[%s] + Trigger select register for DMA1 channel + 0x200 + 32 + read-write + 0xF + 0xF + + + INP + Trigger input number (decimal value) for DMA channel n (n = 0 to 9). + 0 + 4 + read-write + + + val0 + Pin interrupt 0 + 0 + + + val1 + Pin interrupt 1 + 0x1 + + + val2 + Pin interrupt 2 + 0x2 + + + val3 + Pin interrupt 3 + 0x3 + + + val4 + Timer CTIMER0 Match 0 + 0x4 + + + val5 + Timer CTIMER0 Match 1 + 0x5 + + + val6 + Timer CTIMER2 Match 0 + 0x6 + + + val7 + Timer CTIMER4 Match 0 + 0x7 + + + val8 + DMA1 output trigger mux 0 + 0x8 + + + val9 + DMA1 output trigger mux 1 + 0x9 + + + val10 + DMA1 output trigger mux 2 + 0xA + + + val11 + DMA1 output trigger mux 3 + 0xB + + + val12 + SCT0 DMA request 0 + 0xC + + + val13 + SCT0 DMA request 1 + 0xD + + + val14 + HASH DMA RX trigger + 0xE + + + val15 + None + 0xF + + + + + + + 4 + 0x4 + DMA1_OTRIG_INMUX[%s] + DMA1 output trigger selection to become DMA1 trigger + 0x240 + 32 + read-write + 0xF + 0xF + + + INP + DMA trigger output number (decimal value) for DMA channel n (n = 0 to 9). + 0 + 4 + read-write + + + + + DMA0_REQ_ENA + Enable DMA0 requests + 0x740 + 32 + read-write + 0x7FFFFF + 0x7FFFFF + + + REQ_ENA + Controls the 23 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled. + 0 + 23 + read-write + + + + + DMA0_REQ_ENA_SET + Set one or several bits in DMA0_REQ_ENA register + 0x748 + 32 + write-only + 0 + 0x7FFFFF + + + SET + Write : If bit #i = 1, bit #i in DMA0_REQ_ENA register is set to 1; if bit #i = 0 , no change in DMA0_REQ_ENA register + 0 + 23 + write-only + + + + + DMA0_REQ_ENA_CLR + Clear one or several bits in DMA0_REQ_ENA register + 0x750 + 32 + write-only + 0 + 0x7FFFFF + + + CLR + Write : If bit #i = 1, bit #i in DMA0_REQ_ENA register is reset to 0; if bit #i = 0 , no change in DMA0_REQ_ENA register + 0 + 23 + write-only + + + + + DMA1_REQ_ENA + Enable DMA1 requests + 0x760 + 32 + read-write + 0x3FF + 0x3FF + + + REQ_ENA + Controls the 10 request inputs of DMA1. If bit i is '1' the DMA request input #i is enabled. + 0 + 10 + read-write + + + + + DMA1_REQ_ENA_SET + Set one or several bits in DMA1_REQ_ENA register + 0x768 + 32 + write-only + 0 + 0x3FF + + + SET + Write : If bit #i = 1, bit #i in DMA1_REQ_ENA register is set to 1; if bit #i = 0 , no change in DMA1_REQ_ENA register + 0 + 10 + write-only + + + + + DMA1_REQ_ENA_CLR + Clear one or several bits in DMA1_REQ_ENA register + 0x770 + 32 + write-only + 0 + 0x3FF + + + CLR + Write : If bit #i = 1, bit #i in DMA1_REQ_ENA register is reset to 0; if bit #i = 0 , no change in DMA1_REQ_ENA register + 0 + 10 + write-only + + + + + DMA0_ITRIG_ENA + Enable DMA0 triggers + 0x780 + 32 + read-write + 0x3FFFFF + 0x3FFFFF + + + ITRIG_ENA + Controls the 22 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled. + 0 + 22 + read-write + + + + + DMA0_ITRIG_ENA_SET + Set one or several bits in DMA0_ITRIG_ENA register + 0x788 + 32 + write-only + 0 + 0x3FFFFF + + + SET + Write : If bit #i = 1, bit #i in DMA0_ITRIG_ENA register is set to 1; if bit #i = 0 , no change in DMA0_ITRIG_ENA register + 0 + 22 + write-only + + + + + DMA0_ITRIG_ENA_CLR + Clear one or several bits in DMA0_ITRIG_ENA register + 0x790 + 32 + write-only + 0 + 0x3FFFFF + + + CLR + Write : If bit #i = 1, bit #i in DMA0_ITRIG_ENA register is reset to 0; if bit #i = 0 , no change in DMA0_ITRIG_ENA register + 0 + 22 + write-only + + + + + DMA1_ITRIG_ENA + Enable DMA1 triggers + 0x7A0 + 32 + read-write + 0x7FFF + 0x7FFF + + + ITRIG_ENA + Controls the 15 trigger inputs of DMA1. If bit i is '1' the DMA trigger input #i is enabled. + 0 + 15 + read-write + + + + + DMA1_ITRIG_ENA_SET + Set one or several bits in DMA1_ITRIG_ENA register + 0x7A8 + 32 + write-only + 0 + 0x7FFF + + + SET + Write : If bit #i = 1, bit #i in DMA1_ITRIG_ENA register is set to 1; if bit #i = 0 , no change in DMA1_ITRIG_ENA register + 0 + 15 + write-only + + + + + DMA1_ITRIG_ENA_CLR + Clear one or several bits in DMA1_ITRIG_ENA register + 0x7B0 + 32 + write-only + 0 + 0x7FFF + + + CLR + Write : If bit #i = 1, bit #i in DMA1_ITRIG_ENA register is reset to 0; if bit #i = 0 , no change in DMA1_ITRIG_ENA register + 0 + 15 + write-only + + + + + + + CTIMER0 + Standard counter/timers (CTIMER0 to 4) + CTIMER + CTIMER + 0x40008000 + + 0 + 0x88 + registers + + + CTIMER0 + 10 + + + + IR + Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. + 0 + 32 + read-write + 0 + 0xFF + + + MR0INT + Interrupt flag for match channel 0. + 0 + 1 + read-write + + + MR1INT + Interrupt flag for match channel 1. + 1 + 1 + read-write + + + MR2INT + Interrupt flag for match channel 2. + 2 + 1 + read-write + + + MR3INT + Interrupt flag for match channel 3. + 3 + 1 + read-write + + + CR0INT + Interrupt flag for capture channel 0 event. + 4 + 1 + read-write + + + CR1INT + Interrupt flag for capture channel 1 event. + 5 + 1 + read-write + + + CR2INT + Interrupt flag for capture channel 2 event. + 6 + 1 + read-write + + + CR3INT + Interrupt flag for capture channel 3 event. + 7 + 1 + read-write + + + + + TCR + Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. + 0x4 + 32 + read-write + 0 + 0x3 + + + CEN + Counter enable. + 0 + 1 + read-write + + + DISABLED + Disabled.The counters are disabled. + 0 + + + ENABLED + Enabled. The Timer Counter and Prescale Counter are enabled. + 0x1 + + + + + CRST + Counter reset. + 1 + 1 + read-write + + + DISABLED + Disabled. Do nothing. + 0 + + + ENABLED + Enabled. The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of the APB bus clock. The counters remain reset until TCR[1] is returned to zero. + 0x1 + + + + + + + TC + Timer Counter + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + TCVAL + Timer counter value. + 0 + 32 + read-write + + + + + PR + Prescale Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + PRVAL + Prescale counter value. + 0 + 32 + read-write + + + + + PC + Prescale Counter + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + PCVAL + Prescale counter value. + 0 + 32 + read-write + + + + + MCR + Match Control Register + 0x14 + 32 + read-write + 0 + 0xF000FFF + + + MR0I + Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. + 0 + 1 + read-write + + + MR0R + Reset on MR0: the TC will be reset if MR0 matches it. + 1 + 1 + read-write + + + MR0S + Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. + 2 + 1 + read-write + + + MR1I + Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC. + 3 + 1 + read-write + + + MR1R + Reset on MR1: the TC will be reset if MR1 matches it. + 4 + 1 + read-write + + + MR1S + Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. + 5 + 1 + read-write + + + MR2I + Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. + 6 + 1 + read-write + + + MR2R + Reset on MR2: the TC will be reset if MR2 matches it. + 7 + 1 + read-write + + + MR2S + Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC. + 8 + 1 + read-write + + + MR3I + Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC. + 9 + 1 + read-write + + + MR3R + Reset on MR3: the TC will be reset if MR3 matches it. + 10 + 1 + read-write + + + MR3S + Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. + 11 + 1 + read-write + + + MR0RL + Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR). + 24 + 1 + read-write + + + MR1RL + Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR). + 25 + 1 + read-write + + + MR2RL + Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR). + 26 + 1 + read-write + + + MR3RL + Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR). + 27 + 1 + read-write + + + + + 4 + 0x4 + MR[%s] + Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + MATCH + Timer counter match value. + 0 + 32 + read-write + + + + + CCR + Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. + 0x28 + 32 + read-write + 0 + 0xFFF + + + CAP0RE + Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. + 0 + 1 + read-write + + + CAP0FE + Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. + 1 + 1 + read-write + + + CAP0I + Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt. + 2 + 1 + read-write + + + CAP1RE + Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. + 3 + 1 + read-write + + + CAP1FE + Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. + 4 + 1 + read-write + + + CAP1I + Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt. + 5 + 1 + read-write + + + CAP2RE + Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. + 6 + 1 + read-write + + + CAP2FE + Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. + 7 + 1 + read-write + + + CAP2I + Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt. + 8 + 1 + read-write + + + CAP3RE + Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. + 9 + 1 + read-write + + + CAP3FE + Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. + 10 + 1 + read-write + + + CAP3I + Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt. + 11 + 1 + read-write + + + + + 4 + 0x4 + CR[%s] + Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input. + 0x2C + 32 + read-only + 0 + 0xFFFFFFFF + + + CAP + Timer counter capture value. + 0 + 32 + read-only + + + + + EMR + External Match Register. The EMR controls the match function and the external match pins. + 0x3C + 32 + read-write + 0 + 0xFFF + + + EM0 + External Match 0. This bit reflects the state of output MAT0, whether or not this output is connected to a pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by EMR[5:4]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH. + 0 + 1 + read-write + + + EM1 + External Match 1. This bit reflects the state of output MAT1, whether or not this output is connected to a pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by EMR[7:6]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH. + 1 + 1 + read-write + + + EM2 + External Match 2. This bit reflects the state of output MAT2, whether or not this output is connected to a pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by EMR[9:8]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH. + 2 + 1 + read-write + + + EM3 + External Match 3. This bit reflects the state of output MAT3, whether or not this output is connected to a pin. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by MR[11:10]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH. + 3 + 1 + read-write + + + EMC0 + External Match Control 0. Determines the functionality of External Match 0. + 4 + 2 + read-write + + + DO_NOTHING + Do Nothing. + 0 + + + CLEAR + Clear. Clear the corresponding External Match bit/output to 0 (MAT0 pin is LOW if pinned out). + 0x1 + + + SET + Set. Set the corresponding External Match bit/output to 1 (MAT0 pin is HIGH if pinned out). + 0x2 + + + TOGGLE + Toggle. Toggle the corresponding External Match bit/output. + 0x3 + + + + + EMC1 + External Match Control 1. Determines the functionality of External Match 1. + 6 + 2 + read-write + + + DO_NOTHING + Do Nothing. + 0 + + + CLEAR + Clear. Clear the corresponding External Match bit/output to 0 (MAT1 pin is LOW if pinned out). + 0x1 + + + SET + Set. Set the corresponding External Match bit/output to 1 (MAT1 pin is HIGH if pinned out). + 0x2 + + + TOGGLE + Toggle. Toggle the corresponding External Match bit/output. + 0x3 + + + + + EMC2 + External Match Control 2. Determines the functionality of External Match 2. + 8 + 2 + read-write + + + DO_NOTHING + Do Nothing. + 0 + + + CLEAR + Clear. Clear the corresponding External Match bit/output to 0 (MAT2 pin is LOW if pinned out). + 0x1 + + + SET + Set. Set the corresponding External Match bit/output to 1 (MAT2 pin is HIGH if pinned out). + 0x2 + + + TOGGLE + Toggle. Toggle the corresponding External Match bit/output. + 0x3 + + + + + EMC3 + External Match Control 3. Determines the functionality of External Match 3. + 10 + 2 + read-write + + + DO_NOTHING + Do Nothing. + 0 + + + CLEAR + Clear. Clear the corresponding External Match bit/output to 0 (MAT3 pin is LOW if pinned out). + 0x1 + + + SET + Set. Set the corresponding External Match bit/output to 1 (MAT3 pin is HIGH if pinned out). + 0x2 + + + TOGGLE + Toggle. Toggle the corresponding External Match bit/output. + 0x3 + + + + + + + CTCR + Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. + 0x70 + 32 + read-write + 0 + 0xFF + + + CTMODE + Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register. + 0 + 2 + read-write + + + TIMER + Timer Mode. Incremented every rising APB bus clock edge. + 0 + + + COUNTER_RISING_EDGE + Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2. + 0x1 + + + COUNTER_FALLING_EDGE + Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2. + 0x2 + + + COUNTER_DUAL_EDGE + Counter Mode dual edge. TC is incremented on both edges on the CAP input selected by bits 3:2. + 0x3 + + + + + CINSEL + Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer. + 2 + 2 + read-write + + + CHANNEL_0 + Channel 0. CAPn.0 for CTIMERn + 0 + + + CHANNEL_1 + Channel 1. CAPn.1 for CTIMERn + 0x1 + + + CHANNEL_2 + Channel 2. CAPn.2 for CTIMERn + 0x2 + + + CHANNEL_3 + Channel 3. CAPn.3 for CTIMERn + 0x3 + + + + + ENCC + Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs. + 4 + 1 + read-write + + + SELCC + Edge select. When bit 4 is 1, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved. + 5 + 3 + read-write + + + CHANNEL_0_RISING + Channel 0 Rising Edge. Rising edge of the signal on capture channel 0 clears the timer (if bit 4 is set). + 0 + + + CHANNEL_0_FALLING + Channel 0 Falling Edge. Falling edge of the signal on capture channel 0 clears the timer (if bit 4 is set). + 0x1 + + + CHANNEL_1_RISING + Channel 1 Rising Edge. Rising edge of the signal on capture channel 1 clears the timer (if bit 4 is set). + 0x2 + + + CHANNEL_1_FALLING + Channel 1 Falling Edge. Falling edge of the signal on capture channel 1 clears the timer (if bit 4 is set). + 0x3 + + + CHANNEL_2_RISING + Channel 2 Rising Edge. Rising edge of the signal on capture channel 2 clears the timer (if bit 4 is set). + 0x4 + + + CHANNEL_2_FALLING + Channel 2 Falling Edge. Falling edge of the signal on capture channel 2 clears the timer (if bit 4 is set). + 0x5 + + + + + + + PWMC + PWM Control Register. This register enables PWM mode for the external match pins. + 0x74 + 32 + read-write + 0 + 0xF + + + PWMEN0 + PWM mode enable for channel0. + 0 + 1 + read-write + + + MATCH + Match. CTIMERn_MAT0 is controlled by EM0. + 0 + + + PWM + PWM. PWM mode is enabled for CTIMERn_MAT0. + 0x1 + + + + + PWMEN1 + PWM mode enable for channel1. + 1 + 1 + read-write + + + MATCH + Match. CTIMERn_MAT01 is controlled by EM1. + 0 + + + PWM + PWM. PWM mode is enabled for CTIMERn_MAT1. + 0x1 + + + + + PWMEN2 + PWM mode enable for channel2. + 2 + 1 + read-write + + + MATCH + Match. CTIMERn_MAT2 is controlled by EM2. + 0 + + + PWM + PWM. PWM mode is enabled for CTIMERn_MAT2. + 0x1 + + + + + PWMEN3 + PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle. + 3 + 1 + read-write + + + MATCH + Match. CTIMERn_MAT3 is controlled by EM3. + 0 + + + PWM + PWM. PWM mode is enabled for CT132Bn_MAT3. + 0x1 + + + + + + + 4 + 0x4 + MSR[%s] + Match Shadow Register + 0x78 + 32 + read-write + 0 + 0xFFFFFFFF + + + SHADOWW + Timer counter match shadow value. + 0 + 32 + read-write + + + + + + + CTIMER1 + Standard counter/timers (CTIMER0 to 4) + CTIMER + 0x40009000 + + 0 + 0x88 + registers + + + CTIMER1 + 11 + + + + CTIMER2 + Standard counter/timers (CTIMER0 to 4) + CTIMER + 0x40028000 + + 0 + 0x88 + registers + + + CTIMER2 + 36 + + + + CTIMER3 + Standard counter/timers (CTIMER0 to 4) + CTIMER + 0x40029000 + + 0 + 0x88 + registers + + + CTIMER3 + 13 + + + + CTIMER4 + Standard counter/timers (CTIMER0 to 4) + CTIMER + 0x4002A000 + + 0 + 0x88 + registers + + + CTIMER4 + 37 + + + + WWDT + Windowed Watchdog Timer (WWDT) + WWDT + 0x4000C000 + + 0 + 0x1C + registers + + + WDT_BOD + 0 + + + + MOD + Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. + 0 + 32 + read-write + 0 + 0x3F + + + WDEN + Watchdog enable bit. Once this bit is set to one and a watchdog feed is performed, the watchdog timer will run permanently. + 0 + 1 + read-write + + + STOP + Stop. The watchdog timer is stopped. + 0 + + + RUN + Run. The watchdog timer is running. + 0x1 + + + + + WDRESET + Watchdog reset enable bit. Once this bit has been written with a 1 it cannot be re-written with a 0. + 1 + 1 + read-write + + + INTERRUPT + Interrupt. A watchdog time-out will not cause a chip reset. + 0 + + + RESET + Reset. A watchdog time-out will cause a chip reset. + 0x1 + + + + + WDTOF + Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by events associated with WDPROTECT. Cleared by software writing a 0 to this bit position. Causes a chip reset if WDRESET = 1. + 2 + 1 + read-write + + + WDINT + Warning interrupt flag. Set when the timer is at or below the value in WDWARNINT. Cleared by software writing a 1 to this bit position. Note that this bit cannot be cleared while the WARNINT value is equal to the value of the TV register. This can occur if the value of WARNINT is 0 and the WDRESET bit is 0 when TV decrements to 0. + 3 + 1 + read-write + + + WDPROTECT + Watchdog update mode. This bit can be set once by software and is only cleared by a reset. + 4 + 1 + read-write + + + FLEXIBLE + Flexible. The watchdog time-out value (TC) can be changed at any time. + 0 + + + THRESHOLD + Threshold. The watchdog time-out value (TC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW. + 0x1 + + + + + + + TC + Watchdog timer constant register. This 24-bit register determines the time-out value. + 0x4 + 32 + read-write + 0xFF + 0xFFFFFF + + + COUNT + Watchdog time-out value. + 0 + 24 + read-write + + + + + FEED + Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC. + 0x8 + 32 + write-only + 0 + 0 + + + FEED + Feed value should be 0xAA followed by 0x55. + 0 + 8 + write-only + + + + + TV + Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer. + 0xC + 32 + read-only + 0xFF + 0xFFFFFF + + + COUNT + Counter timer value. + 0 + 24 + read-only + + + + + WARNINT + Watchdog Warning Interrupt compare value. + 0x14 + 32 + read-write + 0 + 0x3FF + + + WARNINT + Watchdog warning interrupt compare value. + 0 + 10 + read-write + + + + + WINDOW + Watchdog Window compare value. + 0x18 + 32 + read-write + 0xFFFFFF + 0xFFFFFF + + + WINDOW + Watchdog window value. + 0 + 24 + read-write + + + + + + + MRT0 + Multi-Rate Timer (MRT) + MRT + 0x4000D000 + + 0 + 0xFC + registers + + + MRT0 + 9 + + + + 4 + 0x10 + CHANNEL[%s] + no description available + 0 + + INTVAL + MRT Time interval value register. This value is loaded into the TIMER register. + 0 + 32 + read-write + 0 + 0x80FFFFFF + + + IVALUE + Time interval load value. This value is loaded into the TIMERn register and the MRT channel n starts counting down from IVALUE -1. If the timer is idle, writing a non-zero value to this bit field starts the timer immediately. If the timer is running, writing a zero to this bit field does the following: If LOAD = 1, the timer stops immediately. If LOAD = 0, the timer stops at the end of the time interval. + 0 + 24 + read-write + + + LOAD + Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. This bit is write-only. Reading this bit always returns 0. + 31 + 1 + read-write + + + NO_FORCE_LOAD + No force load. The load from the INTVALn register to the TIMERn register is processed at the end of the time interval if the repeat mode is selected. + 0 + + + FORCE_LOAD + Force load. The INTVALn interval value IVALUE -1 is immediately loaded into the TIMERn register while TIMERn is running. + 0x1 + + + + + + + TIMER + MRT Timer register. This register reads the value of the down-counter. + 0x4 + 32 + read-only + 0xFFFFFF + 0xFFFFFF + + + VALUE + Holds the current timer value of the down-counter. The initial value of the TIMERn register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval or immediately in the following cases: INTVALn register is updated in the idle state. INTVALn register is updated with LOAD = 1. When the timer is in idle state, reading this bit fields returns -1 (0x00FF FFFF). + 0 + 24 + read-only + + + + + CTRL + MRT Control register. This register controls the MRT modes. + 0x8 + 32 + read-write + 0 + 0x7 + + + INTEN + Enable the TIMERn interrupt. + 0 + 1 + read-write + + + DISABLED + Disabled. TIMERn interrupt is disabled. + 0 + + + ENABLED + Enabled. TIMERn interrupt is enabled. + 0x1 + + + + + MODE + Selects timer mode. + 1 + 2 + read-write + + + REPEAT_INTERRUPT_MODE + Repeat interrupt mode. + 0 + + + ONE_SHOT_INTERRUPT_MODE + One-shot interrupt mode. + 0x1 + + + ONE_SHOT_STALL_MODE + One-shot stall mode. + 0x2 + + + + + + + STAT + MRT Status register. + 0xC + 32 + read-write + 0 + 0x7 + + + INTFLAG + Monitors the interrupt flag. + 0 + 1 + read-write + + + NO_PENDING_INTERRUPT + No pending interrupt. Writing a zero is equivalent to no operation. + 0 + + + PENDING_INTERRUPT + Pending interrupt. The interrupt is pending because TIMERn has reached the end of the time interval. If the INTEN bit in the CONTROLn is also set to 1, the interrupt for timer channel n and the global interrupt are raised. Writing a 1 to this bit clears the interrupt request. + 0x1 + + + + + RUN + Indicates the state of TIMERn. This bit is read-only. + 1 + 1 + read-write + + + IDLE_STATE + Idle state. TIMERn is stopped. + 0 + + + RUNNING + Running. TIMERn is running. + 0x1 + + + + + INUSE + Channel In Use flag. Operating details depend on the MULTITASK bit in the MODCFG register, and affects the use of IDLE_CH. See Idle channel register for details of the two operating modes. + 2 + 1 + read-write + + + NO + This channel is not in use. + 0 + + + YES + This channel is in use. + 0x1 + + + + + + + + MODCFG + Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature. + 0xF0 + 32 + read-write + 0x173 + 0x800001FF + + + NOC + Identifies the number of channels in this MRT.(4 channels on this device.) + 0 + 4 + read-write + + + NOB + Identifies the number of timer bits in this MRT. (24 bits wide on this device.) + 4 + 5 + read-write + + + MULTITASK + Selects the operating mode for the INUSE flags and the IDLE_CH register. + 31 + 1 + read-write + + + HARDWARE_STATUS_MODE + Hardware status mode. In this mode, the INUSE(n) flags for all channels are reset. + 0 + + + MULTI_TASK_MODE + Multi-task mode. + 0x1 + + + + + + + IDLE_CH + Idle channel register. This register returns the number of the first idle channel. + 0xF4 + 32 + read-only + 0 + 0xF0 + + + CHAN + Idle channel. Reading the CHAN bits, returns the lowest idle timer channel. The number is positioned such that it can be used as an offset from the MRT base address in order to access the registers for the allocated channel. If all timer channels are running, CHAN = 0xF. See text above for more details. + 4 + 4 + read-only + + + + + IRQ_FLAG + Global interrupt flag register + 0xF8 + 32 + read-write + 0 + 0xF + + + GFLAG0 + Monitors the interrupt flag of TIMER0. + 0 + 1 + read-write + + + NO_PENDING_INTERRUPT + No pending interrupt. Writing a zero is equivalent to no operation. + 0 + + + PENDING_INTERRUPT + Pending interrupt. The interrupt is pending because TIMER0 has reached the end of the time interval. If the INTEN bit in the CONTROL0 register is also set to 1, the interrupt for timer channel 0 and the global interrupt are raised. Writing a 1 to this bit clears the interrupt request. + 0x1 + + + + + GFLAG1 + Monitors the interrupt flag of TIMER1. See description of channel 0. + 1 + 1 + read-write + + + GFLAG2 + Monitors the interrupt flag of TIMER2. See description of channel 0. + 2 + 1 + read-write + + + GFLAG3 + Monitors the interrupt flag of TIMER3. See description of channel 0. + 3 + 1 + read-write + + + + + + + UTICK0 + Micro-tick Timer (UTICK) + UTICK + 0x4000E000 + + 0 + 0x20 + registers + + + UTICK0 + 8 + + + + CTRL + Control register. + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DELAYVAL + Tick interval value. The delay will be equal to DELAYVAL + 1 periods of the timer clock. The minimum usable value is 1, for a delay of 2 timer clocks. A value of 0 stops the timer. + 0 + 31 + read-write + + + REPEAT + Repeat delay. 0 = One-time delay. 1 = Delay repeats continuously. + 31 + 1 + read-write + + + + + STAT + Status register. + 0x4 + 32 + read-write + 0 + 0x3 + + + INTR + Interrupt flag. 0 = No interrupt is pending. 1 = An interrupt is pending. A write of any value to this register clears this flag. + 0 + 1 + read-write + + + ACTIVE + Active flag. 0 = The Micro-Tick Timer is stopped. 1 = The Micro-Tick Timer is currently active. + 1 + 1 + read-write + + + + + CFG + Capture configuration register. + 0x8 + 32 + read-write + 0 + 0xF0F + + + CAPEN0 + Enable Capture 0. 1 = Enabled, 0 = Disabled. + 0 + 1 + read-write + + + CAPEN1 + Enable Capture 1. 1 = Enabled, 0 = Disabled. + 1 + 1 + read-write + + + CAPEN2 + Enable Capture 2. 1 = Enabled, 0 = Disabled. + 2 + 1 + read-write + + + CAPEN3 + Enable Capture 3. 1 = Enabled, 0 = Disabled. + 3 + 1 + read-write + + + CAPPOL0 + Capture Polarity 0. 0 = Positive edge capture, 1 = Negative edge capture. + 8 + 1 + read-write + + + CAPPOL1 + Capture Polarity 1. 0 = Positive edge capture, 1 = Negative edge capture. + 9 + 1 + read-write + + + CAPPOL2 + Capture Polarity 2. 0 = Positive edge capture, 1 = Negative edge capture. + 10 + 1 + read-write + + + CAPPOL3 + Capture Polarity 3. 0 = Positive edge capture, 1 = Negative edge capture. + 11 + 1 + read-write + + + + + CAPCLR + Capture clear register. + 0xC + 32 + write-only + 0 + 0 + + + CAPCLR0 + Clear capture 0. Writing 1 to this bit clears the CAP0 register value. + 0 + 1 + write-only + + + CAPCLR1 + Clear capture 1. Writing 1 to this bit clears the CAP1 register value. + 1 + 1 + write-only + + + CAPCLR2 + Clear capture 2. Writing 1 to this bit clears the CAP2 register value. + 2 + 1 + write-only + + + CAPCLR3 + Clear capture 3. Writing 1 to this bit clears the CAP3 register value. + 3 + 1 + write-only + + + + + 4 + 0x4 + CAP[%s] + Capture register . + 0x10 + 32 + read-only + 0 + 0xFFFFFFFF + + + CAP_VALUE + Capture value for the related capture event (UTICK_CAPn. Note: the value is 1 lower than the actual value of the Micro-tick Timer at the moment of the capture event. + 0 + 31 + read-only + + + VALID + Capture Valid. When 1, a value has been captured based on a transition of the related UTICK_CAPn pin. Cleared by writing to the related bit in the CAPCLR register. + 31 + 1 + read-only + + + + + + + ANACTRL + ANALOGCTRL + ANACTRL + 0x40013000 + + 0 + 0x10C + registers + + + + ANALOG_CTRL_CFG + Various Analog blocks configuration (like FRO 192MHz trimmings source ...) + 0 + 32 + read-write + 0 + 0x1 + + + FRO192M_TRIM_SRC + FRO192M trimming and 'Enable' source. + 0 + 1 + read-write + + + EFUSE + FRO192M trimming and 'Enable' comes from eFUSE. + 0 + + + FRO192MCTRL + FRO192M trimming and 'Enable' comes from FRO192M_CTRL registers. + 0x1 + + + + + + + ANALOG_CTRL_STATUS + Analog Macroblock Identity registers, Flash Status registers + 0x4 + 32 + read-only + 0x50000000 + 0xF0003FFF + + + PMU_ID + Power Management Unit (PMU) Analog macro-bloc identification number : . + 0 + 6 + read-only + + + OSC_ID + Oscillators Analog macro-bloc identification number : . + 6 + 6 + read-only + + + FLASH_PWRDWN + Flash Power Down status. + 12 + 1 + read-only + + + PWRUP + Flash is not in power down mode. + 0 + + + PWRDWN + Flash is in power down mode. + 0x1 + + + + + FLASH_INIT_ERROR + Flash initialization error status. + 13 + 1 + read-only + + + NOERROR + No error. + 0 + + + ERROR + At least one error occured during flash initialization.. + 0x1 + + + + + FINAL_TEST_DONE_VECT + Indicates current status of Final Test. + 28 + 4 + read-only + + + + + FREQ_ME_CTRL + Frequency Measure function control register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPVAL_SCALE + Frequency measure result /Frequency measur scale + 0 + 31 + read-write + + + PROG + Set this bit to one to initiate a frequency measurement cycle. Hardware clears this bit when the measurement cycle has completed and there is valid capture data in the CAPVAL field (bits 30:0). + 31 + 1 + read-write + + + + + FRO192M_CTRL + 192MHz Free Running OScillator (FRO) Control register + 0x10 + 32 + read-write + 0x80D01A + 0xF3FFFFBF + + + BIAS_TRIM + Bias trimming bits (course frequency trimming). + 0 + 6 + read-write + + + TEMP_TRIM + Temperature coefficient trimming bits. + 7 + 7 + read-write + + + ENA_12MHZCLK + 12 MHz clock control. + 14 + 1 + read-write + + + DISABLE + 12 MHz clock is disabled. + 0 + + + ENABLE + 12 MHz clock is enabled. + 0x1 + + + + + ENA_48MHZCLK + 48 MHz clock control. + 15 + 1 + read-write + + + DISABLE + 48 MHz clock is disabled. + 0 + + + ENABLE + 48 MHz clock is enabled. + 0x1 + + + + + DAC_TRIM + Curdac trimming bits (fine frequency trimming) This trim is used to adjust the frequency, given that the bias and temperature trim are set. + 16 + 8 + read-write + + + USBCLKADJ + If this bit is set and the USB peripheral is enabled into full speed device mode, the USB block will provide FRO clock adjustments to lock it to the host clock using the SOF packets. + 24 + 1 + read-write + + + USBMODCHG + If this reads as 1 when reading the DAC_TRIM field and USBCLKADJ=1, it should be reread until it is 0. + 25 + 1 + read-only + + + ATB_CTRL + Analog Test Bus control. + 28 + 2 + read-write + + + ENA_96MHZCLK + 96 MHz clock control. + 30 + 1 + read-write + + + DISABLE + 96 MHz clock is disabled. + 0 + + + ENABLE + 96 MHz clock is enabled. + 0x1 + + + + + WRTRIM + This must be written to 1 to modify the BIAS_TRIM and TEMP_TRIM fields. + 31 + 1 + write-only + + + + + FRO192M_STATUS + 192MHz Free Running OScillator (FRO) Status register + 0x14 + 32 + read-write + 0x3 + 0x3 + + + CLK_VALID + Output clock valid signal. Indicates that CCO clock has settled. + 0 + 1 + read-only + + + NOCLKOUT + No output clock present (None of 12 MHz, 48 MHz or 96 MHz clock is available). + 0 + + + CLKOUT + Clock is present (12 MHz, 48 MHz or 96 MHz can be output if they are enable respectively by FRO192M_CTRL.ENA_12MHZCLK/ENA_48MHZCLK/ENA_96MHZCLK). + 0x1 + + + + + ATB_VCTRL + CCO threshold voltage detector output (signal vcco_ok). Once the CCO voltage crosses the threshold voltage of a SLVT transistor, this output signal will go high. It is also possible to observe the clk_valid signal. + 1 + 1 + read-only + + + + + ADC_CTRL + General Purpose ADC VBAT Divider branch control + 0x18 + 32 + read-write + 0 + 0x1 + + + VBATDIVENABLE + Switch On/Off VBAT divider branch. + 0 + 1 + read-write + + + DISABLE + VBAT divider branch is disabled. + 0 + + + ENABLE + VBAT divider branch is enabled. + 0x1 + + + + + + + XO32M_CTRL + 32 MHz Crystal Oscillator Control register + 0x20 + 32 + read-write + 0x21428A + 0x1FFFFFFE + + + GM + Gm value for Xo. + 1 + 3 + read-write + + + SLAVE + Xo in slave mode. + 4 + 1 + read-write + + + AMP + Amplitude selection , Min amp : 001, Max amp : 110. + 5 + 3 + read-write + + + OSC_CAP_IN + Tune capa banks of Crystal 32-MHz input pin + 8 + 7 + read-write + + + OSC_CAP_OUT + Tune capa banks of Crystal 32-MHz output pin + 15 + 7 + read-write + + + ACBUF_PASS_ENABLE + Bypass enable of XO AC buffer enable in pll and top level. + 22 + 1 + read-write + + + DISABLE + XO AC buffer bypass is disabled. + 0 + + + ENABLE + XO AC buffer bypass is enabled. + 0x1 + + + + + ENABLE_PLL_USB_OUT + Enable XO 32 MHz output to USB HS PLL. + 23 + 1 + read-write + + + DISABLE + XO 32 MHz output to USB HS PLL is disabled. + 0 + + + ENABLE + XO 32 MHz output to USB HS PLL is enabled. + 0x1 + + + + + ENABLE_SYSTEM_CLK_OUT + Enable XO 32 MHz output to CPU system. + 24 + 1 + read-write + + + DISABLE + XO 32 MHz output to CPU system is disabled. + 0 + + + ENABLE + XO 32 MHz output to CPU system is enabled. + 0x1 + + + + + CAPTESTSTARTSRCSEL + Source selection for 'xo32k_captest_start' signal. + 25 + 1 + read-write + + + CAPTEST + Sourced from CAPTESTSTART. + 0 + + + CALIB + Sourced from calibration. + 0x1 + + + + + CAPTESTSTART + 1: Start CapTest. + 26 + 1 + read-write + + + CAPTESTENABLE + Enable signal for captest. + 27 + 1 + read-write + + + DISABLE + Captest is disabled. + 0 + + + ENABLE + Captest is enabled. + 0x1 + + + + + CAPTESTOSCINSEL + Select the input for test. + 28 + 1 + read-write + + + OSCOUT + osc_out (oscillator output) pin. + 0 + + + OSCIN + osc_in (oscillator) pin. + 0x1 + + + + + + + XO32M_STATUS + 32 MHz Crystal Oscillator Status register + 0x24 + 32 + read-only + 0 + 0x1 + + + XO_READY + Indicates XO out frequency statibilty. + 0 + 1 + read-only + + + NOT_STABLE + XO output frequency is not yet stable. + 0 + + + STABLE + XO output frequency is stable. + 0x1 + + + + + + + BOD_DCDC_INT_CTRL + Brown Out Detectors (BoDs) & DCDC interrupts generation control register + 0x30 + 32 + read-write + 0 + 0x3F + + + BODVBAT_INT_ENABLE + BOD VBAT interrupt control. + 0 + 1 + read-write + + + DISABLE + BOD VBAT interrupt is disabled. + 0 + + + ENABLE + BOD VBAT interrupt is enabled. + 0x1 + + + + + BODVBAT_INT_CLEAR + BOD VBAT interrupt clear.1: Clear the interrupt. Self-cleared bit. + 1 + 1 + read-write + + + BODCORE_INT_ENABLE + BOD CORE interrupt control. + 2 + 1 + read-write + + + DISABLE + BOD CORE interrupt is disabled. + 0 + + + ENABLE + BOD CORE interrupt is enabled. + 0x1 + + + + + BODCORE_INT_CLEAR + BOD CORE interrupt clear.1: Clear the interrupt. Self-cleared bit. + 3 + 1 + read-write + + + DCDC_INT_ENABLE + DCDC interrupt control. + 4 + 1 + read-write + + + DISABLE + DCDC interrupt is disabled. + 0 + + + ENABLE + DCDC interrupt is enabled. + 0x1 + + + + + DCDC_INT_CLEAR + DCDC interrupt clear.1: Clear the interrupt. Self-cleared bit. + 5 + 1 + read-write + + + + + BOD_DCDC_INT_STATUS + BoDs & DCDC interrupts status register + 0x34 + 32 + read-only + 0x104 + 0x1FF + + + BODVBAT_STATUS + BOD VBAT Interrupt status before Interrupt Enable. + 0 + 1 + read-only + + + NOT_PENDING + No interrupt pending.. + 0 + + + PENDING + Interrupt pending.. + 0x1 + + + + + BODVBAT_INT_STATUS + BOD VBAT Interrupt status after Interrupt Enable. + 1 + 1 + read-only + + + NOT_PENDING + No interrupt pending.. + 0 + + + PENDING + Interrupt pending.. + 0x1 + + + + + BODVBAT_VAL + Current value of BOD VBAT power status output. + 2 + 1 + read-only + + + NOT_OK + VBAT voltage level is below the threshold. + 0 + + + OK + VBAT voltage level is above the threshold. + 0x1 + + + + + BODCORE_STATUS + BOD CORE Interrupt status before Interrupt Enable. + 3 + 1 + read-only + + + NOT_PENDING + No interrupt pending.. + 0 + + + PENDING + Interrupt pending.. + 0x1 + + + + + BODCORE_INT_STATUS + BOD CORE Interrupt status after Interrupt Enable. + 4 + 1 + read-only + + + NOT_PENDING + No interrupt pending.. + 0 + + + PENDING + Interrupt pending.. + 0x1 + + + + + BODCORE_VAL + Current value of BOD CORE power status output. + 5 + 1 + read-only + + + NOT_OK + CORE voltage level is below the threshold. + 0 + + + OK + CORE voltage level is above the threshold. + 0x1 + + + + + DCDC_STATUS + DCDC Interrupt status before Interrupt Enable. + 6 + 1 + read-only + + + NOT_PENDING + No interrupt pending.. + 0 + + + PENDING + Interrupt pending.. + 0x1 + + + + + DCDC_INT_STATUS + DCDC Interrupt status after Interrupt Enable. + 7 + 1 + read-only + + + NOT_PENDING + No interrupt pending.. + 0 + + + PENDING + Interrupt pending.. + 0x1 + + + + + DCDC_VAL + Current value of DCDC power status output. + 8 + 1 + read-only + + + NOT_OK + DCDC output Voltage is below the targeted regulation level. + 0 + + + OK + DCDC output Voltage is above the targeted regulation level. + 0x1 + + + + + + + RINGO0_CTRL + First Ring Oscillator module control register. + 0x40 + 32 + read-write + 0x40 + 0x803F1FFF + + + SL + Select short or long ringo (for all ringos types). + 0 + 1 + read-write + + + SHORT + Select short ringo (few elements). + 0 + + + LONG + Select long ringo (many elements). + 0x1 + + + + + FS + Ringo frequency output divider. + 1 + 1 + read-write + + + FAST + High frequency output (frequency lower than 100 MHz). + 0 + + + SLOW + Low frequency output (frequency lower than 10 MHz). + 0x1 + + + + + SWN_SWP + PN-Ringos (P-Transistor and N-Transistor processing) control. + 2 + 2 + read-write + + + NORMAL + Normal mode. + 0 + + + P_MONITOR + P-Monitor mode. Measure with weak P transistor. + 0x1 + + + N_MONITOR + P-Monitor mode. Measure with weak N transistor. + 0x2 + + + FORBIDDEN + Don't use. + 0x3 + + + + + PD + Ringo module Power control. + 4 + 1 + read-write + + + POWERED_ON + The Ringo module is enabled. + 0 + + + POWERED_DOWN + The Ringo module is disabled. + 0x1 + + + + + E_ND0 + First NAND2-based ringo control. + 5 + 1 + read-write + + + DISABLE + First NAND2-based ringo is disabled. + 0 + + + ENABLE + First NAND2-based ringo is enabled. + 0x1 + + + + + E_ND1 + Second NAND2-based ringo control. + 6 + 1 + read-write + + + DISABLE + Second NAND2-based ringo is disabled. + 0 + + + ENABLE + Second NAND2-based ringo is enabled. + 0x1 + + + + + E_NR0 + First NOR2-based ringo control. + 7 + 1 + read-write + + + DISABLE + First NOR2-based ringo is disabled. + 0 + + + ENABLE + First NOR2-based ringo is enabled. + 0x1 + + + + + E_NR1 + Second NOR2-based ringo control. + 8 + 1 + read-write + + + DISABLE + Second NORD2-based ringo is disabled. + 0 + + + ENABLE + Second NORD2-based ringo is enabled. + 0x1 + + + + + E_IV0 + First Inverter-based ringo control. + 9 + 1 + read-write + + + DISABLE + First INV-based ringo is disabled. + 0 + + + ENABLE + First INV-based ringo is enabled. + 0x1 + + + + + E_IV1 + Second Inverter-based ringo control. + 10 + 1 + read-write + + + DISABLE + Second INV-based ringo is disabled. + 0 + + + ENABLE + Second INV-based ringo is enabled. + 0x1 + + + + + E_PN0 + First PN (P-Transistor and N-Transistor processing) monitor control. + 11 + 1 + read-write + + + DISABLE + First PN-based ringo is disabled. + 0 + + + ENABLE + First PN-based ringo is enabled. + 0x1 + + + + + E_PN1 + Second PN (P-Transistor and N-Transistor processing) monitor control. + 12 + 1 + read-write + + + DISABLE + Second PN-based ringo is disabled. + 0 + + + ENABLE + Second PN-based ringo is enabled. + 0x1 + + + + + DIVISOR + Ringo out Clock divider value. Frequency Output = Frequency input / (DIViSOR+1). (minimum = Frequency input / 16) + 16 + 4 + read-write + + + DIV_UPDATE_REQ + Ringo clock out Divider status flag. Set when a change is made to the divider value, cleared when the change is complete. + 31 + 1 + read-only + + + + + RINGO1_CTRL + Second Ring Oscillator module control register. + 0x44 + 32 + read-write + 0x40 + 0x803F01FF + + + S + Select short or long ringo (for all ringos types). + 0 + 1 + read-write + + + SHORT + Select short ringo (few elements). + 0 + + + LONG + Select long ringo (many elements). + 0x1 + + + + + FS + Ringo frequency output divider. + 1 + 1 + read-write + + + FAST + High frequency output (frequency lower than 100 MHz). + 0 + + + SLOW + Low frequency output (frequency lower than 10 MHz). + 0x1 + + + + + PD + Ringo module Power control. + 2 + 1 + read-write + + + POWERED_ON + The Ringo module is enabled. + 0 + + + POWERED_DOWN + The Ringo module is disabled. + 0x1 + + + + + E_R24 + . + 3 + 1 + read-write + + + DISABLE + Ringo is disabled. + 0 + + + ENABLE + Ringo is enabled. + 0x1 + + + + + E_R35 + . + 4 + 1 + read-write + + + DISABLE + Ringo is disabled. + 0 + + + ENABLE + Ringo is enabled. + 0x1 + + + + + E_M2 + Metal 2 (M2) monitor control. + 5 + 1 + read-write + + + DISABLE + Ringo is disabled. + 0 + + + ENABLE + Ringo is enabled. + 0x1 + + + + + E_M3 + Metal 3 (M3) monitor control. + 6 + 1 + read-write + + + DISABLE + Ringo is disabled. + 0 + + + ENABLE + Ringo is enabled. + 0x1 + + + + + E_M4 + Metal 4 (M4) monitor control. + 7 + 1 + read-write + + + DISABLE + Ringo is disabled. + 0 + + + ENABLE + Ringo is enabled. + 0x1 + + + + + E_M5 + Metal 5 (M5) monitor control. + 8 + 1 + read-write + + + DISABLE + Ringo is disabled. + 0 + + + ENABLE + Ringo is enabled. + 0x1 + + + + + DIVISOR + Ringo out Clock divider value. Frequency Output = Frequency input / (DIViSOR+1). (minimum = Frequency input / 16) + 16 + 4 + read-write + + + DIV_UPDATE_REQ + Ringo clock out Divider status flag. Set when a change is made to the divider value, cleared when the change is complete. + 31 + 1 + read-only + + + + + RINGO2_CTRL + Third Ring Oscillator module control register. + 0x48 + 32 + read-write + 0x40 + 0x803F01FF + + + S + Select short or long ringo (for all ringos types). + 0 + 1 + read-write + + + SHORT + Select short ringo (few elements). + 0 + + + LONG + Select long ringo (many elements). + 0x1 + + + + + FS + Ringo frequency output divider. + 1 + 1 + read-write + + + FAST + High frequency output (frequency lower than 100 MHz). + 0 + + + SLOW + Low frequency output (frequency lower than 10 MHz). + 0x1 + + + + + PD + Ringo module Power control. + 2 + 1 + read-write + + + POWERED_ON + The Ringo module is enabled. + 0 + + + POWERED_DOWN + The Ringo module is disabled. + 0x1 + + + + + E_R24 + . + 3 + 1 + read-write + + + DISABLE + Ringo is disabled. + 0 + + + ENABLE + Ringo is enabled. + 0x1 + + + + + E_R35 + . + 4 + 1 + read-write + + + DISABLE + Ringo is disabled. + 0 + + + ENABLE + Ringo is enabled. + 0x1 + + + + + E_M2 + Metal 2 (M2) monitor control. + 5 + 1 + read-write + + + DISABLE + Ringo is disabled. + 0 + + + ENABLE + Ringo is enabled. + 0x1 + + + + + E_M3 + Metal 3 (M3) monitor control. + 6 + 1 + read-write + + + DISABLE + Ringo is disabled. + 0 + + + ENABLE + Ringo is enabled. + 0x1 + + + + + E_M4 + Metal 4 (M4) monitor control. + 7 + 1 + read-write + + + DISABLE + Ringo is disabled. + 0 + + + ENABLE + Ringo is enabled. + 0x1 + + + + + E_M5 + Metal 5 (M5) monitor control. + 8 + 1 + read-write + + + DISABLE + Ringo is disabled. + 0 + + + ENABLE + Ringo is enabled. + 0x1 + + + + + DIVISOR + Ringo out Clock divider value. Frequency Output = Frequency input / (DIViSOR+1). (minimum = Frequency input / 16) + 16 + 4 + read-write + + + DIV_UPDATE_REQ + Ringo clock out Divider status flag. Set when a change is made to the divider value, cleared when the change is complete. + 31 + 1 + read-only + + + + + LDO_XO32M + High Speed Crystal Oscillator (12 MHz - 32 MHz) Voltage Source Supply Control register + 0xB0 + 32 + read-write + 0x3A0 + 0x3FE + + + BYPASS + Activate LDO bypass. + 1 + 1 + read-write + + + DISABLE + Disable bypass mode (for normal operations). + 0 + + + ENABLE + Activate LDO bypass. + 0x1 + + + + + HIGHZ + . + 2 + 1 + read-write + + + NORMALMPEDANCE + Output in High normal state. + 0 + + + HIGHIMPEDANCE + Output in High Impedance state. + 0x1 + + + + + VOUT + Sets the LDO output level. + 3 + 3 + read-write + + + V_0P750 + 0.750 V. + 0 + + + V_0P775 + 0.775 V. + 0x1 + + + V_0P800 + 0.800 V. + 0x2 + + + V_0P825 + 0.825 V. + 0x3 + + + V_0P850 + 0.850 V. + 0x4 + + + V_0P875 + 0.875 V. + 0x5 + + + V_0P900 + 0.900 V. + 0x6 + + + V_0P925 + 0.925 V. + 0x7 + + + + + IBIAS + Adjust the biasing current. + 6 + 2 + read-write + + + STABMODE + Stability configuration. + 8 + 2 + read-write + + + + + XO_CAL_CFG + All Crystal Oscillators (both the 32 KHz and the High speed) Capacitive Banks Calibration Configuration register + 0xC0 + 32 + read-write + 0 + 0x3F + + + START_INV + Polarity of the externally applied START signal + 0 + 1 + read-write + + + START_OVR + Override of the START signal. + 1 + 1 + read-write + + + START + Override value of the START signal. + 2 + 1 + read-write + + + STOP_INV + Polarity of the STOP signal. + 3 + 1 + read-write + + + STOP_CNTR_END + Generate the external DONE signal when the counter reaches its end. + 4 + 1 + read-write + + + XO32K_MODE + When 0 : High speed crystal oscillator calibration is used. When 1 : 32 kHz crystal oscillator calibration is used. + 5 + 1 + read-write + + + XO32MHZ + High speed crystal oscillator (12 MHz- 32 MHz) is used + 0 + + + XO32KHZ + 32 kHz crystal oscillator calibration is used. + 0x1 + + + + + + + XO_CAL_CMD + All Crystal Oscillators (both the 32 KHz and the High Speed) Capacitive Banks Calibration Command register. + 0xC4 + 32 + read-write + 0 + 0x7 + + + START + START signal for testing the state machine. + 0 + 1 + read-write + + + STOP + STOP signal for testing the state machine. + 1 + 1 + read-write + + + OVR + Override instructing the state machine to use the START/STOP signals from this register. + 2 + 1 + read-write + + + + + XO_CAL_STATUS + All Crystal Oscillators (both the 32 KHz and the High speed) Capacitive Banks Calibration Status register. + 0xC8 + 32 + read-only + 0 + 0x1FFFF + + + CAL_CNTR + Value of the calibration counter (result of the calibration operation). + 0 + 16 + read-only + + + DONE + Status of the calibration run. 1: Calibration is completed. + 16 + 1 + read-only + + + + + USBHS_PHY_CTRL + USB High Speed Phy Control + 0x100 + 32 + read-write + 0x8 + 0xF + + + usb_vbusvalid_ext + Override value for Vbus if using external detectors. + 0 + 1 + read-write + + + usb_id_ext + Override value for ID if using external detectors. + 1 + 1 + read-write + + + iso_atx + . + 3 + 1 + read-write + + + + + USBHS_PHY_TRIM + USB High Speed Phy Trim values + 0x104 + 32 + read-write + 0 + 0xFFFFFF + + + trim_usb_reg_env_tail_adj_vd + Adjusts time constant of HS RX squelch (envelope) comparator. + 0 + 2 + read-write + + + trim_usbphy_tx_d_cal + . + 2 + 4 + read-write + + + trim_usbphy_tx_cal45dp + . + 6 + 5 + read-write + + + trim_usbphy_tx_cal45dm + . + 11 + 5 + read-write + + + trim_usb2_refbias_tst + . + 16 + 2 + read-write + + + trim_usb2_refbias_vbgadj + . + 18 + 3 + read-write + + + trim_pll_ctrl0_div_sel + . + 21 + 3 + read-write + + + + + USBHS_PHY_STATUS + USB High Speed Phy Status + 0x108 + 32 + read-only + 0 + 0x7F + + + pfd_stable + pfd output is stable. + 0 + 1 + read-only + + + vbusvalid_3vdetect_1p8v + Can be left disconnected if not using High volt interrupts. + 1 + 1 + read-only + + + sess_vld_1p8v + Same as utmi_sessend. + 2 + 1 + read-only + + + usb2_rx_vpin_fs_1p8v + Full speed single ended receiver for 1. + 3 + 1 + read-only + + + usb2_rx_vmin_fs_1p8v + Full speed single ended receiver for 1. + 4 + 1 + read-only + + + usb2_plugged_in_1p8v + this is a proprietary mode described in the reference manual. + 5 + 1 + read-only + + + usb2_iddig_1p8v + ID value in the 1. + 6 + 1 + read-only + + + + + + + PMC + PMC + PMC + 0x40020000 + + 0 + 0xCC + registers + + + + RESETCTRL + Reset Control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] + 0x8 + 32 + read-write + 0 + 0xF + + + DPDWAKEUPRESETENABLE + Wake-up from DEEP POWER DOWN reset event (either from wake up I/O or RTC or OS Event Timer). + 0 + 1 + read-write + + + DISABLE + Reset event from DEEP POWER DOWN mode is disable. + 0 + + + ENABLE + Reset event from DEEP POWER DOWN mode is enable. + 0x1 + + + + + BODVBATRESETENABLE + BOD VBAT reset enable. + 1 + 1 + read-write + + + DISABLE + BOD VBAT reset is disable. + 0 + + + ENABLE + BOD VBAT reset is enable. + 0x1 + + + + + BODCORERESETENABLE + BOD CORE reset enable. + 2 + 1 + read-write + + + DISABLE + BOD CORE reset is disable. + 0 + + + ENABLE + BOD CORE reset is enable. + 0x1 + + + + + SWRRESETENABLE + Software reset enable. + 3 + 1 + read-write + + + DISABLE + Software reset is disable. + 0 + + + ENABLE + Software reset is enable. + 0x1 + + + + + + + RESETCAUSE + Reset Cause register [Reset by: PoR] + 0xC + 32 + read-write + 0x1 + 0x1FF + + + POR + 1 : The last chip reset was caused by a Power On Reset. Write '1' to clear this bit. + 0 + 1 + read-write + oneToClear + + + PADRESET + 1 : The last chip reset was caused by a Pin Reset. Write '1' to clear this bit. + 1 + 1 + read-write + + + BODRESET + 1 : The last chip reset was caused by a Brown Out Detector (BoD), either VBAT BoD or Core Logic BoD. Write '1' to clear this bit. + 2 + 1 + read-write + + + SYSTEMRESET + 1 : The last chip reset was caused by a System Reset requested by the ARM CPU. Write '1' to clear this bit. + 3 + 1 + read-write + + + WDTRESET + 1 : The last chip reset was caused by the Watchdog Timer. Write '1' to clear this bit. + 4 + 1 + read-write + + + SWRRESET + 1 : The last chip reset was caused by a Software. Write '1' to clear this bit. + 5 + 1 + read-write + + + DPDRESET_WAKEUPIO + 1 : The last chip reset was caused by a Wake-up I/O reset event during DEEP POWER DOWN mode. Write '1' to clear this bit. + 6 + 1 + read-write + + + DPDRESET_RTC + 1 : The last chip reset was caused by an RTC (either RTC Alarm or RTC wake up) reset event during DEEP POWER DOWN mode. Write '1' to clear this bit. + 7 + 1 + read-write + + + DPDRESET_OSTIMER + 1 : The last chip reset was caused by a OS Event Timer reset eventduring DEEP POWER DOWN mode. Write '1' to clear this bit. + 8 + 1 + read-write + + + + + BODVBAT + VBAT Brown Out Dectector (BoD) control register [Reset by: PoR, Pin Reset, Software Reset] + 0x30 + 32 + read-write + 0x69 + 0x7F + + + TRIGLVL + BoD trigger level. + 0 + 5 + read-write + + + V_1P00 + 1.00 V. + 0 + + + V_1P10 + 1.10 V. + 0x1 + + + V_1P20 + 1.20 V. + 0x2 + + + V_1P30 + 1.30 V. + 0x3 + + + V_1P40 + 1.40 V. + 0x4 + + + V_1P50 + 1.50 V. + 0x5 + + + V_1P60 + 1.60 V. + 0x6 + + + V_1P65 + 1.65 V. + 0x7 + + + V_1P70 + 1.70 V. + 0x8 + + + V_1P75 + 1.75 V. + 0x9 + + + V_1P80 + 1.80 V. + 0xA + + + V_1P90 + 1.90 V. + 0xB + + + V_2P00 + 2.00 V. + 0xC + + + V_2P10 + 2.10 V. + 0xD + + + V_2P20 + 2.20 V. + 0xE + + + V_2P30 + 2.30 V. + 0xF + + + V_2P40 + 2.40 V. + 0x10 + + + V_2P50 + 2.50 V. + 0x11 + + + V_2P60 + 2.60 V. + 0x12 + + + V_2P70 + 2.70 V. + 0x13 + + + V_2P80 + 2.806 V. + 0x14 + + + V_2P90 + 2.90 V. + 0x15 + + + V_3P00 + 3.00 V. + 0x16 + + + V_3P10 + 3.10 V. + 0x17 + + + V_3P20 + 3.20 V. + 0x18 + + + V_3P30_2 + 3.30 V. + 0x19 + + + V_3P30_3 + 3.30 V. + 0x1A + + + V_3P30_4 + 3.30 V. + 0x1B + + + V_3P30_5 + 3.30 V. + 0x1C + + + V_3P30_6 + 3.30 V. + 0x1D + + + V_3P30_7 + 3.30 V. + 0x1E + + + V_3P30_8 + 3.30 V. + 0x1F + + + + + HYST + BoD Hysteresis control. + 5 + 2 + read-write + + + HYST_25MV + 25 mV. + 0 + + + HYST_50MV + 50 mV. + 0x1 + + + HYST_75MV + 75 mV. + 0x2 + + + HYST_100MV + 100 mV. + 0x3 + + + + + + + BODCORE + Digital Core logic Brown Out Dectector control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] + 0x38 + 32 + read-write + 0x17 + 0x37 + + + TRIGLVL + BoD trigger level. + 0 + 3 + read-write + + + V_0P60 + 0.60 V. + 0 + + + V_0P65 + 0.65 V. + 0x1 + + + V_0P70 + 0.70 V. + 0x2 + + + V_0P75 + 0.75 V. + 0x3 + + + V_0P80 + 0.80 V. + 0x4 + + + V_0P85 + 0.85 V. + 0x5 + + + V_0P90 + 0.90 V. + 0x6 + + + V_0P95 + 0.95 V. + 0x7 + + + + + HYST + BoD Core Hysteresis control. + 4 + 2 + read-write + + + HYST_25MV + 25 mV. + 0 + + + HYST_50MV + 50 mV. + 0x1 + + + HYST_75MV + 75 mV. + 0x2 + + + HYST_100MV + 100 mV. + 0x3 + + + + + + + FRO1M + 1 MHz Free Running Oscillator control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] + 0x44 + 32 + read-write + 0x50 + 0x3FFF + + + FREQSEL + Frequency trimming bits. + 0 + 7 + read-write + + + ATBCTRL + Debug control bits to set the analog/digital test modes. + 7 + 2 + read-write + + + DIVSEL + Divider selection bits. + 9 + 5 + read-write + + + DIV_2 + 2.0. + 0 + + + DIV_4 + 4.0. + 0x1 + + + DIV_6 + 6.0. + 0x2 + + + DIV_8 + 8.0. + 0x3 + + + DIV_10 + 10.0. + 0x4 + + + DIV_12 + 12.0. + 0x5 + + + DIV_14 + 14.0. + 0x6 + + + DIV_16 + 16.0. + 0x7 + + + DIV_18 + 18.0. + 0x8 + + + DIV_20 + 20.0. + 0x9 + + + DIV_22 + 22.0. + 0xA + + + DIV_24 + 24.0. + 0xB + + + DIV_26 + 26.0. + 0xC + + + DIV_28 + 28.0. + 0xD + + + DIV_30 + 30.0. + 0xE + + + DIV_32 + 32.0. + 0xF + + + DIV_34 + 34.0. + 0x10 + + + DIV_36 + 36.0. + 0x11 + + + DIV_38 + 38.0. + 0x12 + + + DIV_40 + 40.0. + 0x13 + + + DIV_42 + 42.0. + 0x14 + + + DIV_44 + 44.0. + 0x15 + + + DIV_46 + 46.0. + 0x16 + + + DIV_48 + 48.0. + 0x17 + + + DIV_50 + 50.0. + 0x18 + + + DIV_52 + 52.0. + 0x19 + + + DIV_54 + 54.0. + 0x1A + + + DIV_56 + 56.0. + 0x1B + + + DIV_58 + 58.0. + 0x1C + + + DIV_60 + 60.0. + 0x1D + + + DIV_62 + 62.0. + 0x1E + + + DIV_1 + 1.0. + 0x1F + + + + + + + FRO32K + 32 KHz Free Running Oscillator (FRO) control register [Reset by: PoR, Brown Out Detectors Reset] + 0x48 + 32 + read-write + 0x90B6 + 0x3FFFE + + + NTAT + Temperature coefficient trimming bits. + 1 + 3 + read-write + + + PTAT + Bias trimming bits (course frequency trimming). + 4 + 3 + read-write + + + CAPCAL + Capacitive dac calibration bits (fine frequency trimming). + 7 + 9 + read-write + + + ATBCTRL + Debug control bits to set the analog/digital test modes. + 16 + 2 + read-write + + + + + XTAL32K + 32 KHz Crystal oscillator (XTAL) control register [Reset by: PoR, Brown Out Detectors Reset] + 0x4C + 32 + read-write + 0x204052 + 0x3FFFFFE + + + IREF + reference output current selection inputs. + 1 + 2 + read-write + + + TEST + Oscillator Test Mode. + 3 + 1 + read-write + + + IBIAS + bias current selection inputs. + 4 + 2 + read-write + + + AMPL + oscillator amplitude selection inputs. + 6 + 2 + read-write + + + CAPBANKIN + Capa bank setting input. + 8 + 7 + read-write + + + CAPBANKOUT + Capa bank setting output. + 15 + 7 + read-write + + + CAPTESTSTARTSRCSEL + Source selection for xo32k_captest_start_ao_set. + 22 + 1 + read-write + + + CAPSTART + Sourced from CAPTESTSTART. + 0 + + + CALIB + Sourced from calibration. + 0x1 + + + + + CAPTESTSTART + Start test. + 23 + 1 + read-write + + + CAPTESTENABLE + Enable signal for cap test. + 24 + 1 + read-write + + + CAPTESTOSCINSEL + Select the input for test. + 25 + 1 + read-write + + + OSCOUT + Oscillator output pin (osc_out). + 0 + + + OSCIN + Oscillator input pin (osc_in). + 0x1 + + + + + + + COMP + Analog Comparator control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] + 0x50 + 32 + read-write + 0xA + 0xFF7FFE + + + HYST + Hysteris when hyst = '1'. + 1 + 1 + read-write + + + DISABLE + Hysteresis is disable. + 0 + + + ENABLE + Hysteresis is enable. + 0x1 + + + + + VREFINPUT + Dedicated control bit to select between internal VREF and VDDA (for the resistive ladder). + 2 + 1 + read-write + + + INTERNALREF + Select internal VREF. + 0 + + + VDDA + Select VDDA. + 0x1 + + + + + LOWPOWER + Low power mode. + 3 + 1 + read-write + + + HIGHSPEED + High speed mode. + 0 + + + LOWSPEED + Low power mode (Low speed). + 0x1 + + + + + PMUX + Control word for P multiplexer:. + 4 + 3 + read-write + + + VREF + VREF (See fiedl VREFINPUT). + 0 + + + CMP0_A + Pin P0_0. + 0x1 + + + CMP0_B + Pin P0_9. + 0x2 + + + CMP0_C + Pin P0_18. + 0x3 + + + CMP0_D + Pin P1_14. + 0x4 + + + CMP0_E + Pin P2_23. + 0x5 + + + + + NMUX + Control word for N multiplexer:. + 7 + 3 + read-write + + + VREF + VREF (See field VREFINPUT). + 0 + + + CMP0_A + Pin P0_0. + 0x1 + + + CMP0_B + Pin P0_9. + 0x2 + + + CMP0_C + Pin P0_18. + 0x3 + + + CMP0_D + Pin P1_14. + 0x4 + + + CMP0_E + Pin P2_23. + 0x5 + + + + + VREF + Control reference voltage step, per steps of (VREFINPUT/31). + 10 + 5 + read-write + + + FILTERCGF_SAMPLEMODE + Filter Sample mode. + 16 + 2 + read-write + + + FILTERCGF_CLKDIV + Filter Clock div . + 18 + 3 + read-write + + + PMUXCAPT + Control word for P multiplexer for Capacitive Touch Controller. + 21 + 3 + read-write + + + + + WAKEIOCAUSE + Allows to identify the Wake-up I/O source from Deep Power Down mode + 0x68 + 32 + read-write + 0 + 0xF + + + WAKEUP0 + Allows to identify Wake up I/O 0 as the wake-up source from Deep Power Down mode. + 0 + 1 + read-only + + + NOEVENT + Last wake up from Deep Power down mode was NOT triggred by wake up I/O 0. + 0 + + + EVENT + Last wake up from Deep Power down mode was triggred by wake up I/O 0. + 0x1 + + + + + WAKEUP1 + Allows to identify Wake up I/O 1 as the wake-up source from Deep Power Down mode. + 1 + 1 + read-write + + + NOEVENT + Last wake up from Deep Power down mode was NOT triggred by wake up I/O 1. + 0 + + + EVENT + Last wake up from Deep Power down mode was triggred by wake up I/O 1. + 0x1 + + + + + WAKEUP2 + Allows to identify Wake up I/O 2 as the wake-up source from Deep Power Down mode. + 2 + 1 + read-write + + + NOEVENT + Last wake up from Deep Power down mode was NOT triggred by wake up I/O 2. + 0 + + + EVENT + Last wake up from Deep Power down mode was triggred by wake up I/O 2. + 0x1 + + + + + WAKEUP3 + Allows to identify Wake up I/O 3 as the wake-up source from Deep Power Down mode. + 3 + 1 + read-write + + + NOEVENT + Last wake up from Deep Power down mode was NOT triggred by wake up I/O 3. + 0 + + + EVENT + Last wake up from Deep Power down mode was triggred by wake up I/O 3. + 0x1 + + + + + + + STATUSCLK + FRO and XTAL status register [Reset by: PoR, Brown Out Detectors Reset] + 0x74 + 32 + read-write + 0x6 + 0x7 + + + XTAL32KOK + XTAL oscillator 32 K OK signal. + 0 + 1 + read-only + + + FRO1MCLKVALID + FRO 1 MHz CCO voltage detector output. + 1 + 1 + read-only + + + XTAL32KOSCFAILURE + XTAL32 KHZ oscillator oscillation failure detection indicator. + 2 + 1 + read-write + + + NOFAIL + No oscillation failure has been detetced since the last time this bit has been cleared.. + 0 + + + FAILURE + At least one oscillation failure has been detetced since the last time this bit has been cleared.. + 0x1 + + + + + + + AOREG1 + General purpose always on domain data storage [Reset by: PoR, Brown Out Detectors Reset] + 0x84 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA31_0 + General purpose always on domain data storage. + 0 + 32 + read-write + + + + + RTCOSC32K + RTC 1 KHZ and 1 Hz clocks source control register [Reset by: PoR, Brown Out Detectors Reset] + 0x98 + 32 + read-write + 0x3FF0008 + 0xC7FF800F + + + SEL + Select the 32K oscillator to be used in Deep Power Down Mode for the RTC (either XTAL32KHz or FRO32KHz) . + 0 + 1 + read-write + + + FRO32K + FRO 32 KHz. + 0 + + + XTAL32K + XTAL 32KHz. + 0x1 + + + + + CLK1KHZDIV + Actual division ratio is : 28 + CLK1KHZDIV. + 1 + 3 + read-write + + + CLK1KHZDIVUPDATEREQ + RTC 1KHz clock Divider status flag. + 15 + 1 + read-write + + + CLK1HZDIV + Actual division ratio is : 31744 + CLK1HZDIV. + 16 + 11 + read-write + + + CLK1HZDIVHALT + Halts the divider counter. + 30 + 1 + read-write + + + CLK1HZDIVUPDATEREQ + RTC 1Hz Divider status flag. + 31 + 1 + read-write + + + + + OSTIMER + OS Timer control register [Reset by: PoR, Brown Out Detectors Reset] + 0x9C + 32 + read-write + 0x8 + 0xF + + + SOFTRESET + Active high reset. + 0 + 1 + read-write + + + CLOCKENABLE + Enable OSTIMER 32 KHz clock. + 1 + 1 + read-write + + + DPDWAKEUPENABLE + Wake up enable in Deep Power Down mode (To be used in Enable Deep Power Down mode). + 2 + 1 + read-write + + + OSC32KPD + Oscilator 32KHz (either FRO32KHz or XTAL32KHz according to RTCOSC32K. + 3 + 1 + read-write + + + + + PDSLEEPCFG0 + Controls the power to various modules during Low Power modes - DEEP SLEEP, POWER DOWN and DEEP POWER DOWN [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Software Reset] + 0xB0 + 32 + read-write + 0xC0 + 0x1FFFFFF + + + PDEN_DCDC + Controls DCDC power during DEEP SLEEP (DCDC is always shut down during POWER DOWN and DEEP POWER DOWN). + 0 + 1 + read-write + + + POWEREDON + DCDC is powered on during low power mode.. + 0 + + + POWEREDOFF + DCDC is powered off during low power mode.. + 0x1 + + + + + PDEN_BIAS + Controls Analog Bias power during DEEP SLEEP and POWER DOWN (always shut down during DEEP POWER DOWN). + 1 + 1 + read-write + + + POWEREDON + Analog Bias is powered on during low power mode.. + 0 + + + POWEREDOFF + Analog Bias is powered off during low power mode.. + 0x1 + + + + + PDEN_BODCORE + Controls Core Logic BoD power during DEEP SLEEP and POWER DOWN (always shut down during DEEP POWER DOWN). + 2 + 1 + read-write + + + POWEREDON + BOD CORE is powered on during low power mode.. + 0 + + + POWEREDOFF + BOD CORE is powered off during low power mode.. + 0x1 + + + + + PDEN_BODVBAT + Controls VBAT BoD power during DEEP SLEEP and POWER DOWN (always shut down during DEEP POWER DOWN). + 3 + 1 + read-write + + + POWEREDON + BOD VBAT is powered on during low power mode.. + 0 + + + POWEREDOFF + BOD VBAT is powered off during low power mode.. + 0x1 + + + + + PDEN_FRO1M + Controls 1 MHz Free Running Oscillator power during DEEP SLEEP, POWER DOWN and DEEP POWER DOWN. + 4 + 1 + read-write + + + POWEREDON + FRO 1MHz is powered on during low power mode.. + 0 + + + POWEREDOFF + FRO 1MHz is powered off during low power mode.. + 0x1 + + + + + PDEN_FRO192M + Controls 192MHz Free Running Oscillator power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). + 5 + 1 + read-write + + + POWEREDON + FRO 192 MHz is powered on during low power mode.. + 0 + + + POWEREDOFF + FRO 192 MHz is powered off during low power mode.. + 0x1 + + + + + PDEN_FRO32K + Controls power during DEEP SLEEP, POWER DOWN and DEEP POWER DOWN. + 6 + 1 + read-write + + + POWEREDON + FRO 32 KHz is powered on during low power mode.. + 0 + + + POWEREDOFF + FRO 32 KHz is powered off during low power mode.. + 0x1 + + + + + PDEN_XTAL32K + Controls crystal 32 KHz power during DEEP SLEEP, POWER DOWN and DEEP POWER DOWN. + 7 + 1 + read-write + + + POWEREDON + crystal 32 KHz is powered on during low power mode.. + 0 + + + POWEREDOFF + crystal 32 KHz is powered off during low power mode.. + 0x1 + + + + + PDEN_XTAL32M + Controls crystal 32 MHz power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). + 8 + 1 + read-write + + + POWEREDON + crystal 32 MHz is powered on during low power mode.. + 0 + + + POWEREDOFF + crystal 32 MHz is powered off during low power mode.. + 0x1 + + + + + PDEN_PLL0 + Controls System PLL (also refered as PLL0) power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). + 9 + 1 + read-write + + + POWEREDON + System PLL (also refered as PLL0) is powered on during low power mode.. + 0 + + + POWEREDOFF + System PLL (also refered as PLL0) is powered off during low power mode.. + 0x1 + + + + + PDEN_PLL1 + Controls USB PLL (also refered as PLL1) power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). + 10 + 1 + read-write + + + POWEREDON + USB PLL (also refered as PLL1) is powered on during low power mode.. + 0 + + + POWEREDOFF + USB PLL (also refered as PLL1) is powered off during low power mode.. + 0x1 + + + + + PDEN_USBFSPHY + Controls USB Full Speed phy power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). + 11 + 1 + read-write + + + POWEREDON + USB Full Speed phy is powered on during low power mode.. + 0 + + + POWEREDOFF + USB Full Speed phy is powered off during low power mode.. + 0x1 + + + + + PDEN_USBHSPHY + Controls USB High Speed Phy power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). + 12 + 1 + read-write + + + POWEREDON + USB High Speed Phy is powered on during low power mode.. + 0 + + + POWEREDOFF + USB High Speed Phy is powered off during low power mode.. + 0x1 + + + + + PDEN_COMP + Controls Analog Comparator power during DEEP SLEEP and POWER DOWN (always shut down during DEEP POWER DOWN). + 13 + 1 + read-write + + + POWEREDON + Analog Comparator is powered on during low power mode.. + 0 + + + POWEREDOFF + Analog Comparator is powered off during low power mode.. + 0x1 + + + + + PDEN_TEMPSENS + Controls Temperature Sensor power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). + 14 + 1 + read-write + + + POWEREDON + Temperature Sensor is powered on during low power mode.. + 0 + + + POWEREDOFF + Temperature Sensor is powered off during low power mode.. + 0x1 + + + + + PDEN_GPADC + Controls General Purpose ADC (GPADC) power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). + 15 + 1 + read-write + + + POWEREDON + General Purpose ADC (GPADC) is powered on during low power mode.. + 0 + + + POWEREDOFF + General Purpose ADC (GPADC) is powered off during low power mode.. + 0x1 + + + + + PDEN_LDOMEM + Controls Memories LDO power during DEEP SLEEP, POWER DOWN and DEEP POWER DOWN. + 16 + 1 + read-write + + + POWEREDON + Memories LDO is powered on during low power mode.. + 0 + + + POWEREDOFF + Memories LDO is powered off during low power mode.. + 0x1 + + + + + PDEN_LDODEEPSLEEP + Controls Deep Sleep LDO power during DEEP SLEEP and POWER DOWN (always shut down during DEEP POWER DOWN). + 17 + 1 + read-write + + + POWEREDON + Deep Sleep LDO is powered on during low power mode.. + 0 + + + POWEREDOFF + Deep Sleep LDO is powered off during low power mode.. + 0x1 + + + + + PDEN_LDOUSBHS + Controls USB high speed LDO power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). + 18 + 1 + read-write + + + POWEREDON + USB high speed LDO is powered on during low power mode.. + 0 + + + POWEREDOFF + USB high speed LDO is powered off during low power mode.. + 0x1 + + + + + PDEN_AUXBIAS + during DEEP SLEEP and POWER DOWN (always shut down during DEEP POWER DOWN). + 19 + 1 + read-write + + + POWEREDON + is powered on during low power mode.. + 0 + + + POWEREDOFF + is powered off during low power mode.. + 0x1 + + + + + PDEN_LDOXO32M + Controls crystal 32 MHz LDO power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). + 20 + 1 + read-write + + + POWEREDON + crystal 32 MHz LDO is powered on during low power mode.. + 0 + + + POWEREDOFF + crystal 32 MHz LDO is powered off during low power mode.. + 0x1 + + + + + PDEN_LDOFLASHNV + Controls Flash NV (high voltage) LDO power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). + 21 + 1 + read-write + + + POWEREDON + Flash NV (high voltage) is powered on during low power mode.. + 0 + + + POWEREDOFF + Flash NV (high voltage) is powered off during low power mode.. + 0x1 + + + + + PDEN_RNG + Controls True Random Number Genetaor (TRNG) clock sources power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). + 22 + 1 + read-write + + + POWEREDON + True Random Number Genetaor (TRNG) clock sources are powered on during low power mode.. + 0 + + + POWEREDOFF + True Random Number Genetaor (TRNG) clock sources are powered off during low power mode.. + 0x1 + + + + + PDEN_PLL0_SSCG + Controls PLL0 Spread Sprectrum module power during DEEP SLEEP (PLL0 Spread Spectrum is always shut down during POWER DOWN and DEEP POWER DOWN). + 23 + 1 + read-write + + + POWEREDON + PLL0 Spread Sprectrum module is powered on during low power mode.. + 0 + + + POWEREDOFF + PLL0 Spread Sprectrum module is powered off during low power mode.. + 0x1 + + + + + PDEN_ROM + Controls ROM power during DEEP SLEEP (ROM is always shut down during POWER DOWN and DEEP POWER DOWN). + 24 + 1 + read-write + + + POWEREDON + ROM is powered on during low power mode.. + 0 + + + POWEREDOFF + ROM is powered off during low power mode.. + 0x1 + + + + + + + PDRUNCFG0 + Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] + 0xB8 + 32 + read-write + 0xDEFFC4 + 0xFFFFEF + + + PDEN_DCDC + Controls power to Bulk DCDC Converter. + 0 + 1 + read-write + + + POWEREDON + DCDC is powered. + 0 + + + POWEREDOFF + DCDC is powered down. + 0x1 + + + + + PDEN_BIAS + Controls power to . + 1 + 1 + read-write + + + POWEREDON + Analog Bias is powered. + 0 + + + POWEREDOFF + Analog Bias is powered down. + 0x1 + + + + + PDEN_BODCORE + Controls power to Core Brown Out Detector (BOD). + 2 + 1 + read-write + + + POWEREDON + BOD CORE is powered. + 0 + + + POWEREDOFF + BOD CORE is powered down. + 0x1 + + + + + PDEN_BODVBAT + Controls power to VBAT Brown Out Detector (BOD). + 3 + 1 + read-write + + + POWEREDON + BOD VBAT is powered. + 0 + + + POWEREDOFF + BOD VBAT is powered down. + 0x1 + + + + + PDEN_FRO192M + Controls power to the Free Running Oscillator (FRO) 192 MHz; The 12MHz, 48 MHz and 96 MHz clocks are derived from this FRO. + 5 + 1 + read-write + + + POWEREDON + FRO 192MHz is powered. + 0 + + + POWEREDOFF + FRO 192MHz is powered down. + 0x1 + + + + + PDEN_FRO32K + Controls power to the Free Running Oscillator (FRO) 32 KHz. + 6 + 1 + read-write + + + POWEREDON + FRO32KHz is powered. + 0 + + + POWEREDOFF + FRO32KHz is powered down. + 0x1 + + + + + PDEN_XTAL32K + Controls power to crystal 32 KHz. + 7 + 1 + read-write + + + POWEREDON + Crystal 32KHz is powered. + 0 + + + POWEREDOFF + Crystal 32KHz is powered down. + 0x1 + + + + + PDEN_XTAL32M + Controls power to crystal 32 MHz. + 8 + 1 + read-write + + + POWEREDON + Crystal 32MHz is powered. + 0 + + + POWEREDOFF + Crystal 32MHz is powered down. + 0x1 + + + + + PDEN_PLL0 + Controls power to System PLL (also refered as PLL0). + 9 + 1 + read-write + + + POWEREDON + PLL0 is powered. + 0 + + + POWEREDOFF + PLL0 is powered down. + 0x1 + + + + + PDEN_PLL1 + Controls power to USB PLL (also refered as PLL1). + 10 + 1 + read-write + + + POWEREDON + PLL1 is powered. + 0 + + + POWEREDOFF + PLL1 is powered down. + 0x1 + + + + + PDEN_USBFSPHY + Controls power to USB Full Speed phy. + 11 + 1 + read-write + + + POWEREDON + USB Full Speed phy is powered. + 0 + + + POWEREDOFF + USB Full Speed phy is powered down. + 0x1 + + + + + PDEN_USBHSPHY + Controls power to USB High Speed Phy. + 12 + 1 + read-write + + + POWEREDON + USB HS phy is powered. + 0 + + + POWEREDOFF + USB HS phy is powered down. + 0x1 + + + + + PDEN_COMP + Controls power to Analog Comparator. + 13 + 1 + read-write + + + POWEREDON + Analog Comparator is powered. + 0 + + + POWEREDOFF + Analog Comparator is powered down. + 0x1 + + + + + PDEN_TEMPSENS + Controls power to Temperature Sensor. + 14 + 1 + read-write + + + POWEREDON + Temperature Sensor is powered. + 0 + + + POWEREDOFF + Temperature Sensor is powered down. + 0x1 + + + + + PDEN_GPADC + Controls power to General Purpose ADC (GPADC). + 15 + 1 + read-write + + + POWEREDON + GPADC is powered. + 0 + + + POWEREDOFF + GPADC is powered down. + 0x1 + + + + + PDEN_LDOMEM + Controls power to Memories LDO. + 16 + 1 + read-write + + + POWEREDON + Memories LDO is powered. + 0 + + + POWEREDOFF + Memories LDO is powered down. + 0x1 + + + + + PDEN_LDODEEPSLEEP + Controls power to Deep Sleep LDO. + 17 + 1 + read-write + + + POWEREDON + Deep Sleep LDO is powered. + 0 + + + POWEREDOFF + Deep Sleep LDO is powered down. + 0x1 + + + + + PDEN_LDOUSBHS + Controls power to USB high speed LDO. + 18 + 1 + read-write + + + POWEREDON + USB high speed LDO is powered. + 0 + + + POWEREDOFF + USB high speed LDO is powered down. + 0x1 + + + + + PDEN_AUXBIAS + Controls power to auxiliary biasing (AUXBIAS) + 19 + 1 + read-write + + + POWEREDON + auxiliary biasing is powered. + 0 + + + POWEREDOFF + auxiliary biasing is powered down. + 0x1 + + + + + PDEN_LDOXO32M + Controls power to crystal 32 MHz LDO. + 20 + 1 + read-write + + + POWEREDON + crystal 32 MHz LDO is powered. + 0 + + + POWEREDOFF + crystal 32 MHz LDO is powered down. + 0x1 + + + + + PDEN_LDOFLASHNV + Controls power to Flasn NV (high voltage) LDO. + 21 + 1 + read-write + + + POWEREDON + Flash NV LDO is powered. + 0 + + + POWEREDOFF + Flash NV LDO is powered down. + 0x1 + + + + + PDEN_RNG + Controls power to all True Random Number Genetaor (TRNG) clock sources. + 22 + 1 + read-write + + + POWEREDON + TRNG clocks are powered. + 0 + + + POWEREDOFF + TRNG clocks are powered down. + 0x1 + + + + + PDEN_PLL0_SSCG + Controls power to System PLL (PLL0) Spread Spectrum module. + 23 + 1 + read-write + + + POWEREDON + PLL0 Sread spectrum module is powered. + 0 + + + POWEREDOFF + PLL0 Sread spectrum module is powered down. + 0x1 + + + + + + + PDRUNCFGSET0 + Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] + 0xC0 + 32 + write-only + 0 + 0xFFFFFFFF + + + PDRUNCFGSET0 + Writing ones to this register sets the corresponding bit or bits in the PDRUNCFG0 register, if they are implemented. + 0 + 32 + write-only + + + + + PDRUNCFGCLR0 + Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] + 0xC8 + 32 + write-only + 0 + 0xFFFFFFFF + + + PDRUNCFGCLR0 + Writing ones to this register clears the corresponding bit or bits in the PDRUNCFG0 register, if they are implemented. + 0 + 32 + write-only + + + + + + + SYSCTL + system controller + SYSCTL + 0x40023000 + + 0 + 0x104 + registers + + + + UPDATELCKOUT + update lock out control + 0 + 32 + read-write + 0 + 0x1 + + + UPDATELCKOUT + All Registers + 0 + 1 + read-write + + + NORMAL_MODE + Normal Mode. Can be written to. + 0 + + + PROTECTED_MODE + Protected Mode. Cannot be written to. + 0x1 + + + + + + + 8 + 0x4 + 0,1,2,3,4,5,6,7 + FCCTRLSEL%s + Selects the source for SCK going into Flexcomm 0 + 0x40 + 32 + read-write + 0 + 0x3030303 + + + SCKINSEL + Selects the source for SCK going into this Flexcomm. + 0 + 2 + read-writeOnce + + + ORIG_FLEX_I2S_SIGNALS + Selects the dedicated FCn_SCK function for this Flexcomm. + 0 + + + SHARED_SET0_I2S_SIGNALS + SCK is taken from shared signal set 0 (defined by SHAREDCTRLSET0). + 0x1 + + + SHARED_SET1_I2S_SIGNALS + SCK is taken from shared signal set 1 (defined by SHAREDCTRLSET1). + 0x2 + + + + + WSINSEL + Selects the source for WS going into this Flexcomm. + 8 + 2 + read-write + + + ORIG_FLEX_I2S_SIGNALS + Selects the dedicated (FCn_TXD_SCL_MISO_WS) function for this Flexcomm. + 0 + + + SHARED_SET0_I2S_SIGNALS + WS is taken from shared signal set 0 (defined by SHAREDCTRLSET0). + 0x1 + + + SHARED_SET1_I2S_SIGNALS + WS is taken from shared signal set 1 (defined by SHAREDCTRLSET1). + 0x2 + + + + + DATAINSEL + Selects the source for DATA input to this Flexcomm. + 16 + 2 + read-write + + + ORIG_FLEX_I2S_SIGNALS + Selects the dedicated FCn_RXD_SDA_MOSI_DATA input for this Flexcomm. + 0 + + + SHARED_SET0_I2S_SIGNALS + Input data is taken from shared signal set 0 (defined by SHAREDCTRLSET0). + 0x1 + + + SHARED_SET1_I2S_SIGNALS + Input data is taken from shared signal set 1 (defined by SHAREDCTRLSET1). + 0x2 + + + + + DATAOUTSEL + Selects the source for DATA output from this Flexcomm. + 24 + 2 + read-write + + + ORIG_FLEX_I2S_SIGNALS + Selects the dedicated FCn_RXD_SDA_MOSI_DATA output from this Flexcomm. + 0 + + + SHARED_SET0_I2S_SIGNALS + Output data is taken from shared signal set 0 (defined by SHAREDCTRLSET0). + 0x1 + + + SHARED_SET1_I2S_SIGNALS + Output data is taken from shared signal set 1 (defined by SHAREDCTRLSET1). + 0x2 + + + + + + + 2 + 0x4 + 0,1 + SHAREDCTRLSET%s + Selects sources and data combinations for shared signal set 0. + 0x80 + 32 + read-write + 0 + 0xFF0777 + + + SHAREDSCKSEL + Selects the source for SCK of this shared signal set. + 0 + 3 + read-write + + + FLEXCOMM0 + SCK for this shared signal set comes from Flexcomm 0. + 0 + + + FLEXCOMM1 + SCK for this shared signal set comes from Flexcomm 1. + 0x1 + + + FLEXCOMM2 + SCK for this shared signal set comes from Flexcomm 2. + 0x2 + + + FLEXCOMM3 + SCK for this shared signal set comes from Flexcomm 3. + 0x3 + + + FLEXCOMM4 + SCK for this shared signal set comes from Flexcomm 4. + 0x4 + + + FLEXCOMM5 + SCK for this shared signal set comes from Flexcomm 5. + 0x5 + + + FLEXCOMM6 + SCK for this shared signal set comes from Flexcomm 6. + 0x6 + + + FLEXCOMM7 + SCK for this shared signal set comes from Flexcomm 7. + 0x7 + + + + + SHAREDWSSEL + Selects the source for WS of this shared signal set. + 4 + 3 + read-write + + + FLEXCOMM0 + WS for this shared signal set comes from Flexcomm 0. + 0 + + + FLEXCOMM1 + WS for this shared signal set comes from Flexcomm 1. + 0x1 + + + FLEXCOMM2 + WS for this shared signal set comes from Flexcomm 2. + 0x2 + + + FLEXCOMM3 + WS for this shared signal set comes from Flexcomm 3. + 0x3 + + + FLEXCOMM4 + WS for this shared signal set comes from Flexcomm 4. + 0x4 + + + FLEXCOMM5 + WS for this shared signal set comes from Flexcomm 5. + 0x5 + + + FLEXCOMM6 + WS for this shared signal set comes from Flexcomm 6. + 0x6 + + + FLEXCOMM7 + WS for this shared signal set comes from Flexcomm 7. + 0x7 + + + + + SHAREDDATASEL + Selects the source for DATA input for this shared signal set. + 8 + 3 + read-write + + + FLEXCOMM0 + DATA input for this shared signal set comes from Flexcomm 0. + 0 + + + FLEXCOMM1 + DATA input for this shared signal set comes from Flexcomm 1. + 0x1 + + + FLEXCOMM2 + DATA input for this shared signal set comes from Flexcomm 2. + 0x2 + + + FLEXCOMM3 + DATA input for this shared signal set comes from Flexcomm 3. + 0x3 + + + FLEXCOMM4 + DATA input for this shared signal set comes from Flexcomm 4. + 0x4 + + + FLEXCOMM5 + DATA input for this shared signal set comes from Flexcomm 5. + 0x5 + + + FLEXCOMM6 + DATA input for this shared signal set comes from Flexcomm 6. + 0x6 + + + FLEXCOMM7 + DATA input for this shared signal set comes from Flexcomm 7. + 0x7 + + + + + FC0DATAOUTEN + Controls FC0 contribution to SHAREDDATAOUT for this shared set. + 16 + 1 + read-write + + + INPUT + Data output from FC0 does not contribute to this shared set. + 0 + + + OUTPUT + Data output from FC0 does contribute to this shared set. + 0x1 + + + + + FC1DATAOUTEN + Controls FC1 contribution to SHAREDDATAOUT for this shared set. + 17 + 1 + read-write + + + INPUT + Data output from FC1 does not contribute to this shared set. + 0 + + + OUTPUT + Data output from FC1 does contribute to this shared set. + 0x1 + + + + + F20DATAOUTEN + Controls FC2 contribution to SHAREDDATAOUT for this shared set. + 18 + 1 + read-write + + + INPUT + Data output from FC2 does not contribute to this shared set. + 0 + + + OUTPUT + Data output from FC2 does contribute to this shared set. + 0x1 + + + + + FC3DATAOUTEN + Controls FC3 contribution to SHAREDDATAOUT for this shared set. + 19 + 1 + read-write + + + INPUT + Data output from FC3 does not contribute to this shared set. + 0 + + + OUTPUT + Data output from FC3 does contribute to this shared set. + 0x1 + + + + + FC4DATAOUTEN + Controls FC4 contribution to SHAREDDATAOUT for this shared set. + 20 + 1 + read-write + + + INPUT + Data output from FC4 does not contribute to this shared set. + 0 + + + OUTPUT + Data output from FC4 does contribute to this shared set. + 0x1 + + + + + FC5DATAOUTEN + Controls FC5 contribution to SHAREDDATAOUT for this shared set. + 21 + 1 + read-write + + + INPUT + Data output from FC5 does not contribute to this shared set. + 0 + + + OUTPUT + Data output from FC5 does contribute to this shared set. + 0x1 + + + + + FC6DATAOUTEN + Controls FC6 contribution to SHAREDDATAOUT for this shared set. + 22 + 1 + read-write + + + INPUT + Data output from FC6 does not contribute to this shared set. + 0 + + + OUTPUT + Data output from FC6 does contribute to this shared set. + 0x1 + + + + + FC7DATAOUTEN + Controls FC7 contribution to SHAREDDATAOUT for this shared set. + 23 + 1 + read-write + + + INPUT + Data output from FC7 does not contribute to this shared set. + 0 + + + OUTPUT + Data output from FC7 does contribute to this shared set. + 0x1 + + + + + + + USB_HS_STATUS + Status register for USB HS + 0x100 + 32 + read-write + 0 + 0x1C0FF00 + + + USBHS_3V_NOK + USB_HS: Low voltage detection on 3.3V supply. + 0 + 1 + read-only + + + SUPPLY_3V_OK + 3v3 supply is good. + 0 + + + SUPPLY_3V_LOW + 3v3 supply is too low. + 0x1 + + + + + + + + + RTC + Real-Time Clock (RTC) + RTC + 0x4002C000 + + 0 + 0x60 + registers + + + RTC + 29 + + + + CTRL + RTC control register + 0 + 32 + read-write + 0x1 + 0x3FD + + + SWRESET + Software reset control + 0 + 1 + read-write + + + NOT_IN_RESET + Not in reset. The RTC is not held in reset. This bit must be cleared prior to configuring or initiating any operation of the RTC. + 0 + + + IN_RESET + In reset. The RTC is held in reset. All register bits within the RTC will be forced to their reset value except the OFD bit. This bit must be cleared before writing to any register in the RTC - including writes to set any of the other bits within this register. Do not attempt to write to any bits of this register at the same time that the reset bit is being cleared. + 0x1 + + + + + ALARM1HZ + RTC 1 Hz timer alarm flag status. + 2 + 1 + read-write + + + NO_MATCH + No match. No match has occurred on the 1 Hz RTC timer. Writing a 0 has no effect. + 0 + + + MATCH + Match. A match condition has occurred on the 1 Hz RTC timer. This flag generates an RTC alarm interrupt request RTC_ALARM which can also wake up the part from any low power mode. Writing a 1 clears this bit. + 0x1 + + + + + WAKE1KHZ + RTC 1 kHz timer wake-up flag status. + 3 + 1 + read-write + + + RUN + Run. The RTC 1 kHz timer is running. Writing a 0 has no effect. + 0 + + + TIMEOUT + Time-out. The 1 kHz high-resolution/wake-up timer has timed out. This flag generates an RTC wake-up interrupt request RTC-WAKE which can also wake up the part from any low power mode. Writing a 1 clears this bit. + 0x1 + + + + + ALARMDPD_EN + RTC 1 Hz timer alarm enable for Deep power-down. + 4 + 1 + read-write + + + DISABLE + Disable. A match on the 1 Hz RTC timer will not bring the part out of Deep power-down mode. + 0 + + + ENABLE + Enable. A match on the 1 Hz RTC timer bring the part out of Deep power-down mode. + 0x1 + + + + + WAKEDPD_EN + RTC 1 kHz timer wake-up enable for Deep power-down. + 5 + 1 + read-write + + + DISABLE + Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode. + 0 + + + ENABLE + Enable. A match on the 1 kHz RTC timer bring the part out of Deep power-down mode. + 0x1 + + + + + RTC1KHZ_EN + RTC 1 kHz clock enable. This bit can be set to 0 to conserve power if the 1 kHz timer is not used. This bit has no effect when the RTC is disabled (bit 7 of this register is 0). + 6 + 1 + read-write + + + DISABLE + Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode. + 0 + + + ENABLE + Enable. The 1 kHz RTC timer is enabled. + 0x1 + + + + + RTC_EN + RTC enable. + 7 + 1 + read-write + + + DISABLE + Disable. The RTC 1 Hz and 1 kHz clocks are shut down and the RTC operation is disabled. This bit should be 0 when writing to load a value in the RTC counter register. + 0 + + + ENABLE + Enable. The 1 Hz RTC clock is running and RTC operation is enabled. This bit must be set to initiate operation of the RTC. The first clock to the RTC counter occurs 1 s after this bit is set. To also enable the high-resolution, 1 kHz clock, set bit 6 in this register. + 0x1 + + + + + RTC_OSC_PD + RTC oscillator power-down control. + 8 + 1 + read-write + + + POWER_UP + See RTC_OSC_BYPASS + 0 + + + POWERED_DOWN + RTC oscillator is powered-down. + 0x1 + + + + + RTC_OSC_BYPASS + RTC oscillator bypass control. + 9 + 1 + read-write + + + USED + The RTC Oscillator operates normally as a crystal oscillator with the crystal connected between the RTC_XTALIN and RTC_XTALOUT pins. + 0 + + + BYPASS + The RTC Oscillator is in bypass mode. In this mode a clock can be directly input into the RTC_XTALIN pin. + 0x1 + + + + + RTC_SUBSEC_ENA + RTC Sub-second counter control. + 10 + 1 + read-write + + + POWER_UP + The sub-second counter (if implemented) is disabled. This bit is cleared by a system-level POR or BOD reset as well as a by the RTC_ENA bit (bit 7 in this register). On modules not equipped with a sub-second counter, this bit will always read-back as a '0'. + 0 + + + POWERED_DOWN + The 32 KHz sub-second counter is enabled (if implemented). Counting commences on the start of the first one-second interval after this bit is set. Note: This bit can only be set after the RTC_ENA bit (bit 7) is set by a previous write operation. Note: The RTC sub-second counter must be re-enabled whenever the chip exits deep power-down mode. + 0x1 + + + + + + + MATCH + RTC match register + 0x4 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + MATVAL + Contains the match value against which the 1 Hz RTC timer will be compared to set the alarm flag RTC_ALARM and generate an alarm interrupt/wake-up if enabled. + 0 + 32 + read-write + + + + + COUNT + RTC counter register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + VAL + A read reflects the current value of the main, 1 Hz RTC timer. A write loads a new initial value into the timer. The RTC counter will count up continuously at a 1 Hz rate once the RTC Software Reset is removed (by clearing bit 0 of the CTRL register). Only write to this register when the RTC_EN bit in the RTC CTRL Register is 0. The counter increments one second after the RTC_EN bit is set. + 0 + 32 + read-write + + + + + WAKE + High-resolution/wake-up timer control register + 0xC + 32 + read-write + 0 + 0xFFFF + + + VAL + A read reflects the current value of the high-resolution/wake-up timer. A write pre-loads a start count value into the wake-up timer and initializes a count-down sequence. Do not write to this register while counting is in progress. + 0 + 16 + read-write + + + + + SUBSEC + RTC Sub-second Counter register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + SUBSEC + A read reflects the current value of the 32Khz sub-second counter. This counter will be cleared whenever the SUBSEC_ENA bit in the RTC_CONTROL register is low. Up-counting at a 32 KHz rate commences at the start of the next one-second interval after the SUBSEC_ENA bit is set. This counter must be re-enabled after exiting deep_powerdown mode or after the main RTC module has been disabled and re-enabled. On modules not equipped with a sub-second counter, this register will read-back as all zeroes. + 0 + 15 + read-only + + + + + 8 + 0x4 + GPREG[%s] + General Purpose register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPDATA + Data retained during Deep power-down mode or loss of main power as long as VBAT is supplied. + 0 + 32 + read-write + + + + + + + OSTIMER + Synchronous OS/Event timer with Wakeup Timer + OSTIMER + 0x4002D000 + + 0 + 0x20 + registers + + + OS_EVENT + 38 + + + + EVTIMERL + EVTIMER Low Register + 0 + 32 + read-only + 0 + 0xFFFFFFFF + + + EVTIMER_COUNT_VALUE + A read reflects the current value of the lower 32 bits of the EVTIMER. Note there is physically only one EVTimer, readable from all domains. + 0 + 32 + read-only + + + + + EVTIMERH + EVTIMER High Register + 0x4 + 32 + read-only + 0 + 0xFFFFFFFF + + + EVTIMER_COUNT_VALUE + A read reflects the current value of the upper 32 bits of the EVTIMER. Note there is physically only one EVTimer, readable from all domains. + 0 + 32 + read-only + + + + + CAPTUREn_L + Local Capture Low Register for CPUn + 0x8 + 32 + read-only + 0 + 0xFFFFFFFF + + + CAPTUREn_VALUE + A read reflects the value of the lower 32 bits of the central EVTIMER at the time the last capture signal was generated by the CPU. A separate pair of CAPTURE registers are implemented for each CPU. Each CPU reads its own capture value at the same pair of addresses. + 0 + 32 + read-only + + + + + CAPTUREn_H + Local Capture High Register for CPUn + 0xC + 32 + read-only + 0 + 0xFFFFFFFF + + + CAPTUREn_VALUE + A read reflects the value of the upper 32 bits of the central EVTIMER at the time the last capture signal was generated by the CPU. A separate pair of CAPTURE registers are implemented for each CPU. Each CPU reads its own capture value at the same pair of addresses. + 0 + 32 + read-only + + + + + MATCHn_L + Local Match Low Register for CPUn + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + MATCHn_VALUE + The value written to the MATCH (L/H) register pair is compared against the central EVTIMER. When a match occurs, an interrupt request is generated if enabled. A separate pair of MATCH registers are implemented for each CPU. Each CPU reads its own local value at the same pair of addresses. + 0 + 32 + read-write + + + + + MATCHn_H + Match High Register for CPUn + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + MATCHn_VALUE + The value written to the MATCH (L/H) register pair is compared against the central EVTIMER. When a match occurs, an interrupt request is generated if enabled. A separate pair of MATCH registers are implemented for each CPU. Each CPU reads its own local value at the same pair of addresses. + 0 + 32 + read-write + + + + + OSEVENT_CTRL + OS_EVENT TIMER Control Register for CPUn + 0x1C + 32 + read-write + 0 + 0x3 + + + OSTIMER_INTRFLAG + This bit is set when a match occurs between the central 64-bit EVTIMER and the value programmed in the Match-register pair for the associated CPU This bit is cleared by writing a '1'. Writes to clear this bit are asynchronous. This should be done before a new match value is written into the MATCH_L/H registers + 0 + 1 + read-write + + + OSTIMER_INTENA + When this bit is '1' an interrupt/wakeup request to the Domainn processor will be asserted when the OSTIMER_INTR flag is set. When this bit is '0', interrupt/wakeup requests due to the OSTIMER_INTR flag are blocked.A separate OSEVENT_CTRL register is implemented for each CPU. Each CPU reads its own local value at the same address. + 1 + 1 + read-write + + + + + + + FLASH + FLASH + FLASH + 0x40034000 + + 0 + 0x1000 + registers + + + + CMD + command register + 0 + 32 + write-only + 0 + 0xFFFFFFFF + + + CMD + command register. + 0 + 32 + write-only + + + + + EVENT + event register + 0x4 + 32 + write-only + 0 + 0x7 + + + RST + When bit is set, the controller and flash are reset. + 0 + 1 + write-only + + + WAKEUP + When bit is set, the controller wakes up from whatever low power or powerdown mode was active. + 1 + 1 + write-only + + + ABORT + When bit is set, a running program/erase command is aborted. + 2 + 1 + write-only + + + + + BURST + read burst register + 0x8 + 32 + read-write + 0x80000000 + 0xFFFFFFFF + + + XOR_MASK + burst 2 XOR mask. + 0 + 20 + read-write + + + DESCR1 + Burst 1 descriptor. + 20 + 4 + read-write + + + DESCR2 + Burst 2 descriptor. + 24 + 4 + read-write + + + DESCR3 + Burst 3 descriptor. + 28 + 4 + read-write + + + + + STARTA + start (or only) address for next flash command + 0x10 + 32 + read-write + 0 + 0x3FFFF + + + STARTA + Address / Start address for commands that take an address (range) as a parameter. + 0 + 18 + read-write + + + + + STOPA + end address for next flash command, if command operates on address ranges + 0x14 + 32 + read-write + 0 + 0x3FFFF + + + STOPA + Stop address for commands that take an address range as a parameter (the word specified by STOPA is included in the address range). + 0 + 18 + read-write + + + + + 8 + 0x4 + DATAW[%s] + data register, word 0-7; Memory data, or command parameter, or command result. + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATAW + no description available + 0 + 32 + read-write + + + + + INT_CLR_ENABLE + Clear interrupt enable bits + 0xFD8 + 32 + write-only + 0 + 0xF + + + FAIL + When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared. + 0 + 1 + write-only + + + ERR + When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared. + 1 + 1 + write-only + + + DONE + When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared. + 2 + 1 + write-only + + + ECC_ERR + When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared. + 3 + 1 + write-only + + + + + INT_SET_ENABLE + Set interrupt enable bits + 0xFDC + 32 + write-only + 0 + 0xF + + + FAIL + When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set. + 0 + 1 + write-only + + + ERR + When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set. + 1 + 1 + write-only + + + DONE + When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set. + 2 + 1 + write-only + + + ECC_ERR + When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set. + 3 + 1 + write-only + + + + + INT_STATUS + Interrupt status bits + 0xFE0 + 32 + read-write + 0 + 0xF + + + FAIL + This status bit is set if execution of a (legal) command failed. + 0 + 1 + read-only + + + ERR + This status bit is set if execution of an illegal command is detected. + 1 + 1 + read-only + + + DONE + This status bit is set at the end of command execution. + 2 + 1 + read-only + + + ECC_ERR + This status bit is set if, during a memory read operation (either a user-requested read, or a speculative read, or reads performed by a controller command), a correctable or uncorrectable error is detected by ECC decoding logic. + 3 + 1 + read-only + + + + + INT_ENABLE + Interrupt enable bits + 0xFE4 + 32 + read-write + 0 + 0xF + + + FAIL + If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high. + 0 + 1 + read-only + + + ERR + If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high. + 1 + 1 + read-only + + + DONE + If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high. + 2 + 1 + read-only + + + ECC_ERR + If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high. + 3 + 1 + read-only + + + + + INT_CLR_STATUS + Clear interrupt status bits + 0xFE8 + 32 + write-only + 0 + 0xF + + + FAIL + When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared. + 0 + 1 + write-only + + + ERR + When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared. + 1 + 1 + write-only + + + DONE + When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared. + 2 + 1 + write-only + + + ECC_ERR + When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared. + 3 + 1 + write-only + + + + + INT_SET_STATUS + Set interrupt status bits + 0xFEC + 32 + write-only + 0 + 0xF + + + FAIL + When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set. + 0 + 1 + write-only + + + ERR + When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set. + 1 + 1 + write-only + + + DONE + When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set. + 2 + 1 + write-only + + + ECC_ERR + When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set. + 3 + 1 + write-only + + + + + MODULE_ID + Controller+Memory module identification + 0xFFC + 32 + read-only + 0xC40F0800 + 0xFFFFFFFF + + + APERTURE + Aperture i. + 0 + 8 + read-only + + + MINOR_REV + Minor revision i. + 8 + 4 + read-only + + + MAJOR_REV + Major revision i. + 12 + 4 + read-only + + + ID + Identifier. + 16 + 16 + read-only + + + + + + + PRINCE + PRINCE + PRINCE + 0x40035000 + + 0 + 0x40 + registers + + + + ENC_ENABLE + Encryption Enable register + 0 + 32 + read-write + 0 + 0x1 + + + EN + Encryption Enable. + 0 + 1 + read-write + + + DISABLED + Encryption of writes to the flash controller DATAW* registers is disabled.. + 0 + + + ENABLED + Encryption of writes to the flash controller DATAW* registers is enabled.. + 0x1 + + + + + + + MASK_LSB + Data Mask register, 32 Least Significant Bits + 0x4 + 32 + write-only + 0 + 0xFFFFFFFF + + + MASKVAL + Value of the 32 Least Significant Bits of the 64-bit data mask. + 0 + 32 + write-only + + + + + MASK_MSB + Data Mask register, 32 Most Significant Bits + 0x8 + 32 + write-only + 0 + 0xFFFFFFFF + + + MASKVAL + Value of the 32 Most Significant Bits of the 64-bit data mask. + 0 + 32 + write-only + + + + + LOCK + Lock register + 0xC + 32 + read-write + 0 + 0x107 + + + LOCKREG0 + Lock Region 0 registers. + 0 + 1 + read-write + + + DISABLED + Disabled. IV_LSB0, IV_MSB0, BASE_ADDR0, and SR_ENABLE0 are writable.. + 0 + + + ENABLED + Enabled. IV_LSB0, IV_MSB0, BASE_ADDR0, and SR_ENABLE0 are not writable.. + 0x1 + + + + + LOCKREG1 + Lock Region 1 registers. + 1 + 1 + read-write + + + DISABLED + Disabled. IV_LSB1, IV_MSB1, BASE_ADDR1, and SR_ENABLE1 are writable.. + 0 + + + ENABLED + Enabled. IV_LSB1, IV_MSB1, BASE_ADDR1, and SR_ENABLE1 are not writable.. + 0x1 + + + + + LOCKREG2 + Lock Region 2 registers. + 2 + 1 + read-write + + + DISABLED + Disabled. IV_LSB2, IV_MSB2, BASE_ADDR2, and SR_ENABLE2 are writable.. + 0 + + + ENABLED + Enabled. IV_LSB2, IV_MSB2, BASE_ADDR2, and SR_ENABLE2 are not writable.. + 0x1 + + + + + LOCKMASK + Lock the Mask registers. + 8 + 1 + read-write + + + DISABLED + Disabled. MASK_LSB, and MASK_MSB are writable.. + 0 + + + ENABLED + Enabled. MASK_LSB, and MASK_MSB are not writable.. + 0x1 + + + + + + + IV_LSB0 + Initial Vector register for region 0, Least Significant Bits + 0x10 + 32 + write-only + 0 + 0xFFFFFFFF + + + IVVAL + Initial Vector value for the 32 Least Significant Bits of the 64-bit Initial Vector. + 0 + 32 + write-only + + + + + IV_MSB0 + Initial Vector register for region 0, Most Significant Bits + 0x14 + 32 + write-only + 0 + 0xFFFFFFFF + + + IVVAL + Initial Vector value for the 32 Most Significant Bits of the 64-bit Initial Vector. + 0 + 32 + write-only + + + + + BASE_ADDR0 + Base Address for region 0 register + 0x18 + 32 + read-write + 0 + 0xFFFFF + + + ADDR_FIXED + Fixed portion of the base address of region 0. + 0 + 18 + read-only + + + ADDR_PRG + Programmable portion of the base address of region 0. + 18 + 2 + read-write + + + + + SR_ENABLE0 + Sub-Region Enable register for region 0 + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + EN + Each bit in this field enables an 8KB subregion for encryption at offset 8KB*bitnum of region 0. + 0 + 32 + read-write + + + + + IV_LSB1 + Initial Vector register for region 1, Least Significant Bits + 0x20 + 32 + write-only + 0 + 0xFFFFFFFF + + + IVVAL + Initial Vector value for the 32 Least Significant Bits of the 64-bit Initial Vector. + 0 + 32 + write-only + + + + + IV_MSB1 + Initial Vector register for region 1, Most Significant Bits + 0x24 + 32 + write-only + 0 + 0xFFFFFFFF + + + IVVAL + Initial Vector value for the 32 Most Significant Bits of the 64-bit Initial Vector. + 0 + 32 + write-only + + + + + BASE_ADDR1 + Base Address for region 1 register + 0x28 + 32 + read-write + 0x40000 + 0xFFFFF + + + ADDR_FIXED + Fixed portion of the base address of region 1. + 0 + 18 + read-only + + + ADDR_PRG + Programmable portion of the base address of region 1. + 18 + 2 + read-write + + + + + SR_ENABLE1 + Sub-Region Enable register for region 1 + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + EN + Each bit in this field enables an 8KB subregion for encryption at offset 8KB*bitnum of region 1. + 0 + 32 + read-write + + + + + IV_LSB2 + Initial Vector register for region 2, Least Significant Bits + 0x30 + 32 + write-only + 0 + 0xFFFFFFFF + + + IVVAL + Initial Vector value for the 32 Least Significant Bits of the 64-bit Initial Vector. + 0 + 32 + write-only + + + + + IV_MSB2 + Initial Vector register for region 2, Most Significant Bits + 0x34 + 32 + write-only + 0 + 0xFFFFFFFF + + + IVVAL + Initial Vector value for the 32 Most Significant Bits of the 64-bit Initial Vector. + 0 + 32 + write-only + + + + + BASE_ADDR2 + Base Address for region 2 register + 0x38 + 32 + read-write + 0x80000 + 0xFFFFF + + + ADDR_FIXED + Fixed portion of the base address of region 2. + 0 + 18 + read-only + + + ADDR_PRG + Programmable portion of the base address of region 2. + 18 + 2 + read-write + + + + + SR_ENABLE2 + Sub-Region Enable register for region 2 + 0x3C + 32 + read-write + 0 + 0xFFFFFFFF + + + EN + Each bit in this field enables an 8KB subregion for encryption at offset 8KB*bitnum of region 2. + 0 + 32 + read-write + + + + + + + USBPHY + Universal System Bus Physical Layer + USBPHY + 0x40038000 + + 0 + 0x110 + registers + + + + PWD + USB PHY Power-Down Register + 0 + 32 + read-write + 0x1E1C00 + 0xFFFFFFFF + + + TXPWDFS + Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled + 10 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the + 0x1 + + + + + TXPWDIBIAS + Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled + 11 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the + 0x1 + + + + + TXPWDV2I + Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled + 12 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Power-down the USB PHY transmit V-to-I converter and the current mirror + 0x1 + + + + + RXPWDENV + Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled + 17 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Power-down the USB high-speed receiver envelope detector (squelch signal) + 0x1 + + + + + RXPWD1PT1 + Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled + 18 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Power-down the USB full-speed differential receiver. + 0x1 + + + + + RXPWDDIFF + Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled + 19 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Power-down the USB high-speed differential receive + 0x1 + + + + + RXPWDRX + This bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled + 20 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Power-down the entire USB PHY receiver block except for the full-speed differential receiver + 0x1 + + + + + + + PWD_SET + USB PHY Power-Down Register + 0x4 + 32 + read-write + 0x1E1C00 + 0xFFFFFFFF + + + TXPWDFS + Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled + 10 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the + 0x1 + + + + + TXPWDIBIAS + Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled + 11 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the + 0x1 + + + + + TXPWDV2I + Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled + 12 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Power-down the USB PHY transmit V-to-I converter and the current mirror + 0x1 + + + + + RXPWDENV + Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled + 17 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Power-down the USB high-speed receiver envelope detector (squelch signal) + 0x1 + + + + + RXPWD1PT1 + Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled + 18 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Power-down the USB full-speed differential receiver. + 0x1 + + + + + RXPWDDIFF + Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled + 19 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Power-down the USB high-speed differential receive + 0x1 + + + + + RXPWDRX + This bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled + 20 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Power-down the entire USB PHY receiver block except for the full-speed differential receiver + 0x1 + + + + + + + PWD_CLR + USB PHY Power-Down Register + 0x8 + 32 + read-write + 0x1E1C00 + 0xFFFFFFFF + + + TXPWDFS + Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled + 10 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the + 0x1 + + + + + TXPWDIBIAS + Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled + 11 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the + 0x1 + + + + + TXPWDV2I + Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled + 12 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Power-down the USB PHY transmit V-to-I converter and the current mirror + 0x1 + + + + + RXPWDENV + Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled + 17 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Power-down the USB high-speed receiver envelope detector (squelch signal) + 0x1 + + + + + RXPWD1PT1 + Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled + 18 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Power-down the USB full-speed differential receiver. + 0x1 + + + + + RXPWDDIFF + Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled + 19 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Power-down the USB high-speed differential receive + 0x1 + + + + + RXPWDRX + This bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled + 20 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Power-down the entire USB PHY receiver block except for the full-speed differential receiver + 0x1 + + + + + + + PWD_TOG + USB PHY Power-Down Register + 0xC + 32 + read-write + 0x1E1C00 + 0xFFFFFFFF + + + TXPWDFS + Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled + 10 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the + 0x1 + + + + + TXPWDIBIAS + Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled + 11 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the + 0x1 + + + + + TXPWDV2I + Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled + 12 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Power-down the USB PHY transmit V-to-I converter and the current mirror + 0x1 + + + + + RXPWDENV + Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled + 17 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Power-down the USB high-speed receiver envelope detector (squelch signal) + 0x1 + + + + + RXPWD1PT1 + Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled + 18 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Power-down the USB full-speed differential receiver. + 0x1 + + + + + RXPWDDIFF + Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled + 19 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Power-down the USB high-speed differential receive + 0x1 + + + + + RXPWDRX + This bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled + 20 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Power-down the entire USB PHY receiver block except for the full-speed differential receiver + 0x1 + + + + + + + TX + USB PHY Transmitter Control Register + 0x10 + 32 + read-write + 0xA000402 + 0xFFFFFFFF + + + D_CAL + Decode to trim the nominal 17 + 0 + 4 + read-write + + + value0 + Maximum current, approximately 19% above nominal. + 0 + + + value7 + Nominal + 0x7 + + + value15 + Minimum current, approximately 19% below nominal. + 0xF + + + + + TXCAL45DM + Decode to trim the nominal 45ohm series termination resistance to the USB_DM output pin + 8 + 4 + read-write + + + TXENCAL45DN + Enable resistance calibration on DN. + 13 + 1 + read-write + + + TXCAL45DP + Decode to trim the nominal 45ohm series termination resistance to the USB_DP output pin + 16 + 4 + read-write + + + TXENCAL45DP + Enable resistance calibration on DP. + 21 + 1 + read-write + + + + + TX_SET + USB PHY Transmitter Control Register + 0x14 + 32 + read-write + 0xA000402 + 0xFFFFFFFF + + + D_CAL + Decode to trim the nominal 17 + 0 + 4 + read-write + + + value0 + Maximum current, approximately 19% above nominal. + 0 + + + value7 + Nominal + 0x7 + + + value15 + Minimum current, approximately 19% below nominal. + 0xF + + + + + TXCAL45DM + Decode to trim the nominal 45ohm series termination resistance to the USB_DM output pin + 8 + 4 + read-write + + + TXENCAL45DN + Enable resistance calibration on DN. + 13 + 1 + read-write + + + TXCAL45DP + Decode to trim the nominal 45ohm series termination resistance to the USB_DP output pin + 16 + 4 + read-write + + + TXENCAL45DP + Enable resistance calibration on DP. + 21 + 1 + read-write + + + + + TX_CLR + USB PHY Transmitter Control Register + 0x18 + 32 + read-write + 0xA000402 + 0xFFFFFFFF + + + D_CAL + Decode to trim the nominal 17 + 0 + 4 + read-write + + + value0 + Maximum current, approximately 19% above nominal. + 0 + + + value7 + Nominal + 0x7 + + + value15 + Minimum current, approximately 19% below nominal. + 0xF + + + + + TXCAL45DM + Decode to trim the nominal 45ohm series termination resistance to the USB_DM output pin + 8 + 4 + read-write + + + TXENCAL45DN + Enable resistance calibration on DN. + 13 + 1 + read-write + + + TXCAL45DP + Decode to trim the nominal 45ohm series termination resistance to the USB_DP output pin + 16 + 4 + read-write + + + TXENCAL45DP + Enable resistance calibration on DP. + 21 + 1 + read-write + + + + + TX_TOG + USB PHY Transmitter Control Register + 0x1C + 32 + read-write + 0xA000402 + 0xFFFFFFFF + + + D_CAL + Decode to trim the nominal 17 + 0 + 4 + read-write + + + value0 + Maximum current, approximately 19% above nominal. + 0 + + + value7 + Nominal + 0x7 + + + value15 + Minimum current, approximately 19% below nominal. + 0xF + + + + + TXCAL45DM + Decode to trim the nominal 45ohm series termination resistance to the USB_DM output pin + 8 + 4 + read-write + + + TXENCAL45DN + Enable resistance calibration on DN. + 13 + 1 + read-write + + + TXCAL45DP + Decode to trim the nominal 45ohm series termination resistance to the USB_DP output pin + 16 + 4 + read-write + + + TXENCAL45DP + Enable resistance calibration on DP. + 21 + 1 + read-write + + + + + RX + USB PHY Receiver Control Register + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENVADJ + The ENVADJ field adjusts the trip point for the envelope detector + 0 + 3 + read-write + + + value0 + Trip-Level Voltage is 0.1000 V + 0 + + + value1 + Trip-Level Voltage is 0.1125 V + 0x1 + + + value2 + Trip-Level Voltage is 0.1250 V + 0x2 + + + value3 + Trip-Level Voltage is 0.0875 V + 0x3 + + + + + DISCONADJ + The DISCONADJ field adjusts the trip point for the disconnect detector. + 4 + 3 + read-write + + + value0 + Trip-Level Voltage is 0.56875 V + 0 + + + value1 + Trip-Level Voltage is 0.55000 V + 0x1 + + + value2 + Trip-Level Voltage is 0.58125 V + 0x2 + + + value3 + Trip-Level Voltage is 0.60000 V + 0x3 + + + + + RXDBYPASS + This test mode is intended for lab use only, replace FS differential receiver with DP single ended receiver + 22 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver + 0x1 + + + + + + + RX_SET + USB PHY Receiver Control Register + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENVADJ + The ENVADJ field adjusts the trip point for the envelope detector + 0 + 3 + read-write + + + value0 + Trip-Level Voltage is 0.1000 V + 0 + + + value1 + Trip-Level Voltage is 0.1125 V + 0x1 + + + value2 + Trip-Level Voltage is 0.1250 V + 0x2 + + + value3 + Trip-Level Voltage is 0.0875 V + 0x3 + + + + + DISCONADJ + The DISCONADJ field adjusts the trip point for the disconnect detector. + 4 + 3 + read-write + + + value0 + Trip-Level Voltage is 0.56875 V + 0 + + + value1 + Trip-Level Voltage is 0.55000 V + 0x1 + + + value2 + Trip-Level Voltage is 0.58125 V + 0x2 + + + value3 + Trip-Level Voltage is 0.60000 V + 0x3 + + + + + RXDBYPASS + This test mode is intended for lab use only, replace FS differential receiver with DP single ended receiver + 22 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver + 0x1 + + + + + + + RX_CLR + USB PHY Receiver Control Register + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENVADJ + The ENVADJ field adjusts the trip point for the envelope detector + 0 + 3 + read-write + + + value0 + Trip-Level Voltage is 0.1000 V + 0 + + + value1 + Trip-Level Voltage is 0.1125 V + 0x1 + + + value2 + Trip-Level Voltage is 0.1250 V + 0x2 + + + value3 + Trip-Level Voltage is 0.0875 V + 0x3 + + + + + DISCONADJ + The DISCONADJ field adjusts the trip point for the disconnect detector. + 4 + 3 + read-write + + + value0 + Trip-Level Voltage is 0.56875 V + 0 + + + value1 + Trip-Level Voltage is 0.55000 V + 0x1 + + + value2 + Trip-Level Voltage is 0.58125 V + 0x2 + + + value3 + Trip-Level Voltage is 0.60000 V + 0x3 + + + + + RXDBYPASS + This test mode is intended for lab use only, replace FS differential receiver with DP single ended receiver + 22 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver + 0x1 + + + + + + + RX_TOG + USB PHY Receiver Control Register + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + ENVADJ + The ENVADJ field adjusts the trip point for the envelope detector + 0 + 3 + read-write + + + value0 + Trip-Level Voltage is 0.1000 V + 0 + + + value1 + Trip-Level Voltage is 0.1125 V + 0x1 + + + value2 + Trip-Level Voltage is 0.1250 V + 0x2 + + + value3 + Trip-Level Voltage is 0.0875 V + 0x3 + + + + + DISCONADJ + The DISCONADJ field adjusts the trip point for the disconnect detector. + 4 + 3 + read-write + + + value0 + Trip-Level Voltage is 0.56875 V + 0 + + + value1 + Trip-Level Voltage is 0.55000 V + 0x1 + + + value2 + Trip-Level Voltage is 0.58125 V + 0x2 + + + value3 + Trip-Level Voltage is 0.60000 V + 0x3 + + + + + RXDBYPASS + This test mode is intended for lab use only, replace FS differential receiver with DP single ended receiver + 22 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver + 0x1 + + + + + + + CTRL + USB PHY General Control Register + 0x30 + 32 + read-write + 0xC0000000 + 0xFFFFFFFF + + + ENHOSTDISCONDETECT + For host mode, enables high-speed disconnect detector + 1 + 1 + read-write + + + HOSTDISCONDETECT_IRQ + Indicates that the device has disconnected in High-Speed mode + 3 + 1 + read-write + + + ENDEVPLUGINDET + Enables non-standard resistive plugged-in detection This bit field controls connection of nominal 200kohm resistors to both the USB_DP and USB_DM pins as one method of detecting when a USB cable is attached in device mode + 4 + 1 + read-write + + + value0 + Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) + 0 + + + value1 + Enables 200kohm pullup resistors on USB_DP and USB_DM pins + 0x1 + + + + + DEVPLUGIN_IRQ + Indicates that the device is connected + 12 + 1 + read-write + + + DATA_ON_LRADC + Data on LR ADC: Enables the LRADC to monitor USB_DP and USB_DM + 13 + 1 + read-write + + + ENUTMILEVEL2 + Enables UTMI+ Level 2 operation for the USB HS PHY + 14 + 1 + read-write + + + ENUTMILEVEL3 + Enables UTMI+ Level 3 operation for the USB HS PHY + 15 + 1 + read-write + + + AUTORESUME_EN + Enable the auto resume feature, when set, HW will use 32KHz clock to send Resume to respond to the device remote wakeup(for host mode only) + 18 + 1 + read-write + + + ENAUTOCLR_CLKGATE + Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended + 19 + 1 + read-write + + + ENAUTOCLR_PHY_PWD + Enables the feature to auto-clear the PWD register bits in PWD if there is wakeup event while USB is suspended + 20 + 1 + read-write + + + FSDLL_RST_EN + Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet. + 24 + 1 + read-write + + + OTG_ID_VALUE + Indicates the results of USB_ID pin while monitoring the cable plugged into the Micro- or Mini-AB receptacle + 27 + 1 + read-write + + + HOST_FORCE_LS_SE0 + Forces the next FS packet that is transmitted to have a EOP with low-speed timing + 28 + 1 + read-write + + + UTMI_SUSPENDM + Used by the PHY to indicate a powered-down state + 29 + 1 + read-write + + + CLKGATE + Gate UTMI Clocks + 30 + 1 + read-write + + + SFTRST + Writing a 1 to this bit will soft-reset the PWD, TX, RX, and CTRL registers + 31 + 1 + read-write + + + + + CTRL_SET + USB PHY General Control Register + 0x34 + 32 + read-write + 0xC0000000 + 0xFFFFFFFF + + + ENHOSTDISCONDETECT + For host mode, enables high-speed disconnect detector + 1 + 1 + read-write + + + HOSTDISCONDETECT_IRQ + Indicates that the device has disconnected in High-Speed mode + 3 + 1 + read-write + + + ENDEVPLUGINDET + Enables non-standard resistive plugged-in detection This bit field controls connection of nominal 200kohm resistors to both the USB_DP and USB_DM pins as one method of detecting when a USB cable is attached in device mode + 4 + 1 + read-write + + + value0 + Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) + 0 + + + value1 + Enables 200kohm pullup resistors on USB_DP and USB_DM pins + 0x1 + + + + + DEVPLUGIN_IRQ + Indicates that the device is connected + 12 + 1 + read-write + + + ENUTMILEVEL2 + Enables UTMI+ Level 2 operation for the USB HS PHY + 14 + 1 + read-write + + + ENUTMILEVEL3 + Enables UTMI+ Level 3 operation for the USB HS PHY + 15 + 1 + read-write + + + AUTORESUME_EN + Enable the auto resume feature, when set, HW will use 32KHz clock to send Resume to respond to the device remote wakeup(for host mode only) + 18 + 1 + read-write + + + ENAUTOCLR_CLKGATE + Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended + 19 + 1 + read-write + + + ENAUTOCLR_PHY_PWD + Enables the feature to auto-clear the PWD register bits in PWD if there is wakeup event while USB is suspended + 20 + 1 + read-write + + + FSDLL_RST_EN + Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet. + 24 + 1 + read-write + + + OTG_ID_VALUE + Indicates the results of USB_ID pin while monitoring the cable plugged into the Micro- or Mini-AB receptacle + 27 + 1 + read-write + + + HOST_FORCE_LS_SE0 + Forces the next FS packet that is transmitted to have a EOP with low-speed timing + 28 + 1 + read-write + + + UTMI_SUSPENDM + Used by the PHY to indicate a powered-down state + 29 + 1 + read-write + + + CLKGATE + Gate UTMI Clocks + 30 + 1 + read-write + + + SFTRST + Writing a 1 to this bit will soft-reset the PWD, TX, RX, and CTRL registers + 31 + 1 + read-write + + + + + CTRL_CLR + USB PHY General Control Register + 0x38 + 32 + read-write + 0xC0000000 + 0xFFFFFFFF + + + ENHOSTDISCONDETECT + For host mode, enables high-speed disconnect detector + 1 + 1 + read-write + + + HOSTDISCONDETECT_IRQ + Indicates that the device has disconnected in High-Speed mode + 3 + 1 + read-write + + + ENDEVPLUGINDET + Enables non-standard resistive plugged-in detection This bit field controls connection of nominal 200kohm resistors to both the USB_DP and USB_DM pins as one method of detecting when a USB cable is attached in device mode + 4 + 1 + read-write + + + value0 + Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) + 0 + + + value1 + Enables 200kohm pullup resistors on USB_DP and USB_DM pins + 0x1 + + + + + DEVPLUGIN_IRQ + Indicates that the device is connected + 12 + 1 + read-write + + + ENUTMILEVEL2 + Enables UTMI+ Level 2 operation for the USB HS PHY + 14 + 1 + read-write + + + ENUTMILEVEL3 + Enables UTMI+ Level 3 operation for the USB HS PHY + 15 + 1 + read-write + + + AUTORESUME_EN + Enable the auto resume feature, when set, HW will use 32KHz clock to send Resume to respond to the device remote wakeup(for host mode only) + 18 + 1 + read-write + + + ENAUTOCLR_CLKGATE + Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended + 19 + 1 + read-write + + + ENAUTOCLR_PHY_PWD + Enables the feature to auto-clear the PWD register bits in PWD if there is wakeup event while USB is suspended + 20 + 1 + read-write + + + FSDLL_RST_EN + Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet. + 24 + 1 + read-write + + + OTG_ID_VALUE + Indicates the results of USB_ID pin while monitoring the cable plugged into the Micro- or Mini-AB receptacle + 27 + 1 + read-write + + + HOST_FORCE_LS_SE0 + Forces the next FS packet that is transmitted to have a EOP with low-speed timing + 28 + 1 + read-write + + + UTMI_SUSPENDM + Used by the PHY to indicate a powered-down state + 29 + 1 + read-write + + + CLKGATE + Gate UTMI Clocks + 30 + 1 + read-write + + + SFTRST + Writing a 1 to this bit will soft-reset the PWD, TX, RX, and CTRL registers + 31 + 1 + read-write + + + + + CTRL_TOG + USB PHY General Control Register + 0x3C + 32 + read-write + 0xC0000000 + 0xFFFFFFFF + + + ENHOSTDISCONDETECT + For host mode, enables high-speed disconnect detector + 1 + 1 + read-write + + + HOSTDISCONDETECT_IRQ + Indicates that the device has disconnected in High-Speed mode + 3 + 1 + read-write + + + ENDEVPLUGINDET + Enables non-standard resistive plugged-in detection This bit field controls connection of nominal 200kohm resistors to both the USB_DP and USB_DM pins as one method of detecting when a USB cable is attached in device mode + 4 + 1 + read-write + + + value0 + Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) + 0 + + + value1 + Enables 200kohm pullup resistors on USB_DP and USB_DM pins + 0x1 + + + + + DEVPLUGIN_IRQ + Indicates that the device is connected + 12 + 1 + read-write + + + ENUTMILEVEL2 + Enables UTMI+ Level 2 operation for the USB HS PHY + 14 + 1 + read-write + + + ENUTMILEVEL3 + Enables UTMI+ Level 3 operation for the USB HS PHY + 15 + 1 + read-write + + + AUTORESUME_EN + Enable the auto resume feature, when set, HW will use 32KHz clock to send Resume to respond to the device remote wakeup(for host mode only) + 18 + 1 + read-write + + + ENAUTOCLR_CLKGATE + Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended + 19 + 1 + read-write + + + ENAUTOCLR_PHY_PWD + Enables the feature to auto-clear the PWD register bits in PWD if there is wakeup event while USB is suspended + 20 + 1 + read-write + + + FSDLL_RST_EN + Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet. + 24 + 1 + read-write + + + OTG_ID_VALUE + Indicates the results of USB_ID pin while monitoring the cable plugged into the Micro- or Mini-AB receptacle + 27 + 1 + read-write + + + HOST_FORCE_LS_SE0 + Forces the next FS packet that is transmitted to have a EOP with low-speed timing + 28 + 1 + read-write + + + UTMI_SUSPENDM + Used by the PHY to indicate a powered-down state + 29 + 1 + read-write + + + CLKGATE + Gate UTMI Clocks + 30 + 1 + read-write + + + SFTRST + Writing a 1 to this bit will soft-reset the PWD, TX, RX, and CTRL registers + 31 + 1 + read-write + + + + + STATUS + USB PHY Status Register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + HOSTDISCONDETECT_STATUS + Indicates at the local host (downstream) port that the remote device has disconnected while in High-Speed mode + 3 + 1 + read-write + + + value0 + USB cable disconnect has not been detected at the local host + 0 + + + value1 + USB cable disconnect has been detected at the local host + 0x1 + + + + + DEVPLUGIN_STATUS + Status indicator for non-standard resistive plugged-in detection Indicates that the device has been connected on the USB_DP and USB_DM lines using the nonstandard resistive plugged-in detection method controlled by CTRL[4] + 6 + 1 + read-write + + + value0 + No attachment to a USB host is detected + 0 + + + value1 + Cable attachment to a USB host is detected + 0x1 + + + + + OTGID_STATUS + Indicates the results of USB_ID pin on the USB cable plugged into the local Micro- or Mini-AB receptacle + 8 + 1 + read-write + + + RESUME_STATUS + Indicates that the host is sending a wake-up after Suspend and has triggered an interrupt. + 10 + 1 + read-write + + + + + DEBUG0 + USB PHY Debug Register 0 + 0x50 + 32 + read-write + 0x7F180000 + 0xFFFFFFFF + + + OTGIDPIOLOCK + Once OTG ID from STATUS_OTGID_STATUS is sampled, use this to hold the value + 0 + 1 + read-write + + + DEBUG_INTERFACE_HOLD + Use holding registers to assist in timing for external UTMI interface. + 1 + 1 + read-write + + + HSTPULLDOWN + This bit field selects whether to connect pulldown resistors on the USB_DP/USB_DM pins if the corresponding pulldown overdrive mode is enabled through DEBUG[5:4} Set bit 3 to value 1'b1 to connect the 15ohm pulldown on USB_DP line + 2 + 2 + read-write + + + ENHSTPULLDOWN + This bit field selects host pulldown overdrive mode + 4 + 2 + read-write + + + TX2RXCOUNT + Delay in between the end of transmit to the beginning of receive + 8 + 4 + read-write + + + ENTX2RXCOUNT + Set this bit to allow a countdown to transition in between TX and RX. + 12 + 1 + read-write + + + SQUELCHRESETCOUNT + Delay in between the detection of squelch to the reset of high-speed RX. + 16 + 5 + read-write + + + ENSQUELCHRESET + Set bit to allow squelch to reset high-speed receive. + 24 + 1 + read-write + + + SQUELCHRESETLENGTH + Duration of RESET in terms of the number of 480-MHz cycles. + 25 + 4 + read-write + + + HOST_RESUME_DEBUG + Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1. + 29 + 1 + read-write + + + CLKGATE + Gate Test Clocks + 30 + 1 + read-write + + + + + DEBUG0_SET + USB PHY Debug Register 0 + 0x54 + 32 + read-write + 0x7F180000 + 0xFFFFFFFF + + + OTGIDPIOLOCK + Once OTG ID from STATUS_OTGID_STATUS is sampled, use this to hold the value + 0 + 1 + read-write + + + DEBUG_INTERFACE_HOLD + Use holding registers to assist in timing for external UTMI interface. + 1 + 1 + read-write + + + HSTPULLDOWN + This bit field selects whether to connect pulldown resistors on the USB_DP/USB_DM pins if the corresponding pulldown overdrive mode is enabled through DEBUG[5:4} Set bit 3 to value 1'b1 to connect the 15ohm pulldown on USB_DP line + 2 + 2 + read-write + + + ENHSTPULLDOWN + This bit field selects host pulldown overdrive mode + 4 + 2 + read-write + + + TX2RXCOUNT + Delay in between the end of transmit to the beginning of receive + 8 + 4 + read-write + + + ENTX2RXCOUNT + Set this bit to allow a countdown to transition in between TX and RX. + 12 + 1 + read-write + + + SQUELCHRESETCOUNT + Delay in between the detection of squelch to the reset of high-speed RX. + 16 + 5 + read-write + + + ENSQUELCHRESET + Set bit to allow squelch to reset high-speed receive. + 24 + 1 + read-write + + + SQUELCHRESETLENGTH + Duration of RESET in terms of the number of 480-MHz cycles. + 25 + 4 + read-write + + + HOST_RESUME_DEBUG + Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1. + 29 + 1 + read-write + + + CLKGATE + Gate Test Clocks + 30 + 1 + read-write + + + + + DEBUG0_CLR + USB PHY Debug Register 0 + 0x58 + 32 + read-write + 0x7F180000 + 0xFFFFFFFF + + + OTGIDPIOLOCK + Once OTG ID from STATUS_OTGID_STATUS is sampled, use this to hold the value + 0 + 1 + read-write + + + DEBUG_INTERFACE_HOLD + Use holding registers to assist in timing for external UTMI interface. + 1 + 1 + read-write + + + HSTPULLDOWN + This bit field selects whether to connect pulldown resistors on the USB_DP/USB_DM pins if the corresponding pulldown overdrive mode is enabled through DEBUG[5:4} Set bit 3 to value 1'b1 to connect the 15ohm pulldown on USB_DP line + 2 + 2 + read-write + + + ENHSTPULLDOWN + This bit field selects host pulldown overdrive mode + 4 + 2 + read-write + + + TX2RXCOUNT + Delay in between the end of transmit to the beginning of receive + 8 + 4 + read-write + + + ENTX2RXCOUNT + Set this bit to allow a countdown to transition in between TX and RX. + 12 + 1 + read-write + + + SQUELCHRESETCOUNT + Delay in between the detection of squelch to the reset of high-speed RX. + 16 + 5 + read-write + + + ENSQUELCHRESET + Set bit to allow squelch to reset high-speed receive. + 24 + 1 + read-write + + + SQUELCHRESETLENGTH + Duration of RESET in terms of the number of 480-MHz cycles. + 25 + 4 + read-write + + + HOST_RESUME_DEBUG + Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1. + 29 + 1 + read-write + + + CLKGATE + Gate Test Clocks + 30 + 1 + read-write + + + + + DEBUG0_TOG + USB PHY Debug Register 0 + 0x5C + 32 + read-write + 0x7F180000 + 0xFFFFFFFF + + + OTGIDPIOLOCK + Once OTG ID from STATUS_OTGID_STATUS is sampled, use this to hold the value + 0 + 1 + read-write + + + DEBUG_INTERFACE_HOLD + Use holding registers to assist in timing for external UTMI interface. + 1 + 1 + read-write + + + HSTPULLDOWN + This bit field selects whether to connect pulldown resistors on the USB_DP/USB_DM pins if the corresponding pulldown overdrive mode is enabled through DEBUG[5:4} Set bit 3 to value 1'b1 to connect the 15ohm pulldown on USB_DP line + 2 + 2 + read-write + + + ENHSTPULLDOWN + This bit field selects host pulldown overdrive mode + 4 + 2 + read-write + + + TX2RXCOUNT + Delay in between the end of transmit to the beginning of receive + 8 + 4 + read-write + + + ENTX2RXCOUNT + Set this bit to allow a countdown to transition in between TX and RX. + 12 + 1 + read-write + + + SQUELCHRESETCOUNT + Delay in between the detection of squelch to the reset of high-speed RX. + 16 + 5 + read-write + + + ENSQUELCHRESET + Set bit to allow squelch to reset high-speed receive. + 24 + 1 + read-write + + + SQUELCHRESETLENGTH + Duration of RESET in terms of the number of 480-MHz cycles. + 25 + 4 + read-write + + + HOST_RESUME_DEBUG + Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1. + 29 + 1 + read-write + + + CLKGATE + Gate Test Clocks + 30 + 1 + read-write + + + + + DEBUG1 + UTMI Debug Status Register 1 + 0x70 + 32 + read-write + 0x1000 + 0xFFFFFFFF + + + ENTAILADJVD + Delay increment of the rise of squelch: + 13 + 2 + read-write + + + value0 + Delay is nominal + 0 + + + value1 + Delay is +20% + 0x1 + + + value2 + Delay is -20% + 0x2 + + + value3 + Delay is -40% + 0x3 + + + + + USB2_REFBIAS_VBGADJ + Adjustment bits on bandgap + 18 + 3 + read-write + + + USB2_REFBIAS_TST + Bias current control for usb2_phy + 21 + 2 + read-write + + + + + DEBUG1_SET + UTMI Debug Status Register 1 + 0x74 + 32 + read-write + 0x1000 + 0xFFFFFFFF + + + ENTAILADJVD + Delay increment of the rise of squelch: + 13 + 2 + read-write + + + value0 + Delay is nominal + 0 + + + value1 + Delay is +20% + 0x1 + + + value2 + Delay is -20% + 0x2 + + + value3 + Delay is -40% + 0x3 + + + + + USB2_REFBIAS_VBGADJ + Adjustment bits on bandgap + 18 + 3 + read-write + + + USB2_REFBIAS_TST + Bias current control for usb2_phy + 21 + 2 + read-write + + + + + DEBUG1_CLR + UTMI Debug Status Register 1 + 0x78 + 32 + read-write + 0x1000 + 0xFFFFFFFF + + + ENTAILADJVD + Delay increment of the rise of squelch: + 13 + 2 + read-write + + + value0 + Delay is nominal + 0 + + + value1 + Delay is +20% + 0x1 + + + value2 + Delay is -20% + 0x2 + + + value3 + Delay is -40% + 0x3 + + + + + USB2_REFBIAS_VBGADJ + Adjustment bits on bandgap + 18 + 3 + read-write + + + USB2_REFBIAS_TST + Bias current control for usb2_phy + 21 + 2 + read-write + + + + + DEBUG1_TOG + UTMI Debug Status Register 1 + 0x7C + 32 + read-write + 0x1000 + 0xFFFFFFFF + + + ENTAILADJVD + Delay increment of the rise of squelch: + 13 + 2 + read-write + + + value0 + Delay is nominal + 0 + + + value1 + Delay is +20% + 0x1 + + + value2 + Delay is -20% + 0x2 + + + value3 + Delay is -40% + 0x3 + + + + + USB2_REFBIAS_VBGADJ + Adjustment bits on bandgap + 18 + 3 + read-write + + + USB2_REFBIAS_TST + Bias current control for usb2_phy + 21 + 2 + read-write + + + + + VERSION + UTMI RTL Version + 0x80 + 32 + read-only + 0x5000000 + 0xFFFFFFFF + + + STEP + Fixed read-only value reflecting the stepping of the RTL version. + 0 + 16 + read-only + + + MINOR + Fixed read-only value reflecting the MINOR field of the RTL version + 16 + 8 + read-only + + + MAJOR + Fixed read-only value reflecting the MAJOR field of the RTL versio + 24 + 8 + read-only + + + + + PLL_SIC + USB PHY PLL Control/Status Register + 0xA0 + 32 + read-write + 0xD12000 + 0xFFFFFFFF + + + MISC2_CONTROL0 + Modifies the operation of the pll_sic_power_int signal + 5 + 1 + read-write + + + PLL_EN_USB_CLKS + Enables the USB clock from PLL to USB PHY + 6 + 1 + read-write + + + PLL_POWER + Power up the USB PLL + 12 + 1 + read-write + + + PLL_ENABLE + Enables the clock output from the USB PLL + 13 + 1 + read-write + + + PLL_BYPASS + Bypass the USB PLL. + 16 + 1 + read-write + + + REFBIAS_PWD_SEL + Reference bias power down select. + 19 + 1 + read-write + + + value0 + Selects PLL_POWER to control the reference bias + 0 + + + value1 + Selects REFBIAS_PWD to control the reference bias + 0x1 + + + + + REFBIAS_PWD + Power down the reference bias This bit is only used when REFBIAS_PWD_SEL is set to 1. + 20 + 1 + read-write + + + PLL_REG_ENABLE + This field controls the USB PLL regulator, set to enable the regulator + 21 + 1 + read-write + + + PLL_DIV_SEL + This field controls the USB PLL feedback loop divider + 22 + 3 + read-write + + + value0 + Divide by 13 + 0 + + + value1 + Divide by 15 + 0x1 + + + value2 + Divide by 16 + 0x2 + + + value3 + Divide by 20 + 0x3 + + + value4 + Divide by 22 + 0x4 + + + value5 + Divide by 25 + 0x5 + + + value6 + Divide by 30 + 0x6 + + + value7 + Divide by 240 + 0x7 + + + + + PLL_LOCK + USB PLL lock status indicator + 31 + 1 + read-write + + + value0 + PLL is not currently locked + 0 + + + value1 + PLL is currently locked + 0x1 + + + + + + + PLL_SIC_SET + USB PHY PLL Control/Status Register + 0xA4 + 32 + read-write + 0xD12000 + 0xFFFFFFFF + + + MISC2_CONTROL0 + Modifies the operation of the pll_sic_power_int signal + 5 + 1 + read-write + + + PLL_EN_USB_CLKS + Enables the USB clock from PLL to USB PHY + 6 + 1 + read-write + + + PLL_POWER + Power up the USB PLL + 12 + 1 + read-write + + + PLL_ENABLE + Enables the clock output from the USB PLL + 13 + 1 + read-write + + + PLL_BYPASS + Bypass the USB PLL. + 16 + 1 + read-write + + + REFBIAS_PWD_SEL + Reference bias power down select. + 19 + 1 + read-write + + + value0 + Selects PLL_POWER to control the reference bias + 0 + + + value1 + Selects REFBIAS_PWD to control the reference bias + 0x1 + + + + + REFBIAS_PWD + Power down the reference bias This bit is only used when REFBIAS_PWD_SEL is set to 1. + 20 + 1 + read-write + + + PLL_REG_ENABLE + This field controls the USB PLL regulator, set to enable the regulator + 21 + 1 + read-write + + + PLL_DIV_SEL + This field controls the USB PLL feedback loop divider + 22 + 3 + read-write + + + value0 + Divide by 13 + 0 + + + value1 + Divide by 15 + 0x1 + + + value2 + Divide by 16 + 0x2 + + + value3 + Divide by 20 + 0x3 + + + value4 + Divide by 22 + 0x4 + + + value5 + Divide by 25 + 0x5 + + + value6 + Divide by 30 + 0x6 + + + value7 + Divide by 240 + 0x7 + + + + + PLL_LOCK + USB PLL lock status indicator + 31 + 1 + read-write + + + value0 + PLL is not currently locked + 0 + + + value1 + PLL is currently locked + 0x1 + + + + + + + PLL_SIC_CLR + USB PHY PLL Control/Status Register + 0xA8 + 32 + read-write + 0xD12000 + 0xFFFFFFFF + + + MISC2_CONTROL0 + Modifies the operation of the pll_sic_power_int signal + 5 + 1 + read-write + + + PLL_EN_USB_CLKS + Enables the USB clock from PLL to USB PHY + 6 + 1 + read-write + + + PLL_POWER + Power up the USB PLL + 12 + 1 + read-write + + + PLL_ENABLE + Enables the clock output from the USB PLL + 13 + 1 + read-write + + + PLL_BYPASS + Bypass the USB PLL. + 16 + 1 + read-write + + + REFBIAS_PWD_SEL + Reference bias power down select. + 19 + 1 + read-write + + + value0 + Selects PLL_POWER to control the reference bias + 0 + + + value1 + Selects REFBIAS_PWD to control the reference bias + 0x1 + + + + + REFBIAS_PWD + Power down the reference bias This bit is only used when REFBIAS_PWD_SEL is set to 1. + 20 + 1 + read-write + + + PLL_REG_ENABLE + This field controls the USB PLL regulator, set to enable the regulator + 21 + 1 + read-write + + + PLL_DIV_SEL + This field controls the USB PLL feedback loop divider + 22 + 3 + read-write + + + value0 + Divide by 13 + 0 + + + value1 + Divide by 15 + 0x1 + + + value2 + Divide by 16 + 0x2 + + + value3 + Divide by 20 + 0x3 + + + value4 + Divide by 22 + 0x4 + + + value5 + Divide by 25 + 0x5 + + + value6 + Divide by 30 + 0x6 + + + value7 + Divide by 240 + 0x7 + + + + + PLL_LOCK + USB PLL lock status indicator + 31 + 1 + read-write + + + value0 + PLL is not currently locked + 0 + + + value1 + PLL is currently locked + 0x1 + + + + + + + PLL_SIC_TOG + USB PHY PLL Control/Status Register + 0xAC + 32 + read-write + 0xD12000 + 0xFFFFFFFF + + + MISC2_CONTROL0 + Modifies the operation of the pll_sic_power_int signal + 5 + 1 + read-write + + + PLL_EN_USB_CLKS + Enables the USB clock from PLL to USB PHY + 6 + 1 + read-write + + + PLL_POWER + Power up the USB PLL + 12 + 1 + read-write + + + PLL_ENABLE + Enables the clock output from the USB PLL + 13 + 1 + read-write + + + PLL_BYPASS + Bypass the USB PLL. + 16 + 1 + read-write + + + REFBIAS_PWD_SEL + Reference bias power down select. + 19 + 1 + read-write + + + value0 + Selects PLL_POWER to control the reference bias + 0 + + + value1 + Selects REFBIAS_PWD to control the reference bias + 0x1 + + + + + REFBIAS_PWD + Power down the reference bias This bit is only used when REFBIAS_PWD_SEL is set to 1. + 20 + 1 + read-write + + + PLL_REG_ENABLE + This field controls the USB PLL regulator, set to enable the regulator + 21 + 1 + read-write + + + PLL_DIV_SEL + This field controls the USB PLL feedback loop divider + 22 + 3 + read-write + + + value0 + Divide by 13 + 0 + + + value1 + Divide by 15 + 0x1 + + + value2 + Divide by 16 + 0x2 + + + value3 + Divide by 20 + 0x3 + + + value4 + Divide by 22 + 0x4 + + + value5 + Divide by 25 + 0x5 + + + value6 + Divide by 30 + 0x6 + + + value7 + Divide by 240 + 0x7 + + + + + PLL_LOCK + USB PLL lock status indicator + 31 + 1 + read-write + + + value0 + PLL is not currently locked + 0 + + + value1 + PLL is currently locked + 0x1 + + + + + + + USB1_VBUS_DETECT + USB PHY VBUS Detect Control Register + 0xC0 + 32 + read-write + 0x700004 + 0xFFFFFFFF + + + VBUSVALID_THRESH + Sets the threshold for the VBUSVALID comparator + 0 + 3 + read-write + + + value0 + 4.0V + 0 + + + value1 + 4.1V + 0x1 + + + value2 + 4.2V + 0x2 + + + value3 + 4.3V + 0x3 + + + value4 + 4.4V(Default) + 0x4 + + + value5 + 4.5V + 0x5 + + + value6 + 4.6V + 0x6 + + + value7 + 4.7V + 0x7 + + + + + VBUS_OVERRIDE_EN + VBUS detect signal override enable + 3 + 1 + read-write + + + value0 + Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) + 0 + + + value1 + Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND + 0x1 + + + + + SESSEND_OVERRIDE + Override value for SESSEND The bit field provides the value for USB1_VBUS_DET_STAT[0] if USB_VBUS_DETECT[3] is set to value 1'b1 + 4 + 1 + read-write + + + BVALID_OVERRIDE + Override value for B-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[1] if USB_VBUS_DETECT[3] is set to value 1'b1 + 5 + 1 + read-write + + + AVALID_OVERRIDE + Override value for A-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[2] if USB_VBUS_DETECT[3] is set to value 1'b1 + 6 + 1 + read-write + + + VBUSVALID_OVERRIDE + Override value for VBUS_VALID signal sent to USB controller The bit field provides the value for VBUS_VALID reported to the USB controller if the value of USB1_VBUS_DETECT[3] is set to 1'b1 + 7 + 1 + read-write + + + VBUSVALID_SEL + Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fields that selects the source of the VBUS_VALID signal reported to the USB controller + 8 + 1 + read-write + + + value0 + Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) + 0 + + + value1 + Use the VBUS_VALID_3V detector results for signal reported to the USB controller + 0x1 + + + + + VBUS_SOURCE_SEL + Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fields that selects the source of the VBUS_VALID signal reported to the USB controller + 9 + 2 + read-write + + + value0 + Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) + 0 + + + value1 + Use the Session Valid comparator results for signal reported to the USB controller + 0x1 + + + value2 + Use the Session Valid comparator results for signal reported to the USB controller + 0x2 + + + + + VBUSVALID_TO_SESSVALID + Selects the comparator used for VBUS_VALID This bit field controls the comparator used to report the VBUS_VALID results in USB1_VBUS_DETECT[3] between the VBUS_VALID comparator and the Session Valid comparator + 18 + 1 + read-write + + + value0 + Use the VBUS_VALID comparator for VBUS_VALID results + 0 + + + value1 + Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. + 0x1 + + + + + PWRUP_CMPS + Enables the VBUS_VALID comparator Powers up the comparator used for the VBUS_VALID detector + 20 + 1 + read-write + + + value0 + Powers down the VBUS_VALID comparator + 0 + + + value1 + Enables the VBUS_VALID comparator (default) + 0x1 + + + + + DISCHARGE_VBUS + Controls VBUS discharge resistor This bit field controls a nominal 22kohm resistor between the USB1_VBUS pin and ground + 26 + 1 + read-write + + + value0 + VBUS discharge resistor is disabled (Default) + 0 + + + value1 + VBUS discharge resistor is enabled + 0x1 + + + + + EN_CHARGER_RESISTOR + Enables resistors used for an older method of resistive battery charger detection + 31 + 1 + read-write + + + value0 + Disable resistive charger detection resistors on USB_DP and USB_DP + 0 + + + value1 + Enable resistive charger detection resistors on USB_DP and USB_DP + 0x1 + + + + + + + USB1_VBUS_DETECT_SET + USB PHY VBUS Detect Control Register + 0xC4 + 32 + read-write + 0x700004 + 0xFFFFFFFF + + + VBUSVALID_THRESH + Sets the threshold for the VBUSVALID comparator + 0 + 3 + read-write + + + value0 + 4.0V + 0 + + + value1 + 4.1V + 0x1 + + + value2 + 4.2V + 0x2 + + + value3 + 4.3V + 0x3 + + + value4 + 4.4V(Default) + 0x4 + + + value5 + 4.5V + 0x5 + + + value6 + 4.6V + 0x6 + + + value7 + 4.7V + 0x7 + + + + + VBUS_OVERRIDE_EN + VBUS detect signal override enable + 3 + 1 + read-write + + + value0 + Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) + 0 + + + value1 + Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND + 0x1 + + + + + SESSEND_OVERRIDE + Override value for SESSEND The bit field provides the value for USB1_VBUS_DET_STAT[0] if USB_VBUS_DETECT[3] is set to value 1'b1 + 4 + 1 + read-write + + + BVALID_OVERRIDE + Override value for B-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[1] if USB_VBUS_DETECT[3] is set to value 1'b1 + 5 + 1 + read-write + + + AVALID_OVERRIDE + Override value for A-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[2] if USB_VBUS_DETECT[3] is set to value 1'b1 + 6 + 1 + read-write + + + VBUSVALID_OVERRIDE + Override value for VBUS_VALID signal sent to USB controller The bit field provides the value for VBUS_VALID reported to the USB controller if the value of USB1_VBUS_DETECT[3] is set to 1'b1 + 7 + 1 + read-write + + + VBUSVALID_SEL + Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fields that selects the source of the VBUS_VALID signal reported to the USB controller + 8 + 1 + read-write + + + value0 + Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) + 0 + + + value1 + Use the VBUS_VALID_3V detector results for signal reported to the USB controller + 0x1 + + + + + VBUS_SOURCE_SEL + Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fields that selects the source of the VBUS_VALID signal reported to the USB controller + 9 + 2 + read-write + + + value0 + Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) + 0 + + + value1 + Use the Session Valid comparator results for signal reported to the USB controller + 0x1 + + + value2 + Use the Session Valid comparator results for signal reported to the USB controller + 0x2 + + + + + VBUSVALID_TO_SESSVALID + Selects the comparator used for VBUS_VALID This bit field controls the comparator used to report the VBUS_VALID results in USB1_VBUS_DETECT[3] between the VBUS_VALID comparator and the Session Valid comparator + 18 + 1 + read-write + + + value0 + Use the VBUS_VALID comparator for VBUS_VALID results + 0 + + + value1 + Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. + 0x1 + + + + + PWRUP_CMPS + Enables the VBUS_VALID comparator Powers up the comparator used for the VBUS_VALID detector + 20 + 1 + read-write + + + value0 + Powers down the VBUS_VALID comparator + 0 + + + value1 + Enables the VBUS_VALID comparator (default) + 0x1 + + + + + DISCHARGE_VBUS + Controls VBUS discharge resistor This bit field controls a nominal 22kohm resistor between the USB1_VBUS pin and ground + 26 + 1 + read-write + + + value0 + VBUS discharge resistor is disabled (Default) + 0 + + + value1 + VBUS discharge resistor is enabled + 0x1 + + + + + EN_CHARGER_RESISTOR + Enables resistors used for an older method of resistive battery charger detection + 31 + 1 + read-write + + + value0 + Disable resistive charger detection resistors on USB_DP and USB_DP + 0 + + + value1 + Enable resistive charger detection resistors on USB_DP and USB_DP + 0x1 + + + + + + + USB1_VBUS_DETECT_CLR + USB PHY VBUS Detect Control Register + 0xC8 + 32 + read-write + 0x700004 + 0xFFFFFFFF + + + VBUSVALID_THRESH + Sets the threshold for the VBUSVALID comparator + 0 + 3 + read-write + + + value0 + 4.0V + 0 + + + value1 + 4.1V + 0x1 + + + value2 + 4.2V + 0x2 + + + value3 + 4.3V + 0x3 + + + value4 + 4.4V(Default) + 0x4 + + + value5 + 4.5V + 0x5 + + + value6 + 4.6V + 0x6 + + + value7 + 4.7V + 0x7 + + + + + VBUS_OVERRIDE_EN + VBUS detect signal override enable + 3 + 1 + read-write + + + value0 + Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) + 0 + + + value1 + Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND + 0x1 + + + + + SESSEND_OVERRIDE + Override value for SESSEND The bit field provides the value for USB1_VBUS_DET_STAT[0] if USB_VBUS_DETECT[3] is set to value 1'b1 + 4 + 1 + read-write + + + BVALID_OVERRIDE + Override value for B-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[1] if USB_VBUS_DETECT[3] is set to value 1'b1 + 5 + 1 + read-write + + + AVALID_OVERRIDE + Override value for A-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[2] if USB_VBUS_DETECT[3] is set to value 1'b1 + 6 + 1 + read-write + + + VBUSVALID_OVERRIDE + Override value for VBUS_VALID signal sent to USB controller The bit field provides the value for VBUS_VALID reported to the USB controller if the value of USB1_VBUS_DETECT[3] is set to 1'b1 + 7 + 1 + read-write + + + VBUSVALID_SEL + Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fields that selects the source of the VBUS_VALID signal reported to the USB controller + 8 + 1 + read-write + + + value0 + Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) + 0 + + + value1 + Use the VBUS_VALID_3V detector results for signal reported to the USB controller + 0x1 + + + + + VBUS_SOURCE_SEL + Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fields that selects the source of the VBUS_VALID signal reported to the USB controller + 9 + 2 + read-write + + + value0 + Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) + 0 + + + value1 + Use the Session Valid comparator results for signal reported to the USB controller + 0x1 + + + value2 + Use the Session Valid comparator results for signal reported to the USB controller + 0x2 + + + + + VBUSVALID_TO_SESSVALID + Selects the comparator used for VBUS_VALID This bit field controls the comparator used to report the VBUS_VALID results in USB1_VBUS_DETECT[3] between the VBUS_VALID comparator and the Session Valid comparator + 18 + 1 + read-write + + + value0 + Use the VBUS_VALID comparator for VBUS_VALID results + 0 + + + value1 + Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. + 0x1 + + + + + PWRUP_CMPS + Enables the VBUS_VALID comparator Powers up the comparator used for the VBUS_VALID detector + 20 + 1 + read-write + + + value0 + Powers down the VBUS_VALID comparator + 0 + + + value1 + Enables the VBUS_VALID comparator (default) + 0x1 + + + + + DISCHARGE_VBUS + Controls VBUS discharge resistor This bit field controls a nominal 22kohm resistor between the USB1_VBUS pin and ground + 26 + 1 + read-write + + + value0 + VBUS discharge resistor is disabled (Default) + 0 + + + value1 + VBUS discharge resistor is enabled + 0x1 + + + + + EN_CHARGER_RESISTOR + Enables resistors used for an older method of resistive battery charger detection + 31 + 1 + read-write + + + value0 + Disable resistive charger detection resistors on USB_DP and USB_DP + 0 + + + value1 + Enable resistive charger detection resistors on USB_DP and USB_DP + 0x1 + + + + + + + USB1_VBUS_DETECT_TOG + USB PHY VBUS Detect Control Register + 0xCC + 32 + read-write + 0x700004 + 0xFFFFFFFF + + + VBUSVALID_THRESH + Sets the threshold for the VBUSVALID comparator + 0 + 3 + read-write + + + value0 + 4.0V + 0 + + + value1 + 4.1V + 0x1 + + + value2 + 4.2V + 0x2 + + + value3 + 4.3V + 0x3 + + + value4 + 4.4V(Default) + 0x4 + + + value5 + 4.5V + 0x5 + + + value6 + 4.6V + 0x6 + + + value7 + 4.7V + 0x7 + + + + + VBUS_OVERRIDE_EN + VBUS detect signal override enable + 3 + 1 + read-write + + + value0 + Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) + 0 + + + value1 + Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND + 0x1 + + + + + SESSEND_OVERRIDE + Override value for SESSEND The bit field provides the value for USB1_VBUS_DET_STAT[0] if USB_VBUS_DETECT[3] is set to value 1'b1 + 4 + 1 + read-write + + + BVALID_OVERRIDE + Override value for B-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[1] if USB_VBUS_DETECT[3] is set to value 1'b1 + 5 + 1 + read-write + + + AVALID_OVERRIDE + Override value for A-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[2] if USB_VBUS_DETECT[3] is set to value 1'b1 + 6 + 1 + read-write + + + VBUSVALID_OVERRIDE + Override value for VBUS_VALID signal sent to USB controller The bit field provides the value for VBUS_VALID reported to the USB controller if the value of USB1_VBUS_DETECT[3] is set to 1'b1 + 7 + 1 + read-write + + + VBUSVALID_SEL + Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fields that selects the source of the VBUS_VALID signal reported to the USB controller + 8 + 1 + read-write + + + value0 + Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) + 0 + + + value1 + Use the VBUS_VALID_3V detector results for signal reported to the USB controller + 0x1 + + + + + VBUS_SOURCE_SEL + Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fields that selects the source of the VBUS_VALID signal reported to the USB controller + 9 + 2 + read-write + + + value0 + Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) + 0 + + + value1 + Use the Session Valid comparator results for signal reported to the USB controller + 0x1 + + + value2 + Use the Session Valid comparator results for signal reported to the USB controller + 0x2 + + + + + VBUSVALID_TO_SESSVALID + Selects the comparator used for VBUS_VALID This bit field controls the comparator used to report the VBUS_VALID results in USB1_VBUS_DETECT[3] between the VBUS_VALID comparator and the Session Valid comparator + 18 + 1 + read-write + + + value0 + Use the VBUS_VALID comparator for VBUS_VALID results + 0 + + + value1 + Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. + 0x1 + + + + + PWRUP_CMPS + Enables the VBUS_VALID comparator Powers up the comparator used for the VBUS_VALID detector + 20 + 1 + read-write + + + value0 + Powers down the VBUS_VALID comparator + 0 + + + value1 + Enables the VBUS_VALID comparator (default) + 0x1 + + + + + DISCHARGE_VBUS + Controls VBUS discharge resistor This bit field controls a nominal 22kohm resistor between the USB1_VBUS pin and ground + 26 + 1 + read-write + + + value0 + VBUS discharge resistor is disabled (Default) + 0 + + + value1 + VBUS discharge resistor is enabled + 0x1 + + + + + EN_CHARGER_RESISTOR + Enables resistors used for an older method of resistive battery charger detection + 31 + 1 + read-write + + + value0 + Disable resistive charger detection resistors on USB_DP and USB_DP + 0 + + + value1 + Enable resistive charger detection resistors on USB_DP and USB_DP + 0x1 + + + + + + + USB1_VBUS_DET_STAT + USB PHY VBUS Detector Status Register + 0xD0 + 32 + read-only + 0 + 0xFFFFFFFF + + + SESSEND + Session End indicator Session End status, value inverted from Session Valid comparator + 0 + 1 + read-only + + + value0 + The VBUS voltage is above the Session Valid threshold + 0 + + + value1 + The VBUS voltage is below the Session Valid threshold + 0x1 + + + + + BVALID + B-Device Session Valid status B-Device Session Valid status, determined by the Session Valid comparator + 1 + 1 + read-only + + + value0 + The VBUS voltage is below the Session Valid threshold + 0 + + + value1 + The VBUS voltage is above the Session Valid threshold + 0x1 + + + + + AVALID + A-Device Session Valid status A-Device Session Valid status, determined by the Session Valid comparator + 2 + 1 + read-only + + + value0 + The VBUS voltage is below the Session Valid threshold + 0 + + + value1 + The VBUS voltage is above the Session Valid threshold + 0x1 + + + + + VBUS_VALID + VBUS voltage status This bit field shows the result of VBUS_VALID detection for the USB1_VBUS pin + 3 + 1 + read-only + + + value0 + VBUS is below the comparator threshold + 0 + + + value1 + VBUS is above the comparator threshold + 0x1 + + + + + VBUS_VALID_3V + VBUS_VALID_3V detector status The VBUS_VALID_3V detector has a lower threshold for the voltage on the USB1_VBUS pin than either the Session Valid or VBUS_VALID comparators + 4 + 1 + read-only + + + value0 + VBUS voltage is below VBUS_VALID_3V threshold + 0 + + + value1 + VBUS voltage is above VBUS_VALID_3V threshold + 0x1 + + + + + + + USB1_CHRG_DETECT + USB PHY Charger Detect Control Register + 0xE0 + 32 + read-write + 0x80180000 + 0xFFFFFFFF + + + PULLUP_DP + This bit is used to pull up DP, for digital charge detect. + 2 + 1 + read-write + + + BGR_IBIAS + USB charge detector bias current reference This bit determines the reference for the bias current of the USB charge detector + 23 + 1 + read-write + + + value0 + Bias current is derived from the USB PHY internal current generator. + 0 + + + value1 + Bias current is derived from the reference generator of the bandgap. + 0x1 + + + + + + + USB1_CHRG_DETECT_SET + USB PHY Charger Detect Control Register + 0xE4 + 32 + read-write + 0x80180000 + 0xFFFFFFFF + + + PULLUP_DP + This bit is used to pull up DP, for digital charge detect. + 2 + 1 + read-write + + + BGR_IBIAS + USB charge detector bias current reference This bit determines the reference for the bias current of the USB charge detector + 23 + 1 + read-write + + + value0 + Bias current is derived from the USB PHY internal current generator. + 0 + + + value1 + Bias current is derived from the reference generator of the bandgap. + 0x1 + + + + + + + USB1_CHRG_DETECT_CLR + USB PHY Charger Detect Control Register + 0xE8 + 32 + read-write + 0x80180000 + 0xFFFFFFFF + + + PULLUP_DP + This bit is used to pull up DP, for digital charge detect. + 2 + 1 + read-write + + + BGR_IBIAS + USB charge detector bias current reference This bit determines the reference for the bias current of the USB charge detector + 23 + 1 + read-write + + + value0 + Bias current is derived from the USB PHY internal current generator. + 0 + + + value1 + Bias current is derived from the reference generator of the bandgap. + 0x1 + + + + + + + USB1_CHRG_DETECT_TOG + USB PHY Charger Detect Control Register + 0xEC + 32 + read-write + 0x80180000 + 0xFFFFFFFF + + + PULLUP_DP + This bit is used to pull up DP, for digital charge detect. + 2 + 1 + read-write + + + BGR_IBIAS + USB charge detector bias current reference This bit determines the reference for the bias current of the USB charge detector + 23 + 1 + read-write + + + value0 + Bias current is derived from the USB PHY internal current generator. + 0 + + + value1 + Bias current is derived from the reference generator of the bandgap. + 0x1 + + + + + + + USB1_CHRG_DET_STAT + USB PHY Charger Detect Status Register + 0xF0 + 32 + read-only + 0 + 0xFFFFFFFF + + + PLUG_CONTACT + Battery Charging Data Contact Detection phase output During the Data Contact Detection phase per the USB Battery Charging Specification Revision 1 + 0 + 1 + read-only + + + value0 + No USB cable attachment has been detected + 0 + + + value1 + A USB cable attachment between the device and host has been detected + 0x1 + + + + + CHRG_DETECTED + Battery Charging Primary Detection phase output During the USB Battery Charging Primary Detection phase using the USBHSDCD module, this bit field indicates whether a Standard Downstream Port or Charging Port was detected + 1 + 1 + read-only + + + value0 + Standard Downstream Port (SDP) has been detected + 0 + + + value1 + Charging Port has been detected + 0x1 + + + + + DM_STATE + Single ended receiver output for the USB_DM pin, from charger detection circuits. + 2 + 1 + read-only + + + value0 + USB_DM pin voltage is < 0.8V + 0 + + + value1 + USB_DM pin voltage is > 2.0V + 0x1 + + + + + DP_STATE + Single ended receiver output for the USB_DP pin, from charger detection circuits. + 3 + 1 + read-only + + + value0 + USB_DP pin voltage is < 0.8V + 0 + + + value1 + USB_DP pin voltage is > 2.0V + 0x1 + + + + + SECDET_DCP + Battery Charging Secondary Detection phase output During the USB Battery Charging Secondary Detection phase using the USBHSDCD module, this bit field indicates which kind of Charging Port was detected + 4 + 1 + read-only + + + value0 + Charging Downstream Port (CDP) has been detected + 0 + + + value1 + Downstream Charging Port (DCP) has been detected + 0x1 + + + + + + + ANACTRL + USB PHY Analog Control Register + 0x100 + 32 + read-write + 0xA000402 + 0xFFFFFFFF + + + DEV_PULLDOWN + Setting this field to 1'b1 will enable the 15kohm pulldown resistors on both USB_DP and USB_DM pins + 10 + 1 + read-write + + + value0 + The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. + 0 + + + value1 + The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. + 0x1 + + + + + + + ANACTRL_SET + USB PHY Analog Control Register + 0x104 + 32 + read-write + 0xA000402 + 0xFFFFFFFF + + + DEV_PULLDOWN + Setting this field to 1'b1 will enable the 15kohm pulldown resistors on both USB_DP and USB_DM pins + 10 + 1 + read-write + + + value0 + The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. + 0 + + + value1 + The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. + 0x1 + + + + + + + ANACTRL_CLR + USB PHY Analog Control Register + 0x108 + 32 + read-write + 0xA000402 + 0xFFFFFFFF + + + DEV_PULLDOWN + Setting this field to 1'b1 will enable the 15kohm pulldown resistors on both USB_DP and USB_DM pins + 10 + 1 + read-write + + + value0 + The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. + 0 + + + value1 + The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. + 0x1 + + + + + + + ANACTRL_TOG + USB PHY Analog Control Register + 0x10C + 32 + read-write + 0xA000402 + 0xFFFFFFFF + + + DEV_PULLDOWN + Setting this field to 1'b1 will enable the 15kohm pulldown resistors on both USB_DP and USB_DM pins + 10 + 1 + read-write + + + value0 + The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. + 0 + + + value1 + The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. + 0x1 + + + + + + + + + RNG + RNG + RNG + 0x4003A000 + + 0 + 0x1000 + registers + + + + RANDOM_NUMBER + This register contains a random 32 bit number which is computed on demand, at each time it is read + 0 + 32 + read-only + 0 + 0xFFFFFFFF + + + RANDOM_NUMBER + This register contains a random 32 bit number which is computed on demand, at each time it is read. + 0 + 32 + read-only + + + + + ENCRYPTED_NUMBER + This register contains a random 32 bit number which is pre-computed + 0x4 + 32 + read-only + 0 + 0xFFFFFFFF + + + ENCRYPTED_NUMBER + This register contains a random 32 bit number which is pre-computed. + 0 + 32 + read-only + + + + + COUNTER_VAL + no description available + 0x8 + 32 + read-write + 0 + 0x1FFF + + + CLK_RATIO + Gives the ratio between the internal clocks frequencies and the register clock frequency for evaluation and certification purposes. + 0 + 8 + read-only + + + REFRESH_CNT + Incremented (till max possible value) each time COUNTER was updated since last reading to any *_NUMBER. + 8 + 5 + read-only + + + + + COUNTER_CFG + no description available + 0xC + 32 + read-write + 0 + 0x3FF + + + MODE + 00: disabled 01: update once. + 0 + 2 + read-write + + + CLOCK_SEL + Selects the internal clock on which to compute statistics. + 2 + 3 + read-write + + + SHIFT4X + To be used to add precision to clock_ratio and determine 'entropy refill'. + 5 + 3 + read-write + + + DIS_ENH_ENTR_REFILL + Disable 'enhanced entropy refill' feature, which is enabled by default when 'mode' > 00. + 8 + 1 + read-write + + + FORCE_ENTR_SPREADING + Forces entropy spreading (interactions between RNGs) even when 'clock_sel'>0. + 9 + 1 + read-write + + + + + ONLINE_TEST_CFG + no description available + 0x10 + 32 + read-write + 0 + 0x7 + + + ACTIVATE + 0: disabled 1: activated Update rythm for VAL depends on COUNTER_CFG if data_sel is set to COUNTER. + 0 + 1 + read-write + + + DATA_SEL + Selects source on which to apply online test: 00: LSB of COUNTER: raw data from one or all sources of entropy 01: MSB of COUNTER: raw data from one or all sources of entropy 10: RANDOM_NUMBER 11: ENCRYPTED_NUMBER 'activate' should be set to 'disabled' before changing this field. + 1 + 2 + read-write + + + + + ONLINE_TEST_VAL + no description available + 0x14 + 32 + read-write + 0 + 0xFFF + + + LIVE_CHI_SQUARED + This value is updated as described in field 'activate'. + 0 + 4 + read-only + + + MIN_CHI_SQUARED + This field is reset when 'activate'==0. + 4 + 4 + read-only + + + MAX_CHI_SQUARED + This field is reset when 'activate'==0. + 8 + 4 + read-only + + + + + MISC_CFG + no description available + 0x18 + 32 + read-write + 0 + 0x3 + + + AES_RESEED + If set, ENCRYPTED_NUMBER generation becomes predictable, provided all secrets and current internal state are known: independant from entropy source. + 0 + 1 + read-write + + + AES_DT_CFG + Set this bit to re-seed AES. + 1 + 1 + read-write + + + + + POWERDOWN + Powerdown mode (standard but certainly useless here) + 0xFF4 + 32 + read-write + 0 + 0x80000003 + + + SOFT_RESET + Request softreset that will go low automaticaly after acknowledge from CORE. + 0 + 1 + read-write + + + FORCE_SOFT_RESET + When used with softreset it forces CORE_RESETN to low on acknowledge from CORE. + 1 + 1 + read-write + + + POWERDOWN + When set all accesses to standard registers are blocked. + 31 + 1 + read-write + + + + + MODULEID + IP identifier + 0xFFC + 32 + read-only + 0xA0B83200 + 0xFFFFFFFF + + + APERTURE + Aperture i. + 0 + 8 + read-only + + + MIN_REV + Minor revision i. + 8 + 4 + read-only + + + MAJ_REV + Major revision i. + 12 + 4 + read-only + + + ID + Identifier. + 16 + 16 + read-only + + + + + + + PUF + PUFCTRL + PUF + 0x4003B000 + + 0 + 0x260 + registers + + + PUF + 56 + + + + CTRL + PUF Control register + 0 + 32 + read-write + 0 + 0x5F + + + zeroize + Begin Zeroize operation for PUF and go to Error state + 0 + 1 + read-write + + + enroll + Begin Enroll operation + 1 + 1 + read-write + + + start + Begin Start operation + 2 + 1 + read-write + + + GENERATEKEY + Begin Set Intrinsic Key operation + 3 + 1 + read-write + + + SETKEY + Begin Set User Key operation + 4 + 1 + read-write + + + GETKEY + Begin Get Key operation + 6 + 1 + read-write + + + + + KEYINDEX + PUF Key Index register + 0x4 + 32 + read-write + 0 + 0xF + + + KEYIDX + Key index for Set Key operations + 0 + 4 + read-write + + + + + KEYSIZE + PUF Key Size register + 0x8 + 32 + read-write + 0 + 0x3F + + + KEYSIZE + Key size for Set Key operations + 0 + 6 + read-write + + + + + STAT + PUF Status register + 0x20 + 32 + read-write + 0x1 + 0xF7 + + + busy + Indicates that operation is in progress + 0 + 1 + read-only + + + SUCCESS + Last operation was successful + 1 + 1 + read-only + + + error + Quiddikey is in the Error state and no operations can be performed + 2 + 1 + read-only + + + KEYINREQ + Request for next part of key + 4 + 1 + read-only + + + KEYOUTAVAIL + Next part of key is available + 5 + 1 + read-only + + + CODEINREQ + Request for next part of AC/KC + 6 + 1 + read-only + + + CODEOUTAVAIL + Next part of AC/KC is available + 7 + 1 + read-only + + + + + ALLOW + PUF Allow register + 0x28 + 32 + read-write + 0 + 0x8F + + + ALLOWENROLL + Enroll operation is allowed + 0 + 1 + read-only + + + ALLOWSTART + Start operation is allowed + 1 + 1 + read-only + + + ALLOWSETKEY + Set Key operations are allowed + 2 + 1 + read-only + + + ALLOWGETKEY + Get Key operation is allowed + 3 + 1 + read-only + + + + + KEYINPUT + PUF Key Input register + 0x40 + 32 + write-only + 0 + 0xFFFFFFFF + + + KEYIN + Key input data + 0 + 32 + write-only + + + + + CODEINPUT + PUF Code Input register + 0x44 + 32 + write-only + 0 + 0xFFFFFFFF + + + CODEIN + AC/KC input data + 0 + 32 + write-only + + + + + CODEOUTPUT + PUF Code Output register + 0x48 + 32 + read-only + 0 + 0xFFFFFFFF + + + CODEOUT + AC/KC output data + 0 + 32 + read-only + + + + + KEYOUTINDEX + PUF Key Output Index register + 0x60 + 32 + read-write + 0 + 0xF + + + KEYOUTIDX + Key index for the key that is currently output via the Key Output register + 0 + 4 + read-only + + + + + KEYOUTPUT + PUF Key Output register + 0x64 + 32 + read-only + 0 + 0xFFFFFFFF + + + KEYOUT + Key output data + 0 + 32 + read-only + + + + + IFSTAT + PUF Interface Status and clear register + 0xDC + 32 + read-write + 0 + 0x1 + + + ERROR + Indicates that an APB error has occurred,Writing logic1 clears the if_error bit + 0 + 1 + read-write + + + + + VERSION + PUF version register. + 0xFC + 32 + read-only + 0 + 0xFFFFFFFF + + + KEYOUT + Version of the PUF module. + 0 + 32 + read-only + + + + + INTEN + PUF Interrupt Enable + 0x100 + 32 + read-write + 0 + 0xF7 + + + READYEN + Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) + 0 + 1 + read-write + + + SUCCESEN + Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) + 1 + 1 + read-write + + + ERROREN + Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) + 2 + 1 + read-write + + + KEYINREQEN + Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) + 4 + 1 + read-write + + + KEYOUTAVAILEN + Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) + 5 + 1 + read-write + + + CODEINREQEN + Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) + 6 + 1 + read-write + + + CODEOUTAVAILEN + Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) + 7 + 1 + read-write + + + + + INTSTAT + PUF interrupt status + 0x104 + 32 + read-write + 0 + 0xF7 + + + READY + Triggers on falling edge of busy, write 1 to clear + 0 + 1 + read-write + + + SUCCESS + Level sensitive interrupt, cleared when interrupt source clears + 1 + 1 + read-write + + + ERROR + Level sensitive interrupt, cleared when interrupt source clears + 2 + 1 + read-write + + + KEYINREQ + Level sensitive interrupt, cleared when interrupt source clears + 4 + 1 + read-write + + + KEYOUTAVAIL + Level sensitive interrupt, cleared when interrupt source clears + 5 + 1 + read-write + + + CODEINREQ + Level sensitive interrupt, cleared when interrupt source clears + 6 + 1 + read-write + + + CODEOUTAVAIL + Level sensitive interrupt, cleared when interrupt source clears + 7 + 1 + read-write + + + + + PWRCTRL + PUF RAM Power Control + 0x108 + 32 + read-write + 0xF8 + 0xFD + + + RAMON + Power on the PUF RAM. + 0 + 1 + read-write + + + RAMSTAT + PUF RAM status. + 1 + 1 + read-write + + + + + CFG + PUF config register for block bits + 0x10C + 32 + read-write + 0 + 0x3 + + + BLOCKENROLL_SETKEY + Block enroll operation. Write 1 to set, cleared on reset. + 0 + 1 + read-write + + + BLOCKKEYOUTPUT + Block set key operation. Write 1 to set, cleared on reset. + 1 + 1 + read-write + + + + + KEYLOCK + Only reset in case of full IC reset + 0x200 + 32 + read-write + 0xAA + 0xFF + + + KEY0 + "10:Write access to KEY0MASK, KEYENABLE.KEY0 and KEYRESET.KEY0 is allowed. 00, 01, 11:Write access to KEY0MASK, KEYENABLE.KEY0 and KEYRESET.KEY0 is NOT allowed. Important Note : Once this field is written with a value different from '10', its value can no longer be modified until un Power On Reset occurs." + 0 + 2 + read-write + + + KEY1 + "10:Write access to KEY1MASK, KEYENABLE.KEY1 and KEYRESET.KEY1 is allowed. 00, 01, 11:Write access to KEY1MASK, KEYENABLE.KEY1 and KEYRESET.KEY1 is NOT allowed. Important Note : Once this field is written with a value different from '10', its value can no longer be modified until un Power On Reset occurs." + 2 + 2 + read-write + + + KEY2 + "10:Write access to KEY2MASK, KEYENABLE.KEY2 and KEYRESET.KEY2 is allowed. 00, 01, 11:Write access to KEY2MASK, KEYENABLE.KEY2 and KEYRESET.KEY2 is NOT allowed. Important Note : Once this field is written with a value different from '10', its value can no longer be modified until un Power On Reset occurs." "10:Write access to KEY3MASK, KEYENABLE.KEY3 and KEYRESET.KEY3 is allowed. 00, 01, 11:Write access to KEY3MASK, KEYENABLE.KEY3 and KEYRESET.KEY3 is NOT allowed. Important Note : Once this field is written with a value different from '10', its value can no longer be modified until un Power On Reset occurs." + 4 + 2 + read-write + + + KEY3 + "10:Write access to KEY3MASK, KEYENABLE.KEY3 and KEYRESET.KEY3 is allowed. 00, 01, 11:Write access to KEY3MASK, KEYENABLE.KEY3 and KEYRESET.KEY3 is NOT allowed. Important Note : Once this field is written with a value different from '10', its value can no longer be modified until un Power On Reset occurs." + 6 + 2 + read-write + + + + + KEYENABLE + no description available + 0x204 + 32 + read-write + 0x55 + 0xFF + + + KEY0 + "10: Data coming out from PUF Index 0 interface are shifted in KEY0 register. 00, 01, 11 : Data coming out from PUF Index 0 interface are NOT shifted in KEY0 register." + 0 + 2 + read-write + + + KEY1 + "10: Data coming out from PUF Index 0 interface are shifted in KEY1 register. 00, 01, 11 : Data coming out from PUF Index 0 interface are NOT shifted in KEY1 register." + 2 + 2 + read-write + + + KEY2 + "10: Data coming out from PUF Index 0 interface are shifted in KEY2 register. 00, 01, 11 : Data coming out from PUF Index 0 interface are NOT shifted in KEY2 register." + 4 + 2 + read-write + + + KEY3 + "10: Data coming out from PUF Index 0 interface are shifted in KEY2 register. 00, 01, 11 : Data coming out from PUF Index 0 interface are NOT shifted in KEY3 register." + 6 + 2 + read-write + + + + + KEYRESET + Reinitialize Keys shift registers counters + 0x208 + 32 + write-only + 0 + 0xFFFFFFFF + + + KEY0 + 10: Reset KEY0 shift register. Self clearing. Must be done before loading any new key. + 0 + 2 + write-only + + + KEY1 + 10: Reset KEY1 shift register. Self clearing. Must be done before loading any new key. + 2 + 2 + write-only + + + KEY2 + 10: Reset KEY2 shift register. Self clearing. Must be done before loading any new key. + 4 + 2 + write-only + + + KEY3 + 10: Reset KEY3 shift register. Self clearing. Must be done before loading any new key. + 6 + 2 + write-only + + + + + IDXBLK_L + no description available + 0x20C + 32 + read-write + 0x8000AAAA + 0xC000FFFF + + + IDX0 + Use to block PUF index 0 + 0 + 2 + read-write + + + IDX1 + Use to block PUF index 1 + 2 + 2 + read-write + + + IDX2 + Use to block PUF index 2 + 4 + 2 + read-write + + + IDX3 + Use to block PUF index 3 + 6 + 2 + read-write + + + IDX4 + Use to block PUF index 4 + 8 + 2 + read-write + + + IDX5 + Use to block PUF index 5 + 10 + 2 + read-write + + + IDX6 + Use to block PUF index 6 + 12 + 2 + read-write + + + IDX7 + Use to block PUF index 7 + 14 + 2 + read-write + + + LOCK_IDX + Lock 0 to 7 PUF key indexes + 30 + 2 + write-only + + + + + IDXBLK_H_DP + no description available + 0x210 + 32 + read-write + 0xAAAA + 0xFFFFFFFF + + + IDX8 + Use to block PUF index 8 + 0 + 2 + read-write + + + IDX9 + Use to block PUF index 9 + 2 + 2 + read-write + + + IDX10 + Use to block PUF index 10 + 4 + 2 + read-write + + + IDX11 + Use to block PUF index 11 + 6 + 2 + read-write + + + IDX12 + Use to block PUF index 12 + 8 + 2 + read-write + + + IDX13 + Use to block PUF index 13 + 10 + 2 + read-write + + + IDX14 + Use to block PUF index 14 + 12 + 2 + read-write + + + IDX15 + Use to block PUF index 15 + 14 + 2 + read-write + + + + + 4 + 0x4 + KEYMASK[%s] + Only reset in case of full IC reset + 0x214 + 32 + write-only + 0 + 0xFFFFFFFF + + + KEYMASK + no description available + 0 + 32 + write-only + + + + + IDXBLK_H + no description available + 0x254 + 32 + read-write + 0x8000AAAA + 0xC000FFFF + + + IDX8 + Use to block PUF index 8 + 0 + 2 + read-write + + + IDX9 + Use to block PUF index 9 + 2 + 2 + read-write + + + IDX10 + Use to block PUF index 10 + 4 + 2 + read-write + + + IDX11 + Use to block PUF index 11 + 6 + 2 + read-write + + + IDX12 + Use to block PUF index 12 + 8 + 2 + read-write + + + IDX13 + Use to block PUF index 13 + 10 + 2 + read-write + + + IDX14 + Use to block PUF index 14 + 12 + 2 + read-write + + + IDX15 + Use to block PUF index 15 + 14 + 2 + read-write + + + LOCK_IDX + Lock 8 to 15 PUF key indexes + 30 + 2 + write-only + + + + + IDXBLK_L_DP + no description available + 0x258 + 32 + read-write + 0xAAAA + 0xFFFF + + + IDX0 + Use to block PUF index 0 + 0 + 2 + read-write + + + IDX1 + Use to block PUF index 1 + 2 + 2 + read-write + + + IDX2 + Use to block PUF index 2 + 4 + 2 + read-write + + + IDX3 + Use to block PUF index 3 + 6 + 2 + read-write + + + IDX4 + Use to block PUF index 4 + 8 + 2 + read-write + + + IDX5 + Use to block PUF index 5 + 10 + 2 + read-write + + + IDX6 + Use to block PUF index 6 + 12 + 2 + read-write + + + IDX7 + Use to block PUF index 7 + 14 + 2 + read-write + + + + + SHIFT_STATUS + no description available + 0x25C + 32 + read-write + 0 + 0xFFFF + + + KEY0 + Index counter from key 0 shift register + 0 + 4 + read-only + + + KEY1 + Index counter from key 1 shift register + 4 + 4 + read-only + + + KEY2 + Index counter from key 2 shift register + 8 + 4 + read-only + + + KEY3 + Index counter from key 3 shift register + 12 + 4 + read-only + + + + + + + PLU + LPC80X Programmable Logic Unit (PLU) + PLU + 0x4003D000 + + 0 + 0xC20 + registers + + + PLU + 52 + + + + 26 + 0x20 + LUT[%s] + no description available + 0 + + 5 + 0x4 + 0,1,2,3,4 + LUT_INP%s + LUT0 input 0 MUX + 0 + 32 + read-write + 0 + 0x3F + + + LUT_INP + Selects the input source to be connected to LUT0 input0. + 0 + 6 + read-write + + + plu_inputs0 + The PLU primary inputs 0. + 0 + + + plu_inputs1 + The PLU primary inputs 1. + 0x1 + + + plu_inputs2 + The PLU primary inputs 2. + 0x2 + + + plu_inputs3 + The PLU primary inputs 3. + 0x3 + + + plu_inputs4 + The PLU primary inputs 4. + 0x4 + + + plu_inputs5 + The PLU primary inputs 5. + 0x5 + + + lut_outputs0 + The output of LUT0. + 0x6 + + + lut_outputs1 + The output of LUT1. + 0x7 + + + lut_outputs2 + The output of LUT2. + 0x8 + + + lut_outputs3 + The output of LUT3. + 0x9 + + + lut_outputs4 + The output of LUT4. + 0xA + + + lut_outputs5 + The output of LUT5. + 0xB + + + lut_outputs6 + The output of LUT6. + 0xC + + + lut_outputs7 + The output of LUT7. + 0xD + + + lut_outputs8 + The output of LUT8. + 0xE + + + lut_outputs9 + The output of LUT9. + 0xF + + + lut_outputs10 + The output of LUT10. + 0x10 + + + lut_outputs11 + The output of LUT11. + 0x11 + + + lut_outputs12 + The output of LUT12. + 0x12 + + + lut_outputs13 + The output of LUT13. + 0x13 + + + lut_outputs14 + The output of LUT14. + 0x14 + + + lut_outputs15 + The output of LUT15. + 0x15 + + + lut_outputs16 + The output of LUT16. + 0x16 + + + lut_outputs17 + The output of LUT17. + 0x17 + + + lut_outputs18 + The output of LUT18. + 0x18 + + + lut_outputs19 + The output of LUT19. + 0x19 + + + lut_outputs20 + The output of LUT20. + 0x1A + + + lut_outputs21 + The output of LUT21. + 0x1B + + + lut_outputs22 + The output of LUT22. + 0x1C + + + lut_outputs23 + The output of LUT23. + 0x1D + + + lut_outputs24 + The output of LUT24. + 0x1E + + + lut_outputs25 + The output of LUT25. + 0x1F + + + state0 + state(0). + 0x20 + + + state1 + state(1). + 0x21 + + + state2 + state(2). + 0x22 + + + state3 + state(3). + 0x23 + + + + + + + + 26 + 0x4 + LUT_TRUTH[%s] + Specifies the Truth Table contents for LUT0 + 0x800 + 32 + read-write + 0 + 0xFFFFFFFF + + + TRUTH_TABLE + Specifies the Truth Table contents for LUT0.. + 0 + 32 + read-write + + + + + OUTPUTS + Provides the current state of the 8 designated PLU Outputs. + 0x900 + 32 + read-write + 0 + 0xFFFFFFFF + + + OUTPUT_STATE + Provides the current state of the 8 designated PLU Outputs.. + 0 + 8 + read-only + + + + + WAKEINT + Wakeup interrupt control for PLU + 0x904 + 32 + read-write + 0 + 0xFFFFFFFF + + + MASK + Interrupt mask (which of the 8 PLU Outputs contribute to interrupt) + 0 + 8 + read-write + + + FILTER_MODE + control input of the PLU, add filtering for glitch + 8 + 2 + read-write + + + BYPASS + Bypass mode. + 0 + + + FILTER1CLK + Filter 1 clock period. + 0x1 + + + FILTER2CLK + Filter 2 clock period. + 0x2 + + + FILTER3CLK + Filter 3 clock period. + 0x3 + + + + + FILTER_CLKSEL + hclk is divided by 2**filter_clksel + 10 + 2 + read-write + + + LATCH_ENABLE + latch the interrupt , then can be cleared with next bit INTR_CLEAR + 12 + 1 + read-write + + + INTR_CLEAR + Write to clear wakeint_latched + 13 + 1 + read-write + oneToClear + + + + + 8 + 0x4 + OUTPUT_MUX[%s] + Selects the source to be connected to PLU Output 0 + 0xC00 + 32 + read-write + 0 + 0xFFFFFFFF + + + OUTPUTn + Selects the source to be connected to PLU Output 0. + 0 + 5 + read-write + + + plu_output0 + The PLU output 0. + 0 + + + plu_output1 + The PLU output 1. + 0x1 + + + plu_output2 + The PLU output 2. + 0x2 + + + plu_output3 + The PLU output 3. + 0x3 + + + plu_output4 + The PLU output 4. + 0x4 + + + plu_output5 + The PLU output 5. + 0x5 + + + plu_output6 + The PLU output 6. + 0x6 + + + plu_output7 + The PLU output 7. + 0x7 + + + plu_output8 + The PLU output 8. + 0x8 + + + plu_output9 + The PLU output 9. + 0x9 + + + plu_output10 + The PLU output 10. + 0xA + + + plu_output11 + The PLU output 11. + 0xB + + + plu_output12 + The PLU output 12. + 0xC + + + plu_output13 + The PLU output 13. + 0xD + + + plu_output14 + The PLU output 14. + 0xE + + + plu_output15 + The PLU output 15. + 0xF + + + plu_output16 + The PLU output 16. + 0x10 + + + plu_output17 + The PLU output 17. + 0x11 + + + plu_output18 + The PLU output 18. + 0x12 + + + plu_output19 + The PLU output 19. + 0x13 + + + plu_output20 + The PLU output 20. + 0x14 + + + plu_output21 + The PLU output 21. + 0x15 + + + plu_output22 + The PLU output 22. + 0x16 + + + plu_output23 + The PLU output 23. + 0x17 + + + plu_output24 + The PLU output 24. + 0x18 + + + plu_output25 + The PLU output 25. + 0x19 + + + state0 + state(0). + 0x1A + + + state1 + state(1). + 0x1B + + + state2 + state(2). + 0x1C + + + state3 + state(3). + 0x1D + + + + + + + + + DMA0 + DMA controller + DMA + DMA + 0x40082000 + + 0 + 0x5DC + registers + + + DMA0 + 1 + + + + CTRL + DMA control. + 0 + 32 + read-write + 0 + 0x1 + + + ENABLE + DMA controller master enable. + 0 + 1 + read-write + + + DISABLED + Disabled. The DMA controller is disabled. This clears any triggers that were asserted at the point when disabled, but does not prevent re-triggering when the DMA controller is re-enabled. + 0 + + + ENABLED + Enabled. The DMA controller is enabled. + 0x1 + + + + + + + INTSTAT + Interrupt status. + 0x4 + 32 + read-only + 0 + 0x6 + + + ACTIVEINT + Summarizes whether any enabled interrupts (other than error interrupts) are pending. + 1 + 1 + read-only + + + NOT_PENDING + Not pending. No enabled interrupts are pending. + 0 + + + PENDING + Pending. At least one enabled interrupt is pending. + 0x1 + + + + + ACTIVEERRINT + Summarizes whether any error interrupts are pending. + 2 + 1 + read-only + + + NOT_PENDING + Not pending. No error interrupts are pending. + 0 + + + PENDING + Pending. At least one error interrupt is pending. + 0x1 + + + + + + + SRAMBASE + SRAM address of the channel configuration table. + 0x8 + 32 + read-write + 0 + 0xFFFFFE00 + + + OFFSET + Address bits 31:9 of the beginning of the DMA descriptor table. For 18 channels, the table must begin on a 512 byte boundary. + 9 + 23 + read-write + + + + + ENABLESET0 + Channel Enable read and Set for all DMA channels. + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENA + Enable for DMA channels. Bit n enables or disables DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = disabled. 1 = enabled. + 0 + 32 + read-write + + + + + ENABLECLR0 + Channel Enable Clear for all DMA channels. + 0x28 + 32 + write-only + 0 + 0 + + + CLR + Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears the channel enable bit n. The number of bits = number of DMA channels in this device. Other bits are reserved. + 0 + 32 + write-only + + + + + ACTIVE0 + Channel Active status for all DMA channels. + 0x30 + 32 + read-only + 0 + 0xFFFFFFFF + + + ACT + Active flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = not active. 1 = active. + 0 + 32 + read-only + + + + + BUSY0 + Channel Busy status for all DMA channels. + 0x38 + 32 + read-only + 0 + 0xFFFFFFFF + + + BSY + Busy flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = not busy. 1 = busy. + 0 + 32 + read-only + + + + + ERRINT0 + Error Interrupt status for all DMA channels. + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + ERR + Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = error interrupt is not active. 1 = error interrupt is active. + 0 + 32 + read-write + + + + + INTENSET0 + Interrupt Enable read and Set for all DMA channels. + 0x48 + 32 + read-write + 0 + 0xFFFFFFFF + + + INTEN + Interrupt Enable read and set for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = interrupt for DMA channel is disabled. 1 = interrupt for DMA channel is enabled. + 0 + 32 + read-write + + + + + INTENCLR0 + Interrupt Enable Clear for all DMA channels. + 0x50 + 32 + write-only + 0 + 0 + + + CLR + Writing ones to this register clears corresponding bits in the INTENSET0. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. + 0 + 32 + write-only + + + + + INTA0 + Interrupt A status for all DMA channels. + 0x58 + 32 + read-write + 0 + 0xFFFFFFFF + + + IA + Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel interrupt A is not active. 1 = the DMA channel interrupt A is active. + 0 + 32 + read-write + + + + + INTB0 + Interrupt B status for all DMA channels. + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + IB + Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel interrupt B is not active. 1 = the DMA channel interrupt B is active. + 0 + 32 + read-write + + + + + SETVALID0 + Set ValidPending control bits for all DMA channels. + 0x68 + 32 + write-only + 0 + 0 + + + SV + SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = sets the VALIDPENDING control bit for DMA channel n + 0 + 32 + write-only + + + + + SETTRIG0 + Set Trigger control bits for all DMA channels. + 0x70 + 32 + write-only + 0 + 0 + + + TRIG + Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = sets the TRIG bit for DMA channel n. + 0 + 32 + write-only + + + + + ABORT0 + Channel Abort control for all DMA channels. + 0x78 + 32 + write-only + 0 + 0 + + + ABORTCTRL + Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = aborts DMA operations on channel n. + 0 + 32 + write-only + + + + + 30 + 0x10 + CHANNEL[%s] + no description available + 0x400 + + CFG + Configuration register for DMA channel . + 0 + 32 + read-write + 0 + 0x7CF73 + + + PERIPHREQEN + Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller. + 0 + 1 + read-write + + + DISABLED + Disabled. Peripheral DMA requests are disabled. + 0 + + + ENABLED + Enabled. Peripheral DMA requests are enabled. + 0x1 + + + + + HWTRIGEN + Hardware Triggering Enable for this channel. + 1 + 1 + read-write + + + DISABLED + Disabled. Hardware triggering is not used. + 0 + + + ENABLED + Enabled. Use hardware triggering. + 0x1 + + + + + TRIGPOL + Trigger Polarity. Selects the polarity of a hardware trigger for this channel. + 4 + 1 + read-write + + + ACTIVE_LOW_FALLING + Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE. + 0 + + + ACTIVE_HIGH_RISING + Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE. + 0x1 + + + + + TRIGTYPE + Trigger Type. Selects hardware trigger as edge triggered or level triggered. + 5 + 1 + read-write + + + EDGE + Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger. + 0 + + + LEVEL + Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed. + 0x1 + + + + + TRIGBURST + Trigger Burst. Selects whether hardware triggers cause a single or burst transfer. + 6 + 1 + read-write + + + SINGLE + Single transfer. Hardware trigger causes a single transfer. + 0 + + + BURST + Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete. + 0x1 + + + + + BURSTPOWER + Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size. + 8 + 4 + read-write + + + SRCBURSTWRAP + Source Burst Wrap. When enabled, the source data address for the DMA is 'wrapped', meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst. + 14 + 1 + read-write + + + DISABLED + Disabled. Source burst wrapping is not enabled for this DMA channel. + 0 + + + ENABLED + Enabled. Source burst wrapping is enabled for this DMA channel. + 0x1 + + + + + DSTBURSTWRAP + Destination Burst Wrap. When enabled, the destination data address for the DMA is 'wrapped', meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst. + 15 + 1 + read-write + + + DISABLED + Disabled. Destination burst wrapping is not enabled for this DMA channel. + 0 + + + ENABLED + Enabled. Destination burst wrapping is enabled for this DMA channel. + 0x1 + + + + + CHPRIORITY + Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported: 0x0 = highest priority. 0x7 = lowest priority. + 16 + 3 + read-write + + + + + CTLSTAT + Control and status register for DMA channel . + 0x4 + 32 + read-only + 0 + 0x5 + + + VALIDPENDING + Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel. + 0 + 1 + read-only + + + NO_EFFECT + No effect. No effect on DMA operation. + 0 + + + VALID_PENDING + Valid pending. + 0x1 + + + + + TRIG + Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1. + 2 + 1 + read-only + + + NOT_TRIGGERED + Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out. + 0 + + + TRIGGERED + Triggered. The trigger for this DMA channel is set. DMA operations will be carried out. + 0x1 + + + + + + + XFERCFG + Transfer configuration register for DMA channel . + 0x8 + 32 + read-write + 0 + 0x3FFF33F + + + CFGVALID + Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled. + 0 + 1 + read-write + + + NOT_VALID + Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting. + 0 + + + VALID + Valid. The current channel descriptor is considered valid. + 0x1 + + + + + RELOAD + Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers. + 1 + 1 + read-write + + + DISABLED + Disabled. Do not reload the channels' control structure when the current descriptor is exhausted. + 0 + + + ENABLED + Enabled. Reload the channels' control structure when the current descriptor is exhausted. + 0x1 + + + + + SWTRIG + Software Trigger. + 2 + 1 + read-write + + + NOT_SET + Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel. + 0 + + + SET + Set. When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0. + 0x1 + + + + + CLRTRIG + Clear Trigger. + 3 + 1 + read-write + + + NOT_CLEARED + Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started. + 0 + + + CLEARED + Cleared. The trigger is cleared when this descriptor is exhausted + 0x1 + + + + + SETINTA + Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed. + 4 + 1 + read-write + + + NO_EFFECT + No effect. + 0 + + + SET + Set. The INTA flag for this channel will be set when the current descriptor is exhausted. + 0x1 + + + + + SETINTB + Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed. + 5 + 1 + read-write + + + NO_EFFECT + No effect. + 0 + + + SET + Set. The INTB flag for this channel will be set when the current descriptor is exhausted. + 0x1 + + + + + WIDTH + Transfer width used for this DMA channel. + 8 + 2 + read-write + + + BIT_8 + 8-bit. 8-bit transfers are performed (8-bit source reads and destination writes). + 0 + + + BIT_16 + 16-bit. 6-bit transfers are performed (16-bit source reads and destination writes). + 0x1 + + + BIT_32 + 32-bit. 32-bit transfers are performed (32-bit source reads and destination writes). + 0x2 + + + + + SRCINC + Determines whether the source address is incremented for each DMA transfer. + 12 + 2 + read-write + + + NO_INCREMENT + No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device. + 0 + + + WIDTH_X_1 + 1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory. + 0x1 + + + WIDTH_X_2 + 2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer. + 0x2 + + + WIDTH_X_4 + 4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer. + 0x3 + + + + + DSTINC + Determines whether the destination address is incremented for each DMA transfer. + 14 + 2 + read-write + + + NO_INCREMENT + No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device. + 0 + + + WIDTH_X_1 + 1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory. + 0x1 + + + WIDTH_X_2 + 2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer. + 0x2 + + + WIDTH_X_4 + 4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer. + 0x3 + + + + + XFERCOUNT + Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of 1,024 transfers will be performed. + 16 + 10 + read-write + + + + + + + + DMA1 + DMA controller + DMA + 0x400A7000 + + 0 + 0x5DC + registers + + + DMA1 + 58 + + + + USB0 + USB 2.0 Device Controller + USB + 0x40084000 + + 0 + 0x38 + registers + + + USB0_NEEDCLK + 27 + + + USB0 + 28 + + + + DEVCMDSTAT + USB Device Command/Status register + 0 + 32 + read-write + 0x800 + 0x171BFBFF + + + DEV_ADDR + USB device address. After bus reset, the address is reset to 0x00. If the enable bit is set, the device will respond on packets for function address DEV_ADDR. When receiving a SetAddress Control Request from the USB host, software must program the new address before completing the status phase of the SetAddress Control Request. + 0 + 7 + read-write + + + DEV_EN + USB device enable. If this bit is set, the HW will start responding on packets for function address DEV_ADDR. + 7 + 1 + read-write + + + SETUP + SETUP token received. If a SETUP token is received and acknowledged by the device, this bit is set. As long as this bit is set all received IN and OUT tokens will be NAKed by HW. SW must clear this bit by writing a one. If this bit is zero, HW will handle the tokens to the CTRL EP0 as indicated by the CTRL EP0 IN and OUT data information programmed by SW. + 8 + 1 + read-write + + + FORCE_NEEDCLK + Forces the NEEDCLK output to always be on: + 9 + 1 + read-write + + + NORMAL + USB_NEEDCLK has normal function. + 0 + + + ALWAYS_ON + USB_NEEDCLK always 1. Clock will not be stopped in case of suspend. + 0x1 + + + + + LPM_SUP + LPM Supported: + 11 + 1 + read-write + + + NO + LPM not supported. + 0 + + + YES + LPM supported. + 0x1 + + + + + INTONNAK_AO + Interrupt on NAK for interrupt and bulk OUT EP + 12 + 1 + read-write + + + DISABLED + Only acknowledged packets generate an interrupt + 0 + + + ENABLED + Both acknowledged and NAKed packets generate interrupts. + 0x1 + + + + + INTONNAK_AI + Interrupt on NAK for interrupt and bulk IN EP + 13 + 1 + read-write + + + DISABLED + Only acknowledged packets generate an interrupt + 0 + + + ENABLED + Both acknowledged and NAKed packets generate interrupts. + 0x1 + + + + + INTONNAK_CO + Interrupt on NAK for control OUT EP + 14 + 1 + read-write + + + DISABLED + Only acknowledged packets generate an interrupt + 0 + + + ENABLED + Both acknowledged and NAKed packets generate interrupts. + 0x1 + + + + + INTONNAK_CI + Interrupt on NAK for control IN EP + 15 + 1 + read-write + + + DISABLED + Only acknowledged packets generate an interrupt + 0 + + + ENABLED + Both acknowledged and NAKed packets generate interrupts. + 0x1 + + + + + DCON + Device status - connect. The connect bit must be set by SW to indicate that the device must signal a connect. The pull-up resistor on USB_DP will be enabled when this bit is set and the VBUSDEBOUNCED bit is one. + 16 + 1 + read-write + + + DSUS + Device status - suspend. The suspend bit indicates the current suspend state. It is set to 1 when the device hasn't seen any activity on its upstream port for more than 3 milliseconds. It is reset to 0 on any activity. When the device is suspended (Suspend bit DSUS = 1) and the software writes a 0 to it, the device will generate a remote wake-up. This will only happen when the device is connected (Connect bit = 1). When the device is not connected or not suspended, a writing a 0 has no effect. Writing a 1 never has an effect. + 17 + 1 + read-write + + + LPM_SUS + Device status - LPM Suspend. This bit represents the current LPM suspend state. It is set to 1 by HW when the device has acknowledged the LPM request from the USB host and the Token Retry Time of 10 ms has elapsed. When the device is in the LPM suspended state (LPM suspend bit = 1) and the software writes a zero to this bit, the device will generate a remote walk-up. Software can only write a zero to this bit when the LPM_REWP bit is set to 1. HW resets this bit when it receives a host initiated resume. HW only updates the LPM_SUS bit when the LPM_SUPP bit is equal to one. + 19 + 1 + read-write + + + LPM_REWP + LPM Remote Wake-up Enabled by USB host. HW sets this bit to one when the bRemoteWake bit in the LPM extended token is set to 1. HW will reset this bit to 0 when it receives the host initiated LPM resume, when a remote wake-up is sent by the device or when a USB bus reset is received. Software can use this bit to check if the remote wake-up feature is enabled by the host for the LPM transaction. + 20 + 1 + read-only + + + DCON_C + Device status - connect change. The Connect Change bit is set when the device's pull-up resistor is disconnected because VBus disappeared. The bit is reset by writing a one to it. + 24 + 1 + read-write + + + DSUS_C + Device status - suspend change. The suspend change bit is set to 1 when the suspend bit toggles. The suspend bit can toggle because: - The device goes in the suspended state - The device is disconnected - The device receives resume signaling on its upstream port. The bit is reset by writing a one to it. + 25 + 1 + read-write + + + DRES_C + Device status - reset change. This bit is set when the device received a bus reset. On a bus reset the device will automatically go to the default state (unconfigured and responding to address 0). The bit is reset by writing a one to it. + 26 + 1 + read-write + + + VBUSDEBOUNCED + This bit indicates if Vbus is detected or not. The bit raises immediately when Vbus becomes high. It drops to zero if Vbus is low for at least 3 ms. If this bit is high and the DCon bit is set, the HW will enable the pull-up resistor to signal a connect. + 28 + 1 + read-only + + + + + INFO + USB Info register + 0x4 + 32 + read-write + 0 + 0x7FFF + + + FRAME_NR + Frame number. This contains the frame number of the last successfully received SOF. In case no SOF was received by the device at the beginning of a frame, the frame number returned is that of the last successfully received SOF. In case the SOF frame number contained a CRC error, the frame number returned will be the corrupted frame number as received by the device. + 0 + 11 + read-only + + + ERR_CODE + The error code which last occurred: + 11 + 4 + read-write + + + NO_ERROR + No error + 0 + + + PID_ENCODING_ERROR + PID encoding error + 0x1 + + + PID_UNKNOWN + PID unknown + 0x2 + + + PACKET_UNEXPECTED + Packet unexpected + 0x3 + + + TOKEN_CRC_ERROR + Token CRC error + 0x4 + + + DATA_CRC_ERROR + Data CRC error + 0x5 + + + TIMEOUT + Time out + 0x6 + + + BABBLE + Babble + 0x7 + + + TRUNCATED_EOP + Truncated EOP + 0x8 + + + SENT_RECEIVED_NAK + Sent/Received NAK + 0x9 + + + SENT_STALL + Sent Stall + 0xA + + + OVERRUN + Overrun + 0xB + + + SENT_EMPTY_PACKET + Sent empty packet + 0xC + + + BITSTUFF_ERROR + Bitstuff error + 0xD + + + SYNC_ERROR + Sync error + 0xE + + + WRONG_DATA_TOGGLE + Wrong data toggle + 0xF + + + + + MINREV + Minor Revision. + 16 + 8 + read-only + + + MAJREV + Major Revision. + 24 + 8 + read-only + + + + + EPLISTSTART + USB EP Command/Status List start address + 0x8 + 32 + read-write + 0 + 0xFFFFFF00 + + + EP_LIST + Start address of the USB EP Command/Status List. + 8 + 24 + read-write + + + + + DATABUFSTART + USB Data buffer start address + 0xC + 32 + read-write + 0 + 0xFFC00000 + + + DA_BUF + Start address of the buffer pointer page where all endpoint data buffers are located. + 22 + 10 + read-write + + + + + LPM + USB Link Power Management register + 0x10 + 32 + read-write + 0 + 0x1FF + + + HIRD_HW + Host Initiated Resume Duration - HW. This is the HIRD value from the last received LPM token + 0 + 4 + read-only + + + HIRD_SW + Host Initiated Resume Duration - SW. This is the time duration required by the USB device system to come out of LPM initiated suspend after receiving the host initiated LPM resume. + 4 + 4 + read-write + + + DATA_PENDING + As long as this bit is set to one and LPM supported bit is set to one, HW will return a NYET handshake on every LPM token it receives. If LPM supported bit is set to one and this bit is zero, HW will return an ACK handshake on every LPM token it receives. If SW has still data pending and LPM is supported, it must set this bit to 1. + 8 + 1 + read-write + + + + + EPSKIP + USB Endpoint skip + 0x14 + 32 + read-write + 0 + 0x3FFFFFFF + + + SKIP + Endpoint skip: Writing 1 to one of these bits, will indicate to HW that it must deactivate the buffer assigned to this endpoint and return control back to software. When HW has deactivated the endpoint, it will clear this bit, but it will not modify the EPINUSE bit. An interrupt will be generated when the Active bit goes from 1 to 0. Note: In case of double-buffering, HW will only clear the Active bit of the buffer indicated by the EPINUSE bit. + 0 + 10 + read-write + + + + + EPINUSE + USB Endpoint Buffer in use + 0x18 + 32 + read-write + 0 + 0x3FC + + + BUF + Buffer in use: This register has one bit per physical endpoint. 0: HW is accessing buffer 0. 1: HW is accessing buffer 1. + 2 + 8 + read-write + + + + + EPBUFCFG + USB Endpoint Buffer Configuration register + 0x1C + 32 + read-write + 0 + 0x3FC + + + BUF_SB + Buffer usage: This register has one bit per physical endpoint. 0: Single-buffer. 1: Double-buffer. If the bit is set to single-buffer (0), it will not toggle the corresponding EPINUSE bit when it clears the active bit. If the bit is set to double-buffer (1), HW will toggle the EPINUSE bit when it clears the Active bit for the buffer. + 2 + 8 + read-write + + + + + INTSTAT + USB interrupt status register + 0x20 + 32 + read-write + 0 + 0xC00003FF + + + EP0OUT + Interrupt status register bit for the Control EP0 OUT direction. This bit will be set if NBytes transitions to zero or the skip bit is set by software or a SETUP packet is successfully received for the control EP0. If the IntOnNAK_CO is set, this bit will also be set when a NAK is transmitted for the Control EP0 OUT direction. Software can clear this bit by writing a one to it. + 0 + 1 + read-write + + + EP0IN + Interrupt status register bit for the Control EP0 IN direction. This bit will be set if NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_CI is set, this bit will also be set when a NAK is transmitted for the Control EP0 IN direction. Software can clear this bit by writing a one to it. + 1 + 1 + read-write + + + EP1OUT + Interrupt status register bit for the EP1 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP1 OUT direction. Software can clear this bit by writing a one to it. + 2 + 1 + read-write + + + EP1IN + Interrupt status register bit for the EP1 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP1 IN direction. Software can clear this bit by writing a one to it. + 3 + 1 + read-write + + + EP2OUT + Interrupt status register bit for the EP2 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP2 OUT direction. Software can clear this bit by writing a one to it. + 4 + 1 + read-write + + + EP2IN + Interrupt status register bit for the EP2 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP2 IN direction. Software can clear this bit by writing a one to it. + 5 + 1 + read-write + + + EP3OUT + Interrupt status register bit for the EP3 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP3 OUT direction. Software can clear this bit by writing a one to it. + 6 + 1 + read-write + + + EP3IN + Interrupt status register bit for the EP3 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP3 IN direction. Software can clear this bit by writing a one to it. + 7 + 1 + read-write + + + EP4OUT + Interrupt status register bit for the EP4 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP4 OUT direction. Software can clear this bit by writing a one to it. + 8 + 1 + read-write + + + EP4IN + Interrupt status register bit for the EP4 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP4 IN direction. Software can clear this bit by writing a one to it. + 9 + 1 + read-write + + + FRAME_INT + Frame interrupt. This bit is set to one every millisecond when the VbusDebounced bit and the DCON bit are set. This bit can be used by software when handling isochronous endpoints. Software can clear this bit by writing a one to it. + 30 + 1 + read-write + + + DEV_INT + Device status interrupt. This bit is set by HW when one of the bits in the Device Status Change register are set. Software can clear this bit by writing a one to it. + 31 + 1 + read-write + + + + + INTEN + USB interrupt enable register + 0x24 + 32 + read-write + 0 + 0xC00003FF + + + EP_INT_EN + If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing bit. + 0 + 10 + read-write + + + FRAME_INT_EN + If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing bit. + 30 + 1 + read-write + + + DEV_INT_EN + If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing bit. + 31 + 1 + read-write + + + + + INTSETSTAT + USB set interrupt status register + 0x28 + 32 + read-write + 0 + 0xC00003FF + + + EP_SET_INT + If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. When this register is read, the same value as the USB interrupt status register is returned. + 0 + 10 + read-write + + + FRAME_SET_INT + If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. When this register is read, the same value as the USB interrupt status register is returned. + 30 + 1 + read-write + + + DEV_SET_INT + If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. When this register is read, the same value as the USB interrupt status register is returned. + 31 + 1 + read-write + + + + + EPTOGGLE + USB Endpoint toggle register + 0x34 + 32 + read-write + 0 + 0x3FF + + + TOGGLE + Endpoint data toggle: This field indicates the current value of the data toggle for the corresponding endpoint. + 0 + 10 + read-write + + + + + + + SCT0 + SCTimer/PWM (SCT) + SCT + 0x40085000 + + 0 + 0x550 + registers + + + SCT0 + 12 + + + + CONFIG + SCT configuration register + 0 + 32 + read-write + 0x1E00 + 0x61FFF + + + UNIFY + SCT operation + 0 + 1 + read-write + + + DUAL_COUNTER + The SCT operates as two 16-bit counters named COUNTER_L and COUNTER_H. + 0 + + + UNIFIED_COUNTER + The SCT operates as a unified 32-bit counter. + 0x1 + + + + + CLKMODE + SCT clock mode + 1 + 2 + read-write + + + SYSTEM_CLOCK_MODE + System Clock Mode. The system clock clocks the entire SCT module including the counter(s) and counter prescalers. + 0 + + + SAMPLED_SYSTEM_CLOCK_MODE + Sampled System Clock Mode. The system clock clocks the SCT module, but the counter and prescalers are only enabled to count when the designated edge is detected on the input selected by the CKSEL field. The minimum pulse width on the selected clock-gate input is 1 bus clock period. This mode is the high-performance, sampled-clock mode. + 0x1 + + + SCT_INPUT_CLOCK_MODE + SCT Input Clock Mode. The input/edge selected by the CKSEL field clocks the SCT module, including the counters and prescalers, after first being synchronized to the system clock. The minimum pulse width on the clock input is 1 bus clock period. This mode is the low-power, sampled-clock mode. + 0x2 + + + ASYNCHRONOUS_MODE + Asynchronous Mode. The entire SCT module is clocked directly by the input/edge selected by the CKSEL field. In this mode, the SCT outputs are switched synchronously to the SCT input clock - not the system clock. The input clock rate must be at least half the system clock rate and can be the same or faster than the system clock. + 0x3 + + + + + CKSEL + SCT clock select. The specific functionality of the designated input/edge is dependent on the CLKMODE bit selection in this register. + 3 + 4 + read-write + + + INPUT_0_RISING_EDGES + Rising edges on input 0. + 0 + + + INPUT_0_FALLING_EDGE + Falling edges on input 0. + 0x1 + + + INPUT_1_RISING_EDGES + Rising edges on input 1. + 0x2 + + + INPUT_1_FALLING_EDGE + Falling edges on input 1. + 0x3 + + + INPUT_2_RISING_EDGES + Rising edges on input 2. + 0x4 + + + INPUT_2_FALLING_EDGE + Falling edges on input 2. + 0x5 + + + INPUT_3_RISING_EDGES + Rising edges on input 3. + 0x6 + + + INPUT_3_FALLING_EDGE + Falling edges on input 3. + 0x7 + + + + + NORELAOD_L + A 1 in this bit prevents the lower match registers from being reloaded from their respective reload registers. Setting this bit eliminates the need to write to the reload registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set. + 7 + 1 + read-write + + + NORELOAD_H + A 1 in this bit prevents the higher match registers from being reloaded from their respective reload registers. Setting this bit eliminates the need to write to the reload registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set. + 8 + 1 + read-write + + + INSYNC + Synchronization for input N (bit 9 = input 0, bit 10 = input 1,, bit 12 = input 3); all other bits are reserved. A 1 in one of these bits subjects the corresponding input to synchronization to the SCT clock, before it is used to create an event. If an input is known to already be synchronous to the SCT clock, this bit may be set to 0 for faster input response. (Note: The SCT clock is the system clock for CKMODEs 0-2. It is the selected, asynchronous SCT input clock for CKMODE3). Note that the INSYNC field only affects inputs used for event generation. It does not apply to the clock input specified in the CKSEL field. + 9 + 4 + read-write + + + AUTOLIMIT_L + A one in this bit causes a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in unidirectional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set. + 17 + 1 + read-write + + + AUTOLIMIT_H + A one in this bit will cause a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in unidirectional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set. + 18 + 1 + read-write + + + + + CTRL + SCT control register + 0x4 + 32 + read-write + 0x40004 + 0x1FFF1FFF + + + DOWN_L + This bit is 1 when the L or unified counter is counting down. Hardware sets this bit when the counter is counting up, counter limit occurs, and BIDIR = 1.Hardware clears this bit when the counter is counting down and a limit condition occurs or when the counter reaches 0. + 0 + 1 + read-write + + + STOP_L + When this bit is 1 and HALT is 0, the L or unified counter does not run, but I/O events related to the counter can occur. If a designated start event occurs, this bit is cleared and counting resumes. + 1 + 1 + read-write + + + HALT_L + When this bit is 1, the L or unified counter does not run and no events can occur. A reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. It is possible to remove the halt condition while keeping the SCT in the stop condition (not running) with a single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set, only software can clear this bit to restore counter operation. This bit is set on reset. + 2 + 1 + read-write + + + CLRCTR_L + Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0. + 3 + 1 + read-write + + + BIDIR_L + L or unified counter direction select + 4 + 1 + read-write + + + UP + Up. The counter counts up to a limit condition, then is cleared to zero. + 0 + + + UP_DOWN + Up-down. The counter counts up to a limit, then counts down to a limit condition or to 0. + 0x1 + + + + + PRE_L + Specifies the factor by which the SCT clock is prescaled to produce the L or unified counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. + 5 + 8 + read-write + + + DOWN_H + This bit is 1 when the H counter is counting down. Hardware sets this bit when the counter is counting, a counter limit condition occurs, and BIDIR is 1. Hardware clears this bit when the counter is counting down and a limit condition occurs or when the counter reaches 0. + 16 + 1 + read-write + + + STOP_H + When this bit is 1 and HALT is 0, the H counter does not, run but I/O events related to the counter can occur. If such an event matches the mask in the Start register, this bit is cleared and counting resumes. + 17 + 1 + read-write + + + HALT_H + When this bit is 1, the H counter does not run and no events can occur. A reset sets this bit. When the HALT_H bit is one, the STOP_H bit is cleared. It is possible to remove the halt condition while keeping the SCT in the stop condition (not running) with a single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set, this bit can only be cleared by software to restore counter operation. This bit is set on reset. + 18 + 1 + read-write + + + CLRCTR_H + Writing a 1 to this bit clears the H counter. This bit always reads as 0. + 19 + 1 + read-write + + + BIDIR_H + Direction select + 20 + 1 + read-write + + + UP + The H counter counts up to its limit condition, then is cleared to zero. + 0 + + + UP_DOWN + The H counter counts up to its limit, then counts down to a limit condition or to 0. + 0x1 + + + + + PRE_H + Specifies the factor by which the SCT clock is prescaled to produce the H counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. + 21 + 8 + read-write + + + + + LIMIT + SCT limit event select register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + LIMMSK_L + If bit n is one, event n is used as a counter limit for the L or unified counter (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. + 0 + 16 + read-write + + + LIMMSK_H + If bit n is one, event n is used as a counter limit for the H counter (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT. + 16 + 16 + read-write + + + + + HALT + SCT halt event select register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + HALTMSK_L + If bit n is one, event n sets the HALT_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. + 0 + 16 + read-write + + + HALTMSK_H + If bit n is one, event n sets the HALT_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT. + 16 + 16 + read-write + + + + + STOP + SCT stop event select register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + STOPMSK_L + If bit n is one, event n sets the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. + 0 + 16 + read-write + + + STOPMSK_H + If bit n is one, event n sets the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT. + 16 + 16 + read-write + + + + + START + SCT start event select register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + STARTMSK_L + If bit n is one, event n clears the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. + 0 + 16 + read-write + + + STARTMSK_H + If bit n is one, event n clears the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT. + 16 + 16 + read-write + + + + + COUNT + SCT counter register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + CTR_L + When UNIFY = 0, read or write the 16-bit L counter value. When UNIFY = 1, read or write the lower 16 bits of the 32-bit unified counter. + 0 + 16 + read-write + + + CTR_H + When UNIFY = 0, read or write the 16-bit H counter value. When UNIFY = 1, read or write the upper 16 bits of the 32-bit unified counter. + 16 + 16 + read-write + + + + + STATE + SCT state register + 0x44 + 32 + read-write + 0 + 0x1F001F + + + STATE_L + State variable. + 0 + 5 + read-write + + + STATE_H + State variable. + 16 + 5 + read-write + + + + + INPUT + SCT input register + 0x48 + 32 + read-only + 0 + 0xFFFFFFFF + + + AIN0 + Input 0 state. Input 0 state on the last SCT clock edge. + 0 + 1 + read-only + + + AIN1 + Input 1 state. Input 1 state on the last SCT clock edge. + 1 + 1 + read-only + + + AIN2 + Input 2 state. Input 2 state on the last SCT clock edge. + 2 + 1 + read-only + + + AIN3 + Input 3 state. Input 3 state on the last SCT clock edge. + 3 + 1 + read-only + + + AIN4 + Input 4 state. Input 4 state on the last SCT clock edge. + 4 + 1 + read-only + + + AIN5 + Input 5 state. Input 5 state on the last SCT clock edge. + 5 + 1 + read-only + + + AIN6 + Input 6 state. Input 6 state on the last SCT clock edge. + 6 + 1 + read-only + + + AIN7 + Input 7 state. Input 7 state on the last SCT clock edge. + 7 + 1 + read-only + + + AIN8 + Input 8 state. Input 8 state on the last SCT clock edge. + 8 + 1 + read-only + + + AIN9 + Input 9 state. Input 9 state on the last SCT clock edge. + 9 + 1 + read-only + + + AIN10 + Input 10 state. Input 10 state on the last SCT clock edge. + 10 + 1 + read-only + + + AIN11 + Input 11 state. Input 11 state on the last SCT clock edge. + 11 + 1 + read-only + + + AIN12 + Input 12 state. Input 12 state on the last SCT clock edge. + 12 + 1 + read-only + + + AIN13 + Input 13 state. Input 13 state on the last SCT clock edge. + 13 + 1 + read-only + + + AIN14 + Input 14 state. Input 14 state on the last SCT clock edge. + 14 + 1 + read-only + + + AIN15 + Input 15 state. Input 15 state on the last SCT clock edge. + 15 + 1 + read-only + + + SIN0 + Input 0 state. Input 0 state following the synchronization specified by INSYNC. + 16 + 1 + read-only + + + SIN1 + Input 1 state. Input 1 state following the synchronization specified by INSYNC. + 17 + 1 + read-only + + + SIN2 + Input 2 state. Input 2 state following the synchronization specified by INSYNC. + 18 + 1 + read-only + + + SIN3 + Input 3 state. Input 3 state following the synchronization specified by INSYNC. + 19 + 1 + read-only + + + SIN4 + Input 4 state. Input 4 state following the synchronization specified by INSYNC. + 20 + 1 + read-only + + + SIN5 + Input 5 state. Input 5 state following the synchronization specified by INSYNC. + 21 + 1 + read-only + + + SIN6 + Input 6 state. Input 6 state following the synchronization specified by INSYNC. + 22 + 1 + read-only + + + SIN7 + Input 7 state. Input 7 state following the synchronization specified by INSYNC. + 23 + 1 + read-only + + + SIN8 + Input 8 state. Input 8 state following the synchronization specified by INSYNC. + 24 + 1 + read-only + + + SIN9 + Input 9 state. Input 9 state following the synchronization specified by INSYNC. + 25 + 1 + read-only + + + SIN10 + Input 10 state. Input 10 state following the synchronization specified by INSYNC. + 26 + 1 + read-only + + + SIN11 + Input 11 state. Input 11 state following the synchronization specified by INSYNC. + 27 + 1 + read-only + + + SIN12 + Input 12 state. Input 12 state following the synchronization specified by INSYNC. + 28 + 1 + read-only + + + SIN13 + Input 13 state. Input 13 state following the synchronization specified by INSYNC. + 29 + 1 + read-only + + + SIN14 + Input 14 state. Input 14 state following the synchronization specified by INSYNC. + 30 + 1 + read-only + + + SIN15 + Input 15 state. Input 15 state following the synchronization specified by INSYNC. + 31 + 1 + read-only + + + + + REGMODE + SCT match/capture mode register + 0x4C + 32 + read-write + 0 + 0xFFFFFFFF + + + REGMOD_L + Each bit controls one match/capture register (register 0 = bit 0, register 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. 0 = register operates as match register. 1 = register operates as capture register. + 0 + 16 + read-write + + + REGMOD_H + Each bit controls one match/capture register (register 0 = bit 16, register 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. 0 = register operates as match registers. 1 = register operates as capture registers. + 16 + 16 + read-write + + + + + OUTPUT + SCT output register + 0x50 + 32 + read-write + 0 + 0xFFFF + + + OUT + Writing a 1 to bit n forces the corresponding output HIGH. Writing a 0 forces the corresponding output LOW (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of outputs in this SCT. + 0 + 16 + read-write + + + + + OUTPUTDIRCTRL + SCT output counter direction control register + 0x54 + 32 + read-write + 0 + 0xFFFFFFFF + + + SETCLR0 + Set/clear operation on output 0. Value 0x3 is reserved. Do not program this value. + 0 + 2 + read-write + + + INDEPENDENT + Set and clear do not depend on the direction of any counter. + 0 + + + L_REVERSED + Set and clear are reversed when counter L or the unified counter is counting down. + 0x1 + + + H_REVERSED + Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + 0x2 + + + + + SETCLR1 + Set/clear operation on output 1. Value 0x3 is reserved. Do not program this value. + 2 + 2 + read-write + + + INDEPENDENT + Set and clear do not depend on the direction of any counter. + 0 + + + L_REVERSED + Set and clear are reversed when counter L or the unified counter is counting down. + 0x1 + + + H_REVERSED + Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + 0x2 + + + + + SETCLR2 + Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value. + 4 + 2 + read-write + + + INDEPENDENT + Set and clear do not depend on the direction of any counter. + 0 + + + L_REVERSED + Set and clear are reversed when counter L or the unified counter is counting down. + 0x1 + + + H_REVERSED + Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + 0x2 + + + + + SETCLR3 + Set/clear operation on output 3. Value 0x3 is reserved. Do not program this value. + 6 + 2 + read-write + + + INDEPENDENT + Set and clear do not depend on the direction of any counter. + 0 + + + L_REVERSED + Set and clear are reversed when counter L or the unified counter is counting down. + 0x1 + + + H_REVERSED + Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + 0x2 + + + + + SETCLR4 + Set/clear operation on output 4. Value 0x3 is reserved. Do not program this value. + 8 + 2 + read-write + + + INDEPENDENT + Set and clear do not depend on the direction of any counter. + 0 + + + L_REVERSED + Set and clear are reversed when counter L or the unified counter is counting down. + 0x1 + + + H_REVERSED + Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + 0x2 + + + + + SETCLR5 + Set/clear operation on output 5. Value 0x3 is reserved. Do not program this value. + 10 + 2 + read-write + + + INDEPENDENT + Set and clear do not depend on the direction of any counter. + 0 + + + L_REVERSED + Set and clear are reversed when counter L or the unified counter is counting down. + 0x1 + + + H_REVERSED + Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + 0x2 + + + + + SETCLR6 + Set/clear operation on output 6. Value 0x3 is reserved. Do not program this value. + 12 + 2 + read-write + + + INDEPENDENT + Set and clear do not depend on the direction of any counter. + 0 + + + L_REVERSED + Set and clear are reversed when counter L or the unified counter is counting down. + 0x1 + + + H_REVERSED + Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + 0x2 + + + + + SETCLR7 + Set/clear operation on output 7. Value 0x3 is reserved. Do not program this value. + 14 + 2 + read-write + + + INDEPENDENT + Set and clear do not depend on the direction of any counter. + 0 + + + L_REVERSED + Set and clear are reversed when counter L or the unified counter is counting down. + 0x1 + + + H_REVERSED + Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + 0x2 + + + + + SETCLR8 + Set/clear operation on output 8. Value 0x3 is reserved. Do not program this value. + 16 + 2 + read-write + + + INDEPENDENT + Set and clear do not depend on the direction of any counter. + 0 + + + L_REVERSED + Set and clear are reversed when counter L or the unified counter is counting down. + 0x1 + + + H_REVERSED + Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + 0x2 + + + + + SETCLR9 + Set/clear operation on output 9. Value 0x3 is reserved. Do not program this value. + 18 + 2 + read-write + + + INDEPENDENT + Set and clear do not depend on the direction of any counter. + 0 + + + L_REVERSED + Set and clear are reversed when counter L or the unified counter is counting down. + 0x1 + + + H_REVERSED + Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + 0x2 + + + + + SETCLR10 + Set/clear operation on output 10. Value 0x3 is reserved. Do not program this value. + 20 + 2 + read-write + + + INDEPENDENT + Set and clear do not depend on the direction of any counter. + 0 + + + L_REVERSED + Set and clear are reversed when counter L or the unified counter is counting down. + 0x1 + + + H_REVERSED + Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + 0x2 + + + + + SETCLR11 + Set/clear operation on output 11. Value 0x3 is reserved. Do not program this value. + 22 + 2 + read-write + + + INDEPENDENT + Set and clear do not depend on the direction of any counter. + 0 + + + L_REVERSED + Set and clear are reversed when counter L or the unified counter is counting down. + 0x1 + + + H_REVERSED + Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + 0x2 + + + + + SETCLR12 + Set/clear operation on output 12. Value 0x3 is reserved. Do not program this value. + 24 + 2 + read-write + + + INDEPENDENT + Set and clear do not depend on the direction of any counter. + 0 + + + L_REVERSED + Set and clear are reversed when counter L or the unified counter is counting down. + 0x1 + + + H_REVERSED + Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + 0x2 + + + + + SETCLR13 + Set/clear operation on output 13. Value 0x3 is reserved. Do not program this value. + 26 + 2 + read-write + + + INDEPENDENT + Set and clear do not depend on the direction of any counter. + 0 + + + L_REVERSED + Set and clear are reversed when counter L or the unified counter is counting down. + 0x1 + + + H_REVERSED + Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + 0x2 + + + + + SETCLR14 + Set/clear operation on output 14. Value 0x3 is reserved. Do not program this value. + 28 + 2 + read-write + + + INDEPENDENT + Set and clear do not depend on the direction of any counter. + 0 + + + L_REVERSED + Set and clear are reversed when counter L or the unified counter is counting down. + 0x1 + + + H_REVERSED + Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + 0x2 + + + + + SETCLR15 + Set/clear operation on output 15. Value 0x3 is reserved. Do not program this value. + 30 + 2 + read-write + + + INDEPENDENT + Set and clear do not depend on the direction of any counter. + 0 + + + L_REVERSED + Set and clear are reversed when counter L or the unified counter is counting down. + 0x1 + + + H_REVERSED + Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + 0x2 + + + + + + + RES + SCT conflict resolution register + 0x58 + 32 + read-write + 0 + 0xFFFFFFFF + + + O0RES + Effect of simultaneous set and clear on output 0. + 0 + 2 + read-write + + + NO_CHANGE + No change. + 0 + + + SET + Set output (or clear based on the SETCLR0 field in the OUTPUTDIRCTRL register). + 0x1 + + + CLEAR + Clear output (or set based on the SETCLR0 field). + 0x2 + + + TOGGLE_OUTPUT + Toggle output. + 0x3 + + + + + O1RES + Effect of simultaneous set and clear on output 1. + 2 + 2 + read-write + + + NO_CHANGE + No change. + 0 + + + SET + Set output (or clear based on the SETCLR1 field in the OUTPUTDIRCTRL register). + 0x1 + + + CLEAR + Clear output (or set based on the SETCLR1 field). + 0x2 + + + TOGGLE_OUTPUT + Toggle output. + 0x3 + + + + + O2RES + Effect of simultaneous set and clear on output 2. + 4 + 2 + read-write + + + NO_CHANGE + No change. + 0 + + + SET + Set output (or clear based on the SETCLR2 field in the OUTPUTDIRCTRL register). + 0x1 + + + CLEAR + Clear output n (or set based on the SETCLR2 field). + 0x2 + + + TOGGLE_OUTPUT + Toggle output. + 0x3 + + + + + O3RES + Effect of simultaneous set and clear on output 3. + 6 + 2 + read-write + + + NO_CHANGE + No change. + 0 + + + SET + Set output (or clear based on the SETCLR3 field in the OUTPUTDIRCTRL register). + 0x1 + + + CLEAR + Clear output (or set based on the SETCLR3 field). + 0x2 + + + TOGGLE_OUTPUT + Toggle output. + 0x3 + + + + + O4RES + Effect of simultaneous set and clear on output 4. + 8 + 2 + read-write + + + NO_CHANGE + No change. + 0 + + + SET + Set output (or clear based on the SETCLR4 field in the OUTPUTDIRCTRL register). + 0x1 + + + CLEAR + Clear output (or set based on the SETCLR4 field). + 0x2 + + + TOGGLE_OUTPUT + Toggle output. + 0x3 + + + + + O5RES + Effect of simultaneous set and clear on output 5. + 10 + 2 + read-write + + + NO_CHANGE + No change. + 0 + + + SET + Set output (or clear based on the SETCLR5 field in the OUTPUTDIRCTRL register). + 0x1 + + + CLEAR + Clear output (or set based on the SETCLR5 field). + 0x2 + + + TOGGLE_OUTPUT + Toggle output. + 0x3 + + + + + O6RES + Effect of simultaneous set and clear on output 6. + 12 + 2 + read-write + + + NO_CHANGE + No change. + 0 + + + SET + Set output (or clear based on the SETCLR6 field in the OUTPUTDIRCTRL register). + 0x1 + + + CLEAR + Clear output (or set based on the SETCLR6 field). + 0x2 + + + TOGGLE_OUTPUT + Toggle output. + 0x3 + + + + + O7RES + Effect of simultaneous set and clear on output 7. + 14 + 2 + read-write + + + NO_CHANGE + No change. + 0 + + + SET + Set output (or clear based on the SETCLR7 field in the OUTPUTDIRCTRL register). + 0x1 + + + CLEAR + Clear output n (or set based on the SETCLR7 field). + 0x2 + + + TOGGLE_OUTPUT + Toggle output. + 0x3 + + + + + O8RES + Effect of simultaneous set and clear on output 8. + 16 + 2 + read-write + + + NO_CHANGE + No change. + 0 + + + SET + Set output (or clear based on the SETCLR8 field in the OUTPUTDIRCTRL register). + 0x1 + + + CLEAR + Clear output (or set based on the SETCLR8 field). + 0x2 + + + TOGGLE_OUTPUT + Toggle output. + 0x3 + + + + + O9RES + Effect of simultaneous set and clear on output 9. + 18 + 2 + read-write + + + NO_CHANGE + No change. + 0 + + + SET + Set output (or clear based on the SETCLR9 field in the OUTPUTDIRCTRL register). + 0x1 + + + CLEAR + Clear output (or set based on the SETCLR9 field). + 0x2 + + + TOGGLE_OUTPUT + Toggle output. + 0x3 + + + + + O10RES + Effect of simultaneous set and clear on output 10. + 20 + 2 + read-write + + + NO_CHANGE + No change. + 0 + + + SET + Set output (or clear based on the SETCLR10 field in the OUTPUTDIRCTRL register). + 0x1 + + + CLEAR + Clear output (or set based on the SETCLR10 field). + 0x2 + + + TOGGLE_OUTPUT + Toggle output. + 0x3 + + + + + O11RES + Effect of simultaneous set and clear on output 11. + 22 + 2 + read-write + + + NO_CHANGE + No change. + 0 + + + SET + Set output (or clear based on the SETCLR11 field in the OUTPUTDIRCTRL register). + 0x1 + + + CLEAR + Clear output (or set based on the SETCLR11 field). + 0x2 + + + TOGGLE_OUTPUT + Toggle output. + 0x3 + + + + + O12RES + Effect of simultaneous set and clear on output 12. + 24 + 2 + read-write + + + NO_CHANGE + No change. + 0 + + + SET + Set output (or clear based on the SETCLR12 field in the OUTPUTDIRCTRL register). + 0x1 + + + CLEAR + Clear output (or set based on the SETCLR12 field). + 0x2 + + + TOGGLE_OUTPUT + Toggle output. + 0x3 + + + + + O13RES + Effect of simultaneous set and clear on output 13. + 26 + 2 + read-write + + + NO_CHANGE + No change. + 0 + + + SET + Set output (or clear based on the SETCLR13 field in the OUTPUTDIRCTRL register). + 0x1 + + + CLEAR + Clear output (or set based on the SETCLR13 field). + 0x2 + + + TOGGLE_OUTPUT + Toggle output. + 0x3 + + + + + O14RES + Effect of simultaneous set and clear on output 14. + 28 + 2 + read-write + + + NO_CHANGE + No change. + 0 + + + SET + Set output (or clear based on the SETCLR14 field in the OUTPUTDIRCTRL register). + 0x1 + + + CLEAR + Clear output (or set based on the SETCLR14 field). + 0x2 + + + TOGGLE_OUTPUT + Toggle output. + 0x3 + + + + + O15RES + Effect of simultaneous set and clear on output 15. + 30 + 2 + read-write + + + NO_CHANGE + No change. + 0 + + + SET + Set output (or clear based on the SETCLR15 field in the OUTPUTDIRCTRL register). + 0x1 + + + CLEAR + Clear output (or set based on the SETCLR15 field). + 0x2 + + + TOGGLE_OUTPUT + Toggle output. + 0x3 + + + + + + + DMA0REQUEST + SCT DMA request 0 register + 0x5C + 32 + read-write + 0 + 0xC000FFFF + + + DEV_0 + If bit n is one, event n triggers DMA request 0 (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. + 0 + 16 + read-write + + + DRL0 + A 1 in this bit triggers DMA request 0 when it loads the MATCH_L/Unified registers from the RELOAD_L/Unified registers. + 30 + 1 + read-write + + + DRQ0 + This read-only bit indicates the state of DMA Request 0. Note that if the related DMA channel is enabled and properly set up, it is unlikely that software will see this flag, it will be cleared rapidly by the DMA service. The flag remaining set could point to an issue with DMA setup. + 31 + 1 + read-write + + + + + DMA1REQUEST + SCT DMA request 1 register + 0x60 + 32 + read-write + 0 + 0xC000FFFF + + + DEV_1 + If bit n is one, event n triggers DMA request 1 (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. + 0 + 16 + read-write + + + DRL1 + A 1 in this bit triggers DMA request 1 when it loads the Match L/Unified registers from the Reload L/Unified registers. + 30 + 1 + read-write + + + DRQ1 + This read-only bit indicates the state of DMA Request 1. Note that if the related DMA channel is enabled and properly set up, it is unlikely that software will see this flag, it will be cleared rapidly by the DMA service. The flag remaining set could point to an issue with DMA setup. + 31 + 1 + read-write + + + + + EVEN + SCT event interrupt enable register + 0xF0 + 32 + read-write + 0 + 0xFFFF + + + IEN + The SCT requests an interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. + 0 + 16 + read-write + + + + + EVFLAG + SCT event flag register + 0xF4 + 32 + read-write + 0 + 0xFFFF + + + FLAG + Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. + 0 + 16 + read-write + + + + + CONEN + SCT conflict interrupt enable register + 0xF8 + 32 + read-write + 0 + 0xFFFF + + + NCEN + The SCT requests an interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of outputs in this SCT. + 0 + 16 + read-write + + + + + CONFLAG + SCT conflict flag register + 0xFC + 32 + read-write + 0 + 0xC000FFFF + + + NCFLAG + Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of outputs in this SCT. + 0 + 16 + read-write + + + BUSERRL + The most recent bus error from this SCT involved writing CTR L/Unified, STATE L/Unified, MATCH L/Unified, or the Output register when the L/U counter was not halted. A word write to certain L and H registers can be half successful and half unsuccessful. + 30 + 1 + read-write + + + BUSERRH + The most recent bus error from this SCT involved writing CTR H, STATE H, MATCH H, or the Output register when the H counter was not halted. + 31 + 1 + read-write + + + + + SCTCAP0 + SCT capture register of capture channel + CAP_MATCH + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPn_L + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. + 0 + 16 + read-write + + + CAPn_H + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. + 16 + 16 + read-write + + + + + SCTMATCH0 + SCT match value register of match channels + CAP_MATCH + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + MATCHn_L + When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. + 0 + 16 + read-write + + + MATCHn_H + When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. + 16 + 16 + read-write + + + + + SCTCAP1 + SCT capture register of capture channel + CAP_MATCH + 0x104 + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPn_L + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. + 0 + 16 + read-write + + + CAPn_H + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. + 16 + 16 + read-write + + + + + SCTMATCH1 + SCT match value register of match channels + CAP_MATCH + 0x104 + 32 + read-write + 0 + 0xFFFFFFFF + + + MATCHn_L + When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. + 0 + 16 + read-write + + + MATCHn_H + When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. + 16 + 16 + read-write + + + + + SCTCAP2 + SCT capture register of capture channel + CAP_MATCH + 0x108 + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPn_L + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. + 0 + 16 + read-write + + + CAPn_H + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. + 16 + 16 + read-write + + + + + SCTMATCH2 + SCT match value register of match channels + CAP_MATCH + 0x108 + 32 + read-write + 0 + 0xFFFFFFFF + + + MATCHn_L + When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. + 0 + 16 + read-write + + + MATCHn_H + When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. + 16 + 16 + read-write + + + + + SCTCAP3 + SCT capture register of capture channel + CAP_MATCH + 0x10C + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPn_L + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. + 0 + 16 + read-write + + + CAPn_H + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. + 16 + 16 + read-write + + + + + SCTMATCH3 + SCT match value register of match channels + CAP_MATCH + 0x10C + 32 + read-write + 0 + 0xFFFFFFFF + + + MATCHn_L + When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. + 0 + 16 + read-write + + + MATCHn_H + When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. + 16 + 16 + read-write + + + + + SCTCAP4 + SCT capture register of capture channel + CAP_MATCH + 0x110 + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPn_L + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. + 0 + 16 + read-write + + + CAPn_H + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. + 16 + 16 + read-write + + + + + SCTMATCH4 + SCT match value register of match channels + CAP_MATCH + 0x110 + 32 + read-write + 0 + 0xFFFFFFFF + + + MATCHn_L + When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. + 0 + 16 + read-write + + + MATCHn_H + When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. + 16 + 16 + read-write + + + + + SCTCAP5 + SCT capture register of capture channel + CAP_MATCH + 0x114 + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPn_L + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. + 0 + 16 + read-write + + + CAPn_H + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. + 16 + 16 + read-write + + + + + SCTMATCH5 + SCT match value register of match channels + CAP_MATCH + 0x114 + 32 + read-write + 0 + 0xFFFFFFFF + + + MATCHn_L + When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. + 0 + 16 + read-write + + + MATCHn_H + When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. + 16 + 16 + read-write + + + + + SCTCAP6 + SCT capture register of capture channel + CAP_MATCH + 0x118 + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPn_L + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. + 0 + 16 + read-write + + + CAPn_H + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. + 16 + 16 + read-write + + + + + SCTMATCH6 + SCT match value register of match channels + CAP_MATCH + 0x118 + 32 + read-write + 0 + 0xFFFFFFFF + + + MATCHn_L + When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. + 0 + 16 + read-write + + + MATCHn_H + When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. + 16 + 16 + read-write + + + + + SCTCAP7 + SCT capture register of capture channel + CAP_MATCH + 0x11C + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPn_L + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. + 0 + 16 + read-write + + + CAPn_H + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. + 16 + 16 + read-write + + + + + SCTMATCH7 + SCT match value register of match channels + CAP_MATCH + 0x11C + 32 + read-write + 0 + 0xFFFFFFFF + + + MATCHn_L + When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. + 0 + 16 + read-write + + + MATCHn_H + When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. + 16 + 16 + read-write + + + + + SCTCAP8 + SCT capture register of capture channel + CAP_MATCH + 0x120 + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPn_L + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. + 0 + 16 + read-write + + + CAPn_H + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. + 16 + 16 + read-write + + + + + SCTMATCH8 + SCT match value register of match channels + CAP_MATCH + 0x120 + 32 + read-write + 0 + 0xFFFFFFFF + + + MATCHn_L + When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. + 0 + 16 + read-write + + + MATCHn_H + When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. + 16 + 16 + read-write + + + + + SCTCAP9 + SCT capture register of capture channel + CAP_MATCH + 0x124 + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPn_L + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. + 0 + 16 + read-write + + + CAPn_H + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. + 16 + 16 + read-write + + + + + SCTMATCH9 + SCT match value register of match channels + CAP_MATCH + 0x124 + 32 + read-write + 0 + 0xFFFFFFFF + + + MATCHn_L + When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. + 0 + 16 + read-write + + + MATCHn_H + When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. + 16 + 16 + read-write + + + + + SCTCAP10 + SCT capture register of capture channel + CAP_MATCH + 0x128 + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPn_L + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. + 0 + 16 + read-write + + + CAPn_H + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. + 16 + 16 + read-write + + + + + SCTMATCH10 + SCT match value register of match channels + CAP_MATCH + 0x128 + 32 + read-write + 0 + 0xFFFFFFFF + + + MATCHn_L + When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. + 0 + 16 + read-write + + + MATCHn_H + When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. + 16 + 16 + read-write + + + + + SCTCAP11 + SCT capture register of capture channel + CAP_MATCH + 0x12C + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPn_L + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. + 0 + 16 + read-write + + + CAPn_H + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. + 16 + 16 + read-write + + + + + SCTMATCH11 + SCT match value register of match channels + CAP_MATCH + 0x12C + 32 + read-write + 0 + 0xFFFFFFFF + + + MATCHn_L + When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. + 0 + 16 + read-write + + + MATCHn_H + When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. + 16 + 16 + read-write + + + + + SCTCAP12 + SCT capture register of capture channel + CAP_MATCH + 0x130 + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPn_L + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. + 0 + 16 + read-write + + + CAPn_H + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. + 16 + 16 + read-write + + + + + SCTMATCH12 + SCT match value register of match channels + CAP_MATCH + 0x130 + 32 + read-write + 0 + 0xFFFFFFFF + + + MATCHn_L + When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. + 0 + 16 + read-write + + + MATCHn_H + When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. + 16 + 16 + read-write + + + + + SCTCAP13 + SCT capture register of capture channel + CAP_MATCH + 0x134 + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPn_L + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. + 0 + 16 + read-write + + + CAPn_H + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. + 16 + 16 + read-write + + + + + SCTMATCH13 + SCT match value register of match channels + CAP_MATCH + 0x134 + 32 + read-write + 0 + 0xFFFFFFFF + + + MATCHn_L + When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. + 0 + 16 + read-write + + + MATCHn_H + When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. + 16 + 16 + read-write + + + + + SCTCAP14 + SCT capture register of capture channel + CAP_MATCH + 0x138 + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPn_L + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. + 0 + 16 + read-write + + + CAPn_H + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. + 16 + 16 + read-write + + + + + SCTMATCH14 + SCT match value register of match channels + CAP_MATCH + 0x138 + 32 + read-write + 0 + 0xFFFFFFFF + + + MATCHn_L + When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. + 0 + 16 + read-write + + + MATCHn_H + When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. + 16 + 16 + read-write + + + + + SCTCAP15 + SCT capture register of capture channel + CAP_MATCH + 0x13C + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPn_L + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. + 0 + 16 + read-write + + + CAPn_H + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. + 16 + 16 + read-write + + + + + SCTMATCH15 + SCT match value register of match channels + CAP_MATCH + 0x13C + 32 + read-write + 0 + 0xFFFFFFFF + + + MATCHn_L + When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. + 0 + 16 + read-write + + + MATCHn_H + When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. + 16 + 16 + read-write + + + + + SCTCAPCTRL0 + SCT capture control register + CAPCTRL_MATCHREL + 0x200 + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPCONn_L + If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. + 0 + 16 + read-write + + + CAPCONn_H + If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. + 16 + 16 + read-write + + + + + SCTMATCHREL0 + SCT match reload value register + CAPCTRL_MATCHREL + 0x200 + 32 + read-write + 0 + 0xFFFFFFFF + + + RELOADn_L + When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. + 0 + 16 + read-write + + + RELOADn_H + When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. + 16 + 16 + read-write + + + + + SCTCAPCTRL1 + SCT capture control register + CAPCTRL_MATCHREL + 0x204 + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPCONn_L + If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. + 0 + 16 + read-write + + + CAPCONn_H + If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. + 16 + 16 + read-write + + + + + SCTMATCHREL1 + SCT match reload value register + CAPCTRL_MATCHREL + 0x204 + 32 + read-write + 0 + 0xFFFFFFFF + + + RELOADn_L + When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. + 0 + 16 + read-write + + + RELOADn_H + When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. + 16 + 16 + read-write + + + + + SCTCAPCTRL2 + SCT capture control register + CAPCTRL_MATCHREL + 0x208 + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPCONn_L + If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. + 0 + 16 + read-write + + + CAPCONn_H + If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. + 16 + 16 + read-write + + + + + SCTMATCHREL2 + SCT match reload value register + CAPCTRL_MATCHREL + 0x208 + 32 + read-write + 0 + 0xFFFFFFFF + + + RELOADn_L + When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. + 0 + 16 + read-write + + + RELOADn_H + When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. + 16 + 16 + read-write + + + + + SCTCAPCTRL3 + SCT capture control register + CAPCTRL_MATCHREL + 0x20C + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPCONn_L + If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. + 0 + 16 + read-write + + + CAPCONn_H + If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. + 16 + 16 + read-write + + + + + SCTMATCHREL3 + SCT match reload value register + CAPCTRL_MATCHREL + 0x20C + 32 + read-write + 0 + 0xFFFFFFFF + + + RELOADn_L + When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. + 0 + 16 + read-write + + + RELOADn_H + When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. + 16 + 16 + read-write + + + + + SCTCAPCTRL4 + SCT capture control register + CAPCTRL_MATCHREL + 0x210 + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPCONn_L + If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. + 0 + 16 + read-write + + + CAPCONn_H + If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. + 16 + 16 + read-write + + + + + SCTMATCHREL4 + SCT match reload value register + CAPCTRL_MATCHREL + 0x210 + 32 + read-write + 0 + 0xFFFFFFFF + + + RELOADn_L + When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. + 0 + 16 + read-write + + + RELOADn_H + When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. + 16 + 16 + read-write + + + + + SCTCAPCTRL5 + SCT capture control register + CAPCTRL_MATCHREL + 0x214 + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPCONn_L + If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. + 0 + 16 + read-write + + + CAPCONn_H + If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. + 16 + 16 + read-write + + + + + SCTMATCHREL5 + SCT match reload value register + CAPCTRL_MATCHREL + 0x214 + 32 + read-write + 0 + 0xFFFFFFFF + + + RELOADn_L + When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. + 0 + 16 + read-write + + + RELOADn_H + When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. + 16 + 16 + read-write + + + + + SCTCAPCTRL6 + SCT capture control register + CAPCTRL_MATCHREL + 0x218 + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPCONn_L + If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. + 0 + 16 + read-write + + + CAPCONn_H + If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. + 16 + 16 + read-write + + + + + SCTMATCHREL6 + SCT match reload value register + CAPCTRL_MATCHREL + 0x218 + 32 + read-write + 0 + 0xFFFFFFFF + + + RELOADn_L + When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. + 0 + 16 + read-write + + + RELOADn_H + When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. + 16 + 16 + read-write + + + + + SCTCAPCTRL7 + SCT capture control register + CAPCTRL_MATCHREL + 0x21C + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPCONn_L + If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. + 0 + 16 + read-write + + + CAPCONn_H + If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. + 16 + 16 + read-write + + + + + SCTMATCHREL7 + SCT match reload value register + CAPCTRL_MATCHREL + 0x21C + 32 + read-write + 0 + 0xFFFFFFFF + + + RELOADn_L + When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. + 0 + 16 + read-write + + + RELOADn_H + When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. + 16 + 16 + read-write + + + + + SCTCAPCTRL8 + SCT capture control register + CAPCTRL_MATCHREL + 0x220 + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPCONn_L + If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. + 0 + 16 + read-write + + + CAPCONn_H + If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. + 16 + 16 + read-write + + + + + SCTMATCHREL8 + SCT match reload value register + CAPCTRL_MATCHREL + 0x220 + 32 + read-write + 0 + 0xFFFFFFFF + + + RELOADn_L + When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. + 0 + 16 + read-write + + + RELOADn_H + When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. + 16 + 16 + read-write + + + + + SCTCAPCTRL9 + SCT capture control register + CAPCTRL_MATCHREL + 0x224 + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPCONn_L + If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. + 0 + 16 + read-write + + + CAPCONn_H + If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. + 16 + 16 + read-write + + + + + SCTMATCHREL9 + SCT match reload value register + CAPCTRL_MATCHREL + 0x224 + 32 + read-write + 0 + 0xFFFFFFFF + + + RELOADn_L + When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. + 0 + 16 + read-write + + + RELOADn_H + When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. + 16 + 16 + read-write + + + + + SCTCAPCTRL10 + SCT capture control register + CAPCTRL_MATCHREL + 0x228 + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPCONn_L + If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. + 0 + 16 + read-write + + + CAPCONn_H + If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. + 16 + 16 + read-write + + + + + SCTMATCHREL10 + SCT match reload value register + CAPCTRL_MATCHREL + 0x228 + 32 + read-write + 0 + 0xFFFFFFFF + + + RELOADn_L + When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. + 0 + 16 + read-write + + + RELOADn_H + When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. + 16 + 16 + read-write + + + + + SCTCAPCTRL11 + SCT capture control register + CAPCTRL_MATCHREL + 0x22C + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPCONn_L + If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. + 0 + 16 + read-write + + + CAPCONn_H + If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. + 16 + 16 + read-write + + + + + SCTMATCHREL11 + SCT match reload value register + CAPCTRL_MATCHREL + 0x22C + 32 + read-write + 0 + 0xFFFFFFFF + + + RELOADn_L + When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. + 0 + 16 + read-write + + + RELOADn_H + When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. + 16 + 16 + read-write + + + + + SCTCAPCTRL12 + SCT capture control register + CAPCTRL_MATCHREL + 0x230 + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPCONn_L + If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. + 0 + 16 + read-write + + + CAPCONn_H + If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. + 16 + 16 + read-write + + + + + SCTMATCHREL12 + SCT match reload value register + CAPCTRL_MATCHREL + 0x230 + 32 + read-write + 0 + 0xFFFFFFFF + + + RELOADn_L + When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. + 0 + 16 + read-write + + + RELOADn_H + When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. + 16 + 16 + read-write + + + + + SCTCAPCTRL13 + SCT capture control register + CAPCTRL_MATCHREL + 0x234 + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPCONn_L + If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. + 0 + 16 + read-write + + + CAPCONn_H + If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. + 16 + 16 + read-write + + + + + SCTMATCHREL13 + SCT match reload value register + CAPCTRL_MATCHREL + 0x234 + 32 + read-write + 0 + 0xFFFFFFFF + + + RELOADn_L + When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. + 0 + 16 + read-write + + + RELOADn_H + When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. + 16 + 16 + read-write + + + + + SCTCAPCTRL14 + SCT capture control register + CAPCTRL_MATCHREL + 0x238 + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPCONn_L + If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. + 0 + 16 + read-write + + + CAPCONn_H + If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. + 16 + 16 + read-write + + + + + SCTMATCHREL14 + SCT match reload value register + CAPCTRL_MATCHREL + 0x238 + 32 + read-write + 0 + 0xFFFFFFFF + + + RELOADn_L + When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. + 0 + 16 + read-write + + + RELOADn_H + When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. + 16 + 16 + read-write + + + + + SCTCAPCTRL15 + SCT capture control register + CAPCTRL_MATCHREL + 0x23C + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPCONn_L + If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. + 0 + 16 + read-write + + + CAPCONn_H + If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. + 16 + 16 + read-write + + + + + SCTMATCHREL15 + SCT match reload value register + CAPCTRL_MATCHREL + 0x23C + 32 + read-write + 0 + 0xFFFFFFFF + + + RELOADn_L + When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. + 0 + 16 + read-write + + + RELOADn_H + When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. + 16 + 16 + read-write + + + + + 16 + 0x8 + EVENT[%s] + no description available + 0x300 + + STATE + SCT event state register 0 + 0 + 32 + read-write + 0 + 0xFFFF + + + STATEMSKn + If bit m is one, event n happens in state m of the counter selected by the HEVENT bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of bits = number of states in this SCT. + 0 + 16 + read-write + + + + + CTRL + SCT event control register 0 + 0x4 + 32 + read-write + 0 + 0x7FFFFF + + + MATCHSEL + Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running. + 0 + 4 + read-write + + + HEVENT + Select L/H counter. Do not set this bit if UNIFY = 1. + 4 + 1 + read-write + + + L_COUNTER + Selects the L state and the L match register selected by MATCHSEL. + 0 + + + H_COUNTER + Selects the H state and the H match register selected by MATCHSEL. + 0x1 + + + + + OUTSEL + Input/output select + 5 + 1 + read-write + + + INPUT + Selects the inputs selected by IOSEL. + 0 + + + OUTPUT + Selects the outputs selected by IOSEL. + 0x1 + + + + + IOSEL + Selects the input or output signal number associated with this event (if any). Do not select an input in this register if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event. + 6 + 4 + read-write + + + IOCOND + Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period . + 10 + 2 + read-write + + + LOW + LOW + 0 + + + RISE + Rise + 0x1 + + + FALL + Fall + 0x2 + + + HIGH + HIGH + 0x3 + + + + + COMBMODE + Selects how the specified match and I/O condition are used and combined. + 12 + 2 + read-write + + + OR + OR. The event occurs when either the specified match or I/O condition occurs. + 0 + + + MATCH + MATCH. Uses the specified match only. + 0x1 + + + IO + IO. Uses the specified I/O condition only. + 0x2 + + + AND + AND. The event occurs when the specified match and I/O condition occur simultaneously. + 0x3 + + + + + STATELD + This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state. + 14 + 1 + read-write + + + ADD + STATEV value is added into STATE (the carry-out is ignored). + 0 + + + LOAD + STATEV value is loaded into STATE. + 0x1 + + + + + STATEV + This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value. + 15 + 5 + read-write + + + MATCHMEM + If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value. + 20 + 1 + read-write + + + DIRECTION + Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved. + 21 + 2 + read-write + + + DIRECTION_INDEPENDENT + Direction independent. This event is triggered regardless of the count direction. + 0 + + + COUNTING_UP + Counting up. This event is triggered only during up-counting when BIDIR = 1. + 0x1 + + + COUNTING_DOWN + Counting down. This event is triggered only during down-counting when BIDIR = 1. + 0x2 + + + + + + + + 10 + 0x8 + OUT[%s] + no description available + 0x500 + + SET + SCT output 0 set register + 0 + 32 + read-write + 0 + 0xFFFF + + + SET + A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output 0 = bit 0, output 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register. + 0 + 16 + read-write + + + + + CLR + SCT output 0 clear register + 0x4 + 32 + read-write + 0 + 0xFFFF + + + CLR + A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register. + 0 + 16 + read-write + + + + + + + + FLEXCOMM0 + Flexcomm serial communication + FLEXCOMM + FLEXCOMM + 0x40086000 + + 0 + 0x1000 + registers + + + FLEXCOMM0 + 14 + + + + PSELID + Peripheral Select and Flexcomm ID register. + 0xFF8 + 32 + read-write + 0x101000 + 0xFFFFF0FF + + + PERSEL + Peripheral Select. This field is writable by software. + 0 + 3 + read-write + + + NO_PERIPH_SELECTED + No peripheral selected. + 0 + + + USART + USART function selected. + 0x1 + + + SPI + SPI function selected. + 0x2 + + + I2C + I2C function selected. + 0x3 + + + I2S_TRANSMIT + I2S transmit function selected. + 0x4 + + + I2S_RECEIVE + I2S receive function selected. + 0x5 + + + + + LOCK + Lock the peripheral select. This field is writable by software. + 3 + 1 + read-write + + + UNLOCKED + Peripheral select can be changed by software. + 0 + + + LOCKED + Peripheral select is locked and cannot be changed until this Flexcomm or the entire device is reset. + 0x1 + + + + + USARTPRESENT + USART present indicator. This field is Read-only. + 4 + 1 + read-only + + + NOT_PRESENT + This Flexcomm does not include the USART function. + 0 + + + PRESENT + This Flexcomm includes the USART function. + 0x1 + + + + + SPIPRESENT + SPI present indicator. This field is Read-only. + 5 + 1 + read-only + + + NOT_PRESENT + This Flexcomm does not include the SPI function. + 0 + + + PRESENT + This Flexcomm includes the SPI function. + 0x1 + + + + + I2CPRESENT + I2C present indicator. This field is Read-only. + 6 + 1 + read-only + + + NOT_PRESENT + This Flexcomm does not include the I2C function. + 0 + + + PRESENT + This Flexcomm includes the I2C function. + 0x1 + + + + + I2SPRESENT + I 2S present indicator. This field is Read-only. + 7 + 1 + read-only + + + NOT_PRESENT + This Flexcomm does not include the I2S function. + 0 + + + PRESENT + This Flexcomm includes the I2S function. + 0x1 + + + + + ID + Flexcomm ID. + 12 + 20 + read-only + + + + + PID + Peripheral identification register. + 0xFFC + 32 + read-only + 0 + 0xFFFFFFFF + + + Aperture + no description available + 0 + 8 + read-only + + + Minor_Rev + Minor revision of module implementation. + 8 + 4 + read-only + + + Major_Rev + Major revision of module implementation. + 12 + 4 + read-only + + + ID + Module identifier for the selected function. + 16 + 16 + read-only + + + + + + + FLEXCOMM1 + Flexcomm serial communication + FLEXCOMM + 0x40087000 + + 0 + 0x1000 + registers + + + FLEXCOMM1 + 15 + + + + FLEXCOMM2 + Flexcomm serial communication + FLEXCOMM + 0x40088000 + + 0 + 0x1000 + registers + + + FLEXCOMM2 + 16 + + + + FLEXCOMM3 + Flexcomm serial communication + FLEXCOMM + 0x40089000 + + 0 + 0x1000 + registers + + + FLEXCOMM3 + 17 + + + + FLEXCOMM4 + Flexcomm serial communication + FLEXCOMM + 0x4008A000 + + 0 + 0x1000 + registers + + + FLEXCOMM4 + 18 + + + + FLEXCOMM5 + Flexcomm serial communication + FLEXCOMM + 0x40096000 + + 0 + 0x1000 + registers + + + FLEXCOMM5 + 19 + + + + FLEXCOMM6 + Flexcomm serial communication + FLEXCOMM + 0x40097000 + + 0 + 0x1000 + registers + + + FLEXCOMM6 + 20 + + + + FLEXCOMM7 + Flexcomm serial communication + FLEXCOMM + 0x40098000 + + 0 + 0x1000 + registers + + + FLEXCOMM7 + 21 + + + + FLEXCOMM8 + Flexcomm serial communication + FLEXCOMM + 0x4009F000 + + 0 + 0x1000 + registers + + + FLEXCOMM8 + 59 + + + + I2C0 + I2C-bus interfaces + FLEXCOMM0 + I2C + I2C + 0x40086000 + + 0 + 0x1000 + registers + + + FLEXCOMM0 + 14 + + + + CFG + Configuration for shared functions. + 0x800 + 32 + read-write + 0 + 0x3F + + + MSTEN + Master Enable. When disabled, configurations settings for the Master function are not changed, but the Master function is internally reset. + 0 + 1 + read-write + + + DISABLED + Disabled. The I2C Master function is disabled. + 0 + + + ENABLED + Enabled. The I2C Master function is enabled. + 0x1 + + + + + SLVEN + Slave Enable. When disabled, configurations settings for the Slave function are not changed, but the Slave function is internally reset. + 1 + 1 + read-write + + + DISABLED + Disabled. The I2C slave function is disabled. + 0 + + + ENABLED + Enabled. The I2C slave function is enabled. + 0x1 + + + + + MONEN + Monitor Enable. When disabled, configurations settings for the Monitor function are not changed, but the Monitor function is internally reset. + 2 + 1 + read-write + + + DISABLED + Disabled. The I2C Monitor function is disabled. + 0 + + + ENABLED + Enabled. The I2C Monitor function is enabled. + 0x1 + + + + + TIMEOUTEN + I2C bus Time-out Enable. When disabled, the time-out function is internally reset. + 3 + 1 + read-write + + + DISABLED + Disabled. Time-out function is disabled. + 0 + + + ENABLED + Enabled. Time-out function is enabled. Both types of time-out flags will be generated and will cause interrupts if they are enabled. Typically, only one time-out will be used in a system. + 0x1 + + + + + MONCLKSTR + Monitor function Clock Stretching. + 4 + 1 + read-write + + + DISABLED + Disabled. The Monitor function will not perform clock stretching. Software or DMA may not always be able to read data provided by the Monitor function before it is overwritten. This mode may be used when non-invasive monitoring is critical. + 0 + + + ENABLED + Enabled. The Monitor function will perform clock stretching in order to ensure that software or DMA can read all incoming data supplied by the Monitor function. + 0x1 + + + + + HSCAPABLE + High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter, as well as the timing for certain I2C signalling, enabling High-speed mode applies to all functions: Master, Slave, and Monitor. + 5 + 1 + read-write + + + FAST_MODE_PLUS + Fast-mode plus. The I 2C interface will support Standard-mode, Fast-mode, and Fast-mode Plus, to the extent that the pin electronics support these modes. Any changes that need to be made to the pin controls, such as changing the drive strength or filtering, must be made by software via the IOCON register associated with each I2C pin, + 0 + + + HIGH_SPEED + High-speed. In addition to Standard-mode, Fast-mode, and Fast-mode Plus, the I 2C interface will support High-speed mode to the extent that the pin electronics support these modes. See Section 25.7.2.2 for more information. + 0x1 + + + + + + + STAT + Status register for Master, Slave, and Monitor functions. + 0x804 + 32 + read-write + 0x801 + 0x30FFF5F + + + MSTPENDING + Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending, the MSTSTATE bits indicate what type of software service if any the master expects. This flag will cause an interrupt when set if, enabled via the INTENSET register. The MSTPENDING flag is not set when the DMA is handling an event (if the MSTDMA bit in the MSTCTL register is set). If the master is in the idle state, and no communication is needed, mask this interrupt. + 0 + 1 + read-only + + + IN_PROGRESS + In progress. Communication is in progress and the Master function is busy and cannot currently accept a command. + 0 + + + PENDING + Pending. The Master function needs software service or is in the idle state. If the master is not in the idle state, it is waiting to receive or transmit data or the NACK bit. + 0x1 + + + + + MSTSTATE + Master State code. The master state code reflects the master state when the MSTPENDING bit is set, that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All other values are reserved. See Table 400 for details of state values and appropriate responses. + 1 + 3 + read-only + + + IDLE + Idle. The Master function is available to be used for a new transaction. + 0 + + + RECEIVE_READY + Receive ready. Received data available (Master Receiver mode). Address plus Read was previously sent and Acknowledged by slave. + 0x1 + + + TRANSMIT_READY + Transmit ready. Data can be transmitted (Master Transmitter mode). Address plus Write was previously sent and Acknowledged by slave. + 0x2 + + + NACK_ADDRESS + NACK Address. Slave NACKed address. + 0x3 + + + NACK_DATA + NACK Data. Slave NACKed transmitted data. + 0x4 + + + + + MSTARBLOSS + Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE. + 4 + 1 + read-write + + + NO_LOSS + No Arbitration Loss has occurred. + 0 + + + ARBITRATION_LOSS + Arbitration loss. The Master function has experienced an Arbitration Loss. At this point, the Master function has already stopped driving the bus and gone to an idle state. Software can respond by doing nothing, or by sending a Start in order to attempt to gain control of the bus when it next becomes idle. + 0x1 + + + + + MSTSTSTPERR + Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE. + 6 + 1 + read-write + + + NO_ERROR + No Start/Stop Error has occurred. + 0 + + + ERROR + The Master function has experienced a Start/Stop Error. A Start or Stop was detected at a time when it is not allowed by the I2C specification. The Master interface has stopped driving the bus and gone to an idle state, no action is required. A request for a Start could be made, or software could attempt to insure that the bus has not stalled. + 0x1 + + + + + SLVPENDING + Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is handling an event (if the SLVDMA bit in the SLVCTL register is set). The SLVPENDING flag is read-only and is automatically cleared when a 1 is written to the SLVCONTINUE bit in the SLVCTL register. The point in time when SlvPending is set depends on whether the I2C interface is in HSCAPABLE mode. See Section 25.7.2.2.2. When the I2C interface is configured to be HSCAPABLE, HS master codes are detected automatically. Due to the requirements of the HS I2C specification, slave addresses must also be detected automatically, since the address must be acknowledged before the clock can be stretched. + 8 + 1 + read-only + + + IN_PROGRESS + In progress. The Slave function does not currently need service. + 0 + + + PENDING + Pending. The Slave function needs service. Information on what is needed can be found in the adjacent SLVSTATE field. + 0x1 + + + + + SLVSTATE + Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled are affected by DMA mode and Automatic Operation modes. + 9 + 2 + read-only + + + SLAVE_ADDRESS + Slave address. Address plus R/W received. At least one of the four slave addresses has been matched by hardware. + 0 + + + SLAVE_RECEIVE + Slave receive. Received data is available (Slave Receiver mode). + 0x1 + + + SLAVE_TRANSMIT + Slave transmit. Data can be transmitted (Slave Transmitter mode). + 0x2 + + + + + SLVNOTSTR + Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in real time. + 11 + 1 + read-only + + + STRETCHING + Stretching. The slave function is currently stretching the I2C bus clock. Deep-Sleep or Power-down mode cannot be entered at this time. + 0 + + + NOT_STRETCHING + Not stretching. The slave function is not currently stretching the I 2C bus clock. Deep-sleep or Power-down mode could be entered at this time. + 0x1 + + + + + SLVIDX + Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers, and provides an identification of the address that was matched. It is possible that more than one address could be matched, but only one match can be reported here. + 12 + 2 + read-only + + + ADDRESS0 + Address 0. Slave address 0 was matched. + 0 + + + ADDRESS1 + Address 1. Slave address 1 was matched. + 0x1 + + + ADDRESS2 + Address 2. Slave address 2 was matched. + 0x2 + + + ADDRESS3 + Address 3. Slave address 3 was matched. + 0x3 + + + + + SLVSEL + Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address, or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that does not match an enabled address on the Slave function, when slave software decides to NACK a matched address, when there is a Stop detected on the bus, when the master NACKs slave data, and in some combinations of Automatic Operation. SLVSEL is not cleared if software NACKs data. + 14 + 1 + read-only + + + NOT_SELECTED + Not selected. The Slave function is not currently selected. + 0 + + + SELECTED + Selected. The Slave function is currently selected. + 0x1 + + + + + SLVDESEL + Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit. + 15 + 1 + read-write + + + NOT_DESELECTED + Not deselected. The Slave function has not become deselected. This does not mean that it is currently selected. That information can be found in the SLVSEL flag. + 0 + + + DESELECTED + Deselected. The Slave function has become deselected. This is specifically caused by the SLVSEL flag changing from 1 to 0. See the description of SLVSEL for details on when that event occurs. + 0x1 + + + + + MONRDY + Monitor Ready. This flag is cleared when the MONRXDAT register is read. + 16 + 1 + read-only + + + NO_DATA + No data. The Monitor function does not currently have data available. + 0 + + + DATA_WAITING + Data waiting. The Monitor function has data waiting to be read. + 0x1 + + + + + MONOV + Monitor Overflow flag. + 17 + 1 + read-write + + + NO_OVERRUN + No overrun. Monitor data has not overrun. + 0 + + + OVERRUN + Overrun. A Monitor data overrun has occurred. This can only happen when Monitor clock stretching not enabled via the MONCLKSTR bit in the CFG register. Writing 1 to this bit clears the flag. + 0x1 + + + + + MONACTIVE + Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop. + 18 + 1 + read-only + + + INACTIVE + Inactive. The Monitor function considers the I2C bus to be inactive. + 0 + + + ACTIVE + Active. The Monitor function considers the I2C bus to be active. + 0x1 + + + + + MONIDLE + Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when set if enabled via the INTENSET register. The flag can be cleared by writing a 1 to this bit. + 19 + 1 + read-write + + + NOT_IDLE + Not idle. The I2C bus is not idle, or this flag has been cleared by software. + 0 + + + IDLE + Idle. The I2C bus has gone idle at least once since the last time this flag was cleared by software. + 0x1 + + + + + EVENTTIMEOUT + Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start, Stop, and clock edges. The flag is cleared by writing a 1 to this bit. No time-out is created when the I2C-bus is idle. + 24 + 1 + read-write + + + NO_TIMEOUT + No time-out. I2C bus events have not caused a time-out. + 0 + + + EVEN_TIMEOUT + Event time-out. The time between I2C bus events has been longer than the time specified by the TIMEOUT register. + 0x1 + + + + + SCLTIMEOUT + SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit. + 25 + 1 + read-write + + + NO_TIMEOUT + No time-out. SCL low time has not caused a time-out. + 0 + + + TIMEOUT + Time-out. SCL low time has caused a time-out. + 0x1 + + + + + + + INTENSET + Interrupt Enable Set and read register. + 0x808 + 32 + read-write + 0 + 0x30B8951 + + + MSTPENDINGEN + Master Pending interrupt Enable. + 0 + 1 + read-write + + + DISABLED + Disabled. The MstPending interrupt is disabled. + 0 + + + ENABLED + Enabled. The MstPending interrupt is enabled. + 0x1 + + + + + MSTARBLOSSEN + Master Arbitration Loss interrupt Enable. + 4 + 1 + read-write + + + DISABLED + Disabled. The MstArbLoss interrupt is disabled. + 0 + + + ENABLED + Enabled. The MstArbLoss interrupt is enabled. + 0x1 + + + + + MSTSTSTPERREN + Master Start/Stop Error interrupt Enable. + 6 + 1 + read-write + + + DISABLED + Disabled. The MstStStpErr interrupt is disabled. + 0 + + + ENABLED + Enabled. The MstStStpErr interrupt is enabled. + 0x1 + + + + + SLVPENDINGEN + Slave Pending interrupt Enable. + 8 + 1 + read-write + + + DISABLED + Disabled. The SlvPending interrupt is disabled. + 0 + + + ENABLED + Enabled. The SlvPending interrupt is enabled. + 0x1 + + + + + SLVNOTSTREN + Slave Not Stretching interrupt Enable. + 11 + 1 + read-write + + + DISABLED + Disabled. The SlvNotStr interrupt is disabled. + 0 + + + ENABLED + Enabled. The SlvNotStr interrupt is enabled. + 0x1 + + + + + SLVDESELEN + Slave Deselect interrupt Enable. + 15 + 1 + read-write + + + DISABLED + Disabled. The SlvDeSel interrupt is disabled. + 0 + + + ENABLED + Enabled. The SlvDeSel interrupt is enabled. + 0x1 + + + + + MONRDYEN + Monitor data Ready interrupt Enable. + 16 + 1 + read-write + + + DISABLED + Disabled. The MonRdy interrupt is disabled. + 0 + + + ENABLED + Enabled. The MonRdy interrupt is enabled. + 0x1 + + + + + MONOVEN + Monitor Overrun interrupt Enable. + 17 + 1 + read-write + + + DISABLED + Disabled. The MonOv interrupt is disabled. + 0 + + + ENABLED + Enabled. The MonOv interrupt is enabled. + 0x1 + + + + + MONIDLEEN + Monitor Idle interrupt Enable. + 19 + 1 + read-write + + + DISABLED + Disabled. The MonIdle interrupt is disabled. + 0 + + + ENABLED + Enabled. The MonIdle interrupt is enabled. + 0x1 + + + + + EVENTTIMEOUTEN + Event time-out interrupt Enable. + 24 + 1 + read-write + + + DISABLED + Disabled. The Event time-out interrupt is disabled. + 0 + + + ENABLED + Enabled. The Event time-out interrupt is enabled. + 0x1 + + + + + SCLTIMEOUTEN + SCL time-out interrupt Enable. + 25 + 1 + read-write + + + DISABLED + Disabled. The SCL time-out interrupt is disabled. + 0 + + + ENABLED + Enabled. The SCL time-out interrupt is enabled. + 0x1 + + + + + + + INTENCLR + Interrupt Enable Clear register. + 0x80C + 32 + write-only + 0 + 0 + + + MSTPENDINGCLR + Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented. + 0 + 1 + write-only + + + MSTARBLOSSCLR + Master Arbitration Loss interrupt clear. + 4 + 1 + write-only + + + MSTSTSTPERRCLR + Master Start/Stop Error interrupt clear. + 6 + 1 + write-only + + + SLVPENDINGCLR + Slave Pending interrupt clear. + 8 + 1 + write-only + + + SLVNOTSTRCLR + Slave Not Stretching interrupt clear. + 11 + 1 + write-only + + + SLVDESELCLR + Slave Deselect interrupt clear. + 15 + 1 + write-only + + + MONRDYCLR + Monitor data Ready interrupt clear. + 16 + 1 + write-only + + + MONOVCLR + Monitor Overrun interrupt clear. + 17 + 1 + write-only + + + MONIDLECLR + Monitor Idle interrupt clear. + 19 + 1 + write-only + + + EVENTTIMEOUTCLR + Event time-out interrupt clear. + 24 + 1 + write-only + + + SCLTIMEOUTCLR + SCL time-out interrupt clear. + 25 + 1 + write-only + + + + + TIMEOUT + Time-out value register. + 0x810 + 32 + read-write + 0xFFFF + 0xFFFF + + + TOMIN + Time-out time value, bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks. + 0 + 4 + read-write + + + TO + Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks, as defined by the CLKDIV register. To change this value while I2C is in operation, disable all time-outs, write a new value to TIMEOUT, then re-enable time-outs. 0x000 = A time-out will occur after 16 counts of the I2C function clock. 0x001 = A time-out will occur after 32 counts of the I2C function clock. 0xFFF = A time-out will occur after 65,536 counts of the I2C function clock. + 4 + 12 + read-write + + + + + CLKDIV + Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function. + 0x814 + 32 + read-write + 0 + 0xFFFF + + + DIVVAL + This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3 before use. 0xFFFF = FCLK is divided by 65,536 before use. + 0 + 16 + read-write + + + + + INTSTAT + Interrupt Status register for Master, Slave, and Monitor functions. + 0x818 + 32 + read-only + 0x801 + 0x30B8951 + + + MSTPENDING + Master Pending. + 0 + 1 + read-only + + + MSTARBLOSS + Master Arbitration Loss flag. + 4 + 1 + read-only + + + MSTSTSTPERR + Master Start/Stop Error flag. + 6 + 1 + read-only + + + SLVPENDING + Slave Pending. + 8 + 1 + read-only + + + SLVNOTSTR + Slave Not Stretching status. + 11 + 1 + read-only + + + SLVDESEL + Slave Deselected flag. + 15 + 1 + read-only + + + MONRDY + Monitor Ready. + 16 + 1 + read-only + + + MONOV + Monitor Overflow flag. + 17 + 1 + read-only + + + MONIDLE + Monitor Idle flag. + 19 + 1 + read-only + + + EVENTTIMEOUT + Event time-out Interrupt flag. + 24 + 1 + read-only + + + SCLTIMEOUT + SCL time-out Interrupt flag. + 25 + 1 + read-only + + + + + MSTCTL + Master control register. + 0x820 + 32 + read-write + 0 + 0xE + + + MSTCONTINUE + Master Continue. This bit is write-only. + 0 + 1 + write-only + + + NO_EFFECT + No effect. + 0 + + + CONTINUE + Continue. Informs the Master function to continue to the next operation. This must done after writing transmit data, reading received data, or any other housekeeping related to the next bus operation. + 0x1 + + + + + MSTSTART + Master Start control. This bit is write-only. + 1 + 1 + read-write + + + NO_EFFECT + No effect. + 0 + + + START + Start. A Start will be generated on the I2C bus at the next allowed time. + 0x1 + + + + + MSTSTOP + Master Stop control. This bit is write-only. + 2 + 1 + read-write + + + NO_EFFECT + No effect. + 0 + + + STOP + Stop. A Stop will be generated on the I2C bus at the next allowed time, preceded by a NACK to the slave if the master is receiving data from the slave (Master Receiver mode). + 0x1 + + + + + MSTDMA + Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start, address, Stop, and address match must always be done with software, typically via an interrupt. Address acknowledgement must also be done by software except when the I2C is configured to be HSCAPABLE (and address acknowledgement is handled entirely by hardware) or when Automatic Operation is enabled. When a DMA data transfer is complete, MSTDMA must be cleared prior to beginning the next operation, typically a Start or Stop.This bit is read/write. + 3 + 1 + read-write + + + DISABLED + Disable. No DMA requests are generated for master operation. + 0 + + + ENABLED + Enable. A DMA request is generated for I2C master data operations. When this I2C master is generating Acknowledge bits in Master Receiver mode, the acknowledge is generated automatically. + 0x1 + + + + + + + MSTTIME + Master timing configuration. + 0x824 + 32 + read-write + 0x77 + 0x77 + + + MSTSCLLOW + Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C bus specification parameters tBUF and tSU;STA have the same values and are also controlled by MSTSCLLOW. + 0 + 3 + read-write + + + CLOCKS_2 + 2 clocks. Minimum SCL low time is 2 clocks of the I2C clock pre-divider. + 0 + + + CLOCKS_3 + 3 clocks. Minimum SCL low time is 3 clocks of the I2C clock pre-divider. + 0x1 + + + CLOCKS_4 + 4 clocks. Minimum SCL low time is 4 clocks of the I2C clock pre-divider. + 0x2 + + + CLOCKS_5 + 5 clocks. Minimum SCL low time is 5 clocks of the I2C clock pre-divider. + 0x3 + + + CLOCKS_6 + 6 clocks. Minimum SCL low time is 6 clocks of the I2C clock pre-divider. + 0x4 + + + CLOCKS_7 + 7 clocks. Minimum SCL low time is 7 clocks of the I2C clock pre-divider. + 0x5 + + + CLOCKS_8 + 8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider. + 0x6 + + + CLOCKS_9 + 9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider. + 0x7 + + + + + MSTSCLHIGH + Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH. + 4 + 3 + read-write + + + CLOCKS_2 + 2 clocks. Minimum SCL high time is 2 clock of the I2C clock pre-divider. + 0 + + + CLOCKS_3 + 3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider . + 0x1 + + + CLOCKS_4 + 4 clocks. Minimum SCL high time is 4 clock of the I2C clock pre-divider. + 0x2 + + + CLOCKS_5 + 5 clocks. Minimum SCL high time is 5 clock of the I2C clock pre-divider. + 0x3 + + + CLOCKS_6 + 6 clocks. Minimum SCL high time is 6 clock of the I2C clock pre-divider. + 0x4 + + + CLOCKS_7 + 7 clocks. Minimum SCL high time is 7 clock of the I2C clock pre-divider. + 0x5 + + + CLOCKS_8 + 8 clocks. Minimum SCL high time is 8 clock of the I2C clock pre-divider. + 0x6 + + + CLOCKS_9 + 9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider. + 0x7 + + + + + + + MSTDAT + Combined Master receiver and transmitter data register. + 0x828 + 32 + read-write + 0 + 0xFF + + + DATA + Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function. + 0 + 8 + read-write + + + + + SLVCTL + Slave control register. + 0x840 + 32 + read-write + 0 + 0x30B + + + SLVCONTINUE + Slave Continue. + 0 + 1 + read-write + + + NO_EFFECT + No effect. + 0 + + + CONTINUE + Continue. Informs the Slave function to continue to the next operation, by clearing the SLVPENDING flag in the STAT register. This must be done after writing transmit data, reading received data, or any other housekeeping related to the next bus operation. Automatic Operation has different requirements. SLVCONTINUE should not be set unless SLVPENDING = 1. + 0x1 + + + + + SLVNACK + Slave NACK. + 1 + 1 + read-write + + + NO_EFFECT + No effect. + 0 + + + NACK + NACK. Causes the Slave function to NACK the master when the slave is receiving data from the master (Slave Receiver mode). + 0x1 + + + + + SLVDMA + Slave DMA enable. + 3 + 1 + read-write + + + DISABLED + Disabled. No DMA requests are issued for Slave mode operation. + 0 + + + ENABLED + Enabled. DMA requests are issued for I2C slave data transmission and reception. + 0x1 + + + + + AUTOACK + Automatic Acknowledge.When this bit is set, it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit is clear and a header matches SLVADR0, the behavior is controlled by AUTONACK in the SLVADR0 register: allowing NACK or interrupt. + 8 + 1 + read-write + + + NORMAL + Normal, non-automatic operation. If AUTONACK = 0, an SlvPending interrupt is generated when a matching address is received. If AUTONACK = 1, received addresses are NACKed (ignored). + 0 + + + AUTOMATIC_ACK + A header with matching SLVADR0 and matching direction as set by AUTOMATCHREAD will be ACKed immediately, allowing the master to move on to the data bytes. If the address matches SLVADR0, but the direction does not match AUTOMATCHREAD, the behavior will depend on the AUTONACK bit in the SLVADR0 register: if AUTONACK is set, then it will be Nacked; else if AUTONACK is clear, then a SlvPending interrupt is generated. + 0x1 + + + + + AUTOMATCHREAD + When AUTOACK is set, this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction, the direction needs to be specified. This bit allows a direction to be chosen for the next operation. + 9 + 1 + read-write + + + I2C_WRITE + The expected next operation in Automatic Mode is an I2C write. + 0 + + + I2C_READ + The expected next operation in Automatic Mode is an I2C read. + 0x1 + + + + + + + SLVDAT + Combined Slave receiver and transmitter data register. + 0x844 + 32 + read-write + 0 + 0xFF + + + DATA + Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function. + 0 + 8 + read-write + + + + + 4 + 0x4 + SLVADR[%s] + Slave address register. + 0x848 + 32 + read-write + 0x1 + 0xFF + + + SADISABLE + Slave Address n Disable. + 0 + 1 + read-write + + + ENABLED + Enabled. Slave Address n is enabled. + 0 + + + DISABLED + Ignored Slave Address n is ignored. + 0x1 + + + + + SLVADR + Slave Address. Seven bit slave address that is compared to received addresses if enabled. + 1 + 7 + read-write + + + AUTONACK + Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD, allows software to ignore I2C traffic while handling previous I2C data or other operations. + 15 + 1 + read-write + + + NORMAL + Normal operation, matching I2C addresses are not ignored. + 0 + + + AUTOMATIC + Automatic-only mode. All incoming addresses are ignored (NACKed), unless AUTOACK is set, it matches SLVADRn, and AUTOMATCHREAD matches the direction. + 0x1 + + + + + + + SLVQUAL0 + Slave Qualification for address 0. + 0x858 + 32 + read-write + 0 + 0xFF + + + QUALMODE0 + Qualify mode for slave address 0. + 0 + 1 + read-write + + + MASK + Mask. The SLVQUAL0 field is used as a logical mask for matching address 0. + 0 + + + EXTEND + Extend. The SLVQUAL0 field is used to extend address 0 matching in a range of addresses. + 0x1 + + + + + SLVQUAL0 + Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is, assuming that it is enabled. If QUALMODE0 = 0, any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of the received address when it is compared to the SLVADR0 register. If QUALMODE0 = 1, an address range is matched for address 0. This range extends from the value defined by SLVADR0 to the address defined by SLVQUAL0 (address matches when SLVADR0[7:1] <= received address <= SLVQUAL0[7:1]). + 1 + 7 + read-write + + + + + MONRXDAT + Monitor receiver data register. + 0x880 + 32 + read-only + 0 + 0x7FF + + + MONRXDAT + Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins. + 0 + 8 + read-only + + + MONSTART + Monitor Received Start. + 8 + 1 + read-only + + + NO_START_DETECTED + No start detected. The Monitor function has not detected a Start event on the I2C bus. + 0 + + + START_DETECTED + Start detected. The Monitor function has detected a Start event on the I2C bus. + 0x1 + + + + + MONRESTART + Monitor Received Repeated Start. + 9 + 1 + read-only + + + NOT_DETECTED + No repeated start detected. The Monitor function has not detected a Repeated Start event on the I2C bus. + 0 + + + DETECTED + Repeated start detected. The Monitor function has detected a Repeated Start event on the I2C bus. + 0x1 + + + + + MONNACK + Monitor Received NACK. + 10 + 1 + read-only + + + ACKNOWLEDGED + Acknowledged. The data currently being provided by the Monitor function was acknowledged by at least one master or slave receiver. + 0 + + + NOT_ACKNOWLEDGED + Not acknowledged. The data currently being provided by the Monitor function was not acknowledged by any receiver. + 0x1 + + + + + + + ID + Peripheral identification register. + 0xFFC + 32 + read-only + 0 + 0xFFFFFFFF + + + APERTURE + Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture. + 0 + 8 + read-only + + + MINOR_REV + Minor revision of module implementation. + 8 + 4 + read-only + + + MAJOR_REV + Major revision of module implementation. + 12 + 4 + read-only + + + ID + Module identifier for the selected function. + 16 + 16 + read-only + + + + + + + I2C1 + I2C-bus interfaces + FLEXCOMM1 + I2C + 0x40087000 + + 0 + 0x1000 + registers + + + FLEXCOMM1 + 15 + + + + I2C2 + I2C-bus interfaces + FLEXCOMM2 + I2C + 0x40088000 + + 0 + 0x1000 + registers + + + FLEXCOMM2 + 16 + + + + I2C3 + I2C-bus interfaces + FLEXCOMM3 + I2C + 0x40089000 + + 0 + 0x1000 + registers + + + FLEXCOMM3 + 17 + + + + I2C4 + I2C-bus interfaces + FLEXCOMM4 + I2C + 0x4008A000 + + 0 + 0x1000 + registers + + + FLEXCOMM4 + 18 + + + + I2C5 + I2C-bus interfaces + FLEXCOMM5 + I2C + 0x40096000 + + 0 + 0x1000 + registers + + + FLEXCOMM5 + 19 + + + + I2C6 + I2C-bus interfaces + FLEXCOMM6 + I2C + 0x40097000 + + 0 + 0x1000 + registers + + + FLEXCOMM6 + 20 + + + + I2C7 + I2C-bus interfaces + FLEXCOMM7 + I2C + 0x40098000 + + 0 + 0x1000 + registers + + + FLEXCOMM7 + 21 + + + + I2S0 + I2S interface + FLEXCOMM0 + I2S + I2S + 0x40086000 + + 0 + 0x1000 + registers + + + FLEXCOMM0 + 14 + + + + 3 + 0x20 + SECCHANNEL[%s] + no description available + 0 + + PCFG1 + Configuration register 1 for channel pair + 0xC20 + 32 + read-write + 0 + 0x401 + + + PAIRENABLE + Enable for this channel pair.. + 0 + 1 + read-write + + + ONECHANNEL + Single channel mode. + 10 + 1 + read-write + + + + + PCFG2 + Configuration register 2 for channel pair + 0xC24 + 32 + read-write + 0 + 0x1FF0000 + + + POSITION + Data Position. + 16 + 9 + read-write + + + + + PSTAT + Status register for channel pair + 0xC28 + 32 + read-write + 0 + 0xF + + + BUSY + Busy status for this channel pair. + 0 + 1 + read-write + + + SLVFRMERR + Save Frame Error flag. + 1 + 1 + read-write + + + LR + Left/Right indication. + 2 + 1 + read-write + + + DATAPAUSED + Data Paused status flag. + 3 + 1 + read-only + + + + + + CFG1 + Configuration register 1 for the primary channel pair. + 0xC00 + 32 + read-write + 0 + 0x1F3FFF + + + MAINENABLE + Main enable for I 2S function in this Flexcomm + 0 + 1 + read-write + + + DISABLED + All I 2S channel pairs in this Flexcomm are disabled and the internal state machines, counters, and flags are reset. No other channel pairs can be enabled. + 0 + + + ENABLED + This I 2S channel pair is enabled. Other channel pairs in this Flexcomm may be enabled in their individual PAIRENABLE bits. + 0x1 + + + + + DATAPAUSE + Data flow Pause. Allows pausing data flow between the I2S serializer/deserializer and the FIFO. This could be done in order to change streams, or while restarting after a data underflow or overflow. When paused, FIFO operations can be done without corrupting data that is in the process of being sent or received. Once a data pause has been requested, the interface may need to complete sending data that was in progress before interrupting the flow of data. Software must check that the pause is actually in effect before taking action. This is done by monitoring the DATAPAUSED flag in the STAT register. When DATAPAUSE is cleared, data transfer will resume at the beginning of the next frame. + 1 + 1 + read-write + + + NORMAL + Normal operation, or resuming normal operation at the next frame if the I2S has already been paused. + 0 + + + PAUSE + A pause in the data flow is being requested. It is in effect when DATAPAUSED in STAT = 1. + 0x1 + + + + + PAIRCOUNT + Provides the number of I2S channel pairs in this Flexcomm This is a read-only field whose value may be different in other Flexcomms. 00 = there is 1 I2S channel pair in this Flexcomm. 01 = there are 2 I2S channel pairs in this Flexcomm. 10 = there are 3 I2S channel pairs in this Flexcomm. 11 = there are 4 I2S channel pairs in this Flexcomm. + 2 + 2 + read-write + + + PAIRS_1 + 1 I2S channel pairs in this flexcomm + 0 + + + PAIRS_2 + 2 I2S channel pairs in this flexcomm + 0x1 + + + PAIRS_3 + 3 I2S channel pairs in this flexcomm + 0x2 + + + PAIRS_4 + 4 I2S channel pairs in this flexcomm + 0x3 + + + + + MSTSLVCFG + Master / slave configuration selection, determining how SCK and WS are used by all channel pairs in this Flexcomm. + 4 + 2 + read-write + + + NORMAL_SLAVE_MODE + Normal slave mode, the default mode. SCK and WS are received from a master and used to transmit or receive data. + 0 + + + WS_SYNC_MASTER + WS synchronized master. WS is received from another master and used to synchronize the generation of SCK, when divided from the Flexcomm function clock. + 0x1 + + + MASTER_USING_SCK + Master using an existing SCK. SCK is received and used directly to generate WS, as well as transmitting or receiving data. + 0x2 + + + NORMAL_MASTER + Normal master mode. SCK and WS are generated so they can be sent to one or more slave devices. + 0x3 + + + + + MODE + Selects the basic I2S operating mode. Other configurations modify this to obtain all supported cases. See Formats and modes for examples. + 6 + 2 + read-write + + + CLASSIC_MODE + I2S mode a.k.a. 'classic' mode. WS has a 50% duty cycle, with (for each enabled channel pair) one piece of left channel data occurring during the first phase, and one pieces of right channel data occurring during the second phase. In this mode, the data region begins one clock after the leading WS edge for the frame. For a 50% WS duty cycle, FRAMELEN must define an even number of I2S clocks for the frame. If FRAMELEN defines an odd number of clocks per frame, the extra clock will occur on the right. + 0 + + + DSP_MODE_WS_50_DUTYCYCLE + DSP mode where WS has a 50% duty cycle. See remark for mode 0. + 0x1 + + + DSP_MODE_WS_1_CLOCK + DSP mode where WS has a one clock long pulse at the beginning of each data frame. + 0x2 + + + DSP_MODE_WS_1_DATA + DSP mode where WS has a one data slot long pulse at the beginning of each data frame. + 0x3 + + + + + RIGHTLOW + Right channel data is in the Low portion of FIFO data. Essentially, this swaps left and right channel data as it is transferred to or from the FIFO. This bit is not used if the data width is greater than 24 bits or if PDMDATA = 1. Note that if the ONECHANNEL field (bit 10 of this register) = 1, the one channel to be used is the nominally the left channel. POSITION can still place that data in the frame where right channel data is normally located. if all enabled channel pairs have ONECHANNEL = 1, then RIGHTLOW = 1 is not allowed. + 8 + 1 + read-write + + + RIGHT_HIGH + The right channel is taken from the high part of the FIFO data. For example, when data is 16 bits, FIFO bits 31:16 are used for the right channel. + 0 + + + RIGHT_LOW + The right channel is taken from the low part of the FIFO data. For example, when data is 16 bits, FIFO bits 15:0 are used for the right channel. + 0x1 + + + + + LEFTJUST + Left Justify data. + 9 + 1 + read-write + + + RIGHT_JUSTIFIED + Data is transferred between the FIFO and the I2S serializer/deserializer right justified, i.e. starting from bit 0 and continuing to the position defined by DATALEN. This would correspond to right justified data in the stream on the data bus. + 0 + + + LEFT_JUSTIFIED + Data is transferred between the FIFO and the I2S serializer/deserializer left justified, i.e. starting from the MSB of the FIFO entry and continuing for the number of bits defined by DATALEN. This would correspond to left justified data in the stream on the data bus. + 0x1 + + + + + ONECHANNEL + Single channel mode. Applies to both transmit and receive. This configuration bit applies only to the first I2S channel pair. Other channel pairs may select this mode independently in their separate CFG1 registers. + 10 + 1 + read-write + + + DUAL_CHANNEL + I2S data for this channel pair is treated as left and right channels. + 0 + + + SINGLE_CHANNEL + I2S data for this channel pair is treated as a single channel, functionally the left channel for this pair. In mode 0 only, the right side of the frame begins at POSITION = 0x100. This is because mode 0 makes a clear distinction between the left and right sides of the frame. When ONECHANNEL = 1, the single channel of data may be placed on the right by setting POSITION to 0x100 + the data position within the right side (e.g. 0x108 would place data starting at the 8th clock after the middle of the frame). In other modes, data for the single channel of data is placed at the clock defined by POSITION. + 0x1 + + + + + PDMDATA + PDM Data selection. This bit controls the data source for I2S transmit, and cannot be set in Rx mode. This bit only has an effect if the device the Flexcomm resides in includes a D-Mic subsystem. For the LPC55xx, this bit applies only to Flexcomm 6,7. + 11 + 1 + read-write + + + NORMAL + Normal operation, data is transferred to or from the Flexcomm FIFO. + 0 + + + DMIC_SUBSYSTEM + The data source is the D-Mic subsystem. When PDMDATA = 1, only the primary channel pair can be used in this Flexcomm. If ONECHANNEL = 1, only the PDM left data is used. the WS rate must match the Fs (sample rate) of the D-Mic decimator. A rate mismatch will at some point cause the I2S to overrun or underrun. + 0x1 + + + + + SCK_POL + SCK polarity. + 12 + 1 + read-write + + + FALLING_EDGE + Data is launched on SCK falling edges and sampled on SCK rising edges (standard for I2S). + 0 + + + RISING_EDGE + Data is launched on SCK rising edges and sampled on SCK falling edges. + 0x1 + + + + + WS_POL + WS polarity. + 13 + 1 + read-write + + + NOT_INVERTED + Data frames begin at a falling edge of WS (standard for classic I2S). + 0 + + + INVERTED + WS is inverted, resulting in a data frame beginning at a rising edge of WS (standard for most 'non-classic' variations of I2S). + 0x1 + + + + + DATALEN + Data Length, minus 1 encoded, defines the number of data bits to be transmitted or received for all I2S channel pairs in this Flexcomm. Note that data is only driven to or received from SDA for the number of bits defined by DATALEN. DATALEN is also used in these ways by the I2S: Determines the size of data transfers between the FIFO and the I2S serializer/deserializer. See FIFO buffer configurations and usage In mode 1, 2, and 3, determines the location of right data following left data in the frame. In mode 3 (where WS has a one data slot long pulse at the beginning of each data frame) determines the duration of the WS pulse. Values: 0x00 to 0x02 = not supported 0x03 = data is 4 bits in length 0x04 = data is 5 bits in length 0x1F = data is 32 bits in length + 16 + 5 + read-write + + + + + CFG2 + Configuration register 2 for the primary channel pair. + 0xC04 + 32 + read-write + 0 + 0x1FF01FF + + + FRAMELEN + Frame Length, minus 1 encoded, defines the number of clocks and data bits in the frames that this channel pair participates in. See Frame format. 0x000 to 0x002 = not supported 0x003 = frame is 4 bits in total length 0x004 = frame is 5 bits in total length 0x1FF = frame is 512 bits in total length if FRAMELEN is an defines an odd length frame (e.g. 33 clocks) in mode 0 or 1, the extra clock appears in the right half. When MODE = 3, FRAMELEN must be larger than DATALEN in order for the WS pulse to be generated correctly. + 0 + 9 + read-write + + + POSITION + Data Position. Defines the location within the frame of the data for this channel pair. POSITION + DATALEN must be less than FRAMELEN. See Frame format. When MODE = 0, POSITION defines the location of data in both the left phase and right phase, starting one clock after the WS edge. In other modes, POSITION defines the location of data within the entire frame. ONECHANNEL = 1 while MODE = 0 is a special case, see the description of ONECHANNEL. The combination of DATALEN and the POSITION fields of all channel pairs must be made such that the channels do not overlap within the frame. 0x000 = data begins at bit position 0 (the first bit position) within the frame or WS phase. 0x001 = data begins at bit position 1 within the frame or WS phase. 0x002 = data begins at bit position 2 within the frame or WS phase. + 16 + 9 + read-write + + + + + STAT + Status register for the primary channel pair. + 0xC08 + 32 + read-write + 0 + 0xD + + + BUSY + Busy status for the primary channel pair. Other BUSY flags may be found in the STAT register for each channel pair. + 0 + 1 + read-only + + + IDLE + The transmitter/receiver for channel pair is currently idle. + 0 + + + BUSY + The transmitter/receiver for channel pair is currently processing data. + 0x1 + + + + + SLVFRMERR + Slave Frame Error flag. This applies when at least one channel pair is operating as a slave. An error indicates that the incoming WS signal did not transition as expected due to a mismatch between FRAMELEN and the actual incoming I2S stream. + 1 + 1 + write-only + + + NO_ERROR + No error has been recorded. + 0 + + + ERROR + An error has been recorded for some channel pair that is operating in slave mode. ERROR is cleared by writing a 1 to this bit position. + 0x1 + + + + + LR + Left/Right indication. This flag is considered to be a debugging aid and is not expected to be used by an I2S driver. Valid when one channel pair is busy. Indicates left or right data being processed for the currently busy channel pair. + 2 + 1 + read-only + + + LEFT_CHANNEL + Left channel. + 0 + + + RIGHT_CHANNEL + Right channel. + 0x1 + + + + + DATAPAUSED + Data Paused status flag. Applies to all I2S channels + 3 + 1 + read-only + + + NOT_PAUSED + Data is not currently paused. A data pause may have been requested but is not yet in force, waiting for an allowed pause point. Refer to the description of the DATAPAUSE control bit in the CFG1 register. + 0 + + + PAUSED + A data pause has been requested and is now in force. + 0x1 + + + + + + + DIV + Clock divider, used by all channel pairs. + 0xC1C + 32 + read-write + 0 + 0xFFF + + + DIV + This field controls how this I2S block uses the Flexcomm function clock. 0x000 = The Flexcomm function clock is used directly. 0x001 = The Flexcomm function clock is divided by 2. 0x002 = The Flexcomm function clock is divided by 3. 0xFFF = The Flexcomm function clock is divided by 4,096. + 0 + 12 + read-write + + + + + FIFOCFG + FIFO configuration and enable register. + 0xE00 + 32 + read-write + 0 + 0x7F033 + + + ENABLETX + Enable the transmit FIFO. + 0 + 1 + read-write + + + DISABLED + The transmit FIFO is not enabled. + 0 + + + ENABLED + The transmit FIFO is enabled. + 0x1 + + + + + ENABLERX + Enable the receive FIFO. + 1 + 1 + read-write + + + DISABLED + The receive FIFO is not enabled. + 0 + + + ENABLED + The receive FIFO is enabled. + 0x1 + + + + + TXI2SE0 + Transmit I2S empty 0. Determines the value sent by the I2S in transmit mode if the TX FIFO becomes empty. This value is sent repeatedly until the I2S is paused, the error is cleared, new data is provided, and the I2S is un-paused. + 2 + 1 + read-write + + + LAST_VALUE + If the TX FIFO becomes empty, the last value is sent. This setting may be used when the data length is 24 bits or less, or when MONO = 1 for this channel pair. + 0 + + + ZERO + If the TX FIFO becomes empty, 0 is sent. Use if the data length is greater than 24 bits or if zero fill is preferred. + 0x1 + + + + + PACK48 + Packing format for 48-bit data. This relates to how data is entered into or taken from the FIFO by software or DMA. + 3 + 1 + read-write + + + BIT_24 + 48-bit I2S FIFO entries are handled as all 24-bit values. + 0 + + + BIT_32_16 + 48-bit I2S FIFO entries are handled as alternating 32-bit and 16-bit values. + 0x1 + + + + + SIZE + FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART. + 4 + 2 + read-only + + + DMATX + DMA configuration for transmit. + 12 + 1 + read-write + + + DISABLED + DMA is not used for the transmit function. + 0 + + + ENABLED + Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. + 0x1 + + + + + DMARX + DMA configuration for receive. + 13 + 1 + read-write + + + DISABLED + DMA is not used for the receive function. + 0 + + + ENABLED + Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. + 0x1 + + + + + WAKETX + Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register. + 14 + 1 + read-write + + + DISABLED + Only enabled interrupts will wake up the device form reduced power modes. + 0 + + + ENABLED + A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in FIFOTRIG, even when the TXLVL interrupt is not enabled. + 0x1 + + + + + WAKERX + Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register. + 15 + 1 + read-write + + + DISABLED + Only enabled interrupts will wake up the device form reduced power modes. + 0 + + + ENABLED + A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in FIFOTRIG, even when the RXLVL interrupt is not enabled. + 0x1 + + + + + EMPTYTX + Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied. + 16 + 1 + read-write + + + EMPTYRX + Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied. + 17 + 1 + read-write + + + POPDBG + Pop FIFO for debug reads. + 18 + 1 + read-write + + + DO_NOT_POP + Debug reads of the FIFO do not pop the FIFO. + 0 + + + POP + A debug read will cause the FIFO to pop. + 0x1 + + + + + + + FIFOSTAT + FIFO status register. + 0xE04 + 32 + read-write + 0x30 + 0x1F1FFB + + + TXERR + TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit. + 0 + 1 + read-write + + + RXERR + RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit. + 1 + 1 + read-write + + + PERINT + Peripheral interrupt. When 1, this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register. + 3 + 1 + read-only + + + TXEMPTY + Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data. + 4 + 1 + read-only + + + TXNOTFULL + Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be written. When 0, the transmit FIFO is full and another write would cause it to overflow. + 5 + 1 + read-only + + + RXNOTEMPTY + Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty. + 6 + 1 + read-only + + + RXFULL + Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow. + 7 + 1 + read-only + + + TXLVL + Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be 0. + 8 + 5 + read-only + + + RXLVL + Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be 1. + 16 + 5 + read-only + + + + + FIFOTRIG + FIFO trigger settings for interrupt and DMA request. + 0xE08 + 32 + read-write + 0 + 0xF0F03 + + + TXLVLENA + Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set. + 0 + 1 + read-write + + + DISABLED + Transmit FIFO level does not generate a FIFO level trigger. + 0 + + + ENABLED + An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register. + 0x1 + + + + + RXLVLENA + Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. + 1 + 1 + read-write + + + DISABLED + Receive FIFO level does not generate a FIFO level trigger. + 0 + + + ENABLED + An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. + 0x1 + + + + + TXLVL + Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX FIFO level decreases to 15 entries (is no longer full). + 8 + 4 + read-write + + + RXLVL + Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX FIFO has received 16 entries (has become full). + 16 + 4 + read-write + + + + + FIFOINTENSET + FIFO interrupt enable set (enable) and read register. + 0xE10 + 32 + read-write + 0 + 0xF + + + TXERR + Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. + 0 + 1 + read-write + + + DISABLED + No interrupt will be generated for a transmit error. + 0 + + + ENABLED + An interrupt will be generated when a transmit error occurs. + 0x1 + + + + + RXERR + Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. + 1 + 1 + read-write + + + DISABLED + No interrupt will be generated for a receive error. + 0 + + + ENABLED + An interrupt will be generated when a receive error occurs. + 0x1 + + + + + TXLVL + Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. + 2 + 1 + read-write + + + DISABLED + No interrupt will be generated based on the TX FIFO level. + 0 + + + ENABLED + If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases to the level specified by TXLVL in the FIFOTRIG register. + 0x1 + + + + + RXLVL + Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. + 3 + 1 + read-write + + + DISABLED + No interrupt will be generated based on the RX FIFO level. + 0 + + + ENABLED + If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level increases to the level specified by RXLVL in the FIFOTRIG register. + 0x1 + + + + + + + FIFOINTENCLR + FIFO interrupt enable clear (disable) and read register. + 0xE14 + 32 + read-write + 0 + 0xF + + + TXERR + Writing one clears the corresponding bits in the FIFOINTENSET register. + 0 + 1 + read-write + + + RXERR + Writing one clears the corresponding bits in the FIFOINTENSET register. + 1 + 1 + read-write + + + TXLVL + Writing one clears the corresponding bits in the FIFOINTENSET register. + 2 + 1 + read-write + + + RXLVL + Writing one clears the corresponding bits in the FIFOINTENSET register. + 3 + 1 + read-write + + + + + FIFOINTSTAT + FIFO interrupt status register. + 0xE18 + 32 + read-only + 0 + 0x1F + + + TXERR + TX FIFO error. + 0 + 1 + read-only + + + RXERR + RX FIFO error. + 1 + 1 + read-only + + + TXLVL + Transmit FIFO level interrupt. + 2 + 1 + read-only + + + RXLVL + Receive FIFO level interrupt. + 3 + 1 + read-only + + + PERINT + Peripheral interrupt. + 4 + 1 + read-only + + + + + FIFOWR + FIFO write data. + 0xE20 + 32 + write-only + 0 + 0 + + + TXDATA + Transmit data to the FIFO. The number of bits used depends on configuration details. + 0 + 32 + write-only + + + + + FIFOWR48H + FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. + 0xE24 + 32 + write-only + 0 + 0 + + + TXDATA + Transmit data to the FIFO. Whether this register is used and the number of bits used depends on configuration details. + 0 + 24 + write-only + + + + + FIFORD + FIFO read data. + 0xE30 + 32 + read-only + 0 + 0 + + + RXDATA + Received data from the FIFO. The number of bits used depends on configuration details. + 0 + 32 + read-only + + + + + FIFORD48H + FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. + 0xE34 + 32 + read-only + 0 + 0xFFFFFF + + + RXDATA + Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details. + 0 + 24 + read-only + + + + + FIFORDNOPOP + FIFO data read with no FIFO pop. + 0xE40 + 32 + read-only + 0 + 0 + + + RXDATA + Received data from the FIFO. + 0 + 32 + read-only + + + + + FIFORD48HNOPOP + FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. + 0xE44 + 32 + read-only + 0 + 0xFFFFFF + + + RXDATA + Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details. + 0 + 24 + read-only + + + + + ID + I2S Module identification + 0xFFC + 32 + read-only + 0xE0900000 + 0xFFFFFFFF + + + Aperture + Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture. + 0 + 8 + read-only + + + Minor_Rev + Minor revision of module implementation, starting at 0. + 8 + 4 + read-only + + + Major_Rev + Major revision of module implementation, starting at 0. + 12 + 4 + read-only + + + ID + Unique module identifier for this IP block. + 16 + 16 + read-only + + + + + + + I2S1 + I2S interface + FLEXCOMM1 + I2S + 0x40087000 + + 0 + 0x1000 + registers + + + FLEXCOMM1 + 15 + + + + I2S2 + I2S interface + FLEXCOMM2 + I2S + 0x40088000 + + 0 + 0x1000 + registers + + + FLEXCOMM2 + 16 + + + + I2S3 + I2S interface + FLEXCOMM3 + I2S + 0x40089000 + + 0 + 0x1000 + registers + + + FLEXCOMM3 + 17 + + + + I2S4 + I2S interface + FLEXCOMM4 + I2S + 0x4008A000 + + 0 + 0x1000 + registers + + + FLEXCOMM4 + 18 + + + + I2S5 + I2S interface + FLEXCOMM5 + I2S + 0x40096000 + + 0 + 0x1000 + registers + + + FLEXCOMM5 + 19 + + + + I2S6 + I2S interface + FLEXCOMM6 + I2S + 0x40097000 + + 0 + 0x1000 + registers + + + FLEXCOMM6 + 20 + + + + I2S7 + I2S interface + FLEXCOMM7 + I2S + 0x40098000 + + 0 + 0x1000 + registers + + + FLEXCOMM7 + 21 + + + + SPI0 + Serial Peripheral Interfaces (SPI) + FLEXCOMM0 + SPI + SPI + 0x40086000 + + 0 + 0x1000 + registers + + + FLEXCOMM0 + 14 + + + + CFG + SPI Configuration register + 0x400 + 32 + read-write + 0 + 0xFBD + + + ENABLE + SPI enable. + 0 + 1 + read-write + + + DISABLED + Disabled. The SPI is disabled and the internal state machine and counters are reset. + 0 + + + ENABLED + Enabled. The SPI is enabled for operation. + 0x1 + + + + + MASTER + Master mode select. + 2 + 1 + read-write + + + SLAVE_MODE + Slave mode. The SPI will operate in slave mode. SCK, MOSI, and the SSEL signals are inputs, MISO is an output. + 0 + + + MASTER_MODE + Master mode. The SPI will operate in master mode. SCK, MOSI, and the SSEL signals are outputs, MISO is an input. + 0x1 + + + + + LSBF + LSB First mode enable. + 3 + 1 + read-write + + + STANDARD + Standard. Data is transmitted and received in standard MSB first order. + 0 + + + REVERSE + Reverse. Data is transmitted and received in reverse order (LSB first). + 0x1 + + + + + CPHA + Clock Phase select. + 4 + 1 + read-write + + + CHANGE + Change. The SPI captures serial data on the first clock transition of the transfer (when the clock changes away from the rest state). Data is changed on the following edge. + 0 + + + CAPTURE + Capture. The SPI changes serial data on the first clock transition of the transfer (when the clock changes away from the rest state). Data is captured on the following edge. + 0x1 + + + + + CPOL + Clock Polarity select. + 5 + 1 + read-write + + + LOW + Low. The rest state of the clock (between transfers) is low. + 0 + + + HIGH + High. The rest state of the clock (between transfers) is high. + 0x1 + + + + + LOOP + Loopback mode enable. Loopback mode applies only to Master mode, and connects transmit and receive data connected together to allow simple software testing. + 7 + 1 + read-write + + + DISABLED + Disabled. + 0 + + + ENABLED + Enabled. + 0x1 + + + + + SPOL0 + SSEL0 Polarity select. + 8 + 1 + read-write + + + LOW + Low. The SSEL0 pin is active low. + 0 + + + HIGH + High. The SSEL0 pin is active high. + 0x1 + + + + + SPOL1 + SSEL1 Polarity select. + 9 + 1 + read-write + + + LOW + Low. The SSEL1 pin is active low. + 0 + + + HIGH + High. The SSEL1 pin is active high. + 0x1 + + + + + SPOL2 + SSEL2 Polarity select. + 10 + 1 + read-write + + + LOW + Low. The SSEL2 pin is active low. + 0 + + + HIGH + High. The SSEL2 pin is active high. + 0x1 + + + + + SPOL3 + SSEL3 Polarity select. + 11 + 1 + read-write + + + LOW + Low. The SSEL3 pin is active low. + 0 + + + HIGH + High. The SSEL3 pin is active high. + 0x1 + + + + + + + DLY + SPI Delay register + 0x404 + 32 + read-write + 0 + 0xFFFF + + + PRE_DELAY + Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted. + 0 + 4 + read-write + + + POST_DELAY + Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted. + 4 + 4 + read-write + + + FRAME_DELAY + If the EOF flag is set, controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted. + 8 + 4 + read-write + + + TRANSFER_DELAY + Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times. 0x2 = The minimum time that SSEL is deasserted is 3 SPI clock times. 0xF = The minimum time that SSEL is deasserted is 16 SPI clock times. + 12 + 4 + read-write + + + + + STAT + SPI Status. Some status flags can be cleared by writing a 1 to that bit position. + 0x408 + 32 + read-write + 0x100 + 0x1C0 + + + SSA + Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted, in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy, and allows waking up the device from reduced power modes when a slave mode access begins. This flag is cleared by software. + 4 + 1 + write-only + + + SSD + Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted, in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software. + 5 + 1 + write-only + + + STALLED + Stalled status flag. This indicates whether the SPI is currently in a stall condition. + 6 + 1 + read-only + + + ENDTRANSFER + End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress, as if the EOT flag had been set prior to the last transmission. This capability is included to support cases where it is not known when transmit data is written that it will be the end of a transfer. The bit is cleared when the transmitter becomes idle as the transfer comes to an end. Forcing an end of transfer in this manner causes any specified FRAME_DELAY and TRANSFER_DELAY to be inserted. + 7 + 1 + read-write + + + MSTIDLE + Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data. + 8 + 1 + read-only + + + + + INTENSET + SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. + 0x40C + 32 + read-write + 0 + 0x130 + + + SSAEN + Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted. + 4 + 1 + read-write + + + DISABLED + Disabled. No interrupt will be generated when any Slave Select transitions from deasserted to asserted. + 0 + + + ENABLED + Enabled. An interrupt will be generated when any Slave Select transitions from deasserted to asserted. + 0x1 + + + + + SSDEN + Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted. + 5 + 1 + read-write + + + DISABLED + Disabled. No interrupt will be generated when all asserted Slave Selects transition to deasserted. + 0 + + + ENABLED + Enabled. An interrupt will be generated when all asserted Slave Selects transition to deasserted. + 0x1 + + + + + MSTIDLEEN + Master idle interrupt enable. + 8 + 1 + read-write + + + DISABLED + No interrupt will be generated when the SPI master function is idle. + 0 + + + ENABLED + An interrupt will be generated when the SPI master function is fully idle. + 0x1 + + + + + + + INTENCLR + SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared. + 0x410 + 32 + write-only + 0 + 0 + + + SSAEN + Writing 1 clears the corresponding bit in the INTENSET register. + 4 + 1 + write-only + + + SSDEN + Writing 1 clears the corresponding bit in the INTENSET register. + 5 + 1 + write-only + + + MSTIDLE + Writing 1 clears the corresponding bit in the INTENSET register. + 8 + 1 + write-only + + + + + DIV + SPI clock Divider + 0x424 + 32 + read-write + 0 + 0xFFFF + + + DIVVAL + Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1, the value 1 results in FCLK/2, up to the maximum possible divide value of 0xFFFF, which results in FCLK/65536. + 0 + 16 + read-write + + + + + INTSTAT + SPI Interrupt Status + 0x428 + 32 + read-only + 0 + 0x130 + + + SSA + Slave Select Assert. + 4 + 1 + read-only + + + SSD + Slave Select Deassert. + 5 + 1 + read-only + + + MSTIDLE + Master Idle status flag. + 8 + 1 + read-only + + + + + FIFOCFG + FIFO configuration and enable register. + 0xE00 + 32 + read-write + 0 + 0x7F033 + + + ENABLETX + Enable the transmit FIFO. + 0 + 1 + read-write + + + DISABLED + The transmit FIFO is not enabled. + 0 + + + ENABLED + The transmit FIFO is enabled. + 0x1 + + + + + ENABLERX + Enable the receive FIFO. + 1 + 1 + read-write + + + DISABLED + The receive FIFO is not enabled. + 0 + + + ENABLED + The receive FIFO is enabled. + 0x1 + + + + + SIZE + FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART. + 4 + 2 + read-only + + + DMATX + DMA configuration for transmit. + 12 + 1 + read-write + + + DISABLED + DMA is not used for the transmit function. + 0 + + + ENABLED + Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. + 0x1 + + + + + DMARX + DMA configuration for receive. + 13 + 1 + read-write + + + DISABLED + DMA is not used for the receive function. + 0 + + + ENABLED + Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. + 0x1 + + + + + WAKETX + Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register. + 14 + 1 + read-write + + + DISABLED + Only enabled interrupts will wake up the device form reduced power modes. + 0 + + + ENABLED + A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in FIFOTRIG, even when the TXLVL interrupt is not enabled. + 0x1 + + + + + WAKERX + Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register. + 15 + 1 + read-write + + + DISABLED + Only enabled interrupts will wake up the device form reduced power modes. + 0 + + + ENABLED + A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in FIFOTRIG, even when the RXLVL interrupt is not enabled. + 0x1 + + + + + EMPTYTX + Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied. + 16 + 1 + read-write + + + EMPTYRX + Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied. + 17 + 1 + read-write + + + POPDBG + Pop FIFO for debug reads. + 18 + 1 + read-write + + + DO_NOT_POP + Debug reads of the FIFO do not pop the FIFO. + 0 + + + POP + A debug read will cause the FIFO to pop. + 0x1 + + + + + + + FIFOSTAT + FIFO status register. + 0xE04 + 32 + read-write + 0x30 + 0x1F1FFB + + + TXERR + TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit. + 0 + 1 + read-write + + + RXERR + RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit. + 1 + 1 + read-write + + + PERINT + Peripheral interrupt. When 1, this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register. + 3 + 1 + read-only + + + TXEMPTY + Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data. + 4 + 1 + read-only + + + TXNOTFULL + Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be written. When 0, the transmit FIFO is full and another write would cause it to overflow. + 5 + 1 + read-only + + + RXNOTEMPTY + Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty. + 6 + 1 + read-only + + + RXFULL + Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow. + 7 + 1 + read-only + + + TXLVL + Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be 0. + 8 + 5 + read-only + + + RXLVL + Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be 1. + 16 + 5 + read-only + + + + + FIFOTRIG + FIFO trigger settings for interrupt and DMA request. + 0xE08 + 32 + read-write + 0 + 0xF0F03 + + + TXLVLENA + Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set. + 0 + 1 + read-write + + + DISABLED + Transmit FIFO level does not generate a FIFO level trigger. + 0 + + + ENABLED + An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register. + 0x1 + + + + + RXLVLENA + Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. + 1 + 1 + read-write + + + DISABLED + Receive FIFO level does not generate a FIFO level trigger. + 0 + + + ENABLED + An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. + 0x1 + + + + + TXLVL + Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX FIFO level decreases to 15 entries (is no longer full). + 8 + 4 + read-write + + + RXLVL + Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX FIFO has received 16 entries (has become full). + 16 + 4 + read-write + + + + + FIFOINTENSET + FIFO interrupt enable set (enable) and read register. + 0xE10 + 32 + read-write + 0 + 0xF + + + TXERR + Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. + 0 + 1 + read-write + + + DISABLED + No interrupt will be generated for a transmit error. + 0 + + + ENABLED + An interrupt will be generated when a transmit error occurs. + 0x1 + + + + + RXERR + Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. + 1 + 1 + read-write + + + DISABLED + No interrupt will be generated for a receive error. + 0 + + + ENABLED + An interrupt will be generated when a receive error occurs. + 0x1 + + + + + TXLVL + Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. + 2 + 1 + read-write + + + DISABLED + No interrupt will be generated based on the TX FIFO level. + 0 + + + ENABLED + If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases to the level specified by TXLVL in the FIFOTRIG register. + 0x1 + + + + + RXLVL + Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. + 3 + 1 + read-write + + + DISABLED + No interrupt will be generated based on the RX FIFO level. + 0 + + + ENABLED + If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level increases to the level specified by RXLVL in the FIFOTRIG register. + 0x1 + + + + + + + FIFOINTENCLR + FIFO interrupt enable clear (disable) and read register. + 0xE14 + 32 + read-write + 0 + 0xF + + + TXERR + Writing one clears the corresponding bits in the FIFOINTENSET register. + 0 + 1 + read-write + + + RXERR + Writing one clears the corresponding bits in the FIFOINTENSET register. + 1 + 1 + read-write + + + TXLVL + Writing one clears the corresponding bits in the FIFOINTENSET register. + 2 + 1 + read-write + + + RXLVL + Writing one clears the corresponding bits in the FIFOINTENSET register. + 3 + 1 + read-write + + + + + FIFOINTSTAT + FIFO interrupt status register. + 0xE18 + 32 + read-only + 0 + 0x1F + + + TXERR + TX FIFO error. + 0 + 1 + read-only + + + RXERR + RX FIFO error. + 1 + 1 + read-only + + + TXLVL + Transmit FIFO level interrupt. + 2 + 1 + read-only + + + RXLVL + Receive FIFO level interrupt. + 3 + 1 + read-only + + + PERINT + Peripheral interrupt. + 4 + 1 + read-only + + + + + FIFOWR + FIFO write data. + 0xE20 + 32 + read-write + 0 + 0 + + + TXDATA + Transmit data to the FIFO. + 0 + 16 + write-only + + + TXSSEL0_N + Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default. + 16 + 1 + write-only + + + ASSERTED + SSEL0 asserted. + 0 + + + NOT_ASSERTED + SSEL0 not asserted. + 0x1 + + + + + TXSSEL1_N + Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default. + 17 + 1 + write-only + + + ASSERTED + SSEL1 asserted. + 0 + + + NOT_ASSERTED + SSEL1 not asserted. + 0x1 + + + + + TXSSEL2_N + Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default. + 18 + 1 + write-only + + + ASSERTED + SSEL2 asserted. + 0 + + + NOT_ASSERTED + SSEL2 not asserted. + 0x1 + + + + + TXSSEL3_N + Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default. + 19 + 1 + write-only + + + ASSERTED + SSEL3 asserted. + 0 + + + NOT_ASSERTED + SSEL3 not asserted. + 0x1 + + + + + EOT + End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register. + 20 + 1 + write-only + + + NOT_DEASSERTED + SSEL not deasserted. This piece of data is not treated as the end of a transfer. SSEL will not be deasserted at the end of this data. + 0 + + + DEASSERTED + SSEL deasserted. This piece of data is treated as the end of a transfer. SSEL will be deasserted at the end of this piece of data. + 0x1 + + + + + EOF + End of frame. Between frames, a delay may be inserted, as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for frame lengths greater than 16 bits. + 21 + 1 + write-only + + + NOT_EOF + Data not EOF. This piece of data transmitted is not treated as the end of a frame. + 0 + + + EOF + Data EOF. This piece of data is treated as the end of a frame, causing the Frame_delay time to be inserted before subsequent data is transmitted. + 0x1 + + + + + RXIGNORE + Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA. + 22 + 1 + write-only + + + READ + Read received data. Received data must be read in order to allow transmission to progress. SPI transmit will halt when the receive data FIFO is full. In slave mode, an overrun error will occur if received data is not read before new data is received. + 0 + + + IGNORE + Ignore received data. Received data is ignored, allowing transmission without reading unneeded received data. No receiver flags are generated. + 0x1 + + + + + LEN + Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5 bits in length. 0xF = Data transfer is 16 bits in length. + 24 + 4 + write-only + + + + + FIFORD + FIFO read data. + 0xE30 + 32 + read-only + 0 + 0xE1FF + + + RXDATA + Received data from the FIFO. + 0 + 16 + read-only + + + RXSSEL0_N + Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG. + 16 + 1 + read-only + + + RXSSEL1_N + Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG. + 17 + 1 + read-only + + + RXSSEL2_N + Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG. + 18 + 1 + read-only + + + RXSSEL3_N + Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG. + 19 + 1 + read-only + + + SOT + Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e., any previous transfer has ended). This information can be used to identify the first piece of data in cases where the transfer length is greater than 16 bits. + 20 + 1 + read-only + + + + + FIFORDNOPOP + FIFO data read with no FIFO pop. + 0xE40 + 32 + read-only + 0 + 0xE1FF + + + RXDATA + Received data from the FIFO. + 0 + 16 + read-only + + + RXSSEL0_N + Slave Select for receive. + 16 + 1 + read-only + + + RXSSEL1_N + Slave Select for receive. + 17 + 1 + read-only + + + RXSSEL2_N + Slave Select for receive. + 18 + 1 + read-only + + + RXSSEL3_N + Slave Select for receive. + 19 + 1 + read-only + + + SOT + Start of transfer flag. + 20 + 1 + read-only + + + + + ID + Peripheral identification register. + 0xFFC + 32 + read-only + 0 + 0xFFFFFFFF + + + APERTURE + Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture. + 0 + 8 + read-only + + + MINOR_REV + Minor revision of module implementation. + 8 + 4 + read-only + + + MAJOR_REV + Major revision of module implementation. + 12 + 4 + read-only + + + ID + Module identifier for the selected function. + 16 + 16 + read-only + + + + + + + SPI1 + Serial Peripheral Interfaces (SPI) + FLEXCOMM1 + SPI + 0x40087000 + + 0 + 0x1000 + registers + + + FLEXCOMM1 + 15 + + + + SPI2 + Serial Peripheral Interfaces (SPI) + FLEXCOMM2 + SPI + 0x40088000 + + 0 + 0x1000 + registers + + + FLEXCOMM2 + 16 + + + + SPI3 + Serial Peripheral Interfaces (SPI) + FLEXCOMM3 + SPI + 0x40089000 + + 0 + 0x1000 + registers + + + FLEXCOMM3 + 17 + + + + SPI4 + Serial Peripheral Interfaces (SPI) + FLEXCOMM4 + SPI + 0x4008A000 + + 0 + 0x1000 + registers + + + FLEXCOMM4 + 18 + + + + SPI5 + Serial Peripheral Interfaces (SPI) + FLEXCOMM5 + SPI + 0x40096000 + + 0 + 0x1000 + registers + + + FLEXCOMM5 + 19 + + + + SPI6 + Serial Peripheral Interfaces (SPI) + FLEXCOMM6 + SPI + 0x40097000 + + 0 + 0x1000 + registers + + + FLEXCOMM6 + 20 + + + + SPI7 + Serial Peripheral Interfaces (SPI) + FLEXCOMM7 + SPI + 0x40098000 + + 0 + 0x1000 + registers + + + FLEXCOMM7 + 21 + + + + SPI8 + Serial Peripheral Interfaces (SPI) + FLEXCOMM8 + SPI + 0x4009F000 + + 0 + 0x1000 + registers + + + FLEXCOMM8 + 59 + + + + USART0 + USARTs + FLEXCOMM0 + USART + USART + 0x40086000 + + 0 + 0x1000 + registers + + + FLEXCOMM0 + 14 + + + + CFG + USART Configuration register. Basic USART configuration settings that typically are not changed during operation. + 0 + 32 + read-write + 0 + 0xFDDBFD + + + ENABLE + USART Enable. + 0 + 1 + read-write + + + DISABLED + Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0, all USART interrupts and DMA transfers are disabled. When Enable is set again, CFG and most other control bits remain unchanged. When re-enabled, the USART will immediately be ready to transmit because the transmitter has been reset and is therefore available. + 0 + + + ENABLED + Enabled. The USART is enabled for operation. + 0x1 + + + + + DATALEN + Selects the data size for the USART. + 2 + 2 + read-write + + + BIT_7 + 7 bit Data length. + 0 + + + BIT_8 + 8 bit Data length. + 0x1 + + + BIT_9 + 9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET bit in the CTL register. + 0x2 + + + + + PARITYSEL + Selects what type of parity is used by the USART. + 4 + 2 + read-write + + + NO_PARITY + No parity. + 0 + + + EVEN_PARITY + Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even, and the number of 1s in a received character is expected to be even. + 0x2 + + + ODD_PARITY + Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd, and the number of 1s in a received character is expected to be odd. + 0x3 + + + + + STOPLEN + Number of stop bits appended to transmitted data. Only a single stop bit is required for received data. + 6 + 1 + read-write + + + BIT_1 + 1 stop bit. + 0 + + + BITS_2 + 2 stop bits. This setting should only be used for asynchronous communication. + 0x1 + + + + + MODE32K + Selects standard or 32 kHz clocking mode. + 7 + 1 + read-write + + + DISABLED + Disabled. USART uses standard clocking. + 0 + + + ENABLED + Enabled. USART uses the 32 kHz clock from the RTC oscillator as the clock source to the BRG, and uses a special bit clocking scheme. + 0x1 + + + + + LINMODE + LIN break mode enable. + 8 + 1 + read-write + + + DISABLED + Disabled. Break detect and generate is configured for normal operation. + 0 + + + ENABLED + Enabled. Break detect and generate is configured for LIN bus operation. + 0x1 + + + + + CTSEN + CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin, or from the USART's own RTS if loopback mode is enabled. + 9 + 1 + read-write + + + DISABLED + No flow control. The transmitter does not receive any automatic flow control signal. + 0 + + + ENABLED + Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes. + 0x1 + + + + + SYNCEN + Selects synchronous or asynchronous operation. + 11 + 1 + read-write + + + ASYNCHRONOUS_MODE + Asynchronous mode. + 0 + + + SYNCHRONOUS_MODE + Synchronous mode. + 0x1 + + + + + CLKPOL + Selects the clock polarity and sampling edge of received data in synchronous mode. + 12 + 1 + read-write + + + FALLING_EDGE + Falling edge. Un_RXD is sampled on the falling edge of SCLK. + 0 + + + RISING_EDGE + Rising edge. Un_RXD is sampled on the rising edge of SCLK. + 0x1 + + + + + SYNCMST + Synchronous mode Master select. + 14 + 1 + read-write + + + SLAVE + Slave. When synchronous mode is enabled, the USART is a slave. + 0 + + + MASTER + Master. When synchronous mode is enabled, the USART is a master. + 0x1 + + + + + LOOP + Selects data loopback mode. + 15 + 1 + read-write + + + NORMAL + Normal operation. + 0 + + + LOOPBACK + Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD and Un_RTS activity will also appear on external pins if these functions are configured to appear on device pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN. + 0x1 + + + + + OETA + Output Enable Turnaround time enable for RS-485 operation. + 18 + 1 + read-write + + + DISABLED + Disabled. If selected by OESEL, the Output Enable signal deasserted at the end of the last stop bit of a transmission. + 0 + + + ENABLED + Enabled. If selected by OESEL, the Output Enable signal remains asserted for one character time after the end of the last stop bit of a transmission. OE will also remain asserted if another transmit begins before it is deasserted. + 0x1 + + + + + AUTOADDR + Automatic Address matching enable. + 19 + 1 + read-write + + + DISABLED + Disabled. When addressing is enabled by ADDRDET, address matching is done by software. This provides the possibility of versatile addressing (e.g. respond to more than one address). + 0 + + + ENABLED + Enabled. When addressing is enabled by ADDRDET, address matching is done by hardware, using the value in the ADDR register as the address to match. + 0x1 + + + + + OESEL + Output Enable Select. + 20 + 1 + read-write + + + STANDARD + Standard. The RTS signal is used as the standard flow control function. + 0 + + + RS_485 + RS-485. The RTS signal configured to provide an output enable signal to control an RS-485 transceiver. + 0x1 + + + + + OEPOL + Output Enable Polarity. + 21 + 1 + read-write + + + LOW + Low. If selected by OESEL, the output enable is active low. + 0 + + + HIGH + High. If selected by OESEL, the output enable is active high. + 0x1 + + + + + RXPOL + Receive data polarity. + 22 + 1 + read-write + + + STANDARD + Standard. The RX signal is used as it arrives from the pin. This means that the RX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1. + 0 + + + INVERTED + Inverted. The RX signal is inverted before being used by the USART. This means that the RX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0. + 0x1 + + + + + TXPOL + Transmit data polarity. + 23 + 1 + read-write + + + STANDARD + Standard. The TX signal is sent out without change. This means that the TX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1. + 0 + + + INVERTED + Inverted. The TX signal is inverted by the USART before being sent out. This means that the TX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0. + 0x1 + + + + + + + CTL + USART Control register. USART control settings that are more likely to change during operation. + 0x4 + 32 + read-write + 0 + 0x10346 + + + TXBRKEN + Break Enable. + 1 + 1 + read-write + + + NORMAL + Normal operation. + 0 + + + CONTINOUS + Continuous break. Continuous break is sent immediately when this bit is set, and remains until this bit is cleared. A break may be sent without danger of corrupting any currently transmitting character if the transmitter is first disabled (TXDIS in CTL is set) and then waiting for the transmitter to be disabled (TXDISINT in STAT = 1) before writing 1 to TXBRKEN. + 0x1 + + + + + ADDRDET + Enable address detect mode. + 2 + 1 + read-write + + + DISABLED + Disabled. The USART presents all incoming data. + 0 + + + ENABLED + Enabled. The USART receiver ignores incoming data that does not have the most significant bit of the data (typically the 9th bit) = 1. When the data MSB bit = 1, the receiver treats the incoming data normally, generating a received data interrupt. Software can then check the data to see if this is an address that should be handled. If it is, the ADDRDET bit is cleared by software and further incoming data is handled normally. + 0x1 + + + + + TXDIS + Transmit Disable. + 6 + 1 + read-write + + + ENABLED + Not disabled. USART transmitter is not disabled. + 0 + + + DISABLED + Disabled. USART transmitter is disabled after any character currently being transmitted is complete. This feature can be used to facilitate software flow control. + 0x1 + + + + + CC + Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode. + 8 + 1 + read-write + + + CLOCK_ON_CHARACTER + Clock on character. In synchronous mode, SCLK cycles only when characters are being sent on Un_TXD or to complete a character that is being received. + 0 + + + CONTINOUS_CLOCK + Continuous clock. SCLK runs continuously in synchronous mode, allowing characters to be received on Un_RxD independently from transmission on Un_TXD). + 0x1 + + + + + CLRCCONRX + Clear Continuous Clock. + 9 + 1 + read-write + + + NO_EFFECT + No effect. No effect on the CC bit. + 0 + + + AUTO_CLEAR + Auto-clear. The CC bit is automatically cleared when a complete character has been received. This bit is cleared at the same time. + 0x1 + + + + + AUTOBAUD + Autobaud enable. + 16 + 1 + read-write + + + DISABLED + Disabled. USART is in normal operating mode. + 0 + + + ENABLED + Enabled. USART is in autobaud mode. This bit should only be set when the USART receiver is idle. The first start bit of RX is measured and used the update the BRG register to match the received data rate. AUTOBAUD is cleared once this process is complete, or if there is an AERR. + 0x1 + + + + + + + STAT + USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them. + 0x8 + 32 + read-write + 0xA + 0x45A + + + RXIDLE + Receiver Idle. When 0, indicates that the receiver is currently in the process of receiving data. When 1, indicates that the receiver is not currently in the process of receiving data. + 1 + 1 + read-only + + + TXIDLE + Transmitter Idle. When 0, indicates that the transmitter is currently in the process of sending data.When 1, indicate that the transmitter is not currently in the process of sending data. + 3 + 1 + read-only + + + CTS + This bit reflects the current state of the CTS signal, regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled. + 4 + 1 + read-only + + + DELTACTS + This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software. + 5 + 1 + write-only + + + TXDISSTAT + Transmitter Disabled Status flag. When 1, this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1). + 6 + 1 + read-only + + + RXBRK + Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the character would be missing. RXBRK is cleared when the Un_RXD pin goes high. + 10 + 1 + read-only + + + DELTARXBRK + This bit is set when a change in the state of receiver break detection occurs. Cleared by software. + 11 + 1 + write-only + + + START + This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software. + 12 + 1 + write-only + + + FRAMERRINT + Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source. + 13 + 1 + write-only + + + PARITYERRINT + Parity Error interrupt flag. This flag is set when a parity error is detected in a received character. + 14 + 1 + write-only + + + RXNOISEINT + Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit, except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a received data bit contains one disagreeing sample. This could indicate line noise, a baud rate or character format mismatch, or loss of synchronization during data reception. + 15 + 1 + write-only + + + ABERR + Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured, essentially an auto baud time-out. + 16 + 1 + write-only + + + + + INTENSET + Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. + 0xC + 32 + read-write + 0 + 0x1F868 + + + TXIDLEEN + When 1, enables an interrupt when the transmitter becomes idle (TXIDLE = 1). + 3 + 1 + read-write + + + DELTACTSEN + When 1, enables an interrupt when there is a change in the state of the CTS input. + 5 + 1 + read-write + + + TXDISEN + When 1, enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details. + 6 + 1 + read-write + + + DELTARXBRKEN + When 1, enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted). + 11 + 1 + read-write + + + STARTEN + When 1, enables an interrupt when a received start bit has been detected. + 12 + 1 + read-write + + + FRAMERREN + When 1, enables an interrupt when a framing error has been detected. + 13 + 1 + read-write + + + PARITYERREN + When 1, enables an interrupt when a parity error has been detected. + 14 + 1 + read-write + + + RXNOISEEN + When 1, enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354. + 15 + 1 + read-write + + + ABERREN + When 1, enables an interrupt when an auto baud error occurs. + 16 + 1 + read-write + + + + + INTENCLR + Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared. + 0x10 + 32 + write-only + 0 + 0 + + + TXIDLECLR + Writing 1 clears the corresponding bit in the INTENSET register. + 3 + 1 + write-only + + + DELTACTSCLR + Writing 1 clears the corresponding bit in the INTENSET register. + 5 + 1 + write-only + + + TXDISCLR + Writing 1 clears the corresponding bit in the INTENSET register. + 6 + 1 + write-only + + + DELTARXBRKCLR + Writing 1 clears the corresponding bit in the INTENSET register. + 11 + 1 + write-only + + + STARTCLR + Writing 1 clears the corresponding bit in the INTENSET register. + 12 + 1 + write-only + + + FRAMERRCLR + Writing 1 clears the corresponding bit in the INTENSET register. + 13 + 1 + write-only + + + PARITYERRCLR + Writing 1 clears the corresponding bit in the INTENSET register. + 14 + 1 + write-only + + + RXNOISECLR + Writing 1 clears the corresponding bit in the INTENSET register. + 15 + 1 + write-only + + + ABERRCLR + Writing 1 clears the corresponding bit in the INTENSET register. + 16 + 1 + write-only + + + + + BRG + Baud Rate Generator register. 16-bit integer baud rate divisor value. + 0x20 + 32 + read-write + 0 + 0xFFFF + + + BRGVAL + This value is used to divide the USART input clock to determine the baud rate, based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided by 3 before use by the USART function. 0xFFFF = FCLK is divided by 65,536 before use by the USART function. + 0 + 16 + read-write + + + + + INTSTAT + Interrupt status register. Reflects interrupts that are currently enabled. + 0x24 + 32 + read-only + 0 + 0x1F968 + + + TXIDLE + Transmitter Idle status. + 3 + 1 + read-only + + + DELTACTS + This bit is set when a change in the state of the CTS input is detected. + 5 + 1 + read-only + + + TXDISINT + Transmitter Disabled Interrupt flag. + 6 + 1 + read-only + + + DELTARXBRK + This bit is set when a change in the state of receiver break detection occurs. + 11 + 1 + read-only + + + START + This bit is set when a start is detected on the receiver input. + 12 + 1 + read-only + + + FRAMERRINT + Framing Error interrupt flag. + 13 + 1 + read-only + + + PARITYERRINT + Parity Error interrupt flag. + 14 + 1 + read-only + + + RXNOISEINT + Received Noise interrupt flag. + 15 + 1 + read-only + + + ABERRINT + Auto baud Error Interrupt flag. + 16 + 1 + read-only + + + + + OSR + Oversample selection register for asynchronous communication. + 0x28 + 32 + read-write + 0xF + 0xF + + + OSRVAL + Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and receive each data bit. + 0 + 4 + read-write + + + + + ADDR + Address register for automatic address matching. + 0x2C + 32 + read-write + 0 + 0xFF + + + ADDRESS + 8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1). + 0 + 8 + read-write + + + + + FIFOCFG + FIFO configuration and enable register. + 0xE00 + 32 + read-write + 0 + 0x7F033 + + + ENABLETX + Enable the transmit FIFO. + 0 + 1 + read-write + + + DISABLED + The transmit FIFO is not enabled. + 0 + + + ENABLED + The transmit FIFO is enabled. + 0x1 + + + + + ENABLERX + Enable the receive FIFO. + 1 + 1 + read-write + + + DISABLED + The receive FIFO is not enabled. + 0 + + + ENABLED + The receive FIFO is enabled. + 0x1 + + + + + SIZE + FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART. + 4 + 2 + read-only + + + DMATX + DMA configuration for transmit. + 12 + 1 + read-write + + + DISABLED + DMA is not used for the transmit function. + 0 + + + ENABLED + Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. + 0x1 + + + + + DMARX + DMA configuration for receive. + 13 + 1 + read-write + + + DISABLED + DMA is not used for the receive function. + 0 + + + ENABLED + Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. + 0x1 + + + + + WAKETX + Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register. + 14 + 1 + read-write + + + DISABLED + Only enabled interrupts will wake up the device form reduced power modes. + 0 + + + ENABLED + A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in FIFOTRIG, even when the TXLVL interrupt is not enabled. + 0x1 + + + + + WAKERX + Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register. + 15 + 1 + read-write + + + DISABLED + Only enabled interrupts will wake up the device form reduced power modes. + 0 + + + ENABLED + A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in FIFOTRIG, even when the RXLVL interrupt is not enabled. + 0x1 + + + + + EMPTYTX + Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied. + 16 + 1 + read-write + + + EMPTYRX + Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied. + 17 + 1 + read-write + + + POPDBG + Pop FIFO for debug reads. + 18 + 1 + read-write + + + DO_NOT_POP + Debug reads of the FIFO do not pop the FIFO. + 0 + + + POP + A debug read will cause the FIFO to pop. + 0x1 + + + + + + + FIFOSTAT + FIFO status register. + 0xE04 + 32 + read-write + 0x30 + 0x1F1FFB + + + TXERR + TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit. + 0 + 1 + read-write + + + RXERR + RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit. + 1 + 1 + read-write + + + PERINT + Peripheral interrupt. When 1, this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register. + 3 + 1 + read-only + + + TXEMPTY + Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data. + 4 + 1 + read-only + + + TXNOTFULL + Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be written. When 0, the transmit FIFO is full and another write would cause it to overflow. + 5 + 1 + read-only + + + RXNOTEMPTY + Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty. + 6 + 1 + read-only + + + RXFULL + Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow. + 7 + 1 + read-only + + + TXLVL + Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be 0. + 8 + 5 + read-only + + + RXLVL + Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be 1. + 16 + 5 + read-only + + + + + FIFOTRIG + FIFO trigger settings for interrupt and DMA request. + 0xE08 + 32 + read-write + 0 + 0xF0F03 + + + TXLVLENA + Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set. + 0 + 1 + read-write + + + DISABLED + Transmit FIFO level does not generate a FIFO level trigger. + 0 + + + ENABLED + An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register. + 0x1 + + + + + RXLVLENA + Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. + 1 + 1 + read-write + + + DISABLED + Receive FIFO level does not generate a FIFO level trigger. + 0 + + + ENABLED + An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. + 0x1 + + + + + TXLVL + Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX FIFO level decreases to 15 entries (is no longer full). + 8 + 4 + read-write + + + RXLVL + Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX FIFO has received 16 entries (has become full). + 16 + 4 + read-write + + + + + FIFOINTENSET + FIFO interrupt enable set (enable) and read register. + 0xE10 + 32 + read-write + 0 + 0xF + + + TXERR + Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. + 0 + 1 + read-write + + + DISABLED + No interrupt will be generated for a transmit error. + 0 + + + ENABLED + An interrupt will be generated when a transmit error occurs. + 0x1 + + + + + RXERR + Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. + 1 + 1 + read-write + + + DISABLED + No interrupt will be generated for a receive error. + 0 + + + ENABLED + An interrupt will be generated when a receive error occurs. + 0x1 + + + + + TXLVL + Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. + 2 + 1 + read-write + + + DISABLED + No interrupt will be generated based on the TX FIFO level. + 0 + + + ENABLED + If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases to the level specified by TXLVL in the FIFOTRIG register. + 0x1 + + + + + RXLVL + Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. + 3 + 1 + read-write + + + DISABLED + No interrupt will be generated based on the RX FIFO level. + 0 + + + ENABLED + If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level increases to the level specified by RXLVL in the FIFOTRIG register. + 0x1 + + + + + + + FIFOINTENCLR + FIFO interrupt enable clear (disable) and read register. + 0xE14 + 32 + read-write + 0 + 0xF + + + TXERR + Writing one clears the corresponding bits in the FIFOINTENSET register. + 0 + 1 + read-write + + + RXERR + Writing one clears the corresponding bits in the FIFOINTENSET register. + 1 + 1 + read-write + + + TXLVL + Writing one clears the corresponding bits in the FIFOINTENSET register. + 2 + 1 + read-write + + + RXLVL + Writing one clears the corresponding bits in the FIFOINTENSET register. + 3 + 1 + read-write + + + + + FIFOINTSTAT + FIFO interrupt status register. + 0xE18 + 32 + read-only + 0 + 0x1F + + + TXERR + TX FIFO error. + 0 + 1 + read-only + + + RXERR + RX FIFO error. + 1 + 1 + read-only + + + TXLVL + Transmit FIFO level interrupt. + 2 + 1 + read-only + + + RXLVL + Receive FIFO level interrupt. + 3 + 1 + read-only + + + PERINT + Peripheral interrupt. + 4 + 1 + read-only + + + + + FIFOWR + FIFO write data. + 0xE20 + 32 + read-write + 0 + 0 + + + TXDATA + Transmit data to the FIFO. + 0 + 9 + write-only + + + + + FIFORD + FIFO read data. + 0xE30 + 32 + read-only + 0 + 0xE1FF + + + RXDATA + Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings. + 0 + 9 + read-only + + + FRAMERR + Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO, and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source. + 13 + 1 + read-only + + + PARITYERR + Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character. + 14 + 1 + read-only + + + RXNOISE + Received Noise flag. See description of the RxNoiseInt bit in Table 354. + 15 + 1 + read-only + + + + + FIFORDNOPOP + FIFO data read with no FIFO pop. + 0xE40 + 32 + read-only + 0 + 0xE1FF + + + RXDATA + Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings. + 0 + 9 + read-only + + + FRAMERR + Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO, and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source. + 13 + 1 + read-only + + + PARITYERR + Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character. + 14 + 1 + read-only + + + RXNOISE + Received Noise flag. See description of the RxNoiseInt bit in Table 354. + 15 + 1 + read-only + + + + + ID + Peripheral identification register. + 0xFFC + 32 + read-only + 0 + 0xFFFFFFFF + + + APERTURE + Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture. + 0 + 8 + read-only + + + MINOR_REV + Minor revision of module implementation. + 8 + 4 + read-only + + + MAJOR_REV + Major revision of module implementation. + 12 + 4 + read-only + + + ID + Module identifier for the selected function. + 16 + 16 + read-only + + + + + + + USART1 + USARTs + FLEXCOMM1 + USART + 0x40087000 + + 0 + 0x1000 + registers + + + FLEXCOMM1 + 15 + + + + USART2 + USARTs + FLEXCOMM2 + USART + 0x40088000 + + 0 + 0x1000 + registers + + + FLEXCOMM2 + 16 + + + + USART3 + USARTs + FLEXCOMM3 + USART + 0x40089000 + + 0 + 0x1000 + registers + + + FLEXCOMM3 + 17 + + + + USART4 + USARTs + FLEXCOMM4 + USART + 0x4008A000 + + 0 + 0x1000 + registers + + + FLEXCOMM4 + 18 + + + + USART5 + USARTs + FLEXCOMM5 + USART + 0x40096000 + + 0 + 0x1000 + registers + + + FLEXCOMM5 + 19 + + + + USART6 + USARTs + FLEXCOMM6 + USART + 0x40097000 + + 0 + 0x1000 + registers + + + FLEXCOMM6 + 20 + + + + USART7 + USARTs + FLEXCOMM7 + USART + 0x40098000 + + 0 + 0x1000 + registers + + + FLEXCOMM7 + 21 + + + + MAILBOX + Mailbox + MAILBOX + 0x4008B000 + + 0 + 0xFC + registers + + + MAILBOX + 31 + + + + 2 + 0x10 + MBOXIRQ[%s] + no description available + 0 + + IRQ + Interrupt request register for the Cortex-M0+ CPU. + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + INTREQ + If any bit is set, an interrupt request is sent to the Cortex-M0+ interrupt controller. + 0 + 32 + read-write + + + + + IRQSET + Set bits in IRQ0 + 0x4 + 32 + write-only + 0 + 0 + + + INTREQSET + Writing 1 sets the corresponding bit in the IRQ0 register. + 0 + 32 + write-only + + + + + IRQCLR + Clear bits in IRQ0 + 0x8 + 32 + write-only + 0 + 0 + + + INTREQCLR + Writing 1 clears the corresponding bit in the IRQ0 register. + 0 + 32 + write-only + + + + + + MUTEX + Mutual exclusion register[1] + 0xF8 + 32 + read-write + 0x1 + 0x1 + + + EX + Cleared when read, set when written. See usage description above. + 0 + 1 + read-write + + + + + + + GPIO + General Purpose I/O (GPIO) + GPIO + GPIO + 0x4008C000 + + 0 + 0x2490 + registers + + + + 4 + 0x20 + B[%s] + no description available + 0 + + 32 + 0x1 + B_[%s] + Byte pin registers for all port GPIO pins + 0 + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + + 4 + 0x80 + W[%s] + no description available + 0x1000 + + 32 + 0x4 + W_[%s] + Word pin registers for all port GPIO pins + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + + 4 + 0x4 + DIR[%s] + Direction registers for all port GPIO pins + 0x2000 + 32 + read-write + 0 + 0xFFFFFFFF + + + DIRP + Selects pin direction for pin PIOm_n (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = input. 1 = output. + 0 + 32 + read-write + + + + + 4 + 0x4 + MASK[%s] + Mask register for all port GPIO pins + 0x2080 + 32 + read-write + 0 + 0xFFFFFFFF + + + MASKP + Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package.0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. + 0 + 32 + read-write + + + + + 4 + 0x4 + PIN[%s] + Port pin register for all port GPIO pins + 0x2100 + 32 + read-write + 0 + 0xFFFFFFFF + + + PORT + Reads pin states or loads output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. + 0 + 32 + read-write + + + + + 4 + 0x4 + MPIN[%s] + Masked port register for all port GPIO pins + 0x2180 + 32 + read-write + 0 + 0xFFFFFFFF + + + MPORTP + Masked port register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. + 0 + 32 + read-write + + + + + 4 + 0x4 + SET[%s] + Write: Set register for port. Read: output bits for port + 0x2200 + 32 + read-write + 0 + 0xFFFFFFFF + + + SETP + Read or set output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. + 0 + 32 + read-write + + + + + 4 + 0x4 + CLR[%s] + Clear port for all port GPIO pins + 0x2280 + 32 + write-only + 0 + 0 + + + CLRP + Clear output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Clear output bit. + 0 + 32 + write-only + + + + + 4 + 0x4 + NOT[%s] + Toggle port for all port GPIO pins + 0x2300 + 32 + write-only + 0 + 0 + + + NOTP + Toggle output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = no operation. 1 = Toggle output bit. + 0 + 32 + write-only + + + + + 4 + 0x4 + DIRSET[%s] + Set pin direction bits for port + 0x2380 + 32 + write-only + 0 + 0 + + + DIRSETP + Set direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Set direction bit. + 0 + 29 + write-only + + + + + 4 + 0x4 + DIRCLR[%s] + Clear pin direction bits for port + 0x2400 + 32 + write-only + 0 + 0 + + + DIRCLRP + Clear direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Clear direction bit. + 0 + 29 + write-only + + + + + 4 + 0x4 + DIRNOT[%s] + Toggle pin direction bits for port + 0x2480 + 32 + write-only + 0 + 0 + + + DIRNOTP + Toggle direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = no operation. 1 = Toggle direction bit. + 0 + 29 + write-only + + + + + + + SECGPIO + General Purpose I/O (GPIO) + GPIO + 0x400A8000 + + 0 + 0x2490 + registers + + + + USBHSD + USB1 High-speed Device Controller + USBHSD + 0x40094000 + + 0 + 0x40 + registers + + + USB1_UTMI + 46 + + + USB1 + 47 + + + USB1_NEEDCLK + 48 + + + + DEVCMDSTAT + USB Device Command/Status register + 0 + 32 + read-write + 0x800 + 0xF7DBFFFF + + + DEV_ADDR + USB device address. + 0 + 7 + read-write + + + DEV_EN + USB device enable. + 7 + 1 + read-write + + + SETUP + SETUP token received. + 8 + 1 + read-write + + + FORCE_NEEDCLK + Forces the NEEDCLK output to always be on:. + 9 + 1 + read-write + + + FORCE_VBUS + If this bit is set to 1, the VBUS voltage indicators from the PHY are overruled. + 10 + 1 + read-write + + + LPM_SUP + LPM Supported:. + 11 + 1 + read-write + + + INTONNAK_AO + Interrupt on NAK for interrupt and bulk OUT EP:. + 12 + 1 + read-write + + + INTONNAK_AI + Interrupt on NAK for interrupt and bulk IN EP:. + 13 + 1 + read-write + + + INTONNAK_CO + Interrupt on NAK for control OUT EP:. + 14 + 1 + read-write + + + INTONNAK_CI + Interrupt on NAK for control IN EP:. + 15 + 1 + read-write + + + DCON + Device status - connect. + 16 + 1 + read-write + + + DSUS + Device status - suspend. + 17 + 1 + read-write + + + LPM_SUS + Device status - LPM Suspend. + 19 + 1 + read-write + + + LPM_REWP + LPM Remote Wake-up Enabled by USB host. + 20 + 1 + read-only + + + Speed + This field indicates the speed at which the device operates: 00b: reserved 01b: full-speed 10b: high-speed 11b: super-speed (reserved for future use). + 22 + 2 + read-only + + + DCON_C + Device status - connect change. + 24 + 1 + read-write + + + DSUS_C + Device status - suspend change. + 25 + 1 + read-write + + + DRES_C + Device status - reset change. + 26 + 1 + read-write + + + VBUS_DEBOUNCED + This bit indicates if VBUS is detected or not. + 28 + 1 + read-only + + + PHY_TEST_MODE + This field is written by firmware to put the PHY into a test mode as defined by the USB2. + 29 + 3 + read-write + + + + + INFO + USB Info register + 0x4 + 32 + read-only + 0x2000000 + 0xFFFF7FFF + + + FRAME_NR + Frame number. + 0 + 11 + read-only + + + ERR_CODE + The error code which last occurred:. + 11 + 4 + read-only + + + Minrev + Minor revision. + 16 + 8 + read-only + + + Majrev + Major revision. + 24 + 8 + read-only + + + + + EPLISTSTART + USB EP Command/Status List start address + 0x8 + 32 + read-write + 0 + 0xFFFFFF00 + + + EP_LIST_PRG + Programmable portion of the USB EP Command/Status List address. + 8 + 12 + read-write + + + EP_LIST_FIXED + Fixed portion of USB EP Command/Status List address. + 20 + 12 + read-only + + + + + DATABUFSTART + USB Data buffer start address + 0xC + 32 + read-write + 0x41000000 + 0xFFFFFFFF + + + DA_BUF + Start address of the memory page where all endpoint data buffers are located. + 0 + 32 + read-write + + + + + LPM + USB Link Power Management register + 0x10 + 32 + read-write + 0 + 0x1FF + + + HIRD_HW + Host Initiated Resume Duration - HW. + 0 + 4 + read-only + + + HIRD_SW + Host Initiated Resume Duration - SW. + 4 + 4 + read-write + + + DATA_PENDING + As long as this bit is set to one and LPM supported bit is set to one, HW will return a NYET handshake on every LPM token it receives. + 8 + 1 + read-write + + + + + EPSKIP + USB Endpoint skip + 0x14 + 32 + read-write + 0 + 0xFFF + + + SKIP + Endpoint skip: Writing 1 to one of these bits, will indicate to HW that it must deactivate the buffer assigned to this endpoint and return control back to software. + 0 + 12 + read-write + + + + + EPINUSE + USB Endpoint Buffer in use + 0x18 + 32 + read-write + 0 + 0xFFC + + + BUF + Buffer in use: This register has one bit per physical endpoint. + 2 + 10 + read-write + + + + + EPBUFCFG + USB Endpoint Buffer Configuration register + 0x1C + 32 + read-write + 0 + 0xFFC + + + BUF_SB + Buffer usage: This register has one bit per physical endpoint. + 2 + 10 + read-write + + + + + INTSTAT + USB interrupt status register + 0x20 + 32 + read-write + 0 + 0xC0000FFF + + + EP0OUT + Interrupt status register bit for the Control EP0 OUT direction. + 0 + 1 + read-write + + + EP0IN + Interrupt status register bit for the Control EP0 IN direction. + 1 + 1 + read-write + + + EP1OUT + Interrupt status register bit for the EP1 OUT direction. + 2 + 1 + read-write + + + EP1IN + Interrupt status register bit for the EP1 IN direction. + 3 + 1 + read-write + + + EP2OUT + Interrupt status register bit for the EP2 OUT direction. + 4 + 1 + read-write + + + EP2IN + Interrupt status register bit for the EP2 IN direction. + 5 + 1 + read-write + + + EP3OUT + Interrupt status register bit for the EP3 OUT direction. + 6 + 1 + read-write + + + EP3IN + Interrupt status register bit for the EP3 IN direction. + 7 + 1 + read-write + + + EP4OUT + Interrupt status register bit for the EP4 OUT direction. + 8 + 1 + read-write + + + EP4IN + Interrupt status register bit for the EP4 IN direction. + 9 + 1 + read-write + + + EP5OUT + Interrupt status register bit for the EP5 OUT direction. + 10 + 1 + read-write + + + EP5IN + Interrupt status register bit for the EP5 IN direction. + 11 + 1 + read-write + + + FRAME_INT + Frame interrupt. + 30 + 1 + read-write + + + DEV_INT + Device status interrupt. + 31 + 1 + read-write + + + + + INTEN + USB interrupt enable register + 0x24 + 32 + read-write + 0 + 0xC0000FFF + + + EP_INT_EN + If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line. + 0 + 12 + read-write + + + FRAME_INT_EN + If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line. + 30 + 1 + read-write + + + DEV_INT_EN + If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line. + 31 + 1 + read-write + + + + + INTSETSTAT + USB set interrupt status register + 0x28 + 32 + read-write + 0 + 0xC0000FFF + + + EP_SET_INT + If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. + 0 + 12 + read-write + + + FRAME_SET_INT + If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. + 30 + 1 + read-write + + + DEV_SET_INT + If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. + 31 + 1 + read-write + + + + + EPTOGGLE + USB Endpoint toggle register + 0x34 + 32 + read-only + 0 + 0x3FFFFFFF + + + TOGGLE + Endpoint data toggle: This field indicates the current value of the data toggle for the corresponding endpoint. + 0 + 30 + read-only + + + + + ULPIDEBUG + UTMI/ULPI debug register + 0x3C + 32 + read-write + 0 + 0x83FFFFFF + + + PHY_ADDR + ULPI mode: Bits 7:0 are used as the address when doing a register access over the ULPI interface. + 0 + 8 + read-write + + + PHY_WDATA + UTMI+ mode: Reserved. + 8 + 8 + read-write + + + PHY_RDATA + UTMI+ mode: Bits 7:0 contains the value returned by the VStatus signal on Vendor Interface of UTMI+. + 16 + 8 + read-write + + + PHY_RW + UTMI+ mode: Reserved. + 24 + 1 + read-write + + + PHY_ACCESS + Software writes this bit to one to start a read or write operation. + 25 + 1 + read-write + + + PHY_MODE + This bit indicates if the interface between the controller is UTMI+ or ULPI. + 31 + 1 + read-write + + + + + + + CRC_ENGINE + CRC engine + CRC + 0x40095000 + + 0 + 0xC + registers + + + + MODE + CRC mode register + 0 + 32 + read-write + 0 + 0x3F + + + CRC_POLY + CRC polynomial: 1X = CRC-32 polynomial 01 = CRC-16 polynomial 00 = CRC-CCITT polynomial + 0 + 2 + read-write + + + BIT_RVS_WR + Data bit order: 1 = Bit order reverse for CRC_WR_DATA (per byte) 0 = No bit order reverse for CRC_WR_DATA (per byte) + 2 + 1 + read-write + + + CMPL_WR + Data complement: 1 = 1's complement for CRC_WR_DATA 0 = No 1's complement for CRC_WR_DATA + 3 + 1 + read-write + + + BIT_RVS_SUM + CRC sum bit order: 1 = Bit order reverse for CRC_SUM 0 = No bit order reverse for CRC_SUM + 4 + 1 + read-write + + + CMPL_SUM + CRC sum complement: 1 = 1's complement for CRC_SUM 0 = No 1's complement for CRC_SUM + 5 + 1 + read-write + + + + + SEED + CRC seed register + 0x4 + 32 + read-write + 0xFFFF + 0xFFFFFFFF + + + CRC_SEED + A write access to this register will load CRC seed value to CRC_SUM register with selected bit order and 1's complement pre-processes. A write access to this register will overrule the CRC calculation in progresses. + 0 + 32 + read-write + + + + + SUM + CRC checksum register + SUM_WR_DATA + 0x8 + 32 + read-only + 0xFFFF + 0xFFFFFFFF + + + CRC_SUM + The most recent CRC sum can be read through this register with selected bit order and 1's complement post-processes. + 0 + 32 + read-only + + + + + WR_DATA + CRC data register + SUM_WR_DATA + 0x8 + 32 + write-only + 0 + 0 + + + CRC_WR_DATA + Data written to this register will be taken to perform CRC calculation with selected bit order and 1's complement pre-process. Any write size 8, 16 or 32-bit are allowed and accept back-to-back transactions. + 0 + 32 + write-only + + + + + + + SDIF + SDMMC + SDIF + 0x4009B000 + + 0 + 0x300 + registers + + + SDIO + 42 + + + + CTRL + Control register + 0 + 32 + read-write + 0 + 0x2070FD7 + + + CONTROLLER_RESET + Controller reset. + 0 + 1 + read-write + + + FIFO_RESET + Fifo reset. + 1 + 1 + read-write + + + DMA_RESET + DMA reset. + 2 + 1 + read-write + + + INT_ENABLE + Global interrupt enable/disable bit. + 4 + 1 + read-write + + + READ_WAIT + Read/wait. + 6 + 1 + read-write + + + SEND_IRQ_RESPONSE + Send irq response. + 7 + 1 + read-write + + + ABORT_READ_DATA + Abort read data. + 8 + 1 + read-write + + + SEND_CCSD + Send ccsd. + 9 + 1 + read-write + + + SEND_AUTO_STOP_CCSD + Send auto stop ccsd. + 10 + 1 + read-write + + + CEATA_DEVICE_INTERRUPT_STATUS + CEATA device interrupt status. + 11 + 1 + read-write + + + CARD_VOLTAGE_A0 + Controls the state of the SD_VOLT0 pin. + 16 + 1 + read-write + + + CARD_VOLTAGE_A1 + Controls the state of the SD_VOLT1 pin. + 17 + 1 + read-write + + + CARD_VOLTAGE_A2 + Controls the state of the SD_VOLT2 pin. + 18 + 1 + read-write + + + USE_INTERNAL_DMAC + SD/MMC DMA use. + 25 + 1 + read-write + + + + + PWREN + Power Enable register + 0x4 + 32 + read-write + 0 + 0x3 + + + POWER_ENABLE0 + Power on/off switch for card 0; once power is turned on, software should wait for regulator/switch ramp-up time before trying to initialize card 0. + 0 + 1 + read-write + + + POWER_ENABLE1 + Power on/off switch for card 1; once power is turned on, software should wait for regulator/switch ramp-up time before trying to initialize card 1. + 1 + 1 + read-write + + + + + CLKDIV + Clock Divider register + 0x8 + 32 + read-write + 0 + 0xFF + + + CLK_DIVIDER0 + Clock divider-0 value. + 0 + 8 + read-write + + + + + CLKENA + Clock Enable register + 0x10 + 32 + read-write + 0 + 0x30003 + + + CCLK0_ENABLE + Clock-enable control for SD card 0 clock. + 0 + 1 + read-write + + + CCLK1_ENABLE + Clock-enable control for SD card 1 clock. + 1 + 1 + read-write + + + CCLK0_LOW_POWER + Low-power control for SD card 0 clock. + 16 + 1 + read-write + + + CCLK1_LOW_POWER + Low-power control for SD card 1 clock. + 17 + 1 + read-write + + + + + TMOUT + Time-out register + 0x14 + 32 + read-write + 0xFFFFFF40 + 0xFFFFFFFF + + + RESPONSE_TIMEOUT + Response time-out value. + 0 + 8 + read-write + + + DATA_TIMEOUT + Value for card Data Read time-out; same value also used for Data Starvation by Host time-out. + 8 + 24 + read-write + + + + + CTYPE + Card Type register + 0x18 + 32 + read-write + 0 + 0x30003 + + + CARD0_WIDTH0 + Indicates if card 0 is 1-bit or 4-bit: 0 - 1-bit mode 1 - 4-bit mode 1 and 4-bit modes only work when 8-bit mode in CARD0_WIDTH1 is not enabled (bit 16 in this register is set to 0). + 0 + 1 + read-write + + + CARD1_WIDTH0 + Indicates if card 1 is 1-bit or 4-bit: 0 - 1-bit mode 1 - 4-bit mode 1 and 4-bit modes only work when 8-bit mode in CARD1_WIDTH1 is not enabled (bit 16 in this register is set to 0). + 1 + 1 + read-write + + + CARD0_WIDTH1 + Indicates if card 0 is 8-bit: 0 - Non 8-bit mode 1 - 8-bit mode. + 16 + 1 + read-write + + + CARD1_WIDTH1 + Indicates if card 1 is 8-bit: 0 - Non 8-bit mode 1 - 8-bit mode. + 17 + 1 + read-write + + + + + BLKSIZ + Block Size register + 0x1C + 32 + read-write + 0x200 + 0xFFFF + + + BLOCK_SIZE + Block size. + 0 + 16 + read-write + + + + + BYTCNT + Byte Count register + 0x20 + 32 + read-write + 0x200 + 0xFFFFFFFF + + + BYTE_COUNT + Number of bytes to be transferred; should be integer multiple of Block Size for block transfers. + 0 + 32 + read-write + + + + + INTMASK + Interrupt Mask register + 0x24 + 32 + read-write + 0 + 0x1FFFF + + + CDET + Card detect. + 0 + 1 + read-write + + + RE + Response error. + 1 + 1 + read-write + + + CDONE + Command done. + 2 + 1 + read-write + + + DTO + Data transfer over. + 3 + 1 + read-write + + + TXDR + Transmit FIFO data request. + 4 + 1 + read-write + + + RXDR + Receive FIFO data request. + 5 + 1 + read-write + + + RCRC + Response CRC error. + 6 + 1 + read-write + + + DCRC + Data CRC error. + 7 + 1 + read-write + + + RTO + Response time-out. + 8 + 1 + read-write + + + DRTO + Data read time-out. + 9 + 1 + read-write + + + HTO + Data starvation-by-host time-out (HTO). + 10 + 1 + read-write + + + FRUN + FIFO underrun/overrun error. + 11 + 1 + read-write + + + HLE + Hardware locked write error. + 12 + 1 + read-write + + + SBE + Start-bit error. + 13 + 1 + read-write + + + ACD + Auto command done. + 14 + 1 + read-write + + + EBE + End-bit error (read)/Write no CRC. + 15 + 1 + read-write + + + SDIO_INT_MASK + Mask SDIO interrupt. + 16 + 1 + read-write + + + + + CMDARG + Command Argument register + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + CMD_ARG + Value indicates command argument to be passed to card. + 0 + 32 + read-write + + + + + CMD + Command register + 0x2C + 32 + read-write + 0 + 0xBFFFFFFF + + + CMD_INDEX + Command index. + 0 + 6 + read-write + + + RESPONSE_EXPECT + Response expect. + 6 + 1 + read-write + + + RESPONSE_LENGTH + Response length. + 7 + 1 + read-write + + + CHECK_RESPONSE_CRC + Check response CRC. + 8 + 1 + read-write + + + DATA_EXPECTED + Data expected. + 9 + 1 + read-write + + + READ_WRITE + read/write. + 10 + 1 + read-write + + + TRANSFER_MODE + Transfer mode. + 11 + 1 + read-write + + + SEND_AUTO_STOP + Send auto stop. + 12 + 1 + read-write + + + WAIT_PRVDATA_COMPLETE + Wait prvdata complete. + 13 + 1 + read-write + + + STOP_ABORT_CMD + Stop abort command. + 14 + 1 + read-write + + + SEND_INITIALIZATION + Send initialization. + 15 + 1 + read-write + + + CARD_NUMBER + Specifies the card number of SDCARD for which the current Command is being executed + 16 + 5 + read-write + + + CARD0 + Command will be execute on SDCARD 0 + 0 + + + CARD1 + Command will be execute on SDCARD 1 + 0x1 + + + + + UPDATE_CLOCK_REGISTERS_ONLY + Update clock registers only. + 21 + 1 + read-write + + + READ_CEATA_DEVICE + Read ceata device. + 22 + 1 + read-write + + + CCS_EXPECTED + CCS expected. + 23 + 1 + read-write + + + ENABLE_BOOT + Enable Boot - this bit should be set only for mandatory boot mode. + 24 + 1 + read-write + + + EXPECT_BOOT_ACK + Expect Boot Acknowledge. + 25 + 1 + read-write + + + DISABLE_BOOT + Disable Boot. + 26 + 1 + read-write + + + BOOT_MODE + Boot Mode. + 27 + 1 + read-write + + + VOLT_SWITCH + Voltage switch bit. + 28 + 1 + read-write + + + USE_HOLD_REG + Use Hold Register. + 29 + 1 + read-write + + + START_CMD + Start command. + 31 + 1 + read-write + + + + + 4 + 0x4 + RESP[%s] + Response register + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + RESPONSE + Bits of response. + 0 + 32 + read-write + + + + + MINTSTS + Masked Interrupt Status register + 0x40 + 32 + read-write + 0 + 0x1FFFF + + + CDET + Card detect. + 0 + 1 + read-write + + + RE + Response error. + 1 + 1 + read-write + + + CDONE + Command done. + 2 + 1 + read-write + + + DTO + Data transfer over. + 3 + 1 + read-write + + + TXDR + Transmit FIFO data request. + 4 + 1 + read-write + + + RXDR + Receive FIFO data request. + 5 + 1 + read-write + + + RCRC + Response CRC error. + 6 + 1 + read-write + + + DCRC + Data CRC error. + 7 + 1 + read-write + + + RTO + Response time-out. + 8 + 1 + read-write + + + DRTO + Data read time-out. + 9 + 1 + read-write + + + HTO + Data starvation-by-host time-out (HTO). + 10 + 1 + read-write + + + FRUN + FIFO underrun/overrun error. + 11 + 1 + read-write + + + HLE + Hardware locked write error. + 12 + 1 + read-write + + + SBE + Start-bit error. + 13 + 1 + read-write + + + ACD + Auto command done. + 14 + 1 + read-write + + + EBE + End-bit error (read)/write no CRC. + 15 + 1 + read-write + + + SDIO_INTERRUPT + Interrupt from SDIO card. + 16 + 1 + read-write + + + + + RINTSTS + Raw Interrupt Status register + 0x44 + 32 + read-write + 0 + 0x1FFFF + + + CDET + Card detect. + 0 + 1 + read-write + + + RE + Response error. + 1 + 1 + read-write + + + CDONE + Command done. + 2 + 1 + read-write + + + DTO + Data transfer over. + 3 + 1 + read-write + + + TXDR + Transmit FIFO data request. + 4 + 1 + read-write + + + RXDR + Receive FIFO data request. + 5 + 1 + read-write + + + RCRC + Response CRC error. + 6 + 1 + read-write + + + DCRC + Data CRC error. + 7 + 1 + read-write + + + RTO_BAR + Response time-out (RTO)/Boot Ack Received (BAR). + 8 + 1 + read-write + + + DRTO_BDS + Data read time-out (DRTO)/Boot Data Start (BDS). + 9 + 1 + read-write + + + HTO + Data starvation-by-host time-out (HTO). + 10 + 1 + read-write + + + FRUN + FIFO underrun/overrun error. + 11 + 1 + read-write + + + HLE + Hardware locked write error. + 12 + 1 + read-write + + + SBE + Start-bit error. + 13 + 1 + read-write + + + ACD + Auto command done. + 14 + 1 + read-write + + + EBE + End-bit error (read)/write no CRC. + 15 + 1 + read-write + + + SDIO_INTERRUPT + Interrupt from SDIO card. + 16 + 1 + read-write + + + + + STATUS + Status register + 0x48 + 32 + read-write + 0x406 + 0xFFFFFFFF + + + FIFO_RX_WATERMARK + FIFO reached Receive watermark level; not qualified with data transfer. + 0 + 1 + read-write + + + FIFO_TX_WATERMARK + FIFO reached Transmit watermark level; not qualified with data transfer. + 1 + 1 + read-write + + + FIFO_EMPTY + FIFO is empty status. + 2 + 1 + read-write + + + FIFO_FULL + FIFO is full status. + 3 + 1 + read-write + + + CMDFSMSTATES + Command FSM states: 0 - Idle 1 - Send init sequence 2 - Tx cmd start bit 3 - Tx cmd tx bit 4 - Tx cmd index + arg 5 - Tx cmd crc7 6 - Tx cmd end bit 7 - Rx resp start bit 8 - Rx resp IRQ response 9 - Rx resp tx bit 10 - Rx resp cmd idx 11 - Rx resp data 12 - Rx resp crc7 13 - Rx resp end bit 14 - Cmd path wait NCC 15 - Wait; CMD-to-response turnaround NOTE: The command FSM state is represented using 19 bits. + 4 + 4 + read-write + + + DATA_3_STATUS + Raw selected card_data[3]; checks whether card is present 0 - card not present 1 - card present. + 8 + 1 + read-write + + + DATA_BUSY + Inverted version of raw selected card_data[0] 0 - card data not busy 1 - card data busy. + 9 + 1 + read-write + + + DATA_STATE_MC_BUSY + Data transmit or receive state-machine is busy. + 10 + 1 + read-write + + + RESPONSE_INDEX + Index of previous response, including any auto-stop sent by core. + 11 + 6 + read-write + + + FIFO_COUNT + FIFO count - Number of filled locations in FIFO. + 17 + 13 + read-write + + + DMA_ACK + DMA acknowledge signal state. + 30 + 1 + read-write + + + DMA_REQ + DMA request signal state. + 31 + 1 + read-write + + + + + FIFOTH + FIFO Threshold Watermark register + 0x4C + 32 + read-write + 0x1F0000 + 0x7FFF0FFF + + + TX_WMARK + FIFO threshold watermark level when transmitting data to card. + 0 + 12 + read-write + + + RX_WMARK + FIFO threshold watermark level when receiving data to card. + 16 + 12 + read-write + + + DMA_MTS + Burst size of multiple transaction; should be programmed same as DW-DMA controller multiple-transaction-size SRC/DEST_MSIZE. + 28 + 3 + read-write + + + + + CDETECT + Card Detect register + 0x50 + 32 + read-write + 0 + 0x1 + + + CARD0_DETECT + Card 0 detect + 0 + 1 + read-write + + + CARD1_DETECT + Card 1 detect + 1 + 1 + read-write + + + + + WRTPRT + Write Protect register + 0x54 + 32 + read-write + 0 + 0x1 + + + WRITE_PROTECT + Write protect. + 0 + 1 + read-write + + + + + TCBCNT + Transferred CIU Card Byte Count register + 0x5C + 32 + read-write + 0 + 0xFFFFFFFF + + + TRANS_CARD_BYTE_COUNT + Number of bytes transferred by CIU unit to card. + 0 + 32 + read-write + + + + + TBBCNT + Transferred Host to BIU-FIFO Byte Count register + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + TRANS_FIFO_BYTE_COUNT + Number of bytes transferred between Host/DMA memory and BIU FIFO. + 0 + 32 + read-write + + + + + DEBNCE + Debounce Count register + 0x64 + 32 + read-write + 0xFFFFFF + 0xFFFFFF + + + DEBOUNCE_COUNT + Number of host clocks (SD_CLK) used by debounce filter logic for card detect; typical debounce time is 5-25 ms. + 0 + 24 + read-write + + + + + RST_N + Hardware Reset + 0x78 + 32 + read-write + 0x1 + 0x1 + + + CARD_RESET + Hardware reset. + 0 + 1 + read-write + + + + + BMOD + Bus Mode register + 0x80 + 32 + read-write + 0 + 0x7FF + + + SWR + Software Reset. + 0 + 1 + read-write + + + FB + Fixed Burst. + 1 + 1 + read-write + + + DSL + Descriptor Skip Length. + 2 + 5 + read-write + + + DE + SD/MMC DMA Enable. + 7 + 1 + read-write + + + PBL + Programmable Burst Length. + 8 + 3 + read-write + + + + + PLDMND + Poll Demand register + 0x84 + 32 + read-write + 0 + 0xFFFFFFFF + + + PD + Poll Demand. + 0 + 32 + read-write + + + + + DBADDR + Descriptor List Base Address register + 0x88 + 32 + read-write + 0 + 0xFFFFFFFF + + + SDL + Start of Descriptor List. + 0 + 32 + read-write + + + + + IDSTS + Internal DMAC Status register + 0x8C + 32 + read-write + 0 + 0x1FF37 + + + TI + Transmit Interrupt. + 0 + 1 + read-write + + + RI + Receive Interrupt. + 1 + 1 + read-write + + + FBE + Fatal Bus Error Interrupt. + 2 + 1 + read-write + + + DU + Descriptor Unavailable Interrupt. + 4 + 1 + read-write + + + CES + Card Error Summary. + 5 + 1 + read-write + + + NIS + Normal Interrupt Summary. + 8 + 1 + read-write + + + AIS + Abnormal Interrupt Summary. + 9 + 1 + read-write + + + EB + Error Bits. + 10 + 3 + read-write + + + FSM + DMAC state machine present state. + 13 + 4 + read-write + + + + + IDINTEN + Internal DMAC Interrupt Enable register + 0x90 + 32 + read-write + 0 + 0x337 + + + TI + Transmit Interrupt Enable. + 0 + 1 + read-write + + + RI + Receive Interrupt Enable. + 1 + 1 + read-write + + + FBE + Fatal Bus Error Enable. + 2 + 1 + read-write + + + DU + Descriptor Unavailable Interrupt. + 4 + 1 + read-write + + + CES + Card Error summary Interrupt Enable. + 5 + 1 + read-write + + + NIS + Normal Interrupt Summary Enable. + 8 + 1 + read-write + + + AIS + Abnormal Interrupt Summary Enable. + 9 + 1 + read-write + + + + + DSCADDR + Current Host Descriptor Address register + 0x94 + 32 + read-write + 0 + 0xFFFFFFFF + + + HDA + Host Descriptor Address Pointer. + 0 + 32 + read-write + + + + + BUFADDR + Current Buffer Descriptor Address register + 0x98 + 32 + read-write + 0 + 0xFFFFFFFF + + + HBA + Host Buffer Address Pointer. + 0 + 32 + read-write + + + + + CARDTHRCTL + Card Threshold Control + 0x100 + 32 + read-write + 0 + 0xFF0003 + + + CARDRDTHREN + Card Read Threshold Enable. + 0 + 1 + read-write + + + BSYCLRINTEN + Busy Clear Interrupt Enable. + 1 + 1 + read-write + + + CARDTHRESHOLD + Card Threshold size. + 16 + 8 + read-write + + + + + BACKENDPWR + Power control + 0x104 + 32 + read-write + 0 + 0x1 + + + BACKENDPWR + Back-end Power control for card application. + 0 + 1 + read-write + + + + + 64 + 0x4 + FIFO[%s] + SDIF FIFO + 0x200 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + SDIF FIFO. + 0 + 32 + read-write + + + + + + + DGBMAILBOX + MCU Debugger Mailbox + DGBMAILBOX + 0x4009C000 + + 0 + 0x100 + registers + + + + CSW + CRC mode register + 0 + 32 + read-write + 0 + 0x3F + + + RESYNCH_REQ + Debugger will set this bit to 1 to request a resynchronrisation + 0 + 1 + read-write + + + REQ_PENDING + Request is pending from debugger (i.e unread value in REQUEST) + 1 + 1 + read-write + + + DBG_OR_ERR + Debugger overrun error (previous REQUEST overwritten before being picked up by ROM) + 2 + 1 + read-write + + + AHB_OR_ERR + AHB overrun Error (Return value overwritten by ROM) + 3 + 1 + read-write + + + SOFT_RESET + Soft Reset for DM (write-only from AHB, not readable and selfclearing). A write to this bit will cause a soft reset for DM. + 4 + 1 + read-write + + + CHIP_RESET_REQ + Write only bit. Once written will cause the chip to reset (note that the DM is not reset by this reset as it is only resettable by a SOFT reset or a POR/BOD event) + 5 + 1 + write-only + + + + + REQUEST + CRC seed register + 0x4 + 32 + read-write + 0xFFFF + 0xFFFFFFFF + + + REQ + Request Value + 0 + 32 + read-write + + + + + RETURN + Return value from ROM. + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + RET + The Return value from ROM. + 0 + 32 + read-write + + + + + ID + Identification register + 0xFC + 32 + read-only + 0x2A0000 + 0xFFFFFFFF + + + ID + Identification value. + 0 + 32 + read-only + + + + + + + ADC0 + ADC + ADC + 0x400A0000 + + 0 + 0x1000 + registers + + + ADC0 + 22 + + + + VERID + Version ID Register + 0 + 32 + read-only + 0x1002C0B + 0xFFFFFFFF + + + RES + Resolution + 0 + 1 + read-only + + + RES_0 + Up to 13-bit differential/12-bit single ended resolution supported. + 0 + + + RES_1 + Up to 16-bit differential/16-bit single ended resolution supported. + 0x1 + + + + + DIFFEN + Differential Supported + 1 + 1 + read-only + + + DIFFEN_0 + Differential operation not supported. + 0 + + + DIFFEN_1 + Differential operation supported. CMDLa[CTYPE] controls fields implemented. + 0x1 + + + + + MVI + Multi Vref Implemented + 3 + 1 + read-only + + + MVI_0 + Single voltage reference high (VREFH) input supported. + 0 + + + MVI_1 + Multiple voltage reference high (VREFH) inputs supported. + 0x1 + + + + + CSW + Channel Scale Width + 4 + 3 + read-only + + + CSW_0 + Channel scaling not supported. + 0 + + + CSW_1 + Channel scaling supported. 1-bit CSCALE control field. + 0x1 + + + CSW_6 + Channel scaling supported. 6-bit CSCALE control field. + 0x6 + + + + + VR1RNGI + Voltage Reference 1 Range Control Bit Implemented + 8 + 1 + read-only + + + VR1RNGI_0 + Range control not required. CFG[VREF1RNG] is not implemented. + 0 + + + VR1RNGI_1 + Range control required. CFG[VREF1RNG] is implemented. + 0x1 + + + + + IADCKI + Internal ADC Clock implemented + 9 + 1 + read-only + + + IADCKI_0 + Internal clock source not implemented. + 0 + + + IADCKI_1 + Internal clock source (and CFG[ADCKEN]) implemented. + 0x1 + + + + + CALOFSI + Calibration Function Implemented + 10 + 1 + read-only + + + CALOFSI_0 + Calibration Not Implemented. + 0 + + + CALOFSI_1 + Calibration Implemented. + 0x1 + + + + + NUM_SEC + Number of Single Ended Outputs Supported + 11 + 1 + read-only + + + NUM_SEC_0 + This design supports one single ended conversion at a time. + 0 + + + NUM_SEC_1 + This design supports two simultanious single ended conversions. + 0x1 + + + + + NUM_FIFO + Number of FIFOs + 12 + 3 + read-only + + + NUM_FIFO_0 + N/A + 0 + + + NUM_FIFO_1 + This design supports one result FIFO. + 0x1 + + + NUM_FIFO_2 + This design supports two result FIFOs. + 0x2 + + + NUM_FIFO_3 + This design supports three result FIFOs. + 0x3 + + + NUM_FIFO_4 + This design supports four result FIFOs. + 0x4 + + + + + MINOR + Minor Version Number + 16 + 8 + read-only + + + MAJOR + Major Version Number + 24 + 8 + read-only + + + + + PARAM + Parameter Register + 0x4 + 32 + read-only + 0xF041010 + 0xFFFFFFFF + + + TRIG_NUM + Trigger Number + 0 + 8 + read-only + + + FIFOSIZE + Result FIFO Depth + 8 + 8 + read-only + + + FIFOSIZE_1 + Result FIFO depth = 1 dataword. + 0x1 + + + FIFOSIZE_4 + Result FIFO depth = 4 datawords. + 0x4 + + + FIFOSIZE_8 + Result FIFO depth = 8 datawords. + 0x8 + + + FIFOSIZE_16 + Result FIFO depth = 16 datawords. + 0x10 + + + FIFOSIZE_32 + Result FIFO depth = 32 datawords. + 0x20 + + + FIFOSIZE_64 + Result FIFO depth = 64 datawords. + 0x40 + + + + + CV_NUM + Compare Value Number + 16 + 8 + read-only + + + CMD_NUM + Command Buffer Number + 24 + 8 + read-only + + + + + CTRL + ADC Control Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADCEN + ADC Enable + 0 + 1 + read-write + + + ADCEN_0 + ADC is disabled. + 0 + + + ADCEN_1 + ADC is enabled. + 0x1 + + + + + RST + Software Reset + 1 + 1 + read-write + + + RST_0 + ADC logic is not reset. + 0 + + + RST_1 + ADC logic is reset. + 0x1 + + + + + DOZEN + Doze Enable + 2 + 1 + read-write + + + DOZEN_0 + ADC is enabled in Doze mode. + 0 + + + DOZEN_1 + ADC is disabled in Doze mode. + 0x1 + + + + + CAL_REQ + Auto-Calibration Request + 3 + 1 + read-write + + + CAL_REQ_0 + No request for auto-calibration has been made. + 0 + + + CAL_REQ_1 + A request for auto-calibration has been made + 0x1 + + + + + CALOFS + Configure for offset calibration function + 4 + 1 + read-write + + + CALOFS_0 + Calibration function disabled + 0 + + + CALOFS_1 + Request for offset calibration function + 0x1 + + + + + RSTFIFO0 + Reset FIFO 0 + 8 + 1 + read-write + + + RSTFIFO0_0 + No effect. + 0 + + + RSTFIFO0_1 + FIFO 0 is reset. + 0x1 + + + + + RSTFIFO1 + Reset FIFO 1 + 9 + 1 + read-write + + + RSTFIFO1_0 + No effect. + 0 + + + RSTFIFO1_1 + FIFO 1 is reset. + 0x1 + + + + + CAL_AVGS + Auto-Calibration Averages + 16 + 3 + read-write + + + CAL_AVGS_0 + Single conversion. + 0 + + + CAL_AVGS_1 + 2 conversions averaged. + 0x1 + + + CAL_AVGS_2 + 4 conversions averaged. + 0x2 + + + CAL_AVGS_3 + 8 conversions averaged. + 0x3 + + + CAL_AVGS_4 + 16 conversions averaged. + 0x4 + + + CAL_AVGS_5 + 32 conversions averaged. + 0x5 + + + CAL_AVGS_6 + 64 conversions averaged. + 0x6 + + + CAL_AVGS_7 + 128 conversions averaged. + 0x7 + + + + + + + STAT + ADC Status Register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + RDY0 + Result FIFO 0 Ready Flag + 0 + 1 + read-only + + + RDY0_0 + Result FIFO 0 data level not above watermark level. + 0 + + + RDY0_1 + Result FIFO 0 holding data above watermark level. + 0x1 + + + + + FOF0 + Result FIFO 0 Overflow Flag + 1 + 1 + read-write + oneToClear + + + FOF0_0 + No result FIFO 0 overflow has occurred since the last time the flag was cleared. + 0 + + + FOF0_1 + At least one result FIFO 0 overflow has occurred since the last time the flag was cleared. + 0x1 + + + + + RDY1 + Result FIFO1 Ready Flag + 2 + 1 + read-only + + + RDY1_0 + Result FIFO1 data level not above watermark level. + 0 + + + RDY1_1 + Result FIFO1 holding data above watermark level. + 0x1 + + + + + FOF1 + Result FIFO1 Overflow Flag + 3 + 1 + read-write + oneToClear + + + FOF1_0 + No result FIFO1 overflow has occurred since the last time the flag was cleared. + 0 + + + FOF1_1 + At least one result FIFO1 overflow has occurred since the last time the flag was cleared. + 0x1 + + + + + TEXC_INT + Interrupt Flag For High Priority Trigger Exception + 8 + 1 + read-write + oneToClear + + + TEXC_INT_0 + No trigger exceptions have occurred. + 0 + + + TEXC_INT_1 + A trigger exception has occurred and is pending acknowledgement. + 0x1 + + + + + TCOMP_INT + Interrupt Flag For Trigger Completion + 9 + 1 + read-write + oneToClear + + + TCOMP_INT_0 + Either IE[TCOMP_IE] is set to 0, or no trigger sequences have run to completion. + 0 + + + TCOMP_INT_1 + Trigger sequence has been completed and all data is stored in the associated FIFO. + 0x1 + + + + + CAL_RDY + Calibration Ready + 10 + 1 + read-only + + + CAL_RDY_0 + Calibration is incomplete or hasn't been ran. + 0 + + + CAL_RDY_1 + The ADC is calibrated. + 0x1 + + + + + ADC_ACTIVE + ADC Active + 11 + 1 + read-only + + + ADC_ACTIVE_0 + The ADC is IDLE. There are no pending triggers to service and no active commands are being processed. + 0 + + + ADC_ACTIVE_1 + The ADC is processing a conversion, running through the power up delay, or servicing a trigger. + 0x1 + + + + + TRGACT + Trigger Active + 16 + 4 + read-only + + + TRGACT_0 + Command (sequence) associated with Trigger 0 currently being executed. + 0 + + + TRGACT_1 + Command (sequence) associated with Trigger 1 currently being executed. + 0x1 + + + TRGACT_2 + Command (sequence) associated with Trigger 2 currently being executed. + 0x2 + + + TRGACT_3 + Command (sequence) from the associated Trigger number is currently being executed. + 0x3 + + + TRGACT_4 + Command (sequence) from the associated Trigger number is currently being executed. + 0x4 + + + TRGACT_5 + Command (sequence) from the associated Trigger number is currently being executed. + 0x5 + + + TRGACT_6 + Command (sequence) from the associated Trigger number is currently being executed. + 0x6 + + + TRGACT_7 + Command (sequence) from the associated Trigger number is currently being executed. + 0x7 + + + TRGACT_8 + Command (sequence) from the associated Trigger number is currently being executed. + 0x8 + + + TRGACT_9 + Command (sequence) from the associated Trigger number is currently being executed. + 0x9 + + + + + CMDACT + Command Active + 24 + 4 + read-only + + + CMDACT_0 + No command is currently in progress. + 0 + + + CMDACT_1 + Command 1 currently being executed. + 0x1 + + + CMDACT_2 + Command 2 currently being executed. + 0x2 + + + CMDACT_3 + Associated command number is currently being executed. + 0x3 + + + CMDACT_4 + Associated command number is currently being executed. + 0x4 + + + CMDACT_5 + Associated command number is currently being executed. + 0x5 + + + CMDACT_6 + Associated command number is currently being executed. + 0x6 + + + CMDACT_7 + Associated command number is currently being executed. + 0x7 + + + CMDACT_8 + Associated command number is currently being executed. + 0x8 + + + CMDACT_9 + Associated command number is currently being executed. + 0x9 + + + + + + + IE + Interrupt Enable Register + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + FWMIE0 + FIFO 0 Watermark Interrupt Enable + 0 + 1 + read-write + + + FWMIE0_0 + FIFO 0 watermark interrupts are not enabled. + 0 + + + FWMIE0_1 + FIFO 0 watermark interrupts are enabled. + 0x1 + + + + + FOFIE0 + Result FIFO 0 Overflow Interrupt Enable + 1 + 1 + read-write + + + FOFIE0_0 + FIFO 0 overflow interrupts are not enabled. + 0 + + + FOFIE0_1 + FIFO 0 overflow interrupts are enabled. + 0x1 + + + + + FWMIE1 + FIFO1 Watermark Interrupt Enable + 2 + 1 + read-write + + + FWMIE1_0 + FIFO1 watermark interrupts are not enabled. + 0 + + + FWMIE1_1 + FIFO1 watermark interrupts are enabled. + 0x1 + + + + + FOFIE1 + Result FIFO1 Overflow Interrupt Enable + 3 + 1 + read-write + + + FOFIE1_0 + No result FIFO1 overflow has occurred since the last time the flag was cleared. + 0 + + + FOFIE1_1 + At least one result FIFO1 overflow has occurred since the last time the flag was cleared. + 0x1 + + + + + TEXC_IE + Trigger Exception Interrupt Enable + 8 + 1 + read-write + + + TEXC_IE_0 + Trigger exception interrupts are disabled. + 0 + + + TEXC_IE_1 + Trigger exception interrupts are enabled. + 0x1 + + + + + TCOMP_IE + Trigger Completion Interrupt Enable + 16 + 16 + read-write + + + TCOMP_IE_0 + Trigger completion interrupts are disabled. + 0 + + + TCOMP_IE_1 + Trigger completion interrupts are enabled for trigger source 0 only. + 0x1 + + + TCOMP_IE_2 + Trigger completion interrupts are enabled for trigger source 1 only. + 0x2 + + + TCOMP_IE_3 + Associated trigger completion interrupts are enabled. + 0x3 + + + TCOMP_IE_4 + Associated trigger completion interrupts are enabled. + 0x4 + + + TCOMP_IE_5 + Associated trigger completion interrupts are enabled. + 0x5 + + + TCOMP_IE_6 + Associated trigger completion interrupts are enabled. + 0x6 + + + TCOMP_IE_7 + Associated trigger completion interrupts are enabled. + 0x7 + + + TCOMP_IE_8 + Associated trigger completion interrupts are enabled. + 0x8 + + + TCOMP_IE_9 + Associated trigger completion interrupts are enabled. + 0x9 + + + TCOMP_IE_65535 + Trigger completion interrupts are enabled for every trigger source. + 0xFFFF + + + + + + + DE + DMA Enable Register + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + FWMDE0 + FIFO 0 Watermark DMA Enable + 0 + 1 + read-write + + + FWMDE0_0 + DMA request disabled. + 0 + + + FWMDE0_1 + DMA request enabled. + 0x1 + + + + + FWMDE1 + FIFO1 Watermark DMA Enable + 1 + 1 + read-write + + + FWMDE1_0 + DMA request disabled. + 0 + + + FWMDE1_1 + DMA request enabled. + 0x1 + + + + + + + CFG + ADC Configuration Register + 0x20 + 32 + read-write + 0x800000 + 0xFFFFFFFF + + + TPRICTRL + ADC trigger priority control + 0 + 2 + read-write + + + TPRICTRL_0 + If a higher priority trigger is detected during command processing, the current conversion is aborted and the new command specified by the trigger is started. + 0 + + + TPRICTRL_1 + If a higher priority trigger is received during command processing, the current command is stopped after after completing the current conversion. If averaging is enabled, the averaging loop will be completed. However, CMDHa[LOOP] will be ignored and the higher priority trigger will be serviced. + 0x1 + + + TPRICTRL_2 + If a higher priority trigger is received during command processing, the current command will be completed (averaging, looping, compare) before servicing the higher priority trigger. + 0x2 + + + + + PWRSEL + Power Configuration Select + 4 + 2 + read-write + + + PWRSEL_0 + Lowest power setting. + 0 + + + PWRSEL_1 + Higher power setting than 0b0. + 0x1 + + + PWRSEL_2 + Higher power setting than 0b1. + 0x2 + + + PWRSEL_3 + Highest power setting. + 0x3 + + + + + REFSEL + Voltage Reference Selection + 6 + 2 + read-write + + + REFSEL_0 + (Default) Option 1 setting. + 0 + + + REFSEL_1 + Option 2 setting. + 0x1 + + + REFSEL_2 + Option 3 setting. + 0x2 + + + + + TRES + Trigger Resume Enable + 8 + 1 + read-write + + + TRES_0 + Trigger sequences interrupted by a high priority trigger exception will not be automatically resumed or restarted. + 0 + + + TRES_1 + Trigger sequences interrupted by a high priority trigger exception will be automatically resumed or restarted. + 0x1 + + + + + TCMDRES + Trigger Command Resume + 9 + 1 + read-write + + + TCMDRES_0 + Trigger sequences interrupted by a high priority trigger exception will be automatically restarted. + 0 + + + TCMDRES_1 + Trigger sequences interrupted by a high priority trigger exception will be resumed from the command executing before the exception. + 0x1 + + + + + HPT_EXDI + High Priority Trigger Exception Disable + 10 + 1 + read-write + + + HPT_EXDI_0 + High priority trigger exceptions are enabled. + 0 + + + HPT_EXDI_1 + High priority trigger exceptions are disabled. + 0x1 + + + + + PUDLY + Power Up Delay + 16 + 8 + read-write + + + PWREN + ADC Analog Pre-Enable + 28 + 1 + read-write + + + PWREN_0 + ADC analog circuits are only enabled while conversions are active. Performance is affected due to analog startup delays. + 0 + + + PWREN_1 + ADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the cost of higher DC current consumption). A single power up delay (CFG[PUDLY]) is executed immediately once PWREN is set, and any detected trigger does not begin ADC operation until the power up delay time has passed. After this initial delay expires the analog will remain pre-enabled, and no additional delays will be executed. + 0x1 + + + + + + + PAUSE + ADC Pause Register + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + PAUSEDLY + Pause Delay + 0 + 9 + read-write + + + PAUSEEN + PAUSE Option Enable + 31 + 1 + read-write + + + PAUSEEN_0 + Pause operation disabled + 0 + + + PAUSEEN_1 + Pause operation enabled + 0x1 + + + + + + + SWTRIG + Software Trigger Register + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + SWT0 + Software trigger 0 event + 0 + 1 + read-write + + + SWT0_0 + No trigger 0 event generated. + 0 + + + SWT0_1 + Trigger 0 event generated. + 0x1 + + + + + SWT1 + Software trigger 1 event + 1 + 1 + read-write + + + SWT1_0 + No trigger 1 event generated. + 0 + + + SWT1_1 + Trigger 1 event generated. + 0x1 + + + + + SWT2 + Software trigger 2 event + 2 + 1 + read-write + + + SWT2_0 + No trigger 2 event generated. + 0 + + + SWT2_1 + Trigger 2 event generated. + 0x1 + + + + + SWT3 + Software trigger 3 event + 3 + 1 + read-write + + + SWT3_0 + No trigger 3 event generated. + 0 + + + SWT3_1 + Trigger 3 event generated. + 0x1 + + + + + SWT4 + Software trigger 4 event + 4 + 1 + read-write + + + SWT4_0 + No trigger 4 event generated. + 0 + + + SWT4_1 + Trigger 4 event generated. + 0x1 + + + + + SWT5 + Software trigger 5 event + 5 + 1 + read-write + + + SWT5_0 + No trigger 5 event generated. + 0 + + + SWT5_1 + Trigger 5 event generated. + 0x1 + + + + + SWT6 + Software trigger 6 event + 6 + 1 + read-write + + + SWT6_0 + No trigger 6 event generated. + 0 + + + SWT6_1 + Trigger 6 event generated. + 0x1 + + + + + SWT7 + Software trigger 7 event + 7 + 1 + read-write + + + SWT7_0 + No trigger 7 event generated. + 0 + + + SWT7_1 + Trigger 7 event generated. + 0x1 + + + + + SWT8 + Software trigger 8 event + 8 + 1 + read-write + + + SWT8_0 + No trigger 8 event generated. + 0 + + + SWT8_1 + Trigger 8 event generated. + 0x1 + + + + + SWT9 + Software trigger 9 event + 9 + 1 + read-write + + + SWT9_0 + No trigger 9 event generated. + 0 + + + SWT9_1 + Trigger 9 event generated. + 0x1 + + + + + SWT10 + Software trigger 10 event + 10 + 1 + read-write + + + SWT10_0 + No trigger 10 event generated. + 0 + + + SWT10_1 + Trigger 10 event generated. + 0x1 + + + + + SWT11 + Software trigger 11 event + 11 + 1 + read-write + + + SWT11_0 + No trigger 11 event generated. + 0 + + + SWT11_1 + Trigger 11 event generated. + 0x1 + + + + + SWT12 + Software trigger 12 event + 12 + 1 + read-write + + + SWT12_0 + No trigger 12 event generated. + 0 + + + SWT12_1 + Trigger 12 event generated. + 0x1 + + + + + SWT13 + Software trigger 13 event + 13 + 1 + read-write + + + SWT13_0 + No trigger 13 event generated. + 0 + + + SWT13_1 + Trigger 13 event generated. + 0x1 + + + + + SWT14 + Software trigger 14 event + 14 + 1 + read-write + + + SWT14_0 + No trigger 14 event generated. + 0 + + + SWT14_1 + Trigger 14 event generated. + 0x1 + + + + + SWT15 + Software trigger 15 event + 15 + 1 + read-write + + + SWT15_0 + No trigger 15 event generated. + 0 + + + SWT15_1 + Trigger 15 event generated. + 0x1 + + + + + + + TSTAT + Trigger Status Register + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + TEXC_NUM + Trigger Exception Number + 0 + 16 + read-write + oneToClear + + + TEXC_NUM_0 + No triggers have been interrupted by a high priority exception. Or CFG[TRES] = 1. + 0 + + + TEXC_NUM_1 + Trigger 0 has been interrupted by a high priority exception. + 0x1 + + + TEXC_NUM_2 + Trigger 1 has been interrupted by a high priority exception. + 0x2 + + + TEXC_NUM_3 + Associated trigger sequence has interrupted by a high priority exception. + 0x3 + + + TEXC_NUM_4 + Associated trigger sequence has interrupted by a high priority exception. + 0x4 + + + TEXC_NUM_5 + Associated trigger sequence has interrupted by a high priority exception. + 0x5 + + + TEXC_NUM_6 + Associated trigger sequence has interrupted by a high priority exception. + 0x6 + + + TEXC_NUM_7 + Associated trigger sequence has interrupted by a high priority exception. + 0x7 + + + TEXC_NUM_8 + Associated trigger sequence has interrupted by a high priority exception. + 0x8 + + + TEXC_NUM_9 + Associated trigger sequence has interrupted by a high priority exception. + 0x9 + + + TEXC_NUM_65535 + Every trigger sequence has been interrupted by a high priority exception. + 0xFFFF + + + + + TCOMP_FLAG + Trigger Completion Flag + 16 + 16 + read-write + oneToClear + + + TCOMP_FLAG_0 + No triggers have been completed. Trigger completion interrupts are disabled. + 0 + + + TCOMP_FLAG_1 + Trigger 0 has been completed and triger 0 has enabled completion interrupts. + 0x1 + + + TCOMP_FLAG_2 + Trigger 1 has been completed and triger 1 has enabled completion interrupts. + 0x2 + + + TCOMP_FLAG_3 + Associated trigger sequence has completed and has enabled completion interrupts. + 0x3 + + + TCOMP_FLAG_4 + Associated trigger sequence has completed and has enabled completion interrupts. + 0x4 + + + TCOMP_FLAG_5 + Associated trigger sequence has completed and has enabled completion interrupts. + 0x5 + + + TCOMP_FLAG_6 + Associated trigger sequence has completed and has enabled completion interrupts. + 0x6 + + + TCOMP_FLAG_7 + Associated trigger sequence has completed and has enabled completion interrupts. + 0x7 + + + TCOMP_FLAG_8 + Associated trigger sequence has completed and has enabled completion interrupts. + 0x8 + + + TCOMP_FLAG_9 + Associated trigger sequence has completed and has enabled completion interrupts. + 0x9 + + + TCOMP_FLAG_65535 + Every trigger sequence has been completed and every trigger has enabled completion interrupts. + 0xFFFF + + + + + + + OFSTRIM + ADC Offset Trim Register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + OFSTRIM_A + Trim for offset + 0 + 5 + read-write + + + OFSTRIM_B + Trim for offset + 16 + 5 + read-write + + + + + 16 + 0x4 + TCTRL[%s] + Trigger Control Register + 0xA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + HTEN + Trigger enable + 0 + 1 + read-write + + + HTEN_0 + Hardware trigger source disabled + 0 + + + HTEN_1 + Hardware trigger source enabled + 0x1 + + + + + FIFO_SEL_A + SAR Result Destination For Channel A + 1 + 1 + read-write + + + FIFO_SEL_A_0 + Result written to FIFO 0 + 0 + + + FIFO_SEL_A_1 + Result written to FIFO 1 + 0x1 + + + + + FIFO_SEL_B + SAR Result Destination For Channel B + 2 + 1 + read-write + + + FIFO_SEL_B_0 + Result written to FIFO 0 + 0 + + + FIFO_SEL_B_1 + Result written to FIFO 1 + 0x1 + + + + + TPRI + Trigger priority setting + 8 + 4 + read-write + + + TPRI_0 + Set to highest priority, Level 1 + 0 + + + TPRI_1 + Set to corresponding priority level + 0x1 + + + TPRI_2 + Set to corresponding priority level + 0x2 + + + TPRI_3 + Set to corresponding priority level + 0x3 + + + TPRI_4 + Set to corresponding priority level + 0x4 + + + TPRI_5 + Set to corresponding priority level + 0x5 + + + TPRI_6 + Set to corresponding priority level + 0x6 + + + TPRI_7 + Set to corresponding priority level + 0x7 + + + TPRI_8 + Set to corresponding priority level + 0x8 + + + TPRI_9 + Set to corresponding priority level + 0x9 + + + TPRI_15 + Set to lowest priority, Level 16 + 0xF + + + + + RSYNC + Trigger Resync + 15 + 1 + read-write + + + TDLY + Trigger delay select + 16 + 4 + read-write + + + TCMD + Trigger command select + 24 + 4 + read-write + + + TCMD_0 + Not a valid selection from the command buffer. Trigger event is ignored. + 0 + + + TCMD_1 + CMD1 is executed + 0x1 + + + TCMD_2 + Corresponding CMD is executed + 0x2 + + + TCMD_3 + Corresponding CMD is executed + 0x3 + + + TCMD_4 + Corresponding CMD is executed + 0x4 + + + TCMD_5 + Corresponding CMD is executed + 0x5 + + + TCMD_6 + Corresponding CMD is executed + 0x6 + + + TCMD_7 + Corresponding CMD is executed + 0x7 + + + TCMD_8 + Corresponding CMD is executed + 0x8 + + + TCMD_9 + Corresponding CMD is executed + 0x9 + + + TCMD_15 + CMD15 is executed + 0xF + + + + + + + 2 + 0x4 + FCTRL[%s] + FIFO Control Register + 0xE0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FCOUNT + Result FIFO counter + 0 + 5 + read-only + + + FWMARK + Watermark level selection + 16 + 4 + read-write + + + + + 2 + 0x4 + GCC[%s] + Gain Calibration Control + 0xF0 + 32 + read-only + 0 + 0xFFFFFFFF + + + GAIN_CAL + Gain Calibration Value + 0 + 16 + read-only + + + RDY + Gain Calibration Value Valid + 24 + 1 + read-only + + + RDY_0 + The gain calibration value is invalid. Run the auto-calibration routine for this value to be written. + 0 + + + RDY_1 + The gain calibration value is valid. It should be used to update the GCRa[GCALR] register field. + 0x1 + + + + + + + 2 + 0x4 + GCR[%s] + Gain Calculation Result + 0xF8 + 32 + read-write + 0 + 0xFFFFFFFF + + + GCALR + Gain Calculation Result + 0 + 16 + read-write + + + RDY + Gain Calculation Ready + 24 + 1 + read-write + + + RDY_0 + The gain offset calculation value is invalid. + 0 + + + RDY_1 + The gain calibration value is valid. + 0x1 + + + + + + + CMDL1 + ADC Command Low Buffer Register + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADCH + Input channel select + 0 + 5 + read-write + + + ADCH_0 + Select CH0A or CH0B or CH0A/CH0B pair. + 0 + + + ADCH_1 + Select CH1A or CH1B or CH1A/CH1B pair. + 0x1 + + + ADCH_2 + Select CH2A or CH2B or CH2A/CH2B pair. + 0x2 + + + ADCH_3 + Select CH3A or CH3B or CH3A/CH3B pair. + 0x3 + + + ADCH_4 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x4 + + + ADCH_5 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x5 + + + ADCH_6 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x6 + + + ADCH_7 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x7 + + + ADCH_8 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x8 + + + ADCH_9 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x9 + + + ADCH_30 + Select CH30A or CH30B or CH30A/CH30B pair. + 0x1E + + + ADCH_31 + Select CH31A or CH31B or CH31A/CH31B pair. + 0x1F + + + + + CTYPE + Conversion Type + 5 + 2 + read-write + + + CTYPE_0 + Single-Ended Mode. Only A side channel is converted. + 0 + + + CTYPE_1 + Single-Ended Mode. Only B side channel is converted. + 0x1 + + + CTYPE_2 + Differential Mode. A-B. + 0x2 + + + CTYPE_3 + Dual-Single-Ended Mode. Both A side and B side channels are converted independently. + 0x3 + + + + + MODE + Select resolution of conversions + 7 + 1 + read-write + + + MODE_0 + Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. + 0 + + + MODE_1 + High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. + 0x1 + + + + + + + CMDH1 + ADC Command High Buffer Register + 0x104 + 32 + read-write + 0 + 0xFFFFFFFF + + + CMPEN + Compare Function Enable + 0 + 2 + read-write + + + CMPEN_0 + Compare disabled. + 0 + + + CMPEN_2 + Compare enabled. Store on true. + 0x2 + + + CMPEN_3 + Compare enabled. Repeat channel acquisition (sample/convert/compare) until true. + 0x3 + + + + + WAIT_TRIG + Wait for trigger assertion before execution. + 2 + 1 + read-write + + + WAIT_TRIG_0 + This command will be automatically executed. + 0 + + + WAIT_TRIG_1 + The active trigger must be asserted again before executing this command. + 0x1 + + + + + LWI + Loop with Increment + 7 + 1 + read-write + + + LWI_0 + Auto channel increment disabled + 0 + + + LWI_1 + Auto channel increment enabled + 0x1 + + + + + STS + Sample Time Select + 8 + 3 + read-write + + + STS_0 + Minimum sample time of 3 ADCK cycles. + 0 + + + STS_1 + 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. + 0x1 + + + STS_2 + 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. + 0x2 + + + STS_3 + 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. + 0x3 + + + STS_4 + 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. + 0x4 + + + STS_5 + 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. + 0x5 + + + STS_6 + 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. + 0x6 + + + STS_7 + 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. + 0x7 + + + + + AVGS + Hardware Average Select + 12 + 3 + read-write + + + AVGS_0 + Single conversion. + 0 + + + AVGS_1 + 2 conversions averaged. + 0x1 + + + AVGS_2 + 4 conversions averaged. + 0x2 + + + AVGS_3 + 8 conversions averaged. + 0x3 + + + AVGS_4 + 16 conversions averaged. + 0x4 + + + AVGS_5 + 32 conversions averaged. + 0x5 + + + AVGS_6 + 64 conversions averaged. + 0x6 + + + AVGS_7 + 128 conversions averaged. + 0x7 + + + + + LOOP + Loop Count Select + 16 + 4 + read-write + + + LOOP_0 + Looping not enabled. Command executes 1 time. + 0 + + + LOOP_1 + Loop 1 time. Command executes 2 times. + 0x1 + + + LOOP_2 + Loop 2 times. Command executes 3 times. + 0x2 + + + LOOP_3 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x3 + + + LOOP_4 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x4 + + + LOOP_5 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x5 + + + LOOP_6 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x6 + + + LOOP_7 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x7 + + + LOOP_8 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x8 + + + LOOP_9 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x9 + + + LOOP_15 + Loop 15 times. Command executes 16 times. + 0xF + + + + + NEXT + Next Command Select + 24 + 4 + read-write + + + NEXT_0 + No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. + 0 + + + NEXT_1 + Select CMD1 command buffer register as next command. + 0x1 + + + NEXT_2 + Select corresponding CMD command buffer register as next command + 0x2 + + + NEXT_3 + Select corresponding CMD command buffer register as next command + 0x3 + + + NEXT_4 + Select corresponding CMD command buffer register as next command + 0x4 + + + NEXT_5 + Select corresponding CMD command buffer register as next command + 0x5 + + + NEXT_6 + Select corresponding CMD command buffer register as next command + 0x6 + + + NEXT_7 + Select corresponding CMD command buffer register as next command + 0x7 + + + NEXT_8 + Select corresponding CMD command buffer register as next command + 0x8 + + + NEXT_9 + Select corresponding CMD command buffer register as next command + 0x9 + + + NEXT_15 + Select CMD15 command buffer register as next command. + 0xF + + + + + + + CMDL2 + ADC Command Low Buffer Register + 0x108 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADCH + Input channel select + 0 + 5 + read-write + + + ADCH_0 + Select CH0A or CH0B or CH0A/CH0B pair. + 0 + + + ADCH_1 + Select CH1A or CH1B or CH1A/CH1B pair. + 0x1 + + + ADCH_2 + Select CH2A or CH2B or CH2A/CH2B pair. + 0x2 + + + ADCH_3 + Select CH3A or CH3B or CH3A/CH3B pair. + 0x3 + + + ADCH_4 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x4 + + + ADCH_5 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x5 + + + ADCH_6 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x6 + + + ADCH_7 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x7 + + + ADCH_8 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x8 + + + ADCH_9 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x9 + + + ADCH_30 + Select CH30A or CH30B or CH30A/CH30B pair. + 0x1E + + + ADCH_31 + Select CH31A or CH31B or CH31A/CH31B pair. + 0x1F + + + + + CTYPE + Conversion Type + 5 + 2 + read-write + + + CTYPE_0 + Single-Ended Mode. Only A side channel is converted. + 0 + + + CTYPE_1 + Single-Ended Mode. Only B side channel is converted. + 0x1 + + + CTYPE_2 + Differential Mode. A-B. + 0x2 + + + CTYPE_3 + Dual-Single-Ended Mode. Both A side and B side channels are converted independently. + 0x3 + + + + + MODE + Select resolution of conversions + 7 + 1 + read-write + + + MODE_0 + Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. + 0 + + + MODE_1 + High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. + 0x1 + + + + + + + CMDH2 + ADC Command High Buffer Register + 0x10C + 32 + read-write + 0 + 0xFFFFFFFF + + + CMPEN + Compare Function Enable + 0 + 2 + read-write + + + CMPEN_0 + Compare disabled. + 0 + + + CMPEN_2 + Compare enabled. Store on true. + 0x2 + + + CMPEN_3 + Compare enabled. Repeat channel acquisition (sample/convert/compare) until true. + 0x3 + + + + + WAIT_TRIG + Wait for trigger assertion before execution. + 2 + 1 + read-write + + + WAIT_TRIG_0 + This command will be automatically executed. + 0 + + + WAIT_TRIG_1 + The active trigger must be asserted again before executing this command. + 0x1 + + + + + LWI + Loop with Increment + 7 + 1 + read-write + + + LWI_0 + Auto channel increment disabled + 0 + + + LWI_1 + Auto channel increment enabled + 0x1 + + + + + STS + Sample Time Select + 8 + 3 + read-write + + + STS_0 + Minimum sample time of 3 ADCK cycles. + 0 + + + STS_1 + 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. + 0x1 + + + STS_2 + 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. + 0x2 + + + STS_3 + 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. + 0x3 + + + STS_4 + 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. + 0x4 + + + STS_5 + 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. + 0x5 + + + STS_6 + 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. + 0x6 + + + STS_7 + 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. + 0x7 + + + + + AVGS + Hardware Average Select + 12 + 3 + read-write + + + AVGS_0 + Single conversion. + 0 + + + AVGS_1 + 2 conversions averaged. + 0x1 + + + AVGS_2 + 4 conversions averaged. + 0x2 + + + AVGS_3 + 8 conversions averaged. + 0x3 + + + AVGS_4 + 16 conversions averaged. + 0x4 + + + AVGS_5 + 32 conversions averaged. + 0x5 + + + AVGS_6 + 64 conversions averaged. + 0x6 + + + AVGS_7 + 128 conversions averaged. + 0x7 + + + + + LOOP + Loop Count Select + 16 + 4 + read-write + + + LOOP_0 + Looping not enabled. Command executes 1 time. + 0 + + + LOOP_1 + Loop 1 time. Command executes 2 times. + 0x1 + + + LOOP_2 + Loop 2 times. Command executes 3 times. + 0x2 + + + LOOP_3 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x3 + + + LOOP_4 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x4 + + + LOOP_5 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x5 + + + LOOP_6 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x6 + + + LOOP_7 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x7 + + + LOOP_8 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x8 + + + LOOP_9 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x9 + + + LOOP_15 + Loop 15 times. Command executes 16 times. + 0xF + + + + + NEXT + Next Command Select + 24 + 4 + read-write + + + NEXT_0 + No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. + 0 + + + NEXT_1 + Select CMD1 command buffer register as next command. + 0x1 + + + NEXT_2 + Select corresponding CMD command buffer register as next command + 0x2 + + + NEXT_3 + Select corresponding CMD command buffer register as next command + 0x3 + + + NEXT_4 + Select corresponding CMD command buffer register as next command + 0x4 + + + NEXT_5 + Select corresponding CMD command buffer register as next command + 0x5 + + + NEXT_6 + Select corresponding CMD command buffer register as next command + 0x6 + + + NEXT_7 + Select corresponding CMD command buffer register as next command + 0x7 + + + NEXT_8 + Select corresponding CMD command buffer register as next command + 0x8 + + + NEXT_9 + Select corresponding CMD command buffer register as next command + 0x9 + + + NEXT_15 + Select CMD15 command buffer register as next command. + 0xF + + + + + + + CMDL3 + ADC Command Low Buffer Register + 0x110 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADCH + Input channel select + 0 + 5 + read-write + + + ADCH_0 + Select CH0A or CH0B or CH0A/CH0B pair. + 0 + + + ADCH_1 + Select CH1A or CH1B or CH1A/CH1B pair. + 0x1 + + + ADCH_2 + Select CH2A or CH2B or CH2A/CH2B pair. + 0x2 + + + ADCH_3 + Select CH3A or CH3B or CH3A/CH3B pair. + 0x3 + + + ADCH_4 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x4 + + + ADCH_5 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x5 + + + ADCH_6 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x6 + + + ADCH_7 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x7 + + + ADCH_8 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x8 + + + ADCH_9 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x9 + + + ADCH_30 + Select CH30A or CH30B or CH30A/CH30B pair. + 0x1E + + + ADCH_31 + Select CH31A or CH31B or CH31A/CH31B pair. + 0x1F + + + + + CTYPE + Conversion Type + 5 + 2 + read-write + + + CTYPE_0 + Single-Ended Mode. Only A side channel is converted. + 0 + + + CTYPE_1 + Single-Ended Mode. Only B side channel is converted. + 0x1 + + + CTYPE_2 + Differential Mode. A-B. + 0x2 + + + CTYPE_3 + Dual-Single-Ended Mode. Both A side and B side channels are converted independently. + 0x3 + + + + + MODE + Select resolution of conversions + 7 + 1 + read-write + + + MODE_0 + Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. + 0 + + + MODE_1 + High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. + 0x1 + + + + + + + CMDH3 + ADC Command High Buffer Register + 0x114 + 32 + read-write + 0 + 0xFFFFFFFF + + + CMPEN + Compare Function Enable + 0 + 2 + read-write + + + CMPEN_0 + Compare disabled. + 0 + + + CMPEN_2 + Compare enabled. Store on true. + 0x2 + + + CMPEN_3 + Compare enabled. Repeat channel acquisition (sample/convert/compare) until true. + 0x3 + + + + + WAIT_TRIG + Wait for trigger assertion before execution. + 2 + 1 + read-write + + + WAIT_TRIG_0 + This command will be automatically executed. + 0 + + + WAIT_TRIG_1 + The active trigger must be asserted again before executing this command. + 0x1 + + + + + LWI + Loop with Increment + 7 + 1 + read-write + + + LWI_0 + Auto channel increment disabled + 0 + + + LWI_1 + Auto channel increment enabled + 0x1 + + + + + STS + Sample Time Select + 8 + 3 + read-write + + + STS_0 + Minimum sample time of 3 ADCK cycles. + 0 + + + STS_1 + 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. + 0x1 + + + STS_2 + 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. + 0x2 + + + STS_3 + 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. + 0x3 + + + STS_4 + 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. + 0x4 + + + STS_5 + 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. + 0x5 + + + STS_6 + 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. + 0x6 + + + STS_7 + 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. + 0x7 + + + + + AVGS + Hardware Average Select + 12 + 3 + read-write + + + AVGS_0 + Single conversion. + 0 + + + AVGS_1 + 2 conversions averaged. + 0x1 + + + AVGS_2 + 4 conversions averaged. + 0x2 + + + AVGS_3 + 8 conversions averaged. + 0x3 + + + AVGS_4 + 16 conversions averaged. + 0x4 + + + AVGS_5 + 32 conversions averaged. + 0x5 + + + AVGS_6 + 64 conversions averaged. + 0x6 + + + AVGS_7 + 128 conversions averaged. + 0x7 + + + + + LOOP + Loop Count Select + 16 + 4 + read-write + + + LOOP_0 + Looping not enabled. Command executes 1 time. + 0 + + + LOOP_1 + Loop 1 time. Command executes 2 times. + 0x1 + + + LOOP_2 + Loop 2 times. Command executes 3 times. + 0x2 + + + LOOP_3 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x3 + + + LOOP_4 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x4 + + + LOOP_5 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x5 + + + LOOP_6 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x6 + + + LOOP_7 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x7 + + + LOOP_8 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x8 + + + LOOP_9 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x9 + + + LOOP_15 + Loop 15 times. Command executes 16 times. + 0xF + + + + + NEXT + Next Command Select + 24 + 4 + read-write + + + NEXT_0 + No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. + 0 + + + NEXT_1 + Select CMD1 command buffer register as next command. + 0x1 + + + NEXT_2 + Select corresponding CMD command buffer register as next command + 0x2 + + + NEXT_3 + Select corresponding CMD command buffer register as next command + 0x3 + + + NEXT_4 + Select corresponding CMD command buffer register as next command + 0x4 + + + NEXT_5 + Select corresponding CMD command buffer register as next command + 0x5 + + + NEXT_6 + Select corresponding CMD command buffer register as next command + 0x6 + + + NEXT_7 + Select corresponding CMD command buffer register as next command + 0x7 + + + NEXT_8 + Select corresponding CMD command buffer register as next command + 0x8 + + + NEXT_9 + Select corresponding CMD command buffer register as next command + 0x9 + + + NEXT_15 + Select CMD15 command buffer register as next command. + 0xF + + + + + + + CMDL4 + ADC Command Low Buffer Register + 0x118 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADCH + Input channel select + 0 + 5 + read-write + + + ADCH_0 + Select CH0A or CH0B or CH0A/CH0B pair. + 0 + + + ADCH_1 + Select CH1A or CH1B or CH1A/CH1B pair. + 0x1 + + + ADCH_2 + Select CH2A or CH2B or CH2A/CH2B pair. + 0x2 + + + ADCH_3 + Select CH3A or CH3B or CH3A/CH3B pair. + 0x3 + + + ADCH_4 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x4 + + + ADCH_5 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x5 + + + ADCH_6 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x6 + + + ADCH_7 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x7 + + + ADCH_8 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x8 + + + ADCH_9 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x9 + + + ADCH_30 + Select CH30A or CH30B or CH30A/CH30B pair. + 0x1E + + + ADCH_31 + Select CH31A or CH31B or CH31A/CH31B pair. + 0x1F + + + + + CTYPE + Conversion Type + 5 + 2 + read-write + + + CTYPE_0 + Single-Ended Mode. Only A side channel is converted. + 0 + + + CTYPE_1 + Single-Ended Mode. Only B side channel is converted. + 0x1 + + + CTYPE_2 + Differential Mode. A-B. + 0x2 + + + CTYPE_3 + Dual-Single-Ended Mode. Both A side and B side channels are converted independently. + 0x3 + + + + + MODE + Select resolution of conversions + 7 + 1 + read-write + + + MODE_0 + Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. + 0 + + + MODE_1 + High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. + 0x1 + + + + + + + CMDH4 + ADC Command High Buffer Register + 0x11C + 32 + read-write + 0 + 0xFFFFFFFF + + + CMPEN + Compare Function Enable + 0 + 2 + read-write + + + CMPEN_0 + Compare disabled. + 0 + + + CMPEN_2 + Compare enabled. Store on true. + 0x2 + + + CMPEN_3 + Compare enabled. Repeat channel acquisition (sample/convert/compare) until true. + 0x3 + + + + + WAIT_TRIG + Wait for trigger assertion before execution. + 2 + 1 + read-write + + + WAIT_TRIG_0 + This command will be automatically executed. + 0 + + + WAIT_TRIG_1 + The active trigger must be asserted again before executing this command. + 0x1 + + + + + LWI + Loop with Increment + 7 + 1 + read-write + + + LWI_0 + Auto channel increment disabled + 0 + + + LWI_1 + Auto channel increment enabled + 0x1 + + + + + STS + Sample Time Select + 8 + 3 + read-write + + + STS_0 + Minimum sample time of 3 ADCK cycles. + 0 + + + STS_1 + 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. + 0x1 + + + STS_2 + 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. + 0x2 + + + STS_3 + 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. + 0x3 + + + STS_4 + 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. + 0x4 + + + STS_5 + 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. + 0x5 + + + STS_6 + 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. + 0x6 + + + STS_7 + 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. + 0x7 + + + + + AVGS + Hardware Average Select + 12 + 3 + read-write + + + AVGS_0 + Single conversion. + 0 + + + AVGS_1 + 2 conversions averaged. + 0x1 + + + AVGS_2 + 4 conversions averaged. + 0x2 + + + AVGS_3 + 8 conversions averaged. + 0x3 + + + AVGS_4 + 16 conversions averaged. + 0x4 + + + AVGS_5 + 32 conversions averaged. + 0x5 + + + AVGS_6 + 64 conversions averaged. + 0x6 + + + AVGS_7 + 128 conversions averaged. + 0x7 + + + + + LOOP + Loop Count Select + 16 + 4 + read-write + + + LOOP_0 + Looping not enabled. Command executes 1 time. + 0 + + + LOOP_1 + Loop 1 time. Command executes 2 times. + 0x1 + + + LOOP_2 + Loop 2 times. Command executes 3 times. + 0x2 + + + LOOP_3 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x3 + + + LOOP_4 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x4 + + + LOOP_5 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x5 + + + LOOP_6 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x6 + + + LOOP_7 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x7 + + + LOOP_8 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x8 + + + LOOP_9 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x9 + + + LOOP_15 + Loop 15 times. Command executes 16 times. + 0xF + + + + + NEXT + Next Command Select + 24 + 4 + read-write + + + NEXT_0 + No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. + 0 + + + NEXT_1 + Select CMD1 command buffer register as next command. + 0x1 + + + NEXT_2 + Select corresponding CMD command buffer register as next command + 0x2 + + + NEXT_3 + Select corresponding CMD command buffer register as next command + 0x3 + + + NEXT_4 + Select corresponding CMD command buffer register as next command + 0x4 + + + NEXT_5 + Select corresponding CMD command buffer register as next command + 0x5 + + + NEXT_6 + Select corresponding CMD command buffer register as next command + 0x6 + + + NEXT_7 + Select corresponding CMD command buffer register as next command + 0x7 + + + NEXT_8 + Select corresponding CMD command buffer register as next command + 0x8 + + + NEXT_9 + Select corresponding CMD command buffer register as next command + 0x9 + + + NEXT_15 + Select CMD15 command buffer register as next command. + 0xF + + + + + + + CMDL5 + ADC Command Low Buffer Register + 0x120 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADCH + Input channel select + 0 + 5 + read-write + + + ADCH_0 + Select CH0A or CH0B or CH0A/CH0B pair. + 0 + + + ADCH_1 + Select CH1A or CH1B or CH1A/CH1B pair. + 0x1 + + + ADCH_2 + Select CH2A or CH2B or CH2A/CH2B pair. + 0x2 + + + ADCH_3 + Select CH3A or CH3B or CH3A/CH3B pair. + 0x3 + + + ADCH_4 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x4 + + + ADCH_5 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x5 + + + ADCH_6 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x6 + + + ADCH_7 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x7 + + + ADCH_8 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x8 + + + ADCH_9 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x9 + + + ADCH_30 + Select CH30A or CH30B or CH30A/CH30B pair. + 0x1E + + + ADCH_31 + Select CH31A or CH31B or CH31A/CH31B pair. + 0x1F + + + + + CTYPE + Conversion Type + 5 + 2 + read-write + + + CTYPE_0 + Single-Ended Mode. Only A side channel is converted. + 0 + + + CTYPE_1 + Single-Ended Mode. Only B side channel is converted. + 0x1 + + + CTYPE_2 + Differential Mode. A-B. + 0x2 + + + CTYPE_3 + Dual-Single-Ended Mode. Both A side and B side channels are converted independently. + 0x3 + + + + + MODE + Select resolution of conversions + 7 + 1 + read-write + + + MODE_0 + Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. + 0 + + + MODE_1 + High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. + 0x1 + + + + + + + CMDH5 + ADC Command High Buffer Register + 0x124 + 32 + read-write + 0 + 0xFFFFFFFF + + + WAIT_TRIG + Wait for trigger assertion before execution. + 2 + 1 + read-write + + + WAIT_TRIG_0 + This command will be automatically executed. + 0 + + + WAIT_TRIG_1 + The active trigger must be asserted again before executing this command. + 0x1 + + + + + LWI + Loop with Increment + 7 + 1 + read-write + + + LWI_0 + Auto channel increment disabled + 0 + + + LWI_1 + Auto channel increment enabled + 0x1 + + + + + STS + Sample Time Select + 8 + 3 + read-write + + + STS_0 + Minimum sample time of 3 ADCK cycles. + 0 + + + STS_1 + 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. + 0x1 + + + STS_2 + 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. + 0x2 + + + STS_3 + 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. + 0x3 + + + STS_4 + 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. + 0x4 + + + STS_5 + 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. + 0x5 + + + STS_6 + 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. + 0x6 + + + STS_7 + 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. + 0x7 + + + + + AVGS + Hardware Average Select + 12 + 3 + read-write + + + AVGS_0 + Single conversion. + 0 + + + AVGS_1 + 2 conversions averaged. + 0x1 + + + AVGS_2 + 4 conversions averaged. + 0x2 + + + AVGS_3 + 8 conversions averaged. + 0x3 + + + AVGS_4 + 16 conversions averaged. + 0x4 + + + AVGS_5 + 32 conversions averaged. + 0x5 + + + AVGS_6 + 64 conversions averaged. + 0x6 + + + AVGS_7 + 128 conversions averaged. + 0x7 + + + + + LOOP + Loop Count Select + 16 + 4 + read-write + + + LOOP_0 + Looping not enabled. Command executes 1 time. + 0 + + + LOOP_1 + Loop 1 time. Command executes 2 times. + 0x1 + + + LOOP_2 + Loop 2 times. Command executes 3 times. + 0x2 + + + LOOP_3 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x3 + + + LOOP_4 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x4 + + + LOOP_5 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x5 + + + LOOP_6 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x6 + + + LOOP_7 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x7 + + + LOOP_8 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x8 + + + LOOP_9 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x9 + + + LOOP_15 + Loop 15 times. Command executes 16 times. + 0xF + + + + + NEXT + Next Command Select + 24 + 4 + read-write + + + NEXT_0 + No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. + 0 + + + NEXT_1 + Select CMD1 command buffer register as next command. + 0x1 + + + NEXT_2 + Select corresponding CMD command buffer register as next command + 0x2 + + + NEXT_3 + Select corresponding CMD command buffer register as next command + 0x3 + + + NEXT_4 + Select corresponding CMD command buffer register as next command + 0x4 + + + NEXT_5 + Select corresponding CMD command buffer register as next command + 0x5 + + + NEXT_6 + Select corresponding CMD command buffer register as next command + 0x6 + + + NEXT_7 + Select corresponding CMD command buffer register as next command + 0x7 + + + NEXT_8 + Select corresponding CMD command buffer register as next command + 0x8 + + + NEXT_9 + Select corresponding CMD command buffer register as next command + 0x9 + + + NEXT_15 + Select CMD15 command buffer register as next command. + 0xF + + + + + + + CMDL6 + ADC Command Low Buffer Register + 0x128 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADCH + Input channel select + 0 + 5 + read-write + + + ADCH_0 + Select CH0A or CH0B or CH0A/CH0B pair. + 0 + + + ADCH_1 + Select CH1A or CH1B or CH1A/CH1B pair. + 0x1 + + + ADCH_2 + Select CH2A or CH2B or CH2A/CH2B pair. + 0x2 + + + ADCH_3 + Select CH3A or CH3B or CH3A/CH3B pair. + 0x3 + + + ADCH_4 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x4 + + + ADCH_5 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x5 + + + ADCH_6 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x6 + + + ADCH_7 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x7 + + + ADCH_8 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x8 + + + ADCH_9 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x9 + + + ADCH_30 + Select CH30A or CH30B or CH30A/CH30B pair. + 0x1E + + + ADCH_31 + Select CH31A or CH31B or CH31A/CH31B pair. + 0x1F + + + + + CTYPE + Conversion Type + 5 + 2 + read-write + + + CTYPE_0 + Single-Ended Mode. Only A side channel is converted. + 0 + + + CTYPE_1 + Single-Ended Mode. Only B side channel is converted. + 0x1 + + + CTYPE_2 + Differential Mode. A-B. + 0x2 + + + CTYPE_3 + Dual-Single-Ended Mode. Both A side and B side channels are converted independently. + 0x3 + + + + + MODE + Select resolution of conversions + 7 + 1 + read-write + + + MODE_0 + Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. + 0 + + + MODE_1 + High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. + 0x1 + + + + + + + CMDH6 + ADC Command High Buffer Register + 0x12C + 32 + read-write + 0 + 0xFFFFFFFF + + + WAIT_TRIG + Wait for trigger assertion before execution. + 2 + 1 + read-write + + + WAIT_TRIG_0 + This command will be automatically executed. + 0 + + + WAIT_TRIG_1 + The active trigger must be asserted again before executing this command. + 0x1 + + + + + LWI + Loop with Increment + 7 + 1 + read-write + + + LWI_0 + Auto channel increment disabled + 0 + + + LWI_1 + Auto channel increment enabled + 0x1 + + + + + STS + Sample Time Select + 8 + 3 + read-write + + + STS_0 + Minimum sample time of 3 ADCK cycles. + 0 + + + STS_1 + 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. + 0x1 + + + STS_2 + 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. + 0x2 + + + STS_3 + 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. + 0x3 + + + STS_4 + 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. + 0x4 + + + STS_5 + 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. + 0x5 + + + STS_6 + 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. + 0x6 + + + STS_7 + 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. + 0x7 + + + + + AVGS + Hardware Average Select + 12 + 3 + read-write + + + AVGS_0 + Single conversion. + 0 + + + AVGS_1 + 2 conversions averaged. + 0x1 + + + AVGS_2 + 4 conversions averaged. + 0x2 + + + AVGS_3 + 8 conversions averaged. + 0x3 + + + AVGS_4 + 16 conversions averaged. + 0x4 + + + AVGS_5 + 32 conversions averaged. + 0x5 + + + AVGS_6 + 64 conversions averaged. + 0x6 + + + AVGS_7 + 128 conversions averaged. + 0x7 + + + + + LOOP + Loop Count Select + 16 + 4 + read-write + + + LOOP_0 + Looping not enabled. Command executes 1 time. + 0 + + + LOOP_1 + Loop 1 time. Command executes 2 times. + 0x1 + + + LOOP_2 + Loop 2 times. Command executes 3 times. + 0x2 + + + LOOP_3 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x3 + + + LOOP_4 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x4 + + + LOOP_5 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x5 + + + LOOP_6 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x6 + + + LOOP_7 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x7 + + + LOOP_8 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x8 + + + LOOP_9 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x9 + + + LOOP_15 + Loop 15 times. Command executes 16 times. + 0xF + + + + + NEXT + Next Command Select + 24 + 4 + read-write + + + NEXT_0 + No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. + 0 + + + NEXT_1 + Select CMD1 command buffer register as next command. + 0x1 + + + NEXT_2 + Select corresponding CMD command buffer register as next command + 0x2 + + + NEXT_3 + Select corresponding CMD command buffer register as next command + 0x3 + + + NEXT_4 + Select corresponding CMD command buffer register as next command + 0x4 + + + NEXT_5 + Select corresponding CMD command buffer register as next command + 0x5 + + + NEXT_6 + Select corresponding CMD command buffer register as next command + 0x6 + + + NEXT_7 + Select corresponding CMD command buffer register as next command + 0x7 + + + NEXT_8 + Select corresponding CMD command buffer register as next command + 0x8 + + + NEXT_9 + Select corresponding CMD command buffer register as next command + 0x9 + + + NEXT_15 + Select CMD15 command buffer register as next command. + 0xF + + + + + + + CMDL7 + ADC Command Low Buffer Register + 0x130 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADCH + Input channel select + 0 + 5 + read-write + + + ADCH_0 + Select CH0A or CH0B or CH0A/CH0B pair. + 0 + + + ADCH_1 + Select CH1A or CH1B or CH1A/CH1B pair. + 0x1 + + + ADCH_2 + Select CH2A or CH2B or CH2A/CH2B pair. + 0x2 + + + ADCH_3 + Select CH3A or CH3B or CH3A/CH3B pair. + 0x3 + + + ADCH_4 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x4 + + + ADCH_5 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x5 + + + ADCH_6 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x6 + + + ADCH_7 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x7 + + + ADCH_8 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x8 + + + ADCH_9 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x9 + + + ADCH_30 + Select CH30A or CH30B or CH30A/CH30B pair. + 0x1E + + + ADCH_31 + Select CH31A or CH31B or CH31A/CH31B pair. + 0x1F + + + + + CTYPE + Conversion Type + 5 + 2 + read-write + + + CTYPE_0 + Single-Ended Mode. Only A side channel is converted. + 0 + + + CTYPE_1 + Single-Ended Mode. Only B side channel is converted. + 0x1 + + + CTYPE_2 + Differential Mode. A-B. + 0x2 + + + CTYPE_3 + Dual-Single-Ended Mode. Both A side and B side channels are converted independently. + 0x3 + + + + + MODE + Select resolution of conversions + 7 + 1 + read-write + + + MODE_0 + Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. + 0 + + + MODE_1 + High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. + 0x1 + + + + + + + CMDH7 + ADC Command High Buffer Register + 0x134 + 32 + read-write + 0 + 0xFFFFFFFF + + + WAIT_TRIG + Wait for trigger assertion before execution. + 2 + 1 + read-write + + + WAIT_TRIG_0 + This command will be automatically executed. + 0 + + + WAIT_TRIG_1 + The active trigger must be asserted again before executing this command. + 0x1 + + + + + LWI + Loop with Increment + 7 + 1 + read-write + + + LWI_0 + Auto channel increment disabled + 0 + + + LWI_1 + Auto channel increment enabled + 0x1 + + + + + STS + Sample Time Select + 8 + 3 + read-write + + + STS_0 + Minimum sample time of 3 ADCK cycles. + 0 + + + STS_1 + 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. + 0x1 + + + STS_2 + 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. + 0x2 + + + STS_3 + 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. + 0x3 + + + STS_4 + 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. + 0x4 + + + STS_5 + 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. + 0x5 + + + STS_6 + 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. + 0x6 + + + STS_7 + 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. + 0x7 + + + + + AVGS + Hardware Average Select + 12 + 3 + read-write + + + AVGS_0 + Single conversion. + 0 + + + AVGS_1 + 2 conversions averaged. + 0x1 + + + AVGS_2 + 4 conversions averaged. + 0x2 + + + AVGS_3 + 8 conversions averaged. + 0x3 + + + AVGS_4 + 16 conversions averaged. + 0x4 + + + AVGS_5 + 32 conversions averaged. + 0x5 + + + AVGS_6 + 64 conversions averaged. + 0x6 + + + AVGS_7 + 128 conversions averaged. + 0x7 + + + + + LOOP + Loop Count Select + 16 + 4 + read-write + + + LOOP_0 + Looping not enabled. Command executes 1 time. + 0 + + + LOOP_1 + Loop 1 time. Command executes 2 times. + 0x1 + + + LOOP_2 + Loop 2 times. Command executes 3 times. + 0x2 + + + LOOP_3 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x3 + + + LOOP_4 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x4 + + + LOOP_5 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x5 + + + LOOP_6 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x6 + + + LOOP_7 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x7 + + + LOOP_8 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x8 + + + LOOP_9 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x9 + + + LOOP_15 + Loop 15 times. Command executes 16 times. + 0xF + + + + + NEXT + Next Command Select + 24 + 4 + read-write + + + NEXT_0 + No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. + 0 + + + NEXT_1 + Select CMD1 command buffer register as next command. + 0x1 + + + NEXT_2 + Select corresponding CMD command buffer register as next command + 0x2 + + + NEXT_3 + Select corresponding CMD command buffer register as next command + 0x3 + + + NEXT_4 + Select corresponding CMD command buffer register as next command + 0x4 + + + NEXT_5 + Select corresponding CMD command buffer register as next command + 0x5 + + + NEXT_6 + Select corresponding CMD command buffer register as next command + 0x6 + + + NEXT_7 + Select corresponding CMD command buffer register as next command + 0x7 + + + NEXT_8 + Select corresponding CMD command buffer register as next command + 0x8 + + + NEXT_9 + Select corresponding CMD command buffer register as next command + 0x9 + + + NEXT_15 + Select CMD15 command buffer register as next command. + 0xF + + + + + + + CMDL8 + ADC Command Low Buffer Register + 0x138 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADCH + Input channel select + 0 + 5 + read-write + + + ADCH_0 + Select CH0A or CH0B or CH0A/CH0B pair. + 0 + + + ADCH_1 + Select CH1A or CH1B or CH1A/CH1B pair. + 0x1 + + + ADCH_2 + Select CH2A or CH2B or CH2A/CH2B pair. + 0x2 + + + ADCH_3 + Select CH3A or CH3B or CH3A/CH3B pair. + 0x3 + + + ADCH_4 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x4 + + + ADCH_5 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x5 + + + ADCH_6 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x6 + + + ADCH_7 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x7 + + + ADCH_8 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x8 + + + ADCH_9 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x9 + + + ADCH_30 + Select CH30A or CH30B or CH30A/CH30B pair. + 0x1E + + + ADCH_31 + Select CH31A or CH31B or CH31A/CH31B pair. + 0x1F + + + + + CTYPE + Conversion Type + 5 + 2 + read-write + + + CTYPE_0 + Single-Ended Mode. Only A side channel is converted. + 0 + + + CTYPE_1 + Single-Ended Mode. Only B side channel is converted. + 0x1 + + + CTYPE_2 + Differential Mode. A-B. + 0x2 + + + CTYPE_3 + Dual-Single-Ended Mode. Both A side and B side channels are converted independently. + 0x3 + + + + + MODE + Select resolution of conversions + 7 + 1 + read-write + + + MODE_0 + Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. + 0 + + + MODE_1 + High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. + 0x1 + + + + + + + CMDH8 + ADC Command High Buffer Register + 0x13C + 32 + read-write + 0 + 0xFFFFFFFF + + + WAIT_TRIG + Wait for trigger assertion before execution. + 2 + 1 + read-write + + + WAIT_TRIG_0 + This command will be automatically executed. + 0 + + + WAIT_TRIG_1 + The active trigger must be asserted again before executing this command. + 0x1 + + + + + LWI + Loop with Increment + 7 + 1 + read-write + + + LWI_0 + Auto channel increment disabled + 0 + + + LWI_1 + Auto channel increment enabled + 0x1 + + + + + STS + Sample Time Select + 8 + 3 + read-write + + + STS_0 + Minimum sample time of 3 ADCK cycles. + 0 + + + STS_1 + 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. + 0x1 + + + STS_2 + 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. + 0x2 + + + STS_3 + 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. + 0x3 + + + STS_4 + 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. + 0x4 + + + STS_5 + 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. + 0x5 + + + STS_6 + 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. + 0x6 + + + STS_7 + 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. + 0x7 + + + + + AVGS + Hardware Average Select + 12 + 3 + read-write + + + AVGS_0 + Single conversion. + 0 + + + AVGS_1 + 2 conversions averaged. + 0x1 + + + AVGS_2 + 4 conversions averaged. + 0x2 + + + AVGS_3 + 8 conversions averaged. + 0x3 + + + AVGS_4 + 16 conversions averaged. + 0x4 + + + AVGS_5 + 32 conversions averaged. + 0x5 + + + AVGS_6 + 64 conversions averaged. + 0x6 + + + AVGS_7 + 128 conversions averaged. + 0x7 + + + + + LOOP + Loop Count Select + 16 + 4 + read-write + + + LOOP_0 + Looping not enabled. Command executes 1 time. + 0 + + + LOOP_1 + Loop 1 time. Command executes 2 times. + 0x1 + + + LOOP_2 + Loop 2 times. Command executes 3 times. + 0x2 + + + LOOP_3 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x3 + + + LOOP_4 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x4 + + + LOOP_5 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x5 + + + LOOP_6 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x6 + + + LOOP_7 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x7 + + + LOOP_8 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x8 + + + LOOP_9 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x9 + + + LOOP_15 + Loop 15 times. Command executes 16 times. + 0xF + + + + + NEXT + Next Command Select + 24 + 4 + read-write + + + NEXT_0 + No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. + 0 + + + NEXT_1 + Select CMD1 command buffer register as next command. + 0x1 + + + NEXT_2 + Select corresponding CMD command buffer register as next command + 0x2 + + + NEXT_3 + Select corresponding CMD command buffer register as next command + 0x3 + + + NEXT_4 + Select corresponding CMD command buffer register as next command + 0x4 + + + NEXT_5 + Select corresponding CMD command buffer register as next command + 0x5 + + + NEXT_6 + Select corresponding CMD command buffer register as next command + 0x6 + + + NEXT_7 + Select corresponding CMD command buffer register as next command + 0x7 + + + NEXT_8 + Select corresponding CMD command buffer register as next command + 0x8 + + + NEXT_9 + Select corresponding CMD command buffer register as next command + 0x9 + + + NEXT_15 + Select CMD15 command buffer register as next command. + 0xF + + + + + + + CMDL9 + ADC Command Low Buffer Register + 0x140 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADCH + Input channel select + 0 + 5 + read-write + + + ADCH_0 + Select CH0A or CH0B or CH0A/CH0B pair. + 0 + + + ADCH_1 + Select CH1A or CH1B or CH1A/CH1B pair. + 0x1 + + + ADCH_2 + Select CH2A or CH2B or CH2A/CH2B pair. + 0x2 + + + ADCH_3 + Select CH3A or CH3B or CH3A/CH3B pair. + 0x3 + + + ADCH_4 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x4 + + + ADCH_5 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x5 + + + ADCH_6 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x6 + + + ADCH_7 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x7 + + + ADCH_8 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x8 + + + ADCH_9 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x9 + + + ADCH_30 + Select CH30A or CH30B or CH30A/CH30B pair. + 0x1E + + + ADCH_31 + Select CH31A or CH31B or CH31A/CH31B pair. + 0x1F + + + + + CTYPE + Conversion Type + 5 + 2 + read-write + + + CTYPE_0 + Single-Ended Mode. Only A side channel is converted. + 0 + + + CTYPE_1 + Single-Ended Mode. Only B side channel is converted. + 0x1 + + + CTYPE_2 + Differential Mode. A-B. + 0x2 + + + CTYPE_3 + Dual-Single-Ended Mode. Both A side and B side channels are converted independently. + 0x3 + + + + + MODE + Select resolution of conversions + 7 + 1 + read-write + + + MODE_0 + Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. + 0 + + + MODE_1 + High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. + 0x1 + + + + + + + CMDH9 + ADC Command High Buffer Register + 0x144 + 32 + read-write + 0 + 0xFFFFFFFF + + + WAIT_TRIG + Wait for trigger assertion before execution. + 2 + 1 + read-write + + + WAIT_TRIG_0 + This command will be automatically executed. + 0 + + + WAIT_TRIG_1 + The active trigger must be asserted again before executing this command. + 0x1 + + + + + LWI + Loop with Increment + 7 + 1 + read-write + + + LWI_0 + Auto channel increment disabled + 0 + + + LWI_1 + Auto channel increment enabled + 0x1 + + + + + STS + Sample Time Select + 8 + 3 + read-write + + + STS_0 + Minimum sample time of 3 ADCK cycles. + 0 + + + STS_1 + 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. + 0x1 + + + STS_2 + 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. + 0x2 + + + STS_3 + 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. + 0x3 + + + STS_4 + 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. + 0x4 + + + STS_5 + 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. + 0x5 + + + STS_6 + 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. + 0x6 + + + STS_7 + 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. + 0x7 + + + + + AVGS + Hardware Average Select + 12 + 3 + read-write + + + AVGS_0 + Single conversion. + 0 + + + AVGS_1 + 2 conversions averaged. + 0x1 + + + AVGS_2 + 4 conversions averaged. + 0x2 + + + AVGS_3 + 8 conversions averaged. + 0x3 + + + AVGS_4 + 16 conversions averaged. + 0x4 + + + AVGS_5 + 32 conversions averaged. + 0x5 + + + AVGS_6 + 64 conversions averaged. + 0x6 + + + AVGS_7 + 128 conversions averaged. + 0x7 + + + + + LOOP + Loop Count Select + 16 + 4 + read-write + + + LOOP_0 + Looping not enabled. Command executes 1 time. + 0 + + + LOOP_1 + Loop 1 time. Command executes 2 times. + 0x1 + + + LOOP_2 + Loop 2 times. Command executes 3 times. + 0x2 + + + LOOP_3 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x3 + + + LOOP_4 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x4 + + + LOOP_5 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x5 + + + LOOP_6 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x6 + + + LOOP_7 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x7 + + + LOOP_8 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x8 + + + LOOP_9 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x9 + + + LOOP_15 + Loop 15 times. Command executes 16 times. + 0xF + + + + + NEXT + Next Command Select + 24 + 4 + read-write + + + NEXT_0 + No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. + 0 + + + NEXT_1 + Select CMD1 command buffer register as next command. + 0x1 + + + NEXT_2 + Select corresponding CMD command buffer register as next command + 0x2 + + + NEXT_3 + Select corresponding CMD command buffer register as next command + 0x3 + + + NEXT_4 + Select corresponding CMD command buffer register as next command + 0x4 + + + NEXT_5 + Select corresponding CMD command buffer register as next command + 0x5 + + + NEXT_6 + Select corresponding CMD command buffer register as next command + 0x6 + + + NEXT_7 + Select corresponding CMD command buffer register as next command + 0x7 + + + NEXT_8 + Select corresponding CMD command buffer register as next command + 0x8 + + + NEXT_9 + Select corresponding CMD command buffer register as next command + 0x9 + + + NEXT_15 + Select CMD15 command buffer register as next command. + 0xF + + + + + + + CMDL10 + ADC Command Low Buffer Register + 0x148 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADCH + Input channel select + 0 + 5 + read-write + + + ADCH_0 + Select CH0A or CH0B or CH0A/CH0B pair. + 0 + + + ADCH_1 + Select CH1A or CH1B or CH1A/CH1B pair. + 0x1 + + + ADCH_2 + Select CH2A or CH2B or CH2A/CH2B pair. + 0x2 + + + ADCH_3 + Select CH3A or CH3B or CH3A/CH3B pair. + 0x3 + + + ADCH_4 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x4 + + + ADCH_5 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x5 + + + ADCH_6 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x6 + + + ADCH_7 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x7 + + + ADCH_8 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x8 + + + ADCH_9 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x9 + + + ADCH_30 + Select CH30A or CH30B or CH30A/CH30B pair. + 0x1E + + + ADCH_31 + Select CH31A or CH31B or CH31A/CH31B pair. + 0x1F + + + + + CTYPE + Conversion Type + 5 + 2 + read-write + + + CTYPE_0 + Single-Ended Mode. Only A side channel is converted. + 0 + + + CTYPE_1 + Single-Ended Mode. Only B side channel is converted. + 0x1 + + + CTYPE_2 + Differential Mode. A-B. + 0x2 + + + CTYPE_3 + Dual-Single-Ended Mode. Both A side and B side channels are converted independently. + 0x3 + + + + + MODE + Select resolution of conversions + 7 + 1 + read-write + + + MODE_0 + Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. + 0 + + + MODE_1 + High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. + 0x1 + + + + + + + CMDH10 + ADC Command High Buffer Register + 0x14C + 32 + read-write + 0 + 0xFFFFFFFF + + + WAIT_TRIG + Wait for trigger assertion before execution. + 2 + 1 + read-write + + + WAIT_TRIG_0 + This command will be automatically executed. + 0 + + + WAIT_TRIG_1 + The active trigger must be asserted again before executing this command. + 0x1 + + + + + LWI + Loop with Increment + 7 + 1 + read-write + + + LWI_0 + Auto channel increment disabled + 0 + + + LWI_1 + Auto channel increment enabled + 0x1 + + + + + STS + Sample Time Select + 8 + 3 + read-write + + + STS_0 + Minimum sample time of 3 ADCK cycles. + 0 + + + STS_1 + 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. + 0x1 + + + STS_2 + 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. + 0x2 + + + STS_3 + 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. + 0x3 + + + STS_4 + 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. + 0x4 + + + STS_5 + 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. + 0x5 + + + STS_6 + 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. + 0x6 + + + STS_7 + 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. + 0x7 + + + + + AVGS + Hardware Average Select + 12 + 3 + read-write + + + AVGS_0 + Single conversion. + 0 + + + AVGS_1 + 2 conversions averaged. + 0x1 + + + AVGS_2 + 4 conversions averaged. + 0x2 + + + AVGS_3 + 8 conversions averaged. + 0x3 + + + AVGS_4 + 16 conversions averaged. + 0x4 + + + AVGS_5 + 32 conversions averaged. + 0x5 + + + AVGS_6 + 64 conversions averaged. + 0x6 + + + AVGS_7 + 128 conversions averaged. + 0x7 + + + + + LOOP + Loop Count Select + 16 + 4 + read-write + + + LOOP_0 + Looping not enabled. Command executes 1 time. + 0 + + + LOOP_1 + Loop 1 time. Command executes 2 times. + 0x1 + + + LOOP_2 + Loop 2 times. Command executes 3 times. + 0x2 + + + LOOP_3 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x3 + + + LOOP_4 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x4 + + + LOOP_5 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x5 + + + LOOP_6 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x6 + + + LOOP_7 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x7 + + + LOOP_8 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x8 + + + LOOP_9 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x9 + + + LOOP_15 + Loop 15 times. Command executes 16 times. + 0xF + + + + + NEXT + Next Command Select + 24 + 4 + read-write + + + NEXT_0 + No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. + 0 + + + NEXT_1 + Select CMD1 command buffer register as next command. + 0x1 + + + NEXT_2 + Select corresponding CMD command buffer register as next command + 0x2 + + + NEXT_3 + Select corresponding CMD command buffer register as next command + 0x3 + + + NEXT_4 + Select corresponding CMD command buffer register as next command + 0x4 + + + NEXT_5 + Select corresponding CMD command buffer register as next command + 0x5 + + + NEXT_6 + Select corresponding CMD command buffer register as next command + 0x6 + + + NEXT_7 + Select corresponding CMD command buffer register as next command + 0x7 + + + NEXT_8 + Select corresponding CMD command buffer register as next command + 0x8 + + + NEXT_9 + Select corresponding CMD command buffer register as next command + 0x9 + + + NEXT_15 + Select CMD15 command buffer register as next command. + 0xF + + + + + + + CMDL11 + ADC Command Low Buffer Register + 0x150 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADCH + Input channel select + 0 + 5 + read-write + + + ADCH_0 + Select CH0A or CH0B or CH0A/CH0B pair. + 0 + + + ADCH_1 + Select CH1A or CH1B or CH1A/CH1B pair. + 0x1 + + + ADCH_2 + Select CH2A or CH2B or CH2A/CH2B pair. + 0x2 + + + ADCH_3 + Select CH3A or CH3B or CH3A/CH3B pair. + 0x3 + + + ADCH_4 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x4 + + + ADCH_5 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x5 + + + ADCH_6 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x6 + + + ADCH_7 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x7 + + + ADCH_8 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x8 + + + ADCH_9 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x9 + + + ADCH_30 + Select CH30A or CH30B or CH30A/CH30B pair. + 0x1E + + + ADCH_31 + Select CH31A or CH31B or CH31A/CH31B pair. + 0x1F + + + + + CTYPE + Conversion Type + 5 + 2 + read-write + + + CTYPE_0 + Single-Ended Mode. Only A side channel is converted. + 0 + + + CTYPE_1 + Single-Ended Mode. Only B side channel is converted. + 0x1 + + + CTYPE_2 + Differential Mode. A-B. + 0x2 + + + CTYPE_3 + Dual-Single-Ended Mode. Both A side and B side channels are converted independently. + 0x3 + + + + + MODE + Select resolution of conversions + 7 + 1 + read-write + + + MODE_0 + Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. + 0 + + + MODE_1 + High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. + 0x1 + + + + + + + CMDH11 + ADC Command High Buffer Register + 0x154 + 32 + read-write + 0 + 0xFFFFFFFF + + + WAIT_TRIG + Wait for trigger assertion before execution. + 2 + 1 + read-write + + + WAIT_TRIG_0 + This command will be automatically executed. + 0 + + + WAIT_TRIG_1 + The active trigger must be asserted again before executing this command. + 0x1 + + + + + LWI + Loop with Increment + 7 + 1 + read-write + + + LWI_0 + Auto channel increment disabled + 0 + + + LWI_1 + Auto channel increment enabled + 0x1 + + + + + STS + Sample Time Select + 8 + 3 + read-write + + + STS_0 + Minimum sample time of 3 ADCK cycles. + 0 + + + STS_1 + 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. + 0x1 + + + STS_2 + 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. + 0x2 + + + STS_3 + 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. + 0x3 + + + STS_4 + 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. + 0x4 + + + STS_5 + 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. + 0x5 + + + STS_6 + 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. + 0x6 + + + STS_7 + 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. + 0x7 + + + + + AVGS + Hardware Average Select + 12 + 3 + read-write + + + AVGS_0 + Single conversion. + 0 + + + AVGS_1 + 2 conversions averaged. + 0x1 + + + AVGS_2 + 4 conversions averaged. + 0x2 + + + AVGS_3 + 8 conversions averaged. + 0x3 + + + AVGS_4 + 16 conversions averaged. + 0x4 + + + AVGS_5 + 32 conversions averaged. + 0x5 + + + AVGS_6 + 64 conversions averaged. + 0x6 + + + AVGS_7 + 128 conversions averaged. + 0x7 + + + + + LOOP + Loop Count Select + 16 + 4 + read-write + + + LOOP_0 + Looping not enabled. Command executes 1 time. + 0 + + + LOOP_1 + Loop 1 time. Command executes 2 times. + 0x1 + + + LOOP_2 + Loop 2 times. Command executes 3 times. + 0x2 + + + LOOP_3 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x3 + + + LOOP_4 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x4 + + + LOOP_5 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x5 + + + LOOP_6 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x6 + + + LOOP_7 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x7 + + + LOOP_8 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x8 + + + LOOP_9 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x9 + + + LOOP_15 + Loop 15 times. Command executes 16 times. + 0xF + + + + + NEXT + Next Command Select + 24 + 4 + read-write + + + NEXT_0 + No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. + 0 + + + NEXT_1 + Select CMD1 command buffer register as next command. + 0x1 + + + NEXT_2 + Select corresponding CMD command buffer register as next command + 0x2 + + + NEXT_3 + Select corresponding CMD command buffer register as next command + 0x3 + + + NEXT_4 + Select corresponding CMD command buffer register as next command + 0x4 + + + NEXT_5 + Select corresponding CMD command buffer register as next command + 0x5 + + + NEXT_6 + Select corresponding CMD command buffer register as next command + 0x6 + + + NEXT_7 + Select corresponding CMD command buffer register as next command + 0x7 + + + NEXT_8 + Select corresponding CMD command buffer register as next command + 0x8 + + + NEXT_9 + Select corresponding CMD command buffer register as next command + 0x9 + + + NEXT_15 + Select CMD15 command buffer register as next command. + 0xF + + + + + + + CMDL12 + ADC Command Low Buffer Register + 0x158 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADCH + Input channel select + 0 + 5 + read-write + + + ADCH_0 + Select CH0A or CH0B or CH0A/CH0B pair. + 0 + + + ADCH_1 + Select CH1A or CH1B or CH1A/CH1B pair. + 0x1 + + + ADCH_2 + Select CH2A or CH2B or CH2A/CH2B pair. + 0x2 + + + ADCH_3 + Select CH3A or CH3B or CH3A/CH3B pair. + 0x3 + + + ADCH_4 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x4 + + + ADCH_5 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x5 + + + ADCH_6 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x6 + + + ADCH_7 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x7 + + + ADCH_8 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x8 + + + ADCH_9 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x9 + + + ADCH_30 + Select CH30A or CH30B or CH30A/CH30B pair. + 0x1E + + + ADCH_31 + Select CH31A or CH31B or CH31A/CH31B pair. + 0x1F + + + + + CTYPE + Conversion Type + 5 + 2 + read-write + + + CTYPE_0 + Single-Ended Mode. Only A side channel is converted. + 0 + + + CTYPE_1 + Single-Ended Mode. Only B side channel is converted. + 0x1 + + + CTYPE_2 + Differential Mode. A-B. + 0x2 + + + CTYPE_3 + Dual-Single-Ended Mode. Both A side and B side channels are converted independently. + 0x3 + + + + + MODE + Select resolution of conversions + 7 + 1 + read-write + + + MODE_0 + Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. + 0 + + + MODE_1 + High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. + 0x1 + + + + + + + CMDH12 + ADC Command High Buffer Register + 0x15C + 32 + read-write + 0 + 0xFFFFFFFF + + + WAIT_TRIG + Wait for trigger assertion before execution. + 2 + 1 + read-write + + + WAIT_TRIG_0 + This command will be automatically executed. + 0 + + + WAIT_TRIG_1 + The active trigger must be asserted again before executing this command. + 0x1 + + + + + LWI + Loop with Increment + 7 + 1 + read-write + + + LWI_0 + Auto channel increment disabled + 0 + + + LWI_1 + Auto channel increment enabled + 0x1 + + + + + STS + Sample Time Select + 8 + 3 + read-write + + + STS_0 + Minimum sample time of 3 ADCK cycles. + 0 + + + STS_1 + 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. + 0x1 + + + STS_2 + 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. + 0x2 + + + STS_3 + 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. + 0x3 + + + STS_4 + 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. + 0x4 + + + STS_5 + 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. + 0x5 + + + STS_6 + 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. + 0x6 + + + STS_7 + 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. + 0x7 + + + + + AVGS + Hardware Average Select + 12 + 3 + read-write + + + AVGS_0 + Single conversion. + 0 + + + AVGS_1 + 2 conversions averaged. + 0x1 + + + AVGS_2 + 4 conversions averaged. + 0x2 + + + AVGS_3 + 8 conversions averaged. + 0x3 + + + AVGS_4 + 16 conversions averaged. + 0x4 + + + AVGS_5 + 32 conversions averaged. + 0x5 + + + AVGS_6 + 64 conversions averaged. + 0x6 + + + AVGS_7 + 128 conversions averaged. + 0x7 + + + + + LOOP + Loop Count Select + 16 + 4 + read-write + + + LOOP_0 + Looping not enabled. Command executes 1 time. + 0 + + + LOOP_1 + Loop 1 time. Command executes 2 times. + 0x1 + + + LOOP_2 + Loop 2 times. Command executes 3 times. + 0x2 + + + LOOP_3 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x3 + + + LOOP_4 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x4 + + + LOOP_5 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x5 + + + LOOP_6 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x6 + + + LOOP_7 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x7 + + + LOOP_8 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x8 + + + LOOP_9 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x9 + + + LOOP_15 + Loop 15 times. Command executes 16 times. + 0xF + + + + + NEXT + Next Command Select + 24 + 4 + read-write + + + NEXT_0 + No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. + 0 + + + NEXT_1 + Select CMD1 command buffer register as next command. + 0x1 + + + NEXT_2 + Select corresponding CMD command buffer register as next command + 0x2 + + + NEXT_3 + Select corresponding CMD command buffer register as next command + 0x3 + + + NEXT_4 + Select corresponding CMD command buffer register as next command + 0x4 + + + NEXT_5 + Select corresponding CMD command buffer register as next command + 0x5 + + + NEXT_6 + Select corresponding CMD command buffer register as next command + 0x6 + + + NEXT_7 + Select corresponding CMD command buffer register as next command + 0x7 + + + NEXT_8 + Select corresponding CMD command buffer register as next command + 0x8 + + + NEXT_9 + Select corresponding CMD command buffer register as next command + 0x9 + + + NEXT_15 + Select CMD15 command buffer register as next command. + 0xF + + + + + + + CMDL13 + ADC Command Low Buffer Register + 0x160 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADCH + Input channel select + 0 + 5 + read-write + + + ADCH_0 + Select CH0A or CH0B or CH0A/CH0B pair. + 0 + + + ADCH_1 + Select CH1A or CH1B or CH1A/CH1B pair. + 0x1 + + + ADCH_2 + Select CH2A or CH2B or CH2A/CH2B pair. + 0x2 + + + ADCH_3 + Select CH3A or CH3B or CH3A/CH3B pair. + 0x3 + + + ADCH_4 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x4 + + + ADCH_5 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x5 + + + ADCH_6 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x6 + + + ADCH_7 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x7 + + + ADCH_8 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x8 + + + ADCH_9 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x9 + + + ADCH_30 + Select CH30A or CH30B or CH30A/CH30B pair. + 0x1E + + + ADCH_31 + Select CH31A or CH31B or CH31A/CH31B pair. + 0x1F + + + + + CTYPE + Conversion Type + 5 + 2 + read-write + + + CTYPE_0 + Single-Ended Mode. Only A side channel is converted. + 0 + + + CTYPE_1 + Single-Ended Mode. Only B side channel is converted. + 0x1 + + + CTYPE_2 + Differential Mode. A-B. + 0x2 + + + CTYPE_3 + Dual-Single-Ended Mode. Both A side and B side channels are converted independently. + 0x3 + + + + + MODE + Select resolution of conversions + 7 + 1 + read-write + + + MODE_0 + Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. + 0 + + + MODE_1 + High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. + 0x1 + + + + + + + CMDH13 + ADC Command High Buffer Register + 0x164 + 32 + read-write + 0 + 0xFFFFFFFF + + + WAIT_TRIG + Wait for trigger assertion before execution. + 2 + 1 + read-write + + + WAIT_TRIG_0 + This command will be automatically executed. + 0 + + + WAIT_TRIG_1 + The active trigger must be asserted again before executing this command. + 0x1 + + + + + LWI + Loop with Increment + 7 + 1 + read-write + + + LWI_0 + Auto channel increment disabled + 0 + + + LWI_1 + Auto channel increment enabled + 0x1 + + + + + STS + Sample Time Select + 8 + 3 + read-write + + + STS_0 + Minimum sample time of 3 ADCK cycles. + 0 + + + STS_1 + 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. + 0x1 + + + STS_2 + 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. + 0x2 + + + STS_3 + 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. + 0x3 + + + STS_4 + 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. + 0x4 + + + STS_5 + 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. + 0x5 + + + STS_6 + 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. + 0x6 + + + STS_7 + 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. + 0x7 + + + + + AVGS + Hardware Average Select + 12 + 3 + read-write + + + AVGS_0 + Single conversion. + 0 + + + AVGS_1 + 2 conversions averaged. + 0x1 + + + AVGS_2 + 4 conversions averaged. + 0x2 + + + AVGS_3 + 8 conversions averaged. + 0x3 + + + AVGS_4 + 16 conversions averaged. + 0x4 + + + AVGS_5 + 32 conversions averaged. + 0x5 + + + AVGS_6 + 64 conversions averaged. + 0x6 + + + AVGS_7 + 128 conversions averaged. + 0x7 + + + + + LOOP + Loop Count Select + 16 + 4 + read-write + + + LOOP_0 + Looping not enabled. Command executes 1 time. + 0 + + + LOOP_1 + Loop 1 time. Command executes 2 times. + 0x1 + + + LOOP_2 + Loop 2 times. Command executes 3 times. + 0x2 + + + LOOP_3 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x3 + + + LOOP_4 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x4 + + + LOOP_5 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x5 + + + LOOP_6 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x6 + + + LOOP_7 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x7 + + + LOOP_8 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x8 + + + LOOP_9 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x9 + + + LOOP_15 + Loop 15 times. Command executes 16 times. + 0xF + + + + + NEXT + Next Command Select + 24 + 4 + read-write + + + NEXT_0 + No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. + 0 + + + NEXT_1 + Select CMD1 command buffer register as next command. + 0x1 + + + NEXT_2 + Select corresponding CMD command buffer register as next command + 0x2 + + + NEXT_3 + Select corresponding CMD command buffer register as next command + 0x3 + + + NEXT_4 + Select corresponding CMD command buffer register as next command + 0x4 + + + NEXT_5 + Select corresponding CMD command buffer register as next command + 0x5 + + + NEXT_6 + Select corresponding CMD command buffer register as next command + 0x6 + + + NEXT_7 + Select corresponding CMD command buffer register as next command + 0x7 + + + NEXT_8 + Select corresponding CMD command buffer register as next command + 0x8 + + + NEXT_9 + Select corresponding CMD command buffer register as next command + 0x9 + + + NEXT_15 + Select CMD15 command buffer register as next command. + 0xF + + + + + + + CMDL14 + ADC Command Low Buffer Register + 0x168 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADCH + Input channel select + 0 + 5 + read-write + + + ADCH_0 + Select CH0A or CH0B or CH0A/CH0B pair. + 0 + + + ADCH_1 + Select CH1A or CH1B or CH1A/CH1B pair. + 0x1 + + + ADCH_2 + Select CH2A or CH2B or CH2A/CH2B pair. + 0x2 + + + ADCH_3 + Select CH3A or CH3B or CH3A/CH3B pair. + 0x3 + + + ADCH_4 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x4 + + + ADCH_5 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x5 + + + ADCH_6 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x6 + + + ADCH_7 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x7 + + + ADCH_8 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x8 + + + ADCH_9 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x9 + + + ADCH_30 + Select CH30A or CH30B or CH30A/CH30B pair. + 0x1E + + + ADCH_31 + Select CH31A or CH31B or CH31A/CH31B pair. + 0x1F + + + + + CTYPE + Conversion Type + 5 + 2 + read-write + + + CTYPE_0 + Single-Ended Mode. Only A side channel is converted. + 0 + + + CTYPE_1 + Single-Ended Mode. Only B side channel is converted. + 0x1 + + + CTYPE_2 + Differential Mode. A-B. + 0x2 + + + CTYPE_3 + Dual-Single-Ended Mode. Both A side and B side channels are converted independently. + 0x3 + + + + + MODE + Select resolution of conversions + 7 + 1 + read-write + + + MODE_0 + Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. + 0 + + + MODE_1 + High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. + 0x1 + + + + + + + CMDH14 + ADC Command High Buffer Register + 0x16C + 32 + read-write + 0 + 0xFFFFFFFF + + + WAIT_TRIG + Wait for trigger assertion before execution. + 2 + 1 + read-write + + + WAIT_TRIG_0 + This command will be automatically executed. + 0 + + + WAIT_TRIG_1 + The active trigger must be asserted again before executing this command. + 0x1 + + + + + LWI + Loop with Increment + 7 + 1 + read-write + + + LWI_0 + Auto channel increment disabled + 0 + + + LWI_1 + Auto channel increment enabled + 0x1 + + + + + STS + Sample Time Select + 8 + 3 + read-write + + + STS_0 + Minimum sample time of 3 ADCK cycles. + 0 + + + STS_1 + 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. + 0x1 + + + STS_2 + 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. + 0x2 + + + STS_3 + 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. + 0x3 + + + STS_4 + 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. + 0x4 + + + STS_5 + 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. + 0x5 + + + STS_6 + 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. + 0x6 + + + STS_7 + 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. + 0x7 + + + + + AVGS + Hardware Average Select + 12 + 3 + read-write + + + AVGS_0 + Single conversion. + 0 + + + AVGS_1 + 2 conversions averaged. + 0x1 + + + AVGS_2 + 4 conversions averaged. + 0x2 + + + AVGS_3 + 8 conversions averaged. + 0x3 + + + AVGS_4 + 16 conversions averaged. + 0x4 + + + AVGS_5 + 32 conversions averaged. + 0x5 + + + AVGS_6 + 64 conversions averaged. + 0x6 + + + AVGS_7 + 128 conversions averaged. + 0x7 + + + + + LOOP + Loop Count Select + 16 + 4 + read-write + + + LOOP_0 + Looping not enabled. Command executes 1 time. + 0 + + + LOOP_1 + Loop 1 time. Command executes 2 times. + 0x1 + + + LOOP_2 + Loop 2 times. Command executes 3 times. + 0x2 + + + LOOP_3 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x3 + + + LOOP_4 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x4 + + + LOOP_5 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x5 + + + LOOP_6 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x6 + + + LOOP_7 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x7 + + + LOOP_8 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x8 + + + LOOP_9 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x9 + + + LOOP_15 + Loop 15 times. Command executes 16 times. + 0xF + + + + + NEXT + Next Command Select + 24 + 4 + read-write + + + NEXT_0 + No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. + 0 + + + NEXT_1 + Select CMD1 command buffer register as next command. + 0x1 + + + NEXT_2 + Select corresponding CMD command buffer register as next command + 0x2 + + + NEXT_3 + Select corresponding CMD command buffer register as next command + 0x3 + + + NEXT_4 + Select corresponding CMD command buffer register as next command + 0x4 + + + NEXT_5 + Select corresponding CMD command buffer register as next command + 0x5 + + + NEXT_6 + Select corresponding CMD command buffer register as next command + 0x6 + + + NEXT_7 + Select corresponding CMD command buffer register as next command + 0x7 + + + NEXT_8 + Select corresponding CMD command buffer register as next command + 0x8 + + + NEXT_9 + Select corresponding CMD command buffer register as next command + 0x9 + + + NEXT_15 + Select CMD15 command buffer register as next command. + 0xF + + + + + + + CMDL15 + ADC Command Low Buffer Register + 0x170 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADCH + Input channel select + 0 + 5 + read-write + + + ADCH_0 + Select CH0A or CH0B or CH0A/CH0B pair. + 0 + + + ADCH_1 + Select CH1A or CH1B or CH1A/CH1B pair. + 0x1 + + + ADCH_2 + Select CH2A or CH2B or CH2A/CH2B pair. + 0x2 + + + ADCH_3 + Select CH3A or CH3B or CH3A/CH3B pair. + 0x3 + + + ADCH_4 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x4 + + + ADCH_5 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x5 + + + ADCH_6 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x6 + + + ADCH_7 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x7 + + + ADCH_8 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x8 + + + ADCH_9 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x9 + + + ADCH_30 + Select CH30A or CH30B or CH30A/CH30B pair. + 0x1E + + + ADCH_31 + Select CH31A or CH31B or CH31A/CH31B pair. + 0x1F + + + + + CTYPE + Conversion Type + 5 + 2 + read-write + + + CTYPE_0 + Single-Ended Mode. Only A side channel is converted. + 0 + + + CTYPE_1 + Single-Ended Mode. Only B side channel is converted. + 0x1 + + + CTYPE_2 + Differential Mode. A-B. + 0x2 + + + CTYPE_3 + Dual-Single-Ended Mode. Both A side and B side channels are converted independently. + 0x3 + + + + + MODE + Select resolution of conversions + 7 + 1 + read-write + + + MODE_0 + Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. + 0 + + + MODE_1 + High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. + 0x1 + + + + + + + CMDH15 + ADC Command High Buffer Register + 0x174 + 32 + read-write + 0 + 0xFFFFFFFF + + + WAIT_TRIG + Wait for trigger assertion before execution. + 2 + 1 + read-write + + + WAIT_TRIG_0 + This command will be automatically executed. + 0 + + + WAIT_TRIG_1 + The active trigger must be asserted again before executing this command. + 0x1 + + + + + LWI + Loop with Increment + 7 + 1 + read-write + + + LWI_0 + Auto channel increment disabled + 0 + + + LWI_1 + Auto channel increment enabled + 0x1 + + + + + STS + Sample Time Select + 8 + 3 + read-write + + + STS_0 + Minimum sample time of 3 ADCK cycles. + 0 + + + STS_1 + 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. + 0x1 + + + STS_2 + 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. + 0x2 + + + STS_3 + 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. + 0x3 + + + STS_4 + 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. + 0x4 + + + STS_5 + 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. + 0x5 + + + STS_6 + 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. + 0x6 + + + STS_7 + 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. + 0x7 + + + + + AVGS + Hardware Average Select + 12 + 3 + read-write + + + AVGS_0 + Single conversion. + 0 + + + AVGS_1 + 2 conversions averaged. + 0x1 + + + AVGS_2 + 4 conversions averaged. + 0x2 + + + AVGS_3 + 8 conversions averaged. + 0x3 + + + AVGS_4 + 16 conversions averaged. + 0x4 + + + AVGS_5 + 32 conversions averaged. + 0x5 + + + AVGS_6 + 64 conversions averaged. + 0x6 + + + AVGS_7 + 128 conversions averaged. + 0x7 + + + + + LOOP + Loop Count Select + 16 + 4 + read-write + + + LOOP_0 + Looping not enabled. Command executes 1 time. + 0 + + + LOOP_1 + Loop 1 time. Command executes 2 times. + 0x1 + + + LOOP_2 + Loop 2 times. Command executes 3 times. + 0x2 + + + LOOP_3 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x3 + + + LOOP_4 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x4 + + + LOOP_5 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x5 + + + LOOP_6 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x6 + + + LOOP_7 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x7 + + + LOOP_8 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x8 + + + LOOP_9 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x9 + + + LOOP_15 + Loop 15 times. Command executes 16 times. + 0xF + + + + + NEXT + Next Command Select + 24 + 4 + read-write + + + NEXT_0 + No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. + 0 + + + NEXT_1 + Select CMD1 command buffer register as next command. + 0x1 + + + NEXT_2 + Select corresponding CMD command buffer register as next command + 0x2 + + + NEXT_3 + Select corresponding CMD command buffer register as next command + 0x3 + + + NEXT_4 + Select corresponding CMD command buffer register as next command + 0x4 + + + NEXT_5 + Select corresponding CMD command buffer register as next command + 0x5 + + + NEXT_6 + Select corresponding CMD command buffer register as next command + 0x6 + + + NEXT_7 + Select corresponding CMD command buffer register as next command + 0x7 + + + NEXT_8 + Select corresponding CMD command buffer register as next command + 0x8 + + + NEXT_9 + Select corresponding CMD command buffer register as next command + 0x9 + + + NEXT_15 + Select CMD15 command buffer register as next command. + 0xF + + + + + + + 4 + 0x4 + 1,2,3,4 + CV%s + Compare Value Register + 0x200 + 32 + read-write + 0 + 0xFFFFFFFF + + + CVL + Compare Value Low. + 0 + 16 + read-write + + + CVH + Compare Value High. + 16 + 16 + read-write + + + + + 2 + 0x4 + RESFIFO[%s] + ADC Data Result FIFO Register + 0x300 + 32 + read-only + 0 + 0xFFFFFFFF + + + D + Data result + 0 + 16 + read-only + + + TSRC + Trigger Source + 16 + 4 + read-only + + + TSRC_0 + Trigger source 0 initiated this conversion. + 0 + + + TSRC_1 + Trigger source 1 initiated this conversion. + 0x1 + + + TSRC_2 + Corresponding trigger source initiated this conversion. + 0x2 + + + TSRC_3 + Corresponding trigger source initiated this conversion. + 0x3 + + + TSRC_4 + Corresponding trigger source initiated this conversion. + 0x4 + + + TSRC_5 + Corresponding trigger source initiated this conversion. + 0x5 + + + TSRC_6 + Corresponding trigger source initiated this conversion. + 0x6 + + + TSRC_7 + Corresponding trigger source initiated this conversion. + 0x7 + + + TSRC_8 + Corresponding trigger source initiated this conversion. + 0x8 + + + TSRC_9 + Corresponding trigger source initiated this conversion. + 0x9 + + + TSRC_15 + Trigger source 15 initiated this conversion. + 0xF + + + + + LOOPCNT + Loop count value + 20 + 4 + read-only + + + LOOPCNT_0 + Result is from initial conversion in command. + 0 + + + LOOPCNT_1 + Result is from second conversion in command. + 0x1 + + + LOOPCNT_2 + Result is from LOOPCNT+1 conversion in command. + 0x2 + + + LOOPCNT_3 + Result is from LOOPCNT+1 conversion in command. + 0x3 + + + LOOPCNT_4 + Result is from LOOPCNT+1 conversion in command. + 0x4 + + + LOOPCNT_5 + Result is from LOOPCNT+1 conversion in command. + 0x5 + + + LOOPCNT_6 + Result is from LOOPCNT+1 conversion in command. + 0x6 + + + LOOPCNT_7 + Result is from LOOPCNT+1 conversion in command. + 0x7 + + + LOOPCNT_8 + Result is from LOOPCNT+1 conversion in command. + 0x8 + + + LOOPCNT_9 + Result is from LOOPCNT+1 conversion in command. + 0x9 + + + LOOPCNT_15 + Result is from 16th conversion in command. + 0xF + + + + + CMDSRC + Command Buffer Source + 24 + 4 + read-only + + + CMDSRC_0 + Not a valid value CMDSRC value for a dataword in RESFIFO. 0x0 is only found in initial FIFO state prior to an ADC conversion result dataword being stored to a RESFIFO buffer. + 0 + + + CMDSRC_1 + CMD1 buffer used as control settings for this conversion. + 0x1 + + + CMDSRC_2 + Corresponding command buffer used as control settings for this conversion. + 0x2 + + + CMDSRC_3 + Corresponding command buffer used as control settings for this conversion. + 0x3 + + + CMDSRC_4 + Corresponding command buffer used as control settings for this conversion. + 0x4 + + + CMDSRC_5 + Corresponding command buffer used as control settings for this conversion. + 0x5 + + + CMDSRC_6 + Corresponding command buffer used as control settings for this conversion. + 0x6 + + + CMDSRC_7 + Corresponding command buffer used as control settings for this conversion. + 0x7 + + + CMDSRC_8 + Corresponding command buffer used as control settings for this conversion. + 0x8 + + + CMDSRC_9 + Corresponding command buffer used as control settings for this conversion. + 0x9 + + + CMDSRC_15 + CMD15 buffer used as control settings for this conversion. + 0xF + + + + + VALID + FIFO entry is valid + 31 + 1 + read-only + + + VALID_0 + FIFO is empty. Discard any read from RESFIFO. + 0 + + + VALID_1 + FIFO record read from RESFIFO is valid. + 0x1 + + + + + + + 33 + 0x4 + CAL_GAR[%s] + Calibration General A-Side Registers + 0x400 + 32 + read-write + 0 + 0xFFFFFFFF + + + CAL_GAR_VAL + Calibration General A Side Register Element + 0 + 16 + read-write + + + + + 33 + 0x4 + CAL_GBR[%s] + Calibration General B-Side Registers + 0x500 + 32 + read-write + 0 + 0xFFFFFFFF + + + CAL_GBR_VAL + Calibration General B Side Register Element + 0 + 16 + read-write + + + + + TST + ADC Test Register + 0xFFC + 32 + read-write + 0 + 0xFFFFFFFF + + + CST_LONG + Calibration Sample Time Long + 0 + 1 + read-write + + + CST_LONG_0 + Normal sample time. Minimum sample time of 3 ADCK cycles. + 0 + + + CST_LONG_1 + Increased sample time. 67 ADCK cycles total sample time. + 0x1 + + + + + FOFFM + Force M-side positive offset + 8 + 1 + read-write + + + FOFFM_0 + Normal operation. No forced offset. + 0 + + + FOFFM_1 + Test configuration. Forced positive offset on MDAC. + 0x1 + + + + + FOFFP + Force P-side positive offset + 9 + 1 + read-write + + + FOFFP_0 + Normal operation. No forced offset. + 0 + + + FOFFP_1 + Test configuration. Forced positive offset on PDAC. + 0x1 + + + + + FOFFM2 + Force M-side negative offset + 10 + 1 + read-write + + + FOFFM2_0 + Normal operation. No forced offset. + 0 + + + FOFFM2_1 + Test configuration. Forced negative offset on MDAC. + 0x1 + + + + + FOFFP2 + Force P-side negative offset + 11 + 1 + read-write + + + FOFFP2_0 + Normal operation. No forced offset. + 0 + + + FOFFP2_1 + Test configuration. Forced negative offset on PDAC. + 0x1 + + + + + TESTEN + Enable test configuration + 23 + 1 + read-write + + + TESTEN_0 + Normal operation. Test configuration not enabled. + 0 + + + TESTEN_1 + Hardware BIST Test in progress. + 0x1 + + + + + + + + + USBFSH + USB0 Full-speed Host controller + USBFSH + 0x400A2000 + + 0 + 0x60 + registers + + + USB0_NEEDCLK + 27 + + + USB0 + 28 + + + + HCREVISION + BCD representation of the version of the HCI specification that is implemented by the Host Controller (HC) + 0 + 32 + read-only + 0x10 + 0xFF + + + REV + Revision. + 0 + 8 + read-only + + + + + HCCONTROL + Defines the operating modes of the HC + 0x4 + 32 + read-write + 0 + 0x7FF + + + CBSR + ControlBulkServiceRatio. + 0 + 2 + read-write + + + PLE + PeriodicListEnable. + 2 + 1 + read-write + + + IE + IsochronousEnable. + 3 + 1 + read-write + + + CLE + ControlListEnable. + 4 + 1 + read-write + + + BLE + BulkListEnable This bit is set to enable the processing of the Bulk list in the next Frame. + 5 + 1 + read-write + + + HCFS + HostControllerFunctionalState for USB 00b: USBRESET 01b: USBRESUME 10b: USBOPERATIONAL 11b: USBSUSPEND A transition to USBOPERATIONAL from another state causes SOFgeneration to begin 1 ms later. + 6 + 2 + read-write + + + IR + InterruptRouting This bit determines the routing of interrupts generated by events registered in HcInterruptStatus. + 8 + 1 + read-write + + + RWC + RemoteWakeupConnected This bit indicates whether HC supports remote wake-up signaling. + 9 + 1 + read-write + + + RWE + RemoteWakeupEnable This bit is used by HCD to enable or disable the remote wake-up feature upon the detection of upstream resume signaling. + 10 + 1 + read-write + + + + + HCCOMMANDSTATUS + This register is used to receive the commands from the Host Controller Driver (HCD) + 0x8 + 32 + read-write + 0 + 0xCF + + + HCR + HostControllerReset This bit is set by HCD to initiate a software reset of HC. + 0 + 1 + read-write + + + CLF + ControlListFilled This bit is used to indicate whether there are any TDs on the Control list. + 1 + 1 + read-write + + + BLF + BulkListFilled This bit is used to indicate whether there are any TDs on the Bulk list. + 2 + 1 + read-write + + + OCR + OwnershipChangeRequest This bit is set by an OS HCD to request a change of control of the HC. + 3 + 1 + read-write + + + SOC + SchedulingOverrunCount These bits are incremented on each scheduling overrun error. + 6 + 2 + read-write + + + + + HCINTERRUPTSTATUS + Indicates the status on various events that cause hardware interrupts by setting the appropriate bits + 0xC + 32 + read-write + 0 + 0xFFFFFC7F + + + SO + SchedulingOverrun This bit is set when the USB schedule for the current Frame overruns and after the update of HccaFrameNumber. + 0 + 1 + read-write + + + WDH + WritebackDoneHead This bit is set immediately after HC has written HcDoneHead to HccaDoneHead. + 1 + 1 + read-write + + + SF + StartofFrame This bit is set by HC at each start of a frame and after the update of HccaFrameNumber. + 2 + 1 + read-write + + + RD + ResumeDetected This bit is set when HC detects that a device on the USB is asserting resume signaling. + 3 + 1 + read-write + + + UE + UnrecoverableError This bit is set when HC detects a system error not related to USB. + 4 + 1 + read-write + + + FNO + FrameNumberOverflow This bit is set when the MSb of HcFmNumber (bit 15) changes value, from 0 to 1 or from 1 to 0, and after HccaFrameNumber has been updated. + 5 + 1 + read-write + + + RHSC + RootHubStatusChange This bit is set when the content of HcRhStatus or the content of any of HcRhPortStatus[NumberofDownstreamPort] has changed. + 6 + 1 + read-write + + + OC + OwnershipChange This bit is set by HC when HCD sets the OwnershipChangeRequest field in HcCommandStatus. + 10 + 22 + read-write + + + + + HCINTERRUPTENABLE + Controls the bits in the HcInterruptStatus register and indicates which events will generate a hardware interrupt + 0x10 + 32 + read-write + 0 + 0xC000007F + + + SO + Scheduling Overrun interrupt. + 0 + 1 + read-write + + + WDH + HcDoneHead Writeback interrupt. + 1 + 1 + read-write + + + SF + Start of Frame interrupt. + 2 + 1 + read-write + + + RD + Resume Detect interrupt. + 3 + 1 + read-write + + + UE + Unrecoverable Error interrupt. + 4 + 1 + read-write + + + FNO + Frame Number Overflow interrupt. + 5 + 1 + read-write + + + RHSC + Root Hub Status Change interrupt. + 6 + 1 + read-write + + + OC + Ownership Change interrupt. + 30 + 1 + read-write + + + MIE + Master Interrupt Enable. + 31 + 1 + read-write + + + + + HCINTERRUPTDISABLE + The bits in this register are used to disable corresponding bits in the HCInterruptStatus register and in turn disable that event leading to hardware interrupt + 0x14 + 32 + read-write + 0 + 0xC000007F + + + SO + Scheduling Overrun interrupt. + 0 + 1 + read-write + + + WDH + HcDoneHead Writeback interrupt. + 1 + 1 + read-write + + + SF + Start of Frame interrupt. + 2 + 1 + read-write + + + RD + Resume Detect interrupt. + 3 + 1 + read-write + + + UE + Unrecoverable Error interrupt. + 4 + 1 + read-write + + + FNO + Frame Number Overflow interrupt. + 5 + 1 + read-write + + + RHSC + Root Hub Status Change interrupt. + 6 + 1 + read-write + + + OC + Ownership Change interrupt. + 30 + 1 + read-write + + + MIE + A 0 written to this field is ignored by HC. + 31 + 1 + read-write + + + + + HCHCCA + Contains the physical address of the host controller communication area + 0x18 + 32 + read-write + 0 + 0xFFFFFF00 + + + HCCA + Base address of the Host Controller Communication Area. + 8 + 24 + read-write + + + + + HCPERIODCURRENTED + Contains the physical address of the current isochronous or interrupt endpoint descriptor + 0x1C + 32 + read-write + 0 + 0xFFFFFFF0 + + + PCED + The content of this register is updated by HC after a periodic ED is processed. + 4 + 28 + read-write + + + + + HCCONTROLHEADED + Contains the physical address of the first endpoint descriptor of the control list + 0x20 + 32 + read-write + 0 + 0xFFFFFFF0 + + + CHED + HC traverses the Control list starting with the HcControlHeadED pointer. + 4 + 28 + read-write + + + + + HCCONTROLCURRENTED + Contains the physical address of the current endpoint descriptor of the control list + 0x24 + 32 + read-write + 0 + 0xFFFFFFF0 + + + CCED + ControlCurrentED. + 4 + 28 + read-write + + + + + HCBULKHEADED + Contains the physical address of the first endpoint descriptor of the bulk list + 0x28 + 32 + read-write + 0 + 0xFFFFFFF0 + + + BHED + BulkHeadED HC traverses the bulk list starting with the HcBulkHeadED pointer. + 4 + 28 + read-write + + + + + HCBULKCURRENTED + Contains the physical address of the current endpoint descriptor of the bulk list + 0x2C + 32 + read-write + 0 + 0xFFFFFFF0 + + + BCED + BulkCurrentED This is advanced to the next ED after the HC has served the current one. + 4 + 28 + read-write + + + + + HCDONEHEAD + Contains the physical address of the last transfer descriptor added to the 'Done' queue + 0x30 + 32 + read-write + 0 + 0xFFFFFFF0 + + + DH + DoneHead When a TD is completed, HC writes the content of HcDoneHead to the NextTD field of the TD. + 4 + 28 + read-write + + + + + HCFMINTERVAL + Defines the bit time interval in a frame and the full speed maximum packet size which would not cause an overrun + 0x34 + 32 + read-write + 0x2EDF + 0xFFFF3FFF + + + FI + FrameInterval This specifies the interval between two consecutive SOFs in bit times. + 0 + 14 + read-write + + + FSMPS + FSLargestDataPacket This field specifies a value which is loaded into the Largest Data Packet Counter at the beginning of each frame. + 16 + 15 + read-write + + + FIT + FrameIntervalToggle HCD toggles this bit whenever it loads a new value to FrameInterval. + 31 + 1 + read-write + + + + + HCFMREMAINING + A 14-bit counter showing the bit time remaining in the current frame + 0x38 + 32 + read-write + 0 + 0x80003FFF + + + FR + FrameRemaining This counter is decremented at each bit time. + 0 + 14 + read-write + + + FRT + FrameRemainingToggle This bit is loaded from the FrameIntervalToggle field of HcFmInterval whenever FrameRemaining reaches 0. + 31 + 1 + read-write + + + + + HCFMNUMBER + Contains a 16-bit counter and provides the timing reference among events happening in the HC and the HCD + 0x3C + 32 + read-write + 0 + 0xFFFF + + + FN + FrameNumber This is incremented when HcFmRemaining is re-loaded. + 0 + 16 + read-write + + + + + HCPERIODICSTART + Contains a programmable 14-bit value which determines the earliest time HC should start processing a periodic list + 0x40 + 32 + read-write + 0 + 0x3FFF + + + PS + PeriodicStart After a hardware reset, this field is cleared and then set by HCD during the HC initialization. + 0 + 14 + read-write + + + + + HCLSTHRESHOLD + Contains 11-bit value which is used by the HC to determine whether to commit to transfer a maximum of 8-byte LS packet before EOF + 0x44 + 32 + read-write + 0x628 + 0xFFF + + + LST + LSThreshold This field contains a value which is compared to the FrameRemaining field prior to initiating a Low Speed transaction. + 0 + 12 + read-write + + + + + HCRHDESCRIPTORA + First of the two registers which describes the characteristics of the root hub + 0x48 + 32 + read-write + 0xFF000902 + 0xFF001FFF + + + NDP + NumberDownstreamPorts These bits specify the number of downstream ports supported by the root hub. + 0 + 8 + read-write + + + PSM + PowerSwitchingMode This bit is used to specify how the power switching of the root hub ports is controlled. + 8 + 1 + read-write + + + NPS + NoPowerSwitching These bits are used to specify whether power switching is supported or port are always powered. + 9 + 1 + read-write + + + DT + DeviceType This bit specifies that the root hub is not a compound device. + 10 + 1 + read-write + + + OCPM + OverCurrentProtectionMode This bit describes how the overcurrent status for the root hub ports are reported. + 11 + 1 + read-write + + + NOCP + NoOverCurrentProtection This bit describes how the overcurrent status for the root hub ports are reported. + 12 + 1 + read-write + + + POTPGT + PowerOnToPowerGoodTime This byte specifies the duration the HCD has to wait before accessing a powered-on port of the root hub. + 24 + 8 + read-write + + + + + HCRHDESCRIPTORB + Second of the two registers which describes the characteristics of the Root Hub + 0x4C + 32 + read-write + 0 + 0x3FFFFFFF + + + DR + DeviceRemovable Each bit is dedicated to a port of the Root Hub. + 0 + 16 + read-write + + + PPCM + PortPowerControlMask Each bit indicates if a port is affected by a global power control command when PowerSwitchingMode is set. + 16 + 16 + read-write + + + + + HCRHSTATUS + This register is divided into two parts + 0x50 + 32 + read-write + 0 + 0x80038003 + + + LPS + (read) LocalPowerStatus The Root Hub does not support the local power status feature; thus, this bit is always read as 0. + 0 + 1 + read-write + + + OCI + OverCurrentIndicator This bit reports overcurrent conditions when the global reporting is implemented. + 1 + 1 + read-write + + + DRWE + (read) DeviceRemoteWakeupEnable This bit enables a ConnectStatusChange bit as a resume event, causing a USBSUSPEND to USBRESUME state transition and setting the ResumeDetected interrupt. + 15 + 1 + read-write + + + LPSC + (read) LocalPowerStatusChange The root hub does not support the local power status feature. + 16 + 1 + read-write + + + OCIC + OverCurrentIndicatorChange This bit is set by hardware when a change has occurred to the OCI field of this register. + 17 + 1 + read-write + + + CRWE + (write) ClearRemoteWakeupEnable Writing a 1 clears DeviceRemoveWakeupEnable. + 31 + 1 + read-write + + + + + HCRHPORTSTATUS + Controls and reports the port events on a per-port basis + 0x54 + 32 + read-write + 0 + 0x1F031F + + + CCS + (read) CurrentConnectStatus This bit reflects the current state of the downstream port. + 0 + 1 + read-write + + + PES + (read) PortEnableStatus This bit indicates whether the port is enabled or disabled. + 1 + 1 + read-write + + + PSS + (read) PortSuspendStatus This bit indicates the port is suspended or in the resume sequence. + 2 + 1 + read-write + + + POCI + (read) PortOverCurrentIndicator This bit is only valid when the Root Hub is configured in such a way that overcurrent conditions are reported on a per-port basis. + 3 + 1 + read-write + + + PRS + (read) PortResetStatus When this bit is set by a write to SetPortReset, port reset signaling is asserted. + 4 + 1 + read-write + + + PPS + (read) PortPowerStatus This bit reflects the porta's power status, regardless of the type of power switching implemented. + 8 + 1 + read-write + + + LSDA + (read) LowSpeedDeviceAttached This bit indicates the speed of the device attached to this port. + 9 + 1 + read-write + + + CSC + ConnectStatusChange This bit is set whenever a connect or disconnect event occurs. + 16 + 1 + read-write + + + PESC + PortEnableStatusChange This bit is set when hardware events cause the PortEnableStatus bit to be cleared. + 17 + 1 + read-write + + + PSSC + PortSuspendStatusChange This bit is set when the full resume sequence is completed. + 18 + 1 + read-write + + + OCIC + PortOverCurrentIndicatorChange This bit is valid only if overcurrent conditions are reported on a per-port basis. + 19 + 1 + read-write + + + PRSC + PortResetStatusChange This bit is set at the end of the 10 ms port reset signal. + 20 + 1 + read-write + + + + + PORTMODE + Controls the port if it is attached to the host block or the device block + 0x5C + 32 + read-write + 0 + 0x10101 + + + ID + Port ID pin value. + 0 + 1 + read-write + + + ID_EN + Port ID pin pull-up enable. + 8 + 1 + read-write + + + DEV_ENABLE + 1: device 0: host. + 16 + 1 + read-write + + + + + + + USBHSH + USB1 High-speed Host Controller + USBHSH + 0x400A3000 + + 0 + 0x54 + registers + + + USB1_UTMI + 46 + + + USB1 + 47 + + + USB1_NEEDCLK + 48 + + + + CAPLENGTH_CHIPID + This register contains the offset value towards the start of the operational register space and the version number of the IP block + 0 + 32 + read-only + 0x1010010 + 0xFFFF00FF + + + CAPLENGTH + Capability Length: This is used as an offset. + 0 + 8 + read-only + + + CHIPID + Chip identification: indicates major and minor revision of the IP: [31:24] = Major revision [23:16] = Minor revision Major revisions used: 0x01: USB2. + 16 + 16 + read-only + + + + + HCSPARAMS + Host Controller Structural Parameters + 0x4 + 32 + read-only + 0x10011 + 0x1001F + + + N_PORTS + This register specifies the number of physical downstream ports implemented on this host controller. + 0 + 4 + read-only + + + PPC + This field indicates whether the host controller implementation includes port power control. + 4 + 1 + read-only + + + P_INDICATOR + This bit indicates whether the ports support port indicator control. + 16 + 1 + read-only + + + + + HCCPARAMS + Host Controller Capability Parameters + 0x8 + 32 + read-only + 0x20006 + 0xFFFFFFFF + + + LPMC + Link Power Management Capability. + 17 + 1 + read-only + + + + + FLADJ_FRINDEX + Frame Length Adjustment + 0xC + 32 + read-write + 0x20 + 0x3FFF003F + + + FLADJ + Frame Length Timing Value. + 0 + 6 + read-write + + + FRINDEX + Frame Index: Bits 29 to16 in this register are used for the frame number field in the SOF packet. + 16 + 14 + read-write + + + + + ATL_PTD_BASE_ADDR + Memory base address where ATL PTD0 is stored + 0x10 + 32 + read-write + 0 + 0xFFFFFFF0 + + + ATL_CUR + This indicates the current PTD that is used by the hardware when it is processing the ATL list. + 4 + 5 + read-write + + + ATL_BASE + Base address to be used by the hardware to find the start of the ATL list. + 9 + 23 + read-write + + + + + ISO_PTD_BASE_ADDR + Memory base address where ISO PTD0 is stored + 0x14 + 32 + read-write + 0 + 0xFFFFFFE0 + + + ISO_FIRST + This indicates the first PTD that is used by the hardware when it is processing the ISO list. + 5 + 5 + read-write + + + ISO_BASE + Base address to be used by the hardware to find the start of the ISO list. + 10 + 22 + read-write + + + + + INT_PTD_BASE_ADDR + Memory base address where INT PTD0 is stored + 0x18 + 32 + read-write + 0 + 0xFFFFFFE0 + + + INT_FIRST + This indicates the first PTD that is used by the hardware when it is processing the INT list. + 5 + 5 + read-write + + + INT_BASE + Base address to be used by the hardware to find the start of the INT list. + 10 + 22 + read-write + + + + + DATA_PAYLOAD_BASE_ADDR + Memory base address that indicates the start of the data payload buffers + 0x1C + 32 + read-write + 0 + 0xFFFF0000 + + + DAT_BASE + Base address to be used by the hardware to find the start of the data payload section. + 16 + 16 + read-write + + + + + USBCMD + USB Command register + 0x20 + 32 + read-write + 0 + 0x1F00078F + + + RS + Run/Stop: 1b = Run. + 0 + 1 + read-write + + + HCRESET + Host Controller Reset: This control bit is used by the software to reset the host controller. + 1 + 1 + read-write + + + FLS + Frame List Size: This field specifies the size of the frame list. + 2 + 2 + read-write + + + LHCR + Light Host Controller Reset: This bit allows the driver software to reset the host controller without affecting the state of the ports. + 7 + 1 + read-write + + + ATL_EN + ATL List enabled. + 8 + 1 + read-write + + + ISO_EN + ISO List enabled. + 9 + 1 + read-write + + + INT_EN + INT List enabled. + 10 + 1 + read-write + + + HIRD + Host-Initiated Resume Duration. + 24 + 4 + read-write + + + LPM_RWU + bRemoteWake field. + 28 + 1 + read-write + + + + + USBSTS + USB Interrupt Status register + 0x24 + 32 + read-write + 0 + 0xF000C + + + PCD + Port Change Detect: The host controller sets this bit to logic 1 when any port has a change bit transition from a 0 to a one or a Force Port Resume bit transition from a 0 to a 1 as a result of a J-K transition detected on a suspended port. + 2 + 1 + read-write + + + FLR + Frame List Rollover: The host controller sets this bit to logic 1 when the frame list index rolls over its maximum value to 0. + 3 + 1 + read-write + + + ATL_IRQ + ATL IRQ: Indicates that an ATL PTD (with I-bit set) was completed. + 16 + 1 + read-write + + + ISO_IRQ + ISO IRQ: Indicates that an ISO PTD (with I-bit set) was completed. + 17 + 1 + read-write + + + INT_IRQ + INT IRQ: Indicates that an INT PTD (with I-bit set) was completed. + 18 + 1 + read-write + + + SOF_IRQ + SOF interrupt: Every time when the host sends a Start of Frame token on the USB bus, this bit is set. + 19 + 1 + read-write + + + + + USBINTR + USB Interrupt Enable register + 0x28 + 32 + read-write + 0 + 0xF000C + + + PCDE + Port Change Detect Interrupt Enable: 1: enable 0: disable. + 2 + 1 + read-write + + + FLRE + Frame List Rollover Interrupt Enable: 1: enable 0: disable. + 3 + 1 + read-write + + + ATL_IRQ_E + ATL IRQ Enable bit: 1: enable 0: disable. + 16 + 1 + read-write + + + ISO_IRQ_E + ISO IRQ Enable bit: 1: enable 0: disable. + 17 + 1 + read-write + + + INT_IRQ_E + INT IRQ Enable bit: 1: enable 0: disable. + 18 + 1 + read-write + + + SOF_E + SOF Interrupt Enable bit: 1: enable 0: disable. + 19 + 1 + read-write + + + + + PORTSC1 + Port Status and Control register + 0x2C + 32 + read-write + 0 + 0xFFFFDFFF + + + CCS + Current Connect Status: Logic 1 indicates a device is present on the port. + 0 + 1 + read-write + + + CSC + Connect Status Change: Logic 1 means that the value of CCS has changed. + 1 + 1 + read-write + + + PED + Port Enabled/Disabled. + 2 + 1 + read-write + + + PEDC + Port Enabled/Disabled Change: Logic 1 means that the value of PED has changed. + 3 + 1 + read-write + + + OCA + Over-current active: Logic 1 means that this port has an over-current condition. + 4 + 1 + read-write + + + OCC + Over-current change: Logic 1 means that the value of OCA has changed. + 5 + 1 + read-write + + + FPR + Force Port Resume: Logic 1 means resume (K-state) detected or driven on the port. + 6 + 1 + read-write + + + SUSP + Suspend: Logic 1 means port is in the suspend state. + 7 + 1 + read-write + + + PR + Port Reset: Logic 1 means the port is in the reset state. + 8 + 1 + read-write + + + SUS_L1 + Suspend using L1 0b = Suspend using L2 1b = Suspend using L1 When this bit is set to a 1 and a non-zero value is specified in the Device Address field, the host controller will generate an LPM Token to enter the L1 state whenever software writes a one to the Suspend bit, as well as L1 exit timing during any device or host-initiated resume. + 9 + 1 + read-write + + + LS + Line Status: This field reflects the current logical levels of the DP (bit 11) and DM (bit 10) signal lines. + 10 + 2 + read-only + + + PP + Port Power: The function of this bit depends on the value of the Port Power Control (PPC) bit in the HCSPARAMS register. + 12 + 1 + read-write + + + PIC + Port Indicator Control : Writing to this field has no effect if the P_INDICATOR bit in the HCSPARAMS register is logic 0. + 14 + 2 + read-write + + + PTC + Port Test Control: A non-zero value indicates that the port is operating in the test mode as indicated by the value. + 16 + 4 + read-write + + + PSPD + Port Speed: 00b: Low-speed 01b: Full-speed 10b: High-speed 11b: Reserved. + 20 + 2 + read-write + + + WOO + Wake on overcurrent enable: Writing this bit to a one enables the port to be sensitive to overcurrent conditions as wake-up events. + 22 + 1 + read-write + + + SUS_STAT + These two bits are used by software to determine whether the most recent L1 suspend request was successful: 00b: Success-state transition was successful (ACK) 01b: Not Yet - Device was unable to enter the L1 state at this time (NYET) 10b: Not supported - Device does not support the L1 state (STALL) 11b: Timeout/Error - Device failed to respond or an error occurred. + 23 + 2 + read-write + + + DEV_ADD + Device Address for LPM tokens. + 25 + 7 + read-write + + + + + ATL_PTD_DONE_MAP + Done map for each ATL PTD + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + ATL_DONE + The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed. + 0 + 32 + read-write + + + + + ATL_PTD_SKIP_MAP + Skip map for each ATL PTD + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + ATL_SKIP + When a bit in the PTD Skip Map is set to logic 1, the corresponding PTD will be skipped, independent of the V bit setting. + 0 + 32 + read-write + + + + + ISO_PTD_DONE_MAP + Done map for each ISO PTD + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + ISO_DONE + The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed. + 0 + 32 + read-write + + + + + ISO_PTD_SKIP_MAP + Skip map for each ISO PTD + 0x3C + 32 + read-write + 0 + 0xFFFFFFFF + + + ISO_SKIP + The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed. + 0 + 32 + read-write + + + + + INT_PTD_DONE_MAP + Done map for each INT PTD + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + INT_DONE + The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed. + 0 + 32 + read-write + + + + + INT_PTD_SKIP_MAP + Skip map for each INT PTD + 0x44 + 32 + read-write + 0 + 0xFFFFFFFF + + + INT_SKIP + When a bit in the PTD Skip Map is set to logic 1, the corresponding PTD will be skipped, independent of the V bit setting. + 0 + 32 + read-write + + + + + LAST_PTD_INUSE + Marks the last PTD in the list for ISO, INT and ATL + 0x48 + 32 + read-write + 0 + 0x1F1F1F + + + ATL_LAST + If hardware has reached this PTD and the J bit is not set, it will go to PTD0 as the next PTD to be processed. + 0 + 5 + read-write + + + ISO_LAST + This indicates the last PTD in the ISO list. + 8 + 5 + read-write + + + INT_LAST + This indicates the last PTD in the INT list. + 16 + 5 + read-write + + + + + UTMIPLUS_ULPI_DEBUG + Register to read/write registers in the attached USB PHY + 0x4C + 32 + read-write + 0 + 0x83FFFFFF + + + PHY_ADDR + UTMI+ mode: Bits 3:0 are used to control VControl signal on Vendor Interface of UTMI+ ULPI mode: Bits 7:0 are used as the address when doing a register access over the ULPI interface. + 0 + 8 + read-write + + + PHY_WDATA + UTMI+ mode: Reserved. + 8 + 8 + read-write + + + PHY_RDATA + UTMI+ mode: Bits 7:0 contains the value returned by the VStatus signal on Vendor Interface of UTMI+ ULPI mode: Bits 7:0 are used for the read data when reading a value to a ULPI PHY register. + 16 + 8 + read-write + + + PHY_RW + UTMI+ mode: Reserved. + 24 + 1 + read-write + + + PHY_ACCESS + Software writes this bit to one to start a read or write operation. + 25 + 1 + read-write + + + PHY_MODE + This bit indicates if the interface between the controller is UTMI+ or ULPI 0b: UTMI+ 1b: ULPI If the hardware supports both modes, this bit is RW by SW. + 31 + 1 + read-write + + + + + PORTMODE + Controls the port if it is attached to the host block or the device block + 0x50 + 32 + read-write + 0x40000 + 0xD0101 + + + ID0 + Port 0 ID pin value. + 0 + 1 + read-write + + + ID0_EN + Port 0 ID pin pull-up enable. + 8 + 1 + read-write + + + DEV_ENABLE + If this bit is set to one, one of the ports will behave as a USB device. + 16 + 1 + read-write + + + SW_CTRL_PDCOM + This bit indicates if the PHY power-down input is controlled by software or by hardware. + 18 + 1 + read-write + + + SW_PDCOM + This bit is only used when SW_CTRL_PDCOM is set to 1b. + 19 + 1 + read-write + + + + + + + HASHCRYPT + Hash-Crypt peripheral + HASHCRYPT + 0x400A4000 + + 0 + 0xA0 + registers + + + HASHCRYPT + 54 + + + + CTRL + Is control register to enable and operate Hash and Crypto + 0 + 32 + read-write + 0 + 0x1317 + + + Mode + The operational mode to use, or 0 if none. Note that the CONFIG register will indicate if specific modes beyond SHA1 and SHA2-256 are available. + 0 + 3 + read-write + + + DISABLED + Disabled + 0 + + + SHA1 + SHA1 is enabled + 0x1 + + + SHA2_256 + SHA2-256 is enabled + 0x2 + + + SHA2_512 + SHA2-512 is enabled (if available) + 0x3 + + + AES + AES if available (see also CRYPTCFG register for more controls) + 0x4 + + + ICB_AES + ICB-AES if available (see also CRYPTCFG register for more controls) + 0x5 + + + SALSA20 + Salsa20/20 if available (including XSalsa - see also CRYPTCFG register) + 0x6 + + + CHACHA20 + ChaCha20 if available (see also CRYPTCFG register for more controls) + 0x7 + + + + + New_Hash + Written with 1 when starting a new Hash/Crypto. It self clears. Note that the WAITING Status bit will clear for a cycle during the initialization from New=1. + 4 + 1 + read-write + + + START + Starts a new Hash/Crypto and initializes the Digest/Result. + 0x1 + + + + + DMA_I + Written with 1 to use DMA to fill INDATA. If Hash, will request from DMA for 16 words and then will process the Hash. If Cryptographic, it will load as many words as needed, including key if not already loaded. It will then request again. Normal model is that the DMA interrupts the processor when its length expires. Note that if the processor will write the key and optionally IV, it should not enable this until it has done so. Otherwise, the DMA will be expected to load those for the 1st block (when needed). + 8 + 1 + read-write + + + NOT_USED + DMA is not used. Processor writes the necessary words when WAITING is set (interrupts), unless AHB Master is used. + 0 + + + PUSH + DMA will push in the data. + 0x1 + + + + + DMA_O + Written to 1 to use DMA to drain the digest/output. If both DMA_I and DMA_O are set, the DMA has to know to switch direction and the locations. This can be used for crypto uses. + 9 + 1 + read-write + + + NOTUSED + DMA is not used. Processor reads the digest/output in response to DIGEST interrupt. + 0 + + + + + HASHSWPB + If 1, will swap bytes in the word for SHA hashing. The default is byte order (so LSB is 1st byte) but this allows swapping to MSB is 1st such as is shown in SHS spec. For cryptographic swapping, see the CRYPTCFG register. + 12 + 1 + read-write + + + + + STATUS + Indicates status of Hash peripheral. + 0x4 + 32 + read-write + 0 + 0x3F0037 + + + WAITING + If 1, the block is waiting for more data to process. + 0 + 1 + read-only + + + NOT_WAITING + Not waiting for data - may be disabled or may be busy. Note that for cryptographic uses, this is not set if IsLast is set nor will it set until at least 1 word is read of the output. + 0 + + + WAITING + Waiting for data to be written in (16 words) + 0x1 + + + + + DIGEST_aka_OUTDATA + For Hash, if 1 then a DIGEST is ready and waiting and there is no active next block already started. For Cryptographic uses, this will be set for each block processed, indicating OUTDATA (and OUTDATA2 if larger output) contains the next value to read out. This is cleared when any data is written, when New is written, for Cryptographic uses when the last word is read out, or when the block is disabled. + 1 + 1 + read-only + + + NOT_READY + No Digest is ready + 0 + + + READY + Digest is ready. Application may read it or may write more data + 0x1 + + + + + ERROR + If 1, an error occurred. For normal uses, this is due to an attempted overrun: INDATA was written when it was not appropriate. For Master cases, this is an AHB bus error; the COUNT field will indicate which block it was on. + 2 + 1 + read-write + oneToClear + + + NO_ERROR + No error. + 0 + + + ERROR + An error occurred since last cleared (written 1 to clear). + 0x1 + + + + + NEEDKEY + Indicates the block wants the key to be written in (set along with WAITING) + 4 + 1 + read-only + + + NOT_NEED + No Key is needed and writes will not be treated as Key + 0 + + + NEED + Key is needed and INDATA/ALIAS will be accepted as Key. Will also set WAITING. + 0x1 + + + + + NEEDIV + Indicates the block wants an IV/NONE to be written in (set along with WAITING) + 5 + 1 + read-only + + + NOT_NEED + No IV/Nonce is needed, either because written already or because not needed. + 0 + + + NEED + IV/Nonce is needed and INDATA/ALIAS will be accepted as IV/Nonce. Will also set WAITING. + 0x1 + + + + + ICBIDX + If ICB-AES is selected, then reads as the ICB index count based on ICBSTRM (from CRYPTCFG). That is, if 3 bits of ICBSTRM, then this will count from 0 to 7 and then back to 0. On 0, it has to compute the full ICB, quicker when not 0. + 16 + 6 + read-only + + + + + INTENSET + Write 1 to enable interrupts; reads back with which are set. + 0x8 + 32 + read-write + 0 + 0x7 + + + WAITING + Indicates if should interrupt when waiting for data input. + 0 + 1 + read-write + + + NO_INTERRUPT + Will not interrupt when waiting. + 0 + + + INTERRUPT + Will interrupt when waiting + 0x1 + + + + + DIGEST + Indicates if should interrupt when Digest (or Outdata) is ready (completed a hash/crypto or completed a full sequence). + 1 + 1 + read-write + + + NO_INTERRUPT + Will not interrupt when Digest is ready + 0 + + + INTERRUPT + Will interrupt when Digest is ready. Interrupt cleared by writing more data, starting a new Hash, or disabling (done). + 0x1 + + + + + ERROR + Indicates if should interrupt on an ERROR (as defined in Status) + 2 + 1 + read-write + + + NOT_INTERRUPT + Will not interrupt on Error. + 0 + + + INTERRUPT + Will interrupt on Error (until cleared). + 0x1 + + + + + + + INTENCLR + Write 1 to clear interrupts. + 0xC + 32 + read-write + 0 + 0 + + + WAITING + Write 1 to clear mask. + 0 + 1 + read-write + oneToClear + + + DIGEST + Write 1 to clear mask. + 1 + 1 + read-write + oneToClear + + + ERROR + Write 1 to clear mask. + 2 + 1 + read-write + oneToClear + + + + + MEMCTRL + Setup Master to access memory (if available) + 0x10 + 32 + read-write + 0 + 0x7FF0001 + + + MASTER + no description available + 0 + 1 + read-write + + + NOT_USED + Mastering is not used and the normal DMA or Interrupt based model is used with INDATA. + 0 + + + ENABLED + Mastering is enabled and DMA and INDATA should not be used. + 0x1 + + + + + COUNT + Number of 512-bit (128-bit if AES, except 1st block which may include key and IV) blocks to copy starting at MEMADDR. This register will decrement after each block is copied, ending in 0. For Hash, the DIGEST interrupt will occur when it reaches 0. Fro AES, the DIGEST/OUTDATA interrupt will occur on ever block. If a bus error occurs, it will stop with this field set to the block that failed. 0:Done - nothing to process. 1 to 2K: Number of 512-bit (or 128bit) blocks to hash. + 16 + 11 + read-write + + + + + MEMADDR + Address to start memory access from (if available). + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + BASE + Address base to start copying from, word aligned (so bits 1:0 must be 0). This field will advance as it processes the words. If it fails with a bus error, the register will contain the failing word. N:Address in Flash or RAM space; RAM only as mapped in this part. May also be able to address SPIFI. + 0 + 32 + read-write + + + + + INDATA + Input of 16 words at a time to load up buffer. + 0x20 + 32 + write-only + 0 + 0 + + + DATA + Write next word in little-endian form. The hash requires big endian word data, but this block swaps the bytes automatically. That is, SHA assumes the data coming in is treated as bytes (e.g. "abcd") and since the ARM core will treat "abcd" as a word as 0x64636261, the block will swap the word to restore into big endian. + 0 + 32 + write-only + + + + + 7 + 0x4 + ALIAS[%s] + no description available + 0x24 + 32 + write-only + 0 + 0 + + + DATA + Write next word in little-endian form. The hash requires big endian word data, but this block swaps the bytes automatically. That is, SHA assumes the data coming in is treated as bytes (e.g. "abcd") and since the ARM core will treat "abcd" as a word as 0x64636261, the block will swap the word to restore into big endian. + 0 + 32 + write-only + + + + + 8 + 0x4 + OUTDATA0[%s] + no description available + 0x40 + 32 + read-only + 0 + 0xFFFFFFFF + + + DIGEST_OUTPUT + One word of the Digest or output. Note that only 1st 4 are populated for AES and 1st 5 are populated for SHA1. + 0 + 32 + read-only + + + + + 8 + 0x4 + OUTDATA1[%s] + no description available + 0x60 + 32 + read-only + 0 + 0xFFFFFFFF + + + OUTPUT + One word of the 2nd half of the output when used. + 0 + 32 + read-only + + + + + CRYPTCFG + Crypto settings for AES and Salsa and ChaCha + 0x80 + 32 + read-write + 0 + 0xF31FFF + + + MSW1ST_OUT + If 1, OUTDATA0 will be read Most significant word 1st for AES. Else it will be read in normal little endian - Least significant word 1st. Note: only if allowed by configuration. + 0 + 1 + read-write + + + SWAPKEY + If 1, will Swap the key input (bytes in each word). + 1 + 1 + read-write + + + SWAPDAT + If 1, will SWAP the data and IV inputs (bytes in each word). + 2 + 1 + read-write + + + MSW1ST + If 1, load of key, IV, and data is MSW 1st for AES. Else, the words are little endian. Note: only if allowed by configuration. + 3 + 1 + read-write + + + AESMODE + AES Cipher mode to use if plain AES + 4 + 2 + read-write + + + ECB + ECB - used as is + 0 + + + CBC + CBC mode (see details on IV/nonce) + 0x1 + + + CTR + CTR mode (see details on IV/nonce). See also AESCTRPOS. + 0x2 + + + + + AESDECRYPT + AES ECB direction. Only encryption used if CTR mode or manual modes such as CFB + 6 + 1 + read-write + + + AESDECRYPT_0 + Encrypt + 0 + + + DECRYPT + Decrypt + 0x1 + + + + + AESSECRET + Selects the Hidden Secret key vs. User key, if provided. If security levels are used, only the highest level is permitted to select this. + 7 + 1 + read-write + + + NORMAL_WAY + User key provided in normal way + 0 + + + AESSECRET_1 + Secret key provided in hidden way by HW + 0x1 + + + + + AESKEYSZ + Sets the AES key size + 8 + 2 + read-write + + + BITS_128 + 128 bit key + 0 + + + BITS_192 + 192 bit key + 0x1 + + + BITS_256 + 256 bit key + 0x2 + + + + + AESCTRPOS + Halfword position of 16b counter in IV if AESMODE is CTR (position is fixed for Salsa and ChaCha). Only supports 16b counter, so application must control any additional bytes if using more. The 16-bit counter is read from the IV and incremented by 1 each time. Any other use CTR should use ECB directly and do its own XOR and so on. + 10 + 3 + read-write + + + STREAMLAST + Is 1 if last stream block. If not 1, then the engine will compute the next "hash". + 16 + 1 + read-write + + + XSALSA + Is 1 if XSalsa 128b NONCE to be used vs. 64b + 17 + 1 + read-write + + + ICBSZ + This sets the ICB size between 32 and 128 bits, using the following rules. Note that the counter is assumed to occupy the low order bits of the IV. + 20 + 2 + read-write + + + BITS_32 + 32 bits of the IV/ctr are used (from 127:96) + 0 + + + BITS_64 + 64 bits of the IV/ctr are used (from 127:64) + 0x1 + + + BITS_96 + 96 bits of the IV/ctr are used (from 127:32) + 0x2 + + + BIT_128 + All 128 bits of the IV/ctr are used + 0x3 + + + + + ICBSTRM + The size of the ICB-AES stream that can be pushed before needing to compute a new IV/ctr (counter start). This optimizes the performance of the stream of blocks after the 1st. + 22 + 2 + read-write + + + BLOCKS_8 + 8 blocks + 0 + + + BLOCKS_16 + 16 blocks + 0x1 + + + BLOCKS_32 + 32 blocks + 0x2 + + + BLOCKS_64 + 64 blocks + 0x3 + + + + + + + CONFIG + Returns the configuration of this block in this chip - indicates what services are available. + 0x84 + 32 + read-write + 0 + 0 + + + DUAL + 1 if 2 x 512 bit buffers, 0 if only 1 x 512 bit + 0 + 1 + read-only + + + DMA + 1 if DMA is connected + 1 + 1 + read-only + + + AHB + 1 if AHB Master is enabled + 3 + 1 + read-only + + + SHA512 + 1 if SHA2-512 included + 5 + 1 + read-only + + + AES + 1 if AES 128 included + 6 + 1 + read-only + + + AESKEY + 1 if AES 192 and 256 also included + 7 + 1 + read-only + + + SECRET + 1 if AES Secret key available + 8 + 1 + read-only + + + SALSA + 1 if Salsa included + 9 + 1 + read-only + + + CHACHA + 1 if ChaCha included + 10 + 1 + read-only + + + ICB + 1 if ICB over AES included + 11 + 1 + read-only + + + + + LOCK + Lock register allows locking to the current security level or unlocking by the lock holding level. + 0x8C + 32 + read-write + 0 + 0xFFF3 + + + SECLOCK + Write 1 to secure-lock this block (if running in a security state). Write 0 to unlock. If locked already, may only write if at same or higher security level as lock. Reads as: 0 if unlocked, else 1, 2, 3 to indicate security level it is locked at. NOTE: this and ID are the only readable registers if locked and current state is lower than lock level. + 0 + 2 + read-write + + + UNLOCK + Unlocks, so block is open to all. But, AHB Master will only issue non-secure requests. + 0 + + + LOCK + Locks to the current security level. AHB Master will issue requests at this level. + 0x1 + + + + + PATTERN + Must write 0xA75 to change lock state. A75:Pattern needed to change bits 1:0 + 4 + 12 + read-write + + + + + 4 + 0x4 + MASK[%s] + no description available + 0x90 + 32 + write-only + 0 + 0 + + + MASK + A random word. + 0 + 32 + write-only + + + + + + + CASPER + CASPER + CASPER + 0x400A5000 + + 0 + 0x84 + registers + + + + CTRL0 + Contains the offsets of AB and CD in the RAM. + 0 + 32 + read-write + 0 + 0x1FFD0005 + + + ABBPAIR + Which bank-pair the offset ABOFF is within. This must be 0 if only 2-up + 0 + 1 + read-write + + + PAIR0 + Bank-pair 0 (1st) + 0 + + + PAIR1 + Bank-pair 1 (2nd) + 0x1 + + + + + ABOFF + Word or DWord Offset of AB values, with B at [2]=0 and A at [2]=1 as far as the code sees (normally will be an interleaved bank so only sequential to AHB). Word offset only allowed if 32 bit operation. Ideally not in the same RAM as the CD values if 4-up + 2 + 1 + read-write + + + CDBPAIR + Which bank-pair the offset CDOFF is within. This must be 0 if only 2-up + 16 + 1 + read-write + + + PAIR0 + Bank-pair 0 (1st) + 0 + + + PAIR1 + Bank-pair 1 (2nd) + 0x1 + + + + + CDOFF + Word or DWord Offset of CD, with D at [2]=0 and C at [2]=1 as far as the code sees (normally will be an interleaved bank so only sequential to AHB). Word offset only allowed if 32 bit operation. Ideally not in the same RAM as the AB values + 18 + 11 + read-write + + + + + CTRL1 + Contains the opcode mode, iteration count, and result offset (in RAM) and also launches the accelerator. Note: with CP version: CTRL0 and CRTL1 can be written in one go with MCRR. + 0x4 + 32 + read-write + 0 + 0xDFFDFFFF + + + ITER + Iteration counter. Is number_cycles - 1. write 0 means Does one cycle - does not iterate. + 0 + 8 + read-write + + + MODE + Operation mode to perform. write 0 means Accelerator is inactive. write others means accelerator is active. + 8 + 8 + read-write + + + RESBPAIR + Which bank-pair the offset RESOFF is within. This must be 0 if only 2-up. Ideally this is not the same bank as ABBPAIR (when 4-up supported) + 16 + 1 + read-write + + + PAIR0 + Bank-pair 0 (1st) + 0 + + + PAIR1 + Bank-pair 1 (2nd) + 0x1 + + + + + RESOFF + Word or DWord Offset of result. Word offset only allowed if 32 bit operation. Ideally not in the same RAM as the AB and CD values + 18 + 11 + read-write + + + CSKIP + Skip rules on Carry if needed. This operation will be skipped based on Carry value (from previous operation) if not 0: + 30 + 2 + read-write + + + NO_SKIP + No Skip + 0 + + + SKIP_IF_1 + Skip if Carry is 1 + 0x1 + + + SKIP_IF_0 + Skip if Carry is 0 + 0x2 + + + SET_AND_SKIP + Set CTRLOFF to CDOFF and Skip + 0x3 + + + + + + + LOADER + Contains an optional loader to load into CTRL0/1 in steps to perform a set of operations. + 0x8 + 32 + read-write + 0 + 0x1FFD00FF + + + COUNT + Number of control pairs to load 0 relative (so 1 means load 1). write 1 means Does one op - does not iterate, write N means N control pairs to load + 0 + 8 + read-write + + + CTRLBPAIR + Which bank-pair the offset CTRLOFF is within. This must be 0 if only 2-up. Does not matter which bank is used as this is loaded when not performing an operation. + 16 + 1 + read-write + + + PAIR0 + Bank-pair 0 (1st) + 0 + + + PAIR1 + Bank-pair 1 (2nd) + 0x1 + + + + + CTRLOFF + DWord Offset of CTRL pair to load next. + 18 + 11 + read-write + + + + + STATUS + Indicates operational status and would contain the carry bit if used. + 0xC + 32 + read-write + 0 + 0x31 + + + DONE + Indicates if the accelerator has finished an operation. Write 1 to clear, or write CTRL1 to clear. + 0 + 1 + read-write + + + BUSY + Busy or just cleared + 0 + + + COMPLETED + Completed last operation + 0x1 + + + + + CARRY + Last carry value if operation produced a carry bit + 4 + 1 + read-only + + + NO_CARRY + Carry was 0 or no carry + 0 + + + CARRY + Carry was 1 + 0x1 + + + + + BUSY + Indicates if the accelerator is busy performing an operation + 5 + 1 + read-only + + + IDLE + Not busy - is idle + 0 + + + BUSY + Is busy + 0x1 + + + + + + + INTENSET + Sets interrupts + 0x10 + 32 + read-write + 0 + 0x1 + + + DONE + Set if the accelerator should interrupt when done. + 0 + 1 + read-write + + + NO_INTERRUPT + Do not interrupt when done + 0 + + + INTERRUPT + Interrupt when done + 0x1 + + + + + + + INTENCLR + Clears interrupts + 0x14 + 32 + read-write + 0 + 0x1 + + + DONE + Written to clear an interrupt set with INTENSET. + 0 + 1 + read-write + oneToClear + + + IGNORED + If written 0, ignored + 0 + + + NO_INTERRUPT + If written 1, do not Interrupt when done + 0x1 + + + + + + + INTSTAT + Interrupt status bits (mask of INTENSET and STATUS) + 0x18 + 32 + read-write + 0 + 0x1 + + + DONE + If set, interrupt is caused by accelerator being done. + 0 + 1 + read-only + + + NOT_CAUSED + Not caused by accelerator being done + 0 + + + CAUSED + Caused by accelerator being done + 0x1 + + + + + + + AREG + A register + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + REG_VALUE + Register to be fed into Multiplier. Is not normally written or read by application, but is available when accelerator not busy. + 0 + 32 + read-write + + + + + BREG + B register + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + REG_VALUE + Register to be fed into Multiplier. Is not normally written or read by application, but is available when accelerator not busy. + 0 + 32 + read-write + + + + + CREG + C register + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + REG_VALUE + Register to be fed into Multiplier. Is not normally written or read by application, but is available when accelerator not busy. + 0 + 32 + read-write + + + + + DREG + D register + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + REG_VALUE + Register to be fed into Multiplier. Is not normally written or read by application, but is available when accelerator not busy. + 0 + 32 + read-write + + + + + RES0 + Result register 0 + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + REG_VALUE + Register to hold working result (from multiplier, adder/xor, etc). Is not normally written or read by application, but is available when accelerator not busy. + 0 + 32 + read-write + + + + + RES1 + Result register 1 + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + REG_VALUE + Register to hold working result (from multiplier, adder/xor, etc). Is not normally written or read by application, but is available when accelerator not busy. + 0 + 32 + read-write + + + + + RES2 + Result register 2 + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + REG_VALUE + Register to hold working result (from multiplier, adder/xor, etc). Is not normally written or read by application, but is available when accelerator not busy. + 0 + 32 + read-write + + + + + RES3 + Result register 3 + 0x3C + 32 + read-write + 0 + 0xFFFFFFFF + + + REG_VALUE + Register to hold working result (from multiplier, adder/xor, etc). Is not normally written or read by application, but is available when accelerator not busy. + 0 + 32 + read-write + + + + + MASK + Optional mask register + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + MASK + Mask to apply as side channel countermeasure. 0: No mask to be used. N: Mask to XOR onto values + 0 + 32 + read-write + + + + + REMASK + Optional re-mask register + 0x64 + 32 + read-write + 0 + 0xFFFFFFFF + + + MASK + Mask to apply as side channel countermeasure. 0: No mask to be used. N: Mask to XOR onto values + 0 + 32 + read-write + + + + + LOCK + Security lock register + 0x80 + 32 + read-write + 0 + 0x1FFFF + + + LOCK + Reads back with security level locked to, or 0. Writes as 0 to unlock, 1 to lock. + 0 + 1 + read-write + + + UNLOCK + unlock + 0 + + + LOCK + Lock to current security level + 0x1 + + + + + KEY + Must be written as 0x73D to change the register. + 4 + 13 + read-write + + + KWY_VALUE + If set during write, will allow lock or unlock + 0x73D + + + + + + + + + POWERQUAD + Digital Signal Co-Processing companion to a Cortex-M v8M CPU core + POWERQUAD + 0x400A6000 + + 0 + 0x260 + registers + + + + OUTBASE + Base address register for output region + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + outbase + Base address register for the output region + 0 + 32 + read-write + + + + + OUTFORMAT + Output format + 0x4 + 32 + read-write + 0 + 0xFF33 + + + out_formatint + Output Internal format (00: q15; 01:q31; 10:float) + 0 + 2 + read-write + + + out_formatext + Output External format (00: q15; 01:q31; 10:float) + 4 + 2 + read-write + + + out_scaler + Output Scaler value (for scaled 'q31' formats) + 8 + 8 + read-write + + + + + TMPBASE + Base address register for temp region + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + tmpbase + Base address register for the temporary region + 0 + 32 + read-write + + + + + TMPFORMAT + Temp format + 0xC + 32 + read-write + 0 + 0xFF33 + + + tmp_formatint + Temp Internal format (00: q15; 01:q31; 10:float) + 0 + 2 + read-write + + + tmp_formatext + Temp External format (00: q15; 01:q31; 10:float) + 4 + 2 + read-write + + + tmp_scaler + Temp Scaler value (for scaled 'q31' formats) + 8 + 8 + read-write + + + + + INABASE + Base address register for input A region + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + inabase + Base address register for the input A region + 0 + 32 + read-write + + + + + INAFORMAT + Input A format + 0x14 + 32 + read-write + 0 + 0xFF33 + + + ina_formatint + Input A Internal format (00: q15; 01:q31; 10:float) + 0 + 2 + read-write + + + ina_formatext + Input A External format (00: q15; 01:q31; 10:float) + 4 + 2 + read-write + + + ina_scaler + Input A Scaler value (for scaled 'q31' formats) + 8 + 8 + read-write + + + + + INBBASE + Base address register for input B region + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + inbbase + Base address register for the input B region + 0 + 32 + read-write + + + + + INBFORMAT + Input B format + 0x1C + 32 + read-write + 0 + 0xFF33 + + + inb_formatint + Input B Internal format (00: q15; 01:q31; 10:float) + 0 + 2 + read-write + + + inb_formatext + Input B External format (00: q15; 01:q31; 10:float) + 4 + 2 + read-write + + + inb_scaler + Input B Scaler value (for scaled 'q31' formats) + 8 + 8 + read-write + + + + + CONTROL + PowerQuad Control register + 0x100 + 32 + read-write + 0 + 0x8000FFFF + + + decode_opcode + opcode specific to decode_machine + 0 + 4 + read-write + + + decode_machine + 0 : Coprocessor , 1 : matrix , 2 : fft , 3 : fir , 4 : stat , 5 : cordic , 6 -15 : NA + 4 + 4 + read-write + + + inst_busy + Instruction busy signal when high indicates processing is on + 31 + 1 + read-only + + + + + LENGTH + Length register + 0x104 + 32 + read-write + 0 + 0xFFFFFFFF + + + inst_length + Length register. When FIR : fir_xlength = inst_length[15:0] , fir_tlength = inst_len[31:16]. When MTX : rows_a = inst_length[4:0] , cols_a = inst_length[12:8] , cols_b = inst_length[20:16] + 0 + 32 + read-write + + + + + CPPRE + Pre-scale register + 0x108 + 32 + read-write + 0 + 0x3FFFF + + + cppre_in + co-processor scaling of input + 0 + 8 + read-write + + + cppre_out + co-processor fixed point output + 8 + 8 + read-write + + + cppre_sat + 1 : forces sub-32 bit saturation + 16 + 1 + read-write + + + cppre_sat8 + 0 = 8bits, 1 = 16bits + 17 + 1 + read-write + + + + + MISC + Misc register + 0x10C + 32 + read-write + 0 + 0xFFFFFFFF + + + inst_misc + Misc register. For Matrix : Used for scale factor + 0 + 32 + read-write + + + + + CURSORY + Cursory register + 0x110 + 32 + read-write + 0 + 0x1 + + + cursory + 1 : Enable cursory mode + 0 + 1 + read-write + + + + + CORDIC_X + Cordic input X register + 0x180 + 32 + read-write + 0 + 0xFFFFFFFF + + + cordic_x + Cordic input x + 0 + 32 + read-write + + + + + CORDIC_Y + Cordic input Y register + 0x184 + 32 + read-write + 0 + 0xFFFFFFFF + + + cordic_y + Cordic input y + 0 + 32 + read-write + + + + + CORDIC_Z + Cordic input Z register + 0x188 + 32 + read-write + 0 + 0xFFFFFFFF + + + cordic_z + Cordic input z + 0 + 32 + read-write + + + + + ERRSTAT + Read/Write register where error statuses are captured (sticky) + 0x18C + 32 + read-write + 0 + 0x1F + + + OVERFLOW + overflow + 0 + 1 + read-write + + + NAN + nan + 1 + 1 + read-write + + + FIXEDOVERFLOW + fixed_pt_overflow + 2 + 1 + read-write + + + UNDERFLOW + underflow + 3 + 1 + read-write + + + BUSERROR + bus_error + 4 + 1 + read-write + + + + + INTREN + INTERRUPT enable register + 0x190 + 32 + read-write + 0 + 0x7F + + + intr_oflow + 1 : Enable interrupt on Floating point overflow + 0 + 1 + read-write + + + intr_nan + 1 : Enable interrupt on Floating point NaN + 1 + 1 + read-write + + + intr_fixed + 1: Enable interrupt on Fixed point Overflow + 2 + 1 + read-write + + + intr_uflow + 1 : Enable interrupt on Subnormal truncation + 3 + 1 + read-write + + + intr_berr + 1: Enable interrupt on AHBM Buss Error + 4 + 1 + read-write + + + intr_comp + 1: Enable interrupt on instruction completion + 7 + 1 + read-write + + + + + EVENTEN + Event Enable register + 0x194 + 32 + read-write + 0 + 0xFFFFFFFF + + + event_oflow + 1 : Enable event trigger on Floating point overflow + 0 + 1 + read-write + + + event_nan + 1 : Enable event trigger on Floating point NaN + 1 + 1 + read-write + + + event_fixed + 1: Enable event trigger on Fixed point Overflow + 2 + 1 + read-write + + + event_uflow + 1 : Enable event trigger on Subnormal truncation + 3 + 1 + read-write + + + event_berr + 1: Enable event trigger on AHBM Buss Error + 4 + 1 + read-write + + + event_comp + 1: Enable event trigger on instruction completion + 7 + 1 + read-write + + + + + INTRSTAT + INTERRUPT STATUS register + 0x198 + 32 + read-write + 0 + 0x1 + + + intr_stat + Intr status ( 1 bit to indicate interrupt captured, 0 means no new interrupt), write any value will clear this bit + 0 + 1 + read-write + + + + + 16 + 0x4 + gpreg[%s] + General purpose register bank N. + 0x200 + 32 + read-write + 0 + 0x7CF73 + + + gpreg + General purpose register bank + 0 + 32 + read-write + + + + + 8 + 0x4 + compreg[%s] + Compute register bank + 0x240 + 32 + read-write + 0 + 0xFFFFFFFF + + + compreg + Compute register bank + 0 + 32 + read-write + + + + + + + AHB_SECURE_CTRL + AHB secure controller + AHB_SECURE_CTRL + 0x400AC000 + + 0 + 0x1000 + registers + + + + SEC_CTRL_FLASH_ROM_SLAVE_RULE + Security access rules for Flash and ROM slaves. + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FLASH_RULE + Security access rules for the whole FLASH : 0x0000_0000 - 0x0009_FFFF + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + ROM_RULE + Security access rules for the whole ROM : 0x0300_0000 - 0x0301_FFFF + 4 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_FLASH_MEM_RULE0 + Security access rules for FLASH sector 0 to sector 20. Each Flash sector is 32 Kbytes. There are 20 FLASH sectors in total. + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + RULE0 + secure control rule0. it can be set when check_reg's write_lock is '0' + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE1 + secure control rule1. it can be set when check_reg's write_lock is '0' + 4 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE2 + secure control rule2. it can be set when check_reg's write_lock is '0' + 8 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE3 + secure control rule3. it can be set when check_reg's write_lock is '0' + 12 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE4 + secure control rule4. it can be set when check_reg's write_lock is '0' + 16 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE5 + secure control rule5. it can be set when check_reg's write_lock is '0' + 20 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE6 + secure control rule6. it can be set when check_reg's write_lock is '0' + 24 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE7 + secure control rule7. it can be set when check_reg's write_lock is '0' + 28 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_FLASH_MEM_RULE1 + Security access rules for FLASH sector 0 to sector 20. Each Flash sector is 32 Kbytes. There are 20 FLASH sectors in total. + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + RULE0 + secure control rule0. it can be set when check_reg's write_lock is '0' + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE1 + secure control rule1. it can be set when check_reg's write_lock is '0' + 4 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE2 + secure control rule2. it can be set when check_reg's write_lock is '0' + 8 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE3 + secure control rule3. it can be set when check_reg's write_lock is '0' + 12 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE4 + secure control rule4. it can be set when check_reg's write_lock is '0' + 16 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE5 + secure control rule5. it can be set when check_reg's write_lock is '0' + 20 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE6 + secure control rule6. it can be set when check_reg's write_lock is '0' + 24 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE7 + secure control rule7. it can be set when check_reg's write_lock is '0' + 28 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_FLASH_MEM_RULE2 + Security access rules for FLASH sector 0 to sector 20. Each Flash sector is 32 Kbytes. There are 20 FLASH sectors in total. + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + RULE0 + secure control rule0. it can be set when check_reg's write_lock is '0' + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE1 + secure control rule1. it can be set when check_reg's write_lock is '0' + 4 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE2 + secure control rule2. it can be set when check_reg's write_lock is '0' + 8 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE3 + secure control rule3. it can be set when check_reg's write_lock is '0' + 12 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE4 + secure control rule4. it can be set when check_reg's write_lock is '0' + 16 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE5 + secure control rule5. it can be set when check_reg's write_lock is '0' + 20 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE6 + secure control rule6. it can be set when check_reg's write_lock is '0' + 24 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE7 + secure control rule7. it can be set when check_reg's write_lock is '0' + 28 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_ROM_MEM_RULE0 + Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total. + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + RULE0 + secure control rule0. it can be set when check_reg's write_lock is '0' + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE1 + secure control rule1. it can be set when check_reg's write_lock is '0' + 4 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE2 + secure control rule2. it can be set when check_reg's write_lock is '0' + 8 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE3 + secure control rule3. it can be set when check_reg's write_lock is '0' + 12 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE4 + secure control rule4. it can be set when check_reg's write_lock is '0' + 16 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE5 + secure control rule5. it can be set when check_reg's write_lock is '0' + 20 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE6 + secure control rule6. it can be set when check_reg's write_lock is '0' + 24 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE7 + secure control rule7. it can be set when check_reg's write_lock is '0' + 28 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_ROM_MEM_RULE1 + Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total. + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + RULE0 + secure control rule0. it can be set when check_reg's write_lock is '0' + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE1 + secure control rule1. it can be set when check_reg's write_lock is '0' + 4 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE2 + secure control rule2. it can be set when check_reg's write_lock is '0' + 8 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE3 + secure control rule3. it can be set when check_reg's write_lock is '0' + 12 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE4 + secure control rule4. it can be set when check_reg's write_lock is '0' + 16 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE5 + secure control rule5. it can be set when check_reg's write_lock is '0' + 20 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE6 + secure control rule6. it can be set when check_reg's write_lock is '0' + 24 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE7 + secure control rule7. it can be set when check_reg's write_lock is '0' + 28 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_ROM_MEM_RULE2 + Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total. + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + RULE0 + secure control rule0. it can be set when check_reg's write_lock is '0' + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE1 + secure control rule1. it can be set when check_reg's write_lock is '0' + 4 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE2 + secure control rule2. it can be set when check_reg's write_lock is '0' + 8 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE3 + secure control rule3. it can be set when check_reg's write_lock is '0' + 12 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE4 + secure control rule4. it can be set when check_reg's write_lock is '0' + 16 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE5 + secure control rule5. it can be set when check_reg's write_lock is '0' + 20 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE6 + secure control rule6. it can be set when check_reg's write_lock is '0' + 24 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE7 + secure control rule7. it can be set when check_reg's write_lock is '0' + 28 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_ROM_MEM_RULE3 + Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total. + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + RULE0 + secure control rule0. it can be set when check_reg's write_lock is '0' + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE1 + secure control rule1. it can be set when check_reg's write_lock is '0' + 4 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE2 + secure control rule2. it can be set when check_reg's write_lock is '0' + 8 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE3 + secure control rule3. it can be set when check_reg's write_lock is '0' + 12 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE4 + secure control rule4. it can be set when check_reg's write_lock is '0' + 16 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE5 + secure control rule5. it can be set when check_reg's write_lock is '0' + 20 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE6 + secure control rule6. it can be set when check_reg's write_lock is '0' + 24 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE7 + secure control rule7. it can be set when check_reg's write_lock is '0' + 28 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_RAMX_SLAVE_RULE + Security access rules for RAMX slaves. + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + RAMX_RULE + Security access rules for the whole RAMX : 0x0400_0000 - 0x0400_7FFF + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_RAMX_MEM_RULE0 + Security access rules for RAMX slaves. + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + RULE0 + secure control rule0. it can be set when check_reg's write_lock is '0' + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE1 + secure control rule1. it can be set when check_reg's write_lock is '0' + 4 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE2 + secure control rule2. it can be set when check_reg's write_lock is '0' + 8 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE3 + secure control rule3. it can be set when check_reg's write_lock is '0' + 12 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE4 + secure control rule4. it can be set when check_reg's write_lock is '0' + 16 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE5 + secure control rule5. it can be set when check_reg's write_lock is '0' + 20 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE6 + secure control rule6. it can be set when check_reg's write_lock is '0' + 24 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE7 + secure control rule7. it can be set when check_reg's write_lock is '0' + 28 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_RAM0_SLAVE_RULE + Security access rules for RAM0 slaves. + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + RAM0_RULE + Security access rules for the whole RAM0 : 0x2000_0000 - 0x2000_FFFF + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_RAM0_MEM_RULE0 + Security access rules for RAM0 slaves. + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + RULE0 + secure control rule0. it can be set when check_reg's write_lock is '0' + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE1 + secure control rule1. it can be set when check_reg's write_lock is '0' + 4 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE2 + secure control rule2. it can be set when check_reg's write_lock is '0' + 8 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE3 + secure control rule3. it can be set when check_reg's write_lock is '0' + 12 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE4 + secure control rule4. it can be set when check_reg's write_lock is '0' + 16 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE5 + secure control rule5. it can be set when check_reg's write_lock is '0' + 20 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE6 + secure control rule6. it can be set when check_reg's write_lock is '0' + 24 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE7 + secure control rule7. it can be set when check_reg's write_lock is '0' + 28 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_RAM0_MEM_RULE1 + Security access rules for RAM0 slaves. + 0x64 + 32 + read-write + 0 + 0xFFFFFFFF + + + RULE0 + secure control rule0. it can be set when check_reg's write_lock is '0' + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE1 + secure control rule1. it can be set when check_reg's write_lock is '0' + 4 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE2 + secure control rule2. it can be set when check_reg's write_lock is '0' + 8 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE3 + secure control rule3. it can be set when check_reg's write_lock is '0' + 12 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE4 + secure control rule4. it can be set when check_reg's write_lock is '0' + 16 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE5 + secure control rule5. it can be set when check_reg's write_lock is '0' + 20 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE6 + secure control rule6. it can be set when check_reg's write_lock is '0' + 24 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE7 + secure control rule7. it can be set when check_reg's write_lock is '0' + 28 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_RAM1_SLAVE_RULE + Security access rules for RAM1 slaves. + 0x70 + 32 + read-write + 0 + 0xFFFFFFFF + + + RAM0_RULE + Security access rules for the whole RAM1 : 0x2001_0000 - 0x2001_FFFF" name="0 + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_RAM1_MEM_RULE0 + Security access rules for RAM1 slaves. + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + RULE0 + secure control rule0. it can be set when check_reg's write_lock is '0' + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE1 + secure control rule1. it can be set when check_reg's write_lock is '0' + 4 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE2 + secure control rule2. it can be set when check_reg's write_lock is '0' + 8 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE3 + secure control rule3. it can be set when check_reg's write_lock is '0' + 12 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE4 + secure control rule4. it can be set when check_reg's write_lock is '0' + 16 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE5 + secure control rule5. it can be set when check_reg's write_lock is '0' + 20 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE6 + secure control rule6. it can be set when check_reg's write_lock is '0' + 24 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE7 + secure control rule7. it can be set when check_reg's write_lock is '0' + 28 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_RAM1_MEM_RULE1 + Security access rules for RAM1 slaves. + 0x84 + 32 + read-write + 0 + 0xFFFFFFFF + + + RULE0 + secure control rule0. it can be set when check_reg's write_lock is '0' + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE1 + secure control rule1. it can be set when check_reg's write_lock is '0' + 4 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE2 + secure control rule2. it can be set when check_reg's write_lock is '0' + 8 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE3 + secure control rule3. it can be set when check_reg's write_lock is '0' + 12 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE4 + secure control rule4. it can be set when check_reg's write_lock is '0' + 16 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE5 + secure control rule5. it can be set when check_reg's write_lock is '0' + 20 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE6 + secure control rule6. it can be set when check_reg's write_lock is '0' + 24 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE7 + secure control rule7. it can be set when check_reg's write_lock is '0' + 28 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_RAM2_SLAVE_RULE + Security access rules for RAM2 slaves. + 0x90 + 32 + read-write + 0 + 0xFFFFFFFF + + + RAM2_RULE + Security access rules for the whole RAM2 : 0x2002_0000 - 0x2002_FFFF + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_RAM2_MEM_RULE0 + Security access rules for RAM2 slaves. + 0xA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + RULE0 + secure control rule0. it can be set when check_reg's write_lock is '0' + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE1 + secure control rule1. it can be set when check_reg's write_lock is '0' + 4 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE2 + secure control rule2. it can be set when check_reg's write_lock is '0' + 8 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE3 + secure control rule3. it can be set when check_reg's write_lock is '0' + 12 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE4 + secure control rule4. it can be set when check_reg's write_lock is '0' + 16 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE5 + secure control rule5. it can be set when check_reg's write_lock is '0' + 20 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE6 + secure control rule6. it can be set when check_reg's write_lock is '0' + 24 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE7 + secure control rule7. it can be set when check_reg's write_lock is '0' + 28 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_RAM2_MEM_RULE1 + Security access rules for RAM2 slaves. + 0xA4 + 32 + read-write + 0 + 0xFFFFFFFF + + + RULE0 + secure control rule0. it can be set when check_reg's write_lock is '0' + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE1 + secure control rule1. it can be set when check_reg's write_lock is '0' + 4 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE2 + secure control rule2. it can be set when check_reg's write_lock is '0' + 8 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE3 + secure control rule3. it can be set when check_reg's write_lock is '0' + 12 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE4 + secure control rule4. it can be set when check_reg's write_lock is '0' + 16 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE5 + secure control rule5. it can be set when check_reg's write_lock is '0' + 20 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE6 + secure control rule6. it can be set when check_reg's write_lock is '0' + 24 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE7 + secure control rule7. it can be set when check_reg's write_lock is '0' + 28 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_RAM3_SLAVE_RULE + Security access rules for RAM3 slaves. + 0xB0 + 32 + read-write + 0 + 0xFFFFFFFF + + + RAM3_RULE + Security access rules for the whole RAM3: 0x2003_0000 - 0x2003_FFFF + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_RAM3_MEM_RULE0 + Security access rules for RAM3 slaves. + 0xC0 + 32 + read-write + 0 + 0xFFFFFFFF + + + RULE0 + secure control rule0. it can be set when check_reg's write_lock is '0' + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE1 + secure control rule1. it can be set when check_reg's write_lock is '0' + 4 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE2 + secure control rule2. it can be set when check_reg's write_lock is '0' + 8 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE3 + secure control rule3. it can be set when check_reg's write_lock is '0' + 12 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE4 + secure control rule4. it can be set when check_reg's write_lock is '0' + 16 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE5 + secure control rule5. it can be set when check_reg's write_lock is '0' + 20 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE6 + secure control rule6. it can be set when check_reg's write_lock is '0' + 24 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE7 + secure control rule7. it can be set when check_reg's write_lock is '0' + 28 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_RAM3_MEM_RULE1 + Security access rules for RAM3 slaves. + 0xC4 + 32 + read-write + 0 + 0xFFFFFFFF + + + RULE0 + secure control rule0. it can be set when check_reg's write_lock is '0' + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE1 + secure control rule1. it can be set when check_reg's write_lock is '0' + 4 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE2 + secure control rule2. it can be set when check_reg's write_lock is '0' + 8 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE3 + secure control rule3. it can be set when check_reg's write_lock is '0' + 12 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE4 + secure control rule4. it can be set when check_reg's write_lock is '0' + 16 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE5 + secure control rule5. it can be set when check_reg's write_lock is '0' + 20 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE6 + secure control rule6. it can be set when check_reg's write_lock is '0' + 24 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE7 + secure control rule7. it can be set when check_reg's write_lock is '0' + 28 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_RAM4_SLAVE_RULE + Security access rules for RAM4 slaves. + 0xD0 + 32 + read-write + 0 + 0xFFFFFFFF + + + RAM4_RULE + Security access rules for the whole RAM4 : 0x2004_0000 - 0x2004_3FFF + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_RAM4_MEM_RULE0 + Security access rules for RAM4 slaves. + 0xE0 + 32 + read-write + 0 + 0xFFFFFFFF + + + RULE0 + secure control rule0. it can be set when check_reg's write_lock is '0' + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE1 + secure control rule1. it can be set when check_reg's write_lock is '0' + 4 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE2 + secure control rule2. it can be set when check_reg's write_lock is '0' + 8 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE3 + secure control rule3. it can be set when check_reg's write_lock is '0' + 12 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_APB_BRIDGE_SLAVE_RULE + Security access rules for both APB Bridges slaves. + 0xF0 + 32 + read-write + 0 + 0xFFFFFFFF + + + APBBRIDGE0_RULE + Security access rules for the whole APB Bridge 0 + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + APBBRIDGE1_RULE + Security access rules for the whole APB Bridge 1 + 4 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_APB_BRIDGE0_MEM_CTRL0 + Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + SYSCON_RULE + System Configuration + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + IOCON_RULE + I/O Configuration + 4 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + GINT0_RULE + GPIO input Interrupt 0 + 8 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + GINT1_RULE + GPIO input Interrupt 1 + 12 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + PINT_RULE + Pin Interrupt and Pattern match + 16 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + SEC_PINT_RULE + Secure Pin Interrupt and Pattern match + 20 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + PMUX_RULE + Peripherals mux + 24 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_APB_BRIDGE0_MEM_CTRL1 + Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. + 0x104 + 32 + read-write + 0 + 0xFFFFFFFF + + + CTIMER0_RULE + Standard counter/Timer 0 + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + CTIMER1_RULE + Standard counter/Timer 1 + 4 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + WWDT_RULE + Windiwed wtachdog Timer + 16 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + MRT_RULE + Multi-rate Timer + 20 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + UTICK_RULE + Micro-Timer + 24 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_APB_BRIDGE0_MEM_CTRL2 + Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. + 0x108 + 32 + read-write + 0 + 0xFFFFFFFF + + + ANACTRL_RULE + Analog Modules controller + 12 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + EFUSE_RULE + eFUSE (One Time Programmable) memory controller + 20 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_APB_BRIDGE0_MEM_CTRL3 + Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. + 0x10C + 32 + write-only + 0 + 0xFFFFFFFF + + + SEC_CTRL_APB_BRIDGE1_MEM_CTRL0 + Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. + 0x110 + 32 + read-write + 0 + 0xFFFFFFFF + + + PMC_RULE + Power Management Controller + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + SYSCTRL_RULE + System Controller + 12 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_APB_BRIDGE1_MEM_CTRL1 + Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. + 0x114 + 32 + read-write + 0 + 0xFFFFFFFF + + + CTIMER2_RULE + Standard counter/Timer 2 + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + CTIMER3_RULE + Standard counter/Timer 3 + 4 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + CTIMER4_RULE + Standard counter/Timer 4 + 8 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RTC_RULE + Real Time Counter + 16 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + OSEVENT_RULE + OS Event Timer + 20 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_APB_BRIDGE1_MEM_CTRL2 + Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. + 0x118 + 32 + read-write + 0 + 0xFFFFFFFF + + + FLASH_CTRL_RULE + Flash Controller + 16 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + PRINCE_RULE + Prince + 20 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_APB_BRIDGE1_MEM_CTRL3 + Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. + 0x11C + 32 + read-write + 0 + 0xFFFFFFFF + + + USBHPHY_RULE + USB High Speed Phy controller + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RNG_RULE + True Random Number Generator + 8 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + PUFF_RULE + PUF + 12 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + PLU_RULE + Programmable Look-Up logic + 20 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_AHB0_0_SLAVE_RULE + Security access rules for AHB peripherals. + 0x120 + 32 + read-write + 0 + 0xFFFFFFFF + + + DMA0_RULE + DMA Controller + 8 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + FS_USB_DEV_RULE + USB Full-speed device + 16 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + SCT_RULE + SCTimer + 20 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + FLEXCOMM0_RULE + Flexcomm interface 0 + 24 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + FLEXCOMM1_RULE + Flexcomm interface 1 + 28 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_AHB0_1_SLAVE_RULE + Security access rules for AHB peripherals. + 0x124 + 32 + read-write + 0 + 0xFFFFFFFF + + + FLEXCOMM2_RULE + Flexcomm interface 2 + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + FLEXCOMM3_RULE + Flexcomm interface 3 + 4 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + FLEXCOMM4_RULE + Flexcomm interface 4 + 8 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + MAILBOX_RULE + Inter CPU communication Mailbox + 12 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + GPIO0_RULE + High Speed GPIO + 16 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_AHB1_0_SLAVE_RULE + Security access rules for AHB peripherals. + 0x130 + 32 + read-write + 0 + 0xFFFFFFFF + + + USB_HS_DEV_RULE + USB high Speed device registers + 16 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + CRC_RULE + CRC engine + 20 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + FLEXCOMM5_RULE + Flexcomm interface 5 + 24 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + FLEXCOMM6_RULE + Flexcomm interface 6 + 28 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_AHB1_1_SLAVE_RULE + Security access rules for AHB peripherals. + 0x134 + 32 + read-write + 0 + 0xFFFFFFFF + + + FLEXCOMM7_RULE + Flexcomm interface 7 + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + SDIO_RULE + SDMMC card interface + 12 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + DBG_MAILBOX_RULE + Debug mailbox (aka ISP-AP) + 16 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + HS_LSPI_RULE + High Speed SPI + 28 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_AHB2_0_SLAVE_RULE + Security access rules for AHB peripherals. + 0x140 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADC_RULE + ADC + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + USB_FS_HOST_RULE + USB Full Speed Host registers. + 8 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + USB_HS_HOST_RULE + USB High speed host registers + 12 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + HASH_RULE + SHA-2 crypto registers + 16 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + CASPER_RULE + RSA/ECC crypto accelerator + 20 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + PQ_RULE + Power Quad (CM33 processor hardware accelerator) + 24 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + DMA1_RULE + DMA Controller (Secure) + 28 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_AHB2_1_SLAVE_RULE + Security access rules for AHB peripherals. + 0x144 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPIO1_RULE + Secure High Speed GPIO + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + AHB_SEC_CTRL_RULE + AHB Secure Controller + 4 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_AHB2_0_MEM_RULE + Security access rules for AHB_SEC_CTRL_AHB. + 0x150 + 32 + read-write + 0 + 0xFFFFFFFF + + + AHB_SEC_CTRL_SECT_0_RULE + Address space: 0x400A_0000 - 0x400A_CFFF + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + AHB_SEC_CTRL_SECT_1_RULE + Address space: 0x400A_D000 - 0x400A_DFFF + 4 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + AHB_SEC_CTRL_SECT_2_RULE + Address space: 0x400A_E000 - 0x400A_EFFF + 8 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + AHB_SEC_CTRL_SECT_3_RULE + Address space: 0x400A_F000 - 0x400A_FFFF + 12 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_USB_HS_SLAVE_RULE + Security access rules for USB High speed RAM slaves. + 0x160 + 32 + read-write + 0 + 0xFFFFFFFF + + + RAM_USB_HS_RULE + Security access rules for the whole USB High Speed RAM : 0x4010_0000 - 0x4010_3FFF + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_USB_HS_MEM_RULE + Security access rules for RAM_USB_HS. + 0x170 + 32 + read-write + 0 + 0xFFFFFFFF + + + SRAM_SECT_0_RULE + Address space: 0x4010_0000 - 0x4010_0FFF + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + SRAM_SECT_1_RULE + Address space: 0x4010_1000 - 0x4010_1FFF + 4 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + SRAM_SECT_2_RULE + Address space: 0x4010_2000 - 0x4010_2FFF + 8 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + SRAM_SECT_3_RULE + Address space: 0x4010_3000 - 0x4010_3FFF + 12 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + 12 + 0x4 + sec_vio_addr[%s] + most recent security violation address for AHB layer n + 0xE00 + 32 + read-only + 0 + 0xFFFFFFFF + + + SEC_VIO_ADDR + security violation address for AHB layer + 0 + 32 + read-only + + + + + 12 + 0x4 + sec_vio_misc_info[%s] + most recent security violation miscellaneous information for AHB layer n + 0xE80 + 32 + read-only + 0 + 0xFF3 + + + SEC_VIO_INFO_WRITE + security violation access read/write indicator. + 0 + 1 + read-only + + + READ + Read access. + 0 + + + WRITE + Write access. + 0x1 + + + + + SEC_VIO_INFO_DATA_ACCESS + security violation access data/code indicator. + 1 + 1 + read-only + + + CODE + Code access. + 0 + + + DATA + Data access. + 0x1 + + + + + SEC_VIO_INFO_MASTER_SEC_LEVEL + bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and privilege level + 4 + 4 + read-only + + + SEC_VIO_INFO_MASTER + security violation master number + 8 + 4 + read-only + + + VALUE_0 + CPU0 Code. + 0 + + + VALUE_1 + CPU0 System. + 0x1 + + + VALUE_2 + CPU1 Data. + 0x2 + + + VALUE_3 + CPU1 System. + 0x3 + + + VALUE_4 + USB-HS Device. + 0x4 + + + VALUE_5 + SDMA0. + 0x5 + + + VALUE_8 + SDIO. + 0x8 + + + VALUE_9 + PowerQuad. + 0x9 + + + VALUE_10 + HASH. + 0xA + + + VALUE_11 + USB-FS Host. + 0xB + + + VALUE_12 + SDMA1. + 0xC + + + + + + + SEC_VIO_INFO_VALID + security violation address/information registers valid flags + 0xF00 + 32 + read-write + 0 + 0x3FFFF + + + VIO_INFO_VALID0 + violation information valid flag for AHB layer 0. Write 1 to clear. + 0 + 1 + read-write + + + NOT_VALID + Not valid. + 0 + + + VALID + Valid (violation occurred). + 0x1 + + + + + VIO_INFO_VALID1 + violation information valid flag for AHB layer 1. Write 1 to clear. + 1 + 1 + read-write + + + NOT_VALID + Not valid. + 0 + + + VALID + Valid (violation occurred). + 0x1 + + + + + VIO_INFO_VALID2 + violation information valid flag for AHB layer 2. Write 1 to clear. + 2 + 1 + read-write + + + NOT_VALID + Not valid. + 0 + + + VALID + Valid (violation occurred). + 0x1 + + + + + VIO_INFO_VALID3 + violation information valid flag for AHB layer 3. Write 1 to clear. + 3 + 1 + read-write + + + NOT_VALID + Not valid. + 0 + + + VALID + Valid (violation occurred). + 0x1 + + + + + VIO_INFO_VALID4 + violation information valid flag for AHB layer 4. Write 1 to clear. + 4 + 1 + read-write + + + NOT_VALID + Not valid. + 0 + + + VALID + Valid (violation occurred). + 0x1 + + + + + VIO_INFO_VALID5 + violation information valid flag for AHB layer 5. Write 1 to clear. + 5 + 1 + read-write + + + NOT_VALID + Not valid. + 0 + + + VALID + Valid (violation occurred). + 0x1 + + + + + VIO_INFO_VALID6 + violation information valid flag for AHB layer 6. Write 1 to clear. + 6 + 1 + read-write + + + NOT_VALID + Not valid. + 0 + + + VALID + Valid (violation occurred). + 0x1 + + + + + VIO_INFO_VALID7 + violation information valid flag for AHB layer 7. Write 1 to clear. + 7 + 1 + read-write + + + NOT_VALID + Not valid. + 0 + + + VALID + Valid (violation occurred). + 0x1 + + + + + VIO_INFO_VALID8 + violation information valid flag for AHB layer 8. Write 1 to clear. + 8 + 1 + read-write + + + NOT_VALID + Not valid. + 0 + + + VALID + Valid (violation occurred). + 0x1 + + + + + VIO_INFO_VALID9 + violation information valid flag for AHB layer 9. Write 1 to clear. + 9 + 1 + read-write + + + NOT_VALID + Not valid. + 0 + + + VALID + Valid (violation occurred). + 0x1 + + + + + VIO_INFO_VALID10 + violation information valid flag for AHB layer 10. Write 1 to clear. + 10 + 1 + read-write + + + NOT_VALID + Not valid. + 0 + + + VALID + Valid (violation occurred). + 0x1 + + + + + VIO_INFO_VALID11 + violation information valid flag for AHB layer 11. Write 1 to clear. + 11 + 1 + read-write + + + NOT_VALID + Not valid. + 0 + + + VALID + Valid (violation occurred). + 0x1 + + + + + + + SEC_GPIO_MASK0 + Secure GPIO mask for port 0 pins. + 0xF80 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + PIO0_PIN0_SEC_MASK + Secure mask for pin P0_0 + 0 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN1_SEC_MASK + Secure mask for pin P0_1 + 1 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN2_SEC_MASK + Secure mask for pin P0_2 + 2 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN3_SEC_MASK + Secure mask for pin P0_3 + 3 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN4_SEC_MASK + Secure mask for pin P0_4 + 4 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN5_SEC_MASK + Secure mask for pin P0_5 + 5 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN6_SEC_MASK + Secure mask for pin P0_6 + 6 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN7_SEC_MASK + Secure mask for pin P0_7 + 7 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN8_SEC_MASK + Secure mask for pin P0_8 + 8 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN9_SEC_MASK + Secure mask for pin P0_9 + 9 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN10_SEC_MASK + Secure mask for pin P0_10 + 10 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN11_SEC_MASK + Secure mask for pin P0_11 + 11 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN12_SEC_MASK + Secure mask for pin P0_12 + 12 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN13_SEC_MASK + Secure mask for pin P0_13 + 13 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN14_SEC_MASK + Secure mask for pin P0_14 + 14 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN15_SEC_MASK + Secure mask for pin P0_15 + 15 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN16_SEC_MASK + Secure mask for pin P0_16 + 16 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN17_SEC_MASK + Secure mask for pin P0_17 + 17 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN18_SEC_MASK + Secure mask for pin P0_18 + 18 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN19_SEC_MASK + Secure mask for pin P0_19 + 19 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN20_SEC_MASK + Secure mask for pin P0_20 + 20 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN21_SEC_MASK + Secure mask for pin P0_21 + 21 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN22_SEC_MASK + Secure mask for pin P0_22 + 22 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN23_SEC_MASK + Secure mask for pin P0_23 + 23 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN24_SEC_MASK + Secure mask for pin P0_24 + 24 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN25_SEC_MASK + Secure mask for pin P0_25 + 25 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN26_SEC_MASK + Secure mask for pin P0_26 + 26 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN27_SEC_MASK + Secure mask for pin P0_27 + 27 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN28_SEC_MASK + Secure mask for pin P0_28 + 28 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN29_SEC_MASK + Secure mask for pin P0_29 + 29 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN30_SEC_MASK + Secure mask for pin P0_30 + 30 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN31_SEC_MASK + Secure mask for pin P0_31 + 31 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + + + SEC_GPIO_MASK1 + Secure GPIO mask for port 1 pins. + 0xF84 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + PIO1_PIN0_SEC_MASK + Secure mask for pin P1_0 + 0 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN1_SEC_MASK + Secure mask for pin P1_1 + 1 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN2_SEC_MASK + Secure mask for pin P1_2 + 2 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN3_SEC_MASK + Secure mask for pin P1_3 + 3 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN4_SEC_MASK + Secure mask for pin P1_4 + 4 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN5_SEC_MASK + Secure mask for pin P1_5 + 5 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN6_SEC_MASK + Secure mask for pin P1_6 + 6 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN7_SEC_MASK + Secure mask for pin P1_7 + 7 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN8_SEC_MASK + Secure mask for pin P1_8 + 8 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN9_SEC_MASK + Secure mask for pin P1_9 + 9 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN10_SEC_MASK + Secure mask for pin P1_10 + 10 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN11_SEC_MASK + Secure mask for pin P1_11 + 11 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN12_SEC_MASK + Secure mask for pin P1_12 + 12 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN13_SEC_MASK + Secure mask for pin P1_13 + 13 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN14_SEC_MASK + Secure mask for pin P1_14 + 14 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN15_SEC_MASK + Secure mask for pin P1_15 + 15 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN16_SEC_MASK + Secure mask for pin P1_16 + 16 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN17_SEC_MASK + Secure mask for pin P1_17 + 17 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN18_SEC_MASK + Secure mask for pin P1_18 + 18 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN19_SEC_MASK + Secure mask for pin P1_19 + 19 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN20_SEC_MASK + Secure mask for pin P1_20 + 20 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN21_SEC_MASK + Secure mask for pin P1_21 + 21 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN22_SEC_MASK + Secure mask for pin P1_22 + 22 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN23_SEC_MASK + Secure mask for pin P1_23 + 23 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN24_SEC_MASK + Secure mask for pin P1_24 + 24 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN25_SEC_MASK + Secure mask for pin P1_25 + 25 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN26_SEC_MASK + Secure mask for pin P1_26 + 26 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN27_SEC_MASK + Secure mask for pin P1_27 + 27 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN28_SEC_MASK + Secure mask for pin P1_28 + 28 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN29_SEC_MASK + Secure mask for pin P1_29 + 29 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN30_SEC_MASK + Secure mask for pin P1_30 + 30 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN31_SEC_MASK + Secure mask for pin P1_31 + 31 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + + + SEC_CPU_INT_MASK0 + Secure Interrupt mask for CPU1 + 0xF90 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + SYS_IRQ + Watchdog Timer, Brown Out Detectors and Flash Controller interrupts + 0 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + SDMA0_IRQ + System DMA 0 (non-secure) interrupt. + 1 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + GPIO_GLOBALINT0_IRQ + GPIO Group 0 interrupt. + 2 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + GPIO_GLOBALINT1_IRQ + GPIO Group 1 interrupt. + 3 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + GPIO_INT0_IRQ0 + Pin interrupt 0 or pattern match engine slice 0 interrupt. + 4 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + GPIO_INT0_IRQ1 + Pin interrupt 1 or pattern match engine slice 1 interrupt. + 5 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + GPIO_INT0_IRQ2 + Pin interrupt 2 or pattern match engine slice 2 interrupt. + 6 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + GPIO_INT0_IRQ3 + Pin interrupt 3 or pattern match engine slice 3 interrupt. + 7 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + UTICK_IRQ + Micro Tick Timer interrupt. + 8 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + MRT_IRQ + Multi-Rate Timer interrupt. + 9 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + CTIMER0_IRQ + Standard counter/timer 0 interrupt. + 10 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + CTIMER1_IRQ + Standard counter/timer 1 interrupt. + 11 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + SCT_IRQ + SCTimer/PWM interrupt. + 12 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + CTIMER3_IRQ + Standard counter/timer 3 interrupt. + 13 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + FLEXCOMM0_IRQ + Flexcomm 0 interrupt (USART, SPI, I2C, I2S). + 14 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + FLEXCOMM1_IRQ + Flexcomm 1 interrupt (USART, SPI, I2C, I2S). + 15 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + FLEXCOMM2_IRQ + Flexcomm 2 interrupt (USART, SPI, I2C, I2S). + 16 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + FLEXCOMM3_IRQ + Flexcomm 3 interrupt (USART, SPI, I2C, I2S). + 17 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + FLEXCOMM4_IRQ + Flexcomm 4 interrupt (USART, SPI, I2C, I2S). + 18 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + FLEXCOMM5_IRQ + Flexcomm 5 interrupt (USART, SPI, I2C, I2S). + 19 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + FLEXCOMM6_IRQ + Flexcomm 6 interrupt (USART, SPI, I2C, I2S). + 20 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + FLEXCOMM7_IRQ + Flexcomm 7 interrupt (USART, SPI, I2C, I2S). + 21 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + ADC_IRQ + General Purpose ADC interrupt. + 22 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + RESERVED0 + Reserved. Read value is undefined, only zero should be written. + 23 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + ACMP_CAPT0_IRQ + Analog Comparator interrupt. + 24 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + RESERVED1 + Reserved. Read value is undefined, only zero should be written. + 25 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + RESERVED2 + Reserved. Read value is undefined, only zero should be written. + 26 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + USB0_NEEDCLK + USB Full Speed Controller Clock request interrupt. + 27 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + USB0_IRQ + USB High Speed Controller interrupt. + 28 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + RTC_IRQ + RTC_LITE0_ALARM_IRQ, RTC_LITE0_WAKEUP_IRQ + 29 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + RESERVED3 + Reserved. Read value is undefined, only zero should be written. + 30 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + MAILBOX_IRQ + Mailbox interrupt. + 31 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + + + SEC_CPU_INT_MASK1 + Secure Interrupt mask for CPU1 + 0xF94 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + GPIO_INT0_IRQ4 + Pin interrupt 4 or pattern match engine slice 4 interrupt. + 0 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + GPIO_INT0_IRQ5 + Pin interrupt 5 or pattern match engine slice 5 interrupt. + 1 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + GPIO_INT0_IRQ6 + Pin interrupt 6 or pattern match engine slice 6 interrupt. + 2 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + GPIO_INT0_IRQ7 + Pin interrupt 7 or pattern match engine slice 7 interrupt. + 3 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + CTIMER2_IRQ + Standard counter/timer 2 interrupt. + 4 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + CTIMER4_IRQ + Standard counter/timer 4 interrupt. + 5 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + OS_EVENT_TIMER_IRQ + OS Event Timer and OS Event Timer Wakeup interrupts + 6 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + RESERVED0 + Reserved. Read value is undefined, only zero should be written. + 7 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + RESERVED1 + Reserved. Read value is undefined, only zero should be written. + 8 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + RESERVED2 + Reserved. Read value is undefined, only zero should be written. + 9 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + SDIO_IRQ + SDIO Controller interrupt. + 10 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + RESERVED3 + Reserved. Read value is undefined, only zero should be written. + 11 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + RESERVED4 + Reserved. Read value is undefined, only zero should be written. + 12 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + RESERVED5 + Reserved. Read value is undefined, only zero should be written. + 13 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + USB1_UTMI_IRQ + USB High Speed Controller UTMI interrupt. + 14 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + USB1_IRQ + USB High Speed Controller interrupt. + 15 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + USB1_NEEDCLK + USB High Speed Controller Clock request interrupt. + 16 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + SEC_HYPERVISOR_CALL_IRQ + Secure fault Hyper Visor call interrupt. + 17 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + SEC_GPIO_INT0_IRQ0 + Secure Pin interrupt 0 or pattern match engine slice 0 interrupt. + 18 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + SEC_GPIO_INT0_IRQ1 + Secure Pin interrupt 1 or pattern match engine slice 1 interrupt. + 19 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + PLU_IRQ + Programmable Look-Up Controller interrupt. + 20 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + SEC_VIO_IRQ + Security Violation interrupt. + 21 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + SHA_IRQ + HASH-AES interrupt. + 22 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + CASPER_IRQ + CASPER interrupt. + 23 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + QDDKEY_IRQ + PUF interrupt. + 24 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + PQ_IRQ + Power Quad interrupt. + 25 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + SDMA1_IRQ + System DMA 1 (Secure) interrupt + 26 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + LSPI_HS_IRQ + High Speed SPI interrupt + 27 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + + + SEC_MASK_LOCK + Security General Purpose register access control. + 0xFBC + 32 + read-write + 0xAAA + 0xFFF + + + SEC_GPIO_MASK0_LOCK + SEC_GPIO_MASK0 register write-lock. + 0 + 2 + read-write + + + BLOCKED + Restricted mode. + 0x1 + + + WRITABLE + Writable. + 0x2 + + + + + SEC_GPIO_MASK1_LOCK + SEC_GPIO_MASK1 register write-lock. + 2 + 2 + read-write + + + BLOCKED + Restricted mode. + 0x1 + + + WRITABLE + Writable. + 0x2 + + + + + SEC_CPU1_INT_MASK0_LOCK + SEC_CPU_INT_MASK0 register write-lock. + 8 + 2 + read-write + + + BLOCKED + Restricted mode. + 0x1 + + + WRITABLE + Writable. + 0x2 + + + + + SEC_CPU1_INT_MASK1_LOCK + SEC_CPU_INT_MASK1 register write-lock. + 10 + 2 + read-write + + + BLOCKED + Restricted mode. + 0x1 + + + WRITABLE + Writable. + 0x2 + + + + + + + MASTER_SEC_LEVEL + master secure level register + 0xFD0 + 32 + read-write + 0x80000000 + 0xFFFFFFFF + + + MCM33C + Micro-CM33 (CPU1) Code bus. + 4 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + MCM33S + Micro-CM33 (CPU1) System bus. + 6 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + USBFSD + USB Full Speed Device. + 8 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + SDMA0 + System DMA 0. + 10 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + SDIO + SDIO. + 16 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + PQ + Power Quad. + 18 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + HASH + Hash. + 20 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + USBFSH + USB Full speed Host. + 22 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + SDMA1 + System DMA 1 security level. + 24 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + MASTER_SEC_LEVEL_LOCK + MASTER_SEC_LEVEL write-lock. + 30 + 2 + read-write + + + BLOCKED + Restricted mode. + 0x1 + + + WRITABLE + Writable. + 0x2 + + + + + + + MASTER_SEC_ANTI_POL_REG + master secure level anti-pole register + 0xFD4 + 32 + read-write + 0xBFFFFFFF + 0xFFFFFFFF + + + MCM33C + Micro-CM33 (CPU1) Code bus. Must be equal to NOT(MASTER_SEC_LEVEL.MCM33C) + 4 + 2 + read-write + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x1 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x2 + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0x3 + + + + + MCM33S + Micro-CM33 (CPU1) System bus. Must be equal to NOT(MASTER_SEC_LEVEL.MCM33S) + 6 + 2 + read-write + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x1 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x2 + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0x3 + + + + + USBFSD + USB Full Speed Device. Must be equal to NOT(MASTER_SEC_LEVEL.USBFSD) + 8 + 2 + read-write + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x1 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x2 + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0x3 + + + + + SDMA0 + System DMA 0. Must be equal to NOT(MASTER_SEC_LEVEL.SDMA0) + 10 + 2 + read-write + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x1 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x2 + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0x3 + + + + + SDIO + SDIO. Must be equal to NOT(MASTER_SEC_LEVEL.SDIO) + 16 + 2 + read-write + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x1 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x2 + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0x3 + + + + + PQ + Power Quad. Must be equal to NOT(MASTER_SEC_LEVEL.PQ) + 18 + 2 + read-write + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x1 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x2 + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0x3 + + + + + HASH + Hash. Must be equal to NOT(MASTER_SEC_LEVEL.HASH) + 20 + 2 + read-write + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x1 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x2 + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0x3 + + + + + USBFSH + USB Full speed Host. Must be equal to NOT(MASTER_SEC_LEVEL.USBFSH) + 22 + 2 + read-write + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x1 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x2 + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0x3 + + + + + SDMA1 + System DMA 1 security level. Must be equal to NOT(MASTER_SEC_LEVEL.SDMA1) + 24 + 2 + read-write + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x1 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x2 + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0x3 + + + + + MASTER_SEC_LEVEL_ANTIPOL_LOCK + MASTER_SEC_ANTI_POL_REG register write-lock. + 30 + 2 + read-write + + + BLOCKED + Restricted mode. + 0x1 + + + WRITABLE + Writable. + 0x2 + + + + + + + CM33_LOCK_REG + Miscalleneous control signals for in CM33 (CPU0) + 0xFEC + 32 + read-write + 0x800002AA + 0xC00003FF + + + LOCK_NS_VTOR + CM33 (CPU0) VTOR_NS register write-lock. + 0 + 2 + read-write + + + BLOCKED + Restricted mode. + 0x1 + + + WRITABLE + Writable. + 0x2 + + + + + LOCK_NS_MPU + CM33 (CPU0) non-secure MPU register write-lock. + 2 + 2 + read-write + + + BLOCKED + Restricted mode. + 0x1 + + + WRITABLE + Writable. + 0x2 + + + + + LOCK_S_VTAIRCR + CM33 (CPU0) VTOR_S, AIRCR.PRIS, IRCR.BFHFNMINS registers write-lock. + 4 + 2 + read-write + + + BLOCKED + Restricted mode. + 0x1 + + + WRITABLE + Writable. + 0x2 + + + + + LOCK_S_MPU + CM33 (CPU0) Secure MPU registers write-lock. + 6 + 2 + read-write + + + BLOCKED + Restricted mode. + 0x1 + + + WRITABLE + Writable. + 0x2 + + + + + LOCK_SAU + CM33 (CPU0) SAU registers write-lock. + 8 + 2 + read-write + + + BLOCKED + Restricted mode. + 0x1 + + + WRITABLE + Writable. + 0x2 + + + + + CM33_LOCK_REG_LOCK + CM33_LOCK_REG write-lock. + 30 + 2 + read-write + + + BLOCKED + Restricted mode. + 0x1 + + + WRITABLE + Writable. + 0x2 + + + + + + + MCM33_LOCK_REG + Miscalleneous control signals for in micro-CM33 (CPU1) + 0xFF0 + 32 + read-write + 0x8000000A + 0xC000000F + + + LOCK_NS_VTOR + micro-CM33 (CPU1) VTOR_NS register write-lock. + 0 + 2 + read-write + + + BLOCKED + Restricted mode. + 0x1 + + + WRITABLE + Writable. + 0x2 + + + + + LOCK_NS_MPU + micro-CM33 (CPU1) non-secure MPU register write-lock. + 2 + 2 + read-write + + + BLOCKED + Restricted mode. + 0x1 + + + WRITABLE + Writable. + 0x2 + + + + + MCM33_LOCK_REG_LOCK + MCM33_LOCK_REG write-lock. + 30 + 2 + read-write + + + BLOCKED + Restricted mode. + 0x1 + + + WRITABLE + Writable. + 0x2 + + + + + + + MISC_CTRL_DP_REG + secure control duplicate register + 0xFF8 + 32 + read-write + 0xAAAA + 0xFFFF + + + WRITE_LOCK + write lock. + 0 + 2 + read-write + + + RESTRICTED + Restricted mode. + 0x1 + + + ACCESSIBLE + Secure control registers can be written. + 0x2 + + + + + ENABLE_SECURE_CHECKING + AHB bus matrix enable secure check. + 2 + 2 + read-write + + + ENABLE + Restricted mode. + 0x1 + + + DISABLE + Disable check. + 0x2 + + + + + ENABLE_S_PRIV_CHECK + AHB bus matrix enable secure privilege check. + 4 + 2 + read-write + + + ENABLE + Restricted mode. + 0x1 + + + DISABLE + Disable check. + 0x2 + + + + + ENABLE_NS_PRIV_CHECK + AHB bus matrix enable non-secure privilege check. + 6 + 2 + read-write + + + ENABLE + Restricted mode. + 0x1 + + + DISABLE + Disable check. + 0x2 + + + + + DISABLE_VIOLATION_ABORT + Disable secure violation abort. + 8 + 2 + read-write + + + DISABLE + Disable abort fort secure checker. + 0x1 + + + ENABLE + Enable abort fort secure checker. + 0x2 + + + + + DISABLE_SIMPLE_MASTER_STRICT_MODE + Disable simple master strict mode. + 10 + 2 + read-write + + + TIER_MODE + Simple master in tier mode. + 0x1 + + + STRICT_MODE + Simple master in strict mode. + 0x2 + + + + + DISABLE_SMART_MASTER_STRICT_MODE + Disable smart master strict mode. + 12 + 2 + read-write + + + TIER_MODE + Smart master in tier mode. + 0x1 + + + STRICT_MODE + Smart master in strict mode. + 0x2 + + + + + IDAU_ALL_NS + Disable IDAU. + 14 + 2 + read-write + + + DISABLE + IDAU is disable. + 0x1 + + + ENABLE + IDAU is enabled. + 0x2 + + + + + + + MISC_CTRL_REG + secure control register + 0xFFC + 32 + read-write + 0xAAAA + 0xFFFF + + + WRITE_LOCK + write lock. + 0 + 2 + read-write + + + RESTRICTED + Restricted mode. + 0x1 + + + ACCESSIBLE + Secure control registers can be written. + 0x2 + + + + + ENABLE_SECURE_CHECKING + AHB bus matrix enable secure check. + 2 + 2 + read-write + + + ENABLE + Restricted mode. + 0x1 + + + DISABLE + Disable check. + 0x2 + + + + + ENABLE_S_PRIV_CHECK + AHB bus matrix enable secure privilege check. + 4 + 2 + read-write + + + ENABLE + Restricted mode. + 0x1 + + + DISABLE + Disable check. + 0x2 + + + + + ENABLE_NS_PRIV_CHECK + AHB bus matrix enable non-secure privilege check. + 6 + 2 + read-write + + + ENABLE + Restricted mode. + 0x1 + + + DISABLE + Disable check. + 0x2 + + + + + DISABLE_VIOLATION_ABORT + Disable secure violation abort. + 8 + 2 + read-write + + + DISABLE + Disable abort fort secure checker. + 0x1 + + + ENABLE + Enable abort fort secure checker. + 0x2 + + + + + DISABLE_SIMPLE_MASTER_STRICT_MODE + Disable simple master strict mode. + 10 + 2 + read-write + + + TIER_MODE + Simple master in tier mode. + 0x1 + + + STRICT_MODE + Simple master in strict mode. + 0x2 + + + + + DISABLE_SMART_MASTER_STRICT_MODE + Disable smart master strict mode. + 12 + 2 + read-write + + + TIER_MODE + Smart master in tier mode. + 0x1 + + + STRICT_MODE + Smart master in strict mode. + 0x2 + + + + + IDAU_ALL_NS + Disable IDAU. + 14 + 2 + read-write + + + DISABLE + IDAU is disable. + 0x1 + + + ENABLE + IDAU is enabled. + 0x2 + + + + + + + + + SCnSCB + no description available + SCNSCB + 0xE000E000 + + 0 + 0x10 + registers + + + + CPPWR + Coprocessor Power Control Register + 0xC + 32 + read-write + 0 + 0 + + + SU0 + State UNKNOWN 0. + 0 + 1 + read-write + + + UNKNOWN_NOT_PERMITTED + The coprocessor state is not permitted to become UNKNOWN. + 0 + + + UNKNOWN_PERMITTED + The coprocessor state is permitted to become UNKNOWN. + 0x1 + + + + + SUS0 + State UNKNOWN Secure only 0. + 1 + 1 + read-write + + + SECURE_AND_NON_SECURE + The SU0 field is accessible from both Security states. + 0 + + + SECURE_ONLY + The SU0 field is only accessible from the Secure state. + 0x1 + + + + + SU1 + State UNKNOWN 1. + 2 + 1 + read-write + + + UNKNOWN_NOT_PERMITTED + The coprocessor state is not permitted to become UNKNOWN. + 0 + + + UNKNOWN_PERMITTED + The coprocessor state is permitted to become UNKNOWN. + 0x1 + + + + + SUS1 + State UNKNOWN Secure only 1. + 3 + 1 + read-write + + + SECURE_AND_NON_SECURE + The SU7 field is accessible from both Security states. + 0 + + + SECURE_ONLY + The SU7 field is only accessible from the Secure state. + 0x1 + + + + + SU2 + State UNKNOWN 2. + 4 + 1 + read-write + + + UNKNOWN_NOT_PERMITTED + The coprocessor state is not permitted to become UNKNOWN. + 0 + + + UNKNOWN_PERMITTED + The coprocessor state is permitted to become UNKNOWN. + 0x1 + + + + + SUS2 + State UNKNOWN Secure only 2. + 5 + 1 + read-write + + + SECURE_AND_NON_SECURE + The SU2 field is accessible from both Security states. + 0 + + + SECURE_ONLY + The SU2 field is only accessible from the Secure state. + 0x1 + + + + + SU3 + State UNKNOWN 3. + 6 + 1 + read-write + + + UNKNOWN_NOT_PERMITTED + The coprocessor state is not permitted to become UNKNOWN. + 0 + + + UNKNOWN_PERMITTED + The coprocessor state is permitted to become UNKNOWN. + 0x1 + + + + + SUS3 + State UNKNOWN Secure only 3. + 7 + 1 + read-write + + + SECURE_AND_NON_SECURE + The SU3 field is accessible from both Security states. + 0 + + + SECURE_ONLY + The SU3 field is only accessible from the Secure state. + 0x1 + + + + + SU4 + State UNKNOWN 4. + 8 + 1 + read-write + + + UNKNOWN_NOT_PERMITTED + The coprocessor state is not permitted to become UNKNOWN. + 0 + + + UNKNOWN_PERMITTED + The coprocessor state is permitted to become UNKNOWN. + 0x1 + + + + + SUS4 + State UNKNOWN Secure only 4. + 9 + 1 + read-write + + + SECURE_AND_NON_SECURE + The SU4 field is accessible from both Security states. + 0 + + + SECURE_ONLY + The SU4 field is only accessible from the Secure state. + 0x1 + + + + + SU5 + State UNKNOWN 5. + 10 + 1 + read-write + + + UNKNOWN_NOT_PERMITTED + The coprocessor state is not permitted to become UNKNOWN. + 0 + + + UNKNOWN_PERMITTED + The coprocessor state is permitted to become UNKNOWN. + 0x1 + + + + + SUS5 + State UNKNOWN Secure only 5. + 11 + 1 + read-write + + + SECURE_AND_NON_SECURE + The SU5 field is accessible from both Security states. + 0 + + + SECURE_ONLY + The SU5 field is only accessible from the Secure state. + 0x1 + + + + + SU6 + State UNKNOWN 6. + 12 + 1 + read-write + + + UNKNOWN_NOT_PERMITTED + The coprocessor state is not permitted to become UNKNOWN. + 0 + + + UNKNOWN_PERMITTED + The coprocessor state is permitted to become UNKNOWN. + 0x1 + + + + + SUS6 + State UNKNOWN Secure only 6. + 13 + 1 + read-write + + + SECURE_AND_NON_SECURE + The SU6 field is accessible from both Security states. + 0 + + + SECURE_ONLY + The SU6 field is only accessible from the Secure state. + 0x1 + + + + + SU7 + State UNKNOWN 7. + 14 + 1 + read-write + + + UNKNOWN_NOT_PERMITTED + The coprocessor state is not permitted to become UNKNOWN. + 0 + + + UNKNOWN_PERMITTED + The coprocessor state is permitted to become UNKNOWN. + 0x1 + + + + + SUS7 + State UNKNOWN Secure only 7. + 15 + 1 + read-write + + + SECURE_AND_NON_SECURE + The SU7 field is accessible from both Security states. + 0 + + + SECURE_ONLY + The SU7 field is only accessible from the Secure state. + 0x1 + + + + + SU10 + State UNKNOWN 10. + 20 + 1 + read-write + + + UNKNOWN_NOT_PERMITTED + The floating-point state is not permitted to become UNKNOWN. + 0 + + + UNKNOWN_PERMITTED + The floating-point state is permitted to become UNKNOWN + 0x1 + + + + + SUS10 + State UNKNOWN Secure only 10. + 21 + 1 + read-write + + + SECURE_AND_NON_SECURE + The SU10 field is accessible from both Security states. + 0 + + + SECURE_ONLY + The SU10 field is only accessible from the Secure state. + 0x1 + + + + + SU11 + State UNKNOWN 11. + 22 + 1 + read-write + + + SUS11 + State UNKNOWN Secure only 11. + 23 + 1 + read-write + + + + + + + NVIC + no description available + NVIC + 0xE000E100 + + 0 + 0xE04 + registers + + + + 16 + 0x4 + ISER[%s] + Interrupt Set Enable Register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + SETENA0 + Interrupt set-enable bits. + 0 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA1 + Interrupt set-enable bits. + 1 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA2 + Interrupt set-enable bits. + 2 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA3 + Interrupt set-enable bits. + 3 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA4 + Interrupt set-enable bits. + 4 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA5 + Interrupt set-enable bits. + 5 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA6 + Interrupt set-enable bits. + 6 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA7 + Interrupt set-enable bits. + 7 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA8 + Interrupt set-enable bits. + 8 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA9 + Interrupt set-enable bits. + 9 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA10 + Interrupt set-enable bits. + 10 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA11 + Interrupt set-enable bits. + 11 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA12 + Interrupt set-enable bits. + 12 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA13 + Interrupt set-enable bits. + 13 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA14 + Interrupt set-enable bits. + 14 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA15 + Interrupt set-enable bits. + 15 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA16 + Interrupt set-enable bits. + 16 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA17 + Interrupt set-enable bits. + 17 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA18 + Interrupt set-enable bits. + 18 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA19 + Interrupt set-enable bits. + 19 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA20 + Interrupt set-enable bits. + 20 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA21 + Interrupt set-enable bits. + 21 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA22 + Interrupt set-enable bits. + 22 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA23 + Interrupt set-enable bits. + 23 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA24 + Interrupt set-enable bits. + 24 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA25 + Interrupt set-enable bits. + 25 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA26 + Interrupt set-enable bits. + 26 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA27 + Interrupt set-enable bits. + 27 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA28 + Interrupt set-enable bits. + 28 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA29 + Interrupt set-enable bits. + 29 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA30 + Interrupt set-enable bits. + 30 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA31 + Interrupt set-enable bits. + 31 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + + + 16 + 0x4 + ICER[%s] + Interrupt Clear Enable Register + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + CLRENA0 + Interrupt clear-enable bits. + 0 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA1 + Interrupt clear-enable bits. + 1 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA2 + Interrupt clear-enable bits. + 2 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA3 + Interrupt clear-enable bits. + 3 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA4 + Interrupt clear-enable bits. + 4 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA5 + Interrupt clear-enable bits. + 5 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA6 + Interrupt clear-enable bits. + 6 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA7 + Interrupt clear-enable bits. + 7 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA8 + Interrupt clear-enable bits. + 8 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA9 + Interrupt clear-enable bits. + 9 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA10 + Interrupt clear-enable bits. + 10 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA11 + Interrupt clear-enable bits. + 11 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA12 + Interrupt clear-enable bits. + 12 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA13 + Interrupt clear-enable bits. + 13 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA14 + Interrupt clear-enable bits. + 14 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA15 + Interrupt clear-enable bits. + 15 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA16 + Interrupt clear-enable bits. + 16 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA17 + Interrupt clear-enable bits. + 17 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA18 + Interrupt clear-enable bits. + 18 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA19 + Interrupt clear-enable bits. + 19 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA20 + Interrupt clear-enable bits. + 20 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA21 + Interrupt clear-enable bits. + 21 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA22 + Interrupt clear-enable bits. + 22 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA23 + Interrupt clear-enable bits. + 23 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA24 + Interrupt clear-enable bits. + 24 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA25 + Interrupt clear-enable bits. + 25 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA26 + Interrupt clear-enable bits. + 26 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA27 + Interrupt clear-enable bits. + 27 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA28 + Interrupt clear-enable bits. + 28 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA29 + Interrupt clear-enable bits. + 29 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA30 + Interrupt clear-enable bits. + 30 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA31 + Interrupt clear-enable bits. + 31 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + + + 16 + 0x4 + ISPR[%s] + Interrupt Set Pending Register + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + SETPEND0 + Interrupt set-pending bits. + 0 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND1 + Interrupt set-pending bits. + 1 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND2 + Interrupt set-pending bits. + 2 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND3 + Interrupt set-pending bits. + 3 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND4 + Interrupt set-pending bits. + 4 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND5 + Interrupt set-pending bits. + 5 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND6 + Interrupt set-pending bits. + 6 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND7 + Interrupt set-pending bits. + 7 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND8 + Interrupt set-pending bits. + 8 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND9 + Interrupt set-pending bits. + 9 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND10 + Interrupt set-pending bits. + 10 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND11 + Interrupt set-pending bits. + 11 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND12 + Interrupt set-pending bits. + 12 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND13 + Interrupt set-pending bits. + 13 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND14 + Interrupt set-pending bits. + 14 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND15 + Interrupt set-pending bits. + 15 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND16 + Interrupt set-pending bits. + 16 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND17 + Interrupt set-pending bits. + 17 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND18 + Interrupt set-pending bits. + 18 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND19 + Interrupt set-pending bits. + 19 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND20 + Interrupt set-pending bits. + 20 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND21 + Interrupt set-pending bits. + 21 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND22 + Interrupt set-pending bits. + 22 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND23 + Interrupt set-pending bits. + 23 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND24 + Interrupt set-pending bits. + 24 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND25 + Interrupt set-pending bits. + 25 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND26 + Interrupt set-pending bits. + 26 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND27 + Interrupt set-pending bits. + 27 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND28 + Interrupt set-pending bits. + 28 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND29 + Interrupt set-pending bits. + 29 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND30 + Interrupt set-pending bits. + 30 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND31 + Interrupt set-pending bits. + 31 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + + + 16 + 0x4 + ICPR[%s] + Interrupt Clear Pending Register + 0x180 + 32 + read-write + 0 + 0xFFFFFFFF + + + CLRPEND0 + Interrupt clear-pending bits. + 0 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND1 + Interrupt clear-pending bits. + 1 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND2 + Interrupt clear-pending bits. + 2 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND3 + Interrupt clear-pending bits. + 3 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND4 + Interrupt clear-pending bits. + 4 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND5 + Interrupt clear-pending bits. + 5 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND6 + Interrupt clear-pending bits. + 6 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND7 + Interrupt clear-pending bits. + 7 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND8 + Interrupt clear-pending bits. + 8 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND9 + Interrupt clear-pending bits. + 9 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND10 + Interrupt clear-pending bits. + 10 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND11 + Interrupt clear-pending bits. + 11 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND12 + Interrupt clear-pending bits. + 12 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND13 + Interrupt clear-pending bits. + 13 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND14 + Interrupt clear-pending bits. + 14 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND15 + Interrupt clear-pending bits. + 15 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND16 + Interrupt clear-pending bits. + 16 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND17 + Interrupt clear-pending bits. + 17 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND18 + Interrupt clear-pending bits. + 18 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND19 + Interrupt clear-pending bits. + 19 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND20 + Interrupt clear-pending bits. + 20 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND21 + Interrupt clear-pending bits. + 21 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND22 + Interrupt clear-pending bits. + 22 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND23 + Interrupt clear-pending bits. + 23 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND24 + Interrupt clear-pending bits. + 24 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND25 + Interrupt clear-pending bits. + 25 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND26 + Interrupt clear-pending bits. + 26 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND27 + Interrupt clear-pending bits. + 27 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND28 + Interrupt clear-pending bits. + 28 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND29 + Interrupt clear-pending bits. + 29 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND30 + Interrupt clear-pending bits. + 30 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND31 + Interrupt clear-pending bits. + 31 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + + + 16 + 0x4 + IABR[%s] + Interrupt Active Bit Register + 0x200 + 32 + read-write + 0 + 0 + + + ACTIVE0 + Active state bits. + 0 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE1 + Active state bits. + 1 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE2 + Active state bits. + 2 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE3 + Active state bits. + 3 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE4 + Active state bits. + 4 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE5 + Active state bits. + 5 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE6 + Active state bits. + 6 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE7 + Active state bits. + 7 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE8 + Active state bits. + 8 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE9 + Active state bits. + 9 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE10 + Active state bits. + 10 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE11 + Active state bits. + 11 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE12 + Active state bits. + 12 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE13 + Active state bits. + 13 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE14 + Active state bits. + 14 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE15 + Active state bits. + 15 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE16 + Active state bits. + 16 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE17 + Active state bits. + 17 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE18 + Active state bits. + 18 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE19 + Active state bits. + 19 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE20 + Active state bits. + 20 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE21 + Active state bits. + 21 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE22 + Active state bits. + 22 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE23 + Active state bits. + 23 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE24 + Active state bits. + 24 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE25 + Active state bits. + 25 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE26 + Active state bits. + 26 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE27 + Active state bits. + 27 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE28 + Active state bits. + 28 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE29 + Active state bits. + 29 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE30 + Active state bits. + 30 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE31 + Active state bits. + 31 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + + + 16 + 0x4 + ITNS[%s] + Interrupt Target Non-secure Register + 0x280 + 32 + read-write + 0 + 0 + + + INTS0 + Interrupt Targets Non-secure bits. + 0 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS1 + Interrupt Targets Non-secure bits. + 1 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS2 + Interrupt Targets Non-secure bits. + 2 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS3 + Interrupt Targets Non-secure bits. + 3 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS4 + Interrupt Targets Non-secure bits. + 4 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS5 + Interrupt Targets Non-secure bits. + 5 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS6 + Interrupt Targets Non-secure bits. + 6 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS7 + Interrupt Targets Non-secure bits. + 7 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS8 + Interrupt Targets Non-secure bits. + 8 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS9 + Interrupt Targets Non-secure bits. + 9 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS10 + Interrupt Targets Non-secure bits. + 10 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS11 + Interrupt Targets Non-secure bits. + 11 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS12 + Interrupt Targets Non-secure bits. + 12 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS13 + Interrupt Targets Non-secure bits. + 13 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS14 + Interrupt Targets Non-secure bits. + 14 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS15 + Interrupt Targets Non-secure bits. + 15 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS16 + Interrupt Targets Non-secure bits. + 16 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS17 + Interrupt Targets Non-secure bits. + 17 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS18 + Interrupt Targets Non-secure bits. + 18 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS19 + Interrupt Targets Non-secure bits. + 19 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS20 + Interrupt Targets Non-secure bits. + 20 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS21 + Interrupt Targets Non-secure bits. + 21 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS22 + Interrupt Targets Non-secure bits. + 22 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS23 + Interrupt Targets Non-secure bits. + 23 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS24 + Interrupt Targets Non-secure bits. + 24 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS25 + Interrupt Targets Non-secure bits. + 25 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS26 + Interrupt Targets Non-secure bits. + 26 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS27 + Interrupt Targets Non-secure bits. + 27 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS28 + Interrupt Targets Non-secure bits. + 28 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS29 + Interrupt Targets Non-secure bits. + 29 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS30 + Interrupt Targets Non-secure bits. + 30 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS31 + Interrupt Targets Non-secure bits. + 31 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + + + 120 + 0x4 + IPR[%s] + Interrupt Priority Register + 0x300 + 32 + read-write + 0 + 0 + + + PRI_0 + no description available + 0 + 8 + read-write + + + PRI_1 + no description available + 8 + 8 + read-write + + + PRI_2 + no description available + 16 + 8 + read-write + + + PRI_3 + no description available + 24 + 8 + read-write + + + + + STIR + Software Trigger Interrupt Register + 0xE00 + 32 + read-write + 0 + 0xFFFFFFFF + + + INTID + Interrupt ID of the interrupt to trigger, in the range 0-479. + 0 + 9 + write-only + + + + + + + SCB + no description available + SCB + 0xE000ED00 + + 0 + 0x90 + registers + + + + AIRCR + Application Interrupt and Reset Control Register + 0xC + 32 + read-write + 0xFA050000 + 0xFFFFFFFF + + + VECTCLRACTIVE + Reserved for Debug use. This bit reads as 0. When writing to the register you must write 0 to this bit, otherwise behavior is UNPREDICTABLE. This bit is not banked between Security states. + 1 + 1 + write-only + + + SYSRESETREQ + System reset request. This bit allows software or a debugger to request a system reset. This bit is not banked between Security states. RW if SYSRESETREQS is 0. When SYSRESETREQS is set to 1, from Non-secure state this bit acts as RAZ/WI. + 2 + 1 + read-write + + + NO_REQUEST + Do not request a system reset. + 0 + + + REQUEST_RESET + Request a system reset. + 0x1 + + + + + SYSRESETREQS + System reset request, Secure state only. The value of this bit defines whether the SYSRESETREQ bit is functional for Non-secure use. This bit is not banked between Security states. RW from Secure State and RAZ/WI from Non-secure state. + 3 + 1 + read-write + + + SECURE_AND_NON_SECURE + SYSRESETREQ functionality is available to both Security states. + 0 + + + SECURE_ONLY + SYSRESETREQ functionality is only available to Secure state. + 0x1 + + + + + PRIGROUP + Interrupt priority grouping field. This field determines the split of group priority from subpriority. This bit is banked between Security states + 8 + 3 + read-write + + + BFHFNMINS + BusFault, HardFault, and NMI Non-secure enable. The value of this bit defines whether BusFault and NMI exceptions are Non-secure, and whether exceptions target the Non-secure HardFault exception. This bit is not banked between Security states. RW from Secure-state and RO from Non-secure state. + 13 + 1 + read-write + + + SECURE + BusFault, HardFault, and NMI are Secure. + 0 + + + NON_SECURE + BusFault and NMI are Non-secure and exceptions can target Non-secure HardFault. + 0x1 + + + + + PRIS + Prioritize Secure exceptions. The value of this bit defines whether Secure exception priority boosting is enabled. This bit is not banked between Security states. RW from Secure state and RAZ/WI from Non-secure state. + 14 + 1 + read-write + + + SAME_PRIORITY + Priority ranges of Secure and Non-secure exceptions are identical + 0 + + + SECURE_PRIORITIZED + Non-secure exceptions are de-prioritized + 0x1 + + + + + ENDIANNESS + Data endianness bit. This bit is not banked between Security states. + 15 + 1 + read-only + + + LITTLE_ENDIAN + Little-endian. + 0 + + + BIG_ENDIAN + Big-endian + 0x1 + + + + + VECTKEY + Register key: Reads as 0xFA05. On writes, write 0x5FA to VECTKEY, otherwise the write is ignored. This Field is not banked between Security states. + 16 + 16 + read-only + + + + + SCR + The SCR controls features of entry to and exit from low-power state. + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + SLEEPONEXIT + Indicates sleep-on-exit when returning from Handler mode to Thread mode. Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application. This bit is banked between Security states. + 1 + 1 + read-write + + + NOT_SLEEP + Do not sleep when returning to Thread mode. + 0 + + + SLEEP + Enter sleep, or deep sleep, on return from an ISR + 0x1 + + + + + SLEEPDEEP + Controls whether the processor uses sleep or deep sleep as its low-power mode. This bit is not banked between Security states. + 2 + 1 + read-write + + + SLEEP + Sleep. + 0 + + + DEEP_SLEEP + Deep sleep. + 0x1 + + + + + SLEEPDEEPS + Controls whether the SLEEPDEEP bit is only accessible from the Secure state. This bit in only accessible from the Secure state, and behaves as RAZ/WI when accessed from the Nonsecure state. This bit is not banked between Security states. + 3 + 1 + read-write + + + SECURE_AND_NON_SECURE + The SLEEPDEEP bit is accessible from both Security states. + 0 + + + SECURE_ONLY + The SLEEPDEEP bit behaves as RAZ/WI when accessed from the Non-secure state. + 0x1 + + + + + SEVONPEND + Send Event on Pending bit. When an event or interrupt enters pending state, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE. The processor also wakes up on execution of an SEV instruction or an external event. This bit is banked between Security states. + 4 + 1 + read-write + + + EXCLUDE_DISABLED_INTERRUPTS + Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded. + 0 + + + INCLUDE_DISABLED_INTERRUPTS + Enabled events and all interrupts, including disabled interrupts, can wakeup the processor + 0x1 + + + + + + + SHCSR + System Handler Control and State Register + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + MEMFAULTACT + MemManage exception active. + 0 + 1 + read-write + + + NOT_ACTIVE + MemManage exception is not active. + 0 + + + ACTIVE + MemManage exception is active. + 0x1 + + + + + BUSFAULTACT + BusFault exception active. + 1 + 1 + read-write + + + NOT_ACTIVE + BusFault exception is not active. + 0 + + + ACTIVE + BusFault exception is active. + 0x1 + + + + + HARDFAULTACT + HardFault exception active. + 2 + 1 + read-write + + + NOT_ACTIVE + HardFault exception is not active. + 0 + + + ACTIVE + HardFault exception is active. + 0x1 + + + + + USGFAULTACT + UsageFault exception active. + 3 + 1 + read-write + + + NOT_ACTIVE + UsageFault exception is not active. + 0 + + + ACTIVE + UsageFault exception is active. + 0x1 + + + + + SECUREFAULTACT + SecureFault exception active + 4 + 1 + read-write + + + NOT_ACTIVE + SecureFault exception is not active. + 0 + + + ACTIVE + SecureFault exception is active. + 0x1 + + + + + NMIACT + NMI exception active. + 5 + 1 + read-write + + + NOT_ACTIVE + NMI exception is not active. + 0 + + + ACTIVE + NMI exception is active. + 0x1 + + + + + SVCALLACT + SVCall active. + 7 + 1 + read-write + + + NOT_ACTIVE + SVCall exception is not active. + 0 + + + ACTIVE + SVCall exception is active. + 0x1 + + + + + MONITORACT + Debug monitor active. + 8 + 1 + read-write + + + NOT_ACTIVE + Debug monitor exception is not active. + 0 + + + ACTIVE + Debug monitor exception is active. + 0x1 + + + + + PENDSVACT + PendSV exception active. + 10 + 1 + read-write + + + NOT_ACTIVE + PendSV exception is not active. + 0 + + + ACTIVE + PendSV exception is active. + 0x1 + + + + + SYSTICKACT + SysTick exception active. + 11 + 1 + read-write + + + NOT_ACTIVE + SysTick exception is not active. + 0 + + + ACTIVE + SysTick exception is active. + 0x1 + + + + + USGFAULTPENDED + UsageFault exception pending. + 12 + 1 + read-write + + + NOT_PENDING + UsageFault exception is not pending. + 0 + + + PENDING + UsageFault exception is pending. + 0x1 + + + + + MEMFAULTPENDED + MemManage exception pending. + 13 + 1 + read-write + + + NOT_PENDING + MemManage exception is not pending. + 0 + + + PENDING + MemManage exception is pending. + 0x1 + + + + + BUSFAULTPENDED + BusFault exception pending. + 14 + 1 + read-write + + + NOT_PENDING + BusFault exception is pending. + 0 + + + PENDING + BusFault exception is not pending. + 0x1 + + + + + SVCALLPENDED + SVCall pending. + 15 + 1 + read-write + + + NOT_PENDING + SVCall exception is not pending. + 0 + + + PENDING + SVCall exception is pending. + 0x1 + + + + + MEMFAULTENA + MemManage enable. + 16 + 1 + read-write + + + DISABLED + MemManage exception is disabled. + 0 + + + ENABLED + MemManage exception is enabled. + 0x1 + + + + + BUSFAULTENA + BusFault enable. + 17 + 1 + read-write + + + DISABLED + BusFault is disabled. + 0 + + + ENABLED + BusFault is enabled. + 0x1 + + + + + USGFAULTENA + UsageFault enable. + 18 + 1 + read-write + + + DISABLED + UsageFault is disabled. + 0 + + + ENABLED + UsageFault is enabled. + 0x1 + + + + + SECUREFAULTENA + SecureFault exception enable. + 19 + 1 + read-write + + + DISABLED + SecureFault exception is disabled. + 0 + + + ENABLED + SecureFault exception is enabled. + 0x1 + + + + + SECUREFAULTPENDED + SecureFault exception pended state bit. + 20 + 1 + read-write + + + DISABLED + SecureFault exception modification is disabled. + 0 + + + ENABLED + SecureFault exception modification is enabled. + 0x1 + + + + + HARDFAULTPENDED + HardFault exception pended state + 21 + 1 + read-write + + + DISABLED + HardFault exception modification is disabled. + 0 + + + ENABLED + HardFault exception modification is enabled. + 0x1 + + + + + + + NSACR + Non-secure Access Control Register + 0x8C + 32 + read-write + 0 + 0 + + + CP0 + CP0 access. + 0 + 1 + read-write + + + NOT_PERMITTED + Non-secure accesses to this coprocessor generate a NOCP UsageFault. + 0 + + + PERMITTED + Non-secure access to this coprocessor permitted. + 0x1 + + + + + CP1 + CP1 access. + 1 + 1 + read-write + + + NOT_PERMITTED + Non-secure accesses to this coprocessor generate a NOCP UsageFault. + 0 + + + PERMITTED + Non-secure access to this coprocessor permitted. + 0x1 + + + + + CP2 + CP2 access. + 2 + 1 + read-write + + + NOT_PERMITTED + Non-secure accesses to this coprocessor generate a NOCP UsageFault. + 0 + + + PERMITTED + Non-secure access to this coprocessor permitted. + 0x1 + + + + + CP3 + CP3 access. + 3 + 1 + read-write + + + NOT_PERMITTED + Non-secure accesses to this coprocessor generate a NOCP UsageFault. + 0 + + + PERMITTED + Non-secure access to this coprocessor permitted. + 0x1 + + + + + CP4 + CP4 access. + 4 + 1 + read-write + + + NOT_PERMITTED + Non-secure accesses to this coprocessor generate a NOCP UsageFault. + 0 + + + PERMITTED + Non-secure access to this coprocessor permitted. + 0x1 + + + + + CP5 + CP5 access. + 5 + 1 + read-write + + + NOT_PERMITTED + Non-secure accesses to this coprocessor generate a NOCP UsageFault. + 0 + + + PERMITTED + Non-secure access to this coprocessor permitted. + 0x1 + + + + + CP6 + CP6 access. + 6 + 1 + read-write + + + NOT_PERMITTED + Non-secure accesses to this coprocessor generate a NOCP UsageFault. + 0 + + + PERMITTED + Non-secure access to this coprocessor permitted. + 0x1 + + + + + CP7 + CP7 access. + 7 + 1 + read-write + + + NOT_PERMITTED + Non-secure accesses to this coprocessor generate a NOCP UsageFault. + 0 + + + PERMITTED + Non-secure access to this coprocessor permitted. + 0x1 + + + + + CP10 + CP10 access. + 10 + 1 + read-write + + + NOT_PERMITTED + Non-secure accesses to the Floating-point Extension generate a NOCP UsageFault. + 0 + + + PERMITTED + Non-secure access to the Floatingpoint Extension permitted. + 0x1 + + + + + CP11 + CP11 access. + 11 + 1 + read-write + + + + + + + SAU + no description available + SAU + 0xE000EDD0 + + 0 + 0xEC + registers + + + + SAU_CTRL + Security Attribution Unit Control Register + 0xD0 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENABLE + Enable. Enables the SAU. This bit is RAZ/WI when the Security Extension is implemented without an SAU region. + 0 + 1 + read-write + + + DISABLED + The SAU is disabled. + 0 + + + ENABLED + The SAU is enabled. + 0x1 + + + + + ALLNS + All Non-secure. + 1 + 1 + read-write + + + SECURED_MEMORY + Memory is marked as Secure and is not Non-secure callable. + 0 + + + NON_SECURED_MEMORY + Memory is marked as Non-secure. + 0x1 + + + + + + + SAU_TYPE + Security Attribution Unit Type Register + 0xD4 + 32 + read-write + 0 + 0xFFFFFFFF + + + SREGION + SAU regions. The number of implemented SAU regions. + 0 + 8 + read-write + + + + + SAU_RNR + Security Attribution Unit Region Number Register + 0xD8 + 32 + read-write + 0 + 0 + + + REGION + Region number. + 0 + 8 + read-write + + + + + SAU_RBAR + Security Attribution Unit Region Base Address Register + 0xDC + 32 + read-write + 0 + 0 + + + BADDR + Base address. Holds bits[31:5] of the base address for the selected SAU region. Bits[4:0] of the base address are defined as 0x00. + 5 + 27 + read-write + + + + + SAU_RLAR + Security Attribution Unit Region Limit Address Register + 0xE0 + 32 + read-write + 0 + 0 + + + ENABLE + Enable. SAU region enable. + 0 + 1 + read-write + + + ENABLED + SAU region is enabled. + 0 + + + DISABLED + SAU region is disabled. + 0x1 + + + + + NSC + Non-secure callable. Controls whether Non-secure state is permitted to execute an SG instruction from this region. + 1 + 1 + read-write + + + NOT_NON_SECURE_CALLABLE + Region is not Non-secure callable. + 0 + + + NON_SECURE_CALLABLE + Region is Non-secure callable. + 0x1 + + + + + LADDR + Limit address. Holds bits[31:5] of the limit address for the selected SAU region. Bits[4:0] of the limit address are defined as 0x1F. + 5 + 27 + read-write + + + + + SFSR + Secure Fault Status Register + 0xE4 + 32 + read-write + 0 + 0xFFFFFFFF + + + INVEP + Invalid entry point. + 0 + 1 + read-write + + + NO_ERROR + Error has not occurred. + 0 + + + ERROR + Error has occurred. + 0x1 + + + + + INVIS + Invalid integrity signature flag. + 1 + 1 + read-write + + + NO_ERROR + Error has not occurred. + 0 + + + ERROR + Error has occurred. + 0x1 + + + + + INVER + Invalid exception return flag. + 2 + 1 + read-write + + + NO_ERROR + Error has not occurred. + 0 + + + ERROR + Error has occurred. + 0x1 + + + + + AUVIOL + Attribution unit violation flag. + 3 + 1 + read-write + + + NO_ERROR + Error has not occurred. + 0 + + + ERROR + Error has occurred. + 0x1 + + + + + INVTRAN + Invalid transition flag. + 4 + 1 + read-write + + + NO_ERROR + Error has not occurred. + 0 + + + ERROR + Error has occurred. + 0x1 + + + + + LSPERR + Lazy state preservation error flag. + 5 + 1 + read-write + + + NO_ERROR + Error has not occurred. + 0 + + + ERROR + Error has occurred. + 0x1 + + + + + SFARVALID + Secure fault address valid. + 6 + 1 + read-write + + + NOT_VALID + SFAR content not valid. + 0 + + + VALID + SFAR content valid. + 0x1 + + + + + LSERR + Lazy state error flag. + 7 + 1 + read-write + + + NO_ERROR + Error has not occurred + 0 + + + ERROR + Error has occurred. + 0x1 + + + + + + + SFAR + Secure Fault Address Register + 0xE8 + 32 + read-write + 0 + 0 + + + ADDRESS + When the SFARVALID bit of the SFSR is set to 1, this field holds the address of an access that caused an SAU violation. + 0 + 32 + read-write + + + + + + + \ No newline at end of file diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/LPC55S69_cm33_core0_features.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/LPC55S69_cm33_core0_features.h new file mode 100644 index 000000000..f9c2d65e1 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/LPC55S69_cm33_core0_features.h @@ -0,0 +1,305 @@ +/* +** ################################################################### +** Version: rev. 1.0, 2018-08-22 +** Build: b190418 +** +** Abstract: +** Chip specific module features. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2019 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2018-08-22) +** Initial version based on v0.2UM +** +** ################################################################### +*/ + +#ifndef _LPC55S69_cm33_core0_FEATURES_H_ +#define _LPC55S69_cm33_core0_FEATURES_H_ + +/* SOC module features */ + +/* @brief CASPER availability on the SoC. */ +#define FSL_FEATURE_SOC_CASPER_COUNT (1) +/* @brief CRC availability on the SoC. */ +#define FSL_FEATURE_SOC_CRC_COUNT (1) +/* @brief CTIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_CTIMER_COUNT (5) +/* @brief DMA availability on the SoC. */ +#define FSL_FEATURE_SOC_DMA_COUNT (2) +/* @brief FLASH availability on the SoC. */ +#define FSL_FEATURE_SOC_FLASH_COUNT (1) +/* @brief FLEXCOMM availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXCOMM_COUNT (9) +/* @brief GINT availability on the SoC. */ +#define FSL_FEATURE_SOC_GINT_COUNT (2) +/* @brief GPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_GPIO_COUNT (1) +/* @brief SECGPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_SECGPIO_COUNT (1) +/* @brief HASHCRYPT availability on the SoC. */ +#define FSL_FEATURE_SOC_HASHCRYPT_COUNT (1) +/* @brief I2C availability on the SoC. */ +#define FSL_FEATURE_SOC_I2C_COUNT (8) +/* @brief I2S availability on the SoC. */ +#define FSL_FEATURE_SOC_I2S_COUNT (8) +/* @brief INPUTMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) +/* @brief IOCON availability on the SoC. */ +#define FSL_FEATURE_SOC_IOCON_COUNT (1) +/* @brief LPADC availability on the SoC. */ +#define FSL_FEATURE_SOC_LPADC_COUNT (1) +/* @brief MAILBOX availability on the SoC. */ +#define FSL_FEATURE_SOC_MAILBOX_COUNT (1) +/* @brief MRT availability on the SoC. */ +#define FSL_FEATURE_SOC_MRT_COUNT (1) +/* @brief OSTIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_OSTIMER_COUNT (1) +/* @brief PINT availability on the SoC. */ +#define FSL_FEATURE_SOC_PINT_COUNT (1) +/* @brief SECPINT availability on the SoC. */ +#define FSL_FEATURE_SOC_SECPINT_COUNT (1) +/* @brief PMC availability on the SoC. */ +#define FSL_FEATURE_SOC_PMC_COUNT (1) +/* @brief POWERQUAD availability on the SoC. */ +#define FSL_FEATURE_SOC_POWERQUAD_COUNT (1) +/* @brief PUF availability on the SoC. */ +#define FSL_FEATURE_SOC_PUF_COUNT (1) +/* @brief RNG1 availability on the SoC. */ +#define FSL_FEATURE_SOC_LPC_RNG1_COUNT (1) +/* @brief RTC availability on the SoC. */ +#define FSL_FEATURE_SOC_RTC_COUNT (1) +/* @brief SCT availability on the SoC. */ +#define FSL_FEATURE_SOC_SCT_COUNT (1) +/* @brief SDIF availability on the SoC. */ +#define FSL_FEATURE_SOC_SDIF_COUNT (1) +/* @brief SPI availability on the SoC. */ +#define FSL_FEATURE_SOC_SPI_COUNT (9) +/* @brief SYSCON availability on the SoC. */ +#define FSL_FEATURE_SOC_SYSCON_COUNT (1) +/* @brief SYSCTL1 availability on the SoC. */ +#define FSL_FEATURE_SOC_SYSCTL1_COUNT (1) +/* @brief USART availability on the SoC. */ +#define FSL_FEATURE_SOC_USART_COUNT (8) +/* @brief USB availability on the SoC. */ +#define FSL_FEATURE_SOC_USB_COUNT (1) +/* @brief USBFSH availability on the SoC. */ +#define FSL_FEATURE_SOC_USBFSH_COUNT (1) +/* @brief USBHSD availability on the SoC. */ +#define FSL_FEATURE_SOC_USBHSD_COUNT (1) +/* @brief USBHSH availability on the SoC. */ +#define FSL_FEATURE_SOC_USBHSH_COUNT (1) +/* @brief USBPHY availability on the SoC. */ +#define FSL_FEATURE_SOC_USBPHY_COUNT (1) +/* @brief UTICK availability on the SoC. */ +#define FSL_FEATURE_SOC_UTICK_COUNT (1) +/* @brief WWDT availability on the SoC. */ +#define FSL_FEATURE_SOC_WWDT_COUNT (1) + +/* LPADC module features */ + +/* @brief FIFO availability on the SoC. */ +#define FSL_FEATURE_LPADC_FIFO_COUNT (2) +/* @brief Has subsequent trigger priority (bitfield CFG[TPRICTRL]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY (1) +/* @brief Has differential mode (bitfield CMDLn[DIFF]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (0) +/* @brief Has channel scale (bitfield CMDLn[CSCALE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_CSCALE (0) +/* @brief Has conversion type select (bitfield CMDLn[CTYPE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (1) +/* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_MODE (1) +/* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */ +#define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1) +/* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */ +#define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (1) +/* @brief Has offset calibration (bitfield CTRL[CALOFS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFS (1) +/* @brief Has gain calibration (bitfield CTRL[CAL_REQ]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ (1) +/* @brief Has calibration average (bitfield CTRL[CAL_AVGS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS (1) +/* @brief Has internal clock (bitfield CFG[ADCKEN]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (0) +/* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG (0) +/* @brief Has calibration (bitfield CFG[CALOFS]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0) +/* @brief Has offset trim (register OFSTRIM). */ +#define FSL_FEATURE_LPADC_HAS_OFSTRIM (1) + +/* CASPER module features */ + +/* @brief Base address of the CASPER dedicated RAM */ +#define FSL_FEATURE_CASPER_RAM_BASE_ADDRESS (0x04000000) +/* @brief Interleaving of the CASPER dedicated RAM */ +#define FSL_FEATURE_CASPER_RAM_IS_INTERLEAVED (1) + +/* DMA module features */ + +/* @brief Number of channels */ +#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (30) +/* @brief Align size of DMA descriptor */ +#define FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE (512) +/* @brief DMA head link descriptor table align size */ +#define FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE (16U) + +/* FLEXCOMM module features */ + +/* @brief I2S has DMIC interconnection */ +#define FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_HAS_DMIC_INTERCONNECTIONn(x) (0) + +/* HASHCRYPT module features */ + +/* @brief the address of alias offset */ +#define FSL_FEATURE_HASHCRYPT_ALIAS_OFFSET (0x00000000) + +/* I2S module features */ + +/* @brief I2S support dual channel transfer. */ +#define FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL (1) +/* @brief I2S has DMIC interconnection. */ +#define FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION (0) + +/* IOCON module features */ + +/* @brief Func bit field width */ +#define FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH (4) + +/* MAILBOX module features */ + +/* @brief Mailbox side for current core */ +#define FSL_FEATURE_MAILBOX_SIDE_A (1) + +/* MRT module features */ + +/* @brief number of channels. */ +#define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4) + +/* PINT module features */ + +/* @brief Number of connected outputs */ +#define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8) + +/* POWERLIB module features */ + +/* @brief LPC55XX's Powerlib API is different with other LPC series devices. */ +#define FSL_FEATURE_POWERLIB_LPC55XX_EXTEND (1) + +/* POWERQUAD module features */ + +/* @brief Sine and Cossine fix errata */ +#define FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA (1) + +/* PUF module features */ + +/* @brief Number of PUF key slots available on device. */ +#define FSL_FEATURE_PUF_HAS_KEYSLOTS (4) +/* @brief the shift status value */ +#define FSL_FEATURE_PUF_HAS_SHIFT_STATUS (1) + +/* SCT module features */ + +/* @brief Number of events */ +#define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (16) +/* @brief Number of states */ +#define FSL_FEATURE_SCT_NUMBER_OF_STATES (32) +/* @brief Number of match capture */ +#define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) +/* @brief Number of outputs */ +#define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) + +/* SDIF module features */ + +/* @brief FIFO depth, every location is a WORD */ +#define FSL_FEATURE_SDIF_FIFO_DEPTH_64_32BITS (64) +/* @brief Max DMA buffer size */ +#define FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE (4096) +/* @brief Max source clock in HZ */ +#define FSL_FEATURE_SDIF_MAX_SOURCE_CLOCK (52000000) +/* @brief support 2 cards */ +#define FSL_FEATURE_SDIF_ONE_INSTANCE_SUPPORT_TWO_CARD (1) + +/* SECPINT module features */ + +/* @brief Number of connected outputs */ +#define FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS (2) + +/* SYSCON module features */ + +/* @brief Pointer to ROM IAP entry functions */ +#define FSL_FEATURE_SYSCON_IAP_ENTRY_LOCATION (0x03000205) +/* @brief Flash page size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (512) +/* @brief Flash sector size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (32768) +/* @brief Flash size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (622592) +/* @brief Has Power Down mode */ +#define FSL_FEATURE_SYSCON_HAS_POWERDOWN_MODE (1) +/* @brief CCM_ANALOG availability on the SoC. */ +#define FSL_FEATURE_SOC_CCM_ANALOG_COUNT (1) + +/* USB module features */ + +/* @brief Size of the USB dedicated RAM */ +#define FSL_FEATURE_USB_USB_RAM (0x00004000) +/* @brief Base address of the USB dedicated RAM */ +#define FSL_FEATURE_USB_USB_RAM_BASE_ADDRESS (0x40100000) +/* @brief USB version */ +#define FSL_FEATURE_USB_VERSION (200) +/* @brief Number of the endpoint in USB FS */ +#define FSL_FEATURE_USB_EP_NUM (5) + +/* USBFSH module features */ + +/* @brief Size of the USB dedicated RAM */ +#define FSL_FEATURE_USBFSH_USB_RAM (0x00004000) +/* @brief Base address of the USB dedicated RAM */ +#define FSL_FEATURE_USBFSH_USB_RAM_BASE_ADDRESS (0x40100000) +/* @brief USBFSH version */ +#define FSL_FEATURE_USBFSH_VERSION (200) + +/* USBHSD module features */ + +/* @brief Size of the USB dedicated RAM */ +#define FSL_FEATURE_USBHSD_USB_RAM (0x00004000) +/* @brief Base address of the USB dedicated RAM */ +#define FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS (0x40100000) +/* @brief USBHSD version */ +#define FSL_FEATURE_USBHSD_VERSION (300) +/* @brief Number of the endpoint in USB HS */ +#define FSL_FEATURE_USBHSD_EP_NUM (6) + +/* USBHSH module features */ + +/* @brief Size of the USB dedicated RAM */ +#define FSL_FEATURE_USBHSH_USB_RAM (0x00004000) +/* @brief Base address of the USB dedicated RAM */ +#define FSL_FEATURE_USBHSH_USB_RAM_BASE_ADDRESS (0x40100000) +/* @brief USBHSH version */ +#define FSL_FEATURE_USBHSH_VERSION (300) + +/* UTICK module features */ + +/* @brief UTICK does not support PD configure. */ +#define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1) + +/* WWDT module features */ + +/* @brief WWDT does not support oscillator lock. */ +#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (1) +/* @brief WWDT does not support power down configure */ +#define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1) + +#endif /* _LPC55S69_cm33_core0_FEATURES_H_ */ + diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/LPC55S69_cm33_core1.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/LPC55S69_cm33_core1.h new file mode 100644 index 000000000..734057d56 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/LPC55S69_cm33_core1.h @@ -0,0 +1,25763 @@ +/* +** ################################################################### +** Processors: LPC55S69JBD100_cm33_core1 +** LPC55S69JBD64_cm33_core1 +** LPC55S69JET98_cm33_core1 +** +** Compilers: GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.4 25 Sep 2018 +** Version: rev. 1.0, 2018-08-22 +** Build: b190430 +** +** Abstract: +** CMSIS Peripheral Access Layer for LPC55S69_cm33_core1 +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2019 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2018-08-22) +** Initial version based on v0.2UM +** +** ################################################################### +*/ + +/*! + * @file LPC55S69_cm33_core1.h + * @version 1.0 + * @date 2018-08-22 + * @brief CMSIS Peripheral Access Layer for LPC55S69_cm33_core1 + * + * CMSIS Peripheral Access Layer for LPC55S69_cm33_core1 + */ + +#ifndef _LPC55S69_CM33_CORE1_H_ +#define _LPC55S69_CM33_CORE1_H_ /**< Symbol preventing repeated inclusion */ + +/** Memory map major version (memory maps with equal major version number are + * compatible) */ +#define MCU_MEM_MAP_VERSION 0x0100U +/** Memory map minor version */ +#define MCU_MEM_MAP_VERSION_MINOR 0x0000U + + +/* ---------------------------------------------------------------------------- + -- Interrupt vector numbers + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Interrupt_vector_numbers Interrupt vector numbers + * @{ + */ + +/** Interrupt Number Definitions */ +#define NUMBER_OF_INT_VECTORS 76 /**< Number of interrupts in the Vector table */ + +typedef enum IRQn { + /* Auxiliary constants */ + NotAvail_IRQn = -128, /**< Not available device specific interrupt */ + + /* Core interrupts */ + NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< Cortex-M33 SV Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /**< Cortex-M33 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< Cortex-M33 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< Cortex-M33 Usage Fault Interrupt */ + SecureFault_IRQn = -9, /**< Cortex-M33 Secure Fault Interrupt */ + SVCall_IRQn = -5, /**< Cortex-M33 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< Cortex-M33 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< Cortex-M33 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< Cortex-M33 System Tick Interrupt */ + + /* Device specific interrupts */ + WDT_BOD_IRQn = 0, /**< Windowed watchdog timer, Brownout detect, Flash interrupt */ + DMA0_IRQn = 1, /**< DMA0 controller */ + GINT0_IRQn = 2, /**< GPIO group 0 */ + GINT1_IRQn = 3, /**< GPIO group 1 */ + PIN_INT0_IRQn = 4, /**< Pin interrupt 0 or pattern match engine slice 0 */ + PIN_INT1_IRQn = 5, /**< Pin interrupt 1or pattern match engine slice 1 */ + PIN_INT2_IRQn = 6, /**< Pin interrupt 2 or pattern match engine slice 2 */ + PIN_INT3_IRQn = 7, /**< Pin interrupt 3 or pattern match engine slice 3 */ + UTICK0_IRQn = 8, /**< Micro-tick Timer */ + MRT0_IRQn = 9, /**< Multi-rate timer */ + CTIMER0_IRQn = 10, /**< Standard counter/timer CTIMER0 */ + CTIMER1_IRQn = 11, /**< Standard counter/timer CTIMER1 */ + SCT0_IRQn = 12, /**< SCTimer/PWM */ + CTIMER3_IRQn = 13, /**< Standard counter/timer CTIMER3 */ + FLEXCOMM0_IRQn = 14, /**< Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) */ + FLEXCOMM1_IRQn = 15, /**< Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) */ + FLEXCOMM2_IRQn = 16, /**< Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) */ + FLEXCOMM3_IRQn = 17, /**< Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) */ + FLEXCOMM4_IRQn = 18, /**< Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) */ + FLEXCOMM5_IRQn = 19, /**< Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) */ + FLEXCOMM6_IRQn = 20, /**< Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) */ + FLEXCOMM7_IRQn = 21, /**< Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) */ + ADC0_IRQn = 22, /**< ADC0 */ + Reserved39_IRQn = 23, /**< Reserved interrupt */ + ACMP_IRQn = 24, /**< ACMP interrupts */ + Reserved41_IRQn = 25, /**< Reserved interrupt */ + Reserved42_IRQn = 26, /**< Reserved interrupt */ + USB0_NEEDCLK_IRQn = 27, /**< USB Activity Wake-up Interrupt */ + USB0_IRQn = 28, /**< USB device */ + RTC_IRQn = 29, /**< RTC alarm and wake-up interrupts */ + Reserved46_IRQn = 30, /**< Reserved interrupt */ + MAILBOX_IRQn = 31, /**< WAKEUP,Mailbox interrupt (present on selected devices) */ + PIN_INT4_IRQn = 32, /**< Pin interrupt 4 or pattern match engine slice 4 int */ + PIN_INT5_IRQn = 33, /**< Pin interrupt 5 or pattern match engine slice 5 int */ + PIN_INT6_IRQn = 34, /**< Pin interrupt 6 or pattern match engine slice 6 int */ + PIN_INT7_IRQn = 35, /**< Pin interrupt 7 or pattern match engine slice 7 int */ + CTIMER2_IRQn = 36, /**< Standard counter/timer CTIMER2 */ + CTIMER4_IRQn = 37, /**< Standard counter/timer CTIMER4 */ + OS_EVENT_IRQn = 38, /**< OSEVTIMER0 and OSEVTIMER0_WAKEUP interrupts */ + Reserved55_IRQn = 39, /**< Reserved interrupt */ + Reserved56_IRQn = 40, /**< Reserved interrupt */ + Reserved57_IRQn = 41, /**< Reserved interrupt */ + SDIO_IRQn = 42, /**< SD/MMC */ + Reserved59_IRQn = 43, /**< Reserved interrupt */ + Reserved60_IRQn = 44, /**< Reserved interrupt */ + Reserved61_IRQn = 45, /**< Reserved interrupt */ + USB1_UTMI_IRQn = 46, /**< USB1_UTMI */ + USB1_IRQn = 47, /**< USB1 interrupt */ + USB1_NEEDCLK_IRQn = 48, /**< USB1 activity */ + SEC_HYPERVISOR_CALL_IRQn = 49, /**< SEC_HYPERVISOR_CALL interrupt */ + SEC_GPIO_INT0_IRQ0_IRQn = 50, /**< SEC_GPIO_INT0_IRQ0 interrupt */ + SEC_GPIO_INT0_IRQ1_IRQn = 51, /**< SEC_GPIO_INT0_IRQ1 interrupt */ + PLU_IRQn = 52, /**< PLU interrupt */ + SEC_VIO_IRQn = 53, /**< SEC_VIO interrupt */ + HASHCRYPT_IRQn = 54, /**< HASHCRYPT interrupt */ + CASER_IRQn = 55, /**< CASPER interrupt */ + PUF_IRQn = 56, /**< PUF interrupt */ + PQ_IRQn = 57, /**< PQ interrupt */ + DMA1_IRQn = 58, /**< DMA1 interrupt */ + FLEXCOMM8_IRQn = 59 /**< Flexcomm Interface 8 (SPI, , FLEXCOMM) */ +} IRQn_Type; + +/*! + * @} + */ /* end of group Interrupt_vector_numbers */ + + +/* ---------------------------------------------------------------------------- + -- Cortex M33 Core Configuration + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Cortex_Core_Configuration Cortex M33 Core Configuration + * @{ + */ + +#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */ +#define __NVIC_PRIO_BITS 3 /**< Number of priority bits implemented in the NVIC */ +#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ +#define __FPU_PRESENT 0 /**< Defines if an FPU is present or not */ +#define __DSP_PRESENT 0 /**< Defines if Armv8-M Mainline core supports DSP instructions */ +#define __SAUREGION_PRESENT 0 /**< Defines if an SAU is present or not */ + +#include "core_cm33.h" /* Core Peripheral Access Layer */ +#include "system_LPC55S69_cm33_core1.h" /* Device specific configuration file */ + +/*! + * @} + */ /* end of group Cortex_Core_Configuration */ + + +/* ---------------------------------------------------------------------------- + -- Mapping Information + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Mapping_Information Mapping Information + * @{ + */ + +/** Mapping Information */ +/*! + * @addtogroup dma_request + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @brief Structure for the DMA hardware request + * + * Defines the structure for the DMA hardware request collections. The user can configure the + * hardware request to trigger the DMA transfer accordingly. The index + * of the hardware request varies according to the to SoC. + */ +typedef enum _dma_request_source +{ + kDma0RequestHashCrypt = 0U, /**< HashCrypt */ + kDma1RequestHashCrypt = 0U, /**< HashCrypt */ + kDma0RequestNoDMARequest1 = 1U, /**< No DMA request 1 */ + kDma1RequestNoDMARequest1 = 1U, /**< No DMA request 1 */ + kDma0RequestFlexcomm8Rx = 2U, /**< Flexcomm Interface 8 RX */ + kDma1RequestFlexcomm8Rx = 2U, /**< Flexcomm Interface 8 RX */ + kDma0RequestFlexcomm8Tx = 3U, /**< Flexcomm Interface 8 TX */ + kDma1RequestFlexcomm8Tx = 3U, /**< Flexcomm Interface 8 TX */ + kDma0RequestFlexcomm0Rx = 4U, /**< Flexcomm Interface 0 RX/I2C Slave */ + kDma1RequestFlexcomm0Rx = 4U, /**< Flexcomm Interface 0 RX/I2C Slave */ + kDma0RequestFlexcomm0Tx = 5U, /**< Flexcomm Interface 0 TX/I2C Master */ + kDma1RequestFlexcomm0Tx = 5U, /**< Flexcomm Interface 0 TX/I2C Master */ + kDma0RequestFlexcomm1Rx = 6U, /**< Flexcomm Interface 1 RX/I2C Slave */ + kDma1RequestFlexcomm1Rx = 6U, /**< Flexcomm Interface 1 RX/I2C Slave */ + kDma0RequestFlexcomm1Tx = 7U, /**< Flexcomm Interface 1 TX/I2C Master */ + kDma1RequestFlexcomm1Tx = 7U, /**< Flexcomm Interface 1 TX/I2C Master */ + kDma0RequestFlexcomm3Rx = 8U, /**< Flexcomm Interface 3 RX/I2C Slave */ + kDma1RequestFlexcomm2Rx = 8U, /**< Flexcomm Interface 2 RX/I2C Slave */ + kDma0RequestFlexcomm3Tx = 9U, /**< Flexcomm Interface 3 TX/I2C Master */ + kDma1RequestFlexcomm2Tx = 9U, /**< Flexcomm Interface 2 TX/I2C Master */ + kDma0RequestFlexcomm2Rx = 10U, /**< Flexcomm Interface 2 RX/I2C Slave */ + kDma0RequestFlexcomm2Tx = 11U, /**< Flexcomm Interface 2 TX/I2C Master */ + kDma0RequestFlexcomm4Rx = 12U, /**< Flexcomm Interface 4 RX/I2C Slave */ + kDma0RequestFlexcomm4Tx = 13U, /**< Flexcomm Interface 4 TX/I2C Master */ + kDma0RequestFlexcomm5Rx = 14U, /**< Flexcomm Interface 5 RX/I2C Slave */ + kDma0RequestFlexcomm5Tx = 15U, /**< Flexcomm Interface 5 TX/I2C Master */ + kDma0RequestFlexcomm6Rx = 16U, /**< Flexcomm Interface 6 RX/I2C Slave */ + kDma0RequestFlexcomm6Tx = 17U, /**< Flexcomm Interface 6 TX/I2C Master */ + kDma0RequestFlexcomm7Rx = 18U, /**< Flexcomm Interface 7 RX/I2C Slave */ + kDma0RequestFlexcomm7Tx = 19U, /**< Flexcomm Interface 7 TX/I2C Master */ + kDma0RequestNoDMARequest20 = 20U, /**< No DMA request 20 */ + kDma0RequestADC0FIFO0 = 21U, /**< ADC0 FIFO 0 */ + kDma0RequestADC0FIFO1 = 22U, /**< ADC0 FIFO 1 */ +} dma_request_source_t; + +/* @} */ + + +/*! + * @} + */ /* end of group Mapping_Information */ + + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- ADC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer + * @{ + */ + +/** ADC - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ + uint8_t RESERVED_0[8]; + __IO uint32_t CTRL; /**< ADC Control Register, offset: 0x10 */ + __IO uint32_t STAT; /**< ADC Status Register, offset: 0x14 */ + __IO uint32_t IE; /**< Interrupt Enable Register, offset: 0x18 */ + __IO uint32_t DE; /**< DMA Enable Register, offset: 0x1C */ + __IO uint32_t CFG; /**< ADC Configuration Register, offset: 0x20 */ + __IO uint32_t PAUSE; /**< ADC Pause Register, offset: 0x24 */ + uint8_t RESERVED_1[12]; + __IO uint32_t SWTRIG; /**< Software Trigger Register, offset: 0x34 */ + __IO uint32_t TSTAT; /**< Trigger Status Register, offset: 0x38 */ + uint8_t RESERVED_2[4]; + __IO uint32_t OFSTRIM; /**< ADC Offset Trim Register, offset: 0x40 */ + uint8_t RESERVED_3[92]; + __IO uint32_t TCTRL[16]; /**< Trigger Control Register, array offset: 0xA0, array step: 0x4 */ + __IO uint32_t FCTRL[2]; /**< FIFO Control Register, array offset: 0xE0, array step: 0x4 */ + uint8_t RESERVED_4[8]; + __I uint32_t GCC[2]; /**< Gain Calibration Control, array offset: 0xF0, array step: 0x4 */ + __IO uint32_t GCR[2]; /**< Gain Calculation Result, array offset: 0xF8, array step: 0x4 */ + struct { /* offset: 0x100, array step: 0x8 */ + __IO uint32_t CMDL; /**< ADC Command Low Buffer Register, array offset: 0x100, array step: 0x8 */ + __IO uint32_t CMDH; /**< ADC Command High Buffer Register, array offset: 0x104, array step: 0x8 */ + } CMD[15]; + uint8_t RESERVED_5[136]; + __IO uint32_t CV[4]; /**< Compare Value Register, array offset: 0x200, array step: 0x4 */ + uint8_t RESERVED_6[240]; + __I uint32_t RESFIFO[2]; /**< ADC Data Result FIFO Register, array offset: 0x300, array step: 0x4 */ + uint8_t RESERVED_7[248]; + __IO uint32_t CAL_GAR[33]; /**< Calibration General A-Side Registers, array offset: 0x400, array step: 0x4 */ + uint8_t RESERVED_8[124]; + __IO uint32_t CAL_GBR[33]; /**< Calibration General B-Side Registers, array offset: 0x500, array step: 0x4 */ + uint8_t RESERVED_9[2680]; + __IO uint32_t TST; /**< ADC Test Register, offset: 0xFFC */ +} ADC_Type; + +/* ---------------------------------------------------------------------------- + -- ADC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Register_Masks ADC Register Masks + * @{ + */ + +/*! @name VERID - Version ID Register */ +/*! @{ */ +#define ADC_VERID_RES_MASK (0x1U) +#define ADC_VERID_RES_SHIFT (0U) +/*! RES - Resolution + * 0b0..Up to 13-bit differential/12-bit single ended resolution supported. + * 0b1..Up to 16-bit differential/16-bit single ended resolution supported. + */ +#define ADC_VERID_RES(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_RES_SHIFT)) & ADC_VERID_RES_MASK) +#define ADC_VERID_DIFFEN_MASK (0x2U) +#define ADC_VERID_DIFFEN_SHIFT (1U) +/*! DIFFEN - Differential Supported + * 0b0..Differential operation not supported. + * 0b1..Differential operation supported. CMDLa[CTYPE] controls fields implemented. + */ +#define ADC_VERID_DIFFEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_DIFFEN_SHIFT)) & ADC_VERID_DIFFEN_MASK) +#define ADC_VERID_MVI_MASK (0x8U) +#define ADC_VERID_MVI_SHIFT (3U) +/*! MVI - Multi Vref Implemented + * 0b0..Single voltage reference high (VREFH) input supported. + * 0b1..Multiple voltage reference high (VREFH) inputs supported. + */ +#define ADC_VERID_MVI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MVI_SHIFT)) & ADC_VERID_MVI_MASK) +#define ADC_VERID_CSW_MASK (0x70U) +#define ADC_VERID_CSW_SHIFT (4U) +/*! CSW - Channel Scale Width + * 0b000..Channel scaling not supported. + * 0b001..Channel scaling supported. 1-bit CSCALE control field. + * 0b110..Channel scaling supported. 6-bit CSCALE control field. + */ +#define ADC_VERID_CSW(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CSW_SHIFT)) & ADC_VERID_CSW_MASK) +#define ADC_VERID_VR1RNGI_MASK (0x100U) +#define ADC_VERID_VR1RNGI_SHIFT (8U) +/*! VR1RNGI - Voltage Reference 1 Range Control Bit Implemented + * 0b0..Range control not required. CFG[VREF1RNG] is not implemented. + * 0b1..Range control required. CFG[VREF1RNG] is implemented. + */ +#define ADC_VERID_VR1RNGI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_VR1RNGI_SHIFT)) & ADC_VERID_VR1RNGI_MASK) +#define ADC_VERID_IADCKI_MASK (0x200U) +#define ADC_VERID_IADCKI_SHIFT (9U) +/*! IADCKI - Internal ADC Clock implemented + * 0b0..Internal clock source not implemented. + * 0b1..Internal clock source (and CFG[ADCKEN]) implemented. + */ +#define ADC_VERID_IADCKI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_IADCKI_SHIFT)) & ADC_VERID_IADCKI_MASK) +#define ADC_VERID_CALOFSI_MASK (0x400U) +#define ADC_VERID_CALOFSI_SHIFT (10U) +/*! CALOFSI - Calibration Function Implemented + * 0b0..Calibration Not Implemented. + * 0b1..Calibration Implemented. + */ +#define ADC_VERID_CALOFSI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CALOFSI_SHIFT)) & ADC_VERID_CALOFSI_MASK) +#define ADC_VERID_NUM_SEC_MASK (0x800U) +#define ADC_VERID_NUM_SEC_SHIFT (11U) +/*! NUM_SEC - Number of Single Ended Outputs Supported + * 0b0..This design supports one single ended conversion at a time. + * 0b1..This design supports two simultanious single ended conversions. + */ +#define ADC_VERID_NUM_SEC(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_SEC_SHIFT)) & ADC_VERID_NUM_SEC_MASK) +#define ADC_VERID_NUM_FIFO_MASK (0x7000U) +#define ADC_VERID_NUM_FIFO_SHIFT (12U) +/*! NUM_FIFO - Number of FIFOs + * 0b000..N/A + * 0b001..This design supports one result FIFO. + * 0b010..This design supports two result FIFOs. + * 0b011..This design supports three result FIFOs. + * 0b100..This design supports four result FIFOs. + */ +#define ADC_VERID_NUM_FIFO(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_FIFO_SHIFT)) & ADC_VERID_NUM_FIFO_MASK) +#define ADC_VERID_MINOR_MASK (0xFF0000U) +#define ADC_VERID_MINOR_SHIFT (16U) +#define ADC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MINOR_SHIFT)) & ADC_VERID_MINOR_MASK) +#define ADC_VERID_MAJOR_MASK (0xFF000000U) +#define ADC_VERID_MAJOR_SHIFT (24U) +#define ADC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MAJOR_SHIFT)) & ADC_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter Register */ +/*! @{ */ +#define ADC_PARAM_TRIG_NUM_MASK (0xFFU) +#define ADC_PARAM_TRIG_NUM_SHIFT (0U) +#define ADC_PARAM_TRIG_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_TRIG_NUM_SHIFT)) & ADC_PARAM_TRIG_NUM_MASK) +#define ADC_PARAM_FIFOSIZE_MASK (0xFF00U) +#define ADC_PARAM_FIFOSIZE_SHIFT (8U) +/*! FIFOSIZE - Result FIFO Depth + * 0b00000001..Result FIFO depth = 1 dataword. + * 0b00000100..Result FIFO depth = 4 datawords. + * 0b00001000..Result FIFO depth = 8 datawords. + * 0b00010000..Result FIFO depth = 16 datawords. + * 0b00100000..Result FIFO depth = 32 datawords. + * 0b01000000..Result FIFO depth = 64 datawords. + */ +#define ADC_PARAM_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_FIFOSIZE_SHIFT)) & ADC_PARAM_FIFOSIZE_MASK) +#define ADC_PARAM_CV_NUM_MASK (0xFF0000U) +#define ADC_PARAM_CV_NUM_SHIFT (16U) +#define ADC_PARAM_CV_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CV_NUM_SHIFT)) & ADC_PARAM_CV_NUM_MASK) +#define ADC_PARAM_CMD_NUM_MASK (0xFF000000U) +#define ADC_PARAM_CMD_NUM_SHIFT (24U) +#define ADC_PARAM_CMD_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CMD_NUM_SHIFT)) & ADC_PARAM_CMD_NUM_MASK) +/*! @} */ + +/*! @name CTRL - ADC Control Register */ +/*! @{ */ +#define ADC_CTRL_ADCEN_MASK (0x1U) +#define ADC_CTRL_ADCEN_SHIFT (0U) +/*! ADCEN - ADC Enable + * 0b0..ADC is disabled. + * 0b1..ADC is enabled. + */ +#define ADC_CTRL_ADCEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ADCEN_SHIFT)) & ADC_CTRL_ADCEN_MASK) +#define ADC_CTRL_RST_MASK (0x2U) +#define ADC_CTRL_RST_SHIFT (1U) +/*! RST - Software Reset + * 0b0..ADC logic is not reset. + * 0b1..ADC logic is reset. + */ +#define ADC_CTRL_RST(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RST_SHIFT)) & ADC_CTRL_RST_MASK) +#define ADC_CTRL_DOZEN_MASK (0x4U) +#define ADC_CTRL_DOZEN_SHIFT (2U) +/*! DOZEN - Doze Enable + * 0b0..ADC is enabled in Doze mode. + * 0b1..ADC is disabled in Doze mode. + */ +#define ADC_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_DOZEN_SHIFT)) & ADC_CTRL_DOZEN_MASK) +#define ADC_CTRL_CAL_REQ_MASK (0x8U) +#define ADC_CTRL_CAL_REQ_SHIFT (3U) +/*! CAL_REQ - Auto-Calibration Request + * 0b0..No request for auto-calibration has been made. + * 0b1..A request for auto-calibration has been made + */ +#define ADC_CTRL_CAL_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CAL_REQ_SHIFT)) & ADC_CTRL_CAL_REQ_MASK) +#define ADC_CTRL_CALOFS_MASK (0x10U) +#define ADC_CTRL_CALOFS_SHIFT (4U) +/*! CALOFS - Configure for offset calibration function + * 0b0..Calibration function disabled + * 0b1..Request for offset calibration function + */ +#define ADC_CTRL_CALOFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CALOFS_SHIFT)) & ADC_CTRL_CALOFS_MASK) +#define ADC_CTRL_RSTFIFO0_MASK (0x100U) +#define ADC_CTRL_RSTFIFO0_SHIFT (8U) +/*! RSTFIFO0 - Reset FIFO 0 + * 0b0..No effect. + * 0b1..FIFO 0 is reset. + */ +#define ADC_CTRL_RSTFIFO0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO0_SHIFT)) & ADC_CTRL_RSTFIFO0_MASK) +#define ADC_CTRL_RSTFIFO1_MASK (0x200U) +#define ADC_CTRL_RSTFIFO1_SHIFT (9U) +/*! RSTFIFO1 - Reset FIFO 1 + * 0b0..No effect. + * 0b1..FIFO 1 is reset. + */ +#define ADC_CTRL_RSTFIFO1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO1_SHIFT)) & ADC_CTRL_RSTFIFO1_MASK) +#define ADC_CTRL_CAL_AVGS_MASK (0x70000U) +#define ADC_CTRL_CAL_AVGS_SHIFT (16U) +/*! CAL_AVGS - Auto-Calibration Averages + * 0b000..Single conversion. + * 0b001..2 conversions averaged. + * 0b010..4 conversions averaged. + * 0b011..8 conversions averaged. + * 0b100..16 conversions averaged. + * 0b101..32 conversions averaged. + * 0b110..64 conversions averaged. + * 0b111..128 conversions averaged. + */ +#define ADC_CTRL_CAL_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CAL_AVGS_SHIFT)) & ADC_CTRL_CAL_AVGS_MASK) +/*! @} */ + +/*! @name STAT - ADC Status Register */ +/*! @{ */ +#define ADC_STAT_RDY0_MASK (0x1U) +#define ADC_STAT_RDY0_SHIFT (0U) +/*! RDY0 - Result FIFO 0 Ready Flag + * 0b0..Result FIFO 0 data level not above watermark level. + * 0b1..Result FIFO 0 holding data above watermark level. + */ +#define ADC_STAT_RDY0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY0_SHIFT)) & ADC_STAT_RDY0_MASK) +#define ADC_STAT_FOF0_MASK (0x2U) +#define ADC_STAT_FOF0_SHIFT (1U) +/*! FOF0 - Result FIFO 0 Overflow Flag + * 0b0..No result FIFO 0 overflow has occurred since the last time the flag was cleared. + * 0b1..At least one result FIFO 0 overflow has occurred since the last time the flag was cleared. + */ +#define ADC_STAT_FOF0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF0_SHIFT)) & ADC_STAT_FOF0_MASK) +#define ADC_STAT_RDY1_MASK (0x4U) +#define ADC_STAT_RDY1_SHIFT (2U) +/*! RDY1 - Result FIFO1 Ready Flag + * 0b0..Result FIFO1 data level not above watermark level. + * 0b1..Result FIFO1 holding data above watermark level. + */ +#define ADC_STAT_RDY1(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY1_SHIFT)) & ADC_STAT_RDY1_MASK) +#define ADC_STAT_FOF1_MASK (0x8U) +#define ADC_STAT_FOF1_SHIFT (3U) +/*! FOF1 - Result FIFO1 Overflow Flag + * 0b0..No result FIFO1 overflow has occurred since the last time the flag was cleared. + * 0b1..At least one result FIFO1 overflow has occurred since the last time the flag was cleared. + */ +#define ADC_STAT_FOF1(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF1_SHIFT)) & ADC_STAT_FOF1_MASK) +#define ADC_STAT_TEXC_INT_MASK (0x100U) +#define ADC_STAT_TEXC_INT_SHIFT (8U) +/*! TEXC_INT - Interrupt Flag For High Priority Trigger Exception + * 0b0..No trigger exceptions have occurred. + * 0b1..A trigger exception has occurred and is pending acknowledgement. + */ +#define ADC_STAT_TEXC_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TEXC_INT_SHIFT)) & ADC_STAT_TEXC_INT_MASK) +#define ADC_STAT_TCOMP_INT_MASK (0x200U) +#define ADC_STAT_TCOMP_INT_SHIFT (9U) +/*! TCOMP_INT - Interrupt Flag For Trigger Completion + * 0b0..Either IE[TCOMP_IE] is set to 0, or no trigger sequences have run to completion. + * 0b1..Trigger sequence has been completed and all data is stored in the associated FIFO. + */ +#define ADC_STAT_TCOMP_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TCOMP_INT_SHIFT)) & ADC_STAT_TCOMP_INT_MASK) +#define ADC_STAT_CAL_RDY_MASK (0x400U) +#define ADC_STAT_CAL_RDY_SHIFT (10U) +/*! CAL_RDY - Calibration Ready + * 0b0..Calibration is incomplete or hasn't been ran. + * 0b1..The ADC is calibrated. + */ +#define ADC_STAT_CAL_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CAL_RDY_SHIFT)) & ADC_STAT_CAL_RDY_MASK) +#define ADC_STAT_ADC_ACTIVE_MASK (0x800U) +#define ADC_STAT_ADC_ACTIVE_SHIFT (11U) +/*! ADC_ACTIVE - ADC Active + * 0b0..The ADC is IDLE. There are no pending triggers to service and no active commands are being processed. + * 0b1..The ADC is processing a conversion, running through the power up delay, or servicing a trigger. + */ +#define ADC_STAT_ADC_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_ADC_ACTIVE_SHIFT)) & ADC_STAT_ADC_ACTIVE_MASK) +#define ADC_STAT_TRGACT_MASK (0xF0000U) +#define ADC_STAT_TRGACT_SHIFT (16U) +/*! TRGACT - Trigger Active + * 0b0000..Command (sequence) associated with Trigger 0 currently being executed. + * 0b0001..Command (sequence) associated with Trigger 1 currently being executed. + * 0b0010..Command (sequence) associated with Trigger 2 currently being executed. + * 0b0011-0b1111..Command (sequence) from the associated Trigger number is currently being executed. + */ +#define ADC_STAT_TRGACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TRGACT_SHIFT)) & ADC_STAT_TRGACT_MASK) +#define ADC_STAT_CMDACT_MASK (0xF000000U) +#define ADC_STAT_CMDACT_SHIFT (24U) +/*! CMDACT - Command Active + * 0b0000..No command is currently in progress. + * 0b0001..Command 1 currently being executed. + * 0b0010..Command 2 currently being executed. + * 0b0011-0b1111..Associated command number is currently being executed. + */ +#define ADC_STAT_CMDACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CMDACT_SHIFT)) & ADC_STAT_CMDACT_MASK) +/*! @} */ + +/*! @name IE - Interrupt Enable Register */ +/*! @{ */ +#define ADC_IE_FWMIE0_MASK (0x1U) +#define ADC_IE_FWMIE0_SHIFT (0U) +/*! FWMIE0 - FIFO 0 Watermark Interrupt Enable + * 0b0..FIFO 0 watermark interrupts are not enabled. + * 0b1..FIFO 0 watermark interrupts are enabled. + */ +#define ADC_IE_FWMIE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE0_SHIFT)) & ADC_IE_FWMIE0_MASK) +#define ADC_IE_FOFIE0_MASK (0x2U) +#define ADC_IE_FOFIE0_SHIFT (1U) +/*! FOFIE0 - Result FIFO 0 Overflow Interrupt Enable + * 0b0..FIFO 0 overflow interrupts are not enabled. + * 0b1..FIFO 0 overflow interrupts are enabled. + */ +#define ADC_IE_FOFIE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE0_SHIFT)) & ADC_IE_FOFIE0_MASK) +#define ADC_IE_FWMIE1_MASK (0x4U) +#define ADC_IE_FWMIE1_SHIFT (2U) +/*! FWMIE1 - FIFO1 Watermark Interrupt Enable + * 0b0..FIFO1 watermark interrupts are not enabled. + * 0b1..FIFO1 watermark interrupts are enabled. + */ +#define ADC_IE_FWMIE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE1_SHIFT)) & ADC_IE_FWMIE1_MASK) +#define ADC_IE_FOFIE1_MASK (0x8U) +#define ADC_IE_FOFIE1_SHIFT (3U) +/*! FOFIE1 - Result FIFO1 Overflow Interrupt Enable + * 0b0..No result FIFO1 overflow has occurred since the last time the flag was cleared. + * 0b1..At least one result FIFO1 overflow has occurred since the last time the flag was cleared. + */ +#define ADC_IE_FOFIE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE1_SHIFT)) & ADC_IE_FOFIE1_MASK) +#define ADC_IE_TEXC_IE_MASK (0x100U) +#define ADC_IE_TEXC_IE_SHIFT (8U) +/*! TEXC_IE - Trigger Exception Interrupt Enable + * 0b0..Trigger exception interrupts are disabled. + * 0b1..Trigger exception interrupts are enabled. + */ +#define ADC_IE_TEXC_IE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_TEXC_IE_SHIFT)) & ADC_IE_TEXC_IE_MASK) +#define ADC_IE_TCOMP_IE_MASK (0xFFFF0000U) +#define ADC_IE_TCOMP_IE_SHIFT (16U) +/*! TCOMP_IE - Trigger Completion Interrupt Enable + * 0b0000000000000000..Trigger completion interrupts are disabled. + * 0b0000000000000001..Trigger completion interrupts are enabled for trigger source 0 only. + * 0b0000000000000010..Trigger completion interrupts are enabled for trigger source 1 only. + * 0b0000000000000011-0b1111111111111110..Associated trigger completion interrupts are enabled. + * 0b1111111111111111..Trigger completion interrupts are enabled for every trigger source. + */ +#define ADC_IE_TCOMP_IE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_TCOMP_IE_SHIFT)) & ADC_IE_TCOMP_IE_MASK) +/*! @} */ + +/*! @name DE - DMA Enable Register */ +/*! @{ */ +#define ADC_DE_FWMDE0_MASK (0x1U) +#define ADC_DE_FWMDE0_SHIFT (0U) +/*! FWMDE0 - FIFO 0 Watermark DMA Enable + * 0b0..DMA request disabled. + * 0b1..DMA request enabled. + */ +#define ADC_DE_FWMDE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE0_SHIFT)) & ADC_DE_FWMDE0_MASK) +#define ADC_DE_FWMDE1_MASK (0x2U) +#define ADC_DE_FWMDE1_SHIFT (1U) +/*! FWMDE1 - FIFO1 Watermark DMA Enable + * 0b0..DMA request disabled. + * 0b1..DMA request enabled. + */ +#define ADC_DE_FWMDE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE1_SHIFT)) & ADC_DE_FWMDE1_MASK) +/*! @} */ + +/*! @name CFG - ADC Configuration Register */ +/*! @{ */ +#define ADC_CFG_TPRICTRL_MASK (0x3U) +#define ADC_CFG_TPRICTRL_SHIFT (0U) +/*! TPRICTRL - ADC trigger priority control + * 0b00..If a higher priority trigger is detected during command processing, the current conversion is aborted + * and the new command specified by the trigger is started. + * 0b01..If a higher priority trigger is received during command processing, the current command is stopped after + * after completing the current conversion. If averaging is enabled, the averaging loop will be completed. + * However, CMDHa[LOOP] will be ignored and the higher priority trigger will be serviced. + * 0b10..If a higher priority trigger is received during command processing, the current command will be + * completed (averaging, looping, compare) before servicing the higher priority trigger. + * 0b11..RESERVED + */ +#define ADC_CFG_TPRICTRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TPRICTRL_SHIFT)) & ADC_CFG_TPRICTRL_MASK) +#define ADC_CFG_PWRSEL_MASK (0x30U) +#define ADC_CFG_PWRSEL_SHIFT (4U) +/*! PWRSEL - Power Configuration Select + * 0b00..Lowest power setting. + * 0b01..Higher power setting than 0b0. + * 0b10..Higher power setting than 0b1. + * 0b11..Highest power setting. + */ +#define ADC_CFG_PWRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWRSEL_SHIFT)) & ADC_CFG_PWRSEL_MASK) +#define ADC_CFG_REFSEL_MASK (0xC0U) +#define ADC_CFG_REFSEL_SHIFT (6U) +/*! REFSEL - Voltage Reference Selection + * 0b00..(Default) Option 1 setting. + * 0b01..Option 2 setting. + * 0b10..Option 3 setting. + * 0b11..Reserved + */ +#define ADC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK) +#define ADC_CFG_TRES_MASK (0x100U) +#define ADC_CFG_TRES_SHIFT (8U) +/*! TRES - Trigger Resume Enable + * 0b0..Trigger sequences interrupted by a high priority trigger exception will not be automatically resumed or restarted. + * 0b1..Trigger sequences interrupted by a high priority trigger exception will be automatically resumed or restarted. + */ +#define ADC_CFG_TRES(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TRES_SHIFT)) & ADC_CFG_TRES_MASK) +#define ADC_CFG_TCMDRES_MASK (0x200U) +#define ADC_CFG_TCMDRES_SHIFT (9U) +/*! TCMDRES - Trigger Command Resume + * 0b0..Trigger sequences interrupted by a high priority trigger exception will be automatically restarted. + * 0b1..Trigger sequences interrupted by a high priority trigger exception will be resumed from the command executing before the exception. + */ +#define ADC_CFG_TCMDRES(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TCMDRES_SHIFT)) & ADC_CFG_TCMDRES_MASK) +#define ADC_CFG_HPT_EXDI_MASK (0x400U) +#define ADC_CFG_HPT_EXDI_SHIFT (10U) +/*! HPT_EXDI - High Priority Trigger Exception Disable + * 0b0..High priority trigger exceptions are enabled. + * 0b1..High priority trigger exceptions are disabled. + */ +#define ADC_CFG_HPT_EXDI(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_HPT_EXDI_SHIFT)) & ADC_CFG_HPT_EXDI_MASK) +#define ADC_CFG_PUDLY_MASK (0xFF0000U) +#define ADC_CFG_PUDLY_SHIFT (16U) +#define ADC_CFG_PUDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PUDLY_SHIFT)) & ADC_CFG_PUDLY_MASK) +#define ADC_CFG_PWREN_MASK (0x10000000U) +#define ADC_CFG_PWREN_SHIFT (28U) +/*! PWREN - ADC Analog Pre-Enable + * 0b0..ADC analog circuits are only enabled while conversions are active. Performance is affected due to analog startup delays. + * 0b1..ADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the cost + * of higher DC current consumption). A single power up delay (CFG[PUDLY]) is executed immediately once PWREN + * is set, and any detected trigger does not begin ADC operation until the power up delay time has passed. + * After this initial delay expires the analog will remain pre-enabled, and no additional delays will be + * executed. + */ +#define ADC_CFG_PWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWREN_SHIFT)) & ADC_CFG_PWREN_MASK) +/*! @} */ + +/*! @name PAUSE - ADC Pause Register */ +/*! @{ */ +#define ADC_PAUSE_PAUSEDLY_MASK (0x1FFU) +#define ADC_PAUSE_PAUSEDLY_SHIFT (0U) +#define ADC_PAUSE_PAUSEDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEDLY_SHIFT)) & ADC_PAUSE_PAUSEDLY_MASK) +#define ADC_PAUSE_PAUSEEN_MASK (0x80000000U) +#define ADC_PAUSE_PAUSEEN_SHIFT (31U) +/*! PAUSEEN - PAUSE Option Enable + * 0b0..Pause operation disabled + * 0b1..Pause operation enabled + */ +#define ADC_PAUSE_PAUSEEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEEN_SHIFT)) & ADC_PAUSE_PAUSEEN_MASK) +/*! @} */ + +/*! @name SWTRIG - Software Trigger Register */ +/*! @{ */ +#define ADC_SWTRIG_SWT0_MASK (0x1U) +#define ADC_SWTRIG_SWT0_SHIFT (0U) +/*! SWT0 - Software trigger 0 event + * 0b0..No trigger 0 event generated. + * 0b1..Trigger 0 event generated. + */ +#define ADC_SWTRIG_SWT0(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT0_SHIFT)) & ADC_SWTRIG_SWT0_MASK) +#define ADC_SWTRIG_SWT1_MASK (0x2U) +#define ADC_SWTRIG_SWT1_SHIFT (1U) +/*! SWT1 - Software trigger 1 event + * 0b0..No trigger 1 event generated. + * 0b1..Trigger 1 event generated. + */ +#define ADC_SWTRIG_SWT1(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT1_SHIFT)) & ADC_SWTRIG_SWT1_MASK) +#define ADC_SWTRIG_SWT2_MASK (0x4U) +#define ADC_SWTRIG_SWT2_SHIFT (2U) +/*! SWT2 - Software trigger 2 event + * 0b0..No trigger 2 event generated. + * 0b1..Trigger 2 event generated. + */ +#define ADC_SWTRIG_SWT2(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT2_SHIFT)) & ADC_SWTRIG_SWT2_MASK) +#define ADC_SWTRIG_SWT3_MASK (0x8U) +#define ADC_SWTRIG_SWT3_SHIFT (3U) +/*! SWT3 - Software trigger 3 event + * 0b0..No trigger 3 event generated. + * 0b1..Trigger 3 event generated. + */ +#define ADC_SWTRIG_SWT3(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT3_SHIFT)) & ADC_SWTRIG_SWT3_MASK) +#define ADC_SWTRIG_SWT4_MASK (0x10U) +#define ADC_SWTRIG_SWT4_SHIFT (4U) +/*! SWT4 - Software trigger 4 event + * 0b0..No trigger 4 event generated. + * 0b1..Trigger 4 event generated. + */ +#define ADC_SWTRIG_SWT4(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT4_SHIFT)) & ADC_SWTRIG_SWT4_MASK) +#define ADC_SWTRIG_SWT5_MASK (0x20U) +#define ADC_SWTRIG_SWT5_SHIFT (5U) +/*! SWT5 - Software trigger 5 event + * 0b0..No trigger 5 event generated. + * 0b1..Trigger 5 event generated. + */ +#define ADC_SWTRIG_SWT5(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT5_SHIFT)) & ADC_SWTRIG_SWT5_MASK) +#define ADC_SWTRIG_SWT6_MASK (0x40U) +#define ADC_SWTRIG_SWT6_SHIFT (6U) +/*! SWT6 - Software trigger 6 event + * 0b0..No trigger 6 event generated. + * 0b1..Trigger 6 event generated. + */ +#define ADC_SWTRIG_SWT6(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT6_SHIFT)) & ADC_SWTRIG_SWT6_MASK) +#define ADC_SWTRIG_SWT7_MASK (0x80U) +#define ADC_SWTRIG_SWT7_SHIFT (7U) +/*! SWT7 - Software trigger 7 event + * 0b0..No trigger 7 event generated. + * 0b1..Trigger 7 event generated. + */ +#define ADC_SWTRIG_SWT7(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT7_SHIFT)) & ADC_SWTRIG_SWT7_MASK) +#define ADC_SWTRIG_SWT8_MASK (0x100U) +#define ADC_SWTRIG_SWT8_SHIFT (8U) +/*! SWT8 - Software trigger 8 event + * 0b0..No trigger 8 event generated. + * 0b1..Trigger 8 event generated. + */ +#define ADC_SWTRIG_SWT8(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT8_SHIFT)) & ADC_SWTRIG_SWT8_MASK) +#define ADC_SWTRIG_SWT9_MASK (0x200U) +#define ADC_SWTRIG_SWT9_SHIFT (9U) +/*! SWT9 - Software trigger 9 event + * 0b0..No trigger 9 event generated. + * 0b1..Trigger 9 event generated. + */ +#define ADC_SWTRIG_SWT9(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT9_SHIFT)) & ADC_SWTRIG_SWT9_MASK) +#define ADC_SWTRIG_SWT10_MASK (0x400U) +#define ADC_SWTRIG_SWT10_SHIFT (10U) +/*! SWT10 - Software trigger 10 event + * 0b0..No trigger 10 event generated. + * 0b1..Trigger 10 event generated. + */ +#define ADC_SWTRIG_SWT10(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT10_SHIFT)) & ADC_SWTRIG_SWT10_MASK) +#define ADC_SWTRIG_SWT11_MASK (0x800U) +#define ADC_SWTRIG_SWT11_SHIFT (11U) +/*! SWT11 - Software trigger 11 event + * 0b0..No trigger 11 event generated. + * 0b1..Trigger 11 event generated. + */ +#define ADC_SWTRIG_SWT11(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT11_SHIFT)) & ADC_SWTRIG_SWT11_MASK) +#define ADC_SWTRIG_SWT12_MASK (0x1000U) +#define ADC_SWTRIG_SWT12_SHIFT (12U) +/*! SWT12 - Software trigger 12 event + * 0b0..No trigger 12 event generated. + * 0b1..Trigger 12 event generated. + */ +#define ADC_SWTRIG_SWT12(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT12_SHIFT)) & ADC_SWTRIG_SWT12_MASK) +#define ADC_SWTRIG_SWT13_MASK (0x2000U) +#define ADC_SWTRIG_SWT13_SHIFT (13U) +/*! SWT13 - Software trigger 13 event + * 0b0..No trigger 13 event generated. + * 0b1..Trigger 13 event generated. + */ +#define ADC_SWTRIG_SWT13(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT13_SHIFT)) & ADC_SWTRIG_SWT13_MASK) +#define ADC_SWTRIG_SWT14_MASK (0x4000U) +#define ADC_SWTRIG_SWT14_SHIFT (14U) +/*! SWT14 - Software trigger 14 event + * 0b0..No trigger 14 event generated. + * 0b1..Trigger 14 event generated. + */ +#define ADC_SWTRIG_SWT14(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT14_SHIFT)) & ADC_SWTRIG_SWT14_MASK) +#define ADC_SWTRIG_SWT15_MASK (0x8000U) +#define ADC_SWTRIG_SWT15_SHIFT (15U) +/*! SWT15 - Software trigger 15 event + * 0b0..No trigger 15 event generated. + * 0b1..Trigger 15 event generated. + */ +#define ADC_SWTRIG_SWT15(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT15_SHIFT)) & ADC_SWTRIG_SWT15_MASK) +/*! @} */ + +/*! @name TSTAT - Trigger Status Register */ +/*! @{ */ +#define ADC_TSTAT_TEXC_NUM_MASK (0xFFFFU) +#define ADC_TSTAT_TEXC_NUM_SHIFT (0U) +/*! TEXC_NUM - Trigger Exception Number + * 0b0000000000000000..No triggers have been interrupted by a high priority exception. Or CFG[TRES] = 1. + * 0b0000000000000001..Trigger 0 has been interrupted by a high priority exception. + * 0b0000000000000010..Trigger 1 has been interrupted by a high priority exception. + * 0b0000000000000011-0b1111111111111110..Associated trigger sequence has interrupted by a high priority exception. + * 0b1111111111111111..Every trigger sequence has been interrupted by a high priority exception. + */ +#define ADC_TSTAT_TEXC_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_TSTAT_TEXC_NUM_SHIFT)) & ADC_TSTAT_TEXC_NUM_MASK) +#define ADC_TSTAT_TCOMP_FLAG_MASK (0xFFFF0000U) +#define ADC_TSTAT_TCOMP_FLAG_SHIFT (16U) +/*! TCOMP_FLAG - Trigger Completion Flag + * 0b0000000000000000..No triggers have been completed. Trigger completion interrupts are disabled. + * 0b0000000000000001..Trigger 0 has been completed and triger 0 has enabled completion interrupts. + * 0b0000000000000010..Trigger 1 has been completed and triger 1 has enabled completion interrupts. + * 0b0000000000000011-0b1111111111111110..Associated trigger sequence has completed and has enabled completion interrupts. + * 0b1111111111111111..Every trigger sequence has been completed and every trigger has enabled completion interrupts. + */ +#define ADC_TSTAT_TCOMP_FLAG(x) (((uint32_t)(((uint32_t)(x)) << ADC_TSTAT_TCOMP_FLAG_SHIFT)) & ADC_TSTAT_TCOMP_FLAG_MASK) +/*! @} */ + +/*! @name OFSTRIM - ADC Offset Trim Register */ +/*! @{ */ +#define ADC_OFSTRIM_OFSTRIM_A_MASK (0x1FU) +#define ADC_OFSTRIM_OFSTRIM_A_SHIFT (0U) +#define ADC_OFSTRIM_OFSTRIM_A(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFSTRIM_OFSTRIM_A_SHIFT)) & ADC_OFSTRIM_OFSTRIM_A_MASK) +#define ADC_OFSTRIM_OFSTRIM_B_MASK (0x1F0000U) +#define ADC_OFSTRIM_OFSTRIM_B_SHIFT (16U) +#define ADC_OFSTRIM_OFSTRIM_B(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFSTRIM_OFSTRIM_B_SHIFT)) & ADC_OFSTRIM_OFSTRIM_B_MASK) +/*! @} */ + +/*! @name TCTRL - Trigger Control Register */ +/*! @{ */ +#define ADC_TCTRL_HTEN_MASK (0x1U) +#define ADC_TCTRL_HTEN_SHIFT (0U) +/*! HTEN - Trigger enable + * 0b0..Hardware trigger source disabled + * 0b1..Hardware trigger source enabled + */ +#define ADC_TCTRL_HTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_HTEN_SHIFT)) & ADC_TCTRL_HTEN_MASK) +#define ADC_TCTRL_FIFO_SEL_A_MASK (0x2U) +#define ADC_TCTRL_FIFO_SEL_A_SHIFT (1U) +/*! FIFO_SEL_A - SAR Result Destination For Channel A + * 0b0..Result written to FIFO 0 + * 0b1..Result written to FIFO 1 + */ +#define ADC_TCTRL_FIFO_SEL_A(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_FIFO_SEL_A_SHIFT)) & ADC_TCTRL_FIFO_SEL_A_MASK) +#define ADC_TCTRL_FIFO_SEL_B_MASK (0x4U) +#define ADC_TCTRL_FIFO_SEL_B_SHIFT (2U) +/*! FIFO_SEL_B - SAR Result Destination For Channel B + * 0b0..Result written to FIFO 0 + * 0b1..Result written to FIFO 1 + */ +#define ADC_TCTRL_FIFO_SEL_B(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_FIFO_SEL_B_SHIFT)) & ADC_TCTRL_FIFO_SEL_B_MASK) +#define ADC_TCTRL_TPRI_MASK (0xF00U) +#define ADC_TCTRL_TPRI_SHIFT (8U) +/*! TPRI - Trigger priority setting + * 0b0000..Set to highest priority, Level 1 + * 0b0001-0b1110..Set to corresponding priority level + * 0b1111..Set to lowest priority, Level 16 + */ +#define ADC_TCTRL_TPRI(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TPRI_SHIFT)) & ADC_TCTRL_TPRI_MASK) +#define ADC_TCTRL_RSYNC_MASK (0x8000U) +#define ADC_TCTRL_RSYNC_SHIFT (15U) +#define ADC_TCTRL_RSYNC(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_RSYNC_SHIFT)) & ADC_TCTRL_RSYNC_MASK) +#define ADC_TCTRL_TDLY_MASK (0xF0000U) +#define ADC_TCTRL_TDLY_SHIFT (16U) +#define ADC_TCTRL_TDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TDLY_SHIFT)) & ADC_TCTRL_TDLY_MASK) +#define ADC_TCTRL_TCMD_MASK (0xF000000U) +#define ADC_TCTRL_TCMD_SHIFT (24U) +/*! TCMD - Trigger command select + * 0b0000..Not a valid selection from the command buffer. Trigger event is ignored. + * 0b0001..CMD1 is executed + * 0b0010-0b1110..Corresponding CMD is executed + * 0b1111..CMD15 is executed + */ +#define ADC_TCTRL_TCMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TCMD_SHIFT)) & ADC_TCTRL_TCMD_MASK) +/*! @} */ + +/* The count of ADC_TCTRL */ +#define ADC_TCTRL_COUNT (16U) + +/*! @name FCTRL - FIFO Control Register */ +/*! @{ */ +#define ADC_FCTRL_FCOUNT_MASK (0x1FU) +#define ADC_FCTRL_FCOUNT_SHIFT (0U) +#define ADC_FCTRL_FCOUNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FCOUNT_SHIFT)) & ADC_FCTRL_FCOUNT_MASK) +#define ADC_FCTRL_FWMARK_MASK (0xF0000U) +#define ADC_FCTRL_FWMARK_SHIFT (16U) +#define ADC_FCTRL_FWMARK(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FWMARK_SHIFT)) & ADC_FCTRL_FWMARK_MASK) +/*! @} */ + +/* The count of ADC_FCTRL */ +#define ADC_FCTRL_COUNT (2U) + +/*! @name GCC - Gain Calibration Control */ +/*! @{ */ +#define ADC_GCC_GAIN_CAL_MASK (0xFFFFU) +#define ADC_GCC_GAIN_CAL_SHIFT (0U) +#define ADC_GCC_GAIN_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCC_GAIN_CAL_SHIFT)) & ADC_GCC_GAIN_CAL_MASK) +#define ADC_GCC_RDY_MASK (0x1000000U) +#define ADC_GCC_RDY_SHIFT (24U) +/*! RDY - Gain Calibration Value Valid + * 0b0..The gain calibration value is invalid. Run the auto-calibration routine for this value to be written. + * 0b1..The gain calibration value is valid. It should be used to update the GCRa[GCALR] register field. + */ +#define ADC_GCC_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCC_RDY_SHIFT)) & ADC_GCC_RDY_MASK) +/*! @} */ + +/* The count of ADC_GCC */ +#define ADC_GCC_COUNT (2U) + +/*! @name GCR - Gain Calculation Result */ +/*! @{ */ +#define ADC_GCR_GCALR_MASK (0xFFFFU) +#define ADC_GCR_GCALR_SHIFT (0U) +#define ADC_GCR_GCALR(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCR_GCALR_SHIFT)) & ADC_GCR_GCALR_MASK) +#define ADC_GCR_RDY_MASK (0x1000000U) +#define ADC_GCR_RDY_SHIFT (24U) +/*! RDY - Gain Calculation Ready + * 0b0..The gain offset calculation value is invalid. + * 0b1..The gain calibration value is valid. + */ +#define ADC_GCR_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCR_RDY_SHIFT)) & ADC_GCR_RDY_MASK) +/*! @} */ + +/* The count of ADC_GCR */ +#define ADC_GCR_COUNT (2U) + +/*! @name CMDL - ADC Command Low Buffer Register */ +/*! @{ */ +#define ADC_CMDL_ADCH_MASK (0x1FU) +#define ADC_CMDL_ADCH_SHIFT (0U) +/*! ADCH - Input channel select + * 0b00000..Select CH0A or CH0B or CH0A/CH0B pair. + * 0b00001..Select CH1A or CH1B or CH1A/CH1B pair. + * 0b00010..Select CH2A or CH2B or CH2A/CH2B pair. + * 0b00011..Select CH3A or CH3B or CH3A/CH3B pair. + * 0b00100-0b11101..Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + * 0b11110..Select CH30A or CH30B or CH30A/CH30B pair. + * 0b11111..Select CH31A or CH31B or CH31A/CH31B pair. + */ +#define ADC_CMDL_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ADCH_SHIFT)) & ADC_CMDL_ADCH_MASK) +#define ADC_CMDL_CTYPE_MASK (0x60U) +#define ADC_CMDL_CTYPE_SHIFT (5U) +/*! CTYPE - Conversion Type + * 0b00..Single-Ended Mode. Only A side channel is converted. + * 0b01..Single-Ended Mode. Only B side channel is converted. + * 0b10..Differential Mode. A-B. + * 0b11..Dual-Single-Ended Mode. Both A side and B side channels are converted independently. + */ +#define ADC_CMDL_CTYPE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_CTYPE_SHIFT)) & ADC_CMDL_CTYPE_MASK) +#define ADC_CMDL_MODE_MASK (0x80U) +#define ADC_CMDL_MODE_SHIFT (7U) +/*! MODE - Select resolution of conversions + * 0b0..Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. + * 0b1..High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. + */ +#define ADC_CMDL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_MODE_SHIFT)) & ADC_CMDL_MODE_MASK) +/*! @} */ + +/* The count of ADC_CMDL */ +#define ADC_CMDL_COUNT (15U) + +/*! @name CMDH - ADC Command High Buffer Register */ +/*! @{ */ +#define ADC_CMDH_CMPEN_MASK (0x3U) +#define ADC_CMDH_CMPEN_SHIFT (0U) +/*! CMPEN - Compare Function Enable + * 0b00..Compare disabled. + * 0b01..Reserved + * 0b10..Compare enabled. Store on true. + * 0b11..Compare enabled. Repeat channel acquisition (sample/convert/compare) until true. + */ +#define ADC_CMDH_CMPEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_CMPEN_SHIFT)) & ADC_CMDH_CMPEN_MASK) +#define ADC_CMDH_WAIT_TRIG_MASK (0x4U) +#define ADC_CMDH_WAIT_TRIG_SHIFT (2U) +/*! WAIT_TRIG - Wait for trigger assertion before execution. + * 0b0..This command will be automatically executed. + * 0b1..The active trigger must be asserted again before executing this command. + */ +#define ADC_CMDH_WAIT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_WAIT_TRIG_SHIFT)) & ADC_CMDH_WAIT_TRIG_MASK) +#define ADC_CMDH_LWI_MASK (0x80U) +#define ADC_CMDH_LWI_SHIFT (7U) +/*! LWI - Loop with Increment + * 0b0..Auto channel increment disabled + * 0b1..Auto channel increment enabled + */ +#define ADC_CMDH_LWI(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LWI_SHIFT)) & ADC_CMDH_LWI_MASK) +#define ADC_CMDH_STS_MASK (0x700U) +#define ADC_CMDH_STS_SHIFT (8U) +/*! STS - Sample Time Select + * 0b000..Minimum sample time of 3 ADCK cycles. + * 0b001..3 + 21 ADCK cycles; 5 ADCK cycles total sample time. + * 0b010..3 + 22 ADCK cycles; 7 ADCK cycles total sample time. + * 0b011..3 + 23 ADCK cycles; 11 ADCK cycles total sample time. + * 0b100..3 + 24 ADCK cycles; 19 ADCK cycles total sample time. + * 0b101..3 + 25 ADCK cycles; 35 ADCK cycles total sample time. + * 0b110..3 + 26 ADCK cycles; 67 ADCK cycles total sample time. + * 0b111..3 + 27 ADCK cycles; 131 ADCK cycles total sample time. + */ +#define ADC_CMDH_STS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_STS_SHIFT)) & ADC_CMDH_STS_MASK) +#define ADC_CMDH_AVGS_MASK (0x7000U) +#define ADC_CMDH_AVGS_SHIFT (12U) +/*! AVGS - Hardware Average Select + * 0b000..Single conversion. + * 0b001..2 conversions averaged. + * 0b010..4 conversions averaged. + * 0b011..8 conversions averaged. + * 0b100..16 conversions averaged. + * 0b101..32 conversions averaged. + * 0b110..64 conversions averaged. + * 0b111..128 conversions averaged. + */ +#define ADC_CMDH_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_AVGS_SHIFT)) & ADC_CMDH_AVGS_MASK) +#define ADC_CMDH_LOOP_MASK (0xF0000U) +#define ADC_CMDH_LOOP_SHIFT (16U) +/*! LOOP - Loop Count Select + * 0b0000..Looping not enabled. Command executes 1 time. + * 0b0001..Loop 1 time. Command executes 2 times. + * 0b0010..Loop 2 times. Command executes 3 times. + * 0b0011-0b1110..Loop corresponding number of times. Command executes LOOP+1 times. + * 0b1111..Loop 15 times. Command executes 16 times. + */ +#define ADC_CMDH_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LOOP_SHIFT)) & ADC_CMDH_LOOP_MASK) +#define ADC_CMDH_NEXT_MASK (0xF000000U) +#define ADC_CMDH_NEXT_SHIFT (24U) +/*! NEXT - Next Command Select + * 0b0000..No next command defined. Terminate conversions at completion of current command. If lower priority + * trigger pending, begin command associated with lower priority trigger. + * 0b0001..Select CMD1 command buffer register as next command. + * 0b0010-0b1110..Select corresponding CMD command buffer register as next command + * 0b1111..Select CMD15 command buffer register as next command. + */ +#define ADC_CMDH_NEXT(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_NEXT_SHIFT)) & ADC_CMDH_NEXT_MASK) +/*! @} */ + +/* The count of ADC_CMDH */ +#define ADC_CMDH_COUNT (15U) + +/*! @name CV - Compare Value Register */ +/*! @{ */ +#define ADC_CV_CVL_MASK (0xFFFFU) +#define ADC_CV_CVL_SHIFT (0U) +#define ADC_CV_CVL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVL_SHIFT)) & ADC_CV_CVL_MASK) +#define ADC_CV_CVH_MASK (0xFFFF0000U) +#define ADC_CV_CVH_SHIFT (16U) +#define ADC_CV_CVH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVH_SHIFT)) & ADC_CV_CVH_MASK) +/*! @} */ + +/* The count of ADC_CV */ +#define ADC_CV_COUNT (4U) + +/*! @name RESFIFO - ADC Data Result FIFO Register */ +/*! @{ */ +#define ADC_RESFIFO_D_MASK (0xFFFFU) +#define ADC_RESFIFO_D_SHIFT (0U) +#define ADC_RESFIFO_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_D_SHIFT)) & ADC_RESFIFO_D_MASK) +#define ADC_RESFIFO_TSRC_MASK (0xF0000U) +#define ADC_RESFIFO_TSRC_SHIFT (16U) +/*! TSRC - Trigger Source + * 0b0000..Trigger source 0 initiated this conversion. + * 0b0001..Trigger source 1 initiated this conversion. + * 0b0010-0b1110..Corresponding trigger source initiated this conversion. + * 0b1111..Trigger source 15 initiated this conversion. + */ +#define ADC_RESFIFO_TSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_TSRC_SHIFT)) & ADC_RESFIFO_TSRC_MASK) +#define ADC_RESFIFO_LOOPCNT_MASK (0xF00000U) +#define ADC_RESFIFO_LOOPCNT_SHIFT (20U) +/*! LOOPCNT - Loop count value + * 0b0000..Result is from initial conversion in command. + * 0b0001..Result is from second conversion in command. + * 0b0010-0b1110..Result is from LOOPCNT+1 conversion in command. + * 0b1111..Result is from 16th conversion in command. + */ +#define ADC_RESFIFO_LOOPCNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_LOOPCNT_SHIFT)) & ADC_RESFIFO_LOOPCNT_MASK) +#define ADC_RESFIFO_CMDSRC_MASK (0xF000000U) +#define ADC_RESFIFO_CMDSRC_SHIFT (24U) +/*! CMDSRC - Command Buffer Source + * 0b0000..Not a valid value CMDSRC value for a dataword in RESFIFO. 0x0 is only found in initial FIFO state + * prior to an ADC conversion result dataword being stored to a RESFIFO buffer. + * 0b0001..CMD1 buffer used as control settings for this conversion. + * 0b0010-0b1110..Corresponding command buffer used as control settings for this conversion. + * 0b1111..CMD15 buffer used as control settings for this conversion. + */ +#define ADC_RESFIFO_CMDSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_CMDSRC_SHIFT)) & ADC_RESFIFO_CMDSRC_MASK) +#define ADC_RESFIFO_VALID_MASK (0x80000000U) +#define ADC_RESFIFO_VALID_SHIFT (31U) +/*! VALID - FIFO entry is valid + * 0b0..FIFO is empty. Discard any read from RESFIFO. + * 0b1..FIFO record read from RESFIFO is valid. + */ +#define ADC_RESFIFO_VALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_VALID_SHIFT)) & ADC_RESFIFO_VALID_MASK) +/*! @} */ + +/* The count of ADC_RESFIFO */ +#define ADC_RESFIFO_COUNT (2U) + +/*! @name CAL_GAR - Calibration General A-Side Registers */ +/*! @{ */ +#define ADC_CAL_GAR_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR_CAL_GAR_VAL_SHIFT (0U) +#define ADC_CAL_GAR_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR_CAL_GAR_VAL_MASK) +/*! @} */ + +/* The count of ADC_CAL_GAR */ +#define ADC_CAL_GAR_COUNT (33U) + +/*! @name CAL_GBR - Calibration General B-Side Registers */ +/*! @{ */ +#define ADC_CAL_GBR_CAL_GBR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GBR_CAL_GBR_VAL_SHIFT (0U) +#define ADC_CAL_GBR_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR_CAL_GBR_VAL_MASK) +/*! @} */ + +/* The count of ADC_CAL_GBR */ +#define ADC_CAL_GBR_COUNT (33U) + +/*! @name TST - ADC Test Register */ +/*! @{ */ +#define ADC_TST_CST_LONG_MASK (0x1U) +#define ADC_TST_CST_LONG_SHIFT (0U) +/*! CST_LONG - Calibration Sample Time Long + * 0b0..Normal sample time. Minimum sample time of 3 ADCK cycles. + * 0b1..Increased sample time. 67 ADCK cycles total sample time. + */ +#define ADC_TST_CST_LONG(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_CST_LONG_SHIFT)) & ADC_TST_CST_LONG_MASK) +#define ADC_TST_FOFFM_MASK (0x100U) +#define ADC_TST_FOFFM_SHIFT (8U) +/*! FOFFM - Force M-side positive offset + * 0b0..Normal operation. No forced offset. + * 0b1..Test configuration. Forced positive offset on MDAC. + */ +#define ADC_TST_FOFFM(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_FOFFM_SHIFT)) & ADC_TST_FOFFM_MASK) +#define ADC_TST_FOFFP_MASK (0x200U) +#define ADC_TST_FOFFP_SHIFT (9U) +/*! FOFFP - Force P-side positive offset + * 0b0..Normal operation. No forced offset. + * 0b1..Test configuration. Forced positive offset on PDAC. + */ +#define ADC_TST_FOFFP(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_FOFFP_SHIFT)) & ADC_TST_FOFFP_MASK) +#define ADC_TST_FOFFM2_MASK (0x400U) +#define ADC_TST_FOFFM2_SHIFT (10U) +/*! FOFFM2 - Force M-side negative offset + * 0b0..Normal operation. No forced offset. + * 0b1..Test configuration. Forced negative offset on MDAC. + */ +#define ADC_TST_FOFFM2(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_FOFFM2_SHIFT)) & ADC_TST_FOFFM2_MASK) +#define ADC_TST_FOFFP2_MASK (0x800U) +#define ADC_TST_FOFFP2_SHIFT (11U) +/*! FOFFP2 - Force P-side negative offset + * 0b0..Normal operation. No forced offset. + * 0b1..Test configuration. Forced negative offset on PDAC. + */ +#define ADC_TST_FOFFP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_FOFFP2_SHIFT)) & ADC_TST_FOFFP2_MASK) +#define ADC_TST_TESTEN_MASK (0x800000U) +#define ADC_TST_TESTEN_SHIFT (23U) +/*! TESTEN - Enable test configuration + * 0b0..Normal operation. Test configuration not enabled. + * 0b1..Hardware BIST Test in progress. + */ +#define ADC_TST_TESTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_TESTEN_SHIFT)) & ADC_TST_TESTEN_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group ADC_Register_Masks */ + + +/* ADC - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral ADC0 base address */ + #define ADC0_BASE (0x500A0000u) + /** Peripheral ADC0 base address */ + #define ADC0_BASE_NS (0x400A0000u) + /** Peripheral ADC0 base pointer */ + #define ADC0 ((ADC_Type *)ADC0_BASE) + /** Peripheral ADC0 base pointer */ + #define ADC0_NS ((ADC_Type *)ADC0_BASE_NS) + /** Array initializer of ADC peripheral base addresses */ + #define ADC_BASE_ADDRS { ADC0_BASE } + /** Array initializer of ADC peripheral base pointers */ + #define ADC_BASE_PTRS { ADC0 } + /** Array initializer of ADC peripheral base addresses */ + #define ADC_BASE_ADDRS_NS { ADC0_BASE_NS } + /** Array initializer of ADC peripheral base pointers */ + #define ADC_BASE_PTRS_NS { ADC0_NS } +#else + /** Peripheral ADC0 base address */ + #define ADC0_BASE (0x400A0000u) + /** Peripheral ADC0 base pointer */ + #define ADC0 ((ADC_Type *)ADC0_BASE) + /** Array initializer of ADC peripheral base addresses */ + #define ADC_BASE_ADDRS { ADC0_BASE } + /** Array initializer of ADC peripheral base pointers */ + #define ADC_BASE_PTRS { ADC0 } +#endif +/** Interrupt vectors for the ADC peripheral type */ +#define ADC_IRQS { ADC0_IRQn } + +/*! + * @} + */ /* end of group ADC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- AHB_SECURE_CTRL Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup AHB_SECURE_CTRL_Peripheral_Access_Layer AHB_SECURE_CTRL Peripheral Access Layer + * @{ + */ + +/** AHB_SECURE_CTRL - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x30 */ + __IO uint32_t SLAVE_RULE; /**< Security access rules for Flash and ROM slaves., array offset: 0x0, array step: 0x30 */ + uint8_t RESERVED_0[12]; + __IO uint32_t SEC_CTRL_FLASH_MEM_RULE[3]; /**< Security access rules for FLASH sector 0 to sector 20. Each Flash sector is 32 Kbytes. There are 20 FLASH sectors in total., array offset: 0x10, array step: index*0x30, index2*0x4 */ + uint8_t RESERVED_1[4]; + __IO uint32_t SEC_CTRL_ROM_MEM_RULE[4]; /**< Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total., array offset: 0x20, array step: index*0x30, index2*0x4 */ + } SEC_CTRL_FLASH_ROM[1]; + struct { /* offset: 0x30, array step: 0x14 */ + __IO uint32_t SLAVE_RULE; /**< Security access rules for RAMX slaves., array offset: 0x30, array step: 0x14 */ + uint8_t RESERVED_0[12]; + __IO uint32_t MEM_RULE[1]; /**< Security access rules for RAMX slaves., array offset: 0x40, array step: index*0x14, index2*0x4 */ + } SEC_CTRL_RAMX[1]; + uint8_t RESERVED_0[12]; + struct { /* offset: 0x50, array step: 0x18 */ + __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM0 slaves., array offset: 0x50, array step: 0x18 */ + uint8_t RESERVED_0[12]; + __IO uint32_t MEM_RULE[2]; /**< Security access rules for RAM0 slaves., array offset: 0x60, array step: index*0x18, index2*0x4 */ + } SEC_CTRL_RAM0[1]; + uint8_t RESERVED_1[8]; + struct { /* offset: 0x70, array step: 0x18 */ + __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM1 slaves., array offset: 0x70, array step: 0x18 */ + uint8_t RESERVED_0[12]; + __IO uint32_t MEM_RULE[2]; /**< Security access rules for RAM1 slaves., array offset: 0x80, array step: index*0x18, index2*0x4 */ + } SEC_CTRL_RAM1[1]; + uint8_t RESERVED_2[8]; + struct { /* offset: 0x90, array step: 0x18 */ + __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM2 slaves., array offset: 0x90, array step: 0x18 */ + uint8_t RESERVED_0[12]; + __IO uint32_t MEM_RULE[2]; /**< Security access rules for RAM2 slaves., array offset: 0xA0, array step: index*0x18, index2*0x4 */ + } SEC_CTRL_RAM2[1]; + uint8_t RESERVED_3[8]; + struct { /* offset: 0xB0, array step: 0x18 */ + __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM3 slaves., array offset: 0xB0, array step: 0x18 */ + uint8_t RESERVED_0[12]; + __IO uint32_t MEM_RULE[2]; /**< Security access rules for RAM3 slaves., array offset: 0xC0, array step: index*0x18, index2*0x4 */ + } SEC_CTRL_RAM3[1]; + uint8_t RESERVED_4[8]; + struct { /* offset: 0xD0, array step: 0x14 */ + __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM4 slaves., array offset: 0xD0, array step: 0x14 */ + uint8_t RESERVED_0[12]; + __IO uint32_t MEM_RULE[1]; /**< Security access rules for RAM4 slaves., array offset: 0xE0, array step: index*0x14, index2*0x4 */ + } SEC_CTRL_RAM4[1]; + uint8_t RESERVED_5[12]; + struct { /* offset: 0xF0, array step: 0x30 */ + __IO uint32_t SLAVE_RULE; /**< Security access rules for both APB Bridges slaves., array offset: 0xF0, array step: 0x30 */ + uint8_t RESERVED_0[12]; + __IO uint32_t SEC_CTRL_APB_BRIDGE0_MEM_CTRL0; /**< Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total., array offset: 0x100, array step: 0x30 */ + __IO uint32_t SEC_CTRL_APB_BRIDGE0_MEM_CTRL1; /**< Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total., array offset: 0x104, array step: 0x30 */ + __IO uint32_t SEC_CTRL_APB_BRIDGE0_MEM_CTRL2; /**< Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total., array offset: 0x108, array step: 0x30 */ + uint32_t SEC_CTRL_APB_BRIDGE0_MEM_CTRL3; /**< Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total., array offset: 0x10C, array step: 0x30 */ + __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL0; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0x110, array step: 0x30 */ + __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL1; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0x114, array step: 0x30 */ + __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL2; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0x118, array step: 0x30 */ + __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL3; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0x11C, array step: 0x30 */ + } SEC_CTRL_APB_BRIDGE[1]; + __IO uint32_t SEC_CTRL_AHB0_0_SLAVE_RULE; /**< Security access rules for AHB peripherals., offset: 0x120 */ + __IO uint32_t SEC_CTRL_AHB0_1_SLAVE_RULE; /**< Security access rules for AHB peripherals., offset: 0x124 */ + uint8_t RESERVED_6[8]; + __IO uint32_t SEC_CTRL_AHB1_0_SLAVE_RULE; /**< Security access rules for AHB peripherals., offset: 0x130 */ + __IO uint32_t SEC_CTRL_AHB1_1_SLAVE_RULE; /**< Security access rules for AHB peripherals., offset: 0x134 */ + uint8_t RESERVED_7[8]; + struct { /* offset: 0x140, array step: 0x14 */ + __IO uint32_t SEC_CTRL_AHB2_0_SLAVE_RULE; /**< Security access rules for AHB peripherals., array offset: 0x140, array step: 0x14 */ + __IO uint32_t SEC_CTRL_AHB2_1_SLAVE_RULE; /**< Security access rules for AHB peripherals., array offset: 0x144, array step: 0x14 */ + uint8_t RESERVED_0[8]; + __IO uint32_t SEC_CTRL_AHB2_0_MEM_RULE[1]; /**< Security access rules for AHB_SEC_CTRL_AHB., array offset: 0x150, array step: index*0x14, index2*0x4 */ + } SEC_CTRL_AHB2[1]; + uint8_t RESERVED_8[12]; + struct { /* offset: 0x160, array step: 0x14 */ + __IO uint32_t SLAVE_RULE; /**< Security access rules for USB High speed RAM slaves., array offset: 0x160, array step: 0x14 */ + uint8_t RESERVED_0[12]; + __IO uint32_t MEM_RULE[1]; /**< Security access rules for RAM_USB_HS., array offset: 0x170, array step: index*0x14, index2*0x4 */ + } SEC_CTRL_USB_HS[1]; + uint8_t RESERVED_9[3212]; + __I uint32_t SEC_VIO_ADDR[12]; /**< most recent security violation address for AHB layer n, array offset: 0xE00, array step: 0x4 */ + uint8_t RESERVED_10[80]; + __I uint32_t SEC_VIO_MISC_INFO[12]; /**< most recent security violation miscellaneous information for AHB layer n, array offset: 0xE80, array step: 0x4 */ + uint8_t RESERVED_11[80]; + __IO uint32_t SEC_VIO_INFO_VALID; /**< security violation address/information registers valid flags, offset: 0xF00 */ + uint8_t RESERVED_12[124]; + __IO uint32_t SEC_GPIO_MASK0; /**< Secure GPIO mask for port 0 pins., offset: 0xF80 */ + __IO uint32_t SEC_GPIO_MASK1; /**< Secure GPIO mask for port 1 pins., offset: 0xF84 */ + uint8_t RESERVED_13[8]; + __IO uint32_t SEC_CPU_INT_MASK0; /**< Secure Interrupt mask for CPU1, offset: 0xF90 */ + __IO uint32_t SEC_CPU_INT_MASK1; /**< Secure Interrupt mask for CPU1, offset: 0xF94 */ + uint8_t RESERVED_14[36]; + __IO uint32_t SEC_MASK_LOCK; /**< Security General Purpose register access control., offset: 0xFBC */ + uint8_t RESERVED_15[16]; + __IO uint32_t MASTER_SEC_LEVEL; /**< master secure level register, offset: 0xFD0 */ + __IO uint32_t MASTER_SEC_ANTI_POL_REG; /**< master secure level anti-pole register, offset: 0xFD4 */ + uint8_t RESERVED_16[20]; + __IO uint32_t CM33_LOCK_REG; /**< Miscalleneous control signals for in CM33 (CPU0), offset: 0xFEC */ + __IO uint32_t MCM33_LOCK_REG; /**< Miscalleneous control signals for in micro-CM33 (CPU1), offset: 0xFF0 */ + uint8_t RESERVED_17[4]; + __IO uint32_t MISC_CTRL_DP_REG; /**< secure control duplicate register, offset: 0xFF8 */ + __IO uint32_t MISC_CTRL_REG; /**< secure control register, offset: 0xFFC */ +} AHB_SECURE_CTRL_Type; + +/* ---------------------------------------------------------------------------- + -- AHB_SECURE_CTRL Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup AHB_SECURE_CTRL_Register_Masks AHB_SECURE_CTRL Register Masks + * @{ + */ + +/*! @name SEC_CTRL_FLASH_ROM_SLAVE_RULE - Security access rules for Flash and ROM slaves. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_SHIFT (0U) +/*! FLASH_RULE - Security access rules for the whole FLASH : 0x0000_0000 - 0x0009_FFFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_SHIFT (4U) +/*! ROM_RULE - Security access rules for the whole ROM : 0x0300_0000 - 0x0301_FFFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_COUNT (1U) + +/*! @name SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE - Security access rules for FLASH sector 0 to sector 20. Each Flash sector is 32 Kbytes. There are 20 FLASH sectors in total. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE0_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE0_SHIFT (0U) +/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE0_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE1_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE1_SHIFT (4U) +/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE1_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE2_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE2_SHIFT (8U) +/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE2_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE3_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE3_SHIFT (12U) +/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE3_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE4_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE4_SHIFT (16U) +/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE4_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE5_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE5_SHIFT (20U) +/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE5_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE6_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE6_SHIFT (24U) +/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE6_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE7_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE7_SHIFT (28U) +/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE7_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_COUNT (1U) + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_COUNT2 (3U) + +/*! @name SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE - Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE0_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE0_SHIFT (0U) +/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE0_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE1_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE1_SHIFT (4U) +/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE1_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE2_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE2_SHIFT (8U) +/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE2_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE3_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE3_SHIFT (12U) +/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE3_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE4_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE4_SHIFT (16U) +/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE4_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE5_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE5_SHIFT (20U) +/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE5_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE6_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE6_SHIFT (24U) +/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE6_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE7_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE7_SHIFT (28U) +/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE7_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_COUNT (1U) + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_COUNT2 (4U) + +/*! @name SEC_CTRL_RAMX_SLAVE_RULE - Security access rules for RAMX slaves. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_SHIFT (0U) +/*! RAMX_RULE - Security access rules for the whole RAMX : 0x0400_0000 - 0x0400_7FFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_COUNT (1U) + +/*! @name SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE - Security access rules for RAMX slaves. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE0_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE0_SHIFT (0U) +/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE0_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE1_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE1_SHIFT (4U) +/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE1_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE2_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE2_SHIFT (8U) +/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE2_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE3_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE3_SHIFT (12U) +/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE3_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE4_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE4_SHIFT (16U) +/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE4_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE5_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE5_SHIFT (20U) +/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE5_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE6_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE6_SHIFT (24U) +/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE6_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE7_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE7_SHIFT (28U) +/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE7_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_COUNT (1U) + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_COUNT2 (1U) + +/*! @name SEC_CTRL_RAM0_SLAVE_RULE - Security access rules for RAM0 slaves. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_SHIFT (0U) +/*! RAM0_RULE - Security access rules for the whole RAM0 : 0x2000_0000 - 0x2000_FFFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_COUNT (1U) + +/*! @name SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE - Security access rules for RAM0 slaves. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE0_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE0_SHIFT (0U) +/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE0_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE1_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE1_SHIFT (4U) +/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE1_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE2_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE2_SHIFT (8U) +/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE2_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE3_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE3_SHIFT (12U) +/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE3_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE4_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE4_SHIFT (16U) +/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE4_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE5_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE5_SHIFT (20U) +/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE5_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE6_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE6_SHIFT (24U) +/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE6_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE7_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE7_SHIFT (28U) +/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE7_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_COUNT (1U) + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_COUNT2 (2U) + +/*! @name SEC_CTRL_RAM1_SLAVE_RULE - Security access rules for RAM1 slaves. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM0_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM0_RULE_SHIFT (0U) +/*! RAM0_RULE - Security access rules for the whole RAM1 : 0x2001_0000 - 0x2001_FFFF" name="0 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM0_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_COUNT (1U) + +/*! @name SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE - Security access rules for RAM1 slaves. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE0_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE0_SHIFT (0U) +/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE0_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE1_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE1_SHIFT (4U) +/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE1_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE2_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE2_SHIFT (8U) +/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE2_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE3_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE3_SHIFT (12U) +/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE3_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE4_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE4_SHIFT (16U) +/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE4_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE5_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE5_SHIFT (20U) +/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE5_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE6_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE6_SHIFT (24U) +/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE6_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE7_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE7_SHIFT (28U) +/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE7_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_COUNT (1U) + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_COUNT2 (2U) + +/*! @name SEC_CTRL_RAM2_SLAVE_RULE - Security access rules for RAM2 slaves. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_SHIFT (0U) +/*! RAM2_RULE - Security access rules for the whole RAM2 : 0x2002_0000 - 0x2002_FFFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_COUNT (1U) + +/*! @name SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE - Security access rules for RAM2 slaves. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE0_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE0_SHIFT (0U) +/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE0_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE1_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE1_SHIFT (4U) +/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE1_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE2_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE2_SHIFT (8U) +/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE2_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE3_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE3_SHIFT (12U) +/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE3_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE4_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE4_SHIFT (16U) +/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE4_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE5_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE5_SHIFT (20U) +/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE5_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE6_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE6_SHIFT (24U) +/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE6_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE7_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE7_SHIFT (28U) +/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE7_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_COUNT (1U) + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_COUNT2 (2U) + +/*! @name SEC_CTRL_RAM3_SLAVE_RULE - Security access rules for RAM3 slaves. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE_SHIFT (0U) +/*! RAM3_RULE - Security access rules for the whole RAM3: 0x2003_0000 - 0x2003_FFFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_COUNT (1U) + +/*! @name SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE - Security access rules for RAM3 slaves. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE0_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE0_SHIFT (0U) +/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE0_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE1_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE1_SHIFT (4U) +/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE1_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE2_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE2_SHIFT (8U) +/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE2_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE3_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE3_SHIFT (12U) +/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE3_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE4_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE4_SHIFT (16U) +/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE4_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE5_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE5_SHIFT (20U) +/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE5_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE6_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE6_SHIFT (24U) +/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE6_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE7_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE7_SHIFT (28U) +/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE7_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_COUNT (1U) + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_COUNT2 (2U) + +/*! @name SEC_CTRL_RAM4_SLAVE_RULE - Security access rules for RAM4 slaves. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE_SHIFT (0U) +/*! RAM4_RULE - Security access rules for the whole RAM4 : 0x2004_0000 - 0x2004_3FFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_COUNT (1U) + +/*! @name SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE - Security access rules for RAM4 slaves. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE0_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE0_SHIFT (0U) +/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE0_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE1_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE1_SHIFT (4U) +/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE1_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE2_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE2_SHIFT (8U) +/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE2_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE3_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE3_SHIFT (12U) +/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE3_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_COUNT (1U) + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_COUNT2 (1U) + +/*! @name SEC_CTRL_APB_BRIDGE_SLAVE_RULE - Security access rules for both APB Bridges slaves. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_SHIFT (0U) +/*! APBBRIDGE0_RULE - Security access rules for the whole APB Bridge 0 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_SHIFT (4U) +/*! APBBRIDGE1_RULE - Security access rules for the whole APB Bridge 1 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_COUNT (1U) + +/*! @name SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_SHIFT (0U) +/*! SYSCON_RULE - System Configuration + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_SHIFT (4U) +/*! IOCON_RULE - I/O Configuration + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_SHIFT (8U) +/*! GINT0_RULE - GPIO input Interrupt 0 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_SHIFT (12U) +/*! GINT1_RULE - GPIO input Interrupt 1 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_SHIFT (16U) +/*! PINT_RULE - Pin Interrupt and Pattern match + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_SHIFT (20U) +/*! SEC_PINT_RULE - Secure Pin Interrupt and Pattern match + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PMUX_RULE_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PMUX_RULE_SHIFT (24U) +/*! PMUX_RULE - Peripherals mux + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PMUX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PMUX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PMUX_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0 */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_COUNT (1U) + +/*! @name SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_SHIFT (0U) +/*! CTIMER0_RULE - Standard counter/Timer 0 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_SHIFT (4U) +/*! CTIMER1_RULE - Standard counter/Timer 1 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_SHIFT (16U) +/*! WWDT_RULE - Windiwed wtachdog Timer + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_SHIFT (20U) +/*! MRT_RULE - Multi-rate Timer + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_SHIFT (24U) +/*! UTICK_RULE - Micro-Timer + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1 */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_COUNT (1U) + +/*! @name SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_SHIFT (12U) +/*! ANACTRL_RULE - Analog Modules controller + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_EFUSE_RULE_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_EFUSE_RULE_SHIFT (20U) +/*! EFUSE_RULE - eFUSE (One Time Programmable) memory controller + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_EFUSE_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_EFUSE_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_EFUSE_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2 */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_COUNT (1U) + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL3 */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL3_COUNT (1U) + +/*! @name SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_SHIFT (0U) +/*! PMC_RULE - Power Management Controller + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_SHIFT (12U) +/*! SYSCTRL_RULE - System Controller + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0 */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_COUNT (1U) + +/*! @name SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_SHIFT (0U) +/*! CTIMER2_RULE - Standard counter/Timer 2 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_SHIFT (4U) +/*! CTIMER3_RULE - Standard counter/Timer 3 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_SHIFT (8U) +/*! CTIMER4_RULE - Standard counter/Timer 4 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_SHIFT (16U) +/*! RTC_RULE - Real Time Counter + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_SHIFT (20U) +/*! OSEVENT_RULE - OS Event Timer + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1 */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_COUNT (1U) + +/*! @name SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_SHIFT (16U) +/*! FLASH_CTRL_RULE - Flash Controller + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_SHIFT (20U) +/*! PRINCE_RULE - Prince + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2 */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_COUNT (1U) + +/*! @name SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_SHIFT (0U) +/*! USBHPHY_RULE - USB High Speed Phy controller + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_SHIFT (8U) +/*! RNG_RULE - True Random Number Generator + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUFF_RULE_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUFF_RULE_SHIFT (12U) +/*! PUFF_RULE - PUF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUFF_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUFF_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUFF_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_SHIFT (20U) +/*! PLU_RULE - Programmable Look-Up logic + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3 */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_COUNT (1U) + +/*! @name SEC_CTRL_AHB0_0_SLAVE_RULE - Security access rules for AHB peripherals. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_DMA0_RULE_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_DMA0_RULE_SHIFT (8U) +/*! DMA0_RULE - DMA Controller + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_DMA0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_DMA0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_DMA0_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FS_USB_DEV_RULE_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FS_USB_DEV_RULE_SHIFT (16U) +/*! FS_USB_DEV_RULE - USB Full-speed device + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FS_USB_DEV_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FS_USB_DEV_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FS_USB_DEV_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_SCT_RULE_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_SCT_RULE_SHIFT (20U) +/*! SCT_RULE - SCTimer + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_SCT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_SCT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_SCT_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FLEXCOMM0_RULE_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FLEXCOMM0_RULE_SHIFT (24U) +/*! FLEXCOMM0_RULE - Flexcomm interface 0 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FLEXCOMM0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FLEXCOMM0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FLEXCOMM0_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FLEXCOMM1_RULE_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FLEXCOMM1_RULE_SHIFT (28U) +/*! FLEXCOMM1_RULE - Flexcomm interface 1 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FLEXCOMM1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FLEXCOMM1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FLEXCOMM1_RULE_MASK) +/*! @} */ + +/*! @name SEC_CTRL_AHB0_1_SLAVE_RULE - Security access rules for AHB peripherals. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM2_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM2_RULE_SHIFT (0U) +/*! FLEXCOMM2_RULE - Flexcomm interface 2 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM2_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM3_RULE_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM3_RULE_SHIFT (4U) +/*! FLEXCOMM3_RULE - Flexcomm interface 3 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM3_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM4_RULE_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM4_RULE_SHIFT (8U) +/*! FLEXCOMM4_RULE - Flexcomm interface 4 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM4_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM4_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM4_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_MAILBOX_RULE_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_MAILBOX_RULE_SHIFT (12U) +/*! MAILBOX_RULE - Inter CPU communication Mailbox + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_MAILBOX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_MAILBOX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_MAILBOX_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_GPIO0_RULE_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_GPIO0_RULE_SHIFT (16U) +/*! GPIO0_RULE - High Speed GPIO + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_GPIO0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_GPIO0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_GPIO0_RULE_MASK) +/*! @} */ + +/*! @name SEC_CTRL_AHB1_0_SLAVE_RULE - Security access rules for AHB peripherals. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_USB_HS_DEV_RULE_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_USB_HS_DEV_RULE_SHIFT (16U) +/*! USB_HS_DEV_RULE - USB high Speed device registers + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_USB_HS_DEV_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_USB_HS_DEV_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_USB_HS_DEV_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_CRC_RULE_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_CRC_RULE_SHIFT (20U) +/*! CRC_RULE - CRC engine + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_CRC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_CRC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_CRC_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_FLEXCOMM5_RULE_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_FLEXCOMM5_RULE_SHIFT (24U) +/*! FLEXCOMM5_RULE - Flexcomm interface 5 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_FLEXCOMM5_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_FLEXCOMM5_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_FLEXCOMM5_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_FLEXCOMM6_RULE_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_FLEXCOMM6_RULE_SHIFT (28U) +/*! FLEXCOMM6_RULE - Flexcomm interface 6 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_FLEXCOMM6_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_FLEXCOMM6_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_FLEXCOMM6_RULE_MASK) +/*! @} */ + +/*! @name SEC_CTRL_AHB1_1_SLAVE_RULE - Security access rules for AHB peripherals. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_FLEXCOMM7_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_FLEXCOMM7_RULE_SHIFT (0U) +/*! FLEXCOMM7_RULE - Flexcomm interface 7 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_FLEXCOMM7_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_FLEXCOMM7_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_FLEXCOMM7_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_SDIO_RULE_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_SDIO_RULE_SHIFT (12U) +/*! SDIO_RULE - SDMMC card interface + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_SDIO_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_SDIO_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_SDIO_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_DBG_MAILBOX_RULE_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_DBG_MAILBOX_RULE_SHIFT (16U) +/*! DBG_MAILBOX_RULE - Debug mailbox (aka ISP-AP) + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_DBG_MAILBOX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_DBG_MAILBOX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_DBG_MAILBOX_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_HS_LSPI_RULE_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_HS_LSPI_RULE_SHIFT (28U) +/*! HS_LSPI_RULE - High Speed SPI + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_HS_LSPI_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_HS_LSPI_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_HS_LSPI_RULE_MASK) +/*! @} */ + +/*! @name SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE - Security access rules for AHB peripherals. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_ADC_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_ADC_RULE_SHIFT (0U) +/*! ADC_RULE - ADC + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_ADC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_ADC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_ADC_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_USB_FS_HOST_RULE_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_USB_FS_HOST_RULE_SHIFT (8U) +/*! USB_FS_HOST_RULE - USB Full Speed Host registers. + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_USB_FS_HOST_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_USB_FS_HOST_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_USB_FS_HOST_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_USB_HS_HOST_RULE_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_USB_HS_HOST_RULE_SHIFT (12U) +/*! USB_HS_HOST_RULE - USB High speed host registers + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_USB_HS_HOST_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_USB_HS_HOST_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_USB_HS_HOST_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_HASH_RULE_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_HASH_RULE_SHIFT (16U) +/*! HASH_RULE - SHA-2 crypto registers + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_HASH_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_HASH_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_HASH_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_CASPER_RULE_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_CASPER_RULE_SHIFT (20U) +/*! CASPER_RULE - RSA/ECC crypto accelerator + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_CASPER_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_CASPER_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_CASPER_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_PQ_RULE_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_PQ_RULE_SHIFT (24U) +/*! PQ_RULE - Power Quad (CM33 processor hardware accelerator) + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_PQ_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_PQ_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_PQ_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_DMA1_RULE_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_DMA1_RULE_SHIFT (28U) +/*! DMA1_RULE - DMA Controller (Secure) + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_DMA1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_DMA1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_DMA1_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_COUNT (1U) + +/*! @name SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE - Security access rules for AHB peripherals. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE_GPIO1_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE_GPIO1_RULE_SHIFT (0U) +/*! GPIO1_RULE - Secure High Speed GPIO + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE_GPIO1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE_GPIO1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE_GPIO1_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE_AHB_SEC_CTRL_RULE_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE_AHB_SEC_CTRL_RULE_SHIFT (4U) +/*! AHB_SEC_CTRL_RULE - AHB Secure Controller + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE_AHB_SEC_CTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE_AHB_SEC_CTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE_AHB_SEC_CTRL_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE_COUNT (1U) + +/*! @name SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE - Security access rules for AHB_SEC_CTRL_AHB. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_SHIFT (0U) +/*! AHB_SEC_CTRL_SECT_0_RULE - Address space: 0x400A_0000 - 0x400A_CFFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_SHIFT (4U) +/*! AHB_SEC_CTRL_SECT_1_RULE - Address space: 0x400A_D000 - 0x400A_DFFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_SHIFT (8U) +/*! AHB_SEC_CTRL_SECT_2_RULE - Address space: 0x400A_E000 - 0x400A_EFFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_SHIFT (12U) +/*! AHB_SEC_CTRL_SECT_3_RULE - Address space: 0x400A_F000 - 0x400A_FFFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_COUNT (1U) + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_COUNT2 (1U) + +/*! @name SEC_CTRL_USB_HS_SLAVE_RULE - Security access rules for USB High speed RAM slaves. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_SHIFT (0U) +/*! RAM_USB_HS_RULE - Security access rules for the whole USB High Speed RAM : 0x4010_0000 - 0x4010_3FFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_COUNT (1U) + +/*! @name SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE - Security access rules for RAM_USB_HS. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_0_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_0_RULE_SHIFT (0U) +/*! SRAM_SECT_0_RULE - Address space: 0x4010_0000 - 0x4010_0FFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_0_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_1_RULE_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_1_RULE_SHIFT (4U) +/*! SRAM_SECT_1_RULE - Address space: 0x4010_1000 - 0x4010_1FFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_1_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_2_RULE_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_2_RULE_SHIFT (8U) +/*! SRAM_SECT_2_RULE - Address space: 0x4010_2000 - 0x4010_2FFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_2_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_3_RULE_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_3_RULE_SHIFT (12U) +/*! SRAM_SECT_3_RULE - Address space: 0x4010_3000 - 0x4010_3FFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_3_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_COUNT (1U) + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_COUNT2 (1U) + +/*! @name SEC_VIO_ADDR - most recent security violation address for AHB layer n */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_MASK (0xFFFFFFFFU) +#define AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_SHIFT (0U) +#define AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_VIO_ADDR */ +#define AHB_SECURE_CTRL_SEC_VIO_ADDR_COUNT (12U) + +/*! @name SEC_VIO_MISC_INFO - most recent security violation miscellaneous information for AHB layer n */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_MASK (0x1U) +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_SHIFT (0U) +/*! SEC_VIO_INFO_WRITE - security violation access read/write indicator. + * 0b0..Read access. + * 0b1..Write access. + */ +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_MASK) +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_MASK (0x2U) +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_SHIFT (1U) +/*! SEC_VIO_INFO_DATA_ACCESS - security violation access data/code indicator. + * 0b0..Code access. + * 0b1..Data access. + */ +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_MASK) +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_MASK (0xF0U) +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_SHIFT (4U) +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_MASK) +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_MASK (0xF00U) +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SHIFT (8U) +/*! SEC_VIO_INFO_MASTER - security violation master number + * 0b0000..CPU0 Code. + * 0b0001..CPU0 System. + * 0b0010..CPU1 Data. + * 0b0011..CPU1 System. + * 0b0100..USB-HS Device. + * 0b0101..SDMA0. + * 0b1000..SDIO. + * 0b1001..PowerQuad. + * 0b1010..HASH. + * 0b1011..USB-FS Host. + * 0b1100..SDMA1. + */ +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_VIO_MISC_INFO */ +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_COUNT (12U) + +/*! @name SEC_VIO_INFO_VALID - security violation address/information registers valid flags */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_MASK (0x1U) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_SHIFT (0U) +/*! VIO_INFO_VALID0 - violation information valid flag for AHB layer 0. Write 1 to clear. + * 0b0..Not valid. + * 0b1..Valid (violation occurred). + */ +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_MASK) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_MASK (0x2U) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_SHIFT (1U) +/*! VIO_INFO_VALID1 - violation information valid flag for AHB layer 1. Write 1 to clear. + * 0b0..Not valid. + * 0b1..Valid (violation occurred). + */ +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_MASK) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_MASK (0x4U) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_SHIFT (2U) +/*! VIO_INFO_VALID2 - violation information valid flag for AHB layer 2. Write 1 to clear. + * 0b0..Not valid. + * 0b1..Valid (violation occurred). + */ +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_MASK) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_MASK (0x8U) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_SHIFT (3U) +/*! VIO_INFO_VALID3 - violation information valid flag for AHB layer 3. Write 1 to clear. + * 0b0..Not valid. + * 0b1..Valid (violation occurred). + */ +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_MASK) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_MASK (0x10U) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_SHIFT (4U) +/*! VIO_INFO_VALID4 - violation information valid flag for AHB layer 4. Write 1 to clear. + * 0b0..Not valid. + * 0b1..Valid (violation occurred). + */ +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_MASK) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_MASK (0x20U) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_SHIFT (5U) +/*! VIO_INFO_VALID5 - violation information valid flag for AHB layer 5. Write 1 to clear. + * 0b0..Not valid. + * 0b1..Valid (violation occurred). + */ +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_MASK) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_MASK (0x40U) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_SHIFT (6U) +/*! VIO_INFO_VALID6 - violation information valid flag for AHB layer 6. Write 1 to clear. + * 0b0..Not valid. + * 0b1..Valid (violation occurred). + */ +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_MASK) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_MASK (0x80U) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_SHIFT (7U) +/*! VIO_INFO_VALID7 - violation information valid flag for AHB layer 7. Write 1 to clear. + * 0b0..Not valid. + * 0b1..Valid (violation occurred). + */ +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_MASK) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_MASK (0x100U) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_SHIFT (8U) +/*! VIO_INFO_VALID8 - violation information valid flag for AHB layer 8. Write 1 to clear. + * 0b0..Not valid. + * 0b1..Valid (violation occurred). + */ +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_MASK) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_MASK (0x200U) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_SHIFT (9U) +/*! VIO_INFO_VALID9 - violation information valid flag for AHB layer 9. Write 1 to clear. + * 0b0..Not valid. + * 0b1..Valid (violation occurred). + */ +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_MASK) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_MASK (0x400U) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_SHIFT (10U) +/*! VIO_INFO_VALID10 - violation information valid flag for AHB layer 10. Write 1 to clear. + * 0b0..Not valid. + * 0b1..Valid (violation occurred). + */ +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_MASK) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_MASK (0x800U) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_SHIFT (11U) +/*! VIO_INFO_VALID11 - violation information valid flag for AHB layer 11. Write 1 to clear. + * 0b0..Not valid. + * 0b1..Valid (violation occurred). + */ +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_MASK) +/*! @} */ + +/*! @name SEC_GPIO_MASK0 - Secure GPIO mask for port 0 pins. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_MASK (0x1U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_SHIFT (0U) +/*! PIO0_PIN0_SEC_MASK - Secure mask for pin P0_0 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_MASK (0x2U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_SHIFT (1U) +/*! PIO0_PIN1_SEC_MASK - Secure mask for pin P0_1 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_MASK (0x4U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_SHIFT (2U) +/*! PIO0_PIN2_SEC_MASK - Secure mask for pin P0_2 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_MASK (0x8U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_SHIFT (3U) +/*! PIO0_PIN3_SEC_MASK - Secure mask for pin P0_3 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_MASK (0x10U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_SHIFT (4U) +/*! PIO0_PIN4_SEC_MASK - Secure mask for pin P0_4 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_MASK (0x20U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_SHIFT (5U) +/*! PIO0_PIN5_SEC_MASK - Secure mask for pin P0_5 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_MASK (0x40U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_SHIFT (6U) +/*! PIO0_PIN6_SEC_MASK - Secure mask for pin P0_6 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_MASK (0x80U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_SHIFT (7U) +/*! PIO0_PIN7_SEC_MASK - Secure mask for pin P0_7 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_MASK (0x100U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_SHIFT (8U) +/*! PIO0_PIN8_SEC_MASK - Secure mask for pin P0_8 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_MASK (0x200U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_SHIFT (9U) +/*! PIO0_PIN9_SEC_MASK - Secure mask for pin P0_9 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_MASK (0x400U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_SHIFT (10U) +/*! PIO0_PIN10_SEC_MASK - Secure mask for pin P0_10 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_MASK (0x800U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_SHIFT (11U) +/*! PIO0_PIN11_SEC_MASK - Secure mask for pin P0_11 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_MASK (0x1000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_SHIFT (12U) +/*! PIO0_PIN12_SEC_MASK - Secure mask for pin P0_12 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_MASK (0x2000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_SHIFT (13U) +/*! PIO0_PIN13_SEC_MASK - Secure mask for pin P0_13 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_MASK (0x4000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_SHIFT (14U) +/*! PIO0_PIN14_SEC_MASK - Secure mask for pin P0_14 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_MASK (0x8000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_SHIFT (15U) +/*! PIO0_PIN15_SEC_MASK - Secure mask for pin P0_15 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_MASK (0x10000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_SHIFT (16U) +/*! PIO0_PIN16_SEC_MASK - Secure mask for pin P0_16 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_MASK (0x20000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_SHIFT (17U) +/*! PIO0_PIN17_SEC_MASK - Secure mask for pin P0_17 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_MASK (0x40000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_SHIFT (18U) +/*! PIO0_PIN18_SEC_MASK - Secure mask for pin P0_18 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_MASK (0x80000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_SHIFT (19U) +/*! PIO0_PIN19_SEC_MASK - Secure mask for pin P0_19 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_MASK (0x100000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_SHIFT (20U) +/*! PIO0_PIN20_SEC_MASK - Secure mask for pin P0_20 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_MASK (0x200000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_SHIFT (21U) +/*! PIO0_PIN21_SEC_MASK - Secure mask for pin P0_21 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_MASK (0x400000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_SHIFT (22U) +/*! PIO0_PIN22_SEC_MASK - Secure mask for pin P0_22 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_MASK (0x800000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_SHIFT (23U) +/*! PIO0_PIN23_SEC_MASK - Secure mask for pin P0_23 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_MASK (0x1000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_SHIFT (24U) +/*! PIO0_PIN24_SEC_MASK - Secure mask for pin P0_24 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_MASK (0x2000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_SHIFT (25U) +/*! PIO0_PIN25_SEC_MASK - Secure mask for pin P0_25 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_MASK (0x4000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_SHIFT (26U) +/*! PIO0_PIN26_SEC_MASK - Secure mask for pin P0_26 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_MASK (0x8000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_SHIFT (27U) +/*! PIO0_PIN27_SEC_MASK - Secure mask for pin P0_27 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_MASK (0x10000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_SHIFT (28U) +/*! PIO0_PIN28_SEC_MASK - Secure mask for pin P0_28 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_MASK (0x20000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_SHIFT (29U) +/*! PIO0_PIN29_SEC_MASK - Secure mask for pin P0_29 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_MASK (0x40000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_SHIFT (30U) +/*! PIO0_PIN30_SEC_MASK - Secure mask for pin P0_30 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_MASK (0x80000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_SHIFT (31U) +/*! PIO0_PIN31_SEC_MASK - Secure mask for pin P0_31 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_MASK) +/*! @} */ + +/*! @name SEC_GPIO_MASK1 - Secure GPIO mask for port 1 pins. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_MASK (0x1U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_SHIFT (0U) +/*! PIO1_PIN0_SEC_MASK - Secure mask for pin P1_0 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_MASK (0x2U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_SHIFT (1U) +/*! PIO1_PIN1_SEC_MASK - Secure mask for pin P1_1 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_MASK (0x4U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_SHIFT (2U) +/*! PIO1_PIN2_SEC_MASK - Secure mask for pin P1_2 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_MASK (0x8U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_SHIFT (3U) +/*! PIO1_PIN3_SEC_MASK - Secure mask for pin P1_3 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_MASK (0x10U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_SHIFT (4U) +/*! PIO1_PIN4_SEC_MASK - Secure mask for pin P1_4 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_MASK (0x20U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_SHIFT (5U) +/*! PIO1_PIN5_SEC_MASK - Secure mask for pin P1_5 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_MASK (0x40U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_SHIFT (6U) +/*! PIO1_PIN6_SEC_MASK - Secure mask for pin P1_6 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_MASK (0x80U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_SHIFT (7U) +/*! PIO1_PIN7_SEC_MASK - Secure mask for pin P1_7 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_MASK (0x100U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_SHIFT (8U) +/*! PIO1_PIN8_SEC_MASK - Secure mask for pin P1_8 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_MASK (0x200U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_SHIFT (9U) +/*! PIO1_PIN9_SEC_MASK - Secure mask for pin P1_9 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_MASK (0x400U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_SHIFT (10U) +/*! PIO1_PIN10_SEC_MASK - Secure mask for pin P1_10 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_MASK (0x800U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_SHIFT (11U) +/*! PIO1_PIN11_SEC_MASK - Secure mask for pin P1_11 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_MASK (0x1000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_SHIFT (12U) +/*! PIO1_PIN12_SEC_MASK - Secure mask for pin P1_12 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_MASK (0x2000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_SHIFT (13U) +/*! PIO1_PIN13_SEC_MASK - Secure mask for pin P1_13 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_MASK (0x4000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_SHIFT (14U) +/*! PIO1_PIN14_SEC_MASK - Secure mask for pin P1_14 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_MASK (0x8000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_SHIFT (15U) +/*! PIO1_PIN15_SEC_MASK - Secure mask for pin P1_15 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_MASK (0x10000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_SHIFT (16U) +/*! PIO1_PIN16_SEC_MASK - Secure mask for pin P1_16 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_MASK (0x20000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_SHIFT (17U) +/*! PIO1_PIN17_SEC_MASK - Secure mask for pin P1_17 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_MASK (0x40000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_SHIFT (18U) +/*! PIO1_PIN18_SEC_MASK - Secure mask for pin P1_18 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_MASK (0x80000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_SHIFT (19U) +/*! PIO1_PIN19_SEC_MASK - Secure mask for pin P1_19 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_MASK (0x100000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_SHIFT (20U) +/*! PIO1_PIN20_SEC_MASK - Secure mask for pin P1_20 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_MASK (0x200000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_SHIFT (21U) +/*! PIO1_PIN21_SEC_MASK - Secure mask for pin P1_21 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_MASK (0x400000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_SHIFT (22U) +/*! PIO1_PIN22_SEC_MASK - Secure mask for pin P1_22 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_MASK (0x800000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_SHIFT (23U) +/*! PIO1_PIN23_SEC_MASK - Secure mask for pin P1_23 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_MASK (0x1000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_SHIFT (24U) +/*! PIO1_PIN24_SEC_MASK - Secure mask for pin P1_24 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_MASK (0x2000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_SHIFT (25U) +/*! PIO1_PIN25_SEC_MASK - Secure mask for pin P1_25 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_MASK (0x4000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_SHIFT (26U) +/*! PIO1_PIN26_SEC_MASK - Secure mask for pin P1_26 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_MASK (0x8000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_SHIFT (27U) +/*! PIO1_PIN27_SEC_MASK - Secure mask for pin P1_27 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_MASK (0x10000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_SHIFT (28U) +/*! PIO1_PIN28_SEC_MASK - Secure mask for pin P1_28 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_MASK (0x20000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_SHIFT (29U) +/*! PIO1_PIN29_SEC_MASK - Secure mask for pin P1_29 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_MASK (0x40000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_SHIFT (30U) +/*! PIO1_PIN30_SEC_MASK - Secure mask for pin P1_30 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_MASK (0x80000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_SHIFT (31U) +/*! PIO1_PIN31_SEC_MASK - Secure mask for pin P1_31 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_MASK) +/*! @} */ + +/*! @name SEC_CPU_INT_MASK0 - Secure Interrupt mask for CPU1 */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ_MASK (0x1U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ_SHIFT (0U) +/*! SYS_IRQ - Watchdog Timer, Brown Out Detectors and Flash Controller interrupts + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ_MASK (0x2U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ_SHIFT (1U) +/*! SDMA0_IRQ - System DMA 0 (non-secure) interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ_MASK (0x4U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ_SHIFT (2U) +/*! GPIO_GLOBALINT0_IRQ - GPIO Group 0 interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ_MASK (0x8U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ_SHIFT (3U) +/*! GPIO_GLOBALINT1_IRQ - GPIO Group 1 interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0_MASK (0x10U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0_SHIFT (4U) +/*! GPIO_INT0_IRQ0 - Pin interrupt 0 or pattern match engine slice 0 interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1_MASK (0x20U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1_SHIFT (5U) +/*! GPIO_INT0_IRQ1 - Pin interrupt 1 or pattern match engine slice 1 interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2_MASK (0x40U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2_SHIFT (6U) +/*! GPIO_INT0_IRQ2 - Pin interrupt 2 or pattern match engine slice 2 interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3_MASK (0x80U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3_SHIFT (7U) +/*! GPIO_INT0_IRQ3 - Pin interrupt 3 or pattern match engine slice 3 interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ_MASK (0x100U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ_SHIFT (8U) +/*! UTICK_IRQ - Micro Tick Timer interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ_MASK (0x200U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ_SHIFT (9U) +/*! MRT_IRQ - Multi-Rate Timer interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ_MASK (0x400U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ_SHIFT (10U) +/*! CTIMER0_IRQ - Standard counter/timer 0 interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ_MASK (0x800U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ_SHIFT (11U) +/*! CTIMER1_IRQ - Standard counter/timer 1 interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ_MASK (0x1000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ_SHIFT (12U) +/*! SCT_IRQ - SCTimer/PWM interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ_MASK (0x2000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ_SHIFT (13U) +/*! CTIMER3_IRQ - Standard counter/timer 3 interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ_MASK (0x4000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ_SHIFT (14U) +/*! FLEXCOMM0_IRQ - Flexcomm 0 interrupt (USART, SPI, I2C, I2S). + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ_MASK (0x8000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ_SHIFT (15U) +/*! FLEXCOMM1_IRQ - Flexcomm 1 interrupt (USART, SPI, I2C, I2S). + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ_MASK (0x10000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ_SHIFT (16U) +/*! FLEXCOMM2_IRQ - Flexcomm 2 interrupt (USART, SPI, I2C, I2S). + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ_MASK (0x20000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ_SHIFT (17U) +/*! FLEXCOMM3_IRQ - Flexcomm 3 interrupt (USART, SPI, I2C, I2S). + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ_MASK (0x40000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ_SHIFT (18U) +/*! FLEXCOMM4_IRQ - Flexcomm 4 interrupt (USART, SPI, I2C, I2S). + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ_MASK (0x80000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ_SHIFT (19U) +/*! FLEXCOMM5_IRQ - Flexcomm 5 interrupt (USART, SPI, I2C, I2S). + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ_MASK (0x100000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ_SHIFT (20U) +/*! FLEXCOMM6_IRQ - Flexcomm 6 interrupt (USART, SPI, I2C, I2S). + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ_MASK (0x200000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ_SHIFT (21U) +/*! FLEXCOMM7_IRQ - Flexcomm 7 interrupt (USART, SPI, I2C, I2S). + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ_MASK (0x400000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ_SHIFT (22U) +/*! ADC_IRQ - General Purpose ADC interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0_MASK (0x800000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0_SHIFT (23U) +/*! RESERVED0 - Reserved. Read value is undefined, only zero should be written. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_CAPT0_IRQ_MASK (0x1000000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_CAPT0_IRQ_SHIFT (24U) +/*! ACMP_CAPT0_IRQ - Analog Comparator interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_CAPT0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_CAPT0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_CAPT0_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1_MASK (0x2000000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1_SHIFT (25U) +/*! RESERVED1 - Reserved. Read value is undefined, only zero should be written. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2_MASK (0x4000000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2_SHIFT (26U) +/*! RESERVED2 - Reserved. Read value is undefined, only zero should be written. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK_MASK (0x8000000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK_SHIFT (27U) +/*! USB0_NEEDCLK - USB Full Speed Controller Clock request interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ_MASK (0x10000000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ_SHIFT (28U) +/*! USB0_IRQ - USB High Speed Controller interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ_MASK (0x20000000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ_SHIFT (29U) +/*! RTC_IRQ - RTC_LITE0_ALARM_IRQ, RTC_LITE0_WAKEUP_IRQ + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3_MASK (0x40000000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3_SHIFT (30U) +/*! RESERVED3 - Reserved. Read value is undefined, only zero should be written. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ_MASK (0x80000000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ_SHIFT (31U) +/*! MAILBOX_IRQ - Mailbox interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ_MASK) +/*! @} */ + +/*! @name SEC_CPU_INT_MASK1 - Secure Interrupt mask for CPU1 */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4_MASK (0x1U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4_SHIFT (0U) +/*! GPIO_INT0_IRQ4 - Pin interrupt 4 or pattern match engine slice 4 interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5_MASK (0x2U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5_SHIFT (1U) +/*! GPIO_INT0_IRQ5 - Pin interrupt 5 or pattern match engine slice 5 interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6_MASK (0x4U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6_SHIFT (2U) +/*! GPIO_INT0_IRQ6 - Pin interrupt 6 or pattern match engine slice 6 interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7_MASK (0x8U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7_SHIFT (3U) +/*! GPIO_INT0_IRQ7 - Pin interrupt 7 or pattern match engine slice 7 interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ_MASK (0x10U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ_SHIFT (4U) +/*! CTIMER2_IRQ - Standard counter/timer 2 interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ_MASK (0x20U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ_SHIFT (5U) +/*! CTIMER4_IRQ - Standard counter/timer 4 interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ_MASK (0x40U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ_SHIFT (6U) +/*! OS_EVENT_TIMER_IRQ - OS Event Timer and OS Event Timer Wakeup interrupts + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0_MASK (0x80U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0_SHIFT (7U) +/*! RESERVED0 - Reserved. Read value is undefined, only zero should be written. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1_MASK (0x100U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1_SHIFT (8U) +/*! RESERVED1 - Reserved. Read value is undefined, only zero should be written. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2_MASK (0x200U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2_SHIFT (9U) +/*! RESERVED2 - Reserved. Read value is undefined, only zero should be written. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ_MASK (0x400U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ_SHIFT (10U) +/*! SDIO_IRQ - SDIO Controller interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3_MASK (0x800U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3_SHIFT (11U) +/*! RESERVED3 - Reserved. Read value is undefined, only zero should be written. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4_MASK (0x1000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4_SHIFT (12U) +/*! RESERVED4 - Reserved. Read value is undefined, only zero should be written. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5_MASK (0x2000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5_SHIFT (13U) +/*! RESERVED5 - Reserved. Read value is undefined, only zero should be written. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_UTMI_IRQ_MASK (0x4000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_UTMI_IRQ_SHIFT (14U) +/*! USB1_UTMI_IRQ - USB High Speed Controller UTMI interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_UTMI_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_UTMI_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_UTMI_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ_MASK (0x8000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ_SHIFT (15U) +/*! USB1_IRQ - USB High Speed Controller interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK_MASK (0x10000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK_SHIFT (16U) +/*! USB1_NEEDCLK - USB High Speed Controller Clock request interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ_MASK (0x20000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ_SHIFT (17U) +/*! SEC_HYPERVISOR_CALL_IRQ - Secure fault Hyper Visor call interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0_MASK (0x40000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0_SHIFT (18U) +/*! SEC_GPIO_INT0_IRQ0 - Secure Pin interrupt 0 or pattern match engine slice 0 interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1_MASK (0x80000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1_SHIFT (19U) +/*! SEC_GPIO_INT0_IRQ1 - Secure Pin interrupt 1 or pattern match engine slice 1 interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ_MASK (0x100000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ_SHIFT (20U) +/*! PLU_IRQ - Programmable Look-Up Controller interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ_MASK (0x200000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ_SHIFT (21U) +/*! SEC_VIO_IRQ - Security Violation interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ_MASK (0x400000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ_SHIFT (22U) +/*! SHA_IRQ - HASH-AES interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ_MASK (0x800000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ_SHIFT (23U) +/*! CASPER_IRQ - CASPER interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_QDDKEY_IRQ_MASK (0x1000000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_QDDKEY_IRQ_SHIFT (24U) +/*! QDDKEY_IRQ - PUF interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_QDDKEY_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_QDDKEY_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_QDDKEY_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ_MASK (0x2000000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ_SHIFT (25U) +/*! PQ_IRQ - Power Quad interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ_MASK (0x4000000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ_SHIFT (26U) +/*! SDMA1_IRQ - System DMA 1 (Secure) interrupt + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ_MASK (0x8000000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ_SHIFT (27U) +/*! LSPI_HS_IRQ - High Speed SPI interrupt + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ_MASK) +/*! @} */ + +/*! @name SEC_MASK_LOCK - Security General Purpose register access control. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_SHIFT (0U) +/*! SEC_GPIO_MASK0_LOCK - SEC_GPIO_MASK0 register write-lock. + * 0b10..Writable. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_MASK) +#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_MASK (0xCU) +#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_SHIFT (2U) +/*! SEC_GPIO_MASK1_LOCK - SEC_GPIO_MASK1 register write-lock. + * 0b10..Writable. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_MASK) +#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK_SHIFT (8U) +/*! SEC_CPU1_INT_MASK0_LOCK - SEC_CPU_INT_MASK0 register write-lock. + * 0b10..Writable. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK_MASK) +#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK_MASK (0xC00U) +#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK_SHIFT (10U) +/*! SEC_CPU1_INT_MASK1_LOCK - SEC_CPU_INT_MASK1 register write-lock. + * 0b10..Writable. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK_MASK) +/*! @} */ + +/*! @name MASTER_SEC_LEVEL - master secure level register */ +/*! @{ */ +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MCM33C_MASK (0x30U) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MCM33C_SHIFT (4U) +/*! MCM33C - Micro-CM33 (CPU1) Code bus. + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MCM33C(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MCM33C_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MCM33C_MASK) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MCM33S_MASK (0xC0U) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MCM33S_SHIFT (6U) +/*! MCM33S - Micro-CM33 (CPU1) System bus. + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MCM33S(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MCM33S_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MCM33S_MASK) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_MASK (0x300U) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_SHIFT (8U) +/*! USBFSD - USB Full Speed Device. + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_MASK) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_MASK (0xC00U) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_SHIFT (10U) +/*! SDMA0 - System DMA 0. + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_MASK) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO_MASK (0x30000U) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO_SHIFT (16U) +/*! SDIO - SDIO. + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO_MASK) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ_MASK (0xC0000U) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ_SHIFT (18U) +/*! PQ - Power Quad. + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ_MASK) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_MASK (0x300000U) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_SHIFT (20U) +/*! HASH - Hash. + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_MASK) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_MASK (0xC00000U) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_SHIFT (22U) +/*! USBFSH - USB Full speed Host. + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_MASK) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_MASK (0x3000000U) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_SHIFT (24U) +/*! SDMA1 - System DMA 1 security level. + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_MASK) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_MASK (0xC0000000U) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_SHIFT (30U) +/*! MASTER_SEC_LEVEL_LOCK - MASTER_SEC_LEVEL write-lock. + * 0b10..Writable. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_MASK) +/*! @} */ + +/*! @name MASTER_SEC_ANTI_POL_REG - master secure level anti-pole register */ +/*! @{ */ +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MCM33C_MASK (0x30U) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MCM33C_SHIFT (4U) +/*! MCM33C - Micro-CM33 (CPU1) Code bus. Must be equal to NOT(MASTER_SEC_LEVEL.MCM33C) + * 0b11..Non-secure and Non-priviledge user access allowed. + * 0b10..Non-secure and Privilege access allowed. + * 0b01..Secure and Non-priviledge user access allowed. + * 0b00..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MCM33C(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MCM33C_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MCM33C_MASK) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MCM33S_MASK (0xC0U) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MCM33S_SHIFT (6U) +/*! MCM33S - Micro-CM33 (CPU1) System bus. Must be equal to NOT(MASTER_SEC_LEVEL.MCM33S) + * 0b11..Non-secure and Non-priviledge user access allowed. + * 0b10..Non-secure and Privilege access allowed. + * 0b01..Secure and Non-priviledge user access allowed. + * 0b00..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MCM33S(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MCM33S_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MCM33S_MASK) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_MASK (0x300U) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_SHIFT (8U) +/*! USBFSD - USB Full Speed Device. Must be equal to NOT(MASTER_SEC_LEVEL.USBFSD) + * 0b11..Non-secure and Non-priviledge user access allowed. + * 0b10..Non-secure and Privilege access allowed. + * 0b01..Secure and Non-priviledge user access allowed. + * 0b00..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_MASK) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_MASK (0xC00U) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_SHIFT (10U) +/*! SDMA0 - System DMA 0. Must be equal to NOT(MASTER_SEC_LEVEL.SDMA0) + * 0b11..Non-secure and Non-priviledge user access allowed. + * 0b10..Non-secure and Privilege access allowed. + * 0b01..Secure and Non-priviledge user access allowed. + * 0b00..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_MASK) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO_MASK (0x30000U) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO_SHIFT (16U) +/*! SDIO - SDIO. Must be equal to NOT(MASTER_SEC_LEVEL.SDIO) + * 0b11..Non-secure and Non-priviledge user access allowed. + * 0b10..Non-secure and Privilege access allowed. + * 0b01..Secure and Non-priviledge user access allowed. + * 0b00..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO_MASK) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ_MASK (0xC0000U) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ_SHIFT (18U) +/*! PQ - Power Quad. Must be equal to NOT(MASTER_SEC_LEVEL.PQ) + * 0b11..Non-secure and Non-priviledge user access allowed. + * 0b10..Non-secure and Privilege access allowed. + * 0b01..Secure and Non-priviledge user access allowed. + * 0b00..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ_MASK) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_MASK (0x300000U) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_SHIFT (20U) +/*! HASH - Hash. Must be equal to NOT(MASTER_SEC_LEVEL.HASH) + * 0b11..Non-secure and Non-priviledge user access allowed. + * 0b10..Non-secure and Privilege access allowed. + * 0b01..Secure and Non-priviledge user access allowed. + * 0b00..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_MASK) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_MASK (0xC00000U) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_SHIFT (22U) +/*! USBFSH - USB Full speed Host. Must be equal to NOT(MASTER_SEC_LEVEL.USBFSH) + * 0b11..Non-secure and Non-priviledge user access allowed. + * 0b10..Non-secure and Privilege access allowed. + * 0b01..Secure and Non-priviledge user access allowed. + * 0b00..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_MASK) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_MASK (0x3000000U) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_SHIFT (24U) +/*! SDMA1 - System DMA 1 security level. Must be equal to NOT(MASTER_SEC_LEVEL.SDMA1) + * 0b11..Non-secure and Non-priviledge user access allowed. + * 0b10..Non-secure and Privilege access allowed. + * 0b01..Secure and Non-priviledge user access allowed. + * 0b00..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_MASK) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_MASK (0xC0000000U) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_SHIFT (30U) +/*! MASTER_SEC_LEVEL_ANTIPOL_LOCK - MASTER_SEC_ANTI_POL_REG register write-lock. + * 0b10..Writable. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_MASK) +/*! @} */ + +/*! @name CM33_LOCK_REG - Miscalleneous control signals for in CM33 (CPU0) */ +/*! @{ */ +#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_NS_VTOR_MASK (0x3U) +#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_NS_VTOR_SHIFT (0U) +/*! LOCK_NS_VTOR - CM33 (CPU0) VTOR_NS register write-lock. + * 0b10..Writable. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_NS_VTOR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_NS_VTOR_SHIFT)) & AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_NS_VTOR_MASK) +#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_NS_MPU_MASK (0xCU) +#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_NS_MPU_SHIFT (2U) +/*! LOCK_NS_MPU - CM33 (CPU0) non-secure MPU register write-lock. + * 0b10..Writable. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_NS_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_NS_MPU_SHIFT)) & AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_NS_MPU_MASK) +#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_S_VTAIRCR_MASK (0x30U) +#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_S_VTAIRCR_SHIFT (4U) +/*! LOCK_S_VTAIRCR - CM33 (CPU0) VTOR_S, AIRCR.PRIS, IRCR.BFHFNMINS registers write-lock. + * 0b10..Writable. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_S_VTAIRCR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_S_VTAIRCR_SHIFT)) & AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_S_VTAIRCR_MASK) +#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_S_MPU_MASK (0xC0U) +#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_S_MPU_SHIFT (6U) +/*! LOCK_S_MPU - CM33 (CPU0) Secure MPU registers write-lock. + * 0b10..Writable. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_S_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_S_MPU_SHIFT)) & AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_S_MPU_MASK) +#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_SAU_MASK (0x300U) +#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_SAU_SHIFT (8U) +/*! LOCK_SAU - CM33 (CPU0) SAU registers write-lock. + * 0b10..Writable. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_SAU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_SAU_SHIFT)) & AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_SAU_MASK) +#define AHB_SECURE_CTRL_CM33_LOCK_REG_CM33_LOCK_REG_LOCK_MASK (0xC0000000U) +#define AHB_SECURE_CTRL_CM33_LOCK_REG_CM33_LOCK_REG_LOCK_SHIFT (30U) +/*! CM33_LOCK_REG_LOCK - CM33_LOCK_REG write-lock. + * 0b10..Writable. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_CM33_LOCK_REG_CM33_LOCK_REG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CM33_LOCK_REG_CM33_LOCK_REG_LOCK_SHIFT)) & AHB_SECURE_CTRL_CM33_LOCK_REG_CM33_LOCK_REG_LOCK_MASK) +/*! @} */ + +/*! @name MCM33_LOCK_REG - Miscalleneous control signals for in micro-CM33 (CPU1) */ +/*! @{ */ +#define AHB_SECURE_CTRL_MCM33_LOCK_REG_LOCK_NS_VTOR_MASK (0x3U) +#define AHB_SECURE_CTRL_MCM33_LOCK_REG_LOCK_NS_VTOR_SHIFT (0U) +/*! LOCK_NS_VTOR - micro-CM33 (CPU1) VTOR_NS register write-lock. + * 0b10..Writable. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_MCM33_LOCK_REG_LOCK_NS_VTOR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MCM33_LOCK_REG_LOCK_NS_VTOR_SHIFT)) & AHB_SECURE_CTRL_MCM33_LOCK_REG_LOCK_NS_VTOR_MASK) +#define AHB_SECURE_CTRL_MCM33_LOCK_REG_LOCK_NS_MPU_MASK (0xCU) +#define AHB_SECURE_CTRL_MCM33_LOCK_REG_LOCK_NS_MPU_SHIFT (2U) +/*! LOCK_NS_MPU - micro-CM33 (CPU1) non-secure MPU register write-lock. + * 0b10..Writable. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_MCM33_LOCK_REG_LOCK_NS_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MCM33_LOCK_REG_LOCK_NS_MPU_SHIFT)) & AHB_SECURE_CTRL_MCM33_LOCK_REG_LOCK_NS_MPU_MASK) +#define AHB_SECURE_CTRL_MCM33_LOCK_REG_MCM33_LOCK_REG_LOCK_MASK (0xC0000000U) +#define AHB_SECURE_CTRL_MCM33_LOCK_REG_MCM33_LOCK_REG_LOCK_SHIFT (30U) +/*! MCM33_LOCK_REG_LOCK - MCM33_LOCK_REG write-lock. + * 0b10..Writable. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_MCM33_LOCK_REG_MCM33_LOCK_REG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MCM33_LOCK_REG_MCM33_LOCK_REG_LOCK_SHIFT)) & AHB_SECURE_CTRL_MCM33_LOCK_REG_MCM33_LOCK_REG_LOCK_MASK) +/*! @} */ + +/*! @name MISC_CTRL_DP_REG - secure control duplicate register */ +/*! @{ */ +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_MASK (0x3U) +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_SHIFT (0U) +/*! WRITE_LOCK - write lock. + * 0b10..Secure control registers can be written. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_MASK) +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_MASK (0xCU) +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_SHIFT (2U) +/*! ENABLE_SECURE_CHECKING - AHB bus matrix enable secure check. + * 0b10..Disable check. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_MASK) +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_MASK (0x30U) +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_SHIFT (4U) +/*! ENABLE_S_PRIV_CHECK - AHB bus matrix enable secure privilege check. + * 0b10..Disable check. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_MASK) +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_MASK (0xC0U) +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_SHIFT (6U) +/*! ENABLE_NS_PRIV_CHECK - AHB bus matrix enable non-secure privilege check. + * 0b10..Disable check. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_MASK) +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_MASK (0x300U) +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_SHIFT (8U) +/*! DISABLE_VIOLATION_ABORT - Disable secure violation abort. + * 0b10..Enable abort fort secure checker. + * 0b01..Disable abort fort secure checker. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_MASK) +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK (0xC00U) +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT (10U) +/*! DISABLE_SIMPLE_MASTER_STRICT_MODE - Disable simple master strict mode. + * 0b10..Simple master in strict mode. + * 0b01..Simple master in tier mode. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK) +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK (0x3000U) +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT (12U) +/*! DISABLE_SMART_MASTER_STRICT_MODE - Disable smart master strict mode. + * 0b10..Smart master in strict mode. + * 0b01..Smart master in tier mode. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK) +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_MASK (0xC000U) +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_SHIFT (14U) +/*! IDAU_ALL_NS - Disable IDAU. + * 0b10..IDAU is enabled. + * 0b01..IDAU is disable. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_MASK) +/*! @} */ + +/*! @name MISC_CTRL_REG - secure control register */ +/*! @{ */ +#define AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_MASK (0x3U) +#define AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_SHIFT (0U) +/*! WRITE_LOCK - write lock. + * 0b10..Secure control registers can be written. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_MASK) +#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_MASK (0xCU) +#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_SHIFT (2U) +/*! ENABLE_SECURE_CHECKING - AHB bus matrix enable secure check. + * 0b10..Disable check. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_MASK) +#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_MASK (0x30U) +#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_SHIFT (4U) +/*! ENABLE_S_PRIV_CHECK - AHB bus matrix enable secure privilege check. + * 0b10..Disable check. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_MASK) +#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_MASK (0xC0U) +#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_SHIFT (6U) +/*! ENABLE_NS_PRIV_CHECK - AHB bus matrix enable non-secure privilege check. + * 0b10..Disable check. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_MASK) +#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_MASK (0x300U) +#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_SHIFT (8U) +/*! DISABLE_VIOLATION_ABORT - Disable secure violation abort. + * 0b10..Enable abort fort secure checker. + * 0b01..Disable abort fort secure checker. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_MASK) +#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK (0xC00U) +#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT (10U) +/*! DISABLE_SIMPLE_MASTER_STRICT_MODE - Disable simple master strict mode. + * 0b10..Simple master in strict mode. + * 0b01..Simple master in tier mode. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK) +#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK (0x3000U) +#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT (12U) +/*! DISABLE_SMART_MASTER_STRICT_MODE - Disable smart master strict mode. + * 0b10..Smart master in strict mode. + * 0b01..Smart master in tier mode. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK) +#define AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_MASK (0xC000U) +#define AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_SHIFT (14U) +/*! IDAU_ALL_NS - Disable IDAU. + * 0b10..IDAU is enabled. + * 0b01..IDAU is disable. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group AHB_SECURE_CTRL_Register_Masks */ + + +/* AHB_SECURE_CTRL - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral AHB_SECURE_CTRL base address */ + #define AHB_SECURE_CTRL_BASE (0x500AC000u) + /** Peripheral AHB_SECURE_CTRL base address */ + #define AHB_SECURE_CTRL_BASE_NS (0x400AC000u) + /** Peripheral AHB_SECURE_CTRL base pointer */ + #define AHB_SECURE_CTRL ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_BASE) + /** Peripheral AHB_SECURE_CTRL base pointer */ + #define AHB_SECURE_CTRL_NS ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_BASE_NS) + /** Array initializer of AHB_SECURE_CTRL peripheral base addresses */ + #define AHB_SECURE_CTRL_BASE_ADDRS { AHB_SECURE_CTRL_BASE } + /** Array initializer of AHB_SECURE_CTRL peripheral base pointers */ + #define AHB_SECURE_CTRL_BASE_PTRS { AHB_SECURE_CTRL } + /** Array initializer of AHB_SECURE_CTRL peripheral base addresses */ + #define AHB_SECURE_CTRL_BASE_ADDRS_NS { AHB_SECURE_CTRL_BASE_NS } + /** Array initializer of AHB_SECURE_CTRL peripheral base pointers */ + #define AHB_SECURE_CTRL_BASE_PTRS_NS { AHB_SECURE_CTRL_NS } +#else + /** Peripheral AHB_SECURE_CTRL base address */ + #define AHB_SECURE_CTRL_BASE (0x400AC000u) + /** Peripheral AHB_SECURE_CTRL base pointer */ + #define AHB_SECURE_CTRL ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_BASE) + /** Array initializer of AHB_SECURE_CTRL peripheral base addresses */ + #define AHB_SECURE_CTRL_BASE_ADDRS { AHB_SECURE_CTRL_BASE } + /** Array initializer of AHB_SECURE_CTRL peripheral base pointers */ + #define AHB_SECURE_CTRL_BASE_PTRS { AHB_SECURE_CTRL } +#endif + +/*! + * @} + */ /* end of group AHB_SECURE_CTRL_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- ANACTRL Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ANACTRL_Peripheral_Access_Layer ANACTRL Peripheral Access Layer + * @{ + */ + +/** ANACTRL - Register Layout Typedef */ +typedef struct { + __IO uint32_t ANALOG_CTRL_CFG; /**< Various Analog blocks configuration (like FRO 192MHz trimmings source ...), offset: 0x0 */ + __I uint32_t ANALOG_CTRL_STATUS; /**< Analog Macroblock Identity registers, Flash Status registers, offset: 0x4 */ + uint8_t RESERVED_0[4]; + __IO uint32_t FREQ_ME_CTRL; /**< Frequency Measure function control register, offset: 0xC */ + __IO uint32_t FRO192M_CTRL; /**< 192MHz Free Running OScillator (FRO) Control register, offset: 0x10 */ + __I uint32_t FRO192M_STATUS; /**< 192MHz Free Running OScillator (FRO) Status register, offset: 0x14 */ + __IO uint32_t ADC_CTRL; /**< General Purpose ADC VBAT Divider branch control, offset: 0x18 */ + uint8_t RESERVED_1[4]; + __IO uint32_t XO32M_CTRL; /**< 32 MHz Crystal Oscillator Control register, offset: 0x20 */ + __I uint32_t XO32M_STATUS; /**< 32 MHz Crystal Oscillator Status register, offset: 0x24 */ + uint8_t RESERVED_2[8]; + __IO uint32_t BOD_DCDC_INT_CTRL; /**< Brown Out Detectors (BoDs) & DCDC interrupts generation control register, offset: 0x30 */ + __I uint32_t BOD_DCDC_INT_STATUS; /**< BoDs & DCDC interrupts status register, offset: 0x34 */ + uint8_t RESERVED_3[8]; + __IO uint32_t RINGO0_CTRL; /**< First Ring Oscillator module control register., offset: 0x40 */ + __IO uint32_t RINGO1_CTRL; /**< Second Ring Oscillator module control register., offset: 0x44 */ + __IO uint32_t RINGO2_CTRL; /**< Third Ring Oscillator module control register., offset: 0x48 */ + uint8_t RESERVED_4[100]; + __IO uint32_t LDO_XO32M; /**< High Speed Crystal Oscillator (12 MHz - 32 MHz) Voltage Source Supply Control register, offset: 0xB0 */ + uint8_t RESERVED_5[12]; + __IO uint32_t XO_CAL_CFG; /**< All Crystal Oscillators (both the 32 KHz and the High speed) Capacitive Banks Calibration Configuration register, offset: 0xC0 */ + __IO uint32_t XO_CAL_CMD; /**< All Crystal Oscillators (both the 32 KHz and the High Speed) Capacitive Banks Calibration Command register., offset: 0xC4 */ + __I uint32_t XO_CAL_STATUS; /**< All Crystal Oscillators (both the 32 KHz and the High speed) Capacitive Banks Calibration Status register., offset: 0xC8 */ + uint8_t RESERVED_6[52]; + __IO uint32_t USBHS_PHY_CTRL; /**< USB High Speed Phy Control, offset: 0x100 */ + __IO uint32_t USBHS_PHY_TRIM; /**< USB High Speed Phy Trim values, offset: 0x104 */ + __I uint32_t USBHS_PHY_STATUS; /**< USB High Speed Phy Status, offset: 0x108 */ +} ANACTRL_Type; + +/* ---------------------------------------------------------------------------- + -- ANACTRL Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ANACTRL_Register_Masks ANACTRL Register Masks + * @{ + */ + +/*! @name ANALOG_CTRL_CFG - Various Analog blocks configuration (like FRO 192MHz trimmings source ...) */ +/*! @{ */ +#define ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC_MASK (0x1U) +#define ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC_SHIFT (0U) +/*! FRO192M_TRIM_SRC - FRO192M trimming and 'Enable' source. + * 0b0..FRO192M trimming and 'Enable' comes from eFUSE. + * 0b1..FRO192M trimming and 'Enable' comes from FRO192M_CTRL registers. + */ +#define ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC_SHIFT)) & ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC_MASK) +/*! @} */ + +/*! @name ANALOG_CTRL_STATUS - Analog Macroblock Identity registers, Flash Status registers */ +/*! @{ */ +#define ANACTRL_ANALOG_CTRL_STATUS_PMU_ID_MASK (0x3FU) +#define ANACTRL_ANALOG_CTRL_STATUS_PMU_ID_SHIFT (0U) +#define ANACTRL_ANALOG_CTRL_STATUS_PMU_ID(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_STATUS_PMU_ID_SHIFT)) & ANACTRL_ANALOG_CTRL_STATUS_PMU_ID_MASK) +#define ANACTRL_ANALOG_CTRL_STATUS_OSC_ID_MASK (0xFC0U) +#define ANACTRL_ANALOG_CTRL_STATUS_OSC_ID_SHIFT (6U) +#define ANACTRL_ANALOG_CTRL_STATUS_OSC_ID(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_STATUS_OSC_ID_SHIFT)) & ANACTRL_ANALOG_CTRL_STATUS_OSC_ID_MASK) +#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_MASK (0x1000U) +#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_SHIFT (12U) +/*! FLASH_PWRDWN - Flash Power Down status. + * 0b0..Flash is not in power down mode. + * 0b1..Flash is in power down mode. + */ +#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_SHIFT)) & ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_MASK) +#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_MASK (0x2000U) +#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_SHIFT (13U) +/*! FLASH_INIT_ERROR - Flash initialization error status. + * 0b0..No error. + * 0b1..At least one error occured during flash initialization.. + */ +#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_SHIFT)) & ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_MASK) +#define ANACTRL_ANALOG_CTRL_STATUS_FINAL_TEST_DONE_VECT_MASK (0xF0000000U) +#define ANACTRL_ANALOG_CTRL_STATUS_FINAL_TEST_DONE_VECT_SHIFT (28U) +#define ANACTRL_ANALOG_CTRL_STATUS_FINAL_TEST_DONE_VECT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_STATUS_FINAL_TEST_DONE_VECT_SHIFT)) & ANACTRL_ANALOG_CTRL_STATUS_FINAL_TEST_DONE_VECT_MASK) +/*! @} */ + +/*! @name FREQ_ME_CTRL - Frequency Measure function control register */ +/*! @{ */ +#define ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_MASK (0x7FFFFFFFU) +#define ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_SHIFT (0U) +#define ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_SHIFT)) & ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_MASK) +#define ANACTRL_FREQ_ME_CTRL_PROG_MASK (0x80000000U) +#define ANACTRL_FREQ_ME_CTRL_PROG_SHIFT (31U) +#define ANACTRL_FREQ_ME_CTRL_PROG(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FREQ_ME_CTRL_PROG_SHIFT)) & ANACTRL_FREQ_ME_CTRL_PROG_MASK) +/*! @} */ + +/*! @name FRO192M_CTRL - 192MHz Free Running OScillator (FRO) Control register */ +/*! @{ */ +#define ANACTRL_FRO192M_CTRL_BIAS_TRIM_MASK (0x3FU) +#define ANACTRL_FRO192M_CTRL_BIAS_TRIM_SHIFT (0U) +#define ANACTRL_FRO192M_CTRL_BIAS_TRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_BIAS_TRIM_SHIFT)) & ANACTRL_FRO192M_CTRL_BIAS_TRIM_MASK) +#define ANACTRL_FRO192M_CTRL_TEMP_TRIM_MASK (0x3F80U) +#define ANACTRL_FRO192M_CTRL_TEMP_TRIM_SHIFT (7U) +#define ANACTRL_FRO192M_CTRL_TEMP_TRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_TEMP_TRIM_SHIFT)) & ANACTRL_FRO192M_CTRL_TEMP_TRIM_MASK) +#define ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK (0x4000U) +#define ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_SHIFT (14U) +/*! ENA_12MHZCLK - 12 MHz clock control. + * 0b0..12 MHz clock is disabled. + * 0b1..12 MHz clock is enabled. + */ +#define ANACTRL_FRO192M_CTRL_ENA_12MHZCLK(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_SHIFT)) & ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK) +#define ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_MASK (0x8000U) +#define ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_SHIFT (15U) +/*! ENA_48MHZCLK - 48 MHz clock control. + * 0b0..48 MHz clock is disabled. + * 0b1..48 MHz clock is enabled. + */ +#define ANACTRL_FRO192M_CTRL_ENA_48MHZCLK(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_SHIFT)) & ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_MASK) +#define ANACTRL_FRO192M_CTRL_DAC_TRIM_MASK (0xFF0000U) +#define ANACTRL_FRO192M_CTRL_DAC_TRIM_SHIFT (16U) +#define ANACTRL_FRO192M_CTRL_DAC_TRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_DAC_TRIM_SHIFT)) & ANACTRL_FRO192M_CTRL_DAC_TRIM_MASK) +#define ANACTRL_FRO192M_CTRL_USBCLKADJ_MASK (0x1000000U) +#define ANACTRL_FRO192M_CTRL_USBCLKADJ_SHIFT (24U) +#define ANACTRL_FRO192M_CTRL_USBCLKADJ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_USBCLKADJ_SHIFT)) & ANACTRL_FRO192M_CTRL_USBCLKADJ_MASK) +#define ANACTRL_FRO192M_CTRL_USBMODCHG_MASK (0x2000000U) +#define ANACTRL_FRO192M_CTRL_USBMODCHG_SHIFT (25U) +#define ANACTRL_FRO192M_CTRL_USBMODCHG(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_USBMODCHG_SHIFT)) & ANACTRL_FRO192M_CTRL_USBMODCHG_MASK) +#define ANACTRL_FRO192M_CTRL_ATB_CTRL_MASK (0x30000000U) +#define ANACTRL_FRO192M_CTRL_ATB_CTRL_SHIFT (28U) +#define ANACTRL_FRO192M_CTRL_ATB_CTRL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_ATB_CTRL_SHIFT)) & ANACTRL_FRO192M_CTRL_ATB_CTRL_MASK) +#define ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK (0x40000000U) +#define ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_SHIFT (30U) +/*! ENA_96MHZCLK - 96 MHz clock control. + * 0b0..96 MHz clock is disabled. + * 0b1..96 MHz clock is enabled. + */ +#define ANACTRL_FRO192M_CTRL_ENA_96MHZCLK(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_SHIFT)) & ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK) +#define ANACTRL_FRO192M_CTRL_WRTRIM_MASK (0x80000000U) +#define ANACTRL_FRO192M_CTRL_WRTRIM_SHIFT (31U) +#define ANACTRL_FRO192M_CTRL_WRTRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_WRTRIM_SHIFT)) & ANACTRL_FRO192M_CTRL_WRTRIM_MASK) +/*! @} */ + +/*! @name FRO192M_STATUS - 192MHz Free Running OScillator (FRO) Status register */ +/*! @{ */ +#define ANACTRL_FRO192M_STATUS_CLK_VALID_MASK (0x1U) +#define ANACTRL_FRO192M_STATUS_CLK_VALID_SHIFT (0U) +/*! CLK_VALID - Output clock valid signal. Indicates that CCO clock has settled. + * 0b0..No output clock present (None of 12 MHz, 48 MHz or 96 MHz clock is available). + * 0b1..Clock is present (12 MHz, 48 MHz or 96 MHz can be output if they are enable respectively by + * FRO192M_CTRL.ENA_12MHZCLK/ENA_48MHZCLK/ENA_96MHZCLK). + */ +#define ANACTRL_FRO192M_STATUS_CLK_VALID(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_STATUS_CLK_VALID_SHIFT)) & ANACTRL_FRO192M_STATUS_CLK_VALID_MASK) +#define ANACTRL_FRO192M_STATUS_ATB_VCTRL_MASK (0x2U) +#define ANACTRL_FRO192M_STATUS_ATB_VCTRL_SHIFT (1U) +#define ANACTRL_FRO192M_STATUS_ATB_VCTRL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_STATUS_ATB_VCTRL_SHIFT)) & ANACTRL_FRO192M_STATUS_ATB_VCTRL_MASK) +/*! @} */ + +/*! @name ADC_CTRL - General Purpose ADC VBAT Divider branch control */ +/*! @{ */ +#define ANACTRL_ADC_CTRL_VBATDIVENABLE_MASK (0x1U) +#define ANACTRL_ADC_CTRL_VBATDIVENABLE_SHIFT (0U) +/*! VBATDIVENABLE - Switch On/Off VBAT divider branch. + * 0b0..VBAT divider branch is disabled. + * 0b1..VBAT divider branch is enabled. + */ +#define ANACTRL_ADC_CTRL_VBATDIVENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ADC_CTRL_VBATDIVENABLE_SHIFT)) & ANACTRL_ADC_CTRL_VBATDIVENABLE_MASK) +/*! @} */ + +/*! @name XO32M_CTRL - 32 MHz Crystal Oscillator Control register */ +/*! @{ */ +#define ANACTRL_XO32M_CTRL_GM_MASK (0xEU) +#define ANACTRL_XO32M_CTRL_GM_SHIFT (1U) +#define ANACTRL_XO32M_CTRL_GM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_GM_SHIFT)) & ANACTRL_XO32M_CTRL_GM_MASK) +#define ANACTRL_XO32M_CTRL_SLAVE_MASK (0x10U) +#define ANACTRL_XO32M_CTRL_SLAVE_SHIFT (4U) +#define ANACTRL_XO32M_CTRL_SLAVE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_SLAVE_SHIFT)) & ANACTRL_XO32M_CTRL_SLAVE_MASK) +#define ANACTRL_XO32M_CTRL_AMP_MASK (0xE0U) +#define ANACTRL_XO32M_CTRL_AMP_SHIFT (5U) +#define ANACTRL_XO32M_CTRL_AMP(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_AMP_SHIFT)) & ANACTRL_XO32M_CTRL_AMP_MASK) +#define ANACTRL_XO32M_CTRL_OSC_CAP_IN_MASK (0x7F00U) +#define ANACTRL_XO32M_CTRL_OSC_CAP_IN_SHIFT (8U) +#define ANACTRL_XO32M_CTRL_OSC_CAP_IN(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_OSC_CAP_IN_SHIFT)) & ANACTRL_XO32M_CTRL_OSC_CAP_IN_MASK) +#define ANACTRL_XO32M_CTRL_OSC_CAP_OUT_MASK (0x3F8000U) +#define ANACTRL_XO32M_CTRL_OSC_CAP_OUT_SHIFT (15U) +#define ANACTRL_XO32M_CTRL_OSC_CAP_OUT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_OSC_CAP_OUT_SHIFT)) & ANACTRL_XO32M_CTRL_OSC_CAP_OUT_MASK) +#define ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK (0x400000U) +#define ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_SHIFT (22U) +/*! ACBUF_PASS_ENABLE - Bypass enable of XO AC buffer enable in pll and top level. + * 0b0..XO AC buffer bypass is disabled. + * 0b1..XO AC buffer bypass is enabled. + */ +#define ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_SHIFT)) & ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK) +#define ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK (0x800000U) +#define ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_SHIFT (23U) +/*! ENABLE_PLL_USB_OUT - Enable XO 32 MHz output to USB HS PLL. + * 0b0..XO 32 MHz output to USB HS PLL is disabled. + * 0b1..XO 32 MHz output to USB HS PLL is enabled. + */ +#define ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_SHIFT)) & ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK) +#define ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK (0x1000000U) +#define ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_SHIFT (24U) +/*! ENABLE_SYSTEM_CLK_OUT - Enable XO 32 MHz output to CPU system. + * 0b0..XO 32 MHz output to CPU system is disabled. + * 0b1..XO 32 MHz output to CPU system is enabled. + */ +#define ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_SHIFT)) & ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK) +#define ANACTRL_XO32M_CTRL_CAPTESTSTARTSRCSEL_MASK (0x2000000U) +#define ANACTRL_XO32M_CTRL_CAPTESTSTARTSRCSEL_SHIFT (25U) +/*! CAPTESTSTARTSRCSEL - Source selection for 'xo32k_captest_start' signal. + * 0b0..Sourced from CAPTESTSTART. + * 0b1..Sourced from calibration. + */ +#define ANACTRL_XO32M_CTRL_CAPTESTSTARTSRCSEL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_CAPTESTSTARTSRCSEL_SHIFT)) & ANACTRL_XO32M_CTRL_CAPTESTSTARTSRCSEL_MASK) +#define ANACTRL_XO32M_CTRL_CAPTESTSTART_MASK (0x4000000U) +#define ANACTRL_XO32M_CTRL_CAPTESTSTART_SHIFT (26U) +#define ANACTRL_XO32M_CTRL_CAPTESTSTART(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_CAPTESTSTART_SHIFT)) & ANACTRL_XO32M_CTRL_CAPTESTSTART_MASK) +#define ANACTRL_XO32M_CTRL_CAPTESTENABLE_MASK (0x8000000U) +#define ANACTRL_XO32M_CTRL_CAPTESTENABLE_SHIFT (27U) +/*! CAPTESTENABLE - Enable signal for captest. + * 0b0..Captest is disabled. + * 0b1..Captest is enabled. + */ +#define ANACTRL_XO32M_CTRL_CAPTESTENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_CAPTESTENABLE_SHIFT)) & ANACTRL_XO32M_CTRL_CAPTESTENABLE_MASK) +#define ANACTRL_XO32M_CTRL_CAPTESTOSCINSEL_MASK (0x10000000U) +#define ANACTRL_XO32M_CTRL_CAPTESTOSCINSEL_SHIFT (28U) +/*! CAPTESTOSCINSEL - Select the input for test. + * 0b0..osc_out (oscillator output) pin. + * 0b1..osc_in (oscillator) pin. + */ +#define ANACTRL_XO32M_CTRL_CAPTESTOSCINSEL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_CAPTESTOSCINSEL_SHIFT)) & ANACTRL_XO32M_CTRL_CAPTESTOSCINSEL_MASK) +/*! @} */ + +/*! @name XO32M_STATUS - 32 MHz Crystal Oscillator Status register */ +/*! @{ */ +#define ANACTRL_XO32M_STATUS_XO_READY_MASK (0x1U) +#define ANACTRL_XO32M_STATUS_XO_READY_SHIFT (0U) +/*! XO_READY - Indicates XO out frequency statibilty. + * 0b0..XO output frequency is not yet stable. + * 0b1..XO output frequency is stable. + */ +#define ANACTRL_XO32M_STATUS_XO_READY(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_STATUS_XO_READY_SHIFT)) & ANACTRL_XO32M_STATUS_XO_READY_MASK) +/*! @} */ + +/*! @name BOD_DCDC_INT_CTRL - Brown Out Detectors (BoDs) & DCDC interrupts generation control register */ +/*! @{ */ +#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_MASK (0x1U) +#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_SHIFT (0U) +/*! BODVBAT_INT_ENABLE - BOD VBAT interrupt control. + * 0b0..BOD VBAT interrupt is disabled. + * 0b1..BOD VBAT interrupt is enabled. + */ +#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_MASK) +#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_MASK (0x2U) +#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_SHIFT (1U) +#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_MASK) +#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_MASK (0x4U) +#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_SHIFT (2U) +/*! BODCORE_INT_ENABLE - BOD CORE interrupt control. + * 0b0..BOD CORE interrupt is disabled. + * 0b1..BOD CORE interrupt is enabled. + */ +#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_MASK) +#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_MASK (0x8U) +#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_SHIFT (3U) +#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_MASK) +#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_MASK (0x10U) +#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_SHIFT (4U) +/*! DCDC_INT_ENABLE - DCDC interrupt control. + * 0b0..DCDC interrupt is disabled. + * 0b1..DCDC interrupt is enabled. + */ +#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_MASK) +#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_MASK (0x20U) +#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_SHIFT (5U) +#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_MASK) +/*! @} */ + +/*! @name BOD_DCDC_INT_STATUS - BoDs & DCDC interrupts status register */ +/*! @{ */ +#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_MASK (0x1U) +#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_SHIFT (0U) +/*! BODVBAT_STATUS - BOD VBAT Interrupt status before Interrupt Enable. + * 0b0..No interrupt pending.. + * 0b1..Interrupt pending.. + */ +#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_MASK) +#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_MASK (0x2U) +#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_SHIFT (1U) +/*! BODVBAT_INT_STATUS - BOD VBAT Interrupt status after Interrupt Enable. + * 0b0..No interrupt pending.. + * 0b1..Interrupt pending.. + */ +#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_MASK) +#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_MASK (0x4U) +#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_SHIFT (2U) +/*! BODVBAT_VAL - Current value of BOD VBAT power status output. + * 0b0..VBAT voltage level is below the threshold. + * 0b1..VBAT voltage level is above the threshold. + */ +#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_MASK) +#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_MASK (0x8U) +#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_SHIFT (3U) +/*! BODCORE_STATUS - BOD CORE Interrupt status before Interrupt Enable. + * 0b0..No interrupt pending.. + * 0b1..Interrupt pending.. + */ +#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_MASK) +#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_MASK (0x10U) +#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_SHIFT (4U) +/*! BODCORE_INT_STATUS - BOD CORE Interrupt status after Interrupt Enable. + * 0b0..No interrupt pending.. + * 0b1..Interrupt pending.. + */ +#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_MASK) +#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_MASK (0x20U) +#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_SHIFT (5U) +/*! BODCORE_VAL - Current value of BOD CORE power status output. + * 0b0..CORE voltage level is below the threshold. + * 0b1..CORE voltage level is above the threshold. + */ +#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_MASK) +#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_MASK (0x40U) +#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_SHIFT (6U) +/*! DCDC_STATUS - DCDC Interrupt status before Interrupt Enable. + * 0b0..No interrupt pending.. + * 0b1..Interrupt pending.. + */ +#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_MASK) +#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_MASK (0x80U) +#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_SHIFT (7U) +/*! DCDC_INT_STATUS - DCDC Interrupt status after Interrupt Enable. + * 0b0..No interrupt pending.. + * 0b1..Interrupt pending.. + */ +#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_MASK) +#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_MASK (0x100U) +#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_SHIFT (8U) +/*! DCDC_VAL - Current value of DCDC power status output. + * 0b0..DCDC output Voltage is below the targeted regulation level. + * 0b1..DCDC output Voltage is above the targeted regulation level. + */ +#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_MASK) +/*! @} */ + +/*! @name RINGO0_CTRL - First Ring Oscillator module control register. */ +/*! @{ */ +#define ANACTRL_RINGO0_CTRL_SL_MASK (0x1U) +#define ANACTRL_RINGO0_CTRL_SL_SHIFT (0U) +/*! SL - Select short or long ringo (for all ringos types). + * 0b0..Select short ringo (few elements). + * 0b1..Select long ringo (many elements). + */ +#define ANACTRL_RINGO0_CTRL_SL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_SL_SHIFT)) & ANACTRL_RINGO0_CTRL_SL_MASK) +#define ANACTRL_RINGO0_CTRL_FS_MASK (0x2U) +#define ANACTRL_RINGO0_CTRL_FS_SHIFT (1U) +/*! FS - Ringo frequency output divider. + * 0b0..High frequency output (frequency lower than 100 MHz). + * 0b1..Low frequency output (frequency lower than 10 MHz). + */ +#define ANACTRL_RINGO0_CTRL_FS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_FS_SHIFT)) & ANACTRL_RINGO0_CTRL_FS_MASK) +#define ANACTRL_RINGO0_CTRL_SWN_SWP_MASK (0xCU) +#define ANACTRL_RINGO0_CTRL_SWN_SWP_SHIFT (2U) +/*! SWN_SWP - PN-Ringos (P-Transistor and N-Transistor processing) control. + * 0b00..Normal mode. + * 0b01..P-Monitor mode. Measure with weak P transistor. + * 0b10..P-Monitor mode. Measure with weak N transistor. + * 0b11..Don't use. + */ +#define ANACTRL_RINGO0_CTRL_SWN_SWP(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_SWN_SWP_SHIFT)) & ANACTRL_RINGO0_CTRL_SWN_SWP_MASK) +#define ANACTRL_RINGO0_CTRL_PD_MASK (0x10U) +#define ANACTRL_RINGO0_CTRL_PD_SHIFT (4U) +/*! PD - Ringo module Power control. + * 0b0..The Ringo module is enabled. + * 0b1..The Ringo module is disabled. + */ +#define ANACTRL_RINGO0_CTRL_PD(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_PD_SHIFT)) & ANACTRL_RINGO0_CTRL_PD_MASK) +#define ANACTRL_RINGO0_CTRL_E_ND0_MASK (0x20U) +#define ANACTRL_RINGO0_CTRL_E_ND0_SHIFT (5U) +/*! E_ND0 - First NAND2-based ringo control. + * 0b0..First NAND2-based ringo is disabled. + * 0b1..First NAND2-based ringo is enabled. + */ +#define ANACTRL_RINGO0_CTRL_E_ND0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_ND0_SHIFT)) & ANACTRL_RINGO0_CTRL_E_ND0_MASK) +#define ANACTRL_RINGO0_CTRL_E_ND1_MASK (0x40U) +#define ANACTRL_RINGO0_CTRL_E_ND1_SHIFT (6U) +/*! E_ND1 - Second NAND2-based ringo control. + * 0b0..Second NAND2-based ringo is disabled. + * 0b1..Second NAND2-based ringo is enabled. + */ +#define ANACTRL_RINGO0_CTRL_E_ND1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_ND1_SHIFT)) & ANACTRL_RINGO0_CTRL_E_ND1_MASK) +#define ANACTRL_RINGO0_CTRL_E_NR0_MASK (0x80U) +#define ANACTRL_RINGO0_CTRL_E_NR0_SHIFT (7U) +/*! E_NR0 - First NOR2-based ringo control. + * 0b0..First NOR2-based ringo is disabled. + * 0b1..First NOR2-based ringo is enabled. + */ +#define ANACTRL_RINGO0_CTRL_E_NR0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_NR0_SHIFT)) & ANACTRL_RINGO0_CTRL_E_NR0_MASK) +#define ANACTRL_RINGO0_CTRL_E_NR1_MASK (0x100U) +#define ANACTRL_RINGO0_CTRL_E_NR1_SHIFT (8U) +/*! E_NR1 - Second NOR2-based ringo control. + * 0b0..Second NORD2-based ringo is disabled. + * 0b1..Second NORD2-based ringo is enabled. + */ +#define ANACTRL_RINGO0_CTRL_E_NR1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_NR1_SHIFT)) & ANACTRL_RINGO0_CTRL_E_NR1_MASK) +#define ANACTRL_RINGO0_CTRL_E_IV0_MASK (0x200U) +#define ANACTRL_RINGO0_CTRL_E_IV0_SHIFT (9U) +/*! E_IV0 - First Inverter-based ringo control. + * 0b0..First INV-based ringo is disabled. + * 0b1..First INV-based ringo is enabled. + */ +#define ANACTRL_RINGO0_CTRL_E_IV0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_IV0_SHIFT)) & ANACTRL_RINGO0_CTRL_E_IV0_MASK) +#define ANACTRL_RINGO0_CTRL_E_IV1_MASK (0x400U) +#define ANACTRL_RINGO0_CTRL_E_IV1_SHIFT (10U) +/*! E_IV1 - Second Inverter-based ringo control. + * 0b0..Second INV-based ringo is disabled. + * 0b1..Second INV-based ringo is enabled. + */ +#define ANACTRL_RINGO0_CTRL_E_IV1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_IV1_SHIFT)) & ANACTRL_RINGO0_CTRL_E_IV1_MASK) +#define ANACTRL_RINGO0_CTRL_E_PN0_MASK (0x800U) +#define ANACTRL_RINGO0_CTRL_E_PN0_SHIFT (11U) +/*! E_PN0 - First PN (P-Transistor and N-Transistor processing) monitor control. + * 0b0..First PN-based ringo is disabled. + * 0b1..First PN-based ringo is enabled. + */ +#define ANACTRL_RINGO0_CTRL_E_PN0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_PN0_SHIFT)) & ANACTRL_RINGO0_CTRL_E_PN0_MASK) +#define ANACTRL_RINGO0_CTRL_E_PN1_MASK (0x1000U) +#define ANACTRL_RINGO0_CTRL_E_PN1_SHIFT (12U) +/*! E_PN1 - Second PN (P-Transistor and N-Transistor processing) monitor control. + * 0b0..Second PN-based ringo is disabled. + * 0b1..Second PN-based ringo is enabled. + */ +#define ANACTRL_RINGO0_CTRL_E_PN1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_PN1_SHIFT)) & ANACTRL_RINGO0_CTRL_E_PN1_MASK) +#define ANACTRL_RINGO0_CTRL_DIVISOR_MASK (0xF0000U) +#define ANACTRL_RINGO0_CTRL_DIVISOR_SHIFT (16U) +#define ANACTRL_RINGO0_CTRL_DIVISOR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_DIVISOR_SHIFT)) & ANACTRL_RINGO0_CTRL_DIVISOR_MASK) +#define ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_MASK (0x80000000U) +#define ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_SHIFT (31U) +#define ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_SHIFT)) & ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_MASK) +/*! @} */ + +/*! @name RINGO1_CTRL - Second Ring Oscillator module control register. */ +/*! @{ */ +#define ANACTRL_RINGO1_CTRL_S_MASK (0x1U) +#define ANACTRL_RINGO1_CTRL_S_SHIFT (0U) +/*! S - Select short or long ringo (for all ringos types). + * 0b0..Select short ringo (few elements). + * 0b1..Select long ringo (many elements). + */ +#define ANACTRL_RINGO1_CTRL_S(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_S_SHIFT)) & ANACTRL_RINGO1_CTRL_S_MASK) +#define ANACTRL_RINGO1_CTRL_FS_MASK (0x2U) +#define ANACTRL_RINGO1_CTRL_FS_SHIFT (1U) +/*! FS - Ringo frequency output divider. + * 0b0..High frequency output (frequency lower than 100 MHz). + * 0b1..Low frequency output (frequency lower than 10 MHz). + */ +#define ANACTRL_RINGO1_CTRL_FS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_FS_SHIFT)) & ANACTRL_RINGO1_CTRL_FS_MASK) +#define ANACTRL_RINGO1_CTRL_PD_MASK (0x4U) +#define ANACTRL_RINGO1_CTRL_PD_SHIFT (2U) +/*! PD - Ringo module Power control. + * 0b0..The Ringo module is enabled. + * 0b1..The Ringo module is disabled. + */ +#define ANACTRL_RINGO1_CTRL_PD(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_PD_SHIFT)) & ANACTRL_RINGO1_CTRL_PD_MASK) +#define ANACTRL_RINGO1_CTRL_E_R24_MASK (0x8U) +#define ANACTRL_RINGO1_CTRL_E_R24_SHIFT (3U) +/*! E_R24 - . + * 0b0..Ringo is disabled. + * 0b1..Ringo is enabled. + */ +#define ANACTRL_RINGO1_CTRL_E_R24(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_R24_SHIFT)) & ANACTRL_RINGO1_CTRL_E_R24_MASK) +#define ANACTRL_RINGO1_CTRL_E_R35_MASK (0x10U) +#define ANACTRL_RINGO1_CTRL_E_R35_SHIFT (4U) +/*! E_R35 - . + * 0b0..Ringo is disabled. + * 0b1..Ringo is enabled. + */ +#define ANACTRL_RINGO1_CTRL_E_R35(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_R35_SHIFT)) & ANACTRL_RINGO1_CTRL_E_R35_MASK) +#define ANACTRL_RINGO1_CTRL_E_M2_MASK (0x20U) +#define ANACTRL_RINGO1_CTRL_E_M2_SHIFT (5U) +/*! E_M2 - Metal 2 (M2) monitor control. + * 0b0..Ringo is disabled. + * 0b1..Ringo is enabled. + */ +#define ANACTRL_RINGO1_CTRL_E_M2(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_M2_SHIFT)) & ANACTRL_RINGO1_CTRL_E_M2_MASK) +#define ANACTRL_RINGO1_CTRL_E_M3_MASK (0x40U) +#define ANACTRL_RINGO1_CTRL_E_M3_SHIFT (6U) +/*! E_M3 - Metal 3 (M3) monitor control. + * 0b0..Ringo is disabled. + * 0b1..Ringo is enabled. + */ +#define ANACTRL_RINGO1_CTRL_E_M3(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_M3_SHIFT)) & ANACTRL_RINGO1_CTRL_E_M3_MASK) +#define ANACTRL_RINGO1_CTRL_E_M4_MASK (0x80U) +#define ANACTRL_RINGO1_CTRL_E_M4_SHIFT (7U) +/*! E_M4 - Metal 4 (M4) monitor control. + * 0b0..Ringo is disabled. + * 0b1..Ringo is enabled. + */ +#define ANACTRL_RINGO1_CTRL_E_M4(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_M4_SHIFT)) & ANACTRL_RINGO1_CTRL_E_M4_MASK) +#define ANACTRL_RINGO1_CTRL_E_M5_MASK (0x100U) +#define ANACTRL_RINGO1_CTRL_E_M5_SHIFT (8U) +/*! E_M5 - Metal 5 (M5) monitor control. + * 0b0..Ringo is disabled. + * 0b1..Ringo is enabled. + */ +#define ANACTRL_RINGO1_CTRL_E_M5(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_M5_SHIFT)) & ANACTRL_RINGO1_CTRL_E_M5_MASK) +#define ANACTRL_RINGO1_CTRL_DIVISOR_MASK (0xF0000U) +#define ANACTRL_RINGO1_CTRL_DIVISOR_SHIFT (16U) +#define ANACTRL_RINGO1_CTRL_DIVISOR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_DIVISOR_SHIFT)) & ANACTRL_RINGO1_CTRL_DIVISOR_MASK) +#define ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_MASK (0x80000000U) +#define ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_SHIFT (31U) +#define ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_SHIFT)) & ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_MASK) +/*! @} */ + +/*! @name RINGO2_CTRL - Third Ring Oscillator module control register. */ +/*! @{ */ +#define ANACTRL_RINGO2_CTRL_S_MASK (0x1U) +#define ANACTRL_RINGO2_CTRL_S_SHIFT (0U) +/*! S - Select short or long ringo (for all ringos types). + * 0b0..Select short ringo (few elements). + * 0b1..Select long ringo (many elements). + */ +#define ANACTRL_RINGO2_CTRL_S(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_S_SHIFT)) & ANACTRL_RINGO2_CTRL_S_MASK) +#define ANACTRL_RINGO2_CTRL_FS_MASK (0x2U) +#define ANACTRL_RINGO2_CTRL_FS_SHIFT (1U) +/*! FS - Ringo frequency output divider. + * 0b0..High frequency output (frequency lower than 100 MHz). + * 0b1..Low frequency output (frequency lower than 10 MHz). + */ +#define ANACTRL_RINGO2_CTRL_FS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_FS_SHIFT)) & ANACTRL_RINGO2_CTRL_FS_MASK) +#define ANACTRL_RINGO2_CTRL_PD_MASK (0x4U) +#define ANACTRL_RINGO2_CTRL_PD_SHIFT (2U) +/*! PD - Ringo module Power control. + * 0b0..The Ringo module is enabled. + * 0b1..The Ringo module is disabled. + */ +#define ANACTRL_RINGO2_CTRL_PD(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_PD_SHIFT)) & ANACTRL_RINGO2_CTRL_PD_MASK) +#define ANACTRL_RINGO2_CTRL_E_R24_MASK (0x8U) +#define ANACTRL_RINGO2_CTRL_E_R24_SHIFT (3U) +/*! E_R24 - . + * 0b0..Ringo is disabled. + * 0b1..Ringo is enabled. + */ +#define ANACTRL_RINGO2_CTRL_E_R24(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_R24_SHIFT)) & ANACTRL_RINGO2_CTRL_E_R24_MASK) +#define ANACTRL_RINGO2_CTRL_E_R35_MASK (0x10U) +#define ANACTRL_RINGO2_CTRL_E_R35_SHIFT (4U) +/*! E_R35 - . + * 0b0..Ringo is disabled. + * 0b1..Ringo is enabled. + */ +#define ANACTRL_RINGO2_CTRL_E_R35(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_R35_SHIFT)) & ANACTRL_RINGO2_CTRL_E_R35_MASK) +#define ANACTRL_RINGO2_CTRL_E_M2_MASK (0x20U) +#define ANACTRL_RINGO2_CTRL_E_M2_SHIFT (5U) +/*! E_M2 - Metal 2 (M2) monitor control. + * 0b0..Ringo is disabled. + * 0b1..Ringo is enabled. + */ +#define ANACTRL_RINGO2_CTRL_E_M2(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_M2_SHIFT)) & ANACTRL_RINGO2_CTRL_E_M2_MASK) +#define ANACTRL_RINGO2_CTRL_E_M3_MASK (0x40U) +#define ANACTRL_RINGO2_CTRL_E_M3_SHIFT (6U) +/*! E_M3 - Metal 3 (M3) monitor control. + * 0b0..Ringo is disabled. + * 0b1..Ringo is enabled. + */ +#define ANACTRL_RINGO2_CTRL_E_M3(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_M3_SHIFT)) & ANACTRL_RINGO2_CTRL_E_M3_MASK) +#define ANACTRL_RINGO2_CTRL_E_M4_MASK (0x80U) +#define ANACTRL_RINGO2_CTRL_E_M4_SHIFT (7U) +/*! E_M4 - Metal 4 (M4) monitor control. + * 0b0..Ringo is disabled. + * 0b1..Ringo is enabled. + */ +#define ANACTRL_RINGO2_CTRL_E_M4(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_M4_SHIFT)) & ANACTRL_RINGO2_CTRL_E_M4_MASK) +#define ANACTRL_RINGO2_CTRL_E_M5_MASK (0x100U) +#define ANACTRL_RINGO2_CTRL_E_M5_SHIFT (8U) +/*! E_M5 - Metal 5 (M5) monitor control. + * 0b0..Ringo is disabled. + * 0b1..Ringo is enabled. + */ +#define ANACTRL_RINGO2_CTRL_E_M5(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_M5_SHIFT)) & ANACTRL_RINGO2_CTRL_E_M5_MASK) +#define ANACTRL_RINGO2_CTRL_DIVISOR_MASK (0xF0000U) +#define ANACTRL_RINGO2_CTRL_DIVISOR_SHIFT (16U) +#define ANACTRL_RINGO2_CTRL_DIVISOR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_DIVISOR_SHIFT)) & ANACTRL_RINGO2_CTRL_DIVISOR_MASK) +#define ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ_MASK (0x80000000U) +#define ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ_SHIFT (31U) +#define ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ_SHIFT)) & ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ_MASK) +/*! @} */ + +/*! @name LDO_XO32M - High Speed Crystal Oscillator (12 MHz - 32 MHz) Voltage Source Supply Control register */ +/*! @{ */ +#define ANACTRL_LDO_XO32M_BYPASS_MASK (0x2U) +#define ANACTRL_LDO_XO32M_BYPASS_SHIFT (1U) +/*! BYPASS - Activate LDO bypass. + * 0b0..Disable bypass mode (for normal operations). + * 0b1..Activate LDO bypass. + */ +#define ANACTRL_LDO_XO32M_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_BYPASS_SHIFT)) & ANACTRL_LDO_XO32M_BYPASS_MASK) +#define ANACTRL_LDO_XO32M_HIGHZ_MASK (0x4U) +#define ANACTRL_LDO_XO32M_HIGHZ_SHIFT (2U) +/*! HIGHZ - . + * 0b0..Output in High normal state. + * 0b1..Output in High Impedance state. + */ +#define ANACTRL_LDO_XO32M_HIGHZ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_HIGHZ_SHIFT)) & ANACTRL_LDO_XO32M_HIGHZ_MASK) +#define ANACTRL_LDO_XO32M_VOUT_MASK (0x38U) +#define ANACTRL_LDO_XO32M_VOUT_SHIFT (3U) +/*! VOUT - Sets the LDO output level. + * 0b000..0.750 V. + * 0b001..0.775 V. + * 0b010..0.800 V. + * 0b011..0.825 V. + * 0b100..0.850 V. + * 0b101..0.875 V. + * 0b110..0.900 V. + * 0b111..0.925 V. + */ +#define ANACTRL_LDO_XO32M_VOUT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_VOUT_SHIFT)) & ANACTRL_LDO_XO32M_VOUT_MASK) +#define ANACTRL_LDO_XO32M_IBIAS_MASK (0xC0U) +#define ANACTRL_LDO_XO32M_IBIAS_SHIFT (6U) +#define ANACTRL_LDO_XO32M_IBIAS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_IBIAS_SHIFT)) & ANACTRL_LDO_XO32M_IBIAS_MASK) +#define ANACTRL_LDO_XO32M_STABMODE_MASK (0x300U) +#define ANACTRL_LDO_XO32M_STABMODE_SHIFT (8U) +#define ANACTRL_LDO_XO32M_STABMODE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_STABMODE_SHIFT)) & ANACTRL_LDO_XO32M_STABMODE_MASK) +/*! @} */ + +/*! @name XO_CAL_CFG - All Crystal Oscillators (both the 32 KHz and the High speed) Capacitive Banks Calibration Configuration register */ +/*! @{ */ +#define ANACTRL_XO_CAL_CFG_START_INV_MASK (0x1U) +#define ANACTRL_XO_CAL_CFG_START_INV_SHIFT (0U) +#define ANACTRL_XO_CAL_CFG_START_INV(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO_CAL_CFG_START_INV_SHIFT)) & ANACTRL_XO_CAL_CFG_START_INV_MASK) +#define ANACTRL_XO_CAL_CFG_START_OVR_MASK (0x2U) +#define ANACTRL_XO_CAL_CFG_START_OVR_SHIFT (1U) +#define ANACTRL_XO_CAL_CFG_START_OVR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO_CAL_CFG_START_OVR_SHIFT)) & ANACTRL_XO_CAL_CFG_START_OVR_MASK) +#define ANACTRL_XO_CAL_CFG_START_MASK (0x4U) +#define ANACTRL_XO_CAL_CFG_START_SHIFT (2U) +#define ANACTRL_XO_CAL_CFG_START(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO_CAL_CFG_START_SHIFT)) & ANACTRL_XO_CAL_CFG_START_MASK) +#define ANACTRL_XO_CAL_CFG_STOP_INV_MASK (0x8U) +#define ANACTRL_XO_CAL_CFG_STOP_INV_SHIFT (3U) +#define ANACTRL_XO_CAL_CFG_STOP_INV(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO_CAL_CFG_STOP_INV_SHIFT)) & ANACTRL_XO_CAL_CFG_STOP_INV_MASK) +#define ANACTRL_XO_CAL_CFG_STOP_CNTR_END_MASK (0x10U) +#define ANACTRL_XO_CAL_CFG_STOP_CNTR_END_SHIFT (4U) +#define ANACTRL_XO_CAL_CFG_STOP_CNTR_END(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO_CAL_CFG_STOP_CNTR_END_SHIFT)) & ANACTRL_XO_CAL_CFG_STOP_CNTR_END_MASK) +#define ANACTRL_XO_CAL_CFG_XO32K_MODE_MASK (0x20U) +#define ANACTRL_XO_CAL_CFG_XO32K_MODE_SHIFT (5U) +/*! XO32K_MODE - When 0 : High speed crystal oscillator calibration is used. When 1 : 32 kHz crystal oscillator calibration is used. + * 0b0..High speed crystal oscillator (12 MHz- 32 MHz) is used + * 0b1..32 kHz crystal oscillator calibration is used. + */ +#define ANACTRL_XO_CAL_CFG_XO32K_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO_CAL_CFG_XO32K_MODE_SHIFT)) & ANACTRL_XO_CAL_CFG_XO32K_MODE_MASK) +/*! @} */ + +/*! @name XO_CAL_CMD - All Crystal Oscillators (both the 32 KHz and the High Speed) Capacitive Banks Calibration Command register. */ +/*! @{ */ +#define ANACTRL_XO_CAL_CMD_START_MASK (0x1U) +#define ANACTRL_XO_CAL_CMD_START_SHIFT (0U) +#define ANACTRL_XO_CAL_CMD_START(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO_CAL_CMD_START_SHIFT)) & ANACTRL_XO_CAL_CMD_START_MASK) +#define ANACTRL_XO_CAL_CMD_STOP_MASK (0x2U) +#define ANACTRL_XO_CAL_CMD_STOP_SHIFT (1U) +#define ANACTRL_XO_CAL_CMD_STOP(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO_CAL_CMD_STOP_SHIFT)) & ANACTRL_XO_CAL_CMD_STOP_MASK) +#define ANACTRL_XO_CAL_CMD_OVR_MASK (0x4U) +#define ANACTRL_XO_CAL_CMD_OVR_SHIFT (2U) +#define ANACTRL_XO_CAL_CMD_OVR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO_CAL_CMD_OVR_SHIFT)) & ANACTRL_XO_CAL_CMD_OVR_MASK) +/*! @} */ + +/*! @name XO_CAL_STATUS - All Crystal Oscillators (both the 32 KHz and the High speed) Capacitive Banks Calibration Status register. */ +/*! @{ */ +#define ANACTRL_XO_CAL_STATUS_CAL_CNTR_MASK (0xFFFFU) +#define ANACTRL_XO_CAL_STATUS_CAL_CNTR_SHIFT (0U) +#define ANACTRL_XO_CAL_STATUS_CAL_CNTR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO_CAL_STATUS_CAL_CNTR_SHIFT)) & ANACTRL_XO_CAL_STATUS_CAL_CNTR_MASK) +#define ANACTRL_XO_CAL_STATUS_DONE_MASK (0x10000U) +#define ANACTRL_XO_CAL_STATUS_DONE_SHIFT (16U) +#define ANACTRL_XO_CAL_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO_CAL_STATUS_DONE_SHIFT)) & ANACTRL_XO_CAL_STATUS_DONE_MASK) +/*! @} */ + +/*! @name USBHS_PHY_CTRL - USB High Speed Phy Control */ +/*! @{ */ +#define ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext_MASK (0x1U) +#define ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext_SHIFT (0U) +#define ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext_SHIFT)) & ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext_MASK) +#define ANACTRL_USBHS_PHY_CTRL_usb_id_ext_MASK (0x2U) +#define ANACTRL_USBHS_PHY_CTRL_usb_id_ext_SHIFT (1U) +#define ANACTRL_USBHS_PHY_CTRL_usb_id_ext(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_CTRL_usb_id_ext_SHIFT)) & ANACTRL_USBHS_PHY_CTRL_usb_id_ext_MASK) +#define ANACTRL_USBHS_PHY_CTRL_iso_atx_MASK (0x8U) +#define ANACTRL_USBHS_PHY_CTRL_iso_atx_SHIFT (3U) +#define ANACTRL_USBHS_PHY_CTRL_iso_atx(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_CTRL_iso_atx_SHIFT)) & ANACTRL_USBHS_PHY_CTRL_iso_atx_MASK) +/*! @} */ + +/*! @name USBHS_PHY_TRIM - USB High Speed Phy Trim values */ +/*! @{ */ +#define ANACTRL_USBHS_PHY_TRIM_trim_usb_reg_env_tail_adj_vd_MASK (0x3U) +#define ANACTRL_USBHS_PHY_TRIM_trim_usb_reg_env_tail_adj_vd_SHIFT (0U) +#define ANACTRL_USBHS_PHY_TRIM_trim_usb_reg_env_tail_adj_vd(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usb_reg_env_tail_adj_vd_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usb_reg_env_tail_adj_vd_MASK) +#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_d_cal_MASK (0x3CU) +#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_d_cal_SHIFT (2U) +#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_d_cal(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_d_cal_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_d_cal_MASK) +#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dp_MASK (0x7C0U) +#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dp_SHIFT (6U) +#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dp(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dp_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dp_MASK) +#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dm_MASK (0xF800U) +#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dm_SHIFT (11U) +#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dm(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dm_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dm_MASK) +#define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_tst_MASK (0x30000U) +#define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_tst_SHIFT (16U) +#define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_tst(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_tst_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_tst_MASK) +#define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_vbgadj_MASK (0x1C0000U) +#define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_vbgadj_SHIFT (18U) +#define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_vbgadj(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_vbgadj_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_vbgadj_MASK) +#define ANACTRL_USBHS_PHY_TRIM_trim_pll_ctrl0_div_sel_MASK (0xE00000U) +#define ANACTRL_USBHS_PHY_TRIM_trim_pll_ctrl0_div_sel_SHIFT (21U) +#define ANACTRL_USBHS_PHY_TRIM_trim_pll_ctrl0_div_sel(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_pll_ctrl0_div_sel_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_pll_ctrl0_div_sel_MASK) +/*! @} */ + +/*! @name USBHS_PHY_STATUS - USB High Speed Phy Status */ +/*! @{ */ +#define ANACTRL_USBHS_PHY_STATUS_pfd_stable_MASK (0x1U) +#define ANACTRL_USBHS_PHY_STATUS_pfd_stable_SHIFT (0U) +#define ANACTRL_USBHS_PHY_STATUS_pfd_stable(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_STATUS_pfd_stable_SHIFT)) & ANACTRL_USBHS_PHY_STATUS_pfd_stable_MASK) +#define ANACTRL_USBHS_PHY_STATUS_vbusvalid_3vdetect_1p8v_MASK (0x2U) +#define ANACTRL_USBHS_PHY_STATUS_vbusvalid_3vdetect_1p8v_SHIFT (1U) +#define ANACTRL_USBHS_PHY_STATUS_vbusvalid_3vdetect_1p8v(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_STATUS_vbusvalid_3vdetect_1p8v_SHIFT)) & ANACTRL_USBHS_PHY_STATUS_vbusvalid_3vdetect_1p8v_MASK) +#define ANACTRL_USBHS_PHY_STATUS_sess_vld_1p8v_MASK (0x4U) +#define ANACTRL_USBHS_PHY_STATUS_sess_vld_1p8v_SHIFT (2U) +#define ANACTRL_USBHS_PHY_STATUS_sess_vld_1p8v(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_STATUS_sess_vld_1p8v_SHIFT)) & ANACTRL_USBHS_PHY_STATUS_sess_vld_1p8v_MASK) +#define ANACTRL_USBHS_PHY_STATUS_usb2_rx_vpin_fs_1p8v_MASK (0x8U) +#define ANACTRL_USBHS_PHY_STATUS_usb2_rx_vpin_fs_1p8v_SHIFT (3U) +#define ANACTRL_USBHS_PHY_STATUS_usb2_rx_vpin_fs_1p8v(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_STATUS_usb2_rx_vpin_fs_1p8v_SHIFT)) & ANACTRL_USBHS_PHY_STATUS_usb2_rx_vpin_fs_1p8v_MASK) +#define ANACTRL_USBHS_PHY_STATUS_usb2_rx_vmin_fs_1p8v_MASK (0x10U) +#define ANACTRL_USBHS_PHY_STATUS_usb2_rx_vmin_fs_1p8v_SHIFT (4U) +#define ANACTRL_USBHS_PHY_STATUS_usb2_rx_vmin_fs_1p8v(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_STATUS_usb2_rx_vmin_fs_1p8v_SHIFT)) & ANACTRL_USBHS_PHY_STATUS_usb2_rx_vmin_fs_1p8v_MASK) +#define ANACTRL_USBHS_PHY_STATUS_usb2_plugged_in_1p8v_MASK (0x20U) +#define ANACTRL_USBHS_PHY_STATUS_usb2_plugged_in_1p8v_SHIFT (5U) +#define ANACTRL_USBHS_PHY_STATUS_usb2_plugged_in_1p8v(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_STATUS_usb2_plugged_in_1p8v_SHIFT)) & ANACTRL_USBHS_PHY_STATUS_usb2_plugged_in_1p8v_MASK) +#define ANACTRL_USBHS_PHY_STATUS_usb2_iddig_1p8v_MASK (0x40U) +#define ANACTRL_USBHS_PHY_STATUS_usb2_iddig_1p8v_SHIFT (6U) +#define ANACTRL_USBHS_PHY_STATUS_usb2_iddig_1p8v(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_STATUS_usb2_iddig_1p8v_SHIFT)) & ANACTRL_USBHS_PHY_STATUS_usb2_iddig_1p8v_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group ANACTRL_Register_Masks */ + + +/* ANACTRL - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral ANACTRL base address */ + #define ANACTRL_BASE (0x50013000u) + /** Peripheral ANACTRL base address */ + #define ANACTRL_BASE_NS (0x40013000u) + /** Peripheral ANACTRL base pointer */ + #define ANACTRL ((ANACTRL_Type *)ANACTRL_BASE) + /** Peripheral ANACTRL base pointer */ + #define ANACTRL_NS ((ANACTRL_Type *)ANACTRL_BASE_NS) + /** Array initializer of ANACTRL peripheral base addresses */ + #define ANACTRL_BASE_ADDRS { ANACTRL_BASE } + /** Array initializer of ANACTRL peripheral base pointers */ + #define ANACTRL_BASE_PTRS { ANACTRL } + /** Array initializer of ANACTRL peripheral base addresses */ + #define ANACTRL_BASE_ADDRS_NS { ANACTRL_BASE_NS } + /** Array initializer of ANACTRL peripheral base pointers */ + #define ANACTRL_BASE_PTRS_NS { ANACTRL_NS } +#else + /** Peripheral ANACTRL base address */ + #define ANACTRL_BASE (0x40013000u) + /** Peripheral ANACTRL base pointer */ + #define ANACTRL ((ANACTRL_Type *)ANACTRL_BASE) + /** Array initializer of ANACTRL peripheral base addresses */ + #define ANACTRL_BASE_ADDRS { ANACTRL_BASE } + /** Array initializer of ANACTRL peripheral base pointers */ + #define ANACTRL_BASE_PTRS { ANACTRL } +#endif + +/*! + * @} + */ /* end of group ANACTRL_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CASPER Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CASPER_Peripheral_Access_Layer CASPER Peripheral Access Layer + * @{ + */ + +/** CASPER - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL0; /**< Contains the offsets of AB and CD in the RAM., offset: 0x0 */ + __IO uint32_t CTRL1; /**< Contains the opcode mode, iteration count, and result offset (in RAM) and also launches the accelerator. Note: with CP version: CTRL0 and CRTL1 can be written in one go with MCRR., offset: 0x4 */ + __IO uint32_t LOADER; /**< Contains an optional loader to load into CTRL0/1 in steps to perform a set of operations., offset: 0x8 */ + __IO uint32_t STATUS; /**< Indicates operational status and would contain the carry bit if used., offset: 0xC */ + __IO uint32_t INTENSET; /**< Sets interrupts, offset: 0x10 */ + __IO uint32_t INTENCLR; /**< Clears interrupts, offset: 0x14 */ + __I uint32_t INTSTAT; /**< Interrupt status bits (mask of INTENSET and STATUS), offset: 0x18 */ + uint8_t RESERVED_0[4]; + __IO uint32_t AREG; /**< A register, offset: 0x20 */ + __IO uint32_t BREG; /**< B register, offset: 0x24 */ + __IO uint32_t CREG; /**< C register, offset: 0x28 */ + __IO uint32_t DREG; /**< D register, offset: 0x2C */ + __IO uint32_t RES0; /**< Result register 0, offset: 0x30 */ + __IO uint32_t RES1; /**< Result register 1, offset: 0x34 */ + __IO uint32_t RES2; /**< Result register 2, offset: 0x38 */ + __IO uint32_t RES3; /**< Result register 3, offset: 0x3C */ + uint8_t RESERVED_1[32]; + __IO uint32_t MASK; /**< Optional mask register, offset: 0x60 */ + __IO uint32_t REMASK; /**< Optional re-mask register, offset: 0x64 */ + uint8_t RESERVED_2[24]; + __IO uint32_t LOCK; /**< Security lock register, offset: 0x80 */ +} CASPER_Type; + +/* ---------------------------------------------------------------------------- + -- CASPER Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CASPER_Register_Masks CASPER Register Masks + * @{ + */ + +/*! @name CTRL0 - Contains the offsets of AB and CD in the RAM. */ +/*! @{ */ +#define CASPER_CTRL0_ABBPAIR_MASK (0x1U) +#define CASPER_CTRL0_ABBPAIR_SHIFT (0U) +/*! ABBPAIR - Which bank-pair the offset ABOFF is within. This must be 0 if only 2-up + * 0b0..Bank-pair 0 (1st) + * 0b1..Bank-pair 1 (2nd) + */ +#define CASPER_CTRL0_ABBPAIR(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_ABBPAIR_SHIFT)) & CASPER_CTRL0_ABBPAIR_MASK) +#define CASPER_CTRL0_ABOFF_MASK (0x4U) +#define CASPER_CTRL0_ABOFF_SHIFT (2U) +#define CASPER_CTRL0_ABOFF(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_ABOFF_SHIFT)) & CASPER_CTRL0_ABOFF_MASK) +#define CASPER_CTRL0_CDBPAIR_MASK (0x10000U) +#define CASPER_CTRL0_CDBPAIR_SHIFT (16U) +/*! CDBPAIR - Which bank-pair the offset CDOFF is within. This must be 0 if only 2-up + * 0b0..Bank-pair 0 (1st) + * 0b1..Bank-pair 1 (2nd) + */ +#define CASPER_CTRL0_CDBPAIR(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_CDBPAIR_SHIFT)) & CASPER_CTRL0_CDBPAIR_MASK) +#define CASPER_CTRL0_CDOFF_MASK (0x1FFC0000U) +#define CASPER_CTRL0_CDOFF_SHIFT (18U) +#define CASPER_CTRL0_CDOFF(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_CDOFF_SHIFT)) & CASPER_CTRL0_CDOFF_MASK) +/*! @} */ + +/*! @name CTRL1 - Contains the opcode mode, iteration count, and result offset (in RAM) and also launches the accelerator. Note: with CP version: CTRL0 and CRTL1 can be written in one go with MCRR. */ +/*! @{ */ +#define CASPER_CTRL1_ITER_MASK (0xFFU) +#define CASPER_CTRL1_ITER_SHIFT (0U) +#define CASPER_CTRL1_ITER(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_ITER_SHIFT)) & CASPER_CTRL1_ITER_MASK) +#define CASPER_CTRL1_MODE_MASK (0xFF00U) +#define CASPER_CTRL1_MODE_SHIFT (8U) +#define CASPER_CTRL1_MODE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_MODE_SHIFT)) & CASPER_CTRL1_MODE_MASK) +#define CASPER_CTRL1_RESBPAIR_MASK (0x10000U) +#define CASPER_CTRL1_RESBPAIR_SHIFT (16U) +/*! RESBPAIR - Which bank-pair the offset RESOFF is within. This must be 0 if only 2-up. Ideally + * this is not the same bank as ABBPAIR (when 4-up supported) + * 0b0..Bank-pair 0 (1st) + * 0b1..Bank-pair 1 (2nd) + */ +#define CASPER_CTRL1_RESBPAIR(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_RESBPAIR_SHIFT)) & CASPER_CTRL1_RESBPAIR_MASK) +#define CASPER_CTRL1_RESOFF_MASK (0x1FFC0000U) +#define CASPER_CTRL1_RESOFF_SHIFT (18U) +#define CASPER_CTRL1_RESOFF(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_RESOFF_SHIFT)) & CASPER_CTRL1_RESOFF_MASK) +#define CASPER_CTRL1_CSKIP_MASK (0xC0000000U) +#define CASPER_CTRL1_CSKIP_SHIFT (30U) +/*! CSKIP - Skip rules on Carry if needed. This operation will be skipped based on Carry value (from previous operation) if not 0: + * 0b00..No Skip + * 0b01..Skip if Carry is 1 + * 0b10..Skip if Carry is 0 + * 0b11..Set CTRLOFF to CDOFF and Skip + */ +#define CASPER_CTRL1_CSKIP(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_CSKIP_SHIFT)) & CASPER_CTRL1_CSKIP_MASK) +/*! @} */ + +/*! @name LOADER - Contains an optional loader to load into CTRL0/1 in steps to perform a set of operations. */ +/*! @{ */ +#define CASPER_LOADER_COUNT_MASK (0xFFU) +#define CASPER_LOADER_COUNT_SHIFT (0U) +#define CASPER_LOADER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOADER_COUNT_SHIFT)) & CASPER_LOADER_COUNT_MASK) +#define CASPER_LOADER_CTRLBPAIR_MASK (0x10000U) +#define CASPER_LOADER_CTRLBPAIR_SHIFT (16U) +/*! CTRLBPAIR - Which bank-pair the offset CTRLOFF is within. This must be 0 if only 2-up. Does not + * matter which bank is used as this is loaded when not performing an operation. + * 0b0..Bank-pair 0 (1st) + * 0b1..Bank-pair 1 (2nd) + */ +#define CASPER_LOADER_CTRLBPAIR(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOADER_CTRLBPAIR_SHIFT)) & CASPER_LOADER_CTRLBPAIR_MASK) +#define CASPER_LOADER_CTRLOFF_MASK (0x1FFC0000U) +#define CASPER_LOADER_CTRLOFF_SHIFT (18U) +#define CASPER_LOADER_CTRLOFF(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOADER_CTRLOFF_SHIFT)) & CASPER_LOADER_CTRLOFF_MASK) +/*! @} */ + +/*! @name STATUS - Indicates operational status and would contain the carry bit if used. */ +/*! @{ */ +#define CASPER_STATUS_DONE_MASK (0x1U) +#define CASPER_STATUS_DONE_SHIFT (0U) +/*! DONE - Indicates if the accelerator has finished an operation. Write 1 to clear, or write CTRL1 to clear. + * 0b0..Busy or just cleared + * 0b1..Completed last operation + */ +#define CASPER_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_STATUS_DONE_SHIFT)) & CASPER_STATUS_DONE_MASK) +#define CASPER_STATUS_CARRY_MASK (0x10U) +#define CASPER_STATUS_CARRY_SHIFT (4U) +/*! CARRY - Last carry value if operation produced a carry bit + * 0b0..Carry was 0 or no carry + * 0b1..Carry was 1 + */ +#define CASPER_STATUS_CARRY(x) (((uint32_t)(((uint32_t)(x)) << CASPER_STATUS_CARRY_SHIFT)) & CASPER_STATUS_CARRY_MASK) +#define CASPER_STATUS_BUSY_MASK (0x20U) +#define CASPER_STATUS_BUSY_SHIFT (5U) +/*! BUSY - Indicates if the accelerator is busy performing an operation + * 0b0..Not busy - is idle + * 0b1..Is busy + */ +#define CASPER_STATUS_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CASPER_STATUS_BUSY_SHIFT)) & CASPER_STATUS_BUSY_MASK) +/*! @} */ + +/*! @name INTENSET - Sets interrupts */ +/*! @{ */ +#define CASPER_INTENSET_DONE_MASK (0x1U) +#define CASPER_INTENSET_DONE_SHIFT (0U) +/*! DONE - Set if the accelerator should interrupt when done. + * 0b0..Do not interrupt when done + * 0b1..Interrupt when done + */ +#define CASPER_INTENSET_DONE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_INTENSET_DONE_SHIFT)) & CASPER_INTENSET_DONE_MASK) +/*! @} */ + +/*! @name INTENCLR - Clears interrupts */ +/*! @{ */ +#define CASPER_INTENCLR_DONE_MASK (0x1U) +#define CASPER_INTENCLR_DONE_SHIFT (0U) +/*! DONE - Written to clear an interrupt set with INTENSET. + * 0b0..If written 0, ignored + * 0b1..If written 1, do not Interrupt when done + */ +#define CASPER_INTENCLR_DONE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_INTENCLR_DONE_SHIFT)) & CASPER_INTENCLR_DONE_MASK) +/*! @} */ + +/*! @name INTSTAT - Interrupt status bits (mask of INTENSET and STATUS) */ +/*! @{ */ +#define CASPER_INTSTAT_DONE_MASK (0x1U) +#define CASPER_INTSTAT_DONE_SHIFT (0U) +/*! DONE - If set, interrupt is caused by accelerator being done. + * 0b0..Not caused by accelerator being done + * 0b1..Caused by accelerator being done + */ +#define CASPER_INTSTAT_DONE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_INTSTAT_DONE_SHIFT)) & CASPER_INTSTAT_DONE_MASK) +/*! @} */ + +/*! @name AREG - A register */ +/*! @{ */ +#define CASPER_AREG_REG_VALUE_MASK (0xFFFFFFFFU) +#define CASPER_AREG_REG_VALUE_SHIFT (0U) +#define CASPER_AREG_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_AREG_REG_VALUE_SHIFT)) & CASPER_AREG_REG_VALUE_MASK) +/*! @} */ + +/*! @name BREG - B register */ +/*! @{ */ +#define CASPER_BREG_REG_VALUE_MASK (0xFFFFFFFFU) +#define CASPER_BREG_REG_VALUE_SHIFT (0U) +#define CASPER_BREG_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_BREG_REG_VALUE_SHIFT)) & CASPER_BREG_REG_VALUE_MASK) +/*! @} */ + +/*! @name CREG - C register */ +/*! @{ */ +#define CASPER_CREG_REG_VALUE_MASK (0xFFFFFFFFU) +#define CASPER_CREG_REG_VALUE_SHIFT (0U) +#define CASPER_CREG_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CREG_REG_VALUE_SHIFT)) & CASPER_CREG_REG_VALUE_MASK) +/*! @} */ + +/*! @name DREG - D register */ +/*! @{ */ +#define CASPER_DREG_REG_VALUE_MASK (0xFFFFFFFFU) +#define CASPER_DREG_REG_VALUE_SHIFT (0U) +#define CASPER_DREG_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_DREG_REG_VALUE_SHIFT)) & CASPER_DREG_REG_VALUE_MASK) +/*! @} */ + +/*! @name RES0 - Result register 0 */ +/*! @{ */ +#define CASPER_RES0_REG_VALUE_MASK (0xFFFFFFFFU) +#define CASPER_RES0_REG_VALUE_SHIFT (0U) +#define CASPER_RES0_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_RES0_REG_VALUE_SHIFT)) & CASPER_RES0_REG_VALUE_MASK) +/*! @} */ + +/*! @name RES1 - Result register 1 */ +/*! @{ */ +#define CASPER_RES1_REG_VALUE_MASK (0xFFFFFFFFU) +#define CASPER_RES1_REG_VALUE_SHIFT (0U) +#define CASPER_RES1_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_RES1_REG_VALUE_SHIFT)) & CASPER_RES1_REG_VALUE_MASK) +/*! @} */ + +/*! @name RES2 - Result register 2 */ +/*! @{ */ +#define CASPER_RES2_REG_VALUE_MASK (0xFFFFFFFFU) +#define CASPER_RES2_REG_VALUE_SHIFT (0U) +#define CASPER_RES2_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_RES2_REG_VALUE_SHIFT)) & CASPER_RES2_REG_VALUE_MASK) +/*! @} */ + +/*! @name RES3 - Result register 3 */ +/*! @{ */ +#define CASPER_RES3_REG_VALUE_MASK (0xFFFFFFFFU) +#define CASPER_RES3_REG_VALUE_SHIFT (0U) +#define CASPER_RES3_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_RES3_REG_VALUE_SHIFT)) & CASPER_RES3_REG_VALUE_MASK) +/*! @} */ + +/*! @name MASK - Optional mask register */ +/*! @{ */ +#define CASPER_MASK_MASK_MASK (0xFFFFFFFFU) +#define CASPER_MASK_MASK_SHIFT (0U) +#define CASPER_MASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << CASPER_MASK_MASK_SHIFT)) & CASPER_MASK_MASK_MASK) +/*! @} */ + +/*! @name REMASK - Optional re-mask register */ +/*! @{ */ +#define CASPER_REMASK_MASK_MASK (0xFFFFFFFFU) +#define CASPER_REMASK_MASK_SHIFT (0U) +#define CASPER_REMASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << CASPER_REMASK_MASK_SHIFT)) & CASPER_REMASK_MASK_MASK) +/*! @} */ + +/*! @name LOCK - Security lock register */ +/*! @{ */ +#define CASPER_LOCK_LOCK_MASK (0x1U) +#define CASPER_LOCK_LOCK_SHIFT (0U) +/*! LOCK - Reads back with security level locked to, or 0. Writes as 0 to unlock, 1 to lock. + * 0b0..unlock + * 0b1..Lock to current security level + */ +#define CASPER_LOCK_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOCK_LOCK_SHIFT)) & CASPER_LOCK_LOCK_MASK) +#define CASPER_LOCK_KEY_MASK (0x1FFF0U) +#define CASPER_LOCK_KEY_SHIFT (4U) +/*! KEY - Must be written as 0x73D to change the register. + * 0b0011100111101..If set during write, will allow lock or unlock + */ +#define CASPER_LOCK_KEY(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOCK_KEY_SHIFT)) & CASPER_LOCK_KEY_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group CASPER_Register_Masks */ + + +/* CASPER - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral CASPER base address */ + #define CASPER_BASE (0x500A5000u) + /** Peripheral CASPER base address */ + #define CASPER_BASE_NS (0x400A5000u) + /** Peripheral CASPER base pointer */ + #define CASPER ((CASPER_Type *)CASPER_BASE) + /** Peripheral CASPER base pointer */ + #define CASPER_NS ((CASPER_Type *)CASPER_BASE_NS) + /** Array initializer of CASPER peripheral base addresses */ + #define CASPER_BASE_ADDRS { CASPER_BASE } + /** Array initializer of CASPER peripheral base pointers */ + #define CASPER_BASE_PTRS { CASPER } + /** Array initializer of CASPER peripheral base addresses */ + #define CASPER_BASE_ADDRS_NS { CASPER_BASE_NS } + /** Array initializer of CASPER peripheral base pointers */ + #define CASPER_BASE_PTRS_NS { CASPER_NS } +#else + /** Peripheral CASPER base address */ + #define CASPER_BASE (0x400A5000u) + /** Peripheral CASPER base pointer */ + #define CASPER ((CASPER_Type *)CASPER_BASE) + /** Array initializer of CASPER peripheral base addresses */ + #define CASPER_BASE_ADDRS { CASPER_BASE } + /** Array initializer of CASPER peripheral base pointers */ + #define CASPER_BASE_PTRS { CASPER } +#endif + +/*! + * @} + */ /* end of group CASPER_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CRC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer + * @{ + */ + +/** CRC - Register Layout Typedef */ +typedef struct { + __IO uint32_t MODE; /**< CRC mode register, offset: 0x0 */ + __IO uint32_t SEED; /**< CRC seed register, offset: 0x4 */ + union { /* offset: 0x8 */ + __I uint32_t SUM; /**< CRC checksum register, offset: 0x8 */ + __O uint32_t WR_DATA; /**< CRC data register, offset: 0x8 */ + }; +} CRC_Type; + +/* ---------------------------------------------------------------------------- + -- CRC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CRC_Register_Masks CRC Register Masks + * @{ + */ + +/*! @name MODE - CRC mode register */ +/*! @{ */ +#define CRC_MODE_CRC_POLY_MASK (0x3U) +#define CRC_MODE_CRC_POLY_SHIFT (0U) +#define CRC_MODE_CRC_POLY(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CRC_POLY_SHIFT)) & CRC_MODE_CRC_POLY_MASK) +#define CRC_MODE_BIT_RVS_WR_MASK (0x4U) +#define CRC_MODE_BIT_RVS_WR_SHIFT (2U) +#define CRC_MODE_BIT_RVS_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_WR_SHIFT)) & CRC_MODE_BIT_RVS_WR_MASK) +#define CRC_MODE_CMPL_WR_MASK (0x8U) +#define CRC_MODE_CMPL_WR_SHIFT (3U) +#define CRC_MODE_CMPL_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_WR_SHIFT)) & CRC_MODE_CMPL_WR_MASK) +#define CRC_MODE_BIT_RVS_SUM_MASK (0x10U) +#define CRC_MODE_BIT_RVS_SUM_SHIFT (4U) +#define CRC_MODE_BIT_RVS_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_SUM_SHIFT)) & CRC_MODE_BIT_RVS_SUM_MASK) +#define CRC_MODE_CMPL_SUM_MASK (0x20U) +#define CRC_MODE_CMPL_SUM_SHIFT (5U) +#define CRC_MODE_CMPL_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_SUM_SHIFT)) & CRC_MODE_CMPL_SUM_MASK) +/*! @} */ + +/*! @name SEED - CRC seed register */ +/*! @{ */ +#define CRC_SEED_CRC_SEED_MASK (0xFFFFFFFFU) +#define CRC_SEED_CRC_SEED_SHIFT (0U) +#define CRC_SEED_CRC_SEED(x) (((uint32_t)(((uint32_t)(x)) << CRC_SEED_CRC_SEED_SHIFT)) & CRC_SEED_CRC_SEED_MASK) +/*! @} */ + +/*! @name SUM - CRC checksum register */ +/*! @{ */ +#define CRC_SUM_CRC_SUM_MASK (0xFFFFFFFFU) +#define CRC_SUM_CRC_SUM_SHIFT (0U) +#define CRC_SUM_CRC_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_SUM_CRC_SUM_SHIFT)) & CRC_SUM_CRC_SUM_MASK) +/*! @} */ + +/*! @name WR_DATA - CRC data register */ +/*! @{ */ +#define CRC_WR_DATA_CRC_WR_DATA_MASK (0xFFFFFFFFU) +#define CRC_WR_DATA_CRC_WR_DATA_SHIFT (0U) +#define CRC_WR_DATA_CRC_WR_DATA(x) (((uint32_t)(((uint32_t)(x)) << CRC_WR_DATA_CRC_WR_DATA_SHIFT)) & CRC_WR_DATA_CRC_WR_DATA_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group CRC_Register_Masks */ + + +/* CRC - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral CRC_ENGINE base address */ + #define CRC_ENGINE_BASE (0x50095000u) + /** Peripheral CRC_ENGINE base address */ + #define CRC_ENGINE_BASE_NS (0x40095000u) + /** Peripheral CRC_ENGINE base pointer */ + #define CRC_ENGINE ((CRC_Type *)CRC_ENGINE_BASE) + /** Peripheral CRC_ENGINE base pointer */ + #define CRC_ENGINE_NS ((CRC_Type *)CRC_ENGINE_BASE_NS) + /** Array initializer of CRC peripheral base addresses */ + #define CRC_BASE_ADDRS { CRC_ENGINE_BASE } + /** Array initializer of CRC peripheral base pointers */ + #define CRC_BASE_PTRS { CRC_ENGINE } + /** Array initializer of CRC peripheral base addresses */ + #define CRC_BASE_ADDRS_NS { CRC_ENGINE_BASE_NS } + /** Array initializer of CRC peripheral base pointers */ + #define CRC_BASE_PTRS_NS { CRC_ENGINE_NS } +#else + /** Peripheral CRC_ENGINE base address */ + #define CRC_ENGINE_BASE (0x40095000u) + /** Peripheral CRC_ENGINE base pointer */ + #define CRC_ENGINE ((CRC_Type *)CRC_ENGINE_BASE) + /** Array initializer of CRC peripheral base addresses */ + #define CRC_BASE_ADDRS { CRC_ENGINE_BASE } + /** Array initializer of CRC peripheral base pointers */ + #define CRC_BASE_PTRS { CRC_ENGINE } +#endif + +/*! + * @} + */ /* end of group CRC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CTIMER Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CTIMER_Peripheral_Access_Layer CTIMER Peripheral Access Layer + * @{ + */ + +/** CTIMER - Register Layout Typedef */ +typedef struct { + __IO uint32_t IR; /**< Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending., offset: 0x0 */ + __IO uint32_t TCR; /**< Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR., offset: 0x4 */ + __IO uint32_t TC; /**< Timer Counter, offset: 0x8 */ + __IO uint32_t PR; /**< Prescale Register, offset: 0xC */ + __IO uint32_t PC; /**< Prescale Counter, offset: 0x10 */ + __IO uint32_t MCR; /**< Match Control Register, offset: 0x14 */ + __IO uint32_t MR[4]; /**< Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC., array offset: 0x18, array step: 0x4 */ + __IO uint32_t CCR; /**< Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place., offset: 0x28 */ + __I uint32_t CR[4]; /**< Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input., array offset: 0x2C, array step: 0x4 */ + __IO uint32_t EMR; /**< External Match Register. The EMR controls the match function and the external match pins., offset: 0x3C */ + uint8_t RESERVED_0[48]; + __IO uint32_t CTCR; /**< Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting., offset: 0x70 */ + __IO uint32_t PWMC; /**< PWM Control Register. This register enables PWM mode for the external match pins., offset: 0x74 */ + __IO uint32_t MSR[4]; /**< Match Shadow Register, array offset: 0x78, array step: 0x4 */ +} CTIMER_Type; + +/* ---------------------------------------------------------------------------- + -- CTIMER Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CTIMER_Register_Masks CTIMER Register Masks + * @{ + */ + +/*! @name IR - Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */ +/*! @{ */ +#define CTIMER_IR_MR0INT_MASK (0x1U) +#define CTIMER_IR_MR0INT_SHIFT (0U) +#define CTIMER_IR_MR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR0INT_SHIFT)) & CTIMER_IR_MR0INT_MASK) +#define CTIMER_IR_MR1INT_MASK (0x2U) +#define CTIMER_IR_MR1INT_SHIFT (1U) +#define CTIMER_IR_MR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR1INT_SHIFT)) & CTIMER_IR_MR1INT_MASK) +#define CTIMER_IR_MR2INT_MASK (0x4U) +#define CTIMER_IR_MR2INT_SHIFT (2U) +#define CTIMER_IR_MR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR2INT_SHIFT)) & CTIMER_IR_MR2INT_MASK) +#define CTIMER_IR_MR3INT_MASK (0x8U) +#define CTIMER_IR_MR3INT_SHIFT (3U) +#define CTIMER_IR_MR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR3INT_SHIFT)) & CTIMER_IR_MR3INT_MASK) +#define CTIMER_IR_CR0INT_MASK (0x10U) +#define CTIMER_IR_CR0INT_SHIFT (4U) +#define CTIMER_IR_CR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR0INT_SHIFT)) & CTIMER_IR_CR0INT_MASK) +#define CTIMER_IR_CR1INT_MASK (0x20U) +#define CTIMER_IR_CR1INT_SHIFT (5U) +#define CTIMER_IR_CR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR1INT_SHIFT)) & CTIMER_IR_CR1INT_MASK) +#define CTIMER_IR_CR2INT_MASK (0x40U) +#define CTIMER_IR_CR2INT_SHIFT (6U) +#define CTIMER_IR_CR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR2INT_SHIFT)) & CTIMER_IR_CR2INT_MASK) +#define CTIMER_IR_CR3INT_MASK (0x80U) +#define CTIMER_IR_CR3INT_SHIFT (7U) +#define CTIMER_IR_CR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR3INT_SHIFT)) & CTIMER_IR_CR3INT_MASK) +/*! @} */ + +/*! @name TCR - Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */ +/*! @{ */ +#define CTIMER_TCR_CEN_MASK (0x1U) +#define CTIMER_TCR_CEN_SHIFT (0U) +/*! CEN - Counter enable. + * 0b0..Disabled.The counters are disabled. + * 0b1..Enabled. The Timer Counter and Prescale Counter are enabled. + */ +#define CTIMER_TCR_CEN(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CEN_SHIFT)) & CTIMER_TCR_CEN_MASK) +#define CTIMER_TCR_CRST_MASK (0x2U) +#define CTIMER_TCR_CRST_SHIFT (1U) +/*! CRST - Counter reset. + * 0b0..Disabled. Do nothing. + * 0b1..Enabled. The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of + * the APB bus clock. The counters remain reset until TCR[1] is returned to zero. + */ +#define CTIMER_TCR_CRST(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CRST_SHIFT)) & CTIMER_TCR_CRST_MASK) +/*! @} */ + +/*! @name TC - Timer Counter */ +/*! @{ */ +#define CTIMER_TC_TCVAL_MASK (0xFFFFFFFFU) +#define CTIMER_TC_TCVAL_SHIFT (0U) +#define CTIMER_TC_TCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TC_TCVAL_SHIFT)) & CTIMER_TC_TCVAL_MASK) +/*! @} */ + +/*! @name PR - Prescale Register */ +/*! @{ */ +#define CTIMER_PR_PRVAL_MASK (0xFFFFFFFFU) +#define CTIMER_PR_PRVAL_SHIFT (0U) +#define CTIMER_PR_PRVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PR_PRVAL_SHIFT)) & CTIMER_PR_PRVAL_MASK) +/*! @} */ + +/*! @name PC - Prescale Counter */ +/*! @{ */ +#define CTIMER_PC_PCVAL_MASK (0xFFFFFFFFU) +#define CTIMER_PC_PCVAL_SHIFT (0U) +#define CTIMER_PC_PCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PC_PCVAL_SHIFT)) & CTIMER_PC_PCVAL_MASK) +/*! @} */ + +/*! @name MCR - Match Control Register */ +/*! @{ */ +#define CTIMER_MCR_MR0I_MASK (0x1U) +#define CTIMER_MCR_MR0I_SHIFT (0U) +#define CTIMER_MCR_MR0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK) +#define CTIMER_MCR_MR0R_MASK (0x2U) +#define CTIMER_MCR_MR0R_SHIFT (1U) +#define CTIMER_MCR_MR0R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0R_SHIFT)) & CTIMER_MCR_MR0R_MASK) +#define CTIMER_MCR_MR0S_MASK (0x4U) +#define CTIMER_MCR_MR0S_SHIFT (2U) +#define CTIMER_MCR_MR0S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0S_SHIFT)) & CTIMER_MCR_MR0S_MASK) +#define CTIMER_MCR_MR1I_MASK (0x8U) +#define CTIMER_MCR_MR1I_SHIFT (3U) +#define CTIMER_MCR_MR1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1I_SHIFT)) & CTIMER_MCR_MR1I_MASK) +#define CTIMER_MCR_MR1R_MASK (0x10U) +#define CTIMER_MCR_MR1R_SHIFT (4U) +#define CTIMER_MCR_MR1R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1R_SHIFT)) & CTIMER_MCR_MR1R_MASK) +#define CTIMER_MCR_MR1S_MASK (0x20U) +#define CTIMER_MCR_MR1S_SHIFT (5U) +#define CTIMER_MCR_MR1S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1S_SHIFT)) & CTIMER_MCR_MR1S_MASK) +#define CTIMER_MCR_MR2I_MASK (0x40U) +#define CTIMER_MCR_MR2I_SHIFT (6U) +#define CTIMER_MCR_MR2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2I_SHIFT)) & CTIMER_MCR_MR2I_MASK) +#define CTIMER_MCR_MR2R_MASK (0x80U) +#define CTIMER_MCR_MR2R_SHIFT (7U) +#define CTIMER_MCR_MR2R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2R_SHIFT)) & CTIMER_MCR_MR2R_MASK) +#define CTIMER_MCR_MR2S_MASK (0x100U) +#define CTIMER_MCR_MR2S_SHIFT (8U) +#define CTIMER_MCR_MR2S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2S_SHIFT)) & CTIMER_MCR_MR2S_MASK) +#define CTIMER_MCR_MR3I_MASK (0x200U) +#define CTIMER_MCR_MR3I_SHIFT (9U) +#define CTIMER_MCR_MR3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3I_SHIFT)) & CTIMER_MCR_MR3I_MASK) +#define CTIMER_MCR_MR3R_MASK (0x400U) +#define CTIMER_MCR_MR3R_SHIFT (10U) +#define CTIMER_MCR_MR3R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3R_SHIFT)) & CTIMER_MCR_MR3R_MASK) +#define CTIMER_MCR_MR3S_MASK (0x800U) +#define CTIMER_MCR_MR3S_SHIFT (11U) +#define CTIMER_MCR_MR3S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3S_SHIFT)) & CTIMER_MCR_MR3S_MASK) +#define CTIMER_MCR_MR0RL_MASK (0x1000000U) +#define CTIMER_MCR_MR0RL_SHIFT (24U) +#define CTIMER_MCR_MR0RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0RL_SHIFT)) & CTIMER_MCR_MR0RL_MASK) +#define CTIMER_MCR_MR1RL_MASK (0x2000000U) +#define CTIMER_MCR_MR1RL_SHIFT (25U) +#define CTIMER_MCR_MR1RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1RL_SHIFT)) & CTIMER_MCR_MR1RL_MASK) +#define CTIMER_MCR_MR2RL_MASK (0x4000000U) +#define CTIMER_MCR_MR2RL_SHIFT (26U) +#define CTIMER_MCR_MR2RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2RL_SHIFT)) & CTIMER_MCR_MR2RL_MASK) +#define CTIMER_MCR_MR3RL_MASK (0x8000000U) +#define CTIMER_MCR_MR3RL_SHIFT (27U) +#define CTIMER_MCR_MR3RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3RL_SHIFT)) & CTIMER_MCR_MR3RL_MASK) +/*! @} */ + +/*! @name MR - Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */ +/*! @{ */ +#define CTIMER_MR_MATCH_MASK (0xFFFFFFFFU) +#define CTIMER_MR_MATCH_SHIFT (0U) +#define CTIMER_MR_MATCH(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MR_MATCH_SHIFT)) & CTIMER_MR_MATCH_MASK) +/*! @} */ + +/* The count of CTIMER_MR */ +#define CTIMER_MR_COUNT (4U) + +/*! @name CCR - Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */ +/*! @{ */ +#define CTIMER_CCR_CAP0RE_MASK (0x1U) +#define CTIMER_CCR_CAP0RE_SHIFT (0U) +#define CTIMER_CCR_CAP0RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0RE_SHIFT)) & CTIMER_CCR_CAP0RE_MASK) +#define CTIMER_CCR_CAP0FE_MASK (0x2U) +#define CTIMER_CCR_CAP0FE_SHIFT (1U) +#define CTIMER_CCR_CAP0FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0FE_SHIFT)) & CTIMER_CCR_CAP0FE_MASK) +#define CTIMER_CCR_CAP0I_MASK (0x4U) +#define CTIMER_CCR_CAP0I_SHIFT (2U) +#define CTIMER_CCR_CAP0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK) +#define CTIMER_CCR_CAP1RE_MASK (0x8U) +#define CTIMER_CCR_CAP1RE_SHIFT (3U) +#define CTIMER_CCR_CAP1RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1RE_SHIFT)) & CTIMER_CCR_CAP1RE_MASK) +#define CTIMER_CCR_CAP1FE_MASK (0x10U) +#define CTIMER_CCR_CAP1FE_SHIFT (4U) +#define CTIMER_CCR_CAP1FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1FE_SHIFT)) & CTIMER_CCR_CAP1FE_MASK) +#define CTIMER_CCR_CAP1I_MASK (0x20U) +#define CTIMER_CCR_CAP1I_SHIFT (5U) +#define CTIMER_CCR_CAP1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1I_SHIFT)) & CTIMER_CCR_CAP1I_MASK) +#define CTIMER_CCR_CAP2RE_MASK (0x40U) +#define CTIMER_CCR_CAP2RE_SHIFT (6U) +#define CTIMER_CCR_CAP2RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2RE_SHIFT)) & CTIMER_CCR_CAP2RE_MASK) +#define CTIMER_CCR_CAP2FE_MASK (0x80U) +#define CTIMER_CCR_CAP2FE_SHIFT (7U) +#define CTIMER_CCR_CAP2FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2FE_SHIFT)) & CTIMER_CCR_CAP2FE_MASK) +#define CTIMER_CCR_CAP2I_MASK (0x100U) +#define CTIMER_CCR_CAP2I_SHIFT (8U) +#define CTIMER_CCR_CAP2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2I_SHIFT)) & CTIMER_CCR_CAP2I_MASK) +#define CTIMER_CCR_CAP3RE_MASK (0x200U) +#define CTIMER_CCR_CAP3RE_SHIFT (9U) +#define CTIMER_CCR_CAP3RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3RE_SHIFT)) & CTIMER_CCR_CAP3RE_MASK) +#define CTIMER_CCR_CAP3FE_MASK (0x400U) +#define CTIMER_CCR_CAP3FE_SHIFT (10U) +#define CTIMER_CCR_CAP3FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3FE_SHIFT)) & CTIMER_CCR_CAP3FE_MASK) +#define CTIMER_CCR_CAP3I_MASK (0x800U) +#define CTIMER_CCR_CAP3I_SHIFT (11U) +#define CTIMER_CCR_CAP3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3I_SHIFT)) & CTIMER_CCR_CAP3I_MASK) +/*! @} */ + +/*! @name CR - Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input. */ +/*! @{ */ +#define CTIMER_CR_CAP_MASK (0xFFFFFFFFU) +#define CTIMER_CR_CAP_SHIFT (0U) +#define CTIMER_CR_CAP(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CR_CAP_SHIFT)) & CTIMER_CR_CAP_MASK) +/*! @} */ + +/* The count of CTIMER_CR */ +#define CTIMER_CR_COUNT (4U) + +/*! @name EMR - External Match Register. The EMR controls the match function and the external match pins. */ +/*! @{ */ +#define CTIMER_EMR_EM0_MASK (0x1U) +#define CTIMER_EMR_EM0_SHIFT (0U) +#define CTIMER_EMR_EM0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM0_SHIFT)) & CTIMER_EMR_EM0_MASK) +#define CTIMER_EMR_EM1_MASK (0x2U) +#define CTIMER_EMR_EM1_SHIFT (1U) +#define CTIMER_EMR_EM1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM1_SHIFT)) & CTIMER_EMR_EM1_MASK) +#define CTIMER_EMR_EM2_MASK (0x4U) +#define CTIMER_EMR_EM2_SHIFT (2U) +#define CTIMER_EMR_EM2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM2_SHIFT)) & CTIMER_EMR_EM2_MASK) +#define CTIMER_EMR_EM3_MASK (0x8U) +#define CTIMER_EMR_EM3_SHIFT (3U) +#define CTIMER_EMR_EM3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM3_SHIFT)) & CTIMER_EMR_EM3_MASK) +#define CTIMER_EMR_EMC0_MASK (0x30U) +#define CTIMER_EMR_EMC0_SHIFT (4U) +/*! EMC0 - External Match Control 0. Determines the functionality of External Match 0. + * 0b00..Do Nothing. + * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT0 pin is LOW if pinned out). + * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT0 pin is HIGH if pinned out). + * 0b11..Toggle. Toggle the corresponding External Match bit/output. + */ +#define CTIMER_EMR_EMC0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC0_SHIFT)) & CTIMER_EMR_EMC0_MASK) +#define CTIMER_EMR_EMC1_MASK (0xC0U) +#define CTIMER_EMR_EMC1_SHIFT (6U) +/*! EMC1 - External Match Control 1. Determines the functionality of External Match 1. + * 0b00..Do Nothing. + * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT1 pin is LOW if pinned out). + * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT1 pin is HIGH if pinned out). + * 0b11..Toggle. Toggle the corresponding External Match bit/output. + */ +#define CTIMER_EMR_EMC1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC1_SHIFT)) & CTIMER_EMR_EMC1_MASK) +#define CTIMER_EMR_EMC2_MASK (0x300U) +#define CTIMER_EMR_EMC2_SHIFT (8U) +/*! EMC2 - External Match Control 2. Determines the functionality of External Match 2. + * 0b00..Do Nothing. + * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT2 pin is LOW if pinned out). + * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT2 pin is HIGH if pinned out). + * 0b11..Toggle. Toggle the corresponding External Match bit/output. + */ +#define CTIMER_EMR_EMC2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC2_SHIFT)) & CTIMER_EMR_EMC2_MASK) +#define CTIMER_EMR_EMC3_MASK (0xC00U) +#define CTIMER_EMR_EMC3_SHIFT (10U) +/*! EMC3 - External Match Control 3. Determines the functionality of External Match 3. + * 0b00..Do Nothing. + * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT3 pin is LOW if pinned out). + * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT3 pin is HIGH if pinned out). + * 0b11..Toggle. Toggle the corresponding External Match bit/output. + */ +#define CTIMER_EMR_EMC3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC3_SHIFT)) & CTIMER_EMR_EMC3_MASK) +/*! @} */ + +/*! @name CTCR - Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */ +/*! @{ */ +#define CTIMER_CTCR_CTMODE_MASK (0x3U) +#define CTIMER_CTCR_CTMODE_SHIFT (0U) +/*! CTMODE - Counter/Timer Mode This field selects which rising APB bus clock edges can increment + * Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC + * is incremented when the Prescale Counter matches the Prescale Register. + * 0b00..Timer Mode. Incremented every rising APB bus clock edge. + * 0b01..Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2. + * 0b10..Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2. + * 0b11..Counter Mode dual edge. TC is incremented on both edges on the CAP input selected by bits 3:2. + */ +#define CTIMER_CTCR_CTMODE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CTMODE_SHIFT)) & CTIMER_CTCR_CTMODE_MASK) +#define CTIMER_CTCR_CINSEL_MASK (0xCU) +#define CTIMER_CTCR_CINSEL_SHIFT (2U) +/*! CINSEL - Count Input Select When bits 1:0 in this register are not 00, these bits select which + * CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input + * in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be + * programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the + * same timer. + * 0b00..Channel 0. CAPn.0 for CTIMERn + * 0b01..Channel 1. CAPn.1 for CTIMERn + * 0b10..Channel 2. CAPn.2 for CTIMERn + * 0b11..Channel 3. CAPn.3 for CTIMERn + */ +#define CTIMER_CTCR_CINSEL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CINSEL_SHIFT)) & CTIMER_CTCR_CINSEL_MASK) +#define CTIMER_CTCR_ENCC_MASK (0x10U) +#define CTIMER_CTCR_ENCC_SHIFT (4U) +#define CTIMER_CTCR_ENCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_ENCC_SHIFT)) & CTIMER_CTCR_ENCC_MASK) +#define CTIMER_CTCR_SELCC_MASK (0xE0U) +#define CTIMER_CTCR_SELCC_SHIFT (5U) +/*! SELCC - Edge select. When bit 4 is 1, these bits select which capture input edge will cause the + * timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to + * 0x3 and 0x6 to 0x7 are reserved. + * 0b000..Channel 0 Rising Edge. Rising edge of the signal on capture channel 0 clears the timer (if bit 4 is set). + * 0b001..Channel 0 Falling Edge. Falling edge of the signal on capture channel 0 clears the timer (if bit 4 is set). + * 0b010..Channel 1 Rising Edge. Rising edge of the signal on capture channel 1 clears the timer (if bit 4 is set). + * 0b011..Channel 1 Falling Edge. Falling edge of the signal on capture channel 1 clears the timer (if bit 4 is set). + * 0b100..Channel 2 Rising Edge. Rising edge of the signal on capture channel 2 clears the timer (if bit 4 is set). + * 0b101..Channel 2 Falling Edge. Falling edge of the signal on capture channel 2 clears the timer (if bit 4 is set). + */ +#define CTIMER_CTCR_SELCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_SELCC_SHIFT)) & CTIMER_CTCR_SELCC_MASK) +/*! @} */ + +/*! @name PWMC - PWM Control Register. This register enables PWM mode for the external match pins. */ +/*! @{ */ +#define CTIMER_PWMC_PWMEN0_MASK (0x1U) +#define CTIMER_PWMC_PWMEN0_SHIFT (0U) +/*! PWMEN0 - PWM mode enable for channel0. + * 0b0..Match. CTIMERn_MAT0 is controlled by EM0. + * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT0. + */ +#define CTIMER_PWMC_PWMEN0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN0_SHIFT)) & CTIMER_PWMC_PWMEN0_MASK) +#define CTIMER_PWMC_PWMEN1_MASK (0x2U) +#define CTIMER_PWMC_PWMEN1_SHIFT (1U) +/*! PWMEN1 - PWM mode enable for channel1. + * 0b0..Match. CTIMERn_MAT01 is controlled by EM1. + * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT1. + */ +#define CTIMER_PWMC_PWMEN1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN1_SHIFT)) & CTIMER_PWMC_PWMEN1_MASK) +#define CTIMER_PWMC_PWMEN2_MASK (0x4U) +#define CTIMER_PWMC_PWMEN2_SHIFT (2U) +/*! PWMEN2 - PWM mode enable for channel2. + * 0b0..Match. CTIMERn_MAT2 is controlled by EM2. + * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT2. + */ +#define CTIMER_PWMC_PWMEN2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN2_SHIFT)) & CTIMER_PWMC_PWMEN2_MASK) +#define CTIMER_PWMC_PWMEN3_MASK (0x8U) +#define CTIMER_PWMC_PWMEN3_SHIFT (3U) +/*! PWMEN3 - PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle. + * 0b0..Match. CTIMERn_MAT3 is controlled by EM3. + * 0b1..PWM. PWM mode is enabled for CT132Bn_MAT3. + */ +#define CTIMER_PWMC_PWMEN3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN3_SHIFT)) & CTIMER_PWMC_PWMEN3_MASK) +/*! @} */ + +/*! @name MSR - Match Shadow Register */ +/*! @{ */ +#define CTIMER_MSR_SHADOWW_MASK (0xFFFFFFFFU) +#define CTIMER_MSR_SHADOWW_SHIFT (0U) +#define CTIMER_MSR_SHADOWW(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MSR_SHADOWW_SHIFT)) & CTIMER_MSR_SHADOWW_MASK) +/*! @} */ + +/* The count of CTIMER_MSR */ +#define CTIMER_MSR_COUNT (4U) + + +/*! + * @} + */ /* end of group CTIMER_Register_Masks */ + + +/* CTIMER - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral CTIMER0 base address */ + #define CTIMER0_BASE (0x50008000u) + /** Peripheral CTIMER0 base address */ + #define CTIMER0_BASE_NS (0x40008000u) + /** Peripheral CTIMER0 base pointer */ + #define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) + /** Peripheral CTIMER0 base pointer */ + #define CTIMER0_NS ((CTIMER_Type *)CTIMER0_BASE_NS) + /** Peripheral CTIMER1 base address */ + #define CTIMER1_BASE (0x50009000u) + /** Peripheral CTIMER1 base address */ + #define CTIMER1_BASE_NS (0x40009000u) + /** Peripheral CTIMER1 base pointer */ + #define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) + /** Peripheral CTIMER1 base pointer */ + #define CTIMER1_NS ((CTIMER_Type *)CTIMER1_BASE_NS) + /** Peripheral CTIMER2 base address */ + #define CTIMER2_BASE (0x50028000u) + /** Peripheral CTIMER2 base address */ + #define CTIMER2_BASE_NS (0x40028000u) + /** Peripheral CTIMER2 base pointer */ + #define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE) + /** Peripheral CTIMER2 base pointer */ + #define CTIMER2_NS ((CTIMER_Type *)CTIMER2_BASE_NS) + /** Peripheral CTIMER3 base address */ + #define CTIMER3_BASE (0x50029000u) + /** Peripheral CTIMER3 base address */ + #define CTIMER3_BASE_NS (0x40029000u) + /** Peripheral CTIMER3 base pointer */ + #define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE) + /** Peripheral CTIMER3 base pointer */ + #define CTIMER3_NS ((CTIMER_Type *)CTIMER3_BASE_NS) + /** Peripheral CTIMER4 base address */ + #define CTIMER4_BASE (0x5002A000u) + /** Peripheral CTIMER4 base address */ + #define CTIMER4_BASE_NS (0x4002A000u) + /** Peripheral CTIMER4 base pointer */ + #define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE) + /** Peripheral CTIMER4 base pointer */ + #define CTIMER4_NS ((CTIMER_Type *)CTIMER4_BASE_NS) + /** Array initializer of CTIMER peripheral base addresses */ + #define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE } + /** Array initializer of CTIMER peripheral base pointers */ + #define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 } + /** Array initializer of CTIMER peripheral base addresses */ + #define CTIMER_BASE_ADDRS_NS { CTIMER0_BASE_NS, CTIMER1_BASE_NS, CTIMER2_BASE_NS, CTIMER3_BASE_NS, CTIMER4_BASE_NS } + /** Array initializer of CTIMER peripheral base pointers */ + #define CTIMER_BASE_PTRS_NS { CTIMER0_NS, CTIMER1_NS, CTIMER2_NS, CTIMER3_NS, CTIMER4_NS } +#else + /** Peripheral CTIMER0 base address */ + #define CTIMER0_BASE (0x40008000u) + /** Peripheral CTIMER0 base pointer */ + #define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) + /** Peripheral CTIMER1 base address */ + #define CTIMER1_BASE (0x40009000u) + /** Peripheral CTIMER1 base pointer */ + #define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) + /** Peripheral CTIMER2 base address */ + #define CTIMER2_BASE (0x40028000u) + /** Peripheral CTIMER2 base pointer */ + #define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE) + /** Peripheral CTIMER3 base address */ + #define CTIMER3_BASE (0x40029000u) + /** Peripheral CTIMER3 base pointer */ + #define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE) + /** Peripheral CTIMER4 base address */ + #define CTIMER4_BASE (0x4002A000u) + /** Peripheral CTIMER4 base pointer */ + #define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE) + /** Array initializer of CTIMER peripheral base addresses */ + #define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE } + /** Array initializer of CTIMER peripheral base pointers */ + #define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 } +#endif +/** Interrupt vectors for the CTIMER peripheral type */ +#define CTIMER_IRQS { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn, CTIMER3_IRQn, CTIMER4_IRQn } + +/*! + * @} + */ /* end of group CTIMER_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DGBMAILBOX Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DGBMAILBOX_Peripheral_Access_Layer DGBMAILBOX Peripheral Access Layer + * @{ + */ + +/** DGBMAILBOX - Register Layout Typedef */ +typedef struct { + __IO uint32_t CSW; /**< CRC mode register, offset: 0x0 */ + __IO uint32_t REQUEST; /**< CRC seed register, offset: 0x4 */ + __IO uint32_t RETURN; /**< Return value from ROM., offset: 0x8 */ + uint8_t RESERVED_0[240]; + __I uint32_t ID; /**< Identification register, offset: 0xFC */ +} DGBMAILBOX_Type; + +/* ---------------------------------------------------------------------------- + -- DGBMAILBOX Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DGBMAILBOX_Register_Masks DGBMAILBOX Register Masks + * @{ + */ + +/*! @name CSW - CRC mode register */ +/*! @{ */ +#define DGBMAILBOX_CSW_RESYNCH_REQ_MASK (0x1U) +#define DGBMAILBOX_CSW_RESYNCH_REQ_SHIFT (0U) +#define DGBMAILBOX_CSW_RESYNCH_REQ(x) (((uint32_t)(((uint32_t)(x)) << DGBMAILBOX_CSW_RESYNCH_REQ_SHIFT)) & DGBMAILBOX_CSW_RESYNCH_REQ_MASK) +#define DGBMAILBOX_CSW_REQ_PENDING_MASK (0x2U) +#define DGBMAILBOX_CSW_REQ_PENDING_SHIFT (1U) +#define DGBMAILBOX_CSW_REQ_PENDING(x) (((uint32_t)(((uint32_t)(x)) << DGBMAILBOX_CSW_REQ_PENDING_SHIFT)) & DGBMAILBOX_CSW_REQ_PENDING_MASK) +#define DGBMAILBOX_CSW_DBG_OR_ERR_MASK (0x4U) +#define DGBMAILBOX_CSW_DBG_OR_ERR_SHIFT (2U) +#define DGBMAILBOX_CSW_DBG_OR_ERR(x) (((uint32_t)(((uint32_t)(x)) << DGBMAILBOX_CSW_DBG_OR_ERR_SHIFT)) & DGBMAILBOX_CSW_DBG_OR_ERR_MASK) +#define DGBMAILBOX_CSW_AHB_OR_ERR_MASK (0x8U) +#define DGBMAILBOX_CSW_AHB_OR_ERR_SHIFT (3U) +#define DGBMAILBOX_CSW_AHB_OR_ERR(x) (((uint32_t)(((uint32_t)(x)) << DGBMAILBOX_CSW_AHB_OR_ERR_SHIFT)) & DGBMAILBOX_CSW_AHB_OR_ERR_MASK) +#define DGBMAILBOX_CSW_SOFT_RESET_MASK (0x10U) +#define DGBMAILBOX_CSW_SOFT_RESET_SHIFT (4U) +#define DGBMAILBOX_CSW_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << DGBMAILBOX_CSW_SOFT_RESET_SHIFT)) & DGBMAILBOX_CSW_SOFT_RESET_MASK) +#define DGBMAILBOX_CSW_CHIP_RESET_REQ_MASK (0x20U) +#define DGBMAILBOX_CSW_CHIP_RESET_REQ_SHIFT (5U) +#define DGBMAILBOX_CSW_CHIP_RESET_REQ(x) (((uint32_t)(((uint32_t)(x)) << DGBMAILBOX_CSW_CHIP_RESET_REQ_SHIFT)) & DGBMAILBOX_CSW_CHIP_RESET_REQ_MASK) +/*! @} */ + +/*! @name REQUEST - CRC seed register */ +/*! @{ */ +#define DGBMAILBOX_REQUEST_REQ_MASK (0xFFFFFFFFU) +#define DGBMAILBOX_REQUEST_REQ_SHIFT (0U) +#define DGBMAILBOX_REQUEST_REQ(x) (((uint32_t)(((uint32_t)(x)) << DGBMAILBOX_REQUEST_REQ_SHIFT)) & DGBMAILBOX_REQUEST_REQ_MASK) +/*! @} */ + +/*! @name RETURN - Return value from ROM. */ +/*! @{ */ +#define DGBMAILBOX_RETURN_RET_MASK (0xFFFFFFFFU) +#define DGBMAILBOX_RETURN_RET_SHIFT (0U) +#define DGBMAILBOX_RETURN_RET(x) (((uint32_t)(((uint32_t)(x)) << DGBMAILBOX_RETURN_RET_SHIFT)) & DGBMAILBOX_RETURN_RET_MASK) +/*! @} */ + +/*! @name ID - Identification register */ +/*! @{ */ +#define DGBMAILBOX_ID_ID_MASK (0xFFFFFFFFU) +#define DGBMAILBOX_ID_ID_SHIFT (0U) +#define DGBMAILBOX_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << DGBMAILBOX_ID_ID_SHIFT)) & DGBMAILBOX_ID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group DGBMAILBOX_Register_Masks */ + + +/* DGBMAILBOX - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral DGBMAILBOX base address */ + #define DGBMAILBOX_BASE (0x5009C000u) + /** Peripheral DGBMAILBOX base address */ + #define DGBMAILBOX_BASE_NS (0x4009C000u) + /** Peripheral DGBMAILBOX base pointer */ + #define DGBMAILBOX ((DGBMAILBOX_Type *)DGBMAILBOX_BASE) + /** Peripheral DGBMAILBOX base pointer */ + #define DGBMAILBOX_NS ((DGBMAILBOX_Type *)DGBMAILBOX_BASE_NS) + /** Array initializer of DGBMAILBOX peripheral base addresses */ + #define DGBMAILBOX_BASE_ADDRS { DGBMAILBOX_BASE } + /** Array initializer of DGBMAILBOX peripheral base pointers */ + #define DGBMAILBOX_BASE_PTRS { DGBMAILBOX } + /** Array initializer of DGBMAILBOX peripheral base addresses */ + #define DGBMAILBOX_BASE_ADDRS_NS { DGBMAILBOX_BASE_NS } + /** Array initializer of DGBMAILBOX peripheral base pointers */ + #define DGBMAILBOX_BASE_PTRS_NS { DGBMAILBOX_NS } +#else + /** Peripheral DGBMAILBOX base address */ + #define DGBMAILBOX_BASE (0x4009C000u) + /** Peripheral DGBMAILBOX base pointer */ + #define DGBMAILBOX ((DGBMAILBOX_Type *)DGBMAILBOX_BASE) + /** Array initializer of DGBMAILBOX peripheral base addresses */ + #define DGBMAILBOX_BASE_ADDRS { DGBMAILBOX_BASE } + /** Array initializer of DGBMAILBOX peripheral base pointers */ + #define DGBMAILBOX_BASE_PTRS { DGBMAILBOX } +#endif + +/*! + * @} + */ /* end of group DGBMAILBOX_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DMA Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer + * @{ + */ + +/** DMA - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< DMA control., offset: 0x0 */ + __I uint32_t INTSTAT; /**< Interrupt status., offset: 0x4 */ + __IO uint32_t SRAMBASE; /**< SRAM address of the channel configuration table., offset: 0x8 */ + uint8_t RESERVED_0[20]; + struct { /* offset: 0x20, array step: 0x5C */ + __IO uint32_t ENABLESET; /**< Channel Enable read and Set for all DMA channels., array offset: 0x20, array step: 0x5C */ + uint8_t RESERVED_0[4]; + __O uint32_t ENABLECLR; /**< Channel Enable Clear for all DMA channels., array offset: 0x28, array step: 0x5C */ + uint8_t RESERVED_1[4]; + __I uint32_t ACTIVE; /**< Channel Active status for all DMA channels., array offset: 0x30, array step: 0x5C */ + uint8_t RESERVED_2[4]; + __I uint32_t BUSY; /**< Channel Busy status for all DMA channels., array offset: 0x38, array step: 0x5C */ + uint8_t RESERVED_3[4]; + __IO uint32_t ERRINT; /**< Error Interrupt status for all DMA channels., array offset: 0x40, array step: 0x5C */ + uint8_t RESERVED_4[4]; + __IO uint32_t INTENSET; /**< Interrupt Enable read and Set for all DMA channels., array offset: 0x48, array step: 0x5C */ + uint8_t RESERVED_5[4]; + __O uint32_t INTENCLR; /**< Interrupt Enable Clear for all DMA channels., array offset: 0x50, array step: 0x5C */ + uint8_t RESERVED_6[4]; + __IO uint32_t INTA; /**< Interrupt A status for all DMA channels., array offset: 0x58, array step: 0x5C */ + uint8_t RESERVED_7[4]; + __IO uint32_t INTB; /**< Interrupt B status for all DMA channels., array offset: 0x60, array step: 0x5C */ + uint8_t RESERVED_8[4]; + __O uint32_t SETVALID; /**< Set ValidPending control bits for all DMA channels., array offset: 0x68, array step: 0x5C */ + uint8_t RESERVED_9[4]; + __O uint32_t SETTRIG; /**< Set Trigger control bits for all DMA channels., array offset: 0x70, array step: 0x5C */ + uint8_t RESERVED_10[4]; + __O uint32_t ABORT; /**< Channel Abort control for all DMA channels., array offset: 0x78, array step: 0x5C */ + } COMMON[1]; + uint8_t RESERVED_1[900]; + struct { /* offset: 0x400, array step: 0x10 */ + __IO uint32_t CFG; /**< Configuration register for DMA channel ., array offset: 0x400, array step: 0x10 */ + __I uint32_t CTLSTAT; /**< Control and status register for DMA channel ., array offset: 0x404, array step: 0x10 */ + __IO uint32_t XFERCFG; /**< Transfer configuration register for DMA channel ., array offset: 0x408, array step: 0x10 */ + uint8_t RESERVED_0[4]; + } CHANNEL[30]; +} DMA_Type; + +/* ---------------------------------------------------------------------------- + -- DMA Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMA_Register_Masks DMA Register Masks + * @{ + */ + +/*! @name CTRL - DMA control. */ +/*! @{ */ +#define DMA_CTRL_ENABLE_MASK (0x1U) +#define DMA_CTRL_ENABLE_SHIFT (0U) +/*! ENABLE - DMA controller master enable. + * 0b0..Disabled. The DMA controller is disabled. This clears any triggers that were asserted at the point when + * disabled, but does not prevent re-triggering when the DMA controller is re-enabled. + * 0b1..Enabled. The DMA controller is enabled. + */ +#define DMA_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CTRL_ENABLE_SHIFT)) & DMA_CTRL_ENABLE_MASK) +/*! @} */ + +/*! @name INTSTAT - Interrupt status. */ +/*! @{ */ +#define DMA_INTSTAT_ACTIVEINT_MASK (0x2U) +#define DMA_INTSTAT_ACTIVEINT_SHIFT (1U) +/*! ACTIVEINT - Summarizes whether any enabled interrupts (other than error interrupts) are pending. + * 0b0..Not pending. No enabled interrupts are pending. + * 0b1..Pending. At least one enabled interrupt is pending. + */ +#define DMA_INTSTAT_ACTIVEINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEINT_SHIFT)) & DMA_INTSTAT_ACTIVEINT_MASK) +#define DMA_INTSTAT_ACTIVEERRINT_MASK (0x4U) +#define DMA_INTSTAT_ACTIVEERRINT_SHIFT (2U) +/*! ACTIVEERRINT - Summarizes whether any error interrupts are pending. + * 0b0..Not pending. No error interrupts are pending. + * 0b1..Pending. At least one error interrupt is pending. + */ +#define DMA_INTSTAT_ACTIVEERRINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEERRINT_SHIFT)) & DMA_INTSTAT_ACTIVEERRINT_MASK) +/*! @} */ + +/*! @name SRAMBASE - SRAM address of the channel configuration table. */ +/*! @{ */ +#define DMA_SRAMBASE_OFFSET_MASK (0xFFFFFE00U) +#define DMA_SRAMBASE_OFFSET_SHIFT (9U) +#define DMA_SRAMBASE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << DMA_SRAMBASE_OFFSET_SHIFT)) & DMA_SRAMBASE_OFFSET_MASK) +/*! @} */ + +/*! @name COMMON_ENABLESET - Channel Enable read and Set for all DMA channels. */ +/*! @{ */ +#define DMA_COMMON_ENABLESET_ENA_MASK (0xFFFFFFFFU) +#define DMA_COMMON_ENABLESET_ENA_SHIFT (0U) +#define DMA_COMMON_ENABLESET_ENA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENA_SHIFT)) & DMA_COMMON_ENABLESET_ENA_MASK) +/*! @} */ + +/* The count of DMA_COMMON_ENABLESET */ +#define DMA_COMMON_ENABLESET_COUNT (1U) + +/*! @name COMMON_ENABLECLR - Channel Enable Clear for all DMA channels. */ +/*! @{ */ +#define DMA_COMMON_ENABLECLR_CLR_MASK (0xFFFFFFFFU) +#define DMA_COMMON_ENABLECLR_CLR_SHIFT (0U) +#define DMA_COMMON_ENABLECLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR_SHIFT)) & DMA_COMMON_ENABLECLR_CLR_MASK) +/*! @} */ + +/* The count of DMA_COMMON_ENABLECLR */ +#define DMA_COMMON_ENABLECLR_COUNT (1U) + +/*! @name COMMON_ACTIVE - Channel Active status for all DMA channels. */ +/*! @{ */ +#define DMA_COMMON_ACTIVE_ACT_MASK (0xFFFFFFFFU) +#define DMA_COMMON_ACTIVE_ACT_SHIFT (0U) +#define DMA_COMMON_ACTIVE_ACT(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACT_SHIFT)) & DMA_COMMON_ACTIVE_ACT_MASK) +/*! @} */ + +/* The count of DMA_COMMON_ACTIVE */ +#define DMA_COMMON_ACTIVE_COUNT (1U) + +/*! @name COMMON_BUSY - Channel Busy status for all DMA channels. */ +/*! @{ */ +#define DMA_COMMON_BUSY_BSY_MASK (0xFFFFFFFFU) +#define DMA_COMMON_BUSY_BSY_SHIFT (0U) +#define DMA_COMMON_BUSY_BSY(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BSY_SHIFT)) & DMA_COMMON_BUSY_BSY_MASK) +/*! @} */ + +/* The count of DMA_COMMON_BUSY */ +#define DMA_COMMON_BUSY_COUNT (1U) + +/*! @name COMMON_ERRINT - Error Interrupt status for all DMA channels. */ +/*! @{ */ +#define DMA_COMMON_ERRINT_ERR_MASK (0xFFFFFFFFU) +#define DMA_COMMON_ERRINT_ERR_SHIFT (0U) +#define DMA_COMMON_ERRINT_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR_SHIFT)) & DMA_COMMON_ERRINT_ERR_MASK) +/*! @} */ + +/* The count of DMA_COMMON_ERRINT */ +#define DMA_COMMON_ERRINT_COUNT (1U) + +/*! @name COMMON_INTENSET - Interrupt Enable read and Set for all DMA channels. */ +/*! @{ */ +#define DMA_COMMON_INTENSET_INTEN_MASK (0xFFFFFFFFU) +#define DMA_COMMON_INTENSET_INTEN_SHIFT (0U) +#define DMA_COMMON_INTENSET_INTEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN_SHIFT)) & DMA_COMMON_INTENSET_INTEN_MASK) +/*! @} */ + +/* The count of DMA_COMMON_INTENSET */ +#define DMA_COMMON_INTENSET_COUNT (1U) + +/*! @name COMMON_INTENCLR - Interrupt Enable Clear for all DMA channels. */ +/*! @{ */ +#define DMA_COMMON_INTENCLR_CLR_MASK (0xFFFFFFFFU) +#define DMA_COMMON_INTENCLR_CLR_SHIFT (0U) +#define DMA_COMMON_INTENCLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR_SHIFT)) & DMA_COMMON_INTENCLR_CLR_MASK) +/*! @} */ + +/* The count of DMA_COMMON_INTENCLR */ +#define DMA_COMMON_INTENCLR_COUNT (1U) + +/*! @name COMMON_INTA - Interrupt A status for all DMA channels. */ +/*! @{ */ +#define DMA_COMMON_INTA_IA_MASK (0xFFFFFFFFU) +#define DMA_COMMON_INTA_IA_SHIFT (0U) +#define DMA_COMMON_INTA_IA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_IA_SHIFT)) & DMA_COMMON_INTA_IA_MASK) +/*! @} */ + +/* The count of DMA_COMMON_INTA */ +#define DMA_COMMON_INTA_COUNT (1U) + +/*! @name COMMON_INTB - Interrupt B status for all DMA channels. */ +/*! @{ */ +#define DMA_COMMON_INTB_IB_MASK (0xFFFFFFFFU) +#define DMA_COMMON_INTB_IB_SHIFT (0U) +#define DMA_COMMON_INTB_IB(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_IB_SHIFT)) & DMA_COMMON_INTB_IB_MASK) +/*! @} */ + +/* The count of DMA_COMMON_INTB */ +#define DMA_COMMON_INTB_COUNT (1U) + +/*! @name COMMON_SETVALID - Set ValidPending control bits for all DMA channels. */ +/*! @{ */ +#define DMA_COMMON_SETVALID_SV_MASK (0xFFFFFFFFU) +#define DMA_COMMON_SETVALID_SV_SHIFT (0U) +#define DMA_COMMON_SETVALID_SV(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SV_SHIFT)) & DMA_COMMON_SETVALID_SV_MASK) +/*! @} */ + +/* The count of DMA_COMMON_SETVALID */ +#define DMA_COMMON_SETVALID_COUNT (1U) + +/*! @name COMMON_SETTRIG - Set Trigger control bits for all DMA channels. */ +/*! @{ */ +#define DMA_COMMON_SETTRIG_TRIG_MASK (0xFFFFFFFFU) +#define DMA_COMMON_SETTRIG_TRIG_SHIFT (0U) +#define DMA_COMMON_SETTRIG_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_TRIG_SHIFT)) & DMA_COMMON_SETTRIG_TRIG_MASK) +/*! @} */ + +/* The count of DMA_COMMON_SETTRIG */ +#define DMA_COMMON_SETTRIG_COUNT (1U) + +/*! @name COMMON_ABORT - Channel Abort control for all DMA channels. */ +/*! @{ */ +#define DMA_COMMON_ABORT_ABORTCTRL_MASK (0xFFFFFFFFU) +#define DMA_COMMON_ABORT_ABORTCTRL_SHIFT (0U) +#define DMA_COMMON_ABORT_ABORTCTRL(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORTCTRL_SHIFT)) & DMA_COMMON_ABORT_ABORTCTRL_MASK) +/*! @} */ + +/* The count of DMA_COMMON_ABORT */ +#define DMA_COMMON_ABORT_COUNT (1U) + +/*! @name CHANNEL_CFG - Configuration register for DMA channel . */ +/*! @{ */ +#define DMA_CHANNEL_CFG_PERIPHREQEN_MASK (0x1U) +#define DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT (0U) +/*! PERIPHREQEN - Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory + * move, any peripheral DMA request associated with that channel can be disabled to prevent any + * interaction between the peripheral and the DMA controller. + * 0b0..Disabled. Peripheral DMA requests are disabled. + * 0b1..Enabled. Peripheral DMA requests are enabled. + */ +#define DMA_CHANNEL_CFG_PERIPHREQEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT)) & DMA_CHANNEL_CFG_PERIPHREQEN_MASK) +#define DMA_CHANNEL_CFG_HWTRIGEN_MASK (0x2U) +#define DMA_CHANNEL_CFG_HWTRIGEN_SHIFT (1U) +/*! HWTRIGEN - Hardware Triggering Enable for this channel. + * 0b0..Disabled. Hardware triggering is not used. + * 0b1..Enabled. Use hardware triggering. + */ +#define DMA_CHANNEL_CFG_HWTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_HWTRIGEN_SHIFT)) & DMA_CHANNEL_CFG_HWTRIGEN_MASK) +#define DMA_CHANNEL_CFG_TRIGPOL_MASK (0x10U) +#define DMA_CHANNEL_CFG_TRIGPOL_SHIFT (4U) +/*! TRIGPOL - Trigger Polarity. Selects the polarity of a hardware trigger for this channel. + * 0b0..Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE. + * 0b1..Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE. + */ +#define DMA_CHANNEL_CFG_TRIGPOL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGPOL_SHIFT)) & DMA_CHANNEL_CFG_TRIGPOL_MASK) +#define DMA_CHANNEL_CFG_TRIGTYPE_MASK (0x20U) +#define DMA_CHANNEL_CFG_TRIGTYPE_SHIFT (5U) +/*! TRIGTYPE - Trigger Type. Selects hardware trigger as edge triggered or level triggered. + * 0b0..Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger. + * 0b1..Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = + * 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the + * trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger + * is, again, asserted. However, the transfer will not be paused until any remaining transfers within the + * current BURSTPOWER length are completed. + */ +#define DMA_CHANNEL_CFG_TRIGTYPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGTYPE_SHIFT)) & DMA_CHANNEL_CFG_TRIGTYPE_MASK) +#define DMA_CHANNEL_CFG_TRIGBURST_MASK (0x40U) +#define DMA_CHANNEL_CFG_TRIGBURST_SHIFT (6U) +/*! TRIGBURST - Trigger Burst. Selects whether hardware triggers cause a single or burst transfer. + * 0b0..Single transfer. Hardware trigger causes a single transfer. + * 0b1..Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a + * burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a + * hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is + * complete. + */ +#define DMA_CHANNEL_CFG_TRIGBURST(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGBURST_SHIFT)) & DMA_CHANNEL_CFG_TRIGBURST_MASK) +#define DMA_CHANNEL_CFG_BURSTPOWER_MASK (0xF00U) +#define DMA_CHANNEL_CFG_BURSTPOWER_SHIFT (8U) +#define DMA_CHANNEL_CFG_BURSTPOWER(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_BURSTPOWER_SHIFT)) & DMA_CHANNEL_CFG_BURSTPOWER_MASK) +#define DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK (0x4000U) +#define DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT (14U) +/*! SRCBURSTWRAP - Source Burst Wrap. When enabled, the source data address for the DMA is + * 'wrapped', meaning that the source address range for each burst will be the same. As an example, this + * could be used to read several sequential registers from a peripheral for each DMA burst, + * reading the same registers again for each burst. + * 0b0..Disabled. Source burst wrapping is not enabled for this DMA channel. + * 0b1..Enabled. Source burst wrapping is enabled for this DMA channel. + */ +#define DMA_CHANNEL_CFG_SRCBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK) +#define DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK (0x8000U) +#define DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT (15U) +/*! DSTBURSTWRAP - Destination Burst Wrap. When enabled, the destination data address for the DMA is + * 'wrapped', meaning that the destination address range for each burst will be the same. As an + * example, this could be used to write several sequential registers to a peripheral for each DMA + * burst, writing the same registers again for each burst. + * 0b0..Disabled. Destination burst wrapping is not enabled for this DMA channel. + * 0b1..Enabled. Destination burst wrapping is enabled for this DMA channel. + */ +#define DMA_CHANNEL_CFG_DSTBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK) +#define DMA_CHANNEL_CFG_CHPRIORITY_MASK (0x70000U) +#define DMA_CHANNEL_CFG_CHPRIORITY_SHIFT (16U) +#define DMA_CHANNEL_CFG_CHPRIORITY(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_CHPRIORITY_SHIFT)) & DMA_CHANNEL_CFG_CHPRIORITY_MASK) +/*! @} */ + +/* The count of DMA_CHANNEL_CFG */ +#define DMA_CHANNEL_CFG_COUNT (30U) + +/*! @name CHANNEL_CTLSTAT - Control and status register for DMA channel . */ +/*! @{ */ +#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK (0x1U) +#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT (0U) +/*! VALIDPENDING - Valid pending flag for this channel. This bit is set when a 1 is written to the + * corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel. + * 0b0..No effect. No effect on DMA operation. + * 0b1..Valid pending. + */ +#define DMA_CHANNEL_CTLSTAT_VALIDPENDING(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT)) & DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK) +#define DMA_CHANNEL_CTLSTAT_TRIG_MASK (0x4U) +#define DMA_CHANNEL_CTLSTAT_TRIG_SHIFT (2U) +/*! TRIG - Trigger flag. Indicates that the trigger for this channel is currently set. This bit is + * cleared at the end of an entire transfer or upon reload when CLRTRIG = 1. + * 0b0..Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out. + * 0b1..Triggered. The trigger for this DMA channel is set. DMA operations will be carried out. + */ +#define DMA_CHANNEL_CTLSTAT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_TRIG_SHIFT)) & DMA_CHANNEL_CTLSTAT_TRIG_MASK) +/*! @} */ + +/* The count of DMA_CHANNEL_CTLSTAT */ +#define DMA_CHANNEL_CTLSTAT_COUNT (30U) + +/*! @name CHANNEL_XFERCFG - Transfer configuration register for DMA channel . */ +/*! @{ */ +#define DMA_CHANNEL_XFERCFG_CFGVALID_MASK (0x1U) +#define DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT (0U) +/*! CFGVALID - Configuration Valid flag. This bit indicates whether the current channel descriptor + * is valid and can potentially be acted upon, if all other activation criteria are fulfilled. + * 0b0..Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting. + * 0b1..Valid. The current channel descriptor is considered valid. + */ +#define DMA_CHANNEL_XFERCFG_CFGVALID(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT)) & DMA_CHANNEL_XFERCFG_CFGVALID_MASK) +#define DMA_CHANNEL_XFERCFG_RELOAD_MASK (0x2U) +#define DMA_CHANNEL_XFERCFG_RELOAD_SHIFT (1U) +/*! RELOAD - Indicates whether the channel's control structure will be reloaded when the current + * descriptor is exhausted. Reloading allows ping-pong and linked transfers. + * 0b0..Disabled. Do not reload the channels' control structure when the current descriptor is exhausted. + * 0b1..Enabled. Reload the channels' control structure when the current descriptor is exhausted. + */ +#define DMA_CHANNEL_XFERCFG_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_RELOAD_SHIFT)) & DMA_CHANNEL_XFERCFG_RELOAD_MASK) +#define DMA_CHANNEL_XFERCFG_SWTRIG_MASK (0x4U) +#define DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT (2U) +/*! SWTRIG - Software Trigger. + * 0b0..Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by + * the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel. + * 0b1..Set. When written by software, the trigger for this channel is set immediately. This feature should not + * be used with level triggering when TRIGBURST = 0. + */ +#define DMA_CHANNEL_XFERCFG_SWTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_SWTRIG_MASK) +#define DMA_CHANNEL_XFERCFG_CLRTRIG_MASK (0x8U) +#define DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT (3U) +/*! CLRTRIG - Clear Trigger. + * 0b0..Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started. + * 0b1..Cleared. The trigger is cleared when this descriptor is exhausted + */ +#define DMA_CHANNEL_XFERCFG_CLRTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_CLRTRIG_MASK) +#define DMA_CHANNEL_XFERCFG_SETINTA_MASK (0x10U) +#define DMA_CHANNEL_XFERCFG_SETINTA_SHIFT (4U) +/*! SETINTA - Set Interrupt flag A for this channel. There is no hardware distinction between + * interrupt A and B. They can be used by software to assist with more complex descriptor usage. By + * convention, interrupt A may be used when only one interrupt flag is needed. + * 0b0..No effect. + * 0b1..Set. The INTA flag for this channel will be set when the current descriptor is exhausted. + */ +#define DMA_CHANNEL_XFERCFG_SETINTA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTA_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTA_MASK) +#define DMA_CHANNEL_XFERCFG_SETINTB_MASK (0x20U) +#define DMA_CHANNEL_XFERCFG_SETINTB_SHIFT (5U) +/*! SETINTB - Set Interrupt flag B for this channel. There is no hardware distinction between + * interrupt A and B. They can be used by software to assist with more complex descriptor usage. By + * convention, interrupt A may be used when only one interrupt flag is needed. + * 0b0..No effect. + * 0b1..Set. The INTB flag for this channel will be set when the current descriptor is exhausted. + */ +#define DMA_CHANNEL_XFERCFG_SETINTB(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTB_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTB_MASK) +#define DMA_CHANNEL_XFERCFG_WIDTH_MASK (0x300U) +#define DMA_CHANNEL_XFERCFG_WIDTH_SHIFT (8U) +/*! WIDTH - Transfer width used for this DMA channel. + * 0b00..8-bit. 8-bit transfers are performed (8-bit source reads and destination writes). + * 0b01..16-bit. 6-bit transfers are performed (16-bit source reads and destination writes). + * 0b10..32-bit. 32-bit transfers are performed (32-bit source reads and destination writes). + * 0b11..Reserved. Reserved setting, do not use. + */ +#define DMA_CHANNEL_XFERCFG_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_WIDTH_SHIFT)) & DMA_CHANNEL_XFERCFG_WIDTH_MASK) +#define DMA_CHANNEL_XFERCFG_SRCINC_MASK (0x3000U) +#define DMA_CHANNEL_XFERCFG_SRCINC_SHIFT (12U) +/*! SRCINC - Determines whether the source address is incremented for each DMA transfer. + * 0b00..No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device. + * 0b01..1 x width. The source address is incremented by the amount specified by Width for each transfer. This is + * the usual case when the source is memory. + * 0b10..2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer. + * 0b11..4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer. + */ +#define DMA_CHANNEL_XFERCFG_SRCINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SRCINC_SHIFT)) & DMA_CHANNEL_XFERCFG_SRCINC_MASK) +#define DMA_CHANNEL_XFERCFG_DSTINC_MASK (0xC000U) +#define DMA_CHANNEL_XFERCFG_DSTINC_SHIFT (14U) +/*! DSTINC - Determines whether the destination address is incremented for each DMA transfer. + * 0b00..No increment. The destination address is not incremented for each transfer. This is the usual case when + * the destination is a peripheral device. + * 0b01..1 x width. The destination address is incremented by the amount specified by Width for each transfer. + * This is the usual case when the destination is memory. + * 0b10..2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer. + * 0b11..4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer. + */ +#define DMA_CHANNEL_XFERCFG_DSTINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_DSTINC_SHIFT)) & DMA_CHANNEL_XFERCFG_DSTINC_MASK) +#define DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK (0x3FF0000U) +#define DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT (16U) +#define DMA_CHANNEL_XFERCFG_XFERCOUNT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT)) & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) +/*! @} */ + +/* The count of DMA_CHANNEL_XFERCFG */ +#define DMA_CHANNEL_XFERCFG_COUNT (30U) + + +/*! + * @} + */ /* end of group DMA_Register_Masks */ + + +/* DMA - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral DMA0 base address */ + #define DMA0_BASE (0x50082000u) + /** Peripheral DMA0 base address */ + #define DMA0_BASE_NS (0x40082000u) + /** Peripheral DMA0 base pointer */ + #define DMA0 ((DMA_Type *)DMA0_BASE) + /** Peripheral DMA0 base pointer */ + #define DMA0_NS ((DMA_Type *)DMA0_BASE_NS) + /** Peripheral DMA1 base address */ + #define DMA1_BASE (0x500A7000u) + /** Peripheral DMA1 base address */ + #define DMA1_BASE_NS (0x400A7000u) + /** Peripheral DMA1 base pointer */ + #define DMA1 ((DMA_Type *)DMA1_BASE) + /** Peripheral DMA1 base pointer */ + #define DMA1_NS ((DMA_Type *)DMA1_BASE_NS) + /** Array initializer of DMA peripheral base addresses */ + #define DMA_BASE_ADDRS { DMA0_BASE, DMA1_BASE } + /** Array initializer of DMA peripheral base pointers */ + #define DMA_BASE_PTRS { DMA0, DMA1 } + /** Array initializer of DMA peripheral base addresses */ + #define DMA_BASE_ADDRS_NS { DMA0_BASE_NS, DMA1_BASE_NS } + /** Array initializer of DMA peripheral base pointers */ + #define DMA_BASE_PTRS_NS { DMA0_NS, DMA1_NS } +#else + /** Peripheral DMA0 base address */ + #define DMA0_BASE (0x40082000u) + /** Peripheral DMA0 base pointer */ + #define DMA0 ((DMA_Type *)DMA0_BASE) + /** Peripheral DMA1 base address */ + #define DMA1_BASE (0x400A7000u) + /** Peripheral DMA1 base pointer */ + #define DMA1 ((DMA_Type *)DMA1_BASE) + /** Array initializer of DMA peripheral base addresses */ + #define DMA_BASE_ADDRS { DMA0_BASE, DMA1_BASE } + /** Array initializer of DMA peripheral base pointers */ + #define DMA_BASE_PTRS { DMA0, DMA1 } +#endif +/** Interrupt vectors for the DMA peripheral type */ +#define DMA_IRQS { DMA0_IRQn, DMA1_IRQn } + +/*! + * @} + */ /* end of group DMA_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FLASH Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLASH_Peripheral_Access_Layer FLASH Peripheral Access Layer + * @{ + */ + +/** FLASH - Register Layout Typedef */ +typedef struct { + __O uint32_t CMD; /**< command register, offset: 0x0 */ + __O uint32_t EVENT; /**< event register, offset: 0x4 */ + __IO uint32_t BURST; /**< read burst register, offset: 0x8 */ + uint8_t RESERVED_0[4]; + __IO uint32_t STARTA; /**< start (or only) address for next flash command, offset: 0x10 */ + __IO uint32_t STOPA; /**< end address for next flash command, if command operates on address ranges, offset: 0x14 */ + uint8_t RESERVED_1[104]; + __IO uint32_t DATAW[8]; /**< data register, word 0-7; Memory data, or command parameter, or command result., array offset: 0x80, array step: 0x4 */ + uint8_t RESERVED_2[3896]; + __O uint32_t INT_CLR_ENABLE; /**< Clear interrupt enable bits, offset: 0xFD8 */ + __O uint32_t INT_SET_ENABLE; /**< Set interrupt enable bits, offset: 0xFDC */ + __I uint32_t INT_STATUS; /**< Interrupt status bits, offset: 0xFE0 */ + __I uint32_t INT_ENABLE; /**< Interrupt enable bits, offset: 0xFE4 */ + __O uint32_t INT_CLR_STATUS; /**< Clear interrupt status bits, offset: 0xFE8 */ + __O uint32_t INT_SET_STATUS; /**< Set interrupt status bits, offset: 0xFEC */ + uint8_t RESERVED_3[12]; + __I uint32_t MODULE_ID; /**< Controller+Memory module identification, offset: 0xFFC */ +} FLASH_Type; + +/* ---------------------------------------------------------------------------- + -- FLASH Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLASH_Register_Masks FLASH Register Masks + * @{ + */ + +/*! @name CMD - command register */ +/*! @{ */ +#define FLASH_CMD_CMD_MASK (0xFFFFFFFFU) +#define FLASH_CMD_CMD_SHIFT (0U) +#define FLASH_CMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMD_CMD_SHIFT)) & FLASH_CMD_CMD_MASK) +/*! @} */ + +/*! @name EVENT - event register */ +/*! @{ */ +#define FLASH_EVENT_RST_MASK (0x1U) +#define FLASH_EVENT_RST_SHIFT (0U) +#define FLASH_EVENT_RST(x) (((uint32_t)(((uint32_t)(x)) << FLASH_EVENT_RST_SHIFT)) & FLASH_EVENT_RST_MASK) +#define FLASH_EVENT_WAKEUP_MASK (0x2U) +#define FLASH_EVENT_WAKEUP_SHIFT (1U) +#define FLASH_EVENT_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << FLASH_EVENT_WAKEUP_SHIFT)) & FLASH_EVENT_WAKEUP_MASK) +#define FLASH_EVENT_ABORT_MASK (0x4U) +#define FLASH_EVENT_ABORT_SHIFT (2U) +#define FLASH_EVENT_ABORT(x) (((uint32_t)(((uint32_t)(x)) << FLASH_EVENT_ABORT_SHIFT)) & FLASH_EVENT_ABORT_MASK) +/*! @} */ + +/*! @name BURST - read burst register */ +/*! @{ */ +#define FLASH_BURST_XOR_MASK_MASK (0xFFFFFU) +#define FLASH_BURST_XOR_MASK_SHIFT (0U) +#define FLASH_BURST_XOR_MASK(x) (((uint32_t)(((uint32_t)(x)) << FLASH_BURST_XOR_MASK_SHIFT)) & FLASH_BURST_XOR_MASK_MASK) +#define FLASH_BURST_DESCR1_MASK (0xF00000U) +#define FLASH_BURST_DESCR1_SHIFT (20U) +#define FLASH_BURST_DESCR1(x) (((uint32_t)(((uint32_t)(x)) << FLASH_BURST_DESCR1_SHIFT)) & FLASH_BURST_DESCR1_MASK) +#define FLASH_BURST_DESCR2_MASK (0xF000000U) +#define FLASH_BURST_DESCR2_SHIFT (24U) +#define FLASH_BURST_DESCR2(x) (((uint32_t)(((uint32_t)(x)) << FLASH_BURST_DESCR2_SHIFT)) & FLASH_BURST_DESCR2_MASK) +#define FLASH_BURST_DESCR3_MASK (0xF0000000U) +#define FLASH_BURST_DESCR3_SHIFT (28U) +#define FLASH_BURST_DESCR3(x) (((uint32_t)(((uint32_t)(x)) << FLASH_BURST_DESCR3_SHIFT)) & FLASH_BURST_DESCR3_MASK) +/*! @} */ + +/*! @name STARTA - start (or only) address for next flash command */ +/*! @{ */ +#define FLASH_STARTA_STARTA_MASK (0x3FFFFU) +#define FLASH_STARTA_STARTA_SHIFT (0U) +#define FLASH_STARTA_STARTA(x) (((uint32_t)(((uint32_t)(x)) << FLASH_STARTA_STARTA_SHIFT)) & FLASH_STARTA_STARTA_MASK) +/*! @} */ + +/*! @name STOPA - end address for next flash command, if command operates on address ranges */ +/*! @{ */ +#define FLASH_STOPA_STOPA_MASK (0x3FFFFU) +#define FLASH_STOPA_STOPA_SHIFT (0U) +#define FLASH_STOPA_STOPA(x) (((uint32_t)(((uint32_t)(x)) << FLASH_STOPA_STOPA_SHIFT)) & FLASH_STOPA_STOPA_MASK) +/*! @} */ + +/*! @name DATAW - data register, word 0-7; Memory data, or command parameter, or command result. */ +/*! @{ */ +#define FLASH_DATAW_DATAW_MASK (0xFFFFFFFFU) +#define FLASH_DATAW_DATAW_SHIFT (0U) +#define FLASH_DATAW_DATAW(x) (((uint32_t)(((uint32_t)(x)) << FLASH_DATAW_DATAW_SHIFT)) & FLASH_DATAW_DATAW_MASK) +/*! @} */ + +/* The count of FLASH_DATAW */ +#define FLASH_DATAW_COUNT (8U) + +/*! @name INT_CLR_ENABLE - Clear interrupt enable bits */ +/*! @{ */ +#define FLASH_INT_CLR_ENABLE_FAIL_MASK (0x1U) +#define FLASH_INT_CLR_ENABLE_FAIL_SHIFT (0U) +#define FLASH_INT_CLR_ENABLE_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_FAIL_SHIFT)) & FLASH_INT_CLR_ENABLE_FAIL_MASK) +#define FLASH_INT_CLR_ENABLE_ERR_MASK (0x2U) +#define FLASH_INT_CLR_ENABLE_ERR_SHIFT (1U) +#define FLASH_INT_CLR_ENABLE_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_ERR_SHIFT)) & FLASH_INT_CLR_ENABLE_ERR_MASK) +#define FLASH_INT_CLR_ENABLE_DONE_MASK (0x4U) +#define FLASH_INT_CLR_ENABLE_DONE_SHIFT (2U) +#define FLASH_INT_CLR_ENABLE_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_DONE_SHIFT)) & FLASH_INT_CLR_ENABLE_DONE_MASK) +#define FLASH_INT_CLR_ENABLE_ECC_ERR_MASK (0x8U) +#define FLASH_INT_CLR_ENABLE_ECC_ERR_SHIFT (3U) +#define FLASH_INT_CLR_ENABLE_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_ECC_ERR_SHIFT)) & FLASH_INT_CLR_ENABLE_ECC_ERR_MASK) +/*! @} */ + +/*! @name INT_SET_ENABLE - Set interrupt enable bits */ +/*! @{ */ +#define FLASH_INT_SET_ENABLE_FAIL_MASK (0x1U) +#define FLASH_INT_SET_ENABLE_FAIL_SHIFT (0U) +#define FLASH_INT_SET_ENABLE_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_FAIL_SHIFT)) & FLASH_INT_SET_ENABLE_FAIL_MASK) +#define FLASH_INT_SET_ENABLE_ERR_MASK (0x2U) +#define FLASH_INT_SET_ENABLE_ERR_SHIFT (1U) +#define FLASH_INT_SET_ENABLE_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_ERR_SHIFT)) & FLASH_INT_SET_ENABLE_ERR_MASK) +#define FLASH_INT_SET_ENABLE_DONE_MASK (0x4U) +#define FLASH_INT_SET_ENABLE_DONE_SHIFT (2U) +#define FLASH_INT_SET_ENABLE_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_DONE_SHIFT)) & FLASH_INT_SET_ENABLE_DONE_MASK) +#define FLASH_INT_SET_ENABLE_ECC_ERR_MASK (0x8U) +#define FLASH_INT_SET_ENABLE_ECC_ERR_SHIFT (3U) +#define FLASH_INT_SET_ENABLE_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_ECC_ERR_SHIFT)) & FLASH_INT_SET_ENABLE_ECC_ERR_MASK) +/*! @} */ + +/*! @name INT_STATUS - Interrupt status bits */ +/*! @{ */ +#define FLASH_INT_STATUS_FAIL_MASK (0x1U) +#define FLASH_INT_STATUS_FAIL_SHIFT (0U) +#define FLASH_INT_STATUS_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_FAIL_SHIFT)) & FLASH_INT_STATUS_FAIL_MASK) +#define FLASH_INT_STATUS_ERR_MASK (0x2U) +#define FLASH_INT_STATUS_ERR_SHIFT (1U) +#define FLASH_INT_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_ERR_SHIFT)) & FLASH_INT_STATUS_ERR_MASK) +#define FLASH_INT_STATUS_DONE_MASK (0x4U) +#define FLASH_INT_STATUS_DONE_SHIFT (2U) +#define FLASH_INT_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_DONE_SHIFT)) & FLASH_INT_STATUS_DONE_MASK) +#define FLASH_INT_STATUS_ECC_ERR_MASK (0x8U) +#define FLASH_INT_STATUS_ECC_ERR_SHIFT (3U) +#define FLASH_INT_STATUS_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_ECC_ERR_SHIFT)) & FLASH_INT_STATUS_ECC_ERR_MASK) +/*! @} */ + +/*! @name INT_ENABLE - Interrupt enable bits */ +/*! @{ */ +#define FLASH_INT_ENABLE_FAIL_MASK (0x1U) +#define FLASH_INT_ENABLE_FAIL_SHIFT (0U) +#define FLASH_INT_ENABLE_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_FAIL_SHIFT)) & FLASH_INT_ENABLE_FAIL_MASK) +#define FLASH_INT_ENABLE_ERR_MASK (0x2U) +#define FLASH_INT_ENABLE_ERR_SHIFT (1U) +#define FLASH_INT_ENABLE_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_ERR_SHIFT)) & FLASH_INT_ENABLE_ERR_MASK) +#define FLASH_INT_ENABLE_DONE_MASK (0x4U) +#define FLASH_INT_ENABLE_DONE_SHIFT (2U) +#define FLASH_INT_ENABLE_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_DONE_SHIFT)) & FLASH_INT_ENABLE_DONE_MASK) +#define FLASH_INT_ENABLE_ECC_ERR_MASK (0x8U) +#define FLASH_INT_ENABLE_ECC_ERR_SHIFT (3U) +#define FLASH_INT_ENABLE_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_ECC_ERR_SHIFT)) & FLASH_INT_ENABLE_ECC_ERR_MASK) +/*! @} */ + +/*! @name INT_CLR_STATUS - Clear interrupt status bits */ +/*! @{ */ +#define FLASH_INT_CLR_STATUS_FAIL_MASK (0x1U) +#define FLASH_INT_CLR_STATUS_FAIL_SHIFT (0U) +#define FLASH_INT_CLR_STATUS_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_FAIL_SHIFT)) & FLASH_INT_CLR_STATUS_FAIL_MASK) +#define FLASH_INT_CLR_STATUS_ERR_MASK (0x2U) +#define FLASH_INT_CLR_STATUS_ERR_SHIFT (1U) +#define FLASH_INT_CLR_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_ERR_SHIFT)) & FLASH_INT_CLR_STATUS_ERR_MASK) +#define FLASH_INT_CLR_STATUS_DONE_MASK (0x4U) +#define FLASH_INT_CLR_STATUS_DONE_SHIFT (2U) +#define FLASH_INT_CLR_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_DONE_SHIFT)) & FLASH_INT_CLR_STATUS_DONE_MASK) +#define FLASH_INT_CLR_STATUS_ECC_ERR_MASK (0x8U) +#define FLASH_INT_CLR_STATUS_ECC_ERR_SHIFT (3U) +#define FLASH_INT_CLR_STATUS_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_ECC_ERR_SHIFT)) & FLASH_INT_CLR_STATUS_ECC_ERR_MASK) +/*! @} */ + +/*! @name INT_SET_STATUS - Set interrupt status bits */ +/*! @{ */ +#define FLASH_INT_SET_STATUS_FAIL_MASK (0x1U) +#define FLASH_INT_SET_STATUS_FAIL_SHIFT (0U) +#define FLASH_INT_SET_STATUS_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_FAIL_SHIFT)) & FLASH_INT_SET_STATUS_FAIL_MASK) +#define FLASH_INT_SET_STATUS_ERR_MASK (0x2U) +#define FLASH_INT_SET_STATUS_ERR_SHIFT (1U) +#define FLASH_INT_SET_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_ERR_SHIFT)) & FLASH_INT_SET_STATUS_ERR_MASK) +#define FLASH_INT_SET_STATUS_DONE_MASK (0x4U) +#define FLASH_INT_SET_STATUS_DONE_SHIFT (2U) +#define FLASH_INT_SET_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_DONE_SHIFT)) & FLASH_INT_SET_STATUS_DONE_MASK) +#define FLASH_INT_SET_STATUS_ECC_ERR_MASK (0x8U) +#define FLASH_INT_SET_STATUS_ECC_ERR_SHIFT (3U) +#define FLASH_INT_SET_STATUS_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_ECC_ERR_SHIFT)) & FLASH_INT_SET_STATUS_ECC_ERR_MASK) +/*! @} */ + +/*! @name MODULE_ID - Controller+Memory module identification */ +/*! @{ */ +#define FLASH_MODULE_ID_APERTURE_MASK (0xFFU) +#define FLASH_MODULE_ID_APERTURE_SHIFT (0U) +#define FLASH_MODULE_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_APERTURE_SHIFT)) & FLASH_MODULE_ID_APERTURE_MASK) +#define FLASH_MODULE_ID_MINOR_REV_MASK (0xF00U) +#define FLASH_MODULE_ID_MINOR_REV_SHIFT (8U) +#define FLASH_MODULE_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_MINOR_REV_SHIFT)) & FLASH_MODULE_ID_MINOR_REV_MASK) +#define FLASH_MODULE_ID_MAJOR_REV_MASK (0xF000U) +#define FLASH_MODULE_ID_MAJOR_REV_SHIFT (12U) +#define FLASH_MODULE_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_MAJOR_REV_SHIFT)) & FLASH_MODULE_ID_MAJOR_REV_MASK) +#define FLASH_MODULE_ID_ID_MASK (0xFFFF0000U) +#define FLASH_MODULE_ID_ID_SHIFT (16U) +#define FLASH_MODULE_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_ID_SHIFT)) & FLASH_MODULE_ID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group FLASH_Register_Masks */ + + +/* FLASH - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral FLASH base address */ + #define FLASH_BASE (0x50034000u) + /** Peripheral FLASH base address */ + #define FLASH_BASE_NS (0x40034000u) + /** Peripheral FLASH base pointer */ + #define FLASH ((FLASH_Type *)FLASH_BASE) + /** Peripheral FLASH base pointer */ + #define FLASH_NS ((FLASH_Type *)FLASH_BASE_NS) + /** Array initializer of FLASH peripheral base addresses */ + #define FLASH_BASE_ADDRS { FLASH_BASE } + /** Array initializer of FLASH peripheral base pointers */ + #define FLASH_BASE_PTRS { FLASH } + /** Array initializer of FLASH peripheral base addresses */ + #define FLASH_BASE_ADDRS_NS { FLASH_BASE_NS } + /** Array initializer of FLASH peripheral base pointers */ + #define FLASH_BASE_PTRS_NS { FLASH_NS } +#else + /** Peripheral FLASH base address */ + #define FLASH_BASE (0x40034000u) + /** Peripheral FLASH base pointer */ + #define FLASH ((FLASH_Type *)FLASH_BASE) + /** Array initializer of FLASH peripheral base addresses */ + #define FLASH_BASE_ADDRS { FLASH_BASE } + /** Array initializer of FLASH peripheral base pointers */ + #define FLASH_BASE_PTRS { FLASH } +#endif + +/*! + * @} + */ /* end of group FLASH_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FLASH_CFPA Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLASH_CFPA_Peripheral_Access_Layer FLASH_CFPA Peripheral Access Layer + * @{ + */ + +/** FLASH_CFPA - Register Layout Typedef */ +typedef struct { + __IO uint32_t HEADER; /**< ., offset: 0x0 */ + __IO uint32_t VERSION; /**< ., offset: 0x4 */ + __IO uint32_t S_FW_VERSION; /**< Secure firmware version (Monotonic counter), offset: 0x8 */ + __IO uint32_t NS_FW_VERSION; /**< Non-Secure firmware version (Monotonic counter), offset: 0xC */ + __IO uint32_t IMAGE_KEY_REVOKE; /**< Image key revocation ID (Monotonic counter), offset: 0x10 */ + uint8_t RESERVED_0[4]; + __IO uint32_t ROTKH_REVOKE; /**< ., offset: 0x18 */ + __IO uint32_t VENDOR_USAGE; /**< ., offset: 0x1C */ + __IO uint32_t DCFG_CC_SOCU_PIN; /**< With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access., offset: 0x20 */ + __IO uint32_t DCFG_CC_SOCU_DFLT; /**< With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access., offset: 0x24 */ + __IO uint32_t ENABLE_FA_MODE; /**< Enable FA mode. SET_FA_MODE Command should write 0xC33CA55A to this word to indicate boot ROM to enter FA mode., offset: 0x28 */ + __IO uint32_t CMPA_PROG_IN_PROGRESS; /**< CMPA Page programming on going. This field shall be set to 0x5CC55AA5 in the active CFPA page each time CMPA page programming is going on. It shall always be set to 0x00000000 in the CFPA scratch area., offset: 0x2C */ + union { /* offset: 0x30 */ + __IO uint32_t PRINCE_REGION0_IV_CODE[14]; /**< ., array offset: 0x30, array step: 0x4 */ + struct { /* offset: 0x30 */ + __IO uint32_t PRINCE_REGION0_IV_HEADER0; /**< ., offset: 0x30 */ + __IO uint32_t PRINCE_REGION0_IV_HEADER1; /**< ., offset: 0x34 */ + __IO uint32_t PRINCE_REGION0_IV_BODY[12]; /**< ., array offset: 0x38, array step: 0x4 */ + } PRINCE_REGION0_IV_CODE_CORE; + }; + union { /* offset: 0x68 */ + __IO uint32_t PRINCE_REGION1_IV_CODE[14]; /**< ., array offset: 0x68, array step: 0x4 */ + struct { /* offset: 0x68 */ + __IO uint32_t PRINCE_REGION1_IV_HEADER0; /**< ., offset: 0x68 */ + __IO uint32_t PRINCE_REGION1_IV_HEADER1; /**< ., offset: 0x6C */ + __IO uint32_t PRINCE_REGION1_IV_BODY[12]; /**< ., array offset: 0x70, array step: 0x4 */ + } PRINCE_REGION1_IV_CODE_CORE; + }; + union { /* offset: 0xA0 */ + __IO uint32_t PRINCE_REGION2_IV_CODE[14]; /**< ., array offset: 0xA0, array step: 0x4 */ + struct { /* offset: 0xA0 */ + __IO uint32_t PRINCE_REGION2_IV_HEADER0; /**< ., offset: 0xA0 */ + __IO uint32_t PRINCE_REGION2_IV_HEADER1; /**< ., offset: 0xA4 */ + __IO uint32_t PRINCE_REGION2_IV_BODY[12]; /**< ., array offset: 0xA8, array step: 0x4 */ + } PRINCE_REGION2_IV_CODE_CORE; + }; + uint8_t RESERVED_1[40]; + __IO uint32_t CUSTOMER_DEFINED[56]; /**< Customer Defined (Programable through ROM API), array offset: 0x100, array step: 0x4 */ + __IO uint32_t SHA256_DIGEST[8]; /**< SHA256_DIGEST0 for DIGEST[31:0] SHA256_DIGEST1 for DIGEST[63:32] SHA256_DIGEST2 for DIGEST[95:64] SHA256_DIGEST3 for DIGEST[127:96] SHA256_DIGEST4 for DIGEST[159:128] SHA256_DIGEST5 for DIGEST[191:160] SHA256_DIGEST6 for DIGEST[223:192] SHA256_DIGEST7 for DIGEST[255:224], array offset: 0x1E0, array step: 0x4 */ +} FLASH_CFPA_Type; + +/* ---------------------------------------------------------------------------- + -- FLASH_CFPA Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLASH_CFPA_Register_Masks FLASH_CFPA Register Masks + * @{ + */ + +/*! @name HEADER - . */ +/*! @{ */ +#define FLASH_CFPA_HEADER_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_HEADER_FIELD_SHIFT (0U) +#define FLASH_CFPA_HEADER_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_HEADER_FIELD_SHIFT)) & FLASH_CFPA_HEADER_FIELD_MASK) +/*! @} */ + +/*! @name VERSION - . */ +/*! @{ */ +#define FLASH_CFPA_VERSION_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_VERSION_FIELD_SHIFT (0U) +#define FLASH_CFPA_VERSION_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_VERSION_FIELD_SHIFT)) & FLASH_CFPA_VERSION_FIELD_MASK) +/*! @} */ + +/*! @name S_FW_VERSION - Secure firmware version (Monotonic counter) */ +/*! @{ */ +#define FLASH_CFPA_S_FW_VERSION_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_S_FW_VERSION_FIELD_SHIFT (0U) +#define FLASH_CFPA_S_FW_VERSION_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_S_FW_VERSION_FIELD_SHIFT)) & FLASH_CFPA_S_FW_VERSION_FIELD_MASK) +/*! @} */ + +/*! @name NS_FW_VERSION - Non-Secure firmware version (Monotonic counter) */ +/*! @{ */ +#define FLASH_CFPA_NS_FW_VERSION_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_NS_FW_VERSION_FIELD_SHIFT (0U) +#define FLASH_CFPA_NS_FW_VERSION_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_NS_FW_VERSION_FIELD_SHIFT)) & FLASH_CFPA_NS_FW_VERSION_FIELD_MASK) +/*! @} */ + +/*! @name IMAGE_KEY_REVOKE - Image key revocation ID (Monotonic counter) */ +/*! @{ */ +#define FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_SHIFT (0U) +#define FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_SHIFT)) & FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_MASK) +/*! @} */ + +/*! @name ROTKH_REVOKE - . */ +/*! @{ */ +#define FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_MASK (0x3U) +#define FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_SHIFT (0U) +#define FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_SHIFT)) & FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_MASK) +#define FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_MASK (0xCU) +#define FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_SHIFT (2U) +#define FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_SHIFT)) & FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_MASK) +#define FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_MASK (0x30U) +#define FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_SHIFT (4U) +#define FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_SHIFT)) & FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_MASK) +/*! @} */ + +/*! @name VENDOR_USAGE - . */ +/*! @{ */ +#define FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_MASK (0xFFFFU) +#define FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_SHIFT (0U) +#define FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_SHIFT)) & FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_MASK) +#define FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE_MASK (0xFFFF0000U) +#define FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE_SHIFT (16U) +#define FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE_SHIFT)) & FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE_MASK) +/*! @} */ + +/*! @name DCFG_CC_SOCU_PIN - With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access. */ +/*! @{ */ +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_MASK (0x1U) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_SHIFT (0U) +/*! NIDEN - Non Secure non-invasive debug enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_MASK) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_MASK (0x2U) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_SHIFT (1U) +/*! DBGEN - Non Secure debug enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_MASK) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN_MASK (0x4U) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN_SHIFT (2U) +/*! SPNIDEN - Secure non-invasive debug enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN_MASK) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_MASK (0x8U) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_SHIFT (3U) +/*! SPIDEN - Secure invasive debug enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_MASK) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_MASK (0x10U) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_SHIFT (4U) +/*! TAPEN - JTAG TAP enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_MASK) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_MCM33_DBGEN_MASK (0x20U) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_MCM33_DBGEN_SHIFT (5U) +/*! MCM33_DBGEN - Micro CM33 invasive debug enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_MCM33_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_MCM33_DBGEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_MCM33_DBGEN_MASK) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_MASK (0x40U) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_SHIFT (6U) +/*! ISP_CMD_EN - ISP Boot Command enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_MASK) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_MASK (0x80U) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_SHIFT (7U) +/*! FA_CMD_EN - FA Command enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_MASK) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_MASK (0x100U) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_SHIFT (8U) +/*! ME_CMD_EN - Flash Mass Erase Command enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_ME_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_MASK) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_MCM33_NIDEN_MASK (0x200U) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_MCM33_NIDEN_SHIFT (9U) +/*! MCM33_NIDEN - Micro CM33 non-invasive debug enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_MCM33_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_MCM33_NIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_MCM33_NIDEN_MASK) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK_MASK (0x8000U) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK_SHIFT (15U) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK_MASK) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_MASK (0xFFFF0000U) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_SHIFT (16U) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_MASK) +/*! @} */ + +/*! @name DCFG_CC_SOCU_DFLT - With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access. */ +/*! @{ */ +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_MASK (0x1U) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_SHIFT (0U) +/*! NIDEN - Non Secure non-invasive debug fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_MASK) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_MASK (0x2U) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_SHIFT (1U) +/*! DBGEN - Non Secure debug fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_MASK) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN_MASK (0x4U) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN_SHIFT (2U) +/*! SPNIDEN - Secure non-invasive debug fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN_MASK) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN_MASK (0x8U) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN_SHIFT (3U) +/*! SPIDEN - Secure invasive debug fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN_MASK) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_MASK (0x10U) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_SHIFT (4U) +/*! TAPEN - JTAG TAP fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_MASK) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_MCM33_DBGEN_MASK (0x20U) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_MCM33_DBGEN_SHIFT (5U) +/*! MCM33_DBGEN - Micro CM33 invasive debug fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_MCM33_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_MCM33_DBGEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_MCM33_DBGEN_MASK) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_MASK (0x40U) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT (6U) +/*! ISP_CMD_EN - ISP Boot Command fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_MASK) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_MASK (0x80U) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_SHIFT (7U) +/*! FA_CMD_EN - FA Command fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_MASK) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_MASK (0x100U) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_SHIFT (8U) +/*! ME_CMD_EN - Flash Mass Erase Command fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_MASK) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_MCM33_NIDEN_MASK (0x200U) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_MCM33_NIDEN_SHIFT (9U) +/*! MCM33_NIDEN - Micro CM33 non-invasive debug fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_MCM33_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_MCM33_NIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_MCM33_NIDEN_MASK) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_MASK (0xFFFF0000U) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT (16U) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_MASK) +/*! @} */ + +/*! @name ENABLE_FA_MODE - Enable FA mode. SET_FA_MODE Command should write 0xC33CA55A to this word to indicate boot ROM to enter FA mode. */ +/*! @{ */ +#define FLASH_CFPA_ENABLE_FA_MODE_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_ENABLE_FA_MODE_FIELD_SHIFT (0U) +#define FLASH_CFPA_ENABLE_FA_MODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ENABLE_FA_MODE_FIELD_SHIFT)) & FLASH_CFPA_ENABLE_FA_MODE_FIELD_MASK) +/*! @} */ + +/*! @name CMPA_PROG_IN_PROGRESS - CMPA Page programming on going. This field shall be set to 0x5CC55AA5 in the active CFPA page each time CMPA page programming is going on. It shall always be set to 0x00000000 in the CFPA scratch area. */ +/*! @{ */ +#define FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_SHIFT (0U) +#define FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_SHIFT)) & FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_MASK) +/*! @} */ + +/*! @name PRINCE_REGION0_IV_CODE - . */ +/*! @{ */ +#define FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_SHIFT (0U) +#define FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_CFPA_PRINCE_REGION0_IV_CODE */ +#define FLASH_CFPA_PRINCE_REGION0_IV_CODE_COUNT (14U) + +/*! @name PRINCE_REGION0_IV_HEADER0 - . */ +/*! @{ */ +#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_SHIFT (0U) +#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_MASK) +/*! @} */ + +/*! @name PRINCE_REGION0_IV_HEADER1 - . */ +/*! @{ */ +#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_MASK (0x3U) +#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_SHIFT (0U) +#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_MASK) +#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_MASK (0xF00U) +#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_SHIFT (8U) +#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_MASK) +#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_MASK (0x3F000000U) +#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_SHIFT (24U) +#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_MASK) +/*! @} */ + +/*! @name PRINCE_REGION0_IV_BODY - . */ +/*! @{ */ +#define FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_SHIFT (0U) +#define FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_CFPA_PRINCE_REGION0_IV_BODY */ +#define FLASH_CFPA_PRINCE_REGION0_IV_BODY_COUNT (12U) + +/*! @name PRINCE_REGION1_IV_CODE - . */ +/*! @{ */ +#define FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_SHIFT (0U) +#define FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_CFPA_PRINCE_REGION1_IV_CODE */ +#define FLASH_CFPA_PRINCE_REGION1_IV_CODE_COUNT (14U) + +/*! @name PRINCE_REGION1_IV_HEADER0 - . */ +/*! @{ */ +#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_SHIFT (0U) +#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_MASK) +/*! @} */ + +/*! @name PRINCE_REGION1_IV_HEADER1 - . */ +/*! @{ */ +#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_MASK (0x3U) +#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_SHIFT (0U) +#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_MASK) +#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_MASK (0xF00U) +#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_SHIFT (8U) +#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_MASK) +#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_MASK (0x3F000000U) +#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_SHIFT (24U) +#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_MASK) +/*! @} */ + +/*! @name PRINCE_REGION1_IV_BODY - . */ +/*! @{ */ +#define FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_SHIFT (0U) +#define FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_CFPA_PRINCE_REGION1_IV_BODY */ +#define FLASH_CFPA_PRINCE_REGION1_IV_BODY_COUNT (12U) + +/*! @name PRINCE_REGION2_IV_CODE - . */ +/*! @{ */ +#define FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_SHIFT (0U) +#define FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_CFPA_PRINCE_REGION2_IV_CODE */ +#define FLASH_CFPA_PRINCE_REGION2_IV_CODE_COUNT (14U) + +/*! @name PRINCE_REGION2_IV_HEADER0 - . */ +/*! @{ */ +#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_SHIFT (0U) +#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_MASK) +/*! @} */ + +/*! @name PRINCE_REGION2_IV_HEADER1 - . */ +/*! @{ */ +#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_MASK (0x3U) +#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_SHIFT (0U) +#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_MASK) +#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_MASK (0xF00U) +#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_SHIFT (8U) +#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_MASK) +#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_MASK (0x3F000000U) +#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_SHIFT (24U) +#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_MASK) +/*! @} */ + +/*! @name PRINCE_REGION2_IV_BODY - . */ +/*! @{ */ +#define FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_SHIFT (0U) +#define FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_CFPA_PRINCE_REGION2_IV_BODY */ +#define FLASH_CFPA_PRINCE_REGION2_IV_BODY_COUNT (12U) + +/*! @name CUSTOMER_DEFINED - Customer Defined (Programable through ROM API) */ +/*! @{ */ +#define FLASH_CFPA_CUSTOMER_DEFINED_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_CUSTOMER_DEFINED_FIELD_SHIFT (0U) +#define FLASH_CFPA_CUSTOMER_DEFINED_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_CUSTOMER_DEFINED_FIELD_SHIFT)) & FLASH_CFPA_CUSTOMER_DEFINED_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_CFPA_CUSTOMER_DEFINED */ +#define FLASH_CFPA_CUSTOMER_DEFINED_COUNT (56U) + +/*! @name SHA256_DIGEST - SHA256_DIGEST0 for DIGEST[31:0] SHA256_DIGEST1 for DIGEST[63:32] SHA256_DIGEST2 for DIGEST[95:64] SHA256_DIGEST3 for DIGEST[127:96] SHA256_DIGEST4 for DIGEST[159:128] SHA256_DIGEST5 for DIGEST[191:160] SHA256_DIGEST6 for DIGEST[223:192] SHA256_DIGEST7 for DIGEST[255:224] */ +/*! @{ */ +#define FLASH_CFPA_SHA256_DIGEST_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_SHA256_DIGEST_FIELD_SHIFT (0U) +#define FLASH_CFPA_SHA256_DIGEST_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_SHA256_DIGEST_FIELD_SHIFT)) & FLASH_CFPA_SHA256_DIGEST_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_CFPA_SHA256_DIGEST */ +#define FLASH_CFPA_SHA256_DIGEST_COUNT (8U) + + +/*! + * @} + */ /* end of group FLASH_CFPA_Register_Masks */ + + +/* FLASH_CFPA - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral FLASH_CFPA0 base address */ + #define FLASH_CFPA0_BASE (0x1009E000u) + /** Peripheral FLASH_CFPA0 base address */ + #define FLASH_CFPA0_BASE_NS (0x9E000u) + /** Peripheral FLASH_CFPA0 base pointer */ + #define FLASH_CFPA0 ((FLASH_CFPA_Type *)FLASH_CFPA0_BASE) + /** Peripheral FLASH_CFPA0 base pointer */ + #define FLASH_CFPA0_NS ((FLASH_CFPA_Type *)FLASH_CFPA0_BASE_NS) + /** Peripheral FLASH_CFPA1 base address */ + #define FLASH_CFPA1_BASE (0x1009E200u) + /** Peripheral FLASH_CFPA1 base address */ + #define FLASH_CFPA1_BASE_NS (0x9E200u) + /** Peripheral FLASH_CFPA1 base pointer */ + #define FLASH_CFPA1 ((FLASH_CFPA_Type *)FLASH_CFPA1_BASE) + /** Peripheral FLASH_CFPA1 base pointer */ + #define FLASH_CFPA1_NS ((FLASH_CFPA_Type *)FLASH_CFPA1_BASE_NS) + /** Peripheral FLASH_CFPA_SCRATCH base address */ + #define FLASH_CFPA_SCRATCH_BASE (0x1009DE00u) + /** Peripheral FLASH_CFPA_SCRATCH base address */ + #define FLASH_CFPA_SCRATCH_BASE_NS (0x9DE00u) + /** Peripheral FLASH_CFPA_SCRATCH base pointer */ + #define FLASH_CFPA_SCRATCH ((FLASH_CFPA_Type *)FLASH_CFPA_SCRATCH_BASE) + /** Peripheral FLASH_CFPA_SCRATCH base pointer */ + #define FLASH_CFPA_SCRATCH_NS ((FLASH_CFPA_Type *)FLASH_CFPA_SCRATCH_BASE_NS) + /** Array initializer of FLASH_CFPA peripheral base addresses */ + #define FLASH_CFPA_BASE_ADDRS { FLASH_CFPA0_BASE, FLASH_CFPA1_BASE, FLASH_CFPA_SCRATCH_BASE } + /** Array initializer of FLASH_CFPA peripheral base pointers */ + #define FLASH_CFPA_BASE_PTRS { FLASH_CFPA0, FLASH_CFPA1, FLASH_CFPA_SCRATCH } + /** Array initializer of FLASH_CFPA peripheral base addresses */ + #define FLASH_CFPA_BASE_ADDRS_NS { FLASH_CFPA0_BASE_NS, FLASH_CFPA1_BASE_NS, FLASH_CFPA_SCRATCH_BASE_NS } + /** Array initializer of FLASH_CFPA peripheral base pointers */ + #define FLASH_CFPA_BASE_PTRS_NS { FLASH_CFPA0_NS, FLASH_CFPA1_NS, FLASH_CFPA_SCRATCH_NS } +#else + /** Peripheral FLASH_CFPA0 base address */ + #define FLASH_CFPA0_BASE (0x9E000u) + /** Peripheral FLASH_CFPA0 base pointer */ + #define FLASH_CFPA0 ((FLASH_CFPA_Type *)FLASH_CFPA0_BASE) + /** Peripheral FLASH_CFPA1 base address */ + #define FLASH_CFPA1_BASE (0x9E200u) + /** Peripheral FLASH_CFPA1 base pointer */ + #define FLASH_CFPA1 ((FLASH_CFPA_Type *)FLASH_CFPA1_BASE) + /** Peripheral FLASH_CFPA_SCRATCH base address */ + #define FLASH_CFPA_SCRATCH_BASE (0x9DE00u) + /** Peripheral FLASH_CFPA_SCRATCH base pointer */ + #define FLASH_CFPA_SCRATCH ((FLASH_CFPA_Type *)FLASH_CFPA_SCRATCH_BASE) + /** Array initializer of FLASH_CFPA peripheral base addresses */ + #define FLASH_CFPA_BASE_ADDRS { FLASH_CFPA0_BASE, FLASH_CFPA1_BASE, FLASH_CFPA_SCRATCH_BASE } + /** Array initializer of FLASH_CFPA peripheral base pointers */ + #define FLASH_CFPA_BASE_PTRS { FLASH_CFPA0, FLASH_CFPA1, FLASH_CFPA_SCRATCH } +#endif + +/*! + * @} + */ /* end of group FLASH_CFPA_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FLASH_CMPA Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLASH_CMPA_Peripheral_Access_Layer FLASH_CMPA Peripheral Access Layer + * @{ + */ + +/** FLASH_CMPA - Register Layout Typedef */ +typedef struct { + __IO uint32_t BOOT_CFG; /**< ., offset: 0x0 */ + __IO uint32_t SPI_FLASH_CFG; /**< ., offset: 0x4 */ + __IO uint32_t USB_ID; /**< ., offset: 0x8 */ + __IO uint32_t SDIO_CFG; /**< ., offset: 0xC */ + __IO uint32_t DCFG_CC_SOCU_PIN; /**< ., offset: 0x10 */ + __IO uint32_t DCFG_CC_SOCU_DFLT; /**< ., offset: 0x14 */ + __IO uint32_t DAP_VENDOR_USAGE_FIXED; /**< ., offset: 0x18 */ + __IO uint32_t SECURE_BOOT_CFG; /**< ., offset: 0x1C */ + __IO uint32_t PRINCE_BASE_ADDR; /**< ., offset: 0x20 */ + __IO uint32_t PRINCE_SR_0; /**< Region 0, sub-region enable, offset: 0x24 */ + __IO uint32_t PRINCE_SR_1; /**< Region 1, sub-region enable, offset: 0x28 */ + __IO uint32_t PRINCE_SR_2; /**< Region 2, sub-region enable, offset: 0x2C */ + uint8_t RESERVED_0[32]; + __IO uint32_t ROTKH[8]; /**< ROTKH0 for Root of Trust Keys Table hash[255:224] ROTKH1 for Root of Trust Keys Table hash[223:192] ROTKH2 for Root of Trust Keys Table hash[191:160] ROTKH3 for Root of Trust Keys Table hash[159:128] ROTKH4 for Root of Trust Keys Table hash[127:96] ROTKH5 for Root of Trust Keys Table hash[95:64] ROTKH6 for Root of Trust Keys Table hash[63:32] ROTKH7 for Root of Trust Keys Table hash[31:0], array offset: 0x50, array step: 0x4 */ + uint8_t RESERVED_1[144]; + __IO uint32_t CUSTOMER_DEFINED[56]; /**< Customer Defined (Programable through ROM API), array offset: 0x100, array step: 0x4 */ + __IO uint32_t SHA256_DIGEST[8]; /**< SHA256_DIGEST0 for DIGEST[31:0] SHA256_DIGEST1 for DIGEST[63:32] SHA256_DIGEST2 for DIGEST[95:64] SHA256_DIGEST3 for DIGEST[127:96] SHA256_DIGEST4 for DIGEST[159:128] SHA256_DIGEST5 for DIGEST[191:160] SHA256_DIGEST6 for DIGEST[223:192] SHA256_DIGEST7 for DIGEST[255:224], array offset: 0x1E0, array step: 0x4 */ +} FLASH_CMPA_Type; + +/* ---------------------------------------------------------------------------- + -- FLASH_CMPA Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLASH_CMPA_Register_Masks FLASH_CMPA Register Masks + * @{ + */ + +/*! @name BOOT_CFG - . */ +/*! @{ */ +#define FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_MASK (0x70U) +#define FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_SHIFT (4U) +/*! DEFAULT_ISP_MODE - Default ISP mode: + * 0b000..Auto ISP + * 0b001..USB_HID_MSC + * 0b010..SPI Slave ISP + * 0b011..I2C Slave ISP + * 0b111..Disable ISP fall through + */ +#define FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_SHIFT)) & FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_MASK) +#define FLASH_CMPA_BOOT_CFG_BOOT_SPEED_MASK (0x180U) +#define FLASH_CMPA_BOOT_CFG_BOOT_SPEED_SHIFT (7U) +/*! BOOT_SPEED - Core clock: + * 0b00..Defined by NMPA.SYSTEM_SPEED_CODE + * 0b01..48MHz FRO + * 0b10..96MHz FRO + */ +#define FLASH_CMPA_BOOT_CFG_BOOT_SPEED(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_BOOT_CFG_BOOT_SPEED_SHIFT)) & FLASH_CMPA_BOOT_CFG_BOOT_SPEED_MASK) +#define FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_MASK (0xFF000000U) +#define FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_SHIFT (24U) +#define FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_SHIFT)) & FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_MASK) +/*! @} */ + +/*! @name SPI_FLASH_CFG - . */ +/*! @{ */ +#define FLASH_CMPA_SPI_FLASH_CFG_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CMPA_SPI_FLASH_CFG_FIELD_SHIFT (0U) +#define FLASH_CMPA_SPI_FLASH_CFG_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SPI_FLASH_CFG_FIELD_SHIFT)) & FLASH_CMPA_SPI_FLASH_CFG_FIELD_MASK) +/*! @} */ + +/*! @name USB_ID - . */ +/*! @{ */ +#define FLASH_CMPA_USB_ID_USB_VENDOR_ID_MASK (0xFFFFU) +#define FLASH_CMPA_USB_ID_USB_VENDOR_ID_SHIFT (0U) +#define FLASH_CMPA_USB_ID_USB_VENDOR_ID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_USB_ID_USB_VENDOR_ID_SHIFT)) & FLASH_CMPA_USB_ID_USB_VENDOR_ID_MASK) +#define FLASH_CMPA_USB_ID_USB_PRODUCT_ID_MASK (0xFFFF0000U) +#define FLASH_CMPA_USB_ID_USB_PRODUCT_ID_SHIFT (16U) +#define FLASH_CMPA_USB_ID_USB_PRODUCT_ID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_USB_ID_USB_PRODUCT_ID_SHIFT)) & FLASH_CMPA_USB_ID_USB_PRODUCT_ID_MASK) +/*! @} */ + +/*! @name SDIO_CFG - . */ +/*! @{ */ +#define FLASH_CMPA_SDIO_CFG_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CMPA_SDIO_CFG_FIELD_SHIFT (0U) +#define FLASH_CMPA_SDIO_CFG_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SDIO_CFG_FIELD_SHIFT)) & FLASH_CMPA_SDIO_CFG_FIELD_MASK) +/*! @} */ + +/*! @name DCFG_CC_SOCU_PIN - . */ +/*! @{ */ +#define FLASH_CMPA_DCFG_CC_SOCU_PIN_NIDEN_MASK (0x1U) +#define FLASH_CMPA_DCFG_CC_SOCU_PIN_NIDEN_SHIFT (0U) +/*! NIDEN - Non Secure non-invasive debug enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CMPA_DCFG_CC_SOCU_PIN_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_PIN_NIDEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_PIN_NIDEN_MASK) +#define FLASH_CMPA_DCFG_CC_SOCU_PIN_DBGEN_MASK (0x2U) +#define FLASH_CMPA_DCFG_CC_SOCU_PIN_DBGEN_SHIFT (1U) +/*! DBGEN - Non Secure debug enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CMPA_DCFG_CC_SOCU_PIN_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_PIN_DBGEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_PIN_DBGEN_MASK) +#define FLASH_CMPA_DCFG_CC_SOCU_PIN_SPNIDEN_MASK (0x4U) +#define FLASH_CMPA_DCFG_CC_SOCU_PIN_SPNIDEN_SHIFT (2U) +/*! SPNIDEN - Secure non-invasive debug enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CMPA_DCFG_CC_SOCU_PIN_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_PIN_SPNIDEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_PIN_SPNIDEN_MASK) +#define FLASH_CMPA_DCFG_CC_SOCU_PIN_SPIDEN_MASK (0x8U) +#define FLASH_CMPA_DCFG_CC_SOCU_PIN_SPIDEN_SHIFT (3U) +/*! SPIDEN - Secure invasive debug enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CMPA_DCFG_CC_SOCU_PIN_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_PIN_SPIDEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_PIN_SPIDEN_MASK) +#define FLASH_CMPA_DCFG_CC_SOCU_PIN_TAPEN_MASK (0x10U) +#define FLASH_CMPA_DCFG_CC_SOCU_PIN_TAPEN_SHIFT (4U) +/*! TAPEN - JTAG TAP enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CMPA_DCFG_CC_SOCU_PIN_TAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_PIN_TAPEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_PIN_TAPEN_MASK) +#define FLASH_CMPA_DCFG_CC_SOCU_PIN_MCM33_DBGEN_MASK (0x20U) +#define FLASH_CMPA_DCFG_CC_SOCU_PIN_MCM33_DBGEN_SHIFT (5U) +/*! MCM33_DBGEN - Micro CM33 invasive debug enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CMPA_DCFG_CC_SOCU_PIN_MCM33_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_PIN_MCM33_DBGEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_PIN_MCM33_DBGEN_MASK) +#define FLASH_CMPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_MASK (0x40U) +#define FLASH_CMPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_SHIFT (6U) +/*! ISP_CMD_EN - ISP Boot Command enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CMPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_MASK) +#define FLASH_CMPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_MASK (0x80U) +#define FLASH_CMPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_SHIFT (7U) +/*! FA_CMD_EN - FA Command enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CMPA_DCFG_CC_SOCU_PIN_FA_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_MASK) +#define FLASH_CMPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_MASK (0x100U) +#define FLASH_CMPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_SHIFT (8U) +/*! ME_CMD_EN - Flash Mass Erase Command enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CMPA_DCFG_CC_SOCU_PIN_ME_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_MASK) +#define FLASH_CMPA_DCFG_CC_SOCU_PIN_MCM33_NIDEN_MASK (0x200U) +#define FLASH_CMPA_DCFG_CC_SOCU_PIN_MCM33_NIDEN_SHIFT (9U) +/*! MCM33_NIDEN - Micro CM33 non-invasive debug enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CMPA_DCFG_CC_SOCU_PIN_MCM33_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_PIN_MCM33_NIDEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_PIN_MCM33_NIDEN_MASK) +#define FLASH_CMPA_DCFG_CC_SOCU_PIN_UUID_CHECK_MASK (0x8000U) +#define FLASH_CMPA_DCFG_CC_SOCU_PIN_UUID_CHECK_SHIFT (15U) +#define FLASH_CMPA_DCFG_CC_SOCU_PIN_UUID_CHECK(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_PIN_UUID_CHECK_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_PIN_UUID_CHECK_MASK) +#define FLASH_CMPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_MASK (0xFFFF0000U) +#define FLASH_CMPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_SHIFT (16U) +#define FLASH_CMPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_MASK) +/*! @} */ + +/*! @name DCFG_CC_SOCU_DFLT - . */ +/*! @{ */ +#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_NIDEN_MASK (0x1U) +#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_NIDEN_SHIFT (0U) +/*! NIDEN - Non Secure non-invasive debug fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_DFLT_NIDEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_DFLT_NIDEN_MASK) +#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_DBGEN_MASK (0x2U) +#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_DBGEN_SHIFT (1U) +/*! DBGEN - Non Secure debug fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_DFLT_DBGEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_DFLT_DBGEN_MASK) +#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_SPNIDEN_MASK (0x4U) +#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_SPNIDEN_SHIFT (2U) +/*! SPNIDEN - Secure non-invasive debug fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_DFLT_SPNIDEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_DFLT_SPNIDEN_MASK) +#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_SPIDEN_MASK (0x8U) +#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_SPIDEN_SHIFT (3U) +/*! SPIDEN - Secure invasive debug fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_DFLT_SPIDEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_DFLT_SPIDEN_MASK) +#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_TAPEN_MASK (0x10U) +#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_TAPEN_SHIFT (4U) +/*! TAPEN - JTAG TAP fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_TAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_DFLT_TAPEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_DFLT_TAPEN_MASK) +#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_MCM33_DBGEN_MASK (0x20U) +#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_MCM33_DBGEN_SHIFT (5U) +/*! MCM33_DBGEN - Micro CM33 invasive debug fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_MCM33_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_DFLT_MCM33_DBGEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_DFLT_MCM33_DBGEN_MASK) +#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_MASK (0x40U) +#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT (6U) +/*! ISP_CMD_EN - ISP Boot Command fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_MASK) +#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_MASK (0x80U) +#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_SHIFT (7U) +/*! FA_CMD_EN - FA Command fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_MASK) +#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_MASK (0x100U) +#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_SHIFT (8U) +/*! ME_CMD_EN - Flash Mass Erase Command fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_MASK) +#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_MCM33_NIDEN_MASK (0x200U) +#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_MCM33_NIDEN_SHIFT (9U) +/*! MCM33_NIDEN - Micro CM33 non-invasive debug fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_MCM33_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_DFLT_MCM33_NIDEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_DFLT_MCM33_NIDEN_MASK) +#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_MASK (0xFFFF0000U) +#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT (16U) +#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_MASK) +/*! @} */ + +/*! @name DAP_VENDOR_USAGE_FIXED - . */ +/*! @{ */ +#define FLASH_CMPA_DAP_VENDOR_USAGE_FIXED_VENDOR_USAGE_MASK (0xFFFF0000U) +#define FLASH_CMPA_DAP_VENDOR_USAGE_FIXED_VENDOR_USAGE_SHIFT (16U) +#define FLASH_CMPA_DAP_VENDOR_USAGE_FIXED_VENDOR_USAGE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DAP_VENDOR_USAGE_FIXED_VENDOR_USAGE_SHIFT)) & FLASH_CMPA_DAP_VENDOR_USAGE_FIXED_VENDOR_USAGE_MASK) +/*! @} */ + +/*! @name SECURE_BOOT_CFG - . */ +/*! @{ */ +#define FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_MASK (0x3U) +#define FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_SHIFT (0U) +#define FLASH_CMPA_SECURE_BOOT_CFG_RSA4K(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_MASK) +#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_ENC_NXP_CFG_MASK (0xCU) +#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_ENC_NXP_CFG_SHIFT (2U) +#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_ENC_NXP_CFG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_DICE_ENC_NXP_CFG_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_DICE_ENC_NXP_CFG_MASK) +#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_MASK (0x30U) +#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_SHIFT (4U) +#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_MASK) +#define FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_MASK (0xC0U) +#define FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_SHIFT (6U) +#define FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_MASK) +#define FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_MASK (0x300U) +#define FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_SHIFT (8U) +#define FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_MASK) +#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_MASK (0xC00U) +#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_SHIFT (10U) +#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_MASK) +#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_MASK (0x3000U) +#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_SHIFT (12U) +#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_MASK) +#define FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_MASK (0xC0000000U) +#define FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_SHIFT (30U) +#define FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_MASK) +/*! @} */ + +/*! @name PRINCE_BASE_ADDR - . */ +/*! @{ */ +#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_MASK (0xFU) +#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_SHIFT (0U) +#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_MASK) +#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_MASK (0xF0U) +#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_SHIFT (4U) +#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_MASK) +#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_MASK (0xF00U) +#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_SHIFT (8U) +#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_MASK) +#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_MASK (0x30000U) +#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_SHIFT (16U) +#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_MASK) +#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_MASK (0xC0000U) +#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_SHIFT (18U) +#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_MASK) +#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG2_MASK (0x300000U) +#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG2_SHIFT (20U) +#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG2(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG2_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG2_MASK) +#define FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_MASK (0x3000000U) +#define FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_SHIFT (24U) +#define FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_MASK) +#define FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_MASK (0xC000000U) +#define FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_SHIFT (26U) +#define FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_MASK) +#define FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_MASK (0x30000000U) +#define FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_SHIFT (28U) +#define FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_MASK) +/*! @} */ + +/*! @name PRINCE_SR_0 - Region 0, sub-region enable */ +/*! @{ */ +#define FLASH_CMPA_PRINCE_SR_0_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CMPA_PRINCE_SR_0_FIELD_SHIFT (0U) +#define FLASH_CMPA_PRINCE_SR_0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_SR_0_FIELD_SHIFT)) & FLASH_CMPA_PRINCE_SR_0_FIELD_MASK) +/*! @} */ + +/*! @name PRINCE_SR_1 - Region 1, sub-region enable */ +/*! @{ */ +#define FLASH_CMPA_PRINCE_SR_1_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CMPA_PRINCE_SR_1_FIELD_SHIFT (0U) +#define FLASH_CMPA_PRINCE_SR_1_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_SR_1_FIELD_SHIFT)) & FLASH_CMPA_PRINCE_SR_1_FIELD_MASK) +/*! @} */ + +/*! @name PRINCE_SR_2 - Region 2, sub-region enable */ +/*! @{ */ +#define FLASH_CMPA_PRINCE_SR_2_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CMPA_PRINCE_SR_2_FIELD_SHIFT (0U) +#define FLASH_CMPA_PRINCE_SR_2_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_SR_2_FIELD_SHIFT)) & FLASH_CMPA_PRINCE_SR_2_FIELD_MASK) +/*! @} */ + +/*! @name ROTKH - ROTKH0 for Root of Trust Keys Table hash[255:224] ROTKH1 for Root of Trust Keys Table hash[223:192] ROTKH2 for Root of Trust Keys Table hash[191:160] ROTKH3 for Root of Trust Keys Table hash[159:128] ROTKH4 for Root of Trust Keys Table hash[127:96] ROTKH5 for Root of Trust Keys Table hash[95:64] ROTKH6 for Root of Trust Keys Table hash[63:32] ROTKH7 for Root of Trust Keys Table hash[31:0] */ +/*! @{ */ +#define FLASH_CMPA_ROTKH_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CMPA_ROTKH_FIELD_SHIFT (0U) +#define FLASH_CMPA_ROTKH_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_ROTKH_FIELD_SHIFT)) & FLASH_CMPA_ROTKH_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_CMPA_ROTKH */ +#define FLASH_CMPA_ROTKH_COUNT (8U) + +/*! @name CUSTOMER_DEFINED - Customer Defined (Programable through ROM API) */ +/*! @{ */ +#define FLASH_CMPA_CUSTOMER_DEFINED_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CMPA_CUSTOMER_DEFINED_FIELD_SHIFT (0U) +#define FLASH_CMPA_CUSTOMER_DEFINED_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CUSTOMER_DEFINED_FIELD_SHIFT)) & FLASH_CMPA_CUSTOMER_DEFINED_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_CMPA_CUSTOMER_DEFINED */ +#define FLASH_CMPA_CUSTOMER_DEFINED_COUNT (56U) + +/*! @name SHA256_DIGEST - SHA256_DIGEST0 for DIGEST[31:0] SHA256_DIGEST1 for DIGEST[63:32] SHA256_DIGEST2 for DIGEST[95:64] SHA256_DIGEST3 for DIGEST[127:96] SHA256_DIGEST4 for DIGEST[159:128] SHA256_DIGEST5 for DIGEST[191:160] SHA256_DIGEST6 for DIGEST[223:192] SHA256_DIGEST7 for DIGEST[255:224] */ +/*! @{ */ +#define FLASH_CMPA_SHA256_DIGEST_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CMPA_SHA256_DIGEST_FIELD_SHIFT (0U) +#define FLASH_CMPA_SHA256_DIGEST_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SHA256_DIGEST_FIELD_SHIFT)) & FLASH_CMPA_SHA256_DIGEST_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_CMPA_SHA256_DIGEST */ +#define FLASH_CMPA_SHA256_DIGEST_COUNT (8U) + + +/*! + * @} + */ /* end of group FLASH_CMPA_Register_Masks */ + + +/* FLASH_CMPA - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral FLASH_CMPA base address */ + #define FLASH_CMPA_BASE (0x1009E400u) + /** Peripheral FLASH_CMPA base address */ + #define FLASH_CMPA_BASE_NS (0x9E400u) + /** Peripheral FLASH_CMPA base pointer */ + #define FLASH_CMPA ((FLASH_CMPA_Type *)FLASH_CMPA_BASE) + /** Peripheral FLASH_CMPA base pointer */ + #define FLASH_CMPA_NS ((FLASH_CMPA_Type *)FLASH_CMPA_BASE_NS) + /** Array initializer of FLASH_CMPA peripheral base addresses */ + #define FLASH_CMPA_BASE_ADDRS { FLASH_CMPA_BASE } + /** Array initializer of FLASH_CMPA peripheral base pointers */ + #define FLASH_CMPA_BASE_PTRS { FLASH_CMPA } + /** Array initializer of FLASH_CMPA peripheral base addresses */ + #define FLASH_CMPA_BASE_ADDRS_NS { FLASH_CMPA_BASE_NS } + /** Array initializer of FLASH_CMPA peripheral base pointers */ + #define FLASH_CMPA_BASE_PTRS_NS { FLASH_CMPA_NS } +#else + /** Peripheral FLASH_CMPA base address */ + #define FLASH_CMPA_BASE (0x9E400u) + /** Peripheral FLASH_CMPA base pointer */ + #define FLASH_CMPA ((FLASH_CMPA_Type *)FLASH_CMPA_BASE) + /** Array initializer of FLASH_CMPA peripheral base addresses */ + #define FLASH_CMPA_BASE_ADDRS { FLASH_CMPA_BASE } + /** Array initializer of FLASH_CMPA peripheral base pointers */ + #define FLASH_CMPA_BASE_PTRS { FLASH_CMPA } +#endif + +/*! + * @} + */ /* end of group FLASH_CMPA_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FLASH_KEY_STORE Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLASH_KEY_STORE_Peripheral_Access_Layer FLASH_KEY_STORE Peripheral Access Layer + * @{ + */ + +/** FLASH_KEY_STORE - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0 */ + __IO uint32_t HEADER; /**< Valid Key Sore Header : 0x95959595, offset: 0x0 */ + __IO uint32_t PUF_DISCHARGE_TIME_IN_MS; /**< puf discharge time in ms., offset: 0x4 */ + } KEY_STORE_HEADER; + __IO uint32_t ACTIVATION_CODE[298]; /**< ., array offset: 0x8, array step: 0x4 */ + union { /* offset: 0x4B0 */ + __IO uint32_t SBKEY_KEY_CODE[14]; /**< ., array offset: 0x4B0, array step: 0x4 */ + struct { /* offset: 0x4B0 */ + __IO uint32_t SBKEY_HEADER0; /**< ., offset: 0x4B0 */ + __IO uint32_t SBKEY_HEADER1; /**< ., offset: 0x4B4 */ + __IO uint32_t SBKEY_BODY[12]; /**< ., array offset: 0x4B8, array step: 0x4 */ + } SBKEY_KEY_CODE_CORE; + }; + union { /* offset: 0x4E8 */ + __IO uint32_t USER_KEK_KEY_CODE[14]; /**< ., array offset: 0x4E8, array step: 0x4 */ + struct { /* offset: 0x4E8 */ + __IO uint32_t USER_KEK_HEADER0; /**< ., offset: 0x4E8 */ + __IO uint32_t USER_KEK_HEADER1; /**< ., offset: 0x4EC */ + __IO uint32_t USER_KEK_BODY[12]; /**< ., array offset: 0x4F0, array step: 0x4 */ + } USER_KEK_KEY_CODE_CORE; + }; + union { /* offset: 0x520 */ + __IO uint32_t UDS_KEY_CODE[14]; /**< ., array offset: 0x520, array step: 0x4 */ + struct { /* offset: 0x520 */ + __IO uint32_t UDS_HEADER0; /**< ., offset: 0x520 */ + __IO uint32_t UDS_HEADER1; /**< ., offset: 0x524 */ + __IO uint32_t UDS_BODY[12]; /**< ., array offset: 0x528, array step: 0x4 */ + } UDS_KEY_CODE_CORE; + }; + union { /* offset: 0x558 */ + __IO uint32_t PRINCE_REGION0_KEY_CODE[14]; /**< ., array offset: 0x558, array step: 0x4 */ + struct { /* offset: 0x558 */ + __IO uint32_t PRINCE_REGION0_HEADER0; /**< ., offset: 0x558 */ + __IO uint32_t PRINCE_REGION0_HEADER1; /**< ., offset: 0x55C */ + __IO uint32_t PRINCE_REGION0_BODY[12]; /**< ., array offset: 0x560, array step: 0x4 */ + } PRINCE_REGION0_KEY_CODE_CORE; + }; + union { /* offset: 0x590 */ + __IO uint32_t PRINCE_REGION1_KEY_CODE[14]; /**< ., array offset: 0x590, array step: 0x4 */ + struct { /* offset: 0x590 */ + __IO uint32_t PRINCE_REGION1_HEADER0; /**< ., offset: 0x590 */ + __IO uint32_t PRINCE_REGION1_HEADER1; /**< ., offset: 0x594 */ + __IO uint32_t PRINCE_REGION1_BODY[12]; /**< ., array offset: 0x598, array step: 0x4 */ + } PRINCE_REGION1_KEY_CODE_CORE; + }; + union { /* offset: 0x5C8 */ + __IO uint32_t PRINCE_REGION2_KEY_CODE[14]; /**< ., array offset: 0x5C8, array step: 0x4 */ + struct { /* offset: 0x5C8 */ + __IO uint32_t PRINCE_REGION2_HEADER0; /**< ., offset: 0x5C8 */ + __IO uint32_t PRINCE_REGION2_HEADER1; /**< ., offset: 0x5CC */ + __IO uint32_t PRINCE_REGION2_BODY[12]; /**< ., array offset: 0x5D0, array step: 0x4 */ + } PRINCE_REGION2_KEY_CODE_CORE; + }; +} FLASH_KEY_STORE_Type; + +/* ---------------------------------------------------------------------------- + -- FLASH_KEY_STORE Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLASH_KEY_STORE_Register_Masks FLASH_KEY_STORE Register Masks + * @{ + */ + +/*! @name HEADER - Valid Key Sore Header : 0x95959595 */ +/*! @{ */ +#define FLASH_KEY_STORE_HEADER_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_HEADER_FIELD_SHIFT (0U) +#define FLASH_KEY_STORE_HEADER_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_HEADER_FIELD_SHIFT)) & FLASH_KEY_STORE_HEADER_FIELD_MASK) +/*! @} */ + +/*! @name PUF_DISCHARGE_TIME_IN_MS - puf discharge time in ms. */ +/*! @{ */ +#define FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD_SHIFT (0U) +#define FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD_SHIFT)) & FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD_MASK) +/*! @} */ + +/*! @name ACTIVATION_CODE - . */ +/*! @{ */ +#define FLASH_KEY_STORE_ACTIVATION_CODE_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_ACTIVATION_CODE_FIELD_SHIFT (0U) +#define FLASH_KEY_STORE_ACTIVATION_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_ACTIVATION_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_ACTIVATION_CODE_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_KEY_STORE_ACTIVATION_CODE */ +#define FLASH_KEY_STORE_ACTIVATION_CODE_COUNT (298U) + +/*! @name SBKEY_KEY_CODE - . */ +/*! @{ */ +#define FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD_SHIFT (0U) +#define FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_KEY_STORE_SBKEY_KEY_CODE */ +#define FLASH_KEY_STORE_SBKEY_KEY_CODE_COUNT (14U) + +/*! @name SBKEY_HEADER0 - . */ +/*! @{ */ +#define FLASH_KEY_STORE_SBKEY_HEADER0_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_SBKEY_HEADER0_FIELD_SHIFT (0U) +#define FLASH_KEY_STORE_SBKEY_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_SBKEY_HEADER0_FIELD_MASK) +/*! @} */ + +/*! @name SBKEY_HEADER1 - . */ +/*! @{ */ +#define FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_MASK (0x3U) +#define FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_SHIFT (0U) +#define FLASH_KEY_STORE_SBKEY_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_MASK) +#define FLASH_KEY_STORE_SBKEY_HEADER1_INDEX_MASK (0xF00U) +#define FLASH_KEY_STORE_SBKEY_HEADER1_INDEX_SHIFT (8U) +#define FLASH_KEY_STORE_SBKEY_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_SBKEY_HEADER1_INDEX_MASK) +#define FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_MASK (0x3F000000U) +#define FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_SHIFT (24U) +#define FLASH_KEY_STORE_SBKEY_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_MASK) +/*! @} */ + +/*! @name SBKEY_BODY - . */ +/*! @{ */ +#define FLASH_KEY_STORE_SBKEY_BODY_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_SBKEY_BODY_FIELD_SHIFT (0U) +#define FLASH_KEY_STORE_SBKEY_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_SBKEY_BODY_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_KEY_STORE_SBKEY_BODY */ +#define FLASH_KEY_STORE_SBKEY_BODY_COUNT (12U) + +/*! @name USER_KEK_KEY_CODE - . */ +/*! @{ */ +#define FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD_SHIFT (0U) +#define FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_KEY_STORE_USER_KEK_KEY_CODE */ +#define FLASH_KEY_STORE_USER_KEK_KEY_CODE_COUNT (14U) + +/*! @name USER_KEK_HEADER0 - . */ +/*! @{ */ +#define FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD_SHIFT (0U) +#define FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD_MASK) +/*! @} */ + +/*! @name USER_KEK_HEADER1 - . */ +/*! @{ */ +#define FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE_MASK (0x3U) +#define FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE_SHIFT (0U) +#define FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE_MASK) +#define FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX_MASK (0xF00U) +#define FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX_SHIFT (8U) +#define FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX_MASK) +#define FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE_MASK (0x3F000000U) +#define FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE_SHIFT (24U) +#define FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE_MASK) +/*! @} */ + +/*! @name USER_KEK_BODY - . */ +/*! @{ */ +#define FLASH_KEY_STORE_USER_KEK_BODY_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_USER_KEK_BODY_FIELD_SHIFT (0U) +#define FLASH_KEY_STORE_USER_KEK_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_USER_KEK_BODY_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_KEY_STORE_USER_KEK_BODY */ +#define FLASH_KEY_STORE_USER_KEK_BODY_COUNT (12U) + +/*! @name UDS_KEY_CODE - . */ +/*! @{ */ +#define FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_SHIFT (0U) +#define FLASH_KEY_STORE_UDS_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_KEY_STORE_UDS_KEY_CODE */ +#define FLASH_KEY_STORE_UDS_KEY_CODE_COUNT (14U) + +/*! @name UDS_HEADER0 - . */ +/*! @{ */ +#define FLASH_KEY_STORE_UDS_HEADER0_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_UDS_HEADER0_FIELD_SHIFT (0U) +#define FLASH_KEY_STORE_UDS_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER0_FIELD_MASK) +/*! @} */ + +/*! @name UDS_HEADER1 - . */ +/*! @{ */ +#define FLASH_KEY_STORE_UDS_HEADER1_TYPE_MASK (0x3U) +#define FLASH_KEY_STORE_UDS_HEADER1_TYPE_SHIFT (0U) +#define FLASH_KEY_STORE_UDS_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER1_TYPE_MASK) +#define FLASH_KEY_STORE_UDS_HEADER1_INDEX_MASK (0xF00U) +#define FLASH_KEY_STORE_UDS_HEADER1_INDEX_SHIFT (8U) +#define FLASH_KEY_STORE_UDS_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER1_INDEX_MASK) +#define FLASH_KEY_STORE_UDS_HEADER1_SIZE_MASK (0x3F000000U) +#define FLASH_KEY_STORE_UDS_HEADER1_SIZE_SHIFT (24U) +#define FLASH_KEY_STORE_UDS_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER1_SIZE_MASK) +/*! @} */ + +/*! @name UDS_BODY - . */ +/*! @{ */ +#define FLASH_KEY_STORE_UDS_BODY_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_UDS_BODY_FIELD_SHIFT (0U) +#define FLASH_KEY_STORE_UDS_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_UDS_BODY_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_KEY_STORE_UDS_BODY */ +#define FLASH_KEY_STORE_UDS_BODY_COUNT (12U) + +/*! @name PRINCE_REGION0_KEY_CODE - . */ +/*! @{ */ +#define FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD_SHIFT (0U) +#define FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE */ +#define FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_COUNT (14U) + +/*! @name PRINCE_REGION0_HEADER0 - . */ +/*! @{ */ +#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD_SHIFT (0U) +#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD_MASK) +/*! @} */ + +/*! @name PRINCE_REGION0_HEADER1 - . */ +/*! @{ */ +#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE_MASK (0x3U) +#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE_SHIFT (0U) +#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE_MASK) +#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX_MASK (0xF00U) +#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX_SHIFT (8U) +#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX_MASK) +#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE_MASK (0x3F000000U) +#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE_SHIFT (24U) +#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE_MASK) +/*! @} */ + +/*! @name PRINCE_REGION0_BODY - . */ +/*! @{ */ +#define FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD_SHIFT (0U) +#define FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_KEY_STORE_PRINCE_REGION0_BODY */ +#define FLASH_KEY_STORE_PRINCE_REGION0_BODY_COUNT (12U) + +/*! @name PRINCE_REGION1_KEY_CODE - . */ +/*! @{ */ +#define FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD_SHIFT (0U) +#define FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE */ +#define FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_COUNT (14U) + +/*! @name PRINCE_REGION1_HEADER0 - . */ +/*! @{ */ +#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD_SHIFT (0U) +#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD_MASK) +/*! @} */ + +/*! @name PRINCE_REGION1_HEADER1 - . */ +/*! @{ */ +#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE_MASK (0x3U) +#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE_SHIFT (0U) +#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE_MASK) +#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX_MASK (0xF00U) +#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX_SHIFT (8U) +#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX_MASK) +#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE_MASK (0x3F000000U) +#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE_SHIFT (24U) +#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE_MASK) +/*! @} */ + +/*! @name PRINCE_REGION1_BODY - . */ +/*! @{ */ +#define FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD_SHIFT (0U) +#define FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_KEY_STORE_PRINCE_REGION1_BODY */ +#define FLASH_KEY_STORE_PRINCE_REGION1_BODY_COUNT (12U) + +/*! @name PRINCE_REGION2_KEY_CODE - . */ +/*! @{ */ +#define FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD_SHIFT (0U) +#define FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE */ +#define FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_COUNT (14U) + +/*! @name PRINCE_REGION2_HEADER0 - . */ +/*! @{ */ +#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD_SHIFT (0U) +#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD_MASK) +/*! @} */ + +/*! @name PRINCE_REGION2_HEADER1 - . */ +/*! @{ */ +#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE_MASK (0x3U) +#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE_SHIFT (0U) +#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE_MASK) +#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX_MASK (0xF00U) +#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX_SHIFT (8U) +#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX_MASK) +#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE_MASK (0x3F000000U) +#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE_SHIFT (24U) +#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE_MASK) +/*! @} */ + +/*! @name PRINCE_REGION2_BODY - . */ +/*! @{ */ +#define FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD_SHIFT (0U) +#define FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_KEY_STORE_PRINCE_REGION2_BODY */ +#define FLASH_KEY_STORE_PRINCE_REGION2_BODY_COUNT (12U) + + +/*! + * @} + */ /* end of group FLASH_KEY_STORE_Register_Masks */ + + +/* FLASH_KEY_STORE - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral FLASH_KEY_STORE base address */ + #define FLASH_KEY_STORE_BASE (0x1009E600u) + /** Peripheral FLASH_KEY_STORE base address */ + #define FLASH_KEY_STORE_BASE_NS (0x9E600u) + /** Peripheral FLASH_KEY_STORE base pointer */ + #define FLASH_KEY_STORE ((FLASH_KEY_STORE_Type *)FLASH_KEY_STORE_BASE) + /** Peripheral FLASH_KEY_STORE base pointer */ + #define FLASH_KEY_STORE_NS ((FLASH_KEY_STORE_Type *)FLASH_KEY_STORE_BASE_NS) + /** Array initializer of FLASH_KEY_STORE peripheral base addresses */ + #define FLASH_KEY_STORE_BASE_ADDRS { FLASH_KEY_STORE_BASE } + /** Array initializer of FLASH_KEY_STORE peripheral base pointers */ + #define FLASH_KEY_STORE_BASE_PTRS { FLASH_KEY_STORE } + /** Array initializer of FLASH_KEY_STORE peripheral base addresses */ + #define FLASH_KEY_STORE_BASE_ADDRS_NS { FLASH_KEY_STORE_BASE_NS } + /** Array initializer of FLASH_KEY_STORE peripheral base pointers */ + #define FLASH_KEY_STORE_BASE_PTRS_NS { FLASH_KEY_STORE_NS } +#else + /** Peripheral FLASH_KEY_STORE base address */ + #define FLASH_KEY_STORE_BASE (0x9E600u) + /** Peripheral FLASH_KEY_STORE base pointer */ + #define FLASH_KEY_STORE ((FLASH_KEY_STORE_Type *)FLASH_KEY_STORE_BASE) + /** Array initializer of FLASH_KEY_STORE peripheral base addresses */ + #define FLASH_KEY_STORE_BASE_ADDRS { FLASH_KEY_STORE_BASE } + /** Array initializer of FLASH_KEY_STORE peripheral base pointers */ + #define FLASH_KEY_STORE_BASE_PTRS { FLASH_KEY_STORE } +#endif + +/*! + * @} + */ /* end of group FLASH_KEY_STORE_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FLEXCOMM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLEXCOMM_Peripheral_Access_Layer FLEXCOMM Peripheral Access Layer + * @{ + */ + +/** FLEXCOMM - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[4088]; + __IO uint32_t PSELID; /**< Peripheral Select and Flexcomm ID register., offset: 0xFF8 */ + __I uint32_t PID; /**< Peripheral identification register., offset: 0xFFC */ +} FLEXCOMM_Type; + +/* ---------------------------------------------------------------------------- + -- FLEXCOMM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLEXCOMM_Register_Masks FLEXCOMM Register Masks + * @{ + */ + +/*! @name PSELID - Peripheral Select and Flexcomm ID register. */ +/*! @{ */ +#define FLEXCOMM_PSELID_PERSEL_MASK (0x7U) +#define FLEXCOMM_PSELID_PERSEL_SHIFT (0U) +/*! PERSEL - Peripheral Select. This field is writable by software. + * 0b000..No peripheral selected. + * 0b001..USART function selected. + * 0b010..SPI function selected. + * 0b011..I2C function selected. + * 0b100..I2S transmit function selected. + * 0b101..I2S receive function selected. + * 0b110..Reserved + * 0b111..Reserved + */ +#define FLEXCOMM_PSELID_PERSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_PERSEL_SHIFT)) & FLEXCOMM_PSELID_PERSEL_MASK) +#define FLEXCOMM_PSELID_LOCK_MASK (0x8U) +#define FLEXCOMM_PSELID_LOCK_SHIFT (3U) +/*! LOCK - Lock the peripheral select. This field is writable by software. + * 0b0..Peripheral select can be changed by software. + * 0b1..Peripheral select is locked and cannot be changed until this Flexcomm or the entire device is reset. + */ +#define FLEXCOMM_PSELID_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_LOCK_SHIFT)) & FLEXCOMM_PSELID_LOCK_MASK) +#define FLEXCOMM_PSELID_USARTPRESENT_MASK (0x10U) +#define FLEXCOMM_PSELID_USARTPRESENT_SHIFT (4U) +/*! USARTPRESENT - USART present indicator. This field is Read-only. + * 0b0..This Flexcomm does not include the USART function. + * 0b1..This Flexcomm includes the USART function. + */ +#define FLEXCOMM_PSELID_USARTPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_USARTPRESENT_SHIFT)) & FLEXCOMM_PSELID_USARTPRESENT_MASK) +#define FLEXCOMM_PSELID_SPIPRESENT_MASK (0x20U) +#define FLEXCOMM_PSELID_SPIPRESENT_SHIFT (5U) +/*! SPIPRESENT - SPI present indicator. This field is Read-only. + * 0b0..This Flexcomm does not include the SPI function. + * 0b1..This Flexcomm includes the SPI function. + */ +#define FLEXCOMM_PSELID_SPIPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_SPIPRESENT_SHIFT)) & FLEXCOMM_PSELID_SPIPRESENT_MASK) +#define FLEXCOMM_PSELID_I2CPRESENT_MASK (0x40U) +#define FLEXCOMM_PSELID_I2CPRESENT_SHIFT (6U) +/*! I2CPRESENT - I2C present indicator. This field is Read-only. + * 0b0..This Flexcomm does not include the I2C function. + * 0b1..This Flexcomm includes the I2C function. + */ +#define FLEXCOMM_PSELID_I2CPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2CPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2CPRESENT_MASK) +#define FLEXCOMM_PSELID_I2SPRESENT_MASK (0x80U) +#define FLEXCOMM_PSELID_I2SPRESENT_SHIFT (7U) +/*! I2SPRESENT - I 2S present indicator. This field is Read-only. + * 0b0..This Flexcomm does not include the I2S function. + * 0b1..This Flexcomm includes the I2S function. + */ +#define FLEXCOMM_PSELID_I2SPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2SPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2SPRESENT_MASK) +#define FLEXCOMM_PSELID_ID_MASK (0xFFFFF000U) +#define FLEXCOMM_PSELID_ID_SHIFT (12U) +#define FLEXCOMM_PSELID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_ID_SHIFT)) & FLEXCOMM_PSELID_ID_MASK) +/*! @} */ + +/*! @name PID - Peripheral identification register. */ +/*! @{ */ +#define FLEXCOMM_PID_Aperture_MASK (0xFFU) +#define FLEXCOMM_PID_Aperture_SHIFT (0U) +#define FLEXCOMM_PID_Aperture(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Aperture_SHIFT)) & FLEXCOMM_PID_Aperture_MASK) +#define FLEXCOMM_PID_Minor_Rev_MASK (0xF00U) +#define FLEXCOMM_PID_Minor_Rev_SHIFT (8U) +#define FLEXCOMM_PID_Minor_Rev(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Minor_Rev_SHIFT)) & FLEXCOMM_PID_Minor_Rev_MASK) +#define FLEXCOMM_PID_Major_Rev_MASK (0xF000U) +#define FLEXCOMM_PID_Major_Rev_SHIFT (12U) +#define FLEXCOMM_PID_Major_Rev(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Major_Rev_SHIFT)) & FLEXCOMM_PID_Major_Rev_MASK) +#define FLEXCOMM_PID_ID_MASK (0xFFFF0000U) +#define FLEXCOMM_PID_ID_SHIFT (16U) +#define FLEXCOMM_PID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_ID_SHIFT)) & FLEXCOMM_PID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group FLEXCOMM_Register_Masks */ + + +/* FLEXCOMM - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral FLEXCOMM0 base address */ + #define FLEXCOMM0_BASE (0x50086000u) + /** Peripheral FLEXCOMM0 base address */ + #define FLEXCOMM0_BASE_NS (0x40086000u) + /** Peripheral FLEXCOMM0 base pointer */ + #define FLEXCOMM0 ((FLEXCOMM_Type *)FLEXCOMM0_BASE) + /** Peripheral FLEXCOMM0 base pointer */ + #define FLEXCOMM0_NS ((FLEXCOMM_Type *)FLEXCOMM0_BASE_NS) + /** Peripheral FLEXCOMM1 base address */ + #define FLEXCOMM1_BASE (0x50087000u) + /** Peripheral FLEXCOMM1 base address */ + #define FLEXCOMM1_BASE_NS (0x40087000u) + /** Peripheral FLEXCOMM1 base pointer */ + #define FLEXCOMM1 ((FLEXCOMM_Type *)FLEXCOMM1_BASE) + /** Peripheral FLEXCOMM1 base pointer */ + #define FLEXCOMM1_NS ((FLEXCOMM_Type *)FLEXCOMM1_BASE_NS) + /** Peripheral FLEXCOMM2 base address */ + #define FLEXCOMM2_BASE (0x50088000u) + /** Peripheral FLEXCOMM2 base address */ + #define FLEXCOMM2_BASE_NS (0x40088000u) + /** Peripheral FLEXCOMM2 base pointer */ + #define FLEXCOMM2 ((FLEXCOMM_Type *)FLEXCOMM2_BASE) + /** Peripheral FLEXCOMM2 base pointer */ + #define FLEXCOMM2_NS ((FLEXCOMM_Type *)FLEXCOMM2_BASE_NS) + /** Peripheral FLEXCOMM3 base address */ + #define FLEXCOMM3_BASE (0x50089000u) + /** Peripheral FLEXCOMM3 base address */ + #define FLEXCOMM3_BASE_NS (0x40089000u) + /** Peripheral FLEXCOMM3 base pointer */ + #define FLEXCOMM3 ((FLEXCOMM_Type *)FLEXCOMM3_BASE) + /** Peripheral FLEXCOMM3 base pointer */ + #define FLEXCOMM3_NS ((FLEXCOMM_Type *)FLEXCOMM3_BASE_NS) + /** Peripheral FLEXCOMM4 base address */ + #define FLEXCOMM4_BASE (0x5008A000u) + /** Peripheral FLEXCOMM4 base address */ + #define FLEXCOMM4_BASE_NS (0x4008A000u) + /** Peripheral FLEXCOMM4 base pointer */ + #define FLEXCOMM4 ((FLEXCOMM_Type *)FLEXCOMM4_BASE) + /** Peripheral FLEXCOMM4 base pointer */ + #define FLEXCOMM4_NS ((FLEXCOMM_Type *)FLEXCOMM4_BASE_NS) + /** Peripheral FLEXCOMM5 base address */ + #define FLEXCOMM5_BASE (0x50096000u) + /** Peripheral FLEXCOMM5 base address */ + #define FLEXCOMM5_BASE_NS (0x40096000u) + /** Peripheral FLEXCOMM5 base pointer */ + #define FLEXCOMM5 ((FLEXCOMM_Type *)FLEXCOMM5_BASE) + /** Peripheral FLEXCOMM5 base pointer */ + #define FLEXCOMM5_NS ((FLEXCOMM_Type *)FLEXCOMM5_BASE_NS) + /** Peripheral FLEXCOMM6 base address */ + #define FLEXCOMM6_BASE (0x50097000u) + /** Peripheral FLEXCOMM6 base address */ + #define FLEXCOMM6_BASE_NS (0x40097000u) + /** Peripheral FLEXCOMM6 base pointer */ + #define FLEXCOMM6 ((FLEXCOMM_Type *)FLEXCOMM6_BASE) + /** Peripheral FLEXCOMM6 base pointer */ + #define FLEXCOMM6_NS ((FLEXCOMM_Type *)FLEXCOMM6_BASE_NS) + /** Peripheral FLEXCOMM7 base address */ + #define FLEXCOMM7_BASE (0x50098000u) + /** Peripheral FLEXCOMM7 base address */ + #define FLEXCOMM7_BASE_NS (0x40098000u) + /** Peripheral FLEXCOMM7 base pointer */ + #define FLEXCOMM7 ((FLEXCOMM_Type *)FLEXCOMM7_BASE) + /** Peripheral FLEXCOMM7 base pointer */ + #define FLEXCOMM7_NS ((FLEXCOMM_Type *)FLEXCOMM7_BASE_NS) + /** Peripheral FLEXCOMM8 base address */ + #define FLEXCOMM8_BASE (0x5009F000u) + /** Peripheral FLEXCOMM8 base address */ + #define FLEXCOMM8_BASE_NS (0x4009F000u) + /** Peripheral FLEXCOMM8 base pointer */ + #define FLEXCOMM8 ((FLEXCOMM_Type *)FLEXCOMM8_BASE) + /** Peripheral FLEXCOMM8 base pointer */ + #define FLEXCOMM8_NS ((FLEXCOMM_Type *)FLEXCOMM8_BASE_NS) + /** Array initializer of FLEXCOMM peripheral base addresses */ + #define FLEXCOMM_BASE_ADDRS { FLEXCOMM0_BASE, FLEXCOMM1_BASE, FLEXCOMM2_BASE, FLEXCOMM3_BASE, FLEXCOMM4_BASE, FLEXCOMM5_BASE, FLEXCOMM6_BASE, FLEXCOMM7_BASE, FLEXCOMM8_BASE } + /** Array initializer of FLEXCOMM peripheral base pointers */ + #define FLEXCOMM_BASE_PTRS { FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8 } + /** Array initializer of FLEXCOMM peripheral base addresses */ + #define FLEXCOMM_BASE_ADDRS_NS { FLEXCOMM0_BASE_NS, FLEXCOMM1_BASE_NS, FLEXCOMM2_BASE_NS, FLEXCOMM3_BASE_NS, FLEXCOMM4_BASE_NS, FLEXCOMM5_BASE_NS, FLEXCOMM6_BASE_NS, FLEXCOMM7_BASE_NS, FLEXCOMM8_BASE_NS } + /** Array initializer of FLEXCOMM peripheral base pointers */ + #define FLEXCOMM_BASE_PTRS_NS { FLEXCOMM0_NS, FLEXCOMM1_NS, FLEXCOMM2_NS, FLEXCOMM3_NS, FLEXCOMM4_NS, FLEXCOMM5_NS, FLEXCOMM6_NS, FLEXCOMM7_NS, FLEXCOMM8_NS } +#else + /** Peripheral FLEXCOMM0 base address */ + #define FLEXCOMM0_BASE (0x40086000u) + /** Peripheral FLEXCOMM0 base pointer */ + #define FLEXCOMM0 ((FLEXCOMM_Type *)FLEXCOMM0_BASE) + /** Peripheral FLEXCOMM1 base address */ + #define FLEXCOMM1_BASE (0x40087000u) + /** Peripheral FLEXCOMM1 base pointer */ + #define FLEXCOMM1 ((FLEXCOMM_Type *)FLEXCOMM1_BASE) + /** Peripheral FLEXCOMM2 base address */ + #define FLEXCOMM2_BASE (0x40088000u) + /** Peripheral FLEXCOMM2 base pointer */ + #define FLEXCOMM2 ((FLEXCOMM_Type *)FLEXCOMM2_BASE) + /** Peripheral FLEXCOMM3 base address */ + #define FLEXCOMM3_BASE (0x40089000u) + /** Peripheral FLEXCOMM3 base pointer */ + #define FLEXCOMM3 ((FLEXCOMM_Type *)FLEXCOMM3_BASE) + /** Peripheral FLEXCOMM4 base address */ + #define FLEXCOMM4_BASE (0x4008A000u) + /** Peripheral FLEXCOMM4 base pointer */ + #define FLEXCOMM4 ((FLEXCOMM_Type *)FLEXCOMM4_BASE) + /** Peripheral FLEXCOMM5 base address */ + #define FLEXCOMM5_BASE (0x40096000u) + /** Peripheral FLEXCOMM5 base pointer */ + #define FLEXCOMM5 ((FLEXCOMM_Type *)FLEXCOMM5_BASE) + /** Peripheral FLEXCOMM6 base address */ + #define FLEXCOMM6_BASE (0x40097000u) + /** Peripheral FLEXCOMM6 base pointer */ + #define FLEXCOMM6 ((FLEXCOMM_Type *)FLEXCOMM6_BASE) + /** Peripheral FLEXCOMM7 base address */ + #define FLEXCOMM7_BASE (0x40098000u) + /** Peripheral FLEXCOMM7 base pointer */ + #define FLEXCOMM7 ((FLEXCOMM_Type *)FLEXCOMM7_BASE) + /** Peripheral FLEXCOMM8 base address */ + #define FLEXCOMM8_BASE (0x4009F000u) + /** Peripheral FLEXCOMM8 base pointer */ + #define FLEXCOMM8 ((FLEXCOMM_Type *)FLEXCOMM8_BASE) + /** Array initializer of FLEXCOMM peripheral base addresses */ + #define FLEXCOMM_BASE_ADDRS { FLEXCOMM0_BASE, FLEXCOMM1_BASE, FLEXCOMM2_BASE, FLEXCOMM3_BASE, FLEXCOMM4_BASE, FLEXCOMM5_BASE, FLEXCOMM6_BASE, FLEXCOMM7_BASE, FLEXCOMM8_BASE } + /** Array initializer of FLEXCOMM peripheral base pointers */ + #define FLEXCOMM_BASE_PTRS { FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8 } +#endif +/** Interrupt vectors for the FLEXCOMM peripheral type */ +#define FLEXCOMM_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn } + +/*! + * @} + */ /* end of group FLEXCOMM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- GINT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GINT_Peripheral_Access_Layer GINT Peripheral Access Layer + * @{ + */ + +/** GINT - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< GPIO grouped interrupt control register, offset: 0x0 */ + uint8_t RESERVED_0[28]; + __IO uint32_t PORT_POL[2]; /**< GPIO grouped interrupt port 0 polarity register, array offset: 0x20, array step: 0x4 */ + uint8_t RESERVED_1[24]; + __IO uint32_t PORT_ENA[2]; /**< GPIO grouped interrupt port 0 enable register, array offset: 0x40, array step: 0x4 */ +} GINT_Type; + +/* ---------------------------------------------------------------------------- + -- GINT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GINT_Register_Masks GINT Register Masks + * @{ + */ + +/*! @name CTRL - GPIO grouped interrupt control register */ +/*! @{ */ +#define GINT_CTRL_INT_MASK (0x1U) +#define GINT_CTRL_INT_SHIFT (0U) +/*! INT - Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect. + * 0b0..No request. No interrupt request is pending. + * 0b1..Request active. Interrupt request is active. + */ +#define GINT_CTRL_INT(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_INT_SHIFT)) & GINT_CTRL_INT_MASK) +#define GINT_CTRL_COMB_MASK (0x2U) +#define GINT_CTRL_COMB_SHIFT (1U) +/*! COMB - Combine enabled inputs for group interrupt + * 0b0..Or. OR functionality: A grouped interrupt is generated when any one of the enabled inputs is active (based on its programmed polarity). + * 0b1..And. AND functionality: An interrupt is generated when all enabled bits are active (based on their programmed polarity). + */ +#define GINT_CTRL_COMB(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_COMB_SHIFT)) & GINT_CTRL_COMB_MASK) +#define GINT_CTRL_TRIG_MASK (0x4U) +#define GINT_CTRL_TRIG_SHIFT (2U) +/*! TRIG - Group interrupt trigger + * 0b0..Edge-triggered. + * 0b1..Level-triggered. + */ +#define GINT_CTRL_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_TRIG_SHIFT)) & GINT_CTRL_TRIG_MASK) +/*! @} */ + +/*! @name PORT_POL - GPIO grouped interrupt port 0 polarity register */ +/*! @{ */ +#define GINT_PORT_POL_POL_MASK (0xFFFFFFFFU) +#define GINT_PORT_POL_POL_SHIFT (0U) +#define GINT_PORT_POL_POL(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL_SHIFT)) & GINT_PORT_POL_POL_MASK) +/*! @} */ + +/* The count of GINT_PORT_POL */ +#define GINT_PORT_POL_COUNT (2U) + +/*! @name PORT_ENA - GPIO grouped interrupt port 0 enable register */ +/*! @{ */ +#define GINT_PORT_ENA_ENA_MASK (0xFFFFFFFFU) +#define GINT_PORT_ENA_ENA_SHIFT (0U) +#define GINT_PORT_ENA_ENA(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA_SHIFT)) & GINT_PORT_ENA_ENA_MASK) +/*! @} */ + +/* The count of GINT_PORT_ENA */ +#define GINT_PORT_ENA_COUNT (2U) + + +/*! + * @} + */ /* end of group GINT_Register_Masks */ + + +/* GINT - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral GINT0 base address */ + #define GINT0_BASE (0x50002000u) + /** Peripheral GINT0 base address */ + #define GINT0_BASE_NS (0x40002000u) + /** Peripheral GINT0 base pointer */ + #define GINT0 ((GINT_Type *)GINT0_BASE) + /** Peripheral GINT0 base pointer */ + #define GINT0_NS ((GINT_Type *)GINT0_BASE_NS) + /** Peripheral GINT1 base address */ + #define GINT1_BASE (0x50003000u) + /** Peripheral GINT1 base address */ + #define GINT1_BASE_NS (0x40003000u) + /** Peripheral GINT1 base pointer */ + #define GINT1 ((GINT_Type *)GINT1_BASE) + /** Peripheral GINT1 base pointer */ + #define GINT1_NS ((GINT_Type *)GINT1_BASE_NS) + /** Array initializer of GINT peripheral base addresses */ + #define GINT_BASE_ADDRS { GINT0_BASE, GINT1_BASE } + /** Array initializer of GINT peripheral base pointers */ + #define GINT_BASE_PTRS { GINT0, GINT1 } + /** Array initializer of GINT peripheral base addresses */ + #define GINT_BASE_ADDRS_NS { GINT0_BASE_NS, GINT1_BASE_NS } + /** Array initializer of GINT peripheral base pointers */ + #define GINT_BASE_PTRS_NS { GINT0_NS, GINT1_NS } +#else + /** Peripheral GINT0 base address */ + #define GINT0_BASE (0x40002000u) + /** Peripheral GINT0 base pointer */ + #define GINT0 ((GINT_Type *)GINT0_BASE) + /** Peripheral GINT1 base address */ + #define GINT1_BASE (0x40003000u) + /** Peripheral GINT1 base pointer */ + #define GINT1 ((GINT_Type *)GINT1_BASE) + /** Array initializer of GINT peripheral base addresses */ + #define GINT_BASE_ADDRS { GINT0_BASE, GINT1_BASE } + /** Array initializer of GINT peripheral base pointers */ + #define GINT_BASE_PTRS { GINT0, GINT1 } +#endif +/** Interrupt vectors for the GINT peripheral type */ +#define GINT_IRQS { GINT0_IRQn, GINT1_IRQn } + +/*! + * @} + */ /* end of group GINT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- GPIO Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer + * @{ + */ + +/** GPIO - Register Layout Typedef */ +typedef struct { + __IO uint8_t B[4][32]; /**< Byte pin registers for all port GPIO pins, array offset: 0x0, array step: index*0x20, index2*0x1 */ + uint8_t RESERVED_0[3968]; + __IO uint32_t W[4][32]; /**< Word pin registers for all port GPIO pins, array offset: 0x1000, array step: index*0x80, index2*0x4 */ + uint8_t RESERVED_1[3584]; + __IO uint32_t DIR[4]; /**< Direction registers for all port GPIO pins, array offset: 0x2000, array step: 0x4 */ + uint8_t RESERVED_2[112]; + __IO uint32_t MASK[4]; /**< Mask register for all port GPIO pins, array offset: 0x2080, array step: 0x4 */ + uint8_t RESERVED_3[112]; + __IO uint32_t PIN[4]; /**< Port pin register for all port GPIO pins, array offset: 0x2100, array step: 0x4 */ + uint8_t RESERVED_4[112]; + __IO uint32_t MPIN[4]; /**< Masked port register for all port GPIO pins, array offset: 0x2180, array step: 0x4 */ + uint8_t RESERVED_5[112]; + __IO uint32_t SET[4]; /**< Write: Set register for port. Read: output bits for port, array offset: 0x2200, array step: 0x4 */ + uint8_t RESERVED_6[112]; + __O uint32_t CLR[4]; /**< Clear port for all port GPIO pins, array offset: 0x2280, array step: 0x4 */ + uint8_t RESERVED_7[112]; + __O uint32_t NOT[4]; /**< Toggle port for all port GPIO pins, array offset: 0x2300, array step: 0x4 */ + uint8_t RESERVED_8[112]; + __O uint32_t DIRSET[4]; /**< Set pin direction bits for port, array offset: 0x2380, array step: 0x4 */ + uint8_t RESERVED_9[112]; + __O uint32_t DIRCLR[4]; /**< Clear pin direction bits for port, array offset: 0x2400, array step: 0x4 */ + uint8_t RESERVED_10[112]; + __O uint32_t DIRNOT[4]; /**< Toggle pin direction bits for port, array offset: 0x2480, array step: 0x4 */ +} GPIO_Type; + +/* ---------------------------------------------------------------------------- + -- GPIO Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPIO_Register_Masks GPIO Register Masks + * @{ + */ + +/*! @name B - Byte pin registers for all port GPIO pins */ +/*! @{ */ +#define GPIO_B_PBYTE_MASK (0x1U) +#define GPIO_B_PBYTE_SHIFT (0U) +#define GPIO_B_PBYTE(x) (((uint8_t)(((uint8_t)(x)) << GPIO_B_PBYTE_SHIFT)) & GPIO_B_PBYTE_MASK) +/*! @} */ + +/* The count of GPIO_B */ +#define GPIO_B_COUNT (4U) + +/* The count of GPIO_B */ +#define GPIO_B_COUNT2 (32U) + +/*! @name W - Word pin registers for all port GPIO pins */ +/*! @{ */ +#define GPIO_W_PWORD_MASK (0xFFFFFFFFU) +#define GPIO_W_PWORD_SHIFT (0U) +#define GPIO_W_PWORD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_W_PWORD_SHIFT)) & GPIO_W_PWORD_MASK) +/*! @} */ + +/* The count of GPIO_W */ +#define GPIO_W_COUNT (4U) + +/* The count of GPIO_W */ +#define GPIO_W_COUNT2 (32U) + +/*! @name DIR - Direction registers for all port GPIO pins */ +/*! @{ */ +#define GPIO_DIR_DIRP_MASK (0xFFFFFFFFU) +#define GPIO_DIR_DIRP_SHIFT (0U) +#define GPIO_DIR_DIRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP_SHIFT)) & GPIO_DIR_DIRP_MASK) +/*! @} */ + +/* The count of GPIO_DIR */ +#define GPIO_DIR_COUNT (4U) + +/*! @name MASK - Mask register for all port GPIO pins */ +/*! @{ */ +#define GPIO_MASK_MASKP_MASK (0xFFFFFFFFU) +#define GPIO_MASK_MASKP_SHIFT (0U) +#define GPIO_MASK_MASKP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP_SHIFT)) & GPIO_MASK_MASKP_MASK) +/*! @} */ + +/* The count of GPIO_MASK */ +#define GPIO_MASK_COUNT (4U) + +/*! @name PIN - Port pin register for all port GPIO pins */ +/*! @{ */ +#define GPIO_PIN_PORT_MASK (0xFFFFFFFFU) +#define GPIO_PIN_PORT_SHIFT (0U) +#define GPIO_PIN_PORT(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT_SHIFT)) & GPIO_PIN_PORT_MASK) +/*! @} */ + +/* The count of GPIO_PIN */ +#define GPIO_PIN_COUNT (4U) + +/*! @name MPIN - Masked port register for all port GPIO pins */ +/*! @{ */ +#define GPIO_MPIN_MPORTP_MASK (0xFFFFFFFFU) +#define GPIO_MPIN_MPORTP_SHIFT (0U) +#define GPIO_MPIN_MPORTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP_SHIFT)) & GPIO_MPIN_MPORTP_MASK) +/*! @} */ + +/* The count of GPIO_MPIN */ +#define GPIO_MPIN_COUNT (4U) + +/*! @name SET - Write: Set register for port. Read: output bits for port */ +/*! @{ */ +#define GPIO_SET_SETP_MASK (0xFFFFFFFFU) +#define GPIO_SET_SETP_SHIFT (0U) +#define GPIO_SET_SETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_SET_SETP_SHIFT)) & GPIO_SET_SETP_MASK) +/*! @} */ + +/* The count of GPIO_SET */ +#define GPIO_SET_COUNT (4U) + +/*! @name CLR - Clear port for all port GPIO pins */ +/*! @{ */ +#define GPIO_CLR_CLRP_MASK (0xFFFFFFFFU) +#define GPIO_CLR_CLRP_SHIFT (0U) +#define GPIO_CLR_CLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP_SHIFT)) & GPIO_CLR_CLRP_MASK) +/*! @} */ + +/* The count of GPIO_CLR */ +#define GPIO_CLR_COUNT (4U) + +/*! @name NOT - Toggle port for all port GPIO pins */ +/*! @{ */ +#define GPIO_NOT_NOTP_MASK (0xFFFFFFFFU) +#define GPIO_NOT_NOTP_SHIFT (0U) +#define GPIO_NOT_NOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP_SHIFT)) & GPIO_NOT_NOTP_MASK) +/*! @} */ + +/* The count of GPIO_NOT */ +#define GPIO_NOT_COUNT (4U) + +/*! @name DIRSET - Set pin direction bits for port */ +/*! @{ */ +#define GPIO_DIRSET_DIRSETP_MASK (0x1FFFFFFFU) +#define GPIO_DIRSET_DIRSETP_SHIFT (0U) +#define GPIO_DIRSET_DIRSETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP_SHIFT)) & GPIO_DIRSET_DIRSETP_MASK) +/*! @} */ + +/* The count of GPIO_DIRSET */ +#define GPIO_DIRSET_COUNT (4U) + +/*! @name DIRCLR - Clear pin direction bits for port */ +/*! @{ */ +#define GPIO_DIRCLR_DIRCLRP_MASK (0x1FFFFFFFU) +#define GPIO_DIRCLR_DIRCLRP_SHIFT (0U) +#define GPIO_DIRCLR_DIRCLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP_SHIFT)) & GPIO_DIRCLR_DIRCLRP_MASK) +/*! @} */ + +/* The count of GPIO_DIRCLR */ +#define GPIO_DIRCLR_COUNT (4U) + +/*! @name DIRNOT - Toggle pin direction bits for port */ +/*! @{ */ +#define GPIO_DIRNOT_DIRNOTP_MASK (0x1FFFFFFFU) +#define GPIO_DIRNOT_DIRNOTP_SHIFT (0U) +#define GPIO_DIRNOT_DIRNOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRNOT_DIRNOTP_SHIFT)) & GPIO_DIRNOT_DIRNOTP_MASK) +/*! @} */ + +/* The count of GPIO_DIRNOT */ +#define GPIO_DIRNOT_COUNT (4U) + + +/*! + * @} + */ /* end of group GPIO_Register_Masks */ + + +/* GPIO - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral GPIO base address */ + #define GPIO_BASE (0x5008C000u) + /** Peripheral GPIO base address */ + #define GPIO_BASE_NS (0x4008C000u) + /** Peripheral GPIO base pointer */ + #define GPIO ((GPIO_Type *)GPIO_BASE) + /** Peripheral GPIO base pointer */ + #define GPIO_NS ((GPIO_Type *)GPIO_BASE_NS) + /** Peripheral SECGPIO base address */ + #define SECGPIO_BASE (0x500A8000u) + /** Peripheral SECGPIO base address */ + #define SECGPIO_BASE_NS (0x400A8000u) + /** Peripheral SECGPIO base pointer */ + #define SECGPIO ((GPIO_Type *)SECGPIO_BASE) + /** Peripheral SECGPIO base pointer */ + #define SECGPIO_NS ((GPIO_Type *)SECGPIO_BASE_NS) + /** Array initializer of GPIO peripheral base addresses */ + #define GPIO_BASE_ADDRS { GPIO_BASE, SECGPIO_BASE } + /** Array initializer of GPIO peripheral base pointers */ + #define GPIO_BASE_PTRS { GPIO, SECGPIO } + /** Array initializer of GPIO peripheral base addresses */ + #define GPIO_BASE_ADDRS_NS { GPIO_BASE_NS, SECGPIO_BASE_NS } + /** Array initializer of GPIO peripheral base pointers */ + #define GPIO_BASE_PTRS_NS { GPIO_NS, SECGPIO_NS } +#else + /** Peripheral GPIO base address */ + #define GPIO_BASE (0x4008C000u) + /** Peripheral GPIO base pointer */ + #define GPIO ((GPIO_Type *)GPIO_BASE) + /** Peripheral SECGPIO base address */ + #define SECGPIO_BASE (0x400A8000u) + /** Peripheral SECGPIO base pointer */ + #define SECGPIO ((GPIO_Type *)SECGPIO_BASE) + /** Array initializer of GPIO peripheral base addresses */ + #define GPIO_BASE_ADDRS { GPIO_BASE, SECGPIO_BASE } + /** Array initializer of GPIO peripheral base pointers */ + #define GPIO_BASE_PTRS { GPIO, SECGPIO } +#endif + +/*! + * @} + */ /* end of group GPIO_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- HASHCRYPT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup HASHCRYPT_Peripheral_Access_Layer HASHCRYPT Peripheral Access Layer + * @{ + */ + +/** HASHCRYPT - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< Is control register to enable and operate Hash and Crypto, offset: 0x0 */ + __IO uint32_t STATUS; /**< Indicates status of Hash peripheral., offset: 0x4 */ + __IO uint32_t INTENSET; /**< Write 1 to enable interrupts; reads back with which are set., offset: 0x8 */ + __IO uint32_t INTENCLR; /**< Write 1 to clear interrupts., offset: 0xC */ + __IO uint32_t MEMCTRL; /**< Setup Master to access memory (if available), offset: 0x10 */ + __IO uint32_t MEMADDR; /**< Address to start memory access from (if available)., offset: 0x14 */ + uint8_t RESERVED_0[8]; + __O uint32_t INDATA; /**< Input of 16 words at a time to load up buffer., offset: 0x20 */ + __O uint32_t ALIAS[7]; /**< , array offset: 0x24, array step: 0x4 */ + __I uint32_t OUTDATA0[8]; /**< , array offset: 0x40, array step: 0x4 */ + __I uint32_t OUTDATA1[8]; /**< , array offset: 0x60, array step: 0x4 */ + __IO uint32_t CRYPTCFG; /**< Crypto settings for AES and Salsa and ChaCha, offset: 0x80 */ + __I uint32_t CONFIG; /**< Returns the configuration of this block in this chip - indicates what services are available., offset: 0x84 */ + uint8_t RESERVED_1[4]; + __IO uint32_t LOCK; /**< Lock register allows locking to the current security level or unlocking by the lock holding level., offset: 0x8C */ + __O uint32_t MASK[4]; /**< , array offset: 0x90, array step: 0x4 */ +} HASHCRYPT_Type; + +/* ---------------------------------------------------------------------------- + -- HASHCRYPT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup HASHCRYPT_Register_Masks HASHCRYPT Register Masks + * @{ + */ + +/*! @name CTRL - Is control register to enable and operate Hash and Crypto */ +/*! @{ */ +#define HASHCRYPT_CTRL_MODE_MASK (0x7U) +#define HASHCRYPT_CTRL_MODE_SHIFT (0U) +/*! Mode - The operational mode to use, or 0 if none. Note that the CONFIG register will indicate if + * specific modes beyond SHA1 and SHA2-256 are available. + * 0b000..Disabled + * 0b001..SHA1 is enabled + * 0b010..SHA2-256 is enabled + * 0b011..SHA2-512 is enabled (if available) + * 0b100..AES if available (see also CRYPTCFG register for more controls) + * 0b101..ICB-AES if available (see also CRYPTCFG register for more controls) + * 0b110..Salsa20/20 if available (including XSalsa - see also CRYPTCFG register) + * 0b111..ChaCha20 if available (see also CRYPTCFG register for more controls) + */ +#define HASHCRYPT_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_MODE_SHIFT)) & HASHCRYPT_CTRL_MODE_MASK) +#define HASHCRYPT_CTRL_NEW_HASH_MASK (0x10U) +#define HASHCRYPT_CTRL_NEW_HASH_SHIFT (4U) +/*! New_Hash - Written with 1 when starting a new Hash/Crypto. It self clears. Note that the WAITING + * Status bit will clear for a cycle during the initialization from New=1. + * 0b1..Starts a new Hash/Crypto and initializes the Digest/Result. + */ +#define HASHCRYPT_CTRL_NEW_HASH(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_NEW_HASH_SHIFT)) & HASHCRYPT_CTRL_NEW_HASH_MASK) +#define HASHCRYPT_CTRL_DMA_I_MASK (0x100U) +#define HASHCRYPT_CTRL_DMA_I_SHIFT (8U) +/*! DMA_I - Written with 1 to use DMA to fill INDATA. If Hash, will request from DMA for 16 words + * and then will process the Hash. If Cryptographic, it will load as many words as needed, + * including key if not already loaded. It will then request again. Normal model is that the DMA + * interrupts the processor when its length expires. Note that if the processor will write the key and + * optionally IV, it should not enable this until it has done so. Otherwise, the DMA will be + * expected to load those for the 1st block (when needed). + * 0b0..DMA is not used. Processor writes the necessary words when WAITING is set (interrupts), unless AHB Master is used. + * 0b1..DMA will push in the data. + */ +#define HASHCRYPT_CTRL_DMA_I(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_DMA_I_SHIFT)) & HASHCRYPT_CTRL_DMA_I_MASK) +#define HASHCRYPT_CTRL_DMA_O_MASK (0x200U) +#define HASHCRYPT_CTRL_DMA_O_SHIFT (9U) +/*! DMA_O - Written to 1 to use DMA to drain the digest/output. If both DMA_I and DMA_O are set, the + * DMA has to know to switch direction and the locations. This can be used for crypto uses. + * 0b0..DMA is not used. Processor reads the digest/output in response to DIGEST interrupt. + */ +#define HASHCRYPT_CTRL_DMA_O(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_DMA_O_SHIFT)) & HASHCRYPT_CTRL_DMA_O_MASK) +#define HASHCRYPT_CTRL_HASHSWPB_MASK (0x1000U) +#define HASHCRYPT_CTRL_HASHSWPB_SHIFT (12U) +#define HASHCRYPT_CTRL_HASHSWPB(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_HASHSWPB_SHIFT)) & HASHCRYPT_CTRL_HASHSWPB_MASK) +/*! @} */ + +/*! @name STATUS - Indicates status of Hash peripheral. */ +/*! @{ */ +#define HASHCRYPT_STATUS_WAITING_MASK (0x1U) +#define HASHCRYPT_STATUS_WAITING_SHIFT (0U) +/*! WAITING - If 1, the block is waiting for more data to process. + * 0b0..Not waiting for data - may be disabled or may be busy. Note that for cryptographic uses, this is not set + * if IsLast is set nor will it set until at least 1 word is read of the output. + * 0b1..Waiting for data to be written in (16 words) + */ +#define HASHCRYPT_STATUS_WAITING(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_WAITING_SHIFT)) & HASHCRYPT_STATUS_WAITING_MASK) +#define HASHCRYPT_STATUS_DIGEST_AKA_OUTDATA_MASK (0x2U) +#define HASHCRYPT_STATUS_DIGEST_AKA_OUTDATA_SHIFT (1U) +/*! DIGEST_aka_OUTDATA - For Hash, if 1 then a DIGEST is ready and waiting and there is no active + * next block already started. For Cryptographic uses, this will be set for each block processed, + * indicating OUTDATA (and OUTDATA2 if larger output) contains the next value to read out. This is + * cleared when any data is written, when New is written, for Cryptographic uses when the last + * word is read out, or when the block is disabled. + * 0b0..No Digest is ready + * 0b1..Digest is ready. Application may read it or may write more data + */ +#define HASHCRYPT_STATUS_DIGEST_AKA_OUTDATA(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_DIGEST_AKA_OUTDATA_SHIFT)) & HASHCRYPT_STATUS_DIGEST_AKA_OUTDATA_MASK) +#define HASHCRYPT_STATUS_ERROR_MASK (0x4U) +#define HASHCRYPT_STATUS_ERROR_SHIFT (2U) +/*! ERROR - If 1, an error occurred. For normal uses, this is due to an attempted overrun: INDATA + * was written when it was not appropriate. For Master cases, this is an AHB bus error; the COUNT + * field will indicate which block it was on. + * 0b0..No error. + * 0b1..An error occurred since last cleared (written 1 to clear). + */ +#define HASHCRYPT_STATUS_ERROR(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_ERROR_SHIFT)) & HASHCRYPT_STATUS_ERROR_MASK) +#define HASHCRYPT_STATUS_NEEDKEY_MASK (0x10U) +#define HASHCRYPT_STATUS_NEEDKEY_SHIFT (4U) +/*! NEEDKEY - Indicates the block wants the key to be written in (set along with WAITING) + * 0b0..No Key is needed and writes will not be treated as Key + * 0b1..Key is needed and INDATA/ALIAS will be accepted as Key. Will also set WAITING. + */ +#define HASHCRYPT_STATUS_NEEDKEY(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_NEEDKEY_SHIFT)) & HASHCRYPT_STATUS_NEEDKEY_MASK) +#define HASHCRYPT_STATUS_NEEDIV_MASK (0x20U) +#define HASHCRYPT_STATUS_NEEDIV_SHIFT (5U) +/*! NEEDIV - Indicates the block wants an IV/NONE to be written in (set along with WAITING) + * 0b0..No IV/Nonce is needed, either because written already or because not needed. + * 0b1..IV/Nonce is needed and INDATA/ALIAS will be accepted as IV/Nonce. Will also set WAITING. + */ +#define HASHCRYPT_STATUS_NEEDIV(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_NEEDIV_SHIFT)) & HASHCRYPT_STATUS_NEEDIV_MASK) +#define HASHCRYPT_STATUS_ICBIDX_MASK (0x3F0000U) +#define HASHCRYPT_STATUS_ICBIDX_SHIFT (16U) +#define HASHCRYPT_STATUS_ICBIDX(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_ICBIDX_SHIFT)) & HASHCRYPT_STATUS_ICBIDX_MASK) +/*! @} */ + +/*! @name INTENSET - Write 1 to enable interrupts; reads back with which are set. */ +/*! @{ */ +#define HASHCRYPT_INTENSET_WAITING_MASK (0x1U) +#define HASHCRYPT_INTENSET_WAITING_SHIFT (0U) +/*! WAITING - Indicates if should interrupt when waiting for data input. + * 0b0..Will not interrupt when waiting. + * 0b1..Will interrupt when waiting + */ +#define HASHCRYPT_INTENSET_WAITING(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENSET_WAITING_SHIFT)) & HASHCRYPT_INTENSET_WAITING_MASK) +#define HASHCRYPT_INTENSET_DIGEST_MASK (0x2U) +#define HASHCRYPT_INTENSET_DIGEST_SHIFT (1U) +/*! DIGEST - Indicates if should interrupt when Digest (or Outdata) is ready (completed a hash/crypto or completed a full sequence). + * 0b0..Will not interrupt when Digest is ready + * 0b1..Will interrupt when Digest is ready. Interrupt cleared by writing more data, starting a new Hash, or disabling (done). + */ +#define HASHCRYPT_INTENSET_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENSET_DIGEST_SHIFT)) & HASHCRYPT_INTENSET_DIGEST_MASK) +#define HASHCRYPT_INTENSET_ERROR_MASK (0x4U) +#define HASHCRYPT_INTENSET_ERROR_SHIFT (2U) +/*! ERROR - Indicates if should interrupt on an ERROR (as defined in Status) + * 0b0..Will not interrupt on Error. + * 0b1..Will interrupt on Error (until cleared). + */ +#define HASHCRYPT_INTENSET_ERROR(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENSET_ERROR_SHIFT)) & HASHCRYPT_INTENSET_ERROR_MASK) +/*! @} */ + +/*! @name INTENCLR - Write 1 to clear interrupts. */ +/*! @{ */ +#define HASHCRYPT_INTENCLR_WAITING_MASK (0x1U) +#define HASHCRYPT_INTENCLR_WAITING_SHIFT (0U) +#define HASHCRYPT_INTENCLR_WAITING(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENCLR_WAITING_SHIFT)) & HASHCRYPT_INTENCLR_WAITING_MASK) +#define HASHCRYPT_INTENCLR_DIGEST_MASK (0x2U) +#define HASHCRYPT_INTENCLR_DIGEST_SHIFT (1U) +#define HASHCRYPT_INTENCLR_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENCLR_DIGEST_SHIFT)) & HASHCRYPT_INTENCLR_DIGEST_MASK) +#define HASHCRYPT_INTENCLR_ERROR_MASK (0x4U) +#define HASHCRYPT_INTENCLR_ERROR_SHIFT (2U) +#define HASHCRYPT_INTENCLR_ERROR(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENCLR_ERROR_SHIFT)) & HASHCRYPT_INTENCLR_ERROR_MASK) +/*! @} */ + +/*! @name MEMCTRL - Setup Master to access memory (if available) */ +/*! @{ */ +#define HASHCRYPT_MEMCTRL_MASTER_MASK (0x1U) +#define HASHCRYPT_MEMCTRL_MASTER_SHIFT (0U) +/*! MASTER + * 0b0..Mastering is not used and the normal DMA or Interrupt based model is used with INDATA. + * 0b1..Mastering is enabled and DMA and INDATA should not be used. + */ +#define HASHCRYPT_MEMCTRL_MASTER(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_MEMCTRL_MASTER_SHIFT)) & HASHCRYPT_MEMCTRL_MASTER_MASK) +#define HASHCRYPT_MEMCTRL_COUNT_MASK (0x7FF0000U) +#define HASHCRYPT_MEMCTRL_COUNT_SHIFT (16U) +#define HASHCRYPT_MEMCTRL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_MEMCTRL_COUNT_SHIFT)) & HASHCRYPT_MEMCTRL_COUNT_MASK) +/*! @} */ + +/*! @name MEMADDR - Address to start memory access from (if available). */ +/*! @{ */ +#define HASHCRYPT_MEMADDR_BASE_MASK (0xFFFFFFFFU) +#define HASHCRYPT_MEMADDR_BASE_SHIFT (0U) +#define HASHCRYPT_MEMADDR_BASE(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_MEMADDR_BASE_SHIFT)) & HASHCRYPT_MEMADDR_BASE_MASK) +/*! @} */ + +/*! @name INDATA - Input of 16 words at a time to load up buffer. */ +/*! @{ */ +#define HASHCRYPT_INDATA_DATA_MASK (0xFFFFFFFFU) +#define HASHCRYPT_INDATA_DATA_SHIFT (0U) +#define HASHCRYPT_INDATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INDATA_DATA_SHIFT)) & HASHCRYPT_INDATA_DATA_MASK) +/*! @} */ + +/*! @name ALIAS - */ +/*! @{ */ +#define HASHCRYPT_ALIAS_DATA_MASK (0xFFFFFFFFU) +#define HASHCRYPT_ALIAS_DATA_SHIFT (0U) +#define HASHCRYPT_ALIAS_DATA(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_ALIAS_DATA_SHIFT)) & HASHCRYPT_ALIAS_DATA_MASK) +/*! @} */ + +/* The count of HASHCRYPT_ALIAS */ +#define HASHCRYPT_ALIAS_COUNT (7U) + +/*! @name OUTDATA0 - */ +/*! @{ */ +#define HASHCRYPT_OUTDATA0_DIGEST_OUTPUT_MASK (0xFFFFFFFFU) +#define HASHCRYPT_OUTDATA0_DIGEST_OUTPUT_SHIFT (0U) +#define HASHCRYPT_OUTDATA0_DIGEST_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_OUTDATA0_DIGEST_OUTPUT_SHIFT)) & HASHCRYPT_OUTDATA0_DIGEST_OUTPUT_MASK) +/*! @} */ + +/* The count of HASHCRYPT_OUTDATA0 */ +#define HASHCRYPT_OUTDATA0_COUNT (8U) + +/*! @name OUTDATA1 - */ +/*! @{ */ +#define HASHCRYPT_OUTDATA1_OUTPUT_MASK (0xFFFFFFFFU) +#define HASHCRYPT_OUTDATA1_OUTPUT_SHIFT (0U) +#define HASHCRYPT_OUTDATA1_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_OUTDATA1_OUTPUT_SHIFT)) & HASHCRYPT_OUTDATA1_OUTPUT_MASK) +/*! @} */ + +/* The count of HASHCRYPT_OUTDATA1 */ +#define HASHCRYPT_OUTDATA1_COUNT (8U) + +/*! @name CRYPTCFG - Crypto settings for AES and Salsa and ChaCha */ +/*! @{ */ +#define HASHCRYPT_CRYPTCFG_MSW1ST_OUT_MASK (0x1U) +#define HASHCRYPT_CRYPTCFG_MSW1ST_OUT_SHIFT (0U) +#define HASHCRYPT_CRYPTCFG_MSW1ST_OUT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_MSW1ST_OUT_SHIFT)) & HASHCRYPT_CRYPTCFG_MSW1ST_OUT_MASK) +#define HASHCRYPT_CRYPTCFG_SWAPKEY_MASK (0x2U) +#define HASHCRYPT_CRYPTCFG_SWAPKEY_SHIFT (1U) +#define HASHCRYPT_CRYPTCFG_SWAPKEY(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_SWAPKEY_SHIFT)) & HASHCRYPT_CRYPTCFG_SWAPKEY_MASK) +#define HASHCRYPT_CRYPTCFG_SWAPDAT_MASK (0x4U) +#define HASHCRYPT_CRYPTCFG_SWAPDAT_SHIFT (2U) +#define HASHCRYPT_CRYPTCFG_SWAPDAT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_SWAPDAT_SHIFT)) & HASHCRYPT_CRYPTCFG_SWAPDAT_MASK) +#define HASHCRYPT_CRYPTCFG_MSW1ST_MASK (0x8U) +#define HASHCRYPT_CRYPTCFG_MSW1ST_SHIFT (3U) +#define HASHCRYPT_CRYPTCFG_MSW1ST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_MSW1ST_SHIFT)) & HASHCRYPT_CRYPTCFG_MSW1ST_MASK) +#define HASHCRYPT_CRYPTCFG_AESMODE_MASK (0x30U) +#define HASHCRYPT_CRYPTCFG_AESMODE_SHIFT (4U) +/*! AESMODE - AES Cipher mode to use if plain AES + * 0b00..ECB - used as is + * 0b01..CBC mode (see details on IV/nonce) + * 0b10..CTR mode (see details on IV/nonce). See also AESCTRPOS. + * 0b11..reserved + */ +#define HASHCRYPT_CRYPTCFG_AESMODE(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESMODE_SHIFT)) & HASHCRYPT_CRYPTCFG_AESMODE_MASK) +#define HASHCRYPT_CRYPTCFG_AESDECRYPT_MASK (0x40U) +#define HASHCRYPT_CRYPTCFG_AESDECRYPT_SHIFT (6U) +/*! AESDECRYPT - AES ECB direction. Only encryption used if CTR mode or manual modes such as CFB + * 0b0..Encrypt + * 0b1..Decrypt + */ +#define HASHCRYPT_CRYPTCFG_AESDECRYPT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESDECRYPT_SHIFT)) & HASHCRYPT_CRYPTCFG_AESDECRYPT_MASK) +#define HASHCRYPT_CRYPTCFG_AESSECRET_MASK (0x80U) +#define HASHCRYPT_CRYPTCFG_AESSECRET_SHIFT (7U) +/*! AESSECRET - Selects the Hidden Secret key vs. User key, if provided. If security levels are + * used, only the highest level is permitted to select this. + * 0b0..User key provided in normal way + * 0b1..Secret key provided in hidden way by HW + */ +#define HASHCRYPT_CRYPTCFG_AESSECRET(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESSECRET_SHIFT)) & HASHCRYPT_CRYPTCFG_AESSECRET_MASK) +#define HASHCRYPT_CRYPTCFG_AESKEYSZ_MASK (0x300U) +#define HASHCRYPT_CRYPTCFG_AESKEYSZ_SHIFT (8U) +/*! AESKEYSZ - Sets the AES key size + * 0b00..128 bit key + * 0b01..192 bit key + * 0b10..256 bit key + * 0b11..reserved + */ +#define HASHCRYPT_CRYPTCFG_AESKEYSZ(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESKEYSZ_SHIFT)) & HASHCRYPT_CRYPTCFG_AESKEYSZ_MASK) +#define HASHCRYPT_CRYPTCFG_AESCTRPOS_MASK (0x1C00U) +#define HASHCRYPT_CRYPTCFG_AESCTRPOS_SHIFT (10U) +#define HASHCRYPT_CRYPTCFG_AESCTRPOS(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESCTRPOS_SHIFT)) & HASHCRYPT_CRYPTCFG_AESCTRPOS_MASK) +#define HASHCRYPT_CRYPTCFG_STREAMLAST_MASK (0x10000U) +#define HASHCRYPT_CRYPTCFG_STREAMLAST_SHIFT (16U) +#define HASHCRYPT_CRYPTCFG_STREAMLAST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_STREAMLAST_SHIFT)) & HASHCRYPT_CRYPTCFG_STREAMLAST_MASK) +#define HASHCRYPT_CRYPTCFG_XSALSA_MASK (0x20000U) +#define HASHCRYPT_CRYPTCFG_XSALSA_SHIFT (17U) +#define HASHCRYPT_CRYPTCFG_XSALSA(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_XSALSA_SHIFT)) & HASHCRYPT_CRYPTCFG_XSALSA_MASK) +#define HASHCRYPT_CRYPTCFG_ICBSZ_MASK (0x300000U) +#define HASHCRYPT_CRYPTCFG_ICBSZ_SHIFT (20U) +/*! ICBSZ - This sets the ICB size between 32 and 128 bits, using the following rules. Note that the + * counter is assumed to occupy the low order bits of the IV. + * 0b00..32 bits of the IV/ctr are used (from 127:96) + * 0b01..64 bits of the IV/ctr are used (from 127:64) + * 0b10..96 bits of the IV/ctr are used (from 127:32) + * 0b11..All 128 bits of the IV/ctr are used + */ +#define HASHCRYPT_CRYPTCFG_ICBSZ(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_ICBSZ_SHIFT)) & HASHCRYPT_CRYPTCFG_ICBSZ_MASK) +#define HASHCRYPT_CRYPTCFG_ICBSTRM_MASK (0xC00000U) +#define HASHCRYPT_CRYPTCFG_ICBSTRM_SHIFT (22U) +/*! ICBSTRM - The size of the ICB-AES stream that can be pushed before needing to compute a new + * IV/ctr (counter start). This optimizes the performance of the stream of blocks after the 1st. + * 0b00..8 blocks + * 0b01..16 blocks + * 0b10..32 blocks + * 0b11..64 blocks + */ +#define HASHCRYPT_CRYPTCFG_ICBSTRM(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_ICBSTRM_SHIFT)) & HASHCRYPT_CRYPTCFG_ICBSTRM_MASK) +/*! @} */ + +/*! @name CONFIG - Returns the configuration of this block in this chip - indicates what services are available. */ +/*! @{ */ +#define HASHCRYPT_CONFIG_DUAL_MASK (0x1U) +#define HASHCRYPT_CONFIG_DUAL_SHIFT (0U) +#define HASHCRYPT_CONFIG_DUAL(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_DUAL_SHIFT)) & HASHCRYPT_CONFIG_DUAL_MASK) +#define HASHCRYPT_CONFIG_DMA_MASK (0x2U) +#define HASHCRYPT_CONFIG_DMA_SHIFT (1U) +#define HASHCRYPT_CONFIG_DMA(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_DMA_SHIFT)) & HASHCRYPT_CONFIG_DMA_MASK) +#define HASHCRYPT_CONFIG_AHB_MASK (0x8U) +#define HASHCRYPT_CONFIG_AHB_SHIFT (3U) +#define HASHCRYPT_CONFIG_AHB(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_AHB_SHIFT)) & HASHCRYPT_CONFIG_AHB_MASK) +#define HASHCRYPT_CONFIG_SHA512_MASK (0x20U) +#define HASHCRYPT_CONFIG_SHA512_SHIFT (5U) +#define HASHCRYPT_CONFIG_SHA512(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_SHA512_SHIFT)) & HASHCRYPT_CONFIG_SHA512_MASK) +#define HASHCRYPT_CONFIG_AES_MASK (0x40U) +#define HASHCRYPT_CONFIG_AES_SHIFT (6U) +#define HASHCRYPT_CONFIG_AES(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_AES_SHIFT)) & HASHCRYPT_CONFIG_AES_MASK) +#define HASHCRYPT_CONFIG_AESKEY_MASK (0x80U) +#define HASHCRYPT_CONFIG_AESKEY_SHIFT (7U) +#define HASHCRYPT_CONFIG_AESKEY(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_AESKEY_SHIFT)) & HASHCRYPT_CONFIG_AESKEY_MASK) +#define HASHCRYPT_CONFIG_SECRET_MASK (0x100U) +#define HASHCRYPT_CONFIG_SECRET_SHIFT (8U) +#define HASHCRYPT_CONFIG_SECRET(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_SECRET_SHIFT)) & HASHCRYPT_CONFIG_SECRET_MASK) +#define HASHCRYPT_CONFIG_SALSA_MASK (0x200U) +#define HASHCRYPT_CONFIG_SALSA_SHIFT (9U) +#define HASHCRYPT_CONFIG_SALSA(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_SALSA_SHIFT)) & HASHCRYPT_CONFIG_SALSA_MASK) +#define HASHCRYPT_CONFIG_CHACHA_MASK (0x400U) +#define HASHCRYPT_CONFIG_CHACHA_SHIFT (10U) +#define HASHCRYPT_CONFIG_CHACHA(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_CHACHA_SHIFT)) & HASHCRYPT_CONFIG_CHACHA_MASK) +#define HASHCRYPT_CONFIG_ICB_MASK (0x800U) +#define HASHCRYPT_CONFIG_ICB_SHIFT (11U) +#define HASHCRYPT_CONFIG_ICB(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_ICB_SHIFT)) & HASHCRYPT_CONFIG_ICB_MASK) +/*! @} */ + +/*! @name LOCK - Lock register allows locking to the current security level or unlocking by the lock holding level. */ +/*! @{ */ +#define HASHCRYPT_LOCK_SECLOCK_MASK (0x3U) +#define HASHCRYPT_LOCK_SECLOCK_SHIFT (0U) +/*! SECLOCK - Write 1 to secure-lock this block (if running in a security state). Write 0 to unlock. + * If locked already, may only write if at same or higher security level as lock. Reads as: 0 if + * unlocked, else 1, 2, 3 to indicate security level it is locked at. NOTE: this and ID are the + * only readable registers if locked and current state is lower than lock level. + * 0b00..Unlocks, so block is open to all. But, AHB Master will only issue non-secure requests. + * 0b01..Locks to the current security level. AHB Master will issue requests at this level. + */ +#define HASHCRYPT_LOCK_SECLOCK(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_LOCK_SECLOCK_SHIFT)) & HASHCRYPT_LOCK_SECLOCK_MASK) +#define HASHCRYPT_LOCK_PATTERN_MASK (0xFFF0U) +#define HASHCRYPT_LOCK_PATTERN_SHIFT (4U) +#define HASHCRYPT_LOCK_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_LOCK_PATTERN_SHIFT)) & HASHCRYPT_LOCK_PATTERN_MASK) +/*! @} */ + +/*! @name MASK - */ +/*! @{ */ +#define HASHCRYPT_MASK_MASK_MASK (0xFFFFFFFFU) +#define HASHCRYPT_MASK_MASK_SHIFT (0U) +#define HASHCRYPT_MASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_MASK_MASK_SHIFT)) & HASHCRYPT_MASK_MASK_MASK) +/*! @} */ + +/* The count of HASHCRYPT_MASK */ +#define HASHCRYPT_MASK_COUNT (4U) + + +/*! + * @} + */ /* end of group HASHCRYPT_Register_Masks */ + + +/* HASHCRYPT - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral HASHCRYPT base address */ + #define HASHCRYPT_BASE (0x500A4000u) + /** Peripheral HASHCRYPT base address */ + #define HASHCRYPT_BASE_NS (0x400A4000u) + /** Peripheral HASHCRYPT base pointer */ + #define HASHCRYPT ((HASHCRYPT_Type *)HASHCRYPT_BASE) + /** Peripheral HASHCRYPT base pointer */ + #define HASHCRYPT_NS ((HASHCRYPT_Type *)HASHCRYPT_BASE_NS) + /** Array initializer of HASHCRYPT peripheral base addresses */ + #define HASHCRYPT_BASE_ADDRS { HASHCRYPT_BASE } + /** Array initializer of HASHCRYPT peripheral base pointers */ + #define HASHCRYPT_BASE_PTRS { HASHCRYPT } + /** Array initializer of HASHCRYPT peripheral base addresses */ + #define HASHCRYPT_BASE_ADDRS_NS { HASHCRYPT_BASE_NS } + /** Array initializer of HASHCRYPT peripheral base pointers */ + #define HASHCRYPT_BASE_PTRS_NS { HASHCRYPT_NS } +#else + /** Peripheral HASHCRYPT base address */ + #define HASHCRYPT_BASE (0x400A4000u) + /** Peripheral HASHCRYPT base pointer */ + #define HASHCRYPT ((HASHCRYPT_Type *)HASHCRYPT_BASE) + /** Array initializer of HASHCRYPT peripheral base addresses */ + #define HASHCRYPT_BASE_ADDRS { HASHCRYPT_BASE } + /** Array initializer of HASHCRYPT peripheral base pointers */ + #define HASHCRYPT_BASE_PTRS { HASHCRYPT } +#endif + +/*! + * @} + */ /* end of group HASHCRYPT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- I2C Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer + * @{ + */ + +/** I2C - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[2048]; + __IO uint32_t CFG; /**< Configuration for shared functions., offset: 0x800 */ + __IO uint32_t STAT; /**< Status register for Master, Slave, and Monitor functions., offset: 0x804 */ + __IO uint32_t INTENSET; /**< Interrupt Enable Set and read register., offset: 0x808 */ + __O uint32_t INTENCLR; /**< Interrupt Enable Clear register., offset: 0x80C */ + __IO uint32_t TIMEOUT; /**< Time-out value register., offset: 0x810 */ + __IO uint32_t CLKDIV; /**< Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function., offset: 0x814 */ + __I uint32_t INTSTAT; /**< Interrupt Status register for Master, Slave, and Monitor functions., offset: 0x818 */ + uint8_t RESERVED_1[4]; + __IO uint32_t MSTCTL; /**< Master control register., offset: 0x820 */ + __IO uint32_t MSTTIME; /**< Master timing configuration., offset: 0x824 */ + __IO uint32_t MSTDAT; /**< Combined Master receiver and transmitter data register., offset: 0x828 */ + uint8_t RESERVED_2[20]; + __IO uint32_t SLVCTL; /**< Slave control register., offset: 0x840 */ + __IO uint32_t SLVDAT; /**< Combined Slave receiver and transmitter data register., offset: 0x844 */ + __IO uint32_t SLVADR[4]; /**< Slave address register., array offset: 0x848, array step: 0x4 */ + __IO uint32_t SLVQUAL0; /**< Slave Qualification for address 0., offset: 0x858 */ + uint8_t RESERVED_3[36]; + __I uint32_t MONRXDAT; /**< Monitor receiver data register., offset: 0x880 */ + uint8_t RESERVED_4[1912]; + __I uint32_t ID; /**< Peripheral identification register., offset: 0xFFC */ +} I2C_Type; + +/* ---------------------------------------------------------------------------- + -- I2C Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2C_Register_Masks I2C Register Masks + * @{ + */ + +/*! @name CFG - Configuration for shared functions. */ +/*! @{ */ +#define I2C_CFG_MSTEN_MASK (0x1U) +#define I2C_CFG_MSTEN_SHIFT (0U) +/*! MSTEN - Master Enable. When disabled, configurations settings for the Master function are not + * changed, but the Master function is internally reset. + * 0b0..Disabled. The I2C Master function is disabled. + * 0b1..Enabled. The I2C Master function is enabled. + */ +#define I2C_CFG_MSTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MSTEN_SHIFT)) & I2C_CFG_MSTEN_MASK) +#define I2C_CFG_SLVEN_MASK (0x2U) +#define I2C_CFG_SLVEN_SHIFT (1U) +/*! SLVEN - Slave Enable. When disabled, configurations settings for the Slave function are not + * changed, but the Slave function is internally reset. + * 0b0..Disabled. The I2C slave function is disabled. + * 0b1..Enabled. The I2C slave function is enabled. + */ +#define I2C_CFG_SLVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_SLVEN_SHIFT)) & I2C_CFG_SLVEN_MASK) +#define I2C_CFG_MONEN_MASK (0x4U) +#define I2C_CFG_MONEN_SHIFT (2U) +/*! MONEN - Monitor Enable. When disabled, configurations settings for the Monitor function are not + * changed, but the Monitor function is internally reset. + * 0b0..Disabled. The I2C Monitor function is disabled. + * 0b1..Enabled. The I2C Monitor function is enabled. + */ +#define I2C_CFG_MONEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONEN_SHIFT)) & I2C_CFG_MONEN_MASK) +#define I2C_CFG_TIMEOUTEN_MASK (0x8U) +#define I2C_CFG_TIMEOUTEN_SHIFT (3U) +/*! TIMEOUTEN - I2C bus Time-out Enable. When disabled, the time-out function is internally reset. + * 0b0..Disabled. Time-out function is disabled. + * 0b1..Enabled. Time-out function is enabled. Both types of time-out flags will be generated and will cause + * interrupts if they are enabled. Typically, only one time-out will be used in a system. + */ +#define I2C_CFG_TIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_TIMEOUTEN_SHIFT)) & I2C_CFG_TIMEOUTEN_MASK) +#define I2C_CFG_MONCLKSTR_MASK (0x10U) +#define I2C_CFG_MONCLKSTR_SHIFT (4U) +/*! MONCLKSTR - Monitor function Clock Stretching. + * 0b0..Disabled. The Monitor function will not perform clock stretching. Software or DMA may not always be able + * to read data provided by the Monitor function before it is overwritten. This mode may be used when + * non-invasive monitoring is critical. + * 0b1..Enabled. The Monitor function will perform clock stretching in order to ensure that software or DMA can + * read all incoming data supplied by the Monitor function. + */ +#define I2C_CFG_MONCLKSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONCLKSTR_SHIFT)) & I2C_CFG_MONCLKSTR_MASK) +#define I2C_CFG_HSCAPABLE_MASK (0x20U) +#define I2C_CFG_HSCAPABLE_SHIFT (5U) +/*! HSCAPABLE - High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive + * and filter, as well as the timing for certain I2C signalling, enabling High-speed mode applies + * to all functions: Master, Slave, and Monitor. + * 0b0..Fast-mode plus. The I 2C interface will support Standard-mode, Fast-mode, and Fast-mode Plus, to the + * extent that the pin electronics support these modes. Any changes that need to be made to the pin controls, + * such as changing the drive strength or filtering, must be made by software via the IOCON register associated + * with each I2C pin, + * 0b1..High-speed. In addition to Standard-mode, Fast-mode, and Fast-mode Plus, the I 2C interface will support + * High-speed mode to the extent that the pin electronics support these modes. See Section 25.7.2.2 for more + * information. + */ +#define I2C_CFG_HSCAPABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_HSCAPABLE_SHIFT)) & I2C_CFG_HSCAPABLE_MASK) +/*! @} */ + +/*! @name STAT - Status register for Master, Slave, and Monitor functions. */ +/*! @{ */ +#define I2C_STAT_MSTPENDING_MASK (0x1U) +#define I2C_STAT_MSTPENDING_SHIFT (0U) +/*! MSTPENDING - Master Pending. Indicates that the Master is waiting to continue communication on + * the I2C-bus (pending) or is idle. When the master is pending, the MSTSTATE bits indicate what + * type of software service if any the master expects. This flag will cause an interrupt when set + * if, enabled via the INTENSET register. The MSTPENDING flag is not set when the DMA is handling + * an event (if the MSTDMA bit in the MSTCTL register is set). If the master is in the idle + * state, and no communication is needed, mask this interrupt. + * 0b0..In progress. Communication is in progress and the Master function is busy and cannot currently accept a command. + * 0b1..Pending. The Master function needs software service or is in the idle state. If the master is not in the + * idle state, it is waiting to receive or transmit data or the NACK bit. + */ +#define I2C_STAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTPENDING_SHIFT)) & I2C_STAT_MSTPENDING_MASK) +#define I2C_STAT_MSTSTATE_MASK (0xEU) +#define I2C_STAT_MSTSTATE_SHIFT (1U) +/*! MSTSTATE - Master State code. The master state code reflects the master state when the + * MSTPENDING bit is set, that is the master is pending or in the idle state. Each value of this field + * indicates a specific required service for the Master function. All other values are reserved. See + * Table 400 for details of state values and appropriate responses. + * 0b000..Idle. The Master function is available to be used for a new transaction. + * 0b001..Receive ready. Received data available (Master Receiver mode). Address plus Read was previously sent and Acknowledged by slave. + * 0b010..Transmit ready. Data can be transmitted (Master Transmitter mode). Address plus Write was previously sent and Acknowledged by slave. + * 0b011..NACK Address. Slave NACKed address. + * 0b100..NACK Data. Slave NACKed transmitted data. + */ +#define I2C_STAT_MSTSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTATE_SHIFT)) & I2C_STAT_MSTSTATE_MASK) +#define I2C_STAT_MSTARBLOSS_MASK (0x10U) +#define I2C_STAT_MSTARBLOSS_SHIFT (4U) +/*! MSTARBLOSS - Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to + * this bit. It is also cleared automatically a 1 is written to MSTCONTINUE. + * 0b0..No Arbitration Loss has occurred. + * 0b1..Arbitration loss. The Master function has experienced an Arbitration Loss. At this point, the Master + * function has already stopped driving the bus and gone to an idle state. Software can respond by doing nothing, + * or by sending a Start in order to attempt to gain control of the bus when it next becomes idle. + */ +#define I2C_STAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTARBLOSS_SHIFT)) & I2C_STAT_MSTARBLOSS_MASK) +#define I2C_STAT_MSTSTSTPERR_MASK (0x40U) +#define I2C_STAT_MSTSTSTPERR_SHIFT (6U) +/*! MSTSTSTPERR - Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to + * this bit. It is also cleared automatically a 1 is written to MSTCONTINUE. + * 0b0..No Start/Stop Error has occurred. + * 0b1..The Master function has experienced a Start/Stop Error. A Start or Stop was detected at a time when it is + * not allowed by the I2C specification. The Master interface has stopped driving the bus and gone to an + * idle state, no action is required. A request for a Start could be made, or software could attempt to insure + * that the bus has not stalled. + */ +#define I2C_STAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTSTPERR_SHIFT)) & I2C_STAT_MSTSTSTPERR_MASK) +#define I2C_STAT_SLVPENDING_MASK (0x100U) +#define I2C_STAT_SLVPENDING_SHIFT (8U) +/*! SLVPENDING - Slave Pending. Indicates that the Slave function is waiting to continue + * communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if + * enabled via INTENSET. The SLVPENDING flag is not set when the DMA is handling an event (if the + * SLVDMA bit in the SLVCTL register is set). The SLVPENDING flag is read-only and is + * automatically cleared when a 1 is written to the SLVCONTINUE bit in the SLVCTL register. The point in time + * when SlvPending is set depends on whether the I2C interface is in HSCAPABLE mode. See Section + * 25.7.2.2.2. When the I2C interface is configured to be HSCAPABLE, HS master codes are + * detected automatically. Due to the requirements of the HS I2C specification, slave addresses must + * also be detected automatically, since the address must be acknowledged before the clock can be + * stretched. + * 0b0..In progress. The Slave function does not currently need service. + * 0b1..Pending. The Slave function needs service. Information on what is needed can be found in the adjacent SLVSTATE field. + */ +#define I2C_STAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVPENDING_SHIFT)) & I2C_STAT_SLVPENDING_MASK) +#define I2C_STAT_SLVSTATE_MASK (0x600U) +#define I2C_STAT_SLVSTATE_SHIFT (9U) +/*! SLVSTATE - Slave State code. Each value of this field indicates a specific required service for + * the Slave function. All other values are reserved. See Table 401 for state values and actions. + * note that the occurrence of some states and how they are handled are affected by DMA mode and + * Automatic Operation modes. + * 0b00..Slave address. Address plus R/W received. At least one of the four slave addresses has been matched by hardware. + * 0b01..Slave receive. Received data is available (Slave Receiver mode). + * 0b10..Slave transmit. Data can be transmitted (Slave Transmitter mode). + */ +#define I2C_STAT_SLVSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSTATE_SHIFT)) & I2C_STAT_SLVSTATE_MASK) +#define I2C_STAT_SLVNOTSTR_MASK (0x800U) +#define I2C_STAT_SLVNOTSTR_SHIFT (11U) +/*! SLVNOTSTR - Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. + * This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave + * operation. This read-only flag reflects the slave function status in real time. + * 0b0..Stretching. The slave function is currently stretching the I2C bus clock. Deep-Sleep or Power-down mode cannot be entered at this time. + * 0b1..Not stretching. The slave function is not currently stretching the I 2C bus clock. Deep-sleep or + * Power-down mode could be entered at this time. + */ +#define I2C_STAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVNOTSTR_SHIFT)) & I2C_STAT_SLVNOTSTR_MASK) +#define I2C_STAT_SLVIDX_MASK (0x3000U) +#define I2C_STAT_SLVIDX_SHIFT (12U) +/*! SLVIDX - Slave address match Index. This field is valid when the I2C slave function has been + * selected by receiving an address that matches one of the slave addresses defined by any enabled + * slave address registers, and provides an identification of the address that was matched. It is + * possible that more than one address could be matched, but only one match can be reported here. + * 0b00..Address 0. Slave address 0 was matched. + * 0b01..Address 1. Slave address 1 was matched. + * 0b10..Address 2. Slave address 2 was matched. + * 0b11..Address 3. Slave address 3 was matched. + */ +#define I2C_STAT_SLVIDX(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVIDX_SHIFT)) & I2C_STAT_SLVIDX_MASK) +#define I2C_STAT_SLVSEL_MASK (0x4000U) +#define I2C_STAT_SLVSEL_SHIFT (14U) +/*! SLVSEL - Slave selected flag. SLVSEL is set after an address match when software tells the Slave + * function to acknowledge the address, or when the address has been automatically acknowledged. + * It is cleared when another address cycle presents an address that does not match an enabled + * address on the Slave function, when slave software decides to NACK a matched address, when + * there is a Stop detected on the bus, when the master NACKs slave data, and in some combinations of + * Automatic Operation. SLVSEL is not cleared if software NACKs data. + * 0b0..Not selected. The Slave function is not currently selected. + * 0b1..Selected. The Slave function is currently selected. + */ +#define I2C_STAT_SLVSEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSEL_SHIFT)) & I2C_STAT_SLVSEL_MASK) +#define I2C_STAT_SLVDESEL_MASK (0x8000U) +#define I2C_STAT_SLVDESEL_SHIFT (15U) +/*! SLVDESEL - Slave Deselected flag. This flag will cause an interrupt when set if enabled via + * INTENSET. This flag can be cleared by writing a 1 to this bit. + * 0b0..Not deselected. The Slave function has not become deselected. This does not mean that it is currently + * selected. That information can be found in the SLVSEL flag. + * 0b1..Deselected. The Slave function has become deselected. This is specifically caused by the SLVSEL flag + * changing from 1 to 0. See the description of SLVSEL for details on when that event occurs. + */ +#define I2C_STAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVDESEL_SHIFT)) & I2C_STAT_SLVDESEL_MASK) +#define I2C_STAT_MONRDY_MASK (0x10000U) +#define I2C_STAT_MONRDY_SHIFT (16U) +/*! MONRDY - Monitor Ready. This flag is cleared when the MONRXDAT register is read. + * 0b0..No data. The Monitor function does not currently have data available. + * 0b1..Data waiting. The Monitor function has data waiting to be read. + */ +#define I2C_STAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONRDY_SHIFT)) & I2C_STAT_MONRDY_MASK) +#define I2C_STAT_MONOV_MASK (0x20000U) +#define I2C_STAT_MONOV_SHIFT (17U) +/*! MONOV - Monitor Overflow flag. + * 0b0..No overrun. Monitor data has not overrun. + * 0b1..Overrun. A Monitor data overrun has occurred. This can only happen when Monitor clock stretching not + * enabled via the MONCLKSTR bit in the CFG register. Writing 1 to this bit clears the flag. + */ +#define I2C_STAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONOV_SHIFT)) & I2C_STAT_MONOV_MASK) +#define I2C_STAT_MONACTIVE_MASK (0x40000U) +#define I2C_STAT_MONACTIVE_SHIFT (18U) +/*! MONACTIVE - Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to + * be active. Active is defined here as when some Master is on the bus: a bus Start has occurred + * more recently than a bus Stop. + * 0b0..Inactive. The Monitor function considers the I2C bus to be inactive. + * 0b1..Active. The Monitor function considers the I2C bus to be active. + */ +#define I2C_STAT_MONACTIVE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONACTIVE_SHIFT)) & I2C_STAT_MONACTIVE_MASK) +#define I2C_STAT_MONIDLE_MASK (0x80000U) +#define I2C_STAT_MONIDLE_SHIFT (19U) +/*! MONIDLE - Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change + * from active to inactive. This can be used by software to decide when to process data + * accumulated by the Monitor function. This flag will cause an interrupt when set if enabled via the + * INTENSET register. The flag can be cleared by writing a 1 to this bit. + * 0b0..Not idle. The I2C bus is not idle, or this flag has been cleared by software. + * 0b1..Idle. The I2C bus has gone idle at least once since the last time this flag was cleared by software. + */ +#define I2C_STAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONIDLE_SHIFT)) & I2C_STAT_MONIDLE_MASK) +#define I2C_STAT_EVENTTIMEOUT_MASK (0x1000000U) +#define I2C_STAT_EVENTTIMEOUT_SHIFT (24U) +/*! EVENTTIMEOUT - Event Time-out Interrupt flag. Indicates when the time between events has been + * longer than the time specified by the TIMEOUT register. Events include Start, Stop, and clock + * edges. The flag is cleared by writing a 1 to this bit. No time-out is created when the I2C-bus + * is idle. + * 0b0..No time-out. I2C bus events have not caused a time-out. + * 0b1..Event time-out. The time between I2C bus events has been longer than the time specified by the TIMEOUT register. + */ +#define I2C_STAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_EVENTTIMEOUT_SHIFT)) & I2C_STAT_EVENTTIMEOUT_MASK) +#define I2C_STAT_SCLTIMEOUT_MASK (0x2000000U) +#define I2C_STAT_SCLTIMEOUT_SHIFT (25U) +/*! SCLTIMEOUT - SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the + * time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit. + * 0b0..No time-out. SCL low time has not caused a time-out. + * 0b1..Time-out. SCL low time has caused a time-out. + */ +#define I2C_STAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SCLTIMEOUT_SHIFT)) & I2C_STAT_SCLTIMEOUT_MASK) +/*! @} */ + +/*! @name INTENSET - Interrupt Enable Set and read register. */ +/*! @{ */ +#define I2C_INTENSET_MSTPENDINGEN_MASK (0x1U) +#define I2C_INTENSET_MSTPENDINGEN_SHIFT (0U) +/*! MSTPENDINGEN - Master Pending interrupt Enable. + * 0b0..Disabled. The MstPending interrupt is disabled. + * 0b1..Enabled. The MstPending interrupt is enabled. + */ +#define I2C_INTENSET_MSTPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTPENDINGEN_SHIFT)) & I2C_INTENSET_MSTPENDINGEN_MASK) +#define I2C_INTENSET_MSTARBLOSSEN_MASK (0x10U) +#define I2C_INTENSET_MSTARBLOSSEN_SHIFT (4U) +/*! MSTARBLOSSEN - Master Arbitration Loss interrupt Enable. + * 0b0..Disabled. The MstArbLoss interrupt is disabled. + * 0b1..Enabled. The MstArbLoss interrupt is enabled. + */ +#define I2C_INTENSET_MSTARBLOSSEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTARBLOSSEN_SHIFT)) & I2C_INTENSET_MSTARBLOSSEN_MASK) +#define I2C_INTENSET_MSTSTSTPERREN_MASK (0x40U) +#define I2C_INTENSET_MSTSTSTPERREN_SHIFT (6U) +/*! MSTSTSTPERREN - Master Start/Stop Error interrupt Enable. + * 0b0..Disabled. The MstStStpErr interrupt is disabled. + * 0b1..Enabled. The MstStStpErr interrupt is enabled. + */ +#define I2C_INTENSET_MSTSTSTPERREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTSTSTPERREN_SHIFT)) & I2C_INTENSET_MSTSTSTPERREN_MASK) +#define I2C_INTENSET_SLVPENDINGEN_MASK (0x100U) +#define I2C_INTENSET_SLVPENDINGEN_SHIFT (8U) +/*! SLVPENDINGEN - Slave Pending interrupt Enable. + * 0b0..Disabled. The SlvPending interrupt is disabled. + * 0b1..Enabled. The SlvPending interrupt is enabled. + */ +#define I2C_INTENSET_SLVPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVPENDINGEN_SHIFT)) & I2C_INTENSET_SLVPENDINGEN_MASK) +#define I2C_INTENSET_SLVNOTSTREN_MASK (0x800U) +#define I2C_INTENSET_SLVNOTSTREN_SHIFT (11U) +/*! SLVNOTSTREN - Slave Not Stretching interrupt Enable. + * 0b0..Disabled. The SlvNotStr interrupt is disabled. + * 0b1..Enabled. The SlvNotStr interrupt is enabled. + */ +#define I2C_INTENSET_SLVNOTSTREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVNOTSTREN_SHIFT)) & I2C_INTENSET_SLVNOTSTREN_MASK) +#define I2C_INTENSET_SLVDESELEN_MASK (0x8000U) +#define I2C_INTENSET_SLVDESELEN_SHIFT (15U) +/*! SLVDESELEN - Slave Deselect interrupt Enable. + * 0b0..Disabled. The SlvDeSel interrupt is disabled. + * 0b1..Enabled. The SlvDeSel interrupt is enabled. + */ +#define I2C_INTENSET_SLVDESELEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVDESELEN_SHIFT)) & I2C_INTENSET_SLVDESELEN_MASK) +#define I2C_INTENSET_MONRDYEN_MASK (0x10000U) +#define I2C_INTENSET_MONRDYEN_SHIFT (16U) +/*! MONRDYEN - Monitor data Ready interrupt Enable. + * 0b0..Disabled. The MonRdy interrupt is disabled. + * 0b1..Enabled. The MonRdy interrupt is enabled. + */ +#define I2C_INTENSET_MONRDYEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONRDYEN_SHIFT)) & I2C_INTENSET_MONRDYEN_MASK) +#define I2C_INTENSET_MONOVEN_MASK (0x20000U) +#define I2C_INTENSET_MONOVEN_SHIFT (17U) +/*! MONOVEN - Monitor Overrun interrupt Enable. + * 0b0..Disabled. The MonOv interrupt is disabled. + * 0b1..Enabled. The MonOv interrupt is enabled. + */ +#define I2C_INTENSET_MONOVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONOVEN_SHIFT)) & I2C_INTENSET_MONOVEN_MASK) +#define I2C_INTENSET_MONIDLEEN_MASK (0x80000U) +#define I2C_INTENSET_MONIDLEEN_SHIFT (19U) +/*! MONIDLEEN - Monitor Idle interrupt Enable. + * 0b0..Disabled. The MonIdle interrupt is disabled. + * 0b1..Enabled. The MonIdle interrupt is enabled. + */ +#define I2C_INTENSET_MONIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONIDLEEN_SHIFT)) & I2C_INTENSET_MONIDLEEN_MASK) +#define I2C_INTENSET_EVENTTIMEOUTEN_MASK (0x1000000U) +#define I2C_INTENSET_EVENTTIMEOUTEN_SHIFT (24U) +/*! EVENTTIMEOUTEN - Event time-out interrupt Enable. + * 0b0..Disabled. The Event time-out interrupt is disabled. + * 0b1..Enabled. The Event time-out interrupt is enabled. + */ +#define I2C_INTENSET_EVENTTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_EVENTTIMEOUTEN_SHIFT)) & I2C_INTENSET_EVENTTIMEOUTEN_MASK) +#define I2C_INTENSET_SCLTIMEOUTEN_MASK (0x2000000U) +#define I2C_INTENSET_SCLTIMEOUTEN_SHIFT (25U) +/*! SCLTIMEOUTEN - SCL time-out interrupt Enable. + * 0b0..Disabled. The SCL time-out interrupt is disabled. + * 0b1..Enabled. The SCL time-out interrupt is enabled. + */ +#define I2C_INTENSET_SCLTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SCLTIMEOUTEN_SHIFT)) & I2C_INTENSET_SCLTIMEOUTEN_MASK) +/*! @} */ + +/*! @name INTENCLR - Interrupt Enable Clear register. */ +/*! @{ */ +#define I2C_INTENCLR_MSTPENDINGCLR_MASK (0x1U) +#define I2C_INTENCLR_MSTPENDINGCLR_SHIFT (0U) +#define I2C_INTENCLR_MSTPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTPENDINGCLR_SHIFT)) & I2C_INTENCLR_MSTPENDINGCLR_MASK) +#define I2C_INTENCLR_MSTARBLOSSCLR_MASK (0x10U) +#define I2C_INTENCLR_MSTARBLOSSCLR_SHIFT (4U) +#define I2C_INTENCLR_MSTARBLOSSCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTARBLOSSCLR_SHIFT)) & I2C_INTENCLR_MSTARBLOSSCLR_MASK) +#define I2C_INTENCLR_MSTSTSTPERRCLR_MASK (0x40U) +#define I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT (6U) +#define I2C_INTENCLR_MSTSTSTPERRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT)) & I2C_INTENCLR_MSTSTSTPERRCLR_MASK) +#define I2C_INTENCLR_SLVPENDINGCLR_MASK (0x100U) +#define I2C_INTENCLR_SLVPENDINGCLR_SHIFT (8U) +#define I2C_INTENCLR_SLVPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVPENDINGCLR_SHIFT)) & I2C_INTENCLR_SLVPENDINGCLR_MASK) +#define I2C_INTENCLR_SLVNOTSTRCLR_MASK (0x800U) +#define I2C_INTENCLR_SLVNOTSTRCLR_SHIFT (11U) +#define I2C_INTENCLR_SLVNOTSTRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVNOTSTRCLR_SHIFT)) & I2C_INTENCLR_SLVNOTSTRCLR_MASK) +#define I2C_INTENCLR_SLVDESELCLR_MASK (0x8000U) +#define I2C_INTENCLR_SLVDESELCLR_SHIFT (15U) +#define I2C_INTENCLR_SLVDESELCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVDESELCLR_SHIFT)) & I2C_INTENCLR_SLVDESELCLR_MASK) +#define I2C_INTENCLR_MONRDYCLR_MASK (0x10000U) +#define I2C_INTENCLR_MONRDYCLR_SHIFT (16U) +#define I2C_INTENCLR_MONRDYCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONRDYCLR_SHIFT)) & I2C_INTENCLR_MONRDYCLR_MASK) +#define I2C_INTENCLR_MONOVCLR_MASK (0x20000U) +#define I2C_INTENCLR_MONOVCLR_SHIFT (17U) +#define I2C_INTENCLR_MONOVCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONOVCLR_SHIFT)) & I2C_INTENCLR_MONOVCLR_MASK) +#define I2C_INTENCLR_MONIDLECLR_MASK (0x80000U) +#define I2C_INTENCLR_MONIDLECLR_SHIFT (19U) +#define I2C_INTENCLR_MONIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONIDLECLR_SHIFT)) & I2C_INTENCLR_MONIDLECLR_MASK) +#define I2C_INTENCLR_EVENTTIMEOUTCLR_MASK (0x1000000U) +#define I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT (24U) +#define I2C_INTENCLR_EVENTTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_EVENTTIMEOUTCLR_MASK) +#define I2C_INTENCLR_SCLTIMEOUTCLR_MASK (0x2000000U) +#define I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT (25U) +#define I2C_INTENCLR_SCLTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_SCLTIMEOUTCLR_MASK) +/*! @} */ + +/*! @name TIMEOUT - Time-out value register. */ +/*! @{ */ +#define I2C_TIMEOUT_TOMIN_MASK (0xFU) +#define I2C_TIMEOUT_TOMIN_SHIFT (0U) +#define I2C_TIMEOUT_TOMIN(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TOMIN_SHIFT)) & I2C_TIMEOUT_TOMIN_MASK) +#define I2C_TIMEOUT_TO_MASK (0xFFF0U) +#define I2C_TIMEOUT_TO_SHIFT (4U) +#define I2C_TIMEOUT_TO(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TO_SHIFT)) & I2C_TIMEOUT_TO_MASK) +/*! @} */ + +/*! @name CLKDIV - Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function. */ +/*! @{ */ +#define I2C_CLKDIV_DIVVAL_MASK (0xFFFFU) +#define I2C_CLKDIV_DIVVAL_SHIFT (0U) +#define I2C_CLKDIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << I2C_CLKDIV_DIVVAL_SHIFT)) & I2C_CLKDIV_DIVVAL_MASK) +/*! @} */ + +/*! @name INTSTAT - Interrupt Status register for Master, Slave, and Monitor functions. */ +/*! @{ */ +#define I2C_INTSTAT_MSTPENDING_MASK (0x1U) +#define I2C_INTSTAT_MSTPENDING_SHIFT (0U) +#define I2C_INTSTAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTPENDING_SHIFT)) & I2C_INTSTAT_MSTPENDING_MASK) +#define I2C_INTSTAT_MSTARBLOSS_MASK (0x10U) +#define I2C_INTSTAT_MSTARBLOSS_SHIFT (4U) +#define I2C_INTSTAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTARBLOSS_SHIFT)) & I2C_INTSTAT_MSTARBLOSS_MASK) +#define I2C_INTSTAT_MSTSTSTPERR_MASK (0x40U) +#define I2C_INTSTAT_MSTSTSTPERR_SHIFT (6U) +#define I2C_INTSTAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTSTSTPERR_SHIFT)) & I2C_INTSTAT_MSTSTSTPERR_MASK) +#define I2C_INTSTAT_SLVPENDING_MASK (0x100U) +#define I2C_INTSTAT_SLVPENDING_SHIFT (8U) +#define I2C_INTSTAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVPENDING_SHIFT)) & I2C_INTSTAT_SLVPENDING_MASK) +#define I2C_INTSTAT_SLVNOTSTR_MASK (0x800U) +#define I2C_INTSTAT_SLVNOTSTR_SHIFT (11U) +#define I2C_INTSTAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVNOTSTR_SHIFT)) & I2C_INTSTAT_SLVNOTSTR_MASK) +#define I2C_INTSTAT_SLVDESEL_MASK (0x8000U) +#define I2C_INTSTAT_SLVDESEL_SHIFT (15U) +#define I2C_INTSTAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVDESEL_SHIFT)) & I2C_INTSTAT_SLVDESEL_MASK) +#define I2C_INTSTAT_MONRDY_MASK (0x10000U) +#define I2C_INTSTAT_MONRDY_SHIFT (16U) +#define I2C_INTSTAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONRDY_SHIFT)) & I2C_INTSTAT_MONRDY_MASK) +#define I2C_INTSTAT_MONOV_MASK (0x20000U) +#define I2C_INTSTAT_MONOV_SHIFT (17U) +#define I2C_INTSTAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONOV_SHIFT)) & I2C_INTSTAT_MONOV_MASK) +#define I2C_INTSTAT_MONIDLE_MASK (0x80000U) +#define I2C_INTSTAT_MONIDLE_SHIFT (19U) +#define I2C_INTSTAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONIDLE_SHIFT)) & I2C_INTSTAT_MONIDLE_MASK) +#define I2C_INTSTAT_EVENTTIMEOUT_MASK (0x1000000U) +#define I2C_INTSTAT_EVENTTIMEOUT_SHIFT (24U) +#define I2C_INTSTAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_EVENTTIMEOUT_SHIFT)) & I2C_INTSTAT_EVENTTIMEOUT_MASK) +#define I2C_INTSTAT_SCLTIMEOUT_MASK (0x2000000U) +#define I2C_INTSTAT_SCLTIMEOUT_SHIFT (25U) +#define I2C_INTSTAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SCLTIMEOUT_SHIFT)) & I2C_INTSTAT_SCLTIMEOUT_MASK) +/*! @} */ + +/*! @name MSTCTL - Master control register. */ +/*! @{ */ +#define I2C_MSTCTL_MSTCONTINUE_MASK (0x1U) +#define I2C_MSTCTL_MSTCONTINUE_SHIFT (0U) +/*! MSTCONTINUE - Master Continue. This bit is write-only. + * 0b0..No effect. + * 0b1..Continue. Informs the Master function to continue to the next operation. This must done after writing + * transmit data, reading received data, or any other housekeeping related to the next bus operation. + */ +#define I2C_MSTCTL_MSTCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTCONTINUE_SHIFT)) & I2C_MSTCTL_MSTCONTINUE_MASK) +#define I2C_MSTCTL_MSTSTART_MASK (0x2U) +#define I2C_MSTCTL_MSTSTART_SHIFT (1U) +/*! MSTSTART - Master Start control. This bit is write-only. + * 0b0..No effect. + * 0b1..Start. A Start will be generated on the I2C bus at the next allowed time. + */ +#define I2C_MSTCTL_MSTSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTART_SHIFT)) & I2C_MSTCTL_MSTSTART_MASK) +#define I2C_MSTCTL_MSTSTOP_MASK (0x4U) +#define I2C_MSTCTL_MSTSTOP_SHIFT (2U) +/*! MSTSTOP - Master Stop control. This bit is write-only. + * 0b0..No effect. + * 0b1..Stop. A Stop will be generated on the I2C bus at the next allowed time, preceded by a NACK to the slave + * if the master is receiving data from the slave (Master Receiver mode). + */ +#define I2C_MSTCTL_MSTSTOP(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTOP_SHIFT)) & I2C_MSTCTL_MSTSTOP_MASK) +#define I2C_MSTCTL_MSTDMA_MASK (0x8U) +#define I2C_MSTCTL_MSTDMA_SHIFT (3U) +/*! MSTDMA - Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type + * operations such as Start, address, Stop, and address match must always be done with software, + * typically via an interrupt. Address acknowledgement must also be done by software except when + * the I2C is configured to be HSCAPABLE (and address acknowledgement is handled entirely by + * hardware) or when Automatic Operation is enabled. When a DMA data transfer is complete, MSTDMA + * must be cleared prior to beginning the next operation, typically a Start or Stop.This bit is + * read/write. + * 0b0..Disable. No DMA requests are generated for master operation. + * 0b1..Enable. A DMA request is generated for I2C master data operations. When this I2C master is generating + * Acknowledge bits in Master Receiver mode, the acknowledge is generated automatically. + */ +#define I2C_MSTCTL_MSTDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTDMA_SHIFT)) & I2C_MSTCTL_MSTDMA_MASK) +/*! @} */ + +/*! @name MSTTIME - Master timing configuration. */ +/*! @{ */ +#define I2C_MSTTIME_MSTSCLLOW_MASK (0x7U) +#define I2C_MSTTIME_MSTSCLLOW_SHIFT (0U) +/*! MSTSCLLOW - Master SCL Low time. Specifies the minimum low time that will be asserted by this + * master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This + * corresponds to the parameter t LOW in the I2C bus specification. I2C bus specification parameters + * tBUF and tSU;STA have the same values and are also controlled by MSTSCLLOW. + * 0b000..2 clocks. Minimum SCL low time is 2 clocks of the I2C clock pre-divider. + * 0b001..3 clocks. Minimum SCL low time is 3 clocks of the I2C clock pre-divider. + * 0b010..4 clocks. Minimum SCL low time is 4 clocks of the I2C clock pre-divider. + * 0b011..5 clocks. Minimum SCL low time is 5 clocks of the I2C clock pre-divider. + * 0b100..6 clocks. Minimum SCL low time is 6 clocks of the I2C clock pre-divider. + * 0b101..7 clocks. Minimum SCL low time is 7 clocks of the I2C clock pre-divider. + * 0b110..8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider. + * 0b111..9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider. + */ +#define I2C_MSTTIME_MSTSCLLOW(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLLOW_SHIFT)) & I2C_MSTTIME_MSTSCLLOW_MASK) +#define I2C_MSTTIME_MSTSCLHIGH_MASK (0x70U) +#define I2C_MSTTIME_MSTSCLHIGH_SHIFT (4U) +/*! MSTSCLHIGH - Master SCL High time. Specifies the minimum high time that will be asserted by this + * master on SCL. Other masters in a multi-master system could shorten this time. This + * corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters + * tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH. + * 0b000..2 clocks. Minimum SCL high time is 2 clock of the I2C clock pre-divider. + * 0b001..3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider . + * 0b010..4 clocks. Minimum SCL high time is 4 clock of the I2C clock pre-divider. + * 0b011..5 clocks. Minimum SCL high time is 5 clock of the I2C clock pre-divider. + * 0b100..6 clocks. Minimum SCL high time is 6 clock of the I2C clock pre-divider. + * 0b101..7 clocks. Minimum SCL high time is 7 clock of the I2C clock pre-divider. + * 0b110..8 clocks. Minimum SCL high time is 8 clock of the I2C clock pre-divider. + * 0b111..9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider. + */ +#define I2C_MSTTIME_MSTSCLHIGH(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLHIGH_SHIFT)) & I2C_MSTTIME_MSTSCLHIGH_MASK) +/*! @} */ + +/*! @name MSTDAT - Combined Master receiver and transmitter data register. */ +/*! @{ */ +#define I2C_MSTDAT_DATA_MASK (0xFFU) +#define I2C_MSTDAT_DATA_SHIFT (0U) +#define I2C_MSTDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTDAT_DATA_SHIFT)) & I2C_MSTDAT_DATA_MASK) +/*! @} */ + +/*! @name SLVCTL - Slave control register. */ +/*! @{ */ +#define I2C_SLVCTL_SLVCONTINUE_MASK (0x1U) +#define I2C_SLVCTL_SLVCONTINUE_SHIFT (0U) +/*! SLVCONTINUE - Slave Continue. + * 0b0..No effect. + * 0b1..Continue. Informs the Slave function to continue to the next operation, by clearing the SLVPENDING flag + * in the STAT register. This must be done after writing transmit data, reading received data, or any other + * housekeeping related to the next bus operation. Automatic Operation has different requirements. SLVCONTINUE + * should not be set unless SLVPENDING = 1. + */ +#define I2C_SLVCTL_SLVCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVCONTINUE_SHIFT)) & I2C_SLVCTL_SLVCONTINUE_MASK) +#define I2C_SLVCTL_SLVNACK_MASK (0x2U) +#define I2C_SLVCTL_SLVNACK_SHIFT (1U) +/*! SLVNACK - Slave NACK. + * 0b0..No effect. + * 0b1..NACK. Causes the Slave function to NACK the master when the slave is receiving data from the master (Slave Receiver mode). + */ +#define I2C_SLVCTL_SLVNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVNACK_SHIFT)) & I2C_SLVCTL_SLVNACK_MASK) +#define I2C_SLVCTL_SLVDMA_MASK (0x8U) +#define I2C_SLVCTL_SLVDMA_SHIFT (3U) +/*! SLVDMA - Slave DMA enable. + * 0b0..Disabled. No DMA requests are issued for Slave mode operation. + * 0b1..Enabled. DMA requests are issued for I2C slave data transmission and reception. + */ +#define I2C_SLVCTL_SLVDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVDMA_SHIFT)) & I2C_SLVCTL_SLVDMA_MASK) +#define I2C_SLVCTL_AUTOACK_MASK (0x100U) +#define I2C_SLVCTL_AUTOACK_SHIFT (8U) +/*! AUTOACK - Automatic Acknowledge.When this bit is set, it will cause an I2C header which matches + * SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA + * to allow processing of the data without intervention. If this bit is clear and a header + * matches SLVADR0, the behavior is controlled by AUTONACK in the SLVADR0 register: allowing NACK or + * interrupt. + * 0b0..Normal, non-automatic operation. If AUTONACK = 0, an SlvPending interrupt is generated when a matching + * address is received. If AUTONACK = 1, received addresses are NACKed (ignored). + * 0b1..A header with matching SLVADR0 and matching direction as set by AUTOMATCHREAD will be ACKed immediately, + * allowing the master to move on to the data bytes. If the address matches SLVADR0, but the direction does + * not match AUTOMATCHREAD, the behavior will depend on the AUTONACK bit in the SLVADR0 register: if AUTONACK + * is set, then it will be Nacked; else if AUTONACK is clear, then a SlvPending interrupt is generated. + */ +#define I2C_SLVCTL_AUTOACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOACK_SHIFT)) & I2C_SLVCTL_AUTOACK_MASK) +#define I2C_SLVCTL_AUTOMATCHREAD_MASK (0x200U) +#define I2C_SLVCTL_AUTOMATCHREAD_SHIFT (9U) +/*! AUTOMATCHREAD - When AUTOACK is set, this bit controls whether it matches a read or write + * request on the next header with an address matching SLVADR0. Since DMA needs to be configured to + * match the transfer direction, the direction needs to be specified. This bit allows a direction to + * be chosen for the next operation. + * 0b0..The expected next operation in Automatic Mode is an I2C write. + * 0b1..The expected next operation in Automatic Mode is an I2C read. + */ +#define I2C_SLVCTL_AUTOMATCHREAD(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOMATCHREAD_SHIFT)) & I2C_SLVCTL_AUTOMATCHREAD_MASK) +/*! @} */ + +/*! @name SLVDAT - Combined Slave receiver and transmitter data register. */ +/*! @{ */ +#define I2C_SLVDAT_DATA_MASK (0xFFU) +#define I2C_SLVDAT_DATA_SHIFT (0U) +#define I2C_SLVDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVDAT_DATA_SHIFT)) & I2C_SLVDAT_DATA_MASK) +/*! @} */ + +/*! @name SLVADR - Slave address register. */ +/*! @{ */ +#define I2C_SLVADR_SADISABLE_MASK (0x1U) +#define I2C_SLVADR_SADISABLE_SHIFT (0U) +/*! SADISABLE - Slave Address n Disable. + * 0b0..Enabled. Slave Address n is enabled. + * 0b1..Ignored Slave Address n is ignored. + */ +#define I2C_SLVADR_SADISABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SADISABLE_SHIFT)) & I2C_SLVADR_SADISABLE_MASK) +#define I2C_SLVADR_SLVADR_MASK (0xFEU) +#define I2C_SLVADR_SLVADR_SHIFT (1U) +#define I2C_SLVADR_SLVADR(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SLVADR_SHIFT)) & I2C_SLVADR_SLVADR_MASK) +#define I2C_SLVADR_AUTONACK_MASK (0x8000U) +#define I2C_SLVADR_AUTONACK_SHIFT (15U) +/*! AUTONACK - Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD, allows + * software to ignore I2C traffic while handling previous I2C data or other operations. + * 0b0..Normal operation, matching I2C addresses are not ignored. + * 0b1..Automatic-only mode. All incoming addresses are ignored (NACKed), unless AUTOACK is set, it matches + * SLVADRn, and AUTOMATCHREAD matches the direction. + */ +#define I2C_SLVADR_AUTONACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_AUTONACK_SHIFT)) & I2C_SLVADR_AUTONACK_MASK) +/*! @} */ + +/* The count of I2C_SLVADR */ +#define I2C_SLVADR_COUNT (4U) + +/*! @name SLVQUAL0 - Slave Qualification for address 0. */ +/*! @{ */ +#define I2C_SLVQUAL0_QUALMODE0_MASK (0x1U) +#define I2C_SLVQUAL0_QUALMODE0_SHIFT (0U) +/*! QUALMODE0 - Qualify mode for slave address 0. + * 0b0..Mask. The SLVQUAL0 field is used as a logical mask for matching address 0. + * 0b1..Extend. The SLVQUAL0 field is used to extend address 0 matching in a range of addresses. + */ +#define I2C_SLVQUAL0_QUALMODE0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_QUALMODE0_SHIFT)) & I2C_SLVQUAL0_QUALMODE0_MASK) +#define I2C_SLVQUAL0_SLVQUAL0_MASK (0xFEU) +#define I2C_SLVQUAL0_SLVQUAL0_SHIFT (1U) +#define I2C_SLVQUAL0_SLVQUAL0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_SLVQUAL0_SHIFT)) & I2C_SLVQUAL0_SLVQUAL0_MASK) +/*! @} */ + +/*! @name MONRXDAT - Monitor receiver data register. */ +/*! @{ */ +#define I2C_MONRXDAT_MONRXDAT_MASK (0xFFU) +#define I2C_MONRXDAT_MONRXDAT_SHIFT (0U) +#define I2C_MONRXDAT_MONRXDAT(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRXDAT_SHIFT)) & I2C_MONRXDAT_MONRXDAT_MASK) +#define I2C_MONRXDAT_MONSTART_MASK (0x100U) +#define I2C_MONRXDAT_MONSTART_SHIFT (8U) +/*! MONSTART - Monitor Received Start. + * 0b0..No start detected. The Monitor function has not detected a Start event on the I2C bus. + * 0b1..Start detected. The Monitor function has detected a Start event on the I2C bus. + */ +#define I2C_MONRXDAT_MONSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONSTART_SHIFT)) & I2C_MONRXDAT_MONSTART_MASK) +#define I2C_MONRXDAT_MONRESTART_MASK (0x200U) +#define I2C_MONRXDAT_MONRESTART_SHIFT (9U) +/*! MONRESTART - Monitor Received Repeated Start. + * 0b0..No repeated start detected. The Monitor function has not detected a Repeated Start event on the I2C bus. + * 0b1..Repeated start detected. The Monitor function has detected a Repeated Start event on the I2C bus. + */ +#define I2C_MONRXDAT_MONRESTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRESTART_SHIFT)) & I2C_MONRXDAT_MONRESTART_MASK) +#define I2C_MONRXDAT_MONNACK_MASK (0x400U) +#define I2C_MONRXDAT_MONNACK_SHIFT (10U) +/*! MONNACK - Monitor Received NACK. + * 0b0..Acknowledged. The data currently being provided by the Monitor function was acknowledged by at least one master or slave receiver. + * 0b1..Not acknowledged. The data currently being provided by the Monitor function was not acknowledged by any receiver. + */ +#define I2C_MONRXDAT_MONNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONNACK_SHIFT)) & I2C_MONRXDAT_MONNACK_MASK) +/*! @} */ + +/*! @name ID - Peripheral identification register. */ +/*! @{ */ +#define I2C_ID_APERTURE_MASK (0xFFU) +#define I2C_ID_APERTURE_SHIFT (0U) +#define I2C_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_APERTURE_SHIFT)) & I2C_ID_APERTURE_MASK) +#define I2C_ID_MINOR_REV_MASK (0xF00U) +#define I2C_ID_MINOR_REV_SHIFT (8U) +#define I2C_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_MINOR_REV_SHIFT)) & I2C_ID_MINOR_REV_MASK) +#define I2C_ID_MAJOR_REV_MASK (0xF000U) +#define I2C_ID_MAJOR_REV_SHIFT (12U) +#define I2C_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_MAJOR_REV_SHIFT)) & I2C_ID_MAJOR_REV_MASK) +#define I2C_ID_ID_MASK (0xFFFF0000U) +#define I2C_ID_ID_SHIFT (16U) +#define I2C_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_ID_SHIFT)) & I2C_ID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group I2C_Register_Masks */ + + +/* I2C - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral I2C0 base address */ + #define I2C0_BASE (0x50086000u) + /** Peripheral I2C0 base address */ + #define I2C0_BASE_NS (0x40086000u) + /** Peripheral I2C0 base pointer */ + #define I2C0 ((I2C_Type *)I2C0_BASE) + /** Peripheral I2C0 base pointer */ + #define I2C0_NS ((I2C_Type *)I2C0_BASE_NS) + /** Peripheral I2C1 base address */ + #define I2C1_BASE (0x50087000u) + /** Peripheral I2C1 base address */ + #define I2C1_BASE_NS (0x40087000u) + /** Peripheral I2C1 base pointer */ + #define I2C1 ((I2C_Type *)I2C1_BASE) + /** Peripheral I2C1 base pointer */ + #define I2C1_NS ((I2C_Type *)I2C1_BASE_NS) + /** Peripheral I2C2 base address */ + #define I2C2_BASE (0x50088000u) + /** Peripheral I2C2 base address */ + #define I2C2_BASE_NS (0x40088000u) + /** Peripheral I2C2 base pointer */ + #define I2C2 ((I2C_Type *)I2C2_BASE) + /** Peripheral I2C2 base pointer */ + #define I2C2_NS ((I2C_Type *)I2C2_BASE_NS) + /** Peripheral I2C3 base address */ + #define I2C3_BASE (0x50089000u) + /** Peripheral I2C3 base address */ + #define I2C3_BASE_NS (0x40089000u) + /** Peripheral I2C3 base pointer */ + #define I2C3 ((I2C_Type *)I2C3_BASE) + /** Peripheral I2C3 base pointer */ + #define I2C3_NS ((I2C_Type *)I2C3_BASE_NS) + /** Peripheral I2C4 base address */ + #define I2C4_BASE (0x5008A000u) + /** Peripheral I2C4 base address */ + #define I2C4_BASE_NS (0x4008A000u) + /** Peripheral I2C4 base pointer */ + #define I2C4 ((I2C_Type *)I2C4_BASE) + /** Peripheral I2C4 base pointer */ + #define I2C4_NS ((I2C_Type *)I2C4_BASE_NS) + /** Peripheral I2C5 base address */ + #define I2C5_BASE (0x50096000u) + /** Peripheral I2C5 base address */ + #define I2C5_BASE_NS (0x40096000u) + /** Peripheral I2C5 base pointer */ + #define I2C5 ((I2C_Type *)I2C5_BASE) + /** Peripheral I2C5 base pointer */ + #define I2C5_NS ((I2C_Type *)I2C5_BASE_NS) + /** Peripheral I2C6 base address */ + #define I2C6_BASE (0x50097000u) + /** Peripheral I2C6 base address */ + #define I2C6_BASE_NS (0x40097000u) + /** Peripheral I2C6 base pointer */ + #define I2C6 ((I2C_Type *)I2C6_BASE) + /** Peripheral I2C6 base pointer */ + #define I2C6_NS ((I2C_Type *)I2C6_BASE_NS) + /** Peripheral I2C7 base address */ + #define I2C7_BASE (0x50098000u) + /** Peripheral I2C7 base address */ + #define I2C7_BASE_NS (0x40098000u) + /** Peripheral I2C7 base pointer */ + #define I2C7 ((I2C_Type *)I2C7_BASE) + /** Peripheral I2C7 base pointer */ + #define I2C7_NS ((I2C_Type *)I2C7_BASE_NS) + /** Array initializer of I2C peripheral base addresses */ + #define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE, I2C4_BASE, I2C5_BASE, I2C6_BASE, I2C7_BASE } + /** Array initializer of I2C peripheral base pointers */ + #define I2C_BASE_PTRS { I2C0, I2C1, I2C2, I2C3, I2C4, I2C5, I2C6, I2C7 } + /** Array initializer of I2C peripheral base addresses */ + #define I2C_BASE_ADDRS_NS { I2C0_BASE_NS, I2C1_BASE_NS, I2C2_BASE_NS, I2C3_BASE_NS, I2C4_BASE_NS, I2C5_BASE_NS, I2C6_BASE_NS, I2C7_BASE_NS } + /** Array initializer of I2C peripheral base pointers */ + #define I2C_BASE_PTRS_NS { I2C0_NS, I2C1_NS, I2C2_NS, I2C3_NS, I2C4_NS, I2C5_NS, I2C6_NS, I2C7_NS } +#else + /** Peripheral I2C0 base address */ + #define I2C0_BASE (0x40086000u) + /** Peripheral I2C0 base pointer */ + #define I2C0 ((I2C_Type *)I2C0_BASE) + /** Peripheral I2C1 base address */ + #define I2C1_BASE (0x40087000u) + /** Peripheral I2C1 base pointer */ + #define I2C1 ((I2C_Type *)I2C1_BASE) + /** Peripheral I2C2 base address */ + #define I2C2_BASE (0x40088000u) + /** Peripheral I2C2 base pointer */ + #define I2C2 ((I2C_Type *)I2C2_BASE) + /** Peripheral I2C3 base address */ + #define I2C3_BASE (0x40089000u) + /** Peripheral I2C3 base pointer */ + #define I2C3 ((I2C_Type *)I2C3_BASE) + /** Peripheral I2C4 base address */ + #define I2C4_BASE (0x4008A000u) + /** Peripheral I2C4 base pointer */ + #define I2C4 ((I2C_Type *)I2C4_BASE) + /** Peripheral I2C5 base address */ + #define I2C5_BASE (0x40096000u) + /** Peripheral I2C5 base pointer */ + #define I2C5 ((I2C_Type *)I2C5_BASE) + /** Peripheral I2C6 base address */ + #define I2C6_BASE (0x40097000u) + /** Peripheral I2C6 base pointer */ + #define I2C6 ((I2C_Type *)I2C6_BASE) + /** Peripheral I2C7 base address */ + #define I2C7_BASE (0x40098000u) + /** Peripheral I2C7 base pointer */ + #define I2C7 ((I2C_Type *)I2C7_BASE) + /** Array initializer of I2C peripheral base addresses */ + #define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE, I2C4_BASE, I2C5_BASE, I2C6_BASE, I2C7_BASE } + /** Array initializer of I2C peripheral base pointers */ + #define I2C_BASE_PTRS { I2C0, I2C1, I2C2, I2C3, I2C4, I2C5, I2C6, I2C7 } +#endif +/** Interrupt vectors for the I2C peripheral type */ +#define I2C_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } + +/*! + * @} + */ /* end of group I2C_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- I2S Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer + * @{ + */ + +/** I2S - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[3072]; + __IO uint32_t CFG1; /**< Configuration register 1 for the primary channel pair., offset: 0xC00 */ + __IO uint32_t CFG2; /**< Configuration register 2 for the primary channel pair., offset: 0xC04 */ + __IO uint32_t STAT; /**< Status register for the primary channel pair., offset: 0xC08 */ + uint8_t RESERVED_1[16]; + __IO uint32_t DIV; /**< Clock divider, used by all channel pairs., offset: 0xC1C */ + struct { /* offset: 0xC20, array step: 0x20 */ + __IO uint32_t PCFG1; /**< Configuration register 1 for channel pair, array offset: 0xC20, array step: 0x20 */ + __IO uint32_t PCFG2; /**< Configuration register 2 for channel pair, array offset: 0xC24, array step: 0x20 */ + __IO uint32_t PSTAT; /**< Status register for channel pair, array offset: 0xC28, array step: 0x20 */ + uint8_t RESERVED_0[20]; + } SECCHANNEL[3]; + uint8_t RESERVED_2[384]; + __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */ + __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ + __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */ + uint8_t RESERVED_3[4]; + __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */ + __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */ + __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */ + uint8_t RESERVED_4[4]; + __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ + __O uint32_t FIFOWR48H; /**< FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE24 */ + uint8_t RESERVED_5[8]; + __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */ + __I uint32_t FIFORD48H; /**< FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE34 */ + uint8_t RESERVED_6[8]; + __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */ + __I uint32_t FIFORD48HNOPOP; /**< FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE44 */ + uint8_t RESERVED_7[436]; + __I uint32_t ID; /**< I2S Module identification, offset: 0xFFC */ +} I2S_Type; + +/* ---------------------------------------------------------------------------- + -- I2S Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2S_Register_Masks I2S Register Masks + * @{ + */ + +/*! @name CFG1 - Configuration register 1 for the primary channel pair. */ +/*! @{ */ +#define I2S_CFG1_MAINENABLE_MASK (0x1U) +#define I2S_CFG1_MAINENABLE_SHIFT (0U) +/*! MAINENABLE - Main enable for I 2S function in this Flexcomm + * 0b0..All I 2S channel pairs in this Flexcomm are disabled and the internal state machines, counters, and flags + * are reset. No other channel pairs can be enabled. + * 0b1..This I 2S channel pair is enabled. Other channel pairs in this Flexcomm may be enabled in their individual PAIRENABLE bits. + */ +#define I2S_CFG1_MAINENABLE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MAINENABLE_SHIFT)) & I2S_CFG1_MAINENABLE_MASK) +#define I2S_CFG1_DATAPAUSE_MASK (0x2U) +#define I2S_CFG1_DATAPAUSE_SHIFT (1U) +/*! DATAPAUSE - Data flow Pause. Allows pausing data flow between the I2S serializer/deserializer + * and the FIFO. This could be done in order to change streams, or while restarting after a data + * underflow or overflow. When paused, FIFO operations can be done without corrupting data that is + * in the process of being sent or received. Once a data pause has been requested, the interface + * may need to complete sending data that was in progress before interrupting the flow of data. + * Software must check that the pause is actually in effect before taking action. This is done by + * monitoring the DATAPAUSED flag in the STAT register. When DATAPAUSE is cleared, data transfer + * will resume at the beginning of the next frame. + * 0b0..Normal operation, or resuming normal operation at the next frame if the I2S has already been paused. + * 0b1..A pause in the data flow is being requested. It is in effect when DATAPAUSED in STAT = 1. + */ +#define I2S_CFG1_DATAPAUSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATAPAUSE_SHIFT)) & I2S_CFG1_DATAPAUSE_MASK) +#define I2S_CFG1_PAIRCOUNT_MASK (0xCU) +#define I2S_CFG1_PAIRCOUNT_SHIFT (2U) +/*! PAIRCOUNT - Provides the number of I2S channel pairs in this Flexcomm This is a read-only field + * whose value may be different in other Flexcomms. 00 = there is 1 I2S channel pair in this + * Flexcomm. 01 = there are 2 I2S channel pairs in this Flexcomm. 10 = there are 3 I2S channel pairs + * in this Flexcomm. 11 = there are 4 I2S channel pairs in this Flexcomm. + * 0b00..1 I2S channel pairs in this flexcomm + * 0b01..2 I2S channel pairs in this flexcomm + * 0b10..3 I2S channel pairs in this flexcomm + * 0b11..4 I2S channel pairs in this flexcomm + */ +#define I2S_CFG1_PAIRCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_PAIRCOUNT_SHIFT)) & I2S_CFG1_PAIRCOUNT_MASK) +#define I2S_CFG1_MSTSLVCFG_MASK (0x30U) +#define I2S_CFG1_MSTSLVCFG_SHIFT (4U) +/*! MSTSLVCFG - Master / slave configuration selection, determining how SCK and WS are used by all channel pairs in this Flexcomm. + * 0b00..Normal slave mode, the default mode. SCK and WS are received from a master and used to transmit or receive data. + * 0b01..WS synchronized master. WS is received from another master and used to synchronize the generation of + * SCK, when divided from the Flexcomm function clock. + * 0b10..Master using an existing SCK. SCK is received and used directly to generate WS, as well as transmitting or receiving data. + * 0b11..Normal master mode. SCK and WS are generated so they can be sent to one or more slave devices. + */ +#define I2S_CFG1_MSTSLVCFG(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MSTSLVCFG_SHIFT)) & I2S_CFG1_MSTSLVCFG_MASK) +#define I2S_CFG1_MODE_MASK (0xC0U) +#define I2S_CFG1_MODE_SHIFT (6U) +/*! MODE - Selects the basic I2S operating mode. Other configurations modify this to obtain all + * supported cases. See Formats and modes for examples. + * 0b00..I2S mode a.k.a. 'classic' mode. WS has a 50% duty cycle, with (for each enabled channel pair) one piece + * of left channel data occurring during the first phase, and one pieces of right channel data occurring + * during the second phase. In this mode, the data region begins one clock after the leading WS edge for the + * frame. For a 50% WS duty cycle, FRAMELEN must define an even number of I2S clocks for the frame. If + * FRAMELEN defines an odd number of clocks per frame, the extra clock will occur on the right. + * 0b01..DSP mode where WS has a 50% duty cycle. See remark for mode 0. + * 0b10..DSP mode where WS has a one clock long pulse at the beginning of each data frame. + * 0b11..DSP mode where WS has a one data slot long pulse at the beginning of each data frame. + */ +#define I2S_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MODE_SHIFT)) & I2S_CFG1_MODE_MASK) +#define I2S_CFG1_RIGHTLOW_MASK (0x100U) +#define I2S_CFG1_RIGHTLOW_SHIFT (8U) +/*! RIGHTLOW - Right channel data is in the Low portion of FIFO data. Essentially, this swaps left + * and right channel data as it is transferred to or from the FIFO. This bit is not used if the + * data width is greater than 24 bits or if PDMDATA = 1. Note that if the ONECHANNEL field (bit 10 + * of this register) = 1, the one channel to be used is the nominally the left channel. POSITION + * can still place that data in the frame where right channel data is normally located. if all + * enabled channel pairs have ONECHANNEL = 1, then RIGHTLOW = 1 is not allowed. + * 0b0..The right channel is taken from the high part of the FIFO data. For example, when data is 16 bits, FIFO + * bits 31:16 are used for the right channel. + * 0b1..The right channel is taken from the low part of the FIFO data. For example, when data is 16 bits, FIFO + * bits 15:0 are used for the right channel. + */ +#define I2S_CFG1_RIGHTLOW(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_RIGHTLOW_SHIFT)) & I2S_CFG1_RIGHTLOW_MASK) +#define I2S_CFG1_LEFTJUST_MASK (0x200U) +#define I2S_CFG1_LEFTJUST_SHIFT (9U) +/*! LEFTJUST - Left Justify data. + * 0b0..Data is transferred between the FIFO and the I2S serializer/deserializer right justified, i.e. starting + * from bit 0 and continuing to the position defined by DATALEN. This would correspond to right justified data + * in the stream on the data bus. + * 0b1..Data is transferred between the FIFO and the I2S serializer/deserializer left justified, i.e. starting + * from the MSB of the FIFO entry and continuing for the number of bits defined by DATALEN. This would + * correspond to left justified data in the stream on the data bus. + */ +#define I2S_CFG1_LEFTJUST(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_LEFTJUST_SHIFT)) & I2S_CFG1_LEFTJUST_MASK) +#define I2S_CFG1_ONECHANNEL_MASK (0x400U) +#define I2S_CFG1_ONECHANNEL_SHIFT (10U) +/*! ONECHANNEL - Single channel mode. Applies to both transmit and receive. This configuration bit + * applies only to the first I2S channel pair. Other channel pairs may select this mode + * independently in their separate CFG1 registers. + * 0b0..I2S data for this channel pair is treated as left and right channels. + * 0b1..I2S data for this channel pair is treated as a single channel, functionally the left channel for this + * pair. In mode 0 only, the right side of the frame begins at POSITION = 0x100. This is because mode 0 makes a + * clear distinction between the left and right sides of the frame. When ONECHANNEL = 1, the single channel + * of data may be placed on the right by setting POSITION to 0x100 + the data position within the right side + * (e.g. 0x108 would place data starting at the 8th clock after the middle of the frame). In other modes, data + * for the single channel of data is placed at the clock defined by POSITION. + */ +#define I2S_CFG1_ONECHANNEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_ONECHANNEL_SHIFT)) & I2S_CFG1_ONECHANNEL_MASK) +#define I2S_CFG1_PDMDATA_MASK (0x800U) +#define I2S_CFG1_PDMDATA_SHIFT (11U) +/*! PDMDATA - PDM Data selection. This bit controls the data source for I2S transmit, and cannot be + * set in Rx mode. This bit only has an effect if the device the Flexcomm resides in includes a + * D-Mic subsystem. For the LPC55xx, this bit applies only to Flexcomm 6,7. + * 0b0..Normal operation, data is transferred to or from the Flexcomm FIFO. + * 0b1..The data source is the D-Mic subsystem. When PDMDATA = 1, only the primary channel pair can be used in + * this Flexcomm. If ONECHANNEL = 1, only the PDM left data is used. the WS rate must match the Fs (sample + * rate) of the D-Mic decimator. A rate mismatch will at some point cause the I2S to overrun or underrun. + */ +#define I2S_CFG1_PDMDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_PDMDATA_SHIFT)) & I2S_CFG1_PDMDATA_MASK) +#define I2S_CFG1_SCK_POL_MASK (0x1000U) +#define I2S_CFG1_SCK_POL_SHIFT (12U) +/*! SCK_POL - SCK polarity. + * 0b0..Data is launched on SCK falling edges and sampled on SCK rising edges (standard for I2S). + * 0b1..Data is launched on SCK rising edges and sampled on SCK falling edges. + */ +#define I2S_CFG1_SCK_POL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_SCK_POL_SHIFT)) & I2S_CFG1_SCK_POL_MASK) +#define I2S_CFG1_WS_POL_MASK (0x2000U) +#define I2S_CFG1_WS_POL_SHIFT (13U) +/*! WS_POL - WS polarity. + * 0b0..Data frames begin at a falling edge of WS (standard for classic I2S). + * 0b1..WS is inverted, resulting in a data frame beginning at a rising edge of WS (standard for most 'non-classic' variations of I2S). + */ +#define I2S_CFG1_WS_POL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_WS_POL_SHIFT)) & I2S_CFG1_WS_POL_MASK) +#define I2S_CFG1_DATALEN_MASK (0x1F0000U) +#define I2S_CFG1_DATALEN_SHIFT (16U) +#define I2S_CFG1_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATALEN_SHIFT)) & I2S_CFG1_DATALEN_MASK) +/*! @} */ + +/*! @name CFG2 - Configuration register 2 for the primary channel pair. */ +/*! @{ */ +#define I2S_CFG2_FRAMELEN_MASK (0x1FFU) +#define I2S_CFG2_FRAMELEN_SHIFT (0U) +#define I2S_CFG2_FRAMELEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_FRAMELEN_SHIFT)) & I2S_CFG2_FRAMELEN_MASK) +#define I2S_CFG2_POSITION_MASK (0x1FF0000U) +#define I2S_CFG2_POSITION_SHIFT (16U) +#define I2S_CFG2_POSITION(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_POSITION_SHIFT)) & I2S_CFG2_POSITION_MASK) +/*! @} */ + +/*! @name STAT - Status register for the primary channel pair. */ +/*! @{ */ +#define I2S_STAT_BUSY_MASK (0x1U) +#define I2S_STAT_BUSY_SHIFT (0U) +/*! BUSY - Busy status for the primary channel pair. Other BUSY flags may be found in the STAT register for each channel pair. + * 0b0..The transmitter/receiver for channel pair is currently idle. + * 0b1..The transmitter/receiver for channel pair is currently processing data. + */ +#define I2S_STAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_BUSY_SHIFT)) & I2S_STAT_BUSY_MASK) +#define I2S_STAT_SLVFRMERR_MASK (0x2U) +#define I2S_STAT_SLVFRMERR_SHIFT (1U) +/*! SLVFRMERR - Slave Frame Error flag. This applies when at least one channel pair is operating as + * a slave. An error indicates that the incoming WS signal did not transition as expected due to + * a mismatch between FRAMELEN and the actual incoming I2S stream. + * 0b0..No error has been recorded. + * 0b1..An error has been recorded for some channel pair that is operating in slave mode. ERROR is cleared by writing a 1 to this bit position. + */ +#define I2S_STAT_SLVFRMERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_SLVFRMERR_SHIFT)) & I2S_STAT_SLVFRMERR_MASK) +#define I2S_STAT_LR_MASK (0x4U) +#define I2S_STAT_LR_SHIFT (2U) +/*! LR - Left/Right indication. This flag is considered to be a debugging aid and is not expected to + * be used by an I2S driver. Valid when one channel pair is busy. Indicates left or right data + * being processed for the currently busy channel pair. + * 0b0..Left channel. + * 0b1..Right channel. + */ +#define I2S_STAT_LR(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_LR_SHIFT)) & I2S_STAT_LR_MASK) +#define I2S_STAT_DATAPAUSED_MASK (0x8U) +#define I2S_STAT_DATAPAUSED_SHIFT (3U) +/*! DATAPAUSED - Data Paused status flag. Applies to all I2S channels + * 0b0..Data is not currently paused. A data pause may have been requested but is not yet in force, waiting for + * an allowed pause point. Refer to the description of the DATAPAUSE control bit in the CFG1 register. + * 0b1..A data pause has been requested and is now in force. + */ +#define I2S_STAT_DATAPAUSED(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_DATAPAUSED_SHIFT)) & I2S_STAT_DATAPAUSED_MASK) +/*! @} */ + +/*! @name DIV - Clock divider, used by all channel pairs. */ +/*! @{ */ +#define I2S_DIV_DIV_MASK (0xFFFU) +#define I2S_DIV_DIV_SHIFT (0U) +#define I2S_DIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_DIV_DIV_SHIFT)) & I2S_DIV_DIV_MASK) +/*! @} */ + +/*! @name SECCHANNEL_PCFG1 - Configuration register 1 for channel pair */ +/*! @{ */ +#define I2S_SECCHANNEL_PCFG1_PAIRENABLE_MASK (0x1U) +#define I2S_SECCHANNEL_PCFG1_PAIRENABLE_SHIFT (0U) +#define I2S_SECCHANNEL_PCFG1_PAIRENABLE(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PCFG1_PAIRENABLE_SHIFT)) & I2S_SECCHANNEL_PCFG1_PAIRENABLE_MASK) +#define I2S_SECCHANNEL_PCFG1_ONECHANNEL_MASK (0x400U) +#define I2S_SECCHANNEL_PCFG1_ONECHANNEL_SHIFT (10U) +#define I2S_SECCHANNEL_PCFG1_ONECHANNEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PCFG1_ONECHANNEL_SHIFT)) & I2S_SECCHANNEL_PCFG1_ONECHANNEL_MASK) +/*! @} */ + +/* The count of I2S_SECCHANNEL_PCFG1 */ +#define I2S_SECCHANNEL_PCFG1_COUNT (3U) + +/*! @name SECCHANNEL_PCFG2 - Configuration register 2 for channel pair */ +/*! @{ */ +#define I2S_SECCHANNEL_PCFG2_POSITION_MASK (0x1FF0000U) +#define I2S_SECCHANNEL_PCFG2_POSITION_SHIFT (16U) +#define I2S_SECCHANNEL_PCFG2_POSITION(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PCFG2_POSITION_SHIFT)) & I2S_SECCHANNEL_PCFG2_POSITION_MASK) +/*! @} */ + +/* The count of I2S_SECCHANNEL_PCFG2 */ +#define I2S_SECCHANNEL_PCFG2_COUNT (3U) + +/*! @name SECCHANNEL_PSTAT - Status register for channel pair */ +/*! @{ */ +#define I2S_SECCHANNEL_PSTAT_BUSY_MASK (0x1U) +#define I2S_SECCHANNEL_PSTAT_BUSY_SHIFT (0U) +#define I2S_SECCHANNEL_PSTAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_BUSY_SHIFT)) & I2S_SECCHANNEL_PSTAT_BUSY_MASK) +#define I2S_SECCHANNEL_PSTAT_SLVFRMERR_MASK (0x2U) +#define I2S_SECCHANNEL_PSTAT_SLVFRMERR_SHIFT (1U) +#define I2S_SECCHANNEL_PSTAT_SLVFRMERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_SLVFRMERR_SHIFT)) & I2S_SECCHANNEL_PSTAT_SLVFRMERR_MASK) +#define I2S_SECCHANNEL_PSTAT_LR_MASK (0x4U) +#define I2S_SECCHANNEL_PSTAT_LR_SHIFT (2U) +#define I2S_SECCHANNEL_PSTAT_LR(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_LR_SHIFT)) & I2S_SECCHANNEL_PSTAT_LR_MASK) +#define I2S_SECCHANNEL_PSTAT_DATAPAUSED_MASK (0x8U) +#define I2S_SECCHANNEL_PSTAT_DATAPAUSED_SHIFT (3U) +#define I2S_SECCHANNEL_PSTAT_DATAPAUSED(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_DATAPAUSED_SHIFT)) & I2S_SECCHANNEL_PSTAT_DATAPAUSED_MASK) +/*! @} */ + +/* The count of I2S_SECCHANNEL_PSTAT */ +#define I2S_SECCHANNEL_PSTAT_COUNT (3U) + +/*! @name FIFOCFG - FIFO configuration and enable register. */ +/*! @{ */ +#define I2S_FIFOCFG_ENABLETX_MASK (0x1U) +#define I2S_FIFOCFG_ENABLETX_SHIFT (0U) +/*! ENABLETX - Enable the transmit FIFO. + * 0b0..The transmit FIFO is not enabled. + * 0b1..The transmit FIFO is enabled. + */ +#define I2S_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLETX_SHIFT)) & I2S_FIFOCFG_ENABLETX_MASK) +#define I2S_FIFOCFG_ENABLERX_MASK (0x2U) +#define I2S_FIFOCFG_ENABLERX_SHIFT (1U) +/*! ENABLERX - Enable the receive FIFO. + * 0b0..The receive FIFO is not enabled. + * 0b1..The receive FIFO is enabled. + */ +#define I2S_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLERX_SHIFT)) & I2S_FIFOCFG_ENABLERX_MASK) +#define I2S_FIFOCFG_TXI2SE0_MASK (0x4U) +#define I2S_FIFOCFG_TXI2SE0_SHIFT (2U) +/*! TXI2SE0 - Transmit I2S empty 0. Determines the value sent by the I2S in transmit mode if the TX + * FIFO becomes empty. This value is sent repeatedly until the I2S is paused, the error is + * cleared, new data is provided, and the I2S is un-paused. + * 0b0..If the TX FIFO becomes empty, the last value is sent. This setting may be used when the data length is 24 + * bits or less, or when MONO = 1 for this channel pair. + * 0b1..If the TX FIFO becomes empty, 0 is sent. Use if the data length is greater than 24 bits or if zero fill is preferred. + */ +#define I2S_FIFOCFG_TXI2SE0(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_TXI2SE0_SHIFT)) & I2S_FIFOCFG_TXI2SE0_MASK) +#define I2S_FIFOCFG_PACK48_MASK (0x8U) +#define I2S_FIFOCFG_PACK48_SHIFT (3U) +/*! PACK48 - Packing format for 48-bit data. This relates to how data is entered into or taken from the FIFO by software or DMA. + * 0b0..48-bit I2S FIFO entries are handled as all 24-bit values. + * 0b1..48-bit I2S FIFO entries are handled as alternating 32-bit and 16-bit values. + */ +#define I2S_FIFOCFG_PACK48(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_PACK48_SHIFT)) & I2S_FIFOCFG_PACK48_MASK) +#define I2S_FIFOCFG_SIZE_MASK (0x30U) +#define I2S_FIFOCFG_SIZE_SHIFT (4U) +#define I2S_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_SIZE_SHIFT)) & I2S_FIFOCFG_SIZE_MASK) +#define I2S_FIFOCFG_DMATX_MASK (0x1000U) +#define I2S_FIFOCFG_DMATX_SHIFT (12U) +/*! DMATX - DMA configuration for transmit. + * 0b0..DMA is not used for the transmit function. + * 0b1..Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. + */ +#define I2S_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMATX_SHIFT)) & I2S_FIFOCFG_DMATX_MASK) +#define I2S_FIFOCFG_DMARX_MASK (0x2000U) +#define I2S_FIFOCFG_DMARX_SHIFT (13U) +/*! DMARX - DMA configuration for receive. + * 0b0..DMA is not used for the receive function. + * 0b1..Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. + */ +#define I2S_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMARX_SHIFT)) & I2S_FIFOCFG_DMARX_MASK) +#define I2S_FIFOCFG_WAKETX_MASK (0x4000U) +#define I2S_FIFOCFG_WAKETX_SHIFT (14U) +/*! WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power + * modes (up to power-down, as long as the peripheral function works in that power mode) without + * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The + * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware + * Wake-up control register. + * 0b0..Only enabled interrupts will wake up the device form reduced power modes. + * 0b1..A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in + * FIFOTRIG, even when the TXLVL interrupt is not enabled. + */ +#define I2S_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKETX_SHIFT)) & I2S_FIFOCFG_WAKETX_MASK) +#define I2S_FIFOCFG_WAKERX_MASK (0x8000U) +#define I2S_FIFOCFG_WAKERX_SHIFT (15U) +/*! WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power + * modes (up to power-down, as long as the peripheral function works in that power mode) without + * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The + * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware + * Wake-up control register. + * 0b0..Only enabled interrupts will wake up the device form reduced power modes. + * 0b1..A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in + * FIFOTRIG, even when the RXLVL interrupt is not enabled. + */ +#define I2S_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKERX_SHIFT)) & I2S_FIFOCFG_WAKERX_MASK) +#define I2S_FIFOCFG_EMPTYTX_MASK (0x10000U) +#define I2S_FIFOCFG_EMPTYTX_SHIFT (16U) +#define I2S_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYTX_SHIFT)) & I2S_FIFOCFG_EMPTYTX_MASK) +#define I2S_FIFOCFG_EMPTYRX_MASK (0x20000U) +#define I2S_FIFOCFG_EMPTYRX_SHIFT (17U) +#define I2S_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYRX_SHIFT)) & I2S_FIFOCFG_EMPTYRX_MASK) +#define I2S_FIFOCFG_POPDBG_MASK (0x40000U) +#define I2S_FIFOCFG_POPDBG_SHIFT (18U) +/*! POPDBG - Pop FIFO for debug reads. + * 0b0..Debug reads of the FIFO do not pop the FIFO. + * 0b1..A debug read will cause the FIFO to pop. + */ +#define I2S_FIFOCFG_POPDBG(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_POPDBG_SHIFT)) & I2S_FIFOCFG_POPDBG_MASK) +/*! @} */ + +/*! @name FIFOSTAT - FIFO status register. */ +/*! @{ */ +#define I2S_FIFOSTAT_TXERR_MASK (0x1U) +#define I2S_FIFOSTAT_TXERR_SHIFT (0U) +#define I2S_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXERR_SHIFT)) & I2S_FIFOSTAT_TXERR_MASK) +#define I2S_FIFOSTAT_RXERR_MASK (0x2U) +#define I2S_FIFOSTAT_RXERR_SHIFT (1U) +#define I2S_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXERR_SHIFT)) & I2S_FIFOSTAT_RXERR_MASK) +#define I2S_FIFOSTAT_PERINT_MASK (0x8U) +#define I2S_FIFOSTAT_PERINT_SHIFT (3U) +#define I2S_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_PERINT_SHIFT)) & I2S_FIFOSTAT_PERINT_MASK) +#define I2S_FIFOSTAT_TXEMPTY_MASK (0x10U) +#define I2S_FIFOSTAT_TXEMPTY_SHIFT (4U) +#define I2S_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXEMPTY_SHIFT)) & I2S_FIFOSTAT_TXEMPTY_MASK) +#define I2S_FIFOSTAT_TXNOTFULL_MASK (0x20U) +#define I2S_FIFOSTAT_TXNOTFULL_SHIFT (5U) +#define I2S_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXNOTFULL_SHIFT)) & I2S_FIFOSTAT_TXNOTFULL_MASK) +#define I2S_FIFOSTAT_RXNOTEMPTY_MASK (0x40U) +#define I2S_FIFOSTAT_RXNOTEMPTY_SHIFT (6U) +#define I2S_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXNOTEMPTY_SHIFT)) & I2S_FIFOSTAT_RXNOTEMPTY_MASK) +#define I2S_FIFOSTAT_RXFULL_MASK (0x80U) +#define I2S_FIFOSTAT_RXFULL_SHIFT (7U) +#define I2S_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXFULL_SHIFT)) & I2S_FIFOSTAT_RXFULL_MASK) +#define I2S_FIFOSTAT_TXLVL_MASK (0x1F00U) +#define I2S_FIFOSTAT_TXLVL_SHIFT (8U) +#define I2S_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXLVL_SHIFT)) & I2S_FIFOSTAT_TXLVL_MASK) +#define I2S_FIFOSTAT_RXLVL_MASK (0x1F0000U) +#define I2S_FIFOSTAT_RXLVL_SHIFT (16U) +#define I2S_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXLVL_SHIFT)) & I2S_FIFOSTAT_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */ +/*! @{ */ +#define I2S_FIFOTRIG_TXLVLENA_MASK (0x1U) +#define I2S_FIFOTRIG_TXLVLENA_SHIFT (0U) +/*! TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled + * in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set. + * 0b0..Transmit FIFO level does not generate a FIFO level trigger. + * 0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register. + */ +#define I2S_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVLENA_SHIFT)) & I2S_FIFOTRIG_TXLVLENA_MASK) +#define I2S_FIFOTRIG_RXLVLENA_MASK (0x2U) +#define I2S_FIFOTRIG_RXLVLENA_SHIFT (1U) +/*! RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled + * in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. + * 0b0..Receive FIFO level does not generate a FIFO level trigger. + * 0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. + */ +#define I2S_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVLENA_SHIFT)) & I2S_FIFOTRIG_RXLVLENA_MASK) +#define I2S_FIFOTRIG_TXLVL_MASK (0xF00U) +#define I2S_FIFOTRIG_TXLVL_SHIFT (8U) +#define I2S_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVL_SHIFT)) & I2S_FIFOTRIG_TXLVL_MASK) +#define I2S_FIFOTRIG_RXLVL_MASK (0xF0000U) +#define I2S_FIFOTRIG_RXLVL_SHIFT (16U) +#define I2S_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVL_SHIFT)) & I2S_FIFOTRIG_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */ +/*! @{ */ +#define I2S_FIFOINTENSET_TXERR_MASK (0x1U) +#define I2S_FIFOINTENSET_TXERR_SHIFT (0U) +/*! TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. + * 0b0..No interrupt will be generated for a transmit error. + * 0b1..An interrupt will be generated when a transmit error occurs. + */ +#define I2S_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXERR_SHIFT)) & I2S_FIFOINTENSET_TXERR_MASK) +#define I2S_FIFOINTENSET_RXERR_MASK (0x2U) +#define I2S_FIFOINTENSET_RXERR_SHIFT (1U) +/*! RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. + * 0b0..No interrupt will be generated for a receive error. + * 0b1..An interrupt will be generated when a receive error occurs. + */ +#define I2S_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXERR_SHIFT)) & I2S_FIFOINTENSET_RXERR_MASK) +#define I2S_FIFOINTENSET_TXLVL_MASK (0x4U) +#define I2S_FIFOINTENSET_TXLVL_SHIFT (2U) +/*! TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level + * specified by the TXLVL field in the FIFOTRIG register. + * 0b0..No interrupt will be generated based on the TX FIFO level. + * 0b1..If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases + * to the level specified by TXLVL in the FIFOTRIG register. + */ +#define I2S_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXLVL_SHIFT)) & I2S_FIFOINTENSET_TXLVL_MASK) +#define I2S_FIFOINTENSET_RXLVL_MASK (0x8U) +#define I2S_FIFOINTENSET_RXLVL_SHIFT (3U) +/*! RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level + * specified by the TXLVL field in the FIFOTRIG register. + * 0b0..No interrupt will be generated based on the RX FIFO level. + * 0b1..If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level + * increases to the level specified by RXLVL in the FIFOTRIG register. + */ +#define I2S_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXLVL_SHIFT)) & I2S_FIFOINTENSET_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */ +/*! @{ */ +#define I2S_FIFOINTENCLR_TXERR_MASK (0x1U) +#define I2S_FIFOINTENCLR_TXERR_SHIFT (0U) +#define I2S_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXERR_SHIFT)) & I2S_FIFOINTENCLR_TXERR_MASK) +#define I2S_FIFOINTENCLR_RXERR_MASK (0x2U) +#define I2S_FIFOINTENCLR_RXERR_SHIFT (1U) +#define I2S_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXERR_SHIFT)) & I2S_FIFOINTENCLR_RXERR_MASK) +#define I2S_FIFOINTENCLR_TXLVL_MASK (0x4U) +#define I2S_FIFOINTENCLR_TXLVL_SHIFT (2U) +#define I2S_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXLVL_SHIFT)) & I2S_FIFOINTENCLR_TXLVL_MASK) +#define I2S_FIFOINTENCLR_RXLVL_MASK (0x8U) +#define I2S_FIFOINTENCLR_RXLVL_SHIFT (3U) +#define I2S_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXLVL_SHIFT)) & I2S_FIFOINTENCLR_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTSTAT - FIFO interrupt status register. */ +/*! @{ */ +#define I2S_FIFOINTSTAT_TXERR_MASK (0x1U) +#define I2S_FIFOINTSTAT_TXERR_SHIFT (0U) +#define I2S_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXERR_SHIFT)) & I2S_FIFOINTSTAT_TXERR_MASK) +#define I2S_FIFOINTSTAT_RXERR_MASK (0x2U) +#define I2S_FIFOINTSTAT_RXERR_SHIFT (1U) +#define I2S_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXERR_SHIFT)) & I2S_FIFOINTSTAT_RXERR_MASK) +#define I2S_FIFOINTSTAT_TXLVL_MASK (0x4U) +#define I2S_FIFOINTSTAT_TXLVL_SHIFT (2U) +#define I2S_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXLVL_SHIFT)) & I2S_FIFOINTSTAT_TXLVL_MASK) +#define I2S_FIFOINTSTAT_RXLVL_MASK (0x8U) +#define I2S_FIFOINTSTAT_RXLVL_SHIFT (3U) +#define I2S_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXLVL_SHIFT)) & I2S_FIFOINTSTAT_RXLVL_MASK) +#define I2S_FIFOINTSTAT_PERINT_MASK (0x10U) +#define I2S_FIFOINTSTAT_PERINT_SHIFT (4U) +#define I2S_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_PERINT_SHIFT)) & I2S_FIFOINTSTAT_PERINT_MASK) +/*! @} */ + +/*! @name FIFOWR - FIFO write data. */ +/*! @{ */ +#define I2S_FIFOWR_TXDATA_MASK (0xFFFFFFFFU) +#define I2S_FIFOWR_TXDATA_SHIFT (0U) +#define I2S_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR_TXDATA_SHIFT)) & I2S_FIFOWR_TXDATA_MASK) +/*! @} */ + +/*! @name FIFOWR48H - FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */ +/*! @{ */ +#define I2S_FIFOWR48H_TXDATA_MASK (0xFFFFFFU) +#define I2S_FIFOWR48H_TXDATA_SHIFT (0U) +#define I2S_FIFOWR48H_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR48H_TXDATA_SHIFT)) & I2S_FIFOWR48H_TXDATA_MASK) +/*! @} */ + +/*! @name FIFORD - FIFO read data. */ +/*! @{ */ +#define I2S_FIFORD_RXDATA_MASK (0xFFFFFFFFU) +#define I2S_FIFORD_RXDATA_SHIFT (0U) +#define I2S_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD_RXDATA_SHIFT)) & I2S_FIFORD_RXDATA_MASK) +/*! @} */ + +/*! @name FIFORD48H - FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */ +/*! @{ */ +#define I2S_FIFORD48H_RXDATA_MASK (0xFFFFFFU) +#define I2S_FIFORD48H_RXDATA_SHIFT (0U) +#define I2S_FIFORD48H_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48H_RXDATA_SHIFT)) & I2S_FIFORD48H_RXDATA_MASK) +/*! @} */ + +/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */ +/*! @{ */ +#define I2S_FIFORDNOPOP_RXDATA_MASK (0xFFFFFFFFU) +#define I2S_FIFORDNOPOP_RXDATA_SHIFT (0U) +#define I2S_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORDNOPOP_RXDATA_SHIFT)) & I2S_FIFORDNOPOP_RXDATA_MASK) +/*! @} */ + +/*! @name FIFORD48HNOPOP - FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */ +/*! @{ */ +#define I2S_FIFORD48HNOPOP_RXDATA_MASK (0xFFFFFFU) +#define I2S_FIFORD48HNOPOP_RXDATA_SHIFT (0U) +#define I2S_FIFORD48HNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48HNOPOP_RXDATA_SHIFT)) & I2S_FIFORD48HNOPOP_RXDATA_MASK) +/*! @} */ + +/*! @name ID - I2S Module identification */ +/*! @{ */ +#define I2S_ID_Aperture_MASK (0xFFU) +#define I2S_ID_Aperture_SHIFT (0U) +#define I2S_ID_Aperture(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_Aperture_SHIFT)) & I2S_ID_Aperture_MASK) +#define I2S_ID_Minor_Rev_MASK (0xF00U) +#define I2S_ID_Minor_Rev_SHIFT (8U) +#define I2S_ID_Minor_Rev(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_Minor_Rev_SHIFT)) & I2S_ID_Minor_Rev_MASK) +#define I2S_ID_Major_Rev_MASK (0xF000U) +#define I2S_ID_Major_Rev_SHIFT (12U) +#define I2S_ID_Major_Rev(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_Major_Rev_SHIFT)) & I2S_ID_Major_Rev_MASK) +#define I2S_ID_ID_MASK (0xFFFF0000U) +#define I2S_ID_ID_SHIFT (16U) +#define I2S_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_ID_SHIFT)) & I2S_ID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group I2S_Register_Masks */ + + +/* I2S - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral I2S0 base address */ + #define I2S0_BASE (0x50086000u) + /** Peripheral I2S0 base address */ + #define I2S0_BASE_NS (0x40086000u) + /** Peripheral I2S0 base pointer */ + #define I2S0 ((I2S_Type *)I2S0_BASE) + /** Peripheral I2S0 base pointer */ + #define I2S0_NS ((I2S_Type *)I2S0_BASE_NS) + /** Peripheral I2S1 base address */ + #define I2S1_BASE (0x50087000u) + /** Peripheral I2S1 base address */ + #define I2S1_BASE_NS (0x40087000u) + /** Peripheral I2S1 base pointer */ + #define I2S1 ((I2S_Type *)I2S1_BASE) + /** Peripheral I2S1 base pointer */ + #define I2S1_NS ((I2S_Type *)I2S1_BASE_NS) + /** Peripheral I2S2 base address */ + #define I2S2_BASE (0x50088000u) + /** Peripheral I2S2 base address */ + #define I2S2_BASE_NS (0x40088000u) + /** Peripheral I2S2 base pointer */ + #define I2S2 ((I2S_Type *)I2S2_BASE) + /** Peripheral I2S2 base pointer */ + #define I2S2_NS ((I2S_Type *)I2S2_BASE_NS) + /** Peripheral I2S3 base address */ + #define I2S3_BASE (0x50089000u) + /** Peripheral I2S3 base address */ + #define I2S3_BASE_NS (0x40089000u) + /** Peripheral I2S3 base pointer */ + #define I2S3 ((I2S_Type *)I2S3_BASE) + /** Peripheral I2S3 base pointer */ + #define I2S3_NS ((I2S_Type *)I2S3_BASE_NS) + /** Peripheral I2S4 base address */ + #define I2S4_BASE (0x5008A000u) + /** Peripheral I2S4 base address */ + #define I2S4_BASE_NS (0x4008A000u) + /** Peripheral I2S4 base pointer */ + #define I2S4 ((I2S_Type *)I2S4_BASE) + /** Peripheral I2S4 base pointer */ + #define I2S4_NS ((I2S_Type *)I2S4_BASE_NS) + /** Peripheral I2S5 base address */ + #define I2S5_BASE (0x50096000u) + /** Peripheral I2S5 base address */ + #define I2S5_BASE_NS (0x40096000u) + /** Peripheral I2S5 base pointer */ + #define I2S5 ((I2S_Type *)I2S5_BASE) + /** Peripheral I2S5 base pointer */ + #define I2S5_NS ((I2S_Type *)I2S5_BASE_NS) + /** Peripheral I2S6 base address */ + #define I2S6_BASE (0x50097000u) + /** Peripheral I2S6 base address */ + #define I2S6_BASE_NS (0x40097000u) + /** Peripheral I2S6 base pointer */ + #define I2S6 ((I2S_Type *)I2S6_BASE) + /** Peripheral I2S6 base pointer */ + #define I2S6_NS ((I2S_Type *)I2S6_BASE_NS) + /** Peripheral I2S7 base address */ + #define I2S7_BASE (0x50098000u) + /** Peripheral I2S7 base address */ + #define I2S7_BASE_NS (0x40098000u) + /** Peripheral I2S7 base pointer */ + #define I2S7 ((I2S_Type *)I2S7_BASE) + /** Peripheral I2S7 base pointer */ + #define I2S7_NS ((I2S_Type *)I2S7_BASE_NS) + /** Array initializer of I2S peripheral base addresses */ + #define I2S_BASE_ADDRS { I2S0_BASE, I2S1_BASE, I2S2_BASE, I2S3_BASE, I2S4_BASE, I2S5_BASE, I2S6_BASE, I2S7_BASE } + /** Array initializer of I2S peripheral base pointers */ + #define I2S_BASE_PTRS { I2S0, I2S1, I2S2, I2S3, I2S4, I2S5, I2S6, I2S7 } + /** Array initializer of I2S peripheral base addresses */ + #define I2S_BASE_ADDRS_NS { I2S0_BASE_NS, I2S1_BASE_NS, I2S2_BASE_NS, I2S3_BASE_NS, I2S4_BASE_NS, I2S5_BASE_NS, I2S6_BASE_NS, I2S7_BASE_NS } + /** Array initializer of I2S peripheral base pointers */ + #define I2S_BASE_PTRS_NS { I2S0_NS, I2S1_NS, I2S2_NS, I2S3_NS, I2S4_NS, I2S5_NS, I2S6_NS, I2S7_NS } +#else + /** Peripheral I2S0 base address */ + #define I2S0_BASE (0x40086000u) + /** Peripheral I2S0 base pointer */ + #define I2S0 ((I2S_Type *)I2S0_BASE) + /** Peripheral I2S1 base address */ + #define I2S1_BASE (0x40087000u) + /** Peripheral I2S1 base pointer */ + #define I2S1 ((I2S_Type *)I2S1_BASE) + /** Peripheral I2S2 base address */ + #define I2S2_BASE (0x40088000u) + /** Peripheral I2S2 base pointer */ + #define I2S2 ((I2S_Type *)I2S2_BASE) + /** Peripheral I2S3 base address */ + #define I2S3_BASE (0x40089000u) + /** Peripheral I2S3 base pointer */ + #define I2S3 ((I2S_Type *)I2S3_BASE) + /** Peripheral I2S4 base address */ + #define I2S4_BASE (0x4008A000u) + /** Peripheral I2S4 base pointer */ + #define I2S4 ((I2S_Type *)I2S4_BASE) + /** Peripheral I2S5 base address */ + #define I2S5_BASE (0x40096000u) + /** Peripheral I2S5 base pointer */ + #define I2S5 ((I2S_Type *)I2S5_BASE) + /** Peripheral I2S6 base address */ + #define I2S6_BASE (0x40097000u) + /** Peripheral I2S6 base pointer */ + #define I2S6 ((I2S_Type *)I2S6_BASE) + /** Peripheral I2S7 base address */ + #define I2S7_BASE (0x40098000u) + /** Peripheral I2S7 base pointer */ + #define I2S7 ((I2S_Type *)I2S7_BASE) + /** Array initializer of I2S peripheral base addresses */ + #define I2S_BASE_ADDRS { I2S0_BASE, I2S1_BASE, I2S2_BASE, I2S3_BASE, I2S4_BASE, I2S5_BASE, I2S6_BASE, I2S7_BASE } + /** Array initializer of I2S peripheral base pointers */ + #define I2S_BASE_PTRS { I2S0, I2S1, I2S2, I2S3, I2S4, I2S5, I2S6, I2S7 } +#endif +/** Interrupt vectors for the I2S peripheral type */ +#define I2S_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } + +/*! + * @} + */ /* end of group I2S_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- INPUTMUX Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup INPUTMUX_Peripheral_Access_Layer INPUTMUX Peripheral Access Layer + * @{ + */ + +/** INPUTMUX - Register Layout Typedef */ +typedef struct { + __IO uint32_t SCT0_INMUX[7]; /**< Input mux register for SCT0 input, array offset: 0x0, array step: 0x4 */ + uint8_t RESERVED_0[4]; + __IO uint32_t TIMER0CAPTSEL[4]; /**< Capture select registers for TIMER0 inputs, array offset: 0x20, array step: 0x4 */ + uint8_t RESERVED_1[16]; + __IO uint32_t TIMER1CAPTSEL[4]; /**< Capture select registers for TIMER1 inputs, array offset: 0x40, array step: 0x4 */ + uint8_t RESERVED_2[16]; + __IO uint32_t TIMER2CAPTSEL[4]; /**< Capture select registers for TIMER2 inputs, array offset: 0x60, array step: 0x4 */ + uint8_t RESERVED_3[80]; + __IO uint32_t PINTSEL[8]; /**< Pin interrupt select register, array offset: 0xC0, array step: 0x4 */ + __IO uint32_t DMA0_ITRIG_INMUX[23]; /**< Trigger select register for DMA0 channel, array offset: 0xE0, array step: 0x4 */ + uint8_t RESERVED_4[36]; + __IO uint32_t DMA0_OTRIG_INMUX[4]; /**< DMA0 output trigger selection to become DMA0 trigger, array offset: 0x160, array step: 0x4 */ + uint8_t RESERVED_5[16]; + __IO uint32_t FREQMEAS_REF; /**< Selection for frequency measurement reference clock, offset: 0x180 */ + __IO uint32_t FREQMEAS_TARGET; /**< Selection for frequency measurement target clock, offset: 0x184 */ + uint8_t RESERVED_6[24]; + __IO uint32_t TIMER3CAPTSEL[4]; /**< Capture select registers for TIMER3 inputs, array offset: 0x1A0, array step: 0x4 */ + uint8_t RESERVED_7[16]; + __IO uint32_t TIMER4CAPTSEL[4]; /**< Capture select registers for TIMER4 inputs, array offset: 0x1C0, array step: 0x4 */ + uint8_t RESERVED_8[16]; + __IO uint32_t PINTSECSEL[2]; /**< Pin interrupt secure select register, array offset: 0x1E0, array step: 0x4 */ + uint8_t RESERVED_9[24]; + __IO uint32_t DMA1_ITRIG_INMUX[10]; /**< Trigger select register for DMA1 channel, array offset: 0x200, array step: 0x4 */ + uint8_t RESERVED_10[24]; + __IO uint32_t DMA1_OTRIG_INMUX[4]; /**< DMA1 output trigger selection to become DMA1 trigger, array offset: 0x240, array step: 0x4 */ + uint8_t RESERVED_11[1264]; + __IO uint32_t DMA0_REQ_ENA; /**< Enable DMA0 requests, offset: 0x740 */ + uint8_t RESERVED_12[4]; + __O uint32_t DMA0_REQ_ENA_SET; /**< Set one or several bits in DMA0_REQ_ENA register, offset: 0x748 */ + uint8_t RESERVED_13[4]; + __O uint32_t DMA0_REQ_ENA_CLR; /**< Clear one or several bits in DMA0_REQ_ENA register, offset: 0x750 */ + uint8_t RESERVED_14[12]; + __IO uint32_t DMA1_REQ_ENA; /**< Enable DMA1 requests, offset: 0x760 */ + uint8_t RESERVED_15[4]; + __O uint32_t DMA1_REQ_ENA_SET; /**< Set one or several bits in DMA1_REQ_ENA register, offset: 0x768 */ + uint8_t RESERVED_16[4]; + __O uint32_t DMA1_REQ_ENA_CLR; /**< Clear one or several bits in DMA1_REQ_ENA register, offset: 0x770 */ + uint8_t RESERVED_17[12]; + __IO uint32_t DMA0_ITRIG_ENA; /**< Enable DMA0 triggers, offset: 0x780 */ + uint8_t RESERVED_18[4]; + __O uint32_t DMA0_ITRIG_ENA_SET; /**< Set one or several bits in DMA0_ITRIG_ENA register, offset: 0x788 */ + uint8_t RESERVED_19[4]; + __O uint32_t DMA0_ITRIG_ENA_CLR; /**< Clear one or several bits in DMA0_ITRIG_ENA register, offset: 0x790 */ + uint8_t RESERVED_20[12]; + __IO uint32_t DMA1_ITRIG_ENA; /**< Enable DMA1 triggers, offset: 0x7A0 */ + uint8_t RESERVED_21[4]; + __O uint32_t DMA1_ITRIG_ENA_SET; /**< Set one or several bits in DMA1_ITRIG_ENA register, offset: 0x7A8 */ + uint8_t RESERVED_22[4]; + __O uint32_t DMA1_ITRIG_ENA_CLR; /**< Clear one or several bits in DMA1_ITRIG_ENA register, offset: 0x7B0 */ +} INPUTMUX_Type; + +/* ---------------------------------------------------------------------------- + -- INPUTMUX Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup INPUTMUX_Register_Masks INPUTMUX Register Masks + * @{ + */ + +/*! @name SCT0_INMUX - Input mux register for SCT0 input */ +/*! @{ */ +#define INPUTMUX_SCT0_INMUX_INP_N_MASK (0x1FU) +#define INPUTMUX_SCT0_INMUX_INP_N_SHIFT (0U) +/*! INP_N - Input number to SCT0 inputs 0 to 6.. + * 0b00000..SCT_GPI0 function selected from IOCON register + * 0b00001..SCT_GPI1 function selected from IOCON register + * 0b00010..SCT_GPI2 function selected from IOCON register + * 0b00011..SCT_GPI3 function selected from IOCON register + * 0b00100..SCT_GPI4 function selected from IOCON register + * 0b00101..SCT_GPI5 function selected from IOCON register + * 0b00110..SCT_GPI6 function selected from IOCON register + * 0b00111..SCT_GPI7 function selected from IOCON register + * 0b01000..T0_OUT0 ctimer 0 match[0] output + * 0b01001..T1_OUT0 ctimer 1 match[0] output + * 0b01010..T2_OUT0 ctimer 2 match[0] output + * 0b01011..T3_OUT0 ctimer 3 match[0] output + * 0b01100..T4_OUT0 ctimer 4 match[0] output + * 0b01101..ADC_IRQ interrupt request from ADC + * 0b01110..GPIOINT_BMATCH + * 0b01111..USB0_FRAME_TOGGLE + * 0b10000..USB1_FRAME_TOGGLE + * 0b10001..COMP_OUTPUT output from analog comparator + * 0b10010..I2S_SHARED_SCK[0] output from I2S pin sharing + * 0b10011..I2S_SHARED_SCK[1] output from I2S pin sharing + * 0b10100..I2S_SHARED_WS[0] output from I2S pin sharing + * 0b10101..I2S_SHARED_WS[1] output from I2S pin sharing + * 0b10110..ARM_TXEV interrupt event from cpu0 or cpu1 + * 0b10111..DEBUG_HALTED from cpu0 or cpu1 + * 0b11000-0b11111..None + */ +#define INPUTMUX_SCT0_INMUX_INP_N(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_SCT0_INMUX_INP_N_SHIFT)) & INPUTMUX_SCT0_INMUX_INP_N_MASK) +/*! @} */ + +/* The count of INPUTMUX_SCT0_INMUX */ +#define INPUTMUX_SCT0_INMUX_COUNT (7U) + +/*! @name TIMER0CAPTSEL - Capture select registers for TIMER0 inputs */ +/*! @{ */ +#define INPUTMUX_TIMER0CAPTSEL_CAPTSEL_MASK (0x1FU) +#define INPUTMUX_TIMER0CAPTSEL_CAPTSEL_SHIFT (0U) +/*! CAPTSEL - Input number to TIMER0 capture inputs 0 to 4 + * 0b00000..CT_INP0 function selected from IOCON register + * 0b00001..CT_INP1 function selected from IOCON register + * 0b00010..CT_INP2 function selected from IOCON register + * 0b00011..CT_INP3 function selected from IOCON register + * 0b00100..CT_INP4 function selected from IOCON register + * 0b00101..CT_INP5 function selected from IOCON register + * 0b00110..CT_INP6 function selected from IOCON register + * 0b00111..CT_INP7 function selected from IOCON register + * 0b01000..CT_INP8 function selected from IOCON register + * 0b01001..CT_INP9 function selected from IOCON register + * 0b01010..CT_INP10 function selected from IOCON register + * 0b01011..CT_INP11 function selected from IOCON register + * 0b01100..CT_INP12 function selected from IOCON register + * 0b01101..CT_INP13 function selected from IOCON register + * 0b01110..CT_INP14 function selected from IOCON register + * 0b01111..CT_INP15 function selected from IOCON register + * 0b10000..CT_INP16 function selected from IOCON register + * 0b10001..CT_INP17 function selected from IOCON register + * 0b10010..CT_INP18 function selected from IOCON register + * 0b10011..CT_INP19 function selected from IOCON register + * 0b10100..USB0_FRAME_TOGGLE + * 0b10101..USB1_FRAME_TOGGLE + * 0b10110..COMP_OUTPUT output from analog comparator + * 0b10111..I2S_SHARED_WS[0] output from I2S pin sharing + * 0b11000..I2S_SHARED_WS[1] output from I2S pin sharing + * 0b11001-0b11111..None + */ +#define INPUTMUX_TIMER0CAPTSEL_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER0CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER0CAPTSEL_CAPTSEL_MASK) +/*! @} */ + +/* The count of INPUTMUX_TIMER0CAPTSEL */ +#define INPUTMUX_TIMER0CAPTSEL_COUNT (4U) + +/*! @name TIMER1CAPTSEL - Capture select registers for TIMER1 inputs */ +/*! @{ */ +#define INPUTMUX_TIMER1CAPTSEL_CAPTSEL_MASK (0x1FU) +#define INPUTMUX_TIMER1CAPTSEL_CAPTSEL_SHIFT (0U) +/*! CAPTSEL - Input number to TIMER1 capture inputs 0 to 4 + * 0b00000..CT_INP0 function selected from IOCON register + * 0b00001..CT_INP1 function selected from IOCON register + * 0b00010..CT_INP2 function selected from IOCON register + * 0b00011..CT_INP3 function selected from IOCON register + * 0b00100..CT_INP4 function selected from IOCON register + * 0b00101..CT_INP5 function selected from IOCON register + * 0b00110..CT_INP6 function selected from IOCON register + * 0b00111..CT_INP7 function selected from IOCON register + * 0b01000..CT_INP8 function selected from IOCON register + * 0b01001..CT_INP9 function selected from IOCON register + * 0b01010..CT_INP10 function selected from IOCON register + * 0b01011..CT_INP11 function selected from IOCON register + * 0b01100..CT_INP12 function selected from IOCON register + * 0b01101..CT_INP13 function selected from IOCON register + * 0b01110..CT_INP14 function selected from IOCON register + * 0b01111..CT_INP15 function selected from IOCON register + * 0b10000..CT_INP16 function selected from IOCON register + * 0b10001..CT_INP17 function selected from IOCON register + * 0b10010..CT_INP18 function selected from IOCON register + * 0b10011..CT_INP19 function selected from IOCON register + * 0b10100..USB0_FRAME_TOGGLE + * 0b10101..USB1_FRAME_TOGGLE + * 0b10110..COMP_OUTPUT output from analog comparator + * 0b10111..I2S_SHARED_WS[0] output from I2S pin sharing + * 0b11000..I2S_SHARED_WS[1] output from I2S pin sharing + * 0b11001-0b11111..None + */ +#define INPUTMUX_TIMER1CAPTSEL_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER1CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER1CAPTSEL_CAPTSEL_MASK) +/*! @} */ + +/* The count of INPUTMUX_TIMER1CAPTSEL */ +#define INPUTMUX_TIMER1CAPTSEL_COUNT (4U) + +/*! @name TIMER2CAPTSEL - Capture select registers for TIMER2 inputs */ +/*! @{ */ +#define INPUTMUX_TIMER2CAPTSEL_CAPTSEL_MASK (0x1FU) +#define INPUTMUX_TIMER2CAPTSEL_CAPTSEL_SHIFT (0U) +/*! CAPTSEL - Input number to TIMER2 capture inputs 0 to 4 + * 0b00000..CT_INP0 function selected from IOCON register + * 0b00001..CT_INP1 function selected from IOCON register + * 0b00010..CT_INP2 function selected from IOCON register + * 0b00011..CT_INP3 function selected from IOCON register + * 0b00100..CT_INP4 function selected from IOCON register + * 0b00101..CT_INP5 function selected from IOCON register + * 0b00110..CT_INP6 function selected from IOCON register + * 0b00111..CT_INP7 function selected from IOCON register + * 0b01000..CT_INP8 function selected from IOCON register + * 0b01001..CT_INP9 function selected from IOCON register + * 0b01010..CT_INP10 function selected from IOCON register + * 0b01011..CT_INP11 function selected from IOCON register + * 0b01100..CT_INP12 function selected from IOCON register + * 0b01101..CT_INP13 function selected from IOCON register + * 0b01110..CT_INP14 function selected from IOCON register + * 0b01111..CT_INP15 function selected from IOCON register + * 0b10000..CT_INP16 function selected from IOCON register + * 0b10001..CT_INP17 function selected from IOCON register + * 0b10010..CT_INP18 function selected from IOCON register + * 0b10011..CT_INP19 function selected from IOCON register + * 0b10100..USB0_FRAME_TOGGLE + * 0b10101..USB1_FRAME_TOGGLE + * 0b10110..COMP_OUTPUT output from analog comparator + * 0b10111..I2S_SHARED_WS[0] output from I2S pin sharing + * 0b11000..I2S_SHARED_WS[1] output from I2S pin sharing + * 0b11001-0b11111..None + */ +#define INPUTMUX_TIMER2CAPTSEL_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER2CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER2CAPTSEL_CAPTSEL_MASK) +/*! @} */ + +/* The count of INPUTMUX_TIMER2CAPTSEL */ +#define INPUTMUX_TIMER2CAPTSEL_COUNT (4U) + +/*! @name PINTSEL - Pin interrupt select register */ +/*! @{ */ +#define INPUTMUX_PINTSEL_INTPIN_MASK (0x7FU) +#define INPUTMUX_PINTSEL_INTPIN_SHIFT (0U) +#define INPUTMUX_PINTSEL_INTPIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PINTSEL_INTPIN_SHIFT)) & INPUTMUX_PINTSEL_INTPIN_MASK) +/*! @} */ + +/* The count of INPUTMUX_PINTSEL */ +#define INPUTMUX_PINTSEL_COUNT (8U) + +/*! @name DMA0_ITRIG_INMUX - Trigger select register for DMA0 channel */ +/*! @{ */ +#define INPUTMUX_DMA0_ITRIG_INMUX_INP_MASK (0x1FU) +#define INPUTMUX_DMA0_ITRIG_INMUX_INP_SHIFT (0U) +/*! INP - Trigger input number (decimal value) for DMA channel n (n = 0 to 22). + * 0b00000..Pin interrupt 0 + * 0b00001..Pin interrupt 1 + * 0b00010..Pin interrupt 2 + * 0b00011..Pin interrupt 3 + * 0b00100..Timer CTIMER0 Match 0 + * 0b00101..Timer CTIMER0 Match 1 + * 0b00110..Timer CTIMER1 Match 0 + * 0b00111..Timer CTIMER1 Match 1 + * 0b01000..Timer CTIMER2 Match 0 + * 0b01001..Timer CTIMER2 Match 1 + * 0b01010..Timer CTIMER3 Match 0 + * 0b01011..Timer CTIMER3 Match 1 + * 0b01100..Timer CTIMER4 Match 0 + * 0b01101..Timer CTIMER4 Match 1 + * 0b01110..COMP_OUTPUT + * 0b01111..DMA0 output trigger mux 0 + * 0b10000..DMA0 output trigger mux 1 + * 0b10001..DMA0 output trigger mux 1 + * 0b10010..DMA0 output trigger mux 3 + * 0b10011..SCT0 DMA request 0 + * 0b10100..SCT0 DMA request 1 + * 0b10101..HASH DMA RX trigger + * 0b10110-0b11111..None + */ +#define INPUTMUX_DMA0_ITRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA0_ITRIG_INMUX_INP_MASK) +/*! @} */ + +/* The count of INPUTMUX_DMA0_ITRIG_INMUX */ +#define INPUTMUX_DMA0_ITRIG_INMUX_COUNT (23U) + +/*! @name DMA0_OTRIG_INMUX - DMA0 output trigger selection to become DMA0 trigger */ +/*! @{ */ +#define INPUTMUX_DMA0_OTRIG_INMUX_INP_MASK (0x1FU) +#define INPUTMUX_DMA0_OTRIG_INMUX_INP_SHIFT (0U) +#define INPUTMUX_DMA0_OTRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_OTRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA0_OTRIG_INMUX_INP_MASK) +/*! @} */ + +/* The count of INPUTMUX_DMA0_OTRIG_INMUX */ +#define INPUTMUX_DMA0_OTRIG_INMUX_COUNT (4U) + +/*! @name FREQMEAS_REF - Selection for frequency measurement reference clock */ +/*! @{ */ +#define INPUTMUX_FREQMEAS_REF_CLKIN_MASK (0x1FU) +#define INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT (0U) +#define INPUTMUX_FREQMEAS_REF_CLKIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_REF_CLKIN_MASK) +/*! @} */ + +/*! @name FREQMEAS_TARGET - Selection for frequency measurement target clock */ +/*! @{ */ +#define INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK (0x1FU) +#define INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT (0U) +#define INPUTMUX_FREQMEAS_TARGET_CLKIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK) +/*! @} */ + +/*! @name TIMER3CAPTSEL - Capture select registers for TIMER3 inputs */ +/*! @{ */ +#define INPUTMUX_TIMER3CAPTSEL_CAPTSEL_MASK (0x1FU) +#define INPUTMUX_TIMER3CAPTSEL_CAPTSEL_SHIFT (0U) +/*! CAPTSEL - Input number to TIMER3 capture inputs 0 to 4 + * 0b00000..CT_INP0 function selected from IOCON register + * 0b00001..CT_INP1 function selected from IOCON register + * 0b00010..CT_INP2 function selected from IOCON register + * 0b00011..CT_INP3 function selected from IOCON register + * 0b00100..CT_INP4 function selected from IOCON register + * 0b00101..CT_INP5 function selected from IOCON register + * 0b00110..CT_INP6 function selected from IOCON register + * 0b00111..CT_INP7 function selected from IOCON register + * 0b01000..CT_INP8 function selected from IOCON register + * 0b01001..CT_INP9 function selected from IOCON register + * 0b01010..CT_INP10 function selected from IOCON register + * 0b01011..CT_INP11 function selected from IOCON register + * 0b01100..CT_INP12 function selected from IOCON register + * 0b01101..CT_INP13 function selected from IOCON register + * 0b01110..CT_INP14 function selected from IOCON register + * 0b01111..CT_INP15 function selected from IOCON register + * 0b10000..CT_INP16 function selected from IOCON register + * 0b10001..CT_INP17 function selected from IOCON register + * 0b10010..CT_INP18 function selected from IOCON register + * 0b10011..CT_INP19 function selected from IOCON register + * 0b10100..USB0_FRAME_TOGGLE + * 0b10101..USB1_FRAME_TOGGLE + * 0b10110..COMP_OUTPUT output from analog comparator + * 0b10111..I2S_SHARED_WS[0] output from I2S pin sharing + * 0b11000..I2S_SHARED_WS[1] output from I2S pin sharing + * 0b11001-0b11111..None + */ +#define INPUTMUX_TIMER3CAPTSEL_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER3CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER3CAPTSEL_CAPTSEL_MASK) +/*! @} */ + +/* The count of INPUTMUX_TIMER3CAPTSEL */ +#define INPUTMUX_TIMER3CAPTSEL_COUNT (4U) + +/*! @name TIMER4CAPTSEL - Capture select registers for TIMER4 inputs */ +/*! @{ */ +#define INPUTMUX_TIMER4CAPTSEL_CAPTSEL_MASK (0x1FU) +#define INPUTMUX_TIMER4CAPTSEL_CAPTSEL_SHIFT (0U) +/*! CAPTSEL - Input number to TIMER4 capture inputs 0 to 4 + * 0b00000..CT_INP0 function selected from IOCON register + * 0b00001..CT_INP1 function selected from IOCON register + * 0b00010..CT_INP2 function selected from IOCON register + * 0b00011..CT_INP3 function selected from IOCON register + * 0b00100..CT_INP4 function selected from IOCON register + * 0b00101..CT_INP5 function selected from IOCON register + * 0b00110..CT_INP6 function selected from IOCON register + * 0b00111..CT_INP7 function selected from IOCON register + * 0b01000..CT_INP8 function selected from IOCON register + * 0b01001..CT_INP9 function selected from IOCON register + * 0b01010..CT_INP10 function selected from IOCON register + * 0b01011..CT_INP11 function selected from IOCON register + * 0b01100..CT_INP12 function selected from IOCON register + * 0b01101..CT_INP13 function selected from IOCON register + * 0b01110..CT_INP14 function selected from IOCON register + * 0b01111..CT_INP15 function selected from IOCON register + * 0b10000..CT_INP16 function selected from IOCON register + * 0b10001..CT_INP17 function selected from IOCON register + * 0b10010..CT_INP18 function selected from IOCON register + * 0b10011..CT_INP19 function selected from IOCON register + * 0b10100..USB0_FRAME_TOGGLE + * 0b10101..USB1_FRAME_TOGGLE + * 0b10110..COMP_OUTPUT output from analog comparator + * 0b10111..I2S_SHARED_WS[0] output from I2S pin sharing + * 0b11000..I2S_SHARED_WS[1] output from I2S pin sharing + * 0b11001-0b11111..None + */ +#define INPUTMUX_TIMER4CAPTSEL_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER4CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER4CAPTSEL_CAPTSEL_MASK) +/*! @} */ + +/* The count of INPUTMUX_TIMER4CAPTSEL */ +#define INPUTMUX_TIMER4CAPTSEL_COUNT (4U) + +/*! @name PINTSECSEL - Pin interrupt secure select register */ +/*! @{ */ +#define INPUTMUX_PINTSECSEL_INTPIN_MASK (0x3FU) +#define INPUTMUX_PINTSECSEL_INTPIN_SHIFT (0U) +#define INPUTMUX_PINTSECSEL_INTPIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PINTSECSEL_INTPIN_SHIFT)) & INPUTMUX_PINTSECSEL_INTPIN_MASK) +/*! @} */ + +/* The count of INPUTMUX_PINTSECSEL */ +#define INPUTMUX_PINTSECSEL_COUNT (2U) + +/*! @name DMA1_ITRIG_INMUX - Trigger select register for DMA1 channel */ +/*! @{ */ +#define INPUTMUX_DMA1_ITRIG_INMUX_INP_MASK (0xFU) +#define INPUTMUX_DMA1_ITRIG_INMUX_INP_SHIFT (0U) +/*! INP - Trigger input number (decimal value) for DMA channel n (n = 0 to 9). + * 0b0000..Pin interrupt 0 + * 0b0001..Pin interrupt 1 + * 0b0010..Pin interrupt 2 + * 0b0011..Pin interrupt 3 + * 0b0100..Timer CTIMER0 Match 0 + * 0b0101..Timer CTIMER0 Match 1 + * 0b0110..Timer CTIMER2 Match 0 + * 0b0111..Timer CTIMER4 Match 0 + * 0b1000..DMA1 output trigger mux 0 + * 0b1001..DMA1 output trigger mux 1 + * 0b1010..DMA1 output trigger mux 2 + * 0b1011..DMA1 output trigger mux 3 + * 0b1100..SCT0 DMA request 0 + * 0b1101..SCT0 DMA request 1 + * 0b1110..HASH DMA RX trigger + * 0b1111..None + */ +#define INPUTMUX_DMA1_ITRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA1_ITRIG_INMUX_INP_MASK) +/*! @} */ + +/* The count of INPUTMUX_DMA1_ITRIG_INMUX */ +#define INPUTMUX_DMA1_ITRIG_INMUX_COUNT (10U) + +/*! @name DMA1_OTRIG_INMUX - DMA1 output trigger selection to become DMA1 trigger */ +/*! @{ */ +#define INPUTMUX_DMA1_OTRIG_INMUX_INP_MASK (0xFU) +#define INPUTMUX_DMA1_OTRIG_INMUX_INP_SHIFT (0U) +#define INPUTMUX_DMA1_OTRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_OTRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA1_OTRIG_INMUX_INP_MASK) +/*! @} */ + +/* The count of INPUTMUX_DMA1_OTRIG_INMUX */ +#define INPUTMUX_DMA1_OTRIG_INMUX_COUNT (4U) + +/*! @name DMA0_REQ_ENA - Enable DMA0 requests */ +/*! @{ */ +#define INPUTMUX_DMA0_REQ_ENA_REQ_ENA_MASK (0x7FFFFFU) +#define INPUTMUX_DMA0_REQ_ENA_REQ_ENA_SHIFT (0U) +#define INPUTMUX_DMA0_REQ_ENA_REQ_ENA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENA_REQ_ENA_SHIFT)) & INPUTMUX_DMA0_REQ_ENA_REQ_ENA_MASK) +/*! @} */ + +/*! @name DMA0_REQ_ENA_SET - Set one or several bits in DMA0_REQ_ENA register */ +/*! @{ */ +#define INPUTMUX_DMA0_REQ_ENA_SET_SET_MASK (0x7FFFFFU) +#define INPUTMUX_DMA0_REQ_ENA_SET_SET_SHIFT (0U) +#define INPUTMUX_DMA0_REQ_ENA_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENA_SET_SET_SHIFT)) & INPUTMUX_DMA0_REQ_ENA_SET_SET_MASK) +/*! @} */ + +/*! @name DMA0_REQ_ENA_CLR - Clear one or several bits in DMA0_REQ_ENA register */ +/*! @{ */ +#define INPUTMUX_DMA0_REQ_ENA_CLR_CLR_MASK (0x7FFFFFU) +#define INPUTMUX_DMA0_REQ_ENA_CLR_CLR_SHIFT (0U) +#define INPUTMUX_DMA0_REQ_ENA_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENA_CLR_CLR_SHIFT)) & INPUTMUX_DMA0_REQ_ENA_CLR_CLR_MASK) +/*! @} */ + +/*! @name DMA1_REQ_ENA - Enable DMA1 requests */ +/*! @{ */ +#define INPUTMUX_DMA1_REQ_ENA_REQ_ENA_MASK (0x3FFU) +#define INPUTMUX_DMA1_REQ_ENA_REQ_ENA_SHIFT (0U) +#define INPUTMUX_DMA1_REQ_ENA_REQ_ENA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENA_REQ_ENA_SHIFT)) & INPUTMUX_DMA1_REQ_ENA_REQ_ENA_MASK) +/*! @} */ + +/*! @name DMA1_REQ_ENA_SET - Set one or several bits in DMA1_REQ_ENA register */ +/*! @{ */ +#define INPUTMUX_DMA1_REQ_ENA_SET_SET_MASK (0x3FFU) +#define INPUTMUX_DMA1_REQ_ENA_SET_SET_SHIFT (0U) +#define INPUTMUX_DMA1_REQ_ENA_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENA_SET_SET_SHIFT)) & INPUTMUX_DMA1_REQ_ENA_SET_SET_MASK) +/*! @} */ + +/*! @name DMA1_REQ_ENA_CLR - Clear one or several bits in DMA1_REQ_ENA register */ +/*! @{ */ +#define INPUTMUX_DMA1_REQ_ENA_CLR_CLR_MASK (0x3FFU) +#define INPUTMUX_DMA1_REQ_ENA_CLR_CLR_SHIFT (0U) +#define INPUTMUX_DMA1_REQ_ENA_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENA_CLR_CLR_SHIFT)) & INPUTMUX_DMA1_REQ_ENA_CLR_CLR_MASK) +/*! @} */ + +/*! @name DMA0_ITRIG_ENA - Enable DMA0 triggers */ +/*! @{ */ +#define INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA_MASK (0x3FFFFFU) +#define INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA_SHIFT (0U) +#define INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA_SHIFT)) & INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA_MASK) +/*! @} */ + +/*! @name DMA0_ITRIG_ENA_SET - Set one or several bits in DMA0_ITRIG_ENA register */ +/*! @{ */ +#define INPUTMUX_DMA0_ITRIG_ENA_SET_SET_MASK (0x3FFFFFU) +#define INPUTMUX_DMA0_ITRIG_ENA_SET_SET_SHIFT (0U) +#define INPUTMUX_DMA0_ITRIG_ENA_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIG_ENA_SET_SET_SHIFT)) & INPUTMUX_DMA0_ITRIG_ENA_SET_SET_MASK) +/*! @} */ + +/*! @name DMA0_ITRIG_ENA_CLR - Clear one or several bits in DMA0_ITRIG_ENA register */ +/*! @{ */ +#define INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR_MASK (0x3FFFFFU) +#define INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR_SHIFT (0U) +#define INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR_SHIFT)) & INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR_MASK) +/*! @} */ + +/*! @name DMA1_ITRIG_ENA - Enable DMA1 triggers */ +/*! @{ */ +#define INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA_MASK (0x7FFFU) +#define INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA_SHIFT (0U) +#define INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA_SHIFT)) & INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA_MASK) +/*! @} */ + +/*! @name DMA1_ITRIG_ENA_SET - Set one or several bits in DMA1_ITRIG_ENA register */ +/*! @{ */ +#define INPUTMUX_DMA1_ITRIG_ENA_SET_SET_MASK (0x7FFFU) +#define INPUTMUX_DMA1_ITRIG_ENA_SET_SET_SHIFT (0U) +#define INPUTMUX_DMA1_ITRIG_ENA_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIG_ENA_SET_SET_SHIFT)) & INPUTMUX_DMA1_ITRIG_ENA_SET_SET_MASK) +/*! @} */ + +/*! @name DMA1_ITRIG_ENA_CLR - Clear one or several bits in DMA1_ITRIG_ENA register */ +/*! @{ */ +#define INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR_MASK (0x7FFFU) +#define INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR_SHIFT (0U) +#define INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR_SHIFT)) & INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group INPUTMUX_Register_Masks */ + + +/* INPUTMUX - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral INPUTMUX base address */ + #define INPUTMUX_BASE (0x50006000u) + /** Peripheral INPUTMUX base address */ + #define INPUTMUX_BASE_NS (0x40006000u) + /** Peripheral INPUTMUX base pointer */ + #define INPUTMUX ((INPUTMUX_Type *)INPUTMUX_BASE) + /** Peripheral INPUTMUX base pointer */ + #define INPUTMUX_NS ((INPUTMUX_Type *)INPUTMUX_BASE_NS) + /** Array initializer of INPUTMUX peripheral base addresses */ + #define INPUTMUX_BASE_ADDRS { INPUTMUX_BASE } + /** Array initializer of INPUTMUX peripheral base pointers */ + #define INPUTMUX_BASE_PTRS { INPUTMUX } + /** Array initializer of INPUTMUX peripheral base addresses */ + #define INPUTMUX_BASE_ADDRS_NS { INPUTMUX_BASE_NS } + /** Array initializer of INPUTMUX peripheral base pointers */ + #define INPUTMUX_BASE_PTRS_NS { INPUTMUX_NS } +#else + /** Peripheral INPUTMUX base address */ + #define INPUTMUX_BASE (0x40006000u) + /** Peripheral INPUTMUX base pointer */ + #define INPUTMUX ((INPUTMUX_Type *)INPUTMUX_BASE) + /** Array initializer of INPUTMUX peripheral base addresses */ + #define INPUTMUX_BASE_ADDRS { INPUTMUX_BASE } + /** Array initializer of INPUTMUX peripheral base pointers */ + #define INPUTMUX_BASE_PTRS { INPUTMUX } +#endif + +/*! + * @} + */ /* end of group INPUTMUX_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- IOCON Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOCON_Peripheral_Access_Layer IOCON Peripheral Access Layer + * @{ + */ + +/** IOCON - Register Layout Typedef */ +typedef struct { + __IO uint32_t PIO[2][32]; /**< Digital I/O control for port 0 pins PIO0_0..Digital I/O control for port 1 pins PIO1_31, array offset: 0x0, array step: index*0x80, index2*0x4 */ +} IOCON_Type; + +/* ---------------------------------------------------------------------------- + -- IOCON Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOCON_Register_Masks IOCON Register Masks + * @{ + */ + +/*! @name PIO - Digital I/O control for port 0 pins PIO0_0..Digital I/O control for port 1 pins PIO1_31 */ +/*! @{ */ +#define IOCON_PIO_FUNC_MASK (0xFU) +#define IOCON_PIO_FUNC_SHIFT (0U) +/*! FUNC - Selects pin function. + * 0b0000..Alternative connection 0. + * 0b0001..Alternative connection 1. + * 0b0010..Alternative connection 2. + * 0b0011..Alternative connection 3. + * 0b0100..Alternative connection 4. + * 0b0101..Alternative connection 5. + * 0b0110..Alternative connection 6. + * 0b0111..Alternative connection 7. + */ +#define IOCON_PIO_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FUNC_SHIFT)) & IOCON_PIO_FUNC_MASK) +#define IOCON_PIO_MODE_MASK (0x30U) +#define IOCON_PIO_MODE_SHIFT (4U) +/*! MODE - Selects function mode (on-chip pull-up/pull-down resistor control). + * 0b00..Inactive. Inactive (no pull-down/pull-up resistor enabled). + * 0b01..Pull-down. Pull-down resistor enabled. + * 0b10..Pull-up. Pull-up resistor enabled. + * 0b11..Repeater. Repeater mode. + */ +#define IOCON_PIO_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_MODE_SHIFT)) & IOCON_PIO_MODE_MASK) +#define IOCON_PIO_SLEW_MASK (0x40U) +#define IOCON_PIO_SLEW_SHIFT (6U) +/*! SLEW - Driver slew rate. + * 0b0..Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + * 0b1..Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + */ +#define IOCON_PIO_SLEW(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_SLEW_SHIFT)) & IOCON_PIO_SLEW_MASK) +#define IOCON_PIO_INVERT_MASK (0x80U) +#define IOCON_PIO_INVERT_SHIFT (7U) +/*! INVERT - Input polarity. + * 0b0..Disabled. Input function is not inverted. + * 0b1..Enabled. Input is function inverted. + */ +#define IOCON_PIO_INVERT(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_INVERT_SHIFT)) & IOCON_PIO_INVERT_MASK) +#define IOCON_PIO_DIGIMODE_MASK (0x100U) +#define IOCON_PIO_DIGIMODE_SHIFT (8U) +/*! DIGIMODE - Select Digital mode. + * 0b0..Analog mode, digital input is disabled. + * 0b1..Digital mode, digital input is enabled. + */ +#define IOCON_PIO_DIGIMODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_DIGIMODE_SHIFT)) & IOCON_PIO_DIGIMODE_MASK) +#define IOCON_PIO_OD_MASK (0x200U) +#define IOCON_PIO_OD_SHIFT (9U) +/*! OD - Controls open-drain mode. + * 0b0..Normal. Normal push-pull output + * 0b1..Open-drain. Simulated open-drain output (high drive disabled). + */ +#define IOCON_PIO_OD(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_OD_SHIFT)) & IOCON_PIO_OD_MASK) +#define IOCON_PIO_ASW_MASK (0x400U) +#define IOCON_PIO_ASW_SHIFT (10U) +/*! ASW - Analog switch input control. Usable only if DIGIMODE = 0b0 + * 0b0..Analog switch is open. + * 0b1..Analog switch is closed. + */ +#define IOCON_PIO_ASW(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_ASW_SHIFT)) & IOCON_PIO_ASW_MASK) +#define IOCON_PIO_SSEL_MASK (0x800U) +#define IOCON_PIO_SSEL_SHIFT (11U) +/*! SSEL - Supply Selection bit. + * 0b0..3V3 Signaling in I2C Mode. + * 0b1..1V8 Signaling in I2C Mode. + */ +#define IOCON_PIO_SSEL(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_SSEL_SHIFT)) & IOCON_PIO_SSEL_MASK) +#define IOCON_PIO_FILTEROFF_MASK (0x1000U) +#define IOCON_PIO_FILTEROFF_SHIFT (12U) +/*! FILTEROFF - Controls input glitch filter. + * 0b0..Filter enabled. Noise pulses below approximately 10 ns are filtered out. + * 0b1..Filter disabled. No input filtering is done. + */ +#define IOCON_PIO_FILTEROFF(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FILTEROFF_SHIFT)) & IOCON_PIO_FILTEROFF_MASK) +#define IOCON_PIO_ECS_MASK (0x2000U) +#define IOCON_PIO_ECS_SHIFT (13U) +/*! ECS - Pull-up current source enable in IIC mode. + * 0b1..Enabled. Pull resistor is conencted. + * 0b0..Disabled. IO is in open drain. + */ +#define IOCON_PIO_ECS(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_ECS_SHIFT)) & IOCON_PIO_ECS_MASK) +#define IOCON_PIO_EGP_MASK (0x4000U) +#define IOCON_PIO_EGP_SHIFT (14U) +/*! EGP - Controls slew rate of I2C pad. + * 0b0..I2C mode. + * 0b1..GPIO mode. + */ +#define IOCON_PIO_EGP(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_EGP_SHIFT)) & IOCON_PIO_EGP_MASK) +#define IOCON_PIO_I2CFILTER_MASK (0x8000U) +#define IOCON_PIO_I2CFILTER_SHIFT (15U) +/*! I2CFILTER - Configures I2C features for standard mode, fast mode, and Fast Mode Plus operation. + * 0b0..I2C 50 ns glitch filter enabled. Typically used for Fast-mode and Fast-mode Plus I2C. + * 0b1..I2C 10 ns glitch filter enabled. Typically used for Standard-mode I2C. + */ +#define IOCON_PIO_I2CFILTER(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CFILTER_SHIFT)) & IOCON_PIO_I2CFILTER_MASK) +/*! @} */ + +/* The count of IOCON_PIO */ +#define IOCON_PIO_COUNT (2U) + +/* The count of IOCON_PIO */ +#define IOCON_PIO_COUNT2 (32U) + + +/*! + * @} + */ /* end of group IOCON_Register_Masks */ + + +/* IOCON - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral IOCON base address */ + #define IOCON_BASE (0x50001000u) + /** Peripheral IOCON base address */ + #define IOCON_BASE_NS (0x40001000u) + /** Peripheral IOCON base pointer */ + #define IOCON ((IOCON_Type *)IOCON_BASE) + /** Peripheral IOCON base pointer */ + #define IOCON_NS ((IOCON_Type *)IOCON_BASE_NS) + /** Array initializer of IOCON peripheral base addresses */ + #define IOCON_BASE_ADDRS { IOCON_BASE } + /** Array initializer of IOCON peripheral base pointers */ + #define IOCON_BASE_PTRS { IOCON } + /** Array initializer of IOCON peripheral base addresses */ + #define IOCON_BASE_ADDRS_NS { IOCON_BASE_NS } + /** Array initializer of IOCON peripheral base pointers */ + #define IOCON_BASE_PTRS_NS { IOCON_NS } +#else + /** Peripheral IOCON base address */ + #define IOCON_BASE (0x40001000u) + /** Peripheral IOCON base pointer */ + #define IOCON ((IOCON_Type *)IOCON_BASE) + /** Array initializer of IOCON peripheral base addresses */ + #define IOCON_BASE_ADDRS { IOCON_BASE } + /** Array initializer of IOCON peripheral base pointers */ + #define IOCON_BASE_PTRS { IOCON } +#endif + +/*! + * @} + */ /* end of group IOCON_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- MAILBOX Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MAILBOX_Peripheral_Access_Layer MAILBOX Peripheral Access Layer + * @{ + */ + +/** MAILBOX - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x10 */ + __IO uint32_t IRQ; /**< Interrupt request register for the Cortex-M0+ CPU., array offset: 0x0, array step: 0x10 */ + __O uint32_t IRQSET; /**< Set bits in IRQ0, array offset: 0x4, array step: 0x10 */ + __O uint32_t IRQCLR; /**< Clear bits in IRQ0, array offset: 0x8, array step: 0x10 */ + uint8_t RESERVED_0[4]; + } MBOXIRQ[2]; + uint8_t RESERVED_0[216]; + __IO uint32_t MUTEX; /**< Mutual exclusion register[1], offset: 0xF8 */ +} MAILBOX_Type; + +/* ---------------------------------------------------------------------------- + -- MAILBOX Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MAILBOX_Register_Masks MAILBOX Register Masks + * @{ + */ + +/*! @name MBOXIRQ_IRQ - Interrupt request register for the Cortex-M0+ CPU. */ +/*! @{ */ +#define MAILBOX_MBOXIRQ_IRQ_INTREQ_MASK (0xFFFFFFFFU) +#define MAILBOX_MBOXIRQ_IRQ_INTREQ_SHIFT (0U) +#define MAILBOX_MBOXIRQ_IRQ_INTREQ(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MBOXIRQ_IRQ_INTREQ_SHIFT)) & MAILBOX_MBOXIRQ_IRQ_INTREQ_MASK) +/*! @} */ + +/* The count of MAILBOX_MBOXIRQ_IRQ */ +#define MAILBOX_MBOXIRQ_IRQ_COUNT (2U) + +/*! @name MBOXIRQ_IRQSET - Set bits in IRQ0 */ +/*! @{ */ +#define MAILBOX_MBOXIRQ_IRQSET_INTREQSET_MASK (0xFFFFFFFFU) +#define MAILBOX_MBOXIRQ_IRQSET_INTREQSET_SHIFT (0U) +#define MAILBOX_MBOXIRQ_IRQSET_INTREQSET(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MBOXIRQ_IRQSET_INTREQSET_SHIFT)) & MAILBOX_MBOXIRQ_IRQSET_INTREQSET_MASK) +/*! @} */ + +/* The count of MAILBOX_MBOXIRQ_IRQSET */ +#define MAILBOX_MBOXIRQ_IRQSET_COUNT (2U) + +/*! @name MBOXIRQ_IRQCLR - Clear bits in IRQ0 */ +/*! @{ */ +#define MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_MASK (0xFFFFFFFFU) +#define MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_SHIFT (0U) +#define MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_SHIFT)) & MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_MASK) +/*! @} */ + +/* The count of MAILBOX_MBOXIRQ_IRQCLR */ +#define MAILBOX_MBOXIRQ_IRQCLR_COUNT (2U) + +/*! @name MUTEX - Mutual exclusion register[1] */ +/*! @{ */ +#define MAILBOX_MUTEX_EX_MASK (0x1U) +#define MAILBOX_MUTEX_EX_SHIFT (0U) +#define MAILBOX_MUTEX_EX(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MUTEX_EX_SHIFT)) & MAILBOX_MUTEX_EX_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group MAILBOX_Register_Masks */ + + +/* MAILBOX - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral MAILBOX base address */ + #define MAILBOX_BASE (0x5008B000u) + /** Peripheral MAILBOX base address */ + #define MAILBOX_BASE_NS (0x4008B000u) + /** Peripheral MAILBOX base pointer */ + #define MAILBOX ((MAILBOX_Type *)MAILBOX_BASE) + /** Peripheral MAILBOX base pointer */ + #define MAILBOX_NS ((MAILBOX_Type *)MAILBOX_BASE_NS) + /** Array initializer of MAILBOX peripheral base addresses */ + #define MAILBOX_BASE_ADDRS { MAILBOX_BASE } + /** Array initializer of MAILBOX peripheral base pointers */ + #define MAILBOX_BASE_PTRS { MAILBOX } + /** Array initializer of MAILBOX peripheral base addresses */ + #define MAILBOX_BASE_ADDRS_NS { MAILBOX_BASE_NS } + /** Array initializer of MAILBOX peripheral base pointers */ + #define MAILBOX_BASE_PTRS_NS { MAILBOX_NS } +#else + /** Peripheral MAILBOX base address */ + #define MAILBOX_BASE (0x4008B000u) + /** Peripheral MAILBOX base pointer */ + #define MAILBOX ((MAILBOX_Type *)MAILBOX_BASE) + /** Array initializer of MAILBOX peripheral base addresses */ + #define MAILBOX_BASE_ADDRS { MAILBOX_BASE } + /** Array initializer of MAILBOX peripheral base pointers */ + #define MAILBOX_BASE_PTRS { MAILBOX } +#endif +/** Interrupt vectors for the MAILBOX peripheral type */ +#define MAILBOX_IRQS { MAILBOX_IRQn } + +/*! + * @} + */ /* end of group MAILBOX_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- MRT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MRT_Peripheral_Access_Layer MRT Peripheral Access Layer + * @{ + */ + +/** MRT - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x10 */ + __IO uint32_t INTVAL; /**< MRT Time interval value register. This value is loaded into the TIMER register., array offset: 0x0, array step: 0x10 */ + __I uint32_t TIMER; /**< MRT Timer register. This register reads the value of the down-counter., array offset: 0x4, array step: 0x10 */ + __IO uint32_t CTRL; /**< MRT Control register. This register controls the MRT modes., array offset: 0x8, array step: 0x10 */ + __IO uint32_t STAT; /**< MRT Status register., array offset: 0xC, array step: 0x10 */ + } CHANNEL[4]; + uint8_t RESERVED_0[176]; + __IO uint32_t MODCFG; /**< Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature., offset: 0xF0 */ + __I uint32_t IDLE_CH; /**< Idle channel register. This register returns the number of the first idle channel., offset: 0xF4 */ + __IO uint32_t IRQ_FLAG; /**< Global interrupt flag register, offset: 0xF8 */ +} MRT_Type; + +/* ---------------------------------------------------------------------------- + -- MRT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MRT_Register_Masks MRT Register Masks + * @{ + */ + +/*! @name CHANNEL_INTVAL - MRT Time interval value register. This value is loaded into the TIMER register. */ +/*! @{ */ +#define MRT_CHANNEL_INTVAL_IVALUE_MASK (0xFFFFFFU) +#define MRT_CHANNEL_INTVAL_IVALUE_SHIFT (0U) +#define MRT_CHANNEL_INTVAL_IVALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_IVALUE_SHIFT)) & MRT_CHANNEL_INTVAL_IVALUE_MASK) +#define MRT_CHANNEL_INTVAL_LOAD_MASK (0x80000000U) +#define MRT_CHANNEL_INTVAL_LOAD_SHIFT (31U) +/*! LOAD - Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. + * This bit is write-only. Reading this bit always returns 0. + * 0b0..No force load. The load from the INTVALn register to the TIMERn register is processed at the end of the + * time interval if the repeat mode is selected. + * 0b1..Force load. The INTVALn interval value IVALUE -1 is immediately loaded into the TIMERn register while TIMERn is running. + */ +#define MRT_CHANNEL_INTVAL_LOAD(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_LOAD_SHIFT)) & MRT_CHANNEL_INTVAL_LOAD_MASK) +/*! @} */ + +/* The count of MRT_CHANNEL_INTVAL */ +#define MRT_CHANNEL_INTVAL_COUNT (4U) + +/*! @name CHANNEL_TIMER - MRT Timer register. This register reads the value of the down-counter. */ +/*! @{ */ +#define MRT_CHANNEL_TIMER_VALUE_MASK (0xFFFFFFU) +#define MRT_CHANNEL_TIMER_VALUE_SHIFT (0U) +#define MRT_CHANNEL_TIMER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_TIMER_VALUE_SHIFT)) & MRT_CHANNEL_TIMER_VALUE_MASK) +/*! @} */ + +/* The count of MRT_CHANNEL_TIMER */ +#define MRT_CHANNEL_TIMER_COUNT (4U) + +/*! @name CHANNEL_CTRL - MRT Control register. This register controls the MRT modes. */ +/*! @{ */ +#define MRT_CHANNEL_CTRL_INTEN_MASK (0x1U) +#define MRT_CHANNEL_CTRL_INTEN_SHIFT (0U) +/*! INTEN - Enable the TIMERn interrupt. + * 0b0..Disabled. TIMERn interrupt is disabled. + * 0b1..Enabled. TIMERn interrupt is enabled. + */ +#define MRT_CHANNEL_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_INTEN_SHIFT)) & MRT_CHANNEL_CTRL_INTEN_MASK) +#define MRT_CHANNEL_CTRL_MODE_MASK (0x6U) +#define MRT_CHANNEL_CTRL_MODE_SHIFT (1U) +/*! MODE - Selects timer mode. + * 0b00..Repeat interrupt mode. + * 0b01..One-shot interrupt mode. + * 0b10..One-shot stall mode. + * 0b11..Reserved. + */ +#define MRT_CHANNEL_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_MODE_SHIFT)) & MRT_CHANNEL_CTRL_MODE_MASK) +/*! @} */ + +/* The count of MRT_CHANNEL_CTRL */ +#define MRT_CHANNEL_CTRL_COUNT (4U) + +/*! @name CHANNEL_STAT - MRT Status register. */ +/*! @{ */ +#define MRT_CHANNEL_STAT_INTFLAG_MASK (0x1U) +#define MRT_CHANNEL_STAT_INTFLAG_SHIFT (0U) +/*! INTFLAG - Monitors the interrupt flag. + * 0b0..No pending interrupt. Writing a zero is equivalent to no operation. + * 0b1..Pending interrupt. The interrupt is pending because TIMERn has reached the end of the time interval. If + * the INTEN bit in the CONTROLn is also set to 1, the interrupt for timer channel n and the global interrupt + * are raised. Writing a 1 to this bit clears the interrupt request. + */ +#define MRT_CHANNEL_STAT_INTFLAG(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INTFLAG_SHIFT)) & MRT_CHANNEL_STAT_INTFLAG_MASK) +#define MRT_CHANNEL_STAT_RUN_MASK (0x2U) +#define MRT_CHANNEL_STAT_RUN_SHIFT (1U) +/*! RUN - Indicates the state of TIMERn. This bit is read-only. + * 0b0..Idle state. TIMERn is stopped. + * 0b1..Running. TIMERn is running. + */ +#define MRT_CHANNEL_STAT_RUN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_RUN_SHIFT)) & MRT_CHANNEL_STAT_RUN_MASK) +#define MRT_CHANNEL_STAT_INUSE_MASK (0x4U) +#define MRT_CHANNEL_STAT_INUSE_SHIFT (2U) +/*! INUSE - Channel In Use flag. Operating details depend on the MULTITASK bit in the MODCFG + * register, and affects the use of IDLE_CH. See Idle channel register for details of the two operating + * modes. + * 0b0..This channel is not in use. + * 0b1..This channel is in use. + */ +#define MRT_CHANNEL_STAT_INUSE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INUSE_SHIFT)) & MRT_CHANNEL_STAT_INUSE_MASK) +/*! @} */ + +/* The count of MRT_CHANNEL_STAT */ +#define MRT_CHANNEL_STAT_COUNT (4U) + +/*! @name MODCFG - Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature. */ +/*! @{ */ +#define MRT_MODCFG_NOC_MASK (0xFU) +#define MRT_MODCFG_NOC_SHIFT (0U) +#define MRT_MODCFG_NOC(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOC_SHIFT)) & MRT_MODCFG_NOC_MASK) +#define MRT_MODCFG_NOB_MASK (0x1F0U) +#define MRT_MODCFG_NOB_SHIFT (4U) +#define MRT_MODCFG_NOB(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOB_SHIFT)) & MRT_MODCFG_NOB_MASK) +#define MRT_MODCFG_MULTITASK_MASK (0x80000000U) +#define MRT_MODCFG_MULTITASK_SHIFT (31U) +/*! MULTITASK - Selects the operating mode for the INUSE flags and the IDLE_CH register. + * 0b0..Hardware status mode. In this mode, the INUSE(n) flags for all channels are reset. + * 0b1..Multi-task mode. + */ +#define MRT_MODCFG_MULTITASK(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_MULTITASK_SHIFT)) & MRT_MODCFG_MULTITASK_MASK) +/*! @} */ + +/*! @name IDLE_CH - Idle channel register. This register returns the number of the first idle channel. */ +/*! @{ */ +#define MRT_IDLE_CH_CHAN_MASK (0xF0U) +#define MRT_IDLE_CH_CHAN_SHIFT (4U) +#define MRT_IDLE_CH_CHAN(x) (((uint32_t)(((uint32_t)(x)) << MRT_IDLE_CH_CHAN_SHIFT)) & MRT_IDLE_CH_CHAN_MASK) +/*! @} */ + +/*! @name IRQ_FLAG - Global interrupt flag register */ +/*! @{ */ +#define MRT_IRQ_FLAG_GFLAG0_MASK (0x1U) +#define MRT_IRQ_FLAG_GFLAG0_SHIFT (0U) +/*! GFLAG0 - Monitors the interrupt flag of TIMER0. + * 0b0..No pending interrupt. Writing a zero is equivalent to no operation. + * 0b1..Pending interrupt. The interrupt is pending because TIMER0 has reached the end of the time interval. If + * the INTEN bit in the CONTROL0 register is also set to 1, the interrupt for timer channel 0 and the global + * interrupt are raised. Writing a 1 to this bit clears the interrupt request. + */ +#define MRT_IRQ_FLAG_GFLAG0(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG0_SHIFT)) & MRT_IRQ_FLAG_GFLAG0_MASK) +#define MRT_IRQ_FLAG_GFLAG1_MASK (0x2U) +#define MRT_IRQ_FLAG_GFLAG1_SHIFT (1U) +#define MRT_IRQ_FLAG_GFLAG1(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG1_SHIFT)) & MRT_IRQ_FLAG_GFLAG1_MASK) +#define MRT_IRQ_FLAG_GFLAG2_MASK (0x4U) +#define MRT_IRQ_FLAG_GFLAG2_SHIFT (2U) +#define MRT_IRQ_FLAG_GFLAG2(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG2_SHIFT)) & MRT_IRQ_FLAG_GFLAG2_MASK) +#define MRT_IRQ_FLAG_GFLAG3_MASK (0x8U) +#define MRT_IRQ_FLAG_GFLAG3_SHIFT (3U) +#define MRT_IRQ_FLAG_GFLAG3(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG3_SHIFT)) & MRT_IRQ_FLAG_GFLAG3_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group MRT_Register_Masks */ + + +/* MRT - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral MRT0 base address */ + #define MRT0_BASE (0x5000D000u) + /** Peripheral MRT0 base address */ + #define MRT0_BASE_NS (0x4000D000u) + /** Peripheral MRT0 base pointer */ + #define MRT0 ((MRT_Type *)MRT0_BASE) + /** Peripheral MRT0 base pointer */ + #define MRT0_NS ((MRT_Type *)MRT0_BASE_NS) + /** Array initializer of MRT peripheral base addresses */ + #define MRT_BASE_ADDRS { MRT0_BASE } + /** Array initializer of MRT peripheral base pointers */ + #define MRT_BASE_PTRS { MRT0 } + /** Array initializer of MRT peripheral base addresses */ + #define MRT_BASE_ADDRS_NS { MRT0_BASE_NS } + /** Array initializer of MRT peripheral base pointers */ + #define MRT_BASE_PTRS_NS { MRT0_NS } +#else + /** Peripheral MRT0 base address */ + #define MRT0_BASE (0x4000D000u) + /** Peripheral MRT0 base pointer */ + #define MRT0 ((MRT_Type *)MRT0_BASE) + /** Array initializer of MRT peripheral base addresses */ + #define MRT_BASE_ADDRS { MRT0_BASE } + /** Array initializer of MRT peripheral base pointers */ + #define MRT_BASE_PTRS { MRT0 } +#endif +/** Interrupt vectors for the MRT peripheral type */ +#define MRT_IRQS { MRT0_IRQn } + +/*! + * @} + */ /* end of group MRT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- OSTIMER Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OSTIMER_Peripheral_Access_Layer OSTIMER Peripheral Access Layer + * @{ + */ + +/** OSTIMER - Register Layout Typedef */ +typedef struct { + __I uint32_t EVTIMERL; /**< EVTIMER Low Register, offset: 0x0 */ + __I uint32_t EVTIMERH; /**< EVTIMER High Register, offset: 0x4 */ + __I uint32_t CAPTUREN_L; /**< Local Capture Low Register for CPUn, offset: 0x8 */ + __I uint32_t CAPTUREN_H; /**< Local Capture High Register for CPUn, offset: 0xC */ + __IO uint32_t MATCHN_L; /**< Local Match Low Register for CPUn, offset: 0x10 */ + __IO uint32_t MATCHN_H; /**< Match High Register for CPUn, offset: 0x14 */ + uint8_t RESERVED_0[4]; + __IO uint32_t OSEVENT_CTRL; /**< OS_EVENT TIMER Control Register for CPUn, offset: 0x1C */ +} OSTIMER_Type; + +/* ---------------------------------------------------------------------------- + -- OSTIMER Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OSTIMER_Register_Masks OSTIMER Register Masks + * @{ + */ + +/*! @name EVTIMERL - EVTIMER Low Register */ +/*! @{ */ +#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_MASK (0xFFFFFFFFU) +#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_SHIFT (0U) +#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_SHIFT)) & OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_MASK) +/*! @} */ + +/*! @name EVTIMERH - EVTIMER High Register */ +/*! @{ */ +#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_MASK (0xFFFFFFFFU) +#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_SHIFT (0U) +#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_SHIFT)) & OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_MASK) +/*! @} */ + +/*! @name CAPTUREN_L - Local Capture Low Register for CPUn */ +/*! @{ */ +#define OSTIMER_CAPTUREN_L_CAPTUREn_VALUE_MASK (0xFFFFFFFFU) +#define OSTIMER_CAPTUREN_L_CAPTUREn_VALUE_SHIFT (0U) +#define OSTIMER_CAPTUREN_L_CAPTUREn_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_CAPTUREN_L_CAPTUREn_VALUE_SHIFT)) & OSTIMER_CAPTUREN_L_CAPTUREn_VALUE_MASK) +/*! @} */ + +/*! @name CAPTUREN_H - Local Capture High Register for CPUn */ +/*! @{ */ +#define OSTIMER_CAPTUREN_H_CAPTUREn_VALUE_MASK (0xFFFFFFFFU) +#define OSTIMER_CAPTUREN_H_CAPTUREn_VALUE_SHIFT (0U) +#define OSTIMER_CAPTUREN_H_CAPTUREn_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_CAPTUREN_H_CAPTUREn_VALUE_SHIFT)) & OSTIMER_CAPTUREN_H_CAPTUREn_VALUE_MASK) +/*! @} */ + +/*! @name MATCHN_L - Local Match Low Register for CPUn */ +/*! @{ */ +#define OSTIMER_MATCHN_L_MATCHn_VALUE_MASK (0xFFFFFFFFU) +#define OSTIMER_MATCHN_L_MATCHn_VALUE_SHIFT (0U) +#define OSTIMER_MATCHN_L_MATCHn_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_MATCHN_L_MATCHn_VALUE_SHIFT)) & OSTIMER_MATCHN_L_MATCHn_VALUE_MASK) +/*! @} */ + +/*! @name MATCHN_H - Match High Register for CPUn */ +/*! @{ */ +#define OSTIMER_MATCHN_H_MATCHn_VALUE_MASK (0xFFFFFFFFU) +#define OSTIMER_MATCHN_H_MATCHn_VALUE_SHIFT (0U) +#define OSTIMER_MATCHN_H_MATCHn_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_MATCHN_H_MATCHn_VALUE_SHIFT)) & OSTIMER_MATCHN_H_MATCHn_VALUE_MASK) +/*! @} */ + +/*! @name OSEVENT_CTRL - OS_EVENT TIMER Control Register for CPUn */ +/*! @{ */ +#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK (0x1U) +#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_SHIFT (0U) +#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_SHIFT)) & OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK) +#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK (0x2U) +#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_SHIFT (1U) +#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_SHIFT)) & OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group OSTIMER_Register_Masks */ + + +/* OSTIMER - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral OSTIMER base address */ + #define OSTIMER_BASE (0x5002D000u) + /** Peripheral OSTIMER base address */ + #define OSTIMER_BASE_NS (0x4002D000u) + /** Peripheral OSTIMER base pointer */ + #define OSTIMER ((OSTIMER_Type *)OSTIMER_BASE) + /** Peripheral OSTIMER base pointer */ + #define OSTIMER_NS ((OSTIMER_Type *)OSTIMER_BASE_NS) + /** Array initializer of OSTIMER peripheral base addresses */ + #define OSTIMER_BASE_ADDRS { OSTIMER_BASE } + /** Array initializer of OSTIMER peripheral base pointers */ + #define OSTIMER_BASE_PTRS { OSTIMER } + /** Array initializer of OSTIMER peripheral base addresses */ + #define OSTIMER_BASE_ADDRS_NS { OSTIMER_BASE_NS } + /** Array initializer of OSTIMER peripheral base pointers */ + #define OSTIMER_BASE_PTRS_NS { OSTIMER_NS } +#else + /** Peripheral OSTIMER base address */ + #define OSTIMER_BASE (0x4002D000u) + /** Peripheral OSTIMER base pointer */ + #define OSTIMER ((OSTIMER_Type *)OSTIMER_BASE) + /** Array initializer of OSTIMER peripheral base addresses */ + #define OSTIMER_BASE_ADDRS { OSTIMER_BASE } + /** Array initializer of OSTIMER peripheral base pointers */ + #define OSTIMER_BASE_PTRS { OSTIMER } +#endif +/** Interrupt vectors for the OSTIMER peripheral type */ +#define OSTIMER_IRQS { OS_EVENT_IRQn } + +/*! + * @} + */ /* end of group OSTIMER_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PINT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PINT_Peripheral_Access_Layer PINT Peripheral Access Layer + * @{ + */ + +/** PINT - Register Layout Typedef */ +typedef struct { + __IO uint32_t ISEL; /**< Pin Interrupt Mode register, offset: 0x0 */ + __IO uint32_t IENR; /**< Pin interrupt level or rising edge interrupt enable register, offset: 0x4 */ + __O uint32_t SIENR; /**< Pin interrupt level or rising edge interrupt set register, offset: 0x8 */ + __O uint32_t CIENR; /**< Pin interrupt level (rising edge interrupt) clear register, offset: 0xC */ + __IO uint32_t IENF; /**< Pin interrupt active level or falling edge interrupt enable register, offset: 0x10 */ + __O uint32_t SIENF; /**< Pin interrupt active level or falling edge interrupt set register, offset: 0x14 */ + __O uint32_t CIENF; /**< Pin interrupt active level or falling edge interrupt clear register, offset: 0x18 */ + __IO uint32_t RISE; /**< Pin interrupt rising edge register, offset: 0x1C */ + __IO uint32_t FALL; /**< Pin interrupt falling edge register, offset: 0x20 */ + __IO uint32_t IST; /**< Pin interrupt status register, offset: 0x24 */ + __IO uint32_t PMCTRL; /**< Pattern match interrupt control register, offset: 0x28 */ + __IO uint32_t PMSRC; /**< Pattern match interrupt bit-slice source register, offset: 0x2C */ + __IO uint32_t PMCFG; /**< Pattern match interrupt bit slice configuration register, offset: 0x30 */ +} PINT_Type; + +/* ---------------------------------------------------------------------------- + -- PINT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PINT_Register_Masks PINT Register Masks + * @{ + */ + +/*! @name ISEL - Pin Interrupt Mode register */ +/*! @{ */ +#define PINT_ISEL_PMODE_MASK (0xFFU) +#define PINT_ISEL_PMODE_SHIFT (0U) +#define PINT_ISEL_PMODE(x) (((uint32_t)(((uint32_t)(x)) << PINT_ISEL_PMODE_SHIFT)) & PINT_ISEL_PMODE_MASK) +/*! @} */ + +/*! @name IENR - Pin interrupt level or rising edge interrupt enable register */ +/*! @{ */ +#define PINT_IENR_ENRL_MASK (0xFFU) +#define PINT_IENR_ENRL_SHIFT (0U) +#define PINT_IENR_ENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENR_ENRL_SHIFT)) & PINT_IENR_ENRL_MASK) +/*! @} */ + +/*! @name SIENR - Pin interrupt level or rising edge interrupt set register */ +/*! @{ */ +#define PINT_SIENR_SETENRL_MASK (0xFFU) +#define PINT_SIENR_SETENRL_SHIFT (0U) +#define PINT_SIENR_SETENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENR_SETENRL_SHIFT)) & PINT_SIENR_SETENRL_MASK) +/*! @} */ + +/*! @name CIENR - Pin interrupt level (rising edge interrupt) clear register */ +/*! @{ */ +#define PINT_CIENR_CENRL_MASK (0xFFU) +#define PINT_CIENR_CENRL_SHIFT (0U) +#define PINT_CIENR_CENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENR_CENRL_SHIFT)) & PINT_CIENR_CENRL_MASK) +/*! @} */ + +/*! @name IENF - Pin interrupt active level or falling edge interrupt enable register */ +/*! @{ */ +#define PINT_IENF_ENAF_MASK (0xFFU) +#define PINT_IENF_ENAF_SHIFT (0U) +#define PINT_IENF_ENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENF_ENAF_SHIFT)) & PINT_IENF_ENAF_MASK) +/*! @} */ + +/*! @name SIENF - Pin interrupt active level or falling edge interrupt set register */ +/*! @{ */ +#define PINT_SIENF_SETENAF_MASK (0xFFU) +#define PINT_SIENF_SETENAF_SHIFT (0U) +#define PINT_SIENF_SETENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENF_SETENAF_SHIFT)) & PINT_SIENF_SETENAF_MASK) +/*! @} */ + +/*! @name CIENF - Pin interrupt active level or falling edge interrupt clear register */ +/*! @{ */ +#define PINT_CIENF_CENAF_MASK (0xFFU) +#define PINT_CIENF_CENAF_SHIFT (0U) +#define PINT_CIENF_CENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENF_CENAF_SHIFT)) & PINT_CIENF_CENAF_MASK) +/*! @} */ + +/*! @name RISE - Pin interrupt rising edge register */ +/*! @{ */ +#define PINT_RISE_RDET_MASK (0xFFU) +#define PINT_RISE_RDET_SHIFT (0U) +#define PINT_RISE_RDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_RISE_RDET_SHIFT)) & PINT_RISE_RDET_MASK) +/*! @} */ + +/*! @name FALL - Pin interrupt falling edge register */ +/*! @{ */ +#define PINT_FALL_FDET_MASK (0xFFU) +#define PINT_FALL_FDET_SHIFT (0U) +#define PINT_FALL_FDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_FALL_FDET_SHIFT)) & PINT_FALL_FDET_MASK) +/*! @} */ + +/*! @name IST - Pin interrupt status register */ +/*! @{ */ +#define PINT_IST_PSTAT_MASK (0xFFU) +#define PINT_IST_PSTAT_SHIFT (0U) +#define PINT_IST_PSTAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_IST_PSTAT_SHIFT)) & PINT_IST_PSTAT_MASK) +/*! @} */ + +/*! @name PMCTRL - Pattern match interrupt control register */ +/*! @{ */ +#define PINT_PMCTRL_SEL_PMATCH_MASK (0x1U) +#define PINT_PMCTRL_SEL_PMATCH_SHIFT (0U) +/*! SEL_PMATCH - Specifies whether the 8 pin interrupts are controlled by the pin interrupt function or by the pattern match function. + * 0b0..Pin interrupt. Interrupts are driven in response to the standard pin interrupt function. + * 0b1..Pattern match. Interrupts are driven in response to pattern matches. + */ +#define PINT_PMCTRL_SEL_PMATCH(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_SEL_PMATCH_SHIFT)) & PINT_PMCTRL_SEL_PMATCH_MASK) +#define PINT_PMCTRL_ENA_RXEV_MASK (0x2U) +#define PINT_PMCTRL_ENA_RXEV_SHIFT (1U) +/*! ENA_RXEV - Enables the RXEV output to the CPU and/or to a GPIO output when the specified boolean expression evaluates to true. + * 0b0..Disabled. RXEV output to the CPU is disabled. + * 0b1..Enabled. RXEV output to the CPU is enabled. + */ +#define PINT_PMCTRL_ENA_RXEV(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_ENA_RXEV_SHIFT)) & PINT_PMCTRL_ENA_RXEV_MASK) +#define PINT_PMCTRL_PMAT_MASK (0xFF000000U) +#define PINT_PMCTRL_PMAT_SHIFT (24U) +#define PINT_PMCTRL_PMAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_PMAT_SHIFT)) & PINT_PMCTRL_PMAT_MASK) +/*! @} */ + +/*! @name PMSRC - Pattern match interrupt bit-slice source register */ +/*! @{ */ +#define PINT_PMSRC_SRC0_MASK (0x700U) +#define PINT_PMSRC_SRC0_SHIFT (8U) +/*! SRC0 - Selects the input source for bit slice 0 + * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 0. + * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 0. + * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 0. + * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 0. + * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 0. + * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 0. + * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 0. + * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 0. + */ +#define PINT_PMSRC_SRC0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC0_SHIFT)) & PINT_PMSRC_SRC0_MASK) +#define PINT_PMSRC_SRC1_MASK (0x3800U) +#define PINT_PMSRC_SRC1_SHIFT (11U) +/*! SRC1 - Selects the input source for bit slice 1 + * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 1. + * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 1. + * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 1. + * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 1. + * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 1. + * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 1. + * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 1. + * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 1. + */ +#define PINT_PMSRC_SRC1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC1_SHIFT)) & PINT_PMSRC_SRC1_MASK) +#define PINT_PMSRC_SRC2_MASK (0x1C000U) +#define PINT_PMSRC_SRC2_SHIFT (14U) +/*! SRC2 - Selects the input source for bit slice 2 + * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 2. + * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 2. + * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 2. + * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 2. + * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 2. + * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 2. + * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 2. + * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 2. + */ +#define PINT_PMSRC_SRC2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC2_SHIFT)) & PINT_PMSRC_SRC2_MASK) +#define PINT_PMSRC_SRC3_MASK (0xE0000U) +#define PINT_PMSRC_SRC3_SHIFT (17U) +/*! SRC3 - Selects the input source for bit slice 3 + * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 3. + * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 3. + * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 3. + * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 3. + * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 3. + * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 3. + * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 3. + * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 3. + */ +#define PINT_PMSRC_SRC3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC3_SHIFT)) & PINT_PMSRC_SRC3_MASK) +#define PINT_PMSRC_SRC4_MASK (0x700000U) +#define PINT_PMSRC_SRC4_SHIFT (20U) +/*! SRC4 - Selects the input source for bit slice 4 + * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 4. + * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 4. + * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 4. + * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 4. + * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 4. + * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 4. + * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 4. + * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 4. + */ +#define PINT_PMSRC_SRC4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC4_SHIFT)) & PINT_PMSRC_SRC4_MASK) +#define PINT_PMSRC_SRC5_MASK (0x3800000U) +#define PINT_PMSRC_SRC5_SHIFT (23U) +/*! SRC5 - Selects the input source for bit slice 5 + * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 5. + * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 5. + * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 5. + * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 5. + * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 5. + * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 5. + * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 5. + * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 5. + */ +#define PINT_PMSRC_SRC5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC5_SHIFT)) & PINT_PMSRC_SRC5_MASK) +#define PINT_PMSRC_SRC6_MASK (0x1C000000U) +#define PINT_PMSRC_SRC6_SHIFT (26U) +/*! SRC6 - Selects the input source for bit slice 6 + * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 6. + * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 6. + * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 6. + * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 6. + * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 6. + * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 6. + * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 6. + * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 6. + */ +#define PINT_PMSRC_SRC6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC6_SHIFT)) & PINT_PMSRC_SRC6_MASK) +#define PINT_PMSRC_SRC7_MASK (0xE0000000U) +#define PINT_PMSRC_SRC7_SHIFT (29U) +/*! SRC7 - Selects the input source for bit slice 7 + * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 7. + * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 7. + * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 7. + * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 7. + * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 7. + * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 7. + * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 7. + * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 7. + */ +#define PINT_PMSRC_SRC7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC7_SHIFT)) & PINT_PMSRC_SRC7_MASK) +/*! @} */ + +/*! @name PMCFG - Pattern match interrupt bit slice configuration register */ +/*! @{ */ +#define PINT_PMCFG_PROD_ENDPTS0_MASK (0x1U) +#define PINT_PMCFG_PROD_ENDPTS0_SHIFT (0U) +/*! PROD_ENDPTS0 - Determines whether slice 0 is an endpoint. + * 0b0..No effect. Slice 0 is not an endpoint. + * 0b1..endpoint. Slice 0 is the endpoint of a product term (minterm). Pin interrupt 0 in the NVIC is raised if the minterm evaluates as true. + */ +#define PINT_PMCFG_PROD_ENDPTS0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS0_SHIFT)) & PINT_PMCFG_PROD_ENDPTS0_MASK) +#define PINT_PMCFG_PROD_ENDPTS1_MASK (0x2U) +#define PINT_PMCFG_PROD_ENDPTS1_SHIFT (1U) +/*! PROD_ENDPTS1 - Determines whether slice 1 is an endpoint. + * 0b0..No effect. Slice 1 is not an endpoint. + * 0b1..endpoint. Slice 1 is the endpoint of a product term (minterm). Pin interrupt 1 in the NVIC is raised if the minterm evaluates as true. + */ +#define PINT_PMCFG_PROD_ENDPTS1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS1_SHIFT)) & PINT_PMCFG_PROD_ENDPTS1_MASK) +#define PINT_PMCFG_PROD_ENDPTS2_MASK (0x4U) +#define PINT_PMCFG_PROD_ENDPTS2_SHIFT (2U) +/*! PROD_ENDPTS2 - Determines whether slice 2 is an endpoint. + * 0b0..No effect. Slice 2 is not an endpoint. + * 0b1..endpoint. Slice 2 is the endpoint of a product term (minterm). Pin interrupt 2 in the NVIC is raised if the minterm evaluates as true. + */ +#define PINT_PMCFG_PROD_ENDPTS2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS2_SHIFT)) & PINT_PMCFG_PROD_ENDPTS2_MASK) +#define PINT_PMCFG_PROD_ENDPTS3_MASK (0x8U) +#define PINT_PMCFG_PROD_ENDPTS3_SHIFT (3U) +/*! PROD_ENDPTS3 - Determines whether slice 3 is an endpoint. + * 0b0..No effect. Slice 3 is not an endpoint. + * 0b1..endpoint. Slice 3 is the endpoint of a product term (minterm). Pin interrupt 3 in the NVIC is raised if the minterm evaluates as true. + */ +#define PINT_PMCFG_PROD_ENDPTS3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS3_SHIFT)) & PINT_PMCFG_PROD_ENDPTS3_MASK) +#define PINT_PMCFG_PROD_ENDPTS4_MASK (0x10U) +#define PINT_PMCFG_PROD_ENDPTS4_SHIFT (4U) +/*! PROD_ENDPTS4 - Determines whether slice 4 is an endpoint. + * 0b0..No effect. Slice 4 is not an endpoint. + * 0b1..endpoint. Slice 4 is the endpoint of a product term (minterm). Pin interrupt 4 in the NVIC is raised if the minterm evaluates as true. + */ +#define PINT_PMCFG_PROD_ENDPTS4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS4_SHIFT)) & PINT_PMCFG_PROD_ENDPTS4_MASK) +#define PINT_PMCFG_PROD_ENDPTS5_MASK (0x20U) +#define PINT_PMCFG_PROD_ENDPTS5_SHIFT (5U) +/*! PROD_ENDPTS5 - Determines whether slice 5 is an endpoint. + * 0b0..No effect. Slice 5 is not an endpoint. + * 0b1..endpoint. Slice 5 is the endpoint of a product term (minterm). Pin interrupt 5 in the NVIC is raised if the minterm evaluates as true. + */ +#define PINT_PMCFG_PROD_ENDPTS5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS5_SHIFT)) & PINT_PMCFG_PROD_ENDPTS5_MASK) +#define PINT_PMCFG_PROD_ENDPTS6_MASK (0x40U) +#define PINT_PMCFG_PROD_ENDPTS6_SHIFT (6U) +/*! PROD_ENDPTS6 - Determines whether slice 6 is an endpoint. + * 0b0..No effect. Slice 6 is not an endpoint. + * 0b1..endpoint. Slice 6 is the endpoint of a product term (minterm). Pin interrupt 6 in the NVIC is raised if the minterm evaluates as true. + */ +#define PINT_PMCFG_PROD_ENDPTS6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS6_SHIFT)) & PINT_PMCFG_PROD_ENDPTS6_MASK) +#define PINT_PMCFG_CFG0_MASK (0x700U) +#define PINT_PMCFG_CFG0_SHIFT (8U) +/*! CFG0 - Specifies the match contribution condition for bit slice 0. + * 0b000..Constant HIGH. This bit slice always contributes to a product term match. + * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input + * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only + * cleared when the PMCFG or the PMSRC registers are written to. + * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + * 0b101..Low level. Match occurs when there is a low level on the specified input. + * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or + * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit + * is cleared after one clock cycle. + */ +#define PINT_PMCFG_CFG0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG0_SHIFT)) & PINT_PMCFG_CFG0_MASK) +#define PINT_PMCFG_CFG1_MASK (0x3800U) +#define PINT_PMCFG_CFG1_SHIFT (11U) +/*! CFG1 - Specifies the match contribution condition for bit slice 1. + * 0b000..Constant HIGH. This bit slice always contributes to a product term match. + * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input + * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only + * cleared when the PMCFG or the PMSRC registers are written to. + * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + * 0b101..Low level. Match occurs when there is a low level on the specified input. + * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or + * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit + * is cleared after one clock cycle. + */ +#define PINT_PMCFG_CFG1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG1_SHIFT)) & PINT_PMCFG_CFG1_MASK) +#define PINT_PMCFG_CFG2_MASK (0x1C000U) +#define PINT_PMCFG_CFG2_SHIFT (14U) +/*! CFG2 - Specifies the match contribution condition for bit slice 2. + * 0b000..Constant HIGH. This bit slice always contributes to a product term match. + * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input + * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only + * cleared when the PMCFG or the PMSRC registers are written to. + * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + * 0b101..Low level. Match occurs when there is a low level on the specified input. + * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or + * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit + * is cleared after one clock cycle. + */ +#define PINT_PMCFG_CFG2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG2_SHIFT)) & PINT_PMCFG_CFG2_MASK) +#define PINT_PMCFG_CFG3_MASK (0xE0000U) +#define PINT_PMCFG_CFG3_SHIFT (17U) +/*! CFG3 - Specifies the match contribution condition for bit slice 3. + * 0b000..Constant HIGH. This bit slice always contributes to a product term match. + * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input + * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only + * cleared when the PMCFG or the PMSRC registers are written to. + * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + * 0b101..Low level. Match occurs when there is a low level on the specified input. + * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or + * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit + * is cleared after one clock cycle. + */ +#define PINT_PMCFG_CFG3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG3_SHIFT)) & PINT_PMCFG_CFG3_MASK) +#define PINT_PMCFG_CFG4_MASK (0x700000U) +#define PINT_PMCFG_CFG4_SHIFT (20U) +/*! CFG4 - Specifies the match contribution condition for bit slice 4. + * 0b000..Constant HIGH. This bit slice always contributes to a product term match. + * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input + * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only + * cleared when the PMCFG or the PMSRC registers are written to. + * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + * 0b101..Low level. Match occurs when there is a low level on the specified input. + * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or + * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit + * is cleared after one clock cycle. + */ +#define PINT_PMCFG_CFG4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG4_SHIFT)) & PINT_PMCFG_CFG4_MASK) +#define PINT_PMCFG_CFG5_MASK (0x3800000U) +#define PINT_PMCFG_CFG5_SHIFT (23U) +/*! CFG5 - Specifies the match contribution condition for bit slice 5. + * 0b000..Constant HIGH. This bit slice always contributes to a product term match. + * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input + * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only + * cleared when the PMCFG or the PMSRC registers are written to. + * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + * 0b101..Low level. Match occurs when there is a low level on the specified input. + * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or + * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit + * is cleared after one clock cycle. + */ +#define PINT_PMCFG_CFG5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG5_SHIFT)) & PINT_PMCFG_CFG5_MASK) +#define PINT_PMCFG_CFG6_MASK (0x1C000000U) +#define PINT_PMCFG_CFG6_SHIFT (26U) +/*! CFG6 - Specifies the match contribution condition for bit slice 6. + * 0b000..Constant HIGH. This bit slice always contributes to a product term match. + * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input + * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only + * cleared when the PMCFG or the PMSRC registers are written to. + * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + * 0b101..Low level. Match occurs when there is a low level on the specified input. + * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or + * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit + * is cleared after one clock cycle. + */ +#define PINT_PMCFG_CFG6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG6_SHIFT)) & PINT_PMCFG_CFG6_MASK) +#define PINT_PMCFG_CFG7_MASK (0xE0000000U) +#define PINT_PMCFG_CFG7_SHIFT (29U) +/*! CFG7 - Specifies the match contribution condition for bit slice 7. + * 0b000..Constant HIGH. This bit slice always contributes to a product term match. + * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input + * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only + * cleared when the PMCFG or the PMSRC registers are written to. + * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + * 0b101..Low level. Match occurs when there is a low level on the specified input. + * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or + * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit + * is cleared after one clock cycle. + */ +#define PINT_PMCFG_CFG7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG7_SHIFT)) & PINT_PMCFG_CFG7_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group PINT_Register_Masks */ + + +/* PINT - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral PINT base address */ + #define PINT_BASE (0x50004000u) + /** Peripheral PINT base address */ + #define PINT_BASE_NS (0x40004000u) + /** Peripheral PINT base pointer */ + #define PINT ((PINT_Type *)PINT_BASE) + /** Peripheral PINT base pointer */ + #define PINT_NS ((PINT_Type *)PINT_BASE_NS) + /** Peripheral SECPINT base address */ + #define SECPINT_BASE (0x50005000u) + /** Peripheral SECPINT base address */ + #define SECPINT_BASE_NS (0x40005000u) + /** Peripheral SECPINT base pointer */ + #define SECPINT ((PINT_Type *)SECPINT_BASE) + /** Peripheral SECPINT base pointer */ + #define SECPINT_NS ((PINT_Type *)SECPINT_BASE_NS) + /** Array initializer of PINT peripheral base addresses */ + #define PINT_BASE_ADDRS { PINT_BASE, SECPINT_BASE } + /** Array initializer of PINT peripheral base pointers */ + #define PINT_BASE_PTRS { PINT, SECPINT } + /** Array initializer of PINT peripheral base addresses */ + #define PINT_BASE_ADDRS_NS { PINT_BASE_NS, SECPINT_BASE_NS } + /** Array initializer of PINT peripheral base pointers */ + #define PINT_BASE_PTRS_NS { PINT_NS, SECPINT_NS } +#else + /** Peripheral PINT base address */ + #define PINT_BASE (0x40004000u) + /** Peripheral PINT base pointer */ + #define PINT ((PINT_Type *)PINT_BASE) + /** Peripheral SECPINT base address */ + #define SECPINT_BASE (0x40005000u) + /** Peripheral SECPINT base pointer */ + #define SECPINT ((PINT_Type *)SECPINT_BASE) + /** Array initializer of PINT peripheral base addresses */ + #define PINT_BASE_ADDRS { PINT_BASE, SECPINT_BASE } + /** Array initializer of PINT peripheral base pointers */ + #define PINT_BASE_PTRS { PINT, SECPINT } +#endif +/** Interrupt vectors for the PINT peripheral type */ +#define PINT_IRQS { PIN_INT0_IRQn, PIN_INT1_IRQn, PIN_INT2_IRQn, PIN_INT3_IRQn, PIN_INT4_IRQn, PIN_INT5_IRQn, PIN_INT6_IRQn, PIN_INT7_IRQn, SEC_GPIO_INT0_IRQ0_IRQn, SEC_GPIO_INT0_IRQ1_IRQn } + +/*! + * @} + */ /* end of group PINT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PLU Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PLU_Peripheral_Access_Layer PLU Peripheral Access Layer + * @{ + */ + +/** PLU - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x20 */ + __IO uint32_t INP[5]; /**< LUT0 input 0 MUX..LUT25 input 4 MUX, array offset: 0x0, array step: index*0x20, index2*0x4 */ + uint8_t RESERVED_0[12]; + } LUT[26]; + uint8_t RESERVED_0[1216]; + __IO uint32_t LUT_TRUTH[26]; /**< Specifies the Truth Table contents for LUT0..Specifies the Truth Table contents for LUT25, array offset: 0x800, array step: 0x4 */ + uint8_t RESERVED_1[152]; + __I uint32_t OUTPUTS; /**< Provides the current state of the 8 designated PLU Outputs., offset: 0x900 */ + __IO uint32_t WAKEINT; /**< Wakeup interrupt control for PLU, offset: 0x904 */ + uint8_t RESERVED_2[760]; + __IO uint32_t OUTPUT_MUX[8]; /**< Selects the source to be connected to PLU Output 0..Selects the source to be connected to PLU Output 7, array offset: 0xC00, array step: 0x4 */ +} PLU_Type; + +/* ---------------------------------------------------------------------------- + -- PLU Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PLU_Register_Masks PLU Register Masks + * @{ + */ + +/*! @name LUT_INP - LUT0 input 0 MUX..LUT25 input 4 MUX */ +/*! @{ */ +#define PLU_LUT_INP_LUT_INP_MASK (0x3FU) +#define PLU_LUT_INP_LUT_INP_SHIFT (0U) +/*! LUT_INP - Selects the input source to be connected to LUT25 input4. + * 0b000000..The PLU primary inputs 0. + * 0b000001..The PLU primary inputs 1. + * 0b000010..The PLU primary inputs 2. + * 0b000011..The PLU primary inputs 3. + * 0b000100..The PLU primary inputs 4. + * 0b000101..The PLU primary inputs 5. + * 0b000110..Tie low. + * 0b000111..The output of LUT1. + * 0b001000..The output of LUT2. + * 0b001001..The output of LUT3. + * 0b001010..The output of LUT4. + * 0b001011..The output of LUT5. + * 0b001100..The output of LUT6. + * 0b001101..The output of LUT7. + * 0b001110..The output of LUT8. + * 0b001111..The output of LUT9. + * 0b010000..The output of LUT10. + * 0b010001..The output of LUT11. + * 0b010010..The output of LUT12. + * 0b010011..The output of LUT13. + * 0b010100..The output of LUT14. + * 0b010101..The output of LUT15. + * 0b010110..The output of LUT16. + * 0b010111..The output of LUT17. + * 0b011000..The output of LUT18. + * 0b011001..The output of LUT19. + * 0b011010..The output of LUT20. + * 0b011011..The output of LUT21. + * 0b011100..The output of LUT22. + * 0b011101..The output of LUT23. + * 0b011110..The output of LUT24. + * 0b011111..The output of LUT25. + * 0b100000..state(0). + * 0b100001..state(1). + * 0b100010..state(2). + * 0b100011..state(3). + */ +#define PLU_LUT_INP_LUT_INP(x) (((uint32_t)(((uint32_t)(x)) << PLU_LUT_INP_LUT_INP_SHIFT)) & PLU_LUT_INP_LUT_INP_MASK) +/*! @} */ + +/* The count of PLU_LUT_INP */ +#define PLU_LUT_INP_COUNT (26U) + +/* The count of PLU_LUT_INP */ +#define PLU_LUT_INP_COUNT2 (5U) + +/*! @name LUT_T_LUT_TRUTH - Specifies the Truth Table contents for LUT0..Specifies the Truth Table contents for LUT25 */ +/*! @{ */ +#define PLU_LUT_T_LUT_TRUTH_TRUTH_TABLE_MASK (0xFFFFFFFFU) +#define PLU_LUT_T_LUT_TRUTH_TRUTH_TABLE_SHIFT (0U) +#define PLU_LUT_T_LUT_TRUTH_TRUTH_TABLE(x) (((uint32_t)(((uint32_t)(x)) << PLU_LUT_T_LUT_TRUTH_TRUTH_TABLE_SHIFT)) & PLU_LUT_T_LUT_TRUTH_TRUTH_TABLE_MASK) +/*! @} */ + +/* The count of PLU_LUT_T_LUT_TRUTH */ +#define PLU_LUT_T_LUT_TRUTH_COUNT (26U) + +/*! @name OUTPUTS - Provides the current state of the 8 designated PLU Outputs. */ +/*! @{ */ +#define PLU_OUTPUTS_OUTPUT_STATE_MASK (0xFFU) +#define PLU_OUTPUTS_OUTPUT_STATE_SHIFT (0U) +#define PLU_OUTPUTS_OUTPUT_STATE(x) (((uint32_t)(((uint32_t)(x)) << PLU_OUTPUTS_OUTPUT_STATE_SHIFT)) & PLU_OUTPUTS_OUTPUT_STATE_MASK) +/*! @} */ + +/*! @name WAKEINT - Wakeup interrupt control for PLU */ +/*! @{ */ +#define PLU_WAKEINT_MASK_MASK (0xFFU) +#define PLU_WAKEINT_MASK_SHIFT (0U) +#define PLU_WAKEINT_MASK(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_MASK_SHIFT)) & PLU_WAKEINT_MASK_MASK) +#define PLU_WAKEINT_FILTER_MODE_MASK (0x300U) +#define PLU_WAKEINT_FILTER_MODE_SHIFT (8U) +/*! FILTER_MODE - control input of the PLU, add filtering for glitch + * 0b00..Bypass mode. + * 0b01..Filter 1 clock period. + * 0b10..Filter 2 clock period. + * 0b11..Filter 3 clock period. + */ +#define PLU_WAKEINT_FILTER_MODE(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_FILTER_MODE_SHIFT)) & PLU_WAKEINT_FILTER_MODE_MASK) +#define PLU_WAKEINT_FILTER_CLKSEL_MASK (0xC00U) +#define PLU_WAKEINT_FILTER_CLKSEL_SHIFT (10U) +#define PLU_WAKEINT_FILTER_CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_FILTER_CLKSEL_SHIFT)) & PLU_WAKEINT_FILTER_CLKSEL_MASK) +#define PLU_WAKEINT_LATCH_ENABLE_MASK (0x1000U) +#define PLU_WAKEINT_LATCH_ENABLE_SHIFT (12U) +#define PLU_WAKEINT_LATCH_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_LATCH_ENABLE_SHIFT)) & PLU_WAKEINT_LATCH_ENABLE_MASK) +#define PLU_WAKEINT_INTR_CLEAR_MASK (0x2000U) +#define PLU_WAKEINT_INTR_CLEAR_SHIFT (13U) +#define PLU_WAKEINT_INTR_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_INTR_CLEAR_SHIFT)) & PLU_WAKEINT_INTR_CLEAR_MASK) +/*! @} */ + +/*! @name OUTPUT_MUX - Selects the source to be connected to PLU Output 0..Selects the source to be connected to PLU Output 7 */ +/*! @{ */ +#define PLU_OUTPUT_MUX_OUTPUTn_MASK (0x1FU) +#define PLU_OUTPUT_MUX_OUTPUTn_SHIFT (0U) +/*! OUTPUTn - Selects the source to be connected to PLU Output 7. + * 0b00000..The PLU output 0. + * 0b00001..The PLU output 1. + * 0b00010..The PLU output 2. + * 0b00011..The PLU output 3. + * 0b00100..The PLU output 4. + * 0b00101..The PLU output 5. + * 0b00110..The PLU output 6. + * 0b00111..The PLU output 7. + * 0b01000..The PLU output 8. + * 0b01001..The PLU output 9. + * 0b01010..The PLU output 10. + * 0b01011..The PLU output 11. + * 0b01100..The PLU output 12. + * 0b01101..The PLU output 13. + * 0b01110..The PLU output 14. + * 0b01111..The PLU output 15. + * 0b10000..The PLU output 16. + * 0b10001..The PLU output 17. + * 0b10010..The PLU output 18. + * 0b10011..The PLU output 19. + * 0b10100..The PLU output 20. + * 0b10101..The PLU output 21. + * 0b10110..The PLU output 22. + * 0b10111..The PLU output 23. + * 0b11000..The PLU output 24. + * 0b11001..The PLU output 25. + * 0b11010..state(0). + * 0b11011..state(1). + * 0b11100..state(2). + * 0b11101..state(3). + */ +#define PLU_OUTPUT_MUX_OUTPUTn(x) (((uint32_t)(((uint32_t)(x)) << PLU_OUTPUT_MUX_OUTPUTn_SHIFT)) & PLU_OUTPUT_MUX_OUTPUTn_MASK) +/*! @} */ + +/* The count of PLU_OUTPUT_MUX */ +#define PLU_OUTPUT_MUX_COUNT (8U) + + +/*! + * @} + */ /* end of group PLU_Register_Masks */ + + +/* PLU - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral PLU base address */ + #define PLU_BASE (0x5003D000u) + /** Peripheral PLU base address */ + #define PLU_BASE_NS (0x4003D000u) + /** Peripheral PLU base pointer */ + #define PLU ((PLU_Type *)PLU_BASE) + /** Peripheral PLU base pointer */ + #define PLU_NS ((PLU_Type *)PLU_BASE_NS) + /** Array initializer of PLU peripheral base addresses */ + #define PLU_BASE_ADDRS { PLU_BASE } + /** Array initializer of PLU peripheral base pointers */ + #define PLU_BASE_PTRS { PLU } + /** Array initializer of PLU peripheral base addresses */ + #define PLU_BASE_ADDRS_NS { PLU_BASE_NS } + /** Array initializer of PLU peripheral base pointers */ + #define PLU_BASE_PTRS_NS { PLU_NS } +#else + /** Peripheral PLU base address */ + #define PLU_BASE (0x4003D000u) + /** Peripheral PLU base pointer */ + #define PLU ((PLU_Type *)PLU_BASE) + /** Array initializer of PLU peripheral base addresses */ + #define PLU_BASE_ADDRS { PLU_BASE } + /** Array initializer of PLU peripheral base pointers */ + #define PLU_BASE_PTRS { PLU } +#endif + +/*! + * @} + */ /* end of group PLU_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PMC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer + * @{ + */ + +/** PMC - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[8]; + __IO uint32_t RESETCTRL; /**< Reset Control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x8 */ + __IO uint32_t RESETCAUSE; /**< Reset Cause register [Reset by: PoR], offset: 0xC */ + uint8_t RESERVED_1[32]; + __IO uint32_t BODVBAT; /**< VBAT Brown Out Dectector (BoD) control register [Reset by: PoR, Pin Reset, Software Reset], offset: 0x30 */ + uint8_t RESERVED_2[4]; + __IO uint32_t BODCORE; /**< Digital Core logic Brown Out Dectector control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x38 */ + uint8_t RESERVED_3[8]; + __IO uint32_t FRO1M; /**< 1 MHz Free Running Oscillator control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x44 */ + __IO uint32_t FRO32K; /**< 32 KHz Free Running Oscillator (FRO) control register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x48 */ + __IO uint32_t XTAL32K; /**< 32 KHz Crystal oscillator (XTAL) control register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x4C */ + __IO uint32_t COMP; /**< Analog Comparator control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x50 */ + uint8_t RESERVED_4[20]; + __IO uint32_t WAKEIOCAUSE; /**< Allows to identify the Wake-up I/O source from Deep Power Down mode, offset: 0x68 */ + uint8_t RESERVED_5[8]; + __IO uint32_t STATUSCLK; /**< FRO and XTAL status register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x74 */ + uint8_t RESERVED_6[12]; + __IO uint32_t AOREG1; /**< General purpose always on domain data storage [Reset by: PoR, Brown Out Detectors Reset], offset: 0x84 */ + uint8_t RESERVED_7[16]; + __IO uint32_t RTCOSC32K; /**< RTC 1 KHZ and 1 Hz clocks source control register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x98 */ + __IO uint32_t OSTIMERr; /**< OS Timer control register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x9C */ + uint8_t RESERVED_8[16]; + __IO uint32_t PDSLEEPCFG0; /**< Controls the power to various modules during Low Power modes - DEEP SLEEP, POWER DOWN and DEEP POWER DOWN [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Software Reset], offset: 0xB0 */ + uint8_t RESERVED_9[4]; + __IO uint32_t PDRUNCFG0; /**< Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0xB8 */ + uint8_t RESERVED_10[4]; + __O uint32_t PDRUNCFGSET0; /**< Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0xC0 */ + uint8_t RESERVED_11[4]; + __O uint32_t PDRUNCFGCLR0; /**< Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0xC8 */ +} PMC_Type; + +/* ---------------------------------------------------------------------------- + -- PMC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PMC_Register_Masks PMC Register Masks + * @{ + */ + +/*! @name RESETCTRL - Reset Control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ +/*! @{ */ +#define PMC_RESETCTRL_DPDWAKEUPRESETENABLE_MASK (0x1U) +#define PMC_RESETCTRL_DPDWAKEUPRESETENABLE_SHIFT (0U) +/*! DPDWAKEUPRESETENABLE - Wake-up from DEEP POWER DOWN reset event (either from wake up I/O or RTC or OS Event Timer). + * 0b0..Reset event from DEEP POWER DOWN mode is disable. + * 0b1..Reset event from DEEP POWER DOWN mode is enable. + */ +#define PMC_RESETCTRL_DPDWAKEUPRESETENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_DPDWAKEUPRESETENABLE_SHIFT)) & PMC_RESETCTRL_DPDWAKEUPRESETENABLE_MASK) +#define PMC_RESETCTRL_BODVBATRESETENABLE_MASK (0x2U) +#define PMC_RESETCTRL_BODVBATRESETENABLE_SHIFT (1U) +/*! BODVBATRESETENABLE - BOD VBAT reset enable. + * 0b0..BOD VBAT reset is disable. + * 0b1..BOD VBAT reset is enable. + */ +#define PMC_RESETCTRL_BODVBATRESETENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_BODVBATRESETENABLE_SHIFT)) & PMC_RESETCTRL_BODVBATRESETENABLE_MASK) +#define PMC_RESETCTRL_BODCORERESETENABLE_MASK (0x4U) +#define PMC_RESETCTRL_BODCORERESETENABLE_SHIFT (2U) +/*! BODCORERESETENABLE - BOD CORE reset enable. + * 0b0..BOD CORE reset is disable. + * 0b1..BOD CORE reset is enable. + */ +#define PMC_RESETCTRL_BODCORERESETENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_BODCORERESETENABLE_SHIFT)) & PMC_RESETCTRL_BODCORERESETENABLE_MASK) +#define PMC_RESETCTRL_SWRRESETENABLE_MASK (0x8U) +#define PMC_RESETCTRL_SWRRESETENABLE_SHIFT (3U) +/*! SWRRESETENABLE - Software reset enable. + * 0b0..Software reset is disable. + * 0b1..Software reset is enable. + */ +#define PMC_RESETCTRL_SWRRESETENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_SWRRESETENABLE_SHIFT)) & PMC_RESETCTRL_SWRRESETENABLE_MASK) +/*! @} */ + +/*! @name RESETCAUSE - Reset Cause register [Reset by: PoR] */ +/*! @{ */ +#define PMC_RESETCAUSE_POR_MASK (0x1U) +#define PMC_RESETCAUSE_POR_SHIFT (0U) +#define PMC_RESETCAUSE_POR(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_POR_SHIFT)) & PMC_RESETCAUSE_POR_MASK) +#define PMC_RESETCAUSE_PADRESET_MASK (0x2U) +#define PMC_RESETCAUSE_PADRESET_SHIFT (1U) +#define PMC_RESETCAUSE_PADRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_PADRESET_SHIFT)) & PMC_RESETCAUSE_PADRESET_MASK) +#define PMC_RESETCAUSE_BODRESET_MASK (0x4U) +#define PMC_RESETCAUSE_BODRESET_SHIFT (2U) +#define PMC_RESETCAUSE_BODRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_BODRESET_SHIFT)) & PMC_RESETCAUSE_BODRESET_MASK) +#define PMC_RESETCAUSE_SYSTEMRESET_MASK (0x8U) +#define PMC_RESETCAUSE_SYSTEMRESET_SHIFT (3U) +#define PMC_RESETCAUSE_SYSTEMRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_SYSTEMRESET_SHIFT)) & PMC_RESETCAUSE_SYSTEMRESET_MASK) +#define PMC_RESETCAUSE_WDTRESET_MASK (0x10U) +#define PMC_RESETCAUSE_WDTRESET_SHIFT (4U) +#define PMC_RESETCAUSE_WDTRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_WDTRESET_SHIFT)) & PMC_RESETCAUSE_WDTRESET_MASK) +#define PMC_RESETCAUSE_SWRRESET_MASK (0x20U) +#define PMC_RESETCAUSE_SWRRESET_SHIFT (5U) +#define PMC_RESETCAUSE_SWRRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_SWRRESET_SHIFT)) & PMC_RESETCAUSE_SWRRESET_MASK) +#define PMC_RESETCAUSE_DPDRESET_WAKEUPIO_MASK (0x40U) +#define PMC_RESETCAUSE_DPDRESET_WAKEUPIO_SHIFT (6U) +#define PMC_RESETCAUSE_DPDRESET_WAKEUPIO(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_DPDRESET_WAKEUPIO_SHIFT)) & PMC_RESETCAUSE_DPDRESET_WAKEUPIO_MASK) +#define PMC_RESETCAUSE_DPDRESET_RTC_MASK (0x80U) +#define PMC_RESETCAUSE_DPDRESET_RTC_SHIFT (7U) +#define PMC_RESETCAUSE_DPDRESET_RTC(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_DPDRESET_RTC_SHIFT)) & PMC_RESETCAUSE_DPDRESET_RTC_MASK) +#define PMC_RESETCAUSE_DPDRESET_OSTIMER_MASK (0x100U) +#define PMC_RESETCAUSE_DPDRESET_OSTIMER_SHIFT (8U) +#define PMC_RESETCAUSE_DPDRESET_OSTIMER(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_DPDRESET_OSTIMER_SHIFT)) & PMC_RESETCAUSE_DPDRESET_OSTIMER_MASK) +/*! @} */ + +/*! @name BODVBAT - VBAT Brown Out Dectector (BoD) control register [Reset by: PoR, Pin Reset, Software Reset] */ +/*! @{ */ +#define PMC_BODVBAT_TRIGLVL_MASK (0x1FU) +#define PMC_BODVBAT_TRIGLVL_SHIFT (0U) +/*! TRIGLVL - BoD trigger level. + * 0b00000..1.00 V. + * 0b00001..1.10 V. + * 0b00010..1.20 V. + * 0b00011..1.30 V. + * 0b00100..1.40 V. + * 0b00101..1.50 V. + * 0b00110..1.60 V. + * 0b00111..1.65 V. + * 0b01000..1.70 V. + * 0b01001..1.75 V. + * 0b01010..1.80 V. + * 0b01011..1.90 V. + * 0b01100..2.00 V. + * 0b01101..2.10 V. + * 0b01110..2.20 V. + * 0b01111..2.30 V. + * 0b10000..2.40 V. + * 0b10001..2.50 V. + * 0b10010..2.60 V. + * 0b10011..2.70 V. + * 0b10100..2.806 V. + * 0b10101..2.90 V. + * 0b10110..3.00 V. + * 0b10111..3.10 V. + * 0b11000..3.20 V. + * 0b11001..3.30 V. + * 0b11010..3.30 V. + * 0b11011..3.30 V. + * 0b11100..3.30 V. + * 0b11101..3.30 V. + * 0b11110..3.30 V. + * 0b11111..3.30 V. + */ +#define PMC_BODVBAT_TRIGLVL(x) (((uint32_t)(((uint32_t)(x)) << PMC_BODVBAT_TRIGLVL_SHIFT)) & PMC_BODVBAT_TRIGLVL_MASK) +#define PMC_BODVBAT_HYST_MASK (0x60U) +#define PMC_BODVBAT_HYST_SHIFT (5U) +/*! HYST - BoD Hysteresis control. + * 0b00..25 mV. + * 0b01..50 mV. + * 0b10..75 mV. + * 0b11..100 mV. + */ +#define PMC_BODVBAT_HYST(x) (((uint32_t)(((uint32_t)(x)) << PMC_BODVBAT_HYST_SHIFT)) & PMC_BODVBAT_HYST_MASK) +/*! @} */ + +/*! @name BODCORE - Digital Core logic Brown Out Dectector control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ +/*! @{ */ +#define PMC_BODCORE_TRIGLVL_MASK (0x7U) +#define PMC_BODCORE_TRIGLVL_SHIFT (0U) +/*! TRIGLVL - BoD trigger level. + * 0b000..0.60 V. + * 0b001..0.65 V. + * 0b010..0.70 V. + * 0b011..0.75 V. + * 0b100..0.80 V. + * 0b101..0.85 V. + * 0b110..0.90 V. + * 0b111..0.95 V. + */ +#define PMC_BODCORE_TRIGLVL(x) (((uint32_t)(((uint32_t)(x)) << PMC_BODCORE_TRIGLVL_SHIFT)) & PMC_BODCORE_TRIGLVL_MASK) +#define PMC_BODCORE_HYST_MASK (0x30U) +#define PMC_BODCORE_HYST_SHIFT (4U) +/*! HYST - BoD Core Hysteresis control. + * 0b00..25 mV. + * 0b01..50 mV. + * 0b10..75 mV. + * 0b11..100 mV. + */ +#define PMC_BODCORE_HYST(x) (((uint32_t)(((uint32_t)(x)) << PMC_BODCORE_HYST_SHIFT)) & PMC_BODCORE_HYST_MASK) +/*! @} */ + +/*! @name FRO1M - 1 MHz Free Running Oscillator control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ +/*! @{ */ +#define PMC_FRO1M_FREQSEL_MASK (0x7FU) +#define PMC_FRO1M_FREQSEL_SHIFT (0U) +#define PMC_FRO1M_FREQSEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_FRO1M_FREQSEL_SHIFT)) & PMC_FRO1M_FREQSEL_MASK) +#define PMC_FRO1M_ATBCTRL_MASK (0x180U) +#define PMC_FRO1M_ATBCTRL_SHIFT (7U) +#define PMC_FRO1M_ATBCTRL(x) (((uint32_t)(((uint32_t)(x)) << PMC_FRO1M_ATBCTRL_SHIFT)) & PMC_FRO1M_ATBCTRL_MASK) +#define PMC_FRO1M_DIVSEL_MASK (0x3E00U) +#define PMC_FRO1M_DIVSEL_SHIFT (9U) +/*! DIVSEL - Divider selection bits. + * 0b00000..2.0. + * 0b00001..4.0. + * 0b00010..6.0. + * 0b00011..8.0. + * 0b00100..10.0. + * 0b00101..12.0. + * 0b00110..14.0. + * 0b00111..16.0. + * 0b01000..18.0. + * 0b01001..20.0. + * 0b01010..22.0. + * 0b01011..24.0. + * 0b01100..26.0. + * 0b01101..28.0. + * 0b01110..30.0. + * 0b01111..32.0. + * 0b10000..34.0. + * 0b10001..36.0. + * 0b10010..38.0. + * 0b10011..40.0. + * 0b10100..42.0. + * 0b10101..44.0. + * 0b10110..46.0. + * 0b10111..48.0. + * 0b11000..50.0. + * 0b11001..52.0. + * 0b11010..54.0. + * 0b11011..56.0. + * 0b11100..58.0. + * 0b11101..60.0. + * 0b11110..62.0. + * 0b11111..1.0. + */ +#define PMC_FRO1M_DIVSEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_FRO1M_DIVSEL_SHIFT)) & PMC_FRO1M_DIVSEL_MASK) +/*! @} */ + +/*! @name FRO32K - 32 KHz Free Running Oscillator (FRO) control register [Reset by: PoR, Brown Out Detectors Reset] */ +/*! @{ */ +#define PMC_FRO32K_NTAT_MASK (0xEU) +#define PMC_FRO32K_NTAT_SHIFT (1U) +#define PMC_FRO32K_NTAT(x) (((uint32_t)(((uint32_t)(x)) << PMC_FRO32K_NTAT_SHIFT)) & PMC_FRO32K_NTAT_MASK) +#define PMC_FRO32K_PTAT_MASK (0x70U) +#define PMC_FRO32K_PTAT_SHIFT (4U) +#define PMC_FRO32K_PTAT(x) (((uint32_t)(((uint32_t)(x)) << PMC_FRO32K_PTAT_SHIFT)) & PMC_FRO32K_PTAT_MASK) +#define PMC_FRO32K_CAPCAL_MASK (0xFF80U) +#define PMC_FRO32K_CAPCAL_SHIFT (7U) +#define PMC_FRO32K_CAPCAL(x) (((uint32_t)(((uint32_t)(x)) << PMC_FRO32K_CAPCAL_SHIFT)) & PMC_FRO32K_CAPCAL_MASK) +#define PMC_FRO32K_ATBCTRL_MASK (0x30000U) +#define PMC_FRO32K_ATBCTRL_SHIFT (16U) +#define PMC_FRO32K_ATBCTRL(x) (((uint32_t)(((uint32_t)(x)) << PMC_FRO32K_ATBCTRL_SHIFT)) & PMC_FRO32K_ATBCTRL_MASK) +/*! @} */ + +/*! @name XTAL32K - 32 KHz Crystal oscillator (XTAL) control register [Reset by: PoR, Brown Out Detectors Reset] */ +/*! @{ */ +#define PMC_XTAL32K_IREF_MASK (0x6U) +#define PMC_XTAL32K_IREF_SHIFT (1U) +#define PMC_XTAL32K_IREF(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_IREF_SHIFT)) & PMC_XTAL32K_IREF_MASK) +#define PMC_XTAL32K_TEST_MASK (0x8U) +#define PMC_XTAL32K_TEST_SHIFT (3U) +#define PMC_XTAL32K_TEST(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_TEST_SHIFT)) & PMC_XTAL32K_TEST_MASK) +#define PMC_XTAL32K_IBIAS_MASK (0x30U) +#define PMC_XTAL32K_IBIAS_SHIFT (4U) +#define PMC_XTAL32K_IBIAS(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_IBIAS_SHIFT)) & PMC_XTAL32K_IBIAS_MASK) +#define PMC_XTAL32K_AMPL_MASK (0xC0U) +#define PMC_XTAL32K_AMPL_SHIFT (6U) +#define PMC_XTAL32K_AMPL(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_AMPL_SHIFT)) & PMC_XTAL32K_AMPL_MASK) +#define PMC_XTAL32K_CAPBANKIN_MASK (0x7F00U) +#define PMC_XTAL32K_CAPBANKIN_SHIFT (8U) +#define PMC_XTAL32K_CAPBANKIN(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPBANKIN_SHIFT)) & PMC_XTAL32K_CAPBANKIN_MASK) +#define PMC_XTAL32K_CAPBANKOUT_MASK (0x3F8000U) +#define PMC_XTAL32K_CAPBANKOUT_SHIFT (15U) +#define PMC_XTAL32K_CAPBANKOUT(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPBANKOUT_SHIFT)) & PMC_XTAL32K_CAPBANKOUT_MASK) +#define PMC_XTAL32K_CAPTESTSTARTSRCSEL_MASK (0x400000U) +#define PMC_XTAL32K_CAPTESTSTARTSRCSEL_SHIFT (22U) +/*! CAPTESTSTARTSRCSEL - Source selection for xo32k_captest_start_ao_set. + * 0b0..Sourced from CAPTESTSTART. + * 0b1..Sourced from calibration. + */ +#define PMC_XTAL32K_CAPTESTSTARTSRCSEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPTESTSTARTSRCSEL_SHIFT)) & PMC_XTAL32K_CAPTESTSTARTSRCSEL_MASK) +#define PMC_XTAL32K_CAPTESTSTART_MASK (0x800000U) +#define PMC_XTAL32K_CAPTESTSTART_SHIFT (23U) +#define PMC_XTAL32K_CAPTESTSTART(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPTESTSTART_SHIFT)) & PMC_XTAL32K_CAPTESTSTART_MASK) +#define PMC_XTAL32K_CAPTESTENABLE_MASK (0x1000000U) +#define PMC_XTAL32K_CAPTESTENABLE_SHIFT (24U) +#define PMC_XTAL32K_CAPTESTENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPTESTENABLE_SHIFT)) & PMC_XTAL32K_CAPTESTENABLE_MASK) +#define PMC_XTAL32K_CAPTESTOSCINSEL_MASK (0x2000000U) +#define PMC_XTAL32K_CAPTESTOSCINSEL_SHIFT (25U) +/*! CAPTESTOSCINSEL - Select the input for test. + * 0b0..Oscillator output pin (osc_out). + * 0b1..Oscillator input pin (osc_in). + */ +#define PMC_XTAL32K_CAPTESTOSCINSEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPTESTOSCINSEL_SHIFT)) & PMC_XTAL32K_CAPTESTOSCINSEL_MASK) +/*! @} */ + +/*! @name COMP - Analog Comparator control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ +/*! @{ */ +#define PMC_COMP_HYST_MASK (0x2U) +#define PMC_COMP_HYST_SHIFT (1U) +/*! HYST - Hysteris when hyst = '1'. + * 0b0..Hysteresis is disable. + * 0b1..Hysteresis is enable. + */ +#define PMC_COMP_HYST(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_HYST_SHIFT)) & PMC_COMP_HYST_MASK) +#define PMC_COMP_VREFINPUT_MASK (0x4U) +#define PMC_COMP_VREFINPUT_SHIFT (2U) +/*! VREFINPUT - Dedicated control bit to select between internal VREF and VDDA (for the resistive ladder). + * 0b0..Select internal VREF. + * 0b1..Select VDDA. + */ +#define PMC_COMP_VREFINPUT(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_VREFINPUT_SHIFT)) & PMC_COMP_VREFINPUT_MASK) +#define PMC_COMP_LOWPOWER_MASK (0x8U) +#define PMC_COMP_LOWPOWER_SHIFT (3U) +/*! LOWPOWER - Low power mode. + * 0b0..High speed mode. + * 0b1..Low power mode (Low speed). + */ +#define PMC_COMP_LOWPOWER(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_LOWPOWER_SHIFT)) & PMC_COMP_LOWPOWER_MASK) +#define PMC_COMP_PMUX_MASK (0x70U) +#define PMC_COMP_PMUX_SHIFT (4U) +/*! PMUX - Control word for P multiplexer:. + * 0b000..VREF (See fiedl VREFINPUT). + * 0b001..Pin P0_0. + * 0b010..Pin P0_9. + * 0b011..Pin P0_18. + * 0b100..Pin P1_14. + * 0b101..Pin P2_23. + */ +#define PMC_COMP_PMUX(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_PMUX_SHIFT)) & PMC_COMP_PMUX_MASK) +#define PMC_COMP_NMUX_MASK (0x380U) +#define PMC_COMP_NMUX_SHIFT (7U) +/*! NMUX - Control word for N multiplexer:. + * 0b000..VREF (See field VREFINPUT). + * 0b001..Pin P0_0. + * 0b010..Pin P0_9. + * 0b011..Pin P0_18. + * 0b100..Pin P1_14. + * 0b101..Pin P2_23. + */ +#define PMC_COMP_NMUX(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_NMUX_SHIFT)) & PMC_COMP_NMUX_MASK) +#define PMC_COMP_VREF_MASK (0x7C00U) +#define PMC_COMP_VREF_SHIFT (10U) +#define PMC_COMP_VREF(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_VREF_SHIFT)) & PMC_COMP_VREF_MASK) +#define PMC_COMP_FILTERCGF_SAMPLEMODE_MASK (0x30000U) +#define PMC_COMP_FILTERCGF_SAMPLEMODE_SHIFT (16U) +#define PMC_COMP_FILTERCGF_SAMPLEMODE(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_FILTERCGF_SAMPLEMODE_SHIFT)) & PMC_COMP_FILTERCGF_SAMPLEMODE_MASK) +#define PMC_COMP_FILTERCGF_CLKDIV_MASK (0x1C0000U) +#define PMC_COMP_FILTERCGF_CLKDIV_SHIFT (18U) +#define PMC_COMP_FILTERCGF_CLKDIV(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_FILTERCGF_CLKDIV_SHIFT)) & PMC_COMP_FILTERCGF_CLKDIV_MASK) +#define PMC_COMP_PMUXCAPT_MASK (0xE00000U) +#define PMC_COMP_PMUXCAPT_SHIFT (21U) +#define PMC_COMP_PMUXCAPT(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_PMUXCAPT_SHIFT)) & PMC_COMP_PMUXCAPT_MASK) +/*! @} */ + +/*! @name WAKEIOCAUSE - Allows to identify the Wake-up I/O source from Deep Power Down mode */ +/*! @{ */ +#define PMC_WAKEIOCAUSE_WAKEUP0_MASK (0x1U) +#define PMC_WAKEIOCAUSE_WAKEUP0_SHIFT (0U) +/*! WAKEUP0 - Allows to identify Wake up I/O 0 as the wake-up source from Deep Power Down mode. + * 0b0..Last wake up from Deep Power down mode was NOT triggred by wake up I/O 0. + * 0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 0. + */ +#define PMC_WAKEIOCAUSE_WAKEUP0(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP0_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP0_MASK) +#define PMC_WAKEIOCAUSE_WAKEUP1_MASK (0x2U) +#define PMC_WAKEIOCAUSE_WAKEUP1_SHIFT (1U) +/*! WAKEUP1 - Allows to identify Wake up I/O 1 as the wake-up source from Deep Power Down mode. + * 0b0..Last wake up from Deep Power down mode was NOT triggred by wake up I/O 1. + * 0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 1. + */ +#define PMC_WAKEIOCAUSE_WAKEUP1(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP1_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP1_MASK) +#define PMC_WAKEIOCAUSE_WAKEUP2_MASK (0x4U) +#define PMC_WAKEIOCAUSE_WAKEUP2_SHIFT (2U) +/*! WAKEUP2 - Allows to identify Wake up I/O 2 as the wake-up source from Deep Power Down mode. + * 0b0..Last wake up from Deep Power down mode was NOT triggred by wake up I/O 2. + * 0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 2. + */ +#define PMC_WAKEIOCAUSE_WAKEUP2(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP2_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP2_MASK) +#define PMC_WAKEIOCAUSE_WAKEUP3_MASK (0x8U) +#define PMC_WAKEIOCAUSE_WAKEUP3_SHIFT (3U) +/*! WAKEUP3 - Allows to identify Wake up I/O 3 as the wake-up source from Deep Power Down mode. + * 0b0..Last wake up from Deep Power down mode was NOT triggred by wake up I/O 3. + * 0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 3. + */ +#define PMC_WAKEIOCAUSE_WAKEUP3(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP3_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP3_MASK) +/*! @} */ + +/*! @name STATUSCLK - FRO and XTAL status register [Reset by: PoR, Brown Out Detectors Reset] */ +/*! @{ */ +#define PMC_STATUSCLK_XTAL32KOK_MASK (0x1U) +#define PMC_STATUSCLK_XTAL32KOK_SHIFT (0U) +#define PMC_STATUSCLK_XTAL32KOK(x) (((uint32_t)(((uint32_t)(x)) << PMC_STATUSCLK_XTAL32KOK_SHIFT)) & PMC_STATUSCLK_XTAL32KOK_MASK) +#define PMC_STATUSCLK_FRO1MCLKVALID_MASK (0x2U) +#define PMC_STATUSCLK_FRO1MCLKVALID_SHIFT (1U) +#define PMC_STATUSCLK_FRO1MCLKVALID(x) (((uint32_t)(((uint32_t)(x)) << PMC_STATUSCLK_FRO1MCLKVALID_SHIFT)) & PMC_STATUSCLK_FRO1MCLKVALID_MASK) +#define PMC_STATUSCLK_XTAL32KOSCFAILURE_MASK (0x4U) +#define PMC_STATUSCLK_XTAL32KOSCFAILURE_SHIFT (2U) +/*! XTAL32KOSCFAILURE - XTAL32 KHZ oscillator oscillation failure detection indicator. + * 0b0..No oscillation failure has been detetced since the last time this bit has been cleared.. + * 0b1..At least one oscillation failure has been detetced since the last time this bit has been cleared.. + */ +#define PMC_STATUSCLK_XTAL32KOSCFAILURE(x) (((uint32_t)(((uint32_t)(x)) << PMC_STATUSCLK_XTAL32KOSCFAILURE_SHIFT)) & PMC_STATUSCLK_XTAL32KOSCFAILURE_MASK) +/*! @} */ + +/*! @name AOREG1 - General purpose always on domain data storage [Reset by: PoR, Brown Out Detectors Reset] */ +/*! @{ */ +#define PMC_AOREG1_DATA31_0_MASK (0xFFFFFFFFU) +#define PMC_AOREG1_DATA31_0_SHIFT (0U) +#define PMC_AOREG1_DATA31_0(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_DATA31_0_SHIFT)) & PMC_AOREG1_DATA31_0_MASK) +/*! @} */ + +/*! @name RTCOSC32K - RTC 1 KHZ and 1 Hz clocks source control register [Reset by: PoR, Brown Out Detectors Reset] */ +/*! @{ */ +#define PMC_RTCOSC32K_SEL_MASK (0x1U) +#define PMC_RTCOSC32K_SEL_SHIFT (0U) +/*! SEL - Select the 32K oscillator to be used in Deep Power Down Mode for the RTC (either XTAL32KHz or FRO32KHz) . + * 0b0..FRO 32 KHz. + * 0b1..XTAL 32KHz. + */ +#define PMC_RTCOSC32K_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_SEL_SHIFT)) & PMC_RTCOSC32K_SEL_MASK) +#define PMC_RTCOSC32K_CLK1KHZDIV_MASK (0xEU) +#define PMC_RTCOSC32K_CLK1KHZDIV_SHIFT (1U) +#define PMC_RTCOSC32K_CLK1KHZDIV(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1KHZDIV_SHIFT)) & PMC_RTCOSC32K_CLK1KHZDIV_MASK) +#define PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ_MASK (0x8000U) +#define PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ_SHIFT (15U) +#define PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ_SHIFT)) & PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ_MASK) +#define PMC_RTCOSC32K_CLK1HZDIV_MASK (0x7FF0000U) +#define PMC_RTCOSC32K_CLK1HZDIV_SHIFT (16U) +#define PMC_RTCOSC32K_CLK1HZDIV(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1HZDIV_SHIFT)) & PMC_RTCOSC32K_CLK1HZDIV_MASK) +#define PMC_RTCOSC32K_CLK1HZDIVHALT_MASK (0x40000000U) +#define PMC_RTCOSC32K_CLK1HZDIVHALT_SHIFT (30U) +#define PMC_RTCOSC32K_CLK1HZDIVHALT(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1HZDIVHALT_SHIFT)) & PMC_RTCOSC32K_CLK1HZDIVHALT_MASK) +#define PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ_MASK (0x80000000U) +#define PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ_SHIFT (31U) +#define PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ_SHIFT)) & PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ_MASK) +/*! @} */ + +/*! @name OSTIMER - OS Timer control register [Reset by: PoR, Brown Out Detectors Reset] */ +/*! @{ */ +#define PMC_OSTIMER_SOFTRESET_MASK (0x1U) +#define PMC_OSTIMER_SOFTRESET_SHIFT (0U) +#define PMC_OSTIMER_SOFTRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_OSTIMER_SOFTRESET_SHIFT)) & PMC_OSTIMER_SOFTRESET_MASK) +#define PMC_OSTIMER_CLOCKENABLE_MASK (0x2U) +#define PMC_OSTIMER_CLOCKENABLE_SHIFT (1U) +#define PMC_OSTIMER_CLOCKENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_OSTIMER_CLOCKENABLE_SHIFT)) & PMC_OSTIMER_CLOCKENABLE_MASK) +#define PMC_OSTIMER_DPDWAKEUPENABLE_MASK (0x4U) +#define PMC_OSTIMER_DPDWAKEUPENABLE_SHIFT (2U) +#define PMC_OSTIMER_DPDWAKEUPENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_OSTIMER_DPDWAKEUPENABLE_SHIFT)) & PMC_OSTIMER_DPDWAKEUPENABLE_MASK) +#define PMC_OSTIMER_OSC32KPD_MASK (0x8U) +#define PMC_OSTIMER_OSC32KPD_SHIFT (3U) +#define PMC_OSTIMER_OSC32KPD(x) (((uint32_t)(((uint32_t)(x)) << PMC_OSTIMER_OSC32KPD_SHIFT)) & PMC_OSTIMER_OSC32KPD_MASK) +/*! @} */ + +/*! @name PDSLEEPCFG0 - Controls the power to various modules during Low Power modes - DEEP SLEEP, POWER DOWN and DEEP POWER DOWN [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Software Reset] */ +/*! @{ */ +#define PMC_PDSLEEPCFG0_PDEN_DCDC_MASK (0x1U) +#define PMC_PDSLEEPCFG0_PDEN_DCDC_SHIFT (0U) +/*! PDEN_DCDC - Controls DCDC power during DEEP SLEEP (DCDC is always shut down during POWER DOWN and DEEP POWER DOWN). + * 0b0..DCDC is powered on during low power mode.. + * 0b1..DCDC is powered off during low power mode.. + */ +#define PMC_PDSLEEPCFG0_PDEN_DCDC(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_DCDC_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_DCDC_MASK) +#define PMC_PDSLEEPCFG0_PDEN_BIAS_MASK (0x2U) +#define PMC_PDSLEEPCFG0_PDEN_BIAS_SHIFT (1U) +/*! PDEN_BIAS - Controls Analog Bias power during DEEP SLEEP and POWER DOWN (always shut down during DEEP POWER DOWN). + * 0b0..Analog Bias is powered on during low power mode.. + * 0b1..Analog Bias is powered off during low power mode.. + */ +#define PMC_PDSLEEPCFG0_PDEN_BIAS(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_BIAS_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_BIAS_MASK) +#define PMC_PDSLEEPCFG0_PDEN_BODCORE_MASK (0x4U) +#define PMC_PDSLEEPCFG0_PDEN_BODCORE_SHIFT (2U) +/*! PDEN_BODCORE - Controls Core Logic BoD power during DEEP SLEEP and POWER DOWN (always shut down during DEEP POWER DOWN). + * 0b0..BOD CORE is powered on during low power mode.. + * 0b1..BOD CORE is powered off during low power mode.. + */ +#define PMC_PDSLEEPCFG0_PDEN_BODCORE(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_BODCORE_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_BODCORE_MASK) +#define PMC_PDSLEEPCFG0_PDEN_BODVBAT_MASK (0x8U) +#define PMC_PDSLEEPCFG0_PDEN_BODVBAT_SHIFT (3U) +/*! PDEN_BODVBAT - Controls VBAT BoD power during DEEP SLEEP and POWER DOWN (always shut down during DEEP POWER DOWN). + * 0b0..BOD VBAT is powered on during low power mode.. + * 0b1..BOD VBAT is powered off during low power mode.. + */ +#define PMC_PDSLEEPCFG0_PDEN_BODVBAT(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_BODVBAT_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_BODVBAT_MASK) +#define PMC_PDSLEEPCFG0_PDEN_FRO1M_MASK (0x10U) +#define PMC_PDSLEEPCFG0_PDEN_FRO1M_SHIFT (4U) +/*! PDEN_FRO1M - Controls 1 MHz Free Running Oscillator power during DEEP SLEEP, POWER DOWN and DEEP POWER DOWN. + * 0b0..FRO 1MHz is powered on during low power mode.. + * 0b1..FRO 1MHz is powered off during low power mode.. + */ +#define PMC_PDSLEEPCFG0_PDEN_FRO1M(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_FRO1M_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_FRO1M_MASK) +#define PMC_PDSLEEPCFG0_PDEN_FRO192M_MASK (0x20U) +#define PMC_PDSLEEPCFG0_PDEN_FRO192M_SHIFT (5U) +/*! PDEN_FRO192M - Controls 192MHz Free Running Oscillator power during DEEP SLEEP (always shut down + * during POWER DOWN and DEEP POWER DOWN). + * 0b0..FRO 192 MHz is powered on during low power mode.. + * 0b1..FRO 192 MHz is powered off during low power mode.. + */ +#define PMC_PDSLEEPCFG0_PDEN_FRO192M(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_FRO192M_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_FRO192M_MASK) +#define PMC_PDSLEEPCFG0_PDEN_FRO32K_MASK (0x40U) +#define PMC_PDSLEEPCFG0_PDEN_FRO32K_SHIFT (6U) +/*! PDEN_FRO32K - Controls power during DEEP SLEEP, POWER DOWN and DEEP POWER DOWN. + * 0b0..FRO 32 KHz is powered on during low power mode.. + * 0b1..FRO 32 KHz is powered off during low power mode.. + */ +#define PMC_PDSLEEPCFG0_PDEN_FRO32K(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_FRO32K_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_FRO32K_MASK) +#define PMC_PDSLEEPCFG0_PDEN_XTAL32K_MASK (0x80U) +#define PMC_PDSLEEPCFG0_PDEN_XTAL32K_SHIFT (7U) +/*! PDEN_XTAL32K - Controls crystal 32 KHz power during DEEP SLEEP, POWER DOWN and DEEP POWER DOWN. + * 0b0..crystal 32 KHz is powered on during low power mode.. + * 0b1..crystal 32 KHz is powered off during low power mode.. + */ +#define PMC_PDSLEEPCFG0_PDEN_XTAL32K(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_XTAL32K_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_XTAL32K_MASK) +#define PMC_PDSLEEPCFG0_PDEN_XTAL32M_MASK (0x100U) +#define PMC_PDSLEEPCFG0_PDEN_XTAL32M_SHIFT (8U) +/*! PDEN_XTAL32M - Controls crystal 32 MHz power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). + * 0b0..crystal 32 MHz is powered on during low power mode.. + * 0b1..crystal 32 MHz is powered off during low power mode.. + */ +#define PMC_PDSLEEPCFG0_PDEN_XTAL32M(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_XTAL32M_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_XTAL32M_MASK) +#define PMC_PDSLEEPCFG0_PDEN_PLL0_MASK (0x200U) +#define PMC_PDSLEEPCFG0_PDEN_PLL0_SHIFT (9U) +/*! PDEN_PLL0 - Controls System PLL (also refered as PLL0) power during DEEP SLEEP (always shut down + * during POWER DOWN and DEEP POWER DOWN). + * 0b0..System PLL (also refered as PLL0) is powered on during low power mode.. + * 0b1..System PLL (also refered as PLL0) is powered off during low power mode.. + */ +#define PMC_PDSLEEPCFG0_PDEN_PLL0(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_PLL0_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_PLL0_MASK) +#define PMC_PDSLEEPCFG0_PDEN_PLL1_MASK (0x400U) +#define PMC_PDSLEEPCFG0_PDEN_PLL1_SHIFT (10U) +/*! PDEN_PLL1 - Controls USB PLL (also refered as PLL1) power during DEEP SLEEP (always shut down + * during POWER DOWN and DEEP POWER DOWN). + * 0b0..USB PLL (also refered as PLL1) is powered on during low power mode.. + * 0b1..USB PLL (also refered as PLL1) is powered off during low power mode.. + */ +#define PMC_PDSLEEPCFG0_PDEN_PLL1(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_PLL1_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_PLL1_MASK) +#define PMC_PDSLEEPCFG0_PDEN_USBFSPHY_MASK (0x800U) +#define PMC_PDSLEEPCFG0_PDEN_USBFSPHY_SHIFT (11U) +/*! PDEN_USBFSPHY - Controls USB Full Speed phy power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). + * 0b0..USB Full Speed phy is powered on during low power mode.. + * 0b1..USB Full Speed phy is powered off during low power mode.. + */ +#define PMC_PDSLEEPCFG0_PDEN_USBFSPHY(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_USBFSPHY_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_USBFSPHY_MASK) +#define PMC_PDSLEEPCFG0_PDEN_USBHSPHY_MASK (0x1000U) +#define PMC_PDSLEEPCFG0_PDEN_USBHSPHY_SHIFT (12U) +/*! PDEN_USBHSPHY - Controls USB High Speed Phy power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). + * 0b0..USB High Speed Phy is powered on during low power mode.. + * 0b1..USB High Speed Phy is powered off during low power mode.. + */ +#define PMC_PDSLEEPCFG0_PDEN_USBHSPHY(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_USBHSPHY_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_USBHSPHY_MASK) +#define PMC_PDSLEEPCFG0_PDEN_COMP_MASK (0x2000U) +#define PMC_PDSLEEPCFG0_PDEN_COMP_SHIFT (13U) +/*! PDEN_COMP - Controls Analog Comparator power during DEEP SLEEP and POWER DOWN (always shut down during DEEP POWER DOWN). + * 0b0..Analog Comparator is powered on during low power mode.. + * 0b1..Analog Comparator is powered off during low power mode.. + */ +#define PMC_PDSLEEPCFG0_PDEN_COMP(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_COMP_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_COMP_MASK) +#define PMC_PDSLEEPCFG0_PDEN_TEMPSENS_MASK (0x4000U) +#define PMC_PDSLEEPCFG0_PDEN_TEMPSENS_SHIFT (14U) +/*! PDEN_TEMPSENS - Controls Temperature Sensor power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). + * 0b0..Temperature Sensor is powered on during low power mode.. + * 0b1..Temperature Sensor is powered off during low power mode.. + */ +#define PMC_PDSLEEPCFG0_PDEN_TEMPSENS(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_TEMPSENS_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_TEMPSENS_MASK) +#define PMC_PDSLEEPCFG0_PDEN_GPADC_MASK (0x8000U) +#define PMC_PDSLEEPCFG0_PDEN_GPADC_SHIFT (15U) +/*! PDEN_GPADC - Controls General Purpose ADC (GPADC) power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). + * 0b0..General Purpose ADC (GPADC) is powered on during low power mode.. + * 0b1..General Purpose ADC (GPADC) is powered off during low power mode.. + */ +#define PMC_PDSLEEPCFG0_PDEN_GPADC(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_GPADC_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_GPADC_MASK) +#define PMC_PDSLEEPCFG0_PDEN_LDOMEM_MASK (0x10000U) +#define PMC_PDSLEEPCFG0_PDEN_LDOMEM_SHIFT (16U) +/*! PDEN_LDOMEM - Controls Memories LDO power during DEEP SLEEP, POWER DOWN and DEEP POWER DOWN. + * 0b0..Memories LDO is powered on during low power mode.. + * 0b1..Memories LDO is powered off during low power mode.. + */ +#define PMC_PDSLEEPCFG0_PDEN_LDOMEM(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_LDOMEM_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_LDOMEM_MASK) +#define PMC_PDSLEEPCFG0_PDEN_LDODEEPSLEEP_MASK (0x20000U) +#define PMC_PDSLEEPCFG0_PDEN_LDODEEPSLEEP_SHIFT (17U) +/*! PDEN_LDODEEPSLEEP - Controls Deep Sleep LDO power during DEEP SLEEP and POWER DOWN (always shut down during DEEP POWER DOWN). + * 0b0..Deep Sleep LDO is powered on during low power mode.. + * 0b1..Deep Sleep LDO is powered off during low power mode.. + */ +#define PMC_PDSLEEPCFG0_PDEN_LDODEEPSLEEP(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_LDODEEPSLEEP_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_LDODEEPSLEEP_MASK) +#define PMC_PDSLEEPCFG0_PDEN_LDOUSBHS_MASK (0x40000U) +#define PMC_PDSLEEPCFG0_PDEN_LDOUSBHS_SHIFT (18U) +/*! PDEN_LDOUSBHS - Controls USB high speed LDO power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). + * 0b0..USB high speed LDO is powered on during low power mode.. + * 0b1..USB high speed LDO is powered off during low power mode.. + */ +#define PMC_PDSLEEPCFG0_PDEN_LDOUSBHS(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_LDOUSBHS_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_LDOUSBHS_MASK) +#define PMC_PDSLEEPCFG0_PDEN_AUXBIAS_MASK (0x80000U) +#define PMC_PDSLEEPCFG0_PDEN_AUXBIAS_SHIFT (19U) +/*! PDEN_AUXBIAS - during DEEP SLEEP and POWER DOWN (always shut down during DEEP POWER DOWN). + * 0b0..is powered on during low power mode.. + * 0b1..is powered off during low power mode.. + */ +#define PMC_PDSLEEPCFG0_PDEN_AUXBIAS(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_AUXBIAS_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_AUXBIAS_MASK) +#define PMC_PDSLEEPCFG0_PDEN_LDOXO32M_MASK (0x100000U) +#define PMC_PDSLEEPCFG0_PDEN_LDOXO32M_SHIFT (20U) +/*! PDEN_LDOXO32M - Controls crystal 32 MHz LDO power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). + * 0b0..crystal 32 MHz LDO is powered on during low power mode.. + * 0b1..crystal 32 MHz LDO is powered off during low power mode.. + */ +#define PMC_PDSLEEPCFG0_PDEN_LDOXO32M(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_LDOXO32M_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_LDOXO32M_MASK) +#define PMC_PDSLEEPCFG0_PDEN_LDOFLASHNV_MASK (0x200000U) +#define PMC_PDSLEEPCFG0_PDEN_LDOFLASHNV_SHIFT (21U) +/*! PDEN_LDOFLASHNV - Controls Flash NV (high voltage) LDO power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). + * 0b0..Flash NV (high voltage) is powered on during low power mode.. + * 0b1..Flash NV (high voltage) is powered off during low power mode.. + */ +#define PMC_PDSLEEPCFG0_PDEN_LDOFLASHNV(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_LDOFLASHNV_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_LDOFLASHNV_MASK) +#define PMC_PDSLEEPCFG0_PDEN_RNG_MASK (0x400000U) +#define PMC_PDSLEEPCFG0_PDEN_RNG_SHIFT (22U) +/*! PDEN_RNG - Controls True Random Number Genetaor (TRNG) clock sources power during DEEP SLEEP + * (always shut down during POWER DOWN and DEEP POWER DOWN). + * 0b0..True Random Number Genetaor (TRNG) clock sources are powered on during low power mode.. + * 0b1..True Random Number Genetaor (TRNG) clock sources are powered off during low power mode.. + */ +#define PMC_PDSLEEPCFG0_PDEN_RNG(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_RNG_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_RNG_MASK) +#define PMC_PDSLEEPCFG0_PDEN_PLL0_SSCG_MASK (0x800000U) +#define PMC_PDSLEEPCFG0_PDEN_PLL0_SSCG_SHIFT (23U) +/*! PDEN_PLL0_SSCG - Controls PLL0 Spread Sprectrum module power during DEEP SLEEP (PLL0 Spread + * Spectrum is always shut down during POWER DOWN and DEEP POWER DOWN). + * 0b0..PLL0 Spread Sprectrum module is powered on during low power mode.. + * 0b1..PLL0 Spread Sprectrum module is powered off during low power mode.. + */ +#define PMC_PDSLEEPCFG0_PDEN_PLL0_SSCG(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_PLL0_SSCG_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_PLL0_SSCG_MASK) +#define PMC_PDSLEEPCFG0_PDEN_ROM_MASK (0x1000000U) +#define PMC_PDSLEEPCFG0_PDEN_ROM_SHIFT (24U) +/*! PDEN_ROM - Controls ROM power during DEEP SLEEP (ROM is always shut down during POWER DOWN and DEEP POWER DOWN). + * 0b0..ROM is powered on during low power mode.. + * 0b1..ROM is powered off during low power mode.. + */ +#define PMC_PDSLEEPCFG0_PDEN_ROM(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_ROM_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_ROM_MASK) +/*! @} */ + +/*! @name PDRUNCFG0 - Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ +/*! @{ */ +#define PMC_PDRUNCFG0_PDEN_DCDC_MASK (0x1U) +#define PMC_PDRUNCFG0_PDEN_DCDC_SHIFT (0U) +/*! PDEN_DCDC - Controls power to Bulk DCDC Converter. + * 0b0..DCDC is powered. + * 0b1..DCDC is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_DCDC(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_DCDC_SHIFT)) & PMC_PDRUNCFG0_PDEN_DCDC_MASK) +#define PMC_PDRUNCFG0_PDEN_BIAS_MASK (0x2U) +#define PMC_PDRUNCFG0_PDEN_BIAS_SHIFT (1U) +/*! PDEN_BIAS - Controls power to . + * 0b0..Analog Bias is powered. + * 0b1..Analog Bias is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_BIAS(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_BIAS_SHIFT)) & PMC_PDRUNCFG0_PDEN_BIAS_MASK) +#define PMC_PDRUNCFG0_PDEN_BODCORE_MASK (0x4U) +#define PMC_PDRUNCFG0_PDEN_BODCORE_SHIFT (2U) +/*! PDEN_BODCORE - Controls power to Core Brown Out Detector (BOD). + * 0b0..BOD CORE is powered. + * 0b1..BOD CORE is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_BODCORE(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_BODCORE_SHIFT)) & PMC_PDRUNCFG0_PDEN_BODCORE_MASK) +#define PMC_PDRUNCFG0_PDEN_BODVBAT_MASK (0x8U) +#define PMC_PDRUNCFG0_PDEN_BODVBAT_SHIFT (3U) +/*! PDEN_BODVBAT - Controls power to VBAT Brown Out Detector (BOD). + * 0b0..BOD VBAT is powered. + * 0b1..BOD VBAT is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_BODVBAT(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_BODVBAT_SHIFT)) & PMC_PDRUNCFG0_PDEN_BODVBAT_MASK) +#define PMC_PDRUNCFG0_PDEN_FRO192M_MASK (0x20U) +#define PMC_PDRUNCFG0_PDEN_FRO192M_SHIFT (5U) +/*! PDEN_FRO192M - Controls power to the Free Running Oscillator (FRO) 192 MHz; The 12MHz, 48 MHz + * and 96 MHz clocks are derived from this FRO. + * 0b0..FRO 192MHz is powered. + * 0b1..FRO 192MHz is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_FRO192M(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_FRO192M_SHIFT)) & PMC_PDRUNCFG0_PDEN_FRO192M_MASK) +#define PMC_PDRUNCFG0_PDEN_FRO32K_MASK (0x40U) +#define PMC_PDRUNCFG0_PDEN_FRO32K_SHIFT (6U) +/*! PDEN_FRO32K - Controls power to the Free Running Oscillator (FRO) 32 KHz. + * 0b0..FRO32KHz is powered. + * 0b1..FRO32KHz is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_FRO32K(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_FRO32K_SHIFT)) & PMC_PDRUNCFG0_PDEN_FRO32K_MASK) +#define PMC_PDRUNCFG0_PDEN_XTAL32K_MASK (0x80U) +#define PMC_PDRUNCFG0_PDEN_XTAL32K_SHIFT (7U) +/*! PDEN_XTAL32K - Controls power to crystal 32 KHz. + * 0b0..Crystal 32KHz is powered. + * 0b1..Crystal 32KHz is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_XTAL32K(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_XTAL32K_SHIFT)) & PMC_PDRUNCFG0_PDEN_XTAL32K_MASK) +#define PMC_PDRUNCFG0_PDEN_XTAL32M_MASK (0x100U) +#define PMC_PDRUNCFG0_PDEN_XTAL32M_SHIFT (8U) +/*! PDEN_XTAL32M - Controls power to crystal 32 MHz. + * 0b0..Crystal 32MHz is powered. + * 0b1..Crystal 32MHz is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_XTAL32M(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_XTAL32M_SHIFT)) & PMC_PDRUNCFG0_PDEN_XTAL32M_MASK) +#define PMC_PDRUNCFG0_PDEN_PLL0_MASK (0x200U) +#define PMC_PDRUNCFG0_PDEN_PLL0_SHIFT (9U) +/*! PDEN_PLL0 - Controls power to System PLL (also refered as PLL0). + * 0b0..PLL0 is powered. + * 0b1..PLL0 is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_PLL0(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_PLL0_SHIFT)) & PMC_PDRUNCFG0_PDEN_PLL0_MASK) +#define PMC_PDRUNCFG0_PDEN_PLL1_MASK (0x400U) +#define PMC_PDRUNCFG0_PDEN_PLL1_SHIFT (10U) +/*! PDEN_PLL1 - Controls power to USB PLL (also refered as PLL1). + * 0b0..PLL1 is powered. + * 0b1..PLL1 is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_PLL1(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_PLL1_SHIFT)) & PMC_PDRUNCFG0_PDEN_PLL1_MASK) +#define PMC_PDRUNCFG0_PDEN_USBFSPHY_MASK (0x800U) +#define PMC_PDRUNCFG0_PDEN_USBFSPHY_SHIFT (11U) +/*! PDEN_USBFSPHY - Controls power to USB Full Speed phy. + * 0b0..USB Full Speed phy is powered. + * 0b1..USB Full Speed phy is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_USBFSPHY(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_USBFSPHY_SHIFT)) & PMC_PDRUNCFG0_PDEN_USBFSPHY_MASK) +#define PMC_PDRUNCFG0_PDEN_USBHSPHY_MASK (0x1000U) +#define PMC_PDRUNCFG0_PDEN_USBHSPHY_SHIFT (12U) +/*! PDEN_USBHSPHY - Controls power to USB High Speed Phy. + * 0b0..USB HS phy is powered. + * 0b1..USB HS phy is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_USBHSPHY(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_USBHSPHY_SHIFT)) & PMC_PDRUNCFG0_PDEN_USBHSPHY_MASK) +#define PMC_PDRUNCFG0_PDEN_COMP_MASK (0x2000U) +#define PMC_PDRUNCFG0_PDEN_COMP_SHIFT (13U) +/*! PDEN_COMP - Controls power to Analog Comparator. + * 0b0..Analog Comparator is powered. + * 0b1..Analog Comparator is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_COMP(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_COMP_SHIFT)) & PMC_PDRUNCFG0_PDEN_COMP_MASK) +#define PMC_PDRUNCFG0_PDEN_TEMPSENS_MASK (0x4000U) +#define PMC_PDRUNCFG0_PDEN_TEMPSENS_SHIFT (14U) +/*! PDEN_TEMPSENS - Controls power to Temperature Sensor. + * 0b0..Temperature Sensor is powered. + * 0b1..Temperature Sensor is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_TEMPSENS(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_TEMPSENS_SHIFT)) & PMC_PDRUNCFG0_PDEN_TEMPSENS_MASK) +#define PMC_PDRUNCFG0_PDEN_GPADC_MASK (0x8000U) +#define PMC_PDRUNCFG0_PDEN_GPADC_SHIFT (15U) +/*! PDEN_GPADC - Controls power to General Purpose ADC (GPADC). + * 0b0..GPADC is powered. + * 0b1..GPADC is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_GPADC(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_GPADC_SHIFT)) & PMC_PDRUNCFG0_PDEN_GPADC_MASK) +#define PMC_PDRUNCFG0_PDEN_LDOMEM_MASK (0x10000U) +#define PMC_PDRUNCFG0_PDEN_LDOMEM_SHIFT (16U) +/*! PDEN_LDOMEM - Controls power to Memories LDO. + * 0b0..Memories LDO is powered. + * 0b1..Memories LDO is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_LDOMEM(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_LDOMEM_SHIFT)) & PMC_PDRUNCFG0_PDEN_LDOMEM_MASK) +#define PMC_PDRUNCFG0_PDEN_LDODEEPSLEEP_MASK (0x20000U) +#define PMC_PDRUNCFG0_PDEN_LDODEEPSLEEP_SHIFT (17U) +/*! PDEN_LDODEEPSLEEP - Controls power to Deep Sleep LDO. + * 0b0..Deep Sleep LDO is powered. + * 0b1..Deep Sleep LDO is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_LDODEEPSLEEP(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_LDODEEPSLEEP_SHIFT)) & PMC_PDRUNCFG0_PDEN_LDODEEPSLEEP_MASK) +#define PMC_PDRUNCFG0_PDEN_LDOUSBHS_MASK (0x40000U) +#define PMC_PDRUNCFG0_PDEN_LDOUSBHS_SHIFT (18U) +/*! PDEN_LDOUSBHS - Controls power to USB high speed LDO. + * 0b0..USB high speed LDO is powered. + * 0b1..USB high speed LDO is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_LDOUSBHS(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_LDOUSBHS_SHIFT)) & PMC_PDRUNCFG0_PDEN_LDOUSBHS_MASK) +#define PMC_PDRUNCFG0_PDEN_AUXBIAS_MASK (0x80000U) +#define PMC_PDRUNCFG0_PDEN_AUXBIAS_SHIFT (19U) +/*! PDEN_AUXBIAS - Controls power to auxiliary biasing (AUXBIAS) + * 0b0..auxiliary biasing is powered. + * 0b1..auxiliary biasing is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_AUXBIAS(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_AUXBIAS_SHIFT)) & PMC_PDRUNCFG0_PDEN_AUXBIAS_MASK) +#define PMC_PDRUNCFG0_PDEN_LDOXO32M_MASK (0x100000U) +#define PMC_PDRUNCFG0_PDEN_LDOXO32M_SHIFT (20U) +/*! PDEN_LDOXO32M - Controls power to crystal 32 MHz LDO. + * 0b0..crystal 32 MHz LDO is powered. + * 0b1..crystal 32 MHz LDO is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_LDOXO32M(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_LDOXO32M_SHIFT)) & PMC_PDRUNCFG0_PDEN_LDOXO32M_MASK) +#define PMC_PDRUNCFG0_PDEN_LDOFLASHNV_MASK (0x200000U) +#define PMC_PDRUNCFG0_PDEN_LDOFLASHNV_SHIFT (21U) +/*! PDEN_LDOFLASHNV - Controls power to Flasn NV (high voltage) LDO. + * 0b0..Flash NV LDO is powered. + * 0b1..Flash NV LDO is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_LDOFLASHNV(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_LDOFLASHNV_SHIFT)) & PMC_PDRUNCFG0_PDEN_LDOFLASHNV_MASK) +#define PMC_PDRUNCFG0_PDEN_RNG_MASK (0x400000U) +#define PMC_PDRUNCFG0_PDEN_RNG_SHIFT (22U) +/*! PDEN_RNG - Controls power to all True Random Number Genetaor (TRNG) clock sources. + * 0b0..TRNG clocks are powered. + * 0b1..TRNG clocks are powered down. + */ +#define PMC_PDRUNCFG0_PDEN_RNG(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_RNG_SHIFT)) & PMC_PDRUNCFG0_PDEN_RNG_MASK) +#define PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK (0x800000U) +#define PMC_PDRUNCFG0_PDEN_PLL0_SSCG_SHIFT (23U) +/*! PDEN_PLL0_SSCG - Controls power to System PLL (PLL0) Spread Spectrum module. + * 0b0..PLL0 Sread spectrum module is powered. + * 0b1..PLL0 Sread spectrum module is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_PLL0_SSCG(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_PLL0_SSCG_SHIFT)) & PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK) +/*! @} */ + +/*! @name PDRUNCFGSET0 - Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ +/*! @{ */ +#define PMC_PDRUNCFGSET0_PDRUNCFGSET0_MASK (0xFFFFFFFFU) +#define PMC_PDRUNCFGSET0_PDRUNCFGSET0_SHIFT (0U) +#define PMC_PDRUNCFGSET0_PDRUNCFGSET0(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFGSET0_PDRUNCFGSET0_SHIFT)) & PMC_PDRUNCFGSET0_PDRUNCFGSET0_MASK) +/*! @} */ + +/*! @name PDRUNCFGCLR0 - Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ +/*! @{ */ +#define PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_MASK (0xFFFFFFFFU) +#define PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_SHIFT (0U) +#define PMC_PDRUNCFGCLR0_PDRUNCFGCLR0(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_SHIFT)) & PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group PMC_Register_Masks */ + + +/* PMC - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral PMC base address */ + #define PMC_BASE (0x50020000u) + /** Peripheral PMC base address */ + #define PMC_BASE_NS (0x40020000u) + /** Peripheral PMC base pointer */ + #define PMC ((PMC_Type *)PMC_BASE) + /** Peripheral PMC base pointer */ + #define PMC_NS ((PMC_Type *)PMC_BASE_NS) + /** Array initializer of PMC peripheral base addresses */ + #define PMC_BASE_ADDRS { PMC_BASE } + /** Array initializer of PMC peripheral base pointers */ + #define PMC_BASE_PTRS { PMC } + /** Array initializer of PMC peripheral base addresses */ + #define PMC_BASE_ADDRS_NS { PMC_BASE_NS } + /** Array initializer of PMC peripheral base pointers */ + #define PMC_BASE_PTRS_NS { PMC_NS } +#else + /** Peripheral PMC base address */ + #define PMC_BASE (0x40020000u) + /** Peripheral PMC base pointer */ + #define PMC ((PMC_Type *)PMC_BASE) + /** Array initializer of PMC peripheral base addresses */ + #define PMC_BASE_ADDRS { PMC_BASE } + /** Array initializer of PMC peripheral base pointers */ + #define PMC_BASE_PTRS { PMC } +#endif + +/*! + * @} + */ /* end of group PMC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- POWERQUAD Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup POWERQUAD_Peripheral_Access_Layer POWERQUAD Peripheral Access Layer + * @{ + */ + +/** POWERQUAD - Register Layout Typedef */ +typedef struct { + __IO uint32_t OUTBASE; /**< Base address register for output region, offset: 0x0 */ + __IO uint32_t OUTFORMAT; /**< Output format, offset: 0x4 */ + __IO uint32_t TMPBASE; /**< Base address register for temp region, offset: 0x8 */ + __IO uint32_t TMPFORMAT; /**< Temp format, offset: 0xC */ + __IO uint32_t INABASE; /**< Base address register for input A region, offset: 0x10 */ + __IO uint32_t INAFORMAT; /**< Input A format, offset: 0x14 */ + __IO uint32_t INBBASE; /**< Base address register for input B region, offset: 0x18 */ + __IO uint32_t INBFORMAT; /**< Input B format, offset: 0x1C */ + uint8_t RESERVED_0[224]; + __IO uint32_t CONTROL; /**< PowerQuad Control register, offset: 0x100 */ + __IO uint32_t LENGTH; /**< Length register, offset: 0x104 */ + __IO uint32_t CPPRE; /**< Pre-scale register, offset: 0x108 */ + __IO uint32_t MISC; /**< Misc register, offset: 0x10C */ + __IO uint32_t CURSORY; /**< Cursory register, offset: 0x110 */ + uint8_t RESERVED_1[108]; + __IO uint32_t CORDIC_X; /**< Cordic input X register, offset: 0x180 */ + __IO uint32_t CORDIC_Y; /**< Cordic input Y register, offset: 0x184 */ + __IO uint32_t CORDIC_Z; /**< Cordic input Z register, offset: 0x188 */ + __IO uint32_t ERRSTAT; /**< Read/Write register where error statuses are captured (sticky), offset: 0x18C */ + __IO uint32_t INTREN; /**< INTERRUPT enable register, offset: 0x190 */ + __IO uint32_t EVENTEN; /**< Event Enable register, offset: 0x194 */ + __IO uint32_t INTRSTAT; /**< INTERRUPT STATUS register, offset: 0x198 */ + uint8_t RESERVED_2[100]; + __IO uint32_t GPREG[16]; /**< General purpose register bank N., array offset: 0x200, array step: 0x4 */ + __IO uint32_t COMPREG[8]; /**< Compute register bank, array offset: 0x240, array step: 0x4 */ +} POWERQUAD_Type; + +/* ---------------------------------------------------------------------------- + -- POWERQUAD Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup POWERQUAD_Register_Masks POWERQUAD Register Masks + * @{ + */ + +/*! @name OUTBASE - Base address register for output region */ +/*! @{ */ +#define POWERQUAD_OUTBASE_OUTBASE_MASK (0xFFFFFFFFU) +#define POWERQUAD_OUTBASE_OUTBASE_SHIFT (0U) +#define POWERQUAD_OUTBASE_OUTBASE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTBASE_OUTBASE_SHIFT)) & POWERQUAD_OUTBASE_OUTBASE_MASK) +/*! @} */ + +/*! @name OUTFORMAT - Output format */ +/*! @{ */ +#define POWERQUAD_OUTFORMAT_OUT_FORMATINT_MASK (0x3U) +#define POWERQUAD_OUTFORMAT_OUT_FORMATINT_SHIFT (0U) +#define POWERQUAD_OUTFORMAT_OUT_FORMATINT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTFORMAT_OUT_FORMATINT_SHIFT)) & POWERQUAD_OUTFORMAT_OUT_FORMATINT_MASK) +#define POWERQUAD_OUTFORMAT_OUT_FORMATEXT_MASK (0x30U) +#define POWERQUAD_OUTFORMAT_OUT_FORMATEXT_SHIFT (4U) +#define POWERQUAD_OUTFORMAT_OUT_FORMATEXT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTFORMAT_OUT_FORMATEXT_SHIFT)) & POWERQUAD_OUTFORMAT_OUT_FORMATEXT_MASK) +#define POWERQUAD_OUTFORMAT_OUT_SCALER_MASK (0xFF00U) +#define POWERQUAD_OUTFORMAT_OUT_SCALER_SHIFT (8U) +#define POWERQUAD_OUTFORMAT_OUT_SCALER(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTFORMAT_OUT_SCALER_SHIFT)) & POWERQUAD_OUTFORMAT_OUT_SCALER_MASK) +/*! @} */ + +/*! @name TMPBASE - Base address register for temp region */ +/*! @{ */ +#define POWERQUAD_TMPBASE_TMPBASE_MASK (0xFFFFFFFFU) +#define POWERQUAD_TMPBASE_TMPBASE_SHIFT (0U) +#define POWERQUAD_TMPBASE_TMPBASE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPBASE_TMPBASE_SHIFT)) & POWERQUAD_TMPBASE_TMPBASE_MASK) +/*! @} */ + +/*! @name TMPFORMAT - Temp format */ +/*! @{ */ +#define POWERQUAD_TMPFORMAT_TMP_FORMATINT_MASK (0x3U) +#define POWERQUAD_TMPFORMAT_TMP_FORMATINT_SHIFT (0U) +#define POWERQUAD_TMPFORMAT_TMP_FORMATINT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPFORMAT_TMP_FORMATINT_SHIFT)) & POWERQUAD_TMPFORMAT_TMP_FORMATINT_MASK) +#define POWERQUAD_TMPFORMAT_TMP_FORMATEXT_MASK (0x30U) +#define POWERQUAD_TMPFORMAT_TMP_FORMATEXT_SHIFT (4U) +#define POWERQUAD_TMPFORMAT_TMP_FORMATEXT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPFORMAT_TMP_FORMATEXT_SHIFT)) & POWERQUAD_TMPFORMAT_TMP_FORMATEXT_MASK) +#define POWERQUAD_TMPFORMAT_TMP_SCALER_MASK (0xFF00U) +#define POWERQUAD_TMPFORMAT_TMP_SCALER_SHIFT (8U) +#define POWERQUAD_TMPFORMAT_TMP_SCALER(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPFORMAT_TMP_SCALER_SHIFT)) & POWERQUAD_TMPFORMAT_TMP_SCALER_MASK) +/*! @} */ + +/*! @name INABASE - Base address register for input A region */ +/*! @{ */ +#define POWERQUAD_INABASE_INABASE_MASK (0xFFFFFFFFU) +#define POWERQUAD_INABASE_INABASE_SHIFT (0U) +#define POWERQUAD_INABASE_INABASE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INABASE_INABASE_SHIFT)) & POWERQUAD_INABASE_INABASE_MASK) +/*! @} */ + +/*! @name INAFORMAT - Input A format */ +/*! @{ */ +#define POWERQUAD_INAFORMAT_INA_FORMATINT_MASK (0x3U) +#define POWERQUAD_INAFORMAT_INA_FORMATINT_SHIFT (0U) +#define POWERQUAD_INAFORMAT_INA_FORMATINT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INAFORMAT_INA_FORMATINT_SHIFT)) & POWERQUAD_INAFORMAT_INA_FORMATINT_MASK) +#define POWERQUAD_INAFORMAT_INA_FORMATEXT_MASK (0x30U) +#define POWERQUAD_INAFORMAT_INA_FORMATEXT_SHIFT (4U) +#define POWERQUAD_INAFORMAT_INA_FORMATEXT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INAFORMAT_INA_FORMATEXT_SHIFT)) & POWERQUAD_INAFORMAT_INA_FORMATEXT_MASK) +#define POWERQUAD_INAFORMAT_INA_SCALER_MASK (0xFF00U) +#define POWERQUAD_INAFORMAT_INA_SCALER_SHIFT (8U) +#define POWERQUAD_INAFORMAT_INA_SCALER(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INAFORMAT_INA_SCALER_SHIFT)) & POWERQUAD_INAFORMAT_INA_SCALER_MASK) +/*! @} */ + +/*! @name INBBASE - Base address register for input B region */ +/*! @{ */ +#define POWERQUAD_INBBASE_INBBASE_MASK (0xFFFFFFFFU) +#define POWERQUAD_INBBASE_INBBASE_SHIFT (0U) +#define POWERQUAD_INBBASE_INBBASE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBBASE_INBBASE_SHIFT)) & POWERQUAD_INBBASE_INBBASE_MASK) +/*! @} */ + +/*! @name INBFORMAT - Input B format */ +/*! @{ */ +#define POWERQUAD_INBFORMAT_INB_FORMATINT_MASK (0x3U) +#define POWERQUAD_INBFORMAT_INB_FORMATINT_SHIFT (0U) +#define POWERQUAD_INBFORMAT_INB_FORMATINT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBFORMAT_INB_FORMATINT_SHIFT)) & POWERQUAD_INBFORMAT_INB_FORMATINT_MASK) +#define POWERQUAD_INBFORMAT_INB_FORMATEXT_MASK (0x30U) +#define POWERQUAD_INBFORMAT_INB_FORMATEXT_SHIFT (4U) +#define POWERQUAD_INBFORMAT_INB_FORMATEXT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBFORMAT_INB_FORMATEXT_SHIFT)) & POWERQUAD_INBFORMAT_INB_FORMATEXT_MASK) +#define POWERQUAD_INBFORMAT_INB_SCALER_MASK (0xFF00U) +#define POWERQUAD_INBFORMAT_INB_SCALER_SHIFT (8U) +#define POWERQUAD_INBFORMAT_INB_SCALER(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBFORMAT_INB_SCALER_SHIFT)) & POWERQUAD_INBFORMAT_INB_SCALER_MASK) +/*! @} */ + +/*! @name CONTROL - PowerQuad Control register */ +/*! @{ */ +#define POWERQUAD_CONTROL_DECODE_OPCODE_MASK (0xFU) +#define POWERQUAD_CONTROL_DECODE_OPCODE_SHIFT (0U) +#define POWERQUAD_CONTROL_DECODE_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CONTROL_DECODE_OPCODE_SHIFT)) & POWERQUAD_CONTROL_DECODE_OPCODE_MASK) +#define POWERQUAD_CONTROL_DECODE_MACHINE_MASK (0xF0U) +#define POWERQUAD_CONTROL_DECODE_MACHINE_SHIFT (4U) +#define POWERQUAD_CONTROL_DECODE_MACHINE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CONTROL_DECODE_MACHINE_SHIFT)) & POWERQUAD_CONTROL_DECODE_MACHINE_MASK) +#define POWERQUAD_CONTROL_INST_BUSY_MASK (0x80000000U) +#define POWERQUAD_CONTROL_INST_BUSY_SHIFT (31U) +#define POWERQUAD_CONTROL_INST_BUSY(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CONTROL_INST_BUSY_SHIFT)) & POWERQUAD_CONTROL_INST_BUSY_MASK) +/*! @} */ + +/*! @name LENGTH - Length register */ +/*! @{ */ +#define POWERQUAD_LENGTH_INST_LENGTH_MASK (0xFFFFFFFFU) +#define POWERQUAD_LENGTH_INST_LENGTH_SHIFT (0U) +#define POWERQUAD_LENGTH_INST_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_LENGTH_INST_LENGTH_SHIFT)) & POWERQUAD_LENGTH_INST_LENGTH_MASK) +/*! @} */ + +/*! @name CPPRE - Pre-scale register */ +/*! @{ */ +#define POWERQUAD_CPPRE_CPPRE_IN_MASK (0xFFU) +#define POWERQUAD_CPPRE_CPPRE_IN_SHIFT (0U) +#define POWERQUAD_CPPRE_CPPRE_IN(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_IN_SHIFT)) & POWERQUAD_CPPRE_CPPRE_IN_MASK) +#define POWERQUAD_CPPRE_CPPRE_OUT_MASK (0xFF00U) +#define POWERQUAD_CPPRE_CPPRE_OUT_SHIFT (8U) +#define POWERQUAD_CPPRE_CPPRE_OUT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_OUT_SHIFT)) & POWERQUAD_CPPRE_CPPRE_OUT_MASK) +#define POWERQUAD_CPPRE_CPPRE_SAT_MASK (0x10000U) +#define POWERQUAD_CPPRE_CPPRE_SAT_SHIFT (16U) +#define POWERQUAD_CPPRE_CPPRE_SAT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_SAT_SHIFT)) & POWERQUAD_CPPRE_CPPRE_SAT_MASK) +#define POWERQUAD_CPPRE_CPPRE_SAT8_MASK (0x20000U) +#define POWERQUAD_CPPRE_CPPRE_SAT8_SHIFT (17U) +#define POWERQUAD_CPPRE_CPPRE_SAT8(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_SAT8_SHIFT)) & POWERQUAD_CPPRE_CPPRE_SAT8_MASK) +/*! @} */ + +/*! @name MISC - Misc register */ +/*! @{ */ +#define POWERQUAD_MISC_INST_MISC_MASK (0xFFFFFFFFU) +#define POWERQUAD_MISC_INST_MISC_SHIFT (0U) +#define POWERQUAD_MISC_INST_MISC(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_MISC_INST_MISC_SHIFT)) & POWERQUAD_MISC_INST_MISC_MASK) +/*! @} */ + +/*! @name CURSORY - Cursory register */ +/*! @{ */ +#define POWERQUAD_CURSORY_CURSORY_MASK (0x1U) +#define POWERQUAD_CURSORY_CURSORY_SHIFT (0U) +#define POWERQUAD_CURSORY_CURSORY(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CURSORY_CURSORY_SHIFT)) & POWERQUAD_CURSORY_CURSORY_MASK) +/*! @} */ + +/*! @name CORDIC_X - Cordic input X register */ +/*! @{ */ +#define POWERQUAD_CORDIC_X_CORDIC_X_MASK (0xFFFFFFFFU) +#define POWERQUAD_CORDIC_X_CORDIC_X_SHIFT (0U) +#define POWERQUAD_CORDIC_X_CORDIC_X(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CORDIC_X_CORDIC_X_SHIFT)) & POWERQUAD_CORDIC_X_CORDIC_X_MASK) +/*! @} */ + +/*! @name CORDIC_Y - Cordic input Y register */ +/*! @{ */ +#define POWERQUAD_CORDIC_Y_CORDIC_Y_MASK (0xFFFFFFFFU) +#define POWERQUAD_CORDIC_Y_CORDIC_Y_SHIFT (0U) +#define POWERQUAD_CORDIC_Y_CORDIC_Y(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CORDIC_Y_CORDIC_Y_SHIFT)) & POWERQUAD_CORDIC_Y_CORDIC_Y_MASK) +/*! @} */ + +/*! @name CORDIC_Z - Cordic input Z register */ +/*! @{ */ +#define POWERQUAD_CORDIC_Z_CORDIC_Z_MASK (0xFFFFFFFFU) +#define POWERQUAD_CORDIC_Z_CORDIC_Z_SHIFT (0U) +#define POWERQUAD_CORDIC_Z_CORDIC_Z(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CORDIC_Z_CORDIC_Z_SHIFT)) & POWERQUAD_CORDIC_Z_CORDIC_Z_MASK) +/*! @} */ + +/*! @name ERRSTAT - Read/Write register where error statuses are captured (sticky) */ +/*! @{ */ +#define POWERQUAD_ERRSTAT_OVERFLOW_MASK (0x1U) +#define POWERQUAD_ERRSTAT_OVERFLOW_SHIFT (0U) +#define POWERQUAD_ERRSTAT_OVERFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_OVERFLOW_SHIFT)) & POWERQUAD_ERRSTAT_OVERFLOW_MASK) +#define POWERQUAD_ERRSTAT_NAN_MASK (0x2U) +#define POWERQUAD_ERRSTAT_NAN_SHIFT (1U) +#define POWERQUAD_ERRSTAT_NAN(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_NAN_SHIFT)) & POWERQUAD_ERRSTAT_NAN_MASK) +#define POWERQUAD_ERRSTAT_FIXEDOVERFLOW_MASK (0x4U) +#define POWERQUAD_ERRSTAT_FIXEDOVERFLOW_SHIFT (2U) +#define POWERQUAD_ERRSTAT_FIXEDOVERFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_FIXEDOVERFLOW_SHIFT)) & POWERQUAD_ERRSTAT_FIXEDOVERFLOW_MASK) +#define POWERQUAD_ERRSTAT_UNDERFLOW_MASK (0x8U) +#define POWERQUAD_ERRSTAT_UNDERFLOW_SHIFT (3U) +#define POWERQUAD_ERRSTAT_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_UNDERFLOW_SHIFT)) & POWERQUAD_ERRSTAT_UNDERFLOW_MASK) +#define POWERQUAD_ERRSTAT_BUSERROR_MASK (0x10U) +#define POWERQUAD_ERRSTAT_BUSERROR_SHIFT (4U) +#define POWERQUAD_ERRSTAT_BUSERROR(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_BUSERROR_SHIFT)) & POWERQUAD_ERRSTAT_BUSERROR_MASK) +/*! @} */ + +/*! @name INTREN - INTERRUPT enable register */ +/*! @{ */ +#define POWERQUAD_INTREN_INTR_OFLOW_MASK (0x1U) +#define POWERQUAD_INTREN_INTR_OFLOW_SHIFT (0U) +#define POWERQUAD_INTREN_INTR_OFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_OFLOW_SHIFT)) & POWERQUAD_INTREN_INTR_OFLOW_MASK) +#define POWERQUAD_INTREN_INTR_NAN_MASK (0x2U) +#define POWERQUAD_INTREN_INTR_NAN_SHIFT (1U) +#define POWERQUAD_INTREN_INTR_NAN(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_NAN_SHIFT)) & POWERQUAD_INTREN_INTR_NAN_MASK) +#define POWERQUAD_INTREN_INTR_FIXED_MASK (0x4U) +#define POWERQUAD_INTREN_INTR_FIXED_SHIFT (2U) +#define POWERQUAD_INTREN_INTR_FIXED(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_FIXED_SHIFT)) & POWERQUAD_INTREN_INTR_FIXED_MASK) +#define POWERQUAD_INTREN_INTR_UFLOW_MASK (0x8U) +#define POWERQUAD_INTREN_INTR_UFLOW_SHIFT (3U) +#define POWERQUAD_INTREN_INTR_UFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_UFLOW_SHIFT)) & POWERQUAD_INTREN_INTR_UFLOW_MASK) +#define POWERQUAD_INTREN_INTR_BERR_MASK (0x10U) +#define POWERQUAD_INTREN_INTR_BERR_SHIFT (4U) +#define POWERQUAD_INTREN_INTR_BERR(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_BERR_SHIFT)) & POWERQUAD_INTREN_INTR_BERR_MASK) +#define POWERQUAD_INTREN_INTR_COMP_MASK (0x80U) +#define POWERQUAD_INTREN_INTR_COMP_SHIFT (7U) +#define POWERQUAD_INTREN_INTR_COMP(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_COMP_SHIFT)) & POWERQUAD_INTREN_INTR_COMP_MASK) +/*! @} */ + +/*! @name EVENTEN - Event Enable register */ +/*! @{ */ +#define POWERQUAD_EVENTEN_EVENT_OFLOW_MASK (0x1U) +#define POWERQUAD_EVENTEN_EVENT_OFLOW_SHIFT (0U) +#define POWERQUAD_EVENTEN_EVENT_OFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_OFLOW_SHIFT)) & POWERQUAD_EVENTEN_EVENT_OFLOW_MASK) +#define POWERQUAD_EVENTEN_EVENT_NAN_MASK (0x2U) +#define POWERQUAD_EVENTEN_EVENT_NAN_SHIFT (1U) +#define POWERQUAD_EVENTEN_EVENT_NAN(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_NAN_SHIFT)) & POWERQUAD_EVENTEN_EVENT_NAN_MASK) +#define POWERQUAD_EVENTEN_EVENT_FIXED_MASK (0x4U) +#define POWERQUAD_EVENTEN_EVENT_FIXED_SHIFT (2U) +#define POWERQUAD_EVENTEN_EVENT_FIXED(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_FIXED_SHIFT)) & POWERQUAD_EVENTEN_EVENT_FIXED_MASK) +#define POWERQUAD_EVENTEN_EVENT_UFLOW_MASK (0x8U) +#define POWERQUAD_EVENTEN_EVENT_UFLOW_SHIFT (3U) +#define POWERQUAD_EVENTEN_EVENT_UFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_UFLOW_SHIFT)) & POWERQUAD_EVENTEN_EVENT_UFLOW_MASK) +#define POWERQUAD_EVENTEN_EVENT_BERR_MASK (0x10U) +#define POWERQUAD_EVENTEN_EVENT_BERR_SHIFT (4U) +#define POWERQUAD_EVENTEN_EVENT_BERR(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_BERR_SHIFT)) & POWERQUAD_EVENTEN_EVENT_BERR_MASK) +#define POWERQUAD_EVENTEN_EVENT_COMP_MASK (0x80U) +#define POWERQUAD_EVENTEN_EVENT_COMP_SHIFT (7U) +#define POWERQUAD_EVENTEN_EVENT_COMP(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_COMP_SHIFT)) & POWERQUAD_EVENTEN_EVENT_COMP_MASK) +/*! @} */ + +/*! @name INTRSTAT - INTERRUPT STATUS register */ +/*! @{ */ +#define POWERQUAD_INTRSTAT_INTR_STAT_MASK (0x1U) +#define POWERQUAD_INTRSTAT_INTR_STAT_SHIFT (0U) +#define POWERQUAD_INTRSTAT_INTR_STAT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTRSTAT_INTR_STAT_SHIFT)) & POWERQUAD_INTRSTAT_INTR_STAT_MASK) +/*! @} */ + +/*! @name GPREG - General purpose register bank N. */ +/*! @{ */ +#define POWERQUAD_GPREG_GPREG_MASK (0xFFFFFFFFU) +#define POWERQUAD_GPREG_GPREG_SHIFT (0U) +#define POWERQUAD_GPREG_GPREG(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_GPREG_GPREG_SHIFT)) & POWERQUAD_GPREG_GPREG_MASK) +/*! @} */ + +/* The count of POWERQUAD_GPREG */ +#define POWERQUAD_GPREG_COUNT (16U) + +/*! @name COMPREGS_COMPREG - Compute register bank */ +/*! @{ */ +#define POWERQUAD_COMPREGS_COMPREG_COMPREG_MASK (0xFFFFFFFFU) +#define POWERQUAD_COMPREGS_COMPREG_COMPREG_SHIFT (0U) +#define POWERQUAD_COMPREGS_COMPREG_COMPREG(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_COMPREGS_COMPREG_COMPREG_SHIFT)) & POWERQUAD_COMPREGS_COMPREG_COMPREG_MASK) +/*! @} */ + +/* The count of POWERQUAD_COMPREGS_COMPREG */ +#define POWERQUAD_COMPREGS_COMPREG_COUNT (8U) + + +/*! + * @} + */ /* end of group POWERQUAD_Register_Masks */ + + +/* POWERQUAD - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral POWERQUAD base address */ + #define POWERQUAD_BASE (0x500A6000u) + /** Peripheral POWERQUAD base address */ + #define POWERQUAD_BASE_NS (0x400A6000u) + /** Peripheral POWERQUAD base pointer */ + #define POWERQUAD ((POWERQUAD_Type *)POWERQUAD_BASE) + /** Peripheral POWERQUAD base pointer */ + #define POWERQUAD_NS ((POWERQUAD_Type *)POWERQUAD_BASE_NS) + /** Array initializer of POWERQUAD peripheral base addresses */ + #define POWERQUAD_BASE_ADDRS { POWERQUAD_BASE } + /** Array initializer of POWERQUAD peripheral base pointers */ + #define POWERQUAD_BASE_PTRS { POWERQUAD } + /** Array initializer of POWERQUAD peripheral base addresses */ + #define POWERQUAD_BASE_ADDRS_NS { POWERQUAD_BASE_NS } + /** Array initializer of POWERQUAD peripheral base pointers */ + #define POWERQUAD_BASE_PTRS_NS { POWERQUAD_NS } +#else + /** Peripheral POWERQUAD base address */ + #define POWERQUAD_BASE (0x400A6000u) + /** Peripheral POWERQUAD base pointer */ + #define POWERQUAD ((POWERQUAD_Type *)POWERQUAD_BASE) + /** Array initializer of POWERQUAD peripheral base addresses */ + #define POWERQUAD_BASE_ADDRS { POWERQUAD_BASE } + /** Array initializer of POWERQUAD peripheral base pointers */ + #define POWERQUAD_BASE_PTRS { POWERQUAD } +#endif + +/*! + * @} + */ /* end of group POWERQUAD_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PRINCE Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PRINCE_Peripheral_Access_Layer PRINCE Peripheral Access Layer + * @{ + */ + +/** PRINCE - Register Layout Typedef */ +typedef struct { + __IO uint32_t ENC_ENABLE; /**< Encryption Enable register, offset: 0x0 */ + __O uint32_t MASK_LSB; /**< Data Mask register, 32 Least Significant Bits, offset: 0x4 */ + __O uint32_t MASK_MSB; /**< Data Mask register, 32 Most Significant Bits, offset: 0x8 */ + __IO uint32_t LOCK; /**< Lock register, offset: 0xC */ + __O uint32_t IV_LSB0; /**< Initial Vector register for region 0, Least Significant Bits, offset: 0x10 */ + __O uint32_t IV_MSB0; /**< Initial Vector register for region 0, Most Significant Bits, offset: 0x14 */ + __IO uint32_t BASE_ADDR0; /**< Base Address for region 0 register, offset: 0x18 */ + __IO uint32_t SR_ENABLE0; /**< Sub-Region Enable register for region 0, offset: 0x1C */ + __O uint32_t IV_LSB1; /**< Initial Vector register for region 1, Least Significant Bits, offset: 0x20 */ + __O uint32_t IV_MSB1; /**< Initial Vector register for region 1, Most Significant Bits, offset: 0x24 */ + __IO uint32_t BASE_ADDR1; /**< Base Address for region 1 register, offset: 0x28 */ + __IO uint32_t SR_ENABLE1; /**< Sub-Region Enable register for region 1, offset: 0x2C */ + __O uint32_t IV_LSB2; /**< Initial Vector register for region 2, Least Significant Bits, offset: 0x30 */ + __O uint32_t IV_MSB2; /**< Initial Vector register for region 2, Most Significant Bits, offset: 0x34 */ + __IO uint32_t BASE_ADDR2; /**< Base Address for region 2 register, offset: 0x38 */ + __IO uint32_t SR_ENABLE2; /**< Sub-Region Enable register for region 2, offset: 0x3C */ +} PRINCE_Type; + +/* ---------------------------------------------------------------------------- + -- PRINCE Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PRINCE_Register_Masks PRINCE Register Masks + * @{ + */ + +/*! @name ENC_ENABLE - Encryption Enable register */ +/*! @{ */ +#define PRINCE_ENC_ENABLE_EN_MASK (0x1U) +#define PRINCE_ENC_ENABLE_EN_SHIFT (0U) +/*! EN - Encryption Enable. + * 0b0..Encryption of writes to the flash controller DATAW* registers is disabled.. + * 0b1..Encryption of writes to the flash controller DATAW* registers is enabled.. + */ +#define PRINCE_ENC_ENABLE_EN(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_ENC_ENABLE_EN_SHIFT)) & PRINCE_ENC_ENABLE_EN_MASK) +/*! @} */ + +/*! @name MASK_LSB - Data Mask register, 32 Least Significant Bits */ +/*! @{ */ +#define PRINCE_MASK_LSB_MASKVAL_MASK (0xFFFFFFFFU) +#define PRINCE_MASK_LSB_MASKVAL_SHIFT (0U) +#define PRINCE_MASK_LSB_MASKVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_MASK_LSB_MASKVAL_SHIFT)) & PRINCE_MASK_LSB_MASKVAL_MASK) +/*! @} */ + +/*! @name MASK_MSB - Data Mask register, 32 Most Significant Bits */ +/*! @{ */ +#define PRINCE_MASK_MSB_MASKVAL_MASK (0xFFFFFFFFU) +#define PRINCE_MASK_MSB_MASKVAL_SHIFT (0U) +#define PRINCE_MASK_MSB_MASKVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_MASK_MSB_MASKVAL_SHIFT)) & PRINCE_MASK_MSB_MASKVAL_MASK) +/*! @} */ + +/*! @name LOCK - Lock register */ +/*! @{ */ +#define PRINCE_LOCK_LOCKREG0_MASK (0x1U) +#define PRINCE_LOCK_LOCKREG0_SHIFT (0U) +/*! LOCKREG0 - Lock Region 0 registers. + * 0b0..Disabled. IV_LSB0, IV_MSB0, BASE_ADDR0, and SR_ENABLE0 are writable.. + * 0b1..Enabled. IV_LSB0, IV_MSB0, BASE_ADDR0, and SR_ENABLE0 are not writable.. + */ +#define PRINCE_LOCK_LOCKREG0(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKREG0_SHIFT)) & PRINCE_LOCK_LOCKREG0_MASK) +#define PRINCE_LOCK_LOCKREG1_MASK (0x2U) +#define PRINCE_LOCK_LOCKREG1_SHIFT (1U) +/*! LOCKREG1 - Lock Region 1 registers. + * 0b0..Disabled. IV_LSB1, IV_MSB1, BASE_ADDR1, and SR_ENABLE1 are writable.. + * 0b1..Enabled. IV_LSB1, IV_MSB1, BASE_ADDR1, and SR_ENABLE1 are not writable.. + */ +#define PRINCE_LOCK_LOCKREG1(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKREG1_SHIFT)) & PRINCE_LOCK_LOCKREG1_MASK) +#define PRINCE_LOCK_LOCKREG2_MASK (0x4U) +#define PRINCE_LOCK_LOCKREG2_SHIFT (2U) +/*! LOCKREG2 - Lock Region 2 registers. + * 0b0..Disabled. IV_LSB2, IV_MSB2, BASE_ADDR2, and SR_ENABLE2 are writable.. + * 0b1..Enabled. IV_LSB2, IV_MSB2, BASE_ADDR2, and SR_ENABLE2 are not writable.. + */ +#define PRINCE_LOCK_LOCKREG2(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKREG2_SHIFT)) & PRINCE_LOCK_LOCKREG2_MASK) +#define PRINCE_LOCK_LOCKMASK_MASK (0x100U) +#define PRINCE_LOCK_LOCKMASK_SHIFT (8U) +/*! LOCKMASK - Lock the Mask registers. + * 0b0..Disabled. MASK_LSB, and MASK_MSB are writable.. + * 0b1..Enabled. MASK_LSB, and MASK_MSB are not writable.. + */ +#define PRINCE_LOCK_LOCKMASK(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKMASK_SHIFT)) & PRINCE_LOCK_LOCKMASK_MASK) +/*! @} */ + +/*! @name IV_LSB0 - Initial Vector register for region 0, Least Significant Bits */ +/*! @{ */ +#define PRINCE_IV_LSB0_IVVAL_MASK (0xFFFFFFFFU) +#define PRINCE_IV_LSB0_IVVAL_SHIFT (0U) +#define PRINCE_IV_LSB0_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_LSB0_IVVAL_SHIFT)) & PRINCE_IV_LSB0_IVVAL_MASK) +/*! @} */ + +/*! @name IV_MSB0 - Initial Vector register for region 0, Most Significant Bits */ +/*! @{ */ +#define PRINCE_IV_MSB0_IVVAL_MASK (0xFFFFFFFFU) +#define PRINCE_IV_MSB0_IVVAL_SHIFT (0U) +#define PRINCE_IV_MSB0_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_MSB0_IVVAL_SHIFT)) & PRINCE_IV_MSB0_IVVAL_MASK) +/*! @} */ + +/*! @name BASE_ADDR0 - Base Address for region 0 register */ +/*! @{ */ +#define PRINCE_BASE_ADDR0_ADDR_FIXED_MASK (0x3FFFFU) +#define PRINCE_BASE_ADDR0_ADDR_FIXED_SHIFT (0U) +#define PRINCE_BASE_ADDR0_ADDR_FIXED(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR0_ADDR_FIXED_SHIFT)) & PRINCE_BASE_ADDR0_ADDR_FIXED_MASK) +#define PRINCE_BASE_ADDR0_ADDR_PRG_MASK (0xC0000U) +#define PRINCE_BASE_ADDR0_ADDR_PRG_SHIFT (18U) +#define PRINCE_BASE_ADDR0_ADDR_PRG(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR0_ADDR_PRG_SHIFT)) & PRINCE_BASE_ADDR0_ADDR_PRG_MASK) +/*! @} */ + +/*! @name SR_ENABLE0 - Sub-Region Enable register for region 0 */ +/*! @{ */ +#define PRINCE_SR_ENABLE0_EN_MASK (0xFFFFFFFFU) +#define PRINCE_SR_ENABLE0_EN_SHIFT (0U) +#define PRINCE_SR_ENABLE0_EN(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_SR_ENABLE0_EN_SHIFT)) & PRINCE_SR_ENABLE0_EN_MASK) +/*! @} */ + +/*! @name IV_LSB1 - Initial Vector register for region 1, Least Significant Bits */ +/*! @{ */ +#define PRINCE_IV_LSB1_IVVAL_MASK (0xFFFFFFFFU) +#define PRINCE_IV_LSB1_IVVAL_SHIFT (0U) +#define PRINCE_IV_LSB1_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_LSB1_IVVAL_SHIFT)) & PRINCE_IV_LSB1_IVVAL_MASK) +/*! @} */ + +/*! @name IV_MSB1 - Initial Vector register for region 1, Most Significant Bits */ +/*! @{ */ +#define PRINCE_IV_MSB1_IVVAL_MASK (0xFFFFFFFFU) +#define PRINCE_IV_MSB1_IVVAL_SHIFT (0U) +#define PRINCE_IV_MSB1_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_MSB1_IVVAL_SHIFT)) & PRINCE_IV_MSB1_IVVAL_MASK) +/*! @} */ + +/*! @name BASE_ADDR1 - Base Address for region 1 register */ +/*! @{ */ +#define PRINCE_BASE_ADDR1_ADDR_FIXED_MASK (0x3FFFFU) +#define PRINCE_BASE_ADDR1_ADDR_FIXED_SHIFT (0U) +#define PRINCE_BASE_ADDR1_ADDR_FIXED(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR1_ADDR_FIXED_SHIFT)) & PRINCE_BASE_ADDR1_ADDR_FIXED_MASK) +#define PRINCE_BASE_ADDR1_ADDR_PRG_MASK (0xC0000U) +#define PRINCE_BASE_ADDR1_ADDR_PRG_SHIFT (18U) +#define PRINCE_BASE_ADDR1_ADDR_PRG(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR1_ADDR_PRG_SHIFT)) & PRINCE_BASE_ADDR1_ADDR_PRG_MASK) +/*! @} */ + +/*! @name SR_ENABLE1 - Sub-Region Enable register for region 1 */ +/*! @{ */ +#define PRINCE_SR_ENABLE1_EN_MASK (0xFFFFFFFFU) +#define PRINCE_SR_ENABLE1_EN_SHIFT (0U) +#define PRINCE_SR_ENABLE1_EN(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_SR_ENABLE1_EN_SHIFT)) & PRINCE_SR_ENABLE1_EN_MASK) +/*! @} */ + +/*! @name IV_LSB2 - Initial Vector register for region 2, Least Significant Bits */ +/*! @{ */ +#define PRINCE_IV_LSB2_IVVAL_MASK (0xFFFFFFFFU) +#define PRINCE_IV_LSB2_IVVAL_SHIFT (0U) +#define PRINCE_IV_LSB2_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_LSB2_IVVAL_SHIFT)) & PRINCE_IV_LSB2_IVVAL_MASK) +/*! @} */ + +/*! @name IV_MSB2 - Initial Vector register for region 2, Most Significant Bits */ +/*! @{ */ +#define PRINCE_IV_MSB2_IVVAL_MASK (0xFFFFFFFFU) +#define PRINCE_IV_MSB2_IVVAL_SHIFT (0U) +#define PRINCE_IV_MSB2_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_MSB2_IVVAL_SHIFT)) & PRINCE_IV_MSB2_IVVAL_MASK) +/*! @} */ + +/*! @name BASE_ADDR2 - Base Address for region 2 register */ +/*! @{ */ +#define PRINCE_BASE_ADDR2_ADDR_FIXED_MASK (0x3FFFFU) +#define PRINCE_BASE_ADDR2_ADDR_FIXED_SHIFT (0U) +#define PRINCE_BASE_ADDR2_ADDR_FIXED(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR2_ADDR_FIXED_SHIFT)) & PRINCE_BASE_ADDR2_ADDR_FIXED_MASK) +#define PRINCE_BASE_ADDR2_ADDR_PRG_MASK (0xC0000U) +#define PRINCE_BASE_ADDR2_ADDR_PRG_SHIFT (18U) +#define PRINCE_BASE_ADDR2_ADDR_PRG(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR2_ADDR_PRG_SHIFT)) & PRINCE_BASE_ADDR2_ADDR_PRG_MASK) +/*! @} */ + +/*! @name SR_ENABLE2 - Sub-Region Enable register for region 2 */ +/*! @{ */ +#define PRINCE_SR_ENABLE2_EN_MASK (0xFFFFFFFFU) +#define PRINCE_SR_ENABLE2_EN_SHIFT (0U) +#define PRINCE_SR_ENABLE2_EN(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_SR_ENABLE2_EN_SHIFT)) & PRINCE_SR_ENABLE2_EN_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group PRINCE_Register_Masks */ + + +/* PRINCE - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral PRINCE base address */ + #define PRINCE_BASE (0x50035000u) + /** Peripheral PRINCE base address */ + #define PRINCE_BASE_NS (0x40035000u) + /** Peripheral PRINCE base pointer */ + #define PRINCE ((PRINCE_Type *)PRINCE_BASE) + /** Peripheral PRINCE base pointer */ + #define PRINCE_NS ((PRINCE_Type *)PRINCE_BASE_NS) + /** Array initializer of PRINCE peripheral base addresses */ + #define PRINCE_BASE_ADDRS { PRINCE_BASE } + /** Array initializer of PRINCE peripheral base pointers */ + #define PRINCE_BASE_PTRS { PRINCE } + /** Array initializer of PRINCE peripheral base addresses */ + #define PRINCE_BASE_ADDRS_NS { PRINCE_BASE_NS } + /** Array initializer of PRINCE peripheral base pointers */ + #define PRINCE_BASE_PTRS_NS { PRINCE_NS } +#else + /** Peripheral PRINCE base address */ + #define PRINCE_BASE (0x40035000u) + /** Peripheral PRINCE base pointer */ + #define PRINCE ((PRINCE_Type *)PRINCE_BASE) + /** Array initializer of PRINCE peripheral base addresses */ + #define PRINCE_BASE_ADDRS { PRINCE_BASE } + /** Array initializer of PRINCE peripheral base pointers */ + #define PRINCE_BASE_PTRS { PRINCE } +#endif + +/*! + * @} + */ /* end of group PRINCE_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PUF Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PUF_Peripheral_Access_Layer PUF Peripheral Access Layer + * @{ + */ + +/** PUF - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< PUF Control register, offset: 0x0 */ + __IO uint32_t KEYINDEX; /**< PUF Key Index register, offset: 0x4 */ + __IO uint32_t KEYSIZE; /**< PUF Key Size register, offset: 0x8 */ + uint8_t RESERVED_0[20]; + __I uint32_t STAT; /**< PUF Status register, offset: 0x20 */ + uint8_t RESERVED_1[4]; + __I uint32_t ALLOW; /**< PUF Allow register, offset: 0x28 */ + uint8_t RESERVED_2[20]; + __O uint32_t KEYINPUT; /**< PUF Key Input register, offset: 0x40 */ + __O uint32_t CODEINPUT; /**< PUF Code Input register, offset: 0x44 */ + __I uint32_t CODEOUTPUT; /**< PUF Code Output register, offset: 0x48 */ + uint8_t RESERVED_3[20]; + __I uint32_t KEYOUTINDEX; /**< PUF Key Output Index register, offset: 0x60 */ + __I uint32_t KEYOUTPUT; /**< PUF Key Output register, offset: 0x64 */ + uint8_t RESERVED_4[116]; + __IO uint32_t IFSTAT; /**< PUF Interface Status and clear register, offset: 0xDC */ + uint8_t RESERVED_5[28]; + __I uint32_t VERSION; /**< PUF version register., offset: 0xFC */ + __IO uint32_t INTEN; /**< PUF Interrupt Enable, offset: 0x100 */ + __IO uint32_t INTSTAT; /**< PUF interrupt status, offset: 0x104 */ + __IO uint32_t PWRCTRL; /**< PUF RAM Power Control, offset: 0x108 */ + __IO uint32_t CFG; /**< PUF config register for block bits, offset: 0x10C */ + uint8_t RESERVED_6[240]; + __IO uint32_t KEYLOCK; /**< Only reset in case of full IC reset, offset: 0x200 */ + __IO uint32_t KEYENABLE; /**< , offset: 0x204 */ + __O uint32_t KEYRESET; /**< Reinitialize Keys shift registers counters, offset: 0x208 */ + __IO uint32_t IDXBLK_L; /**< , offset: 0x20C */ + __IO uint32_t IDXBLK_H_DP; /**< , offset: 0x210 */ + __O uint32_t KEYMASK[4]; /**< Only reset in case of full IC reset, array offset: 0x214, array step: 0x4 */ + uint8_t RESERVED_7[48]; + __IO uint32_t IDXBLK_H; /**< , offset: 0x254 */ + __IO uint32_t IDXBLK_L_DP; /**< , offset: 0x258 */ + __I uint32_t SHIFT_STATUS; /**< , offset: 0x25C */ +} PUF_Type; + +/* ---------------------------------------------------------------------------- + -- PUF Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PUF_Register_Masks PUF Register Masks + * @{ + */ + +/*! @name CTRL - PUF Control register */ +/*! @{ */ +#define PUF_CTRL_ZEROIZE_MASK (0x1U) +#define PUF_CTRL_ZEROIZE_SHIFT (0U) +#define PUF_CTRL_ZEROIZE(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_ZEROIZE_SHIFT)) & PUF_CTRL_ZEROIZE_MASK) +#define PUF_CTRL_ENROLL_MASK (0x2U) +#define PUF_CTRL_ENROLL_SHIFT (1U) +#define PUF_CTRL_ENROLL(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_ENROLL_SHIFT)) & PUF_CTRL_ENROLL_MASK) +#define PUF_CTRL_START_MASK (0x4U) +#define PUF_CTRL_START_SHIFT (2U) +#define PUF_CTRL_START(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_START_SHIFT)) & PUF_CTRL_START_MASK) +#define PUF_CTRL_GENERATEKEY_MASK (0x8U) +#define PUF_CTRL_GENERATEKEY_SHIFT (3U) +#define PUF_CTRL_GENERATEKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_GENERATEKEY_SHIFT)) & PUF_CTRL_GENERATEKEY_MASK) +#define PUF_CTRL_SETKEY_MASK (0x10U) +#define PUF_CTRL_SETKEY_SHIFT (4U) +#define PUF_CTRL_SETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_SETKEY_SHIFT)) & PUF_CTRL_SETKEY_MASK) +#define PUF_CTRL_GETKEY_MASK (0x40U) +#define PUF_CTRL_GETKEY_SHIFT (6U) +#define PUF_CTRL_GETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_GETKEY_SHIFT)) & PUF_CTRL_GETKEY_MASK) +/*! @} */ + +/*! @name KEYINDEX - PUF Key Index register */ +/*! @{ */ +#define PUF_KEYINDEX_KEYIDX_MASK (0xFU) +#define PUF_KEYINDEX_KEYIDX_SHIFT (0U) +#define PUF_KEYINDEX_KEYIDX(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYINDEX_KEYIDX_SHIFT)) & PUF_KEYINDEX_KEYIDX_MASK) +/*! @} */ + +/*! @name KEYSIZE - PUF Key Size register */ +/*! @{ */ +#define PUF_KEYSIZE_KEYSIZE_MASK (0x3FU) +#define PUF_KEYSIZE_KEYSIZE_SHIFT (0U) +#define PUF_KEYSIZE_KEYSIZE(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYSIZE_KEYSIZE_SHIFT)) & PUF_KEYSIZE_KEYSIZE_MASK) +/*! @} */ + +/*! @name STAT - PUF Status register */ +/*! @{ */ +#define PUF_STAT_BUSY_MASK (0x1U) +#define PUF_STAT_BUSY_SHIFT (0U) +#define PUF_STAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_BUSY_SHIFT)) & PUF_STAT_BUSY_MASK) +#define PUF_STAT_SUCCESS_MASK (0x2U) +#define PUF_STAT_SUCCESS_SHIFT (1U) +#define PUF_STAT_SUCCESS(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_SUCCESS_SHIFT)) & PUF_STAT_SUCCESS_MASK) +#define PUF_STAT_ERROR_MASK (0x4U) +#define PUF_STAT_ERROR_SHIFT (2U) +#define PUF_STAT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_ERROR_SHIFT)) & PUF_STAT_ERROR_MASK) +#define PUF_STAT_KEYINREQ_MASK (0x10U) +#define PUF_STAT_KEYINREQ_SHIFT (4U) +#define PUF_STAT_KEYINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_KEYINREQ_SHIFT)) & PUF_STAT_KEYINREQ_MASK) +#define PUF_STAT_KEYOUTAVAIL_MASK (0x20U) +#define PUF_STAT_KEYOUTAVAIL_SHIFT (5U) +#define PUF_STAT_KEYOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_KEYOUTAVAIL_SHIFT)) & PUF_STAT_KEYOUTAVAIL_MASK) +#define PUF_STAT_CODEINREQ_MASK (0x40U) +#define PUF_STAT_CODEINREQ_SHIFT (6U) +#define PUF_STAT_CODEINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_CODEINREQ_SHIFT)) & PUF_STAT_CODEINREQ_MASK) +#define PUF_STAT_CODEOUTAVAIL_MASK (0x80U) +#define PUF_STAT_CODEOUTAVAIL_SHIFT (7U) +#define PUF_STAT_CODEOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_CODEOUTAVAIL_SHIFT)) & PUF_STAT_CODEOUTAVAIL_MASK) +/*! @} */ + +/*! @name ALLOW - PUF Allow register */ +/*! @{ */ +#define PUF_ALLOW_ALLOWENROLL_MASK (0x1U) +#define PUF_ALLOW_ALLOWENROLL_SHIFT (0U) +#define PUF_ALLOW_ALLOWENROLL(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWENROLL_SHIFT)) & PUF_ALLOW_ALLOWENROLL_MASK) +#define PUF_ALLOW_ALLOWSTART_MASK (0x2U) +#define PUF_ALLOW_ALLOWSTART_SHIFT (1U) +#define PUF_ALLOW_ALLOWSTART(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWSTART_SHIFT)) & PUF_ALLOW_ALLOWSTART_MASK) +#define PUF_ALLOW_ALLOWSETKEY_MASK (0x4U) +#define PUF_ALLOW_ALLOWSETKEY_SHIFT (2U) +#define PUF_ALLOW_ALLOWSETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWSETKEY_SHIFT)) & PUF_ALLOW_ALLOWSETKEY_MASK) +#define PUF_ALLOW_ALLOWGETKEY_MASK (0x8U) +#define PUF_ALLOW_ALLOWGETKEY_SHIFT (3U) +#define PUF_ALLOW_ALLOWGETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWGETKEY_SHIFT)) & PUF_ALLOW_ALLOWGETKEY_MASK) +/*! @} */ + +/*! @name KEYINPUT - PUF Key Input register */ +/*! @{ */ +#define PUF_KEYINPUT_KEYIN_MASK (0xFFFFFFFFU) +#define PUF_KEYINPUT_KEYIN_SHIFT (0U) +#define PUF_KEYINPUT_KEYIN(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYINPUT_KEYIN_SHIFT)) & PUF_KEYINPUT_KEYIN_MASK) +/*! @} */ + +/*! @name CODEINPUT - PUF Code Input register */ +/*! @{ */ +#define PUF_CODEINPUT_CODEIN_MASK (0xFFFFFFFFU) +#define PUF_CODEINPUT_CODEIN_SHIFT (0U) +#define PUF_CODEINPUT_CODEIN(x) (((uint32_t)(((uint32_t)(x)) << PUF_CODEINPUT_CODEIN_SHIFT)) & PUF_CODEINPUT_CODEIN_MASK) +/*! @} */ + +/*! @name CODEOUTPUT - PUF Code Output register */ +/*! @{ */ +#define PUF_CODEOUTPUT_CODEOUT_MASK (0xFFFFFFFFU) +#define PUF_CODEOUTPUT_CODEOUT_SHIFT (0U) +#define PUF_CODEOUTPUT_CODEOUT(x) (((uint32_t)(((uint32_t)(x)) << PUF_CODEOUTPUT_CODEOUT_SHIFT)) & PUF_CODEOUTPUT_CODEOUT_MASK) +/*! @} */ + +/*! @name KEYOUTINDEX - PUF Key Output Index register */ +/*! @{ */ +#define PUF_KEYOUTINDEX_KEYOUTIDX_MASK (0xFU) +#define PUF_KEYOUTINDEX_KEYOUTIDX_SHIFT (0U) +#define PUF_KEYOUTINDEX_KEYOUTIDX(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYOUTINDEX_KEYOUTIDX_SHIFT)) & PUF_KEYOUTINDEX_KEYOUTIDX_MASK) +/*! @} */ + +/*! @name KEYOUTPUT - PUF Key Output register */ +/*! @{ */ +#define PUF_KEYOUTPUT_KEYOUT_MASK (0xFFFFFFFFU) +#define PUF_KEYOUTPUT_KEYOUT_SHIFT (0U) +#define PUF_KEYOUTPUT_KEYOUT(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYOUTPUT_KEYOUT_SHIFT)) & PUF_KEYOUTPUT_KEYOUT_MASK) +/*! @} */ + +/*! @name IFSTAT - PUF Interface Status and clear register */ +/*! @{ */ +#define PUF_IFSTAT_ERROR_MASK (0x1U) +#define PUF_IFSTAT_ERROR_SHIFT (0U) +#define PUF_IFSTAT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_IFSTAT_ERROR_SHIFT)) & PUF_IFSTAT_ERROR_MASK) +/*! @} */ + +/*! @name VERSION - PUF version register. */ +/*! @{ */ +#define PUF_VERSION_KEYOUT_MASK (0xFFFFFFFFU) +#define PUF_VERSION_KEYOUT_SHIFT (0U) +#define PUF_VERSION_KEYOUT(x) (((uint32_t)(((uint32_t)(x)) << PUF_VERSION_KEYOUT_SHIFT)) & PUF_VERSION_KEYOUT_MASK) +/*! @} */ + +/*! @name INTEN - PUF Interrupt Enable */ +/*! @{ */ +#define PUF_INTEN_READYEN_MASK (0x1U) +#define PUF_INTEN_READYEN_SHIFT (0U) +#define PUF_INTEN_READYEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_READYEN_SHIFT)) & PUF_INTEN_READYEN_MASK) +#define PUF_INTEN_SUCCESEN_MASK (0x2U) +#define PUF_INTEN_SUCCESEN_SHIFT (1U) +#define PUF_INTEN_SUCCESEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_SUCCESEN_SHIFT)) & PUF_INTEN_SUCCESEN_MASK) +#define PUF_INTEN_ERROREN_MASK (0x4U) +#define PUF_INTEN_ERROREN_SHIFT (2U) +#define PUF_INTEN_ERROREN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_ERROREN_SHIFT)) & PUF_INTEN_ERROREN_MASK) +#define PUF_INTEN_KEYINREQEN_MASK (0x10U) +#define PUF_INTEN_KEYINREQEN_SHIFT (4U) +#define PUF_INTEN_KEYINREQEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_KEYINREQEN_SHIFT)) & PUF_INTEN_KEYINREQEN_MASK) +#define PUF_INTEN_KEYOUTAVAILEN_MASK (0x20U) +#define PUF_INTEN_KEYOUTAVAILEN_SHIFT (5U) +#define PUF_INTEN_KEYOUTAVAILEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_KEYOUTAVAILEN_SHIFT)) & PUF_INTEN_KEYOUTAVAILEN_MASK) +#define PUF_INTEN_CODEINREQEN_MASK (0x40U) +#define PUF_INTEN_CODEINREQEN_SHIFT (6U) +#define PUF_INTEN_CODEINREQEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_CODEINREQEN_SHIFT)) & PUF_INTEN_CODEINREQEN_MASK) +#define PUF_INTEN_CODEOUTAVAILEN_MASK (0x80U) +#define PUF_INTEN_CODEOUTAVAILEN_SHIFT (7U) +#define PUF_INTEN_CODEOUTAVAILEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_CODEOUTAVAILEN_SHIFT)) & PUF_INTEN_CODEOUTAVAILEN_MASK) +/*! @} */ + +/*! @name INTSTAT - PUF interrupt status */ +/*! @{ */ +#define PUF_INTSTAT_READY_MASK (0x1U) +#define PUF_INTSTAT_READY_SHIFT (0U) +#define PUF_INTSTAT_READY(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_READY_SHIFT)) & PUF_INTSTAT_READY_MASK) +#define PUF_INTSTAT_SUCCESS_MASK (0x2U) +#define PUF_INTSTAT_SUCCESS_SHIFT (1U) +#define PUF_INTSTAT_SUCCESS(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_SUCCESS_SHIFT)) & PUF_INTSTAT_SUCCESS_MASK) +#define PUF_INTSTAT_ERROR_MASK (0x4U) +#define PUF_INTSTAT_ERROR_SHIFT (2U) +#define PUF_INTSTAT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_ERROR_SHIFT)) & PUF_INTSTAT_ERROR_MASK) +#define PUF_INTSTAT_KEYINREQ_MASK (0x10U) +#define PUF_INTSTAT_KEYINREQ_SHIFT (4U) +#define PUF_INTSTAT_KEYINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_KEYINREQ_SHIFT)) & PUF_INTSTAT_KEYINREQ_MASK) +#define PUF_INTSTAT_KEYOUTAVAIL_MASK (0x20U) +#define PUF_INTSTAT_KEYOUTAVAIL_SHIFT (5U) +#define PUF_INTSTAT_KEYOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_KEYOUTAVAIL_SHIFT)) & PUF_INTSTAT_KEYOUTAVAIL_MASK) +#define PUF_INTSTAT_CODEINREQ_MASK (0x40U) +#define PUF_INTSTAT_CODEINREQ_SHIFT (6U) +#define PUF_INTSTAT_CODEINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_CODEINREQ_SHIFT)) & PUF_INTSTAT_CODEINREQ_MASK) +#define PUF_INTSTAT_CODEOUTAVAIL_MASK (0x80U) +#define PUF_INTSTAT_CODEOUTAVAIL_SHIFT (7U) +#define PUF_INTSTAT_CODEOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_CODEOUTAVAIL_SHIFT)) & PUF_INTSTAT_CODEOUTAVAIL_MASK) +/*! @} */ + +/*! @name PWRCTRL - PUF RAM Power Control */ +/*! @{ */ +#define PUF_PWRCTRL_RAMON_MASK (0x1U) +#define PUF_PWRCTRL_RAMON_SHIFT (0U) +#define PUF_PWRCTRL_RAMON(x) (((uint32_t)(((uint32_t)(x)) << PUF_PWRCTRL_RAMON_SHIFT)) & PUF_PWRCTRL_RAMON_MASK) +#define PUF_PWRCTRL_RAMSTAT_MASK (0x2U) +#define PUF_PWRCTRL_RAMSTAT_SHIFT (1U) +#define PUF_PWRCTRL_RAMSTAT(x) (((uint32_t)(((uint32_t)(x)) << PUF_PWRCTRL_RAMSTAT_SHIFT)) & PUF_PWRCTRL_RAMSTAT_MASK) +/*! @} */ + +/*! @name CFG - PUF config register for block bits */ +/*! @{ */ +#define PUF_CFG_BLOCKENROLL_SETKEY_MASK (0x1U) +#define PUF_CFG_BLOCKENROLL_SETKEY_SHIFT (0U) +#define PUF_CFG_BLOCKENROLL_SETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CFG_BLOCKENROLL_SETKEY_SHIFT)) & PUF_CFG_BLOCKENROLL_SETKEY_MASK) +#define PUF_CFG_BLOCKKEYOUTPUT_MASK (0x2U) +#define PUF_CFG_BLOCKKEYOUTPUT_SHIFT (1U) +#define PUF_CFG_BLOCKKEYOUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PUF_CFG_BLOCKKEYOUTPUT_SHIFT)) & PUF_CFG_BLOCKKEYOUTPUT_MASK) +/*! @} */ + +/*! @name KEYLOCK - Only reset in case of full IC reset */ +/*! @{ */ +#define PUF_KEYLOCK_KEY0_MASK (0x3U) +#define PUF_KEYLOCK_KEY0_SHIFT (0U) +#define PUF_KEYLOCK_KEY0(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_KEY0_SHIFT)) & PUF_KEYLOCK_KEY0_MASK) +#define PUF_KEYLOCK_KEY1_MASK (0xCU) +#define PUF_KEYLOCK_KEY1_SHIFT (2U) +#define PUF_KEYLOCK_KEY1(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_KEY1_SHIFT)) & PUF_KEYLOCK_KEY1_MASK) +#define PUF_KEYLOCK_KEY2_MASK (0x30U) +#define PUF_KEYLOCK_KEY2_SHIFT (4U) +#define PUF_KEYLOCK_KEY2(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_KEY2_SHIFT)) & PUF_KEYLOCK_KEY2_MASK) +#define PUF_KEYLOCK_KEY3_MASK (0xC0U) +#define PUF_KEYLOCK_KEY3_SHIFT (6U) +#define PUF_KEYLOCK_KEY3(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_KEY3_SHIFT)) & PUF_KEYLOCK_KEY3_MASK) +/*! @} */ + +/*! @name KEYENABLE - */ +/*! @{ */ +#define PUF_KEYENABLE_KEY0_MASK (0x3U) +#define PUF_KEYENABLE_KEY0_SHIFT (0U) +#define PUF_KEYENABLE_KEY0(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_KEY0_SHIFT)) & PUF_KEYENABLE_KEY0_MASK) +#define PUF_KEYENABLE_KEY1_MASK (0xCU) +#define PUF_KEYENABLE_KEY1_SHIFT (2U) +#define PUF_KEYENABLE_KEY1(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_KEY1_SHIFT)) & PUF_KEYENABLE_KEY1_MASK) +#define PUF_KEYENABLE_KEY2_MASK (0x30U) +#define PUF_KEYENABLE_KEY2_SHIFT (4U) +#define PUF_KEYENABLE_KEY2(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_KEY2_SHIFT)) & PUF_KEYENABLE_KEY2_MASK) +#define PUF_KEYENABLE_KEY3_MASK (0xC0U) +#define PUF_KEYENABLE_KEY3_SHIFT (6U) +#define PUF_KEYENABLE_KEY3(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_KEY3_SHIFT)) & PUF_KEYENABLE_KEY3_MASK) +/*! @} */ + +/*! @name KEYRESET - Reinitialize Keys shift registers counters */ +/*! @{ */ +#define PUF_KEYRESET_KEY0_MASK (0x3U) +#define PUF_KEYRESET_KEY0_SHIFT (0U) +#define PUF_KEYRESET_KEY0(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_KEY0_SHIFT)) & PUF_KEYRESET_KEY0_MASK) +#define PUF_KEYRESET_KEY1_MASK (0xCU) +#define PUF_KEYRESET_KEY1_SHIFT (2U) +#define PUF_KEYRESET_KEY1(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_KEY1_SHIFT)) & PUF_KEYRESET_KEY1_MASK) +#define PUF_KEYRESET_KEY2_MASK (0x30U) +#define PUF_KEYRESET_KEY2_SHIFT (4U) +#define PUF_KEYRESET_KEY2(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_KEY2_SHIFT)) & PUF_KEYRESET_KEY2_MASK) +#define PUF_KEYRESET_KEY3_MASK (0xC0U) +#define PUF_KEYRESET_KEY3_SHIFT (6U) +#define PUF_KEYRESET_KEY3(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_KEY3_SHIFT)) & PUF_KEYRESET_KEY3_MASK) +/*! @} */ + +/*! @name IDXBLK_L - */ +/*! @{ */ +#define PUF_IDXBLK_L_IDX0_MASK (0x3U) +#define PUF_IDXBLK_L_IDX0_SHIFT (0U) +#define PUF_IDXBLK_L_IDX0(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX0_SHIFT)) & PUF_IDXBLK_L_IDX0_MASK) +#define PUF_IDXBLK_L_IDX1_MASK (0xCU) +#define PUF_IDXBLK_L_IDX1_SHIFT (2U) +#define PUF_IDXBLK_L_IDX1(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX1_SHIFT)) & PUF_IDXBLK_L_IDX1_MASK) +#define PUF_IDXBLK_L_IDX2_MASK (0x30U) +#define PUF_IDXBLK_L_IDX2_SHIFT (4U) +#define PUF_IDXBLK_L_IDX2(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX2_SHIFT)) & PUF_IDXBLK_L_IDX2_MASK) +#define PUF_IDXBLK_L_IDX3_MASK (0xC0U) +#define PUF_IDXBLK_L_IDX3_SHIFT (6U) +#define PUF_IDXBLK_L_IDX3(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX3_SHIFT)) & PUF_IDXBLK_L_IDX3_MASK) +#define PUF_IDXBLK_L_IDX4_MASK (0x300U) +#define PUF_IDXBLK_L_IDX4_SHIFT (8U) +#define PUF_IDXBLK_L_IDX4(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX4_SHIFT)) & PUF_IDXBLK_L_IDX4_MASK) +#define PUF_IDXBLK_L_IDX5_MASK (0xC00U) +#define PUF_IDXBLK_L_IDX5_SHIFT (10U) +#define PUF_IDXBLK_L_IDX5(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX5_SHIFT)) & PUF_IDXBLK_L_IDX5_MASK) +#define PUF_IDXBLK_L_IDX6_MASK (0x3000U) +#define PUF_IDXBLK_L_IDX6_SHIFT (12U) +#define PUF_IDXBLK_L_IDX6(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX6_SHIFT)) & PUF_IDXBLK_L_IDX6_MASK) +#define PUF_IDXBLK_L_IDX7_MASK (0xC000U) +#define PUF_IDXBLK_L_IDX7_SHIFT (14U) +#define PUF_IDXBLK_L_IDX7(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX7_SHIFT)) & PUF_IDXBLK_L_IDX7_MASK) +#define PUF_IDXBLK_L_LOCK_IDX_MASK (0xC0000000U) +#define PUF_IDXBLK_L_LOCK_IDX_SHIFT (30U) +#define PUF_IDXBLK_L_LOCK_IDX(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_LOCK_IDX_SHIFT)) & PUF_IDXBLK_L_LOCK_IDX_MASK) +/*! @} */ + +/*! @name IDXBLK_H_DP - */ +/*! @{ */ +#define PUF_IDXBLK_H_DP_IDX8_MASK (0x3U) +#define PUF_IDXBLK_H_DP_IDX8_SHIFT (0U) +#define PUF_IDXBLK_H_DP_IDX8(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX8_SHIFT)) & PUF_IDXBLK_H_DP_IDX8_MASK) +#define PUF_IDXBLK_H_DP_IDX9_MASK (0xCU) +#define PUF_IDXBLK_H_DP_IDX9_SHIFT (2U) +#define PUF_IDXBLK_H_DP_IDX9(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX9_SHIFT)) & PUF_IDXBLK_H_DP_IDX9_MASK) +#define PUF_IDXBLK_H_DP_IDX10_MASK (0x30U) +#define PUF_IDXBLK_H_DP_IDX10_SHIFT (4U) +#define PUF_IDXBLK_H_DP_IDX10(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX10_SHIFT)) & PUF_IDXBLK_H_DP_IDX10_MASK) +#define PUF_IDXBLK_H_DP_IDX11_MASK (0xC0U) +#define PUF_IDXBLK_H_DP_IDX11_SHIFT (6U) +#define PUF_IDXBLK_H_DP_IDX11(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX11_SHIFT)) & PUF_IDXBLK_H_DP_IDX11_MASK) +#define PUF_IDXBLK_H_DP_IDX12_MASK (0x300U) +#define PUF_IDXBLK_H_DP_IDX12_SHIFT (8U) +#define PUF_IDXBLK_H_DP_IDX12(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX12_SHIFT)) & PUF_IDXBLK_H_DP_IDX12_MASK) +#define PUF_IDXBLK_H_DP_IDX13_MASK (0xC00U) +#define PUF_IDXBLK_H_DP_IDX13_SHIFT (10U) +#define PUF_IDXBLK_H_DP_IDX13(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX13_SHIFT)) & PUF_IDXBLK_H_DP_IDX13_MASK) +#define PUF_IDXBLK_H_DP_IDX14_MASK (0x3000U) +#define PUF_IDXBLK_H_DP_IDX14_SHIFT (12U) +#define PUF_IDXBLK_H_DP_IDX14(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX14_SHIFT)) & PUF_IDXBLK_H_DP_IDX14_MASK) +#define PUF_IDXBLK_H_DP_IDX15_MASK (0xC000U) +#define PUF_IDXBLK_H_DP_IDX15_SHIFT (14U) +#define PUF_IDXBLK_H_DP_IDX15(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX15_SHIFT)) & PUF_IDXBLK_H_DP_IDX15_MASK) +/*! @} */ + +/*! @name KEYMASK - Only reset in case of full IC reset */ +/*! @{ */ +#define PUF_KEYMASK_KEYMASK_MASK (0xFFFFFFFFU) +#define PUF_KEYMASK_KEYMASK_SHIFT (0U) +#define PUF_KEYMASK_KEYMASK(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYMASK_KEYMASK_SHIFT)) & PUF_KEYMASK_KEYMASK_MASK) +/*! @} */ + +/* The count of PUF_KEYMASK */ +#define PUF_KEYMASK_COUNT (4U) + +/*! @name IDXBLK_H - */ +/*! @{ */ +#define PUF_IDXBLK_H_IDX8_MASK (0x3U) +#define PUF_IDXBLK_H_IDX8_SHIFT (0U) +#define PUF_IDXBLK_H_IDX8(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX8_SHIFT)) & PUF_IDXBLK_H_IDX8_MASK) +#define PUF_IDXBLK_H_IDX9_MASK (0xCU) +#define PUF_IDXBLK_H_IDX9_SHIFT (2U) +#define PUF_IDXBLK_H_IDX9(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX9_SHIFT)) & PUF_IDXBLK_H_IDX9_MASK) +#define PUF_IDXBLK_H_IDX10_MASK (0x30U) +#define PUF_IDXBLK_H_IDX10_SHIFT (4U) +#define PUF_IDXBLK_H_IDX10(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX10_SHIFT)) & PUF_IDXBLK_H_IDX10_MASK) +#define PUF_IDXBLK_H_IDX11_MASK (0xC0U) +#define PUF_IDXBLK_H_IDX11_SHIFT (6U) +#define PUF_IDXBLK_H_IDX11(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX11_SHIFT)) & PUF_IDXBLK_H_IDX11_MASK) +#define PUF_IDXBLK_H_IDX12_MASK (0x300U) +#define PUF_IDXBLK_H_IDX12_SHIFT (8U) +#define PUF_IDXBLK_H_IDX12(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX12_SHIFT)) & PUF_IDXBLK_H_IDX12_MASK) +#define PUF_IDXBLK_H_IDX13_MASK (0xC00U) +#define PUF_IDXBLK_H_IDX13_SHIFT (10U) +#define PUF_IDXBLK_H_IDX13(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX13_SHIFT)) & PUF_IDXBLK_H_IDX13_MASK) +#define PUF_IDXBLK_H_IDX14_MASK (0x3000U) +#define PUF_IDXBLK_H_IDX14_SHIFT (12U) +#define PUF_IDXBLK_H_IDX14(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX14_SHIFT)) & PUF_IDXBLK_H_IDX14_MASK) +#define PUF_IDXBLK_H_IDX15_MASK (0xC000U) +#define PUF_IDXBLK_H_IDX15_SHIFT (14U) +#define PUF_IDXBLK_H_IDX15(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX15_SHIFT)) & PUF_IDXBLK_H_IDX15_MASK) +#define PUF_IDXBLK_H_LOCK_IDX_MASK (0xC0000000U) +#define PUF_IDXBLK_H_LOCK_IDX_SHIFT (30U) +#define PUF_IDXBLK_H_LOCK_IDX(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_LOCK_IDX_SHIFT)) & PUF_IDXBLK_H_LOCK_IDX_MASK) +/*! @} */ + +/*! @name IDXBLK_L_DP - */ +/*! @{ */ +#define PUF_IDXBLK_L_DP_IDX0_MASK (0x3U) +#define PUF_IDXBLK_L_DP_IDX0_SHIFT (0U) +#define PUF_IDXBLK_L_DP_IDX0(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX0_SHIFT)) & PUF_IDXBLK_L_DP_IDX0_MASK) +#define PUF_IDXBLK_L_DP_IDX1_MASK (0xCU) +#define PUF_IDXBLK_L_DP_IDX1_SHIFT (2U) +#define PUF_IDXBLK_L_DP_IDX1(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX1_SHIFT)) & PUF_IDXBLK_L_DP_IDX1_MASK) +#define PUF_IDXBLK_L_DP_IDX2_MASK (0x30U) +#define PUF_IDXBLK_L_DP_IDX2_SHIFT (4U) +#define PUF_IDXBLK_L_DP_IDX2(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX2_SHIFT)) & PUF_IDXBLK_L_DP_IDX2_MASK) +#define PUF_IDXBLK_L_DP_IDX3_MASK (0xC0U) +#define PUF_IDXBLK_L_DP_IDX3_SHIFT (6U) +#define PUF_IDXBLK_L_DP_IDX3(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX3_SHIFT)) & PUF_IDXBLK_L_DP_IDX3_MASK) +#define PUF_IDXBLK_L_DP_IDX4_MASK (0x300U) +#define PUF_IDXBLK_L_DP_IDX4_SHIFT (8U) +#define PUF_IDXBLK_L_DP_IDX4(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX4_SHIFT)) & PUF_IDXBLK_L_DP_IDX4_MASK) +#define PUF_IDXBLK_L_DP_IDX5_MASK (0xC00U) +#define PUF_IDXBLK_L_DP_IDX5_SHIFT (10U) +#define PUF_IDXBLK_L_DP_IDX5(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX5_SHIFT)) & PUF_IDXBLK_L_DP_IDX5_MASK) +#define PUF_IDXBLK_L_DP_IDX6_MASK (0x3000U) +#define PUF_IDXBLK_L_DP_IDX6_SHIFT (12U) +#define PUF_IDXBLK_L_DP_IDX6(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX6_SHIFT)) & PUF_IDXBLK_L_DP_IDX6_MASK) +#define PUF_IDXBLK_L_DP_IDX7_MASK (0xC000U) +#define PUF_IDXBLK_L_DP_IDX7_SHIFT (14U) +#define PUF_IDXBLK_L_DP_IDX7(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX7_SHIFT)) & PUF_IDXBLK_L_DP_IDX7_MASK) +/*! @} */ + +/*! @name SHIFT_STATUS - */ +/*! @{ */ +#define PUF_SHIFT_STATUS_KEY0_MASK (0xFU) +#define PUF_SHIFT_STATUS_KEY0_SHIFT (0U) +#define PUF_SHIFT_STATUS_KEY0(x) (((uint32_t)(((uint32_t)(x)) << PUF_SHIFT_STATUS_KEY0_SHIFT)) & PUF_SHIFT_STATUS_KEY0_MASK) +#define PUF_SHIFT_STATUS_KEY1_MASK (0xF0U) +#define PUF_SHIFT_STATUS_KEY1_SHIFT (4U) +#define PUF_SHIFT_STATUS_KEY1(x) (((uint32_t)(((uint32_t)(x)) << PUF_SHIFT_STATUS_KEY1_SHIFT)) & PUF_SHIFT_STATUS_KEY1_MASK) +#define PUF_SHIFT_STATUS_KEY2_MASK (0xF00U) +#define PUF_SHIFT_STATUS_KEY2_SHIFT (8U) +#define PUF_SHIFT_STATUS_KEY2(x) (((uint32_t)(((uint32_t)(x)) << PUF_SHIFT_STATUS_KEY2_SHIFT)) & PUF_SHIFT_STATUS_KEY2_MASK) +#define PUF_SHIFT_STATUS_KEY3_MASK (0xF000U) +#define PUF_SHIFT_STATUS_KEY3_SHIFT (12U) +#define PUF_SHIFT_STATUS_KEY3(x) (((uint32_t)(((uint32_t)(x)) << PUF_SHIFT_STATUS_KEY3_SHIFT)) & PUF_SHIFT_STATUS_KEY3_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group PUF_Register_Masks */ + + +/* PUF - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral PUF base address */ + #define PUF_BASE (0x5003B000u) + /** Peripheral PUF base address */ + #define PUF_BASE_NS (0x4003B000u) + /** Peripheral PUF base pointer */ + #define PUF ((PUF_Type *)PUF_BASE) + /** Peripheral PUF base pointer */ + #define PUF_NS ((PUF_Type *)PUF_BASE_NS) + /** Array initializer of PUF peripheral base addresses */ + #define PUF_BASE_ADDRS { PUF_BASE } + /** Array initializer of PUF peripheral base pointers */ + #define PUF_BASE_PTRS { PUF } + /** Array initializer of PUF peripheral base addresses */ + #define PUF_BASE_ADDRS_NS { PUF_BASE_NS } + /** Array initializer of PUF peripheral base pointers */ + #define PUF_BASE_PTRS_NS { PUF_NS } +#else + /** Peripheral PUF base address */ + #define PUF_BASE (0x4003B000u) + /** Peripheral PUF base pointer */ + #define PUF ((PUF_Type *)PUF_BASE) + /** Array initializer of PUF peripheral base addresses */ + #define PUF_BASE_ADDRS { PUF_BASE } + /** Array initializer of PUF peripheral base pointers */ + #define PUF_BASE_PTRS { PUF } +#endif +/** Interrupt vectors for the PUF peripheral type */ +#define PUF_IRQS { PUF_IRQn } + +/*! + * @} + */ /* end of group PUF_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- RNG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RNG_Peripheral_Access_Layer RNG Peripheral Access Layer + * @{ + */ + +/** RNG - Register Layout Typedef */ +typedef struct { + __I uint32_t RANDOM_NUMBER; /**< This register contains a random 32 bit number which is computed on demand, at each time it is read, offset: 0x0 */ + __I uint32_t ENCRYPTED_NUMBER; /**< This register contains a random 32 bit number which is pre-computed, offset: 0x4 */ + __I uint32_t COUNTER_VAL; /**< , offset: 0x8 */ + __IO uint32_t COUNTER_CFG; /**< , offset: 0xC */ + __IO uint32_t ONLINE_TEST_CFG; /**< , offset: 0x10 */ + __I uint32_t ONLINE_TEST_VAL; /**< , offset: 0x14 */ + __IO uint32_t MISC_CFG; /**< , offset: 0x18 */ + uint8_t RESERVED_0[4056]; + __IO uint32_t POWERDOWN; /**< Powerdown mode (standard but certainly useless here), offset: 0xFF4 */ + uint8_t RESERVED_1[4]; + __I uint32_t MODULEID; /**< IP identifier, offset: 0xFFC */ +} RNG_Type; + +/* ---------------------------------------------------------------------------- + -- RNG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RNG_Register_Masks RNG Register Masks + * @{ + */ + +/*! @name RANDOM_NUMBER - This register contains a random 32 bit number which is computed on demand, at each time it is read */ +/*! @{ */ +#define RNG_RANDOM_NUMBER_RANDOM_NUMBER_MASK (0xFFFFFFFFU) +#define RNG_RANDOM_NUMBER_RANDOM_NUMBER_SHIFT (0U) +#define RNG_RANDOM_NUMBER_RANDOM_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << RNG_RANDOM_NUMBER_RANDOM_NUMBER_SHIFT)) & RNG_RANDOM_NUMBER_RANDOM_NUMBER_MASK) +/*! @} */ + +/*! @name ENCRYPTED_NUMBER - This register contains a random 32 bit number which is pre-computed */ +/*! @{ */ +#define RNG_ENCRYPTED_NUMBER_ENCRYPTED_NUMBER_MASK (0xFFFFFFFFU) +#define RNG_ENCRYPTED_NUMBER_ENCRYPTED_NUMBER_SHIFT (0U) +#define RNG_ENCRYPTED_NUMBER_ENCRYPTED_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << RNG_ENCRYPTED_NUMBER_ENCRYPTED_NUMBER_SHIFT)) & RNG_ENCRYPTED_NUMBER_ENCRYPTED_NUMBER_MASK) +/*! @} */ + +/*! @name COUNTER_VAL - */ +/*! @{ */ +#define RNG_COUNTER_VAL_CLK_RATIO_MASK (0xFFU) +#define RNG_COUNTER_VAL_CLK_RATIO_SHIFT (0U) +#define RNG_COUNTER_VAL_CLK_RATIO(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_VAL_CLK_RATIO_SHIFT)) & RNG_COUNTER_VAL_CLK_RATIO_MASK) +#define RNG_COUNTER_VAL_REFRESH_CNT_MASK (0x1F00U) +#define RNG_COUNTER_VAL_REFRESH_CNT_SHIFT (8U) +#define RNG_COUNTER_VAL_REFRESH_CNT(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_VAL_REFRESH_CNT_SHIFT)) & RNG_COUNTER_VAL_REFRESH_CNT_MASK) +/*! @} */ + +/*! @name COUNTER_CFG - */ +/*! @{ */ +#define RNG_COUNTER_CFG_MODE_MASK (0x3U) +#define RNG_COUNTER_CFG_MODE_SHIFT (0U) +#define RNG_COUNTER_CFG_MODE(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_CFG_MODE_SHIFT)) & RNG_COUNTER_CFG_MODE_MASK) +#define RNG_COUNTER_CFG_CLOCK_SEL_MASK (0x1CU) +#define RNG_COUNTER_CFG_CLOCK_SEL_SHIFT (2U) +#define RNG_COUNTER_CFG_CLOCK_SEL(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_CFG_CLOCK_SEL_SHIFT)) & RNG_COUNTER_CFG_CLOCK_SEL_MASK) +#define RNG_COUNTER_CFG_SHIFT4X_MASK (0xE0U) +#define RNG_COUNTER_CFG_SHIFT4X_SHIFT (5U) +#define RNG_COUNTER_CFG_SHIFT4X(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_CFG_SHIFT4X_SHIFT)) & RNG_COUNTER_CFG_SHIFT4X_MASK) +#define RNG_COUNTER_CFG_DIS_ENH_ENTR_REFILL_MASK (0x100U) +#define RNG_COUNTER_CFG_DIS_ENH_ENTR_REFILL_SHIFT (8U) +#define RNG_COUNTER_CFG_DIS_ENH_ENTR_REFILL(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_CFG_DIS_ENH_ENTR_REFILL_SHIFT)) & RNG_COUNTER_CFG_DIS_ENH_ENTR_REFILL_MASK) +#define RNG_COUNTER_CFG_FORCE_ENTR_SPREADING_MASK (0x200U) +#define RNG_COUNTER_CFG_FORCE_ENTR_SPREADING_SHIFT (9U) +#define RNG_COUNTER_CFG_FORCE_ENTR_SPREADING(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_CFG_FORCE_ENTR_SPREADING_SHIFT)) & RNG_COUNTER_CFG_FORCE_ENTR_SPREADING_MASK) +/*! @} */ + +/*! @name ONLINE_TEST_CFG - */ +/*! @{ */ +#define RNG_ONLINE_TEST_CFG_ACTIVATE_MASK (0x1U) +#define RNG_ONLINE_TEST_CFG_ACTIVATE_SHIFT (0U) +#define RNG_ONLINE_TEST_CFG_ACTIVATE(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_CFG_ACTIVATE_SHIFT)) & RNG_ONLINE_TEST_CFG_ACTIVATE_MASK) +#define RNG_ONLINE_TEST_CFG_DATA_SEL_MASK (0x6U) +#define RNG_ONLINE_TEST_CFG_DATA_SEL_SHIFT (1U) +#define RNG_ONLINE_TEST_CFG_DATA_SEL(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_CFG_DATA_SEL_SHIFT)) & RNG_ONLINE_TEST_CFG_DATA_SEL_MASK) +/*! @} */ + +/*! @name ONLINE_TEST_VAL - */ +/*! @{ */ +#define RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED_MASK (0xFU) +#define RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED_SHIFT (0U) +#define RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED_SHIFT)) & RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED_MASK) +#define RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_MASK (0xF0U) +#define RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_SHIFT (4U) +#define RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_SHIFT)) & RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_MASK) +#define RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_MASK (0xF00U) +#define RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_SHIFT (8U) +#define RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_SHIFT)) & RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_MASK) +/*! @} */ + +/*! @name MISC_CFG - */ +/*! @{ */ +#define RNG_MISC_CFG_AES_RESEED_MASK (0x1U) +#define RNG_MISC_CFG_AES_RESEED_SHIFT (0U) +#define RNG_MISC_CFG_AES_RESEED(x) (((uint32_t)(((uint32_t)(x)) << RNG_MISC_CFG_AES_RESEED_SHIFT)) & RNG_MISC_CFG_AES_RESEED_MASK) +#define RNG_MISC_CFG_AES_DT_CFG_MASK (0x2U) +#define RNG_MISC_CFG_AES_DT_CFG_SHIFT (1U) +#define RNG_MISC_CFG_AES_DT_CFG(x) (((uint32_t)(((uint32_t)(x)) << RNG_MISC_CFG_AES_DT_CFG_SHIFT)) & RNG_MISC_CFG_AES_DT_CFG_MASK) +/*! @} */ + +/*! @name POWERDOWN - Powerdown mode (standard but certainly useless here) */ +/*! @{ */ +#define RNG_POWERDOWN_SOFT_RESET_MASK (0x1U) +#define RNG_POWERDOWN_SOFT_RESET_SHIFT (0U) +#define RNG_POWERDOWN_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << RNG_POWERDOWN_SOFT_RESET_SHIFT)) & RNG_POWERDOWN_SOFT_RESET_MASK) +#define RNG_POWERDOWN_FORCE_SOFT_RESET_MASK (0x2U) +#define RNG_POWERDOWN_FORCE_SOFT_RESET_SHIFT (1U) +#define RNG_POWERDOWN_FORCE_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << RNG_POWERDOWN_FORCE_SOFT_RESET_SHIFT)) & RNG_POWERDOWN_FORCE_SOFT_RESET_MASK) +#define RNG_POWERDOWN_POWERDOWN_MASK (0x80000000U) +#define RNG_POWERDOWN_POWERDOWN_SHIFT (31U) +#define RNG_POWERDOWN_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << RNG_POWERDOWN_POWERDOWN_SHIFT)) & RNG_POWERDOWN_POWERDOWN_MASK) +/*! @} */ + +/*! @name MODULEID - IP identifier */ +/*! @{ */ +#define RNG_MODULEID_APERTURE_MASK (0xFFU) +#define RNG_MODULEID_APERTURE_SHIFT (0U) +#define RNG_MODULEID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << RNG_MODULEID_APERTURE_SHIFT)) & RNG_MODULEID_APERTURE_MASK) +#define RNG_MODULEID_MIN_REV_MASK (0xF00U) +#define RNG_MODULEID_MIN_REV_SHIFT (8U) +#define RNG_MODULEID_MIN_REV(x) (((uint32_t)(((uint32_t)(x)) << RNG_MODULEID_MIN_REV_SHIFT)) & RNG_MODULEID_MIN_REV_MASK) +#define RNG_MODULEID_MAJ_REV_MASK (0xF000U) +#define RNG_MODULEID_MAJ_REV_SHIFT (12U) +#define RNG_MODULEID_MAJ_REV(x) (((uint32_t)(((uint32_t)(x)) << RNG_MODULEID_MAJ_REV_SHIFT)) & RNG_MODULEID_MAJ_REV_MASK) +#define RNG_MODULEID_ID_MASK (0xFFFF0000U) +#define RNG_MODULEID_ID_SHIFT (16U) +#define RNG_MODULEID_ID(x) (((uint32_t)(((uint32_t)(x)) << RNG_MODULEID_ID_SHIFT)) & RNG_MODULEID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group RNG_Register_Masks */ + + +/* RNG - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral RNG base address */ + #define RNG_BASE (0x5003A000u) + /** Peripheral RNG base address */ + #define RNG_BASE_NS (0x4003A000u) + /** Peripheral RNG base pointer */ + #define RNG ((RNG_Type *)RNG_BASE) + /** Peripheral RNG base pointer */ + #define RNG_NS ((RNG_Type *)RNG_BASE_NS) + /** Array initializer of RNG peripheral base addresses */ + #define RNG_BASE_ADDRS { RNG_BASE } + /** Array initializer of RNG peripheral base pointers */ + #define RNG_BASE_PTRS { RNG } + /** Array initializer of RNG peripheral base addresses */ + #define RNG_BASE_ADDRS_NS { RNG_BASE_NS } + /** Array initializer of RNG peripheral base pointers */ + #define RNG_BASE_PTRS_NS { RNG_NS } +#else + /** Peripheral RNG base address */ + #define RNG_BASE (0x4003A000u) + /** Peripheral RNG base pointer */ + #define RNG ((RNG_Type *)RNG_BASE) + /** Array initializer of RNG peripheral base addresses */ + #define RNG_BASE_ADDRS { RNG_BASE } + /** Array initializer of RNG peripheral base pointers */ + #define RNG_BASE_PTRS { RNG } +#endif + +/*! + * @} + */ /* end of group RNG_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- RTC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer + * @{ + */ + +/** RTC - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< RTC control register, offset: 0x0 */ + __IO uint32_t MATCH; /**< RTC match register, offset: 0x4 */ + __IO uint32_t COUNT; /**< RTC counter register, offset: 0x8 */ + __IO uint32_t WAKE; /**< High-resolution/wake-up timer control register, offset: 0xC */ + __I uint32_t SUBSEC; /**< RTC Sub-second Counter register, offset: 0x10 */ + uint8_t RESERVED_0[44]; + __IO uint32_t GPREG[8]; /**< General Purpose register, array offset: 0x40, array step: 0x4 */ +} RTC_Type; + +/* ---------------------------------------------------------------------------- + -- RTC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RTC_Register_Masks RTC Register Masks + * @{ + */ + +/*! @name CTRL - RTC control register */ +/*! @{ */ +#define RTC_CTRL_SWRESET_MASK (0x1U) +#define RTC_CTRL_SWRESET_SHIFT (0U) +/*! SWRESET - Software reset control + * 0b0..Not in reset. The RTC is not held in reset. This bit must be cleared prior to configuring or initiating any operation of the RTC. + * 0b1..In reset. The RTC is held in reset. All register bits within the RTC will be forced to their reset value + * except the OFD bit. This bit must be cleared before writing to any register in the RTC - including writes + * to set any of the other bits within this register. Do not attempt to write to any bits of this register at + * the same time that the reset bit is being cleared. + */ +#define RTC_CTRL_SWRESET(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_SWRESET_SHIFT)) & RTC_CTRL_SWRESET_MASK) +#define RTC_CTRL_ALARM1HZ_MASK (0x4U) +#define RTC_CTRL_ALARM1HZ_SHIFT (2U) +/*! ALARM1HZ - RTC 1 Hz timer alarm flag status. + * 0b0..No match. No match has occurred on the 1 Hz RTC timer. Writing a 0 has no effect. + * 0b1..Match. A match condition has occurred on the 1 Hz RTC timer. This flag generates an RTC alarm interrupt + * request RTC_ALARM which can also wake up the part from any low power mode. Writing a 1 clears this bit. + */ +#define RTC_CTRL_ALARM1HZ(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARM1HZ_SHIFT)) & RTC_CTRL_ALARM1HZ_MASK) +#define RTC_CTRL_WAKE1KHZ_MASK (0x8U) +#define RTC_CTRL_WAKE1KHZ_SHIFT (3U) +/*! WAKE1KHZ - RTC 1 kHz timer wake-up flag status. + * 0b0..Run. The RTC 1 kHz timer is running. Writing a 0 has no effect. + * 0b1..Time-out. The 1 kHz high-resolution/wake-up timer has timed out. This flag generates an RTC wake-up + * interrupt request RTC-WAKE which can also wake up the part from any low power mode. Writing a 1 clears this bit. + */ +#define RTC_CTRL_WAKE1KHZ(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKE1KHZ_SHIFT)) & RTC_CTRL_WAKE1KHZ_MASK) +#define RTC_CTRL_ALARMDPD_EN_MASK (0x10U) +#define RTC_CTRL_ALARMDPD_EN_SHIFT (4U) +/*! ALARMDPD_EN - RTC 1 Hz timer alarm enable for Deep power-down. + * 0b0..Disable. A match on the 1 Hz RTC timer will not bring the part out of Deep power-down mode. + * 0b1..Enable. A match on the 1 Hz RTC timer bring the part out of Deep power-down mode. + */ +#define RTC_CTRL_ALARMDPD_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARMDPD_EN_SHIFT)) & RTC_CTRL_ALARMDPD_EN_MASK) +#define RTC_CTRL_WAKEDPD_EN_MASK (0x20U) +#define RTC_CTRL_WAKEDPD_EN_SHIFT (5U) +/*! WAKEDPD_EN - RTC 1 kHz timer wake-up enable for Deep power-down. + * 0b0..Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode. + * 0b1..Enable. A match on the 1 kHz RTC timer bring the part out of Deep power-down mode. + */ +#define RTC_CTRL_WAKEDPD_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKEDPD_EN_SHIFT)) & RTC_CTRL_WAKEDPD_EN_MASK) +#define RTC_CTRL_RTC1KHZ_EN_MASK (0x40U) +#define RTC_CTRL_RTC1KHZ_EN_SHIFT (6U) +/*! RTC1KHZ_EN - RTC 1 kHz clock enable. This bit can be set to 0 to conserve power if the 1 kHz + * timer is not used. This bit has no effect when the RTC is disabled (bit 7 of this register is 0). + * 0b0..Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode. + * 0b1..Enable. The 1 kHz RTC timer is enabled. + */ +#define RTC_CTRL_RTC1KHZ_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC1KHZ_EN_SHIFT)) & RTC_CTRL_RTC1KHZ_EN_MASK) +#define RTC_CTRL_RTC_EN_MASK (0x80U) +#define RTC_CTRL_RTC_EN_SHIFT (7U) +/*! RTC_EN - RTC enable. + * 0b0..Disable. The RTC 1 Hz and 1 kHz clocks are shut down and the RTC operation is disabled. This bit should + * be 0 when writing to load a value in the RTC counter register. + * 0b1..Enable. The 1 Hz RTC clock is running and RTC operation is enabled. This bit must be set to initiate + * operation of the RTC. The first clock to the RTC counter occurs 1 s after this bit is set. To also enable the + * high-resolution, 1 kHz clock, set bit 6 in this register. + */ +#define RTC_CTRL_RTC_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_EN_SHIFT)) & RTC_CTRL_RTC_EN_MASK) +#define RTC_CTRL_RTC_OSC_PD_MASK (0x100U) +#define RTC_CTRL_RTC_OSC_PD_SHIFT (8U) +/*! RTC_OSC_PD - RTC oscillator power-down control. + * 0b0..See RTC_OSC_BYPASS + * 0b1..RTC oscillator is powered-down. + */ +#define RTC_CTRL_RTC_OSC_PD(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_OSC_PD_SHIFT)) & RTC_CTRL_RTC_OSC_PD_MASK) +#define RTC_CTRL_RTC_OSC_BYPASS_MASK (0x200U) +#define RTC_CTRL_RTC_OSC_BYPASS_SHIFT (9U) +/*! RTC_OSC_BYPASS - RTC oscillator bypass control. + * 0b0..The RTC Oscillator operates normally as a crystal oscillator with the crystal connected between the RTC_XTALIN and RTC_XTALOUT pins. + * 0b1..The RTC Oscillator is in bypass mode. In this mode a clock can be directly input into the RTC_XTALIN pin. + */ +#define RTC_CTRL_RTC_OSC_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_OSC_BYPASS_SHIFT)) & RTC_CTRL_RTC_OSC_BYPASS_MASK) +#define RTC_CTRL_RTC_SUBSEC_ENA_MASK (0x400U) +#define RTC_CTRL_RTC_SUBSEC_ENA_SHIFT (10U) +/*! RTC_SUBSEC_ENA - RTC Sub-second counter control. + * 0b0..The sub-second counter (if implemented) is disabled. This bit is cleared by a system-level POR or BOD + * reset as well as a by the RTC_ENA bit (bit 7 in this register). On modules not equipped with a sub-second + * counter, this bit will always read-back as a '0'. + * 0b1..The 32 KHz sub-second counter is enabled (if implemented). Counting commences on the start of the first + * one-second interval after this bit is set. Note: This bit can only be set after the RTC_ENA bit (bit 7) is + * set by a previous write operation. Note: The RTC sub-second counter must be re-enabled whenever the chip + * exits deep power-down mode. + */ +#define RTC_CTRL_RTC_SUBSEC_ENA(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_SUBSEC_ENA_SHIFT)) & RTC_CTRL_RTC_SUBSEC_ENA_MASK) +/*! @} */ + +/*! @name MATCH - RTC match register */ +/*! @{ */ +#define RTC_MATCH_MATVAL_MASK (0xFFFFFFFFU) +#define RTC_MATCH_MATVAL_SHIFT (0U) +#define RTC_MATCH_MATVAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_MATCH_MATVAL_SHIFT)) & RTC_MATCH_MATVAL_MASK) +/*! @} */ + +/*! @name COUNT - RTC counter register */ +/*! @{ */ +#define RTC_COUNT_VAL_MASK (0xFFFFFFFFU) +#define RTC_COUNT_VAL_SHIFT (0U) +#define RTC_COUNT_VAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_COUNT_VAL_SHIFT)) & RTC_COUNT_VAL_MASK) +/*! @} */ + +/*! @name WAKE - High-resolution/wake-up timer control register */ +/*! @{ */ +#define RTC_WAKE_VAL_MASK (0xFFFFU) +#define RTC_WAKE_VAL_SHIFT (0U) +#define RTC_WAKE_VAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_VAL_SHIFT)) & RTC_WAKE_VAL_MASK) +/*! @} */ + +/*! @name SUBSEC - RTC Sub-second Counter register */ +/*! @{ */ +#define RTC_SUBSEC_SUBSEC_MASK (0x7FFFU) +#define RTC_SUBSEC_SUBSEC_SHIFT (0U) +#define RTC_SUBSEC_SUBSEC(x) (((uint32_t)(((uint32_t)(x)) << RTC_SUBSEC_SUBSEC_SHIFT)) & RTC_SUBSEC_SUBSEC_MASK) +/*! @} */ + +/*! @name GPREG - General Purpose register */ +/*! @{ */ +#define RTC_GPREG_GPDATA_MASK (0xFFFFFFFFU) +#define RTC_GPREG_GPDATA_SHIFT (0U) +#define RTC_GPREG_GPDATA(x) (((uint32_t)(((uint32_t)(x)) << RTC_GPREG_GPDATA_SHIFT)) & RTC_GPREG_GPDATA_MASK) +/*! @} */ + +/* The count of RTC_GPREG */ +#define RTC_GPREG_COUNT (8U) + + +/*! + * @} + */ /* end of group RTC_Register_Masks */ + + +/* RTC - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral RTC base address */ + #define RTC_BASE (0x5002C000u) + /** Peripheral RTC base address */ + #define RTC_BASE_NS (0x4002C000u) + /** Peripheral RTC base pointer */ + #define RTC ((RTC_Type *)RTC_BASE) + /** Peripheral RTC base pointer */ + #define RTC_NS ((RTC_Type *)RTC_BASE_NS) + /** Array initializer of RTC peripheral base addresses */ + #define RTC_BASE_ADDRS { RTC_BASE } + /** Array initializer of RTC peripheral base pointers */ + #define RTC_BASE_PTRS { RTC } + /** Array initializer of RTC peripheral base addresses */ + #define RTC_BASE_ADDRS_NS { RTC_BASE_NS } + /** Array initializer of RTC peripheral base pointers */ + #define RTC_BASE_PTRS_NS { RTC_NS } +#else + /** Peripheral RTC base address */ + #define RTC_BASE (0x4002C000u) + /** Peripheral RTC base pointer */ + #define RTC ((RTC_Type *)RTC_BASE) + /** Array initializer of RTC peripheral base addresses */ + #define RTC_BASE_ADDRS { RTC_BASE } + /** Array initializer of RTC peripheral base pointers */ + #define RTC_BASE_PTRS { RTC } +#endif +/** Interrupt vectors for the RTC peripheral type */ +#define RTC_IRQS { RTC_IRQn } + +/*! + * @} + */ /* end of group RTC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SCT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SCT_Peripheral_Access_Layer SCT Peripheral Access Layer + * @{ + */ + +/** SCT - Register Layout Typedef */ +typedef struct { + __IO uint32_t CONFIG; /**< SCT configuration register, offset: 0x0 */ + __IO uint32_t CTRL; /**< SCT control register, offset: 0x4 */ + __IO uint32_t LIMIT; /**< SCT limit event select register, offset: 0x8 */ + __IO uint32_t HALT; /**< SCT halt event select register, offset: 0xC */ + __IO uint32_t STOP; /**< SCT stop event select register, offset: 0x10 */ + __IO uint32_t START; /**< SCT start event select register, offset: 0x14 */ + uint8_t RESERVED_0[40]; + __IO uint32_t COUNT; /**< SCT counter register, offset: 0x40 */ + __IO uint32_t STATE; /**< SCT state register, offset: 0x44 */ + __I uint32_t INPUT; /**< SCT input register, offset: 0x48 */ + __IO uint32_t REGMODE; /**< SCT match/capture mode register, offset: 0x4C */ + __IO uint32_t OUTPUT; /**< SCT output register, offset: 0x50 */ + __IO uint32_t OUTPUTDIRCTRL; /**< SCT output counter direction control register, offset: 0x54 */ + __IO uint32_t RES; /**< SCT conflict resolution register, offset: 0x58 */ + __IO uint32_t DMA0REQUEST; /**< SCT DMA request 0 register, offset: 0x5C */ + __IO uint32_t DMA1REQUEST; /**< SCT DMA request 1 register, offset: 0x60 */ + uint8_t RESERVED_1[140]; + __IO uint32_t EVEN; /**< SCT event interrupt enable register, offset: 0xF0 */ + __IO uint32_t EVFLAG; /**< SCT event flag register, offset: 0xF4 */ + __IO uint32_t CONEN; /**< SCT conflict interrupt enable register, offset: 0xF8 */ + __IO uint32_t CONFLAG; /**< SCT conflict flag register, offset: 0xFC */ + union { /* offset: 0x100 */ + __IO uint32_t SCTCAP[16]; /**< SCT capture register of capture channel, array offset: 0x100, array step: 0x4 */ + __IO uint32_t SCTMATCH[16]; /**< SCT match value register of match channels, array offset: 0x100, array step: 0x4 */ + }; + uint8_t RESERVED_2[192]; + union { /* offset: 0x200 */ + __IO uint32_t SCTCAPCTRL[16]; /**< SCT capture control register, array offset: 0x200, array step: 0x4 */ + __IO uint32_t SCTMATCHREL[16]; /**< SCT match reload value register, array offset: 0x200, array step: 0x4 */ + }; + uint8_t RESERVED_3[192]; + struct { /* offset: 0x300, array step: 0x8 */ + __IO uint32_t STATE; /**< SCT event state register 0, array offset: 0x300, array step: 0x8 */ + __IO uint32_t CTRL; /**< SCT event control register 0, array offset: 0x304, array step: 0x8 */ + } EVENT[16]; + uint8_t RESERVED_4[384]; + struct { /* offset: 0x500, array step: 0x8 */ + __IO uint32_t SET; /**< SCT output 0 set register, array offset: 0x500, array step: 0x8 */ + __IO uint32_t CLR; /**< SCT output 0 clear register, array offset: 0x504, array step: 0x8 */ + } OUT[10]; +} SCT_Type; + +/* ---------------------------------------------------------------------------- + -- SCT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SCT_Register_Masks SCT Register Masks + * @{ + */ + +/*! @name CONFIG - SCT configuration register */ +/*! @{ */ +#define SCT_CONFIG_UNIFY_MASK (0x1U) +#define SCT_CONFIG_UNIFY_SHIFT (0U) +/*! UNIFY - SCT operation + * 0b0..The SCT operates as two 16-bit counters named COUNTER_L and COUNTER_H. + * 0b1..The SCT operates as a unified 32-bit counter. + */ +#define SCT_CONFIG_UNIFY(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_UNIFY_SHIFT)) & SCT_CONFIG_UNIFY_MASK) +#define SCT_CONFIG_CLKMODE_MASK (0x6U) +#define SCT_CONFIG_CLKMODE_SHIFT (1U) +/*! CLKMODE - SCT clock mode + * 0b00..System Clock Mode. The system clock clocks the entire SCT module including the counter(s) and counter prescalers. + * 0b01..Sampled System Clock Mode. The system clock clocks the SCT module, but the counter and prescalers are + * only enabled to count when the designated edge is detected on the input selected by the CKSEL field. The + * minimum pulse width on the selected clock-gate input is 1 bus clock period. This mode is the + * high-performance, sampled-clock mode. + * 0b10..SCT Input Clock Mode. The input/edge selected by the CKSEL field clocks the SCT module, including the + * counters and prescalers, after first being synchronized to the system clock. The minimum pulse width on the + * clock input is 1 bus clock period. This mode is the low-power, sampled-clock mode. + * 0b11..Asynchronous Mode. The entire SCT module is clocked directly by the input/edge selected by the CKSEL + * field. In this mode, the SCT outputs are switched synchronously to the SCT input clock - not the system + * clock. The input clock rate must be at least half the system clock rate and can be the same or faster than + * the system clock. + */ +#define SCT_CONFIG_CLKMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CLKMODE_SHIFT)) & SCT_CONFIG_CLKMODE_MASK) +#define SCT_CONFIG_CKSEL_MASK (0x78U) +#define SCT_CONFIG_CKSEL_SHIFT (3U) +/*! CKSEL - SCT clock select. The specific functionality of the designated input/edge is dependent + * on the CLKMODE bit selection in this register. + * 0b0000..Rising edges on input 0. + * 0b0001..Falling edges on input 0. + * 0b0010..Rising edges on input 1. + * 0b0011..Falling edges on input 1. + * 0b0100..Rising edges on input 2. + * 0b0101..Falling edges on input 2. + * 0b0110..Rising edges on input 3. + * 0b0111..Falling edges on input 3. + */ +#define SCT_CONFIG_CKSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CKSEL_SHIFT)) & SCT_CONFIG_CKSEL_MASK) +#define SCT_CONFIG_NORELAOD_L_MASK (0x80U) +#define SCT_CONFIG_NORELAOD_L_SHIFT (7U) +#define SCT_CONFIG_NORELAOD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELAOD_L_SHIFT)) & SCT_CONFIG_NORELAOD_L_MASK) +#define SCT_CONFIG_NORELOAD_H_MASK (0x100U) +#define SCT_CONFIG_NORELOAD_H_SHIFT (8U) +#define SCT_CONFIG_NORELOAD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_H_SHIFT)) & SCT_CONFIG_NORELOAD_H_MASK) +#define SCT_CONFIG_INSYNC_MASK (0x1E00U) +#define SCT_CONFIG_INSYNC_SHIFT (9U) +#define SCT_CONFIG_INSYNC(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_INSYNC_SHIFT)) & SCT_CONFIG_INSYNC_MASK) +#define SCT_CONFIG_AUTOLIMIT_L_MASK (0x20000U) +#define SCT_CONFIG_AUTOLIMIT_L_SHIFT (17U) +#define SCT_CONFIG_AUTOLIMIT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_L_SHIFT)) & SCT_CONFIG_AUTOLIMIT_L_MASK) +#define SCT_CONFIG_AUTOLIMIT_H_MASK (0x40000U) +#define SCT_CONFIG_AUTOLIMIT_H_SHIFT (18U) +#define SCT_CONFIG_AUTOLIMIT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_H_SHIFT)) & SCT_CONFIG_AUTOLIMIT_H_MASK) +/*! @} */ + +/*! @name CTRL - SCT control register */ +/*! @{ */ +#define SCT_CTRL_DOWN_L_MASK (0x1U) +#define SCT_CTRL_DOWN_L_SHIFT (0U) +#define SCT_CTRL_DOWN_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_L_SHIFT)) & SCT_CTRL_DOWN_L_MASK) +#define SCT_CTRL_STOP_L_MASK (0x2U) +#define SCT_CTRL_STOP_L_SHIFT (1U) +#define SCT_CTRL_STOP_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_L_SHIFT)) & SCT_CTRL_STOP_L_MASK) +#define SCT_CTRL_HALT_L_MASK (0x4U) +#define SCT_CTRL_HALT_L_SHIFT (2U) +#define SCT_CTRL_HALT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_L_SHIFT)) & SCT_CTRL_HALT_L_MASK) +#define SCT_CTRL_CLRCTR_L_MASK (0x8U) +#define SCT_CTRL_CLRCTR_L_SHIFT (3U) +#define SCT_CTRL_CLRCTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_L_SHIFT)) & SCT_CTRL_CLRCTR_L_MASK) +#define SCT_CTRL_BIDIR_L_MASK (0x10U) +#define SCT_CTRL_BIDIR_L_SHIFT (4U) +/*! BIDIR_L - L or unified counter direction select + * 0b0..Up. The counter counts up to a limit condition, then is cleared to zero. + * 0b1..Up-down. The counter counts up to a limit, then counts down to a limit condition or to 0. + */ +#define SCT_CTRL_BIDIR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_L_SHIFT)) & SCT_CTRL_BIDIR_L_MASK) +#define SCT_CTRL_PRE_L_MASK (0x1FE0U) +#define SCT_CTRL_PRE_L_SHIFT (5U) +#define SCT_CTRL_PRE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_L_SHIFT)) & SCT_CTRL_PRE_L_MASK) +#define SCT_CTRL_DOWN_H_MASK (0x10000U) +#define SCT_CTRL_DOWN_H_SHIFT (16U) +#define SCT_CTRL_DOWN_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_H_SHIFT)) & SCT_CTRL_DOWN_H_MASK) +#define SCT_CTRL_STOP_H_MASK (0x20000U) +#define SCT_CTRL_STOP_H_SHIFT (17U) +#define SCT_CTRL_STOP_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_H_SHIFT)) & SCT_CTRL_STOP_H_MASK) +#define SCT_CTRL_HALT_H_MASK (0x40000U) +#define SCT_CTRL_HALT_H_SHIFT (18U) +#define SCT_CTRL_HALT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_H_SHIFT)) & SCT_CTRL_HALT_H_MASK) +#define SCT_CTRL_CLRCTR_H_MASK (0x80000U) +#define SCT_CTRL_CLRCTR_H_SHIFT (19U) +#define SCT_CTRL_CLRCTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_H_SHIFT)) & SCT_CTRL_CLRCTR_H_MASK) +#define SCT_CTRL_BIDIR_H_MASK (0x100000U) +#define SCT_CTRL_BIDIR_H_SHIFT (20U) +/*! BIDIR_H - Direction select + * 0b0..The H counter counts up to its limit condition, then is cleared to zero. + * 0b1..The H counter counts up to its limit, then counts down to a limit condition or to 0. + */ +#define SCT_CTRL_BIDIR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_H_SHIFT)) & SCT_CTRL_BIDIR_H_MASK) +#define SCT_CTRL_PRE_H_MASK (0x1FE00000U) +#define SCT_CTRL_PRE_H_SHIFT (21U) +#define SCT_CTRL_PRE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_H_SHIFT)) & SCT_CTRL_PRE_H_MASK) +/*! @} */ + +/*! @name LIMIT - SCT limit event select register */ +/*! @{ */ +#define SCT_LIMIT_LIMMSK_L_MASK (0xFFFFU) +#define SCT_LIMIT_LIMMSK_L_SHIFT (0U) +#define SCT_LIMIT_LIMMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_L_SHIFT)) & SCT_LIMIT_LIMMSK_L_MASK) +#define SCT_LIMIT_LIMMSK_H_MASK (0xFFFF0000U) +#define SCT_LIMIT_LIMMSK_H_SHIFT (16U) +#define SCT_LIMIT_LIMMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_H_SHIFT)) & SCT_LIMIT_LIMMSK_H_MASK) +/*! @} */ + +/*! @name HALT - SCT halt event select register */ +/*! @{ */ +#define SCT_HALT_HALTMSK_L_MASK (0xFFFFU) +#define SCT_HALT_HALTMSK_L_SHIFT (0U) +#define SCT_HALT_HALTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_L_SHIFT)) & SCT_HALT_HALTMSK_L_MASK) +#define SCT_HALT_HALTMSK_H_MASK (0xFFFF0000U) +#define SCT_HALT_HALTMSK_H_SHIFT (16U) +#define SCT_HALT_HALTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_H_SHIFT)) & SCT_HALT_HALTMSK_H_MASK) +/*! @} */ + +/*! @name STOP - SCT stop event select register */ +/*! @{ */ +#define SCT_STOP_STOPMSK_L_MASK (0xFFFFU) +#define SCT_STOP_STOPMSK_L_SHIFT (0U) +#define SCT_STOP_STOPMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_L_SHIFT)) & SCT_STOP_STOPMSK_L_MASK) +#define SCT_STOP_STOPMSK_H_MASK (0xFFFF0000U) +#define SCT_STOP_STOPMSK_H_SHIFT (16U) +#define SCT_STOP_STOPMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_H_SHIFT)) & SCT_STOP_STOPMSK_H_MASK) +/*! @} */ + +/*! @name START - SCT start event select register */ +/*! @{ */ +#define SCT_START_STARTMSK_L_MASK (0xFFFFU) +#define SCT_START_STARTMSK_L_SHIFT (0U) +#define SCT_START_STARTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_L_SHIFT)) & SCT_START_STARTMSK_L_MASK) +#define SCT_START_STARTMSK_H_MASK (0xFFFF0000U) +#define SCT_START_STARTMSK_H_SHIFT (16U) +#define SCT_START_STARTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_H_SHIFT)) & SCT_START_STARTMSK_H_MASK) +/*! @} */ + +/*! @name COUNT - SCT counter register */ +/*! @{ */ +#define SCT_COUNT_CTR_L_MASK (0xFFFFU) +#define SCT_COUNT_CTR_L_SHIFT (0U) +#define SCT_COUNT_CTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_L_SHIFT)) & SCT_COUNT_CTR_L_MASK) +#define SCT_COUNT_CTR_H_MASK (0xFFFF0000U) +#define SCT_COUNT_CTR_H_SHIFT (16U) +#define SCT_COUNT_CTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_H_SHIFT)) & SCT_COUNT_CTR_H_MASK) +/*! @} */ + +/*! @name STATE - SCT state register */ +/*! @{ */ +#define SCT_STATE_STATE_L_MASK (0x1FU) +#define SCT_STATE_STATE_L_SHIFT (0U) +#define SCT_STATE_STATE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_L_SHIFT)) & SCT_STATE_STATE_L_MASK) +#define SCT_STATE_STATE_H_MASK (0x1F0000U) +#define SCT_STATE_STATE_H_SHIFT (16U) +#define SCT_STATE_STATE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_H_SHIFT)) & SCT_STATE_STATE_H_MASK) +/*! @} */ + +/*! @name INPUT - SCT input register */ +/*! @{ */ +#define SCT_INPUT_AIN0_MASK (0x1U) +#define SCT_INPUT_AIN0_SHIFT (0U) +#define SCT_INPUT_AIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN0_SHIFT)) & SCT_INPUT_AIN0_MASK) +#define SCT_INPUT_AIN1_MASK (0x2U) +#define SCT_INPUT_AIN1_SHIFT (1U) +#define SCT_INPUT_AIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN1_SHIFT)) & SCT_INPUT_AIN1_MASK) +#define SCT_INPUT_AIN2_MASK (0x4U) +#define SCT_INPUT_AIN2_SHIFT (2U) +#define SCT_INPUT_AIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN2_SHIFT)) & SCT_INPUT_AIN2_MASK) +#define SCT_INPUT_AIN3_MASK (0x8U) +#define SCT_INPUT_AIN3_SHIFT (3U) +#define SCT_INPUT_AIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN3_SHIFT)) & SCT_INPUT_AIN3_MASK) +#define SCT_INPUT_AIN4_MASK (0x10U) +#define SCT_INPUT_AIN4_SHIFT (4U) +#define SCT_INPUT_AIN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN4_SHIFT)) & SCT_INPUT_AIN4_MASK) +#define SCT_INPUT_AIN5_MASK (0x20U) +#define SCT_INPUT_AIN5_SHIFT (5U) +#define SCT_INPUT_AIN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN5_SHIFT)) & SCT_INPUT_AIN5_MASK) +#define SCT_INPUT_AIN6_MASK (0x40U) +#define SCT_INPUT_AIN6_SHIFT (6U) +#define SCT_INPUT_AIN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN6_SHIFT)) & SCT_INPUT_AIN6_MASK) +#define SCT_INPUT_AIN7_MASK (0x80U) +#define SCT_INPUT_AIN7_SHIFT (7U) +#define SCT_INPUT_AIN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN7_SHIFT)) & SCT_INPUT_AIN7_MASK) +#define SCT_INPUT_AIN8_MASK (0x100U) +#define SCT_INPUT_AIN8_SHIFT (8U) +#define SCT_INPUT_AIN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN8_SHIFT)) & SCT_INPUT_AIN8_MASK) +#define SCT_INPUT_AIN9_MASK (0x200U) +#define SCT_INPUT_AIN9_SHIFT (9U) +#define SCT_INPUT_AIN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN9_SHIFT)) & SCT_INPUT_AIN9_MASK) +#define SCT_INPUT_AIN10_MASK (0x400U) +#define SCT_INPUT_AIN10_SHIFT (10U) +#define SCT_INPUT_AIN10(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN10_SHIFT)) & SCT_INPUT_AIN10_MASK) +#define SCT_INPUT_AIN11_MASK (0x800U) +#define SCT_INPUT_AIN11_SHIFT (11U) +#define SCT_INPUT_AIN11(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN11_SHIFT)) & SCT_INPUT_AIN11_MASK) +#define SCT_INPUT_AIN12_MASK (0x1000U) +#define SCT_INPUT_AIN12_SHIFT (12U) +#define SCT_INPUT_AIN12(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN12_SHIFT)) & SCT_INPUT_AIN12_MASK) +#define SCT_INPUT_AIN13_MASK (0x2000U) +#define SCT_INPUT_AIN13_SHIFT (13U) +#define SCT_INPUT_AIN13(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN13_SHIFT)) & SCT_INPUT_AIN13_MASK) +#define SCT_INPUT_AIN14_MASK (0x4000U) +#define SCT_INPUT_AIN14_SHIFT (14U) +#define SCT_INPUT_AIN14(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN14_SHIFT)) & SCT_INPUT_AIN14_MASK) +#define SCT_INPUT_AIN15_MASK (0x8000U) +#define SCT_INPUT_AIN15_SHIFT (15U) +#define SCT_INPUT_AIN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN15_SHIFT)) & SCT_INPUT_AIN15_MASK) +#define SCT_INPUT_SIN0_MASK (0x10000U) +#define SCT_INPUT_SIN0_SHIFT (16U) +#define SCT_INPUT_SIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN0_SHIFT)) & SCT_INPUT_SIN0_MASK) +#define SCT_INPUT_SIN1_MASK (0x20000U) +#define SCT_INPUT_SIN1_SHIFT (17U) +#define SCT_INPUT_SIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN1_SHIFT)) & SCT_INPUT_SIN1_MASK) +#define SCT_INPUT_SIN2_MASK (0x40000U) +#define SCT_INPUT_SIN2_SHIFT (18U) +#define SCT_INPUT_SIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN2_SHIFT)) & SCT_INPUT_SIN2_MASK) +#define SCT_INPUT_SIN3_MASK (0x80000U) +#define SCT_INPUT_SIN3_SHIFT (19U) +#define SCT_INPUT_SIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN3_SHIFT)) & SCT_INPUT_SIN3_MASK) +#define SCT_INPUT_SIN4_MASK (0x100000U) +#define SCT_INPUT_SIN4_SHIFT (20U) +#define SCT_INPUT_SIN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN4_SHIFT)) & SCT_INPUT_SIN4_MASK) +#define SCT_INPUT_SIN5_MASK (0x200000U) +#define SCT_INPUT_SIN5_SHIFT (21U) +#define SCT_INPUT_SIN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN5_SHIFT)) & SCT_INPUT_SIN5_MASK) +#define SCT_INPUT_SIN6_MASK (0x400000U) +#define SCT_INPUT_SIN6_SHIFT (22U) +#define SCT_INPUT_SIN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN6_SHIFT)) & SCT_INPUT_SIN6_MASK) +#define SCT_INPUT_SIN7_MASK (0x800000U) +#define SCT_INPUT_SIN7_SHIFT (23U) +#define SCT_INPUT_SIN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN7_SHIFT)) & SCT_INPUT_SIN7_MASK) +#define SCT_INPUT_SIN8_MASK (0x1000000U) +#define SCT_INPUT_SIN8_SHIFT (24U) +#define SCT_INPUT_SIN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN8_SHIFT)) & SCT_INPUT_SIN8_MASK) +#define SCT_INPUT_SIN9_MASK (0x2000000U) +#define SCT_INPUT_SIN9_SHIFT (25U) +#define SCT_INPUT_SIN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN9_SHIFT)) & SCT_INPUT_SIN9_MASK) +#define SCT_INPUT_SIN10_MASK (0x4000000U) +#define SCT_INPUT_SIN10_SHIFT (26U) +#define SCT_INPUT_SIN10(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN10_SHIFT)) & SCT_INPUT_SIN10_MASK) +#define SCT_INPUT_SIN11_MASK (0x8000000U) +#define SCT_INPUT_SIN11_SHIFT (27U) +#define SCT_INPUT_SIN11(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN11_SHIFT)) & SCT_INPUT_SIN11_MASK) +#define SCT_INPUT_SIN12_MASK (0x10000000U) +#define SCT_INPUT_SIN12_SHIFT (28U) +#define SCT_INPUT_SIN12(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN12_SHIFT)) & SCT_INPUT_SIN12_MASK) +#define SCT_INPUT_SIN13_MASK (0x20000000U) +#define SCT_INPUT_SIN13_SHIFT (29U) +#define SCT_INPUT_SIN13(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN13_SHIFT)) & SCT_INPUT_SIN13_MASK) +#define SCT_INPUT_SIN14_MASK (0x40000000U) +#define SCT_INPUT_SIN14_SHIFT (30U) +#define SCT_INPUT_SIN14(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN14_SHIFT)) & SCT_INPUT_SIN14_MASK) +#define SCT_INPUT_SIN15_MASK (0x80000000U) +#define SCT_INPUT_SIN15_SHIFT (31U) +#define SCT_INPUT_SIN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN15_SHIFT)) & SCT_INPUT_SIN15_MASK) +/*! @} */ + +/*! @name REGMODE - SCT match/capture mode register */ +/*! @{ */ +#define SCT_REGMODE_REGMOD_L_MASK (0xFFFFU) +#define SCT_REGMODE_REGMOD_L_SHIFT (0U) +#define SCT_REGMODE_REGMOD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L_SHIFT)) & SCT_REGMODE_REGMOD_L_MASK) +#define SCT_REGMODE_REGMOD_H_MASK (0xFFFF0000U) +#define SCT_REGMODE_REGMOD_H_SHIFT (16U) +#define SCT_REGMODE_REGMOD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H_SHIFT)) & SCT_REGMODE_REGMOD_H_MASK) +/*! @} */ + +/*! @name OUTPUT - SCT output register */ +/*! @{ */ +#define SCT_OUTPUT_OUT_MASK (0xFFFFU) +#define SCT_OUTPUT_OUT_SHIFT (0U) +#define SCT_OUTPUT_OUT(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT_SHIFT)) & SCT_OUTPUT_OUT_MASK) +/*! @} */ + +/*! @name OUTPUTDIRCTRL - SCT output counter direction control register */ +/*! @{ */ +#define SCT_OUTPUTDIRCTRL_SETCLR0_MASK (0x3U) +#define SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT (0U) +/*! SETCLR0 - Set/clear operation on output 0. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR0(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR0_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR1_MASK (0xCU) +#define SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT (2U) +/*! SETCLR1 - Set/clear operation on output 1. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR1(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR1_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR2_MASK (0x30U) +#define SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT (4U) +/*! SETCLR2 - Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR2(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR2_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR3_MASK (0xC0U) +#define SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT (6U) +/*! SETCLR3 - Set/clear operation on output 3. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR3(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR3_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR4_MASK (0x300U) +#define SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT (8U) +/*! SETCLR4 - Set/clear operation on output 4. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR4(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR4_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR5_MASK (0xC00U) +#define SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT (10U) +/*! SETCLR5 - Set/clear operation on output 5. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR5(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR5_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR6_MASK (0x3000U) +#define SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT (12U) +/*! SETCLR6 - Set/clear operation on output 6. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR6(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR6_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR7_MASK (0xC000U) +#define SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT (14U) +/*! SETCLR7 - Set/clear operation on output 7. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR7(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR7_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR8_MASK (0x30000U) +#define SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT (16U) +/*! SETCLR8 - Set/clear operation on output 8. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR8(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR8_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR9_MASK (0xC0000U) +#define SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT (18U) +/*! SETCLR9 - Set/clear operation on output 9. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR9(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR9_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR10_MASK (0x300000U) +#define SCT_OUTPUTDIRCTRL_SETCLR10_SHIFT (20U) +/*! SETCLR10 - Set/clear operation on output 10. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR10(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR10_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR10_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR11_MASK (0xC00000U) +#define SCT_OUTPUTDIRCTRL_SETCLR11_SHIFT (22U) +/*! SETCLR11 - Set/clear operation on output 11. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR11(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR11_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR11_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR12_MASK (0x3000000U) +#define SCT_OUTPUTDIRCTRL_SETCLR12_SHIFT (24U) +/*! SETCLR12 - Set/clear operation on output 12. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR12(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR12_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR12_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR13_MASK (0xC000000U) +#define SCT_OUTPUTDIRCTRL_SETCLR13_SHIFT (26U) +/*! SETCLR13 - Set/clear operation on output 13. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR13(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR13_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR13_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR14_MASK (0x30000000U) +#define SCT_OUTPUTDIRCTRL_SETCLR14_SHIFT (28U) +/*! SETCLR14 - Set/clear operation on output 14. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR14(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR14_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR14_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR15_MASK (0xC0000000U) +#define SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT (30U) +/*! SETCLR15 - Set/clear operation on output 15. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR15(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR15_MASK) +/*! @} */ + +/*! @name RES - SCT conflict resolution register */ +/*! @{ */ +#define SCT_RES_O0RES_MASK (0x3U) +#define SCT_RES_O0RES_SHIFT (0U) +/*! O0RES - Effect of simultaneous set and clear on output 0. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR0 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR0 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O0RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O0RES_SHIFT)) & SCT_RES_O0RES_MASK) +#define SCT_RES_O1RES_MASK (0xCU) +#define SCT_RES_O1RES_SHIFT (2U) +/*! O1RES - Effect of simultaneous set and clear on output 1. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR1 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR1 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O1RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O1RES_SHIFT)) & SCT_RES_O1RES_MASK) +#define SCT_RES_O2RES_MASK (0x30U) +#define SCT_RES_O2RES_SHIFT (4U) +/*! O2RES - Effect of simultaneous set and clear on output 2. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR2 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output n (or set based on the SETCLR2 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O2RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O2RES_SHIFT)) & SCT_RES_O2RES_MASK) +#define SCT_RES_O3RES_MASK (0xC0U) +#define SCT_RES_O3RES_SHIFT (6U) +/*! O3RES - Effect of simultaneous set and clear on output 3. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR3 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR3 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O3RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O3RES_SHIFT)) & SCT_RES_O3RES_MASK) +#define SCT_RES_O4RES_MASK (0x300U) +#define SCT_RES_O4RES_SHIFT (8U) +/*! O4RES - Effect of simultaneous set and clear on output 4. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR4 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR4 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O4RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O4RES_SHIFT)) & SCT_RES_O4RES_MASK) +#define SCT_RES_O5RES_MASK (0xC00U) +#define SCT_RES_O5RES_SHIFT (10U) +/*! O5RES - Effect of simultaneous set and clear on output 5. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR5 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR5 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O5RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O5RES_SHIFT)) & SCT_RES_O5RES_MASK) +#define SCT_RES_O6RES_MASK (0x3000U) +#define SCT_RES_O6RES_SHIFT (12U) +/*! O6RES - Effect of simultaneous set and clear on output 6. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR6 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR6 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O6RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O6RES_SHIFT)) & SCT_RES_O6RES_MASK) +#define SCT_RES_O7RES_MASK (0xC000U) +#define SCT_RES_O7RES_SHIFT (14U) +/*! O7RES - Effect of simultaneous set and clear on output 7. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR7 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output n (or set based on the SETCLR7 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O7RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O7RES_SHIFT)) & SCT_RES_O7RES_MASK) +#define SCT_RES_O8RES_MASK (0x30000U) +#define SCT_RES_O8RES_SHIFT (16U) +/*! O8RES - Effect of simultaneous set and clear on output 8. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR8 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR8 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O8RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O8RES_SHIFT)) & SCT_RES_O8RES_MASK) +#define SCT_RES_O9RES_MASK (0xC0000U) +#define SCT_RES_O9RES_SHIFT (18U) +/*! O9RES - Effect of simultaneous set and clear on output 9. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR9 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR9 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O9RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O9RES_SHIFT)) & SCT_RES_O9RES_MASK) +#define SCT_RES_O10RES_MASK (0x300000U) +#define SCT_RES_O10RES_SHIFT (20U) +/*! O10RES - Effect of simultaneous set and clear on output 10. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR10 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR10 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O10RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O10RES_SHIFT)) & SCT_RES_O10RES_MASK) +#define SCT_RES_O11RES_MASK (0xC00000U) +#define SCT_RES_O11RES_SHIFT (22U) +/*! O11RES - Effect of simultaneous set and clear on output 11. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR11 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR11 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O11RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O11RES_SHIFT)) & SCT_RES_O11RES_MASK) +#define SCT_RES_O12RES_MASK (0x3000000U) +#define SCT_RES_O12RES_SHIFT (24U) +/*! O12RES - Effect of simultaneous set and clear on output 12. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR12 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR12 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O12RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O12RES_SHIFT)) & SCT_RES_O12RES_MASK) +#define SCT_RES_O13RES_MASK (0xC000000U) +#define SCT_RES_O13RES_SHIFT (26U) +/*! O13RES - Effect of simultaneous set and clear on output 13. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR13 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR13 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O13RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O13RES_SHIFT)) & SCT_RES_O13RES_MASK) +#define SCT_RES_O14RES_MASK (0x30000000U) +#define SCT_RES_O14RES_SHIFT (28U) +/*! O14RES - Effect of simultaneous set and clear on output 14. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR14 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR14 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O14RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O14RES_SHIFT)) & SCT_RES_O14RES_MASK) +#define SCT_RES_O15RES_MASK (0xC0000000U) +#define SCT_RES_O15RES_SHIFT (30U) +/*! O15RES - Effect of simultaneous set and clear on output 15. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR15 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR15 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O15RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O15RES_SHIFT)) & SCT_RES_O15RES_MASK) +/*! @} */ + +/*! @name DMA0REQUEST - SCT DMA request 0 register */ +/*! @{ */ +#define SCT_DMA0REQUEST_DEV_0_MASK (0xFFFFU) +#define SCT_DMA0REQUEST_DEV_0_SHIFT (0U) +#define SCT_DMA0REQUEST_DEV_0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA0REQUEST_DEV_0_SHIFT)) & SCT_DMA0REQUEST_DEV_0_MASK) +#define SCT_DMA0REQUEST_DRL0_MASK (0x40000000U) +#define SCT_DMA0REQUEST_DRL0_SHIFT (30U) +#define SCT_DMA0REQUEST_DRL0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA0REQUEST_DRL0_SHIFT)) & SCT_DMA0REQUEST_DRL0_MASK) +#define SCT_DMA0REQUEST_DRQ0_MASK (0x80000000U) +#define SCT_DMA0REQUEST_DRQ0_SHIFT (31U) +#define SCT_DMA0REQUEST_DRQ0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA0REQUEST_DRQ0_SHIFT)) & SCT_DMA0REQUEST_DRQ0_MASK) +/*! @} */ + +/*! @name DMA1REQUEST - SCT DMA request 1 register */ +/*! @{ */ +#define SCT_DMA1REQUEST_DEV_1_MASK (0xFFFFU) +#define SCT_DMA1REQUEST_DEV_1_SHIFT (0U) +#define SCT_DMA1REQUEST_DEV_1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA1REQUEST_DEV_1_SHIFT)) & SCT_DMA1REQUEST_DEV_1_MASK) +#define SCT_DMA1REQUEST_DRL1_MASK (0x40000000U) +#define SCT_DMA1REQUEST_DRL1_SHIFT (30U) +#define SCT_DMA1REQUEST_DRL1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA1REQUEST_DRL1_SHIFT)) & SCT_DMA1REQUEST_DRL1_MASK) +#define SCT_DMA1REQUEST_DRQ1_MASK (0x80000000U) +#define SCT_DMA1REQUEST_DRQ1_SHIFT (31U) +#define SCT_DMA1REQUEST_DRQ1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA1REQUEST_DRQ1_SHIFT)) & SCT_DMA1REQUEST_DRQ1_MASK) +/*! @} */ + +/*! @name EVEN - SCT event interrupt enable register */ +/*! @{ */ +#define SCT_EVEN_IEN_MASK (0xFFFFU) +#define SCT_EVEN_IEN_SHIFT (0U) +#define SCT_EVEN_IEN(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN_SHIFT)) & SCT_EVEN_IEN_MASK) +/*! @} */ + +/*! @name EVFLAG - SCT event flag register */ +/*! @{ */ +#define SCT_EVFLAG_FLAG_MASK (0xFFFFU) +#define SCT_EVFLAG_FLAG_SHIFT (0U) +#define SCT_EVFLAG_FLAG(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG_SHIFT)) & SCT_EVFLAG_FLAG_MASK) +/*! @} */ + +/*! @name CONEN - SCT conflict interrupt enable register */ +/*! @{ */ +#define SCT_CONEN_NCEN_MASK (0xFFFFU) +#define SCT_CONEN_NCEN_SHIFT (0U) +#define SCT_CONEN_NCEN(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN_SHIFT)) & SCT_CONEN_NCEN_MASK) +/*! @} */ + +/*! @name CONFLAG - SCT conflict flag register */ +/*! @{ */ +#define SCT_CONFLAG_NCFLAG_MASK (0xFFFFU) +#define SCT_CONFLAG_NCFLAG_SHIFT (0U) +#define SCT_CONFLAG_NCFLAG(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG_SHIFT)) & SCT_CONFLAG_NCFLAG_MASK) +#define SCT_CONFLAG_BUSERRL_MASK (0x40000000U) +#define SCT_CONFLAG_BUSERRL_SHIFT (30U) +#define SCT_CONFLAG_BUSERRL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRL_SHIFT)) & SCT_CONFLAG_BUSERRL_MASK) +#define SCT_CONFLAG_BUSERRH_MASK (0x80000000U) +#define SCT_CONFLAG_BUSERRH_SHIFT (31U) +#define SCT_CONFLAG_BUSERRH(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRH_SHIFT)) & SCT_CONFLAG_BUSERRH_MASK) +/*! @} */ + +/*! @name SCTCAP - SCT capture register of capture channel */ +/*! @{ */ +#define SCT_SCTCAP_CAPn_L_MASK (0xFFFFU) +#define SCT_SCTCAP_CAPn_L_SHIFT (0U) +#define SCT_SCTCAP_CAPn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAP_CAPn_L_SHIFT)) & SCT_SCTCAP_CAPn_L_MASK) +#define SCT_SCTCAP_CAPn_H_MASK (0xFFFF0000U) +#define SCT_SCTCAP_CAPn_H_SHIFT (16U) +#define SCT_SCTCAP_CAPn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAP_CAPn_H_SHIFT)) & SCT_SCTCAP_CAPn_H_MASK) +/*! @} */ + +/* The count of SCT_SCTCAP */ +#define SCT_SCTCAP_COUNT (16U) + +/*! @name SCTMATCH - SCT match value register of match channels */ +/*! @{ */ +#define SCT_SCTMATCH_MATCHn_L_MASK (0xFFFFU) +#define SCT_SCTMATCH_MATCHn_L_SHIFT (0U) +#define SCT_SCTMATCH_MATCHn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCH_MATCHn_L_SHIFT)) & SCT_SCTMATCH_MATCHn_L_MASK) +#define SCT_SCTMATCH_MATCHn_H_MASK (0xFFFF0000U) +#define SCT_SCTMATCH_MATCHn_H_SHIFT (16U) +#define SCT_SCTMATCH_MATCHn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCH_MATCHn_H_SHIFT)) & SCT_SCTMATCH_MATCHn_H_MASK) +/*! @} */ + +/* The count of SCT_SCTMATCH */ +#define SCT_SCTMATCH_COUNT (16U) + +/*! @name SCTCAPCTRL - SCT capture control register */ +/*! @{ */ +#define SCT_SCTCAPCTRL_CAPCONn_L_MASK (0xFFFFU) +#define SCT_SCTCAPCTRL_CAPCONn_L_SHIFT (0U) +#define SCT_SCTCAPCTRL_CAPCONn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAPCTRL_CAPCONn_L_SHIFT)) & SCT_SCTCAPCTRL_CAPCONn_L_MASK) +#define SCT_SCTCAPCTRL_CAPCONn_H_MASK (0xFFFF0000U) +#define SCT_SCTCAPCTRL_CAPCONn_H_SHIFT (16U) +#define SCT_SCTCAPCTRL_CAPCONn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAPCTRL_CAPCONn_H_SHIFT)) & SCT_SCTCAPCTRL_CAPCONn_H_MASK) +/*! @} */ + +/* The count of SCT_SCTCAPCTRL */ +#define SCT_SCTCAPCTRL_COUNT (16U) + +/*! @name SCTMATCHREL - SCT match reload value register */ +/*! @{ */ +#define SCT_SCTMATCHREL_RELOADn_L_MASK (0xFFFFU) +#define SCT_SCTMATCHREL_RELOADn_L_SHIFT (0U) +#define SCT_SCTMATCHREL_RELOADn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCHREL_RELOADn_L_SHIFT)) & SCT_SCTMATCHREL_RELOADn_L_MASK) +#define SCT_SCTMATCHREL_RELOADn_H_MASK (0xFFFF0000U) +#define SCT_SCTMATCHREL_RELOADn_H_SHIFT (16U) +#define SCT_SCTMATCHREL_RELOADn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCHREL_RELOADn_H_SHIFT)) & SCT_SCTMATCHREL_RELOADn_H_MASK) +/*! @} */ + +/* The count of SCT_SCTMATCHREL */ +#define SCT_SCTMATCHREL_COUNT (16U) + +/*! @name EVENT_STATE - SCT event state register 0 */ +/*! @{ */ +#define SCT_EVENT_STATE_STATEMSKn_MASK (0xFFFFU) +#define SCT_EVENT_STATE_STATEMSKn_SHIFT (0U) +#define SCT_EVENT_STATE_STATEMSKn(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_STATE_STATEMSKn_SHIFT)) & SCT_EVENT_STATE_STATEMSKn_MASK) +/*! @} */ + +/* The count of SCT_EVENT_STATE */ +#define SCT_EVENT_STATE_COUNT (16U) + +/*! @name EVENT_CTRL - SCT event control register 0 */ +/*! @{ */ +#define SCT_EVENT_CTRL_MATCHSEL_MASK (0xFU) +#define SCT_EVENT_CTRL_MATCHSEL_SHIFT (0U) +#define SCT_EVENT_CTRL_MATCHSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_MATCHSEL_SHIFT)) & SCT_EVENT_CTRL_MATCHSEL_MASK) +#define SCT_EVENT_CTRL_HEVENT_MASK (0x10U) +#define SCT_EVENT_CTRL_HEVENT_SHIFT (4U) +/*! HEVENT - Select L/H counter. Do not set this bit if UNIFY = 1. + * 0b0..Selects the L state and the L match register selected by MATCHSEL. + * 0b1..Selects the H state and the H match register selected by MATCHSEL. + */ +#define SCT_EVENT_CTRL_HEVENT(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_HEVENT_SHIFT)) & SCT_EVENT_CTRL_HEVENT_MASK) +#define SCT_EVENT_CTRL_OUTSEL_MASK (0x20U) +#define SCT_EVENT_CTRL_OUTSEL_SHIFT (5U) +/*! OUTSEL - Input/output select + * 0b0..Selects the inputs selected by IOSEL. + * 0b1..Selects the outputs selected by IOSEL. + */ +#define SCT_EVENT_CTRL_OUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_OUTSEL_SHIFT)) & SCT_EVENT_CTRL_OUTSEL_MASK) +#define SCT_EVENT_CTRL_IOSEL_MASK (0x3C0U) +#define SCT_EVENT_CTRL_IOSEL_SHIFT (6U) +#define SCT_EVENT_CTRL_IOSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_IOSEL_SHIFT)) & SCT_EVENT_CTRL_IOSEL_MASK) +#define SCT_EVENT_CTRL_IOCOND_MASK (0xC00U) +#define SCT_EVENT_CTRL_IOCOND_SHIFT (10U) +/*! IOCOND - Selects the I/O condition for event n. (The detection of edges on outputs lag the + * conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state + * detection, an input must have a minimum pulse width of at least one SCT clock period . + * 0b00..LOW + * 0b01..Rise + * 0b10..Fall + * 0b11..HIGH + */ +#define SCT_EVENT_CTRL_IOCOND(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_IOCOND_SHIFT)) & SCT_EVENT_CTRL_IOCOND_MASK) +#define SCT_EVENT_CTRL_COMBMODE_MASK (0x3000U) +#define SCT_EVENT_CTRL_COMBMODE_SHIFT (12U) +/*! COMBMODE - Selects how the specified match and I/O condition are used and combined. + * 0b00..OR. The event occurs when either the specified match or I/O condition occurs. + * 0b01..MATCH. Uses the specified match only. + * 0b10..IO. Uses the specified I/O condition only. + * 0b11..AND. The event occurs when the specified match and I/O condition occur simultaneously. + */ +#define SCT_EVENT_CTRL_COMBMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_COMBMODE_SHIFT)) & SCT_EVENT_CTRL_COMBMODE_MASK) +#define SCT_EVENT_CTRL_STATELD_MASK (0x4000U) +#define SCT_EVENT_CTRL_STATELD_SHIFT (14U) +/*! STATELD - This bit controls how the STATEV value modifies the state selected by HEVENT when this + * event is the highest-numbered event occurring for that state. + * 0b0..STATEV value is added into STATE (the carry-out is ignored). + * 0b1..STATEV value is loaded into STATE. + */ +#define SCT_EVENT_CTRL_STATELD(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_STATELD_SHIFT)) & SCT_EVENT_CTRL_STATELD_MASK) +#define SCT_EVENT_CTRL_STATEV_MASK (0xF8000U) +#define SCT_EVENT_CTRL_STATEV_SHIFT (15U) +#define SCT_EVENT_CTRL_STATEV(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_STATEV_SHIFT)) & SCT_EVENT_CTRL_STATEV_MASK) +#define SCT_EVENT_CTRL_MATCHMEM_MASK (0x100000U) +#define SCT_EVENT_CTRL_MATCHMEM_SHIFT (20U) +#define SCT_EVENT_CTRL_MATCHMEM(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_MATCHMEM_SHIFT)) & SCT_EVENT_CTRL_MATCHMEM_MASK) +#define SCT_EVENT_CTRL_DIRECTION_MASK (0x600000U) +#define SCT_EVENT_CTRL_DIRECTION_SHIFT (21U) +/*! DIRECTION - Direction qualifier for event generation. This field only applies when the counters + * are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved. + * 0b00..Direction independent. This event is triggered regardless of the count direction. + * 0b01..Counting up. This event is triggered only during up-counting when BIDIR = 1. + * 0b10..Counting down. This event is triggered only during down-counting when BIDIR = 1. + */ +#define SCT_EVENT_CTRL_DIRECTION(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_DIRECTION_SHIFT)) & SCT_EVENT_CTRL_DIRECTION_MASK) +/*! @} */ + +/* The count of SCT_EVENT_CTRL */ +#define SCT_EVENT_CTRL_COUNT (16U) + +/*! @name OUT_SET - SCT output 0 set register */ +/*! @{ */ +#define SCT_OUT_SET_SET_MASK (0xFFFFU) +#define SCT_OUT_SET_SET_SHIFT (0U) +#define SCT_OUT_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_SET_SET_SHIFT)) & SCT_OUT_SET_SET_MASK) +/*! @} */ + +/* The count of SCT_OUT_SET */ +#define SCT_OUT_SET_COUNT (10U) + +/*! @name OUT_CLR - SCT output 0 clear register */ +/*! @{ */ +#define SCT_OUT_CLR_CLR_MASK (0xFFFFU) +#define SCT_OUT_CLR_CLR_SHIFT (0U) +#define SCT_OUT_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_CLR_CLR_SHIFT)) & SCT_OUT_CLR_CLR_MASK) +/*! @} */ + +/* The count of SCT_OUT_CLR */ +#define SCT_OUT_CLR_COUNT (10U) + + +/*! + * @} + */ /* end of group SCT_Register_Masks */ + + +/* SCT - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral SCT0 base address */ + #define SCT0_BASE (0x50085000u) + /** Peripheral SCT0 base address */ + #define SCT0_BASE_NS (0x40085000u) + /** Peripheral SCT0 base pointer */ + #define SCT0 ((SCT_Type *)SCT0_BASE) + /** Peripheral SCT0 base pointer */ + #define SCT0_NS ((SCT_Type *)SCT0_BASE_NS) + /** Array initializer of SCT peripheral base addresses */ + #define SCT_BASE_ADDRS { SCT0_BASE } + /** Array initializer of SCT peripheral base pointers */ + #define SCT_BASE_PTRS { SCT0 } + /** Array initializer of SCT peripheral base addresses */ + #define SCT_BASE_ADDRS_NS { SCT0_BASE_NS } + /** Array initializer of SCT peripheral base pointers */ + #define SCT_BASE_PTRS_NS { SCT0_NS } +#else + /** Peripheral SCT0 base address */ + #define SCT0_BASE (0x40085000u) + /** Peripheral SCT0 base pointer */ + #define SCT0 ((SCT_Type *)SCT0_BASE) + /** Array initializer of SCT peripheral base addresses */ + #define SCT_BASE_ADDRS { SCT0_BASE } + /** Array initializer of SCT peripheral base pointers */ + #define SCT_BASE_PTRS { SCT0 } +#endif +/** Interrupt vectors for the SCT peripheral type */ +#define SCT_IRQS { SCT0_IRQn } + +/*! + * @} + */ /* end of group SCT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SDIF Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDIF_Peripheral_Access_Layer SDIF Peripheral Access Layer + * @{ + */ + +/** SDIF - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< Control register, offset: 0x0 */ + __IO uint32_t PWREN; /**< Power Enable register, offset: 0x4 */ + __IO uint32_t CLKDIV; /**< Clock Divider register, offset: 0x8 */ + uint8_t RESERVED_0[4]; + __IO uint32_t CLKENA; /**< Clock Enable register, offset: 0x10 */ + __IO uint32_t TMOUT; /**< Time-out register, offset: 0x14 */ + __IO uint32_t CTYPE; /**< Card Type register, offset: 0x18 */ + __IO uint32_t BLKSIZ; /**< Block Size register, offset: 0x1C */ + __IO uint32_t BYTCNT; /**< Byte Count register, offset: 0x20 */ + __IO uint32_t INTMASK; /**< Interrupt Mask register, offset: 0x24 */ + __IO uint32_t CMDARG; /**< Command Argument register, offset: 0x28 */ + __IO uint32_t CMD; /**< Command register, offset: 0x2C */ + __IO uint32_t RESP[4]; /**< Response register, array offset: 0x30, array step: 0x4 */ + __IO uint32_t MINTSTS; /**< Masked Interrupt Status register, offset: 0x40 */ + __IO uint32_t RINTSTS; /**< Raw Interrupt Status register, offset: 0x44 */ + __IO uint32_t STATUS; /**< Status register, offset: 0x48 */ + __IO uint32_t FIFOTH; /**< FIFO Threshold Watermark register, offset: 0x4C */ + __IO uint32_t CDETECT; /**< Card Detect register, offset: 0x50 */ + __IO uint32_t WRTPRT; /**< Write Protect register, offset: 0x54 */ + uint8_t RESERVED_1[4]; + __IO uint32_t TCBCNT; /**< Transferred CIU Card Byte Count register, offset: 0x5C */ + __IO uint32_t TBBCNT; /**< Transferred Host to BIU-FIFO Byte Count register, offset: 0x60 */ + __IO uint32_t DEBNCE; /**< Debounce Count register, offset: 0x64 */ + uint8_t RESERVED_2[16]; + __IO uint32_t RST_N; /**< Hardware Reset, offset: 0x78 */ + uint8_t RESERVED_3[4]; + __IO uint32_t BMOD; /**< Bus Mode register, offset: 0x80 */ + __IO uint32_t PLDMND; /**< Poll Demand register, offset: 0x84 */ + __IO uint32_t DBADDR; /**< Descriptor List Base Address register, offset: 0x88 */ + __IO uint32_t IDSTS; /**< Internal DMAC Status register, offset: 0x8C */ + __IO uint32_t IDINTEN; /**< Internal DMAC Interrupt Enable register, offset: 0x90 */ + __IO uint32_t DSCADDR; /**< Current Host Descriptor Address register, offset: 0x94 */ + __IO uint32_t BUFADDR; /**< Current Buffer Descriptor Address register, offset: 0x98 */ + uint8_t RESERVED_4[100]; + __IO uint32_t CARDTHRCTL; /**< Card Threshold Control, offset: 0x100 */ + __IO uint32_t BACKENDPWR; /**< Power control, offset: 0x104 */ + uint8_t RESERVED_5[248]; + __IO uint32_t FIFO[64]; /**< SDIF FIFO, array offset: 0x200, array step: 0x4 */ +} SDIF_Type; + +/* ---------------------------------------------------------------------------- + -- SDIF Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDIF_Register_Masks SDIF Register Masks + * @{ + */ + +/*! @name CTRL - Control register */ +/*! @{ */ +#define SDIF_CTRL_CONTROLLER_RESET_MASK (0x1U) +#define SDIF_CTRL_CONTROLLER_RESET_SHIFT (0U) +#define SDIF_CTRL_CONTROLLER_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CONTROLLER_RESET_SHIFT)) & SDIF_CTRL_CONTROLLER_RESET_MASK) +#define SDIF_CTRL_FIFO_RESET_MASK (0x2U) +#define SDIF_CTRL_FIFO_RESET_SHIFT (1U) +#define SDIF_CTRL_FIFO_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_FIFO_RESET_SHIFT)) & SDIF_CTRL_FIFO_RESET_MASK) +#define SDIF_CTRL_DMA_RESET_MASK (0x4U) +#define SDIF_CTRL_DMA_RESET_SHIFT (2U) +#define SDIF_CTRL_DMA_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_DMA_RESET_SHIFT)) & SDIF_CTRL_DMA_RESET_MASK) +#define SDIF_CTRL_INT_ENABLE_MASK (0x10U) +#define SDIF_CTRL_INT_ENABLE_SHIFT (4U) +#define SDIF_CTRL_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_INT_ENABLE_SHIFT)) & SDIF_CTRL_INT_ENABLE_MASK) +#define SDIF_CTRL_READ_WAIT_MASK (0x40U) +#define SDIF_CTRL_READ_WAIT_SHIFT (6U) +#define SDIF_CTRL_READ_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_READ_WAIT_SHIFT)) & SDIF_CTRL_READ_WAIT_MASK) +#define SDIF_CTRL_SEND_IRQ_RESPONSE_MASK (0x80U) +#define SDIF_CTRL_SEND_IRQ_RESPONSE_SHIFT (7U) +#define SDIF_CTRL_SEND_IRQ_RESPONSE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_IRQ_RESPONSE_SHIFT)) & SDIF_CTRL_SEND_IRQ_RESPONSE_MASK) +#define SDIF_CTRL_ABORT_READ_DATA_MASK (0x100U) +#define SDIF_CTRL_ABORT_READ_DATA_SHIFT (8U) +#define SDIF_CTRL_ABORT_READ_DATA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_ABORT_READ_DATA_SHIFT)) & SDIF_CTRL_ABORT_READ_DATA_MASK) +#define SDIF_CTRL_SEND_CCSD_MASK (0x200U) +#define SDIF_CTRL_SEND_CCSD_SHIFT (9U) +#define SDIF_CTRL_SEND_CCSD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_CCSD_SHIFT)) & SDIF_CTRL_SEND_CCSD_MASK) +#define SDIF_CTRL_SEND_AUTO_STOP_CCSD_MASK (0x400U) +#define SDIF_CTRL_SEND_AUTO_STOP_CCSD_SHIFT (10U) +#define SDIF_CTRL_SEND_AUTO_STOP_CCSD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_AUTO_STOP_CCSD_SHIFT)) & SDIF_CTRL_SEND_AUTO_STOP_CCSD_MASK) +#define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_MASK (0x800U) +#define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_SHIFT (11U) +#define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_SHIFT)) & SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_MASK) +#define SDIF_CTRL_CARD_VOLTAGE_A0_MASK (0x10000U) +#define SDIF_CTRL_CARD_VOLTAGE_A0_SHIFT (16U) +#define SDIF_CTRL_CARD_VOLTAGE_A0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A0_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A0_MASK) +#define SDIF_CTRL_CARD_VOLTAGE_A1_MASK (0x20000U) +#define SDIF_CTRL_CARD_VOLTAGE_A1_SHIFT (17U) +#define SDIF_CTRL_CARD_VOLTAGE_A1(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A1_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A1_MASK) +#define SDIF_CTRL_CARD_VOLTAGE_A2_MASK (0x40000U) +#define SDIF_CTRL_CARD_VOLTAGE_A2_SHIFT (18U) +#define SDIF_CTRL_CARD_VOLTAGE_A2(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A2_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A2_MASK) +#define SDIF_CTRL_USE_INTERNAL_DMAC_MASK (0x2000000U) +#define SDIF_CTRL_USE_INTERNAL_DMAC_SHIFT (25U) +#define SDIF_CTRL_USE_INTERNAL_DMAC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_USE_INTERNAL_DMAC_SHIFT)) & SDIF_CTRL_USE_INTERNAL_DMAC_MASK) +/*! @} */ + +/*! @name PWREN - Power Enable register */ +/*! @{ */ +#define SDIF_PWREN_POWER_ENABLE0_MASK (0x1U) +#define SDIF_PWREN_POWER_ENABLE0_SHIFT (0U) +#define SDIF_PWREN_POWER_ENABLE0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_PWREN_POWER_ENABLE0_SHIFT)) & SDIF_PWREN_POWER_ENABLE0_MASK) +#define SDIF_PWREN_POWER_ENABLE1_MASK (0x2U) +#define SDIF_PWREN_POWER_ENABLE1_SHIFT (1U) +#define SDIF_PWREN_POWER_ENABLE1(x) (((uint32_t)(((uint32_t)(x)) << SDIF_PWREN_POWER_ENABLE1_SHIFT)) & SDIF_PWREN_POWER_ENABLE1_MASK) +/*! @} */ + +/*! @name CLKDIV - Clock Divider register */ +/*! @{ */ +#define SDIF_CLKDIV_CLK_DIVIDER0_MASK (0xFFU) +#define SDIF_CLKDIV_CLK_DIVIDER0_SHIFT (0U) +#define SDIF_CLKDIV_CLK_DIVIDER0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKDIV_CLK_DIVIDER0_SHIFT)) & SDIF_CLKDIV_CLK_DIVIDER0_MASK) +/*! @} */ + +/*! @name CLKENA - Clock Enable register */ +/*! @{ */ +#define SDIF_CLKENA_CCLK0_ENABLE_MASK (0x1U) +#define SDIF_CLKENA_CCLK0_ENABLE_SHIFT (0U) +#define SDIF_CLKENA_CCLK0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK0_ENABLE_SHIFT)) & SDIF_CLKENA_CCLK0_ENABLE_MASK) +#define SDIF_CLKENA_CCLK1_ENABLE_MASK (0x2U) +#define SDIF_CLKENA_CCLK1_ENABLE_SHIFT (1U) +#define SDIF_CLKENA_CCLK1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK1_ENABLE_SHIFT)) & SDIF_CLKENA_CCLK1_ENABLE_MASK) +#define SDIF_CLKENA_CCLK0_LOW_POWER_MASK (0x10000U) +#define SDIF_CLKENA_CCLK0_LOW_POWER_SHIFT (16U) +#define SDIF_CLKENA_CCLK0_LOW_POWER(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK0_LOW_POWER_SHIFT)) & SDIF_CLKENA_CCLK0_LOW_POWER_MASK) +#define SDIF_CLKENA_CCLK1_LOW_POWER_MASK (0x20000U) +#define SDIF_CLKENA_CCLK1_LOW_POWER_SHIFT (17U) +#define SDIF_CLKENA_CCLK1_LOW_POWER(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK1_LOW_POWER_SHIFT)) & SDIF_CLKENA_CCLK1_LOW_POWER_MASK) +/*! @} */ + +/*! @name TMOUT - Time-out register */ +/*! @{ */ +#define SDIF_TMOUT_RESPONSE_TIMEOUT_MASK (0xFFU) +#define SDIF_TMOUT_RESPONSE_TIMEOUT_SHIFT (0U) +#define SDIF_TMOUT_RESPONSE_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TMOUT_RESPONSE_TIMEOUT_SHIFT)) & SDIF_TMOUT_RESPONSE_TIMEOUT_MASK) +#define SDIF_TMOUT_DATA_TIMEOUT_MASK (0xFFFFFF00U) +#define SDIF_TMOUT_DATA_TIMEOUT_SHIFT (8U) +#define SDIF_TMOUT_DATA_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TMOUT_DATA_TIMEOUT_SHIFT)) & SDIF_TMOUT_DATA_TIMEOUT_MASK) +/*! @} */ + +/*! @name CTYPE - Card Type register */ +/*! @{ */ +#define SDIF_CTYPE_CARD0_WIDTH0_MASK (0x1U) +#define SDIF_CTYPE_CARD0_WIDTH0_SHIFT (0U) +#define SDIF_CTYPE_CARD0_WIDTH0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD0_WIDTH0_SHIFT)) & SDIF_CTYPE_CARD0_WIDTH0_MASK) +#define SDIF_CTYPE_CARD1_WIDTH0_MASK (0x2U) +#define SDIF_CTYPE_CARD1_WIDTH0_SHIFT (1U) +#define SDIF_CTYPE_CARD1_WIDTH0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD1_WIDTH0_SHIFT)) & SDIF_CTYPE_CARD1_WIDTH0_MASK) +#define SDIF_CTYPE_CARD0_WIDTH1_MASK (0x10000U) +#define SDIF_CTYPE_CARD0_WIDTH1_SHIFT (16U) +#define SDIF_CTYPE_CARD0_WIDTH1(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD0_WIDTH1_SHIFT)) & SDIF_CTYPE_CARD0_WIDTH1_MASK) +#define SDIF_CTYPE_CARD1_WIDTH1_MASK (0x20000U) +#define SDIF_CTYPE_CARD1_WIDTH1_SHIFT (17U) +#define SDIF_CTYPE_CARD1_WIDTH1(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD1_WIDTH1_SHIFT)) & SDIF_CTYPE_CARD1_WIDTH1_MASK) +/*! @} */ + +/*! @name BLKSIZ - Block Size register */ +/*! @{ */ +#define SDIF_BLKSIZ_BLOCK_SIZE_MASK (0xFFFFU) +#define SDIF_BLKSIZ_BLOCK_SIZE_SHIFT (0U) +#define SDIF_BLKSIZ_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BLKSIZ_BLOCK_SIZE_SHIFT)) & SDIF_BLKSIZ_BLOCK_SIZE_MASK) +/*! @} */ + +/*! @name BYTCNT - Byte Count register */ +/*! @{ */ +#define SDIF_BYTCNT_BYTE_COUNT_MASK (0xFFFFFFFFU) +#define SDIF_BYTCNT_BYTE_COUNT_SHIFT (0U) +#define SDIF_BYTCNT_BYTE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BYTCNT_BYTE_COUNT_SHIFT)) & SDIF_BYTCNT_BYTE_COUNT_MASK) +/*! @} */ + +/*! @name INTMASK - Interrupt Mask register */ +/*! @{ */ +#define SDIF_INTMASK_CDET_MASK (0x1U) +#define SDIF_INTMASK_CDET_SHIFT (0U) +#define SDIF_INTMASK_CDET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_CDET_SHIFT)) & SDIF_INTMASK_CDET_MASK) +#define SDIF_INTMASK_RE_MASK (0x2U) +#define SDIF_INTMASK_RE_SHIFT (1U) +#define SDIF_INTMASK_RE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RE_SHIFT)) & SDIF_INTMASK_RE_MASK) +#define SDIF_INTMASK_CDONE_MASK (0x4U) +#define SDIF_INTMASK_CDONE_SHIFT (2U) +#define SDIF_INTMASK_CDONE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_CDONE_SHIFT)) & SDIF_INTMASK_CDONE_MASK) +#define SDIF_INTMASK_DTO_MASK (0x8U) +#define SDIF_INTMASK_DTO_SHIFT (3U) +#define SDIF_INTMASK_DTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DTO_SHIFT)) & SDIF_INTMASK_DTO_MASK) +#define SDIF_INTMASK_TXDR_MASK (0x10U) +#define SDIF_INTMASK_TXDR_SHIFT (4U) +#define SDIF_INTMASK_TXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_TXDR_SHIFT)) & SDIF_INTMASK_TXDR_MASK) +#define SDIF_INTMASK_RXDR_MASK (0x20U) +#define SDIF_INTMASK_RXDR_SHIFT (5U) +#define SDIF_INTMASK_RXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RXDR_SHIFT)) & SDIF_INTMASK_RXDR_MASK) +#define SDIF_INTMASK_RCRC_MASK (0x40U) +#define SDIF_INTMASK_RCRC_SHIFT (6U) +#define SDIF_INTMASK_RCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RCRC_SHIFT)) & SDIF_INTMASK_RCRC_MASK) +#define SDIF_INTMASK_DCRC_MASK (0x80U) +#define SDIF_INTMASK_DCRC_SHIFT (7U) +#define SDIF_INTMASK_DCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DCRC_SHIFT)) & SDIF_INTMASK_DCRC_MASK) +#define SDIF_INTMASK_RTO_MASK (0x100U) +#define SDIF_INTMASK_RTO_SHIFT (8U) +#define SDIF_INTMASK_RTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RTO_SHIFT)) & SDIF_INTMASK_RTO_MASK) +#define SDIF_INTMASK_DRTO_MASK (0x200U) +#define SDIF_INTMASK_DRTO_SHIFT (9U) +#define SDIF_INTMASK_DRTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DRTO_SHIFT)) & SDIF_INTMASK_DRTO_MASK) +#define SDIF_INTMASK_HTO_MASK (0x400U) +#define SDIF_INTMASK_HTO_SHIFT (10U) +#define SDIF_INTMASK_HTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_HTO_SHIFT)) & SDIF_INTMASK_HTO_MASK) +#define SDIF_INTMASK_FRUN_MASK (0x800U) +#define SDIF_INTMASK_FRUN_SHIFT (11U) +#define SDIF_INTMASK_FRUN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_FRUN_SHIFT)) & SDIF_INTMASK_FRUN_MASK) +#define SDIF_INTMASK_HLE_MASK (0x1000U) +#define SDIF_INTMASK_HLE_SHIFT (12U) +#define SDIF_INTMASK_HLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_HLE_SHIFT)) & SDIF_INTMASK_HLE_MASK) +#define SDIF_INTMASK_SBE_MASK (0x2000U) +#define SDIF_INTMASK_SBE_SHIFT (13U) +#define SDIF_INTMASK_SBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_SBE_SHIFT)) & SDIF_INTMASK_SBE_MASK) +#define SDIF_INTMASK_ACD_MASK (0x4000U) +#define SDIF_INTMASK_ACD_SHIFT (14U) +#define SDIF_INTMASK_ACD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_ACD_SHIFT)) & SDIF_INTMASK_ACD_MASK) +#define SDIF_INTMASK_EBE_MASK (0x8000U) +#define SDIF_INTMASK_EBE_SHIFT (15U) +#define SDIF_INTMASK_EBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_EBE_SHIFT)) & SDIF_INTMASK_EBE_MASK) +#define SDIF_INTMASK_SDIO_INT_MASK_MASK (0x10000U) +#define SDIF_INTMASK_SDIO_INT_MASK_SHIFT (16U) +#define SDIF_INTMASK_SDIO_INT_MASK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_SDIO_INT_MASK_SHIFT)) & SDIF_INTMASK_SDIO_INT_MASK_MASK) +/*! @} */ + +/*! @name CMDARG - Command Argument register */ +/*! @{ */ +#define SDIF_CMDARG_CMD_ARG_MASK (0xFFFFFFFFU) +#define SDIF_CMDARG_CMD_ARG_SHIFT (0U) +#define SDIF_CMDARG_CMD_ARG(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMDARG_CMD_ARG_SHIFT)) & SDIF_CMDARG_CMD_ARG_MASK) +/*! @} */ + +/*! @name CMD - Command register */ +/*! @{ */ +#define SDIF_CMD_CMD_INDEX_MASK (0x3FU) +#define SDIF_CMD_CMD_INDEX_SHIFT (0U) +#define SDIF_CMD_CMD_INDEX(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CMD_INDEX_SHIFT)) & SDIF_CMD_CMD_INDEX_MASK) +#define SDIF_CMD_RESPONSE_EXPECT_MASK (0x40U) +#define SDIF_CMD_RESPONSE_EXPECT_SHIFT (6U) +#define SDIF_CMD_RESPONSE_EXPECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_RESPONSE_EXPECT_SHIFT)) & SDIF_CMD_RESPONSE_EXPECT_MASK) +#define SDIF_CMD_RESPONSE_LENGTH_MASK (0x80U) +#define SDIF_CMD_RESPONSE_LENGTH_SHIFT (7U) +#define SDIF_CMD_RESPONSE_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_RESPONSE_LENGTH_SHIFT)) & SDIF_CMD_RESPONSE_LENGTH_MASK) +#define SDIF_CMD_CHECK_RESPONSE_CRC_MASK (0x100U) +#define SDIF_CMD_CHECK_RESPONSE_CRC_SHIFT (8U) +#define SDIF_CMD_CHECK_RESPONSE_CRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CHECK_RESPONSE_CRC_SHIFT)) & SDIF_CMD_CHECK_RESPONSE_CRC_MASK) +#define SDIF_CMD_DATA_EXPECTED_MASK (0x200U) +#define SDIF_CMD_DATA_EXPECTED_SHIFT (9U) +#define SDIF_CMD_DATA_EXPECTED(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_DATA_EXPECTED_SHIFT)) & SDIF_CMD_DATA_EXPECTED_MASK) +#define SDIF_CMD_READ_WRITE_MASK (0x400U) +#define SDIF_CMD_READ_WRITE_SHIFT (10U) +#define SDIF_CMD_READ_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_READ_WRITE_SHIFT)) & SDIF_CMD_READ_WRITE_MASK) +#define SDIF_CMD_TRANSFER_MODE_MASK (0x800U) +#define SDIF_CMD_TRANSFER_MODE_SHIFT (11U) +#define SDIF_CMD_TRANSFER_MODE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_TRANSFER_MODE_SHIFT)) & SDIF_CMD_TRANSFER_MODE_MASK) +#define SDIF_CMD_SEND_AUTO_STOP_MASK (0x1000U) +#define SDIF_CMD_SEND_AUTO_STOP_SHIFT (12U) +#define SDIF_CMD_SEND_AUTO_STOP(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_SEND_AUTO_STOP_SHIFT)) & SDIF_CMD_SEND_AUTO_STOP_MASK) +#define SDIF_CMD_WAIT_PRVDATA_COMPLETE_MASK (0x2000U) +#define SDIF_CMD_WAIT_PRVDATA_COMPLETE_SHIFT (13U) +#define SDIF_CMD_WAIT_PRVDATA_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_WAIT_PRVDATA_COMPLETE_SHIFT)) & SDIF_CMD_WAIT_PRVDATA_COMPLETE_MASK) +#define SDIF_CMD_STOP_ABORT_CMD_MASK (0x4000U) +#define SDIF_CMD_STOP_ABORT_CMD_SHIFT (14U) +#define SDIF_CMD_STOP_ABORT_CMD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_STOP_ABORT_CMD_SHIFT)) & SDIF_CMD_STOP_ABORT_CMD_MASK) +#define SDIF_CMD_SEND_INITIALIZATION_MASK (0x8000U) +#define SDIF_CMD_SEND_INITIALIZATION_SHIFT (15U) +#define SDIF_CMD_SEND_INITIALIZATION(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_SEND_INITIALIZATION_SHIFT)) & SDIF_CMD_SEND_INITIALIZATION_MASK) +#define SDIF_CMD_CARD_NUMBER_MASK (0x1F0000U) +#define SDIF_CMD_CARD_NUMBER_SHIFT (16U) +/*! CARD_NUMBER - Specifies the card number of SDCARD for which the current Command is being executed + * 0b00000..Command will be execute on SDCARD 0 + * 0b00001..Command will be execute on SDCARD 1 + */ +#define SDIF_CMD_CARD_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CARD_NUMBER_SHIFT)) & SDIF_CMD_CARD_NUMBER_MASK) +#define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_MASK (0x200000U) +#define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_SHIFT (21U) +#define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_SHIFT)) & SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_MASK) +#define SDIF_CMD_READ_CEATA_DEVICE_MASK (0x400000U) +#define SDIF_CMD_READ_CEATA_DEVICE_SHIFT (22U) +#define SDIF_CMD_READ_CEATA_DEVICE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_READ_CEATA_DEVICE_SHIFT)) & SDIF_CMD_READ_CEATA_DEVICE_MASK) +#define SDIF_CMD_CCS_EXPECTED_MASK (0x800000U) +#define SDIF_CMD_CCS_EXPECTED_SHIFT (23U) +#define SDIF_CMD_CCS_EXPECTED(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CCS_EXPECTED_SHIFT)) & SDIF_CMD_CCS_EXPECTED_MASK) +#define SDIF_CMD_ENABLE_BOOT_MASK (0x1000000U) +#define SDIF_CMD_ENABLE_BOOT_SHIFT (24U) +#define SDIF_CMD_ENABLE_BOOT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_ENABLE_BOOT_SHIFT)) & SDIF_CMD_ENABLE_BOOT_MASK) +#define SDIF_CMD_EXPECT_BOOT_ACK_MASK (0x2000000U) +#define SDIF_CMD_EXPECT_BOOT_ACK_SHIFT (25U) +#define SDIF_CMD_EXPECT_BOOT_ACK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_EXPECT_BOOT_ACK_SHIFT)) & SDIF_CMD_EXPECT_BOOT_ACK_MASK) +#define SDIF_CMD_DISABLE_BOOT_MASK (0x4000000U) +#define SDIF_CMD_DISABLE_BOOT_SHIFT (26U) +#define SDIF_CMD_DISABLE_BOOT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_DISABLE_BOOT_SHIFT)) & SDIF_CMD_DISABLE_BOOT_MASK) +#define SDIF_CMD_BOOT_MODE_MASK (0x8000000U) +#define SDIF_CMD_BOOT_MODE_SHIFT (27U) +#define SDIF_CMD_BOOT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_BOOT_MODE_SHIFT)) & SDIF_CMD_BOOT_MODE_MASK) +#define SDIF_CMD_VOLT_SWITCH_MASK (0x10000000U) +#define SDIF_CMD_VOLT_SWITCH_SHIFT (28U) +#define SDIF_CMD_VOLT_SWITCH(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_VOLT_SWITCH_SHIFT)) & SDIF_CMD_VOLT_SWITCH_MASK) +#define SDIF_CMD_USE_HOLD_REG_MASK (0x20000000U) +#define SDIF_CMD_USE_HOLD_REG_SHIFT (29U) +#define SDIF_CMD_USE_HOLD_REG(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_USE_HOLD_REG_SHIFT)) & SDIF_CMD_USE_HOLD_REG_MASK) +#define SDIF_CMD_START_CMD_MASK (0x80000000U) +#define SDIF_CMD_START_CMD_SHIFT (31U) +#define SDIF_CMD_START_CMD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_START_CMD_SHIFT)) & SDIF_CMD_START_CMD_MASK) +/*! @} */ + +/*! @name RESP - Response register */ +/*! @{ */ +#define SDIF_RESP_RESPONSE_MASK (0xFFFFFFFFU) +#define SDIF_RESP_RESPONSE_SHIFT (0U) +#define SDIF_RESP_RESPONSE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RESP_RESPONSE_SHIFT)) & SDIF_RESP_RESPONSE_MASK) +/*! @} */ + +/* The count of SDIF_RESP */ +#define SDIF_RESP_COUNT (4U) + +/*! @name MINTSTS - Masked Interrupt Status register */ +/*! @{ */ +#define SDIF_MINTSTS_CDET_MASK (0x1U) +#define SDIF_MINTSTS_CDET_SHIFT (0U) +#define SDIF_MINTSTS_CDET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_CDET_SHIFT)) & SDIF_MINTSTS_CDET_MASK) +#define SDIF_MINTSTS_RE_MASK (0x2U) +#define SDIF_MINTSTS_RE_SHIFT (1U) +#define SDIF_MINTSTS_RE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RE_SHIFT)) & SDIF_MINTSTS_RE_MASK) +#define SDIF_MINTSTS_CDONE_MASK (0x4U) +#define SDIF_MINTSTS_CDONE_SHIFT (2U) +#define SDIF_MINTSTS_CDONE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_CDONE_SHIFT)) & SDIF_MINTSTS_CDONE_MASK) +#define SDIF_MINTSTS_DTO_MASK (0x8U) +#define SDIF_MINTSTS_DTO_SHIFT (3U) +#define SDIF_MINTSTS_DTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DTO_SHIFT)) & SDIF_MINTSTS_DTO_MASK) +#define SDIF_MINTSTS_TXDR_MASK (0x10U) +#define SDIF_MINTSTS_TXDR_SHIFT (4U) +#define SDIF_MINTSTS_TXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_TXDR_SHIFT)) & SDIF_MINTSTS_TXDR_MASK) +#define SDIF_MINTSTS_RXDR_MASK (0x20U) +#define SDIF_MINTSTS_RXDR_SHIFT (5U) +#define SDIF_MINTSTS_RXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RXDR_SHIFT)) & SDIF_MINTSTS_RXDR_MASK) +#define SDIF_MINTSTS_RCRC_MASK (0x40U) +#define SDIF_MINTSTS_RCRC_SHIFT (6U) +#define SDIF_MINTSTS_RCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RCRC_SHIFT)) & SDIF_MINTSTS_RCRC_MASK) +#define SDIF_MINTSTS_DCRC_MASK (0x80U) +#define SDIF_MINTSTS_DCRC_SHIFT (7U) +#define SDIF_MINTSTS_DCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DCRC_SHIFT)) & SDIF_MINTSTS_DCRC_MASK) +#define SDIF_MINTSTS_RTO_MASK (0x100U) +#define SDIF_MINTSTS_RTO_SHIFT (8U) +#define SDIF_MINTSTS_RTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RTO_SHIFT)) & SDIF_MINTSTS_RTO_MASK) +#define SDIF_MINTSTS_DRTO_MASK (0x200U) +#define SDIF_MINTSTS_DRTO_SHIFT (9U) +#define SDIF_MINTSTS_DRTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DRTO_SHIFT)) & SDIF_MINTSTS_DRTO_MASK) +#define SDIF_MINTSTS_HTO_MASK (0x400U) +#define SDIF_MINTSTS_HTO_SHIFT (10U) +#define SDIF_MINTSTS_HTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_HTO_SHIFT)) & SDIF_MINTSTS_HTO_MASK) +#define SDIF_MINTSTS_FRUN_MASK (0x800U) +#define SDIF_MINTSTS_FRUN_SHIFT (11U) +#define SDIF_MINTSTS_FRUN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_FRUN_SHIFT)) & SDIF_MINTSTS_FRUN_MASK) +#define SDIF_MINTSTS_HLE_MASK (0x1000U) +#define SDIF_MINTSTS_HLE_SHIFT (12U) +#define SDIF_MINTSTS_HLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_HLE_SHIFT)) & SDIF_MINTSTS_HLE_MASK) +#define SDIF_MINTSTS_SBE_MASK (0x2000U) +#define SDIF_MINTSTS_SBE_SHIFT (13U) +#define SDIF_MINTSTS_SBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_SBE_SHIFT)) & SDIF_MINTSTS_SBE_MASK) +#define SDIF_MINTSTS_ACD_MASK (0x4000U) +#define SDIF_MINTSTS_ACD_SHIFT (14U) +#define SDIF_MINTSTS_ACD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_ACD_SHIFT)) & SDIF_MINTSTS_ACD_MASK) +#define SDIF_MINTSTS_EBE_MASK (0x8000U) +#define SDIF_MINTSTS_EBE_SHIFT (15U) +#define SDIF_MINTSTS_EBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_EBE_SHIFT)) & SDIF_MINTSTS_EBE_MASK) +#define SDIF_MINTSTS_SDIO_INTERRUPT_MASK (0x10000U) +#define SDIF_MINTSTS_SDIO_INTERRUPT_SHIFT (16U) +#define SDIF_MINTSTS_SDIO_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_SDIO_INTERRUPT_SHIFT)) & SDIF_MINTSTS_SDIO_INTERRUPT_MASK) +/*! @} */ + +/*! @name RINTSTS - Raw Interrupt Status register */ +/*! @{ */ +#define SDIF_RINTSTS_CDET_MASK (0x1U) +#define SDIF_RINTSTS_CDET_SHIFT (0U) +#define SDIF_RINTSTS_CDET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_CDET_SHIFT)) & SDIF_RINTSTS_CDET_MASK) +#define SDIF_RINTSTS_RE_MASK (0x2U) +#define SDIF_RINTSTS_RE_SHIFT (1U) +#define SDIF_RINTSTS_RE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RE_SHIFT)) & SDIF_RINTSTS_RE_MASK) +#define SDIF_RINTSTS_CDONE_MASK (0x4U) +#define SDIF_RINTSTS_CDONE_SHIFT (2U) +#define SDIF_RINTSTS_CDONE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_CDONE_SHIFT)) & SDIF_RINTSTS_CDONE_MASK) +#define SDIF_RINTSTS_DTO_MASK (0x8U) +#define SDIF_RINTSTS_DTO_SHIFT (3U) +#define SDIF_RINTSTS_DTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DTO_SHIFT)) & SDIF_RINTSTS_DTO_MASK) +#define SDIF_RINTSTS_TXDR_MASK (0x10U) +#define SDIF_RINTSTS_TXDR_SHIFT (4U) +#define SDIF_RINTSTS_TXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_TXDR_SHIFT)) & SDIF_RINTSTS_TXDR_MASK) +#define SDIF_RINTSTS_RXDR_MASK (0x20U) +#define SDIF_RINTSTS_RXDR_SHIFT (5U) +#define SDIF_RINTSTS_RXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RXDR_SHIFT)) & SDIF_RINTSTS_RXDR_MASK) +#define SDIF_RINTSTS_RCRC_MASK (0x40U) +#define SDIF_RINTSTS_RCRC_SHIFT (6U) +#define SDIF_RINTSTS_RCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RCRC_SHIFT)) & SDIF_RINTSTS_RCRC_MASK) +#define SDIF_RINTSTS_DCRC_MASK (0x80U) +#define SDIF_RINTSTS_DCRC_SHIFT (7U) +#define SDIF_RINTSTS_DCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DCRC_SHIFT)) & SDIF_RINTSTS_DCRC_MASK) +#define SDIF_RINTSTS_RTO_BAR_MASK (0x100U) +#define SDIF_RINTSTS_RTO_BAR_SHIFT (8U) +#define SDIF_RINTSTS_RTO_BAR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RTO_BAR_SHIFT)) & SDIF_RINTSTS_RTO_BAR_MASK) +#define SDIF_RINTSTS_DRTO_BDS_MASK (0x200U) +#define SDIF_RINTSTS_DRTO_BDS_SHIFT (9U) +#define SDIF_RINTSTS_DRTO_BDS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DRTO_BDS_SHIFT)) & SDIF_RINTSTS_DRTO_BDS_MASK) +#define SDIF_RINTSTS_HTO_MASK (0x400U) +#define SDIF_RINTSTS_HTO_SHIFT (10U) +#define SDIF_RINTSTS_HTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_HTO_SHIFT)) & SDIF_RINTSTS_HTO_MASK) +#define SDIF_RINTSTS_FRUN_MASK (0x800U) +#define SDIF_RINTSTS_FRUN_SHIFT (11U) +#define SDIF_RINTSTS_FRUN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_FRUN_SHIFT)) & SDIF_RINTSTS_FRUN_MASK) +#define SDIF_RINTSTS_HLE_MASK (0x1000U) +#define SDIF_RINTSTS_HLE_SHIFT (12U) +#define SDIF_RINTSTS_HLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_HLE_SHIFT)) & SDIF_RINTSTS_HLE_MASK) +#define SDIF_RINTSTS_SBE_MASK (0x2000U) +#define SDIF_RINTSTS_SBE_SHIFT (13U) +#define SDIF_RINTSTS_SBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_SBE_SHIFT)) & SDIF_RINTSTS_SBE_MASK) +#define SDIF_RINTSTS_ACD_MASK (0x4000U) +#define SDIF_RINTSTS_ACD_SHIFT (14U) +#define SDIF_RINTSTS_ACD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_ACD_SHIFT)) & SDIF_RINTSTS_ACD_MASK) +#define SDIF_RINTSTS_EBE_MASK (0x8000U) +#define SDIF_RINTSTS_EBE_SHIFT (15U) +#define SDIF_RINTSTS_EBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_EBE_SHIFT)) & SDIF_RINTSTS_EBE_MASK) +#define SDIF_RINTSTS_SDIO_INTERRUPT_MASK (0x10000U) +#define SDIF_RINTSTS_SDIO_INTERRUPT_SHIFT (16U) +#define SDIF_RINTSTS_SDIO_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_SDIO_INTERRUPT_SHIFT)) & SDIF_RINTSTS_SDIO_INTERRUPT_MASK) +/*! @} */ + +/*! @name STATUS - Status register */ +/*! @{ */ +#define SDIF_STATUS_FIFO_RX_WATERMARK_MASK (0x1U) +#define SDIF_STATUS_FIFO_RX_WATERMARK_SHIFT (0U) +#define SDIF_STATUS_FIFO_RX_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_RX_WATERMARK_SHIFT)) & SDIF_STATUS_FIFO_RX_WATERMARK_MASK) +#define SDIF_STATUS_FIFO_TX_WATERMARK_MASK (0x2U) +#define SDIF_STATUS_FIFO_TX_WATERMARK_SHIFT (1U) +#define SDIF_STATUS_FIFO_TX_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_TX_WATERMARK_SHIFT)) & SDIF_STATUS_FIFO_TX_WATERMARK_MASK) +#define SDIF_STATUS_FIFO_EMPTY_MASK (0x4U) +#define SDIF_STATUS_FIFO_EMPTY_SHIFT (2U) +#define SDIF_STATUS_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_EMPTY_SHIFT)) & SDIF_STATUS_FIFO_EMPTY_MASK) +#define SDIF_STATUS_FIFO_FULL_MASK (0x8U) +#define SDIF_STATUS_FIFO_FULL_SHIFT (3U) +#define SDIF_STATUS_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_FULL_SHIFT)) & SDIF_STATUS_FIFO_FULL_MASK) +#define SDIF_STATUS_CMDFSMSTATES_MASK (0xF0U) +#define SDIF_STATUS_CMDFSMSTATES_SHIFT (4U) +#define SDIF_STATUS_CMDFSMSTATES(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_CMDFSMSTATES_SHIFT)) & SDIF_STATUS_CMDFSMSTATES_MASK) +#define SDIF_STATUS_DATA_3_STATUS_MASK (0x100U) +#define SDIF_STATUS_DATA_3_STATUS_SHIFT (8U) +#define SDIF_STATUS_DATA_3_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_3_STATUS_SHIFT)) & SDIF_STATUS_DATA_3_STATUS_MASK) +#define SDIF_STATUS_DATA_BUSY_MASK (0x200U) +#define SDIF_STATUS_DATA_BUSY_SHIFT (9U) +#define SDIF_STATUS_DATA_BUSY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_BUSY_SHIFT)) & SDIF_STATUS_DATA_BUSY_MASK) +#define SDIF_STATUS_DATA_STATE_MC_BUSY_MASK (0x400U) +#define SDIF_STATUS_DATA_STATE_MC_BUSY_SHIFT (10U) +#define SDIF_STATUS_DATA_STATE_MC_BUSY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_STATE_MC_BUSY_SHIFT)) & SDIF_STATUS_DATA_STATE_MC_BUSY_MASK) +#define SDIF_STATUS_RESPONSE_INDEX_MASK (0x1F800U) +#define SDIF_STATUS_RESPONSE_INDEX_SHIFT (11U) +#define SDIF_STATUS_RESPONSE_INDEX(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_RESPONSE_INDEX_SHIFT)) & SDIF_STATUS_RESPONSE_INDEX_MASK) +#define SDIF_STATUS_FIFO_COUNT_MASK (0x3FFE0000U) +#define SDIF_STATUS_FIFO_COUNT_SHIFT (17U) +#define SDIF_STATUS_FIFO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_COUNT_SHIFT)) & SDIF_STATUS_FIFO_COUNT_MASK) +#define SDIF_STATUS_DMA_ACK_MASK (0x40000000U) +#define SDIF_STATUS_DMA_ACK_SHIFT (30U) +#define SDIF_STATUS_DMA_ACK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DMA_ACK_SHIFT)) & SDIF_STATUS_DMA_ACK_MASK) +#define SDIF_STATUS_DMA_REQ_MASK (0x80000000U) +#define SDIF_STATUS_DMA_REQ_SHIFT (31U) +#define SDIF_STATUS_DMA_REQ(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DMA_REQ_SHIFT)) & SDIF_STATUS_DMA_REQ_MASK) +/*! @} */ + +/*! @name FIFOTH - FIFO Threshold Watermark register */ +/*! @{ */ +#define SDIF_FIFOTH_TX_WMARK_MASK (0xFFFU) +#define SDIF_FIFOTH_TX_WMARK_SHIFT (0U) +#define SDIF_FIFOTH_TX_WMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_TX_WMARK_SHIFT)) & SDIF_FIFOTH_TX_WMARK_MASK) +#define SDIF_FIFOTH_RX_WMARK_MASK (0xFFF0000U) +#define SDIF_FIFOTH_RX_WMARK_SHIFT (16U) +#define SDIF_FIFOTH_RX_WMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_RX_WMARK_SHIFT)) & SDIF_FIFOTH_RX_WMARK_MASK) +#define SDIF_FIFOTH_DMA_MTS_MASK (0x70000000U) +#define SDIF_FIFOTH_DMA_MTS_SHIFT (28U) +#define SDIF_FIFOTH_DMA_MTS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_DMA_MTS_SHIFT)) & SDIF_FIFOTH_DMA_MTS_MASK) +/*! @} */ + +/*! @name CDETECT - Card Detect register */ +/*! @{ */ +#define SDIF_CDETECT_CARD0_DETECT_MASK (0x1U) +#define SDIF_CDETECT_CARD0_DETECT_SHIFT (0U) +#define SDIF_CDETECT_CARD0_DETECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CDETECT_CARD0_DETECT_SHIFT)) & SDIF_CDETECT_CARD0_DETECT_MASK) +#define SDIF_CDETECT_CARD1_DETECT_MASK (0x2U) +#define SDIF_CDETECT_CARD1_DETECT_SHIFT (1U) +#define SDIF_CDETECT_CARD1_DETECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CDETECT_CARD1_DETECT_SHIFT)) & SDIF_CDETECT_CARD1_DETECT_MASK) +/*! @} */ + +/*! @name WRTPRT - Write Protect register */ +/*! @{ */ +#define SDIF_WRTPRT_WRITE_PROTECT_MASK (0x1U) +#define SDIF_WRTPRT_WRITE_PROTECT_SHIFT (0U) +#define SDIF_WRTPRT_WRITE_PROTECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_WRTPRT_WRITE_PROTECT_SHIFT)) & SDIF_WRTPRT_WRITE_PROTECT_MASK) +/*! @} */ + +/*! @name TCBCNT - Transferred CIU Card Byte Count register */ +/*! @{ */ +#define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_MASK (0xFFFFFFFFU) +#define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_SHIFT (0U) +#define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_SHIFT)) & SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_MASK) +/*! @} */ + +/*! @name TBBCNT - Transferred Host to BIU-FIFO Byte Count register */ +/*! @{ */ +#define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_MASK (0xFFFFFFFFU) +#define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_SHIFT (0U) +#define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_SHIFT)) & SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_MASK) +/*! @} */ + +/*! @name DEBNCE - Debounce Count register */ +/*! @{ */ +#define SDIF_DEBNCE_DEBOUNCE_COUNT_MASK (0xFFFFFFU) +#define SDIF_DEBNCE_DEBOUNCE_COUNT_SHIFT (0U) +#define SDIF_DEBNCE_DEBOUNCE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_DEBNCE_DEBOUNCE_COUNT_SHIFT)) & SDIF_DEBNCE_DEBOUNCE_COUNT_MASK) +/*! @} */ + +/*! @name RST_N - Hardware Reset */ +/*! @{ */ +#define SDIF_RST_N_CARD_RESET_MASK (0x1U) +#define SDIF_RST_N_CARD_RESET_SHIFT (0U) +#define SDIF_RST_N_CARD_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RST_N_CARD_RESET_SHIFT)) & SDIF_RST_N_CARD_RESET_MASK) +/*! @} */ + +/*! @name BMOD - Bus Mode register */ +/*! @{ */ +#define SDIF_BMOD_SWR_MASK (0x1U) +#define SDIF_BMOD_SWR_SHIFT (0U) +#define SDIF_BMOD_SWR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_SWR_SHIFT)) & SDIF_BMOD_SWR_MASK) +#define SDIF_BMOD_FB_MASK (0x2U) +#define SDIF_BMOD_FB_SHIFT (1U) +#define SDIF_BMOD_FB(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_FB_SHIFT)) & SDIF_BMOD_FB_MASK) +#define SDIF_BMOD_DSL_MASK (0x7CU) +#define SDIF_BMOD_DSL_SHIFT (2U) +#define SDIF_BMOD_DSL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_DSL_SHIFT)) & SDIF_BMOD_DSL_MASK) +#define SDIF_BMOD_DE_MASK (0x80U) +#define SDIF_BMOD_DE_SHIFT (7U) +#define SDIF_BMOD_DE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_DE_SHIFT)) & SDIF_BMOD_DE_MASK) +#define SDIF_BMOD_PBL_MASK (0x700U) +#define SDIF_BMOD_PBL_SHIFT (8U) +#define SDIF_BMOD_PBL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_PBL_SHIFT)) & SDIF_BMOD_PBL_MASK) +/*! @} */ + +/*! @name PLDMND - Poll Demand register */ +/*! @{ */ +#define SDIF_PLDMND_PD_MASK (0xFFFFFFFFU) +#define SDIF_PLDMND_PD_SHIFT (0U) +#define SDIF_PLDMND_PD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_PLDMND_PD_SHIFT)) & SDIF_PLDMND_PD_MASK) +/*! @} */ + +/*! @name DBADDR - Descriptor List Base Address register */ +/*! @{ */ +#define SDIF_DBADDR_SDL_MASK (0xFFFFFFFFU) +#define SDIF_DBADDR_SDL_SHIFT (0U) +#define SDIF_DBADDR_SDL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_DBADDR_SDL_SHIFT)) & SDIF_DBADDR_SDL_MASK) +/*! @} */ + +/*! @name IDSTS - Internal DMAC Status register */ +/*! @{ */ +#define SDIF_IDSTS_TI_MASK (0x1U) +#define SDIF_IDSTS_TI_SHIFT (0U) +#define SDIF_IDSTS_TI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_TI_SHIFT)) & SDIF_IDSTS_TI_MASK) +#define SDIF_IDSTS_RI_MASK (0x2U) +#define SDIF_IDSTS_RI_SHIFT (1U) +#define SDIF_IDSTS_RI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_RI_SHIFT)) & SDIF_IDSTS_RI_MASK) +#define SDIF_IDSTS_FBE_MASK (0x4U) +#define SDIF_IDSTS_FBE_SHIFT (2U) +#define SDIF_IDSTS_FBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_FBE_SHIFT)) & SDIF_IDSTS_FBE_MASK) +#define SDIF_IDSTS_DU_MASK (0x10U) +#define SDIF_IDSTS_DU_SHIFT (4U) +#define SDIF_IDSTS_DU(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_DU_SHIFT)) & SDIF_IDSTS_DU_MASK) +#define SDIF_IDSTS_CES_MASK (0x20U) +#define SDIF_IDSTS_CES_SHIFT (5U) +#define SDIF_IDSTS_CES(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_CES_SHIFT)) & SDIF_IDSTS_CES_MASK) +#define SDIF_IDSTS_NIS_MASK (0x100U) +#define SDIF_IDSTS_NIS_SHIFT (8U) +#define SDIF_IDSTS_NIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_NIS_SHIFT)) & SDIF_IDSTS_NIS_MASK) +#define SDIF_IDSTS_AIS_MASK (0x200U) +#define SDIF_IDSTS_AIS_SHIFT (9U) +#define SDIF_IDSTS_AIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_AIS_SHIFT)) & SDIF_IDSTS_AIS_MASK) +#define SDIF_IDSTS_EB_MASK (0x1C00U) +#define SDIF_IDSTS_EB_SHIFT (10U) +#define SDIF_IDSTS_EB(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_EB_SHIFT)) & SDIF_IDSTS_EB_MASK) +#define SDIF_IDSTS_FSM_MASK (0x1E000U) +#define SDIF_IDSTS_FSM_SHIFT (13U) +#define SDIF_IDSTS_FSM(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_FSM_SHIFT)) & SDIF_IDSTS_FSM_MASK) +/*! @} */ + +/*! @name IDINTEN - Internal DMAC Interrupt Enable register */ +/*! @{ */ +#define SDIF_IDINTEN_TI_MASK (0x1U) +#define SDIF_IDINTEN_TI_SHIFT (0U) +#define SDIF_IDINTEN_TI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_TI_SHIFT)) & SDIF_IDINTEN_TI_MASK) +#define SDIF_IDINTEN_RI_MASK (0x2U) +#define SDIF_IDINTEN_RI_SHIFT (1U) +#define SDIF_IDINTEN_RI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_RI_SHIFT)) & SDIF_IDINTEN_RI_MASK) +#define SDIF_IDINTEN_FBE_MASK (0x4U) +#define SDIF_IDINTEN_FBE_SHIFT (2U) +#define SDIF_IDINTEN_FBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_FBE_SHIFT)) & SDIF_IDINTEN_FBE_MASK) +#define SDIF_IDINTEN_DU_MASK (0x10U) +#define SDIF_IDINTEN_DU_SHIFT (4U) +#define SDIF_IDINTEN_DU(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_DU_SHIFT)) & SDIF_IDINTEN_DU_MASK) +#define SDIF_IDINTEN_CES_MASK (0x20U) +#define SDIF_IDINTEN_CES_SHIFT (5U) +#define SDIF_IDINTEN_CES(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_CES_SHIFT)) & SDIF_IDINTEN_CES_MASK) +#define SDIF_IDINTEN_NIS_MASK (0x100U) +#define SDIF_IDINTEN_NIS_SHIFT (8U) +#define SDIF_IDINTEN_NIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_NIS_SHIFT)) & SDIF_IDINTEN_NIS_MASK) +#define SDIF_IDINTEN_AIS_MASK (0x200U) +#define SDIF_IDINTEN_AIS_SHIFT (9U) +#define SDIF_IDINTEN_AIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_AIS_SHIFT)) & SDIF_IDINTEN_AIS_MASK) +/*! @} */ + +/*! @name DSCADDR - Current Host Descriptor Address register */ +/*! @{ */ +#define SDIF_DSCADDR_HDA_MASK (0xFFFFFFFFU) +#define SDIF_DSCADDR_HDA_SHIFT (0U) +#define SDIF_DSCADDR_HDA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_DSCADDR_HDA_SHIFT)) & SDIF_DSCADDR_HDA_MASK) +/*! @} */ + +/*! @name BUFADDR - Current Buffer Descriptor Address register */ +/*! @{ */ +#define SDIF_BUFADDR_HBA_MASK (0xFFFFFFFFU) +#define SDIF_BUFADDR_HBA_SHIFT (0U) +#define SDIF_BUFADDR_HBA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BUFADDR_HBA_SHIFT)) & SDIF_BUFADDR_HBA_MASK) +/*! @} */ + +/*! @name CARDTHRCTL - Card Threshold Control */ +/*! @{ */ +#define SDIF_CARDTHRCTL_CARDRDTHREN_MASK (0x1U) +#define SDIF_CARDTHRCTL_CARDRDTHREN_SHIFT (0U) +#define SDIF_CARDTHRCTL_CARDRDTHREN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_CARDRDTHREN_SHIFT)) & SDIF_CARDTHRCTL_CARDRDTHREN_MASK) +#define SDIF_CARDTHRCTL_BSYCLRINTEN_MASK (0x2U) +#define SDIF_CARDTHRCTL_BSYCLRINTEN_SHIFT (1U) +#define SDIF_CARDTHRCTL_BSYCLRINTEN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_BSYCLRINTEN_SHIFT)) & SDIF_CARDTHRCTL_BSYCLRINTEN_MASK) +#define SDIF_CARDTHRCTL_CARDTHRESHOLD_MASK (0xFF0000U) +#define SDIF_CARDTHRCTL_CARDTHRESHOLD_SHIFT (16U) +#define SDIF_CARDTHRCTL_CARDTHRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_CARDTHRESHOLD_SHIFT)) & SDIF_CARDTHRCTL_CARDTHRESHOLD_MASK) +/*! @} */ + +/*! @name BACKENDPWR - Power control */ +/*! @{ */ +#define SDIF_BACKENDPWR_BACKENDPWR_MASK (0x1U) +#define SDIF_BACKENDPWR_BACKENDPWR_SHIFT (0U) +#define SDIF_BACKENDPWR_BACKENDPWR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BACKENDPWR_BACKENDPWR_SHIFT)) & SDIF_BACKENDPWR_BACKENDPWR_MASK) +/*! @} */ + +/*! @name FIFO - SDIF FIFO */ +/*! @{ */ +#define SDIF_FIFO_DATA_MASK (0xFFFFFFFFU) +#define SDIF_FIFO_DATA_SHIFT (0U) +#define SDIF_FIFO_DATA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFO_DATA_SHIFT)) & SDIF_FIFO_DATA_MASK) +/*! @} */ + +/* The count of SDIF_FIFO */ +#define SDIF_FIFO_COUNT (64U) + + +/*! + * @} + */ /* end of group SDIF_Register_Masks */ + + +/* SDIF - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral SDIF base address */ + #define SDIF_BASE (0x5009B000u) + /** Peripheral SDIF base address */ + #define SDIF_BASE_NS (0x4009B000u) + /** Peripheral SDIF base pointer */ + #define SDIF ((SDIF_Type *)SDIF_BASE) + /** Peripheral SDIF base pointer */ + #define SDIF_NS ((SDIF_Type *)SDIF_BASE_NS) + /** Array initializer of SDIF peripheral base addresses */ + #define SDIF_BASE_ADDRS { SDIF_BASE } + /** Array initializer of SDIF peripheral base pointers */ + #define SDIF_BASE_PTRS { SDIF } + /** Array initializer of SDIF peripheral base addresses */ + #define SDIF_BASE_ADDRS_NS { SDIF_BASE_NS } + /** Array initializer of SDIF peripheral base pointers */ + #define SDIF_BASE_PTRS_NS { SDIF_NS } +#else + /** Peripheral SDIF base address */ + #define SDIF_BASE (0x4009B000u) + /** Peripheral SDIF base pointer */ + #define SDIF ((SDIF_Type *)SDIF_BASE) + /** Array initializer of SDIF peripheral base addresses */ + #define SDIF_BASE_ADDRS { SDIF_BASE } + /** Array initializer of SDIF peripheral base pointers */ + #define SDIF_BASE_PTRS { SDIF } +#endif +/** Interrupt vectors for the SDIF peripheral type */ +#define SDIF_IRQS { SDIO_IRQn } + +/*! + * @} + */ /* end of group SDIF_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SPI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer + * @{ + */ + +/** SPI - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[1024]; + __IO uint32_t CFG; /**< SPI Configuration register, offset: 0x400 */ + __IO uint32_t DLY; /**< SPI Delay register, offset: 0x404 */ + __IO uint32_t STAT; /**< SPI Status. Some status flags can be cleared by writing a 1 to that bit position., offset: 0x408 */ + __IO uint32_t INTENSET; /**< SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set., offset: 0x40C */ + __O uint32_t INTENCLR; /**< SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared., offset: 0x410 */ + uint8_t RESERVED_1[16]; + __IO uint32_t DIV; /**< SPI clock Divider, offset: 0x424 */ + __I uint32_t INTSTAT; /**< SPI Interrupt Status, offset: 0x428 */ + uint8_t RESERVED_2[2516]; + __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */ + __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ + __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */ + uint8_t RESERVED_3[4]; + __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */ + __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */ + __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */ + uint8_t RESERVED_4[4]; + __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ + uint8_t RESERVED_5[12]; + __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */ + uint8_t RESERVED_6[12]; + __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */ + uint8_t RESERVED_7[440]; + __I uint32_t ID; /**< Peripheral identification register., offset: 0xFFC */ +} SPI_Type; + +/* ---------------------------------------------------------------------------- + -- SPI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPI_Register_Masks SPI Register Masks + * @{ + */ + +/*! @name CFG - SPI Configuration register */ +/*! @{ */ +#define SPI_CFG_ENABLE_MASK (0x1U) +#define SPI_CFG_ENABLE_SHIFT (0U) +/*! ENABLE - SPI enable. + * 0b0..Disabled. The SPI is disabled and the internal state machine and counters are reset. + * 0b1..Enabled. The SPI is enabled for operation. + */ +#define SPI_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_ENABLE_SHIFT)) & SPI_CFG_ENABLE_MASK) +#define SPI_CFG_MASTER_MASK (0x4U) +#define SPI_CFG_MASTER_SHIFT (2U) +/*! MASTER - Master mode select. + * 0b0..Slave mode. The SPI will operate in slave mode. SCK, MOSI, and the SSEL signals are inputs, MISO is an output. + * 0b1..Master mode. The SPI will operate in master mode. SCK, MOSI, and the SSEL signals are outputs, MISO is an input. + */ +#define SPI_CFG_MASTER(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_MASTER_SHIFT)) & SPI_CFG_MASTER_MASK) +#define SPI_CFG_LSBF_MASK (0x8U) +#define SPI_CFG_LSBF_SHIFT (3U) +/*! LSBF - LSB First mode enable. + * 0b0..Standard. Data is transmitted and received in standard MSB first order. + * 0b1..Reverse. Data is transmitted and received in reverse order (LSB first). + */ +#define SPI_CFG_LSBF(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LSBF_SHIFT)) & SPI_CFG_LSBF_MASK) +#define SPI_CFG_CPHA_MASK (0x10U) +#define SPI_CFG_CPHA_SHIFT (4U) +/*! CPHA - Clock Phase select. + * 0b0..Change. The SPI captures serial data on the first clock transition of the transfer (when the clock + * changes away from the rest state). Data is changed on the following edge. + * 0b1..Capture. The SPI changes serial data on the first clock transition of the transfer (when the clock + * changes away from the rest state). Data is captured on the following edge. + */ +#define SPI_CFG_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPHA_SHIFT)) & SPI_CFG_CPHA_MASK) +#define SPI_CFG_CPOL_MASK (0x20U) +#define SPI_CFG_CPOL_SHIFT (5U) +/*! CPOL - Clock Polarity select. + * 0b0..Low. The rest state of the clock (between transfers) is low. + * 0b1..High. The rest state of the clock (between transfers) is high. + */ +#define SPI_CFG_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPOL_SHIFT)) & SPI_CFG_CPOL_MASK) +#define SPI_CFG_LOOP_MASK (0x80U) +#define SPI_CFG_LOOP_SHIFT (7U) +/*! LOOP - Loopback mode enable. Loopback mode applies only to Master mode, and connects transmit + * and receive data connected together to allow simple software testing. + * 0b0..Disabled. + * 0b1..Enabled. + */ +#define SPI_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LOOP_SHIFT)) & SPI_CFG_LOOP_MASK) +#define SPI_CFG_SPOL0_MASK (0x100U) +#define SPI_CFG_SPOL0_SHIFT (8U) +/*! SPOL0 - SSEL0 Polarity select. + * 0b0..Low. The SSEL0 pin is active low. + * 0b1..High. The SSEL0 pin is active high. + */ +#define SPI_CFG_SPOL0(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL0_SHIFT)) & SPI_CFG_SPOL0_MASK) +#define SPI_CFG_SPOL1_MASK (0x200U) +#define SPI_CFG_SPOL1_SHIFT (9U) +/*! SPOL1 - SSEL1 Polarity select. + * 0b0..Low. The SSEL1 pin is active low. + * 0b1..High. The SSEL1 pin is active high. + */ +#define SPI_CFG_SPOL1(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL1_SHIFT)) & SPI_CFG_SPOL1_MASK) +#define SPI_CFG_SPOL2_MASK (0x400U) +#define SPI_CFG_SPOL2_SHIFT (10U) +/*! SPOL2 - SSEL2 Polarity select. + * 0b0..Low. The SSEL2 pin is active low. + * 0b1..High. The SSEL2 pin is active high. + */ +#define SPI_CFG_SPOL2(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL2_SHIFT)) & SPI_CFG_SPOL2_MASK) +#define SPI_CFG_SPOL3_MASK (0x800U) +#define SPI_CFG_SPOL3_SHIFT (11U) +/*! SPOL3 - SSEL3 Polarity select. + * 0b0..Low. The SSEL3 pin is active low. + * 0b1..High. The SSEL3 pin is active high. + */ +#define SPI_CFG_SPOL3(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL3_SHIFT)) & SPI_CFG_SPOL3_MASK) +/*! @} */ + +/*! @name DLY - SPI Delay register */ +/*! @{ */ +#define SPI_DLY_PRE_DELAY_MASK (0xFU) +#define SPI_DLY_PRE_DELAY_SHIFT (0U) +#define SPI_DLY_PRE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_PRE_DELAY_SHIFT)) & SPI_DLY_PRE_DELAY_MASK) +#define SPI_DLY_POST_DELAY_MASK (0xF0U) +#define SPI_DLY_POST_DELAY_SHIFT (4U) +#define SPI_DLY_POST_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_POST_DELAY_SHIFT)) & SPI_DLY_POST_DELAY_MASK) +#define SPI_DLY_FRAME_DELAY_MASK (0xF00U) +#define SPI_DLY_FRAME_DELAY_SHIFT (8U) +#define SPI_DLY_FRAME_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_FRAME_DELAY_SHIFT)) & SPI_DLY_FRAME_DELAY_MASK) +#define SPI_DLY_TRANSFER_DELAY_MASK (0xF000U) +#define SPI_DLY_TRANSFER_DELAY_SHIFT (12U) +#define SPI_DLY_TRANSFER_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_TRANSFER_DELAY_SHIFT)) & SPI_DLY_TRANSFER_DELAY_MASK) +/*! @} */ + +/*! @name STAT - SPI Status. Some status flags can be cleared by writing a 1 to that bit position. */ +/*! @{ */ +#define SPI_STAT_SSA_MASK (0x10U) +#define SPI_STAT_SSA_SHIFT (4U) +#define SPI_STAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSA_SHIFT)) & SPI_STAT_SSA_MASK) +#define SPI_STAT_SSD_MASK (0x20U) +#define SPI_STAT_SSD_SHIFT (5U) +#define SPI_STAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSD_SHIFT)) & SPI_STAT_SSD_MASK) +#define SPI_STAT_STALLED_MASK (0x40U) +#define SPI_STAT_STALLED_SHIFT (6U) +#define SPI_STAT_STALLED(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_STALLED_SHIFT)) & SPI_STAT_STALLED_MASK) +#define SPI_STAT_ENDTRANSFER_MASK (0x80U) +#define SPI_STAT_ENDTRANSFER_SHIFT (7U) +#define SPI_STAT_ENDTRANSFER(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_ENDTRANSFER_SHIFT)) & SPI_STAT_ENDTRANSFER_MASK) +#define SPI_STAT_MSTIDLE_MASK (0x100U) +#define SPI_STAT_MSTIDLE_SHIFT (8U) +#define SPI_STAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_MSTIDLE_SHIFT)) & SPI_STAT_MSTIDLE_MASK) +/*! @} */ + +/*! @name INTENSET - SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */ +/*! @{ */ +#define SPI_INTENSET_SSAEN_MASK (0x10U) +#define SPI_INTENSET_SSAEN_SHIFT (4U) +/*! SSAEN - Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted. + * 0b0..Disabled. No interrupt will be generated when any Slave Select transitions from deasserted to asserted. + * 0b1..Enabled. An interrupt will be generated when any Slave Select transitions from deasserted to asserted. + */ +#define SPI_INTENSET_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSAEN_SHIFT)) & SPI_INTENSET_SSAEN_MASK) +#define SPI_INTENSET_SSDEN_MASK (0x20U) +#define SPI_INTENSET_SSDEN_SHIFT (5U) +/*! SSDEN - Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted. + * 0b0..Disabled. No interrupt will be generated when all asserted Slave Selects transition to deasserted. + * 0b1..Enabled. An interrupt will be generated when all asserted Slave Selects transition to deasserted. + */ +#define SPI_INTENSET_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSDEN_SHIFT)) & SPI_INTENSET_SSDEN_MASK) +#define SPI_INTENSET_MSTIDLEEN_MASK (0x100U) +#define SPI_INTENSET_MSTIDLEEN_SHIFT (8U) +/*! MSTIDLEEN - Master idle interrupt enable. + * 0b0..No interrupt will be generated when the SPI master function is idle. + * 0b1..An interrupt will be generated when the SPI master function is fully idle. + */ +#define SPI_INTENSET_MSTIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_MSTIDLEEN_SHIFT)) & SPI_INTENSET_MSTIDLEEN_MASK) +/*! @} */ + +/*! @name INTENCLR - SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared. */ +/*! @{ */ +#define SPI_INTENCLR_SSAEN_MASK (0x10U) +#define SPI_INTENCLR_SSAEN_SHIFT (4U) +#define SPI_INTENCLR_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSAEN_SHIFT)) & SPI_INTENCLR_SSAEN_MASK) +#define SPI_INTENCLR_SSDEN_MASK (0x20U) +#define SPI_INTENCLR_SSDEN_SHIFT (5U) +#define SPI_INTENCLR_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSDEN_SHIFT)) & SPI_INTENCLR_SSDEN_MASK) +#define SPI_INTENCLR_MSTIDLE_MASK (0x100U) +#define SPI_INTENCLR_MSTIDLE_SHIFT (8U) +#define SPI_INTENCLR_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_MSTIDLE_SHIFT)) & SPI_INTENCLR_MSTIDLE_MASK) +/*! @} */ + +/*! @name DIV - SPI clock Divider */ +/*! @{ */ +#define SPI_DIV_DIVVAL_MASK (0xFFFFU) +#define SPI_DIV_DIVVAL_SHIFT (0U) +#define SPI_DIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << SPI_DIV_DIVVAL_SHIFT)) & SPI_DIV_DIVVAL_MASK) +/*! @} */ + +/*! @name INTSTAT - SPI Interrupt Status */ +/*! @{ */ +#define SPI_INTSTAT_SSA_MASK (0x10U) +#define SPI_INTSTAT_SSA_SHIFT (4U) +#define SPI_INTSTAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSA_SHIFT)) & SPI_INTSTAT_SSA_MASK) +#define SPI_INTSTAT_SSD_MASK (0x20U) +#define SPI_INTSTAT_SSD_SHIFT (5U) +#define SPI_INTSTAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSD_SHIFT)) & SPI_INTSTAT_SSD_MASK) +#define SPI_INTSTAT_MSTIDLE_MASK (0x100U) +#define SPI_INTSTAT_MSTIDLE_SHIFT (8U) +#define SPI_INTSTAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_MSTIDLE_SHIFT)) & SPI_INTSTAT_MSTIDLE_MASK) +/*! @} */ + +/*! @name FIFOCFG - FIFO configuration and enable register. */ +/*! @{ */ +#define SPI_FIFOCFG_ENABLETX_MASK (0x1U) +#define SPI_FIFOCFG_ENABLETX_SHIFT (0U) +/*! ENABLETX - Enable the transmit FIFO. + * 0b0..The transmit FIFO is not enabled. + * 0b1..The transmit FIFO is enabled. + */ +#define SPI_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLETX_SHIFT)) & SPI_FIFOCFG_ENABLETX_MASK) +#define SPI_FIFOCFG_ENABLERX_MASK (0x2U) +#define SPI_FIFOCFG_ENABLERX_SHIFT (1U) +/*! ENABLERX - Enable the receive FIFO. + * 0b0..The receive FIFO is not enabled. + * 0b1..The receive FIFO is enabled. + */ +#define SPI_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLERX_SHIFT)) & SPI_FIFOCFG_ENABLERX_MASK) +#define SPI_FIFOCFG_SIZE_MASK (0x30U) +#define SPI_FIFOCFG_SIZE_SHIFT (4U) +#define SPI_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_SIZE_SHIFT)) & SPI_FIFOCFG_SIZE_MASK) +#define SPI_FIFOCFG_DMATX_MASK (0x1000U) +#define SPI_FIFOCFG_DMATX_SHIFT (12U) +/*! DMATX - DMA configuration for transmit. + * 0b0..DMA is not used for the transmit function. + * 0b1..Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. + */ +#define SPI_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMATX_SHIFT)) & SPI_FIFOCFG_DMATX_MASK) +#define SPI_FIFOCFG_DMARX_MASK (0x2000U) +#define SPI_FIFOCFG_DMARX_SHIFT (13U) +/*! DMARX - DMA configuration for receive. + * 0b0..DMA is not used for the receive function. + * 0b1..Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. + */ +#define SPI_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMARX_SHIFT)) & SPI_FIFOCFG_DMARX_MASK) +#define SPI_FIFOCFG_WAKETX_MASK (0x4000U) +#define SPI_FIFOCFG_WAKETX_SHIFT (14U) +/*! WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power + * modes (up to power-down, as long as the peripheral function works in that power mode) without + * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The + * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware + * Wake-up control register. + * 0b0..Only enabled interrupts will wake up the device form reduced power modes. + * 0b1..A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in + * FIFOTRIG, even when the TXLVL interrupt is not enabled. + */ +#define SPI_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKETX_SHIFT)) & SPI_FIFOCFG_WAKETX_MASK) +#define SPI_FIFOCFG_WAKERX_MASK (0x8000U) +#define SPI_FIFOCFG_WAKERX_SHIFT (15U) +/*! WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power + * modes (up to power-down, as long as the peripheral function works in that power mode) without + * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The + * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware + * Wake-up control register. + * 0b0..Only enabled interrupts will wake up the device form reduced power modes. + * 0b1..A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in + * FIFOTRIG, even when the RXLVL interrupt is not enabled. + */ +#define SPI_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKERX_SHIFT)) & SPI_FIFOCFG_WAKERX_MASK) +#define SPI_FIFOCFG_EMPTYTX_MASK (0x10000U) +#define SPI_FIFOCFG_EMPTYTX_SHIFT (16U) +#define SPI_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYTX_SHIFT)) & SPI_FIFOCFG_EMPTYTX_MASK) +#define SPI_FIFOCFG_EMPTYRX_MASK (0x20000U) +#define SPI_FIFOCFG_EMPTYRX_SHIFT (17U) +#define SPI_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYRX_SHIFT)) & SPI_FIFOCFG_EMPTYRX_MASK) +#define SPI_FIFOCFG_POPDBG_MASK (0x40000U) +#define SPI_FIFOCFG_POPDBG_SHIFT (18U) +/*! POPDBG - Pop FIFO for debug reads. + * 0b0..Debug reads of the FIFO do not pop the FIFO. + * 0b1..A debug read will cause the FIFO to pop. + */ +#define SPI_FIFOCFG_POPDBG(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_POPDBG_SHIFT)) & SPI_FIFOCFG_POPDBG_MASK) +/*! @} */ + +/*! @name FIFOSTAT - FIFO status register. */ +/*! @{ */ +#define SPI_FIFOSTAT_TXERR_MASK (0x1U) +#define SPI_FIFOSTAT_TXERR_SHIFT (0U) +#define SPI_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXERR_SHIFT)) & SPI_FIFOSTAT_TXERR_MASK) +#define SPI_FIFOSTAT_RXERR_MASK (0x2U) +#define SPI_FIFOSTAT_RXERR_SHIFT (1U) +#define SPI_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXERR_SHIFT)) & SPI_FIFOSTAT_RXERR_MASK) +#define SPI_FIFOSTAT_PERINT_MASK (0x8U) +#define SPI_FIFOSTAT_PERINT_SHIFT (3U) +#define SPI_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_PERINT_SHIFT)) & SPI_FIFOSTAT_PERINT_MASK) +#define SPI_FIFOSTAT_TXEMPTY_MASK (0x10U) +#define SPI_FIFOSTAT_TXEMPTY_SHIFT (4U) +#define SPI_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXEMPTY_SHIFT)) & SPI_FIFOSTAT_TXEMPTY_MASK) +#define SPI_FIFOSTAT_TXNOTFULL_MASK (0x20U) +#define SPI_FIFOSTAT_TXNOTFULL_SHIFT (5U) +#define SPI_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXNOTFULL_SHIFT)) & SPI_FIFOSTAT_TXNOTFULL_MASK) +#define SPI_FIFOSTAT_RXNOTEMPTY_MASK (0x40U) +#define SPI_FIFOSTAT_RXNOTEMPTY_SHIFT (6U) +#define SPI_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXNOTEMPTY_SHIFT)) & SPI_FIFOSTAT_RXNOTEMPTY_MASK) +#define SPI_FIFOSTAT_RXFULL_MASK (0x80U) +#define SPI_FIFOSTAT_RXFULL_SHIFT (7U) +#define SPI_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXFULL_SHIFT)) & SPI_FIFOSTAT_RXFULL_MASK) +#define SPI_FIFOSTAT_TXLVL_MASK (0x1F00U) +#define SPI_FIFOSTAT_TXLVL_SHIFT (8U) +#define SPI_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXLVL_SHIFT)) & SPI_FIFOSTAT_TXLVL_MASK) +#define SPI_FIFOSTAT_RXLVL_MASK (0x1F0000U) +#define SPI_FIFOSTAT_RXLVL_SHIFT (16U) +#define SPI_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXLVL_SHIFT)) & SPI_FIFOSTAT_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */ +/*! @{ */ +#define SPI_FIFOTRIG_TXLVLENA_MASK (0x1U) +#define SPI_FIFOTRIG_TXLVLENA_SHIFT (0U) +/*! TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled + * in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set. + * 0b0..Transmit FIFO level does not generate a FIFO level trigger. + * 0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register. + */ +#define SPI_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVLENA_SHIFT)) & SPI_FIFOTRIG_TXLVLENA_MASK) +#define SPI_FIFOTRIG_RXLVLENA_MASK (0x2U) +#define SPI_FIFOTRIG_RXLVLENA_SHIFT (1U) +/*! RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled + * in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. + * 0b0..Receive FIFO level does not generate a FIFO level trigger. + * 0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. + */ +#define SPI_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVLENA_SHIFT)) & SPI_FIFOTRIG_RXLVLENA_MASK) +#define SPI_FIFOTRIG_TXLVL_MASK (0xF00U) +#define SPI_FIFOTRIG_TXLVL_SHIFT (8U) +#define SPI_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVL_SHIFT)) & SPI_FIFOTRIG_TXLVL_MASK) +#define SPI_FIFOTRIG_RXLVL_MASK (0xF0000U) +#define SPI_FIFOTRIG_RXLVL_SHIFT (16U) +#define SPI_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVL_SHIFT)) & SPI_FIFOTRIG_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */ +/*! @{ */ +#define SPI_FIFOINTENSET_TXERR_MASK (0x1U) +#define SPI_FIFOINTENSET_TXERR_SHIFT (0U) +/*! TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. + * 0b0..No interrupt will be generated for a transmit error. + * 0b1..An interrupt will be generated when a transmit error occurs. + */ +#define SPI_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXERR_SHIFT)) & SPI_FIFOINTENSET_TXERR_MASK) +#define SPI_FIFOINTENSET_RXERR_MASK (0x2U) +#define SPI_FIFOINTENSET_RXERR_SHIFT (1U) +/*! RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. + * 0b0..No interrupt will be generated for a receive error. + * 0b1..An interrupt will be generated when a receive error occurs. + */ +#define SPI_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXERR_SHIFT)) & SPI_FIFOINTENSET_RXERR_MASK) +#define SPI_FIFOINTENSET_TXLVL_MASK (0x4U) +#define SPI_FIFOINTENSET_TXLVL_SHIFT (2U) +/*! TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level + * specified by the TXLVL field in the FIFOTRIG register. + * 0b0..No interrupt will be generated based on the TX FIFO level. + * 0b1..If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases + * to the level specified by TXLVL in the FIFOTRIG register. + */ +#define SPI_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXLVL_SHIFT)) & SPI_FIFOINTENSET_TXLVL_MASK) +#define SPI_FIFOINTENSET_RXLVL_MASK (0x8U) +#define SPI_FIFOINTENSET_RXLVL_SHIFT (3U) +/*! RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level + * specified by the TXLVL field in the FIFOTRIG register. + * 0b0..No interrupt will be generated based on the RX FIFO level. + * 0b1..If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level + * increases to the level specified by RXLVL in the FIFOTRIG register. + */ +#define SPI_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXLVL_SHIFT)) & SPI_FIFOINTENSET_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */ +/*! @{ */ +#define SPI_FIFOINTENCLR_TXERR_MASK (0x1U) +#define SPI_FIFOINTENCLR_TXERR_SHIFT (0U) +#define SPI_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXERR_SHIFT)) & SPI_FIFOINTENCLR_TXERR_MASK) +#define SPI_FIFOINTENCLR_RXERR_MASK (0x2U) +#define SPI_FIFOINTENCLR_RXERR_SHIFT (1U) +#define SPI_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXERR_SHIFT)) & SPI_FIFOINTENCLR_RXERR_MASK) +#define SPI_FIFOINTENCLR_TXLVL_MASK (0x4U) +#define SPI_FIFOINTENCLR_TXLVL_SHIFT (2U) +#define SPI_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXLVL_SHIFT)) & SPI_FIFOINTENCLR_TXLVL_MASK) +#define SPI_FIFOINTENCLR_RXLVL_MASK (0x8U) +#define SPI_FIFOINTENCLR_RXLVL_SHIFT (3U) +#define SPI_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXLVL_SHIFT)) & SPI_FIFOINTENCLR_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTSTAT - FIFO interrupt status register. */ +/*! @{ */ +#define SPI_FIFOINTSTAT_TXERR_MASK (0x1U) +#define SPI_FIFOINTSTAT_TXERR_SHIFT (0U) +#define SPI_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXERR_SHIFT)) & SPI_FIFOINTSTAT_TXERR_MASK) +#define SPI_FIFOINTSTAT_RXERR_MASK (0x2U) +#define SPI_FIFOINTSTAT_RXERR_SHIFT (1U) +#define SPI_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXERR_SHIFT)) & SPI_FIFOINTSTAT_RXERR_MASK) +#define SPI_FIFOINTSTAT_TXLVL_MASK (0x4U) +#define SPI_FIFOINTSTAT_TXLVL_SHIFT (2U) +#define SPI_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXLVL_SHIFT)) & SPI_FIFOINTSTAT_TXLVL_MASK) +#define SPI_FIFOINTSTAT_RXLVL_MASK (0x8U) +#define SPI_FIFOINTSTAT_RXLVL_SHIFT (3U) +#define SPI_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXLVL_SHIFT)) & SPI_FIFOINTSTAT_RXLVL_MASK) +#define SPI_FIFOINTSTAT_PERINT_MASK (0x10U) +#define SPI_FIFOINTSTAT_PERINT_SHIFT (4U) +#define SPI_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_PERINT_SHIFT)) & SPI_FIFOINTSTAT_PERINT_MASK) +/*! @} */ + +/*! @name FIFOWR - FIFO write data. */ +/*! @{ */ +#define SPI_FIFOWR_TXDATA_MASK (0xFFFFU) +#define SPI_FIFOWR_TXDATA_SHIFT (0U) +#define SPI_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXDATA_SHIFT)) & SPI_FIFOWR_TXDATA_MASK) +#define SPI_FIFOWR_TXSSEL0_N_MASK (0x10000U) +#define SPI_FIFOWR_TXSSEL0_N_SHIFT (16U) +/*! TXSSEL0_N - Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default. + * 0b0..SSEL0 asserted. + * 0b1..SSEL0 not asserted. + */ +#define SPI_FIFOWR_TXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL0_N_SHIFT)) & SPI_FIFOWR_TXSSEL0_N_MASK) +#define SPI_FIFOWR_TXSSEL1_N_MASK (0x20000U) +#define SPI_FIFOWR_TXSSEL1_N_SHIFT (17U) +/*! TXSSEL1_N - Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default. + * 0b0..SSEL1 asserted. + * 0b1..SSEL1 not asserted. + */ +#define SPI_FIFOWR_TXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL1_N_SHIFT)) & SPI_FIFOWR_TXSSEL1_N_MASK) +#define SPI_FIFOWR_TXSSEL2_N_MASK (0x40000U) +#define SPI_FIFOWR_TXSSEL2_N_SHIFT (18U) +/*! TXSSEL2_N - Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default. + * 0b0..SSEL2 asserted. + * 0b1..SSEL2 not asserted. + */ +#define SPI_FIFOWR_TXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL2_N_SHIFT)) & SPI_FIFOWR_TXSSEL2_N_MASK) +#define SPI_FIFOWR_TXSSEL3_N_MASK (0x80000U) +#define SPI_FIFOWR_TXSSEL3_N_SHIFT (19U) +/*! TXSSEL3_N - Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default. + * 0b0..SSEL3 asserted. + * 0b1..SSEL3 not asserted. + */ +#define SPI_FIFOWR_TXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL3_N_SHIFT)) & SPI_FIFOWR_TXSSEL3_N_MASK) +#define SPI_FIFOWR_EOT_MASK (0x100000U) +#define SPI_FIFOWR_EOT_SHIFT (20U) +/*! EOT - End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain + * so far at least the time specified by the Transfer_delay value in the DLY register. + * 0b0..SSEL not deasserted. This piece of data is not treated as the end of a transfer. SSEL will not be deasserted at the end of this data. + * 0b1..SSEL deasserted. This piece of data is treated as the end of a transfer. SSEL will be deasserted at the end of this piece of data. + */ +#define SPI_FIFOWR_EOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOT_SHIFT)) & SPI_FIFOWR_EOT_MASK) +#define SPI_FIFOWR_EOF_MASK (0x200000U) +#define SPI_FIFOWR_EOF_SHIFT (21U) +/*! EOF - End of frame. Between frames, a delay may be inserted, as defined by the Frame_delay value + * in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay + * value = 0. This control can be used as part of the support for frame lengths greater than 16 + * bits. + * 0b0..Data not EOF. This piece of data transmitted is not treated as the end of a frame. + * 0b1..Data EOF. This piece of data is treated as the end of a frame, causing the Frame_delay time to be + * inserted before subsequent data is transmitted. + */ +#define SPI_FIFOWR_EOF(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOF_SHIFT)) & SPI_FIFOWR_EOF_MASK) +#define SPI_FIFOWR_RXIGNORE_MASK (0x400000U) +#define SPI_FIFOWR_RXIGNORE_SHIFT (22U) +/*! RXIGNORE - Receive Ignore. This allows data to be transmitted using the SPI without the need to + * read unneeded data from the receiver. Setting this bit simplifies the transmit process and can + * be used with the DMA. + * 0b0..Read received data. Received data must be read in order to allow transmission to progress. SPI transmit + * will halt when the receive data FIFO is full. In slave mode, an overrun error will occur if received data + * is not read before new data is received. + * 0b1..Ignore received data. Received data is ignored, allowing transmission without reading unneeded received + * data. No receiver flags are generated. + */ +#define SPI_FIFOWR_RXIGNORE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_RXIGNORE_SHIFT)) & SPI_FIFOWR_RXIGNORE_MASK) +#define SPI_FIFOWR_LEN_MASK (0xF000000U) +#define SPI_FIFOWR_LEN_SHIFT (24U) +#define SPI_FIFOWR_LEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_LEN_SHIFT)) & SPI_FIFOWR_LEN_MASK) +/*! @} */ + +/*! @name FIFORD - FIFO read data. */ +/*! @{ */ +#define SPI_FIFORD_RXDATA_MASK (0xFFFFU) +#define SPI_FIFORD_RXDATA_SHIFT (0U) +#define SPI_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXDATA_SHIFT)) & SPI_FIFORD_RXDATA_MASK) +#define SPI_FIFORD_RXSSEL0_N_MASK (0x10000U) +#define SPI_FIFORD_RXSSEL0_N_SHIFT (16U) +#define SPI_FIFORD_RXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL0_N_SHIFT)) & SPI_FIFORD_RXSSEL0_N_MASK) +#define SPI_FIFORD_RXSSEL1_N_MASK (0x20000U) +#define SPI_FIFORD_RXSSEL1_N_SHIFT (17U) +#define SPI_FIFORD_RXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL1_N_SHIFT)) & SPI_FIFORD_RXSSEL1_N_MASK) +#define SPI_FIFORD_RXSSEL2_N_MASK (0x40000U) +#define SPI_FIFORD_RXSSEL2_N_SHIFT (18U) +#define SPI_FIFORD_RXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL2_N_SHIFT)) & SPI_FIFORD_RXSSEL2_N_MASK) +#define SPI_FIFORD_RXSSEL3_N_MASK (0x80000U) +#define SPI_FIFORD_RXSSEL3_N_SHIFT (19U) +#define SPI_FIFORD_RXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL3_N_SHIFT)) & SPI_FIFORD_RXSSEL3_N_MASK) +#define SPI_FIFORD_SOT_MASK (0x100000U) +#define SPI_FIFORD_SOT_SHIFT (20U) +#define SPI_FIFORD_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_SOT_SHIFT)) & SPI_FIFORD_SOT_MASK) +/*! @} */ + +/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */ +/*! @{ */ +#define SPI_FIFORDNOPOP_RXDATA_MASK (0xFFFFU) +#define SPI_FIFORDNOPOP_RXDATA_SHIFT (0U) +#define SPI_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXDATA_SHIFT)) & SPI_FIFORDNOPOP_RXDATA_MASK) +#define SPI_FIFORDNOPOP_RXSSEL0_N_MASK (0x10000U) +#define SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT (16U) +#define SPI_FIFORDNOPOP_RXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL0_N_MASK) +#define SPI_FIFORDNOPOP_RXSSEL1_N_MASK (0x20000U) +#define SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT (17U) +#define SPI_FIFORDNOPOP_RXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL1_N_MASK) +#define SPI_FIFORDNOPOP_RXSSEL2_N_MASK (0x40000U) +#define SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT (18U) +#define SPI_FIFORDNOPOP_RXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL2_N_MASK) +#define SPI_FIFORDNOPOP_RXSSEL3_N_MASK (0x80000U) +#define SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT (19U) +#define SPI_FIFORDNOPOP_RXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL3_N_MASK) +#define SPI_FIFORDNOPOP_SOT_MASK (0x100000U) +#define SPI_FIFORDNOPOP_SOT_SHIFT (20U) +#define SPI_FIFORDNOPOP_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_SOT_SHIFT)) & SPI_FIFORDNOPOP_SOT_MASK) +/*! @} */ + +/*! @name ID - Peripheral identification register. */ +/*! @{ */ +#define SPI_ID_APERTURE_MASK (0xFFU) +#define SPI_ID_APERTURE_SHIFT (0U) +#define SPI_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_APERTURE_SHIFT)) & SPI_ID_APERTURE_MASK) +#define SPI_ID_MINOR_REV_MASK (0xF00U) +#define SPI_ID_MINOR_REV_SHIFT (8U) +#define SPI_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_MINOR_REV_SHIFT)) & SPI_ID_MINOR_REV_MASK) +#define SPI_ID_MAJOR_REV_MASK (0xF000U) +#define SPI_ID_MAJOR_REV_SHIFT (12U) +#define SPI_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_MAJOR_REV_SHIFT)) & SPI_ID_MAJOR_REV_MASK) +#define SPI_ID_ID_MASK (0xFFFF0000U) +#define SPI_ID_ID_SHIFT (16U) +#define SPI_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_ID_SHIFT)) & SPI_ID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SPI_Register_Masks */ + + +/* SPI - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral SPI0 base address */ + #define SPI0_BASE (0x50086000u) + /** Peripheral SPI0 base address */ + #define SPI0_BASE_NS (0x40086000u) + /** Peripheral SPI0 base pointer */ + #define SPI0 ((SPI_Type *)SPI0_BASE) + /** Peripheral SPI0 base pointer */ + #define SPI0_NS ((SPI_Type *)SPI0_BASE_NS) + /** Peripheral SPI1 base address */ + #define SPI1_BASE (0x50087000u) + /** Peripheral SPI1 base address */ + #define SPI1_BASE_NS (0x40087000u) + /** Peripheral SPI1 base pointer */ + #define SPI1 ((SPI_Type *)SPI1_BASE) + /** Peripheral SPI1 base pointer */ + #define SPI1_NS ((SPI_Type *)SPI1_BASE_NS) + /** Peripheral SPI2 base address */ + #define SPI2_BASE (0x50088000u) + /** Peripheral SPI2 base address */ + #define SPI2_BASE_NS (0x40088000u) + /** Peripheral SPI2 base pointer */ + #define SPI2 ((SPI_Type *)SPI2_BASE) + /** Peripheral SPI2 base pointer */ + #define SPI2_NS ((SPI_Type *)SPI2_BASE_NS) + /** Peripheral SPI3 base address */ + #define SPI3_BASE (0x50089000u) + /** Peripheral SPI3 base address */ + #define SPI3_BASE_NS (0x40089000u) + /** Peripheral SPI3 base pointer */ + #define SPI3 ((SPI_Type *)SPI3_BASE) + /** Peripheral SPI3 base pointer */ + #define SPI3_NS ((SPI_Type *)SPI3_BASE_NS) + /** Peripheral SPI4 base address */ + #define SPI4_BASE (0x5008A000u) + /** Peripheral SPI4 base address */ + #define SPI4_BASE_NS (0x4008A000u) + /** Peripheral SPI4 base pointer */ + #define SPI4 ((SPI_Type *)SPI4_BASE) + /** Peripheral SPI4 base pointer */ + #define SPI4_NS ((SPI_Type *)SPI4_BASE_NS) + /** Peripheral SPI5 base address */ + #define SPI5_BASE (0x50096000u) + /** Peripheral SPI5 base address */ + #define SPI5_BASE_NS (0x40096000u) + /** Peripheral SPI5 base pointer */ + #define SPI5 ((SPI_Type *)SPI5_BASE) + /** Peripheral SPI5 base pointer */ + #define SPI5_NS ((SPI_Type *)SPI5_BASE_NS) + /** Peripheral SPI6 base address */ + #define SPI6_BASE (0x50097000u) + /** Peripheral SPI6 base address */ + #define SPI6_BASE_NS (0x40097000u) + /** Peripheral SPI6 base pointer */ + #define SPI6 ((SPI_Type *)SPI6_BASE) + /** Peripheral SPI6 base pointer */ + #define SPI6_NS ((SPI_Type *)SPI6_BASE_NS) + /** Peripheral SPI7 base address */ + #define SPI7_BASE (0x50098000u) + /** Peripheral SPI7 base address */ + #define SPI7_BASE_NS (0x40098000u) + /** Peripheral SPI7 base pointer */ + #define SPI7 ((SPI_Type *)SPI7_BASE) + /** Peripheral SPI7 base pointer */ + #define SPI7_NS ((SPI_Type *)SPI7_BASE_NS) + /** Peripheral SPI8 base address */ + #define SPI8_BASE (0x5009F000u) + /** Peripheral SPI8 base address */ + #define SPI8_BASE_NS (0x4009F000u) + /** Peripheral SPI8 base pointer */ + #define SPI8 ((SPI_Type *)SPI8_BASE) + /** Peripheral SPI8 base pointer */ + #define SPI8_NS ((SPI_Type *)SPI8_BASE_NS) + /** Array initializer of SPI peripheral base addresses */ + #define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE, SPI2_BASE, SPI3_BASE, SPI4_BASE, SPI5_BASE, SPI6_BASE, SPI7_BASE, SPI8_BASE } + /** Array initializer of SPI peripheral base pointers */ + #define SPI_BASE_PTRS { SPI0, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SPI7, SPI8 } + /** Array initializer of SPI peripheral base addresses */ + #define SPI_BASE_ADDRS_NS { SPI0_BASE_NS, SPI1_BASE_NS, SPI2_BASE_NS, SPI3_BASE_NS, SPI4_BASE_NS, SPI5_BASE_NS, SPI6_BASE_NS, SPI7_BASE_NS, SPI8_BASE_NS } + /** Array initializer of SPI peripheral base pointers */ + #define SPI_BASE_PTRS_NS { SPI0_NS, SPI1_NS, SPI2_NS, SPI3_NS, SPI4_NS, SPI5_NS, SPI6_NS, SPI7_NS, SPI8_NS } +#else + /** Peripheral SPI0 base address */ + #define SPI0_BASE (0x40086000u) + /** Peripheral SPI0 base pointer */ + #define SPI0 ((SPI_Type *)SPI0_BASE) + /** Peripheral SPI1 base address */ + #define SPI1_BASE (0x40087000u) + /** Peripheral SPI1 base pointer */ + #define SPI1 ((SPI_Type *)SPI1_BASE) + /** Peripheral SPI2 base address */ + #define SPI2_BASE (0x40088000u) + /** Peripheral SPI2 base pointer */ + #define SPI2 ((SPI_Type *)SPI2_BASE) + /** Peripheral SPI3 base address */ + #define SPI3_BASE (0x40089000u) + /** Peripheral SPI3 base pointer */ + #define SPI3 ((SPI_Type *)SPI3_BASE) + /** Peripheral SPI4 base address */ + #define SPI4_BASE (0x4008A000u) + /** Peripheral SPI4 base pointer */ + #define SPI4 ((SPI_Type *)SPI4_BASE) + /** Peripheral SPI5 base address */ + #define SPI5_BASE (0x40096000u) + /** Peripheral SPI5 base pointer */ + #define SPI5 ((SPI_Type *)SPI5_BASE) + /** Peripheral SPI6 base address */ + #define SPI6_BASE (0x40097000u) + /** Peripheral SPI6 base pointer */ + #define SPI6 ((SPI_Type *)SPI6_BASE) + /** Peripheral SPI7 base address */ + #define SPI7_BASE (0x40098000u) + /** Peripheral SPI7 base pointer */ + #define SPI7 ((SPI_Type *)SPI7_BASE) + /** Peripheral SPI8 base address */ + #define SPI8_BASE (0x4009F000u) + /** Peripheral SPI8 base pointer */ + #define SPI8 ((SPI_Type *)SPI8_BASE) + /** Array initializer of SPI peripheral base addresses */ + #define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE, SPI2_BASE, SPI3_BASE, SPI4_BASE, SPI5_BASE, SPI6_BASE, SPI7_BASE, SPI8_BASE } + /** Array initializer of SPI peripheral base pointers */ + #define SPI_BASE_PTRS { SPI0, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SPI7, SPI8 } +#endif +/** Interrupt vectors for the SPI peripheral type */ +#define SPI_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn } + +/*! + * @} + */ /* end of group SPI_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SYSCON Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SYSCON_Peripheral_Access_Layer SYSCON Peripheral Access Layer + * @{ + */ + +/** SYSCON - Register Layout Typedef */ +typedef struct { + __IO uint32_t MEMORYREMAP; /**< Memory Remap control register, offset: 0x0 */ + uint8_t RESERVED_0[12]; + __IO uint32_t AHBMATPRIO; /**< AHB Matrix priority control register Priority values are 3 = highest, 0 = lowest, offset: 0x10 */ + uint8_t RESERVED_1[36]; + __IO uint32_t CPU0STCKCAL; /**< System tick calibration for secure part of CPU0, offset: 0x38 */ + __IO uint32_t CPU0NSTCKCAL; /**< System tick calibration for non-secure part of CPU0, offset: 0x3C */ + __IO uint32_t CPU1TCKCAL; /**< System tick calibration for CPU1, offset: 0x40 */ + uint8_t RESERVED_2[4]; + __IO uint32_t NMISRC; /**< NMI Source Select, offset: 0x48 */ + uint8_t RESERVED_3[180]; + union { /* offset: 0x100 */ + struct { /* offset: 0x100 */ + __IO uint32_t PRESETCTRL0; /**< Peripheral reset control 0, offset: 0x100 */ + __IO uint32_t PRESETCTRL1; /**< Peripheral reset control 1, offset: 0x104 */ + __IO uint32_t PRESETCTRL2; /**< Peripheral reset control 2, offset: 0x108 */ + } PRESETCTRL; + __IO uint32_t PRESETCTRLX[3]; /**< Peripheral reset control register, array offset: 0x100, array step: 0x4 */ + }; + uint8_t RESERVED_4[20]; + __IO uint32_t PRESETCTRLSET[3]; /**< Peripheral reset control set register, array offset: 0x120, array step: 0x4 */ + uint8_t RESERVED_5[20]; + __IO uint32_t PRESETCTRLCLR[3]; /**< Peripheral reset contro clearl register, array offset: 0x140, array step: 0x4 */ + uint8_t RESERVED_6[20]; + __O uint32_t SWR_RESET; /**< generate a software_reset, offset: 0x160 */ + uint8_t RESERVED_7[156]; + union { /* offset: 0x200 */ + struct { /* offset: 0x200 */ + __IO uint32_t AHBCLKCTRL0; /**< AHB Clock control 0, offset: 0x200 */ + __IO uint32_t AHBCLKCTRL1; /**< AHB Clock control 1, offset: 0x204 */ + __IO uint32_t AHBCLKCTRL2; /**< AHB Clock control 2, offset: 0x208 */ + } AHBCLKCTRL; + __IO uint32_t AHBCLKCTRLX[3]; /**< Peripheral reset control register, array offset: 0x200, array step: 0x4 */ + }; + uint8_t RESERVED_8[20]; + __IO uint32_t AHBCLKCTRLSET[3]; /**< Peripheral reset control register, array offset: 0x220, array step: 0x4 */ + uint8_t RESERVED_9[20]; + __IO uint32_t AHBCLKCTRLCLR[3]; /**< Peripheral reset control register, array offset: 0x240, array step: 0x4 */ + uint8_t RESERVED_10[20]; + union { /* offset: 0x260 */ + struct { /* offset: 0x260 */ + __IO uint32_t SYSTICKCLKSEL0; /**< System Tick Timer for CPU0 source select, offset: 0x260 */ + __IO uint32_t SYSTICKCLKSEL1; /**< System Tick Timer for CPU1 source select, offset: 0x264 */ + } SYSTICKCLKSEL; + __IO uint32_t SYSTICKCLKSELX[2]; /**< Peripheral reset control register, array offset: 0x260, array step: 0x4 */ + }; + __IO uint32_t TRACECLKSEL; /**< Trace clock source select, offset: 0x268 */ + union { /* offset: 0x26C */ + struct { /* offset: 0x26C */ + __IO uint32_t CTIMERCLKSEL0; /**< CTimer 0 clock source select, offset: 0x26C */ + __IO uint32_t CTIMERCLKSEL1; /**< CTimer 1 clock source select, offset: 0x270 */ + __IO uint32_t CTIMERCLKSEL2; /**< CTimer 2 clock source select, offset: 0x274 */ + __IO uint32_t CTIMERCLKSEL3; /**< CTimer 3 clock source select, offset: 0x278 */ + __IO uint32_t CTIMERCLKSEL4; /**< CTimer 4 clock source select, offset: 0x27C */ + } CTIMERCLKSEL; + __IO uint32_t CTIMERCLKSELX[5]; /**< Peripheral reset control register, array offset: 0x26C, array step: 0x4 */ + }; + __IO uint32_t MAINCLKSELA; /**< Main clock A source select, offset: 0x280 */ + __IO uint32_t MAINCLKSELB; /**< Main clock source select, offset: 0x284 */ + __IO uint32_t CLKOUTSEL; /**< CLKOUT clock source select, offset: 0x288 */ + uint8_t RESERVED_11[4]; + __IO uint32_t PLL0CLKSEL; /**< PLL0 clock source select, offset: 0x290 */ + __IO uint32_t PLL1CLKSEL; /**< PLL1 clock source select, offset: 0x294 */ + uint8_t RESERVED_12[12]; + __IO uint32_t ADCCLKSEL; /**< ADC clock source select, offset: 0x2A4 */ + __IO uint32_t USB0CLKSEL; /**< FS USB clock source select, offset: 0x2A8 */ + __IO uint32_t USB1CLKSEL; /**< HS USB clock source select - NOT USED, offset: 0x2AC */ + union { /* offset: 0x2B0 */ + struct { /* offset: 0x2B0 */ + __IO uint32_t FCCLKSEL0; /**< Flexcomm Interface 0 clock source select for Fractional Rate Divider, offset: 0x2B0 */ + __IO uint32_t FCCLKSEL1; /**< Flexcomm Interface 1 clock source select for Fractional Rate Divider, offset: 0x2B4 */ + __IO uint32_t FCCLKSEL2; /**< Flexcomm Interface 2 clock source select for Fractional Rate Divider, offset: 0x2B8 */ + __IO uint32_t FCCLKSEL3; /**< Flexcomm Interface 3 clock source select for Fractional Rate Divider, offset: 0x2BC */ + __IO uint32_t FCCLKSEL4; /**< Flexcomm Interface 4 clock source select for Fractional Rate Divider, offset: 0x2C0 */ + __IO uint32_t FCCLKSEL5; /**< Flexcomm Interface 5 clock source select for Fractional Rate Divider, offset: 0x2C4 */ + __IO uint32_t FCCLKSEL6; /**< Flexcomm Interface 6 clock source select for Fractional Rate Divider, offset: 0x2C8 */ + __IO uint32_t FCCLKSEL7; /**< Flexcomm Interface 7 clock source select for Fractional Rate Divider, offset: 0x2CC */ + } FCCLKSEL; + __IO uint32_t FCCLKSELX[8]; /**< Peripheral reset control register, array offset: 0x2B0, array step: 0x4 */ + }; + __IO uint32_t HSLSPICLKSEL; /**< HS LSPI clock source select, offset: 0x2D0 */ + uint8_t RESERVED_13[12]; + __IO uint32_t MCLKCLKSEL; /**< MCLK clock source select, offset: 0x2E0 */ + uint8_t RESERVED_14[12]; + __IO uint32_t SCTCLKSEL; /**< SCTimer/PWM clock source select, offset: 0x2F0 */ + uint8_t RESERVED_15[4]; + __IO uint32_t SDIOCLKSEL; /**< SDIO clock source select, offset: 0x2F8 */ + uint8_t RESERVED_16[4]; + __IO uint32_t SYSTICKCLKDIV0; /**< System Tick Timer divider for CPU0, offset: 0x300 */ + __IO uint32_t SYSTICKCLKDIV1; /**< System Tick Timer divider for CPU1, offset: 0x304 */ + __IO uint32_t TRACECLKDIV; /**< TRACE clock divider, offset: 0x308 */ + uint8_t RESERVED_17[20]; + union { /* offset: 0x320 */ + struct { /* offset: 0x320 */ + __IO uint32_t FLEXFRG0CTRL; /**< Fractional rate divider for flexcomm 0, offset: 0x320 */ + __IO uint32_t FLEXFRG1CTRL; /**< Fractional rate divider for flexcomm 1, offset: 0x324 */ + __IO uint32_t FLEXFRG2CTRL; /**< Fractional rate divider for flexcomm 2, offset: 0x328 */ + __IO uint32_t FLEXFRG3CTRL; /**< Fractional rate divider for flexcomm 3, offset: 0x32C */ + __IO uint32_t FLEXFRG4CTRL; /**< Fractional rate divider for flexcomm 4, offset: 0x330 */ + __IO uint32_t FLEXFRG5CTRL; /**< Fractional rate divider for flexcomm 5, offset: 0x334 */ + __IO uint32_t FLEXFRG6CTRL; /**< Fractional rate divider for flexcomm 6, offset: 0x338 */ + __IO uint32_t FLEXFRG7CTRL; /**< Fractional rate divider for flexcomm 7, offset: 0x33C */ + } FLEXFRGCTRL; + __IO uint32_t FLEXFRGXCTRL[8]; /**< Peripheral reset control register, array offset: 0x320, array step: 0x4 */ + }; + uint8_t RESERVED_18[64]; + __IO uint32_t AHBCLKDIV; /**< System clock divider, offset: 0x380 */ + __IO uint32_t CLKOUTDIV; /**< CLKOUT clock divider, offset: 0x384 */ + __IO uint32_t FROHFDIV; /**< FRO_HF (96MHz) clock divider, offset: 0x388 */ + __IO uint32_t WDTCLKDIV; /**< WDT clock divider, offset: 0x38C */ + uint8_t RESERVED_19[4]; + __IO uint32_t ADCCLKDIV; /**< ADC clock divider, offset: 0x394 */ + __IO uint32_t USB0CLKDIV; /**< USB0 Clock divider, offset: 0x398 */ + uint8_t RESERVED_20[16]; + __IO uint32_t MCLKDIV; /**< I2S MCLK clock divider, offset: 0x3AC */ + uint8_t RESERVED_21[4]; + __IO uint32_t SCTCLKDIV; /**< SCT/PWM clock divider, offset: 0x3B4 */ + uint8_t RESERVED_22[4]; + __IO uint32_t SDIOCLKDIV; /**< SDIO clock divider, offset: 0x3BC */ + uint8_t RESERVED_23[4]; + __IO uint32_t PLL0CLKDIV; /**< PLL0 clock divider, offset: 0x3C4 */ + uint8_t RESERVED_24[52]; + __IO uint32_t CLOCKGENUPDATELOCKOUT; /**< Control clock configuration registers access (like xxxDIV, xxxSEL), offset: 0x3FC */ + __IO uint32_t FMCCR; /**< FMC configuration register - INTERNAL USE ONLY, offset: 0x400 */ + uint8_t RESERVED_25[8]; + __IO uint32_t USB0CLKCTRL; /**< USB0 clock control, offset: 0x40C */ + __I uint32_t USB0CLKSTAT; /**< USB0 clock status, offset: 0x410 */ + uint8_t RESERVED_26[8]; + __O uint32_t FMCFLUSH; /**< FMCflush control, offset: 0x41C */ + __IO uint32_t MCLKIO; /**< MCLK control, offset: 0x420 */ + __IO uint32_t USB1CLKCTRL; /**< USB1 clock control, offset: 0x424 */ + __I uint32_t USB1CLKSTAT; /**< USB1 clock status, offset: 0x428 */ + uint8_t RESERVED_27[36]; + __IO uint32_t FLASHBANKENABLE; /**< Flash Banks control, offset: 0x450 */ + uint8_t RESERVED_28[12]; + __IO uint32_t SDIOCLKCTRL; /**< SDIO CCLKIN phase and delay control, offset: 0x460 */ + uint8_t RESERVED_29[252]; + __IO uint32_t PLL1CTRL; /**< PLL1 550m control, offset: 0x560 */ + __I uint32_t PLL1STAT; /**< PLL1 550m status, offset: 0x564 */ + __IO uint32_t PLL1NDEC; /**< PLL1 550m N divider, offset: 0x568 */ + __IO uint32_t PLL1MDEC; /**< PLL1 550m M divider, offset: 0x56C */ + __IO uint32_t PLL1PDEC; /**< PLL1 550m P divider, offset: 0x570 */ + uint8_t RESERVED_30[12]; + __IO uint32_t PLL0CTRL; /**< PLL0 550m control, offset: 0x580 */ + __I uint32_t PLL0STAT; /**< PLL0 550m status, offset: 0x584 */ + __IO uint32_t PLL0NDEC; /**< PLL0 550m N divider, offset: 0x588 */ + __IO uint32_t PLL0PDEC; /**< PLL0 550m P divider, offset: 0x58C */ + __IO uint32_t PLL0SSCG0; /**< PLL0 Spread Spectrum Wrapper control register 0, offset: 0x590 */ + __IO uint32_t PLL0SSCG1; /**< PLL0 Spread Spectrum Wrapper control register 1, offset: 0x594 */ + uint8_t RESERVED_31[52]; + __IO uint32_t EFUSECLKCTRL; /**< eFUSE controller clock enable, offset: 0x5CC */ + uint8_t RESERVED_32[176]; + __IO uint32_t STARTER[2]; /**< Start logic wake-up enable register, array offset: 0x680, array step: 0x4 */ + uint8_t RESERVED_33[24]; + __O uint32_t STARTERSET[2]; /**< Set bits in STARTER, array offset: 0x6A0, array step: 0x4 */ + uint8_t RESERVED_34[24]; + __O uint32_t STARTERCLR[2]; /**< Clear bits in STARTER, array offset: 0x6C0, array step: 0x4 */ + uint8_t RESERVED_35[184]; + __IO uint32_t HARDWARESLEEP; /**< Hardware Sleep control, offset: 0x780 */ + uint8_t RESERVED_36[124]; + __IO uint32_t CPUCTRL; /**< CPU Control for multiple processors, offset: 0x800 */ + __IO uint32_t CPBOOT; /**< Coprocessor Boot Address, offset: 0x804 */ + __IO uint32_t CPSTACK; /**< Coprocessor Stack Address, offset: 0x808 */ + __I uint32_t CPSTAT; /**< CPU Status, offset: 0x80C */ + uint8_t RESERVED_37[240]; + __IO uint32_t DICE_REG0; /**< Composite Device Identifier, offset: 0x900 */ + __IO uint32_t DICE_REG1; /**< Composite Device Identifier, offset: 0x904 */ + __IO uint32_t DICE_REG2; /**< Composite Device Identifier, offset: 0x908 */ + __IO uint32_t DICE_REG3; /**< Composite Device Identifier, offset: 0x90C */ + __IO uint32_t DICE_REG4; /**< Composite Device Identifier, offset: 0x910 */ + __IO uint32_t DICE_REG5; /**< Composite Device Identifier, offset: 0x914 */ + __IO uint32_t DICE_REG6; /**< Composite Device Identifier, offset: 0x918 */ + __IO uint32_t DICE_REG7; /**< Composite Device Identifier, offset: 0x91C */ + uint8_t RESERVED_38[248]; + __IO uint32_t CLOCK_CTRL; /**< Various system clock controls : Flash clock (48 MHz) control, clocks to Frequency Measures, offset: 0xA18 */ + uint8_t RESERVED_39[244]; + __IO uint32_t COMP_INT_CTRL; /**< Comparator Interrupt control, offset: 0xB10 */ + __I uint32_t COMP_INT_STATUS; /**< Comparator Interrupt status, offset: 0xB14 */ + uint8_t RESERVED_40[748]; + __IO uint32_t AUTOCLKGATEOVERRIDE; /**< Control automatic clock gating, offset: 0xE04 */ + __IO uint32_t GPIOPSYNC; /**< Enable bypass of the first stage of synchonization inside GPIO_INT module, offset: 0xE08 */ + uint8_t RESERVED_41[404]; + __IO uint32_t DEBUG_LOCK_EN; /**< Control write access to security registers -- FOR INTERNAl USE ONLY, offset: 0xFA0 */ + __IO uint32_t DEBUG_FEATURES; /**< Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control -- FOR INTERNAl USE ONLY, offset: 0xFA4 */ + __IO uint32_t DEBUG_FEATURES_DP; /**< Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control DUPLICATE register -- FOR INTERNAl USE ONLY, offset: 0xFA8 */ + uint8_t RESERVED_42[4]; + __O uint32_t CODESECURITYPROTTEST; /**< Security code to allow test (Design for Testability) access -- FOR INTERNAl USE ONLY, offset: 0xFB0 */ + __O uint32_t CODESECURITYPROTCPU0; /**< Security code to allow CPU0 (CM33) Debug Access Port (DAP) -- FOR INTERNAl USE ONLY, offset: 0xFB4 */ + __O uint32_t CODESECURITYPROTCPU1; /**< Security code to allow CPU1 (Micro CM33) Debug Access Port (DAP) -- FOR INTERNAl USE ONLY, offset: 0xFB8 */ + __O uint32_t KEY_BLOCK; /**< block quiddikey/PUF all index. -- FOR INTERNAL USE ONLY, offset: 0xFBC */ + __IO uint32_t DEBUG_AUTH_SCRATCH; /**< Debug authentication scratch registers -- FOR INTERNAL USE ONLY, offset: 0xFC0 */ + uint8_t RESERVED_43[16]; + __IO uint32_t CPUCFG; /**< CPUs configuration register, offset: 0xFD4 */ + uint8_t RESERVED_44[20]; + __IO uint32_t PERIPHENCFG; /**< peripheral enable configuration -- FOR INTERNAL USE ONLY, offset: 0xFEC */ + uint8_t RESERVED_45[8]; + __I uint32_t DEVICE_ID0; /**< Device ID, offset: 0xFF8 */ + __I uint32_t DIEID; /**< Chip revision ID and Number, offset: 0xFFC */ +} SYSCON_Type; + +/* ---------------------------------------------------------------------------- + -- SYSCON Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SYSCON_Register_Masks SYSCON Register Masks + * @{ + */ + +/*! @name MEMORYREMAP - Memory Remap control register */ +/*! @{ */ +#define SYSCON_MEMORYREMAP_MAP_MASK (0x3U) +#define SYSCON_MEMORYREMAP_MAP_SHIFT (0U) +/*! MAP - Select the location of the vector table :. + * 0b00..Vector Table in ROM. + * 0b01..Vector Table in RAM. + * 0b10..Vector Table in Flash. + * 0b11..Vector Table in Flash. + */ +#define SYSCON_MEMORYREMAP_MAP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MEMORYREMAP_MAP_SHIFT)) & SYSCON_MEMORYREMAP_MAP_MASK) +/*! @} */ + +/*! @name AHBMATPRIO - AHB Matrix priority control register Priority values are 3 = highest, 0 = lowest */ +/*! @{ */ +#define SYSCON_AHBMATPRIO_PRI_TEAL_CBUS_MASK (0x3U) +#define SYSCON_AHBMATPRIO_PRI_TEAL_CBUS_SHIFT (0U) +#define SYSCON_AHBMATPRIO_PRI_TEAL_CBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_TEAL_CBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_TEAL_CBUS_MASK) +#define SYSCON_AHBMATPRIO_PRI_TEAL_SBUS_MASK (0xCU) +#define SYSCON_AHBMATPRIO_PRI_TEAL_SBUS_SHIFT (2U) +#define SYSCON_AHBMATPRIO_PRI_TEAL_SBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_TEAL_SBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_TEAL_SBUS_MASK) +#define SYSCON_AHBMATPRIO_PRI_UTEAL_CBUS_MASK (0x30U) +#define SYSCON_AHBMATPRIO_PRI_UTEAL_CBUS_SHIFT (4U) +#define SYSCON_AHBMATPRIO_PRI_UTEAL_CBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_UTEAL_CBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_UTEAL_CBUS_MASK) +#define SYSCON_AHBMATPRIO_PRI_UTEAL_SBUS_MASK (0xC0U) +#define SYSCON_AHBMATPRIO_PRI_UTEAL_SBUS_SHIFT (6U) +#define SYSCON_AHBMATPRIO_PRI_UTEAL_SBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_UTEAL_SBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_UTEAL_SBUS_MASK) +#define SYSCON_AHBMATPRIO_PRI_USB_FS_MASK (0x300U) +#define SYSCON_AHBMATPRIO_PRI_USB_FS_SHIFT (8U) +#define SYSCON_AHBMATPRIO_PRI_USB_FS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USB_FS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USB_FS_MASK) +#define SYSCON_AHBMATPRIO_PRI_SDMA0_MASK (0xC00U) +#define SYSCON_AHBMATPRIO_PRI_SDMA0_SHIFT (10U) +#define SYSCON_AHBMATPRIO_PRI_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SDMA0_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SDMA0_MASK) +#define SYSCON_AHBMATPRIO_PRI_EZH_B_D_MASK (0x3000U) +#define SYSCON_AHBMATPRIO_PRI_EZH_B_D_SHIFT (12U) +#define SYSCON_AHBMATPRIO_PRI_EZH_B_D(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_EZH_B_D_SHIFT)) & SYSCON_AHBMATPRIO_PRI_EZH_B_D_MASK) +#define SYSCON_AHBMATPRIO_PRI_EZH_B_I_MASK (0xC000U) +#define SYSCON_AHBMATPRIO_PRI_EZH_B_I_SHIFT (14U) +#define SYSCON_AHBMATPRIO_PRI_EZH_B_I(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_EZH_B_I_SHIFT)) & SYSCON_AHBMATPRIO_PRI_EZH_B_I_MASK) +#define SYSCON_AHBMATPRIO_PRI_SDIO_MASK (0x30000U) +#define SYSCON_AHBMATPRIO_PRI_SDIO_SHIFT (16U) +#define SYSCON_AHBMATPRIO_PRI_SDIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SDIO_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SDIO_MASK) +#define SYSCON_AHBMATPRIO_PRI_PQ_MASK (0xC0000U) +#define SYSCON_AHBMATPRIO_PRI_PQ_SHIFT (18U) +#define SYSCON_AHBMATPRIO_PRI_PQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_PQ_SHIFT)) & SYSCON_AHBMATPRIO_PRI_PQ_MASK) +#define SYSCON_AHBMATPRIO_PRI_SHA2_MASK (0x300000U) +#define SYSCON_AHBMATPRIO_PRI_SHA2_SHIFT (20U) +#define SYSCON_AHBMATPRIO_PRI_SHA2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SHA2_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SHA2_MASK) +#define SYSCON_AHBMATPRIO_PRI_USB_HS_MASK (0xC00000U) +#define SYSCON_AHBMATPRIO_PRI_USB_HS_SHIFT (22U) +#define SYSCON_AHBMATPRIO_PRI_USB_HS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USB_HS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USB_HS_MASK) +#define SYSCON_AHBMATPRIO_PRI_SDMA1_MASK (0x3000000U) +#define SYSCON_AHBMATPRIO_PRI_SDMA1_SHIFT (24U) +#define SYSCON_AHBMATPRIO_PRI_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SDMA1_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SDMA1_MASK) +/*! @} */ + +/*! @name CPU0STCKCAL - System tick calibration for secure part of CPU0 */ +/*! @{ */ +#define SYSCON_CPU0STCKCAL_CAL_MASK (0xFFFFFFU) +#define SYSCON_CPU0STCKCAL_CAL_SHIFT (0U) +#define SYSCON_CPU0STCKCAL_CAL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0STCKCAL_CAL_SHIFT)) & SYSCON_CPU0STCKCAL_CAL_MASK) +#define SYSCON_CPU0STCKCAL_SKEW_MASK (0x1000000U) +#define SYSCON_CPU0STCKCAL_SKEW_SHIFT (24U) +#define SYSCON_CPU0STCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0STCKCAL_SKEW_SHIFT)) & SYSCON_CPU0STCKCAL_SKEW_MASK) +#define SYSCON_CPU0STCKCAL_NOREF_MASK (0x2000000U) +#define SYSCON_CPU0STCKCAL_NOREF_SHIFT (25U) +#define SYSCON_CPU0STCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0STCKCAL_NOREF_SHIFT)) & SYSCON_CPU0STCKCAL_NOREF_MASK) +/*! @} */ + +/*! @name CPU0NSTCKCAL - System tick calibration for non-secure part of CPU0 */ +/*! @{ */ +#define SYSCON_CPU0NSTCKCAL_CAL_MASK (0xFFFFFFU) +#define SYSCON_CPU0NSTCKCAL_CAL_SHIFT (0U) +#define SYSCON_CPU0NSTCKCAL_CAL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_CAL_SHIFT)) & SYSCON_CPU0NSTCKCAL_CAL_MASK) +#define SYSCON_CPU0NSTCKCAL_SKEW_MASK (0x1000000U) +#define SYSCON_CPU0NSTCKCAL_SKEW_SHIFT (24U) +#define SYSCON_CPU0NSTCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_SKEW_SHIFT)) & SYSCON_CPU0NSTCKCAL_SKEW_MASK) +#define SYSCON_CPU0NSTCKCAL_NOREF_MASK (0x2000000U) +#define SYSCON_CPU0NSTCKCAL_NOREF_SHIFT (25U) +#define SYSCON_CPU0NSTCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_NOREF_SHIFT)) & SYSCON_CPU0NSTCKCAL_NOREF_MASK) +/*! @} */ + +/*! @name CPU1TCKCAL - System tick calibration for CPU1 */ +/*! @{ */ +#define SYSCON_CPU1TCKCAL_CAL_MASK (0xFFFFFFU) +#define SYSCON_CPU1TCKCAL_CAL_SHIFT (0U) +#define SYSCON_CPU1TCKCAL_CAL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU1TCKCAL_CAL_SHIFT)) & SYSCON_CPU1TCKCAL_CAL_MASK) +#define SYSCON_CPU1TCKCAL_SKEW_MASK (0x1000000U) +#define SYSCON_CPU1TCKCAL_SKEW_SHIFT (24U) +#define SYSCON_CPU1TCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU1TCKCAL_SKEW_SHIFT)) & SYSCON_CPU1TCKCAL_SKEW_MASK) +#define SYSCON_CPU1TCKCAL_NOREF_MASK (0x2000000U) +#define SYSCON_CPU1TCKCAL_NOREF_SHIFT (25U) +#define SYSCON_CPU1TCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU1TCKCAL_NOREF_SHIFT)) & SYSCON_CPU1TCKCAL_NOREF_MASK) +/*! @} */ + +/*! @name NMISRC - NMI Source Select */ +/*! @{ */ +#define SYSCON_NMISRC_IRQCPU0_MASK (0x3FU) +#define SYSCON_NMISRC_IRQCPU0_SHIFT (0U) +#define SYSCON_NMISRC_IRQCPU0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQCPU0_SHIFT)) & SYSCON_NMISRC_IRQCPU0_MASK) +#define SYSCON_NMISRC_IRQCPU1_MASK (0x3F00U) +#define SYSCON_NMISRC_IRQCPU1_SHIFT (8U) +#define SYSCON_NMISRC_IRQCPU1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQCPU1_SHIFT)) & SYSCON_NMISRC_IRQCPU1_MASK) +#define SYSCON_NMISRC_NMIENCPU1_MASK (0x40000000U) +#define SYSCON_NMISRC_NMIENCPU1_SHIFT (30U) +#define SYSCON_NMISRC_NMIENCPU1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIENCPU1_SHIFT)) & SYSCON_NMISRC_NMIENCPU1_MASK) +#define SYSCON_NMISRC_NMIENCPU0_MASK (0x80000000U) +#define SYSCON_NMISRC_NMIENCPU0_SHIFT (31U) +#define SYSCON_NMISRC_NMIENCPU0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIENCPU0_SHIFT)) & SYSCON_NMISRC_NMIENCPU0_MASK) +/*! @} */ + +/*! @name PRESETCTRL0 - Peripheral reset control 0 */ +/*! @{ */ +#define SYSCON_PRESETCTRL0_ROM_RST_MASK (0x2U) +#define SYSCON_PRESETCTRL0_ROM_RST_SHIFT (1U) +/*! ROM_RST - ROM reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_ROM_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_ROM_RST_SHIFT)) & SYSCON_PRESETCTRL0_ROM_RST_MASK) +#define SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_MASK (0x8U) +#define SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_SHIFT (3U) +/*! SRAM_CTRL1_RST - SRAM Controller 1 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_SRAM_CTRL1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_SHIFT)) & SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_MASK) +#define SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_MASK (0x10U) +#define SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_SHIFT (4U) +/*! SRAM_CTRL2_RST - SRAM Controller 2 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_SRAM_CTRL2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_SHIFT)) & SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_MASK) +#define SYSCON_PRESETCTRL0_SRAM_CTRL3_RST_MASK (0x20U) +#define SYSCON_PRESETCTRL0_SRAM_CTRL3_RST_SHIFT (5U) +/*! SRAM_CTRL3_RST - SRAM Controller 3 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_SRAM_CTRL3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SRAM_CTRL3_RST_SHIFT)) & SYSCON_PRESETCTRL0_SRAM_CTRL3_RST_MASK) +#define SYSCON_PRESETCTRL0_SRAM_CTRL4_RST_MASK (0x40U) +#define SYSCON_PRESETCTRL0_SRAM_CTRL4_RST_SHIFT (6U) +/*! SRAM_CTRL4_RST - SRAM Controller 4 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_SRAM_CTRL4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SRAM_CTRL4_RST_SHIFT)) & SYSCON_PRESETCTRL0_SRAM_CTRL4_RST_MASK) +#define SYSCON_PRESETCTRL0_FLASH_RST_MASK (0x80U) +#define SYSCON_PRESETCTRL0_FLASH_RST_SHIFT (7U) +/*! FLASH_RST - Flash controller reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_FLASH_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_FLASH_RST_SHIFT)) & SYSCON_PRESETCTRL0_FLASH_RST_MASK) +#define SYSCON_PRESETCTRL0_FMC_RST_MASK (0x100U) +#define SYSCON_PRESETCTRL0_FMC_RST_SHIFT (8U) +/*! FMC_RST - FMC controller reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_FMC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_FMC_RST_SHIFT)) & SYSCON_PRESETCTRL0_FMC_RST_MASK) +#define SYSCON_PRESETCTRL0_MUX0_RST_MASK (0x800U) +#define SYSCON_PRESETCTRL0_MUX0_RST_SHIFT (11U) +/*! MUX0_RST - Input Mux 0 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_MUX0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_MUX0_RST_SHIFT)) & SYSCON_PRESETCTRL0_MUX0_RST_MASK) +#define SYSCON_PRESETCTRL0_IOCON_RST_MASK (0x2000U) +#define SYSCON_PRESETCTRL0_IOCON_RST_SHIFT (13U) +/*! IOCON_RST - I/O controller reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_IOCON_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_IOCON_RST_SHIFT)) & SYSCON_PRESETCTRL0_IOCON_RST_MASK) +#define SYSCON_PRESETCTRL0_GPIO0_RST_MASK (0x4000U) +#define SYSCON_PRESETCTRL0_GPIO0_RST_SHIFT (14U) +/*! GPIO0_RST - GPIO0 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_GPIO0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO0_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO0_RST_MASK) +#define SYSCON_PRESETCTRL0_GPIO1_RST_MASK (0x8000U) +#define SYSCON_PRESETCTRL0_GPIO1_RST_SHIFT (15U) +/*! GPIO1_RST - GPIO1 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_GPIO1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO1_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO1_RST_MASK) +#define SYSCON_PRESETCTRL0_GPIO2_RST_MASK (0x10000U) +#define SYSCON_PRESETCTRL0_GPIO2_RST_SHIFT (16U) +/*! GPIO2_RST - GPIO2 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_GPIO2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO2_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO2_RST_MASK) +#define SYSCON_PRESETCTRL0_GPIO3_RST_MASK (0x20000U) +#define SYSCON_PRESETCTRL0_GPIO3_RST_SHIFT (17U) +/*! GPIO3_RST - GPIO3 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_GPIO3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO3_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO3_RST_MASK) +#define SYSCON_PRESETCTRL0_PINT_RST_MASK (0x40000U) +#define SYSCON_PRESETCTRL0_PINT_RST_SHIFT (18U) +/*! PINT_RST - Pin interrupt (PINT) reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_PINT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_PINT_RST_SHIFT)) & SYSCON_PRESETCTRL0_PINT_RST_MASK) +#define SYSCON_PRESETCTRL0_GINT_RST_MASK (0x80000U) +#define SYSCON_PRESETCTRL0_GINT_RST_SHIFT (19U) +/*! GINT_RST - Group interrupt (GINT) reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_GINT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GINT_RST_SHIFT)) & SYSCON_PRESETCTRL0_GINT_RST_MASK) +#define SYSCON_PRESETCTRL0_DMA0_RST_MASK (0x100000U) +#define SYSCON_PRESETCTRL0_DMA0_RST_SHIFT (20U) +/*! DMA0_RST - DMA0 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_DMA0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_DMA0_RST_SHIFT)) & SYSCON_PRESETCTRL0_DMA0_RST_MASK) +#define SYSCON_PRESETCTRL0_CRCGEN_RST_MASK (0x200000U) +#define SYSCON_PRESETCTRL0_CRCGEN_RST_SHIFT (21U) +/*! CRCGEN_RST - CRCGEN reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_CRCGEN_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_CRCGEN_RST_SHIFT)) & SYSCON_PRESETCTRL0_CRCGEN_RST_MASK) +#define SYSCON_PRESETCTRL0_WWDT_RST_MASK (0x400000U) +#define SYSCON_PRESETCTRL0_WWDT_RST_SHIFT (22U) +/*! WWDT_RST - Watchdog Timer reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_WWDT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_WWDT_RST_SHIFT)) & SYSCON_PRESETCTRL0_WWDT_RST_MASK) +#define SYSCON_PRESETCTRL0_RTC_RST_MASK (0x800000U) +#define SYSCON_PRESETCTRL0_RTC_RST_SHIFT (23U) +/*! RTC_RST - Real Time Clock (RTC) reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_RTC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_RTC_RST_SHIFT)) & SYSCON_PRESETCTRL0_RTC_RST_MASK) +#define SYSCON_PRESETCTRL0_MAILBOX_RST_MASK (0x4000000U) +#define SYSCON_PRESETCTRL0_MAILBOX_RST_SHIFT (26U) +/*! MAILBOX_RST - Inter CPU communication Mailbox reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_MAILBOX_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_MAILBOX_RST_SHIFT)) & SYSCON_PRESETCTRL0_MAILBOX_RST_MASK) +#define SYSCON_PRESETCTRL0_ADC_RST_MASK (0x8000000U) +#define SYSCON_PRESETCTRL0_ADC_RST_SHIFT (27U) +/*! ADC_RST - ADC reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_ADC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_ADC_RST_SHIFT)) & SYSCON_PRESETCTRL0_ADC_RST_MASK) +/*! @} */ + +/*! @name PRESETCTRL1 - Peripheral reset control 1 */ +/*! @{ */ +#define SYSCON_PRESETCTRL1_MRT_RST_MASK (0x1U) +#define SYSCON_PRESETCTRL1_MRT_RST_SHIFT (0U) +/*! MRT_RST - MRT reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_MRT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_MRT_RST_SHIFT)) & SYSCON_PRESETCTRL1_MRT_RST_MASK) +#define SYSCON_PRESETCTRL1_OSTIMER0_RST_MASK (0x2U) +#define SYSCON_PRESETCTRL1_OSTIMER0_RST_SHIFT (1U) +/*! OSTIMER0_RST - OS Timer 0 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_OSTIMER0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_OSTIMER0_RST_SHIFT)) & SYSCON_PRESETCTRL1_OSTIMER0_RST_MASK) +#define SYSCON_PRESETCTRL1_SCT0_RST_MASK (0x4U) +#define SYSCON_PRESETCTRL1_SCT0_RST_SHIFT (2U) +/*! SCT0_RST - SCT0 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_SCT0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_SCT0_RST_SHIFT)) & SYSCON_PRESETCTRL1_SCT0_RST_MASK) +#define SYSCON_PRESETCTRL1_SCTIPU_RST_MASK (0x40U) +#define SYSCON_PRESETCTRL1_SCTIPU_RST_SHIFT (6U) +/*! SCTIPU_RST - SCTIPU reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_SCTIPU_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_SCTIPU_RST_SHIFT)) & SYSCON_PRESETCTRL1_SCTIPU_RST_MASK) +#define SYSCON_PRESETCTRL1_UTICK0_RST_MASK (0x400U) +#define SYSCON_PRESETCTRL1_UTICK0_RST_SHIFT (10U) +/*! UTICK0_RST - UTICK0 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_UTICK0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_UTICK0_RST_SHIFT)) & SYSCON_PRESETCTRL1_UTICK0_RST_MASK) +#define SYSCON_PRESETCTRL1_FC0_RST_MASK (0x800U) +#define SYSCON_PRESETCTRL1_FC0_RST_SHIFT (11U) +/*! FC0_RST - FC0 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_FC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC0_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC0_RST_MASK) +#define SYSCON_PRESETCTRL1_FC1_RST_MASK (0x1000U) +#define SYSCON_PRESETCTRL1_FC1_RST_SHIFT (12U) +/*! FC1_RST - FC1 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_FC1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC1_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC1_RST_MASK) +#define SYSCON_PRESETCTRL1_FC2_RST_MASK (0x2000U) +#define SYSCON_PRESETCTRL1_FC2_RST_SHIFT (13U) +/*! FC2_RST - FC2 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_FC2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC2_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC2_RST_MASK) +#define SYSCON_PRESETCTRL1_FC3_RST_MASK (0x4000U) +#define SYSCON_PRESETCTRL1_FC3_RST_SHIFT (14U) +/*! FC3_RST - FC3 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_FC3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC3_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC3_RST_MASK) +#define SYSCON_PRESETCTRL1_FC4_RST_MASK (0x8000U) +#define SYSCON_PRESETCTRL1_FC4_RST_SHIFT (15U) +/*! FC4_RST - FC4 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_FC4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC4_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC4_RST_MASK) +#define SYSCON_PRESETCTRL1_FC5_RST_MASK (0x10000U) +#define SYSCON_PRESETCTRL1_FC5_RST_SHIFT (16U) +/*! FC5_RST - FC5 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_FC5_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC5_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC5_RST_MASK) +#define SYSCON_PRESETCTRL1_FC6_RST_MASK (0x20000U) +#define SYSCON_PRESETCTRL1_FC6_RST_SHIFT (17U) +/*! FC6_RST - FC6 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_FC6_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC6_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC6_RST_MASK) +#define SYSCON_PRESETCTRL1_FC7_RST_MASK (0x40000U) +#define SYSCON_PRESETCTRL1_FC7_RST_SHIFT (18U) +/*! FC7_RST - FC7 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_FC7_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC7_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC7_RST_MASK) +#define SYSCON_PRESETCTRL1_TIMER2_RST_MASK (0x400000U) +#define SYSCON_PRESETCTRL1_TIMER2_RST_SHIFT (22U) +/*! TIMER2_RST - Timer 2 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_TIMER2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_TIMER2_RST_SHIFT)) & SYSCON_PRESETCTRL1_TIMER2_RST_MASK) +#define SYSCON_PRESETCTRL1_USB0_DEV_RST_MASK (0x2000000U) +#define SYSCON_PRESETCTRL1_USB0_DEV_RST_SHIFT (25U) +/*! USB0_DEV_RST - USB0 DEV reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_USB0_DEV_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_USB0_DEV_RST_SHIFT)) & SYSCON_PRESETCTRL1_USB0_DEV_RST_MASK) +#define SYSCON_PRESETCTRL1_TIMER0_RST_MASK (0x4000000U) +#define SYSCON_PRESETCTRL1_TIMER0_RST_SHIFT (26U) +/*! TIMER0_RST - Timer 0 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_TIMER0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_TIMER0_RST_SHIFT)) & SYSCON_PRESETCTRL1_TIMER0_RST_MASK) +#define SYSCON_PRESETCTRL1_TIMER1_RST_MASK (0x8000000U) +#define SYSCON_PRESETCTRL1_TIMER1_RST_SHIFT (27U) +/*! TIMER1_RST - Timer 1 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_TIMER1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_TIMER1_RST_SHIFT)) & SYSCON_PRESETCTRL1_TIMER1_RST_MASK) +#define SYSCON_PRESETCTRL1_PVT_RST_MASK (0x10000000U) +#define SYSCON_PRESETCTRL1_PVT_RST_SHIFT (28U) +/*! PVT_RST - PVT reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_PVT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_PVT_RST_SHIFT)) & SYSCON_PRESETCTRL1_PVT_RST_MASK) +#define SYSCON_PRESETCTRL1_EZHA_RST_MASK (0x40000000U) +#define SYSCON_PRESETCTRL1_EZHA_RST_SHIFT (30U) +/*! EZHA_RST - EZH a reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_EZHA_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_EZHA_RST_SHIFT)) & SYSCON_PRESETCTRL1_EZHA_RST_MASK) +#define SYSCON_PRESETCTRL1_EZHB_RST_MASK (0x80000000U) +#define SYSCON_PRESETCTRL1_EZHB_RST_SHIFT (31U) +/*! EZHB_RST - EZH b reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_EZHB_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_EZHB_RST_SHIFT)) & SYSCON_PRESETCTRL1_EZHB_RST_MASK) +/*! @} */ + +/*! @name PRESETCTRL2 - Peripheral reset control 2 */ +/*! @{ */ +#define SYSCON_PRESETCTRL2_DMA1_RST_MASK (0x2U) +#define SYSCON_PRESETCTRL2_DMA1_RST_SHIFT (1U) +/*! DMA1_RST - DMA1 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_DMA1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_DMA1_RST_SHIFT)) & SYSCON_PRESETCTRL2_DMA1_RST_MASK) +#define SYSCON_PRESETCTRL2_COMP_RST_MASK (0x4U) +#define SYSCON_PRESETCTRL2_COMP_RST_SHIFT (2U) +/*! COMP_RST - Comparator reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_COMP_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_COMP_RST_SHIFT)) & SYSCON_PRESETCTRL2_COMP_RST_MASK) +#define SYSCON_PRESETCTRL2_SDIO_RST_MASK (0x8U) +#define SYSCON_PRESETCTRL2_SDIO_RST_SHIFT (3U) +/*! SDIO_RST - SDIO reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_SDIO_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_SDIO_RST_SHIFT)) & SYSCON_PRESETCTRL2_SDIO_RST_MASK) +#define SYSCON_PRESETCTRL2_USB1_HOST_RST_MASK (0x10U) +#define SYSCON_PRESETCTRL2_USB1_HOST_RST_SHIFT (4U) +/*! USB1_HOST_RST - USB1 Host reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_USB1_HOST_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB1_HOST_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB1_HOST_RST_MASK) +#define SYSCON_PRESETCTRL2_USB1_DEV_RST_MASK (0x20U) +#define SYSCON_PRESETCTRL2_USB1_DEV_RST_SHIFT (5U) +/*! USB1_DEV_RST - USB1 dev reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_USB1_DEV_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB1_DEV_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB1_DEV_RST_MASK) +#define SYSCON_PRESETCTRL2_USB1_RAM_RST_MASK (0x40U) +#define SYSCON_PRESETCTRL2_USB1_RAM_RST_SHIFT (6U) +/*! USB1_RAM_RST - USB1 RAM reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_USB1_RAM_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB1_RAM_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB1_RAM_RST_MASK) +#define SYSCON_PRESETCTRL2_USB1_PHY_RST_MASK (0x80U) +#define SYSCON_PRESETCTRL2_USB1_PHY_RST_SHIFT (7U) +/*! USB1_PHY_RST - USB1 PHY reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_USB1_PHY_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB1_PHY_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB1_PHY_RST_MASK) +#define SYSCON_PRESETCTRL2_FREQME_RST_MASK (0x100U) +#define SYSCON_PRESETCTRL2_FREQME_RST_SHIFT (8U) +/*! FREQME_RST - Frequency meter reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_FREQME_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_FREQME_RST_SHIFT)) & SYSCON_PRESETCTRL2_FREQME_RST_MASK) +#define SYSCON_PRESETCTRL2_GPIO4_RST_MASK (0x200U) +#define SYSCON_PRESETCTRL2_GPIO4_RST_SHIFT (9U) +/*! GPIO4_RST - GPIO4 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_GPIO4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_GPIO4_RST_SHIFT)) & SYSCON_PRESETCTRL2_GPIO4_RST_MASK) +#define SYSCON_PRESETCTRL2_GPIO5_RST_MASK (0x400U) +#define SYSCON_PRESETCTRL2_GPIO5_RST_SHIFT (10U) +/*! GPIO5_RST - GPIO5 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_GPIO5_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_GPIO5_RST_SHIFT)) & SYSCON_PRESETCTRL2_GPIO5_RST_MASK) +#define SYSCON_PRESETCTRL2_OTP_RST_MASK (0x1000U) +#define SYSCON_PRESETCTRL2_OTP_RST_SHIFT (12U) +/*! OTP_RST - OTP reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_OTP_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_OTP_RST_SHIFT)) & SYSCON_PRESETCTRL2_OTP_RST_MASK) +#define SYSCON_PRESETCTRL2_RNG_RST_MASK (0x2000U) +#define SYSCON_PRESETCTRL2_RNG_RST_SHIFT (13U) +/*! RNG_RST - RNG reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_RNG_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_RNG_RST_SHIFT)) & SYSCON_PRESETCTRL2_RNG_RST_MASK) +#define SYSCON_PRESETCTRL2_MUX1_RST_MASK (0x4000U) +#define SYSCON_PRESETCTRL2_MUX1_RST_SHIFT (14U) +/*! MUX1_RST - Peripheral Input Mux 1 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_MUX1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_MUX1_RST_SHIFT)) & SYSCON_PRESETCTRL2_MUX1_RST_MASK) +#define SYSCON_PRESETCTRL2_USB0_HOSTM_RST_MASK (0x10000U) +#define SYSCON_PRESETCTRL2_USB0_HOSTM_RST_SHIFT (16U) +/*! USB0_HOSTM_RST - USB0 Host Master reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_USB0_HOSTM_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB0_HOSTM_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB0_HOSTM_RST_MASK) +#define SYSCON_PRESETCTRL2_USB0_HOSTS_RST_MASK (0x20000U) +#define SYSCON_PRESETCTRL2_USB0_HOSTS_RST_SHIFT (17U) +/*! USB0_HOSTS_RST - USB0 Host Slave reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_USB0_HOSTS_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB0_HOSTS_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB0_HOSTS_RST_MASK) +#define SYSCON_PRESETCTRL2_HASH0_RST_MASK (0x40000U) +#define SYSCON_PRESETCTRL2_HASH0_RST_SHIFT (18U) +/*! HASH0_RST - HASH0 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_HASH0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_HASH0_RST_SHIFT)) & SYSCON_PRESETCTRL2_HASH0_RST_MASK) +#define SYSCON_PRESETCTRL2_PQ_RST_MASK (0x80000U) +#define SYSCON_PRESETCTRL2_PQ_RST_SHIFT (19U) +/*! PQ_RST - Power Quad reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_PQ_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_PQ_RST_SHIFT)) & SYSCON_PRESETCTRL2_PQ_RST_MASK) +#define SYSCON_PRESETCTRL2_PLULUT_RST_MASK (0x100000U) +#define SYSCON_PRESETCTRL2_PLULUT_RST_SHIFT (20U) +/*! PLULUT_RST - PLU LUT reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_PLULUT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_PLULUT_RST_SHIFT)) & SYSCON_PRESETCTRL2_PLULUT_RST_MASK) +#define SYSCON_PRESETCTRL2_TIMER3_RST_MASK (0x200000U) +#define SYSCON_PRESETCTRL2_TIMER3_RST_SHIFT (21U) +/*! TIMER3_RST - Timer 3 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_TIMER3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_TIMER3_RST_SHIFT)) & SYSCON_PRESETCTRL2_TIMER3_RST_MASK) +#define SYSCON_PRESETCTRL2_TIMER4_RST_MASK (0x400000U) +#define SYSCON_PRESETCTRL2_TIMER4_RST_SHIFT (22U) +/*! TIMER4_RST - Timer 4 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_TIMER4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_TIMER4_RST_SHIFT)) & SYSCON_PRESETCTRL2_TIMER4_RST_MASK) +#define SYSCON_PRESETCTRL2_PUF_RST_MASK (0x800000U) +#define SYSCON_PRESETCTRL2_PUF_RST_SHIFT (23U) +/*! PUF_RST - PUF reset control reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_PUF_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_PUF_RST_SHIFT)) & SYSCON_PRESETCTRL2_PUF_RST_MASK) +#define SYSCON_PRESETCTRL2_CASPER_RST_MASK (0x1000000U) +#define SYSCON_PRESETCTRL2_CASPER_RST_SHIFT (24U) +/*! CASPER_RST - Casper reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_CASPER_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_CASPER_RST_SHIFT)) & SYSCON_PRESETCTRL2_CASPER_RST_MASK) +#define SYSCON_PRESETCTRL2_CAPT0_RST_MASK (0x2000000U) +#define SYSCON_PRESETCTRL2_CAPT0_RST_SHIFT (25U) +/*! CAPT0_RST - CAPT0 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_CAPT0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_CAPT0_RST_SHIFT)) & SYSCON_PRESETCTRL2_CAPT0_RST_MASK) +#define SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_MASK (0x8000000U) +#define SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_SHIFT (27U) +/*! ANALOG_CTRL_RST - analog control reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_ANALOG_CTRL_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_SHIFT)) & SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_MASK) +#define SYSCON_PRESETCTRL2_HS_LSPI_RST_MASK (0x10000000U) +#define SYSCON_PRESETCTRL2_HS_LSPI_RST_SHIFT (28U) +/*! HS_LSPI_RST - HS LSPI reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_HS_LSPI_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_HS_LSPI_RST_SHIFT)) & SYSCON_PRESETCTRL2_HS_LSPI_RST_MASK) +#define SYSCON_PRESETCTRL2_GPIO_SEC_RST_MASK (0x20000000U) +#define SYSCON_PRESETCTRL2_GPIO_SEC_RST_SHIFT (29U) +/*! GPIO_SEC_RST - GPIO secure reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_GPIO_SEC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_GPIO_SEC_RST_SHIFT)) & SYSCON_PRESETCTRL2_GPIO_SEC_RST_MASK) +#define SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST_MASK (0x40000000U) +#define SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST_SHIFT (30U) +/*! GPIO_SEC_INT_RST - GPIO secure int reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST_SHIFT)) & SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST_MASK) +/*! @} */ + +/*! @name PRESETCTRLX - Peripheral reset control register */ +/*! @{ */ +#define SYSCON_PRESETCTRLX_DATA_MASK (0xFFFFFFFFU) +#define SYSCON_PRESETCTRLX_DATA_SHIFT (0U) +#define SYSCON_PRESETCTRLX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLX_DATA_SHIFT)) & SYSCON_PRESETCTRLX_DATA_MASK) +/*! @} */ + +/* The count of SYSCON_PRESETCTRLX */ +#define SYSCON_PRESETCTRLX_COUNT (3U) + +/*! @name PRESETCTRLSET - Peripheral reset control set register */ +/*! @{ */ +#define SYSCON_PRESETCTRLSET_DATA_MASK (0xFFFFFFFFU) +#define SYSCON_PRESETCTRLSET_DATA_SHIFT (0U) +#define SYSCON_PRESETCTRLSET_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLSET_DATA_SHIFT)) & SYSCON_PRESETCTRLSET_DATA_MASK) +/*! @} */ + +/* The count of SYSCON_PRESETCTRLSET */ +#define SYSCON_PRESETCTRLSET_COUNT (3U) + +/*! @name PRESETCTRLCLR - Peripheral reset contro clearl register */ +/*! @{ */ +#define SYSCON_PRESETCTRLCLR_DATA_MASK (0xFFFFFFFFU) +#define SYSCON_PRESETCTRLCLR_DATA_SHIFT (0U) +#define SYSCON_PRESETCTRLCLR_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLCLR_DATA_SHIFT)) & SYSCON_PRESETCTRLCLR_DATA_MASK) +/*! @} */ + +/* The count of SYSCON_PRESETCTRLCLR */ +#define SYSCON_PRESETCTRLCLR_COUNT (3U) + +/*! @name SWR_RESET - generate a software_reset */ +/*! @{ */ +#define SYSCON_SWR_RESET_SWR_RESET_MASK (0xFFFFFFFFU) +#define SYSCON_SWR_RESET_SWR_RESET_SHIFT (0U) +/*! SWR_RESET - Write 0x5A00_0001 to generate a software_reset. + * 0b01011010000000000000000000000001..Generate a software reset. + * 0b00000000000000000000000000000000..Bloc is not reset. + */ +#define SYSCON_SWR_RESET_SWR_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SWR_RESET_SWR_RESET_SHIFT)) & SYSCON_SWR_RESET_SWR_RESET_MASK) +/*! @} */ + +/*! @name AHBCLKCTRL0 - AHB Clock control 0 */ +/*! @{ */ +#define SYSCON_AHBCLKCTRL0_ROM_MASK (0x2U) +#define SYSCON_AHBCLKCTRL0_ROM_SHIFT (1U) +/*! ROM - Enables the clock for the ROM. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_ROM_SHIFT)) & SYSCON_AHBCLKCTRL0_ROM_MASK) +#define SYSCON_AHBCLKCTRL0_SRAM_CTRL1_MASK (0x8U) +#define SYSCON_AHBCLKCTRL0_SRAM_CTRL1_SHIFT (3U) +/*! SRAM_CTRL1 - Enables the clock for the SRAM Controller 1. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_SRAM_CTRL1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL1_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL1_MASK) +#define SYSCON_AHBCLKCTRL0_SRAM_CTRL2_MASK (0x10U) +#define SYSCON_AHBCLKCTRL0_SRAM_CTRL2_SHIFT (4U) +/*! SRAM_CTRL2 - Enables the clock for the SRAM Controller 2. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_SRAM_CTRL2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL2_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL2_MASK) +#define SYSCON_AHBCLKCTRL0_SRAM_CTRL3_MASK (0x20U) +#define SYSCON_AHBCLKCTRL0_SRAM_CTRL3_SHIFT (5U) +/*! SRAM_CTRL3 - Enables the clock for the SRAM Controller 3. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_SRAM_CTRL3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL3_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL3_MASK) +#define SYSCON_AHBCLKCTRL0_SRAM_CTRL4_MASK (0x40U) +#define SYSCON_AHBCLKCTRL0_SRAM_CTRL4_SHIFT (6U) +/*! SRAM_CTRL4 - Enables the clock for the SRAM Controller 4. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_SRAM_CTRL4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL4_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL4_MASK) +#define SYSCON_AHBCLKCTRL0_FLASH_MASK (0x80U) +#define SYSCON_AHBCLKCTRL0_FLASH_SHIFT (7U) +/*! FLASH - Enables the clock for the Flash controller. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_FLASH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_FLASH_SHIFT)) & SYSCON_AHBCLKCTRL0_FLASH_MASK) +#define SYSCON_AHBCLKCTRL0_FMC_MASK (0x100U) +#define SYSCON_AHBCLKCTRL0_FMC_SHIFT (8U) +/*! FMC - Enables the clock for the FMC controller. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_FMC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_FMC_SHIFT)) & SYSCON_AHBCLKCTRL0_FMC_MASK) +#define SYSCON_AHBCLKCTRL0_MUX0_MASK (0x800U) +#define SYSCON_AHBCLKCTRL0_MUX0_SHIFT (11U) +/*! MUX0 - Enables the clock for the Input Mux 0. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_MUX0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_MUX0_SHIFT)) & SYSCON_AHBCLKCTRL0_MUX0_MASK) +#define SYSCON_AHBCLKCTRL0_IOCON_MASK (0x2000U) +#define SYSCON_AHBCLKCTRL0_IOCON_SHIFT (13U) +/*! IOCON - Enables the clock for the I/O controller. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_IOCON(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_IOCON_SHIFT)) & SYSCON_AHBCLKCTRL0_IOCON_MASK) +#define SYSCON_AHBCLKCTRL0_GPIO0_MASK (0x4000U) +#define SYSCON_AHBCLKCTRL0_GPIO0_SHIFT (14U) +/*! GPIO0 - Enables the clock for the GPIO0. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_GPIO0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO0_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO0_MASK) +#define SYSCON_AHBCLKCTRL0_GPIO1_MASK (0x8000U) +#define SYSCON_AHBCLKCTRL0_GPIO1_SHIFT (15U) +/*! GPIO1 - Enables the clock for the GPIO1. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_GPIO1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO1_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO1_MASK) +#define SYSCON_AHBCLKCTRL0_GPIO2_MASK (0x10000U) +#define SYSCON_AHBCLKCTRL0_GPIO2_SHIFT (16U) +/*! GPIO2 - Enables the clock for the GPIO2. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_GPIO2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO2_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO2_MASK) +#define SYSCON_AHBCLKCTRL0_GPIO3_MASK (0x20000U) +#define SYSCON_AHBCLKCTRL0_GPIO3_SHIFT (17U) +/*! GPIO3 - Enables the clock for the GPIO3. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_GPIO3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO3_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO3_MASK) +#define SYSCON_AHBCLKCTRL0_PINT_MASK (0x40000U) +#define SYSCON_AHBCLKCTRL0_PINT_SHIFT (18U) +/*! PINT - Enables the clock for the Pin interrupt (PINT). + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_PINT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_PINT_SHIFT)) & SYSCON_AHBCLKCTRL0_PINT_MASK) +#define SYSCON_AHBCLKCTRL0_GINT_MASK (0x80000U) +#define SYSCON_AHBCLKCTRL0_GINT_SHIFT (19U) +/*! GINT - Enables the clock for the Group interrupt (GINT). + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_GINT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GINT_SHIFT)) & SYSCON_AHBCLKCTRL0_GINT_MASK) +#define SYSCON_AHBCLKCTRL0_DMA0_MASK (0x100000U) +#define SYSCON_AHBCLKCTRL0_DMA0_SHIFT (20U) +/*! DMA0 - Enables the clock for the DMA0. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_DMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_DMA0_SHIFT)) & SYSCON_AHBCLKCTRL0_DMA0_MASK) +#define SYSCON_AHBCLKCTRL0_CRCGEN_MASK (0x200000U) +#define SYSCON_AHBCLKCTRL0_CRCGEN_SHIFT (21U) +/*! CRCGEN - Enables the clock for the CRCGEN. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_CRCGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_CRCGEN_SHIFT)) & SYSCON_AHBCLKCTRL0_CRCGEN_MASK) +#define SYSCON_AHBCLKCTRL0_WWDT_MASK (0x400000U) +#define SYSCON_AHBCLKCTRL0_WWDT_SHIFT (22U) +/*! WWDT - Enables the clock for the Watchdog Timer. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_WWDT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_WWDT_SHIFT)) & SYSCON_AHBCLKCTRL0_WWDT_MASK) +#define SYSCON_AHBCLKCTRL0_RTC_MASK (0x800000U) +#define SYSCON_AHBCLKCTRL0_RTC_SHIFT (23U) +/*! RTC - Enables the clock for the Real Time Clock (RTC). + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_RTC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_RTC_SHIFT)) & SYSCON_AHBCLKCTRL0_RTC_MASK) +#define SYSCON_AHBCLKCTRL0_MAILBOX_MASK (0x4000000U) +#define SYSCON_AHBCLKCTRL0_MAILBOX_SHIFT (26U) +/*! MAILBOX - Enables the clock for the Inter CPU communication Mailbox. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_MAILBOX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_MAILBOX_SHIFT)) & SYSCON_AHBCLKCTRL0_MAILBOX_MASK) +#define SYSCON_AHBCLKCTRL0_ADC_MASK (0x8000000U) +#define SYSCON_AHBCLKCTRL0_ADC_SHIFT (27U) +/*! ADC - Enables the clock for the ADC. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_ADC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_ADC_SHIFT)) & SYSCON_AHBCLKCTRL0_ADC_MASK) +/*! @} */ + +/*! @name AHBCLKCTRL1 - AHB Clock control 1 */ +/*! @{ */ +#define SYSCON_AHBCLKCTRL1_MRT_MASK (0x1U) +#define SYSCON_AHBCLKCTRL1_MRT_SHIFT (0U) +/*! MRT - Enables the clock for the MRT. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_MRT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_MRT_SHIFT)) & SYSCON_AHBCLKCTRL1_MRT_MASK) +#define SYSCON_AHBCLKCTRL1_OSTIMER0_MASK (0x2U) +#define SYSCON_AHBCLKCTRL1_OSTIMER0_SHIFT (1U) +/*! OSTIMER0 - Enables the clock for the OS Timer 0. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_OSTIMER0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_OSTIMER0_SHIFT)) & SYSCON_AHBCLKCTRL1_OSTIMER0_MASK) +#define SYSCON_AHBCLKCTRL1_SCT0_MASK (0x4U) +#define SYSCON_AHBCLKCTRL1_SCT0_SHIFT (2U) +/*! SCT0 - Enables the clock for the SCT0. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_SCT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_SCT0_SHIFT)) & SYSCON_AHBCLKCTRL1_SCT0_MASK) +#define SYSCON_AHBCLKCTRL1_SCTIPU_MASK (0x40U) +#define SYSCON_AHBCLKCTRL1_SCTIPU_SHIFT (6U) +/*! SCTIPU - Enables the clock for the SCTIPU. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_SCTIPU(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_SCTIPU_SHIFT)) & SYSCON_AHBCLKCTRL1_SCTIPU_MASK) +#define SYSCON_AHBCLKCTRL1_UTICK0_MASK (0x400U) +#define SYSCON_AHBCLKCTRL1_UTICK0_SHIFT (10U) +/*! UTICK0 - Enables the clock for the UTICK0. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_UTICK0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_UTICK0_SHIFT)) & SYSCON_AHBCLKCTRL1_UTICK0_MASK) +#define SYSCON_AHBCLKCTRL1_FC0_MASK (0x800U) +#define SYSCON_AHBCLKCTRL1_FC0_SHIFT (11U) +/*! FC0 - Enables the clock for the FC0. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_FC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC0_SHIFT)) & SYSCON_AHBCLKCTRL1_FC0_MASK) +#define SYSCON_AHBCLKCTRL1_FC1_MASK (0x1000U) +#define SYSCON_AHBCLKCTRL1_FC1_SHIFT (12U) +/*! FC1 - Enables the clock for the FC1. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_FC1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC1_SHIFT)) & SYSCON_AHBCLKCTRL1_FC1_MASK) +#define SYSCON_AHBCLKCTRL1_FC2_MASK (0x2000U) +#define SYSCON_AHBCLKCTRL1_FC2_SHIFT (13U) +/*! FC2 - Enables the clock for the FC2. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_FC2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC2_SHIFT)) & SYSCON_AHBCLKCTRL1_FC2_MASK) +#define SYSCON_AHBCLKCTRL1_FC3_MASK (0x4000U) +#define SYSCON_AHBCLKCTRL1_FC3_SHIFT (14U) +/*! FC3 - Enables the clock for the FC3. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_FC3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC3_SHIFT)) & SYSCON_AHBCLKCTRL1_FC3_MASK) +#define SYSCON_AHBCLKCTRL1_FC4_MASK (0x8000U) +#define SYSCON_AHBCLKCTRL1_FC4_SHIFT (15U) +/*! FC4 - Enables the clock for the FC4. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_FC4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC4_SHIFT)) & SYSCON_AHBCLKCTRL1_FC4_MASK) +#define SYSCON_AHBCLKCTRL1_FC5_MASK (0x10000U) +#define SYSCON_AHBCLKCTRL1_FC5_SHIFT (16U) +/*! FC5 - Enables the clock for the FC5. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_FC5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC5_SHIFT)) & SYSCON_AHBCLKCTRL1_FC5_MASK) +#define SYSCON_AHBCLKCTRL1_FC6_MASK (0x20000U) +#define SYSCON_AHBCLKCTRL1_FC6_SHIFT (17U) +/*! FC6 - Enables the clock for the FC6. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_FC6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC6_SHIFT)) & SYSCON_AHBCLKCTRL1_FC6_MASK) +#define SYSCON_AHBCLKCTRL1_FC7_MASK (0x40000U) +#define SYSCON_AHBCLKCTRL1_FC7_SHIFT (18U) +/*! FC7 - Enables the clock for the FC7. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_FC7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC7_SHIFT)) & SYSCON_AHBCLKCTRL1_FC7_MASK) +#define SYSCON_AHBCLKCTRL1_TIMER2_MASK (0x400000U) +#define SYSCON_AHBCLKCTRL1_TIMER2_SHIFT (22U) +/*! TIMER2 - Enables the clock for the Timer 2. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_TIMER2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_TIMER2_SHIFT)) & SYSCON_AHBCLKCTRL1_TIMER2_MASK) +#define SYSCON_AHBCLKCTRL1_USB0_DEV_MASK (0x2000000U) +#define SYSCON_AHBCLKCTRL1_USB0_DEV_SHIFT (25U) +/*! USB0_DEV - Enables the clock for the USB0 DEV. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_USB0_DEV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_USB0_DEV_SHIFT)) & SYSCON_AHBCLKCTRL1_USB0_DEV_MASK) +#define SYSCON_AHBCLKCTRL1_TIMER0_MASK (0x4000000U) +#define SYSCON_AHBCLKCTRL1_TIMER0_SHIFT (26U) +/*! TIMER0 - Enables the clock for the Timer 0. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_TIMER0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_TIMER0_SHIFT)) & SYSCON_AHBCLKCTRL1_TIMER0_MASK) +#define SYSCON_AHBCLKCTRL1_TIMER1_MASK (0x8000000U) +#define SYSCON_AHBCLKCTRL1_TIMER1_SHIFT (27U) +/*! TIMER1 - Enables the clock for the Timer 1. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_TIMER1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_TIMER1_SHIFT)) & SYSCON_AHBCLKCTRL1_TIMER1_MASK) +#define SYSCON_AHBCLKCTRL1_PVT_MASK (0x10000000U) +#define SYSCON_AHBCLKCTRL1_PVT_SHIFT (28U) +/*! PVT - Enables the clock for the PVT. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_PVT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_PVT_SHIFT)) & SYSCON_AHBCLKCTRL1_PVT_MASK) +#define SYSCON_AHBCLKCTRL1_EZHA_MASK (0x40000000U) +#define SYSCON_AHBCLKCTRL1_EZHA_SHIFT (30U) +/*! EZHA - Enables the clock for the EZH a. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_EZHA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_EZHA_SHIFT)) & SYSCON_AHBCLKCTRL1_EZHA_MASK) +#define SYSCON_AHBCLKCTRL1_EZHB_MASK (0x80000000U) +#define SYSCON_AHBCLKCTRL1_EZHB_SHIFT (31U) +/*! EZHB - Enables the clock for the EZH b. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_EZHB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_EZHB_SHIFT)) & SYSCON_AHBCLKCTRL1_EZHB_MASK) +/*! @} */ + +/*! @name AHBCLKCTRL2 - AHB Clock control 2 */ +/*! @{ */ +#define SYSCON_AHBCLKCTRL2_DMA1_MASK (0x2U) +#define SYSCON_AHBCLKCTRL2_DMA1_SHIFT (1U) +/*! DMA1 - Enables the clock for the DMA1. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_DMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_DMA1_SHIFT)) & SYSCON_AHBCLKCTRL2_DMA1_MASK) +#define SYSCON_AHBCLKCTRL2_COMP_MASK (0x4U) +#define SYSCON_AHBCLKCTRL2_COMP_SHIFT (2U) +/*! COMP - Enables the clock for the Comparator. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_COMP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_COMP_SHIFT)) & SYSCON_AHBCLKCTRL2_COMP_MASK) +#define SYSCON_AHBCLKCTRL2_SDIO_MASK (0x8U) +#define SYSCON_AHBCLKCTRL2_SDIO_SHIFT (3U) +/*! SDIO - Enables the clock for the SDIO. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_SDIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_SDIO_SHIFT)) & SYSCON_AHBCLKCTRL2_SDIO_MASK) +#define SYSCON_AHBCLKCTRL2_USB1_HOST_MASK (0x10U) +#define SYSCON_AHBCLKCTRL2_USB1_HOST_SHIFT (4U) +/*! USB1_HOST - Enables the clock for the USB1 Host. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_USB1_HOST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB1_HOST_SHIFT)) & SYSCON_AHBCLKCTRL2_USB1_HOST_MASK) +#define SYSCON_AHBCLKCTRL2_USB1_DEV_MASK (0x20U) +#define SYSCON_AHBCLKCTRL2_USB1_DEV_SHIFT (5U) +/*! USB1_DEV - Enables the clock for the USB1 dev. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_USB1_DEV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB1_DEV_SHIFT)) & SYSCON_AHBCLKCTRL2_USB1_DEV_MASK) +#define SYSCON_AHBCLKCTRL2_USB1_RAM_MASK (0x40U) +#define SYSCON_AHBCLKCTRL2_USB1_RAM_SHIFT (6U) +/*! USB1_RAM - Enables the clock for the USB1 RAM. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_USB1_RAM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB1_RAM_SHIFT)) & SYSCON_AHBCLKCTRL2_USB1_RAM_MASK) +#define SYSCON_AHBCLKCTRL2_USB1_PHY_MASK (0x80U) +#define SYSCON_AHBCLKCTRL2_USB1_PHY_SHIFT (7U) +/*! USB1_PHY - Enables the clock for the USB1 PHY. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_USB1_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB1_PHY_SHIFT)) & SYSCON_AHBCLKCTRL2_USB1_PHY_MASK) +#define SYSCON_AHBCLKCTRL2_FREQME_MASK (0x100U) +#define SYSCON_AHBCLKCTRL2_FREQME_SHIFT (8U) +/*! FREQME - Enables the clock for the Frequency meter. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_FREQME(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_FREQME_SHIFT)) & SYSCON_AHBCLKCTRL2_FREQME_MASK) +#define SYSCON_AHBCLKCTRL2_GPIO4_MASK (0x200U) +#define SYSCON_AHBCLKCTRL2_GPIO4_SHIFT (9U) +/*! GPIO4 - Enables the clock for the GPIO4. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_GPIO4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_GPIO4_SHIFT)) & SYSCON_AHBCLKCTRL2_GPIO4_MASK) +#define SYSCON_AHBCLKCTRL2_GPIO5_MASK (0x400U) +#define SYSCON_AHBCLKCTRL2_GPIO5_SHIFT (10U) +/*! GPIO5 - Enables the clock for the GPIO5. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_GPIO5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_GPIO5_SHIFT)) & SYSCON_AHBCLKCTRL2_GPIO5_MASK) +#define SYSCON_AHBCLKCTRL2_OTP_MASK (0x1000U) +#define SYSCON_AHBCLKCTRL2_OTP_SHIFT (12U) +/*! OTP - Enables the clock for the OTP. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_OTP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_OTP_SHIFT)) & SYSCON_AHBCLKCTRL2_OTP_MASK) +#define SYSCON_AHBCLKCTRL2_RNG_MASK (0x2000U) +#define SYSCON_AHBCLKCTRL2_RNG_SHIFT (13U) +/*! RNG - Enables the clock for the RNG. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_RNG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_RNG_SHIFT)) & SYSCON_AHBCLKCTRL2_RNG_MASK) +#define SYSCON_AHBCLKCTRL2_MUX1_MASK (0x4000U) +#define SYSCON_AHBCLKCTRL2_MUX1_SHIFT (14U) +/*! MUX1 - Enables the clock for the Peripheral Input Mux 1. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_MUX1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_MUX1_SHIFT)) & SYSCON_AHBCLKCTRL2_MUX1_MASK) +#define SYSCON_AHBCLKCTRL2_USB0_HOSTM_MASK (0x10000U) +#define SYSCON_AHBCLKCTRL2_USB0_HOSTM_SHIFT (16U) +/*! USB0_HOSTM - Enables the clock for the USB0 Host Master. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_USB0_HOSTM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB0_HOSTM_SHIFT)) & SYSCON_AHBCLKCTRL2_USB0_HOSTM_MASK) +#define SYSCON_AHBCLKCTRL2_USB0_HOSTS_MASK (0x20000U) +#define SYSCON_AHBCLKCTRL2_USB0_HOSTS_SHIFT (17U) +/*! USB0_HOSTS - Enables the clock for the USB0 Host Slave. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_USB0_HOSTS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB0_HOSTS_SHIFT)) & SYSCON_AHBCLKCTRL2_USB0_HOSTS_MASK) +#define SYSCON_AHBCLKCTRL2_HASH0_MASK (0x40000U) +#define SYSCON_AHBCLKCTRL2_HASH0_SHIFT (18U) +/*! HASH0 - Enables the clock for the HASH0. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_HASH0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_HASH0_SHIFT)) & SYSCON_AHBCLKCTRL2_HASH0_MASK) +#define SYSCON_AHBCLKCTRL2_PQ_MASK (0x80000U) +#define SYSCON_AHBCLKCTRL2_PQ_SHIFT (19U) +/*! PQ - Enables the clock for the Power Quad. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_PQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_PQ_SHIFT)) & SYSCON_AHBCLKCTRL2_PQ_MASK) +#define SYSCON_AHBCLKCTRL2_PLULUT_MASK (0x100000U) +#define SYSCON_AHBCLKCTRL2_PLULUT_SHIFT (20U) +/*! PLULUT - Enables the clock for the PLU LUT. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_PLULUT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_PLULUT_SHIFT)) & SYSCON_AHBCLKCTRL2_PLULUT_MASK) +#define SYSCON_AHBCLKCTRL2_TIMER3_MASK (0x200000U) +#define SYSCON_AHBCLKCTRL2_TIMER3_SHIFT (21U) +/*! TIMER3 - Enables the clock for the Timer 3. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_TIMER3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_TIMER3_SHIFT)) & SYSCON_AHBCLKCTRL2_TIMER3_MASK) +#define SYSCON_AHBCLKCTRL2_TIMER4_MASK (0x400000U) +#define SYSCON_AHBCLKCTRL2_TIMER4_SHIFT (22U) +/*! TIMER4 - Enables the clock for the Timer 4. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_TIMER4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_TIMER4_SHIFT)) & SYSCON_AHBCLKCTRL2_TIMER4_MASK) +#define SYSCON_AHBCLKCTRL2_PUF_MASK (0x800000U) +#define SYSCON_AHBCLKCTRL2_PUF_SHIFT (23U) +/*! PUF - Enables the clock for the PUF reset control. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_PUF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_PUF_SHIFT)) & SYSCON_AHBCLKCTRL2_PUF_MASK) +#define SYSCON_AHBCLKCTRL2_CASPER_MASK (0x1000000U) +#define SYSCON_AHBCLKCTRL2_CASPER_SHIFT (24U) +/*! CASPER - Enables the clock for the Casper. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_CASPER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_CASPER_SHIFT)) & SYSCON_AHBCLKCTRL2_CASPER_MASK) +#define SYSCON_AHBCLKCTRL2_CAPT0_MASK (0x2000000U) +#define SYSCON_AHBCLKCTRL2_CAPT0_SHIFT (25U) +/*! CAPT0 - Enables the clock for the CAPT0. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_CAPT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_CAPT0_SHIFT)) & SYSCON_AHBCLKCTRL2_CAPT0_MASK) +#define SYSCON_AHBCLKCTRL2_ANALOG_CTRL_MASK (0x8000000U) +#define SYSCON_AHBCLKCTRL2_ANALOG_CTRL_SHIFT (27U) +/*! ANALOG_CTRL - Enables the clock for the analog control. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_ANALOG_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_ANALOG_CTRL_SHIFT)) & SYSCON_AHBCLKCTRL2_ANALOG_CTRL_MASK) +#define SYSCON_AHBCLKCTRL2_HS_LSPI_MASK (0x10000000U) +#define SYSCON_AHBCLKCTRL2_HS_LSPI_SHIFT (28U) +/*! HS_LSPI - Enables the clock for the HS LSPI. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_HS_LSPI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_HS_LSPI_SHIFT)) & SYSCON_AHBCLKCTRL2_HS_LSPI_MASK) +#define SYSCON_AHBCLKCTRL2_GPIO_SEC_MASK (0x20000000U) +#define SYSCON_AHBCLKCTRL2_GPIO_SEC_SHIFT (29U) +/*! GPIO_SEC - Enables the clock for the GPIO secure. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_GPIO_SEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_GPIO_SEC_SHIFT)) & SYSCON_AHBCLKCTRL2_GPIO_SEC_MASK) +#define SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_MASK (0x40000000U) +#define SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_SHIFT (30U) +/*! GPIO_SEC_INT - Enables the clock for the GPIO secure int. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_GPIO_SEC_INT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_SHIFT)) & SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_MASK) +/*! @} */ + +/*! @name AHBCLKCTRLX - Peripheral reset control register */ +/*! @{ */ +#define SYSCON_AHBCLKCTRLX_DATA_MASK (0xFFFFFFFFU) +#define SYSCON_AHBCLKCTRLX_DATA_SHIFT (0U) +#define SYSCON_AHBCLKCTRLX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLX_DATA_SHIFT)) & SYSCON_AHBCLKCTRLX_DATA_MASK) +/*! @} */ + +/* The count of SYSCON_AHBCLKCTRLX */ +#define SYSCON_AHBCLKCTRLX_COUNT (3U) + +/*! @name AHBCLKCTRLSET - Peripheral reset control register */ +/*! @{ */ +#define SYSCON_AHBCLKCTRLSET_DATA_MASK (0xFFFFFFFFU) +#define SYSCON_AHBCLKCTRLSET_DATA_SHIFT (0U) +#define SYSCON_AHBCLKCTRLSET_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLSET_DATA_SHIFT)) & SYSCON_AHBCLKCTRLSET_DATA_MASK) +/*! @} */ + +/* The count of SYSCON_AHBCLKCTRLSET */ +#define SYSCON_AHBCLKCTRLSET_COUNT (3U) + +/*! @name AHBCLKCTRLCLR - Peripheral reset control register */ +/*! @{ */ +#define SYSCON_AHBCLKCTRLCLR_DATA_MASK (0xFFFFFFFFU) +#define SYSCON_AHBCLKCTRLCLR_DATA_SHIFT (0U) +#define SYSCON_AHBCLKCTRLCLR_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLCLR_DATA_SHIFT)) & SYSCON_AHBCLKCTRLCLR_DATA_MASK) +/*! @} */ + +/* The count of SYSCON_AHBCLKCTRLCLR */ +#define SYSCON_AHBCLKCTRLCLR_COUNT (3U) + +/*! @name SYSTICKCLKSEL0 - System Tick Timer for CPU0 source select */ +/*! @{ */ +#define SYSCON_SYSTICKCLKSEL0_SEL_MASK (0x7U) +#define SYSCON_SYSTICKCLKSEL0_SEL_SHIFT (0U) +/*! SEL - System Tick Timer for CPU0 source select. + * 0b000..System Tick 0 divided clock. + * 0b001..FRO 1MHz clock. + * 0b010..Oscillator 32 kHz clock. + * 0b011..No clock. + * 0b100..No clock. + * 0b101..No clock. + * 0b110..No clock. + * 0b111..No clock. + */ +#define SYSCON_SYSTICKCLKSEL0_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKSEL0_SEL_SHIFT)) & SYSCON_SYSTICKCLKSEL0_SEL_MASK) +/*! @} */ + +/*! @name SYSTICKCLKSEL1 - System Tick Timer for CPU1 source select */ +/*! @{ */ +#define SYSCON_SYSTICKCLKSEL1_SEL_MASK (0x7U) +#define SYSCON_SYSTICKCLKSEL1_SEL_SHIFT (0U) +/*! SEL - System Tick Timer for CPU1 source select. + * 0b000..System Tick 1 divided clock. + * 0b001..FRO 1MHz clock. + * 0b010..Oscillator 32 kHz clock. + * 0b011..No clock. + * 0b100..No clock. + * 0b101..No clock. + * 0b110..No clock. + * 0b111..No clock. + */ +#define SYSCON_SYSTICKCLKSEL1_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKSEL1_SEL_SHIFT)) & SYSCON_SYSTICKCLKSEL1_SEL_MASK) +/*! @} */ + +/*! @name SYSTICKCLKSELX - Peripheral reset control register */ +/*! @{ */ +#define SYSCON_SYSTICKCLKSELX_DATA_MASK (0xFFFFFFFFU) +#define SYSCON_SYSTICKCLKSELX_DATA_SHIFT (0U) +#define SYSCON_SYSTICKCLKSELX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKSELX_DATA_SHIFT)) & SYSCON_SYSTICKCLKSELX_DATA_MASK) +/*! @} */ + +/* The count of SYSCON_SYSTICKCLKSELX */ +#define SYSCON_SYSTICKCLKSELX_COUNT (2U) + +/*! @name TRACECLKSEL - Trace clock source select */ +/*! @{ */ +#define SYSCON_TRACECLKSEL_SEL_MASK (0x7U) +#define SYSCON_TRACECLKSEL_SEL_SHIFT (0U) +/*! SEL - Trace clock source select. + * 0b000..Trace divided clock. + * 0b001..FRO 1MHz clock. + * 0b010..Oscillator 32 kHz clock. + * 0b011..No clock. + * 0b100..No clock. + * 0b101..No clock. + * 0b110..No clock. + * 0b111..No clock. + */ +#define SYSCON_TRACECLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKSEL_SEL_SHIFT)) & SYSCON_TRACECLKSEL_SEL_MASK) +/*! @} */ + +/*! @name CTIMERCLKSEL0 - CTimer 0 clock source select */ +/*! @{ */ +#define SYSCON_CTIMERCLKSEL0_SEL_MASK (0x7U) +#define SYSCON_CTIMERCLKSEL0_SEL_SHIFT (0U) +/*! SEL - CTimer 0 clock source select. + * 0b000..Main clock. + * 0b001..PLL0 clock. + * 0b010..No clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32kHz clock. + * 0b111..No clock. + */ +#define SYSCON_CTIMERCLKSEL0_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL0_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL0_SEL_MASK) +/*! @} */ + +/*! @name CTIMERCLKSEL1 - CTimer 1 clock source select */ +/*! @{ */ +#define SYSCON_CTIMERCLKSEL1_SEL_MASK (0x7U) +#define SYSCON_CTIMERCLKSEL1_SEL_SHIFT (0U) +/*! SEL - CTimer 1 clock source select. + * 0b000..Main clock. + * 0b001..PLL0 clock. + * 0b010..No clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32kHz clock. + * 0b111..No clock. + */ +#define SYSCON_CTIMERCLKSEL1_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL1_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL1_SEL_MASK) +/*! @} */ + +/*! @name CTIMERCLKSEL2 - CTimer 2 clock source select */ +/*! @{ */ +#define SYSCON_CTIMERCLKSEL2_SEL_MASK (0x7U) +#define SYSCON_CTIMERCLKSEL2_SEL_SHIFT (0U) +/*! SEL - CTimer 2 clock source select. + * 0b000..Main clock. + * 0b001..PLL0 clock. + * 0b010..No clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32kHz clock. + * 0b111..No clock. + */ +#define SYSCON_CTIMERCLKSEL2_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL2_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL2_SEL_MASK) +/*! @} */ + +/*! @name CTIMERCLKSEL3 - CTimer 3 clock source select */ +/*! @{ */ +#define SYSCON_CTIMERCLKSEL3_SEL_MASK (0x7U) +#define SYSCON_CTIMERCLKSEL3_SEL_SHIFT (0U) +/*! SEL - CTimer 3 clock source select. + * 0b000..Main clock. + * 0b001..PLL0 clock. + * 0b010..No clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32kHz clock. + * 0b111..No clock. + */ +#define SYSCON_CTIMERCLKSEL3_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL3_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL3_SEL_MASK) +/*! @} */ + +/*! @name CTIMERCLKSEL4 - CTimer 4 clock source select */ +/*! @{ */ +#define SYSCON_CTIMERCLKSEL4_SEL_MASK (0x7U) +#define SYSCON_CTIMERCLKSEL4_SEL_SHIFT (0U) +/*! SEL - CTimer 4 clock source select. + * 0b000..Main clock. + * 0b001..PLL0 clock. + * 0b010..No clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32kHz clock. + * 0b111..No clock. + */ +#define SYSCON_CTIMERCLKSEL4_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL4_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL4_SEL_MASK) +/*! @} */ + +/*! @name CTIMERCLKSELX - Peripheral reset control register */ +/*! @{ */ +#define SYSCON_CTIMERCLKSELX_DATA_MASK (0xFFFFFFFFU) +#define SYSCON_CTIMERCLKSELX_DATA_SHIFT (0U) +#define SYSCON_CTIMERCLKSELX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSELX_DATA_SHIFT)) & SYSCON_CTIMERCLKSELX_DATA_MASK) +/*! @} */ + +/* The count of SYSCON_CTIMERCLKSELX */ +#define SYSCON_CTIMERCLKSELX_COUNT (5U) + +/*! @name MAINCLKSELA - Main clock A source select */ +/*! @{ */ +#define SYSCON_MAINCLKSELA_SEL_MASK (0x7U) +#define SYSCON_MAINCLKSELA_SEL_SHIFT (0U) +/*! SEL - Main clock A source select. + * 0b000..FRO 12 MHz clock. + * 0b001..CLKIN clock. + * 0b010..FRO 1MHz clock. + * 0b011..FRO 96 MHz clock. + * 0b100..No clock. + * 0b101..No clock. + * 0b110..No clock. + * 0b111..No clock. + */ +#define SYSCON_MAINCLKSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELA_SEL_SHIFT)) & SYSCON_MAINCLKSELA_SEL_MASK) +/*! @} */ + +/*! @name MAINCLKSELB - Main clock source select */ +/*! @{ */ +#define SYSCON_MAINCLKSELB_SEL_MASK (0x7U) +#define SYSCON_MAINCLKSELB_SEL_SHIFT (0U) +/*! SEL - Main clock source select. + * 0b000..Main Clock A. + * 0b001..PLL0 clock. + * 0b010..PLL1 clock. + * 0b011..Oscillator 32 kHz clock. + * 0b100..No clock. + * 0b101..No clock. + * 0b110..No clock. + * 0b111..No clock. + */ +#define SYSCON_MAINCLKSELB_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELB_SEL_SHIFT)) & SYSCON_MAINCLKSELB_SEL_MASK) +/*! @} */ + +/*! @name CLKOUTSEL - CLKOUT clock source select */ +/*! @{ */ +#define SYSCON_CLKOUTSEL_SEL_MASK (0x7U) +#define SYSCON_CLKOUTSEL_SEL_SHIFT (0U) +/*! SEL - CLKOUT clock source select. + * 0b000..Main clock. + * 0b001..PLL0 clock. + * 0b010..CLKIN clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..PLL1 clock. + * 0b110..Oscillator 32kHz clock. + * 0b111..No clock. + */ +#define SYSCON_CLKOUTSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTSEL_SEL_SHIFT)) & SYSCON_CLKOUTSEL_SEL_MASK) +/*! @} */ + +/*! @name PLL0CLKSEL - PLL0 clock source select */ +/*! @{ */ +#define SYSCON_PLL0CLKSEL_SEL_MASK (0x7U) +#define SYSCON_PLL0CLKSEL_SEL_SHIFT (0U) +/*! SEL - PLL0 clock source select. + * 0b000..FRO 12 MHz clock. + * 0b001..CLKIN clock. + * 0b010..FRO 1MHz clock. + * 0b011..Oscillator 32kHz clock. + * 0b100..No clock. + * 0b101..No clock. + * 0b110..No clock. + * 0b111..No clock. + */ +#define SYSCON_PLL0CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKSEL_SEL_SHIFT)) & SYSCON_PLL0CLKSEL_SEL_MASK) +/*! @} */ + +/*! @name PLL1CLKSEL - PLL1 clock source select */ +/*! @{ */ +#define SYSCON_PLL1CLKSEL_SEL_MASK (0x7U) +#define SYSCON_PLL1CLKSEL_SEL_SHIFT (0U) +/*! SEL - PLL1 clock source select. + * 0b000..FRO 12 MHz clock. + * 0b001..CLKIN clock. + * 0b010..FRO 1MHz clock. + * 0b011..Oscillator 32kHz clock. + * 0b100..No clock. + * 0b101..No clock. + * 0b110..No clock. + * 0b111..No clock. + */ +#define SYSCON_PLL1CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CLKSEL_SEL_SHIFT)) & SYSCON_PLL1CLKSEL_SEL_MASK) +/*! @} */ + +/*! @name ADCCLKSEL - ADC clock source select */ +/*! @{ */ +#define SYSCON_ADCCLKSEL_SEL_MASK (0x7U) +#define SYSCON_ADCCLKSEL_SEL_SHIFT (0U) +/*! SEL - ADC clock source select. + * 0b000..Main clock. + * 0b001..PLL0 clock. + * 0b010..FRO 96 MHz clock. + * 0b011..No clock. + * 0b100..No clock. + * 0b101..No clock. + * 0b110..No clock. + * 0b111..No clock. + */ +#define SYSCON_ADCCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKSEL_SEL_SHIFT)) & SYSCON_ADCCLKSEL_SEL_MASK) +/*! @} */ + +/*! @name USB0CLKSEL - FS USB clock source select */ +/*! @{ */ +#define SYSCON_USB0CLKSEL_SEL_MASK (0x7U) +#define SYSCON_USB0CLKSEL_SEL_SHIFT (0U) +/*! SEL - FS USB clock source select. + * 0b000..Main clock. + * 0b001..PLL0 clock. + * 0b010..No clock. + * 0b011..FRO 96 MHz clock. + * 0b100..No clock. + * 0b101..PLL1 clock. + * 0b110..No clock. + * 0b111..No clock. + */ +#define SYSCON_USB0CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKSEL_SEL_SHIFT)) & SYSCON_USB0CLKSEL_SEL_MASK) +/*! @} */ + +/*! @name USB1CLKSEL - HS USB clock source select - NOT USED */ +/*! @{ */ +#define SYSCON_USB1CLKSEL_SEL_MASK (0x7U) +#define SYSCON_USB1CLKSEL_SEL_SHIFT (0U) +/*! SEL - HS USB clock source select. + * 0b000..Main clock. + * 0b001..PLL0 clock. + * 0b010..CLKIN clock. + * 0b011..No clock. + * 0b100..No clock. + * 0b101..PLL1 clock. + * 0b110..No clock. + * 0b111..No clock. + */ +#define SYSCON_USB1CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKSEL_SEL_SHIFT)) & SYSCON_USB1CLKSEL_SEL_MASK) +/*! @} */ + +/*! @name FCCLKSEL0 - Flexcomm Interface 0 clock source select for Fractional Rate Divider */ +/*! @{ */ +#define SYSCON_FCCLKSEL0_SEL_MASK (0x7U) +#define SYSCON_FCCLKSEL0_SEL_SHIFT (0U) +/*! SEL - Flexcomm Interface 0 clock source select for Fractional Rate Divider. + * 0b000..Main clock. + * 0b001..system PLL divided clock. + * 0b010..FRO 12 MHz clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32 kHz clock. + * 0b111..No clock. + */ +#define SYSCON_FCCLKSEL0_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL0_SEL_SHIFT)) & SYSCON_FCCLKSEL0_SEL_MASK) +/*! @} */ + +/*! @name FCCLKSEL1 - Flexcomm Interface 1 clock source select for Fractional Rate Divider */ +/*! @{ */ +#define SYSCON_FCCLKSEL1_SEL_MASK (0x7U) +#define SYSCON_FCCLKSEL1_SEL_SHIFT (0U) +/*! SEL - Flexcomm Interface 1 clock source select for Fractional Rate Divider. + * 0b000..Main clock. + * 0b001..system PLL divided clock. + * 0b010..FRO 12 MHz clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32 kHz clock. + * 0b111..No clock. + */ +#define SYSCON_FCCLKSEL1_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL1_SEL_SHIFT)) & SYSCON_FCCLKSEL1_SEL_MASK) +/*! @} */ + +/*! @name FCCLKSEL2 - Flexcomm Interface 2 clock source select for Fractional Rate Divider */ +/*! @{ */ +#define SYSCON_FCCLKSEL2_SEL_MASK (0x7U) +#define SYSCON_FCCLKSEL2_SEL_SHIFT (0U) +/*! SEL - Flexcomm Interface 2 clock source select for Fractional Rate Divider. + * 0b000..Main clock. + * 0b001..system PLL divided clock. + * 0b010..FRO 12 MHz clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32 kHz clock. + * 0b111..No clock. + */ +#define SYSCON_FCCLKSEL2_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL2_SEL_SHIFT)) & SYSCON_FCCLKSEL2_SEL_MASK) +/*! @} */ + +/*! @name FCCLKSEL3 - Flexcomm Interface 3 clock source select for Fractional Rate Divider */ +/*! @{ */ +#define SYSCON_FCCLKSEL3_SEL_MASK (0x7U) +#define SYSCON_FCCLKSEL3_SEL_SHIFT (0U) +/*! SEL - Flexcomm Interface 3 clock source select for Fractional Rate Divider. + * 0b000..Main clock. + * 0b001..system PLL divided clock. + * 0b010..FRO 12 MHz clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32 kHz clock. + * 0b111..No clock. + */ +#define SYSCON_FCCLKSEL3_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL3_SEL_SHIFT)) & SYSCON_FCCLKSEL3_SEL_MASK) +/*! @} */ + +/*! @name FCCLKSEL4 - Flexcomm Interface 4 clock source select for Fractional Rate Divider */ +/*! @{ */ +#define SYSCON_FCCLKSEL4_SEL_MASK (0x7U) +#define SYSCON_FCCLKSEL4_SEL_SHIFT (0U) +/*! SEL - Flexcomm Interface 4 clock source select for Fractional Rate Divider. + * 0b000..Main clock. + * 0b001..system PLL divided clock. + * 0b010..FRO 12 MHz clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32 kHz clock. + * 0b111..No clock. + */ +#define SYSCON_FCCLKSEL4_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL4_SEL_SHIFT)) & SYSCON_FCCLKSEL4_SEL_MASK) +/*! @} */ + +/*! @name FCCLKSEL5 - Flexcomm Interface 5 clock source select for Fractional Rate Divider */ +/*! @{ */ +#define SYSCON_FCCLKSEL5_SEL_MASK (0x7U) +#define SYSCON_FCCLKSEL5_SEL_SHIFT (0U) +/*! SEL - Flexcomm Interface 5 clock source select for Fractional Rate Divider. + * 0b000..Main clock. + * 0b001..system PLL divided clock. + * 0b010..FRO 12 MHz clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32 kHz clock. + * 0b111..No clock. + */ +#define SYSCON_FCCLKSEL5_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL5_SEL_SHIFT)) & SYSCON_FCCLKSEL5_SEL_MASK) +/*! @} */ + +/*! @name FCCLKSEL6 - Flexcomm Interface 6 clock source select for Fractional Rate Divider */ +/*! @{ */ +#define SYSCON_FCCLKSEL6_SEL_MASK (0x7U) +#define SYSCON_FCCLKSEL6_SEL_SHIFT (0U) +/*! SEL - Flexcomm Interface 6 clock source select for Fractional Rate Divider. + * 0b000..Main clock. + * 0b001..system PLL divided clock. + * 0b010..FRO 12 MHz clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32 kHz clock. + * 0b111..No clock. + */ +#define SYSCON_FCCLKSEL6_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL6_SEL_SHIFT)) & SYSCON_FCCLKSEL6_SEL_MASK) +/*! @} */ + +/*! @name FCCLKSEL7 - Flexcomm Interface 7 clock source select for Fractional Rate Divider */ +/*! @{ */ +#define SYSCON_FCCLKSEL7_SEL_MASK (0x7U) +#define SYSCON_FCCLKSEL7_SEL_SHIFT (0U) +/*! SEL - Flexcomm Interface 7 clock source select for Fractional Rate Divider. + * 0b000..Main clock. + * 0b001..system PLL divided clock. + * 0b010..FRO 12 MHz clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32 kHz clock. + * 0b111..No clock. + */ +#define SYSCON_FCCLKSEL7_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL7_SEL_SHIFT)) & SYSCON_FCCLKSEL7_SEL_MASK) +/*! @} */ + +/*! @name FCCLKSELX - Peripheral reset control register */ +/*! @{ */ +#define SYSCON_FCCLKSELX_DATA_MASK (0xFFFFFFFFU) +#define SYSCON_FCCLKSELX_DATA_SHIFT (0U) +#define SYSCON_FCCLKSELX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSELX_DATA_SHIFT)) & SYSCON_FCCLKSELX_DATA_MASK) +/*! @} */ + +/* The count of SYSCON_FCCLKSELX */ +#define SYSCON_FCCLKSELX_COUNT (8U) + +/*! @name HSLSPICLKSEL - HS LSPI clock source select */ +/*! @{ */ +#define SYSCON_HSLSPICLKSEL_SEL_MASK (0x7U) +#define SYSCON_HSLSPICLKSEL_SEL_SHIFT (0U) +/*! SEL - HS LSPI clock source select. + * 0b000..Main clock. + * 0b001..system PLL divided clock. + * 0b010..FRO 12 MHz clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..No clock. + * 0b110..Oscillator 32 kHz clock. + * 0b111..No clock. + */ +#define SYSCON_HSLSPICLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HSLSPICLKSEL_SEL_SHIFT)) & SYSCON_HSLSPICLKSEL_SEL_MASK) +/*! @} */ + +/*! @name MCLKCLKSEL - MCLK clock source select */ +/*! @{ */ +#define SYSCON_MCLKCLKSEL_SEL_MASK (0x7U) +#define SYSCON_MCLKCLKSEL_SEL_SHIFT (0U) +/*! SEL - MCLK clock source select. + * 0b000..FRO 96 MHz clock. + * 0b001..PLL0 clock. + * 0b010..No clock. + * 0b011..No clock. + * 0b100..No clock. + * 0b101..No clock. + * 0b110..No clock. + * 0b111..No clock. + */ +#define SYSCON_MCLKCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKCLKSEL_SEL_SHIFT)) & SYSCON_MCLKCLKSEL_SEL_MASK) +/*! @} */ + +/*! @name SCTCLKSEL - SCTimer/PWM clock source select */ +/*! @{ */ +#define SYSCON_SCTCLKSEL_SEL_MASK (0x7U) +#define SYSCON_SCTCLKSEL_SEL_SHIFT (0U) +/*! SEL - SCTimer/PWM clock source select. + * 0b000..Main clock. + * 0b001..PLL0 clock. + * 0b010..CLKIN clock. + * 0b011..FRO 96 MHz clock. + * 0b100..No clock. + * 0b101..MCLK clock. + * 0b110..No clock. + * 0b111..No clock. + */ +#define SYSCON_SCTCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKSEL_SEL_SHIFT)) & SYSCON_SCTCLKSEL_SEL_MASK) +/*! @} */ + +/*! @name SDIOCLKSEL - SDIO clock source select */ +/*! @{ */ +#define SYSCON_SDIOCLKSEL_SEL_MASK (0x7U) +#define SYSCON_SDIOCLKSEL_SEL_SHIFT (0U) +/*! SEL - SDIO clock source select. + * 0b000..Main clock. + * 0b001..PLL0 clock. + * 0b010..No clock. + * 0b011..FRO 96 MHz clock. + * 0b100..No clock. + * 0b101..PLL1 clock. + * 0b110..No clock. + * 0b111..No clock. + */ +#define SYSCON_SDIOCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKSEL_SEL_SHIFT)) & SYSCON_SDIOCLKSEL_SEL_MASK) +/*! @} */ + +/*! @name SYSTICKCLKDIV0 - System Tick Timer divider for CPU0 */ +/*! @{ */ +#define SYSCON_SYSTICKCLKDIV0_DIV_MASK (0xFFU) +#define SYSCON_SYSTICKCLKDIV0_DIV_SHIFT (0U) +#define SYSCON_SYSTICKCLKDIV0_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV0_DIV_SHIFT)) & SYSCON_SYSTICKCLKDIV0_DIV_MASK) +#define SYSCON_SYSTICKCLKDIV0_RESET_MASK (0x20000000U) +#define SYSCON_SYSTICKCLKDIV0_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_SYSTICKCLKDIV0_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV0_RESET_SHIFT)) & SYSCON_SYSTICKCLKDIV0_RESET_MASK) +#define SYSCON_SYSTICKCLKDIV0_HALT_MASK (0x40000000U) +#define SYSCON_SYSTICKCLKDIV0_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stoped. + * 0b0..Divider clock is running. + */ +#define SYSCON_SYSTICKCLKDIV0_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV0_HALT_SHIFT)) & SYSCON_SYSTICKCLKDIV0_HALT_MASK) +#define SYSCON_SYSTICKCLKDIV0_REQFLAG_MASK (0x80000000U) +#define SYSCON_SYSTICKCLKDIV0_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_SYSTICKCLKDIV0_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV0_REQFLAG_SHIFT)) & SYSCON_SYSTICKCLKDIV0_REQFLAG_MASK) +/*! @} */ + +/*! @name SYSTICKCLKDIV1 - System Tick Timer divider for CPU1 */ +/*! @{ */ +#define SYSCON_SYSTICKCLKDIV1_DIV_MASK (0xFFU) +#define SYSCON_SYSTICKCLKDIV1_DIV_SHIFT (0U) +#define SYSCON_SYSTICKCLKDIV1_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV1_DIV_SHIFT)) & SYSCON_SYSTICKCLKDIV1_DIV_MASK) +#define SYSCON_SYSTICKCLKDIV1_RESET_MASK (0x20000000U) +#define SYSCON_SYSTICKCLKDIV1_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_SYSTICKCLKDIV1_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV1_RESET_SHIFT)) & SYSCON_SYSTICKCLKDIV1_RESET_MASK) +#define SYSCON_SYSTICKCLKDIV1_HALT_MASK (0x40000000U) +#define SYSCON_SYSTICKCLKDIV1_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stoped. + * 0b0..Divider clock is running. + */ +#define SYSCON_SYSTICKCLKDIV1_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV1_HALT_SHIFT)) & SYSCON_SYSTICKCLKDIV1_HALT_MASK) +#define SYSCON_SYSTICKCLKDIV1_REQFLAG_MASK (0x80000000U) +#define SYSCON_SYSTICKCLKDIV1_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_SYSTICKCLKDIV1_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV1_REQFLAG_SHIFT)) & SYSCON_SYSTICKCLKDIV1_REQFLAG_MASK) +/*! @} */ + +/*! @name TRACECLKDIV - TRACE clock divider */ +/*! @{ */ +#define SYSCON_TRACECLKDIV_DIV_MASK (0xFFU) +#define SYSCON_TRACECLKDIV_DIV_SHIFT (0U) +#define SYSCON_TRACECLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_DIV_SHIFT)) & SYSCON_TRACECLKDIV_DIV_MASK) +#define SYSCON_TRACECLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_TRACECLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_TRACECLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_RESET_SHIFT)) & SYSCON_TRACECLKDIV_RESET_MASK) +#define SYSCON_TRACECLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_TRACECLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stoped. + * 0b0..Divider clock is running. + */ +#define SYSCON_TRACECLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_HALT_SHIFT)) & SYSCON_TRACECLKDIV_HALT_MASK) +#define SYSCON_TRACECLKDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_TRACECLKDIV_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_TRACECLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_REQFLAG_SHIFT)) & SYSCON_TRACECLKDIV_REQFLAG_MASK) +/*! @} */ + +/*! @name FLEXFRG0CTRL - Fractional rate divider for flexcomm 0 */ +/*! @{ */ +#define SYSCON_FLEXFRG0CTRL_DIV_MASK (0xFFU) +#define SYSCON_FLEXFRG0CTRL_DIV_SHIFT (0U) +#define SYSCON_FLEXFRG0CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG0CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG0CTRL_DIV_MASK) +#define SYSCON_FLEXFRG0CTRL_MULT_MASK (0xFF00U) +#define SYSCON_FLEXFRG0CTRL_MULT_SHIFT (8U) +#define SYSCON_FLEXFRG0CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG0CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG0CTRL_MULT_MASK) +/*! @} */ + +/*! @name FLEXFRG1CTRL - Fractional rate divider for flexcomm 1 */ +/*! @{ */ +#define SYSCON_FLEXFRG1CTRL_DIV_MASK (0xFFU) +#define SYSCON_FLEXFRG1CTRL_DIV_SHIFT (0U) +#define SYSCON_FLEXFRG1CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG1CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG1CTRL_DIV_MASK) +#define SYSCON_FLEXFRG1CTRL_MULT_MASK (0xFF00U) +#define SYSCON_FLEXFRG1CTRL_MULT_SHIFT (8U) +#define SYSCON_FLEXFRG1CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG1CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG1CTRL_MULT_MASK) +/*! @} */ + +/*! @name FLEXFRG2CTRL - Fractional rate divider for flexcomm 2 */ +/*! @{ */ +#define SYSCON_FLEXFRG2CTRL_DIV_MASK (0xFFU) +#define SYSCON_FLEXFRG2CTRL_DIV_SHIFT (0U) +#define SYSCON_FLEXFRG2CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG2CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG2CTRL_DIV_MASK) +#define SYSCON_FLEXFRG2CTRL_MULT_MASK (0xFF00U) +#define SYSCON_FLEXFRG2CTRL_MULT_SHIFT (8U) +#define SYSCON_FLEXFRG2CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG2CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG2CTRL_MULT_MASK) +/*! @} */ + +/*! @name FLEXFRG3CTRL - Fractional rate divider for flexcomm 3 */ +/*! @{ */ +#define SYSCON_FLEXFRG3CTRL_DIV_MASK (0xFFU) +#define SYSCON_FLEXFRG3CTRL_DIV_SHIFT (0U) +#define SYSCON_FLEXFRG3CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG3CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG3CTRL_DIV_MASK) +#define SYSCON_FLEXFRG3CTRL_MULT_MASK (0xFF00U) +#define SYSCON_FLEXFRG3CTRL_MULT_SHIFT (8U) +#define SYSCON_FLEXFRG3CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG3CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG3CTRL_MULT_MASK) +/*! @} */ + +/*! @name FLEXFRG4CTRL - Fractional rate divider for flexcomm 4 */ +/*! @{ */ +#define SYSCON_FLEXFRG4CTRL_DIV_MASK (0xFFU) +#define SYSCON_FLEXFRG4CTRL_DIV_SHIFT (0U) +#define SYSCON_FLEXFRG4CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG4CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG4CTRL_DIV_MASK) +#define SYSCON_FLEXFRG4CTRL_MULT_MASK (0xFF00U) +#define SYSCON_FLEXFRG4CTRL_MULT_SHIFT (8U) +#define SYSCON_FLEXFRG4CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG4CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG4CTRL_MULT_MASK) +/*! @} */ + +/*! @name FLEXFRG5CTRL - Fractional rate divider for flexcomm 5 */ +/*! @{ */ +#define SYSCON_FLEXFRG5CTRL_DIV_MASK (0xFFU) +#define SYSCON_FLEXFRG5CTRL_DIV_SHIFT (0U) +#define SYSCON_FLEXFRG5CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG5CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG5CTRL_DIV_MASK) +#define SYSCON_FLEXFRG5CTRL_MULT_MASK (0xFF00U) +#define SYSCON_FLEXFRG5CTRL_MULT_SHIFT (8U) +#define SYSCON_FLEXFRG5CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG5CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG5CTRL_MULT_MASK) +/*! @} */ + +/*! @name FLEXFRG6CTRL - Fractional rate divider for flexcomm 6 */ +/*! @{ */ +#define SYSCON_FLEXFRG6CTRL_DIV_MASK (0xFFU) +#define SYSCON_FLEXFRG6CTRL_DIV_SHIFT (0U) +#define SYSCON_FLEXFRG6CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG6CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG6CTRL_DIV_MASK) +#define SYSCON_FLEXFRG6CTRL_MULT_MASK (0xFF00U) +#define SYSCON_FLEXFRG6CTRL_MULT_SHIFT (8U) +#define SYSCON_FLEXFRG6CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG6CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG6CTRL_MULT_MASK) +/*! @} */ + +/*! @name FLEXFRG7CTRL - Fractional rate divider for flexcomm 7 */ +/*! @{ */ +#define SYSCON_FLEXFRG7CTRL_DIV_MASK (0xFFU) +#define SYSCON_FLEXFRG7CTRL_DIV_SHIFT (0U) +#define SYSCON_FLEXFRG7CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG7CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG7CTRL_DIV_MASK) +#define SYSCON_FLEXFRG7CTRL_MULT_MASK (0xFF00U) +#define SYSCON_FLEXFRG7CTRL_MULT_SHIFT (8U) +#define SYSCON_FLEXFRG7CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG7CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG7CTRL_MULT_MASK) +/*! @} */ + +/*! @name FLEXFRGXCTRL - Peripheral reset control register */ +/*! @{ */ +#define SYSCON_FLEXFRGXCTRL_DATA_MASK (0xFFFFFFFFU) +#define SYSCON_FLEXFRGXCTRL_DATA_SHIFT (0U) +#define SYSCON_FLEXFRGXCTRL_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRGXCTRL_DATA_SHIFT)) & SYSCON_FLEXFRGXCTRL_DATA_MASK) +/*! @} */ + +/* The count of SYSCON_FLEXFRGXCTRL */ +#define SYSCON_FLEXFRGXCTRL_COUNT (8U) + +/*! @name AHBCLKDIV - System clock divider */ +/*! @{ */ +#define SYSCON_AHBCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_AHBCLKDIV_DIV_SHIFT (0U) +#define SYSCON_AHBCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_DIV_SHIFT)) & SYSCON_AHBCLKDIV_DIV_MASK) +#define SYSCON_AHBCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_AHBCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_AHBCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_RESET_SHIFT)) & SYSCON_AHBCLKDIV_RESET_MASK) +#define SYSCON_AHBCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_AHBCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stoped. + * 0b0..Divider clock is running. + */ +#define SYSCON_AHBCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_HALT_SHIFT)) & SYSCON_AHBCLKDIV_HALT_MASK) +#define SYSCON_AHBCLKDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_AHBCLKDIV_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_AHBCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_REQFLAG_SHIFT)) & SYSCON_AHBCLKDIV_REQFLAG_MASK) +/*! @} */ + +/*! @name CLKOUTDIV - CLKOUT clock divider */ +/*! @{ */ +#define SYSCON_CLKOUTDIV_DIV_MASK (0xFFU) +#define SYSCON_CLKOUTDIV_DIV_SHIFT (0U) +#define SYSCON_CLKOUTDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_DIV_SHIFT)) & SYSCON_CLKOUTDIV_DIV_MASK) +#define SYSCON_CLKOUTDIV_RESET_MASK (0x20000000U) +#define SYSCON_CLKOUTDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_CLKOUTDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_RESET_SHIFT)) & SYSCON_CLKOUTDIV_RESET_MASK) +#define SYSCON_CLKOUTDIV_HALT_MASK (0x40000000U) +#define SYSCON_CLKOUTDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stoped. + * 0b0..Divider clock is running. + */ +#define SYSCON_CLKOUTDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_HALT_SHIFT)) & SYSCON_CLKOUTDIV_HALT_MASK) +#define SYSCON_CLKOUTDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_CLKOUTDIV_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_CLKOUTDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_REQFLAG_SHIFT)) & SYSCON_CLKOUTDIV_REQFLAG_MASK) +/*! @} */ + +/*! @name FROHFDIV - FRO_HF (96MHz) clock divider */ +/*! @{ */ +#define SYSCON_FROHFDIV_DIV_MASK (0xFFU) +#define SYSCON_FROHFDIV_DIV_SHIFT (0U) +#define SYSCON_FROHFDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_DIV_SHIFT)) & SYSCON_FROHFDIV_DIV_MASK) +#define SYSCON_FROHFDIV_RESET_MASK (0x20000000U) +#define SYSCON_FROHFDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_FROHFDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_RESET_SHIFT)) & SYSCON_FROHFDIV_RESET_MASK) +#define SYSCON_FROHFDIV_HALT_MASK (0x40000000U) +#define SYSCON_FROHFDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stoped. + * 0b0..Divider clock is running. + */ +#define SYSCON_FROHFDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_HALT_SHIFT)) & SYSCON_FROHFDIV_HALT_MASK) +#define SYSCON_FROHFDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_FROHFDIV_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_FROHFDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_REQFLAG_SHIFT)) & SYSCON_FROHFDIV_REQFLAG_MASK) +/*! @} */ + +/*! @name WDTCLKDIV - WDT clock divider */ +/*! @{ */ +#define SYSCON_WDTCLKDIV_DIV_MASK (0x3FU) +#define SYSCON_WDTCLKDIV_DIV_SHIFT (0U) +#define SYSCON_WDTCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_DIV_SHIFT)) & SYSCON_WDTCLKDIV_DIV_MASK) +#define SYSCON_WDTCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_WDTCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_WDTCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_RESET_SHIFT)) & SYSCON_WDTCLKDIV_RESET_MASK) +#define SYSCON_WDTCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_WDTCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stoped. + * 0b0..Divider clock is running. + */ +#define SYSCON_WDTCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_HALT_SHIFT)) & SYSCON_WDTCLKDIV_HALT_MASK) +#define SYSCON_WDTCLKDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_WDTCLKDIV_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_WDTCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_REQFLAG_SHIFT)) & SYSCON_WDTCLKDIV_REQFLAG_MASK) +/*! @} */ + +/*! @name ADCCLKDIV - ADC clock divider */ +/*! @{ */ +#define SYSCON_ADCCLKDIV_DIV_MASK (0x7U) +#define SYSCON_ADCCLKDIV_DIV_SHIFT (0U) +#define SYSCON_ADCCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_DIV_SHIFT)) & SYSCON_ADCCLKDIV_DIV_MASK) +#define SYSCON_ADCCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_ADCCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_ADCCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_RESET_SHIFT)) & SYSCON_ADCCLKDIV_RESET_MASK) +#define SYSCON_ADCCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_ADCCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stoped. + * 0b0..Divider clock is running. + */ +#define SYSCON_ADCCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_HALT_SHIFT)) & SYSCON_ADCCLKDIV_HALT_MASK) +#define SYSCON_ADCCLKDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_ADCCLKDIV_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_ADCCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_REQFLAG_SHIFT)) & SYSCON_ADCCLKDIV_REQFLAG_MASK) +/*! @} */ + +/*! @name USB0CLKDIV - USB0 Clock divider */ +/*! @{ */ +#define SYSCON_USB0CLKDIV_DIV_MASK (0xFFU) +#define SYSCON_USB0CLKDIV_DIV_SHIFT (0U) +#define SYSCON_USB0CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_DIV_SHIFT)) & SYSCON_USB0CLKDIV_DIV_MASK) +#define SYSCON_USB0CLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_USB0CLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_USB0CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_RESET_SHIFT)) & SYSCON_USB0CLKDIV_RESET_MASK) +#define SYSCON_USB0CLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_USB0CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stoped. + * 0b0..Divider clock is running. + */ +#define SYSCON_USB0CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_HALT_SHIFT)) & SYSCON_USB0CLKDIV_HALT_MASK) +#define SYSCON_USB0CLKDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_USB0CLKDIV_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_USB0CLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_REQFLAG_SHIFT)) & SYSCON_USB0CLKDIV_REQFLAG_MASK) +/*! @} */ + +/*! @name MCLKDIV - I2S MCLK clock divider */ +/*! @{ */ +#define SYSCON_MCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_MCLKDIV_DIV_SHIFT (0U) +#define SYSCON_MCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_DIV_SHIFT)) & SYSCON_MCLKDIV_DIV_MASK) +#define SYSCON_MCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_MCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_MCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_RESET_SHIFT)) & SYSCON_MCLKDIV_RESET_MASK) +#define SYSCON_MCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_MCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stoped. + * 0b0..Divider clock is running. + */ +#define SYSCON_MCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_HALT_SHIFT)) & SYSCON_MCLKDIV_HALT_MASK) +#define SYSCON_MCLKDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_MCLKDIV_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_MCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_REQFLAG_SHIFT)) & SYSCON_MCLKDIV_REQFLAG_MASK) +/*! @} */ + +/*! @name SCTCLKDIV - SCT/PWM clock divider */ +/*! @{ */ +#define SYSCON_SCTCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_SCTCLKDIV_DIV_SHIFT (0U) +#define SYSCON_SCTCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_DIV_SHIFT)) & SYSCON_SCTCLKDIV_DIV_MASK) +#define SYSCON_SCTCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_SCTCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_SCTCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_RESET_SHIFT)) & SYSCON_SCTCLKDIV_RESET_MASK) +#define SYSCON_SCTCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_SCTCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stoped. + * 0b0..Divider clock is running. + */ +#define SYSCON_SCTCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_HALT_SHIFT)) & SYSCON_SCTCLKDIV_HALT_MASK) +#define SYSCON_SCTCLKDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_SCTCLKDIV_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_SCTCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_REQFLAG_SHIFT)) & SYSCON_SCTCLKDIV_REQFLAG_MASK) +/*! @} */ + +/*! @name SDIOCLKDIV - SDIO clock divider */ +/*! @{ */ +#define SYSCON_SDIOCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_SDIOCLKDIV_DIV_SHIFT (0U) +#define SYSCON_SDIOCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_DIV_SHIFT)) & SYSCON_SDIOCLKDIV_DIV_MASK) +#define SYSCON_SDIOCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_SDIOCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_SDIOCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_RESET_SHIFT)) & SYSCON_SDIOCLKDIV_RESET_MASK) +#define SYSCON_SDIOCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_SDIOCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stoped. + * 0b0..Divider clock is running. + */ +#define SYSCON_SDIOCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_HALT_SHIFT)) & SYSCON_SDIOCLKDIV_HALT_MASK) +#define SYSCON_SDIOCLKDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_SDIOCLKDIV_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_SDIOCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_REQFLAG_SHIFT)) & SYSCON_SDIOCLKDIV_REQFLAG_MASK) +/*! @} */ + +/*! @name PLL0CLKDIV - PLL0 clock divider */ +/*! @{ */ +#define SYSCON_PLL0CLKDIV_DIV_MASK (0xFFU) +#define SYSCON_PLL0CLKDIV_DIV_SHIFT (0U) +#define SYSCON_PLL0CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKDIV_DIV_SHIFT)) & SYSCON_PLL0CLKDIV_DIV_MASK) +#define SYSCON_PLL0CLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_PLL0CLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_PLL0CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKDIV_RESET_SHIFT)) & SYSCON_PLL0CLKDIV_RESET_MASK) +#define SYSCON_PLL0CLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_PLL0CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stoped. + * 0b0..Divider clock is running. + */ +#define SYSCON_PLL0CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKDIV_HALT_SHIFT)) & SYSCON_PLL0CLKDIV_HALT_MASK) +#define SYSCON_PLL0CLKDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_PLL0CLKDIV_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_PLL0CLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKDIV_REQFLAG_SHIFT)) & SYSCON_PLL0CLKDIV_REQFLAG_MASK) +/*! @} */ + +/*! @name CLOCKGENUPDATELOCKOUT - Control clock configuration registers access (like xxxDIV, xxxSEL) */ +/*! @{ */ +#define SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT_MASK (0xFFFFFFFFU) +#define SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT_SHIFT (0U) +/*! CLOCKGENUPDATELOCKOUT - Control clock configuration registers access (like xxxDIV, xxxSEL). + * 0b00000000000000000000000000000001..update all clock configuration. + * 0b00000000000000000000000000000000..all hardware clock configruration are freeze. + */ +#define SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT_SHIFT)) & SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT_MASK) +/*! @} */ + +/*! @name FMCCR - FMC configuration register - INTERNAL USE ONLY */ +/*! @{ */ +#define SYSCON_FMCCR_FETCHCTL_MASK (0x3U) +#define SYSCON_FMCCR_FETCHCTL_SHIFT (0U) +/*! FETCHCTL - Fetch control + * 0b00..No buffering (bypass always used) for Fetch cycles + * 0b01..One buffer is used for all Fetch cycles + * 0b10..All buffers can be used for Fetch cycles + */ +#define SYSCON_FMCCR_FETCHCTL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_FETCHCTL_SHIFT)) & SYSCON_FMCCR_FETCHCTL_MASK) +#define SYSCON_FMCCR_DATACTL_MASK (0xCU) +#define SYSCON_FMCCR_DATACTL_SHIFT (2U) +/*! DATACTL - Data control + * 0b00..No buffering (bypass always used) for Data cycles + * 0b01..One buffer is used for all Data cycles + * 0b10..All buffers can be used for Data cycles + */ +#define SYSCON_FMCCR_DATACTL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_DATACTL_SHIFT)) & SYSCON_FMCCR_DATACTL_MASK) +#define SYSCON_FMCCR_ACCEL_MASK (0x10U) +#define SYSCON_FMCCR_ACCEL_SHIFT (4U) +#define SYSCON_FMCCR_ACCEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_ACCEL_SHIFT)) & SYSCON_FMCCR_ACCEL_MASK) +#define SYSCON_FMCCR_PREFEN_MASK (0x20U) +#define SYSCON_FMCCR_PREFEN_SHIFT (5U) +#define SYSCON_FMCCR_PREFEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_PREFEN_SHIFT)) & SYSCON_FMCCR_PREFEN_MASK) +#define SYSCON_FMCCR_PREFOVR_MASK (0x40U) +#define SYSCON_FMCCR_PREFOVR_SHIFT (6U) +#define SYSCON_FMCCR_PREFOVR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_PREFOVR_SHIFT)) & SYSCON_FMCCR_PREFOVR_MASK) +#define SYSCON_FMCCR_PREFCRI_MASK (0x700U) +#define SYSCON_FMCCR_PREFCRI_SHIFT (8U) +#define SYSCON_FMCCR_PREFCRI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_PREFCRI_SHIFT)) & SYSCON_FMCCR_PREFCRI_MASK) +#define SYSCON_FMCCR_FMCTIM_MASK (0x1F000U) +#define SYSCON_FMCCR_FMCTIM_SHIFT (12U) +#define SYSCON_FMCCR_FMCTIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_FMCTIM_SHIFT)) & SYSCON_FMCCR_FMCTIM_MASK) +#define SYSCON_FMCCR_PFISLRU_MASK (0x20000U) +#define SYSCON_FMCCR_PFISLRU_SHIFT (17U) +#define SYSCON_FMCCR_PFISLRU(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_PFISLRU_SHIFT)) & SYSCON_FMCCR_PFISLRU_MASK) +#define SYSCON_FMCCR_PFADAP_MASK (0x40000U) +#define SYSCON_FMCCR_PFADAP_SHIFT (18U) +#define SYSCON_FMCCR_PFADAP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_PFADAP_SHIFT)) & SYSCON_FMCCR_PFADAP_MASK) +/*! @} */ + +/*! @name USB0CLKCTRL - USB0 clock control */ +/*! @{ */ +#define SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK_MASK (0x1U) +#define SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK_SHIFT (0U) +/*! AP_FS_DEV_CLK - USB0 Device USB0_NEEDCLK signal control:. + * 0b0..Under hardware control. + * 0b1..Forced high. + */ +#define SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK_SHIFT)) & SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK_MASK) +#define SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK_MASK (0x2U) +#define SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK_SHIFT (1U) +/*! POL_FS_DEV_CLK - USB0 Device USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt:. + * 0b0..Falling edge of device USB0_NEEDCLK triggers wake-up. + * 0b1..Rising edge of device USB0_NEEDCLK triggers wake-up. + */ +#define SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK_SHIFT)) & SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK_MASK) +#define SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK_MASK (0x4U) +#define SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK_SHIFT (2U) +/*! AP_FS_HOST_CLK - USB0 Host USB0_NEEDCLK signal control:. + * 0b0..Under hardware control. + * 0b1..Forced high. + */ +#define SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK_SHIFT)) & SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK_MASK) +#define SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK_MASK (0x8U) +#define SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK_SHIFT (3U) +/*! POL_FS_HOST_CLK - USB0 Host USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt:. + * 0b0..Falling edge of device USB0_NEEDCLK triggers wake-up. + * 0b1..Rising edge of device USB0_NEEDCLK triggers wake-up. + */ +#define SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK_SHIFT)) & SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK_MASK) +#define SYSCON_USB0CLKCTRL_PU_DISABLE_MASK (0x10U) +#define SYSCON_USB0CLKCTRL_PU_DISABLE_SHIFT (4U) +/*! PU_DISABLE - Internal pull-up disable control. + * 0b1..Internal pull-up disable. + * 0b0..Internal pull-up enable. + */ +#define SYSCON_USB0CLKCTRL_PU_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_PU_DISABLE_SHIFT)) & SYSCON_USB0CLKCTRL_PU_DISABLE_MASK) +/*! @} */ + +/*! @name USB0CLKSTAT - USB0 clock status */ +/*! @{ */ +#define SYSCON_USB0CLKSTAT_DEV_NEED_CLKST_MASK (0x1U) +#define SYSCON_USB0CLKSTAT_DEV_NEED_CLKST_SHIFT (0U) +/*! DEV_NEED_CLKST - USB0 Device USB0_NEEDCLK signal status:. + * 0b1..USB0 Device clock is high. + * 0b0..USB0 Device clock is low. + */ +#define SYSCON_USB0CLKSTAT_DEV_NEED_CLKST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKSTAT_DEV_NEED_CLKST_SHIFT)) & SYSCON_USB0CLKSTAT_DEV_NEED_CLKST_MASK) +#define SYSCON_USB0CLKSTAT_HOST_NEED_CLKST_MASK (0x2U) +#define SYSCON_USB0CLKSTAT_HOST_NEED_CLKST_SHIFT (1U) +/*! HOST_NEED_CLKST - USB0 Host USB0_NEEDCLK signal status:. + * 0b1..USB0 Host clock is high. + * 0b0..USB0 Host clock is low. + */ +#define SYSCON_USB0CLKSTAT_HOST_NEED_CLKST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKSTAT_HOST_NEED_CLKST_SHIFT)) & SYSCON_USB0CLKSTAT_HOST_NEED_CLKST_MASK) +/*! @} */ + +/*! @name FMCFLUSH - FMCflush control */ +/*! @{ */ +#define SYSCON_FMCFLUSH_FLUSH_MASK (0x1U) +#define SYSCON_FMCFLUSH_FLUSH_SHIFT (0U) +#define SYSCON_FMCFLUSH_FLUSH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCFLUSH_FLUSH_SHIFT)) & SYSCON_FMCFLUSH_FLUSH_MASK) +/*! @} */ + +/*! @name MCLKIO - MCLK control */ +/*! @{ */ +#define SYSCON_MCLKIO_MCLKIO_MASK (0xFFFFFFFFU) +#define SYSCON_MCLKIO_MCLKIO_SHIFT (0U) +/*! MCLKIO - MCLK control. + * 0b00000000000000000000000000000000..input mode. + * 0b00000000000000000000000000000001..output mode. + */ +#define SYSCON_MCLKIO_MCLKIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKIO_MCLKIO_SHIFT)) & SYSCON_MCLKIO_MCLKIO_MASK) +/*! @} */ + +/*! @name USB1CLKCTRL - USB1 clock control */ +/*! @{ */ +#define SYSCON_USB1CLKCTRL_AP_HS_DEV_CLK_MASK (0x1U) +#define SYSCON_USB1CLKCTRL_AP_HS_DEV_CLK_SHIFT (0U) +/*! AP_HS_DEV_CLK - USB1 Device need_clock signal control:. + * 0b0..Under hardware control. + * 0b1..Forced high. + */ +#define SYSCON_USB1CLKCTRL_AP_HS_DEV_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_AP_HS_DEV_CLK_SHIFT)) & SYSCON_USB1CLKCTRL_AP_HS_DEV_CLK_MASK) +#define SYSCON_USB1CLKCTRL_POL_HS_DEV_CLK_MASK (0x2U) +#define SYSCON_USB1CLKCTRL_POL_HS_DEV_CLK_SHIFT (1U) +/*! POL_HS_DEV_CLK - USB1 Device need_clock polarity for triggering the USB1 wake-up interrupt:. + * 0b0..Falling edge of device need_clock triggers wake-up. + * 0b1..Rising edge of device need_clock triggers wake-up. + */ +#define SYSCON_USB1CLKCTRL_POL_HS_DEV_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_POL_HS_DEV_CLK_SHIFT)) & SYSCON_USB1CLKCTRL_POL_HS_DEV_CLK_MASK) +#define SYSCON_USB1CLKCTRL_AP_HS_HOST_CLK_MASK (0x4U) +#define SYSCON_USB1CLKCTRL_AP_HS_HOST_CLK_SHIFT (2U) +/*! AP_HS_HOST_CLK - USB1 Host need_clock signal control:. + * 0b0..Under hardware control. + * 0b1..Forced high. + */ +#define SYSCON_USB1CLKCTRL_AP_HS_HOST_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_AP_HS_HOST_CLK_SHIFT)) & SYSCON_USB1CLKCTRL_AP_HS_HOST_CLK_MASK) +#define SYSCON_USB1CLKCTRL_POL_HS_HOST_CLK_MASK (0x8U) +#define SYSCON_USB1CLKCTRL_POL_HS_HOST_CLK_SHIFT (3U) +/*! POL_HS_HOST_CLK - USB1 Host need_clock polarity for triggering the USB1 wake-up interrupt: 0 + * Falling edge of device need_clock triggers wake-up. + * 0b0..Falling edge of device need_clock triggers wake-up. + * 0b1..Rising edge of device need_clock triggers wake-up. + */ +#define SYSCON_USB1CLKCTRL_POL_HS_HOST_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_POL_HS_HOST_CLK_SHIFT)) & SYSCON_USB1CLKCTRL_POL_HS_HOST_CLK_MASK) +#define SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N_MASK (0x10U) +#define SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N_SHIFT (4U) +/*! HS_DEV_WAKEUP_N - External user wake-up signal for device mode; asserting this signal (active + * low) will result in exiting the low power mode; input to synchronous control logic:. + * 0b0..Forces USB1 PHY to wake-up. + * 0b1..Normal USB1 PHY behavior. + */ +#define SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N_SHIFT)) & SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N_MASK) +/*! @} */ + +/*! @name USB1CLKSTAT - USB1 clock status */ +/*! @{ */ +#define SYSCON_USB1CLKSTAT_DEV_NEED_CLKST_MASK (0x1U) +#define SYSCON_USB1CLKSTAT_DEV_NEED_CLKST_SHIFT (0U) +/*! DEV_NEED_CLKST - USB1 Device need_clock signal status:. + * 0b1..USB1 Device clock is high. + * 0b0..USB1 Device clock is low. + */ +#define SYSCON_USB1CLKSTAT_DEV_NEED_CLKST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKSTAT_DEV_NEED_CLKST_SHIFT)) & SYSCON_USB1CLKSTAT_DEV_NEED_CLKST_MASK) +#define SYSCON_USB1CLKSTAT_HOST_NEED_CLKST_MASK (0x2U) +#define SYSCON_USB1CLKSTAT_HOST_NEED_CLKST_SHIFT (1U) +/*! HOST_NEED_CLKST - USB1 Host need_clock signal status:. + * 0b1..USB1 Host clock is high. + * 0b0..USB1 Host clock is low. + */ +#define SYSCON_USB1CLKSTAT_HOST_NEED_CLKST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKSTAT_HOST_NEED_CLKST_SHIFT)) & SYSCON_USB1CLKSTAT_HOST_NEED_CLKST_MASK) +/*! @} */ + +/*! @name FLASHBANKENABLE - Flash Banks control */ +/*! @{ */ +#define SYSCON_FLASHBANKENABLE_BANK0_MASK (0xFU) +#define SYSCON_FLASHBANKENABLE_BANK0_SHIFT (0U) +/*! BANK0 - Flash Bank0 control. + * 0b0000..Flash BANK0 checker is enabled (all Flash pages inside this bank cannot be erased nor programmed). + * 0b1010..1010: Flash BANK0 checker is disabled (all Flash pages inside this bank can be erased and programmed). + */ +#define SYSCON_FLASHBANKENABLE_BANK0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHBANKENABLE_BANK0_SHIFT)) & SYSCON_FLASHBANKENABLE_BANK0_MASK) +#define SYSCON_FLASHBANKENABLE_BANK1_MASK (0xF0U) +#define SYSCON_FLASHBANKENABLE_BANK1_SHIFT (4U) +/*! BANK1 - Flash Bank1 control. + * 0b0000..Flash BANK1 checker is enabled (all Flash pages inside this bank cannot be erased nor programmed). + * 0b1010..1010: Flash BANK1 checker is disabled (all Flash pages inside this bank can be erased and programmed). + */ +#define SYSCON_FLASHBANKENABLE_BANK1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHBANKENABLE_BANK1_SHIFT)) & SYSCON_FLASHBANKENABLE_BANK1_MASK) +#define SYSCON_FLASHBANKENABLE_BANK2_MASK (0xF00U) +#define SYSCON_FLASHBANKENABLE_BANK2_SHIFT (8U) +/*! BANK2 - Flash Bank2 control. + * 0b0000..Flash BANK2 checker is enabled (all Flash pages inside this bank cannot be erased nor programmed). + * 0b1010..1010: Flash BANK2 checker is disabled (all Flash pages inside this bank can be erased and programmed). + */ +#define SYSCON_FLASHBANKENABLE_BANK2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHBANKENABLE_BANK2_SHIFT)) & SYSCON_FLASHBANKENABLE_BANK2_MASK) +/*! @} */ + +/*! @name SDIOCLKCTRL - SDIO CCLKIN phase and delay control */ +/*! @{ */ +#define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK (0x3U) +#define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_SHIFT (0U) +/*! CCLK_DRV_PHASE - Programmable delay value by which cclk_in_drv is phase-shifted with regard to cclk_in. + * 0b00..0 degree shift. + * 0b01..90 degree shift. + * 0b10..180 degree shift. + * 0b11..270 degree shift. + */ +#define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK) +#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK (0xCU) +#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_SHIFT (2U) +/*! CCLK_SAMPLE_PHASE - Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in. + * 0b00..0 degree shift. + * 0b01..90 degree shift. + * 0b10..180 degree shift. + * 0b11..270 degree shift. + */ +#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK) +#define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK (0x80U) +#define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_SHIFT (7U) +/*! PHASE_ACTIVE - Enables the delays CCLK_DRV_PHASE and CCLK_SAMPLE_PHASE. + * 0b0..Bypassed. + * 0b1..Activates phase shift logic. When active, the clock divider is active and phase delays are enabled. + */ +#define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK) +#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_MASK (0x1F0000U) +#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_SHIFT (16U) +#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_MASK) +#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK (0x800000U) +#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_SHIFT (23U) +/*! CCLK_DRV_DELAY_ACTIVE - Enables drive delay, as controlled by the CCLK_DRV_DELAY field. + * 0b1..Enable drive delay. + * 0b0..Disable drive delay. + */ +#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK) +#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_MASK (0x1F000000U) +#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_SHIFT (24U) +#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_MASK) +#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK (0x80000000U) +#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_SHIFT (31U) +/*! CCLK_SAMPLE_DELAY_ACTIVE - Enables sample delay, as controlled by the CCLK_SAMPLE_DELAY field. + * 0b1..Enables sample delay. + * 0b0..Disables sample delay. + */ +#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK) +/*! @} */ + +/*! @name PLL1CTRL - PLL1 550m control */ +/*! @{ */ +#define SYSCON_PLL1CTRL_SELR_MASK (0xFU) +#define SYSCON_PLL1CTRL_SELR_SHIFT (0U) +#define SYSCON_PLL1CTRL_SELR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SELR_SHIFT)) & SYSCON_PLL1CTRL_SELR_MASK) +#define SYSCON_PLL1CTRL_SELI_MASK (0x3F0U) +#define SYSCON_PLL1CTRL_SELI_SHIFT (4U) +#define SYSCON_PLL1CTRL_SELI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SELI_SHIFT)) & SYSCON_PLL1CTRL_SELI_MASK) +#define SYSCON_PLL1CTRL_SELP_MASK (0x7C00U) +#define SYSCON_PLL1CTRL_SELP_SHIFT (10U) +#define SYSCON_PLL1CTRL_SELP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SELP_SHIFT)) & SYSCON_PLL1CTRL_SELP_MASK) +#define SYSCON_PLL1CTRL_BYPASSPLL_MASK (0x8000U) +#define SYSCON_PLL1CTRL_BYPASSPLL_SHIFT (15U) +/*! BYPASSPLL - Bypass PLL input clock is sent directly to the PLL output (default). + * 0b1..PLL input clock is sent directly to the PLL output. + * 0b0..use PLL. + */ +#define SYSCON_PLL1CTRL_BYPASSPLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPLL_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPLL_MASK) +#define SYSCON_PLL1CTRL_BYPASSPOSTDIV2_MASK (0x10000U) +#define SYSCON_PLL1CTRL_BYPASSPOSTDIV2_SHIFT (16U) +/*! BYPASSPOSTDIV2 - bypass of the divide-by-2 divider in the post-divider. + * 0b1..bypass of the divide-by-2 divider in the post-divider. + * 0b0..use the divide-by-2 divider in the post-divider. + */ +#define SYSCON_PLL1CTRL_BYPASSPOSTDIV2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPOSTDIV2_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPOSTDIV2_MASK) +#define SYSCON_PLL1CTRL_LIMUPOFF_MASK (0x20000U) +#define SYSCON_PLL1CTRL_LIMUPOFF_SHIFT (17U) +#define SYSCON_PLL1CTRL_LIMUPOFF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_LIMUPOFF_SHIFT)) & SYSCON_PLL1CTRL_LIMUPOFF_MASK) +#define SYSCON_PLL1CTRL_BWDIRECT_MASK (0x40000U) +#define SYSCON_PLL1CTRL_BWDIRECT_SHIFT (18U) +/*! BWDIRECT - control of the bandwidth of the PLL. + * 0b1..modify the bandwidth of the PLL directly. + * 0b0..the bandwidth is changed synchronously with the feedback-divider. + */ +#define SYSCON_PLL1CTRL_BWDIRECT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BWDIRECT_SHIFT)) & SYSCON_PLL1CTRL_BWDIRECT_MASK) +#define SYSCON_PLL1CTRL_BYPASSPREDIV_MASK (0x80000U) +#define SYSCON_PLL1CTRL_BYPASSPREDIV_SHIFT (19U) +/*! BYPASSPREDIV - bypass of the pre-divider. + * 0b1..bypass of the pre-divider. + * 0b0..use the pre-divider. + */ +#define SYSCON_PLL1CTRL_BYPASSPREDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPREDIV_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPREDIV_MASK) +#define SYSCON_PLL1CTRL_BYPASSPOSTDIV_MASK (0x100000U) +#define SYSCON_PLL1CTRL_BYPASSPOSTDIV_SHIFT (20U) +/*! BYPASSPOSTDIV - bypass of the post-divider. + * 0b1..bypass of the post-divider. + * 0b0..use the post-divider. + */ +#define SYSCON_PLL1CTRL_BYPASSPOSTDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPOSTDIV_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPOSTDIV_MASK) +#define SYSCON_PLL1CTRL_CLKEN_MASK (0x200000U) +#define SYSCON_PLL1CTRL_CLKEN_SHIFT (21U) +/*! CLKEN - enable the output clock. + * 0b1..Enable the output clock. + * 0b0..Disable the output clock. + */ +#define SYSCON_PLL1CTRL_CLKEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_CLKEN_SHIFT)) & SYSCON_PLL1CTRL_CLKEN_MASK) +#define SYSCON_PLL1CTRL_FRMEN_MASK (0x400000U) +#define SYSCON_PLL1CTRL_FRMEN_SHIFT (22U) +#define SYSCON_PLL1CTRL_FRMEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_FRMEN_SHIFT)) & SYSCON_PLL1CTRL_FRMEN_MASK) +#define SYSCON_PLL1CTRL_FRMCLKSTABLE_MASK (0x800000U) +#define SYSCON_PLL1CTRL_FRMCLKSTABLE_SHIFT (23U) +#define SYSCON_PLL1CTRL_FRMCLKSTABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_FRMCLKSTABLE_SHIFT)) & SYSCON_PLL1CTRL_FRMCLKSTABLE_MASK) +#define SYSCON_PLL1CTRL_SKEWEN_MASK (0x1000000U) +#define SYSCON_PLL1CTRL_SKEWEN_SHIFT (24U) +/*! SKEWEN - Skew mode. + * 0b1..skewmode is enable. + * 0b0..skewmode is disable. + */ +#define SYSCON_PLL1CTRL_SKEWEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SKEWEN_SHIFT)) & SYSCON_PLL1CTRL_SKEWEN_MASK) +/*! @} */ + +/*! @name PLL1STAT - PLL1 550m status */ +/*! @{ */ +#define SYSCON_PLL1STAT_LOCK_MASK (0x1U) +#define SYSCON_PLL1STAT_LOCK_SHIFT (0U) +#define SYSCON_PLL1STAT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_LOCK_SHIFT)) & SYSCON_PLL1STAT_LOCK_MASK) +#define SYSCON_PLL1STAT_PREDIVACK_MASK (0x2U) +#define SYSCON_PLL1STAT_PREDIVACK_SHIFT (1U) +#define SYSCON_PLL1STAT_PREDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_PREDIVACK_SHIFT)) & SYSCON_PLL1STAT_PREDIVACK_MASK) +#define SYSCON_PLL1STAT_FEEDDIVACK_MASK (0x4U) +#define SYSCON_PLL1STAT_FEEDDIVACK_SHIFT (2U) +#define SYSCON_PLL1STAT_FEEDDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_FEEDDIVACK_SHIFT)) & SYSCON_PLL1STAT_FEEDDIVACK_MASK) +#define SYSCON_PLL1STAT_POSTDIVACK_MASK (0x8U) +#define SYSCON_PLL1STAT_POSTDIVACK_SHIFT (3U) +#define SYSCON_PLL1STAT_POSTDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_POSTDIVACK_SHIFT)) & SYSCON_PLL1STAT_POSTDIVACK_MASK) +#define SYSCON_PLL1STAT_FRMDET_MASK (0x10U) +#define SYSCON_PLL1STAT_FRMDET_SHIFT (4U) +#define SYSCON_PLL1STAT_FRMDET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_FRMDET_SHIFT)) & SYSCON_PLL1STAT_FRMDET_MASK) +/*! @} */ + +/*! @name PLL1NDEC - PLL1 550m N divider */ +/*! @{ */ +#define SYSCON_PLL1NDEC_NDIV_MASK (0xFFU) +#define SYSCON_PLL1NDEC_NDIV_SHIFT (0U) +#define SYSCON_PLL1NDEC_NDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1NDEC_NDIV_SHIFT)) & SYSCON_PLL1NDEC_NDIV_MASK) +#define SYSCON_PLL1NDEC_NREQ_MASK (0x100U) +#define SYSCON_PLL1NDEC_NREQ_SHIFT (8U) +#define SYSCON_PLL1NDEC_NREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1NDEC_NREQ_SHIFT)) & SYSCON_PLL1NDEC_NREQ_MASK) +/*! @} */ + +/*! @name PLL1MDEC - PLL1 550m M divider */ +/*! @{ */ +#define SYSCON_PLL1MDEC_MDIV_MASK (0xFFFFU) +#define SYSCON_PLL1MDEC_MDIV_SHIFT (0U) +#define SYSCON_PLL1MDEC_MDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1MDEC_MDIV_SHIFT)) & SYSCON_PLL1MDEC_MDIV_MASK) +#define SYSCON_PLL1MDEC_MREQ_MASK (0x10000U) +#define SYSCON_PLL1MDEC_MREQ_SHIFT (16U) +#define SYSCON_PLL1MDEC_MREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1MDEC_MREQ_SHIFT)) & SYSCON_PLL1MDEC_MREQ_MASK) +/*! @} */ + +/*! @name PLL1PDEC - PLL1 550m P divider */ +/*! @{ */ +#define SYSCON_PLL1PDEC_PDIV_MASK (0x1FU) +#define SYSCON_PLL1PDEC_PDIV_SHIFT (0U) +#define SYSCON_PLL1PDEC_PDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1PDEC_PDIV_SHIFT)) & SYSCON_PLL1PDEC_PDIV_MASK) +#define SYSCON_PLL1PDEC_PREQ_MASK (0x20U) +#define SYSCON_PLL1PDEC_PREQ_SHIFT (5U) +#define SYSCON_PLL1PDEC_PREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1PDEC_PREQ_SHIFT)) & SYSCON_PLL1PDEC_PREQ_MASK) +/*! @} */ + +/*! @name PLL0CTRL - PLL0 550m control */ +/*! @{ */ +#define SYSCON_PLL0CTRL_SELR_MASK (0xFU) +#define SYSCON_PLL0CTRL_SELR_SHIFT (0U) +#define SYSCON_PLL0CTRL_SELR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SELR_SHIFT)) & SYSCON_PLL0CTRL_SELR_MASK) +#define SYSCON_PLL0CTRL_SELI_MASK (0x3F0U) +#define SYSCON_PLL0CTRL_SELI_SHIFT (4U) +#define SYSCON_PLL0CTRL_SELI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SELI_SHIFT)) & SYSCON_PLL0CTRL_SELI_MASK) +#define SYSCON_PLL0CTRL_SELP_MASK (0x7C00U) +#define SYSCON_PLL0CTRL_SELP_SHIFT (10U) +#define SYSCON_PLL0CTRL_SELP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SELP_SHIFT)) & SYSCON_PLL0CTRL_SELP_MASK) +#define SYSCON_PLL0CTRL_BYPASSPLL_MASK (0x8000U) +#define SYSCON_PLL0CTRL_BYPASSPLL_SHIFT (15U) +/*! BYPASSPLL - Bypass PLL input clock is sent directly to the PLL output (default). + * 0b1..Bypass PLL input clock is sent directly to the PLL output. + * 0b0..use PLL. + */ +#define SYSCON_PLL0CTRL_BYPASSPLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPLL_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPLL_MASK) +#define SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK (0x10000U) +#define SYSCON_PLL0CTRL_BYPASSPOSTDIV2_SHIFT (16U) +/*! BYPASSPOSTDIV2 - bypass of the divide-by-2 divider in the post-divider. + * 0b1..bypass of the divide-by-2 divider in the post-divider. + * 0b0..use the divide-by-2 divider in the post-divider. + */ +#define SYSCON_PLL0CTRL_BYPASSPOSTDIV2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPOSTDIV2_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK) +#define SYSCON_PLL0CTRL_LIMUPOFF_MASK (0x20000U) +#define SYSCON_PLL0CTRL_LIMUPOFF_SHIFT (17U) +#define SYSCON_PLL0CTRL_LIMUPOFF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_LIMUPOFF_SHIFT)) & SYSCON_PLL0CTRL_LIMUPOFF_MASK) +#define SYSCON_PLL0CTRL_BWDIRECT_MASK (0x40000U) +#define SYSCON_PLL0CTRL_BWDIRECT_SHIFT (18U) +/*! BWDIRECT - Control of the bandwidth of the PLL. + * 0b1..modify the bandwidth of the PLL directly. + * 0b0..the bandwidth is changed synchronously with the feedback-divider. + */ +#define SYSCON_PLL0CTRL_BWDIRECT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BWDIRECT_SHIFT)) & SYSCON_PLL0CTRL_BWDIRECT_MASK) +#define SYSCON_PLL0CTRL_BYPASSPREDIV_MASK (0x80000U) +#define SYSCON_PLL0CTRL_BYPASSPREDIV_SHIFT (19U) +/*! BYPASSPREDIV - bypass of the pre-divider. + * 0b1..bypass of the pre-divider. + * 0b0..use the pre-divider. + */ +#define SYSCON_PLL0CTRL_BYPASSPREDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPREDIV_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPREDIV_MASK) +#define SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK (0x100000U) +#define SYSCON_PLL0CTRL_BYPASSPOSTDIV_SHIFT (20U) +/*! BYPASSPOSTDIV - bypass of the post-divider. + * 0b1..bypass of the post-divider. + * 0b0..use the post-divider. + */ +#define SYSCON_PLL0CTRL_BYPASSPOSTDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPOSTDIV_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK) +#define SYSCON_PLL0CTRL_CLKEN_MASK (0x200000U) +#define SYSCON_PLL0CTRL_CLKEN_SHIFT (21U) +/*! CLKEN - enable the output clock. + * 0b1..enable the output clock. + * 0b0..disable the output clock. + */ +#define SYSCON_PLL0CTRL_CLKEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_CLKEN_SHIFT)) & SYSCON_PLL0CTRL_CLKEN_MASK) +#define SYSCON_PLL0CTRL_FRMEN_MASK (0x400000U) +#define SYSCON_PLL0CTRL_FRMEN_SHIFT (22U) +/*! FRMEN - free running mode. + * 0b1..free running mode is enable. + * 0b0..free running mode is disable. + */ +#define SYSCON_PLL0CTRL_FRMEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_FRMEN_SHIFT)) & SYSCON_PLL0CTRL_FRMEN_MASK) +#define SYSCON_PLL0CTRL_FRMCLKSTABLE_MASK (0x800000U) +#define SYSCON_PLL0CTRL_FRMCLKSTABLE_SHIFT (23U) +#define SYSCON_PLL0CTRL_FRMCLKSTABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_FRMCLKSTABLE_SHIFT)) & SYSCON_PLL0CTRL_FRMCLKSTABLE_MASK) +#define SYSCON_PLL0CTRL_SKEWEN_MASK (0x1000000U) +#define SYSCON_PLL0CTRL_SKEWEN_SHIFT (24U) +/*! SKEWEN - skew mode. + * 0b1..skew mode is enable. + * 0b0..skew mode is disable. + */ +#define SYSCON_PLL0CTRL_SKEWEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SKEWEN_SHIFT)) & SYSCON_PLL0CTRL_SKEWEN_MASK) +/*! @} */ + +/*! @name PLL0STAT - PLL0 550m status */ +/*! @{ */ +#define SYSCON_PLL0STAT_LOCK_MASK (0x1U) +#define SYSCON_PLL0STAT_LOCK_SHIFT (0U) +#define SYSCON_PLL0STAT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_LOCK_SHIFT)) & SYSCON_PLL0STAT_LOCK_MASK) +#define SYSCON_PLL0STAT_PREDIVACK_MASK (0x2U) +#define SYSCON_PLL0STAT_PREDIVACK_SHIFT (1U) +#define SYSCON_PLL0STAT_PREDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_PREDIVACK_SHIFT)) & SYSCON_PLL0STAT_PREDIVACK_MASK) +#define SYSCON_PLL0STAT_FEEDDIVACK_MASK (0x4U) +#define SYSCON_PLL0STAT_FEEDDIVACK_SHIFT (2U) +#define SYSCON_PLL0STAT_FEEDDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_FEEDDIVACK_SHIFT)) & SYSCON_PLL0STAT_FEEDDIVACK_MASK) +#define SYSCON_PLL0STAT_POSTDIVACK_MASK (0x8U) +#define SYSCON_PLL0STAT_POSTDIVACK_SHIFT (3U) +#define SYSCON_PLL0STAT_POSTDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_POSTDIVACK_SHIFT)) & SYSCON_PLL0STAT_POSTDIVACK_MASK) +#define SYSCON_PLL0STAT_FRMDET_MASK (0x10U) +#define SYSCON_PLL0STAT_FRMDET_SHIFT (4U) +#define SYSCON_PLL0STAT_FRMDET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_FRMDET_SHIFT)) & SYSCON_PLL0STAT_FRMDET_MASK) +/*! @} */ + +/*! @name PLL0NDEC - PLL0 550m N divider */ +/*! @{ */ +#define SYSCON_PLL0NDEC_NDIV_MASK (0xFFU) +#define SYSCON_PLL0NDEC_NDIV_SHIFT (0U) +#define SYSCON_PLL0NDEC_NDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0NDEC_NDIV_SHIFT)) & SYSCON_PLL0NDEC_NDIV_MASK) +#define SYSCON_PLL0NDEC_NREQ_MASK (0x100U) +#define SYSCON_PLL0NDEC_NREQ_SHIFT (8U) +#define SYSCON_PLL0NDEC_NREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0NDEC_NREQ_SHIFT)) & SYSCON_PLL0NDEC_NREQ_MASK) +/*! @} */ + +/*! @name PLL0PDEC - PLL0 550m P divider */ +/*! @{ */ +#define SYSCON_PLL0PDEC_PDIV_MASK (0x1FU) +#define SYSCON_PLL0PDEC_PDIV_SHIFT (0U) +#define SYSCON_PLL0PDEC_PDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0PDEC_PDIV_SHIFT)) & SYSCON_PLL0PDEC_PDIV_MASK) +#define SYSCON_PLL0PDEC_PREQ_MASK (0x20U) +#define SYSCON_PLL0PDEC_PREQ_SHIFT (5U) +#define SYSCON_PLL0PDEC_PREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0PDEC_PREQ_SHIFT)) & SYSCON_PLL0PDEC_PREQ_MASK) +/*! @} */ + +/*! @name PLL0SSCG0 - PLL0 Spread Spectrum Wrapper control register 0 */ +/*! @{ */ +#define SYSCON_PLL0SSCG0_MD_LBS_MASK (0xFFFFFFFFU) +#define SYSCON_PLL0SSCG0_MD_LBS_SHIFT (0U) +#define SYSCON_PLL0SSCG0_MD_LBS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG0_MD_LBS_SHIFT)) & SYSCON_PLL0SSCG0_MD_LBS_MASK) +/*! @} */ + +/*! @name PLL0SSCG1 - PLL0 Spread Spectrum Wrapper control register 1 */ +/*! @{ */ +#define SYSCON_PLL0SSCG1_MD_MBS_MASK (0x1U) +#define SYSCON_PLL0SSCG1_MD_MBS_SHIFT (0U) +#define SYSCON_PLL0SSCG1_MD_MBS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MD_MBS_SHIFT)) & SYSCON_PLL0SSCG1_MD_MBS_MASK) +#define SYSCON_PLL0SSCG1_MD_REQ_MASK (0x2U) +#define SYSCON_PLL0SSCG1_MD_REQ_SHIFT (1U) +#define SYSCON_PLL0SSCG1_MD_REQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MD_REQ_SHIFT)) & SYSCON_PLL0SSCG1_MD_REQ_MASK) +#define SYSCON_PLL0SSCG1_MF_MASK (0x1CU) +#define SYSCON_PLL0SSCG1_MF_SHIFT (2U) +#define SYSCON_PLL0SSCG1_MF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MF_SHIFT)) & SYSCON_PLL0SSCG1_MF_MASK) +#define SYSCON_PLL0SSCG1_MR_MASK (0xE0U) +#define SYSCON_PLL0SSCG1_MR_SHIFT (5U) +#define SYSCON_PLL0SSCG1_MR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MR_SHIFT)) & SYSCON_PLL0SSCG1_MR_MASK) +#define SYSCON_PLL0SSCG1_MC_MASK (0x300U) +#define SYSCON_PLL0SSCG1_MC_SHIFT (8U) +#define SYSCON_PLL0SSCG1_MC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MC_SHIFT)) & SYSCON_PLL0SSCG1_MC_MASK) +#define SYSCON_PLL0SSCG1_MDIV_EXT_MASK (0x3FFFC00U) +#define SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT (10U) +#define SYSCON_PLL0SSCG1_MDIV_EXT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT)) & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) +#define SYSCON_PLL0SSCG1_MREQ_MASK (0x4000000U) +#define SYSCON_PLL0SSCG1_MREQ_SHIFT (26U) +#define SYSCON_PLL0SSCG1_MREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MREQ_SHIFT)) & SYSCON_PLL0SSCG1_MREQ_MASK) +#define SYSCON_PLL0SSCG1_DITHER_MASK (0x8000000U) +#define SYSCON_PLL0SSCG1_DITHER_SHIFT (27U) +#define SYSCON_PLL0SSCG1_DITHER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_DITHER_SHIFT)) & SYSCON_PLL0SSCG1_DITHER_MASK) +#define SYSCON_PLL0SSCG1_SEL_EXT_MASK (0x10000000U) +#define SYSCON_PLL0SSCG1_SEL_EXT_SHIFT (28U) +#define SYSCON_PLL0SSCG1_SEL_EXT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_SEL_EXT_SHIFT)) & SYSCON_PLL0SSCG1_SEL_EXT_MASK) +/*! @} */ + +/*! @name EFUSECLKCTRL - eFUSE controller clock enable */ +/*! @{ */ +#define SYSCON_EFUSECLKCTRL_EFUSECLKENA_MASK (0x1U) +#define SYSCON_EFUSECLKCTRL_EFUSECLKENA_SHIFT (0U) +#define SYSCON_EFUSECLKCTRL_EFUSECLKENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EFUSECLKCTRL_EFUSECLKENA_SHIFT)) & SYSCON_EFUSECLKCTRL_EFUSECLKENA_MASK) +/*! @} */ + +/*! @name STARTER - Start logic wake-up enable register */ +/*! @{ */ +#define SYSCON_STARTER_GPIO_INT04_MASK (0x1U) +#define SYSCON_STARTER_GPIO_INT04_SHIFT (0U) +/*! GPIO_INT04 - GPIO_INT04 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_GPIO_INT04(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GPIO_INT04_SHIFT)) & SYSCON_STARTER_GPIO_INT04_MASK) +#define SYSCON_STARTER_SYS_MASK (0x1U) +#define SYSCON_STARTER_SYS_SHIFT (0U) +/*! SYS - SYS interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_SYS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SYS_SHIFT)) & SYSCON_STARTER_SYS_MASK) +#define SYSCON_STARTER_GPIO_INT05_MASK (0x2U) +#define SYSCON_STARTER_GPIO_INT05_SHIFT (1U) +/*! GPIO_INT05 - GPIO_INT05 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_GPIO_INT05(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GPIO_INT05_SHIFT)) & SYSCON_STARTER_GPIO_INT05_MASK) +#define SYSCON_STARTER_SDMA0_MASK (0x2U) +#define SYSCON_STARTER_SDMA0_SHIFT (1U) +/*! SDMA0 - SDMA0 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SDMA0_SHIFT)) & SYSCON_STARTER_SDMA0_MASK) +#define SYSCON_STARTER_GINT0_MASK (0x4U) +#define SYSCON_STARTER_GINT0_SHIFT (2U) +/*! GINT0 - GINT0 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_GINT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GINT0_SHIFT)) & SYSCON_STARTER_GINT0_MASK) +#define SYSCON_STARTER_GPIO_INT06_MASK (0x4U) +#define SYSCON_STARTER_GPIO_INT06_SHIFT (2U) +/*! GPIO_INT06 - GPIO_INT06 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_GPIO_INT06(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GPIO_INT06_SHIFT)) & SYSCON_STARTER_GPIO_INT06_MASK) +#define SYSCON_STARTER_GINT1_MASK (0x8U) +#define SYSCON_STARTER_GINT1_SHIFT (3U) +/*! GINT1 - GINT1 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_GINT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GINT1_SHIFT)) & SYSCON_STARTER_GINT1_MASK) +#define SYSCON_STARTER_GPIO_INT07_MASK (0x8U) +#define SYSCON_STARTER_GPIO_INT07_SHIFT (3U) +/*! GPIO_INT07 - GPIO_INT07 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_GPIO_INT07(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GPIO_INT07_SHIFT)) & SYSCON_STARTER_GPIO_INT07_MASK) +#define SYSCON_STARTER_CTIMER2_MASK (0x10U) +#define SYSCON_STARTER_CTIMER2_SHIFT (4U) +/*! CTIMER2 - CTIMER2 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_CTIMER2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER2_SHIFT)) & SYSCON_STARTER_CTIMER2_MASK) +#define SYSCON_STARTER_PIO_INT0_MASK (0x10U) +#define SYSCON_STARTER_PIO_INT0_SHIFT (4U) +/*! PIO_INT0 - PIO_INT0 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_PIO_INT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIO_INT0_SHIFT)) & SYSCON_STARTER_PIO_INT0_MASK) +#define SYSCON_STARTER_CTIMER4_MASK (0x20U) +#define SYSCON_STARTER_CTIMER4_SHIFT (5U) +/*! CTIMER4 - CTIMER4 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER4_SHIFT)) & SYSCON_STARTER_CTIMER4_MASK) +#define SYSCON_STARTER_PIO_INT1_MASK (0x20U) +#define SYSCON_STARTER_PIO_INT1_SHIFT (5U) +/*! PIO_INT1 - PIO_INT1 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_PIO_INT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIO_INT1_SHIFT)) & SYSCON_STARTER_PIO_INT1_MASK) +#define SYSCON_STARTER_OS_EVENT_MASK (0x40U) +#define SYSCON_STARTER_OS_EVENT_SHIFT (6U) +/*! OS_EVENT - OS_EVENT interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_OS_EVENT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_OS_EVENT_SHIFT)) & SYSCON_STARTER_OS_EVENT_MASK) +#define SYSCON_STARTER_PIO_INT2_MASK (0x40U) +#define SYSCON_STARTER_PIO_INT2_SHIFT (6U) +/*! PIO_INT2 - PIO_INT2 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_PIO_INT2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIO_INT2_SHIFT)) & SYSCON_STARTER_PIO_INT2_MASK) +#define SYSCON_STARTER_PIO_INT3_MASK (0x80U) +#define SYSCON_STARTER_PIO_INT3_SHIFT (7U) +/*! PIO_INT3 - PIO_INT3 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_PIO_INT3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIO_INT3_SHIFT)) & SYSCON_STARTER_PIO_INT3_MASK) +#define SYSCON_STARTER_UTICK0_MASK (0x100U) +#define SYSCON_STARTER_UTICK0_SHIFT (8U) +/*! UTICK0 - UTICK0 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_UTICK0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_UTICK0_SHIFT)) & SYSCON_STARTER_UTICK0_MASK) +#define SYSCON_STARTER_MRT0_MASK (0x200U) +#define SYSCON_STARTER_MRT0_SHIFT (9U) +/*! MRT0 - MRT0 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_MRT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_MRT0_SHIFT)) & SYSCON_STARTER_MRT0_MASK) +#define SYSCON_STARTER_CTIMER0_MASK (0x400U) +#define SYSCON_STARTER_CTIMER0_SHIFT (10U) +/*! CTIMER0 - CTIMER0 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_CTIMER0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER0_SHIFT)) & SYSCON_STARTER_CTIMER0_MASK) +#define SYSCON_STARTER_SDIO_MASK (0x400U) +#define SYSCON_STARTER_SDIO_SHIFT (10U) +/*! SDIO - SDIO interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_SDIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SDIO_SHIFT)) & SYSCON_STARTER_SDIO_MASK) +#define SYSCON_STARTER_CTIMER1_MASK (0x800U) +#define SYSCON_STARTER_CTIMER1_SHIFT (11U) +/*! CTIMER1 - CTIMER1 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_CTIMER1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER1_SHIFT)) & SYSCON_STARTER_CTIMER1_MASK) +#define SYSCON_STARTER_SCT0_MASK (0x1000U) +#define SYSCON_STARTER_SCT0_SHIFT (12U) +/*! SCT0 - SCT0 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_SCT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SCT0_SHIFT)) & SYSCON_STARTER_SCT0_MASK) +#define SYSCON_STARTER_CTIMER3_MASK (0x2000U) +#define SYSCON_STARTER_CTIMER3_SHIFT (13U) +/*! CTIMER3 - CTIMER3 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER3_SHIFT)) & SYSCON_STARTER_CTIMER3_MASK) +#define SYSCON_STARTER_FLEXINT0_MASK (0x4000U) +#define SYSCON_STARTER_FLEXINT0_SHIFT (14U) +/*! FLEXINT0 - FLEXINT0 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_FLEXINT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXINT0_SHIFT)) & SYSCON_STARTER_FLEXINT0_MASK) +#define SYSCON_STARTER_FLEXINT1_MASK (0x8000U) +#define SYSCON_STARTER_FLEXINT1_SHIFT (15U) +/*! FLEXINT1 - FLEXINT1 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_FLEXINT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXINT1_SHIFT)) & SYSCON_STARTER_FLEXINT1_MASK) +#define SYSCON_STARTER_USB1_MASK (0x8000U) +#define SYSCON_STARTER_USB1_SHIFT (15U) +/*! USB1 - USB1 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_USB1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB1_SHIFT)) & SYSCON_STARTER_USB1_MASK) +#define SYSCON_STARTER_FLEXINT2_MASK (0x10000U) +#define SYSCON_STARTER_FLEXINT2_SHIFT (16U) +/*! FLEXINT2 - FLEXINT2 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_FLEXINT2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXINT2_SHIFT)) & SYSCON_STARTER_FLEXINT2_MASK) +#define SYSCON_STARTER_USB1_NEEDCLK_MASK (0x10000U) +#define SYSCON_STARTER_USB1_NEEDCLK_SHIFT (16U) +/*! USB1_NEEDCLK - USB1_NEEDCLK interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_USB1_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB1_NEEDCLK_SHIFT)) & SYSCON_STARTER_USB1_NEEDCLK_MASK) +#define SYSCON_STARTER_FLEXINT3_MASK (0x20000U) +#define SYSCON_STARTER_FLEXINT3_SHIFT (17U) +/*! FLEXINT3 - FLEXINT3 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_FLEXINT3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXINT3_SHIFT)) & SYSCON_STARTER_FLEXINT3_MASK) +#define SYSCON_STARTER_SEC_HYPERVISOR_CALL_MASK (0x20000U) +#define SYSCON_STARTER_SEC_HYPERVISOR_CALL_SHIFT (17U) +/*! SEC_HYPERVISOR_CALL - SEC_HYPERVISOR_CALL interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_SEC_HYPERVISOR_CALL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SEC_HYPERVISOR_CALL_SHIFT)) & SYSCON_STARTER_SEC_HYPERVISOR_CALL_MASK) +#define SYSCON_STARTER_FLEXINT4_MASK (0x40000U) +#define SYSCON_STARTER_FLEXINT4_SHIFT (18U) +/*! FLEXINT4 - FLEXINT4 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_FLEXINT4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXINT4_SHIFT)) & SYSCON_STARTER_FLEXINT4_MASK) +#define SYSCON_STARTER_SEC_GPIO_INT00_MASK (0x40000U) +#define SYSCON_STARTER_SEC_GPIO_INT00_SHIFT (18U) +/*! SEC_GPIO_INT00 - SEC_GPIO_INT00 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_SEC_GPIO_INT00(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SEC_GPIO_INT00_SHIFT)) & SYSCON_STARTER_SEC_GPIO_INT00_MASK) +#define SYSCON_STARTER_FLEXINT5_MASK (0x80000U) +#define SYSCON_STARTER_FLEXINT5_SHIFT (19U) +/*! FLEXINT5 - FLEXINT5 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_FLEXINT5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXINT5_SHIFT)) & SYSCON_STARTER_FLEXINT5_MASK) +#define SYSCON_STARTER_SEC_GPIO_INT01_MASK (0x80000U) +#define SYSCON_STARTER_SEC_GPIO_INT01_SHIFT (19U) +/*! SEC_GPIO_INT01 - SEC_GPIO_INT01 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_SEC_GPIO_INT01(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SEC_GPIO_INT01_SHIFT)) & SYSCON_STARTER_SEC_GPIO_INT01_MASK) +#define SYSCON_STARTER_FLEXINT6_MASK (0x100000U) +#define SYSCON_STARTER_FLEXINT6_SHIFT (20U) +/*! FLEXINT6 - FLEXINT6 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_FLEXINT6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXINT6_SHIFT)) & SYSCON_STARTER_FLEXINT6_MASK) +#define SYSCON_STARTER_PLU_MASK (0x100000U) +#define SYSCON_STARTER_PLU_SHIFT (20U) +/*! PLU - PLU interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_PLU(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PLU_SHIFT)) & SYSCON_STARTER_PLU_MASK) +#define SYSCON_STARTER_FLEXINT7_MASK (0x200000U) +#define SYSCON_STARTER_FLEXINT7_SHIFT (21U) +/*! FLEXINT7 - FLEXINT7 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_FLEXINT7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXINT7_SHIFT)) & SYSCON_STARTER_FLEXINT7_MASK) +#define SYSCON_STARTER_SEC_VIO_MASK (0x200000U) +#define SYSCON_STARTER_SEC_VIO_SHIFT (21U) +/*! SEC_VIO - SEC_VIO interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_SEC_VIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SEC_VIO_SHIFT)) & SYSCON_STARTER_SEC_VIO_MASK) +#define SYSCON_STARTER_ADC0_MASK (0x400000U) +#define SYSCON_STARTER_ADC0_SHIFT (22U) +/*! ADC0 - ADC0 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ADC0_SHIFT)) & SYSCON_STARTER_ADC0_MASK) +#define SYSCON_STARTER_SHA_MASK (0x400000U) +#define SYSCON_STARTER_SHA_SHIFT (22U) +/*! SHA - SHA interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_SHA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SHA_SHIFT)) & SYSCON_STARTER_SHA_MASK) +#define SYSCON_STARTER_CASER_MASK (0x800000U) +#define SYSCON_STARTER_CASER_SHIFT (23U) +/*! CASER - CASER interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_CASER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CASER_SHIFT)) & SYSCON_STARTER_CASER_MASK) +#define SYSCON_STARTER_ADC0_THCMP_OVR_MASK (0x1000000U) +#define SYSCON_STARTER_ADC0_THCMP_OVR_SHIFT (24U) +/*! ADC0_THCMP_OVR - ADC0_THCMP_OVR interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_ADC0_THCMP_OVR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ADC0_THCMP_OVR_SHIFT)) & SYSCON_STARTER_ADC0_THCMP_OVR_MASK) +#define SYSCON_STARTER_QDDKEY_MASK (0x1000000U) +#define SYSCON_STARTER_QDDKEY_SHIFT (24U) +/*! QDDKEY - QDDKEY interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_QDDKEY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_QDDKEY_SHIFT)) & SYSCON_STARTER_QDDKEY_MASK) +#define SYSCON_STARTER_PQ_MASK (0x2000000U) +#define SYSCON_STARTER_PQ_SHIFT (25U) +/*! PQ - PQ interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_PQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PQ_SHIFT)) & SYSCON_STARTER_PQ_MASK) +#define SYSCON_STARTER_SDMA1_MASK (0x4000000U) +#define SYSCON_STARTER_SDMA1_SHIFT (26U) +/*! SDMA1 - SDMA1 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SDMA1_SHIFT)) & SYSCON_STARTER_SDMA1_MASK) +#define SYSCON_STARTER_LSPI_HS_MASK (0x8000000U) +#define SYSCON_STARTER_LSPI_HS_SHIFT (27U) +/*! LSPI_HS - LSPI_HS interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_LSPI_HS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_LSPI_HS_SHIFT)) & SYSCON_STARTER_LSPI_HS_MASK) +#define SYSCON_STARTER_USB0_NEEDCLK_MASK (0x8000000U) +#define SYSCON_STARTER_USB0_NEEDCLK_SHIFT (27U) +/*! USB0_NEEDCLK - USB0_NEEDCLK interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_USB0_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB0_NEEDCLK_SHIFT)) & SYSCON_STARTER_USB0_NEEDCLK_MASK) +#define SYSCON_STARTER_USB0_MASK (0x10000000U) +#define SYSCON_STARTER_USB0_SHIFT (28U) +/*! USB0 - USB0 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_USB0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB0_SHIFT)) & SYSCON_STARTER_USB0_MASK) +#define SYSCON_STARTER_RTC_LITE0_MASK (0x20000000U) +#define SYSCON_STARTER_RTC_LITE0_SHIFT (29U) +/*! RTC_LITE0 - RTC_LITE0 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_RTC_LITE0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_RTC_LITE0_SHIFT)) & SYSCON_STARTER_RTC_LITE0_MASK) +#define SYSCON_STARTER_EZH_ARCH_B0_MASK (0x40000000U) +#define SYSCON_STARTER_EZH_ARCH_B0_SHIFT (30U) +/*! EZH_ARCH_B0 - EZH_ARCH_B0 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_EZH_ARCH_B0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_EZH_ARCH_B0_SHIFT)) & SYSCON_STARTER_EZH_ARCH_B0_MASK) +#define SYSCON_STARTER_WAKEUPPADS_MASK (0x80000000U) +#define SYSCON_STARTER_WAKEUPPADS_SHIFT (31U) +#define SYSCON_STARTER_WAKEUPPADS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_WAKEUPPADS_SHIFT)) & SYSCON_STARTER_WAKEUPPADS_MASK) +#define SYSCON_STARTER_WAKEUP_MAILBOX0_MASK (0x80000000U) +#define SYSCON_STARTER_WAKEUP_MAILBOX0_SHIFT (31U) +/*! WAKEUP_MAILBOX0 - WAKEUP_MAILBOX0 interrupt wake-up. + * 0b0..Wake-up disabled. + * 0b1..Wake-up enabled. + */ +#define SYSCON_STARTER_WAKEUP_MAILBOX0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_WAKEUP_MAILBOX0_SHIFT)) & SYSCON_STARTER_WAKEUP_MAILBOX0_MASK) +/*! @} */ + +/* The count of SYSCON_STARTER */ +#define SYSCON_STARTER_COUNT (2U) + +/*! @name STARTERSET - Set bits in STARTER */ +/*! @{ */ +#define SYSCON_STARTERSET_GPIO_INT04_SET_MASK (0x1U) +#define SYSCON_STARTERSET_GPIO_INT04_SET_SHIFT (0U) +#define SYSCON_STARTERSET_GPIO_INT04_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_INT04_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_INT04_SET_MASK) +#define SYSCON_STARTERSET_SYS_SET_MASK (0x1U) +#define SYSCON_STARTERSET_SYS_SET_SHIFT (0U) +#define SYSCON_STARTERSET_SYS_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SYS_SET_SHIFT)) & SYSCON_STARTERSET_SYS_SET_MASK) +#define SYSCON_STARTERSET_GPIO_INT05_SET_MASK (0x2U) +#define SYSCON_STARTERSET_GPIO_INT05_SET_SHIFT (1U) +#define SYSCON_STARTERSET_GPIO_INT05_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_INT05_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_INT05_SET_MASK) +#define SYSCON_STARTERSET_SDMA0_SET_MASK (0x2U) +#define SYSCON_STARTERSET_SDMA0_SET_SHIFT (1U) +#define SYSCON_STARTERSET_SDMA0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SDMA0_SET_SHIFT)) & SYSCON_STARTERSET_SDMA0_SET_MASK) +#define SYSCON_STARTERSET_GPIO_GLOBALINT0_SET_MASK (0x4U) +#define SYSCON_STARTERSET_GPIO_GLOBALINT0_SET_SHIFT (2U) +#define SYSCON_STARTERSET_GPIO_GLOBALINT0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_GLOBALINT0_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_GLOBALINT0_SET_MASK) +#define SYSCON_STARTERSET_GPIO_INT06_SET_MASK (0x4U) +#define SYSCON_STARTERSET_GPIO_INT06_SET_SHIFT (2U) +#define SYSCON_STARTERSET_GPIO_INT06_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_INT06_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_INT06_SET_MASK) +#define SYSCON_STARTERSET_GPIO_GLOBALINT1_SET_MASK (0x8U) +#define SYSCON_STARTERSET_GPIO_GLOBALINT1_SET_SHIFT (3U) +#define SYSCON_STARTERSET_GPIO_GLOBALINT1_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_GLOBALINT1_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_GLOBALINT1_SET_MASK) +#define SYSCON_STARTERSET_GPIO_INT07_SET_MASK (0x8U) +#define SYSCON_STARTERSET_GPIO_INT07_SET_SHIFT (3U) +#define SYSCON_STARTERSET_GPIO_INT07_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_INT07_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_INT07_SET_MASK) +#define SYSCON_STARTERSET_CTIMER2_SET_MASK (0x10U) +#define SYSCON_STARTERSET_CTIMER2_SET_SHIFT (4U) +#define SYSCON_STARTERSET_CTIMER2_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_CTIMER2_SET_SHIFT)) & SYSCON_STARTERSET_CTIMER2_SET_MASK) +#define SYSCON_STARTERSET_GPIO_INT00_SET_MASK (0x10U) +#define SYSCON_STARTERSET_GPIO_INT00_SET_SHIFT (4U) +#define SYSCON_STARTERSET_GPIO_INT00_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_INT00_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_INT00_SET_MASK) +#define SYSCON_STARTERSET_CTIMER4_SET_MASK (0x20U) +#define SYSCON_STARTERSET_CTIMER4_SET_SHIFT (5U) +#define SYSCON_STARTERSET_CTIMER4_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_CTIMER4_SET_SHIFT)) & SYSCON_STARTERSET_CTIMER4_SET_MASK) +#define SYSCON_STARTERSET_GPIO_INT01_SET_MASK (0x20U) +#define SYSCON_STARTERSET_GPIO_INT01_SET_SHIFT (5U) +#define SYSCON_STARTERSET_GPIO_INT01_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_INT01_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_INT01_SET_MASK) +#define SYSCON_STARTERSET_GPIO_INT02_SET_MASK (0x40U) +#define SYSCON_STARTERSET_GPIO_INT02_SET_SHIFT (6U) +#define SYSCON_STARTERSET_GPIO_INT02_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_INT02_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_INT02_SET_MASK) +#define SYSCON_STARTERSET_OS_EVENT_SET_MASK (0x40U) +#define SYSCON_STARTERSET_OS_EVENT_SET_SHIFT (6U) +#define SYSCON_STARTERSET_OS_EVENT_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_OS_EVENT_SET_SHIFT)) & SYSCON_STARTERSET_OS_EVENT_SET_MASK) +#define SYSCON_STARTERSET_GPIO_INT03_SET_MASK (0x80U) +#define SYSCON_STARTERSET_GPIO_INT03_SET_SHIFT (7U) +#define SYSCON_STARTERSET_GPIO_INT03_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_INT03_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_INT03_SET_MASK) +#define SYSCON_STARTERSET_UTICK0_SET_MASK (0x100U) +#define SYSCON_STARTERSET_UTICK0_SET_SHIFT (8U) +#define SYSCON_STARTERSET_UTICK0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_UTICK0_SET_SHIFT)) & SYSCON_STARTERSET_UTICK0_SET_MASK) +#define SYSCON_STARTERSET_MRT0_SET_MASK (0x200U) +#define SYSCON_STARTERSET_MRT0_SET_SHIFT (9U) +#define SYSCON_STARTERSET_MRT0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_MRT0_SET_SHIFT)) & SYSCON_STARTERSET_MRT0_SET_MASK) +#define SYSCON_STARTERSET_CTIMER0_SET_MASK (0x400U) +#define SYSCON_STARTERSET_CTIMER0_SET_SHIFT (10U) +#define SYSCON_STARTERSET_CTIMER0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_CTIMER0_SET_SHIFT)) & SYSCON_STARTERSET_CTIMER0_SET_MASK) +#define SYSCON_STARTERSET_SDIO_SET_MASK (0x400U) +#define SYSCON_STARTERSET_SDIO_SET_SHIFT (10U) +#define SYSCON_STARTERSET_SDIO_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SDIO_SET_SHIFT)) & SYSCON_STARTERSET_SDIO_SET_MASK) +#define SYSCON_STARTERSET_CTIMER1_SET_MASK (0x800U) +#define SYSCON_STARTERSET_CTIMER1_SET_SHIFT (11U) +#define SYSCON_STARTERSET_CTIMER1_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_CTIMER1_SET_SHIFT)) & SYSCON_STARTERSET_CTIMER1_SET_MASK) +#define SYSCON_STARTERSET_SCT0_SET_MASK (0x1000U) +#define SYSCON_STARTERSET_SCT0_SET_SHIFT (12U) +#define SYSCON_STARTERSET_SCT0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SCT0_SET_SHIFT)) & SYSCON_STARTERSET_SCT0_SET_MASK) +#define SYSCON_STARTERSET_CTIMER3_SET_MASK (0x2000U) +#define SYSCON_STARTERSET_CTIMER3_SET_SHIFT (13U) +#define SYSCON_STARTERSET_CTIMER3_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_CTIMER3_SET_SHIFT)) & SYSCON_STARTERSET_CTIMER3_SET_MASK) +#define SYSCON_STARTERSET_FLEXINT0_SET_MASK (0x4000U) +#define SYSCON_STARTERSET_FLEXINT0_SET_SHIFT (14U) +#define SYSCON_STARTERSET_FLEXINT0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXINT0_SET_SHIFT)) & SYSCON_STARTERSET_FLEXINT0_SET_MASK) +#define SYSCON_STARTERSET_FLEXINT1_SET_MASK (0x8000U) +#define SYSCON_STARTERSET_FLEXINT1_SET_SHIFT (15U) +#define SYSCON_STARTERSET_FLEXINT1_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXINT1_SET_SHIFT)) & SYSCON_STARTERSET_FLEXINT1_SET_MASK) +#define SYSCON_STARTERSET_USB1_SET_MASK (0x8000U) +#define SYSCON_STARTERSET_USB1_SET_SHIFT (15U) +#define SYSCON_STARTERSET_USB1_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_USB1_SET_SHIFT)) & SYSCON_STARTERSET_USB1_SET_MASK) +#define SYSCON_STARTERSET_FLEXINT2_SET_MASK (0x10000U) +#define SYSCON_STARTERSET_FLEXINT2_SET_SHIFT (16U) +#define SYSCON_STARTERSET_FLEXINT2_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXINT2_SET_SHIFT)) & SYSCON_STARTERSET_FLEXINT2_SET_MASK) +#define SYSCON_STARTERSET_USB1_NEEDCLK_SET_MASK (0x10000U) +#define SYSCON_STARTERSET_USB1_NEEDCLK_SET_SHIFT (16U) +#define SYSCON_STARTERSET_USB1_NEEDCLK_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_USB1_NEEDCLK_SET_SHIFT)) & SYSCON_STARTERSET_USB1_NEEDCLK_SET_MASK) +#define SYSCON_STARTERSET_FLEXINT3_SET_MASK (0x20000U) +#define SYSCON_STARTERSET_FLEXINT3_SET_SHIFT (17U) +#define SYSCON_STARTERSET_FLEXINT3_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXINT3_SET_SHIFT)) & SYSCON_STARTERSET_FLEXINT3_SET_MASK) +#define SYSCON_STARTERSET_SEC_HYPERVISOR_CALL_SET_MASK (0x20000U) +#define SYSCON_STARTERSET_SEC_HYPERVISOR_CALL_SET_SHIFT (17U) +#define SYSCON_STARTERSET_SEC_HYPERVISOR_CALL_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SEC_HYPERVISOR_CALL_SET_SHIFT)) & SYSCON_STARTERSET_SEC_HYPERVISOR_CALL_SET_MASK) +#define SYSCON_STARTERSET_FLEXINT4_SET_MASK (0x40000U) +#define SYSCON_STARTERSET_FLEXINT4_SET_SHIFT (18U) +#define SYSCON_STARTERSET_FLEXINT4_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXINT4_SET_SHIFT)) & SYSCON_STARTERSET_FLEXINT4_SET_MASK) +#define SYSCON_STARTERSET_SEC_GPIO_INT00_SET_MASK (0x40000U) +#define SYSCON_STARTERSET_SEC_GPIO_INT00_SET_SHIFT (18U) +#define SYSCON_STARTERSET_SEC_GPIO_INT00_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SEC_GPIO_INT00_SET_SHIFT)) & SYSCON_STARTERSET_SEC_GPIO_INT00_SET_MASK) +#define SYSCON_STARTERSET_FLEXINT5_SET_MASK (0x80000U) +#define SYSCON_STARTERSET_FLEXINT5_SET_SHIFT (19U) +#define SYSCON_STARTERSET_FLEXINT5_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXINT5_SET_SHIFT)) & SYSCON_STARTERSET_FLEXINT5_SET_MASK) +#define SYSCON_STARTERSET_SEC_GPIO_INT01_SET_MASK (0x80000U) +#define SYSCON_STARTERSET_SEC_GPIO_INT01_SET_SHIFT (19U) +#define SYSCON_STARTERSET_SEC_GPIO_INT01_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SEC_GPIO_INT01_SET_SHIFT)) & SYSCON_STARTERSET_SEC_GPIO_INT01_SET_MASK) +#define SYSCON_STARTERSET_FLEXINT6_SET_MASK (0x100000U) +#define SYSCON_STARTERSET_FLEXINT6_SET_SHIFT (20U) +#define SYSCON_STARTERSET_FLEXINT6_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXINT6_SET_SHIFT)) & SYSCON_STARTERSET_FLEXINT6_SET_MASK) +#define SYSCON_STARTERSET_PLU_SET_MASK (0x100000U) +#define SYSCON_STARTERSET_PLU_SET_SHIFT (20U) +#define SYSCON_STARTERSET_PLU_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_PLU_SET_SHIFT)) & SYSCON_STARTERSET_PLU_SET_MASK) +#define SYSCON_STARTERSET_FLEXINT7_SET_MASK (0x200000U) +#define SYSCON_STARTERSET_FLEXINT7_SET_SHIFT (21U) +#define SYSCON_STARTERSET_FLEXINT7_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXINT7_SET_SHIFT)) & SYSCON_STARTERSET_FLEXINT7_SET_MASK) +#define SYSCON_STARTERSET_SEC_VIO_SET_MASK (0x200000U) +#define SYSCON_STARTERSET_SEC_VIO_SET_SHIFT (21U) +#define SYSCON_STARTERSET_SEC_VIO_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SEC_VIO_SET_SHIFT)) & SYSCON_STARTERSET_SEC_VIO_SET_MASK) +#define SYSCON_STARTERSET_ADC0_SET_MASK (0x400000U) +#define SYSCON_STARTERSET_ADC0_SET_SHIFT (22U) +#define SYSCON_STARTERSET_ADC0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_ADC0_SET_SHIFT)) & SYSCON_STARTERSET_ADC0_SET_MASK) +#define SYSCON_STARTERSET_SHA_SET_MASK (0x400000U) +#define SYSCON_STARTERSET_SHA_SET_SHIFT (22U) +#define SYSCON_STARTERSET_SHA_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SHA_SET_SHIFT)) & SYSCON_STARTERSET_SHA_SET_MASK) +#define SYSCON_STARTERSET_CASER_SET_MASK (0x800000U) +#define SYSCON_STARTERSET_CASER_SET_SHIFT (23U) +#define SYSCON_STARTERSET_CASER_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_CASER_SET_SHIFT)) & SYSCON_STARTERSET_CASER_SET_MASK) +#define SYSCON_STARTERSET_ADC0_THCMP_OVR_SET_MASK (0x1000000U) +#define SYSCON_STARTERSET_ADC0_THCMP_OVR_SET_SHIFT (24U) +#define SYSCON_STARTERSET_ADC0_THCMP_OVR_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_ADC0_THCMP_OVR_SET_SHIFT)) & SYSCON_STARTERSET_ADC0_THCMP_OVR_SET_MASK) +#define SYSCON_STARTERSET_QDDKEY_SET_MASK (0x1000000U) +#define SYSCON_STARTERSET_QDDKEY_SET_SHIFT (24U) +#define SYSCON_STARTERSET_QDDKEY_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_QDDKEY_SET_SHIFT)) & SYSCON_STARTERSET_QDDKEY_SET_MASK) +#define SYSCON_STARTERSET_PQ_SET_MASK (0x2000000U) +#define SYSCON_STARTERSET_PQ_SET_SHIFT (25U) +#define SYSCON_STARTERSET_PQ_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_PQ_SET_SHIFT)) & SYSCON_STARTERSET_PQ_SET_MASK) +#define SYSCON_STARTERSET_SDMA1_SET_MASK (0x4000000U) +#define SYSCON_STARTERSET_SDMA1_SET_SHIFT (26U) +#define SYSCON_STARTERSET_SDMA1_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SDMA1_SET_SHIFT)) & SYSCON_STARTERSET_SDMA1_SET_MASK) +#define SYSCON_STARTERSET_LSPI_HS_SET_MASK (0x8000000U) +#define SYSCON_STARTERSET_LSPI_HS_SET_SHIFT (27U) +#define SYSCON_STARTERSET_LSPI_HS_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_LSPI_HS_SET_SHIFT)) & SYSCON_STARTERSET_LSPI_HS_SET_MASK) +#define SYSCON_STARTERSET_USB0_NEEDCLK_SET_MASK (0x8000000U) +#define SYSCON_STARTERSET_USB0_NEEDCLK_SET_SHIFT (27U) +#define SYSCON_STARTERSET_USB0_NEEDCLK_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_USB0_NEEDCLK_SET_SHIFT)) & SYSCON_STARTERSET_USB0_NEEDCLK_SET_MASK) +#define SYSCON_STARTERSET_USB0_SET_MASK (0x10000000U) +#define SYSCON_STARTERSET_USB0_SET_SHIFT (28U) +#define SYSCON_STARTERSET_USB0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_USB0_SET_SHIFT)) & SYSCON_STARTERSET_USB0_SET_MASK) +#define SYSCON_STARTERSET_RTC_LITE0_SET_MASK (0x20000000U) +#define SYSCON_STARTERSET_RTC_LITE0_SET_SHIFT (29U) +#define SYSCON_STARTERSET_RTC_LITE0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_RTC_LITE0_SET_SHIFT)) & SYSCON_STARTERSET_RTC_LITE0_SET_MASK) +#define SYSCON_STARTERSET_EZH_ARCH_B0_SET_MASK (0x40000000U) +#define SYSCON_STARTERSET_EZH_ARCH_B0_SET_SHIFT (30U) +#define SYSCON_STARTERSET_EZH_ARCH_B0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_EZH_ARCH_B0_SET_SHIFT)) & SYSCON_STARTERSET_EZH_ARCH_B0_SET_MASK) +#define SYSCON_STARTERSET_WAKEUPPADS_SET_MASK (0x80000000U) +#define SYSCON_STARTERSET_WAKEUPPADS_SET_SHIFT (31U) +#define SYSCON_STARTERSET_WAKEUPPADS_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_WAKEUPPADS_SET_SHIFT)) & SYSCON_STARTERSET_WAKEUPPADS_SET_MASK) +#define SYSCON_STARTERSET_WAKEUP_MAILBOX0_SET_MASK (0x80000000U) +#define SYSCON_STARTERSET_WAKEUP_MAILBOX0_SET_SHIFT (31U) +#define SYSCON_STARTERSET_WAKEUP_MAILBOX0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_WAKEUP_MAILBOX0_SET_SHIFT)) & SYSCON_STARTERSET_WAKEUP_MAILBOX0_SET_MASK) +/*! @} */ + +/* The count of SYSCON_STARTERSET */ +#define SYSCON_STARTERSET_COUNT (2U) + +/*! @name STARTERCLR - Clear bits in STARTER */ +/*! @{ */ +#define SYSCON_STARTERCLR_GPIO_INT04_CLR_MASK (0x1U) +#define SYSCON_STARTERCLR_GPIO_INT04_CLR_SHIFT (0U) +#define SYSCON_STARTERCLR_GPIO_INT04_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_INT04_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_INT04_CLR_MASK) +#define SYSCON_STARTERCLR_SYS_CLR_MASK (0x1U) +#define SYSCON_STARTERCLR_SYS_CLR_SHIFT (0U) +#define SYSCON_STARTERCLR_SYS_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SYS_CLR_SHIFT)) & SYSCON_STARTERCLR_SYS_CLR_MASK) +#define SYSCON_STARTERCLR_GPIO_INT05_CLR_MASK (0x2U) +#define SYSCON_STARTERCLR_GPIO_INT05_CLR_SHIFT (1U) +#define SYSCON_STARTERCLR_GPIO_INT05_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_INT05_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_INT05_CLR_MASK) +#define SYSCON_STARTERCLR_SDMA0_CLR_MASK (0x2U) +#define SYSCON_STARTERCLR_SDMA0_CLR_SHIFT (1U) +#define SYSCON_STARTERCLR_SDMA0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SDMA0_CLR_SHIFT)) & SYSCON_STARTERCLR_SDMA0_CLR_MASK) +#define SYSCON_STARTERCLR_GPIO_GLOBALINT0_CLR_MASK (0x4U) +#define SYSCON_STARTERCLR_GPIO_GLOBALINT0_CLR_SHIFT (2U) +#define SYSCON_STARTERCLR_GPIO_GLOBALINT0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_GLOBALINT0_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_GLOBALINT0_CLR_MASK) +#define SYSCON_STARTERCLR_GPIO_INT06_CLR_MASK (0x4U) +#define SYSCON_STARTERCLR_GPIO_INT06_CLR_SHIFT (2U) +#define SYSCON_STARTERCLR_GPIO_INT06_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_INT06_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_INT06_CLR_MASK) +#define SYSCON_STARTERCLR_GPIO_GLOBALINT1_CLR_MASK (0x8U) +#define SYSCON_STARTERCLR_GPIO_GLOBALINT1_CLR_SHIFT (3U) +#define SYSCON_STARTERCLR_GPIO_GLOBALINT1_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_GLOBALINT1_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_GLOBALINT1_CLR_MASK) +#define SYSCON_STARTERCLR_GPIO_INT07_CLR_MASK (0x8U) +#define SYSCON_STARTERCLR_GPIO_INT07_CLR_SHIFT (3U) +#define SYSCON_STARTERCLR_GPIO_INT07_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_INT07_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_INT07_CLR_MASK) +#define SYSCON_STARTERCLR_CTIMER2_CLR_MASK (0x10U) +#define SYSCON_STARTERCLR_CTIMER2_CLR_SHIFT (4U) +#define SYSCON_STARTERCLR_CTIMER2_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_CTIMER2_CLR_SHIFT)) & SYSCON_STARTERCLR_CTIMER2_CLR_MASK) +#define SYSCON_STARTERCLR_GPIO_INT00_CLR_MASK (0x10U) +#define SYSCON_STARTERCLR_GPIO_INT00_CLR_SHIFT (4U) +#define SYSCON_STARTERCLR_GPIO_INT00_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_INT00_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_INT00_CLR_MASK) +#define SYSCON_STARTERCLR_CTIMER4_CLR_MASK (0x20U) +#define SYSCON_STARTERCLR_CTIMER4_CLR_SHIFT (5U) +#define SYSCON_STARTERCLR_CTIMER4_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_CTIMER4_CLR_SHIFT)) & SYSCON_STARTERCLR_CTIMER4_CLR_MASK) +#define SYSCON_STARTERCLR_GPIO_INT01_CLR_MASK (0x20U) +#define SYSCON_STARTERCLR_GPIO_INT01_CLR_SHIFT (5U) +#define SYSCON_STARTERCLR_GPIO_INT01_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_INT01_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_INT01_CLR_MASK) +#define SYSCON_STARTERCLR_GPIO_INT02_CLR_MASK (0x40U) +#define SYSCON_STARTERCLR_GPIO_INT02_CLR_SHIFT (6U) +#define SYSCON_STARTERCLR_GPIO_INT02_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_INT02_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_INT02_CLR_MASK) +#define SYSCON_STARTERCLR_OS_EVENT_CLR_MASK (0x40U) +#define SYSCON_STARTERCLR_OS_EVENT_CLR_SHIFT (6U) +#define SYSCON_STARTERCLR_OS_EVENT_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_OS_EVENT_CLR_SHIFT)) & SYSCON_STARTERCLR_OS_EVENT_CLR_MASK) +#define SYSCON_STARTERCLR_GPIO_INT03_CLR_MASK (0x80U) +#define SYSCON_STARTERCLR_GPIO_INT03_CLR_SHIFT (7U) +#define SYSCON_STARTERCLR_GPIO_INT03_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_INT03_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_INT03_CLR_MASK) +#define SYSCON_STARTERCLR_UTICK0_CLR_MASK (0x100U) +#define SYSCON_STARTERCLR_UTICK0_CLR_SHIFT (8U) +#define SYSCON_STARTERCLR_UTICK0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_UTICK0_CLR_SHIFT)) & SYSCON_STARTERCLR_UTICK0_CLR_MASK) +#define SYSCON_STARTERCLR_MRT0_CLR_MASK (0x200U) +#define SYSCON_STARTERCLR_MRT0_CLR_SHIFT (9U) +#define SYSCON_STARTERCLR_MRT0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_MRT0_CLR_SHIFT)) & SYSCON_STARTERCLR_MRT0_CLR_MASK) +#define SYSCON_STARTERCLR_CTIMER0_CLR_MASK (0x400U) +#define SYSCON_STARTERCLR_CTIMER0_CLR_SHIFT (10U) +#define SYSCON_STARTERCLR_CTIMER0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_CTIMER0_CLR_SHIFT)) & SYSCON_STARTERCLR_CTIMER0_CLR_MASK) +#define SYSCON_STARTERCLR_SDIO_CLR_MASK (0x400U) +#define SYSCON_STARTERCLR_SDIO_CLR_SHIFT (10U) +#define SYSCON_STARTERCLR_SDIO_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SDIO_CLR_SHIFT)) & SYSCON_STARTERCLR_SDIO_CLR_MASK) +#define SYSCON_STARTERCLR_CTIMER1_CLR_MASK (0x800U) +#define SYSCON_STARTERCLR_CTIMER1_CLR_SHIFT (11U) +#define SYSCON_STARTERCLR_CTIMER1_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_CTIMER1_CLR_SHIFT)) & SYSCON_STARTERCLR_CTIMER1_CLR_MASK) +#define SYSCON_STARTERCLR_SCT0_CLR_MASK (0x1000U) +#define SYSCON_STARTERCLR_SCT0_CLR_SHIFT (12U) +#define SYSCON_STARTERCLR_SCT0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SCT0_CLR_SHIFT)) & SYSCON_STARTERCLR_SCT0_CLR_MASK) +#define SYSCON_STARTERCLR_CTIMER3_CLR_MASK (0x2000U) +#define SYSCON_STARTERCLR_CTIMER3_CLR_SHIFT (13U) +#define SYSCON_STARTERCLR_CTIMER3_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_CTIMER3_CLR_SHIFT)) & SYSCON_STARTERCLR_CTIMER3_CLR_MASK) +#define SYSCON_STARTERCLR_FLEXINT0_CLR_MASK (0x4000U) +#define SYSCON_STARTERCLR_FLEXINT0_CLR_SHIFT (14U) +#define SYSCON_STARTERCLR_FLEXINT0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_FLEXINT0_CLR_SHIFT)) & SYSCON_STARTERCLR_FLEXINT0_CLR_MASK) +#define SYSCON_STARTERCLR_FLEXINT1_CLR_MASK (0x8000U) +#define SYSCON_STARTERCLR_FLEXINT1_CLR_SHIFT (15U) +#define SYSCON_STARTERCLR_FLEXINT1_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_FLEXINT1_CLR_SHIFT)) & SYSCON_STARTERCLR_FLEXINT1_CLR_MASK) +#define SYSCON_STARTERCLR_USB1_CLR_MASK (0x8000U) +#define SYSCON_STARTERCLR_USB1_CLR_SHIFT (15U) +#define SYSCON_STARTERCLR_USB1_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_USB1_CLR_SHIFT)) & SYSCON_STARTERCLR_USB1_CLR_MASK) +#define SYSCON_STARTERCLR_FLEXINT2_CLR_MASK (0x10000U) +#define SYSCON_STARTERCLR_FLEXINT2_CLR_SHIFT (16U) +#define SYSCON_STARTERCLR_FLEXINT2_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_FLEXINT2_CLR_SHIFT)) & SYSCON_STARTERCLR_FLEXINT2_CLR_MASK) +#define SYSCON_STARTERCLR_USB1_NEEDCLK_CLR_MASK (0x10000U) +#define SYSCON_STARTERCLR_USB1_NEEDCLK_CLR_SHIFT (16U) +#define SYSCON_STARTERCLR_USB1_NEEDCLK_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_USB1_NEEDCLK_CLR_SHIFT)) & SYSCON_STARTERCLR_USB1_NEEDCLK_CLR_MASK) +#define SYSCON_STARTERCLR_FLEXINT3_CLR_MASK (0x20000U) +#define SYSCON_STARTERCLR_FLEXINT3_CLR_SHIFT (17U) +#define SYSCON_STARTERCLR_FLEXINT3_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_FLEXINT3_CLR_SHIFT)) & SYSCON_STARTERCLR_FLEXINT3_CLR_MASK) +#define SYSCON_STARTERCLR_SEC_HYPERVISOR_CALL_CLR_MASK (0x20000U) +#define SYSCON_STARTERCLR_SEC_HYPERVISOR_CALL_CLR_SHIFT (17U) +#define SYSCON_STARTERCLR_SEC_HYPERVISOR_CALL_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SEC_HYPERVISOR_CALL_CLR_SHIFT)) & SYSCON_STARTERCLR_SEC_HYPERVISOR_CALL_CLR_MASK) +#define SYSCON_STARTERCLR_FLEXINT4_CLR_MASK (0x40000U) +#define SYSCON_STARTERCLR_FLEXINT4_CLR_SHIFT (18U) +#define SYSCON_STARTERCLR_FLEXINT4_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_FLEXINT4_CLR_SHIFT)) & SYSCON_STARTERCLR_FLEXINT4_CLR_MASK) +#define SYSCON_STARTERCLR_SEC_GPIO_INT00_CLR_MASK (0x40000U) +#define SYSCON_STARTERCLR_SEC_GPIO_INT00_CLR_SHIFT (18U) +#define SYSCON_STARTERCLR_SEC_GPIO_INT00_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SEC_GPIO_INT00_CLR_SHIFT)) & SYSCON_STARTERCLR_SEC_GPIO_INT00_CLR_MASK) +#define SYSCON_STARTERCLR_FLEXINT5_CLR_MASK (0x80000U) +#define SYSCON_STARTERCLR_FLEXINT5_CLR_SHIFT (19U) +#define SYSCON_STARTERCLR_FLEXINT5_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_FLEXINT5_CLR_SHIFT)) & SYSCON_STARTERCLR_FLEXINT5_CLR_MASK) +#define SYSCON_STARTERCLR_SEC_GPIO_INT01_CLR_MASK (0x80000U) +#define SYSCON_STARTERCLR_SEC_GPIO_INT01_CLR_SHIFT (19U) +#define SYSCON_STARTERCLR_SEC_GPIO_INT01_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SEC_GPIO_INT01_CLR_SHIFT)) & SYSCON_STARTERCLR_SEC_GPIO_INT01_CLR_MASK) +#define SYSCON_STARTERCLR_FLEXINT6_CLR_MASK (0x100000U) +#define SYSCON_STARTERCLR_FLEXINT6_CLR_SHIFT (20U) +#define SYSCON_STARTERCLR_FLEXINT6_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_FLEXINT6_CLR_SHIFT)) & SYSCON_STARTERCLR_FLEXINT6_CLR_MASK) +#define SYSCON_STARTERCLR_PLU_CLR_MASK (0x100000U) +#define SYSCON_STARTERCLR_PLU_CLR_SHIFT (20U) +#define SYSCON_STARTERCLR_PLU_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_PLU_CLR_SHIFT)) & SYSCON_STARTERCLR_PLU_CLR_MASK) +#define SYSCON_STARTERCLR_FLEXINT7_CLR_MASK (0x200000U) +#define SYSCON_STARTERCLR_FLEXINT7_CLR_SHIFT (21U) +#define SYSCON_STARTERCLR_FLEXINT7_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_FLEXINT7_CLR_SHIFT)) & SYSCON_STARTERCLR_FLEXINT7_CLR_MASK) +#define SYSCON_STARTERCLR_SEC_VIO_CLR_MASK (0x200000U) +#define SYSCON_STARTERCLR_SEC_VIO_CLR_SHIFT (21U) +#define SYSCON_STARTERCLR_SEC_VIO_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SEC_VIO_CLR_SHIFT)) & SYSCON_STARTERCLR_SEC_VIO_CLR_MASK) +#define SYSCON_STARTERCLR_ADC0_CLR_MASK (0x400000U) +#define SYSCON_STARTERCLR_ADC0_CLR_SHIFT (22U) +#define SYSCON_STARTERCLR_ADC0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_ADC0_CLR_SHIFT)) & SYSCON_STARTERCLR_ADC0_CLR_MASK) +#define SYSCON_STARTERCLR_SHA_CLR_MASK (0x400000U) +#define SYSCON_STARTERCLR_SHA_CLR_SHIFT (22U) +#define SYSCON_STARTERCLR_SHA_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SHA_CLR_SHIFT)) & SYSCON_STARTERCLR_SHA_CLR_MASK) +#define SYSCON_STARTERCLR_CASER_CLR_MASK (0x800000U) +#define SYSCON_STARTERCLR_CASER_CLR_SHIFT (23U) +#define SYSCON_STARTERCLR_CASER_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_CASER_CLR_SHIFT)) & SYSCON_STARTERCLR_CASER_CLR_MASK) +#define SYSCON_STARTERCLR_ADC0_THCMP_OVR_CLR_MASK (0x1000000U) +#define SYSCON_STARTERCLR_ADC0_THCMP_OVR_CLR_SHIFT (24U) +#define SYSCON_STARTERCLR_ADC0_THCMP_OVR_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_ADC0_THCMP_OVR_CLR_SHIFT)) & SYSCON_STARTERCLR_ADC0_THCMP_OVR_CLR_MASK) +#define SYSCON_STARTERCLR_QDDKEY_CLR_MASK (0x1000000U) +#define SYSCON_STARTERCLR_QDDKEY_CLR_SHIFT (24U) +#define SYSCON_STARTERCLR_QDDKEY_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_QDDKEY_CLR_SHIFT)) & SYSCON_STARTERCLR_QDDKEY_CLR_MASK) +#define SYSCON_STARTERCLR_PQ_CLR_MASK (0x2000000U) +#define SYSCON_STARTERCLR_PQ_CLR_SHIFT (25U) +#define SYSCON_STARTERCLR_PQ_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_PQ_CLR_SHIFT)) & SYSCON_STARTERCLR_PQ_CLR_MASK) +#define SYSCON_STARTERCLR_SDMA1_CLR_MASK (0x4000000U) +#define SYSCON_STARTERCLR_SDMA1_CLR_SHIFT (26U) +#define SYSCON_STARTERCLR_SDMA1_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SDMA1_CLR_SHIFT)) & SYSCON_STARTERCLR_SDMA1_CLR_MASK) +#define SYSCON_STARTERCLR_LSPI_HS_CLR_MASK (0x8000000U) +#define SYSCON_STARTERCLR_LSPI_HS_CLR_SHIFT (27U) +#define SYSCON_STARTERCLR_LSPI_HS_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_LSPI_HS_CLR_SHIFT)) & SYSCON_STARTERCLR_LSPI_HS_CLR_MASK) +#define SYSCON_STARTERCLR_USB0_NEEDCLK_CLR_MASK (0x8000000U) +#define SYSCON_STARTERCLR_USB0_NEEDCLK_CLR_SHIFT (27U) +#define SYSCON_STARTERCLR_USB0_NEEDCLK_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_USB0_NEEDCLK_CLR_SHIFT)) & SYSCON_STARTERCLR_USB0_NEEDCLK_CLR_MASK) +#define SYSCON_STARTERCLR_USB0_CLR_MASK (0x10000000U) +#define SYSCON_STARTERCLR_USB0_CLR_SHIFT (28U) +#define SYSCON_STARTERCLR_USB0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_USB0_CLR_SHIFT)) & SYSCON_STARTERCLR_USB0_CLR_MASK) +#define SYSCON_STARTERCLR_RTC_LITE0_CLR_MASK (0x20000000U) +#define SYSCON_STARTERCLR_RTC_LITE0_CLR_SHIFT (29U) +#define SYSCON_STARTERCLR_RTC_LITE0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_RTC_LITE0_CLR_SHIFT)) & SYSCON_STARTERCLR_RTC_LITE0_CLR_MASK) +#define SYSCON_STARTERCLR_EZH_ARCH_B0_CLR_MASK (0x40000000U) +#define SYSCON_STARTERCLR_EZH_ARCH_B0_CLR_SHIFT (30U) +#define SYSCON_STARTERCLR_EZH_ARCH_B0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_EZH_ARCH_B0_CLR_SHIFT)) & SYSCON_STARTERCLR_EZH_ARCH_B0_CLR_MASK) +#define SYSCON_STARTERCLR_WAKEUPPADS_CLR_MASK (0x80000000U) +#define SYSCON_STARTERCLR_WAKEUPPADS_CLR_SHIFT (31U) +#define SYSCON_STARTERCLR_WAKEUPPADS_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_WAKEUPPADS_CLR_SHIFT)) & SYSCON_STARTERCLR_WAKEUPPADS_CLR_MASK) +#define SYSCON_STARTERCLR_WAKEUP_MAILBOX0_CLR_MASK (0x80000000U) +#define SYSCON_STARTERCLR_WAKEUP_MAILBOX0_CLR_SHIFT (31U) +#define SYSCON_STARTERCLR_WAKEUP_MAILBOX0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_WAKEUP_MAILBOX0_CLR_SHIFT)) & SYSCON_STARTERCLR_WAKEUP_MAILBOX0_CLR_MASK) +/*! @} */ + +/* The count of SYSCON_STARTERCLR */ +#define SYSCON_STARTERCLR_COUNT (2U) + +/*! @name HARDWARESLEEP - Hardware Sleep control */ +/*! @{ */ +#define SYSCON_HARDWARESLEEP_FORCED_MASK (0x1U) +#define SYSCON_HARDWARESLEEP_FORCED_SHIFT (0U) +#define SYSCON_HARDWARESLEEP_FORCED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HARDWARESLEEP_FORCED_SHIFT)) & SYSCON_HARDWARESLEEP_FORCED_MASK) +#define SYSCON_HARDWARESLEEP_PERIPHERALS_MASK (0x2U) +#define SYSCON_HARDWARESLEEP_PERIPHERALS_SHIFT (1U) +#define SYSCON_HARDWARESLEEP_PERIPHERALS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HARDWARESLEEP_PERIPHERALS_SHIFT)) & SYSCON_HARDWARESLEEP_PERIPHERALS_MASK) +#define SYSCON_HARDWARESLEEP_SDMA0_MASK (0x8U) +#define SYSCON_HARDWARESLEEP_SDMA0_SHIFT (3U) +#define SYSCON_HARDWARESLEEP_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HARDWARESLEEP_SDMA0_SHIFT)) & SYSCON_HARDWARESLEEP_SDMA0_MASK) +#define SYSCON_HARDWARESLEEP_SDMA1_MASK (0x20U) +#define SYSCON_HARDWARESLEEP_SDMA1_SHIFT (5U) +#define SYSCON_HARDWARESLEEP_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HARDWARESLEEP_SDMA1_SHIFT)) & SYSCON_HARDWARESLEEP_SDMA1_MASK) +/*! @} */ + +/*! @name CPUCTRL - CPU Control for multiple processors */ +/*! @{ */ +#define SYSCON_CPUCTRL_CPU1CLKEN_MASK (0x8U) +#define SYSCON_CPUCTRL_CPU1CLKEN_SHIFT (3U) +/*! CPU1CLKEN - CPU1 clock enable. + * 0b1..The CPU1 clock is enabled. + * 0b0..The CPU1 clock is not enabled. + */ +#define SYSCON_CPUCTRL_CPU1CLKEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCTRL_CPU1CLKEN_SHIFT)) & SYSCON_CPUCTRL_CPU1CLKEN_MASK) +#define SYSCON_CPUCTRL_CPU1RSTEN_MASK (0x20U) +#define SYSCON_CPUCTRL_CPU1RSTEN_SHIFT (5U) +/*! CPU1RSTEN - CPU1 reset. + * 0b1..The CPU1 is being reset. + * 0b0..The CPU1 is not being reset. + */ +#define SYSCON_CPUCTRL_CPU1RSTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCTRL_CPU1RSTEN_SHIFT)) & SYSCON_CPUCTRL_CPU1RSTEN_MASK) +/*! @} */ + +/*! @name CPBOOT - Coprocessor Boot Address */ +/*! @{ */ +#define SYSCON_CPBOOT_CPBOOT_MASK (0xFFFFFFFFU) +#define SYSCON_CPBOOT_CPBOOT_SHIFT (0U) +#define SYSCON_CPBOOT_CPBOOT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPBOOT_CPBOOT_SHIFT)) & SYSCON_CPBOOT_CPBOOT_MASK) +/*! @} */ + +/*! @name CPSTACK - Coprocessor Stack Address */ +/*! @{ */ +#define SYSCON_CPSTACK_CPSTACK_MASK (0xFFFFFFFFU) +#define SYSCON_CPSTACK_CPSTACK_SHIFT (0U) +#define SYSCON_CPSTACK_CPSTACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTACK_CPSTACK_SHIFT)) & SYSCON_CPSTACK_CPSTACK_MASK) +/*! @} */ + +/*! @name CPSTAT - CPU Status */ +/*! @{ */ +#define SYSCON_CPSTAT_CPU0SLEEPING_MASK (0x1U) +#define SYSCON_CPSTAT_CPU0SLEEPING_SHIFT (0U) +/*! CPU0SLEEPING - The CPU0 sleeping state. + * 0b1..the CPU is sleeping. + * 0b0..the CPU is not sleeping. + */ +#define SYSCON_CPSTAT_CPU0SLEEPING(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CPU0SLEEPING_SHIFT)) & SYSCON_CPSTAT_CPU0SLEEPING_MASK) +#define SYSCON_CPSTAT_CPU1SLEEPING_MASK (0x2U) +#define SYSCON_CPSTAT_CPU1SLEEPING_SHIFT (1U) +/*! CPU1SLEEPING - The CPU1 sleeping state. + * 0b1..the CPU is sleeping. + * 0b0..the CPU is not sleeping. + */ +#define SYSCON_CPSTAT_CPU1SLEEPING(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CPU1SLEEPING_SHIFT)) & SYSCON_CPSTAT_CPU1SLEEPING_MASK) +#define SYSCON_CPSTAT_CPU0LOCKUP_MASK (0x4U) +#define SYSCON_CPSTAT_CPU0LOCKUP_SHIFT (2U) +/*! CPU0LOCKUP - The CPU0 lockup state. + * 0b1..the CPU is in lockup. + * 0b0..the CPU is not in lockup. + */ +#define SYSCON_CPSTAT_CPU0LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CPU0LOCKUP_SHIFT)) & SYSCON_CPSTAT_CPU0LOCKUP_MASK) +#define SYSCON_CPSTAT_CPU1LOCKUP_MASK (0x8U) +#define SYSCON_CPSTAT_CPU1LOCKUP_SHIFT (3U) +/*! CPU1LOCKUP - The CPU1 lockup state. + * 0b1..the CPU is in lockup. + * 0b0..the CPU is not in lockup. + */ +#define SYSCON_CPSTAT_CPU1LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CPU1LOCKUP_SHIFT)) & SYSCON_CPSTAT_CPU1LOCKUP_MASK) +/*! @} */ + +/*! @name DICE_REG0 - Composite Device Identifier */ +/*! @{ */ +#define SYSCON_DICE_REG0_DICE_REG0_MASK (0xFFFFFFFFU) +#define SYSCON_DICE_REG0_DICE_REG0_SHIFT (0U) +#define SYSCON_DICE_REG0_DICE_REG0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DICE_REG0_DICE_REG0_SHIFT)) & SYSCON_DICE_REG0_DICE_REG0_MASK) +/*! @} */ + +/*! @name DICE_REG1 - Composite Device Identifier */ +/*! @{ */ +#define SYSCON_DICE_REG1_DICE_REG1_MASK (0xFFFFFFFFU) +#define SYSCON_DICE_REG1_DICE_REG1_SHIFT (0U) +#define SYSCON_DICE_REG1_DICE_REG1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DICE_REG1_DICE_REG1_SHIFT)) & SYSCON_DICE_REG1_DICE_REG1_MASK) +/*! @} */ + +/*! @name DICE_REG2 - Composite Device Identifier */ +/*! @{ */ +#define SYSCON_DICE_REG2_DICE_REG2_MASK (0xFFFFFFFFU) +#define SYSCON_DICE_REG2_DICE_REG2_SHIFT (0U) +#define SYSCON_DICE_REG2_DICE_REG2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DICE_REG2_DICE_REG2_SHIFT)) & SYSCON_DICE_REG2_DICE_REG2_MASK) +/*! @} */ + +/*! @name DICE_REG3 - Composite Device Identifier */ +/*! @{ */ +#define SYSCON_DICE_REG3_DICE_REG3_MASK (0xFFFFFFFFU) +#define SYSCON_DICE_REG3_DICE_REG3_SHIFT (0U) +#define SYSCON_DICE_REG3_DICE_REG3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DICE_REG3_DICE_REG3_SHIFT)) & SYSCON_DICE_REG3_DICE_REG3_MASK) +/*! @} */ + +/*! @name DICE_REG4 - Composite Device Identifier */ +/*! @{ */ +#define SYSCON_DICE_REG4_DICE_REG4_MASK (0xFFFFFFFFU) +#define SYSCON_DICE_REG4_DICE_REG4_SHIFT (0U) +#define SYSCON_DICE_REG4_DICE_REG4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DICE_REG4_DICE_REG4_SHIFT)) & SYSCON_DICE_REG4_DICE_REG4_MASK) +/*! @} */ + +/*! @name DICE_REG5 - Composite Device Identifier */ +/*! @{ */ +#define SYSCON_DICE_REG5_DICE_REG5_MASK (0xFFFFFFFFU) +#define SYSCON_DICE_REG5_DICE_REG5_SHIFT (0U) +#define SYSCON_DICE_REG5_DICE_REG5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DICE_REG5_DICE_REG5_SHIFT)) & SYSCON_DICE_REG5_DICE_REG5_MASK) +/*! @} */ + +/*! @name DICE_REG6 - Composite Device Identifier */ +/*! @{ */ +#define SYSCON_DICE_REG6_DICE_REG6_MASK (0xFFFFFFFFU) +#define SYSCON_DICE_REG6_DICE_REG6_SHIFT (0U) +#define SYSCON_DICE_REG6_DICE_REG6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DICE_REG6_DICE_REG6_SHIFT)) & SYSCON_DICE_REG6_DICE_REG6_MASK) +/*! @} */ + +/*! @name DICE_REG7 - Composite Device Identifier */ +/*! @{ */ +#define SYSCON_DICE_REG7_DICE_REG7_MASK (0xFFFFFFFFU) +#define SYSCON_DICE_REG7_DICE_REG7_SHIFT (0U) +#define SYSCON_DICE_REG7_DICE_REG7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DICE_REG7_DICE_REG7_SHIFT)) & SYSCON_DICE_REG7_DICE_REG7_MASK) +/*! @} */ + +/*! @name CLOCK_CTRL - Various system clock controls : Flash clock (48 MHz) control, clocks to Frequency Measures */ +/*! @{ */ +#define SYSCON_CLOCK_CTRL_FLASH48MHZ_ENA_MASK (0x1U) +#define SYSCON_CLOCK_CTRL_FLASH48MHZ_ENA_SHIFT (0U) +/*! FLASH48MHZ_ENA - Enable Flash 48 MHz clock. + * 0b1..The clock is enabled. + * 0b0..The clock is not enabled. + */ +#define SYSCON_CLOCK_CTRL_FLASH48MHZ_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FLASH48MHZ_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FLASH48MHZ_ENA_MASK) +#define SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_MASK (0x2U) +#define SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_SHIFT (1U) +/*! XTAL32MHZ_FREQM_ENA - Enable XTAL32MHz clock for Frequency Measure module. + * 0b1..The clock is enabled. + * 0b0..The clock is not enabled. + */ +#define SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_MASK) +#define SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_MASK (0x4U) +#define SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_SHIFT (2U) +/*! FRO1MHZ_UTICK_ENA - Enable FRO 1MHz clock for Frequency Measure module and for UTICK. + * 0b1..The clock is enabled. + * 0b0..The clock is not enabled. + */ +#define SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_MASK) +#define SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_MASK (0x8U) +#define SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_SHIFT (3U) +/*! FRO12MHZ_FREQM_ENA - Enable FRO 12MHz clock for Frequency Measure module. + * 0b1..The clock is enabled. + * 0b0..The clock is not enabled. + */ +#define SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_MASK) +#define SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_MASK (0x10U) +#define SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_SHIFT (4U) +/*! FRO_HF_FREQM_ENA - Enable FRO 96MHz clock for Frequency Measure module. + * 0b1..The clock is enabled. + * 0b0..The clock is not enabled. + */ +#define SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_MASK) +#define SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK (0x20U) +#define SYSCON_CLOCK_CTRL_CLKIN_ENA_SHIFT (5U) +/*! CLKIN_ENA - Enable clock_in clock for clock module. + * 0b1..The clock is enabled. + * 0b0..The clock is not enabled. + */ +#define SYSCON_CLOCK_CTRL_CLKIN_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_CLKIN_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK) +#define SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK (0x40U) +#define SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_SHIFT (6U) +/*! FRO1MHZ_CLK_ENA - Enable FRO 1MHz clock for clock muxing in clock gen. + * 0b1..The clock is enabled. + * 0b0..The clock is not enabled. + */ +#define SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK) +#define SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_MASK (0x80U) +#define SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_SHIFT (7U) +/*! ANA_FRO12M_CLK_ENA - Enable FRO 12MHz clock for analog control of the FRO 192MHz. + * 0b1..The clock is enabled. + * 0b0..The clock is not enabled. + */ +#define SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_MASK) +#define SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_MASK (0x100U) +#define SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_SHIFT (8U) +/*! XO_CAL_CLK_ENA - Enable clock for cristal oscilator calibration. + * 0b1..The clock is enabled. + * 0b0..The clock is not enabled. + */ +#define SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_MASK) +#define SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA_MASK (0x200U) +#define SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA_SHIFT (9U) +/*! PLU_DEGLITCH_CLK_ENA - Enable clocks FRO_1MHz and FRO_12MHz for PLU deglitching. + * 0b1..The clock is enabled. + * 0b0..The clock is not enabled. + */ +#define SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA_MASK) +/*! @} */ + +/*! @name COMP_INT_CTRL - Comparator Interrupt control */ +/*! @{ */ +#define SYSCON_COMP_INT_CTRL_INT_ENABLE_MASK (0x1U) +#define SYSCON_COMP_INT_CTRL_INT_ENABLE_SHIFT (0U) +/*! INT_ENABLE - Analog Comparator interrupt enable control:. + * 0b1..interrupt enable. + * 0b0..interrupt disable. + */ +#define SYSCON_COMP_INT_CTRL_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_ENABLE_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_ENABLE_MASK) +#define SYSCON_COMP_INT_CTRL_INT_CLEAR_MASK (0x2U) +#define SYSCON_COMP_INT_CTRL_INT_CLEAR_SHIFT (1U) +/*! INT_CLEAR - Analog Comparator interrupt clear. + * 0b0..No effect. + * 0b1..Clear the interrupt. Self-cleared bit. + */ +#define SYSCON_COMP_INT_CTRL_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_CLEAR_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_CLEAR_MASK) +#define SYSCON_COMP_INT_CTRL_INT_CTRL_MASK (0x1CU) +#define SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT (2U) +/*! INT_CTRL - Comparator interrupt type selector:. + * 0b000..The analog comparator interrupt edge sensitive is disabled. + * 0b010..analog comparator interrupt is rising edge sensitive. + * 0b100..analog comparator interrupt is falling edge sensitive. + * 0b110..analog comparator interrupt is rising and falling edge sensitive. + * 0b001..The analog comparator interrupt level sensitive is disabled. + * 0b011..Analog Comparator interrupt is high level sensitive. + * 0b101..Analog Comparator interrupt is low level sensitive. + * 0b111..The analog comparator interrupt level sensitive is disabled. + */ +#define SYSCON_COMP_INT_CTRL_INT_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_CTRL_MASK) +#define SYSCON_COMP_INT_CTRL_INT_SOURCE_MASK (0x20U) +#define SYSCON_COMP_INT_CTRL_INT_SOURCE_SHIFT (5U) +/*! INT_SOURCE - Select which Analog comparator output (filtered our un-filtered) is used for interrupt detection. + * 0b0..Select Analog Comparator filtered output as input for interrupt detection. + * 0b1..Select Analog Comparator raw output (unfiltered) as input for interrupt detection. Must be used when + * Analog comparator is used as wake up source in Power down mode. + */ +#define SYSCON_COMP_INT_CTRL_INT_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_SOURCE_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_SOURCE_MASK) +/*! @} */ + +/*! @name COMP_INT_STATUS - Comparator Interrupt status */ +/*! @{ */ +#define SYSCON_COMP_INT_STATUS_STATUS_MASK (0x1U) +#define SYSCON_COMP_INT_STATUS_STATUS_SHIFT (0U) +/*! STATUS - Interrupt status BEFORE Interrupt Enable. + * 0b0..no interrupt pending. + * 0b1..interrupt pending. + */ +#define SYSCON_COMP_INT_STATUS_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_STATUS_STATUS_SHIFT)) & SYSCON_COMP_INT_STATUS_STATUS_MASK) +#define SYSCON_COMP_INT_STATUS_INT_STATUS_MASK (0x2U) +#define SYSCON_COMP_INT_STATUS_INT_STATUS_SHIFT (1U) +/*! INT_STATUS - Interrupt status AFTER Interrupt Enable. + * 0b0..no interrupt pending. + * 0b1..interrupt pending. + */ +#define SYSCON_COMP_INT_STATUS_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_STATUS_INT_STATUS_SHIFT)) & SYSCON_COMP_INT_STATUS_INT_STATUS_MASK) +#define SYSCON_COMP_INT_STATUS_VAL_MASK (0x4U) +#define SYSCON_COMP_INT_STATUS_VAL_SHIFT (2U) +/*! VAL - comparator analog output. + * 0b1..P+ is greater than P-. + * 0b0..P+ is smaller than P-. + */ +#define SYSCON_COMP_INT_STATUS_VAL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_STATUS_VAL_SHIFT)) & SYSCON_COMP_INT_STATUS_VAL_MASK) +/*! @} */ + +/*! @name AUTOCLKGATEOVERRIDE - Control automatic clock gating */ +/*! @{ */ +#define SYSCON_AUTOCLKGATEOVERRIDE_ROM_MASK (0x1U) +#define SYSCON_AUTOCLKGATEOVERRIDE_ROM_SHIFT (0U) +/*! ROM - Control automatic clock gating of ROM controller. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_ROM_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_ROM_MASK) +#define SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL_MASK (0x2U) +#define SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL_SHIFT (1U) +/*! RAMX_CTRL - Control automatic clock gating of RAMX controller. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL_MASK) +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL_MASK (0x4U) +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL_SHIFT (2U) +/*! RAM0_CTRL - Control automatic clock gating of RAM0 controller. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL_MASK) +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL_MASK (0x8U) +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL_SHIFT (3U) +/*! RAM1_CTRL - Control automatic clock gating of RAM1 controller. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL_MASK) +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL_MASK (0x10U) +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL_SHIFT (4U) +/*! RAM2_CTRL - Control automatic clock gating of RAM2 controller. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL_MASK) +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM3_CTRL_MASK (0x20U) +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM3_CTRL_SHIFT (5U) +/*! RAM3_CTRL - Control automatic clock gating of RAM3 controller. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM3_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM3_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM3_CTRL_MASK) +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM4_CTRL_MASK (0x40U) +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM4_CTRL_SHIFT (6U) +/*! RAM4_CTRL - Control automatic clock gating of RAM4 controller. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM4_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM4_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM4_CTRL_MASK) +#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_MASK (0x80U) +#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_SHIFT (7U) +/*! SYNC0_APB - Control automatic clock gating of synchronous bridge controller 0. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_MASK) +#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_MASK (0x100U) +#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_SHIFT (8U) +/*! SYNC1_APB - Control automatic clock gating of synchronous bridge controller 1. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_MASK) +#define SYSCON_AUTOCLKGATEOVERRIDE_FLASH_MASK (0x200U) +#define SYSCON_AUTOCLKGATEOVERRIDE_FLASH_SHIFT (9U) +/*! FLASH - Control automatic clock gating of FLASH controller. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_FLASH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_FLASH_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_FLASH_MASK) +#define SYSCON_AUTOCLKGATEOVERRIDE_FMC_MASK (0x400U) +#define SYSCON_AUTOCLKGATEOVERRIDE_FMC_SHIFT (10U) +/*! FMC - Control automatic clock gating of FMC controller. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_FMC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_FMC_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_FMC_MASK) +#define SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_MASK (0x800U) +#define SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_SHIFT (11U) +/*! CRCGEN - Control automatic clock gating of CRCGEN controller. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_MASK) +#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_MASK (0x1000U) +#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_SHIFT (12U) +/*! SDMA0 - Control automatic clock gating of DMA0 controller. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_MASK) +#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_MASK (0x2000U) +#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_SHIFT (13U) +/*! SDMA1 - Control automatic clock gating of DMA1 controller. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_MASK) +#define SYSCON_AUTOCLKGATEOVERRIDE_USB_MASK (0x4000U) +#define SYSCON_AUTOCLKGATEOVERRIDE_USB_SHIFT (14U) +/*! USB - Control automatic clock gating of USB controller. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_USB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_USB_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_USB_MASK) +#define SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_MASK (0x8000U) +#define SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_SHIFT (15U) +/*! SYSCON - Control automatic clock gating of synchronous system controller registers bank. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_SYSCON(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_MASK) +#define SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_MASK (0xFFFF0000U) +#define SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_SHIFT (16U) +/*! ENABLEUPDATE - The value 0xC0DE must be written for AUTOCLKGATEOVERRIDE registers fields updates to have effect. + * 0b1100000011011110..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0000000000000000..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_MASK) +/*! @} */ + +/*! @name GPIOPSYNC - Enable bypass of the first stage of synchonization inside GPIO_INT module */ +/*! @{ */ +#define SYSCON_GPIOPSYNC_PSYNC_MASK (0x1U) +#define SYSCON_GPIOPSYNC_PSYNC_SHIFT (0U) +/*! PSYNC - Enable bypass of the first stage of synchonization inside GPIO_INT module. + * 0b1..bypass of the first stage of synchonization inside GPIO_INT module. + * 0b0..use the first stage of synchonization inside GPIO_INT module. + */ +#define SYSCON_GPIOPSYNC_PSYNC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_GPIOPSYNC_PSYNC_SHIFT)) & SYSCON_GPIOPSYNC_PSYNC_MASK) +/*! @} */ + +/*! @name DEBUG_LOCK_EN - Control write access to security registers -- FOR INTERNAl USE ONLY */ +/*! @{ */ +#define SYSCON_DEBUG_LOCK_EN_LOCK_ALL_MASK (0xFU) +#define SYSCON_DEBUG_LOCK_EN_LOCK_ALL_SHIFT (0U) +/*! LOCK_ALL - Control write access to CODESECURITYPROTTEST, CODESECURITYPROTCPU0, + * CODESECURITYPROTCPU1, CM33_DEBUG_FEATURES, MCM33_DEBUG_FEATURES and DBG_AUTH_SCRATCH registers. + * 0b1010..1010: Enable write access to all 6 registers. + * 0b0000..Any other value than b1010: disable write access to all 6 registers. + */ +#define SYSCON_DEBUG_LOCK_EN_LOCK_ALL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_LOCK_EN_LOCK_ALL_SHIFT)) & SYSCON_DEBUG_LOCK_EN_LOCK_ALL_MASK) +/*! @} */ + +/*! @name DEBUG_FEATURES - Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control -- FOR INTERNAl USE ONLY */ +/*! @{ */ +#define SYSCON_DEBUG_FEATURES_CM33_DBGEN_MASK (0x3U) +#define SYSCON_DEBUG_FEATURES_CM33_DBGEN_SHIFT (0U) +/*! CM33_DBGEN - CM33 (CPU0) Invasive debug control:. + * 0b10..10: Invasive debug is enabled. + * 0b01..Any other value than b10: invasive debug is disable. + */ +#define SYSCON_DEBUG_FEATURES_CM33_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CM33_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CM33_DBGEN_MASK) +#define SYSCON_DEBUG_FEATURES_CM33_NIDEN_MASK (0xCU) +#define SYSCON_DEBUG_FEATURES_CM33_NIDEN_SHIFT (2U) +/*! CM33_NIDEN - CM33 (CPU0) Non Invasive debug control:. + * 0b10..10: Invasive debug is enabled. + * 0b01..Any other value than b10: invasive debug is disable. + */ +#define SYSCON_DEBUG_FEATURES_CM33_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CM33_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CM33_NIDEN_MASK) +#define SYSCON_DEBUG_FEATURES_CM33_SPIDEN_MASK (0x30U) +#define SYSCON_DEBUG_FEATURES_CM33_SPIDEN_SHIFT (4U) +/*! CM33_SPIDEN - CM33 (CPU0) Secure Invasive debug control:. + * 0b10..10: Invasive debug is enabled. + * 0b01..Any other value than b10: invasive debug is disable. + */ +#define SYSCON_DEBUG_FEATURES_CM33_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CM33_SPIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CM33_SPIDEN_MASK) +#define SYSCON_DEBUG_FEATURES_CM33_SPNIDEN_MASK (0xC0U) +#define SYSCON_DEBUG_FEATURES_CM33_SPNIDEN_SHIFT (6U) +/*! CM33_SPNIDEN - CM33 (CPU0) Secure Non Invasive debug control:. + * 0b10..10: Invasive debug is enabled. + * 0b01..Any other value than b10: invasive debug is disable. + */ +#define SYSCON_DEBUG_FEATURES_CM33_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CM33_SPNIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CM33_SPNIDEN_MASK) +#define SYSCON_DEBUG_FEATURES_MCM33_DBGEN_MASK (0x300U) +#define SYSCON_DEBUG_FEATURES_MCM33_DBGEN_SHIFT (8U) +/*! MCM33_DBGEN - Micro-CM33 (CPU1) Invasive debug control:. + * 0b10..10: Invasive debug is enabled. + * 0b01..Any other value than b10: invasive debug is disable. + */ +#define SYSCON_DEBUG_FEATURES_MCM33_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_MCM33_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_MCM33_DBGEN_MASK) +#define SYSCON_DEBUG_FEATURES_MCM33_NIDEN_MASK (0xC00U) +#define SYSCON_DEBUG_FEATURES_MCM33_NIDEN_SHIFT (10U) +/*! MCM33_NIDEN - Micro-CM33 (CPU1) Non Invasive debug control:. + * 0b10..10: Invasive debug is enabled. + * 0b01..Any other value than b10: invasive debug is disable. + */ +#define SYSCON_DEBUG_FEATURES_MCM33_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_MCM33_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_MCM33_NIDEN_MASK) +/*! @} */ + +/*! @name DEBUG_FEATURES_DP - Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control DUPLICATE register -- FOR INTERNAl USE ONLY */ +/*! @{ */ +#define SYSCON_DEBUG_FEATURES_DP_CM33_DBGEN_MASK (0x3U) +#define SYSCON_DEBUG_FEATURES_DP_CM33_DBGEN_SHIFT (0U) +/*! CM33_DBGEN - CM33 (CPU0) Invasive debug control:. + * 0b10..10: Invasive debug is enabled. + * 0b01..Any other value than b10: invasive debug is disable. + */ +#define SYSCON_DEBUG_FEATURES_DP_CM33_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CM33_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CM33_DBGEN_MASK) +#define SYSCON_DEBUG_FEATURES_DP_CM33_NIDEN_MASK (0xCU) +#define SYSCON_DEBUG_FEATURES_DP_CM33_NIDEN_SHIFT (2U) +/*! CM33_NIDEN - CM33 (CPU0) Non Invasive debug control:. + * 0b10..10: Invasive debug is enabled. + * 0b01..Any other value than b10: invasive debug is disable. + */ +#define SYSCON_DEBUG_FEATURES_DP_CM33_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CM33_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CM33_NIDEN_MASK) +#define SYSCON_DEBUG_FEATURES_DP_CM33_SPIDEN_MASK (0x30U) +#define SYSCON_DEBUG_FEATURES_DP_CM33_SPIDEN_SHIFT (4U) +/*! CM33_SPIDEN - CM33 (CPU0) Secure Invasive debug control:. + * 0b10..10: Invasive debug is enabled. + * 0b01..Any other value than b10: invasive debug is disable. + */ +#define SYSCON_DEBUG_FEATURES_DP_CM33_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CM33_SPIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CM33_SPIDEN_MASK) +#define SYSCON_DEBUG_FEATURES_DP_CM33_SPNIDEN_MASK (0xC0U) +#define SYSCON_DEBUG_FEATURES_DP_CM33_SPNIDEN_SHIFT (6U) +/*! CM33_SPNIDEN - CM33 (CPU0) Secure Non Invasive debug control:. + * 0b10..10: Invasive debug is enabled. + * 0b01..Any other value than b10: invasive debug is disable. + */ +#define SYSCON_DEBUG_FEATURES_DP_CM33_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CM33_SPNIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CM33_SPNIDEN_MASK) +#define SYSCON_DEBUG_FEATURES_DP_MCM33_DBGEN_MASK (0x300U) +#define SYSCON_DEBUG_FEATURES_DP_MCM33_DBGEN_SHIFT (8U) +/*! MCM33_DBGEN - Micro-CM33 (CPU1) Invasive debug control:. + * 0b10..10: Invasive debug is enabled. + * 0b01..Any other value than b10: invasive debug is disable. + */ +#define SYSCON_DEBUG_FEATURES_DP_MCM33_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_MCM33_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_MCM33_DBGEN_MASK) +#define SYSCON_DEBUG_FEATURES_DP_MCM33_NIDEN_MASK (0xC00U) +#define SYSCON_DEBUG_FEATURES_DP_MCM33_NIDEN_SHIFT (10U) +/*! MCM33_NIDEN - Micro-CM33 (CPU1) Non Invasive debug control:. + * 0b10..10: Invasive debug is enabled. + * 0b01..Any other value than b10: invasive debug is disable. + */ +#define SYSCON_DEBUG_FEATURES_DP_MCM33_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_MCM33_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_MCM33_NIDEN_MASK) +/*! @} */ + +/*! @name CODESECURITYPROTTEST - Security code to allow test (Design for Testability) access -- FOR INTERNAl USE ONLY */ +/*! @{ */ +#define SYSCON_CODESECURITYPROTTEST_SEC_CODE_MASK (0xFFFFFFFFU) +#define SYSCON_CODESECURITYPROTTEST_SEC_CODE_SHIFT (0U) +/*! SEC_CODE - Security code to allow test access : 0x12345678. + * 0b00010010001101000101011001111000..Security code to allow test access. + * 0b00000000000000000000000000000000..test access is not allowed. + */ +#define SYSCON_CODESECURITYPROTTEST_SEC_CODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CODESECURITYPROTTEST_SEC_CODE_SHIFT)) & SYSCON_CODESECURITYPROTTEST_SEC_CODE_MASK) +/*! @} */ + +/*! @name CODESECURITYPROTCPU0 - Security code to allow CPU0 (CM33) Debug Access Port (DAP) -- FOR INTERNAl USE ONLY */ +/*! @{ */ +#define SYSCON_CODESECURITYPROTCPU0_SEC_CODE_MASK (0xFFFFFFFFU) +#define SYSCON_CODESECURITYPROTCPU0_SEC_CODE_SHIFT (0U) +/*! SEC_CODE - Security code to allow CPU0 DAP: 0x12345678. + * 0b00010010001101000101011001111000..Security code to allow CPU0 DAP. + * 0b00000000000000000000000000000000..CPU0 DAP is not allowed. + */ +#define SYSCON_CODESECURITYPROTCPU0_SEC_CODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CODESECURITYPROTCPU0_SEC_CODE_SHIFT)) & SYSCON_CODESECURITYPROTCPU0_SEC_CODE_MASK) +/*! @} */ + +/*! @name CODESECURITYPROTCPU1 - Security code to allow CPU1 (Micro CM33) Debug Access Port (DAP) -- FOR INTERNAl USE ONLY */ +/*! @{ */ +#define SYSCON_CODESECURITYPROTCPU1_SEC_CODE_MASK (0xFFFFFFFFU) +#define SYSCON_CODESECURITYPROTCPU1_SEC_CODE_SHIFT (0U) +/*! SEC_CODE - Security code to allow CPU1 DAP: 0x12345678. + * 0b00010010001101000101011001111000..Security code to allow CPU1 DAP. + * 0b00000000000000000000000000000000..CPU1 DAP is not allowed. + */ +#define SYSCON_CODESECURITYPROTCPU1_SEC_CODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CODESECURITYPROTCPU1_SEC_CODE_SHIFT)) & SYSCON_CODESECURITYPROTCPU1_SEC_CODE_MASK) +/*! @} */ + +/*! @name KEY_BLOCK - block quiddikey/PUF all index. -- FOR INTERNAL USE ONLY */ +/*! @{ */ +#define SYSCON_KEY_BLOCK_KEY_BLOCK_MASK (0xFFFFFFFFU) +#define SYSCON_KEY_BLOCK_KEY_BLOCK_SHIFT (0U) +#define SYSCON_KEY_BLOCK_KEY_BLOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_KEY_BLOCK_KEY_BLOCK_SHIFT)) & SYSCON_KEY_BLOCK_KEY_BLOCK_MASK) +/*! @} */ + +/*! @name DEBUG_AUTH_SCRATCH - Debug authentication scratch registers -- FOR INTERNAL USE ONLY */ +/*! @{ */ +#define SYSCON_DEBUG_AUTH_SCRATCH_SCRATCH_MASK (0xFFFFFFFFU) +#define SYSCON_DEBUG_AUTH_SCRATCH_SCRATCH_SHIFT (0U) +#define SYSCON_DEBUG_AUTH_SCRATCH_SCRATCH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_AUTH_SCRATCH_SCRATCH_SHIFT)) & SYSCON_DEBUG_AUTH_SCRATCH_SCRATCH_MASK) +/*! @} */ + +/*! @name CPUCFG - CPUs configuration register */ +/*! @{ */ +#define SYSCON_CPUCFG_CPU1ENABLE_MASK (0x4U) +#define SYSCON_CPUCFG_CPU1ENABLE_SHIFT (2U) +/*! CPU1ENABLE - Enable CPU1. + * 0b0..CPU1 is disable (Processor in reset). + * 0b1..CPU1 is enable. + */ +#define SYSCON_CPUCFG_CPU1ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCFG_CPU1ENABLE_SHIFT)) & SYSCON_CPUCFG_CPU1ENABLE_MASK) +/*! @} */ + +/*! @name PERIPHENCFG - peripheral enable configuration -- FOR INTERNAL USE ONLY */ +/*! @{ */ +#define SYSCON_PERIPHENCFG_SCTEN_MASK (0x1U) +#define SYSCON_PERIPHENCFG_SCTEN_SHIFT (0U) +/*! SCTEN - SCT enable. + * 0b1..peripheral is enable. + * 0b0..peripheral is disable. + */ +#define SYSCON_PERIPHENCFG_SCTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PERIPHENCFG_SCTEN_SHIFT)) & SYSCON_PERIPHENCFG_SCTEN_MASK) +#define SYSCON_PERIPHENCFG_ADCEN_MASK (0x2U) +#define SYSCON_PERIPHENCFG_ADCEN_SHIFT (1U) +/*! ADCEN - ADC enable. + * 0b1..peripheral is enable. + * 0b0..peripheral is disable. + */ +#define SYSCON_PERIPHENCFG_ADCEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PERIPHENCFG_ADCEN_SHIFT)) & SYSCON_PERIPHENCFG_ADCEN_MASK) +#define SYSCON_PERIPHENCFG_USB0EN_MASK (0x4U) +#define SYSCON_PERIPHENCFG_USB0EN_SHIFT (2U) +/*! USB0EN - USB0 enable. + * 0b1..peripheral is enable. + * 0b0..peripheral is disable. + */ +#define SYSCON_PERIPHENCFG_USB0EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PERIPHENCFG_USB0EN_SHIFT)) & SYSCON_PERIPHENCFG_USB0EN_MASK) +#define SYSCON_PERIPHENCFG_PUFFEN_MASK (0x40U) +#define SYSCON_PERIPHENCFG_PUFFEN_SHIFT (6U) +/*! PUFFEN - Puff enable. + * 0b1..peripheral is enable. + * 0b0..peripheral is disable. + */ +#define SYSCON_PERIPHENCFG_PUFFEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PERIPHENCFG_PUFFEN_SHIFT)) & SYSCON_PERIPHENCFG_PUFFEN_MASK) +#define SYSCON_PERIPHENCFG_USB1EN_MASK (0x400U) +#define SYSCON_PERIPHENCFG_USB1EN_SHIFT (10U) +/*! USB1EN - USB1 enable. + * 0b1..peripheral is enable. + * 0b0..peripheral is disable. + */ +#define SYSCON_PERIPHENCFG_USB1EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PERIPHENCFG_USB1EN_SHIFT)) & SYSCON_PERIPHENCFG_USB1EN_MASK) +#define SYSCON_PERIPHENCFG_SDIOEN_MASK (0x800U) +#define SYSCON_PERIPHENCFG_SDIOEN_SHIFT (11U) +/*! SDIOEN - SDIO enable. + * 0b1..peripheral is enable. + * 0b0..peripheral is disable. + */ +#define SYSCON_PERIPHENCFG_SDIOEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PERIPHENCFG_SDIOEN_SHIFT)) & SYSCON_PERIPHENCFG_SDIOEN_MASK) +#define SYSCON_PERIPHENCFG_HASHEN_MASK (0x1000U) +#define SYSCON_PERIPHENCFG_HASHEN_SHIFT (12U) +/*! HASHEN - HASH enable. + * 0b1..peripheral is enable. + * 0b0..peripheral is disable. + */ +#define SYSCON_PERIPHENCFG_HASHEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PERIPHENCFG_HASHEN_SHIFT)) & SYSCON_PERIPHENCFG_HASHEN_MASK) +#define SYSCON_PERIPHENCFG_PRINCEEN_MASK (0x4000U) +#define SYSCON_PERIPHENCFG_PRINCEEN_SHIFT (14U) +/*! PRINCEEN - PRINCE enable. + * 0b1..peripheral is enable. + * 0b0..peripheral is disable. + */ +#define SYSCON_PERIPHENCFG_PRINCEEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PERIPHENCFG_PRINCEEN_SHIFT)) & SYSCON_PERIPHENCFG_PRINCEEN_MASK) +/*! @} */ + +/*! @name DEVICE_ID0 - Device ID */ +/*! @{ */ +#define SYSCON_DEVICE_ID0_PARTCONFIG_MASK (0xFFU) +#define SYSCON_DEVICE_ID0_PARTCONFIG_SHIFT (0U) +#define SYSCON_DEVICE_ID0_PARTCONFIG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_PARTCONFIG_SHIFT)) & SYSCON_DEVICE_ID0_PARTCONFIG_MASK) +#define SYSCON_DEVICE_ID0_SRAM_SIZE_MASK (0xF00U) +#define SYSCON_DEVICE_ID0_SRAM_SIZE_SHIFT (8U) +#define SYSCON_DEVICE_ID0_SRAM_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_SRAM_SIZE_SHIFT)) & SYSCON_DEVICE_ID0_SRAM_SIZE_MASK) +#define SYSCON_DEVICE_ID0_FLASH_SIZE_MASK (0x7000U) +#define SYSCON_DEVICE_ID0_FLASH_SIZE_SHIFT (12U) +#define SYSCON_DEVICE_ID0_FLASH_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_FLASH_SIZE_SHIFT)) & SYSCON_DEVICE_ID0_FLASH_SIZE_MASK) +#define SYSCON_DEVICE_ID0_ROM_REV_MINOR_MASK (0xF00000U) +#define SYSCON_DEVICE_ID0_ROM_REV_MINOR_SHIFT (20U) +#define SYSCON_DEVICE_ID0_ROM_REV_MINOR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_ROM_REV_MINOR_SHIFT)) & SYSCON_DEVICE_ID0_ROM_REV_MINOR_MASK) +#define SYSCON_DEVICE_ID0_MODELNUM_EXTENTION_MASK (0x7000000U) +#define SYSCON_DEVICE_ID0_MODELNUM_EXTENTION_SHIFT (24U) +#define SYSCON_DEVICE_ID0_MODELNUM_EXTENTION(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_MODELNUM_EXTENTION_SHIFT)) & SYSCON_DEVICE_ID0_MODELNUM_EXTENTION_MASK) +/*! @} */ + +/*! @name DIEID - Chip revision ID and Number */ +/*! @{ */ +#define SYSCON_DIEID_REV_ID_MASK (0xFU) +#define SYSCON_DIEID_REV_ID_SHIFT (0U) +#define SYSCON_DIEID_REV_ID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DIEID_REV_ID_SHIFT)) & SYSCON_DIEID_REV_ID_MASK) +#define SYSCON_DIEID_MCO_NUM_IN_DIE_ID_MASK (0xFFFFF0U) +#define SYSCON_DIEID_MCO_NUM_IN_DIE_ID_SHIFT (4U) +#define SYSCON_DIEID_MCO_NUM_IN_DIE_ID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DIEID_MCO_NUM_IN_DIE_ID_SHIFT)) & SYSCON_DIEID_MCO_NUM_IN_DIE_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SYSCON_Register_Masks */ + + +/* SYSCON - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral SYSCON base address */ + #define SYSCON_BASE (0x50000000u) + /** Peripheral SYSCON base address */ + #define SYSCON_BASE_NS (0x40000000u) + /** Peripheral SYSCON base pointer */ + #define SYSCON ((SYSCON_Type *)SYSCON_BASE) + /** Peripheral SYSCON base pointer */ + #define SYSCON_NS ((SYSCON_Type *)SYSCON_BASE_NS) + /** Array initializer of SYSCON peripheral base addresses */ + #define SYSCON_BASE_ADDRS { SYSCON_BASE } + /** Array initializer of SYSCON peripheral base pointers */ + #define SYSCON_BASE_PTRS { SYSCON } + /** Array initializer of SYSCON peripheral base addresses */ + #define SYSCON_BASE_ADDRS_NS { SYSCON_BASE_NS } + /** Array initializer of SYSCON peripheral base pointers */ + #define SYSCON_BASE_PTRS_NS { SYSCON_NS } +#else + /** Peripheral SYSCON base address */ + #define SYSCON_BASE (0x40000000u) + /** Peripheral SYSCON base pointer */ + #define SYSCON ((SYSCON_Type *)SYSCON_BASE) + /** Array initializer of SYSCON peripheral base addresses */ + #define SYSCON_BASE_ADDRS { SYSCON_BASE } + /** Array initializer of SYSCON peripheral base pointers */ + #define SYSCON_BASE_PTRS { SYSCON } +#endif + +/*! + * @} + */ /* end of group SYSCON_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SYSCTL Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SYSCTL_Peripheral_Access_Layer SYSCTL Peripheral Access Layer + * @{ + */ + +/** SYSCTL - Register Layout Typedef */ +typedef struct { + __IO uint32_t UPDATELCKOUT; /**< update lock out control, offset: 0x0 */ + uint8_t RESERVED_0[60]; + __IO uint32_t FCCTRLSEL[8]; /**< Selects the source for SCK going into Flexcomm 0..Selects the source for SCK going into Flexcomm 7, array offset: 0x40, array step: 0x4 */ + uint8_t RESERVED_1[32]; + __IO uint32_t SHAREDCTRLSET[2]; /**< Selects sources and data combinations for shared signal set 0...Selects sources and data combinations for shared signal set 1., array offset: 0x80, array step: 0x4 */ + uint8_t RESERVED_2[120]; + __I uint32_t USB_HS_STATUS; /**< Status register for USB HS, offset: 0x100 */ +} SYSCTL_Type; + +/* ---------------------------------------------------------------------------- + -- SYSCTL Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SYSCTL_Register_Masks SYSCTL Register Masks + * @{ + */ + +/*! @name UPDATELCKOUT - update lock out control */ +/*! @{ */ +#define SYSCTL_UPDATELCKOUT_UPDATELCKOUT_MASK (0x1U) +#define SYSCTL_UPDATELCKOUT_UPDATELCKOUT_SHIFT (0U) +/*! UPDATELCKOUT - All Registers + * 0b0..Normal Mode. Can be written to. + * 0b1..Protected Mode. Cannot be written to. + */ +#define SYSCTL_UPDATELCKOUT_UPDATELCKOUT(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_UPDATELCKOUT_UPDATELCKOUT_SHIFT)) & SYSCTL_UPDATELCKOUT_UPDATELCKOUT_MASK) +/*! @} */ + +/*! @name FCCTRLSEL - Selects the source for SCK going into Flexcomm 0..Selects the source for SCK going into Flexcomm 7 */ +/*! @{ */ +#define SYSCTL_FCCTRLSEL_SCKINSEL_MASK (0x3U) +#define SYSCTL_FCCTRLSEL_SCKINSEL_SHIFT (0U) +/*! SCKINSEL - Selects the source for SCK going into this Flexcomm. + * 0b00..Selects the dedicated FCn_SCK function for this Flexcomm. + * 0b01..SCK is taken from shared signal set 0 (defined by SHAREDCTRLSET0). + * 0b10..SCK is taken from shared signal set 1 (defined by SHAREDCTRLSET1). + * 0b11..Reserved. + */ +#define SYSCTL_FCCTRLSEL_SCKINSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_SCKINSEL_SHIFT)) & SYSCTL_FCCTRLSEL_SCKINSEL_MASK) +#define SYSCTL_FCCTRLSEL_WSINSEL_MASK (0x300U) +#define SYSCTL_FCCTRLSEL_WSINSEL_SHIFT (8U) +/*! WSINSEL - Selects the source for WS going into this Flexcomm. + * 0b00..Selects the dedicated (FCn_TXD_SCL_MISO_WS) function for this Flexcomm. + * 0b01..WS is taken from shared signal set 0 (defined by SHAREDCTRLSET0). + * 0b10..WS is taken from shared signal set 1 (defined by SHAREDCTRLSET1). + * 0b11..Reserved. + */ +#define SYSCTL_FCCTRLSEL_WSINSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_WSINSEL_SHIFT)) & SYSCTL_FCCTRLSEL_WSINSEL_MASK) +#define SYSCTL_FCCTRLSEL_DATAINSEL_MASK (0x30000U) +#define SYSCTL_FCCTRLSEL_DATAINSEL_SHIFT (16U) +/*! DATAINSEL - Selects the source for DATA input to this Flexcomm. + * 0b00..Selects the dedicated FCn_RXD_SDA_MOSI_DATA input for this Flexcomm. + * 0b01..Input data is taken from shared signal set 0 (defined by SHAREDCTRLSET0). + * 0b10..Input data is taken from shared signal set 1 (defined by SHAREDCTRLSET1). + * 0b11..Reserved. + */ +#define SYSCTL_FCCTRLSEL_DATAINSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_DATAINSEL_SHIFT)) & SYSCTL_FCCTRLSEL_DATAINSEL_MASK) +#define SYSCTL_FCCTRLSEL_DATAOUTSEL_MASK (0x3000000U) +#define SYSCTL_FCCTRLSEL_DATAOUTSEL_SHIFT (24U) +/*! DATAOUTSEL - Selects the source for DATA output from this Flexcomm. + * 0b00..Selects the dedicated FCn_RXD_SDA_MOSI_DATA output from this Flexcomm. + * 0b01..Output data is taken from shared signal set 0 (defined by SHAREDCTRLSET0). + * 0b10..Output data is taken from shared signal set 1 (defined by SHAREDCTRLSET1). + * 0b11..Reserved. + */ +#define SYSCTL_FCCTRLSEL_DATAOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_DATAOUTSEL_SHIFT)) & SYSCTL_FCCTRLSEL_DATAOUTSEL_MASK) +/*! @} */ + +/* The count of SYSCTL_FCCTRLSEL */ +#define SYSCTL_FCCTRLSEL_COUNT (8U) + +/*! @name SHARECTRLSET_SHAREDCTRLSET - Selects sources and data combinations for shared signal set 0...Selects sources and data combinations for shared signal set 1. */ +/*! @{ */ +#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDSCKSEL_MASK (0x7U) +#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDSCKSEL_SHIFT (0U) +/*! SHAREDSCKSEL - Selects the source for SCK of this shared signal set. + * 0b000..SCK for this shared signal set comes from Flexcomm 0. + * 0b001..SCK for this shared signal set comes from Flexcomm 1. + * 0b010..SCK for this shared signal set comes from Flexcomm 2. + * 0b011..SCK for this shared signal set comes from Flexcomm 3. + * 0b100..SCK for this shared signal set comes from Flexcomm 4. + * 0b101..SCK for this shared signal set comes from Flexcomm 5. + * 0b110..SCK for this shared signal set comes from Flexcomm 6. + * 0b111..SCK for this shared signal set comes from Flexcomm 7. + */ +#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDSCKSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDSCKSEL_SHIFT)) & SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDSCKSEL_MASK) +#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDWSSEL_MASK (0x70U) +#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDWSSEL_SHIFT (4U) +/*! SHAREDWSSEL - Selects the source for WS of this shared signal set. + * 0b000..WS for this shared signal set comes from Flexcomm 0. + * 0b001..WS for this shared signal set comes from Flexcomm 1. + * 0b010..WS for this shared signal set comes from Flexcomm 2. + * 0b011..WS for this shared signal set comes from Flexcomm 3. + * 0b100..WS for this shared signal set comes from Flexcomm 4. + * 0b101..WS for this shared signal set comes from Flexcomm 5. + * 0b110..WS for this shared signal set comes from Flexcomm 6. + * 0b111..WS for this shared signal set comes from Flexcomm 7. + */ +#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDWSSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDWSSEL_SHIFT)) & SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDWSSEL_MASK) +#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDDATASEL_MASK (0x700U) +#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDDATASEL_SHIFT (8U) +/*! SHAREDDATASEL - Selects the source for DATA input for this shared signal set. + * 0b000..DATA input for this shared signal set comes from Flexcomm 0. + * 0b001..DATA input for this shared signal set comes from Flexcomm 1. + * 0b010..DATA input for this shared signal set comes from Flexcomm 2. + * 0b011..DATA input for this shared signal set comes from Flexcomm 3. + * 0b100..DATA input for this shared signal set comes from Flexcomm 4. + * 0b101..DATA input for this shared signal set comes from Flexcomm 5. + * 0b110..DATA input for this shared signal set comes from Flexcomm 6. + * 0b111..DATA input for this shared signal set comes from Flexcomm 7. + */ +#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDDATASEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDDATASEL_SHIFT)) & SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDDATASEL_MASK) +#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC0DATAOUTEN_MASK (0x10000U) +#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC0DATAOUTEN_SHIFT (16U) +/*! FC0DATAOUTEN - Controls FC0 contribution to SHAREDDATAOUT for this shared set. + * 0b0..Data output from FC0 does not contribute to this shared set. + * 0b1..Data output from FC0 does contribute to this shared set. + */ +#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC0DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC0DATAOUTEN_SHIFT)) & SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC0DATAOUTEN_MASK) +#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC1DATAOUTEN_MASK (0x20000U) +#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC1DATAOUTEN_SHIFT (17U) +/*! FC1DATAOUTEN - Controls FC1 contribution to SHAREDDATAOUT for this shared set. + * 0b0..Data output from FC1 does not contribute to this shared set. + * 0b1..Data output from FC1 does contribute to this shared set. + */ +#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC1DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC1DATAOUTEN_SHIFT)) & SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC1DATAOUTEN_MASK) +#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_F20DATAOUTEN_MASK (0x40000U) +#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_F20DATAOUTEN_SHIFT (18U) +/*! F20DATAOUTEN - Controls FC2 contribution to SHAREDDATAOUT for this shared set. + * 0b0..Data output from FC2 does not contribute to this shared set. + * 0b1..Data output from FC2 does contribute to this shared set. + */ +#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_F20DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHARECTRLSET_SHAREDCTRLSET_F20DATAOUTEN_SHIFT)) & SYSCTL_SHARECTRLSET_SHAREDCTRLSET_F20DATAOUTEN_MASK) +#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC3DATAOUTEN_MASK (0x80000U) +#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC3DATAOUTEN_SHIFT (19U) +/*! FC3DATAOUTEN - Controls FC3 contribution to SHAREDDATAOUT for this shared set. + * 0b0..Data output from FC3 does not contribute to this shared set. + * 0b1..Data output from FC3 does contribute to this shared set. + */ +#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC3DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC3DATAOUTEN_SHIFT)) & SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC3DATAOUTEN_MASK) +#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC4DATAOUTEN_MASK (0x100000U) +#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC4DATAOUTEN_SHIFT (20U) +/*! FC4DATAOUTEN - Controls FC4 contribution to SHAREDDATAOUT for this shared set. + * 0b0..Data output from FC4 does not contribute to this shared set. + * 0b1..Data output from FC4 does contribute to this shared set. + */ +#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC4DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC4DATAOUTEN_SHIFT)) & SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC4DATAOUTEN_MASK) +#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC5DATAOUTEN_MASK (0x200000U) +#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC5DATAOUTEN_SHIFT (21U) +/*! FC5DATAOUTEN - Controls FC5 contribution to SHAREDDATAOUT for this shared set. + * 0b0..Data output from FC5 does not contribute to this shared set. + * 0b1..Data output from FC5 does contribute to this shared set. + */ +#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC5DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC5DATAOUTEN_SHIFT)) & SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC5DATAOUTEN_MASK) +#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC6DATAOUTEN_MASK (0x400000U) +#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC6DATAOUTEN_SHIFT (22U) +/*! FC6DATAOUTEN - Controls FC6 contribution to SHAREDDATAOUT for this shared set. + * 0b0..Data output from FC6 does not contribute to this shared set. + * 0b1..Data output from FC6 does contribute to this shared set. + */ +#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC6DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC6DATAOUTEN_SHIFT)) & SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC6DATAOUTEN_MASK) +#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC7DATAOUTEN_MASK (0x800000U) +#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC7DATAOUTEN_SHIFT (23U) +/*! FC7DATAOUTEN - Controls FC7 contribution to SHAREDDATAOUT for this shared set. + * 0b0..Data output from FC7 does not contribute to this shared set. + * 0b1..Data output from FC7 does contribute to this shared set. + */ +#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC7DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC7DATAOUTEN_SHIFT)) & SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC7DATAOUTEN_MASK) +/*! @} */ + +/* The count of SYSCTL_SHARECTRLSET_SHAREDCTRLSET */ +#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_COUNT (2U) + +/*! @name USB_HS_STATUS - Status register for USB HS */ +/*! @{ */ +#define SYSCTL_USB_HS_STATUS_USBHS_3V_NOK_MASK (0x1U) +#define SYSCTL_USB_HS_STATUS_USBHS_3V_NOK_SHIFT (0U) +/*! USBHS_3V_NOK - USB_HS: Low voltage detection on 3.3V supply. + * 0b0..3v3 supply is good. + * 0b1..3v3 supply is too low. + */ +#define SYSCTL_USB_HS_STATUS_USBHS_3V_NOK(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_USB_HS_STATUS_USBHS_3V_NOK_SHIFT)) & SYSCTL_USB_HS_STATUS_USBHS_3V_NOK_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SYSCTL_Register_Masks */ + + +/* SYSCTL - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral SYSCTL base address */ + #define SYSCTL_BASE (0x50023000u) + /** Peripheral SYSCTL base address */ + #define SYSCTL_BASE_NS (0x40023000u) + /** Peripheral SYSCTL base pointer */ + #define SYSCTL ((SYSCTL_Type *)SYSCTL_BASE) + /** Peripheral SYSCTL base pointer */ + #define SYSCTL_NS ((SYSCTL_Type *)SYSCTL_BASE_NS) + /** Array initializer of SYSCTL peripheral base addresses */ + #define SYSCTL_BASE_ADDRS { SYSCTL_BASE } + /** Array initializer of SYSCTL peripheral base pointers */ + #define SYSCTL_BASE_PTRS { SYSCTL } + /** Array initializer of SYSCTL peripheral base addresses */ + #define SYSCTL_BASE_ADDRS_NS { SYSCTL_BASE_NS } + /** Array initializer of SYSCTL peripheral base pointers */ + #define SYSCTL_BASE_PTRS_NS { SYSCTL_NS } +#else + /** Peripheral SYSCTL base address */ + #define SYSCTL_BASE (0x40023000u) + /** Peripheral SYSCTL base pointer */ + #define SYSCTL ((SYSCTL_Type *)SYSCTL_BASE) + /** Array initializer of SYSCTL peripheral base addresses */ + #define SYSCTL_BASE_ADDRS { SYSCTL_BASE } + /** Array initializer of SYSCTL peripheral base pointers */ + #define SYSCTL_BASE_PTRS { SYSCTL } +#endif + +/*! + * @} + */ /* end of group SYSCTL_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USART Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USART_Peripheral_Access_Layer USART Peripheral Access Layer + * @{ + */ + +/** USART - Register Layout Typedef */ +typedef struct { + __IO uint32_t CFG; /**< USART Configuration register. Basic USART configuration settings that typically are not changed during operation., offset: 0x0 */ + __IO uint32_t CTL; /**< USART Control register. USART control settings that are more likely to change during operation., offset: 0x4 */ + __IO uint32_t STAT; /**< USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them., offset: 0x8 */ + __IO uint32_t INTENSET; /**< Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set., offset: 0xC */ + __O uint32_t INTENCLR; /**< Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared., offset: 0x10 */ + uint8_t RESERVED_0[12]; + __IO uint32_t BRG; /**< Baud Rate Generator register. 16-bit integer baud rate divisor value., offset: 0x20 */ + __I uint32_t INTSTAT; /**< Interrupt status register. Reflects interrupts that are currently enabled., offset: 0x24 */ + __IO uint32_t OSR; /**< Oversample selection register for asynchronous communication., offset: 0x28 */ + __IO uint32_t ADDR; /**< Address register for automatic address matching., offset: 0x2C */ + uint8_t RESERVED_1[3536]; + __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */ + __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ + __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */ + uint8_t RESERVED_2[4]; + __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */ + __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */ + __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */ + uint8_t RESERVED_3[4]; + __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ + uint8_t RESERVED_4[12]; + __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */ + uint8_t RESERVED_5[12]; + __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */ + uint8_t RESERVED_6[440]; + __I uint32_t ID; /**< Peripheral identification register., offset: 0xFFC */ +} USART_Type; + +/* ---------------------------------------------------------------------------- + -- USART Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USART_Register_Masks USART Register Masks + * @{ + */ + +/*! @name CFG - USART Configuration register. Basic USART configuration settings that typically are not changed during operation. */ +/*! @{ */ +#define USART_CFG_ENABLE_MASK (0x1U) +#define USART_CFG_ENABLE_SHIFT (0U) +/*! ENABLE - USART Enable. + * 0b0..Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0, + * all USART interrupts and DMA transfers are disabled. When Enable is set again, CFG and most other control + * bits remain unchanged. When re-enabled, the USART will immediately be ready to transmit because the + * transmitter has been reset and is therefore available. + * 0b1..Enabled. The USART is enabled for operation. + */ +#define USART_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_ENABLE_SHIFT)) & USART_CFG_ENABLE_MASK) +#define USART_CFG_DATALEN_MASK (0xCU) +#define USART_CFG_DATALEN_SHIFT (2U) +/*! DATALEN - Selects the data size for the USART. + * 0b00..7 bit Data length. + * 0b01..8 bit Data length. + * 0b10..9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET bit in the CTL register. + * 0b11..Reserved. + */ +#define USART_CFG_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_DATALEN_SHIFT)) & USART_CFG_DATALEN_MASK) +#define USART_CFG_PARITYSEL_MASK (0x30U) +#define USART_CFG_PARITYSEL_SHIFT (4U) +/*! PARITYSEL - Selects what type of parity is used by the USART. + * 0b00..No parity. + * 0b01..Reserved. + * 0b10..Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even, + * and the number of 1s in a received character is expected to be even. + * 0b11..Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd, + * and the number of 1s in a received character is expected to be odd. + */ +#define USART_CFG_PARITYSEL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_PARITYSEL_SHIFT)) & USART_CFG_PARITYSEL_MASK) +#define USART_CFG_STOPLEN_MASK (0x40U) +#define USART_CFG_STOPLEN_SHIFT (6U) +/*! STOPLEN - Number of stop bits appended to transmitted data. Only a single stop bit is required for received data. + * 0b0..1 stop bit. + * 0b1..2 stop bits. This setting should only be used for asynchronous communication. + */ +#define USART_CFG_STOPLEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_STOPLEN_SHIFT)) & USART_CFG_STOPLEN_MASK) +#define USART_CFG_MODE32K_MASK (0x80U) +#define USART_CFG_MODE32K_SHIFT (7U) +/*! MODE32K - Selects standard or 32 kHz clocking mode. + * 0b0..Disabled. USART uses standard clocking. + * 0b1..Enabled. USART uses the 32 kHz clock from the RTC oscillator as the clock source to the BRG, and uses a special bit clocking scheme. + */ +#define USART_CFG_MODE32K(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_MODE32K_SHIFT)) & USART_CFG_MODE32K_MASK) +#define USART_CFG_LINMODE_MASK (0x100U) +#define USART_CFG_LINMODE_SHIFT (8U) +/*! LINMODE - LIN break mode enable. + * 0b0..Disabled. Break detect and generate is configured for normal operation. + * 0b1..Enabled. Break detect and generate is configured for LIN bus operation. + */ +#define USART_CFG_LINMODE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_LINMODE_SHIFT)) & USART_CFG_LINMODE_MASK) +#define USART_CFG_CTSEN_MASK (0x200U) +#define USART_CFG_CTSEN_SHIFT (9U) +/*! CTSEN - CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input + * pin, or from the USART's own RTS if loopback mode is enabled. + * 0b0..No flow control. The transmitter does not receive any automatic flow control signal. + * 0b1..Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes. + */ +#define USART_CFG_CTSEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_CTSEN_SHIFT)) & USART_CFG_CTSEN_MASK) +#define USART_CFG_SYNCEN_MASK (0x800U) +#define USART_CFG_SYNCEN_SHIFT (11U) +/*! SYNCEN - Selects synchronous or asynchronous operation. + * 0b0..Asynchronous mode. + * 0b1..Synchronous mode. + */ +#define USART_CFG_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCEN_SHIFT)) & USART_CFG_SYNCEN_MASK) +#define USART_CFG_CLKPOL_MASK (0x1000U) +#define USART_CFG_CLKPOL_SHIFT (12U) +/*! CLKPOL - Selects the clock polarity and sampling edge of received data in synchronous mode. + * 0b0..Falling edge. Un_RXD is sampled on the falling edge of SCLK. + * 0b1..Rising edge. Un_RXD is sampled on the rising edge of SCLK. + */ +#define USART_CFG_CLKPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_CLKPOL_SHIFT)) & USART_CFG_CLKPOL_MASK) +#define USART_CFG_SYNCMST_MASK (0x4000U) +#define USART_CFG_SYNCMST_SHIFT (14U) +/*! SYNCMST - Synchronous mode Master select. + * 0b0..Slave. When synchronous mode is enabled, the USART is a slave. + * 0b1..Master. When synchronous mode is enabled, the USART is a master. + */ +#define USART_CFG_SYNCMST(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCMST_SHIFT)) & USART_CFG_SYNCMST_MASK) +#define USART_CFG_LOOP_MASK (0x8000U) +#define USART_CFG_LOOP_SHIFT (15U) +/*! LOOP - Selects data loopback mode. + * 0b0..Normal operation. + * 0b1..Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial + * data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD + * and Un_RTS activity will also appear on external pins if these functions are configured to appear on device + * pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN. + */ +#define USART_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_LOOP_SHIFT)) & USART_CFG_LOOP_MASK) +#define USART_CFG_OETA_MASK (0x40000U) +#define USART_CFG_OETA_SHIFT (18U) +/*! OETA - Output Enable Turnaround time enable for RS-485 operation. + * 0b0..Disabled. If selected by OESEL, the Output Enable signal deasserted at the end of the last stop bit of a transmission. + * 0b1..Enabled. If selected by OESEL, the Output Enable signal remains asserted for one character time after the + * end of the last stop bit of a transmission. OE will also remain asserted if another transmit begins + * before it is deasserted. + */ +#define USART_CFG_OETA(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OETA_SHIFT)) & USART_CFG_OETA_MASK) +#define USART_CFG_AUTOADDR_MASK (0x80000U) +#define USART_CFG_AUTOADDR_SHIFT (19U) +/*! AUTOADDR - Automatic Address matching enable. + * 0b0..Disabled. When addressing is enabled by ADDRDET, address matching is done by software. This provides the + * possibility of versatile addressing (e.g. respond to more than one address). + * 0b1..Enabled. When addressing is enabled by ADDRDET, address matching is done by hardware, using the value in + * the ADDR register as the address to match. + */ +#define USART_CFG_AUTOADDR(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_AUTOADDR_SHIFT)) & USART_CFG_AUTOADDR_MASK) +#define USART_CFG_OESEL_MASK (0x100000U) +#define USART_CFG_OESEL_SHIFT (20U) +/*! OESEL - Output Enable Select. + * 0b0..Standard. The RTS signal is used as the standard flow control function. + * 0b1..RS-485. The RTS signal configured to provide an output enable signal to control an RS-485 transceiver. + */ +#define USART_CFG_OESEL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OESEL_SHIFT)) & USART_CFG_OESEL_MASK) +#define USART_CFG_OEPOL_MASK (0x200000U) +#define USART_CFG_OEPOL_SHIFT (21U) +/*! OEPOL - Output Enable Polarity. + * 0b0..Low. If selected by OESEL, the output enable is active low. + * 0b1..High. If selected by OESEL, the output enable is active high. + */ +#define USART_CFG_OEPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OEPOL_SHIFT)) & USART_CFG_OEPOL_MASK) +#define USART_CFG_RXPOL_MASK (0x400000U) +#define USART_CFG_RXPOL_SHIFT (22U) +/*! RXPOL - Receive data polarity. + * 0b0..Standard. The RX signal is used as it arrives from the pin. This means that the RX rest value is 1, start + * bit is 0, data is not inverted, and the stop bit is 1. + * 0b1..Inverted. The RX signal is inverted before being used by the USART. This means that the RX rest value is + * 0, start bit is 1, data is inverted, and the stop bit is 0. + */ +#define USART_CFG_RXPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_RXPOL_SHIFT)) & USART_CFG_RXPOL_MASK) +#define USART_CFG_TXPOL_MASK (0x800000U) +#define USART_CFG_TXPOL_SHIFT (23U) +/*! TXPOL - Transmit data polarity. + * 0b0..Standard. The TX signal is sent out without change. This means that the TX rest value is 1, start bit is + * 0, data is not inverted, and the stop bit is 1. + * 0b1..Inverted. The TX signal is inverted by the USART before being sent out. This means that the TX rest value + * is 0, start bit is 1, data is inverted, and the stop bit is 0. + */ +#define USART_CFG_TXPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_TXPOL_SHIFT)) & USART_CFG_TXPOL_MASK) +/*! @} */ + +/*! @name CTL - USART Control register. USART control settings that are more likely to change during operation. */ +/*! @{ */ +#define USART_CTL_TXBRKEN_MASK (0x2U) +#define USART_CTL_TXBRKEN_SHIFT (1U) +/*! TXBRKEN - Break Enable. + * 0b0..Normal operation. + * 0b1..Continuous break. Continuous break is sent immediately when this bit is set, and remains until this bit + * is cleared. A break may be sent without danger of corrupting any currently transmitting character if the + * transmitter is first disabled (TXDIS in CTL is set) and then waiting for the transmitter to be disabled + * (TXDISINT in STAT = 1) before writing 1 to TXBRKEN. + */ +#define USART_CTL_TXBRKEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXBRKEN_SHIFT)) & USART_CTL_TXBRKEN_MASK) +#define USART_CTL_ADDRDET_MASK (0x4U) +#define USART_CTL_ADDRDET_SHIFT (2U) +/*! ADDRDET - Enable address detect mode. + * 0b0..Disabled. The USART presents all incoming data. + * 0b1..Enabled. The USART receiver ignores incoming data that does not have the most significant bit of the data + * (typically the 9th bit) = 1. When the data MSB bit = 1, the receiver treats the incoming data normally, + * generating a received data interrupt. Software can then check the data to see if this is an address that + * should be handled. If it is, the ADDRDET bit is cleared by software and further incoming data is handled + * normally. + */ +#define USART_CTL_ADDRDET(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_ADDRDET_SHIFT)) & USART_CTL_ADDRDET_MASK) +#define USART_CTL_TXDIS_MASK (0x40U) +#define USART_CTL_TXDIS_SHIFT (6U) +/*! TXDIS - Transmit Disable. + * 0b0..Not disabled. USART transmitter is not disabled. + * 0b1..Disabled. USART transmitter is disabled after any character currently being transmitted is complete. This + * feature can be used to facilitate software flow control. + */ +#define USART_CTL_TXDIS(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXDIS_SHIFT)) & USART_CTL_TXDIS_MASK) +#define USART_CTL_CC_MASK (0x100U) +#define USART_CTL_CC_SHIFT (8U) +/*! CC - Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode. + * 0b0..Clock on character. In synchronous mode, SCLK cycles only when characters are being sent on Un_TXD or to + * complete a character that is being received. + * 0b1..Continuous clock. SCLK runs continuously in synchronous mode, allowing characters to be received on + * Un_RxD independently from transmission on Un_TXD). + */ +#define USART_CTL_CC(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_CC_SHIFT)) & USART_CTL_CC_MASK) +#define USART_CTL_CLRCCONRX_MASK (0x200U) +#define USART_CTL_CLRCCONRX_SHIFT (9U) +/*! CLRCCONRX - Clear Continuous Clock. + * 0b0..No effect. No effect on the CC bit. + * 0b1..Auto-clear. The CC bit is automatically cleared when a complete character has been received. This bit is cleared at the same time. + */ +#define USART_CTL_CLRCCONRX(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_CLRCCONRX_SHIFT)) & USART_CTL_CLRCCONRX_MASK) +#define USART_CTL_AUTOBAUD_MASK (0x10000U) +#define USART_CTL_AUTOBAUD_SHIFT (16U) +/*! AUTOBAUD - Autobaud enable. + * 0b0..Disabled. USART is in normal operating mode. + * 0b1..Enabled. USART is in autobaud mode. This bit should only be set when the USART receiver is idle. The + * first start bit of RX is measured and used the update the BRG register to match the received data rate. + * AUTOBAUD is cleared once this process is complete, or if there is an AERR. + */ +#define USART_CTL_AUTOBAUD(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_AUTOBAUD_SHIFT)) & USART_CTL_AUTOBAUD_MASK) +/*! @} */ + +/*! @name STAT - USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them. */ +/*! @{ */ +#define USART_STAT_RXIDLE_MASK (0x2U) +#define USART_STAT_RXIDLE_SHIFT (1U) +#define USART_STAT_RXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXIDLE_SHIFT)) & USART_STAT_RXIDLE_MASK) +#define USART_STAT_TXIDLE_MASK (0x8U) +#define USART_STAT_TXIDLE_SHIFT (3U) +#define USART_STAT_TXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXIDLE_SHIFT)) & USART_STAT_TXIDLE_MASK) +#define USART_STAT_CTS_MASK (0x10U) +#define USART_STAT_CTS_SHIFT (4U) +#define USART_STAT_CTS(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_CTS_SHIFT)) & USART_STAT_CTS_MASK) +#define USART_STAT_DELTACTS_MASK (0x20U) +#define USART_STAT_DELTACTS_SHIFT (5U) +#define USART_STAT_DELTACTS(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTACTS_SHIFT)) & USART_STAT_DELTACTS_MASK) +#define USART_STAT_TXDISSTAT_MASK (0x40U) +#define USART_STAT_TXDISSTAT_SHIFT (6U) +#define USART_STAT_TXDISSTAT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXDISSTAT_SHIFT)) & USART_STAT_TXDISSTAT_MASK) +#define USART_STAT_RXBRK_MASK (0x400U) +#define USART_STAT_RXBRK_SHIFT (10U) +#define USART_STAT_RXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXBRK_SHIFT)) & USART_STAT_RXBRK_MASK) +#define USART_STAT_DELTARXBRK_MASK (0x800U) +#define USART_STAT_DELTARXBRK_SHIFT (11U) +#define USART_STAT_DELTARXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTARXBRK_SHIFT)) & USART_STAT_DELTARXBRK_MASK) +#define USART_STAT_START_MASK (0x1000U) +#define USART_STAT_START_SHIFT (12U) +#define USART_STAT_START(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_START_SHIFT)) & USART_STAT_START_MASK) +#define USART_STAT_FRAMERRINT_MASK (0x2000U) +#define USART_STAT_FRAMERRINT_SHIFT (13U) +#define USART_STAT_FRAMERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_FRAMERRINT_SHIFT)) & USART_STAT_FRAMERRINT_MASK) +#define USART_STAT_PARITYERRINT_MASK (0x4000U) +#define USART_STAT_PARITYERRINT_SHIFT (14U) +#define USART_STAT_PARITYERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_PARITYERRINT_SHIFT)) & USART_STAT_PARITYERRINT_MASK) +#define USART_STAT_RXNOISEINT_MASK (0x8000U) +#define USART_STAT_RXNOISEINT_SHIFT (15U) +#define USART_STAT_RXNOISEINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXNOISEINT_SHIFT)) & USART_STAT_RXNOISEINT_MASK) +#define USART_STAT_ABERR_MASK (0x10000U) +#define USART_STAT_ABERR_SHIFT (16U) +#define USART_STAT_ABERR(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_ABERR_SHIFT)) & USART_STAT_ABERR_MASK) +/*! @} */ + +/*! @name INTENSET - Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */ +/*! @{ */ +#define USART_INTENSET_TXIDLEEN_MASK (0x8U) +#define USART_INTENSET_TXIDLEEN_SHIFT (3U) +#define USART_INTENSET_TXIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXIDLEEN_SHIFT)) & USART_INTENSET_TXIDLEEN_MASK) +#define USART_INTENSET_DELTACTSEN_MASK (0x20U) +#define USART_INTENSET_DELTACTSEN_SHIFT (5U) +#define USART_INTENSET_DELTACTSEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTACTSEN_SHIFT)) & USART_INTENSET_DELTACTSEN_MASK) +#define USART_INTENSET_TXDISEN_MASK (0x40U) +#define USART_INTENSET_TXDISEN_SHIFT (6U) +#define USART_INTENSET_TXDISEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXDISEN_SHIFT)) & USART_INTENSET_TXDISEN_MASK) +#define USART_INTENSET_DELTARXBRKEN_MASK (0x800U) +#define USART_INTENSET_DELTARXBRKEN_SHIFT (11U) +#define USART_INTENSET_DELTARXBRKEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTARXBRKEN_SHIFT)) & USART_INTENSET_DELTARXBRKEN_MASK) +#define USART_INTENSET_STARTEN_MASK (0x1000U) +#define USART_INTENSET_STARTEN_SHIFT (12U) +#define USART_INTENSET_STARTEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_STARTEN_SHIFT)) & USART_INTENSET_STARTEN_MASK) +#define USART_INTENSET_FRAMERREN_MASK (0x2000U) +#define USART_INTENSET_FRAMERREN_SHIFT (13U) +#define USART_INTENSET_FRAMERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_FRAMERREN_SHIFT)) & USART_INTENSET_FRAMERREN_MASK) +#define USART_INTENSET_PARITYERREN_MASK (0x4000U) +#define USART_INTENSET_PARITYERREN_SHIFT (14U) +#define USART_INTENSET_PARITYERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_PARITYERREN_SHIFT)) & USART_INTENSET_PARITYERREN_MASK) +#define USART_INTENSET_RXNOISEEN_MASK (0x8000U) +#define USART_INTENSET_RXNOISEEN_SHIFT (15U) +#define USART_INTENSET_RXNOISEEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_RXNOISEEN_SHIFT)) & USART_INTENSET_RXNOISEEN_MASK) +#define USART_INTENSET_ABERREN_MASK (0x10000U) +#define USART_INTENSET_ABERREN_SHIFT (16U) +#define USART_INTENSET_ABERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_ABERREN_SHIFT)) & USART_INTENSET_ABERREN_MASK) +/*! @} */ + +/*! @name INTENCLR - Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared. */ +/*! @{ */ +#define USART_INTENCLR_TXIDLECLR_MASK (0x8U) +#define USART_INTENCLR_TXIDLECLR_SHIFT (3U) +#define USART_INTENCLR_TXIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXIDLECLR_SHIFT)) & USART_INTENCLR_TXIDLECLR_MASK) +#define USART_INTENCLR_DELTACTSCLR_MASK (0x20U) +#define USART_INTENCLR_DELTACTSCLR_SHIFT (5U) +#define USART_INTENCLR_DELTACTSCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTACTSCLR_SHIFT)) & USART_INTENCLR_DELTACTSCLR_MASK) +#define USART_INTENCLR_TXDISCLR_MASK (0x40U) +#define USART_INTENCLR_TXDISCLR_SHIFT (6U) +#define USART_INTENCLR_TXDISCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXDISCLR_SHIFT)) & USART_INTENCLR_TXDISCLR_MASK) +#define USART_INTENCLR_DELTARXBRKCLR_MASK (0x800U) +#define USART_INTENCLR_DELTARXBRKCLR_SHIFT (11U) +#define USART_INTENCLR_DELTARXBRKCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTARXBRKCLR_SHIFT)) & USART_INTENCLR_DELTARXBRKCLR_MASK) +#define USART_INTENCLR_STARTCLR_MASK (0x1000U) +#define USART_INTENCLR_STARTCLR_SHIFT (12U) +#define USART_INTENCLR_STARTCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_STARTCLR_SHIFT)) & USART_INTENCLR_STARTCLR_MASK) +#define USART_INTENCLR_FRAMERRCLR_MASK (0x2000U) +#define USART_INTENCLR_FRAMERRCLR_SHIFT (13U) +#define USART_INTENCLR_FRAMERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_FRAMERRCLR_SHIFT)) & USART_INTENCLR_FRAMERRCLR_MASK) +#define USART_INTENCLR_PARITYERRCLR_MASK (0x4000U) +#define USART_INTENCLR_PARITYERRCLR_SHIFT (14U) +#define USART_INTENCLR_PARITYERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_PARITYERRCLR_SHIFT)) & USART_INTENCLR_PARITYERRCLR_MASK) +#define USART_INTENCLR_RXNOISECLR_MASK (0x8000U) +#define USART_INTENCLR_RXNOISECLR_SHIFT (15U) +#define USART_INTENCLR_RXNOISECLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_RXNOISECLR_SHIFT)) & USART_INTENCLR_RXNOISECLR_MASK) +#define USART_INTENCLR_ABERRCLR_MASK (0x10000U) +#define USART_INTENCLR_ABERRCLR_SHIFT (16U) +#define USART_INTENCLR_ABERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_ABERRCLR_SHIFT)) & USART_INTENCLR_ABERRCLR_MASK) +/*! @} */ + +/*! @name BRG - Baud Rate Generator register. 16-bit integer baud rate divisor value. */ +/*! @{ */ +#define USART_BRG_BRGVAL_MASK (0xFFFFU) +#define USART_BRG_BRGVAL_SHIFT (0U) +#define USART_BRG_BRGVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_BRG_BRGVAL_SHIFT)) & USART_BRG_BRGVAL_MASK) +/*! @} */ + +/*! @name INTSTAT - Interrupt status register. Reflects interrupts that are currently enabled. */ +/*! @{ */ +#define USART_INTSTAT_TXIDLE_MASK (0x8U) +#define USART_INTSTAT_TXIDLE_SHIFT (3U) +#define USART_INTSTAT_TXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXIDLE_SHIFT)) & USART_INTSTAT_TXIDLE_MASK) +#define USART_INTSTAT_DELTACTS_MASK (0x20U) +#define USART_INTSTAT_DELTACTS_SHIFT (5U) +#define USART_INTSTAT_DELTACTS(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTACTS_SHIFT)) & USART_INTSTAT_DELTACTS_MASK) +#define USART_INTSTAT_TXDISINT_MASK (0x40U) +#define USART_INTSTAT_TXDISINT_SHIFT (6U) +#define USART_INTSTAT_TXDISINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXDISINT_SHIFT)) & USART_INTSTAT_TXDISINT_MASK) +#define USART_INTSTAT_DELTARXBRK_MASK (0x800U) +#define USART_INTSTAT_DELTARXBRK_SHIFT (11U) +#define USART_INTSTAT_DELTARXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTARXBRK_SHIFT)) & USART_INTSTAT_DELTARXBRK_MASK) +#define USART_INTSTAT_START_MASK (0x1000U) +#define USART_INTSTAT_START_SHIFT (12U) +#define USART_INTSTAT_START(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_START_SHIFT)) & USART_INTSTAT_START_MASK) +#define USART_INTSTAT_FRAMERRINT_MASK (0x2000U) +#define USART_INTSTAT_FRAMERRINT_SHIFT (13U) +#define USART_INTSTAT_FRAMERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_FRAMERRINT_SHIFT)) & USART_INTSTAT_FRAMERRINT_MASK) +#define USART_INTSTAT_PARITYERRINT_MASK (0x4000U) +#define USART_INTSTAT_PARITYERRINT_SHIFT (14U) +#define USART_INTSTAT_PARITYERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_PARITYERRINT_SHIFT)) & USART_INTSTAT_PARITYERRINT_MASK) +#define USART_INTSTAT_RXNOISEINT_MASK (0x8000U) +#define USART_INTSTAT_RXNOISEINT_SHIFT (15U) +#define USART_INTSTAT_RXNOISEINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_RXNOISEINT_SHIFT)) & USART_INTSTAT_RXNOISEINT_MASK) +#define USART_INTSTAT_ABERRINT_MASK (0x10000U) +#define USART_INTSTAT_ABERRINT_SHIFT (16U) +#define USART_INTSTAT_ABERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_ABERRINT_SHIFT)) & USART_INTSTAT_ABERRINT_MASK) +/*! @} */ + +/*! @name OSR - Oversample selection register for asynchronous communication. */ +/*! @{ */ +#define USART_OSR_OSRVAL_MASK (0xFU) +#define USART_OSR_OSRVAL_SHIFT (0U) +#define USART_OSR_OSRVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_OSR_OSRVAL_SHIFT)) & USART_OSR_OSRVAL_MASK) +/*! @} */ + +/*! @name ADDR - Address register for automatic address matching. */ +/*! @{ */ +#define USART_ADDR_ADDRESS_MASK (0xFFU) +#define USART_ADDR_ADDRESS_SHIFT (0U) +#define USART_ADDR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << USART_ADDR_ADDRESS_SHIFT)) & USART_ADDR_ADDRESS_MASK) +/*! @} */ + +/*! @name FIFOCFG - FIFO configuration and enable register. */ +/*! @{ */ +#define USART_FIFOCFG_ENABLETX_MASK (0x1U) +#define USART_FIFOCFG_ENABLETX_SHIFT (0U) +/*! ENABLETX - Enable the transmit FIFO. + * 0b0..The transmit FIFO is not enabled. + * 0b1..The transmit FIFO is enabled. + */ +#define USART_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLETX_SHIFT)) & USART_FIFOCFG_ENABLETX_MASK) +#define USART_FIFOCFG_ENABLERX_MASK (0x2U) +#define USART_FIFOCFG_ENABLERX_SHIFT (1U) +/*! ENABLERX - Enable the receive FIFO. + * 0b0..The receive FIFO is not enabled. + * 0b1..The receive FIFO is enabled. + */ +#define USART_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLERX_SHIFT)) & USART_FIFOCFG_ENABLERX_MASK) +#define USART_FIFOCFG_SIZE_MASK (0x30U) +#define USART_FIFOCFG_SIZE_SHIFT (4U) +#define USART_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_SIZE_SHIFT)) & USART_FIFOCFG_SIZE_MASK) +#define USART_FIFOCFG_DMATX_MASK (0x1000U) +#define USART_FIFOCFG_DMATX_SHIFT (12U) +/*! DMATX - DMA configuration for transmit. + * 0b0..DMA is not used for the transmit function. + * 0b1..Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. + */ +#define USART_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMATX_SHIFT)) & USART_FIFOCFG_DMATX_MASK) +#define USART_FIFOCFG_DMARX_MASK (0x2000U) +#define USART_FIFOCFG_DMARX_SHIFT (13U) +/*! DMARX - DMA configuration for receive. + * 0b0..DMA is not used for the receive function. + * 0b1..Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. + */ +#define USART_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMARX_SHIFT)) & USART_FIFOCFG_DMARX_MASK) +#define USART_FIFOCFG_WAKETX_MASK (0x4000U) +#define USART_FIFOCFG_WAKETX_SHIFT (14U) +/*! WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power + * modes (up to power-down, as long as the peripheral function works in that power mode) without + * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The + * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware + * Wake-up control register. + * 0b0..Only enabled interrupts will wake up the device form reduced power modes. + * 0b1..A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in + * FIFOTRIG, even when the TXLVL interrupt is not enabled. + */ +#define USART_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKETX_SHIFT)) & USART_FIFOCFG_WAKETX_MASK) +#define USART_FIFOCFG_WAKERX_MASK (0x8000U) +#define USART_FIFOCFG_WAKERX_SHIFT (15U) +/*! WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power + * modes (up to power-down, as long as the peripheral function works in that power mode) without + * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The + * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware + * Wake-up control register. + * 0b0..Only enabled interrupts will wake up the device form reduced power modes. + * 0b1..A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in + * FIFOTRIG, even when the RXLVL interrupt is not enabled. + */ +#define USART_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKERX_SHIFT)) & USART_FIFOCFG_WAKERX_MASK) +#define USART_FIFOCFG_EMPTYTX_MASK (0x10000U) +#define USART_FIFOCFG_EMPTYTX_SHIFT (16U) +#define USART_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYTX_SHIFT)) & USART_FIFOCFG_EMPTYTX_MASK) +#define USART_FIFOCFG_EMPTYRX_MASK (0x20000U) +#define USART_FIFOCFG_EMPTYRX_SHIFT (17U) +#define USART_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYRX_SHIFT)) & USART_FIFOCFG_EMPTYRX_MASK) +#define USART_FIFOCFG_POPDBG_MASK (0x40000U) +#define USART_FIFOCFG_POPDBG_SHIFT (18U) +/*! POPDBG - Pop FIFO for debug reads. + * 0b0..Debug reads of the FIFO do not pop the FIFO. + * 0b1..A debug read will cause the FIFO to pop. + */ +#define USART_FIFOCFG_POPDBG(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_POPDBG_SHIFT)) & USART_FIFOCFG_POPDBG_MASK) +/*! @} */ + +/*! @name FIFOSTAT - FIFO status register. */ +/*! @{ */ +#define USART_FIFOSTAT_TXERR_MASK (0x1U) +#define USART_FIFOSTAT_TXERR_SHIFT (0U) +#define USART_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXERR_SHIFT)) & USART_FIFOSTAT_TXERR_MASK) +#define USART_FIFOSTAT_RXERR_MASK (0x2U) +#define USART_FIFOSTAT_RXERR_SHIFT (1U) +#define USART_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXERR_SHIFT)) & USART_FIFOSTAT_RXERR_MASK) +#define USART_FIFOSTAT_PERINT_MASK (0x8U) +#define USART_FIFOSTAT_PERINT_SHIFT (3U) +#define USART_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_PERINT_SHIFT)) & USART_FIFOSTAT_PERINT_MASK) +#define USART_FIFOSTAT_TXEMPTY_MASK (0x10U) +#define USART_FIFOSTAT_TXEMPTY_SHIFT (4U) +#define USART_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXEMPTY_SHIFT)) & USART_FIFOSTAT_TXEMPTY_MASK) +#define USART_FIFOSTAT_TXNOTFULL_MASK (0x20U) +#define USART_FIFOSTAT_TXNOTFULL_SHIFT (5U) +#define USART_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXNOTFULL_SHIFT)) & USART_FIFOSTAT_TXNOTFULL_MASK) +#define USART_FIFOSTAT_RXNOTEMPTY_MASK (0x40U) +#define USART_FIFOSTAT_RXNOTEMPTY_SHIFT (6U) +#define USART_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXNOTEMPTY_SHIFT)) & USART_FIFOSTAT_RXNOTEMPTY_MASK) +#define USART_FIFOSTAT_RXFULL_MASK (0x80U) +#define USART_FIFOSTAT_RXFULL_SHIFT (7U) +#define USART_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXFULL_SHIFT)) & USART_FIFOSTAT_RXFULL_MASK) +#define USART_FIFOSTAT_TXLVL_MASK (0x1F00U) +#define USART_FIFOSTAT_TXLVL_SHIFT (8U) +#define USART_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXLVL_SHIFT)) & USART_FIFOSTAT_TXLVL_MASK) +#define USART_FIFOSTAT_RXLVL_MASK (0x1F0000U) +#define USART_FIFOSTAT_RXLVL_SHIFT (16U) +#define USART_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXLVL_SHIFT)) & USART_FIFOSTAT_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */ +/*! @{ */ +#define USART_FIFOTRIG_TXLVLENA_MASK (0x1U) +#define USART_FIFOTRIG_TXLVLENA_SHIFT (0U) +/*! TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled + * in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set. + * 0b0..Transmit FIFO level does not generate a FIFO level trigger. + * 0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register. + */ +#define USART_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVLENA_SHIFT)) & USART_FIFOTRIG_TXLVLENA_MASK) +#define USART_FIFOTRIG_RXLVLENA_MASK (0x2U) +#define USART_FIFOTRIG_RXLVLENA_SHIFT (1U) +/*! RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled + * in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. + * 0b0..Receive FIFO level does not generate a FIFO level trigger. + * 0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. + */ +#define USART_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVLENA_SHIFT)) & USART_FIFOTRIG_RXLVLENA_MASK) +#define USART_FIFOTRIG_TXLVL_MASK (0xF00U) +#define USART_FIFOTRIG_TXLVL_SHIFT (8U) +#define USART_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVL_SHIFT)) & USART_FIFOTRIG_TXLVL_MASK) +#define USART_FIFOTRIG_RXLVL_MASK (0xF0000U) +#define USART_FIFOTRIG_RXLVL_SHIFT (16U) +#define USART_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVL_SHIFT)) & USART_FIFOTRIG_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */ +/*! @{ */ +#define USART_FIFOINTENSET_TXERR_MASK (0x1U) +#define USART_FIFOINTENSET_TXERR_SHIFT (0U) +/*! TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. + * 0b0..No interrupt will be generated for a transmit error. + * 0b1..An interrupt will be generated when a transmit error occurs. + */ +#define USART_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXERR_SHIFT)) & USART_FIFOINTENSET_TXERR_MASK) +#define USART_FIFOINTENSET_RXERR_MASK (0x2U) +#define USART_FIFOINTENSET_RXERR_SHIFT (1U) +/*! RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. + * 0b0..No interrupt will be generated for a receive error. + * 0b1..An interrupt will be generated when a receive error occurs. + */ +#define USART_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXERR_SHIFT)) & USART_FIFOINTENSET_RXERR_MASK) +#define USART_FIFOINTENSET_TXLVL_MASK (0x4U) +#define USART_FIFOINTENSET_TXLVL_SHIFT (2U) +/*! TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level + * specified by the TXLVL field in the FIFOTRIG register. + * 0b0..No interrupt will be generated based on the TX FIFO level. + * 0b1..If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases + * to the level specified by TXLVL in the FIFOTRIG register. + */ +#define USART_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXLVL_SHIFT)) & USART_FIFOINTENSET_TXLVL_MASK) +#define USART_FIFOINTENSET_RXLVL_MASK (0x8U) +#define USART_FIFOINTENSET_RXLVL_SHIFT (3U) +/*! RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level + * specified by the TXLVL field in the FIFOTRIG register. + * 0b0..No interrupt will be generated based on the RX FIFO level. + * 0b1..If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level + * increases to the level specified by RXLVL in the FIFOTRIG register. + */ +#define USART_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXLVL_SHIFT)) & USART_FIFOINTENSET_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */ +/*! @{ */ +#define USART_FIFOINTENCLR_TXERR_MASK (0x1U) +#define USART_FIFOINTENCLR_TXERR_SHIFT (0U) +#define USART_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXERR_SHIFT)) & USART_FIFOINTENCLR_TXERR_MASK) +#define USART_FIFOINTENCLR_RXERR_MASK (0x2U) +#define USART_FIFOINTENCLR_RXERR_SHIFT (1U) +#define USART_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXERR_SHIFT)) & USART_FIFOINTENCLR_RXERR_MASK) +#define USART_FIFOINTENCLR_TXLVL_MASK (0x4U) +#define USART_FIFOINTENCLR_TXLVL_SHIFT (2U) +#define USART_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXLVL_SHIFT)) & USART_FIFOINTENCLR_TXLVL_MASK) +#define USART_FIFOINTENCLR_RXLVL_MASK (0x8U) +#define USART_FIFOINTENCLR_RXLVL_SHIFT (3U) +#define USART_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXLVL_SHIFT)) & USART_FIFOINTENCLR_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTSTAT - FIFO interrupt status register. */ +/*! @{ */ +#define USART_FIFOINTSTAT_TXERR_MASK (0x1U) +#define USART_FIFOINTSTAT_TXERR_SHIFT (0U) +#define USART_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXERR_SHIFT)) & USART_FIFOINTSTAT_TXERR_MASK) +#define USART_FIFOINTSTAT_RXERR_MASK (0x2U) +#define USART_FIFOINTSTAT_RXERR_SHIFT (1U) +#define USART_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXERR_SHIFT)) & USART_FIFOINTSTAT_RXERR_MASK) +#define USART_FIFOINTSTAT_TXLVL_MASK (0x4U) +#define USART_FIFOINTSTAT_TXLVL_SHIFT (2U) +#define USART_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXLVL_SHIFT)) & USART_FIFOINTSTAT_TXLVL_MASK) +#define USART_FIFOINTSTAT_RXLVL_MASK (0x8U) +#define USART_FIFOINTSTAT_RXLVL_SHIFT (3U) +#define USART_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXLVL_SHIFT)) & USART_FIFOINTSTAT_RXLVL_MASK) +#define USART_FIFOINTSTAT_PERINT_MASK (0x10U) +#define USART_FIFOINTSTAT_PERINT_SHIFT (4U) +#define USART_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_PERINT_SHIFT)) & USART_FIFOINTSTAT_PERINT_MASK) +/*! @} */ + +/*! @name FIFOWR - FIFO write data. */ +/*! @{ */ +#define USART_FIFOWR_TXDATA_MASK (0x1FFU) +#define USART_FIFOWR_TXDATA_SHIFT (0U) +#define USART_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOWR_TXDATA_SHIFT)) & USART_FIFOWR_TXDATA_MASK) +/*! @} */ + +/*! @name FIFORD - FIFO read data. */ +/*! @{ */ +#define USART_FIFORD_RXDATA_MASK (0x1FFU) +#define USART_FIFORD_RXDATA_SHIFT (0U) +#define USART_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXDATA_SHIFT)) & USART_FIFORD_RXDATA_MASK) +#define USART_FIFORD_FRAMERR_MASK (0x2000U) +#define USART_FIFORD_FRAMERR_SHIFT (13U) +#define USART_FIFORD_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_FRAMERR_SHIFT)) & USART_FIFORD_FRAMERR_MASK) +#define USART_FIFORD_PARITYERR_MASK (0x4000U) +#define USART_FIFORD_PARITYERR_SHIFT (14U) +#define USART_FIFORD_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_PARITYERR_SHIFT)) & USART_FIFORD_PARITYERR_MASK) +#define USART_FIFORD_RXNOISE_MASK (0x8000U) +#define USART_FIFORD_RXNOISE_SHIFT (15U) +#define USART_FIFORD_RXNOISE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXNOISE_SHIFT)) & USART_FIFORD_RXNOISE_MASK) +/*! @} */ + +/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */ +/*! @{ */ +#define USART_FIFORDNOPOP_RXDATA_MASK (0x1FFU) +#define USART_FIFORDNOPOP_RXDATA_SHIFT (0U) +#define USART_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXDATA_SHIFT)) & USART_FIFORDNOPOP_RXDATA_MASK) +#define USART_FIFORDNOPOP_FRAMERR_MASK (0x2000U) +#define USART_FIFORDNOPOP_FRAMERR_SHIFT (13U) +#define USART_FIFORDNOPOP_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_FRAMERR_SHIFT)) & USART_FIFORDNOPOP_FRAMERR_MASK) +#define USART_FIFORDNOPOP_PARITYERR_MASK (0x4000U) +#define USART_FIFORDNOPOP_PARITYERR_SHIFT (14U) +#define USART_FIFORDNOPOP_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_PARITYERR_SHIFT)) & USART_FIFORDNOPOP_PARITYERR_MASK) +#define USART_FIFORDNOPOP_RXNOISE_MASK (0x8000U) +#define USART_FIFORDNOPOP_RXNOISE_SHIFT (15U) +#define USART_FIFORDNOPOP_RXNOISE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXNOISE_SHIFT)) & USART_FIFORDNOPOP_RXNOISE_MASK) +/*! @} */ + +/*! @name ID - Peripheral identification register. */ +/*! @{ */ +#define USART_ID_APERTURE_MASK (0xFFU) +#define USART_ID_APERTURE_SHIFT (0U) +#define USART_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_APERTURE_SHIFT)) & USART_ID_APERTURE_MASK) +#define USART_ID_MINOR_REV_MASK (0xF00U) +#define USART_ID_MINOR_REV_SHIFT (8U) +#define USART_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_MINOR_REV_SHIFT)) & USART_ID_MINOR_REV_MASK) +#define USART_ID_MAJOR_REV_MASK (0xF000U) +#define USART_ID_MAJOR_REV_SHIFT (12U) +#define USART_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_MAJOR_REV_SHIFT)) & USART_ID_MAJOR_REV_MASK) +#define USART_ID_ID_MASK (0xFFFF0000U) +#define USART_ID_ID_SHIFT (16U) +#define USART_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_ID_SHIFT)) & USART_ID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group USART_Register_Masks */ + + +/* USART - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral USART0 base address */ + #define USART0_BASE (0x50086000u) + /** Peripheral USART0 base address */ + #define USART0_BASE_NS (0x40086000u) + /** Peripheral USART0 base pointer */ + #define USART0 ((USART_Type *)USART0_BASE) + /** Peripheral USART0 base pointer */ + #define USART0_NS ((USART_Type *)USART0_BASE_NS) + /** Peripheral USART1 base address */ + #define USART1_BASE (0x50087000u) + /** Peripheral USART1 base address */ + #define USART1_BASE_NS (0x40087000u) + /** Peripheral USART1 base pointer */ + #define USART1 ((USART_Type *)USART1_BASE) + /** Peripheral USART1 base pointer */ + #define USART1_NS ((USART_Type *)USART1_BASE_NS) + /** Peripheral USART2 base address */ + #define USART2_BASE (0x50088000u) + /** Peripheral USART2 base address */ + #define USART2_BASE_NS (0x40088000u) + /** Peripheral USART2 base pointer */ + #define USART2 ((USART_Type *)USART2_BASE) + /** Peripheral USART2 base pointer */ + #define USART2_NS ((USART_Type *)USART2_BASE_NS) + /** Peripheral USART3 base address */ + #define USART3_BASE (0x50089000u) + /** Peripheral USART3 base address */ + #define USART3_BASE_NS (0x40089000u) + /** Peripheral USART3 base pointer */ + #define USART3 ((USART_Type *)USART3_BASE) + /** Peripheral USART3 base pointer */ + #define USART3_NS ((USART_Type *)USART3_BASE_NS) + /** Peripheral USART4 base address */ + #define USART4_BASE (0x5008A000u) + /** Peripheral USART4 base address */ + #define USART4_BASE_NS (0x4008A000u) + /** Peripheral USART4 base pointer */ + #define USART4 ((USART_Type *)USART4_BASE) + /** Peripheral USART4 base pointer */ + #define USART4_NS ((USART_Type *)USART4_BASE_NS) + /** Peripheral USART5 base address */ + #define USART5_BASE (0x50096000u) + /** Peripheral USART5 base address */ + #define USART5_BASE_NS (0x40096000u) + /** Peripheral USART5 base pointer */ + #define USART5 ((USART_Type *)USART5_BASE) + /** Peripheral USART5 base pointer */ + #define USART5_NS ((USART_Type *)USART5_BASE_NS) + /** Peripheral USART6 base address */ + #define USART6_BASE (0x50097000u) + /** Peripheral USART6 base address */ + #define USART6_BASE_NS (0x40097000u) + /** Peripheral USART6 base pointer */ + #define USART6 ((USART_Type *)USART6_BASE) + /** Peripheral USART6 base pointer */ + #define USART6_NS ((USART_Type *)USART6_BASE_NS) + /** Peripheral USART7 base address */ + #define USART7_BASE (0x50098000u) + /** Peripheral USART7 base address */ + #define USART7_BASE_NS (0x40098000u) + /** Peripheral USART7 base pointer */ + #define USART7 ((USART_Type *)USART7_BASE) + /** Peripheral USART7 base pointer */ + #define USART7_NS ((USART_Type *)USART7_BASE_NS) + /** Array initializer of USART peripheral base addresses */ + #define USART_BASE_ADDRS { USART0_BASE, USART1_BASE, USART2_BASE, USART3_BASE, USART4_BASE, USART5_BASE, USART6_BASE, USART7_BASE } + /** Array initializer of USART peripheral base pointers */ + #define USART_BASE_PTRS { USART0, USART1, USART2, USART3, USART4, USART5, USART6, USART7 } + /** Array initializer of USART peripheral base addresses */ + #define USART_BASE_ADDRS_NS { USART0_BASE_NS, USART1_BASE_NS, USART2_BASE_NS, USART3_BASE_NS, USART4_BASE_NS, USART5_BASE_NS, USART6_BASE_NS, USART7_BASE_NS } + /** Array initializer of USART peripheral base pointers */ + #define USART_BASE_PTRS_NS { USART0_NS, USART1_NS, USART2_NS, USART3_NS, USART4_NS, USART5_NS, USART6_NS, USART7_NS } +#else + /** Peripheral USART0 base address */ + #define USART0_BASE (0x40086000u) + /** Peripheral USART0 base pointer */ + #define USART0 ((USART_Type *)USART0_BASE) + /** Peripheral USART1 base address */ + #define USART1_BASE (0x40087000u) + /** Peripheral USART1 base pointer */ + #define USART1 ((USART_Type *)USART1_BASE) + /** Peripheral USART2 base address */ + #define USART2_BASE (0x40088000u) + /** Peripheral USART2 base pointer */ + #define USART2 ((USART_Type *)USART2_BASE) + /** Peripheral USART3 base address */ + #define USART3_BASE (0x40089000u) + /** Peripheral USART3 base pointer */ + #define USART3 ((USART_Type *)USART3_BASE) + /** Peripheral USART4 base address */ + #define USART4_BASE (0x4008A000u) + /** Peripheral USART4 base pointer */ + #define USART4 ((USART_Type *)USART4_BASE) + /** Peripheral USART5 base address */ + #define USART5_BASE (0x40096000u) + /** Peripheral USART5 base pointer */ + #define USART5 ((USART_Type *)USART5_BASE) + /** Peripheral USART6 base address */ + #define USART6_BASE (0x40097000u) + /** Peripheral USART6 base pointer */ + #define USART6 ((USART_Type *)USART6_BASE) + /** Peripheral USART7 base address */ + #define USART7_BASE (0x40098000u) + /** Peripheral USART7 base pointer */ + #define USART7 ((USART_Type *)USART7_BASE) + /** Array initializer of USART peripheral base addresses */ + #define USART_BASE_ADDRS { USART0_BASE, USART1_BASE, USART2_BASE, USART3_BASE, USART4_BASE, USART5_BASE, USART6_BASE, USART7_BASE } + /** Array initializer of USART peripheral base pointers */ + #define USART_BASE_PTRS { USART0, USART1, USART2, USART3, USART4, USART5, USART6, USART7 } +#endif +/** Interrupt vectors for the USART peripheral type */ +#define USART_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } + +/*! + * @} + */ /* end of group USART_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USB Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer + * @{ + */ + +/** USB - Register Layout Typedef */ +typedef struct { + __IO uint32_t DEVCMDSTAT; /**< USB Device Command/Status register, offset: 0x0 */ + __IO uint32_t INFO; /**< USB Info register, offset: 0x4 */ + __IO uint32_t EPLISTSTART; /**< USB EP Command/Status List start address, offset: 0x8 */ + __IO uint32_t DATABUFSTART; /**< USB Data buffer start address, offset: 0xC */ + __IO uint32_t LPM; /**< USB Link Power Management register, offset: 0x10 */ + __IO uint32_t EPSKIP; /**< USB Endpoint skip, offset: 0x14 */ + __IO uint32_t EPINUSE; /**< USB Endpoint Buffer in use, offset: 0x18 */ + __IO uint32_t EPBUFCFG; /**< USB Endpoint Buffer Configuration register, offset: 0x1C */ + __IO uint32_t INTSTAT; /**< USB interrupt status register, offset: 0x20 */ + __IO uint32_t INTEN; /**< USB interrupt enable register, offset: 0x24 */ + __IO uint32_t INTSETSTAT; /**< USB set interrupt status register, offset: 0x28 */ + uint8_t RESERVED_0[8]; + __IO uint32_t EPTOGGLE; /**< USB Endpoint toggle register, offset: 0x34 */ +} USB_Type; + +/* ---------------------------------------------------------------------------- + -- USB Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_Register_Masks USB Register Masks + * @{ + */ + +/*! @name DEVCMDSTAT - USB Device Command/Status register */ +/*! @{ */ +#define USB_DEVCMDSTAT_DEV_ADDR_MASK (0x7FU) +#define USB_DEVCMDSTAT_DEV_ADDR_SHIFT (0U) +#define USB_DEVCMDSTAT_DEV_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_ADDR_SHIFT)) & USB_DEVCMDSTAT_DEV_ADDR_MASK) +#define USB_DEVCMDSTAT_DEV_EN_MASK (0x80U) +#define USB_DEVCMDSTAT_DEV_EN_SHIFT (7U) +#define USB_DEVCMDSTAT_DEV_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_EN_SHIFT)) & USB_DEVCMDSTAT_DEV_EN_MASK) +#define USB_DEVCMDSTAT_SETUP_MASK (0x100U) +#define USB_DEVCMDSTAT_SETUP_SHIFT (8U) +#define USB_DEVCMDSTAT_SETUP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_SETUP_SHIFT)) & USB_DEVCMDSTAT_SETUP_MASK) +#define USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK (0x200U) +#define USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT (9U) +/*! FORCE_NEEDCLK - Forces the NEEDCLK output to always be on: + * 0b0..USB_NEEDCLK has normal function. + * 0b1..USB_NEEDCLK always 1. Clock will not be stopped in case of suspend. + */ +#define USB_DEVCMDSTAT_FORCE_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT)) & USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK) +#define USB_DEVCMDSTAT_LPM_SUP_MASK (0x800U) +#define USB_DEVCMDSTAT_LPM_SUP_SHIFT (11U) +/*! LPM_SUP - LPM Supported: + * 0b0..LPM not supported. + * 0b1..LPM supported. + */ +#define USB_DEVCMDSTAT_LPM_SUP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUP_SHIFT)) & USB_DEVCMDSTAT_LPM_SUP_MASK) +#define USB_DEVCMDSTAT_INTONNAK_AO_MASK (0x1000U) +#define USB_DEVCMDSTAT_INTONNAK_AO_SHIFT (12U) +/*! INTONNAK_AO - Interrupt on NAK for interrupt and bulk OUT EP + * 0b0..Only acknowledged packets generate an interrupt + * 0b1..Both acknowledged and NAKed packets generate interrupts. + */ +#define USB_DEVCMDSTAT_INTONNAK_AO(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AO_MASK) +#define USB_DEVCMDSTAT_INTONNAK_AI_MASK (0x2000U) +#define USB_DEVCMDSTAT_INTONNAK_AI_SHIFT (13U) +/*! INTONNAK_AI - Interrupt on NAK for interrupt and bulk IN EP + * 0b0..Only acknowledged packets generate an interrupt + * 0b1..Both acknowledged and NAKed packets generate interrupts. + */ +#define USB_DEVCMDSTAT_INTONNAK_AI(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AI_MASK) +#define USB_DEVCMDSTAT_INTONNAK_CO_MASK (0x4000U) +#define USB_DEVCMDSTAT_INTONNAK_CO_SHIFT (14U) +/*! INTONNAK_CO - Interrupt on NAK for control OUT EP + * 0b0..Only acknowledged packets generate an interrupt + * 0b1..Both acknowledged and NAKed packets generate interrupts. + */ +#define USB_DEVCMDSTAT_INTONNAK_CO(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CO_MASK) +#define USB_DEVCMDSTAT_INTONNAK_CI_MASK (0x8000U) +#define USB_DEVCMDSTAT_INTONNAK_CI_SHIFT (15U) +/*! INTONNAK_CI - Interrupt on NAK for control IN EP + * 0b0..Only acknowledged packets generate an interrupt + * 0b1..Both acknowledged and NAKed packets generate interrupts. + */ +#define USB_DEVCMDSTAT_INTONNAK_CI(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CI_MASK) +#define USB_DEVCMDSTAT_DCON_MASK (0x10000U) +#define USB_DEVCMDSTAT_DCON_SHIFT (16U) +#define USB_DEVCMDSTAT_DCON(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_SHIFT)) & USB_DEVCMDSTAT_DCON_MASK) +#define USB_DEVCMDSTAT_DSUS_MASK (0x20000U) +#define USB_DEVCMDSTAT_DSUS_SHIFT (17U) +#define USB_DEVCMDSTAT_DSUS(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_SHIFT)) & USB_DEVCMDSTAT_DSUS_MASK) +#define USB_DEVCMDSTAT_LPM_SUS_MASK (0x80000U) +#define USB_DEVCMDSTAT_LPM_SUS_SHIFT (19U) +#define USB_DEVCMDSTAT_LPM_SUS(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUS_SHIFT)) & USB_DEVCMDSTAT_LPM_SUS_MASK) +#define USB_DEVCMDSTAT_LPM_REWP_MASK (0x100000U) +#define USB_DEVCMDSTAT_LPM_REWP_SHIFT (20U) +#define USB_DEVCMDSTAT_LPM_REWP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_REWP_SHIFT)) & USB_DEVCMDSTAT_LPM_REWP_MASK) +#define USB_DEVCMDSTAT_DCON_C_MASK (0x1000000U) +#define USB_DEVCMDSTAT_DCON_C_SHIFT (24U) +#define USB_DEVCMDSTAT_DCON_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_C_SHIFT)) & USB_DEVCMDSTAT_DCON_C_MASK) +#define USB_DEVCMDSTAT_DSUS_C_MASK (0x2000000U) +#define USB_DEVCMDSTAT_DSUS_C_SHIFT (25U) +#define USB_DEVCMDSTAT_DSUS_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_C_SHIFT)) & USB_DEVCMDSTAT_DSUS_C_MASK) +#define USB_DEVCMDSTAT_DRES_C_MASK (0x4000000U) +#define USB_DEVCMDSTAT_DRES_C_SHIFT (26U) +#define USB_DEVCMDSTAT_DRES_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DRES_C_SHIFT)) & USB_DEVCMDSTAT_DRES_C_MASK) +#define USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK (0x10000000U) +#define USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT (28U) +#define USB_DEVCMDSTAT_VBUSDEBOUNCED(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT)) & USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK) +/*! @} */ + +/*! @name INFO - USB Info register */ +/*! @{ */ +#define USB_INFO_FRAME_NR_MASK (0x7FFU) +#define USB_INFO_FRAME_NR_SHIFT (0U) +#define USB_INFO_FRAME_NR(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_FRAME_NR_SHIFT)) & USB_INFO_FRAME_NR_MASK) +#define USB_INFO_ERR_CODE_MASK (0x7800U) +#define USB_INFO_ERR_CODE_SHIFT (11U) +/*! ERR_CODE - The error code which last occurred: + * 0b0000..No error + * 0b0001..PID encoding error + * 0b0010..PID unknown + * 0b0011..Packet unexpected + * 0b0100..Token CRC error + * 0b0101..Data CRC error + * 0b0110..Time out + * 0b0111..Babble + * 0b1000..Truncated EOP + * 0b1001..Sent/Received NAK + * 0b1010..Sent Stall + * 0b1011..Overrun + * 0b1100..Sent empty packet + * 0b1101..Bitstuff error + * 0b1110..Sync error + * 0b1111..Wrong data toggle + */ +#define USB_INFO_ERR_CODE(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_ERR_CODE_SHIFT)) & USB_INFO_ERR_CODE_MASK) +#define USB_INFO_MINREV_MASK (0xFF0000U) +#define USB_INFO_MINREV_SHIFT (16U) +#define USB_INFO_MINREV(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_MINREV_SHIFT)) & USB_INFO_MINREV_MASK) +#define USB_INFO_MAJREV_MASK (0xFF000000U) +#define USB_INFO_MAJREV_SHIFT (24U) +#define USB_INFO_MAJREV(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_MAJREV_SHIFT)) & USB_INFO_MAJREV_MASK) +/*! @} */ + +/*! @name EPLISTSTART - USB EP Command/Status List start address */ +/*! @{ */ +#define USB_EPLISTSTART_EP_LIST_MASK (0xFFFFFF00U) +#define USB_EPLISTSTART_EP_LIST_SHIFT (8U) +#define USB_EPLISTSTART_EP_LIST(x) (((uint32_t)(((uint32_t)(x)) << USB_EPLISTSTART_EP_LIST_SHIFT)) & USB_EPLISTSTART_EP_LIST_MASK) +/*! @} */ + +/*! @name DATABUFSTART - USB Data buffer start address */ +/*! @{ */ +#define USB_DATABUFSTART_DA_BUF_MASK (0xFFC00000U) +#define USB_DATABUFSTART_DA_BUF_SHIFT (22U) +#define USB_DATABUFSTART_DA_BUF(x) (((uint32_t)(((uint32_t)(x)) << USB_DATABUFSTART_DA_BUF_SHIFT)) & USB_DATABUFSTART_DA_BUF_MASK) +/*! @} */ + +/*! @name LPM - USB Link Power Management register */ +/*! @{ */ +#define USB_LPM_HIRD_HW_MASK (0xFU) +#define USB_LPM_HIRD_HW_SHIFT (0U) +#define USB_LPM_HIRD_HW(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_HW_SHIFT)) & USB_LPM_HIRD_HW_MASK) +#define USB_LPM_HIRD_SW_MASK (0xF0U) +#define USB_LPM_HIRD_SW_SHIFT (4U) +#define USB_LPM_HIRD_SW(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_SW_SHIFT)) & USB_LPM_HIRD_SW_MASK) +#define USB_LPM_DATA_PENDING_MASK (0x100U) +#define USB_LPM_DATA_PENDING_SHIFT (8U) +#define USB_LPM_DATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_DATA_PENDING_SHIFT)) & USB_LPM_DATA_PENDING_MASK) +/*! @} */ + +/*! @name EPSKIP - USB Endpoint skip */ +/*! @{ */ +#define USB_EPSKIP_SKIP_MASK (0x3FFU) +#define USB_EPSKIP_SKIP_SHIFT (0U) +#define USB_EPSKIP_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USB_EPSKIP_SKIP_SHIFT)) & USB_EPSKIP_SKIP_MASK) +/*! @} */ + +/*! @name EPINUSE - USB Endpoint Buffer in use */ +/*! @{ */ +#define USB_EPINUSE_BUF_MASK (0x3FCU) +#define USB_EPINUSE_BUF_SHIFT (2U) +#define USB_EPINUSE_BUF(x) (((uint32_t)(((uint32_t)(x)) << USB_EPINUSE_BUF_SHIFT)) & USB_EPINUSE_BUF_MASK) +/*! @} */ + +/*! @name EPBUFCFG - USB Endpoint Buffer Configuration register */ +/*! @{ */ +#define USB_EPBUFCFG_BUF_SB_MASK (0x3FCU) +#define USB_EPBUFCFG_BUF_SB_SHIFT (2U) +#define USB_EPBUFCFG_BUF_SB(x) (((uint32_t)(((uint32_t)(x)) << USB_EPBUFCFG_BUF_SB_SHIFT)) & USB_EPBUFCFG_BUF_SB_MASK) +/*! @} */ + +/*! @name INTSTAT - USB interrupt status register */ +/*! @{ */ +#define USB_INTSTAT_EP0OUT_MASK (0x1U) +#define USB_INTSTAT_EP0OUT_SHIFT (0U) +#define USB_INTSTAT_EP0OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0OUT_SHIFT)) & USB_INTSTAT_EP0OUT_MASK) +#define USB_INTSTAT_EP0IN_MASK (0x2U) +#define USB_INTSTAT_EP0IN_SHIFT (1U) +#define USB_INTSTAT_EP0IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0IN_SHIFT)) & USB_INTSTAT_EP0IN_MASK) +#define USB_INTSTAT_EP1OUT_MASK (0x4U) +#define USB_INTSTAT_EP1OUT_SHIFT (2U) +#define USB_INTSTAT_EP1OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1OUT_SHIFT)) & USB_INTSTAT_EP1OUT_MASK) +#define USB_INTSTAT_EP1IN_MASK (0x8U) +#define USB_INTSTAT_EP1IN_SHIFT (3U) +#define USB_INTSTAT_EP1IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1IN_SHIFT)) & USB_INTSTAT_EP1IN_MASK) +#define USB_INTSTAT_EP2OUT_MASK (0x10U) +#define USB_INTSTAT_EP2OUT_SHIFT (4U) +#define USB_INTSTAT_EP2OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2OUT_SHIFT)) & USB_INTSTAT_EP2OUT_MASK) +#define USB_INTSTAT_EP2IN_MASK (0x20U) +#define USB_INTSTAT_EP2IN_SHIFT (5U) +#define USB_INTSTAT_EP2IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2IN_SHIFT)) & USB_INTSTAT_EP2IN_MASK) +#define USB_INTSTAT_EP3OUT_MASK (0x40U) +#define USB_INTSTAT_EP3OUT_SHIFT (6U) +#define USB_INTSTAT_EP3OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3OUT_SHIFT)) & USB_INTSTAT_EP3OUT_MASK) +#define USB_INTSTAT_EP3IN_MASK (0x80U) +#define USB_INTSTAT_EP3IN_SHIFT (7U) +#define USB_INTSTAT_EP3IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3IN_SHIFT)) & USB_INTSTAT_EP3IN_MASK) +#define USB_INTSTAT_EP4OUT_MASK (0x100U) +#define USB_INTSTAT_EP4OUT_SHIFT (8U) +#define USB_INTSTAT_EP4OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4OUT_SHIFT)) & USB_INTSTAT_EP4OUT_MASK) +#define USB_INTSTAT_EP4IN_MASK (0x200U) +#define USB_INTSTAT_EP4IN_SHIFT (9U) +#define USB_INTSTAT_EP4IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4IN_SHIFT)) & USB_INTSTAT_EP4IN_MASK) +#define USB_INTSTAT_FRAME_INT_MASK (0x40000000U) +#define USB_INTSTAT_FRAME_INT_SHIFT (30U) +#define USB_INTSTAT_FRAME_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_FRAME_INT_SHIFT)) & USB_INTSTAT_FRAME_INT_MASK) +#define USB_INTSTAT_DEV_INT_MASK (0x80000000U) +#define USB_INTSTAT_DEV_INT_SHIFT (31U) +#define USB_INTSTAT_DEV_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_DEV_INT_SHIFT)) & USB_INTSTAT_DEV_INT_MASK) +/*! @} */ + +/*! @name INTEN - USB interrupt enable register */ +/*! @{ */ +#define USB_INTEN_EP_INT_EN_MASK (0x3FFU) +#define USB_INTEN_EP_INT_EN_SHIFT (0U) +#define USB_INTEN_EP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_EP_INT_EN_SHIFT)) & USB_INTEN_EP_INT_EN_MASK) +#define USB_INTEN_FRAME_INT_EN_MASK (0x40000000U) +#define USB_INTEN_FRAME_INT_EN_SHIFT (30U) +#define USB_INTEN_FRAME_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_FRAME_INT_EN_SHIFT)) & USB_INTEN_FRAME_INT_EN_MASK) +#define USB_INTEN_DEV_INT_EN_MASK (0x80000000U) +#define USB_INTEN_DEV_INT_EN_SHIFT (31U) +#define USB_INTEN_DEV_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_DEV_INT_EN_SHIFT)) & USB_INTEN_DEV_INT_EN_MASK) +/*! @} */ + +/*! @name INTSETSTAT - USB set interrupt status register */ +/*! @{ */ +#define USB_INTSETSTAT_EP_SET_INT_MASK (0x3FFU) +#define USB_INTSETSTAT_EP_SET_INT_SHIFT (0U) +#define USB_INTSETSTAT_EP_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_EP_SET_INT_SHIFT)) & USB_INTSETSTAT_EP_SET_INT_MASK) +#define USB_INTSETSTAT_FRAME_SET_INT_MASK (0x40000000U) +#define USB_INTSETSTAT_FRAME_SET_INT_SHIFT (30U) +#define USB_INTSETSTAT_FRAME_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_FRAME_SET_INT_SHIFT)) & USB_INTSETSTAT_FRAME_SET_INT_MASK) +#define USB_INTSETSTAT_DEV_SET_INT_MASK (0x80000000U) +#define USB_INTSETSTAT_DEV_SET_INT_SHIFT (31U) +#define USB_INTSETSTAT_DEV_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_DEV_SET_INT_SHIFT)) & USB_INTSETSTAT_DEV_SET_INT_MASK) +/*! @} */ + +/*! @name EPTOGGLE - USB Endpoint toggle register */ +/*! @{ */ +#define USB_EPTOGGLE_TOGGLE_MASK (0x3FFU) +#define USB_EPTOGGLE_TOGGLE_SHIFT (0U) +#define USB_EPTOGGLE_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << USB_EPTOGGLE_TOGGLE_SHIFT)) & USB_EPTOGGLE_TOGGLE_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group USB_Register_Masks */ + + +/* USB - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral USB0 base address */ + #define USB0_BASE (0x50084000u) + /** Peripheral USB0 base address */ + #define USB0_BASE_NS (0x40084000u) + /** Peripheral USB0 base pointer */ + #define USB0 ((USB_Type *)USB0_BASE) + /** Peripheral USB0 base pointer */ + #define USB0_NS ((USB_Type *)USB0_BASE_NS) + /** Array initializer of USB peripheral base addresses */ + #define USB_BASE_ADDRS { USB0_BASE } + /** Array initializer of USB peripheral base pointers */ + #define USB_BASE_PTRS { USB0 } + /** Array initializer of USB peripheral base addresses */ + #define USB_BASE_ADDRS_NS { USB0_BASE_NS } + /** Array initializer of USB peripheral base pointers */ + #define USB_BASE_PTRS_NS { USB0_NS } +#else + /** Peripheral USB0 base address */ + #define USB0_BASE (0x40084000u) + /** Peripheral USB0 base pointer */ + #define USB0 ((USB_Type *)USB0_BASE) + /** Array initializer of USB peripheral base addresses */ + #define USB_BASE_ADDRS { USB0_BASE } + /** Array initializer of USB peripheral base pointers */ + #define USB_BASE_PTRS { USB0 } +#endif +/** Interrupt vectors for the USB peripheral type */ +#define USB_IRQS { USB0_IRQn } +#define USB_NEEDCLK_IRQS { USB0_NEEDCLK_IRQn } + +/*! + * @} + */ /* end of group USB_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USBFSH Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBFSH_Peripheral_Access_Layer USBFSH Peripheral Access Layer + * @{ + */ + +/** USBFSH - Register Layout Typedef */ +typedef struct { + __I uint32_t HCREVISION; /**< BCD representation of the version of the HCI specification that is implemented by the Host Controller (HC), offset: 0x0 */ + __IO uint32_t HCCONTROL; /**< Defines the operating modes of the HC, offset: 0x4 */ + __IO uint32_t HCCOMMANDSTATUS; /**< This register is used to receive the commands from the Host Controller Driver (HCD), offset: 0x8 */ + __IO uint32_t HCINTERRUPTSTATUS; /**< Indicates the status on various events that cause hardware interrupts by setting the appropriate bits, offset: 0xC */ + __IO uint32_t HCINTERRUPTENABLE; /**< Controls the bits in the HcInterruptStatus register and indicates which events will generate a hardware interrupt, offset: 0x10 */ + __IO uint32_t HCINTERRUPTDISABLE; /**< The bits in this register are used to disable corresponding bits in the HCInterruptStatus register and in turn disable that event leading to hardware interrupt, offset: 0x14 */ + __IO uint32_t HCHCCA; /**< Contains the physical address of the host controller communication area, offset: 0x18 */ + __IO uint32_t HCPERIODCURRENTED; /**< Contains the physical address of the current isochronous or interrupt endpoint descriptor, offset: 0x1C */ + __IO uint32_t HCCONTROLHEADED; /**< Contains the physical address of the first endpoint descriptor of the control list, offset: 0x20 */ + __IO uint32_t HCCONTROLCURRENTED; /**< Contains the physical address of the current endpoint descriptor of the control list, offset: 0x24 */ + __IO uint32_t HCBULKHEADED; /**< Contains the physical address of the first endpoint descriptor of the bulk list, offset: 0x28 */ + __IO uint32_t HCBULKCURRENTED; /**< Contains the physical address of the current endpoint descriptor of the bulk list, offset: 0x2C */ + __IO uint32_t HCDONEHEAD; /**< Contains the physical address of the last transfer descriptor added to the 'Done' queue, offset: 0x30 */ + __IO uint32_t HCFMINTERVAL; /**< Defines the bit time interval in a frame and the full speed maximum packet size which would not cause an overrun, offset: 0x34 */ + __IO uint32_t HCFMREMAINING; /**< A 14-bit counter showing the bit time remaining in the current frame, offset: 0x38 */ + __IO uint32_t HCFMNUMBER; /**< Contains a 16-bit counter and provides the timing reference among events happening in the HC and the HCD, offset: 0x3C */ + __IO uint32_t HCPERIODICSTART; /**< Contains a programmable 14-bit value which determines the earliest time HC should start processing a periodic list, offset: 0x40 */ + __IO uint32_t HCLSTHRESHOLD; /**< Contains 11-bit value which is used by the HC to determine whether to commit to transfer a maximum of 8-byte LS packet before EOF, offset: 0x44 */ + __IO uint32_t HCRHDESCRIPTORA; /**< First of the two registers which describes the characteristics of the root hub, offset: 0x48 */ + __IO uint32_t HCRHDESCRIPTORB; /**< Second of the two registers which describes the characteristics of the Root Hub, offset: 0x4C */ + __IO uint32_t HCRHSTATUS; /**< This register is divided into two parts, offset: 0x50 */ + __IO uint32_t HCRHPORTSTATUS; /**< Controls and reports the port events on a per-port basis, offset: 0x54 */ + uint8_t RESERVED_0[4]; + __IO uint32_t PORTMODE; /**< Controls the port if it is attached to the host block or the device block, offset: 0x5C */ +} USBFSH_Type; + +/* ---------------------------------------------------------------------------- + -- USBFSH Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBFSH_Register_Masks USBFSH Register Masks + * @{ + */ + +/*! @name HCREVISION - BCD representation of the version of the HCI specification that is implemented by the Host Controller (HC) */ +/*! @{ */ +#define USBFSH_HCREVISION_REV_MASK (0xFFU) +#define USBFSH_HCREVISION_REV_SHIFT (0U) +#define USBFSH_HCREVISION_REV(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCREVISION_REV_SHIFT)) & USBFSH_HCREVISION_REV_MASK) +/*! @} */ + +/*! @name HCCONTROL - Defines the operating modes of the HC */ +/*! @{ */ +#define USBFSH_HCCONTROL_CBSR_MASK (0x3U) +#define USBFSH_HCCONTROL_CBSR_SHIFT (0U) +#define USBFSH_HCCONTROL_CBSR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_CBSR_SHIFT)) & USBFSH_HCCONTROL_CBSR_MASK) +#define USBFSH_HCCONTROL_PLE_MASK (0x4U) +#define USBFSH_HCCONTROL_PLE_SHIFT (2U) +#define USBFSH_HCCONTROL_PLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_PLE_SHIFT)) & USBFSH_HCCONTROL_PLE_MASK) +#define USBFSH_HCCONTROL_IE_MASK (0x8U) +#define USBFSH_HCCONTROL_IE_SHIFT (3U) +#define USBFSH_HCCONTROL_IE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_IE_SHIFT)) & USBFSH_HCCONTROL_IE_MASK) +#define USBFSH_HCCONTROL_CLE_MASK (0x10U) +#define USBFSH_HCCONTROL_CLE_SHIFT (4U) +#define USBFSH_HCCONTROL_CLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_CLE_SHIFT)) & USBFSH_HCCONTROL_CLE_MASK) +#define USBFSH_HCCONTROL_BLE_MASK (0x20U) +#define USBFSH_HCCONTROL_BLE_SHIFT (5U) +#define USBFSH_HCCONTROL_BLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_BLE_SHIFT)) & USBFSH_HCCONTROL_BLE_MASK) +#define USBFSH_HCCONTROL_HCFS_MASK (0xC0U) +#define USBFSH_HCCONTROL_HCFS_SHIFT (6U) +#define USBFSH_HCCONTROL_HCFS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_HCFS_SHIFT)) & USBFSH_HCCONTROL_HCFS_MASK) +#define USBFSH_HCCONTROL_IR_MASK (0x100U) +#define USBFSH_HCCONTROL_IR_SHIFT (8U) +#define USBFSH_HCCONTROL_IR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_IR_SHIFT)) & USBFSH_HCCONTROL_IR_MASK) +#define USBFSH_HCCONTROL_RWC_MASK (0x200U) +#define USBFSH_HCCONTROL_RWC_SHIFT (9U) +#define USBFSH_HCCONTROL_RWC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_RWC_SHIFT)) & USBFSH_HCCONTROL_RWC_MASK) +#define USBFSH_HCCONTROL_RWE_MASK (0x400U) +#define USBFSH_HCCONTROL_RWE_SHIFT (10U) +#define USBFSH_HCCONTROL_RWE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_RWE_SHIFT)) & USBFSH_HCCONTROL_RWE_MASK) +/*! @} */ + +/*! @name HCCOMMANDSTATUS - This register is used to receive the commands from the Host Controller Driver (HCD) */ +/*! @{ */ +#define USBFSH_HCCOMMANDSTATUS_HCR_MASK (0x1U) +#define USBFSH_HCCOMMANDSTATUS_HCR_SHIFT (0U) +#define USBFSH_HCCOMMANDSTATUS_HCR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_HCR_SHIFT)) & USBFSH_HCCOMMANDSTATUS_HCR_MASK) +#define USBFSH_HCCOMMANDSTATUS_CLF_MASK (0x2U) +#define USBFSH_HCCOMMANDSTATUS_CLF_SHIFT (1U) +#define USBFSH_HCCOMMANDSTATUS_CLF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_CLF_SHIFT)) & USBFSH_HCCOMMANDSTATUS_CLF_MASK) +#define USBFSH_HCCOMMANDSTATUS_BLF_MASK (0x4U) +#define USBFSH_HCCOMMANDSTATUS_BLF_SHIFT (2U) +#define USBFSH_HCCOMMANDSTATUS_BLF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_BLF_SHIFT)) & USBFSH_HCCOMMANDSTATUS_BLF_MASK) +#define USBFSH_HCCOMMANDSTATUS_OCR_MASK (0x8U) +#define USBFSH_HCCOMMANDSTATUS_OCR_SHIFT (3U) +#define USBFSH_HCCOMMANDSTATUS_OCR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_OCR_SHIFT)) & USBFSH_HCCOMMANDSTATUS_OCR_MASK) +#define USBFSH_HCCOMMANDSTATUS_SOC_MASK (0xC0U) +#define USBFSH_HCCOMMANDSTATUS_SOC_SHIFT (6U) +#define USBFSH_HCCOMMANDSTATUS_SOC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_SOC_SHIFT)) & USBFSH_HCCOMMANDSTATUS_SOC_MASK) +/*! @} */ + +/*! @name HCINTERRUPTSTATUS - Indicates the status on various events that cause hardware interrupts by setting the appropriate bits */ +/*! @{ */ +#define USBFSH_HCINTERRUPTSTATUS_SO_MASK (0x1U) +#define USBFSH_HCINTERRUPTSTATUS_SO_SHIFT (0U) +#define USBFSH_HCINTERRUPTSTATUS_SO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_SO_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_SO_MASK) +#define USBFSH_HCINTERRUPTSTATUS_WDH_MASK (0x2U) +#define USBFSH_HCINTERRUPTSTATUS_WDH_SHIFT (1U) +#define USBFSH_HCINTERRUPTSTATUS_WDH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_WDH_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_WDH_MASK) +#define USBFSH_HCINTERRUPTSTATUS_SF_MASK (0x4U) +#define USBFSH_HCINTERRUPTSTATUS_SF_SHIFT (2U) +#define USBFSH_HCINTERRUPTSTATUS_SF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_SF_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_SF_MASK) +#define USBFSH_HCINTERRUPTSTATUS_RD_MASK (0x8U) +#define USBFSH_HCINTERRUPTSTATUS_RD_SHIFT (3U) +#define USBFSH_HCINTERRUPTSTATUS_RD(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_RD_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_RD_MASK) +#define USBFSH_HCINTERRUPTSTATUS_UE_MASK (0x10U) +#define USBFSH_HCINTERRUPTSTATUS_UE_SHIFT (4U) +#define USBFSH_HCINTERRUPTSTATUS_UE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_UE_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_UE_MASK) +#define USBFSH_HCINTERRUPTSTATUS_FNO_MASK (0x20U) +#define USBFSH_HCINTERRUPTSTATUS_FNO_SHIFT (5U) +#define USBFSH_HCINTERRUPTSTATUS_FNO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_FNO_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_FNO_MASK) +#define USBFSH_HCINTERRUPTSTATUS_RHSC_MASK (0x40U) +#define USBFSH_HCINTERRUPTSTATUS_RHSC_SHIFT (6U) +#define USBFSH_HCINTERRUPTSTATUS_RHSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_RHSC_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_RHSC_MASK) +#define USBFSH_HCINTERRUPTSTATUS_OC_MASK (0xFFFFFC00U) +#define USBFSH_HCINTERRUPTSTATUS_OC_SHIFT (10U) +#define USBFSH_HCINTERRUPTSTATUS_OC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_OC_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_OC_MASK) +/*! @} */ + +/*! @name HCINTERRUPTENABLE - Controls the bits in the HcInterruptStatus register and indicates which events will generate a hardware interrupt */ +/*! @{ */ +#define USBFSH_HCINTERRUPTENABLE_SO_MASK (0x1U) +#define USBFSH_HCINTERRUPTENABLE_SO_SHIFT (0U) +#define USBFSH_HCINTERRUPTENABLE_SO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_SO_SHIFT)) & USBFSH_HCINTERRUPTENABLE_SO_MASK) +#define USBFSH_HCINTERRUPTENABLE_WDH_MASK (0x2U) +#define USBFSH_HCINTERRUPTENABLE_WDH_SHIFT (1U) +#define USBFSH_HCINTERRUPTENABLE_WDH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_WDH_SHIFT)) & USBFSH_HCINTERRUPTENABLE_WDH_MASK) +#define USBFSH_HCINTERRUPTENABLE_SF_MASK (0x4U) +#define USBFSH_HCINTERRUPTENABLE_SF_SHIFT (2U) +#define USBFSH_HCINTERRUPTENABLE_SF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_SF_SHIFT)) & USBFSH_HCINTERRUPTENABLE_SF_MASK) +#define USBFSH_HCINTERRUPTENABLE_RD_MASK (0x8U) +#define USBFSH_HCINTERRUPTENABLE_RD_SHIFT (3U) +#define USBFSH_HCINTERRUPTENABLE_RD(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_RD_SHIFT)) & USBFSH_HCINTERRUPTENABLE_RD_MASK) +#define USBFSH_HCINTERRUPTENABLE_UE_MASK (0x10U) +#define USBFSH_HCINTERRUPTENABLE_UE_SHIFT (4U) +#define USBFSH_HCINTERRUPTENABLE_UE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_UE_SHIFT)) & USBFSH_HCINTERRUPTENABLE_UE_MASK) +#define USBFSH_HCINTERRUPTENABLE_FNO_MASK (0x20U) +#define USBFSH_HCINTERRUPTENABLE_FNO_SHIFT (5U) +#define USBFSH_HCINTERRUPTENABLE_FNO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_FNO_SHIFT)) & USBFSH_HCINTERRUPTENABLE_FNO_MASK) +#define USBFSH_HCINTERRUPTENABLE_RHSC_MASK (0x40U) +#define USBFSH_HCINTERRUPTENABLE_RHSC_SHIFT (6U) +#define USBFSH_HCINTERRUPTENABLE_RHSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_RHSC_SHIFT)) & USBFSH_HCINTERRUPTENABLE_RHSC_MASK) +#define USBFSH_HCINTERRUPTENABLE_OC_MASK (0x40000000U) +#define USBFSH_HCINTERRUPTENABLE_OC_SHIFT (30U) +#define USBFSH_HCINTERRUPTENABLE_OC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_OC_SHIFT)) & USBFSH_HCINTERRUPTENABLE_OC_MASK) +#define USBFSH_HCINTERRUPTENABLE_MIE_MASK (0x80000000U) +#define USBFSH_HCINTERRUPTENABLE_MIE_SHIFT (31U) +#define USBFSH_HCINTERRUPTENABLE_MIE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_MIE_SHIFT)) & USBFSH_HCINTERRUPTENABLE_MIE_MASK) +/*! @} */ + +/*! @name HCINTERRUPTDISABLE - The bits in this register are used to disable corresponding bits in the HCInterruptStatus register and in turn disable that event leading to hardware interrupt */ +/*! @{ */ +#define USBFSH_HCINTERRUPTDISABLE_SO_MASK (0x1U) +#define USBFSH_HCINTERRUPTDISABLE_SO_SHIFT (0U) +#define USBFSH_HCINTERRUPTDISABLE_SO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_SO_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_SO_MASK) +#define USBFSH_HCINTERRUPTDISABLE_WDH_MASK (0x2U) +#define USBFSH_HCINTERRUPTDISABLE_WDH_SHIFT (1U) +#define USBFSH_HCINTERRUPTDISABLE_WDH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_WDH_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_WDH_MASK) +#define USBFSH_HCINTERRUPTDISABLE_SF_MASK (0x4U) +#define USBFSH_HCINTERRUPTDISABLE_SF_SHIFT (2U) +#define USBFSH_HCINTERRUPTDISABLE_SF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_SF_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_SF_MASK) +#define USBFSH_HCINTERRUPTDISABLE_RD_MASK (0x8U) +#define USBFSH_HCINTERRUPTDISABLE_RD_SHIFT (3U) +#define USBFSH_HCINTERRUPTDISABLE_RD(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_RD_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_RD_MASK) +#define USBFSH_HCINTERRUPTDISABLE_UE_MASK (0x10U) +#define USBFSH_HCINTERRUPTDISABLE_UE_SHIFT (4U) +#define USBFSH_HCINTERRUPTDISABLE_UE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_UE_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_UE_MASK) +#define USBFSH_HCINTERRUPTDISABLE_FNO_MASK (0x20U) +#define USBFSH_HCINTERRUPTDISABLE_FNO_SHIFT (5U) +#define USBFSH_HCINTERRUPTDISABLE_FNO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_FNO_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_FNO_MASK) +#define USBFSH_HCINTERRUPTDISABLE_RHSC_MASK (0x40U) +#define USBFSH_HCINTERRUPTDISABLE_RHSC_SHIFT (6U) +#define USBFSH_HCINTERRUPTDISABLE_RHSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_RHSC_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_RHSC_MASK) +#define USBFSH_HCINTERRUPTDISABLE_OC_MASK (0x40000000U) +#define USBFSH_HCINTERRUPTDISABLE_OC_SHIFT (30U) +#define USBFSH_HCINTERRUPTDISABLE_OC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_OC_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_OC_MASK) +#define USBFSH_HCINTERRUPTDISABLE_MIE_MASK (0x80000000U) +#define USBFSH_HCINTERRUPTDISABLE_MIE_SHIFT (31U) +#define USBFSH_HCINTERRUPTDISABLE_MIE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_MIE_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_MIE_MASK) +/*! @} */ + +/*! @name HCHCCA - Contains the physical address of the host controller communication area */ +/*! @{ */ +#define USBFSH_HCHCCA_HCCA_MASK (0xFFFFFF00U) +#define USBFSH_HCHCCA_HCCA_SHIFT (8U) +#define USBFSH_HCHCCA_HCCA(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCHCCA_HCCA_SHIFT)) & USBFSH_HCHCCA_HCCA_MASK) +/*! @} */ + +/*! @name HCPERIODCURRENTED - Contains the physical address of the current isochronous or interrupt endpoint descriptor */ +/*! @{ */ +#define USBFSH_HCPERIODCURRENTED_PCED_MASK (0xFFFFFFF0U) +#define USBFSH_HCPERIODCURRENTED_PCED_SHIFT (4U) +#define USBFSH_HCPERIODCURRENTED_PCED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCPERIODCURRENTED_PCED_SHIFT)) & USBFSH_HCPERIODCURRENTED_PCED_MASK) +/*! @} */ + +/*! @name HCCONTROLHEADED - Contains the physical address of the first endpoint descriptor of the control list */ +/*! @{ */ +#define USBFSH_HCCONTROLHEADED_CHED_MASK (0xFFFFFFF0U) +#define USBFSH_HCCONTROLHEADED_CHED_SHIFT (4U) +#define USBFSH_HCCONTROLHEADED_CHED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROLHEADED_CHED_SHIFT)) & USBFSH_HCCONTROLHEADED_CHED_MASK) +/*! @} */ + +/*! @name HCCONTROLCURRENTED - Contains the physical address of the current endpoint descriptor of the control list */ +/*! @{ */ +#define USBFSH_HCCONTROLCURRENTED_CCED_MASK (0xFFFFFFF0U) +#define USBFSH_HCCONTROLCURRENTED_CCED_SHIFT (4U) +#define USBFSH_HCCONTROLCURRENTED_CCED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROLCURRENTED_CCED_SHIFT)) & USBFSH_HCCONTROLCURRENTED_CCED_MASK) +/*! @} */ + +/*! @name HCBULKHEADED - Contains the physical address of the first endpoint descriptor of the bulk list */ +/*! @{ */ +#define USBFSH_HCBULKHEADED_BHED_MASK (0xFFFFFFF0U) +#define USBFSH_HCBULKHEADED_BHED_SHIFT (4U) +#define USBFSH_HCBULKHEADED_BHED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCBULKHEADED_BHED_SHIFT)) & USBFSH_HCBULKHEADED_BHED_MASK) +/*! @} */ + +/*! @name HCBULKCURRENTED - Contains the physical address of the current endpoint descriptor of the bulk list */ +/*! @{ */ +#define USBFSH_HCBULKCURRENTED_BCED_MASK (0xFFFFFFF0U) +#define USBFSH_HCBULKCURRENTED_BCED_SHIFT (4U) +#define USBFSH_HCBULKCURRENTED_BCED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCBULKCURRENTED_BCED_SHIFT)) & USBFSH_HCBULKCURRENTED_BCED_MASK) +/*! @} */ + +/*! @name HCDONEHEAD - Contains the physical address of the last transfer descriptor added to the 'Done' queue */ +/*! @{ */ +#define USBFSH_HCDONEHEAD_DH_MASK (0xFFFFFFF0U) +#define USBFSH_HCDONEHEAD_DH_SHIFT (4U) +#define USBFSH_HCDONEHEAD_DH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCDONEHEAD_DH_SHIFT)) & USBFSH_HCDONEHEAD_DH_MASK) +/*! @} */ + +/*! @name HCFMINTERVAL - Defines the bit time interval in a frame and the full speed maximum packet size which would not cause an overrun */ +/*! @{ */ +#define USBFSH_HCFMINTERVAL_FI_MASK (0x3FFFU) +#define USBFSH_HCFMINTERVAL_FI_SHIFT (0U) +#define USBFSH_HCFMINTERVAL_FI(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FI_SHIFT)) & USBFSH_HCFMINTERVAL_FI_MASK) +#define USBFSH_HCFMINTERVAL_FSMPS_MASK (0x7FFF0000U) +#define USBFSH_HCFMINTERVAL_FSMPS_SHIFT (16U) +#define USBFSH_HCFMINTERVAL_FSMPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FSMPS_SHIFT)) & USBFSH_HCFMINTERVAL_FSMPS_MASK) +#define USBFSH_HCFMINTERVAL_FIT_MASK (0x80000000U) +#define USBFSH_HCFMINTERVAL_FIT_SHIFT (31U) +#define USBFSH_HCFMINTERVAL_FIT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FIT_SHIFT)) & USBFSH_HCFMINTERVAL_FIT_MASK) +/*! @} */ + +/*! @name HCFMREMAINING - A 14-bit counter showing the bit time remaining in the current frame */ +/*! @{ */ +#define USBFSH_HCFMREMAINING_FR_MASK (0x3FFFU) +#define USBFSH_HCFMREMAINING_FR_SHIFT (0U) +#define USBFSH_HCFMREMAINING_FR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMREMAINING_FR_SHIFT)) & USBFSH_HCFMREMAINING_FR_MASK) +#define USBFSH_HCFMREMAINING_FRT_MASK (0x80000000U) +#define USBFSH_HCFMREMAINING_FRT_SHIFT (31U) +#define USBFSH_HCFMREMAINING_FRT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMREMAINING_FRT_SHIFT)) & USBFSH_HCFMREMAINING_FRT_MASK) +/*! @} */ + +/*! @name HCFMNUMBER - Contains a 16-bit counter and provides the timing reference among events happening in the HC and the HCD */ +/*! @{ */ +#define USBFSH_HCFMNUMBER_FN_MASK (0xFFFFU) +#define USBFSH_HCFMNUMBER_FN_SHIFT (0U) +#define USBFSH_HCFMNUMBER_FN(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMNUMBER_FN_SHIFT)) & USBFSH_HCFMNUMBER_FN_MASK) +/*! @} */ + +/*! @name HCPERIODICSTART - Contains a programmable 14-bit value which determines the earliest time HC should start processing a periodic list */ +/*! @{ */ +#define USBFSH_HCPERIODICSTART_PS_MASK (0x3FFFU) +#define USBFSH_HCPERIODICSTART_PS_SHIFT (0U) +#define USBFSH_HCPERIODICSTART_PS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCPERIODICSTART_PS_SHIFT)) & USBFSH_HCPERIODICSTART_PS_MASK) +/*! @} */ + +/*! @name HCLSTHRESHOLD - Contains 11-bit value which is used by the HC to determine whether to commit to transfer a maximum of 8-byte LS packet before EOF */ +/*! @{ */ +#define USBFSH_HCLSTHRESHOLD_LST_MASK (0xFFFU) +#define USBFSH_HCLSTHRESHOLD_LST_SHIFT (0U) +#define USBFSH_HCLSTHRESHOLD_LST(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCLSTHRESHOLD_LST_SHIFT)) & USBFSH_HCLSTHRESHOLD_LST_MASK) +/*! @} */ + +/*! @name HCRHDESCRIPTORA - First of the two registers which describes the characteristics of the root hub */ +/*! @{ */ +#define USBFSH_HCRHDESCRIPTORA_NDP_MASK (0xFFU) +#define USBFSH_HCRHDESCRIPTORA_NDP_SHIFT (0U) +#define USBFSH_HCRHDESCRIPTORA_NDP(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NDP_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NDP_MASK) +#define USBFSH_HCRHDESCRIPTORA_PSM_MASK (0x100U) +#define USBFSH_HCRHDESCRIPTORA_PSM_SHIFT (8U) +#define USBFSH_HCRHDESCRIPTORA_PSM(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_PSM_SHIFT)) & USBFSH_HCRHDESCRIPTORA_PSM_MASK) +#define USBFSH_HCRHDESCRIPTORA_NPS_MASK (0x200U) +#define USBFSH_HCRHDESCRIPTORA_NPS_SHIFT (9U) +#define USBFSH_HCRHDESCRIPTORA_NPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NPS_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NPS_MASK) +#define USBFSH_HCRHDESCRIPTORA_DT_MASK (0x400U) +#define USBFSH_HCRHDESCRIPTORA_DT_SHIFT (10U) +#define USBFSH_HCRHDESCRIPTORA_DT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_DT_SHIFT)) & USBFSH_HCRHDESCRIPTORA_DT_MASK) +#define USBFSH_HCRHDESCRIPTORA_OCPM_MASK (0x800U) +#define USBFSH_HCRHDESCRIPTORA_OCPM_SHIFT (11U) +#define USBFSH_HCRHDESCRIPTORA_OCPM(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_OCPM_SHIFT)) & USBFSH_HCRHDESCRIPTORA_OCPM_MASK) +#define USBFSH_HCRHDESCRIPTORA_NOCP_MASK (0x1000U) +#define USBFSH_HCRHDESCRIPTORA_NOCP_SHIFT (12U) +#define USBFSH_HCRHDESCRIPTORA_NOCP(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NOCP_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NOCP_MASK) +#define USBFSH_HCRHDESCRIPTORA_POTPGT_MASK (0xFF000000U) +#define USBFSH_HCRHDESCRIPTORA_POTPGT_SHIFT (24U) +#define USBFSH_HCRHDESCRIPTORA_POTPGT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_POTPGT_SHIFT)) & USBFSH_HCRHDESCRIPTORA_POTPGT_MASK) +/*! @} */ + +/*! @name HCRHDESCRIPTORB - Second of the two registers which describes the characteristics of the Root Hub */ +/*! @{ */ +#define USBFSH_HCRHDESCRIPTORB_DR_MASK (0xFFFFU) +#define USBFSH_HCRHDESCRIPTORB_DR_SHIFT (0U) +#define USBFSH_HCRHDESCRIPTORB_DR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORB_DR_SHIFT)) & USBFSH_HCRHDESCRIPTORB_DR_MASK) +#define USBFSH_HCRHDESCRIPTORB_PPCM_MASK (0xFFFF0000U) +#define USBFSH_HCRHDESCRIPTORB_PPCM_SHIFT (16U) +#define USBFSH_HCRHDESCRIPTORB_PPCM(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORB_PPCM_SHIFT)) & USBFSH_HCRHDESCRIPTORB_PPCM_MASK) +/*! @} */ + +/*! @name HCRHSTATUS - This register is divided into two parts */ +/*! @{ */ +#define USBFSH_HCRHSTATUS_LPS_MASK (0x1U) +#define USBFSH_HCRHSTATUS_LPS_SHIFT (0U) +#define USBFSH_HCRHSTATUS_LPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_LPS_SHIFT)) & USBFSH_HCRHSTATUS_LPS_MASK) +#define USBFSH_HCRHSTATUS_OCI_MASK (0x2U) +#define USBFSH_HCRHSTATUS_OCI_SHIFT (1U) +#define USBFSH_HCRHSTATUS_OCI(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_OCI_SHIFT)) & USBFSH_HCRHSTATUS_OCI_MASK) +#define USBFSH_HCRHSTATUS_DRWE_MASK (0x8000U) +#define USBFSH_HCRHSTATUS_DRWE_SHIFT (15U) +#define USBFSH_HCRHSTATUS_DRWE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_DRWE_SHIFT)) & USBFSH_HCRHSTATUS_DRWE_MASK) +#define USBFSH_HCRHSTATUS_LPSC_MASK (0x10000U) +#define USBFSH_HCRHSTATUS_LPSC_SHIFT (16U) +#define USBFSH_HCRHSTATUS_LPSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_LPSC_SHIFT)) & USBFSH_HCRHSTATUS_LPSC_MASK) +#define USBFSH_HCRHSTATUS_OCIC_MASK (0x20000U) +#define USBFSH_HCRHSTATUS_OCIC_SHIFT (17U) +#define USBFSH_HCRHSTATUS_OCIC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_OCIC_SHIFT)) & USBFSH_HCRHSTATUS_OCIC_MASK) +#define USBFSH_HCRHSTATUS_CRWE_MASK (0x80000000U) +#define USBFSH_HCRHSTATUS_CRWE_SHIFT (31U) +#define USBFSH_HCRHSTATUS_CRWE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_CRWE_SHIFT)) & USBFSH_HCRHSTATUS_CRWE_MASK) +/*! @} */ + +/*! @name HCRHPORTSTATUS - Controls and reports the port events on a per-port basis */ +/*! @{ */ +#define USBFSH_HCRHPORTSTATUS_CCS_MASK (0x1U) +#define USBFSH_HCRHPORTSTATUS_CCS_SHIFT (0U) +#define USBFSH_HCRHPORTSTATUS_CCS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_CCS_SHIFT)) & USBFSH_HCRHPORTSTATUS_CCS_MASK) +#define USBFSH_HCRHPORTSTATUS_PES_MASK (0x2U) +#define USBFSH_HCRHPORTSTATUS_PES_SHIFT (1U) +#define USBFSH_HCRHPORTSTATUS_PES(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PES_SHIFT)) & USBFSH_HCRHPORTSTATUS_PES_MASK) +#define USBFSH_HCRHPORTSTATUS_PSS_MASK (0x4U) +#define USBFSH_HCRHPORTSTATUS_PSS_SHIFT (2U) +#define USBFSH_HCRHPORTSTATUS_PSS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PSS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PSS_MASK) +#define USBFSH_HCRHPORTSTATUS_POCI_MASK (0x8U) +#define USBFSH_HCRHPORTSTATUS_POCI_SHIFT (3U) +#define USBFSH_HCRHPORTSTATUS_POCI(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_POCI_SHIFT)) & USBFSH_HCRHPORTSTATUS_POCI_MASK) +#define USBFSH_HCRHPORTSTATUS_PRS_MASK (0x10U) +#define USBFSH_HCRHPORTSTATUS_PRS_SHIFT (4U) +#define USBFSH_HCRHPORTSTATUS_PRS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PRS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PRS_MASK) +#define USBFSH_HCRHPORTSTATUS_PPS_MASK (0x100U) +#define USBFSH_HCRHPORTSTATUS_PPS_SHIFT (8U) +#define USBFSH_HCRHPORTSTATUS_PPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PPS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PPS_MASK) +#define USBFSH_HCRHPORTSTATUS_LSDA_MASK (0x200U) +#define USBFSH_HCRHPORTSTATUS_LSDA_SHIFT (9U) +#define USBFSH_HCRHPORTSTATUS_LSDA(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_LSDA_SHIFT)) & USBFSH_HCRHPORTSTATUS_LSDA_MASK) +#define USBFSH_HCRHPORTSTATUS_CSC_MASK (0x10000U) +#define USBFSH_HCRHPORTSTATUS_CSC_SHIFT (16U) +#define USBFSH_HCRHPORTSTATUS_CSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_CSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_CSC_MASK) +#define USBFSH_HCRHPORTSTATUS_PESC_MASK (0x20000U) +#define USBFSH_HCRHPORTSTATUS_PESC_SHIFT (17U) +#define USBFSH_HCRHPORTSTATUS_PESC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PESC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PESC_MASK) +#define USBFSH_HCRHPORTSTATUS_PSSC_MASK (0x40000U) +#define USBFSH_HCRHPORTSTATUS_PSSC_SHIFT (18U) +#define USBFSH_HCRHPORTSTATUS_PSSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PSSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PSSC_MASK) +#define USBFSH_HCRHPORTSTATUS_OCIC_MASK (0x80000U) +#define USBFSH_HCRHPORTSTATUS_OCIC_SHIFT (19U) +#define USBFSH_HCRHPORTSTATUS_OCIC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_OCIC_SHIFT)) & USBFSH_HCRHPORTSTATUS_OCIC_MASK) +#define USBFSH_HCRHPORTSTATUS_PRSC_MASK (0x100000U) +#define USBFSH_HCRHPORTSTATUS_PRSC_SHIFT (20U) +#define USBFSH_HCRHPORTSTATUS_PRSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PRSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PRSC_MASK) +/*! @} */ + +/*! @name PORTMODE - Controls the port if it is attached to the host block or the device block */ +/*! @{ */ +#define USBFSH_PORTMODE_ID_MASK (0x1U) +#define USBFSH_PORTMODE_ID_SHIFT (0U) +#define USBFSH_PORTMODE_ID(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_ID_SHIFT)) & USBFSH_PORTMODE_ID_MASK) +#define USBFSH_PORTMODE_ID_EN_MASK (0x100U) +#define USBFSH_PORTMODE_ID_EN_SHIFT (8U) +#define USBFSH_PORTMODE_ID_EN(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_ID_EN_SHIFT)) & USBFSH_PORTMODE_ID_EN_MASK) +#define USBFSH_PORTMODE_DEV_ENABLE_MASK (0x10000U) +#define USBFSH_PORTMODE_DEV_ENABLE_SHIFT (16U) +#define USBFSH_PORTMODE_DEV_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_DEV_ENABLE_SHIFT)) & USBFSH_PORTMODE_DEV_ENABLE_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group USBFSH_Register_Masks */ + + +/* USBFSH - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral USBFSH base address */ + #define USBFSH_BASE (0x500A2000u) + /** Peripheral USBFSH base address */ + #define USBFSH_BASE_NS (0x400A2000u) + /** Peripheral USBFSH base pointer */ + #define USBFSH ((USBFSH_Type *)USBFSH_BASE) + /** Peripheral USBFSH base pointer */ + #define USBFSH_NS ((USBFSH_Type *)USBFSH_BASE_NS) + /** Array initializer of USBFSH peripheral base addresses */ + #define USBFSH_BASE_ADDRS { USBFSH_BASE } + /** Array initializer of USBFSH peripheral base pointers */ + #define USBFSH_BASE_PTRS { USBFSH } + /** Array initializer of USBFSH peripheral base addresses */ + #define USBFSH_BASE_ADDRS_NS { USBFSH_BASE_NS } + /** Array initializer of USBFSH peripheral base pointers */ + #define USBFSH_BASE_PTRS_NS { USBFSH_NS } +#else + /** Peripheral USBFSH base address */ + #define USBFSH_BASE (0x400A2000u) + /** Peripheral USBFSH base pointer */ + #define USBFSH ((USBFSH_Type *)USBFSH_BASE) + /** Array initializer of USBFSH peripheral base addresses */ + #define USBFSH_BASE_ADDRS { USBFSH_BASE } + /** Array initializer of USBFSH peripheral base pointers */ + #define USBFSH_BASE_PTRS { USBFSH } +#endif +/** Interrupt vectors for the USBFSH peripheral type */ +#define USBFSH_IRQS { USB0_IRQn } +#define USBFSH_NEEDCLK_IRQS { USB0_NEEDCLK_IRQn } + +/*! + * @} + */ /* end of group USBFSH_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USBHSD Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBHSD_Peripheral_Access_Layer USBHSD Peripheral Access Layer + * @{ + */ + +/** USBHSD - Register Layout Typedef */ +typedef struct { + __IO uint32_t DEVCMDSTAT; /**< USB Device Command/Status register, offset: 0x0 */ + __I uint32_t INFO; /**< USB Info register, offset: 0x4 */ + __IO uint32_t EPLISTSTART; /**< USB EP Command/Status List start address, offset: 0x8 */ + __IO uint32_t DATABUFSTART; /**< USB Data buffer start address, offset: 0xC */ + __IO uint32_t LPM; /**< USB Link Power Management register, offset: 0x10 */ + __IO uint32_t EPSKIP; /**< USB Endpoint skip, offset: 0x14 */ + __IO uint32_t EPINUSE; /**< USB Endpoint Buffer in use, offset: 0x18 */ + __IO uint32_t EPBUFCFG; /**< USB Endpoint Buffer Configuration register, offset: 0x1C */ + __IO uint32_t INTSTAT; /**< USB interrupt status register, offset: 0x20 */ + __IO uint32_t INTEN; /**< USB interrupt enable register, offset: 0x24 */ + __IO uint32_t INTSETSTAT; /**< USB set interrupt status register, offset: 0x28 */ + uint8_t RESERVED_0[8]; + __I uint32_t EPTOGGLE; /**< USB Endpoint toggle register, offset: 0x34 */ + uint8_t RESERVED_1[4]; + __IO uint32_t ULPIDEBUG; /**< UTMI/ULPI debug register, offset: 0x3C */ +} USBHSD_Type; + +/* ---------------------------------------------------------------------------- + -- USBHSD Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBHSD_Register_Masks USBHSD Register Masks + * @{ + */ + +/*! @name DEVCMDSTAT - USB Device Command/Status register */ +/*! @{ */ +#define USBHSD_DEVCMDSTAT_DEV_ADDR_MASK (0x7FU) +#define USBHSD_DEVCMDSTAT_DEV_ADDR_SHIFT (0U) +#define USBHSD_DEVCMDSTAT_DEV_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DEV_ADDR_SHIFT)) & USBHSD_DEVCMDSTAT_DEV_ADDR_MASK) +#define USBHSD_DEVCMDSTAT_DEV_EN_MASK (0x80U) +#define USBHSD_DEVCMDSTAT_DEV_EN_SHIFT (7U) +#define USBHSD_DEVCMDSTAT_DEV_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DEV_EN_SHIFT)) & USBHSD_DEVCMDSTAT_DEV_EN_MASK) +#define USBHSD_DEVCMDSTAT_SETUP_MASK (0x100U) +#define USBHSD_DEVCMDSTAT_SETUP_SHIFT (8U) +#define USBHSD_DEVCMDSTAT_SETUP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_SETUP_SHIFT)) & USBHSD_DEVCMDSTAT_SETUP_MASK) +#define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_MASK (0x200U) +#define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT (9U) +#define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT)) & USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_MASK) +#define USBHSD_DEVCMDSTAT_FORCE_VBUS_MASK (0x400U) +#define USBHSD_DEVCMDSTAT_FORCE_VBUS_SHIFT (10U) +#define USBHSD_DEVCMDSTAT_FORCE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_FORCE_VBUS_SHIFT)) & USBHSD_DEVCMDSTAT_FORCE_VBUS_MASK) +#define USBHSD_DEVCMDSTAT_LPM_SUP_MASK (0x800U) +#define USBHSD_DEVCMDSTAT_LPM_SUP_SHIFT (11U) +#define USBHSD_DEVCMDSTAT_LPM_SUP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_SUP_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_SUP_MASK) +#define USBHSD_DEVCMDSTAT_INTONNAK_AO_MASK (0x1000U) +#define USBHSD_DEVCMDSTAT_INTONNAK_AO_SHIFT (12U) +#define USBHSD_DEVCMDSTAT_INTONNAK_AO(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_AO_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_AO_MASK) +#define USBHSD_DEVCMDSTAT_INTONNAK_AI_MASK (0x2000U) +#define USBHSD_DEVCMDSTAT_INTONNAK_AI_SHIFT (13U) +#define USBHSD_DEVCMDSTAT_INTONNAK_AI(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_AI_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_AI_MASK) +#define USBHSD_DEVCMDSTAT_INTONNAK_CO_MASK (0x4000U) +#define USBHSD_DEVCMDSTAT_INTONNAK_CO_SHIFT (14U) +#define USBHSD_DEVCMDSTAT_INTONNAK_CO(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_CO_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_CO_MASK) +#define USBHSD_DEVCMDSTAT_INTONNAK_CI_MASK (0x8000U) +#define USBHSD_DEVCMDSTAT_INTONNAK_CI_SHIFT (15U) +#define USBHSD_DEVCMDSTAT_INTONNAK_CI(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_CI_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_CI_MASK) +#define USBHSD_DEVCMDSTAT_DCON_MASK (0x10000U) +#define USBHSD_DEVCMDSTAT_DCON_SHIFT (16U) +#define USBHSD_DEVCMDSTAT_DCON(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DCON_SHIFT)) & USBHSD_DEVCMDSTAT_DCON_MASK) +#define USBHSD_DEVCMDSTAT_DSUS_MASK (0x20000U) +#define USBHSD_DEVCMDSTAT_DSUS_SHIFT (17U) +#define USBHSD_DEVCMDSTAT_DSUS(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DSUS_SHIFT)) & USBHSD_DEVCMDSTAT_DSUS_MASK) +#define USBHSD_DEVCMDSTAT_LPM_SUS_MASK (0x80000U) +#define USBHSD_DEVCMDSTAT_LPM_SUS_SHIFT (19U) +#define USBHSD_DEVCMDSTAT_LPM_SUS(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_SUS_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_SUS_MASK) +#define USBHSD_DEVCMDSTAT_LPM_REWP_MASK (0x100000U) +#define USBHSD_DEVCMDSTAT_LPM_REWP_SHIFT (20U) +#define USBHSD_DEVCMDSTAT_LPM_REWP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_REWP_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_REWP_MASK) +#define USBHSD_DEVCMDSTAT_Speed_MASK (0xC00000U) +#define USBHSD_DEVCMDSTAT_Speed_SHIFT (22U) +#define USBHSD_DEVCMDSTAT_Speed(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_Speed_SHIFT)) & USBHSD_DEVCMDSTAT_Speed_MASK) +#define USBHSD_DEVCMDSTAT_DCON_C_MASK (0x1000000U) +#define USBHSD_DEVCMDSTAT_DCON_C_SHIFT (24U) +#define USBHSD_DEVCMDSTAT_DCON_C(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DCON_C_SHIFT)) & USBHSD_DEVCMDSTAT_DCON_C_MASK) +#define USBHSD_DEVCMDSTAT_DSUS_C_MASK (0x2000000U) +#define USBHSD_DEVCMDSTAT_DSUS_C_SHIFT (25U) +#define USBHSD_DEVCMDSTAT_DSUS_C(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DSUS_C_SHIFT)) & USBHSD_DEVCMDSTAT_DSUS_C_MASK) +#define USBHSD_DEVCMDSTAT_DRES_C_MASK (0x4000000U) +#define USBHSD_DEVCMDSTAT_DRES_C_SHIFT (26U) +#define USBHSD_DEVCMDSTAT_DRES_C(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DRES_C_SHIFT)) & USBHSD_DEVCMDSTAT_DRES_C_MASK) +#define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_MASK (0x10000000U) +#define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_SHIFT (28U) +#define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_SHIFT)) & USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_MASK) +#define USBHSD_DEVCMDSTAT_PHY_TEST_MODE_MASK (0xE0000000U) +#define USBHSD_DEVCMDSTAT_PHY_TEST_MODE_SHIFT (29U) +#define USBHSD_DEVCMDSTAT_PHY_TEST_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_PHY_TEST_MODE_SHIFT)) & USBHSD_DEVCMDSTAT_PHY_TEST_MODE_MASK) +/*! @} */ + +/*! @name INFO - USB Info register */ +/*! @{ */ +#define USBHSD_INFO_FRAME_NR_MASK (0x7FFU) +#define USBHSD_INFO_FRAME_NR_SHIFT (0U) +#define USBHSD_INFO_FRAME_NR(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_FRAME_NR_SHIFT)) & USBHSD_INFO_FRAME_NR_MASK) +#define USBHSD_INFO_ERR_CODE_MASK (0x7800U) +#define USBHSD_INFO_ERR_CODE_SHIFT (11U) +#define USBHSD_INFO_ERR_CODE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_ERR_CODE_SHIFT)) & USBHSD_INFO_ERR_CODE_MASK) +#define USBHSD_INFO_Minrev_MASK (0xFF0000U) +#define USBHSD_INFO_Minrev_SHIFT (16U) +#define USBHSD_INFO_Minrev(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_Minrev_SHIFT)) & USBHSD_INFO_Minrev_MASK) +#define USBHSD_INFO_Majrev_MASK (0xFF000000U) +#define USBHSD_INFO_Majrev_SHIFT (24U) +#define USBHSD_INFO_Majrev(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_Majrev_SHIFT)) & USBHSD_INFO_Majrev_MASK) +/*! @} */ + +/*! @name EPLISTSTART - USB EP Command/Status List start address */ +/*! @{ */ +#define USBHSD_EPLISTSTART_EP_LIST_PRG_MASK (0xFFF00U) +#define USBHSD_EPLISTSTART_EP_LIST_PRG_SHIFT (8U) +#define USBHSD_EPLISTSTART_EP_LIST_PRG(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPLISTSTART_EP_LIST_PRG_SHIFT)) & USBHSD_EPLISTSTART_EP_LIST_PRG_MASK) +#define USBHSD_EPLISTSTART_EP_LIST_FIXED_MASK (0xFFF00000U) +#define USBHSD_EPLISTSTART_EP_LIST_FIXED_SHIFT (20U) +#define USBHSD_EPLISTSTART_EP_LIST_FIXED(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPLISTSTART_EP_LIST_FIXED_SHIFT)) & USBHSD_EPLISTSTART_EP_LIST_FIXED_MASK) +/*! @} */ + +/*! @name DATABUFSTART - USB Data buffer start address */ +/*! @{ */ +#define USBHSD_DATABUFSTART_DA_BUF_MASK (0xFFFFFFFFU) +#define USBHSD_DATABUFSTART_DA_BUF_SHIFT (0U) +#define USBHSD_DATABUFSTART_DA_BUF(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DATABUFSTART_DA_BUF_SHIFT)) & USBHSD_DATABUFSTART_DA_BUF_MASK) +/*! @} */ + +/*! @name LPM - USB Link Power Management register */ +/*! @{ */ +#define USBHSD_LPM_HIRD_HW_MASK (0xFU) +#define USBHSD_LPM_HIRD_HW_SHIFT (0U) +#define USBHSD_LPM_HIRD_HW(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_HIRD_HW_SHIFT)) & USBHSD_LPM_HIRD_HW_MASK) +#define USBHSD_LPM_HIRD_SW_MASK (0xF0U) +#define USBHSD_LPM_HIRD_SW_SHIFT (4U) +#define USBHSD_LPM_HIRD_SW(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_HIRD_SW_SHIFT)) & USBHSD_LPM_HIRD_SW_MASK) +#define USBHSD_LPM_DATA_PENDING_MASK (0x100U) +#define USBHSD_LPM_DATA_PENDING_SHIFT (8U) +#define USBHSD_LPM_DATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_DATA_PENDING_SHIFT)) & USBHSD_LPM_DATA_PENDING_MASK) +/*! @} */ + +/*! @name EPSKIP - USB Endpoint skip */ +/*! @{ */ +#define USBHSD_EPSKIP_SKIP_MASK (0xFFFU) +#define USBHSD_EPSKIP_SKIP_SHIFT (0U) +#define USBHSD_EPSKIP_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPSKIP_SKIP_SHIFT)) & USBHSD_EPSKIP_SKIP_MASK) +/*! @} */ + +/*! @name EPINUSE - USB Endpoint Buffer in use */ +/*! @{ */ +#define USBHSD_EPINUSE_BUF_MASK (0xFFCU) +#define USBHSD_EPINUSE_BUF_SHIFT (2U) +#define USBHSD_EPINUSE_BUF(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPINUSE_BUF_SHIFT)) & USBHSD_EPINUSE_BUF_MASK) +/*! @} */ + +/*! @name EPBUFCFG - USB Endpoint Buffer Configuration register */ +/*! @{ */ +#define USBHSD_EPBUFCFG_BUF_SB_MASK (0xFFCU) +#define USBHSD_EPBUFCFG_BUF_SB_SHIFT (2U) +#define USBHSD_EPBUFCFG_BUF_SB(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPBUFCFG_BUF_SB_SHIFT)) & USBHSD_EPBUFCFG_BUF_SB_MASK) +/*! @} */ + +/*! @name INTSTAT - USB interrupt status register */ +/*! @{ */ +#define USBHSD_INTSTAT_EP0OUT_MASK (0x1U) +#define USBHSD_INTSTAT_EP0OUT_SHIFT (0U) +#define USBHSD_INTSTAT_EP0OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP0OUT_SHIFT)) & USBHSD_INTSTAT_EP0OUT_MASK) +#define USBHSD_INTSTAT_EP0IN_MASK (0x2U) +#define USBHSD_INTSTAT_EP0IN_SHIFT (1U) +#define USBHSD_INTSTAT_EP0IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP0IN_SHIFT)) & USBHSD_INTSTAT_EP0IN_MASK) +#define USBHSD_INTSTAT_EP1OUT_MASK (0x4U) +#define USBHSD_INTSTAT_EP1OUT_SHIFT (2U) +#define USBHSD_INTSTAT_EP1OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP1OUT_SHIFT)) & USBHSD_INTSTAT_EP1OUT_MASK) +#define USBHSD_INTSTAT_EP1IN_MASK (0x8U) +#define USBHSD_INTSTAT_EP1IN_SHIFT (3U) +#define USBHSD_INTSTAT_EP1IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP1IN_SHIFT)) & USBHSD_INTSTAT_EP1IN_MASK) +#define USBHSD_INTSTAT_EP2OUT_MASK (0x10U) +#define USBHSD_INTSTAT_EP2OUT_SHIFT (4U) +#define USBHSD_INTSTAT_EP2OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP2OUT_SHIFT)) & USBHSD_INTSTAT_EP2OUT_MASK) +#define USBHSD_INTSTAT_EP2IN_MASK (0x20U) +#define USBHSD_INTSTAT_EP2IN_SHIFT (5U) +#define USBHSD_INTSTAT_EP2IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP2IN_SHIFT)) & USBHSD_INTSTAT_EP2IN_MASK) +#define USBHSD_INTSTAT_EP3OUT_MASK (0x40U) +#define USBHSD_INTSTAT_EP3OUT_SHIFT (6U) +#define USBHSD_INTSTAT_EP3OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP3OUT_SHIFT)) & USBHSD_INTSTAT_EP3OUT_MASK) +#define USBHSD_INTSTAT_EP3IN_MASK (0x80U) +#define USBHSD_INTSTAT_EP3IN_SHIFT (7U) +#define USBHSD_INTSTAT_EP3IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP3IN_SHIFT)) & USBHSD_INTSTAT_EP3IN_MASK) +#define USBHSD_INTSTAT_EP4OUT_MASK (0x100U) +#define USBHSD_INTSTAT_EP4OUT_SHIFT (8U) +#define USBHSD_INTSTAT_EP4OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP4OUT_SHIFT)) & USBHSD_INTSTAT_EP4OUT_MASK) +#define USBHSD_INTSTAT_EP4IN_MASK (0x200U) +#define USBHSD_INTSTAT_EP4IN_SHIFT (9U) +#define USBHSD_INTSTAT_EP4IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP4IN_SHIFT)) & USBHSD_INTSTAT_EP4IN_MASK) +#define USBHSD_INTSTAT_EP5OUT_MASK (0x400U) +#define USBHSD_INTSTAT_EP5OUT_SHIFT (10U) +#define USBHSD_INTSTAT_EP5OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP5OUT_SHIFT)) & USBHSD_INTSTAT_EP5OUT_MASK) +#define USBHSD_INTSTAT_EP5IN_MASK (0x800U) +#define USBHSD_INTSTAT_EP5IN_SHIFT (11U) +#define USBHSD_INTSTAT_EP5IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP5IN_SHIFT)) & USBHSD_INTSTAT_EP5IN_MASK) +#define USBHSD_INTSTAT_FRAME_INT_MASK (0x40000000U) +#define USBHSD_INTSTAT_FRAME_INT_SHIFT (30U) +#define USBHSD_INTSTAT_FRAME_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_FRAME_INT_SHIFT)) & USBHSD_INTSTAT_FRAME_INT_MASK) +#define USBHSD_INTSTAT_DEV_INT_MASK (0x80000000U) +#define USBHSD_INTSTAT_DEV_INT_SHIFT (31U) +#define USBHSD_INTSTAT_DEV_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_DEV_INT_SHIFT)) & USBHSD_INTSTAT_DEV_INT_MASK) +/*! @} */ + +/*! @name INTEN - USB interrupt enable register */ +/*! @{ */ +#define USBHSD_INTEN_EP_INT_EN_MASK (0xFFFU) +#define USBHSD_INTEN_EP_INT_EN_SHIFT (0U) +#define USBHSD_INTEN_EP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_EP_INT_EN_SHIFT)) & USBHSD_INTEN_EP_INT_EN_MASK) +#define USBHSD_INTEN_FRAME_INT_EN_MASK (0x40000000U) +#define USBHSD_INTEN_FRAME_INT_EN_SHIFT (30U) +#define USBHSD_INTEN_FRAME_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_FRAME_INT_EN_SHIFT)) & USBHSD_INTEN_FRAME_INT_EN_MASK) +#define USBHSD_INTEN_DEV_INT_EN_MASK (0x80000000U) +#define USBHSD_INTEN_DEV_INT_EN_SHIFT (31U) +#define USBHSD_INTEN_DEV_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_DEV_INT_EN_SHIFT)) & USBHSD_INTEN_DEV_INT_EN_MASK) +/*! @} */ + +/*! @name INTSETSTAT - USB set interrupt status register */ +/*! @{ */ +#define USBHSD_INTSETSTAT_EP_SET_INT_MASK (0xFFFU) +#define USBHSD_INTSETSTAT_EP_SET_INT_SHIFT (0U) +#define USBHSD_INTSETSTAT_EP_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_EP_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_EP_SET_INT_MASK) +#define USBHSD_INTSETSTAT_FRAME_SET_INT_MASK (0x40000000U) +#define USBHSD_INTSETSTAT_FRAME_SET_INT_SHIFT (30U) +#define USBHSD_INTSETSTAT_FRAME_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_FRAME_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_FRAME_SET_INT_MASK) +#define USBHSD_INTSETSTAT_DEV_SET_INT_MASK (0x80000000U) +#define USBHSD_INTSETSTAT_DEV_SET_INT_SHIFT (31U) +#define USBHSD_INTSETSTAT_DEV_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_DEV_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_DEV_SET_INT_MASK) +/*! @} */ + +/*! @name EPTOGGLE - USB Endpoint toggle register */ +/*! @{ */ +#define USBHSD_EPTOGGLE_TOGGLE_MASK (0x3FFFFFFFU) +#define USBHSD_EPTOGGLE_TOGGLE_SHIFT (0U) +#define USBHSD_EPTOGGLE_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPTOGGLE_TOGGLE_SHIFT)) & USBHSD_EPTOGGLE_TOGGLE_MASK) +/*! @} */ + +/*! @name ULPIDEBUG - UTMI/ULPI debug register */ +/*! @{ */ +#define USBHSD_ULPIDEBUG_PHY_ADDR_MASK (0xFFU) +#define USBHSD_ULPIDEBUG_PHY_ADDR_SHIFT (0U) +#define USBHSD_ULPIDEBUG_PHY_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_ADDR_SHIFT)) & USBHSD_ULPIDEBUG_PHY_ADDR_MASK) +#define USBHSD_ULPIDEBUG_PHY_WDATA_MASK (0xFF00U) +#define USBHSD_ULPIDEBUG_PHY_WDATA_SHIFT (8U) +#define USBHSD_ULPIDEBUG_PHY_WDATA(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_WDATA_SHIFT)) & USBHSD_ULPIDEBUG_PHY_WDATA_MASK) +#define USBHSD_ULPIDEBUG_PHY_RDATA_MASK (0xFF0000U) +#define USBHSD_ULPIDEBUG_PHY_RDATA_SHIFT (16U) +#define USBHSD_ULPIDEBUG_PHY_RDATA(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_RDATA_SHIFT)) & USBHSD_ULPIDEBUG_PHY_RDATA_MASK) +#define USBHSD_ULPIDEBUG_PHY_RW_MASK (0x1000000U) +#define USBHSD_ULPIDEBUG_PHY_RW_SHIFT (24U) +#define USBHSD_ULPIDEBUG_PHY_RW(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_RW_SHIFT)) & USBHSD_ULPIDEBUG_PHY_RW_MASK) +#define USBHSD_ULPIDEBUG_PHY_ACCESS_MASK (0x2000000U) +#define USBHSD_ULPIDEBUG_PHY_ACCESS_SHIFT (25U) +#define USBHSD_ULPIDEBUG_PHY_ACCESS(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_ACCESS_SHIFT)) & USBHSD_ULPIDEBUG_PHY_ACCESS_MASK) +#define USBHSD_ULPIDEBUG_PHY_MODE_MASK (0x80000000U) +#define USBHSD_ULPIDEBUG_PHY_MODE_SHIFT (31U) +#define USBHSD_ULPIDEBUG_PHY_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_MODE_SHIFT)) & USBHSD_ULPIDEBUG_PHY_MODE_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group USBHSD_Register_Masks */ + + +/* USBHSD - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral USBHSD base address */ + #define USBHSD_BASE (0x50094000u) + /** Peripheral USBHSD base address */ + #define USBHSD_BASE_NS (0x40094000u) + /** Peripheral USBHSD base pointer */ + #define USBHSD ((USBHSD_Type *)USBHSD_BASE) + /** Peripheral USBHSD base pointer */ + #define USBHSD_NS ((USBHSD_Type *)USBHSD_BASE_NS) + /** Array initializer of USBHSD peripheral base addresses */ + #define USBHSD_BASE_ADDRS { USBHSD_BASE } + /** Array initializer of USBHSD peripheral base pointers */ + #define USBHSD_BASE_PTRS { USBHSD } + /** Array initializer of USBHSD peripheral base addresses */ + #define USBHSD_BASE_ADDRS_NS { USBHSD_BASE_NS } + /** Array initializer of USBHSD peripheral base pointers */ + #define USBHSD_BASE_PTRS_NS { USBHSD_NS } +#else + /** Peripheral USBHSD base address */ + #define USBHSD_BASE (0x40094000u) + /** Peripheral USBHSD base pointer */ + #define USBHSD ((USBHSD_Type *)USBHSD_BASE) + /** Array initializer of USBHSD peripheral base addresses */ + #define USBHSD_BASE_ADDRS { USBHSD_BASE } + /** Array initializer of USBHSD peripheral base pointers */ + #define USBHSD_BASE_PTRS { USBHSD } +#endif +/** Interrupt vectors for the USBHSD peripheral type */ +#define USBHSD_IRQS { USB1_IRQn } +#define USBHSD_NEEDCLK_IRQS { USB1_NEEDCLK_IRQn } + +/*! + * @} + */ /* end of group USBHSD_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USBHSH Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBHSH_Peripheral_Access_Layer USBHSH Peripheral Access Layer + * @{ + */ + +/** USBHSH - Register Layout Typedef */ +typedef struct { + __I uint32_t CAPLENGTH_CHIPID; /**< This register contains the offset value towards the start of the operational register space and the version number of the IP block, offset: 0x0 */ + __I uint32_t HCSPARAMS; /**< Host Controller Structural Parameters, offset: 0x4 */ + __I uint32_t HCCPARAMS; /**< Host Controller Capability Parameters, offset: 0x8 */ + __IO uint32_t FLADJ_FRINDEX; /**< Frame Length Adjustment, offset: 0xC */ + __IO uint32_t ATL_PTD_BASE_ADDR; /**< Memory base address where ATL PTD0 is stored, offset: 0x10 */ + __IO uint32_t ISO_PTD_BASE_ADDR; /**< Memory base address where ISO PTD0 is stored, offset: 0x14 */ + __IO uint32_t INT_PTD_BASE_ADDR; /**< Memory base address where INT PTD0 is stored, offset: 0x18 */ + __IO uint32_t DATA_PAYLOAD_BASE_ADDR; /**< Memory base address that indicates the start of the data payload buffers, offset: 0x1C */ + __IO uint32_t USBCMD; /**< USB Command register, offset: 0x20 */ + __IO uint32_t USBSTS; /**< USB Interrupt Status register, offset: 0x24 */ + __IO uint32_t USBINTR; /**< USB Interrupt Enable register, offset: 0x28 */ + __IO uint32_t PORTSC1; /**< Port Status and Control register, offset: 0x2C */ + __IO uint32_t ATL_PTD_DONE_MAP; /**< Done map for each ATL PTD, offset: 0x30 */ + __IO uint32_t ATL_PTD_SKIP_MAP; /**< Skip map for each ATL PTD, offset: 0x34 */ + __IO uint32_t ISO_PTD_DONE_MAP; /**< Done map for each ISO PTD, offset: 0x38 */ + __IO uint32_t ISO_PTD_SKIP_MAP; /**< Skip map for each ISO PTD, offset: 0x3C */ + __IO uint32_t INT_PTD_DONE_MAP; /**< Done map for each INT PTD, offset: 0x40 */ + __IO uint32_t INT_PTD_SKIP_MAP; /**< Skip map for each INT PTD, offset: 0x44 */ + __IO uint32_t LAST_PTD_INUSE; /**< Marks the last PTD in the list for ISO, INT and ATL, offset: 0x48 */ + __IO uint32_t UTMIPLUS_ULPI_DEBUG; /**< Register to read/write registers in the attached USB PHY, offset: 0x4C */ + __IO uint32_t PORTMODE; /**< Controls the port if it is attached to the host block or the device block, offset: 0x50 */ +} USBHSH_Type; + +/* ---------------------------------------------------------------------------- + -- USBHSH Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBHSH_Register_Masks USBHSH Register Masks + * @{ + */ + +/*! @name CAPLENGTH_CHIPID - This register contains the offset value towards the start of the operational register space and the version number of the IP block */ +/*! @{ */ +#define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_MASK (0xFFU) +#define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_SHIFT (0U) +#define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_SHIFT)) & USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_MASK) +#define USBHSH_CAPLENGTH_CHIPID_CHIPID_MASK (0xFFFF0000U) +#define USBHSH_CAPLENGTH_CHIPID_CHIPID_SHIFT (16U) +#define USBHSH_CAPLENGTH_CHIPID_CHIPID(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_CAPLENGTH_CHIPID_CHIPID_SHIFT)) & USBHSH_CAPLENGTH_CHIPID_CHIPID_MASK) +/*! @} */ + +/*! @name HCSPARAMS - Host Controller Structural Parameters */ +/*! @{ */ +#define USBHSH_HCSPARAMS_N_PORTS_MASK (0xFU) +#define USBHSH_HCSPARAMS_N_PORTS_SHIFT (0U) +#define USBHSH_HCSPARAMS_N_PORTS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_N_PORTS_SHIFT)) & USBHSH_HCSPARAMS_N_PORTS_MASK) +#define USBHSH_HCSPARAMS_PPC_MASK (0x10U) +#define USBHSH_HCSPARAMS_PPC_SHIFT (4U) +#define USBHSH_HCSPARAMS_PPC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_PPC_SHIFT)) & USBHSH_HCSPARAMS_PPC_MASK) +#define USBHSH_HCSPARAMS_P_INDICATOR_MASK (0x10000U) +#define USBHSH_HCSPARAMS_P_INDICATOR_SHIFT (16U) +#define USBHSH_HCSPARAMS_P_INDICATOR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_P_INDICATOR_SHIFT)) & USBHSH_HCSPARAMS_P_INDICATOR_MASK) +/*! @} */ + +/*! @name HCCPARAMS - Host Controller Capability Parameters */ +/*! @{ */ +#define USBHSH_HCCPARAMS_LPMC_MASK (0x20000U) +#define USBHSH_HCCPARAMS_LPMC_SHIFT (17U) +#define USBHSH_HCCPARAMS_LPMC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCCPARAMS_LPMC_SHIFT)) & USBHSH_HCCPARAMS_LPMC_MASK) +/*! @} */ + +/*! @name FLADJ_FRINDEX - Frame Length Adjustment */ +/*! @{ */ +#define USBHSH_FLADJ_FRINDEX_FLADJ_MASK (0x3FU) +#define USBHSH_FLADJ_FRINDEX_FLADJ_SHIFT (0U) +#define USBHSH_FLADJ_FRINDEX_FLADJ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_FLADJ_FRINDEX_FLADJ_SHIFT)) & USBHSH_FLADJ_FRINDEX_FLADJ_MASK) +#define USBHSH_FLADJ_FRINDEX_FRINDEX_MASK (0x3FFF0000U) +#define USBHSH_FLADJ_FRINDEX_FRINDEX_SHIFT (16U) +#define USBHSH_FLADJ_FRINDEX_FRINDEX(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_FLADJ_FRINDEX_FRINDEX_SHIFT)) & USBHSH_FLADJ_FRINDEX_FRINDEX_MASK) +/*! @} */ + +/*! @name ATL_PTD_BASE_ADDR - Memory base address where ATL PTD0 is stored */ +/*! @{ */ +#define USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR_MASK (0x1F0U) +#define USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR_SHIFT (4U) +#define USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR_SHIFT)) & USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR_MASK) +#define USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE_MASK (0xFFFFFE00U) +#define USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE_SHIFT (9U) +#define USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE_SHIFT)) & USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE_MASK) +/*! @} */ + +/*! @name ISO_PTD_BASE_ADDR - Memory base address where ISO PTD0 is stored */ +/*! @{ */ +#define USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST_MASK (0x3E0U) +#define USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST_SHIFT (5U) +#define USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST_SHIFT)) & USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST_MASK) +#define USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE_MASK (0xFFFFFC00U) +#define USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE_SHIFT (10U) +#define USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE_SHIFT)) & USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE_MASK) +/*! @} */ + +/*! @name INT_PTD_BASE_ADDR - Memory base address where INT PTD0 is stored */ +/*! @{ */ +#define USBHSH_INT_PTD_BASE_ADDR_INT_FIRST_MASK (0x3E0U) +#define USBHSH_INT_PTD_BASE_ADDR_INT_FIRST_SHIFT (5U) +#define USBHSH_INT_PTD_BASE_ADDR_INT_FIRST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INT_PTD_BASE_ADDR_INT_FIRST_SHIFT)) & USBHSH_INT_PTD_BASE_ADDR_INT_FIRST_MASK) +#define USBHSH_INT_PTD_BASE_ADDR_INT_BASE_MASK (0xFFFFFC00U) +#define USBHSH_INT_PTD_BASE_ADDR_INT_BASE_SHIFT (10U) +#define USBHSH_INT_PTD_BASE_ADDR_INT_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INT_PTD_BASE_ADDR_INT_BASE_SHIFT)) & USBHSH_INT_PTD_BASE_ADDR_INT_BASE_MASK) +/*! @} */ + +/*! @name DATA_PAYLOAD_BASE_ADDR - Memory base address that indicates the start of the data payload buffers */ +/*! @{ */ +#define USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE_MASK (0xFFFF0000U) +#define USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE_SHIFT (16U) +#define USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE_SHIFT)) & USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE_MASK) +/*! @} */ + +/*! @name USBCMD - USB Command register */ +/*! @{ */ +#define USBHSH_USBCMD_RS_MASK (0x1U) +#define USBHSH_USBCMD_RS_SHIFT (0U) +#define USBHSH_USBCMD_RS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_RS_SHIFT)) & USBHSH_USBCMD_RS_MASK) +#define USBHSH_USBCMD_HCRESET_MASK (0x2U) +#define USBHSH_USBCMD_HCRESET_SHIFT (1U) +#define USBHSH_USBCMD_HCRESET(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_HCRESET_SHIFT)) & USBHSH_USBCMD_HCRESET_MASK) +#define USBHSH_USBCMD_FLS_MASK (0xCU) +#define USBHSH_USBCMD_FLS_SHIFT (2U) +#define USBHSH_USBCMD_FLS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_FLS_SHIFT)) & USBHSH_USBCMD_FLS_MASK) +#define USBHSH_USBCMD_LHCR_MASK (0x80U) +#define USBHSH_USBCMD_LHCR_SHIFT (7U) +#define USBHSH_USBCMD_LHCR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_LHCR_SHIFT)) & USBHSH_USBCMD_LHCR_MASK) +#define USBHSH_USBCMD_ATL_EN_MASK (0x100U) +#define USBHSH_USBCMD_ATL_EN_SHIFT (8U) +#define USBHSH_USBCMD_ATL_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_ATL_EN_SHIFT)) & USBHSH_USBCMD_ATL_EN_MASK) +#define USBHSH_USBCMD_ISO_EN_MASK (0x200U) +#define USBHSH_USBCMD_ISO_EN_SHIFT (9U) +#define USBHSH_USBCMD_ISO_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_ISO_EN_SHIFT)) & USBHSH_USBCMD_ISO_EN_MASK) +#define USBHSH_USBCMD_INT_EN_MASK (0x400U) +#define USBHSH_USBCMD_INT_EN_SHIFT (10U) +#define USBHSH_USBCMD_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_INT_EN_SHIFT)) & USBHSH_USBCMD_INT_EN_MASK) +#define USBHSH_USBCMD_HIRD_MASK (0xF000000U) +#define USBHSH_USBCMD_HIRD_SHIFT (24U) +#define USBHSH_USBCMD_HIRD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_HIRD_SHIFT)) & USBHSH_USBCMD_HIRD_MASK) +#define USBHSH_USBCMD_LPM_RWU_MASK (0x10000000U) +#define USBHSH_USBCMD_LPM_RWU_SHIFT (28U) +#define USBHSH_USBCMD_LPM_RWU(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_LPM_RWU_SHIFT)) & USBHSH_USBCMD_LPM_RWU_MASK) +/*! @} */ + +/*! @name USBSTS - USB Interrupt Status register */ +/*! @{ */ +#define USBHSH_USBSTS_PCD_MASK (0x4U) +#define USBHSH_USBSTS_PCD_SHIFT (2U) +#define USBHSH_USBSTS_PCD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_PCD_SHIFT)) & USBHSH_USBSTS_PCD_MASK) +#define USBHSH_USBSTS_FLR_MASK (0x8U) +#define USBHSH_USBSTS_FLR_SHIFT (3U) +#define USBHSH_USBSTS_FLR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_FLR_SHIFT)) & USBHSH_USBSTS_FLR_MASK) +#define USBHSH_USBSTS_ATL_IRQ_MASK (0x10000U) +#define USBHSH_USBSTS_ATL_IRQ_SHIFT (16U) +#define USBHSH_USBSTS_ATL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_ATL_IRQ_SHIFT)) & USBHSH_USBSTS_ATL_IRQ_MASK) +#define USBHSH_USBSTS_ISO_IRQ_MASK (0x20000U) +#define USBHSH_USBSTS_ISO_IRQ_SHIFT (17U) +#define USBHSH_USBSTS_ISO_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_ISO_IRQ_SHIFT)) & USBHSH_USBSTS_ISO_IRQ_MASK) +#define USBHSH_USBSTS_INT_IRQ_MASK (0x40000U) +#define USBHSH_USBSTS_INT_IRQ_SHIFT (18U) +#define USBHSH_USBSTS_INT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_INT_IRQ_SHIFT)) & USBHSH_USBSTS_INT_IRQ_MASK) +#define USBHSH_USBSTS_SOF_IRQ_MASK (0x80000U) +#define USBHSH_USBSTS_SOF_IRQ_SHIFT (19U) +#define USBHSH_USBSTS_SOF_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_SOF_IRQ_SHIFT)) & USBHSH_USBSTS_SOF_IRQ_MASK) +/*! @} */ + +/*! @name USBINTR - USB Interrupt Enable register */ +/*! @{ */ +#define USBHSH_USBINTR_PCDE_MASK (0x4U) +#define USBHSH_USBINTR_PCDE_SHIFT (2U) +#define USBHSH_USBINTR_PCDE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_PCDE_SHIFT)) & USBHSH_USBINTR_PCDE_MASK) +#define USBHSH_USBINTR_FLRE_MASK (0x8U) +#define USBHSH_USBINTR_FLRE_SHIFT (3U) +#define USBHSH_USBINTR_FLRE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_FLRE_SHIFT)) & USBHSH_USBINTR_FLRE_MASK) +#define USBHSH_USBINTR_ATL_IRQ_E_MASK (0x10000U) +#define USBHSH_USBINTR_ATL_IRQ_E_SHIFT (16U) +#define USBHSH_USBINTR_ATL_IRQ_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_ATL_IRQ_E_SHIFT)) & USBHSH_USBINTR_ATL_IRQ_E_MASK) +#define USBHSH_USBINTR_ISO_IRQ_E_MASK (0x20000U) +#define USBHSH_USBINTR_ISO_IRQ_E_SHIFT (17U) +#define USBHSH_USBINTR_ISO_IRQ_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_ISO_IRQ_E_SHIFT)) & USBHSH_USBINTR_ISO_IRQ_E_MASK) +#define USBHSH_USBINTR_INT_IRQ_E_MASK (0x40000U) +#define USBHSH_USBINTR_INT_IRQ_E_SHIFT (18U) +#define USBHSH_USBINTR_INT_IRQ_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_INT_IRQ_E_SHIFT)) & USBHSH_USBINTR_INT_IRQ_E_MASK) +#define USBHSH_USBINTR_SOF_E_MASK (0x80000U) +#define USBHSH_USBINTR_SOF_E_SHIFT (19U) +#define USBHSH_USBINTR_SOF_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_SOF_E_SHIFT)) & USBHSH_USBINTR_SOF_E_MASK) +/*! @} */ + +/*! @name PORTSC1 - Port Status and Control register */ +/*! @{ */ +#define USBHSH_PORTSC1_CCS_MASK (0x1U) +#define USBHSH_PORTSC1_CCS_SHIFT (0U) +#define USBHSH_PORTSC1_CCS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_CCS_SHIFT)) & USBHSH_PORTSC1_CCS_MASK) +#define USBHSH_PORTSC1_CSC_MASK (0x2U) +#define USBHSH_PORTSC1_CSC_SHIFT (1U) +#define USBHSH_PORTSC1_CSC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_CSC_SHIFT)) & USBHSH_PORTSC1_CSC_MASK) +#define USBHSH_PORTSC1_PED_MASK (0x4U) +#define USBHSH_PORTSC1_PED_SHIFT (2U) +#define USBHSH_PORTSC1_PED(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PED_SHIFT)) & USBHSH_PORTSC1_PED_MASK) +#define USBHSH_PORTSC1_PEDC_MASK (0x8U) +#define USBHSH_PORTSC1_PEDC_SHIFT (3U) +#define USBHSH_PORTSC1_PEDC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PEDC_SHIFT)) & USBHSH_PORTSC1_PEDC_MASK) +#define USBHSH_PORTSC1_OCA_MASK (0x10U) +#define USBHSH_PORTSC1_OCA_SHIFT (4U) +#define USBHSH_PORTSC1_OCA(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_OCA_SHIFT)) & USBHSH_PORTSC1_OCA_MASK) +#define USBHSH_PORTSC1_OCC_MASK (0x20U) +#define USBHSH_PORTSC1_OCC_SHIFT (5U) +#define USBHSH_PORTSC1_OCC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_OCC_SHIFT)) & USBHSH_PORTSC1_OCC_MASK) +#define USBHSH_PORTSC1_FPR_MASK (0x40U) +#define USBHSH_PORTSC1_FPR_SHIFT (6U) +#define USBHSH_PORTSC1_FPR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_FPR_SHIFT)) & USBHSH_PORTSC1_FPR_MASK) +#define USBHSH_PORTSC1_SUSP_MASK (0x80U) +#define USBHSH_PORTSC1_SUSP_SHIFT (7U) +#define USBHSH_PORTSC1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_SUSP_SHIFT)) & USBHSH_PORTSC1_SUSP_MASK) +#define USBHSH_PORTSC1_PR_MASK (0x100U) +#define USBHSH_PORTSC1_PR_SHIFT (8U) +#define USBHSH_PORTSC1_PR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PR_SHIFT)) & USBHSH_PORTSC1_PR_MASK) +#define USBHSH_PORTSC1_SUS_L1_MASK (0x200U) +#define USBHSH_PORTSC1_SUS_L1_SHIFT (9U) +#define USBHSH_PORTSC1_SUS_L1(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_SUS_L1_SHIFT)) & USBHSH_PORTSC1_SUS_L1_MASK) +#define USBHSH_PORTSC1_LS_MASK (0xC00U) +#define USBHSH_PORTSC1_LS_SHIFT (10U) +#define USBHSH_PORTSC1_LS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_LS_SHIFT)) & USBHSH_PORTSC1_LS_MASK) +#define USBHSH_PORTSC1_PP_MASK (0x1000U) +#define USBHSH_PORTSC1_PP_SHIFT (12U) +#define USBHSH_PORTSC1_PP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PP_SHIFT)) & USBHSH_PORTSC1_PP_MASK) +#define USBHSH_PORTSC1_PIC_MASK (0xC000U) +#define USBHSH_PORTSC1_PIC_SHIFT (14U) +#define USBHSH_PORTSC1_PIC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PIC_SHIFT)) & USBHSH_PORTSC1_PIC_MASK) +#define USBHSH_PORTSC1_PTC_MASK (0xF0000U) +#define USBHSH_PORTSC1_PTC_SHIFT (16U) +#define USBHSH_PORTSC1_PTC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PTC_SHIFT)) & USBHSH_PORTSC1_PTC_MASK) +#define USBHSH_PORTSC1_PSPD_MASK (0x300000U) +#define USBHSH_PORTSC1_PSPD_SHIFT (20U) +#define USBHSH_PORTSC1_PSPD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PSPD_SHIFT)) & USBHSH_PORTSC1_PSPD_MASK) +#define USBHSH_PORTSC1_WOO_MASK (0x400000U) +#define USBHSH_PORTSC1_WOO_SHIFT (22U) +#define USBHSH_PORTSC1_WOO(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_WOO_SHIFT)) & USBHSH_PORTSC1_WOO_MASK) +#define USBHSH_PORTSC1_SUS_STAT_MASK (0x1800000U) +#define USBHSH_PORTSC1_SUS_STAT_SHIFT (23U) +#define USBHSH_PORTSC1_SUS_STAT(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_SUS_STAT_SHIFT)) & USBHSH_PORTSC1_SUS_STAT_MASK) +#define USBHSH_PORTSC1_DEV_ADD_MASK (0xFE000000U) +#define USBHSH_PORTSC1_DEV_ADD_SHIFT (25U) +#define USBHSH_PORTSC1_DEV_ADD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_DEV_ADD_SHIFT)) & USBHSH_PORTSC1_DEV_ADD_MASK) +/*! @} */ + +/*! @name ATL_PTD_DONE_MAP - Done map for each ATL PTD */ +/*! @{ */ +#define USBHSH_ATL_PTD_DONE_MAP_ATL_DONE_MASK (0xFFFFFFFFU) +#define USBHSH_ATL_PTD_DONE_MAP_ATL_DONE_SHIFT (0U) +#define USBHSH_ATL_PTD_DONE_MAP_ATL_DONE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATL_PTD_DONE_MAP_ATL_DONE_SHIFT)) & USBHSH_ATL_PTD_DONE_MAP_ATL_DONE_MASK) +/*! @} */ + +/*! @name ATL_PTD_SKIP_MAP - Skip map for each ATL PTD */ +/*! @{ */ +#define USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP_MASK (0xFFFFFFFFU) +#define USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP_SHIFT (0U) +#define USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP_SHIFT)) & USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP_MASK) +/*! @} */ + +/*! @name ISO_PTD_DONE_MAP - Done map for each ISO PTD */ +/*! @{ */ +#define USBHSH_ISO_PTD_DONE_MAP_ISO_DONE_MASK (0xFFFFFFFFU) +#define USBHSH_ISO_PTD_DONE_MAP_ISO_DONE_SHIFT (0U) +#define USBHSH_ISO_PTD_DONE_MAP_ISO_DONE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISO_PTD_DONE_MAP_ISO_DONE_SHIFT)) & USBHSH_ISO_PTD_DONE_MAP_ISO_DONE_MASK) +/*! @} */ + +/*! @name ISO_PTD_SKIP_MAP - Skip map for each ISO PTD */ +/*! @{ */ +#define USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP_MASK (0xFFFFFFFFU) +#define USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP_SHIFT (0U) +#define USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP_SHIFT)) & USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP_MASK) +/*! @} */ + +/*! @name INT_PTD_DONE_MAP - Done map for each INT PTD */ +/*! @{ */ +#define USBHSH_INT_PTD_DONE_MAP_INT_DONE_MASK (0xFFFFFFFFU) +#define USBHSH_INT_PTD_DONE_MAP_INT_DONE_SHIFT (0U) +#define USBHSH_INT_PTD_DONE_MAP_INT_DONE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INT_PTD_DONE_MAP_INT_DONE_SHIFT)) & USBHSH_INT_PTD_DONE_MAP_INT_DONE_MASK) +/*! @} */ + +/*! @name INT_PTD_SKIP_MAP - Skip map for each INT PTD */ +/*! @{ */ +#define USBHSH_INT_PTD_SKIP_MAP_INT_SKIP_MASK (0xFFFFFFFFU) +#define USBHSH_INT_PTD_SKIP_MAP_INT_SKIP_SHIFT (0U) +#define USBHSH_INT_PTD_SKIP_MAP_INT_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INT_PTD_SKIP_MAP_INT_SKIP_SHIFT)) & USBHSH_INT_PTD_SKIP_MAP_INT_SKIP_MASK) +/*! @} */ + +/*! @name LAST_PTD_INUSE - Marks the last PTD in the list for ISO, INT and ATL */ +/*! @{ */ +#define USBHSH_LAST_PTD_INUSE_ATL_LAST_MASK (0x1FU) +#define USBHSH_LAST_PTD_INUSE_ATL_LAST_SHIFT (0U) +#define USBHSH_LAST_PTD_INUSE_ATL_LAST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_LAST_PTD_INUSE_ATL_LAST_SHIFT)) & USBHSH_LAST_PTD_INUSE_ATL_LAST_MASK) +#define USBHSH_LAST_PTD_INUSE_ISO_LAST_MASK (0x1F00U) +#define USBHSH_LAST_PTD_INUSE_ISO_LAST_SHIFT (8U) +#define USBHSH_LAST_PTD_INUSE_ISO_LAST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_LAST_PTD_INUSE_ISO_LAST_SHIFT)) & USBHSH_LAST_PTD_INUSE_ISO_LAST_MASK) +#define USBHSH_LAST_PTD_INUSE_INT_LAST_MASK (0x1F0000U) +#define USBHSH_LAST_PTD_INUSE_INT_LAST_SHIFT (16U) +#define USBHSH_LAST_PTD_INUSE_INT_LAST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_LAST_PTD_INUSE_INT_LAST_SHIFT)) & USBHSH_LAST_PTD_INUSE_INT_LAST_MASK) +/*! @} */ + +/*! @name UTMIPLUS_ULPI_DEBUG - Register to read/write registers in the attached USB PHY */ +/*! @{ */ +#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ADDR_MASK (0xFFU) +#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ADDR_SHIFT (0U) +#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ADDR_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ADDR_MASK) +#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_WDATA_MASK (0xFF00U) +#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_WDATA_SHIFT (8U) +#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_WDATA(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_WDATA_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_WDATA_MASK) +#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RDATA_MASK (0xFF0000U) +#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RDATA_SHIFT (16U) +#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RDATA(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RDATA_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RDATA_MASK) +#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RW_MASK (0x1000000U) +#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RW_SHIFT (24U) +#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RW(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RW_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RW_MASK) +#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ACCESS_MASK (0x2000000U) +#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ACCESS_SHIFT (25U) +#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ACCESS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ACCESS_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ACCESS_MASK) +#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_MODE_MASK (0x80000000U) +#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_MODE_SHIFT (31U) +#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_MODE_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_MODE_MASK) +/*! @} */ + +/*! @name PORTMODE - Controls the port if it is attached to the host block or the device block */ +/*! @{ */ +#define USBHSH_PORTMODE_ID0_MASK (0x1U) +#define USBHSH_PORTMODE_ID0_SHIFT (0U) +#define USBHSH_PORTMODE_ID0(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_ID0_SHIFT)) & USBHSH_PORTMODE_ID0_MASK) +#define USBHSH_PORTMODE_ID0_EN_MASK (0x100U) +#define USBHSH_PORTMODE_ID0_EN_SHIFT (8U) +#define USBHSH_PORTMODE_ID0_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_ID0_EN_SHIFT)) & USBHSH_PORTMODE_ID0_EN_MASK) +#define USBHSH_PORTMODE_DEV_ENABLE_MASK (0x10000U) +#define USBHSH_PORTMODE_DEV_ENABLE_SHIFT (16U) +#define USBHSH_PORTMODE_DEV_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_DEV_ENABLE_SHIFT)) & USBHSH_PORTMODE_DEV_ENABLE_MASK) +#define USBHSH_PORTMODE_SW_CTRL_PDCOM_MASK (0x40000U) +#define USBHSH_PORTMODE_SW_CTRL_PDCOM_SHIFT (18U) +#define USBHSH_PORTMODE_SW_CTRL_PDCOM(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_SW_CTRL_PDCOM_SHIFT)) & USBHSH_PORTMODE_SW_CTRL_PDCOM_MASK) +#define USBHSH_PORTMODE_SW_PDCOM_MASK (0x80000U) +#define USBHSH_PORTMODE_SW_PDCOM_SHIFT (19U) +#define USBHSH_PORTMODE_SW_PDCOM(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_SW_PDCOM_SHIFT)) & USBHSH_PORTMODE_SW_PDCOM_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group USBHSH_Register_Masks */ + + +/* USBHSH - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral USBHSH base address */ + #define USBHSH_BASE (0x500A3000u) + /** Peripheral USBHSH base address */ + #define USBHSH_BASE_NS (0x400A3000u) + /** Peripheral USBHSH base pointer */ + #define USBHSH ((USBHSH_Type *)USBHSH_BASE) + /** Peripheral USBHSH base pointer */ + #define USBHSH_NS ((USBHSH_Type *)USBHSH_BASE_NS) + /** Array initializer of USBHSH peripheral base addresses */ + #define USBHSH_BASE_ADDRS { USBHSH_BASE } + /** Array initializer of USBHSH peripheral base pointers */ + #define USBHSH_BASE_PTRS { USBHSH } + /** Array initializer of USBHSH peripheral base addresses */ + #define USBHSH_BASE_ADDRS_NS { USBHSH_BASE_NS } + /** Array initializer of USBHSH peripheral base pointers */ + #define USBHSH_BASE_PTRS_NS { USBHSH_NS } +#else + /** Peripheral USBHSH base address */ + #define USBHSH_BASE (0x400A3000u) + /** Peripheral USBHSH base pointer */ + #define USBHSH ((USBHSH_Type *)USBHSH_BASE) + /** Array initializer of USBHSH peripheral base addresses */ + #define USBHSH_BASE_ADDRS { USBHSH_BASE } + /** Array initializer of USBHSH peripheral base pointers */ + #define USBHSH_BASE_PTRS { USBHSH } +#endif +/** Interrupt vectors for the USBHSH peripheral type */ +#define USBHSH_IRQS { USB1_IRQn } +#define USBHSH_NEEDCLK_IRQS { USB1_NEEDCLK_IRQn } + +/*! + * @} + */ /* end of group USBHSH_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USBPHY Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBPHY_Peripheral_Access_Layer USBPHY Peripheral Access Layer + * @{ + */ + +/** USBPHY - Register Layout Typedef */ +typedef struct { + __IO uint32_t PWD; /**< USB PHY Power-Down Register, offset: 0x0 */ + __IO uint32_t PWD_SET; /**< USB PHY Power-Down Register, offset: 0x4 */ + __IO uint32_t PWD_CLR; /**< USB PHY Power-Down Register, offset: 0x8 */ + __IO uint32_t PWD_TOG; /**< USB PHY Power-Down Register, offset: 0xC */ + __IO uint32_t TX; /**< USB PHY Transmitter Control Register, offset: 0x10 */ + __IO uint32_t TX_SET; /**< USB PHY Transmitter Control Register, offset: 0x14 */ + __IO uint32_t TX_CLR; /**< USB PHY Transmitter Control Register, offset: 0x18 */ + __IO uint32_t TX_TOG; /**< USB PHY Transmitter Control Register, offset: 0x1C */ + __IO uint32_t RX; /**< USB PHY Receiver Control Register, offset: 0x20 */ + __IO uint32_t RX_SET; /**< USB PHY Receiver Control Register, offset: 0x24 */ + __IO uint32_t RX_CLR; /**< USB PHY Receiver Control Register, offset: 0x28 */ + __IO uint32_t RX_TOG; /**< USB PHY Receiver Control Register, offset: 0x2C */ + __IO uint32_t CTRL; /**< USB PHY General Control Register, offset: 0x30 */ + __IO uint32_t CTRL_SET; /**< USB PHY General Control Register, offset: 0x34 */ + __IO uint32_t CTRL_CLR; /**< USB PHY General Control Register, offset: 0x38 */ + __IO uint32_t CTRL_TOG; /**< USB PHY General Control Register, offset: 0x3C */ + __IO uint32_t STATUS; /**< USB PHY Status Register, offset: 0x40 */ + uint8_t RESERVED_0[12]; + __IO uint32_t DEBUG0; /**< USB PHY Debug Register 0, offset: 0x50 */ + __IO uint32_t DEBUG0_SET; /**< USB PHY Debug Register 0, offset: 0x54 */ + __IO uint32_t DEBUG0_CLR; /**< USB PHY Debug Register 0, offset: 0x58 */ + __IO uint32_t DEBUG0_TOG; /**< USB PHY Debug Register 0, offset: 0x5C */ + uint8_t RESERVED_1[16]; + __IO uint32_t DEBUG1; /**< UTMI Debug Status Register 1, offset: 0x70 */ + __IO uint32_t DEBUG1_SET; /**< UTMI Debug Status Register 1, offset: 0x74 */ + __IO uint32_t DEBUG1_CLR; /**< UTMI Debug Status Register 1, offset: 0x78 */ + __IO uint32_t DEBUG1_TOG; /**< UTMI Debug Status Register 1, offset: 0x7C */ + __I uint32_t VERSION; /**< UTMI RTL Version, offset: 0x80 */ + uint8_t RESERVED_2[28]; + __IO uint32_t PLL_SIC; /**< USB PHY PLL Control/Status Register, offset: 0xA0 */ + __IO uint32_t PLL_SIC_SET; /**< USB PHY PLL Control/Status Register, offset: 0xA4 */ + __IO uint32_t PLL_SIC_CLR; /**< USB PHY PLL Control/Status Register, offset: 0xA8 */ + __IO uint32_t PLL_SIC_TOG; /**< USB PHY PLL Control/Status Register, offset: 0xAC */ + uint8_t RESERVED_3[16]; + __IO uint32_t USB1_VBUS_DETECT; /**< USB PHY VBUS Detect Control Register, offset: 0xC0 */ + __IO uint32_t USB1_VBUS_DETECT_SET; /**< USB PHY VBUS Detect Control Register, offset: 0xC4 */ + __IO uint32_t USB1_VBUS_DETECT_CLR; /**< USB PHY VBUS Detect Control Register, offset: 0xC8 */ + __IO uint32_t USB1_VBUS_DETECT_TOG; /**< USB PHY VBUS Detect Control Register, offset: 0xCC */ + __I uint32_t USB1_VBUS_DET_STAT; /**< USB PHY VBUS Detector Status Register, offset: 0xD0 */ + uint8_t RESERVED_4[12]; + __IO uint32_t USB1_CHRG_DETECT; /**< USB PHY Charger Detect Control Register, offset: 0xE0 */ + __IO uint32_t USB1_CHRG_DETECT_SET; /**< USB PHY Charger Detect Control Register, offset: 0xE4 */ + __IO uint32_t USB1_CHRG_DETECT_CLR; /**< USB PHY Charger Detect Control Register, offset: 0xE8 */ + __IO uint32_t USB1_CHRG_DETECT_TOG; /**< USB PHY Charger Detect Control Register, offset: 0xEC */ + __I uint32_t USB1_CHRG_DET_STAT; /**< USB PHY Charger Detect Status Register, offset: 0xF0 */ + uint8_t RESERVED_5[12]; + __IO uint32_t ANACTRLr; /**< USB PHY Analog Control Register, offset: 0x100 */ + __IO uint32_t ANACTRL_SET; /**< USB PHY Analog Control Register, offset: 0x104 */ + __IO uint32_t ANACTRL_CLR; /**< USB PHY Analog Control Register, offset: 0x108 */ + __IO uint32_t ANACTRL_TOG; /**< USB PHY Analog Control Register, offset: 0x10C */ +} USBPHY_Type; + +/* ---------------------------------------------------------------------------- + -- USBPHY Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBPHY_Register_Masks USBPHY Register Masks + * @{ + */ + +/*! @name PWD - USB PHY Power-Down Register */ +/*! @{ */ +#define USBPHY_PWD_TXPWDFS_MASK (0x400U) +#define USBPHY_PWD_TXPWDFS_SHIFT (10U) +/*! TXPWDFS + * 0b0..Normal operation. + * 0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the + */ +#define USBPHY_PWD_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDFS_SHIFT)) & USBPHY_PWD_TXPWDFS_MASK) +#define USBPHY_PWD_TXPWDIBIAS_MASK (0x800U) +#define USBPHY_PWD_TXPWDIBIAS_SHIFT (11U) +/*! TXPWDIBIAS + * 0b0..Normal operation. + * 0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the + */ +#define USBPHY_PWD_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TXPWDIBIAS_MASK) +#define USBPHY_PWD_TXPWDV2I_MASK (0x1000U) +#define USBPHY_PWD_TXPWDV2I_SHIFT (12U) +/*! TXPWDV2I + * 0b0..Normal operation. + * 0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror + */ +#define USBPHY_PWD_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDV2I_SHIFT)) & USBPHY_PWD_TXPWDV2I_MASK) +#define USBPHY_PWD_RXPWDENV_MASK (0x20000U) +#define USBPHY_PWD_RXPWDENV_SHIFT (17U) +/*! RXPWDENV + * 0b0..Normal operation. + * 0b1..Power-down the USB high-speed receiver envelope detector (squelch signal) + */ +#define USBPHY_PWD_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDENV_SHIFT)) & USBPHY_PWD_RXPWDENV_MASK) +#define USBPHY_PWD_RXPWD1PT1_MASK (0x40000U) +#define USBPHY_PWD_RXPWD1PT1_SHIFT (18U) +/*! RXPWD1PT1 + * 0b0..Normal operation. + * 0b1..Power-down the USB full-speed differential receiver. + */ +#define USBPHY_PWD_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWD1PT1_SHIFT)) & USBPHY_PWD_RXPWD1PT1_MASK) +#define USBPHY_PWD_RXPWDDIFF_MASK (0x80000U) +#define USBPHY_PWD_RXPWDDIFF_SHIFT (19U) +/*! RXPWDDIFF + * 0b0..Normal operation. + * 0b1..Power-down the USB high-speed differential receive + */ +#define USBPHY_PWD_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDDIFF_SHIFT)) & USBPHY_PWD_RXPWDDIFF_MASK) +#define USBPHY_PWD_RXPWDRX_MASK (0x100000U) +#define USBPHY_PWD_RXPWDRX_SHIFT (20U) +/*! RXPWDRX + * 0b0..Normal operation. + * 0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver + */ +#define USBPHY_PWD_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDRX_SHIFT)) & USBPHY_PWD_RXPWDRX_MASK) +/*! @} */ + +/*! @name PWD_SET - USB PHY Power-Down Register */ +/*! @{ */ +#define USBPHY_PWD_SET_TXPWDFS_MASK (0x400U) +#define USBPHY_PWD_SET_TXPWDFS_SHIFT (10U) +/*! TXPWDFS + * 0b0..Normal operation. + * 0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the + */ +#define USBPHY_PWD_SET_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDFS_SHIFT)) & USBPHY_PWD_SET_TXPWDFS_MASK) +#define USBPHY_PWD_SET_TXPWDIBIAS_MASK (0x800U) +#define USBPHY_PWD_SET_TXPWDIBIAS_SHIFT (11U) +/*! TXPWDIBIAS + * 0b0..Normal operation. + * 0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the + */ +#define USBPHY_PWD_SET_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_SET_TXPWDIBIAS_MASK) +#define USBPHY_PWD_SET_TXPWDV2I_MASK (0x1000U) +#define USBPHY_PWD_SET_TXPWDV2I_SHIFT (12U) +/*! TXPWDV2I + * 0b0..Normal operation. + * 0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror + */ +#define USBPHY_PWD_SET_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDV2I_SHIFT)) & USBPHY_PWD_SET_TXPWDV2I_MASK) +#define USBPHY_PWD_SET_RXPWDENV_MASK (0x20000U) +#define USBPHY_PWD_SET_RXPWDENV_SHIFT (17U) +/*! RXPWDENV + * 0b0..Normal operation. + * 0b1..Power-down the USB high-speed receiver envelope detector (squelch signal) + */ +#define USBPHY_PWD_SET_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDENV_SHIFT)) & USBPHY_PWD_SET_RXPWDENV_MASK) +#define USBPHY_PWD_SET_RXPWD1PT1_MASK (0x40000U) +#define USBPHY_PWD_SET_RXPWD1PT1_SHIFT (18U) +/*! RXPWD1PT1 + * 0b0..Normal operation. + * 0b1..Power-down the USB full-speed differential receiver. + */ +#define USBPHY_PWD_SET_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWD1PT1_SHIFT)) & USBPHY_PWD_SET_RXPWD1PT1_MASK) +#define USBPHY_PWD_SET_RXPWDDIFF_MASK (0x80000U) +#define USBPHY_PWD_SET_RXPWDDIFF_SHIFT (19U) +/*! RXPWDDIFF + * 0b0..Normal operation. + * 0b1..Power-down the USB high-speed differential receive + */ +#define USBPHY_PWD_SET_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDDIFF_SHIFT)) & USBPHY_PWD_SET_RXPWDDIFF_MASK) +#define USBPHY_PWD_SET_RXPWDRX_MASK (0x100000U) +#define USBPHY_PWD_SET_RXPWDRX_SHIFT (20U) +/*! RXPWDRX + * 0b0..Normal operation. + * 0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver + */ +#define USBPHY_PWD_SET_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDRX_SHIFT)) & USBPHY_PWD_SET_RXPWDRX_MASK) +/*! @} */ + +/*! @name PWD_CLR - USB PHY Power-Down Register */ +/*! @{ */ +#define USBPHY_PWD_CLR_TXPWDFS_MASK (0x400U) +#define USBPHY_PWD_CLR_TXPWDFS_SHIFT (10U) +/*! TXPWDFS + * 0b0..Normal operation. + * 0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the + */ +#define USBPHY_PWD_CLR_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDFS_SHIFT)) & USBPHY_PWD_CLR_TXPWDFS_MASK) +#define USBPHY_PWD_CLR_TXPWDIBIAS_MASK (0x800U) +#define USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT (11U) +/*! TXPWDIBIAS + * 0b0..Normal operation. + * 0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the + */ +#define USBPHY_PWD_CLR_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_CLR_TXPWDIBIAS_MASK) +#define USBPHY_PWD_CLR_TXPWDV2I_MASK (0x1000U) +#define USBPHY_PWD_CLR_TXPWDV2I_SHIFT (12U) +/*! TXPWDV2I + * 0b0..Normal operation. + * 0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror + */ +#define USBPHY_PWD_CLR_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDV2I_SHIFT)) & USBPHY_PWD_CLR_TXPWDV2I_MASK) +#define USBPHY_PWD_CLR_RXPWDENV_MASK (0x20000U) +#define USBPHY_PWD_CLR_RXPWDENV_SHIFT (17U) +/*! RXPWDENV + * 0b0..Normal operation. + * 0b1..Power-down the USB high-speed receiver envelope detector (squelch signal) + */ +#define USBPHY_PWD_CLR_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDENV_SHIFT)) & USBPHY_PWD_CLR_RXPWDENV_MASK) +#define USBPHY_PWD_CLR_RXPWD1PT1_MASK (0x40000U) +#define USBPHY_PWD_CLR_RXPWD1PT1_SHIFT (18U) +/*! RXPWD1PT1 + * 0b0..Normal operation. + * 0b1..Power-down the USB full-speed differential receiver. + */ +#define USBPHY_PWD_CLR_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWD1PT1_SHIFT)) & USBPHY_PWD_CLR_RXPWD1PT1_MASK) +#define USBPHY_PWD_CLR_RXPWDDIFF_MASK (0x80000U) +#define USBPHY_PWD_CLR_RXPWDDIFF_SHIFT (19U) +/*! RXPWDDIFF + * 0b0..Normal operation. + * 0b1..Power-down the USB high-speed differential receive + */ +#define USBPHY_PWD_CLR_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDDIFF_SHIFT)) & USBPHY_PWD_CLR_RXPWDDIFF_MASK) +#define USBPHY_PWD_CLR_RXPWDRX_MASK (0x100000U) +#define USBPHY_PWD_CLR_RXPWDRX_SHIFT (20U) +/*! RXPWDRX + * 0b0..Normal operation. + * 0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver + */ +#define USBPHY_PWD_CLR_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDRX_SHIFT)) & USBPHY_PWD_CLR_RXPWDRX_MASK) +/*! @} */ + +/*! @name PWD_TOG - USB PHY Power-Down Register */ +/*! @{ */ +#define USBPHY_PWD_TOG_TXPWDFS_MASK (0x400U) +#define USBPHY_PWD_TOG_TXPWDFS_SHIFT (10U) +/*! TXPWDFS + * 0b0..Normal operation. + * 0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the + */ +#define USBPHY_PWD_TOG_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDFS_SHIFT)) & USBPHY_PWD_TOG_TXPWDFS_MASK) +#define USBPHY_PWD_TOG_TXPWDIBIAS_MASK (0x800U) +#define USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT (11U) +/*! TXPWDIBIAS + * 0b0..Normal operation. + * 0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the + */ +#define USBPHY_PWD_TOG_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TOG_TXPWDIBIAS_MASK) +#define USBPHY_PWD_TOG_TXPWDV2I_MASK (0x1000U) +#define USBPHY_PWD_TOG_TXPWDV2I_SHIFT (12U) +/*! TXPWDV2I + * 0b0..Normal operation. + * 0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror + */ +#define USBPHY_PWD_TOG_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDV2I_SHIFT)) & USBPHY_PWD_TOG_TXPWDV2I_MASK) +#define USBPHY_PWD_TOG_RXPWDENV_MASK (0x20000U) +#define USBPHY_PWD_TOG_RXPWDENV_SHIFT (17U) +/*! RXPWDENV + * 0b0..Normal operation. + * 0b1..Power-down the USB high-speed receiver envelope detector (squelch signal) + */ +#define USBPHY_PWD_TOG_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDENV_SHIFT)) & USBPHY_PWD_TOG_RXPWDENV_MASK) +#define USBPHY_PWD_TOG_RXPWD1PT1_MASK (0x40000U) +#define USBPHY_PWD_TOG_RXPWD1PT1_SHIFT (18U) +/*! RXPWD1PT1 + * 0b0..Normal operation. + * 0b1..Power-down the USB full-speed differential receiver. + */ +#define USBPHY_PWD_TOG_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWD1PT1_SHIFT)) & USBPHY_PWD_TOG_RXPWD1PT1_MASK) +#define USBPHY_PWD_TOG_RXPWDDIFF_MASK (0x80000U) +#define USBPHY_PWD_TOG_RXPWDDIFF_SHIFT (19U) +/*! RXPWDDIFF + * 0b0..Normal operation. + * 0b1..Power-down the USB high-speed differential receive + */ +#define USBPHY_PWD_TOG_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDDIFF_SHIFT)) & USBPHY_PWD_TOG_RXPWDDIFF_MASK) +#define USBPHY_PWD_TOG_RXPWDRX_MASK (0x100000U) +#define USBPHY_PWD_TOG_RXPWDRX_SHIFT (20U) +/*! RXPWDRX + * 0b0..Normal operation. + * 0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver + */ +#define USBPHY_PWD_TOG_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDRX_SHIFT)) & USBPHY_PWD_TOG_RXPWDRX_MASK) +/*! @} */ + +/*! @name TX - USB PHY Transmitter Control Register */ +/*! @{ */ +#define USBPHY_TX_D_CAL_MASK (0xFU) +#define USBPHY_TX_D_CAL_SHIFT (0U) +/*! D_CAL + * 0b0000..Maximum current, approximately 19% above nominal. + * 0b0111..Nominal + * 0b1111..Minimum current, approximately 19% below nominal. + */ +#define USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TX_D_CAL_MASK) +#define USBPHY_TX_TXCAL45DM_MASK (0xF00U) +#define USBPHY_TX_TXCAL45DM_SHIFT (8U) +#define USBPHY_TX_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DM_SHIFT)) & USBPHY_TX_TXCAL45DM_MASK) +#define USBPHY_TX_TXENCAL45DN_MASK (0x2000U) +#define USBPHY_TX_TXENCAL45DN_SHIFT (13U) +#define USBPHY_TX_TXENCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXENCAL45DN_SHIFT)) & USBPHY_TX_TXENCAL45DN_MASK) +#define USBPHY_TX_TXCAL45DP_MASK (0xF0000U) +#define USBPHY_TX_TXCAL45DP_SHIFT (16U) +#define USBPHY_TX_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DP_SHIFT)) & USBPHY_TX_TXCAL45DP_MASK) +#define USBPHY_TX_TXENCAL45DP_MASK (0x200000U) +#define USBPHY_TX_TXENCAL45DP_SHIFT (21U) +#define USBPHY_TX_TXENCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXENCAL45DP_SHIFT)) & USBPHY_TX_TXENCAL45DP_MASK) +/*! @} */ + +/*! @name TX_SET - USB PHY Transmitter Control Register */ +/*! @{ */ +#define USBPHY_TX_SET_D_CAL_MASK (0xFU) +#define USBPHY_TX_SET_D_CAL_SHIFT (0U) +/*! D_CAL + * 0b0000..Maximum current, approximately 19% above nominal. + * 0b0111..Nominal + * 0b1111..Minimum current, approximately 19% below nominal. + */ +#define USBPHY_TX_SET_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_D_CAL_SHIFT)) & USBPHY_TX_SET_D_CAL_MASK) +#define USBPHY_TX_SET_TXCAL45DM_MASK (0xF00U) +#define USBPHY_TX_SET_TXCAL45DM_SHIFT (8U) +#define USBPHY_TX_SET_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DM_SHIFT)) & USBPHY_TX_SET_TXCAL45DM_MASK) +#define USBPHY_TX_SET_TXENCAL45DN_MASK (0x2000U) +#define USBPHY_TX_SET_TXENCAL45DN_SHIFT (13U) +#define USBPHY_TX_SET_TXENCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXENCAL45DN_SHIFT)) & USBPHY_TX_SET_TXENCAL45DN_MASK) +#define USBPHY_TX_SET_TXCAL45DP_MASK (0xF0000U) +#define USBPHY_TX_SET_TXCAL45DP_SHIFT (16U) +#define USBPHY_TX_SET_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DP_SHIFT)) & USBPHY_TX_SET_TXCAL45DP_MASK) +#define USBPHY_TX_SET_TXENCAL45DP_MASK (0x200000U) +#define USBPHY_TX_SET_TXENCAL45DP_SHIFT (21U) +#define USBPHY_TX_SET_TXENCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXENCAL45DP_SHIFT)) & USBPHY_TX_SET_TXENCAL45DP_MASK) +/*! @} */ + +/*! @name TX_CLR - USB PHY Transmitter Control Register */ +/*! @{ */ +#define USBPHY_TX_CLR_D_CAL_MASK (0xFU) +#define USBPHY_TX_CLR_D_CAL_SHIFT (0U) +/*! D_CAL + * 0b0000..Maximum current, approximately 19% above nominal. + * 0b0111..Nominal + * 0b1111..Minimum current, approximately 19% below nominal. + */ +#define USBPHY_TX_CLR_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_D_CAL_SHIFT)) & USBPHY_TX_CLR_D_CAL_MASK) +#define USBPHY_TX_CLR_TXCAL45DM_MASK (0xF00U) +#define USBPHY_TX_CLR_TXCAL45DM_SHIFT (8U) +#define USBPHY_TX_CLR_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DM_SHIFT)) & USBPHY_TX_CLR_TXCAL45DM_MASK) +#define USBPHY_TX_CLR_TXENCAL45DN_MASK (0x2000U) +#define USBPHY_TX_CLR_TXENCAL45DN_SHIFT (13U) +#define USBPHY_TX_CLR_TXENCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXENCAL45DN_SHIFT)) & USBPHY_TX_CLR_TXENCAL45DN_MASK) +#define USBPHY_TX_CLR_TXCAL45DP_MASK (0xF0000U) +#define USBPHY_TX_CLR_TXCAL45DP_SHIFT (16U) +#define USBPHY_TX_CLR_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXCAL45DP_MASK) +#define USBPHY_TX_CLR_TXENCAL45DP_MASK (0x200000U) +#define USBPHY_TX_CLR_TXENCAL45DP_SHIFT (21U) +#define USBPHY_TX_CLR_TXENCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXENCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXENCAL45DP_MASK) +/*! @} */ + +/*! @name TX_TOG - USB PHY Transmitter Control Register */ +/*! @{ */ +#define USBPHY_TX_TOG_D_CAL_MASK (0xFU) +#define USBPHY_TX_TOG_D_CAL_SHIFT (0U) +/*! D_CAL + * 0b0000..Maximum current, approximately 19% above nominal. + * 0b0111..Nominal + * 0b1111..Minimum current, approximately 19% below nominal. + */ +#define USBPHY_TX_TOG_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_D_CAL_SHIFT)) & USBPHY_TX_TOG_D_CAL_MASK) +#define USBPHY_TX_TOG_TXCAL45DM_MASK (0xF00U) +#define USBPHY_TX_TOG_TXCAL45DM_SHIFT (8U) +#define USBPHY_TX_TOG_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DM_SHIFT)) & USBPHY_TX_TOG_TXCAL45DM_MASK) +#define USBPHY_TX_TOG_TXENCAL45DN_MASK (0x2000U) +#define USBPHY_TX_TOG_TXENCAL45DN_SHIFT (13U) +#define USBPHY_TX_TOG_TXENCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXENCAL45DN_SHIFT)) & USBPHY_TX_TOG_TXENCAL45DN_MASK) +#define USBPHY_TX_TOG_TXCAL45DP_MASK (0xF0000U) +#define USBPHY_TX_TOG_TXCAL45DP_SHIFT (16U) +#define USBPHY_TX_TOG_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXCAL45DP_MASK) +#define USBPHY_TX_TOG_TXENCAL45DP_MASK (0x200000U) +#define USBPHY_TX_TOG_TXENCAL45DP_SHIFT (21U) +#define USBPHY_TX_TOG_TXENCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXENCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXENCAL45DP_MASK) +/*! @} */ + +/*! @name RX - USB PHY Receiver Control Register */ +/*! @{ */ +#define USBPHY_RX_ENVADJ_MASK (0x7U) +#define USBPHY_RX_ENVADJ_SHIFT (0U) +/*! ENVADJ + * 0b000..Trip-Level Voltage is 0.1000 V + * 0b001..Trip-Level Voltage is 0.1125 V + * 0b010..Trip-Level Voltage is 0.1250 V + * 0b011..Trip-Level Voltage is 0.0875 V + * 0b100..reserved + * 0b101..reserved + * 0b110..reserved + * 0b111..reserved + */ +#define USBPHY_RX_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_ENVADJ_SHIFT)) & USBPHY_RX_ENVADJ_MASK) +#define USBPHY_RX_DISCONADJ_MASK (0x70U) +#define USBPHY_RX_DISCONADJ_SHIFT (4U) +/*! DISCONADJ + * 0b000..Trip-Level Voltage is 0.56875 V + * 0b001..Trip-Level Voltage is 0.55000 V + * 0b010..Trip-Level Voltage is 0.58125 V + * 0b011..Trip-Level Voltage is 0.60000 V + * 0b100..reserved + * 0b101..reserved + * 0b110..reserved + * 0b111..reserved + */ +#define USBPHY_RX_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_DISCONADJ_SHIFT)) & USBPHY_RX_DISCONADJ_MASK) +#define USBPHY_RX_RXDBYPASS_MASK (0x400000U) +#define USBPHY_RX_RXDBYPASS_SHIFT (22U) +/*! RXDBYPASS + * 0b0..Normal operation. + * 0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver + */ +#define USBPHY_RX_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RXDBYPASS_SHIFT)) & USBPHY_RX_RXDBYPASS_MASK) +/*! @} */ + +/*! @name RX_SET - USB PHY Receiver Control Register */ +/*! @{ */ +#define USBPHY_RX_SET_ENVADJ_MASK (0x7U) +#define USBPHY_RX_SET_ENVADJ_SHIFT (0U) +/*! ENVADJ + * 0b000..Trip-Level Voltage is 0.1000 V + * 0b001..Trip-Level Voltage is 0.1125 V + * 0b010..Trip-Level Voltage is 0.1250 V + * 0b011..Trip-Level Voltage is 0.0875 V + * 0b100..reserved + * 0b101..reserved + * 0b110..reserved + * 0b111..reserved + */ +#define USBPHY_RX_SET_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_ENVADJ_SHIFT)) & USBPHY_RX_SET_ENVADJ_MASK) +#define USBPHY_RX_SET_DISCONADJ_MASK (0x70U) +#define USBPHY_RX_SET_DISCONADJ_SHIFT (4U) +/*! DISCONADJ + * 0b000..Trip-Level Voltage is 0.56875 V + * 0b001..Trip-Level Voltage is 0.55000 V + * 0b010..Trip-Level Voltage is 0.58125 V + * 0b011..Trip-Level Voltage is 0.60000 V + * 0b100..reserved + * 0b101..reserved + * 0b110..reserved + * 0b111..reserved + */ +#define USBPHY_RX_SET_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_DISCONADJ_SHIFT)) & USBPHY_RX_SET_DISCONADJ_MASK) +#define USBPHY_RX_SET_RXDBYPASS_MASK (0x400000U) +#define USBPHY_RX_SET_RXDBYPASS_SHIFT (22U) +/*! RXDBYPASS + * 0b0..Normal operation. + * 0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver + */ +#define USBPHY_RX_SET_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RXDBYPASS_SHIFT)) & USBPHY_RX_SET_RXDBYPASS_MASK) +/*! @} */ + +/*! @name RX_CLR - USB PHY Receiver Control Register */ +/*! @{ */ +#define USBPHY_RX_CLR_ENVADJ_MASK (0x7U) +#define USBPHY_RX_CLR_ENVADJ_SHIFT (0U) +/*! ENVADJ + * 0b000..Trip-Level Voltage is 0.1000 V + * 0b001..Trip-Level Voltage is 0.1125 V + * 0b010..Trip-Level Voltage is 0.1250 V + * 0b011..Trip-Level Voltage is 0.0875 V + * 0b100..reserved + * 0b101..reserved + * 0b110..reserved + * 0b111..reserved + */ +#define USBPHY_RX_CLR_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_ENVADJ_SHIFT)) & USBPHY_RX_CLR_ENVADJ_MASK) +#define USBPHY_RX_CLR_DISCONADJ_MASK (0x70U) +#define USBPHY_RX_CLR_DISCONADJ_SHIFT (4U) +/*! DISCONADJ + * 0b000..Trip-Level Voltage is 0.56875 V + * 0b001..Trip-Level Voltage is 0.55000 V + * 0b010..Trip-Level Voltage is 0.58125 V + * 0b011..Trip-Level Voltage is 0.60000 V + * 0b100..reserved + * 0b101..reserved + * 0b110..reserved + * 0b111..reserved + */ +#define USBPHY_RX_CLR_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_DISCONADJ_SHIFT)) & USBPHY_RX_CLR_DISCONADJ_MASK) +#define USBPHY_RX_CLR_RXDBYPASS_MASK (0x400000U) +#define USBPHY_RX_CLR_RXDBYPASS_SHIFT (22U) +/*! RXDBYPASS + * 0b0..Normal operation. + * 0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver + */ +#define USBPHY_RX_CLR_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RXDBYPASS_SHIFT)) & USBPHY_RX_CLR_RXDBYPASS_MASK) +/*! @} */ + +/*! @name RX_TOG - USB PHY Receiver Control Register */ +/*! @{ */ +#define USBPHY_RX_TOG_ENVADJ_MASK (0x7U) +#define USBPHY_RX_TOG_ENVADJ_SHIFT (0U) +/*! ENVADJ + * 0b000..Trip-Level Voltage is 0.1000 V + * 0b001..Trip-Level Voltage is 0.1125 V + * 0b010..Trip-Level Voltage is 0.1250 V + * 0b011..Trip-Level Voltage is 0.0875 V + * 0b100..reserved + * 0b101..reserved + * 0b110..reserved + * 0b111..reserved + */ +#define USBPHY_RX_TOG_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_ENVADJ_SHIFT)) & USBPHY_RX_TOG_ENVADJ_MASK) +#define USBPHY_RX_TOG_DISCONADJ_MASK (0x70U) +#define USBPHY_RX_TOG_DISCONADJ_SHIFT (4U) +/*! DISCONADJ + * 0b000..Trip-Level Voltage is 0.56875 V + * 0b001..Trip-Level Voltage is 0.55000 V + * 0b010..Trip-Level Voltage is 0.58125 V + * 0b011..Trip-Level Voltage is 0.60000 V + * 0b100..reserved + * 0b101..reserved + * 0b110..reserved + * 0b111..reserved + */ +#define USBPHY_RX_TOG_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_DISCONADJ_SHIFT)) & USBPHY_RX_TOG_DISCONADJ_MASK) +#define USBPHY_RX_TOG_RXDBYPASS_MASK (0x400000U) +#define USBPHY_RX_TOG_RXDBYPASS_SHIFT (22U) +/*! RXDBYPASS + * 0b0..Normal operation. + * 0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver + */ +#define USBPHY_RX_TOG_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RXDBYPASS_SHIFT)) & USBPHY_RX_TOG_RXDBYPASS_MASK) +/*! @} */ + +/*! @name CTRL - USB PHY General Control Register */ +/*! @{ */ +#define USBPHY_CTRL_ENHOSTDISCONDETECT_MASK (0x2U) +#define USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT (1U) +#define USBPHY_CTRL_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_ENHOSTDISCONDETECT_MASK) +#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK (0x8U) +#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT (3U) +#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK) +#define USBPHY_CTRL_ENDEVPLUGINDET_MASK (0x10U) +#define USBPHY_CTRL_ENDEVPLUGINDET_SHIFT (4U) +/*! ENDEVPLUGINDET + * 0b0..Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) + * 0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins + */ +#define USBPHY_CTRL_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_ENDEVPLUGINDET_MASK) +#define USBPHY_CTRL_DEVPLUGIN_IRQ_MASK (0x1000U) +#define USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT (12U) +#define USBPHY_CTRL_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_IRQ_MASK) +#define USBPHY_CTRL_DATA_ON_LRADC_MASK (0x2000U) +#define USBPHY_CTRL_DATA_ON_LRADC_SHIFT (13U) +#define USBPHY_CTRL_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_DATA_ON_LRADC_MASK) +#define USBPHY_CTRL_ENUTMILEVEL2_MASK (0x4000U) +#define USBPHY_CTRL_ENUTMILEVEL2_SHIFT (14U) +#define USBPHY_CTRL_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL2_MASK) +#define USBPHY_CTRL_ENUTMILEVEL3_MASK (0x8000U) +#define USBPHY_CTRL_ENUTMILEVEL3_SHIFT (15U) +#define USBPHY_CTRL_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL3_MASK) +#define USBPHY_CTRL_AUTORESUME_EN_MASK (0x40000U) +#define USBPHY_CTRL_AUTORESUME_EN_SHIFT (18U) +#define USBPHY_CTRL_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_AUTORESUME_EN_MASK) +#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK (0x80000U) +#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT (19U) +#define USBPHY_CTRL_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK) +#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK (0x100000U) +#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT (20U) +#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK) +#define USBPHY_CTRL_FSDLL_RST_EN_MASK (0x1000000U) +#define USBPHY_CTRL_FSDLL_RST_EN_SHIFT (24U) +#define USBPHY_CTRL_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_FSDLL_RST_EN_MASK) +#define USBPHY_CTRL_OTG_ID_VALUE_MASK (0x8000000U) +#define USBPHY_CTRL_OTG_ID_VALUE_SHIFT (27U) +#define USBPHY_CTRL_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_OTG_ID_VALUE_MASK) +#define USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK (0x10000000U) +#define USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT (28U) +#define USBPHY_CTRL_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK) +#define USBPHY_CTRL_UTMI_SUSPENDM_MASK (0x20000000U) +#define USBPHY_CTRL_UTMI_SUSPENDM_SHIFT (29U) +#define USBPHY_CTRL_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_UTMI_SUSPENDM_MASK) +#define USBPHY_CTRL_CLKGATE_MASK (0x40000000U) +#define USBPHY_CTRL_CLKGATE_SHIFT (30U) +#define USBPHY_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLKGATE_SHIFT)) & USBPHY_CTRL_CLKGATE_MASK) +#define USBPHY_CTRL_SFTRST_MASK (0x80000000U) +#define USBPHY_CTRL_SFTRST_SHIFT (31U) +#define USBPHY_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SFTRST_SHIFT)) & USBPHY_CTRL_SFTRST_MASK) +/*! @} */ + +/*! @name CTRL_SET - USB PHY General Control Register */ +/*! @{ */ +#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK (0x2U) +#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT (1U) +#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK) +#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK (0x8U) +#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT (3U) +#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK) +#define USBPHY_CTRL_SET_ENDEVPLUGINDET_MASK (0x10U) +#define USBPHY_CTRL_SET_ENDEVPLUGINDET_SHIFT (4U) +/*! ENDEVPLUGINDET + * 0b0..Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) + * 0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins + */ +#define USBPHY_CTRL_SET_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_SET_ENDEVPLUGINDET_MASK) +#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK (0x1000U) +#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT (12U) +#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK) +#define USBPHY_CTRL_SET_ENUTMILEVEL2_MASK (0x4000U) +#define USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT (14U) +#define USBPHY_CTRL_SET_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL2_MASK) +#define USBPHY_CTRL_SET_ENUTMILEVEL3_MASK (0x8000U) +#define USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT (15U) +#define USBPHY_CTRL_SET_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL3_MASK) +#define USBPHY_CTRL_SET_AUTORESUME_EN_MASK (0x40000U) +#define USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT (18U) +#define USBPHY_CTRL_SET_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_SET_AUTORESUME_EN_MASK) +#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK (0x80000U) +#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT (19U) +#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK) +#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK (0x100000U) +#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT (20U) +#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK) +#define USBPHY_CTRL_SET_FSDLL_RST_EN_MASK (0x1000000U) +#define USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT (24U) +#define USBPHY_CTRL_SET_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_SET_FSDLL_RST_EN_MASK) +#define USBPHY_CTRL_SET_OTG_ID_VALUE_MASK (0x8000000U) +#define USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT (27U) +#define USBPHY_CTRL_SET_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_VALUE_MASK) +#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK (0x10000000U) +#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT (28U) +#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK) +#define USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK (0x20000000U) +#define USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT (29U) +#define USBPHY_CTRL_SET_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK) +#define USBPHY_CTRL_SET_CLKGATE_MASK (0x40000000U) +#define USBPHY_CTRL_SET_CLKGATE_SHIFT (30U) +#define USBPHY_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_CLKGATE_MASK) +#define USBPHY_CTRL_SET_SFTRST_MASK (0x80000000U) +#define USBPHY_CTRL_SET_SFTRST_SHIFT (31U) +#define USBPHY_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_SFTRST_SHIFT)) & USBPHY_CTRL_SET_SFTRST_MASK) +/*! @} */ + +/*! @name CTRL_CLR - USB PHY General Control Register */ +/*! @{ */ +#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK (0x2U) +#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT (1U) +#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK) +#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK (0x8U) +#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT (3U) +#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK) +#define USBPHY_CTRL_CLR_ENDEVPLUGINDET_MASK (0x10U) +#define USBPHY_CTRL_CLR_ENDEVPLUGINDET_SHIFT (4U) +/*! ENDEVPLUGINDET + * 0b0..Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) + * 0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins + */ +#define USBPHY_CTRL_CLR_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_CLR_ENDEVPLUGINDET_MASK) +#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK (0x1000U) +#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT (12U) +#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK) +#define USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK (0x4000U) +#define USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT (14U) +#define USBPHY_CTRL_CLR_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK) +#define USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK (0x8000U) +#define USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT (15U) +#define USBPHY_CTRL_CLR_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK) +#define USBPHY_CTRL_CLR_AUTORESUME_EN_MASK (0x40000U) +#define USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT (18U) +#define USBPHY_CTRL_CLR_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_CLR_AUTORESUME_EN_MASK) +#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK (0x80000U) +#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT (19U) +#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK) +#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK (0x100000U) +#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT (20U) +#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK) +#define USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK (0x1000000U) +#define USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT (24U) +#define USBPHY_CTRL_CLR_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK) +#define USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK (0x8000000U) +#define USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT (27U) +#define USBPHY_CTRL_CLR_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK) +#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK (0x10000000U) +#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT (28U) +#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK) +#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK (0x20000000U) +#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT (29U) +#define USBPHY_CTRL_CLR_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK) +#define USBPHY_CTRL_CLR_CLKGATE_MASK (0x40000000U) +#define USBPHY_CTRL_CLR_CLKGATE_SHIFT (30U) +#define USBPHY_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_CLKGATE_MASK) +#define USBPHY_CTRL_CLR_SFTRST_MASK (0x80000000U) +#define USBPHY_CTRL_CLR_SFTRST_SHIFT (31U) +#define USBPHY_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_SFTRST_SHIFT)) & USBPHY_CTRL_CLR_SFTRST_MASK) +/*! @} */ + +/*! @name CTRL_TOG - USB PHY General Control Register */ +/*! @{ */ +#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK (0x2U) +#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT (1U) +#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK) +#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK (0x8U) +#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT (3U) +#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK) +#define USBPHY_CTRL_TOG_ENDEVPLUGINDET_MASK (0x10U) +#define USBPHY_CTRL_TOG_ENDEVPLUGINDET_SHIFT (4U) +/*! ENDEVPLUGINDET + * 0b0..Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) + * 0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins + */ +#define USBPHY_CTRL_TOG_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_TOG_ENDEVPLUGINDET_MASK) +#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK (0x1000U) +#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT (12U) +#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK) +#define USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK (0x4000U) +#define USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT (14U) +#define USBPHY_CTRL_TOG_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK) +#define USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK (0x8000U) +#define USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT (15U) +#define USBPHY_CTRL_TOG_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK) +#define USBPHY_CTRL_TOG_AUTORESUME_EN_MASK (0x40000U) +#define USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT (18U) +#define USBPHY_CTRL_TOG_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_TOG_AUTORESUME_EN_MASK) +#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK (0x80000U) +#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT (19U) +#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK) +#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK (0x100000U) +#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT (20U) +#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK) +#define USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK (0x1000000U) +#define USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT (24U) +#define USBPHY_CTRL_TOG_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK) +#define USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK (0x8000000U) +#define USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT (27U) +#define USBPHY_CTRL_TOG_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK) +#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK (0x10000000U) +#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT (28U) +#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK) +#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK (0x20000000U) +#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT (29U) +#define USBPHY_CTRL_TOG_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK) +#define USBPHY_CTRL_TOG_CLKGATE_MASK (0x40000000U) +#define USBPHY_CTRL_TOG_CLKGATE_SHIFT (30U) +#define USBPHY_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_CLKGATE_MASK) +#define USBPHY_CTRL_TOG_SFTRST_MASK (0x80000000U) +#define USBPHY_CTRL_TOG_SFTRST_SHIFT (31U) +#define USBPHY_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_SFTRST_SHIFT)) & USBPHY_CTRL_TOG_SFTRST_MASK) +/*! @} */ + +/*! @name STATUS - USB PHY Status Register */ +/*! @{ */ +#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK (0x8U) +#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT (3U) +/*! HOSTDISCONDETECT_STATUS + * 0b0..USB cable disconnect has not been detected at the local host + * 0b1..USB cable disconnect has been detected at the local host + */ +#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT)) & USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK) +#define USBPHY_STATUS_DEVPLUGIN_STATUS_MASK (0x40U) +#define USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT (6U) +/*! DEVPLUGIN_STATUS + * 0b0..No attachment to a USB host is detected + * 0b1..Cable attachment to a USB host is detected + */ +#define USBPHY_STATUS_DEVPLUGIN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT)) & USBPHY_STATUS_DEVPLUGIN_STATUS_MASK) +#define USBPHY_STATUS_OTGID_STATUS_MASK (0x100U) +#define USBPHY_STATUS_OTGID_STATUS_SHIFT (8U) +#define USBPHY_STATUS_OTGID_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_OTGID_STATUS_SHIFT)) & USBPHY_STATUS_OTGID_STATUS_MASK) +#define USBPHY_STATUS_RESUME_STATUS_MASK (0x400U) +#define USBPHY_STATUS_RESUME_STATUS_SHIFT (10U) +#define USBPHY_STATUS_RESUME_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RESUME_STATUS_SHIFT)) & USBPHY_STATUS_RESUME_STATUS_MASK) +/*! @} */ + +/*! @name DEBUG0 - USB PHY Debug Register 0 */ +/*! @{ */ +#define USBPHY_DEBUG0_OTGIDPIOLOCK_MASK (0x1U) +#define USBPHY_DEBUG0_OTGIDPIOLOCK_SHIFT (0U) +#define USBPHY_DEBUG0_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG0_OTGIDPIOLOCK_MASK) +#define USBPHY_DEBUG0_DEBUG_INTERFACE_HOLD_MASK (0x2U) +#define USBPHY_DEBUG0_DEBUG_INTERFACE_HOLD_SHIFT (1U) +#define USBPHY_DEBUG0_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG0_DEBUG_INTERFACE_HOLD_MASK) +#define USBPHY_DEBUG0_HSTPULLDOWN_MASK (0xCU) +#define USBPHY_DEBUG0_HSTPULLDOWN_SHIFT (2U) +#define USBPHY_DEBUG0_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_HSTPULLDOWN_MASK) +#define USBPHY_DEBUG0_ENHSTPULLDOWN_MASK (0x30U) +#define USBPHY_DEBUG0_ENHSTPULLDOWN_SHIFT (4U) +#define USBPHY_DEBUG0_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_ENHSTPULLDOWN_MASK) +#define USBPHY_DEBUG0_TX2RXCOUNT_MASK (0xF00U) +#define USBPHY_DEBUG0_TX2RXCOUNT_SHIFT (8U) +#define USBPHY_DEBUG0_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_TX2RXCOUNT_MASK) +#define USBPHY_DEBUG0_ENTX2RXCOUNT_MASK (0x1000U) +#define USBPHY_DEBUG0_ENTX2RXCOUNT_SHIFT (12U) +#define USBPHY_DEBUG0_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_ENTX2RXCOUNT_MASK) +#define USBPHY_DEBUG0_SQUELCHRESETCOUNT_MASK (0x1F0000U) +#define USBPHY_DEBUG0_SQUELCHRESETCOUNT_SHIFT (16U) +#define USBPHY_DEBUG0_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG0_SQUELCHRESETCOUNT_MASK) +#define USBPHY_DEBUG0_ENSQUELCHRESET_MASK (0x1000000U) +#define USBPHY_DEBUG0_ENSQUELCHRESET_SHIFT (24U) +#define USBPHY_DEBUG0_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG0_ENSQUELCHRESET_MASK) +#define USBPHY_DEBUG0_SQUELCHRESETLENGTH_MASK (0x1E000000U) +#define USBPHY_DEBUG0_SQUELCHRESETLENGTH_SHIFT (25U) +#define USBPHY_DEBUG0_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG0_SQUELCHRESETLENGTH_MASK) +#define USBPHY_DEBUG0_HOST_RESUME_DEBUG_MASK (0x20000000U) +#define USBPHY_DEBUG0_HOST_RESUME_DEBUG_SHIFT (29U) +#define USBPHY_DEBUG0_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG0_HOST_RESUME_DEBUG_MASK) +#define USBPHY_DEBUG0_CLKGATE_MASK (0x40000000U) +#define USBPHY_DEBUG0_CLKGATE_SHIFT (30U) +#define USBPHY_DEBUG0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLKGATE_SHIFT)) & USBPHY_DEBUG0_CLKGATE_MASK) +/*! @} */ + +/*! @name DEBUG0_SET - USB PHY Debug Register 0 */ +/*! @{ */ +#define USBPHY_DEBUG0_SET_OTGIDPIOLOCK_MASK (0x1U) +#define USBPHY_DEBUG0_SET_OTGIDPIOLOCK_SHIFT (0U) +#define USBPHY_DEBUG0_SET_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG0_SET_OTGIDPIOLOCK_MASK) +#define USBPHY_DEBUG0_SET_DEBUG_INTERFACE_HOLD_MASK (0x2U) +#define USBPHY_DEBUG0_SET_DEBUG_INTERFACE_HOLD_SHIFT (1U) +#define USBPHY_DEBUG0_SET_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG0_SET_DEBUG_INTERFACE_HOLD_MASK) +#define USBPHY_DEBUG0_SET_HSTPULLDOWN_MASK (0xCU) +#define USBPHY_DEBUG0_SET_HSTPULLDOWN_SHIFT (2U) +#define USBPHY_DEBUG0_SET_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_SET_HSTPULLDOWN_MASK) +#define USBPHY_DEBUG0_SET_ENHSTPULLDOWN_MASK (0x30U) +#define USBPHY_DEBUG0_SET_ENHSTPULLDOWN_SHIFT (4U) +#define USBPHY_DEBUG0_SET_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_SET_ENHSTPULLDOWN_MASK) +#define USBPHY_DEBUG0_SET_TX2RXCOUNT_MASK (0xF00U) +#define USBPHY_DEBUG0_SET_TX2RXCOUNT_SHIFT (8U) +#define USBPHY_DEBUG0_SET_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_SET_TX2RXCOUNT_MASK) +#define USBPHY_DEBUG0_SET_ENTX2RXCOUNT_MASK (0x1000U) +#define USBPHY_DEBUG0_SET_ENTX2RXCOUNT_SHIFT (12U) +#define USBPHY_DEBUG0_SET_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_SET_ENTX2RXCOUNT_MASK) +#define USBPHY_DEBUG0_SET_SQUELCHRESETCOUNT_MASK (0x1F0000U) +#define USBPHY_DEBUG0_SET_SQUELCHRESETCOUNT_SHIFT (16U) +#define USBPHY_DEBUG0_SET_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG0_SET_SQUELCHRESETCOUNT_MASK) +#define USBPHY_DEBUG0_SET_ENSQUELCHRESET_MASK (0x1000000U) +#define USBPHY_DEBUG0_SET_ENSQUELCHRESET_SHIFT (24U) +#define USBPHY_DEBUG0_SET_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG0_SET_ENSQUELCHRESET_MASK) +#define USBPHY_DEBUG0_SET_SQUELCHRESETLENGTH_MASK (0x1E000000U) +#define USBPHY_DEBUG0_SET_SQUELCHRESETLENGTH_SHIFT (25U) +#define USBPHY_DEBUG0_SET_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG0_SET_SQUELCHRESETLENGTH_MASK) +#define USBPHY_DEBUG0_SET_HOST_RESUME_DEBUG_MASK (0x20000000U) +#define USBPHY_DEBUG0_SET_HOST_RESUME_DEBUG_SHIFT (29U) +#define USBPHY_DEBUG0_SET_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG0_SET_HOST_RESUME_DEBUG_MASK) +#define USBPHY_DEBUG0_SET_CLKGATE_MASK (0x40000000U) +#define USBPHY_DEBUG0_SET_CLKGATE_SHIFT (30U) +#define USBPHY_DEBUG0_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_CLKGATE_SHIFT)) & USBPHY_DEBUG0_SET_CLKGATE_MASK) +/*! @} */ + +/*! @name DEBUG0_CLR - USB PHY Debug Register 0 */ +/*! @{ */ +#define USBPHY_DEBUG0_CLR_OTGIDPIOLOCK_MASK (0x1U) +#define USBPHY_DEBUG0_CLR_OTGIDPIOLOCK_SHIFT (0U) +#define USBPHY_DEBUG0_CLR_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG0_CLR_OTGIDPIOLOCK_MASK) +#define USBPHY_DEBUG0_CLR_DEBUG_INTERFACE_HOLD_MASK (0x2U) +#define USBPHY_DEBUG0_CLR_DEBUG_INTERFACE_HOLD_SHIFT (1U) +#define USBPHY_DEBUG0_CLR_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG0_CLR_DEBUG_INTERFACE_HOLD_MASK) +#define USBPHY_DEBUG0_CLR_HSTPULLDOWN_MASK (0xCU) +#define USBPHY_DEBUG0_CLR_HSTPULLDOWN_SHIFT (2U) +#define USBPHY_DEBUG0_CLR_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_CLR_HSTPULLDOWN_MASK) +#define USBPHY_DEBUG0_CLR_ENHSTPULLDOWN_MASK (0x30U) +#define USBPHY_DEBUG0_CLR_ENHSTPULLDOWN_SHIFT (4U) +#define USBPHY_DEBUG0_CLR_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_CLR_ENHSTPULLDOWN_MASK) +#define USBPHY_DEBUG0_CLR_TX2RXCOUNT_MASK (0xF00U) +#define USBPHY_DEBUG0_CLR_TX2RXCOUNT_SHIFT (8U) +#define USBPHY_DEBUG0_CLR_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_CLR_TX2RXCOUNT_MASK) +#define USBPHY_DEBUG0_CLR_ENTX2RXCOUNT_MASK (0x1000U) +#define USBPHY_DEBUG0_CLR_ENTX2RXCOUNT_SHIFT (12U) +#define USBPHY_DEBUG0_CLR_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_CLR_ENTX2RXCOUNT_MASK) +#define USBPHY_DEBUG0_CLR_SQUELCHRESETCOUNT_MASK (0x1F0000U) +#define USBPHY_DEBUG0_CLR_SQUELCHRESETCOUNT_SHIFT (16U) +#define USBPHY_DEBUG0_CLR_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG0_CLR_SQUELCHRESETCOUNT_MASK) +#define USBPHY_DEBUG0_CLR_ENSQUELCHRESET_MASK (0x1000000U) +#define USBPHY_DEBUG0_CLR_ENSQUELCHRESET_SHIFT (24U) +#define USBPHY_DEBUG0_CLR_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG0_CLR_ENSQUELCHRESET_MASK) +#define USBPHY_DEBUG0_CLR_SQUELCHRESETLENGTH_MASK (0x1E000000U) +#define USBPHY_DEBUG0_CLR_SQUELCHRESETLENGTH_SHIFT (25U) +#define USBPHY_DEBUG0_CLR_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG0_CLR_SQUELCHRESETLENGTH_MASK) +#define USBPHY_DEBUG0_CLR_HOST_RESUME_DEBUG_MASK (0x20000000U) +#define USBPHY_DEBUG0_CLR_HOST_RESUME_DEBUG_SHIFT (29U) +#define USBPHY_DEBUG0_CLR_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG0_CLR_HOST_RESUME_DEBUG_MASK) +#define USBPHY_DEBUG0_CLR_CLKGATE_MASK (0x40000000U) +#define USBPHY_DEBUG0_CLR_CLKGATE_SHIFT (30U) +#define USBPHY_DEBUG0_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_CLKGATE_SHIFT)) & USBPHY_DEBUG0_CLR_CLKGATE_MASK) +/*! @} */ + +/*! @name DEBUG0_TOG - USB PHY Debug Register 0 */ +/*! @{ */ +#define USBPHY_DEBUG0_TOG_OTGIDPIOLOCK_MASK (0x1U) +#define USBPHY_DEBUG0_TOG_OTGIDPIOLOCK_SHIFT (0U) +#define USBPHY_DEBUG0_TOG_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG0_TOG_OTGIDPIOLOCK_MASK) +#define USBPHY_DEBUG0_TOG_DEBUG_INTERFACE_HOLD_MASK (0x2U) +#define USBPHY_DEBUG0_TOG_DEBUG_INTERFACE_HOLD_SHIFT (1U) +#define USBPHY_DEBUG0_TOG_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG0_TOG_DEBUG_INTERFACE_HOLD_MASK) +#define USBPHY_DEBUG0_TOG_HSTPULLDOWN_MASK (0xCU) +#define USBPHY_DEBUG0_TOG_HSTPULLDOWN_SHIFT (2U) +#define USBPHY_DEBUG0_TOG_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_TOG_HSTPULLDOWN_MASK) +#define USBPHY_DEBUG0_TOG_ENHSTPULLDOWN_MASK (0x30U) +#define USBPHY_DEBUG0_TOG_ENHSTPULLDOWN_SHIFT (4U) +#define USBPHY_DEBUG0_TOG_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_TOG_ENHSTPULLDOWN_MASK) +#define USBPHY_DEBUG0_TOG_TX2RXCOUNT_MASK (0xF00U) +#define USBPHY_DEBUG0_TOG_TX2RXCOUNT_SHIFT (8U) +#define USBPHY_DEBUG0_TOG_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_TOG_TX2RXCOUNT_MASK) +#define USBPHY_DEBUG0_TOG_ENTX2RXCOUNT_MASK (0x1000U) +#define USBPHY_DEBUG0_TOG_ENTX2RXCOUNT_SHIFT (12U) +#define USBPHY_DEBUG0_TOG_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_TOG_ENTX2RXCOUNT_MASK) +#define USBPHY_DEBUG0_TOG_SQUELCHRESETCOUNT_MASK (0x1F0000U) +#define USBPHY_DEBUG0_TOG_SQUELCHRESETCOUNT_SHIFT (16U) +#define USBPHY_DEBUG0_TOG_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG0_TOG_SQUELCHRESETCOUNT_MASK) +#define USBPHY_DEBUG0_TOG_ENSQUELCHRESET_MASK (0x1000000U) +#define USBPHY_DEBUG0_TOG_ENSQUELCHRESET_SHIFT (24U) +#define USBPHY_DEBUG0_TOG_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG0_TOG_ENSQUELCHRESET_MASK) +#define USBPHY_DEBUG0_TOG_SQUELCHRESETLENGTH_MASK (0x1E000000U) +#define USBPHY_DEBUG0_TOG_SQUELCHRESETLENGTH_SHIFT (25U) +#define USBPHY_DEBUG0_TOG_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG0_TOG_SQUELCHRESETLENGTH_MASK) +#define USBPHY_DEBUG0_TOG_HOST_RESUME_DEBUG_MASK (0x20000000U) +#define USBPHY_DEBUG0_TOG_HOST_RESUME_DEBUG_SHIFT (29U) +#define USBPHY_DEBUG0_TOG_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG0_TOG_HOST_RESUME_DEBUG_MASK) +#define USBPHY_DEBUG0_TOG_CLKGATE_MASK (0x40000000U) +#define USBPHY_DEBUG0_TOG_CLKGATE_SHIFT (30U) +#define USBPHY_DEBUG0_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_CLKGATE_SHIFT)) & USBPHY_DEBUG0_TOG_CLKGATE_MASK) +/*! @} */ + +/*! @name DEBUG1 - UTMI Debug Status Register 1 */ +/*! @{ */ +#define USBPHY_DEBUG1_ENTAILADJVD_MASK (0x6000U) +#define USBPHY_DEBUG1_ENTAILADJVD_SHIFT (13U) +/*! ENTAILADJVD + * 0b00..Delay is nominal + * 0b01..Delay is +20% + * 0b10..Delay is -20% + * 0b11..Delay is -40% + */ +#define USBPHY_DEBUG1_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_ENTAILADJVD_MASK) +#define USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ_MASK (0x1C0000U) +#define USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ_SHIFT (18U) +#define USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ_MASK) +#define USBPHY_DEBUG1_USB2_REFBIAS_TST_MASK (0x600000U) +#define USBPHY_DEBUG1_USB2_REFBIAS_TST_SHIFT (21U) +#define USBPHY_DEBUG1_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_USB2_REFBIAS_TST_SHIFT)) & USBPHY_DEBUG1_USB2_REFBIAS_TST_MASK) +/*! @} */ + +/*! @name DEBUG1_SET - UTMI Debug Status Register 1 */ +/*! @{ */ +#define USBPHY_DEBUG1_SET_ENTAILADJVD_MASK (0x6000U) +#define USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT (13U) +/*! ENTAILADJVD + * 0b00..Delay is nominal + * 0b01..Delay is +20% + * 0b10..Delay is -20% + * 0b11..Delay is -40% + */ +#define USBPHY_DEBUG1_SET_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_SET_ENTAILADJVD_MASK) +#define USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ_MASK (0x1C0000U) +#define USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ_SHIFT (18U) +#define USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ_MASK) +#define USBPHY_DEBUG1_SET_USB2_REFBIAS_TST_MASK (0x600000U) +#define USBPHY_DEBUG1_SET_USB2_REFBIAS_TST_SHIFT (21U) +#define USBPHY_DEBUG1_SET_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_USB2_REFBIAS_TST_SHIFT)) & USBPHY_DEBUG1_SET_USB2_REFBIAS_TST_MASK) +/*! @} */ + +/*! @name DEBUG1_CLR - UTMI Debug Status Register 1 */ +/*! @{ */ +#define USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK (0x6000U) +#define USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT (13U) +/*! ENTAILADJVD + * 0b00..Delay is nominal + * 0b01..Delay is +20% + * 0b10..Delay is -20% + * 0b11..Delay is -40% + */ +#define USBPHY_DEBUG1_CLR_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK) +#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ_MASK (0x1C0000U) +#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ_SHIFT (18U) +#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ_MASK) +#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST_MASK (0x600000U) +#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST_SHIFT (21U) +#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST_SHIFT)) & USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST_MASK) +/*! @} */ + +/*! @name DEBUG1_TOG - UTMI Debug Status Register 1 */ +/*! @{ */ +#define USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK (0x6000U) +#define USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT (13U) +/*! ENTAILADJVD + * 0b00..Delay is nominal + * 0b01..Delay is +20% + * 0b10..Delay is -20% + * 0b11..Delay is -40% + */ +#define USBPHY_DEBUG1_TOG_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK) +#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ_MASK (0x1C0000U) +#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ_SHIFT (18U) +#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ_MASK) +#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST_MASK (0x600000U) +#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST_SHIFT (21U) +#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST_SHIFT)) & USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST_MASK) +/*! @} */ + +/*! @name VERSION - UTMI RTL Version */ +/*! @{ */ +#define USBPHY_VERSION_STEP_MASK (0xFFFFU) +#define USBPHY_VERSION_STEP_SHIFT (0U) +#define USBPHY_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_STEP_SHIFT)) & USBPHY_VERSION_STEP_MASK) +#define USBPHY_VERSION_MINOR_MASK (0xFF0000U) +#define USBPHY_VERSION_MINOR_SHIFT (16U) +#define USBPHY_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MINOR_SHIFT)) & USBPHY_VERSION_MINOR_MASK) +#define USBPHY_VERSION_MAJOR_MASK (0xFF000000U) +#define USBPHY_VERSION_MAJOR_SHIFT (24U) +#define USBPHY_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MAJOR_SHIFT)) & USBPHY_VERSION_MAJOR_MASK) +/*! @} */ + +/*! @name PLL_SIC - USB PHY PLL Control/Status Register */ +/*! @{ */ +#define USBPHY_PLL_SIC_MISC2_CONTROL0_MASK (0x20U) +#define USBPHY_PLL_SIC_MISC2_CONTROL0_SHIFT (5U) +#define USBPHY_PLL_SIC_MISC2_CONTROL0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_MISC2_CONTROL0_SHIFT)) & USBPHY_PLL_SIC_MISC2_CONTROL0_MASK) +#define USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK (0x40U) +#define USBPHY_PLL_SIC_PLL_EN_USB_CLKS_SHIFT (6U) +#define USBPHY_PLL_SIC_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK) +#define USBPHY_PLL_SIC_PLL_POWER_MASK (0x1000U) +#define USBPHY_PLL_SIC_PLL_POWER_SHIFT (12U) +#define USBPHY_PLL_SIC_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_PLL_POWER_MASK) +#define USBPHY_PLL_SIC_PLL_ENABLE_MASK (0x2000U) +#define USBPHY_PLL_SIC_PLL_ENABLE_SHIFT (13U) +#define USBPHY_PLL_SIC_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_PLL_ENABLE_MASK) +#define USBPHY_PLL_SIC_PLL_BYPASS_MASK (0x10000U) +#define USBPHY_PLL_SIC_PLL_BYPASS_SHIFT (16U) +#define USBPHY_PLL_SIC_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_PLL_BYPASS_MASK) +#define USBPHY_PLL_SIC_REFBIAS_PWD_SEL_MASK (0x80000U) +#define USBPHY_PLL_SIC_REFBIAS_PWD_SEL_SHIFT (19U) +/*! REFBIAS_PWD_SEL + * 0b0..Selects PLL_POWER to control the reference bias + * 0b1..Selects REFBIAS_PWD to control the reference bias + */ +#define USBPHY_PLL_SIC_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_REFBIAS_PWD_SEL_MASK) +#define USBPHY_PLL_SIC_REFBIAS_PWD_MASK (0x100000U) +#define USBPHY_PLL_SIC_REFBIAS_PWD_SHIFT (20U) +#define USBPHY_PLL_SIC_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_REFBIAS_PWD_MASK) +#define USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK (0x200000U) +#define USBPHY_PLL_SIC_PLL_REG_ENABLE_SHIFT (21U) +#define USBPHY_PLL_SIC_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK) +#define USBPHY_PLL_SIC_PLL_DIV_SEL_MASK (0x1C00000U) +#define USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT (22U) +/*! PLL_DIV_SEL + * 0b000..Divide by 13 + * 0b001..Divide by 15 + * 0b010..Divide by 16 + * 0b011..Divide by 20 + * 0b100..Divide by 22 + * 0b101..Divide by 25 + * 0b110..Divide by 30 + * 0b111..Divide by 240 + */ +#define USBPHY_PLL_SIC_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_PLL_DIV_SEL_MASK) +#define USBPHY_PLL_SIC_PLL_LOCK_MASK (0x80000000U) +#define USBPHY_PLL_SIC_PLL_LOCK_SHIFT (31U) +/*! PLL_LOCK + * 0b0..PLL is not currently locked + * 0b1..PLL is currently locked + */ +#define USBPHY_PLL_SIC_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_PLL_LOCK_MASK) +/*! @} */ + +/*! @name PLL_SIC_SET - USB PHY PLL Control/Status Register */ +/*! @{ */ +#define USBPHY_PLL_SIC_SET_MISC2_CONTROL0_MASK (0x20U) +#define USBPHY_PLL_SIC_SET_MISC2_CONTROL0_SHIFT (5U) +#define USBPHY_PLL_SIC_SET_MISC2_CONTROL0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_MISC2_CONTROL0_SHIFT)) & USBPHY_PLL_SIC_SET_MISC2_CONTROL0_MASK) +#define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK (0x40U) +#define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_SHIFT (6U) +#define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK) +#define USBPHY_PLL_SIC_SET_PLL_POWER_MASK (0x1000U) +#define USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT (12U) +#define USBPHY_PLL_SIC_SET_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_POWER_MASK) +#define USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK (0x2000U) +#define USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT (13U) +#define USBPHY_PLL_SIC_SET_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK) +#define USBPHY_PLL_SIC_SET_PLL_BYPASS_MASK (0x10000U) +#define USBPHY_PLL_SIC_SET_PLL_BYPASS_SHIFT (16U) +#define USBPHY_PLL_SIC_SET_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_BYPASS_MASK) +#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_MASK (0x80000U) +#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_SHIFT (19U) +/*! REFBIAS_PWD_SEL + * 0b0..Selects PLL_POWER to control the reference bias + * 0b1..Selects REFBIAS_PWD to control the reference bias + */ +#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_MASK) +#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_MASK (0x100000U) +#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SHIFT (20U) +#define USBPHY_PLL_SIC_SET_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_SET_REFBIAS_PWD_MASK) +#define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK (0x200000U) +#define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_SHIFT (21U) +#define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK) +#define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK (0x1C00000U) +#define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT (22U) +/*! PLL_DIV_SEL + * 0b000..Divide by 13 + * 0b001..Divide by 15 + * 0b010..Divide by 16 + * 0b011..Divide by 20 + * 0b100..Divide by 22 + * 0b101..Divide by 25 + * 0b110..Divide by 30 + * 0b111..Divide by 240 + */ +#define USBPHY_PLL_SIC_SET_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK) +#define USBPHY_PLL_SIC_SET_PLL_LOCK_MASK (0x80000000U) +#define USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT (31U) +/*! PLL_LOCK + * 0b0..PLL is not currently locked + * 0b1..PLL is currently locked + */ +#define USBPHY_PLL_SIC_SET_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_LOCK_MASK) +/*! @} */ + +/*! @name PLL_SIC_CLR - USB PHY PLL Control/Status Register */ +/*! @{ */ +#define USBPHY_PLL_SIC_CLR_MISC2_CONTROL0_MASK (0x20U) +#define USBPHY_PLL_SIC_CLR_MISC2_CONTROL0_SHIFT (5U) +#define USBPHY_PLL_SIC_CLR_MISC2_CONTROL0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_MISC2_CONTROL0_SHIFT)) & USBPHY_PLL_SIC_CLR_MISC2_CONTROL0_MASK) +#define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_MASK (0x40U) +#define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_SHIFT (6U) +#define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_MASK) +#define USBPHY_PLL_SIC_CLR_PLL_POWER_MASK (0x1000U) +#define USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT (12U) +#define USBPHY_PLL_SIC_CLR_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_POWER_MASK) +#define USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK (0x2000U) +#define USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT (13U) +#define USBPHY_PLL_SIC_CLR_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK) +#define USBPHY_PLL_SIC_CLR_PLL_BYPASS_MASK (0x10000U) +#define USBPHY_PLL_SIC_CLR_PLL_BYPASS_SHIFT (16U) +#define USBPHY_PLL_SIC_CLR_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_BYPASS_MASK) +#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_MASK (0x80000U) +#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_SHIFT (19U) +/*! REFBIAS_PWD_SEL + * 0b0..Selects PLL_POWER to control the reference bias + * 0b1..Selects REFBIAS_PWD to control the reference bias + */ +#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_MASK) +#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_MASK (0x100000U) +#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SHIFT (20U) +#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_CLR_REFBIAS_PWD_MASK) +#define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_MASK (0x200000U) +#define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_SHIFT (21U) +#define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_MASK) +#define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK (0x1C00000U) +#define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT (22U) +/*! PLL_DIV_SEL + * 0b000..Divide by 13 + * 0b001..Divide by 15 + * 0b010..Divide by 16 + * 0b011..Divide by 20 + * 0b100..Divide by 22 + * 0b101..Divide by 25 + * 0b110..Divide by 30 + * 0b111..Divide by 240 + */ +#define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK) +#define USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK (0x80000000U) +#define USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT (31U) +/*! PLL_LOCK + * 0b0..PLL is not currently locked + * 0b1..PLL is currently locked + */ +#define USBPHY_PLL_SIC_CLR_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK) +/*! @} */ + +/*! @name PLL_SIC_TOG - USB PHY PLL Control/Status Register */ +/*! @{ */ +#define USBPHY_PLL_SIC_TOG_MISC2_CONTROL0_MASK (0x20U) +#define USBPHY_PLL_SIC_TOG_MISC2_CONTROL0_SHIFT (5U) +#define USBPHY_PLL_SIC_TOG_MISC2_CONTROL0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_MISC2_CONTROL0_SHIFT)) & USBPHY_PLL_SIC_TOG_MISC2_CONTROL0_MASK) +#define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_MASK (0x40U) +#define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_SHIFT (6U) +#define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_MASK) +#define USBPHY_PLL_SIC_TOG_PLL_POWER_MASK (0x1000U) +#define USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT (12U) +#define USBPHY_PLL_SIC_TOG_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_POWER_MASK) +#define USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK (0x2000U) +#define USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT (13U) +#define USBPHY_PLL_SIC_TOG_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK) +#define USBPHY_PLL_SIC_TOG_PLL_BYPASS_MASK (0x10000U) +#define USBPHY_PLL_SIC_TOG_PLL_BYPASS_SHIFT (16U) +#define USBPHY_PLL_SIC_TOG_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_BYPASS_MASK) +#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_MASK (0x80000U) +#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_SHIFT (19U) +/*! REFBIAS_PWD_SEL + * 0b0..Selects PLL_POWER to control the reference bias + * 0b1..Selects REFBIAS_PWD to control the reference bias + */ +#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_MASK) +#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_MASK (0x100000U) +#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SHIFT (20U) +#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_TOG_REFBIAS_PWD_MASK) +#define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_MASK (0x200000U) +#define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_SHIFT (21U) +#define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_MASK) +#define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK (0x1C00000U) +#define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT (22U) +/*! PLL_DIV_SEL + * 0b000..Divide by 13 + * 0b001..Divide by 15 + * 0b010..Divide by 16 + * 0b011..Divide by 20 + * 0b100..Divide by 22 + * 0b101..Divide by 25 + * 0b110..Divide by 30 + * 0b111..Divide by 240 + */ +#define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK) +#define USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK (0x80000000U) +#define USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT (31U) +/*! PLL_LOCK + * 0b0..PLL is not currently locked + * 0b1..PLL is currently locked + */ +#define USBPHY_PLL_SIC_TOG_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK) +/*! @} */ + +/*! @name USB1_VBUS_DETECT - USB PHY VBUS Detect Control Register */ +/*! @{ */ +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK (0x7U) +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT (0U) +/*! VBUSVALID_THRESH + * 0b000..4.0V + * 0b001..4.1V + * 0b010..4.2V + * 0b011..4.3V + * 0b100..4.4V(Default) + * 0b101..4.5V + * 0b110..4.6V + * 0b111..4.7V + */ +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK) +#define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK (0x8U) +#define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT (3U) +/*! VBUS_OVERRIDE_EN + * 0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) + * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND + */ +#define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK) +#define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK (0x10U) +#define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT (4U) +#define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK) +#define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK (0x20U) +#define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT (5U) +#define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK) +#define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK (0x40U) +#define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT (6U) +#define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK) +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK (0x80U) +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT (7U) +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK) +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_MASK (0x100U) +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_SHIFT (8U) +/*! VBUSVALID_SEL + * 0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) + * 0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller + */ +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_MASK) +#define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_MASK (0x600U) +#define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_SHIFT (9U) +/*! VBUS_SOURCE_SEL + * 0b00..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) + * 0b01..Use the Session Valid comparator results for signal reported to the USB controller + * 0b10..Use the Session Valid comparator results for signal reported to the USB controller + * 0b11..Reserved, do not use + */ +#define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_MASK) +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_MASK (0x40000U) +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_SHIFT (18U) +/*! VBUSVALID_TO_SESSVALID + * 0b0..Use the VBUS_VALID comparator for VBUS_VALID results + * 0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. + */ +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_MASK) +#define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_MASK (0x100000U) +#define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_SHIFT (20U) +/*! PWRUP_CMPS + * 0b0..Powers down the VBUS_VALID comparator + * 0b1..Enables the VBUS_VALID comparator (default) + */ +#define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_MASK) +#define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK (0x4000000U) +#define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT (26U) +/*! DISCHARGE_VBUS + * 0b0..VBUS discharge resistor is disabled (Default) + * 0b1..VBUS discharge resistor is enabled + */ +#define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK) +#define USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_MASK (0x80000000U) +#define USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_SHIFT (31U) +/*! EN_CHARGER_RESISTOR + * 0b0..Disable resistive charger detection resistors on USB_DP and USB_DP + * 0b1..Enable resistive charger detection resistors on USB_DP and USB_DP + */ +#define USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_MASK) +/*! @} */ + +/*! @name USB1_VBUS_DETECT_SET - USB PHY VBUS Detect Control Register */ +/*! @{ */ +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK (0x7U) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT (0U) +/*! VBUSVALID_THRESH + * 0b000..4.0V + * 0b001..4.1V + * 0b010..4.2V + * 0b011..4.3V + * 0b100..4.4V(Default) + * 0b101..4.5V + * 0b110..4.6V + * 0b111..4.7V + */ +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK (0x8U) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_SHIFT (3U) +/*! VBUS_OVERRIDE_EN + * 0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) + * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND + */ +#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK) +#define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_MASK (0x10U) +#define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_SHIFT (4U) +#define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_MASK) +#define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK (0x20U) +#define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_SHIFT (5U) +#define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK) +#define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK (0x40U) +#define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_SHIFT (6U) +#define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK (0x80U) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_SHIFT (7U) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_MASK (0x100U) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_SHIFT (8U) +/*! VBUSVALID_SEL + * 0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) + * 0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller + */ +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_MASK) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_MASK (0x600U) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_SHIFT (9U) +/*! VBUS_SOURCE_SEL + * 0b00..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) + * 0b01..Use the Session Valid comparator results for signal reported to the USB controller + * 0b10..Use the Session Valid comparator results for signal reported to the USB controller + * 0b11..Reserved, do not use + */ +#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_MASK) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_MASK (0x40000U) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_SHIFT (18U) +/*! VBUSVALID_TO_SESSVALID + * 0b0..Use the VBUS_VALID comparator for VBUS_VALID results + * 0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. + */ +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_MASK) +#define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_MASK (0x100000U) +#define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_SHIFT (20U) +/*! PWRUP_CMPS + * 0b0..Powers down the VBUS_VALID comparator + * 0b1..Enables the VBUS_VALID comparator (default) + */ +#define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_MASK) +#define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK (0x4000000U) +#define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT (26U) +/*! DISCHARGE_VBUS + * 0b0..VBUS discharge resistor is disabled (Default) + * 0b1..VBUS discharge resistor is enabled + */ +#define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK) +#define USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_MASK (0x80000000U) +#define USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_SHIFT (31U) +/*! EN_CHARGER_RESISTOR + * 0b0..Disable resistive charger detection resistors on USB_DP and USB_DP + * 0b1..Enable resistive charger detection resistors on USB_DP and USB_DP + */ +#define USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_MASK) +/*! @} */ + +/*! @name USB1_VBUS_DETECT_CLR - USB PHY VBUS Detect Control Register */ +/*! @{ */ +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK (0x7U) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT (0U) +/*! VBUSVALID_THRESH + * 0b000..4.0V + * 0b001..4.1V + * 0b010..4.2V + * 0b011..4.3V + * 0b100..4.4V(Default) + * 0b101..4.5V + * 0b110..4.6V + * 0b111..4.7V + */ +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_MASK (0x8U) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_SHIFT (3U) +/*! VBUS_OVERRIDE_EN + * 0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) + * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND + */ +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_MASK) +#define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_MASK (0x10U) +#define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_SHIFT (4U) +#define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_MASK) +#define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_MASK (0x20U) +#define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_SHIFT (5U) +#define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_MASK) +#define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_MASK (0x40U) +#define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_SHIFT (6U) +#define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_MASK) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_MASK (0x80U) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_SHIFT (7U) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_MASK) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_MASK (0x100U) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_SHIFT (8U) +/*! VBUSVALID_SEL + * 0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) + * 0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller + */ +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_MASK) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_MASK (0x600U) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_SHIFT (9U) +/*! VBUS_SOURCE_SEL + * 0b00..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) + * 0b01..Use the Session Valid comparator results for signal reported to the USB controller + * 0b10..Use the Session Valid comparator results for signal reported to the USB controller + * 0b11..Reserved, do not use + */ +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_MASK) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_MASK (0x40000U) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_SHIFT (18U) +/*! VBUSVALID_TO_SESSVALID + * 0b0..Use the VBUS_VALID comparator for VBUS_VALID results + * 0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. + */ +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_MASK) +#define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_MASK (0x100000U) +#define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_SHIFT (20U) +/*! PWRUP_CMPS + * 0b0..Powers down the VBUS_VALID comparator + * 0b1..Enables the VBUS_VALID comparator (default) + */ +#define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_MASK) +#define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK (0x4000000U) +#define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT (26U) +/*! DISCHARGE_VBUS + * 0b0..VBUS discharge resistor is disabled (Default) + * 0b1..VBUS discharge resistor is enabled + */ +#define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK) +#define USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_MASK (0x80000000U) +#define USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_SHIFT (31U) +/*! EN_CHARGER_RESISTOR + * 0b0..Disable resistive charger detection resistors on USB_DP and USB_DP + * 0b1..Enable resistive charger detection resistors on USB_DP and USB_DP + */ +#define USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_MASK) +/*! @} */ + +/*! @name USB1_VBUS_DETECT_TOG - USB PHY VBUS Detect Control Register */ +/*! @{ */ +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK (0x7U) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT (0U) +/*! VBUSVALID_THRESH + * 0b000..4.0V + * 0b001..4.1V + * 0b010..4.2V + * 0b011..4.3V + * 0b100..4.4V(Default) + * 0b101..4.5V + * 0b110..4.6V + * 0b111..4.7V + */ +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_MASK (0x8U) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_SHIFT (3U) +/*! VBUS_OVERRIDE_EN + * 0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) + * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND + */ +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_MASK) +#define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_MASK (0x10U) +#define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_SHIFT (4U) +#define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_MASK) +#define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_MASK (0x20U) +#define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_SHIFT (5U) +#define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_MASK) +#define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_MASK (0x40U) +#define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_SHIFT (6U) +#define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_MASK) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_MASK (0x80U) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_SHIFT (7U) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_MASK) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_MASK (0x100U) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_SHIFT (8U) +/*! VBUSVALID_SEL + * 0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) + * 0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller + */ +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_MASK) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_MASK (0x600U) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_SHIFT (9U) +/*! VBUS_SOURCE_SEL + * 0b00..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) + * 0b01..Use the Session Valid comparator results for signal reported to the USB controller + * 0b10..Use the Session Valid comparator results for signal reported to the USB controller + * 0b11..Reserved, do not use + */ +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_MASK) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_MASK (0x40000U) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_SHIFT (18U) +/*! VBUSVALID_TO_SESSVALID + * 0b0..Use the VBUS_VALID comparator for VBUS_VALID results + * 0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. + */ +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_MASK) +#define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_MASK (0x100000U) +#define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_SHIFT (20U) +/*! PWRUP_CMPS + * 0b0..Powers down the VBUS_VALID comparator + * 0b1..Enables the VBUS_VALID comparator (default) + */ +#define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_MASK) +#define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK (0x4000000U) +#define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT (26U) +/*! DISCHARGE_VBUS + * 0b0..VBUS discharge resistor is disabled (Default) + * 0b1..VBUS discharge resistor is enabled + */ +#define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK) +#define USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_MASK (0x80000000U) +#define USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_SHIFT (31U) +/*! EN_CHARGER_RESISTOR + * 0b0..Disable resistive charger detection resistors on USB_DP and USB_DP + * 0b1..Enable resistive charger detection resistors on USB_DP and USB_DP + */ +#define USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_MASK) +/*! @} */ + +/*! @name USB1_VBUS_DET_STAT - USB PHY VBUS Detector Status Register */ +/*! @{ */ +#define USBPHY_USB1_VBUS_DET_STAT_SESSEND_MASK (0x1U) +#define USBPHY_USB1_VBUS_DET_STAT_SESSEND_SHIFT (0U) +/*! SESSEND + * 0b0..The VBUS voltage is above the Session Valid threshold + * 0b1..The VBUS voltage is below the Session Valid threshold + */ +#define USBPHY_USB1_VBUS_DET_STAT_SESSEND(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_SESSEND_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_SESSEND_MASK) +#define USBPHY_USB1_VBUS_DET_STAT_BVALID_MASK (0x2U) +#define USBPHY_USB1_VBUS_DET_STAT_BVALID_SHIFT (1U) +/*! BVALID + * 0b0..The VBUS voltage is below the Session Valid threshold + * 0b1..The VBUS voltage is above the Session Valid threshold + */ +#define USBPHY_USB1_VBUS_DET_STAT_BVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_BVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_BVALID_MASK) +#define USBPHY_USB1_VBUS_DET_STAT_AVALID_MASK (0x4U) +#define USBPHY_USB1_VBUS_DET_STAT_AVALID_SHIFT (2U) +/*! AVALID + * 0b0..The VBUS voltage is below the Session Valid threshold + * 0b1..The VBUS voltage is above the Session Valid threshold + */ +#define USBPHY_USB1_VBUS_DET_STAT_AVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_AVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_AVALID_MASK) +#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_MASK (0x8U) +#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_SHIFT (3U) +/*! VBUS_VALID + * 0b0..VBUS is below the comparator threshold + * 0b1..VBUS is above the comparator threshold + */ +#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_MASK) +#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_MASK (0x10U) +#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_SHIFT (4U) +/*! VBUS_VALID_3V + * 0b0..VBUS voltage is below VBUS_VALID_3V threshold + * 0b1..VBUS voltage is above VBUS_VALID_3V threshold + */ +#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_MASK) +/*! @} */ + +/*! @name USB1_CHRG_DETECT - USB PHY Charger Detect Control Register */ +/*! @{ */ +#define USBPHY_USB1_CHRG_DETECT_PULLUP_DP_MASK (0x4U) +#define USBPHY_USB1_CHRG_DETECT_PULLUP_DP_SHIFT (2U) +#define USBPHY_USB1_CHRG_DETECT_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_PULLUP_DP_MASK) +#define USBPHY_USB1_CHRG_DETECT_BGR_IBIAS_MASK (0x800000U) +#define USBPHY_USB1_CHRG_DETECT_BGR_IBIAS_SHIFT (23U) +/*! BGR_IBIAS + * 0b0..Bias current is derived from the USB PHY internal current generator. + * 0b1..Bias current is derived from the reference generator of the bandgap. + */ +#define USBPHY_USB1_CHRG_DETECT_BGR_IBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_BGR_IBIAS_SHIFT)) & USBPHY_USB1_CHRG_DETECT_BGR_IBIAS_MASK) +/*! @} */ + +/*! @name USB1_CHRG_DETECT_SET - USB PHY Charger Detect Control Register */ +/*! @{ */ +#define USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_MASK (0x4U) +#define USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_SHIFT (2U) +#define USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_MASK) +#define USBPHY_USB1_CHRG_DETECT_SET_BGR_IBIAS_MASK (0x800000U) +#define USBPHY_USB1_CHRG_DETECT_SET_BGR_IBIAS_SHIFT (23U) +/*! BGR_IBIAS + * 0b0..Bias current is derived from the USB PHY internal current generator. + * 0b1..Bias current is derived from the reference generator of the bandgap. + */ +#define USBPHY_USB1_CHRG_DETECT_SET_BGR_IBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_BGR_IBIAS_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_BGR_IBIAS_MASK) +/*! @} */ + +/*! @name USB1_CHRG_DETECT_CLR - USB PHY Charger Detect Control Register */ +/*! @{ */ +#define USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_MASK (0x4U) +#define USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_SHIFT (2U) +#define USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_MASK) +#define USBPHY_USB1_CHRG_DETECT_CLR_BGR_IBIAS_MASK (0x800000U) +#define USBPHY_USB1_CHRG_DETECT_CLR_BGR_IBIAS_SHIFT (23U) +/*! BGR_IBIAS + * 0b0..Bias current is derived from the USB PHY internal current generator. + * 0b1..Bias current is derived from the reference generator of the bandgap. + */ +#define USBPHY_USB1_CHRG_DETECT_CLR_BGR_IBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_BGR_IBIAS_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_BGR_IBIAS_MASK) +/*! @} */ + +/*! @name USB1_CHRG_DETECT_TOG - USB PHY Charger Detect Control Register */ +/*! @{ */ +#define USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_MASK (0x4U) +#define USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_SHIFT (2U) +#define USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_MASK) +#define USBPHY_USB1_CHRG_DETECT_TOG_BGR_IBIAS_MASK (0x800000U) +#define USBPHY_USB1_CHRG_DETECT_TOG_BGR_IBIAS_SHIFT (23U) +/*! BGR_IBIAS + * 0b0..Bias current is derived from the USB PHY internal current generator. + * 0b1..Bias current is derived from the reference generator of the bandgap. + */ +#define USBPHY_USB1_CHRG_DETECT_TOG_BGR_IBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_BGR_IBIAS_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_BGR_IBIAS_MASK) +/*! @} */ + +/*! @name USB1_CHRG_DET_STAT - USB PHY Charger Detect Status Register */ +/*! @{ */ +#define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_MASK (0x1U) +#define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_SHIFT (0U) +/*! PLUG_CONTACT + * 0b0..No USB cable attachment has been detected + * 0b1..A USB cable attachment between the device and host has been detected + */ +#define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_MASK) +#define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_MASK (0x2U) +#define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_SHIFT (1U) +/*! CHRG_DETECTED + * 0b0..Standard Downstream Port (SDP) has been detected + * 0b1..Charging Port has been detected + */ +#define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_MASK) +#define USBPHY_USB1_CHRG_DET_STAT_DM_STATE_MASK (0x4U) +#define USBPHY_USB1_CHRG_DET_STAT_DM_STATE_SHIFT (2U) +/*! DM_STATE + * 0b0..USB_DM pin voltage is < 0.8V + * 0b1..USB_DM pin voltage is > 2.0V + */ +#define USBPHY_USB1_CHRG_DET_STAT_DM_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_DM_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_DM_STATE_MASK) +#define USBPHY_USB1_CHRG_DET_STAT_DP_STATE_MASK (0x8U) +#define USBPHY_USB1_CHRG_DET_STAT_DP_STATE_SHIFT (3U) +/*! DP_STATE + * 0b0..USB_DP pin voltage is < 0.8V + * 0b1..USB_DP pin voltage is > 2.0V + */ +#define USBPHY_USB1_CHRG_DET_STAT_DP_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_DP_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_DP_STATE_MASK) +#define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_MASK (0x10U) +#define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_SHIFT (4U) +/*! SECDET_DCP + * 0b0..Charging Downstream Port (CDP) has been detected + * 0b1..Downstream Charging Port (DCP) has been detected + */ +#define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_MASK) +/*! @} */ + +/*! @name ANACTRL - USB PHY Analog Control Register */ +/*! @{ */ +#define USBPHY_ANACTRL_DEV_PULLDOWN_MASK (0x400U) +#define USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT (10U) +/*! DEV_PULLDOWN + * 0b0..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. + * 0b1..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. + */ +#define USBPHY_ANACTRL_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_DEV_PULLDOWN_MASK) +/*! @} */ + +/*! @name ANACTRL_SET - USB PHY Analog Control Register */ +/*! @{ */ +#define USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK (0x400U) +#define USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT (10U) +/*! DEV_PULLDOWN + * 0b0..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. + * 0b1..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. + */ +#define USBPHY_ANACTRL_SET_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK) +/*! @} */ + +/*! @name ANACTRL_CLR - USB PHY Analog Control Register */ +/*! @{ */ +#define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK (0x400U) +#define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT (10U) +/*! DEV_PULLDOWN + * 0b0..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. + * 0b1..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. + */ +#define USBPHY_ANACTRL_CLR_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK) +/*! @} */ + +/*! @name ANACTRL_TOG - USB PHY Analog Control Register */ +/*! @{ */ +#define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK (0x400U) +#define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT (10U) +/*! DEV_PULLDOWN + * 0b0..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. + * 0b1..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. + */ +#define USBPHY_ANACTRL_TOG_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group USBPHY_Register_Masks */ + + +/* USBPHY - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral USBPHY base address */ + #define USBPHY_BASE (0x50038000u) + /** Peripheral USBPHY base address */ + #define USBPHY_BASE_NS (0x40038000u) + /** Peripheral USBPHY base pointer */ + #define USBPHY ((USBPHY_Type *)USBPHY_BASE) + /** Peripheral USBPHY base pointer */ + #define USBPHY_NS ((USBPHY_Type *)USBPHY_BASE_NS) + /** Array initializer of USBPHY peripheral base addresses */ + #define USBPHY_BASE_ADDRS { USBPHY_BASE } + /** Array initializer of USBPHY peripheral base pointers */ + #define USBPHY_BASE_PTRS { USBPHY } + /** Array initializer of USBPHY peripheral base addresses */ + #define USBPHY_BASE_ADDRS_NS { USBPHY_BASE_NS } + /** Array initializer of USBPHY peripheral base pointers */ + #define USBPHY_BASE_PTRS_NS { USBPHY_NS } +#else + /** Peripheral USBPHY base address */ + #define USBPHY_BASE (0x40038000u) + /** Peripheral USBPHY base pointer */ + #define USBPHY ((USBPHY_Type *)USBPHY_BASE) + /** Array initializer of USBPHY peripheral base addresses */ + #define USBPHY_BASE_ADDRS { USBPHY_BASE } + /** Array initializer of USBPHY peripheral base pointers */ + #define USBPHY_BASE_PTRS { USBPHY } +#endif + +/*! + * @} + */ /* end of group USBPHY_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- UTICK Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup UTICK_Peripheral_Access_Layer UTICK Peripheral Access Layer + * @{ + */ + +/** UTICK - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< Control register., offset: 0x0 */ + __IO uint32_t STAT; /**< Status register., offset: 0x4 */ + __IO uint32_t CFG; /**< Capture configuration register., offset: 0x8 */ + __O uint32_t CAPCLR; /**< Capture clear register., offset: 0xC */ + __I uint32_t CAP[4]; /**< Capture register ., array offset: 0x10, array step: 0x4 */ +} UTICK_Type; + +/* ---------------------------------------------------------------------------- + -- UTICK Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup UTICK_Register_Masks UTICK Register Masks + * @{ + */ + +/*! @name CTRL - Control register. */ +/*! @{ */ +#define UTICK_CTRL_DELAYVAL_MASK (0x7FFFFFFFU) +#define UTICK_CTRL_DELAYVAL_SHIFT (0U) +#define UTICK_CTRL_DELAYVAL(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_DELAYVAL_SHIFT)) & UTICK_CTRL_DELAYVAL_MASK) +#define UTICK_CTRL_REPEAT_MASK (0x80000000U) +#define UTICK_CTRL_REPEAT_SHIFT (31U) +#define UTICK_CTRL_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_REPEAT_SHIFT)) & UTICK_CTRL_REPEAT_MASK) +/*! @} */ + +/*! @name STAT - Status register. */ +/*! @{ */ +#define UTICK_STAT_INTR_MASK (0x1U) +#define UTICK_STAT_INTR_SHIFT (0U) +#define UTICK_STAT_INTR(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_INTR_SHIFT)) & UTICK_STAT_INTR_MASK) +#define UTICK_STAT_ACTIVE_MASK (0x2U) +#define UTICK_STAT_ACTIVE_SHIFT (1U) +#define UTICK_STAT_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_ACTIVE_SHIFT)) & UTICK_STAT_ACTIVE_MASK) +/*! @} */ + +/*! @name CFG - Capture configuration register. */ +/*! @{ */ +#define UTICK_CFG_CAPEN0_MASK (0x1U) +#define UTICK_CFG_CAPEN0_SHIFT (0U) +#define UTICK_CFG_CAPEN0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN0_SHIFT)) & UTICK_CFG_CAPEN0_MASK) +#define UTICK_CFG_CAPEN1_MASK (0x2U) +#define UTICK_CFG_CAPEN1_SHIFT (1U) +#define UTICK_CFG_CAPEN1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN1_SHIFT)) & UTICK_CFG_CAPEN1_MASK) +#define UTICK_CFG_CAPEN2_MASK (0x4U) +#define UTICK_CFG_CAPEN2_SHIFT (2U) +#define UTICK_CFG_CAPEN2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN2_SHIFT)) & UTICK_CFG_CAPEN2_MASK) +#define UTICK_CFG_CAPEN3_MASK (0x8U) +#define UTICK_CFG_CAPEN3_SHIFT (3U) +#define UTICK_CFG_CAPEN3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN3_SHIFT)) & UTICK_CFG_CAPEN3_MASK) +#define UTICK_CFG_CAPPOL0_MASK (0x100U) +#define UTICK_CFG_CAPPOL0_SHIFT (8U) +#define UTICK_CFG_CAPPOL0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL0_SHIFT)) & UTICK_CFG_CAPPOL0_MASK) +#define UTICK_CFG_CAPPOL1_MASK (0x200U) +#define UTICK_CFG_CAPPOL1_SHIFT (9U) +#define UTICK_CFG_CAPPOL1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL1_SHIFT)) & UTICK_CFG_CAPPOL1_MASK) +#define UTICK_CFG_CAPPOL2_MASK (0x400U) +#define UTICK_CFG_CAPPOL2_SHIFT (10U) +#define UTICK_CFG_CAPPOL2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL2_SHIFT)) & UTICK_CFG_CAPPOL2_MASK) +#define UTICK_CFG_CAPPOL3_MASK (0x800U) +#define UTICK_CFG_CAPPOL3_SHIFT (11U) +#define UTICK_CFG_CAPPOL3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL3_SHIFT)) & UTICK_CFG_CAPPOL3_MASK) +/*! @} */ + +/*! @name CAPCLR - Capture clear register. */ +/*! @{ */ +#define UTICK_CAPCLR_CAPCLR0_MASK (0x1U) +#define UTICK_CAPCLR_CAPCLR0_SHIFT (0U) +#define UTICK_CAPCLR_CAPCLR0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR0_SHIFT)) & UTICK_CAPCLR_CAPCLR0_MASK) +#define UTICK_CAPCLR_CAPCLR1_MASK (0x2U) +#define UTICK_CAPCLR_CAPCLR1_SHIFT (1U) +#define UTICK_CAPCLR_CAPCLR1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR1_SHIFT)) & UTICK_CAPCLR_CAPCLR1_MASK) +#define UTICK_CAPCLR_CAPCLR2_MASK (0x4U) +#define UTICK_CAPCLR_CAPCLR2_SHIFT (2U) +#define UTICK_CAPCLR_CAPCLR2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR2_SHIFT)) & UTICK_CAPCLR_CAPCLR2_MASK) +#define UTICK_CAPCLR_CAPCLR3_MASK (0x8U) +#define UTICK_CAPCLR_CAPCLR3_SHIFT (3U) +#define UTICK_CAPCLR_CAPCLR3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR3_SHIFT)) & UTICK_CAPCLR_CAPCLR3_MASK) +/*! @} */ + +/*! @name CAP - Capture register . */ +/*! @{ */ +#define UTICK_CAP_CAP_VALUE_MASK (0x7FFFFFFFU) +#define UTICK_CAP_CAP_VALUE_SHIFT (0U) +#define UTICK_CAP_CAP_VALUE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_CAP_VALUE_SHIFT)) & UTICK_CAP_CAP_VALUE_MASK) +#define UTICK_CAP_VALID_MASK (0x80000000U) +#define UTICK_CAP_VALID_SHIFT (31U) +#define UTICK_CAP_VALID(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_VALID_SHIFT)) & UTICK_CAP_VALID_MASK) +/*! @} */ + +/* The count of UTICK_CAP */ +#define UTICK_CAP_COUNT (4U) + + +/*! + * @} + */ /* end of group UTICK_Register_Masks */ + + +/* UTICK - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral UTICK0 base address */ + #define UTICK0_BASE (0x5000E000u) + /** Peripheral UTICK0 base address */ + #define UTICK0_BASE_NS (0x4000E000u) + /** Peripheral UTICK0 base pointer */ + #define UTICK0 ((UTICK_Type *)UTICK0_BASE) + /** Peripheral UTICK0 base pointer */ + #define UTICK0_NS ((UTICK_Type *)UTICK0_BASE_NS) + /** Array initializer of UTICK peripheral base addresses */ + #define UTICK_BASE_ADDRS { UTICK0_BASE } + /** Array initializer of UTICK peripheral base pointers */ + #define UTICK_BASE_PTRS { UTICK0 } + /** Array initializer of UTICK peripheral base addresses */ + #define UTICK_BASE_ADDRS_NS { UTICK0_BASE_NS } + /** Array initializer of UTICK peripheral base pointers */ + #define UTICK_BASE_PTRS_NS { UTICK0_NS } +#else + /** Peripheral UTICK0 base address */ + #define UTICK0_BASE (0x4000E000u) + /** Peripheral UTICK0 base pointer */ + #define UTICK0 ((UTICK_Type *)UTICK0_BASE) + /** Array initializer of UTICK peripheral base addresses */ + #define UTICK_BASE_ADDRS { UTICK0_BASE } + /** Array initializer of UTICK peripheral base pointers */ + #define UTICK_BASE_PTRS { UTICK0 } +#endif +/** Interrupt vectors for the UTICK peripheral type */ +#define UTICK_IRQS { UTICK0_IRQn } + +/*! + * @} + */ /* end of group UTICK_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- WWDT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WWDT_Peripheral_Access_Layer WWDT Peripheral Access Layer + * @{ + */ + +/** WWDT - Register Layout Typedef */ +typedef struct { + __IO uint32_t MOD; /**< Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer., offset: 0x0 */ + __IO uint32_t TC; /**< Watchdog timer constant register. This 24-bit register determines the time-out value., offset: 0x4 */ + __O uint32_t FEED; /**< Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC., offset: 0x8 */ + __I uint32_t TV; /**< Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer., offset: 0xC */ + uint8_t RESERVED_0[4]; + __IO uint32_t WARNINT; /**< Watchdog Warning Interrupt compare value., offset: 0x14 */ + __IO uint32_t WINDOW; /**< Watchdog Window compare value., offset: 0x18 */ +} WWDT_Type; + +/* ---------------------------------------------------------------------------- + -- WWDT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WWDT_Register_Masks WWDT Register Masks + * @{ + */ + +/*! @name MOD - Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */ +/*! @{ */ +#define WWDT_MOD_WDEN_MASK (0x1U) +#define WWDT_MOD_WDEN_SHIFT (0U) +/*! WDEN - Watchdog enable bit. Once this bit is set to one and a watchdog feed is performed, the + * watchdog timer will run permanently. + * 0b0..Stop. The watchdog timer is stopped. + * 0b1..Run. The watchdog timer is running. + */ +#define WWDT_MOD_WDEN(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDEN_SHIFT)) & WWDT_MOD_WDEN_MASK) +#define WWDT_MOD_WDRESET_MASK (0x2U) +#define WWDT_MOD_WDRESET_SHIFT (1U) +/*! WDRESET - Watchdog reset enable bit. Once this bit has been written with a 1 it cannot be re-written with a 0. + * 0b0..Interrupt. A watchdog time-out will not cause a chip reset. + * 0b1..Reset. A watchdog time-out will cause a chip reset. + */ +#define WWDT_MOD_WDRESET(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDRESET_SHIFT)) & WWDT_MOD_WDRESET_MASK) +#define WWDT_MOD_WDTOF_MASK (0x4U) +#define WWDT_MOD_WDTOF_SHIFT (2U) +#define WWDT_MOD_WDTOF(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDTOF_SHIFT)) & WWDT_MOD_WDTOF_MASK) +#define WWDT_MOD_WDINT_MASK (0x8U) +#define WWDT_MOD_WDINT_SHIFT (3U) +#define WWDT_MOD_WDINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDINT_SHIFT)) & WWDT_MOD_WDINT_MASK) +#define WWDT_MOD_WDPROTECT_MASK (0x10U) +#define WWDT_MOD_WDPROTECT_SHIFT (4U) +/*! WDPROTECT - Watchdog update mode. This bit can be set once by software and is only cleared by a reset. + * 0b0..Flexible. The watchdog time-out value (TC) can be changed at any time. + * 0b1..Threshold. The watchdog time-out value (TC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW. + */ +#define WWDT_MOD_WDPROTECT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDPROTECT_SHIFT)) & WWDT_MOD_WDPROTECT_MASK) +/*! @} */ + +/*! @name TC - Watchdog timer constant register. This 24-bit register determines the time-out value. */ +/*! @{ */ +#define WWDT_TC_COUNT_MASK (0xFFFFFFU) +#define WWDT_TC_COUNT_SHIFT (0U) +#define WWDT_TC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TC_COUNT_SHIFT)) & WWDT_TC_COUNT_MASK) +/*! @} */ + +/*! @name FEED - Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC. */ +/*! @{ */ +#define WWDT_FEED_FEED_MASK (0xFFU) +#define WWDT_FEED_FEED_SHIFT (0U) +#define WWDT_FEED_FEED(x) (((uint32_t)(((uint32_t)(x)) << WWDT_FEED_FEED_SHIFT)) & WWDT_FEED_FEED_MASK) +/*! @} */ + +/*! @name TV - Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer. */ +/*! @{ */ +#define WWDT_TV_COUNT_MASK (0xFFFFFFU) +#define WWDT_TV_COUNT_SHIFT (0U) +#define WWDT_TV_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TV_COUNT_SHIFT)) & WWDT_TV_COUNT_MASK) +/*! @} */ + +/*! @name WARNINT - Watchdog Warning Interrupt compare value. */ +/*! @{ */ +#define WWDT_WARNINT_WARNINT_MASK (0x3FFU) +#define WWDT_WARNINT_WARNINT_SHIFT (0U) +#define WWDT_WARNINT_WARNINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WARNINT_WARNINT_SHIFT)) & WWDT_WARNINT_WARNINT_MASK) +/*! @} */ + +/*! @name WINDOW - Watchdog Window compare value. */ +/*! @{ */ +#define WWDT_WINDOW_WINDOW_MASK (0xFFFFFFU) +#define WWDT_WINDOW_WINDOW_SHIFT (0U) +#define WWDT_WINDOW_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WINDOW_WINDOW_SHIFT)) & WWDT_WINDOW_WINDOW_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group WWDT_Register_Masks */ + + +/* WWDT - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral WWDT base address */ + #define WWDT_BASE (0x5000C000u) + /** Peripheral WWDT base address */ + #define WWDT_BASE_NS (0x4000C000u) + /** Peripheral WWDT base pointer */ + #define WWDT ((WWDT_Type *)WWDT_BASE) + /** Peripheral WWDT base pointer */ + #define WWDT_NS ((WWDT_Type *)WWDT_BASE_NS) + /** Array initializer of WWDT peripheral base addresses */ + #define WWDT_BASE_ADDRS { WWDT_BASE } + /** Array initializer of WWDT peripheral base pointers */ + #define WWDT_BASE_PTRS { WWDT } + /** Array initializer of WWDT peripheral base addresses */ + #define WWDT_BASE_ADDRS_NS { WWDT_BASE_NS } + /** Array initializer of WWDT peripheral base pointers */ + #define WWDT_BASE_PTRS_NS { WWDT_NS } +#else + /** Peripheral WWDT base address */ + #define WWDT_BASE (0x4000C000u) + /** Peripheral WWDT base pointer */ + #define WWDT ((WWDT_Type *)WWDT_BASE) + /** Array initializer of WWDT peripheral base addresses */ + #define WWDT_BASE_ADDRS { WWDT_BASE } + /** Array initializer of WWDT peripheral base pointers */ + #define WWDT_BASE_PTRS { WWDT } +#endif +/** Interrupt vectors for the WWDT peripheral type */ +#define WWDT_IRQS { WDT_BOD_IRQn } + +/*! + * @} + */ /* end of group WWDT_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +/* ---------------------------------------------------------------------------- + -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + * @{ + */ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang system_header + #endif +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma system_include +#endif + +/** + * @brief Mask and left-shift a bit field value for use in a register bit range. + * @param field Name of the register bit field. + * @param value Value of the bit field. + * @return Masked and shifted value. + */ +#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) +/** + * @brief Mask and right-shift a register value to extract a bit field value. + * @param field Name of the register bit field. + * @param value Value of the register. + * @return Masked and shifted bit field value. + */ +#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) + +/*! + * @} + */ /* end of group Bit_Field_Generic_Macros */ + + +/* ---------------------------------------------------------------------------- + -- SDK Compatibility + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDK_Compatibility_Symbols SDK Compatibility + * @{ + */ + +/** High Speed SPI (Flexcomm 8) interrupt name */ +#define LSPI_HS_IRQn FLEXCOMM8_IRQn + +/** EMC CS base address */ +#define EMC_CS0_BASE (0x80000000u) +#define EMC_CS1_BASE (0x90000000u) +#define EMC_CS2_BASE (0x98000000u) +#define EMC_CS3_BASE (0x9C000000u) +#define EMC_DYCS0_BASE (0xA0000000u) +#define EMC_DYCS1_BASE (0xB0000000u) +#define EMC_DYCS2_BASE (0xC0000000u) +#define EMC_DYCS3_BASE (0xD0000000u) +#define EMC_CS_ADDRESS {EMC_CS0_BASE, EMC_CS1_BASE, EMC_CS2_BASE, EMC_CS3_BASE} +#define EMC_DYCS_ADDRESS {EMC_DYCS0_BASE, EMC_DYCS1_BASE, EMC_DYCS2_BASE, EMC_DYCS3_BASE} + +/** OTP API */ +typedef struct { + uint32_t (*otpInit)(void); /** Initializes OTP controller */ + uint32_t (*otpEnableBankWriteMask)(uint32_t bankMask); /** Unlock one or more OTP banks for write access */ + uint32_t (*otpDisableBankWriteMask)(uint32_t bankMask); /** Lock one or more OTP banks for write access */ + uint32_t (*otpEnableBankWriteLock)(uint32_t bankIndex, uint32_t regEnableMask, uint32_t regDisableMask, + uint32_t lockWrite); /** Locks or unlocks write access to a register of an OTP bank and the write lock */ + uint32_t (*otpEnableBankReadLock)(uint32_t bankIndex, uint32_t regEnableMask, uint32_t regDisableMask, + uint32_t lockWrite); /** Locks or unlocks read access to a register of an OTP bank and the write lock */ + uint32_t (*otpProgramReg)(uint32_t bankIndex, uint32_t regIndex, uint32_t value); /** Program a single register in an OTP bank */ + uint32_t RESERVED_0[5]; + uint32_t (*rngRead)(void); /** Returns 32-bit number from hardware random number generator */ + uint32_t (*otpGetDriverVersion)(void); /** Returns the version of the OTP driver in ROM */ +} OTP_API_Type; + +/** ROM API */ +typedef struct { + __I uint32_t usbdApiBase; /** USB API Base */ + uint32_t RESERVED_0[13]; + __I OTP_API_Type *otpApiBase; /** OTP API Base */ + __I uint32_t aesApiBase; /** AES API Base */ + __I uint32_t secureApiBase; /** Secure API Base */ +} ROM_API_Type; + +/** ROM API base address */ +#define ROM_API_BASE (0x03000200u) +/** ROM API base pointer */ +#define ROM_API (*(ROM_API_Type**) ROM_API_BASE) +/** OTP API base pointer */ +#define OTP_API (ROM_API->otpApiBase) + +/*! + * @} + */ /* end of group SDK_Compatibility_Symbols */ + + +#endif /* _LPC55S69_CM33_CORE1_H_ */ + diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/LPC55S69_cm33_core1.xml b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/LPC55S69_cm33_core1.xml new file mode 100644 index 000000000..edfadd570 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/LPC55S69_cm33_core1.xml @@ -0,0 +1,87406 @@ + + + nxp.com + LPC55S69_cm33_core1 + 1.0 + LPC55S69JBD100,LPC55S69JBD64,LPC55S69JET98 + +Copyright 2016-2019 NXP +All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + + + CM33 + r2p0 + little + false + false + true + 3 + false + + 8 + 32 + + + FLASH_CFPA0 + FLASH_CFPA + FLASH_CFPA + FLASH_CFPA + 0x9E000 + + 0 + 0x200 + registers + + + + HEADER + . + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + VERSION + . + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + S_FW_Version + Secure firmware version (Monotonic counter) + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + NS_FW_Version + Non-Secure firmware version (Monotonic counter) + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + IMAGE_KEY_REVOKE + Image key revocation ID (Monotonic counter) + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + ROTKH_REVOKE + . + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + RoTK0_EN + RoT Key 0 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked + 0 + 2 + read-write + + + RoTK1_EN + RoT Key 1 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked + 2 + 2 + read-write + + + RoTK2_EN + RoT Key 2 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked + 4 + 2 + read-write + + + + + VENDOR_USAGE + . + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + DBG_VENDOR_USAGE + DBG_VENDOR_USAGE. + 0 + 16 + read-write + + + INVERSE_VALUE + inverse value of bits [15:0] + 16 + 16 + read-write + + + + + DCFG_CC_SOCU_PIN + With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access. + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + NIDEN + Non Secure non-invasive debug enable + 0 + 1 + read-write + + + VALUE_0 + Use DAP to enable + 0 + + + VALUE_1 + Fixed state + 0x1 + + + + + DBGEN + Non Secure debug enable + 1 + 1 + read-write + + + VALUE_0 + Use DAP to enable + 0 + + + VALUE_1 + Fixed state + 0x1 + + + + + SPNIDEN + Secure non-invasive debug enable + 2 + 1 + read-write + + + VALUE_0 + Use DAP to enable + 0 + + + VALUE_1 + Fixed state + 0x1 + + + + + SPIDEN + Secure invasive debug enable + 3 + 1 + read-write + + + VALUE_0 + Use DAP to enable + 0 + + + VALUE_1 + Fixed state + 0x1 + + + + + TAPEN + JTAG TAP enable + 4 + 1 + read-write + + + VALUE_0 + Use DAP to enable + 0 + + + VALUE_1 + Fixed state + 0x1 + + + + + MCM33_DBGEN + Micro CM33 invasive debug enable + 5 + 1 + read-write + + + VALUE_0 + Use DAP to enable + 0 + + + VALUE_1 + Fixed state + 0x1 + + + + + ISP_CMD_EN + ISP Boot Command enable + 6 + 1 + read-write + + + VALUE_0 + Use DAP to enable + 0 + + + VALUE_1 + Fixed state + 0x1 + + + + + FA_CMD_EN + FA Command enable + 7 + 1 + read-write + + + VALUE_0 + Use DAP to enable + 0 + + + VALUE_1 + Fixed state + 0x1 + + + + + ME_CMD_EN + Flash Mass Erase Command enable + 8 + 1 + read-write + + + VALUE_0 + Use DAP to enable + 0 + + + VALUE_1 + Fixed state + 0x1 + + + + + MCM33_NIDEN + Micro CM33 non-invasive debug enable + 9 + 1 + read-write + + + VALUE_0 + Use DAP to enable + 0 + + + VALUE_1 + Fixed state + 0x1 + + + + + UUID_CHECK + Enforce UUID match during Debug authentication. + 15 + 1 + read-write + + + INVERSE_VALUE + inverse value of bits [15:0] + 16 + 16 + read-write + + + + + DCFG_CC_SOCU_DFLT + With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access. + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + NIDEN + Non Secure non-invasive debug fixed state + 0 + 1 + read-write + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + DBGEN + Non Secure debug fixed state + 1 + 1 + read-write + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + SPNIDEN + Secure non-invasive debug fixed state + 2 + 1 + read-write + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + SPIDEN + Secure invasive debug fixed state + 3 + 1 + read-write + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + TAPEN + JTAG TAP fixed state + 4 + 1 + read-write + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + MCM33_DBGEN + Micro CM33 invasive debug fixed state + 5 + 1 + read-write + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + ISP_CMD_EN + ISP Boot Command fixed state + 6 + 1 + read-write + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + FA_CMD_EN + FA Command fixed state + 7 + 1 + read-write + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + ME_CMD_EN + Flash Mass Erase Command fixed state + 8 + 1 + read-write + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + MCM33_NIDEN + Micro CM33 non-invasive debug fixed state + 9 + 1 + read-write + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + INVERSE_VALUE + inverse value of bits [15:0] + 16 + 16 + read-write + + + + + ENABLE_FA_MODE + Enable FA mode. SET_FA_MODE Command should write 0xC33CA55A to this word to indicate boot ROM to enter FA mode. + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + CMPA_PROG_IN_PROGRESS + CMPA Page programming on going. This field shall be set to 0x5CC55AA5 in the active CFPA page each time CMPA page programming is going on. It shall always be set to 0x00000000 in the CFPA scratch area. + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_IV_CODE0 + . + PRINCE_REGION0_IV_CODE + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_IV_HEADER0 + . + PRINCE_REGION0_IV_CODE + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_IV_CODE1 + . + PRINCE_REGION0_IV_CODE + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_IV_HEADER1 + . + PRINCE_REGION0_IV_CODE + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + TYPE + . + 0 + 2 + read-write + + + INDEX + . + 8 + 4 + read-write + + + SIZE + . + 24 + 6 + read-write + + + + + PRINCE_REGION0_IV_BODY0 + . + PRINCE_REGION0_IV_CODE + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_IV_CODE2 + . + PRINCE_REGION0_IV_CODE + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_IV_BODY1 + . + PRINCE_REGION0_IV_CODE + 0x3C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_IV_CODE3 + . + PRINCE_REGION0_IV_CODE + 0x3C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_IV_BODY2 + . + PRINCE_REGION0_IV_CODE + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_IV_CODE4 + . + PRINCE_REGION0_IV_CODE + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_IV_BODY3 + . + PRINCE_REGION0_IV_CODE + 0x44 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_IV_CODE5 + . + PRINCE_REGION0_IV_CODE + 0x44 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_IV_BODY4 + . + PRINCE_REGION0_IV_CODE + 0x48 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_IV_CODE6 + . + PRINCE_REGION0_IV_CODE + 0x48 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_IV_BODY5 + . + PRINCE_REGION0_IV_CODE + 0x4C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_IV_CODE7 + . + PRINCE_REGION0_IV_CODE + 0x4C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_IV_BODY6 + . + PRINCE_REGION0_IV_CODE + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_IV_CODE8 + . + PRINCE_REGION0_IV_CODE + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_IV_BODY7 + . + PRINCE_REGION0_IV_CODE + 0x54 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_IV_CODE9 + . + PRINCE_REGION0_IV_CODE + 0x54 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_IV_BODY8 + . + PRINCE_REGION0_IV_CODE + 0x58 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_IV_CODE10 + . + PRINCE_REGION0_IV_CODE + 0x58 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_IV_BODY9 + . + PRINCE_REGION0_IV_CODE + 0x5C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_IV_CODE11 + . + PRINCE_REGION0_IV_CODE + 0x5C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_IV_BODY10 + . + PRINCE_REGION0_IV_CODE + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_IV_CODE12 + . + PRINCE_REGION0_IV_CODE + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_IV_BODY11 + . + PRINCE_REGION0_IV_CODE + 0x64 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_IV_CODE13 + . + PRINCE_REGION0_IV_CODE + 0x64 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_IV_CODE0 + . + PRINCE_REGION1_IV_CODE + 0x68 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_IV_HEADER0 + . + PRINCE_REGION1_IV_CODE + 0x68 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_IV_CODE1 + . + PRINCE_REGION1_IV_CODE + 0x6C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_IV_HEADER1 + . + PRINCE_REGION1_IV_CODE + 0x6C + 32 + read-write + 0 + 0xFFFFFFFF + + + TYPE + . + 0 + 2 + read-write + + + INDEX + . + 8 + 4 + read-write + + + SIZE + . + 24 + 6 + read-write + + + + + PRINCE_REGION1_IV_BODY0 + . + PRINCE_REGION1_IV_CODE + 0x70 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_IV_CODE2 + . + PRINCE_REGION1_IV_CODE + 0x70 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_IV_BODY1 + . + PRINCE_REGION1_IV_CODE + 0x74 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_IV_CODE3 + . + PRINCE_REGION1_IV_CODE + 0x74 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_IV_BODY2 + . + PRINCE_REGION1_IV_CODE + 0x78 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_IV_CODE4 + . + PRINCE_REGION1_IV_CODE + 0x78 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_IV_BODY3 + . + PRINCE_REGION1_IV_CODE + 0x7C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_IV_CODE5 + . + PRINCE_REGION1_IV_CODE + 0x7C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_IV_BODY4 + . + PRINCE_REGION1_IV_CODE + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_IV_CODE6 + . + PRINCE_REGION1_IV_CODE + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_IV_BODY5 + . + PRINCE_REGION1_IV_CODE + 0x84 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_IV_CODE7 + . + PRINCE_REGION1_IV_CODE + 0x84 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_IV_BODY6 + . + PRINCE_REGION1_IV_CODE + 0x88 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_IV_CODE8 + . + PRINCE_REGION1_IV_CODE + 0x88 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_IV_BODY7 + . + PRINCE_REGION1_IV_CODE + 0x8C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_IV_CODE9 + . + PRINCE_REGION1_IV_CODE + 0x8C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_IV_BODY8 + . + PRINCE_REGION1_IV_CODE + 0x90 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_IV_CODE10 + . + PRINCE_REGION1_IV_CODE + 0x90 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_IV_BODY9 + . + PRINCE_REGION1_IV_CODE + 0x94 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_IV_CODE11 + . + PRINCE_REGION1_IV_CODE + 0x94 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_IV_BODY10 + . + PRINCE_REGION1_IV_CODE + 0x98 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_IV_CODE12 + . + PRINCE_REGION1_IV_CODE + 0x98 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_IV_BODY11 + . + PRINCE_REGION1_IV_CODE + 0x9C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_IV_CODE13 + . + PRINCE_REGION1_IV_CODE + 0x9C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_IV_CODE0 + . + PRINCE_REGION2_IV_CODE + 0xA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_IV_HEADER0 + . + PRINCE_REGION2_IV_CODE + 0xA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_IV_CODE1 + . + PRINCE_REGION2_IV_CODE + 0xA4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_IV_HEADER1 + . + PRINCE_REGION2_IV_CODE + 0xA4 + 32 + read-write + 0 + 0xFFFFFFFF + + + TYPE + . + 0 + 2 + read-write + + + INDEX + . + 8 + 4 + read-write + + + SIZE + . + 24 + 6 + read-write + + + + + PRINCE_REGION2_IV_BODY0 + . + PRINCE_REGION2_IV_CODE + 0xA8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_IV_CODE2 + . + PRINCE_REGION2_IV_CODE + 0xA8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_IV_BODY1 + . + PRINCE_REGION2_IV_CODE + 0xAC + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_IV_CODE3 + . + PRINCE_REGION2_IV_CODE + 0xAC + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_IV_BODY2 + . + PRINCE_REGION2_IV_CODE + 0xB0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_IV_CODE4 + . + PRINCE_REGION2_IV_CODE + 0xB0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_IV_BODY3 + . + PRINCE_REGION2_IV_CODE + 0xB4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_IV_CODE5 + . + PRINCE_REGION2_IV_CODE + 0xB4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_IV_BODY4 + . + PRINCE_REGION2_IV_CODE + 0xB8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_IV_CODE6 + . + PRINCE_REGION2_IV_CODE + 0xB8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_IV_BODY5 + . + PRINCE_REGION2_IV_CODE + 0xBC + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_IV_CODE7 + . + PRINCE_REGION2_IV_CODE + 0xBC + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_IV_BODY6 + . + PRINCE_REGION2_IV_CODE + 0xC0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_IV_CODE8 + . + PRINCE_REGION2_IV_CODE + 0xC0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_IV_BODY7 + . + PRINCE_REGION2_IV_CODE + 0xC4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_IV_CODE9 + . + PRINCE_REGION2_IV_CODE + 0xC4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_IV_BODY8 + . + PRINCE_REGION2_IV_CODE + 0xC8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_IV_CODE10 + . + PRINCE_REGION2_IV_CODE + 0xC8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_IV_BODY9 + . + PRINCE_REGION2_IV_CODE + 0xCC + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_IV_CODE11 + . + PRINCE_REGION2_IV_CODE + 0xCC + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_IV_BODY10 + . + PRINCE_REGION2_IV_CODE + 0xD0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_IV_CODE12 + . + PRINCE_REGION2_IV_CODE + 0xD0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_IV_BODY11 + . + PRINCE_REGION2_IV_CODE + 0xD4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_IV_CODE13 + . + PRINCE_REGION2_IV_CODE + 0xD4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + 56 + 0x4 + CUSTOMER_DEFINED[%s] + Customer Defined (Programable through ROM API) + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + 8 + 0x4 + SHA256_DIGEST[%s] + SHA256_DIGEST0 for DIGEST[31:0] SHA256_DIGEST1 for DIGEST[63:32] SHA256_DIGEST2 for DIGEST[95:64] SHA256_DIGEST3 for DIGEST[127:96] SHA256_DIGEST4 for DIGEST[159:128] SHA256_DIGEST5 for DIGEST[191:160] SHA256_DIGEST6 for DIGEST[223:192] SHA256_DIGEST7 for DIGEST[255:224] + 0x1E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + + + FLASH_CFPA_SCRATCH + FLASH_CFPA + FLASH_CFPA + 0x9DE00 + + 0 + 0x200 + registers + + + + FLASH_CFPA1 + FLASH_CFPA + FLASH_CFPA + 0x9E200 + + 0 + 0x200 + registers + + + + FLASH_CMPA + FLASH_CMPA + FLASH_CMPA + 0x9E400 + + 0 + 0x200 + registers + + + + BOOT_CFG + . + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DEFAULT_ISP_MODE + Default ISP mode: + 4 + 3 + read-write + + + VALUE_0 + Auto ISP + 0 + + + VALUE_1 + USB_HID_MSC + 0x1 + + + VALUE_2 + SPI Slave ISP + 0x2 + + + VALUE_3 + I2C Slave ISP + 0x3 + + + VALUE_7 + Disable ISP fall through + 0x7 + + + + + BOOT_SPEED + Core clock: + 7 + 2 + read-write + + + VALUE_0 + Defined by NMPA.SYSTEM_SPEED_CODE + 0 + + + VALUE_1 + 48MHz FRO + 0x1 + + + VALUE_2 + 96MHz FRO + 0x2 + + + + + BOOT_FAILURE_PIN + GPIO port and pin number to use for indicating failure reason. The toggle rate of the pin is used to decode the error type. [2:0] - Defines GPIO port [7:3] - Defines GPIO pin + 24 + 8 + read-write + + + + + SPI_FLASH_CFG + . + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + USB_ID + . + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + USB_VENDOR_ID + . + 0 + 16 + read-write + + + USB_PRODUCT_ID + . + 16 + 16 + read-write + + + + + SDIO_CFG + . + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + DCFG_CC_SOCU_PIN + . + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + NIDEN + Non Secure non-invasive debug enable + 0 + 1 + read-write + + + VALUE_0 + Use DAP to enable + 0 + + + VALUE_1 + Fixed state + 0x1 + + + + + DBGEN + Non Secure debug enable + 1 + 1 + read-write + + + VALUE_0 + Use DAP to enable + 0 + + + VALUE_1 + Fixed state + 0x1 + + + + + SPNIDEN + Secure non-invasive debug enable + 2 + 1 + read-write + + + VALUE_0 + Use DAP to enable + 0 + + + VALUE_1 + Fixed state + 0x1 + + + + + SPIDEN + Secure invasive debug enable + 3 + 1 + read-write + + + VALUE_0 + Use DAP to enable + 0 + + + VALUE_1 + Fixed state + 0x1 + + + + + TAPEN + JTAG TAP enable + 4 + 1 + read-write + + + VALUE_0 + Use DAP to enable + 0 + + + VALUE_1 + Fixed state + 0x1 + + + + + MCM33_DBGEN + Micro CM33 invasive debug enable + 5 + 1 + read-write + + + VALUE_0 + Use DAP to enable + 0 + + + VALUE_1 + Fixed state + 0x1 + + + + + ISP_CMD_EN + ISP Boot Command enable + 6 + 1 + read-write + + + VALUE_0 + Use DAP to enable + 0 + + + VALUE_1 + Fixed state + 0x1 + + + + + FA_CMD_EN + FA Command enable + 7 + 1 + read-write + + + VALUE_0 + Use DAP to enable + 0 + + + VALUE_1 + Fixed state + 0x1 + + + + + ME_CMD_EN + Flash Mass Erase Command enable + 8 + 1 + read-write + + + VALUE_0 + Use DAP to enable + 0 + + + VALUE_1 + Fixed state + 0x1 + + + + + MCM33_NIDEN + Micro CM33 non-invasive debug enable + 9 + 1 + read-write + + + VALUE_0 + Use DAP to enable + 0 + + + VALUE_1 + Fixed state + 0x1 + + + + + UUID_CHECK + Enforce UUID match during Debug authentication. + 15 + 1 + read-write + + + INVERSE_VALUE + inverse value of bits [15:0] + 16 + 16 + read-write + + + + + DCFG_CC_SOCU_DFLT + . + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + NIDEN + Non Secure non-invasive debug fixed state + 0 + 1 + read-write + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + DBGEN + Non Secure debug fixed state + 1 + 1 + read-write + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + SPNIDEN + Secure non-invasive debug fixed state + 2 + 1 + read-write + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + SPIDEN + Secure invasive debug fixed state + 3 + 1 + read-write + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + TAPEN + JTAG TAP fixed state + 4 + 1 + read-write + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + MCM33_DBGEN + Micro CM33 invasive debug fixed state + 5 + 1 + read-write + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + ISP_CMD_EN + ISP Boot Command fixed state + 6 + 1 + read-write + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + FA_CMD_EN + FA Command fixed state + 7 + 1 + read-write + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + ME_CMD_EN + Flash Mass Erase Command fixed state + 8 + 1 + read-write + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + MCM33_NIDEN + Micro CM33 non-invasive debug fixed state + 9 + 1 + read-write + + + DISABLE + Disable + 0 + + + ENABLE + Enable + 0x1 + + + + + INVERSE_VALUE + inverse value of bits [15:0] + 16 + 16 + read-write + + + + + DAP_VENDOR_USAGE_FIXED + . + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + VENDOR_USAGE + Upper 16 bits of vendor usage field defined in DAP. Lower 16-bits come from customer field area. + 16 + 16 + read-write + + + + + SECURE_BOOT_CFG + . + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + RSA4K + Use RSA4096 keys only. 00- RSA2048 keys 01, 10, 11 - RSA4096 keys + 0 + 2 + read-write + + + DICE_ENC_NXP_CFG + Include NXP area in DICE computation. 00 - not included 01, 10, 11 - included + 2 + 2 + read-write + + + DICE_CUST_CFG + Include Customer factory area (including keys) in DICE computation. 00 - not included 01, 10, 11 - included + 4 + 2 + read-write + + + SKIP_DICE + Skip DICE computation. 00 - Enable DICE 01,10,11 - Disable DICE + 6 + 2 + read-write + + + TZM_IMAGE_TYPE + TrustZone-M mode. 00 - TZM mode in image header. 01 - Disable TZ-M. Boots to NonSecure. 10 - TZ-M enable boots to secure mode. 11 - Preset TZM checker from image header. + 8 + 2 + read-write + + + BLOCK_SET_KEY + Block PUF key code generation. 00 - Enable Key code generation 01, 10, 11 - Disable key code generation + 10 + 2 + read-write + + + BLOCK_ENROLL + Block PUF enrollement. 00 - Enable enrollment mode 01, 10, 11 - Disable further enrollmnet + 12 + 2 + read-write + + + SEC_BOOT_EN + Secure boot enable. 00 - Plain image (internal flash with or without CRC) 01, 10, 11 - Boot signed images. (internal flash, RSA signed) + 30 + 2 + read-write + + + + + PRINCE_BASE_ADDR + . + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR0_PRG + Programmable portion of the base address of region 0. + 0 + 4 + read-write + + + ADDR1_PRG + Programmable portion of the base address of region 1. + 4 + 4 + read-write + + + ADDR2_PRG + Programmable portion of the base address of region 2. + 8 + 4 + read-write + + + LOCK_REG0 + Lock PRINCE region0 settings. 00 - Region is not locked. 01, 10, 11 - Region is locked. + 16 + 2 + read-write + + + LOCK_REG1 + Lock PRINCE region1 settings. 00 - Region is not locked. 01, 10, 11 - Region is locked. + 18 + 2 + read-write + + + LOCK_REG2 + Lock PRINCE region2 settings. 00 - Region is not locked. 01, 10, 11 - Region is locked. + 20 + 2 + read-write + + + REG0_ERASE_CHECK_EN + For PRINCE region0 enable checking whether all encrypted pages are erased together. 00 - Check is disabled. 01, 10, 11 - Check is enabled. + 24 + 2 + read-write + + + REG1_ERASE_CHECK_EN + For PRINCE region1 enable checking whether all encrypted pages are erased together. 00 - Check is disabled. 01, 10, 11 - Check is enabled. + 26 + 2 + read-write + + + REG2_ERASE_CHECK_EN + For PRINCE region2 enable checking whether all encrypted pages are erased together. 00 - Check is disabled. 01, 10, 11 - Check is enabled. + 28 + 2 + read-write + + + + + PRINCE_SR_0 + Region 0, sub-region enable + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_SR_1 + Region 1, sub-region enable + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_SR_2 + Region 2, sub-region enable + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + 8 + 0x4 + ROTKH[%s] + ROTKH0 for Root of Trust Keys Table hash[255:224] ROTKH1 for Root of Trust Keys Table hash[223:192] ROTKH2 for Root of Trust Keys Table hash[191:160] ROTKH3 for Root of Trust Keys Table hash[159:128] ROTKH4 for Root of Trust Keys Table hash[127:96] ROTKH5 for Root of Trust Keys Table hash[95:64] ROTKH6 for Root of Trust Keys Table hash[63:32] ROTKH7 for Root of Trust Keys Table hash[31:0] + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + 56 + 0x4 + CUSTOMER_DEFINED[%s] + Customer Defined (Programable through ROM API) + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + 8 + 0x4 + SHA256_DIGEST[%s] + SHA256_DIGEST0 for DIGEST[31:0] SHA256_DIGEST1 for DIGEST[63:32] SHA256_DIGEST2 for DIGEST[95:64] SHA256_DIGEST3 for DIGEST[127:96] SHA256_DIGEST4 for DIGEST[159:128] SHA256_DIGEST5 for DIGEST[191:160] SHA256_DIGEST6 for DIGEST[223:192] SHA256_DIGEST7 for DIGEST[255:224] + 0x1E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + + + FLASH_KEY_STORE + FLASH_KEY_STORE + FLASH_KEY_STORE + 0x9E600 + + 0 + 0x600 + registers + + + + HEADER + Valid Key Sore Header : 0x95959595 + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + puf_discharge_time_in_ms + puf discharge time in ms. + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + 298 + 0x4 + ACTIVATION_CODE[%s] + . + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + SBKEY_HEADER0 + . + SBKEY_KEY_CODE + 0x4B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + SBKEY_KEY_CODE0 + . + SBKEY_KEY_CODE + 0x4B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + SBKEY_HEADER1 + . + SBKEY_KEY_CODE + 0x4B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + TYPE + . + 0 + 2 + read-write + + + INDEX + . + 8 + 4 + read-write + + + SIZE + . + 24 + 6 + read-write + + + + + SBKEY_KEY_CODE1 + . + SBKEY_KEY_CODE + 0x4B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + SBKEY_BODY0 + . + SBKEY_KEY_CODE + 0x4B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + SBKEY_KEY_CODE2 + . + SBKEY_KEY_CODE + 0x4B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + SBKEY_BODY1 + . + SBKEY_KEY_CODE + 0x4BC + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + SBKEY_KEY_CODE3 + . + SBKEY_KEY_CODE + 0x4BC + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + SBKEY_BODY2 + . + SBKEY_KEY_CODE + 0x4C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + SBKEY_KEY_CODE4 + . + SBKEY_KEY_CODE + 0x4C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + SBKEY_BODY3 + . + SBKEY_KEY_CODE + 0x4C4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + SBKEY_KEY_CODE5 + . + SBKEY_KEY_CODE + 0x4C4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + SBKEY_BODY4 + . + SBKEY_KEY_CODE + 0x4C8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + SBKEY_KEY_CODE6 + . + SBKEY_KEY_CODE + 0x4C8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + SBKEY_BODY5 + . + SBKEY_KEY_CODE + 0x4CC + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + SBKEY_KEY_CODE7 + . + SBKEY_KEY_CODE + 0x4CC + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + SBKEY_BODY6 + . + SBKEY_KEY_CODE + 0x4D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + SBKEY_KEY_CODE8 + . + SBKEY_KEY_CODE + 0x4D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + SBKEY_BODY7 + . + SBKEY_KEY_CODE + 0x4D4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + SBKEY_KEY_CODE9 + . + SBKEY_KEY_CODE + 0x4D4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + SBKEY_BODY8 + . + SBKEY_KEY_CODE + 0x4D8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + SBKEY_KEY_CODE10 + . + SBKEY_KEY_CODE + 0x4D8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + SBKEY_BODY9 + . + SBKEY_KEY_CODE + 0x4DC + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + SBKEY_KEY_CODE11 + . + SBKEY_KEY_CODE + 0x4DC + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + SBKEY_BODY10 + . + SBKEY_KEY_CODE + 0x4E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + SBKEY_KEY_CODE12 + . + SBKEY_KEY_CODE + 0x4E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + SBKEY_BODY11 + . + SBKEY_KEY_CODE + 0x4E4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + SBKEY_KEY_CODE13 + . + SBKEY_KEY_CODE + 0x4E4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + USER_KEK_HEADER0 + . + USER_KEK_KEY_CODE + 0x4E8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + USER_KEK_KEY_CODE0 + . + USER_KEK_KEY_CODE + 0x4E8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + USER_KEK_HEADER1 + . + USER_KEK_KEY_CODE + 0x4EC + 32 + read-write + 0 + 0xFFFFFFFF + + + TYPE + . + 0 + 2 + read-write + + + INDEX + . + 8 + 4 + read-write + + + SIZE + . + 24 + 6 + read-write + + + + + USER_KEK_KEY_CODE1 + . + USER_KEK_KEY_CODE + 0x4EC + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + USER_KEK_BODY0 + . + USER_KEK_KEY_CODE + 0x4F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + USER_KEK_KEY_CODE2 + . + USER_KEK_KEY_CODE + 0x4F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + USER_KEK_BODY1 + . + USER_KEK_KEY_CODE + 0x4F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + USER_KEK_KEY_CODE3 + . + USER_KEK_KEY_CODE + 0x4F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + USER_KEK_BODY2 + . + USER_KEK_KEY_CODE + 0x4F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + USER_KEK_KEY_CODE4 + . + USER_KEK_KEY_CODE + 0x4F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + USER_KEK_BODY3 + . + USER_KEK_KEY_CODE + 0x4FC + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + USER_KEK_KEY_CODE5 + . + USER_KEK_KEY_CODE + 0x4FC + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + USER_KEK_BODY4 + . + USER_KEK_KEY_CODE + 0x500 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + USER_KEK_KEY_CODE6 + . + USER_KEK_KEY_CODE + 0x500 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + USER_KEK_BODY5 + . + USER_KEK_KEY_CODE + 0x504 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + USER_KEK_KEY_CODE7 + . + USER_KEK_KEY_CODE + 0x504 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + USER_KEK_BODY6 + . + USER_KEK_KEY_CODE + 0x508 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + USER_KEK_KEY_CODE8 + . + USER_KEK_KEY_CODE + 0x508 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + USER_KEK_BODY7 + . + USER_KEK_KEY_CODE + 0x50C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + USER_KEK_KEY_CODE9 + . + USER_KEK_KEY_CODE + 0x50C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + USER_KEK_BODY8 + . + USER_KEK_KEY_CODE + 0x510 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + USER_KEK_KEY_CODE10 + . + USER_KEK_KEY_CODE + 0x510 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + USER_KEK_BODY9 + . + USER_KEK_KEY_CODE + 0x514 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + USER_KEK_KEY_CODE11 + . + USER_KEK_KEY_CODE + 0x514 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + USER_KEK_BODY10 + . + USER_KEK_KEY_CODE + 0x518 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + USER_KEK_KEY_CODE12 + . + USER_KEK_KEY_CODE + 0x518 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + USER_KEK_BODY11 + . + USER_KEK_KEY_CODE + 0x51C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + USER_KEK_KEY_CODE13 + . + USER_KEK_KEY_CODE + 0x51C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + UDS_HEADER0 + . + UDS_KEY_CODE + 0x520 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + UDS_KEY_CODE0 + . + UDS_KEY_CODE + 0x520 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + UDS_HEADER1 + . + UDS_KEY_CODE + 0x524 + 32 + read-write + 0 + 0xFFFFFFFF + + + TYPE + . + 0 + 2 + read-write + + + INDEX + . + 8 + 4 + read-write + + + SIZE + . + 24 + 6 + read-write + + + + + UDS_KEY_CODE1 + . + UDS_KEY_CODE + 0x524 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + UDS_BODY0 + . + UDS_KEY_CODE + 0x528 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + UDS_KEY_CODE2 + . + UDS_KEY_CODE + 0x528 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + UDS_BODY1 + . + UDS_KEY_CODE + 0x52C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + UDS_KEY_CODE3 + . + UDS_KEY_CODE + 0x52C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + UDS_BODY2 + . + UDS_KEY_CODE + 0x530 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + UDS_KEY_CODE4 + . + UDS_KEY_CODE + 0x530 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + UDS_BODY3 + . + UDS_KEY_CODE + 0x534 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + UDS_KEY_CODE5 + . + UDS_KEY_CODE + 0x534 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + UDS_BODY4 + . + UDS_KEY_CODE + 0x538 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + UDS_KEY_CODE6 + . + UDS_KEY_CODE + 0x538 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + UDS_BODY5 + . + UDS_KEY_CODE + 0x53C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + UDS_KEY_CODE7 + . + UDS_KEY_CODE + 0x53C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + UDS_BODY6 + . + UDS_KEY_CODE + 0x540 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + UDS_KEY_CODE8 + . + UDS_KEY_CODE + 0x540 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + UDS_BODY7 + . + UDS_KEY_CODE + 0x544 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + UDS_KEY_CODE9 + . + UDS_KEY_CODE + 0x544 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + UDS_BODY8 + . + UDS_KEY_CODE + 0x548 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + UDS_KEY_CODE10 + . + UDS_KEY_CODE + 0x548 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + UDS_BODY9 + . + UDS_KEY_CODE + 0x54C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + UDS_KEY_CODE11 + . + UDS_KEY_CODE + 0x54C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + UDS_BODY10 + . + UDS_KEY_CODE + 0x550 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + UDS_KEY_CODE12 + . + UDS_KEY_CODE + 0x550 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + UDS_BODY11 + . + UDS_KEY_CODE + 0x554 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + UDS_KEY_CODE13 + . + UDS_KEY_CODE + 0x554 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_HEADER0 + . + PRINCE_REGION0_KEY_CODE + 0x558 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_KEY_CODE0 + . + PRINCE_REGION0_KEY_CODE + 0x558 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_HEADER1 + . + PRINCE_REGION0_KEY_CODE + 0x55C + 32 + read-write + 0 + 0xFFFFFFFF + + + TYPE + . + 0 + 2 + read-write + + + INDEX + . + 8 + 4 + read-write + + + SIZE + . + 24 + 6 + read-write + + + + + PRINCE_REGION0_KEY_CODE1 + . + PRINCE_REGION0_KEY_CODE + 0x55C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_BODY0 + . + PRINCE_REGION0_KEY_CODE + 0x560 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_KEY_CODE2 + . + PRINCE_REGION0_KEY_CODE + 0x560 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_BODY1 + . + PRINCE_REGION0_KEY_CODE + 0x564 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_KEY_CODE3 + . + PRINCE_REGION0_KEY_CODE + 0x564 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_BODY2 + . + PRINCE_REGION0_KEY_CODE + 0x568 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_KEY_CODE4 + . + PRINCE_REGION0_KEY_CODE + 0x568 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_BODY3 + . + PRINCE_REGION0_KEY_CODE + 0x56C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_KEY_CODE5 + . + PRINCE_REGION0_KEY_CODE + 0x56C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_BODY4 + . + PRINCE_REGION0_KEY_CODE + 0x570 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_KEY_CODE6 + . + PRINCE_REGION0_KEY_CODE + 0x570 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_BODY5 + . + PRINCE_REGION0_KEY_CODE + 0x574 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_KEY_CODE7 + . + PRINCE_REGION0_KEY_CODE + 0x574 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_BODY6 + . + PRINCE_REGION0_KEY_CODE + 0x578 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_KEY_CODE8 + . + PRINCE_REGION0_KEY_CODE + 0x578 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_BODY7 + . + PRINCE_REGION0_KEY_CODE + 0x57C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_KEY_CODE9 + . + PRINCE_REGION0_KEY_CODE + 0x57C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_BODY8 + . + PRINCE_REGION0_KEY_CODE + 0x580 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_KEY_CODE10 + . + PRINCE_REGION0_KEY_CODE + 0x580 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_BODY9 + . + PRINCE_REGION0_KEY_CODE + 0x584 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_KEY_CODE11 + . + PRINCE_REGION0_KEY_CODE + 0x584 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_BODY10 + . + PRINCE_REGION0_KEY_CODE + 0x588 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_KEY_CODE12 + . + PRINCE_REGION0_KEY_CODE + 0x588 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_BODY11 + . + PRINCE_REGION0_KEY_CODE + 0x58C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION0_KEY_CODE13 + . + PRINCE_REGION0_KEY_CODE + 0x58C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_HEADER0 + . + PRINCE_REGION1_KEY_CODE + 0x590 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_KEY_CODE0 + . + PRINCE_REGION1_KEY_CODE + 0x590 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_HEADER1 + . + PRINCE_REGION1_KEY_CODE + 0x594 + 32 + read-write + 0 + 0xFFFFFFFF + + + TYPE + . + 0 + 2 + read-write + + + INDEX + . + 8 + 4 + read-write + + + SIZE + . + 24 + 6 + read-write + + + + + PRINCE_REGION1_KEY_CODE1 + . + PRINCE_REGION1_KEY_CODE + 0x594 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_BODY0 + . + PRINCE_REGION1_KEY_CODE + 0x598 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_KEY_CODE2 + . + PRINCE_REGION1_KEY_CODE + 0x598 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_BODY1 + . + PRINCE_REGION1_KEY_CODE + 0x59C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_KEY_CODE3 + . + PRINCE_REGION1_KEY_CODE + 0x59C + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_BODY2 + . + PRINCE_REGION1_KEY_CODE + 0x5A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_KEY_CODE4 + . + PRINCE_REGION1_KEY_CODE + 0x5A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_BODY3 + . + PRINCE_REGION1_KEY_CODE + 0x5A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_KEY_CODE5 + . + PRINCE_REGION1_KEY_CODE + 0x5A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_BODY4 + . + PRINCE_REGION1_KEY_CODE + 0x5A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_KEY_CODE6 + . + PRINCE_REGION1_KEY_CODE + 0x5A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_BODY5 + . + PRINCE_REGION1_KEY_CODE + 0x5AC + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_KEY_CODE7 + . + PRINCE_REGION1_KEY_CODE + 0x5AC + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_BODY6 + . + PRINCE_REGION1_KEY_CODE + 0x5B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_KEY_CODE8 + . + PRINCE_REGION1_KEY_CODE + 0x5B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_BODY7 + . + PRINCE_REGION1_KEY_CODE + 0x5B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_KEY_CODE9 + . + PRINCE_REGION1_KEY_CODE + 0x5B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_BODY8 + . + PRINCE_REGION1_KEY_CODE + 0x5B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_KEY_CODE10 + . + PRINCE_REGION1_KEY_CODE + 0x5B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_BODY9 + . + PRINCE_REGION1_KEY_CODE + 0x5BC + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_KEY_CODE11 + . + PRINCE_REGION1_KEY_CODE + 0x5BC + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_BODY10 + . + PRINCE_REGION1_KEY_CODE + 0x5C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_KEY_CODE12 + . + PRINCE_REGION1_KEY_CODE + 0x5C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_BODY11 + . + PRINCE_REGION1_KEY_CODE + 0x5C4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION1_KEY_CODE13 + . + PRINCE_REGION1_KEY_CODE + 0x5C4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_HEADER0 + . + PRINCE_REGION2_KEY_CODE + 0x5C8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_KEY_CODE0 + . + PRINCE_REGION2_KEY_CODE + 0x5C8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_HEADER1 + . + PRINCE_REGION2_KEY_CODE + 0x5CC + 32 + read-write + 0 + 0xFFFFFFFF + + + TYPE + . + 0 + 2 + read-write + + + INDEX + . + 8 + 4 + read-write + + + SIZE + . + 24 + 6 + read-write + + + + + PRINCE_REGION2_KEY_CODE1 + . + PRINCE_REGION2_KEY_CODE + 0x5CC + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_BODY0 + . + PRINCE_REGION2_KEY_CODE + 0x5D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_KEY_CODE2 + . + PRINCE_REGION2_KEY_CODE + 0x5D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_BODY1 + . + PRINCE_REGION2_KEY_CODE + 0x5D4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_KEY_CODE3 + . + PRINCE_REGION2_KEY_CODE + 0x5D4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_BODY2 + . + PRINCE_REGION2_KEY_CODE + 0x5D8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_KEY_CODE4 + . + PRINCE_REGION2_KEY_CODE + 0x5D8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_BODY3 + . + PRINCE_REGION2_KEY_CODE + 0x5DC + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_KEY_CODE5 + . + PRINCE_REGION2_KEY_CODE + 0x5DC + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_BODY4 + . + PRINCE_REGION2_KEY_CODE + 0x5E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_KEY_CODE6 + . + PRINCE_REGION2_KEY_CODE + 0x5E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_BODY5 + . + PRINCE_REGION2_KEY_CODE + 0x5E4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_KEY_CODE7 + . + PRINCE_REGION2_KEY_CODE + 0x5E4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_BODY6 + . + PRINCE_REGION2_KEY_CODE + 0x5E8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_KEY_CODE8 + . + PRINCE_REGION2_KEY_CODE + 0x5E8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_BODY7 + . + PRINCE_REGION2_KEY_CODE + 0x5EC + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_KEY_CODE9 + . + PRINCE_REGION2_KEY_CODE + 0x5EC + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_BODY8 + . + PRINCE_REGION2_KEY_CODE + 0x5F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_KEY_CODE10 + . + PRINCE_REGION2_KEY_CODE + 0x5F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_BODY9 + . + PRINCE_REGION2_KEY_CODE + 0x5F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_KEY_CODE11 + . + PRINCE_REGION2_KEY_CODE + 0x5F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_BODY10 + . + PRINCE_REGION2_KEY_CODE + 0x5F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_KEY_CODE12 + . + PRINCE_REGION2_KEY_CODE + 0x5F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_BODY11 + . + PRINCE_REGION2_KEY_CODE + 0x5FC + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + PRINCE_REGION2_KEY_CODE13 + . + PRINCE_REGION2_KEY_CODE + 0x5FC + 32 + read-write + 0 + 0xFFFFFFFF + + + FIELD + . + 0 + 32 + read-write + + + + + + + SYSCON + SYSCON + SYSCON + 0x40000000 + + 0 + 0x1000 + registers + + + + MEMORYREMAP + Memory Remap control register + 0 + 32 + read-write + 0 + 0x3 + + + MAP + Select the location of the vector table :. + 0 + 2 + read-write + + + ROM0 + Vector Table in ROM. + 0 + + + RAM1 + Vector Table in RAM. + 0x1 + + + FLASH0 + Vector Table in Flash. + 0x2 + + + FLASH1 + Vector Table in Flash. + 0x3 + + + + + + + AHBMATPRIO + AHB Matrix priority control register Priority values are 3 = highest, 0 = lowest + 0x10 + 32 + read-write + 0 + 0x3FFFFFF + + + PRI_TEAL_CBUS + Teal C-AHB bus. + 0 + 2 + read-write + + + PRI_TEAL_SBUS + Teal S-AHB bus. + 2 + 2 + read-write + + + PRI_UTEAL_CBUS + Micro Teal C-AHB bus. + 4 + 2 + read-write + + + PRI_UTEAL_SBUS + Micro Teal S-AHB bus. + 6 + 2 + read-write + + + PRI_USB_FS + USB-FS.(USB0) + 8 + 2 + read-write + + + PRI_SDMA0 + DMA0 controller priority. + 10 + 2 + read-write + + + PRI_EZH_B_D + EZH B data bus. + 12 + 2 + read-write + + + PRI_EZH_B_I + EZH B instruction bus. + 14 + 2 + read-write + + + PRI_SDIO + SDIO. + 16 + 2 + read-write + + + PRI_PQ + PQ (Teal HW Accelerator). + 18 + 2 + read-write + + + PRI_SHA2 + SHA-2. + 20 + 2 + read-write + + + PRI_USB_HS + USB-HS.(USB1) + 22 + 2 + read-write + + + PRI_SDMA1 + DMA1 controller priority. + 24 + 2 + read-write + + + + + CPU0STCKCAL + System tick calibration for secure part of CPU0 + 0x38 + 32 + read-write + 0 + 0x3FFFFFF + + + CAL + System tick timer calibration value. + 0 + 24 + read-write + + + SKEW + Initial value for the Systick timer. + 24 + 1 + read-write + + + NOREF + Initial value for the Systick timer. + 25 + 1 + read-write + + + + + CPU0NSTCKCAL + System tick calibration for non-secure part of CPU0 + 0x3C + 32 + read-write + 0 + 0x3FFFFFF + + + CAL + System tick timer calibration value. + 0 + 24 + read-write + + + SKEW + Initial value for the Systick timer. + 24 + 1 + read-write + + + NOREF + Initial value for the Systick timer. + 25 + 1 + read-write + + + + + CPU1TCKCAL + System tick calibration for CPU1 + 0x40 + 32 + read-write + 0 + 0x3FFFFFF + + + CAL + System tick timer calibration value. + 0 + 24 + read-write + + + SKEW + Initial value for the Systick timer. + 24 + 1 + read-write + + + NOREF + Initial value for the Systick timer. + 25 + 1 + read-write + + + + + NMISRC + NMI Source Select + 0x48 + 32 + read-write + 0 + 0xC0003F3F + + + IRQCPU0 + The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for the CPU0, if enabled by NMIENCPU0. + 0 + 6 + read-write + + + IRQCPU1 + The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for the CPU1, if enabled by NMIENCPU1. + 8 + 6 + read-write + + + NMIENCPU1 + Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by IRQCPU1. + 30 + 1 + read-write + + + NMIENCPU0 + Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by IRQCPU0. + 31 + 1 + read-write + + + + + PRESETCTRL0 + Peripheral reset control 0 + PRESETCTRL + 0x100 + 32 + read-write + 0 + 0xCFFE9FA + + + ROM_RST + ROM reset control. + 1 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + SRAM_CTRL1_RST + SRAM Controller 1 reset control. + 3 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + SRAM_CTRL2_RST + SRAM Controller 2 reset control. + 4 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + SRAM_CTRL3_RST + SRAM Controller 3 reset control. + 5 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + SRAM_CTRL4_RST + SRAM Controller 4 reset control. + 6 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + FLASH_RST + Flash controller reset control. + 7 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + FMC_RST + FMC controller reset control. + 8 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + MUX0_RST + Input Mux 0 reset control. + 11 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + IOCON_RST + I/O controller reset control. + 13 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + GPIO0_RST + GPIO0 reset control. + 14 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + GPIO1_RST + GPIO1 reset control. + 15 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + GPIO2_RST + GPIO2 reset control. + 16 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + GPIO3_RST + GPIO3 reset control. + 17 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + PINT_RST + Pin interrupt (PINT) reset control. + 18 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + GINT_RST + Group interrupt (GINT) reset control. + 19 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + DMA0_RST + DMA0 reset control. + 20 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + CRCGEN_RST + CRCGEN reset control. + 21 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + WWDT_RST + Watchdog Timer reset control. + 22 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + RTC_RST + Real Time Clock (RTC) reset control. + 23 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + MAILBOX_RST + Inter CPU communication Mailbox reset control. + 26 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + ADC_RST + ADC reset control. + 27 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + + + PRESETCTRLX0 + Peripheral reset control register + PRESETCTRL + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + PRESETCTRL1 + Peripheral reset control 1 + PRESETCTRL + 0x104 + 32 + read-write + 0 + 0xDE57FC47 + + + MRT_RST + MRT reset control. + 0 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + OSTIMER0_RST + OS Timer 0 reset control. + 1 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + SCT0_RST + SCT0 reset control. + 2 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + SCTIPU_RST + SCTIPU reset control. + 6 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + UTICK0_RST + UTICK0 reset control. + 10 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + FC0_RST + FC0 reset control. + 11 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + FC1_RST + FC1 reset control. + 12 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + FC2_RST + FC2 reset control. + 13 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + FC3_RST + FC3 reset control. + 14 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + FC4_RST + FC4 reset control. + 15 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + FC5_RST + FC5 reset control. + 16 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + FC6_RST + FC6 reset control. + 17 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + FC7_RST + FC7 reset control. + 18 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + TIMER2_RST + Timer 2 reset control. + 22 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + USB0_DEV_RST + USB0 DEV reset control. + 25 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + TIMER0_RST + Timer 0 reset control. + 26 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + TIMER1_RST + Timer 1 reset control. + 27 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + PVT_RST + PVT reset control. + 28 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + EZHA_RST + EZH a reset control. + 30 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + EZHB_RST + EZH b reset control. + 31 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + + + PRESETCTRLX1 + Peripheral reset control register + PRESETCTRL + 0x104 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + PRESETCTRL2 + Peripheral reset control 2 + PRESETCTRL + 0x108 + 32 + read-write + 0 + 0x7FFF77FE + + + DMA1_RST + DMA1 reset control. + 1 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + COMP_RST + Comparator reset control. + 2 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + SDIO_RST + SDIO reset control. + 3 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + USB1_HOST_RST + USB1 Host reset control. + 4 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + USB1_DEV_RST + USB1 dev reset control. + 5 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + USB1_RAM_RST + USB1 RAM reset control. + 6 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + USB1_PHY_RST + USB1 PHY reset control. + 7 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + FREQME_RST + Frequency meter reset control. + 8 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + GPIO4_RST + GPIO4 reset control. + 9 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + GPIO5_RST + GPIO5 reset control. + 10 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + OTP_RST + OTP reset control. + 12 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + RNG_RST + RNG reset control. + 13 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + MUX1_RST + Peripheral Input Mux 1 reset control. + 14 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + USB0_HOSTM_RST + USB0 Host Master reset control. + 16 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + USB0_HOSTS_RST + USB0 Host Slave reset control. + 17 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + HASH0_RST + HASH0 reset control. + 18 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + PQ_RST + Power Quad reset control. + 19 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + PLULUT_RST + PLU LUT reset control. + 20 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + TIMER3_RST + Timer 3 reset control. + 21 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + TIMER4_RST + Timer 4 reset control. + 22 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + PUF_RST + PUF reset control reset control. + 23 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + CASPER_RST + Casper reset control. + 24 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + CAPT0_RST + CAPT0 reset control. + 25 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + ANALOG_CTRL_RST + analog control reset control. + 27 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + HS_LSPI_RST + HS LSPI reset control. + 28 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + GPIO_SEC_RST + GPIO secure reset control. + 29 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + GPIO_SEC_INT_RST + GPIO secure int reset control. + 30 + 1 + read-write + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Bloc is reset. + 0x1 + + + + + + + PRESETCTRLX2 + Peripheral reset control register + PRESETCTRL + 0x108 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + 3 + 0x4 + PRESETCTRLSET[%s] + Peripheral reset control set register + 0x120 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + 3 + 0x4 + PRESETCTRLCLR[%s] + Peripheral reset contro clearl register + 0x140 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + SWR_RESET + generate a software_reset + 0x160 + 32 + write-only + 0 + 0xFFFFFFFF + + + SWR_RESET + Write 0x5A00_0001 to generate a software_reset. + 0 + 32 + write-only + + + RELEASED + Bloc is not reset. + 0 + + + ASSERTED + Generate a software reset. + 0x5A000001 + + + + + + + AHBCLKCTRL0 + AHB Clock control 0 + AHBCLKCTRL + 0x200 + 32 + read-write + 0x180 + 0xCFFE9FA + + + ROM + Enables the clock for the ROM. + 1 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + SRAM_CTRL1 + Enables the clock for the SRAM Controller 1. + 3 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + SRAM_CTRL2 + Enables the clock for the SRAM Controller 2. + 4 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + SRAM_CTRL3 + Enables the clock for the SRAM Controller 3. + 5 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + SRAM_CTRL4 + Enables the clock for the SRAM Controller 4. + 6 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + FLASH + Enables the clock for the Flash controller. + 7 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + FMC + Enables the clock for the FMC controller. + 8 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + MUX0 + Enables the clock for the Input Mux 0. + 11 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + IOCON + Enables the clock for the I/O controller. + 13 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + GPIO0 + Enables the clock for the GPIO0. + 14 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + GPIO1 + Enables the clock for the GPIO1. + 15 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + GPIO2 + Enables the clock for the GPIO2. + 16 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + GPIO3 + Enables the clock for the GPIO3. + 17 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + PINT + Enables the clock for the Pin interrupt (PINT). + 18 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + GINT + Enables the clock for the Group interrupt (GINT). + 19 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + DMA0 + Enables the clock for the DMA0. + 20 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + CRCGEN + Enables the clock for the CRCGEN. + 21 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + WWDT + Enables the clock for the Watchdog Timer. + 22 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + RTC + Enables the clock for the Real Time Clock (RTC). + 23 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + MAILBOX + Enables the clock for the Inter CPU communication Mailbox. + 26 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + ADC + Enables the clock for the ADC. + 27 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + + + AHBCLKCTRLX0 + Peripheral reset control register + AHBCLKCTRL + 0x200 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + AHBCLKCTRL1 + AHB Clock control 1 + AHBCLKCTRL + 0x204 + 32 + read-write + 0 + 0xDE57FC47 + + + MRT + Enables the clock for the MRT. + 0 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + OSTIMER0 + Enables the clock for the OS Timer 0. + 1 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + SCT0 + Enables the clock for the SCT0. + 2 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + SCTIPU + Enables the clock for the SCTIPU. + 6 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + UTICK0 + Enables the clock for the UTICK0. + 10 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + FC0 + Enables the clock for the FC0. + 11 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + FC1 + Enables the clock for the FC1. + 12 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + FC2 + Enables the clock for the FC2. + 13 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + FC3 + Enables the clock for the FC3. + 14 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + FC4 + Enables the clock for the FC4. + 15 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + FC5 + Enables the clock for the FC5. + 16 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + FC6 + Enables the clock for the FC6. + 17 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + FC7 + Enables the clock for the FC7. + 18 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + TIMER2 + Enables the clock for the Timer 2. + 22 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + USB0_DEV + Enables the clock for the USB0 DEV. + 25 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + TIMER0 + Enables the clock for the Timer 0. + 26 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + TIMER1 + Enables the clock for the Timer 1. + 27 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + PVT + Enables the clock for the PVT. + 28 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + EZHA + Enables the clock for the EZH a. + 30 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + EZHB + Enables the clock for the EZH b. + 31 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + + + AHBCLKCTRLX1 + Peripheral reset control register + AHBCLKCTRL + 0x204 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + AHBCLKCTRL2 + AHB Clock control 2 + AHBCLKCTRL + 0x208 + 32 + read-write + 0 + 0x7FFF77FE + + + DMA1 + Enables the clock for the DMA1. + 1 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + COMP + Enables the clock for the Comparator. + 2 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + SDIO + Enables the clock for the SDIO. + 3 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + USB1_HOST + Enables the clock for the USB1 Host. + 4 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + USB1_DEV + Enables the clock for the USB1 dev. + 5 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + USB1_RAM + Enables the clock for the USB1 RAM. + 6 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + USB1_PHY + Enables the clock for the USB1 PHY. + 7 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + FREQME + Enables the clock for the Frequency meter. + 8 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + GPIO4 + Enables the clock for the GPIO4. + 9 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + GPIO5 + Enables the clock for the GPIO5. + 10 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + OTP + Enables the clock for the OTP. + 12 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + RNG + Enables the clock for the RNG. + 13 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + MUX1 + Enables the clock for the Peripheral Input Mux 1. + 14 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + USB0_HOSTM + Enables the clock for the USB0 Host Master. + 16 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + USB0_HOSTS + Enables the clock for the USB0 Host Slave. + 17 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + HASH0 + Enables the clock for the HASH0. + 18 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + PQ + Enables the clock for the Power Quad. + 19 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + PLULUT + Enables the clock for the PLU LUT. + 20 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + TIMER3 + Enables the clock for the Timer 3. + 21 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + TIMER4 + Enables the clock for the Timer 4. + 22 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + PUF + Enables the clock for the PUF reset control. + 23 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + CASPER + Enables the clock for the Casper. + 24 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + CAPT0 + Enables the clock for the CAPT0. + 25 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + ANALOG_CTRL + Enables the clock for the analog control. + 27 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + HS_LSPI + Enables the clock for the HS LSPI. + 28 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + GPIO_SEC + Enables the clock for the GPIO secure. + 29 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + GPIO_SEC_INT + Enables the clock for the GPIO secure int. + 30 + 1 + read-write + + + DISABLE + Disable Clock. + 0 + + + ENABLE + Enable Clock. + 0x1 + + + + + + + AHBCLKCTRLX2 + Peripheral reset control register + AHBCLKCTRL + 0x208 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + 3 + 0x4 + AHBCLKCTRLSET[%s] + Peripheral reset control register + 0x220 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + 3 + 0x4 + AHBCLKCTRLCLR[%s] + Peripheral reset control register + 0x240 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + SYSTICKCLKSEL0 + System Tick Timer for CPU0 source select + SYSTICKCLKSEL + 0x260 + 32 + read-write + 0x7 + 0x7 + + + SEL + System Tick Timer for CPU0 source select. + 0 + 3 + read-write + + + ENUM_0x0 + System Tick 0 divided clock. + 0 + + + ENUM_0x1 + FRO 1MHz clock. + 0x1 + + + ENUM_0x2 + Oscillator 32 kHz clock. + 0x2 + + + ENUM_0x3 + No clock. + 0x3 + + + ENUM_0x4 + No clock. + 0x4 + + + ENUM_0x5 + No clock. + 0x5 + + + ENUM_0x6 + No clock. + 0x6 + + + ENUM_0x7 + No clock. + 0x7 + + + + + + + SYSTICKCLKSELX0 + Peripheral reset control register + SYSTICKCLKSEL + 0x260 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + SYSTICKCLKSEL1 + System Tick Timer for CPU1 source select + SYSTICKCLKSEL + 0x264 + 32 + read-write + 0x7 + 0x7 + + + SEL + System Tick Timer for CPU1 source select. + 0 + 3 + read-write + + + ENUM_0x0 + System Tick 1 divided clock. + 0 + + + ENUM_0x1 + FRO 1MHz clock. + 0x1 + + + ENUM_0x2 + Oscillator 32 kHz clock. + 0x2 + + + ENUM_0x3 + No clock. + 0x3 + + + ENUM_0x4 + No clock. + 0x4 + + + ENUM_0x5 + No clock. + 0x5 + + + ENUM_0x6 + No clock. + 0x6 + + + ENUM_0x7 + No clock. + 0x7 + + + + + + + SYSTICKCLKSELX1 + Peripheral reset control register + SYSTICKCLKSEL + 0x264 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + TRACECLKSEL + Trace clock source select + 0x268 + 32 + read-write + 0x7 + 0x7 + + + SEL + Trace clock source select. + 0 + 3 + read-write + + + ENUM_0x0 + Trace divided clock. + 0 + + + ENUM_0x1 + FRO 1MHz clock. + 0x1 + + + ENUM_0x2 + Oscillator 32 kHz clock. + 0x2 + + + ENUM_0x3 + No clock. + 0x3 + + + ENUM_0x4 + No clock. + 0x4 + + + ENUM_0x5 + No clock. + 0x5 + + + ENUM_0x6 + No clock. + 0x6 + + + ENUM_0x7 + No clock. + 0x7 + + + + + + + CTIMERCLKSEL0 + CTimer 0 clock source select + CTIMERCLKSEL + 0x26C + 32 + read-write + 0x7 + 0x7 + + + SEL + CTimer 0 clock source select. + 0 + 3 + read-write + + + ENUM_0x0 + Main clock. + 0 + + + ENUM_0x1 + PLL0 clock. + 0x1 + + + ENUM_0x2 + No clock. + 0x2 + + + ENUM_0x3 + FRO 96 MHz clock. + 0x3 + + + ENUM_0x4 + FRO 1MHz clock. + 0x4 + + + ENUM_0x5 + MCLK clock. + 0x5 + + + ENUM_0x6 + Oscillator 32kHz clock. + 0x6 + + + ENUM_0x7 + No clock. + 0x7 + + + + + + + CTIMERCLKSELX0 + Peripheral reset control register + CTIMERCLKSEL + 0x26C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + CTIMERCLKSEL1 + CTimer 1 clock source select + CTIMERCLKSEL + 0x270 + 32 + read-write + 0x7 + 0x7 + + + SEL + CTimer 1 clock source select. + 0 + 3 + read-write + + + ENUM_0x0 + Main clock. + 0 + + + ENUM_0x1 + PLL0 clock. + 0x1 + + + ENUM_0x2 + No clock. + 0x2 + + + ENUM_0x3 + FRO 96 MHz clock. + 0x3 + + + ENUM_0x4 + FRO 1MHz clock. + 0x4 + + + ENUM_0x5 + MCLK clock. + 0x5 + + + ENUM_0x6 + Oscillator 32kHz clock. + 0x6 + + + ENUM_0x7 + No clock. + 0x7 + + + + + + + CTIMERCLKSELX1 + Peripheral reset control register + CTIMERCLKSEL + 0x270 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + CTIMERCLKSEL2 + CTimer 2 clock source select + CTIMERCLKSEL + 0x274 + 32 + read-write + 0x7 + 0x7 + + + SEL + CTimer 2 clock source select. + 0 + 3 + read-write + + + ENUM_0x0 + Main clock. + 0 + + + ENUM_0x1 + PLL0 clock. + 0x1 + + + ENUM_0x2 + No clock. + 0x2 + + + ENUM_0x3 + FRO 96 MHz clock. + 0x3 + + + ENUM_0x4 + FRO 1MHz clock. + 0x4 + + + ENUM_0x5 + MCLK clock. + 0x5 + + + ENUM_0x6 + Oscillator 32kHz clock. + 0x6 + + + ENUM_0x7 + No clock. + 0x7 + + + + + + + CTIMERCLKSELX2 + Peripheral reset control register + CTIMERCLKSEL + 0x274 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + CTIMERCLKSEL3 + CTimer 3 clock source select + CTIMERCLKSEL + 0x278 + 32 + read-write + 0x7 + 0x7 + + + SEL + CTimer 3 clock source select. + 0 + 3 + read-write + + + ENUM_0x0 + Main clock. + 0 + + + ENUM_0x1 + PLL0 clock. + 0x1 + + + ENUM_0x2 + No clock. + 0x2 + + + ENUM_0x3 + FRO 96 MHz clock. + 0x3 + + + ENUM_0x4 + FRO 1MHz clock. + 0x4 + + + ENUM_0x5 + MCLK clock. + 0x5 + + + ENUM_0x6 + Oscillator 32kHz clock. + 0x6 + + + ENUM_0x7 + No clock. + 0x7 + + + + + + + CTIMERCLKSELX3 + Peripheral reset control register + CTIMERCLKSEL + 0x278 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + CTIMERCLKSEL4 + CTimer 4 clock source select + CTIMERCLKSEL + 0x27C + 32 + read-write + 0x7 + 0x7 + + + SEL + CTimer 4 clock source select. + 0 + 3 + read-write + + + ENUM_0x0 + Main clock. + 0 + + + ENUM_0x1 + PLL0 clock. + 0x1 + + + ENUM_0x2 + No clock. + 0x2 + + + ENUM_0x3 + FRO 96 MHz clock. + 0x3 + + + ENUM_0x4 + FRO 1MHz clock. + 0x4 + + + ENUM_0x5 + MCLK clock. + 0x5 + + + ENUM_0x6 + Oscillator 32kHz clock. + 0x6 + + + ENUM_0x7 + No clock. + 0x7 + + + + + + + CTIMERCLKSELX4 + Peripheral reset control register + CTIMERCLKSEL + 0x27C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + MAINCLKSELA + Main clock A source select + 0x280 + 32 + read-write + 0 + 0x7 + + + SEL + Main clock A source select. + 0 + 3 + read-write + + + ENUM_0x0 + FRO 12 MHz clock. + 0 + + + ENUM_0x1 + CLKIN clock. + 0x1 + + + ENUM_0x2 + FRO 1MHz clock. + 0x2 + + + ENUM_0x3 + FRO 96 MHz clock. + 0x3 + + + ENUM_0x4 + No clock. + 0x4 + + + ENUM_0x5 + No clock. + 0x5 + + + ENUM_0x6 + No clock. + 0x6 + + + ENUM_0x7 + No clock. + 0x7 + + + + + + + MAINCLKSELB + Main clock source select + 0x284 + 32 + read-write + 0 + 0x7 + + + SEL + Main clock source select. + 0 + 3 + read-write + + + ENUM_0x0 + Main Clock A. + 0 + + + ENUM_0x1 + PLL0 clock. + 0x1 + + + ENUM_0x2 + PLL1 clock. + 0x2 + + + ENUM_0x3 + Oscillator 32 kHz clock. + 0x3 + + + ENUM_0x4 + No clock. + 0x4 + + + ENUM_0x5 + No clock. + 0x5 + + + ENUM_0x6 + No clock. + 0x6 + + + ENUM_0x7 + No clock. + 0x7 + + + + + + + CLKOUTSEL + CLKOUT clock source select + 0x288 + 32 + read-write + 0x7 + 0x7 + + + SEL + CLKOUT clock source select. + 0 + 3 + read-write + + + ENUM_0x0 + Main clock. + 0 + + + ENUM_0x1 + PLL0 clock. + 0x1 + + + ENUM_0x2 + CLKIN clock. + 0x2 + + + ENUM_0x3 + FRO 96 MHz clock. + 0x3 + + + ENUM_0x4 + FRO 1MHz clock. + 0x4 + + + ENUM_0x5 + PLL1 clock. + 0x5 + + + ENUM_0x6 + Oscillator 32kHz clock. + 0x6 + + + ENUM_0x7 + No clock. + 0x7 + + + + + + + PLL0CLKSEL + PLL0 clock source select + 0x290 + 32 + read-write + 0x7 + 0x7 + + + SEL + PLL0 clock source select. + 0 + 3 + read-write + + + ENUM_0x0 + FRO 12 MHz clock. + 0 + + + ENUM_0x1 + CLKIN clock. + 0x1 + + + ENUM_0x2 + FRO 1MHz clock. + 0x2 + + + ENUM_0x3 + Oscillator 32kHz clock. + 0x3 + + + ENUM_0x4 + No clock. + 0x4 + + + ENUM_0x5 + No clock. + 0x5 + + + ENUM_0x6 + No clock. + 0x6 + + + ENUM_0x7 + No clock. + 0x7 + + + + + + + PLL1CLKSEL + PLL1 clock source select + 0x294 + 32 + read-write + 0x7 + 0x7 + + + SEL + PLL1 clock source select. + 0 + 3 + read-write + + + ENUM_0x0 + FRO 12 MHz clock. + 0 + + + ENUM_0x1 + CLKIN clock. + 0x1 + + + ENUM_0x2 + FRO 1MHz clock. + 0x2 + + + ENUM_0x3 + Oscillator 32kHz clock. + 0x3 + + + ENUM_0x4 + No clock. + 0x4 + + + ENUM_0x5 + No clock. + 0x5 + + + ENUM_0x6 + No clock. + 0x6 + + + ENUM_0x7 + No clock. + 0x7 + + + + + + + ADCCLKSEL + ADC clock source select + 0x2A4 + 32 + read-write + 0x7 + 0x7 + + + SEL + ADC clock source select. + 0 + 3 + read-write + + + ENUM_0x0 + Main clock. + 0 + + + ENUM_0x1 + PLL0 clock. + 0x1 + + + ENUM_0x2 + FRO 96 MHz clock. + 0x2 + + + ENUM_0x3 + No clock. + 0x3 + + + ENUM_0x4 + No clock. + 0x4 + + + ENUM_0x5 + No clock. + 0x5 + + + ENUM_0x6 + No clock. + 0x6 + + + ENUM_0x7 + No clock. + 0x7 + + + + + + + USB0CLKSEL + FS USB clock source select + 0x2A8 + 32 + read-write + 0x7 + 0x7 + + + SEL + FS USB clock source select. + 0 + 3 + read-write + + + ENUM_0x0 + Main clock. + 0 + + + ENUM_0x1 + PLL0 clock. + 0x1 + + + ENUM_0x2 + No clock. + 0x2 + + + ENUM_0x3 + FRO 96 MHz clock. + 0x3 + + + ENUM_0x4 + No clock. + 0x4 + + + ENUM_0x5 + PLL1 clock. + 0x5 + + + ENUM_0x6 + No clock. + 0x6 + + + ENUM_0x7 + No clock. + 0x7 + + + + + + + USB1CLKSEL + HS USB clock source select - NOT USED + 0x2AC + 32 + read-write + 0x7 + 0x7 + + + SEL + HS USB clock source select. + 0 + 3 + read-write + + + ENUM_0x0 + Main clock. + 0 + + + ENUM_0x1 + PLL0 clock. + 0x1 + + + ENUM_0x2 + CLKIN clock. + 0x2 + + + ENUM_0x3 + No clock. + 0x3 + + + ENUM_0x4 + No clock. + 0x4 + + + ENUM_0x5 + PLL1 clock. + 0x5 + + + ENUM_0x6 + No clock. + 0x6 + + + ENUM_0x7 + No clock. + 0x7 + + + + + + + FCCLKSEL0 + Flexcomm Interface 0 clock source select for Fractional Rate Divider + FCCLKSEL + 0x2B0 + 32 + read-write + 0x7 + 0x7 + + + SEL + Flexcomm Interface 0 clock source select for Fractional Rate Divider. + 0 + 3 + read-write + + + ENUM_0x0 + Main clock. + 0 + + + ENUM_0x1 + system PLL divided clock. + 0x1 + + + ENUM_0x2 + FRO 12 MHz clock. + 0x2 + + + ENUM_0x3 + FRO 96 MHz clock. + 0x3 + + + ENUM_0x4 + FRO 1MHz clock. + 0x4 + + + ENUM_0x5 + MCLK clock. + 0x5 + + + ENUM_0x6 + Oscillator 32 kHz clock. + 0x6 + + + ENUM_0x7 + No clock. + 0x7 + + + + + + + FCCLKSELX0 + Peripheral reset control register + FCCLKSEL + 0x2B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + FCCLKSEL1 + Flexcomm Interface 1 clock source select for Fractional Rate Divider + FCCLKSEL + 0x2B4 + 32 + read-write + 0x7 + 0x7 + + + SEL + Flexcomm Interface 1 clock source select for Fractional Rate Divider. + 0 + 3 + read-write + + + ENUM_0x0 + Main clock. + 0 + + + ENUM_0x1 + system PLL divided clock. + 0x1 + + + ENUM_0x2 + FRO 12 MHz clock. + 0x2 + + + ENUM_0x3 + FRO 96 MHz clock. + 0x3 + + + ENUM_0x4 + FRO 1MHz clock. + 0x4 + + + ENUM_0x5 + MCLK clock. + 0x5 + + + ENUM_0x6 + Oscillator 32 kHz clock. + 0x6 + + + ENUM_0x7 + No clock. + 0x7 + + + + + + + FCCLKSELX1 + Peripheral reset control register + FCCLKSEL + 0x2B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + FCCLKSEL2 + Flexcomm Interface 2 clock source select for Fractional Rate Divider + FCCLKSEL + 0x2B8 + 32 + read-write + 0x7 + 0x7 + + + SEL + Flexcomm Interface 2 clock source select for Fractional Rate Divider. + 0 + 3 + read-write + + + ENUM_0x0 + Main clock. + 0 + + + ENUM_0x1 + system PLL divided clock. + 0x1 + + + ENUM_0x2 + FRO 12 MHz clock. + 0x2 + + + ENUM_0x3 + FRO 96 MHz clock. + 0x3 + + + ENUM_0x4 + FRO 1MHz clock. + 0x4 + + + ENUM_0x5 + MCLK clock. + 0x5 + + + ENUM_0x6 + Oscillator 32 kHz clock. + 0x6 + + + ENUM_0x7 + No clock. + 0x7 + + + + + + + FCCLKSELX2 + Peripheral reset control register + FCCLKSEL + 0x2B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + FCCLKSEL3 + Flexcomm Interface 3 clock source select for Fractional Rate Divider + FCCLKSEL + 0x2BC + 32 + read-write + 0x7 + 0x7 + + + SEL + Flexcomm Interface 3 clock source select for Fractional Rate Divider. + 0 + 3 + read-write + + + ENUM_0x0 + Main clock. + 0 + + + ENUM_0x1 + system PLL divided clock. + 0x1 + + + ENUM_0x2 + FRO 12 MHz clock. + 0x2 + + + ENUM_0x3 + FRO 96 MHz clock. + 0x3 + + + ENUM_0x4 + FRO 1MHz clock. + 0x4 + + + ENUM_0x5 + MCLK clock. + 0x5 + + + ENUM_0x6 + Oscillator 32 kHz clock. + 0x6 + + + ENUM_0x7 + No clock. + 0x7 + + + + + + + FCCLKSELX3 + Peripheral reset control register + FCCLKSEL + 0x2BC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + FCCLKSEL4 + Flexcomm Interface 4 clock source select for Fractional Rate Divider + FCCLKSEL + 0x2C0 + 32 + read-write + 0x7 + 0x7 + + + SEL + Flexcomm Interface 4 clock source select for Fractional Rate Divider. + 0 + 3 + read-write + + + ENUM_0x0 + Main clock. + 0 + + + ENUM_0x1 + system PLL divided clock. + 0x1 + + + ENUM_0x2 + FRO 12 MHz clock. + 0x2 + + + ENUM_0x3 + FRO 96 MHz clock. + 0x3 + + + ENUM_0x4 + FRO 1MHz clock. + 0x4 + + + ENUM_0x5 + MCLK clock. + 0x5 + + + ENUM_0x6 + Oscillator 32 kHz clock. + 0x6 + + + ENUM_0x7 + No clock. + 0x7 + + + + + + + FCCLKSELX4 + Peripheral reset control register + FCCLKSEL + 0x2C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + FCCLKSEL5 + Flexcomm Interface 5 clock source select for Fractional Rate Divider + FCCLKSEL + 0x2C4 + 32 + read-write + 0x7 + 0x7 + + + SEL + Flexcomm Interface 5 clock source select for Fractional Rate Divider. + 0 + 3 + read-write + + + ENUM_0x0 + Main clock. + 0 + + + ENUM_0x1 + system PLL divided clock. + 0x1 + + + ENUM_0x2 + FRO 12 MHz clock. + 0x2 + + + ENUM_0x3 + FRO 96 MHz clock. + 0x3 + + + ENUM_0x4 + FRO 1MHz clock. + 0x4 + + + ENUM_0x5 + MCLK clock. + 0x5 + + + ENUM_0x6 + Oscillator 32 kHz clock. + 0x6 + + + ENUM_0x7 + No clock. + 0x7 + + + + + + + FCCLKSELX5 + Peripheral reset control register + FCCLKSEL + 0x2C4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + FCCLKSEL6 + Flexcomm Interface 6 clock source select for Fractional Rate Divider + FCCLKSEL + 0x2C8 + 32 + read-write + 0x7 + 0x7 + + + SEL + Flexcomm Interface 6 clock source select for Fractional Rate Divider. + 0 + 3 + read-write + + + ENUM_0x0 + Main clock. + 0 + + + ENUM_0x1 + system PLL divided clock. + 0x1 + + + ENUM_0x2 + FRO 12 MHz clock. + 0x2 + + + ENUM_0x3 + FRO 96 MHz clock. + 0x3 + + + ENUM_0x4 + FRO 1MHz clock. + 0x4 + + + ENUM_0x5 + MCLK clock. + 0x5 + + + ENUM_0x6 + Oscillator 32 kHz clock. + 0x6 + + + ENUM_0x7 + No clock. + 0x7 + + + + + + + FCCLKSELX6 + Peripheral reset control register + FCCLKSEL + 0x2C8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + FCCLKSEL7 + Flexcomm Interface 7 clock source select for Fractional Rate Divider + FCCLKSEL + 0x2CC + 32 + read-write + 0x7 + 0x7 + + + SEL + Flexcomm Interface 7 clock source select for Fractional Rate Divider. + 0 + 3 + read-write + + + ENUM_0x0 + Main clock. + 0 + + + ENUM_0x1 + system PLL divided clock. + 0x1 + + + ENUM_0x2 + FRO 12 MHz clock. + 0x2 + + + ENUM_0x3 + FRO 96 MHz clock. + 0x3 + + + ENUM_0x4 + FRO 1MHz clock. + 0x4 + + + ENUM_0x5 + MCLK clock. + 0x5 + + + ENUM_0x6 + Oscillator 32 kHz clock. + 0x6 + + + ENUM_0x7 + No clock. + 0x7 + + + + + + + FCCLKSELX7 + Peripheral reset control register + FCCLKSEL + 0x2CC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + HSLSPICLKSEL + HS LSPI clock source select + 0x2D0 + 32 + read-write + 0x7 + 0x7 + + + SEL + HS LSPI clock source select. + 0 + 3 + read-write + + + ENUM_0x0 + Main clock. + 0 + + + ENUM_0x1 + system PLL divided clock. + 0x1 + + + ENUM_0x2 + FRO 12 MHz clock. + 0x2 + + + ENUM_0x3 + FRO 96 MHz clock. + 0x3 + + + ENUM_0x4 + FRO 1MHz clock. + 0x4 + + + ENUM_0x5 + No clock. + 0x5 + + + ENUM_0x6 + Oscillator 32 kHz clock. + 0x6 + + + ENUM_0x7 + No clock. + 0x7 + + + + + + + MCLKCLKSEL + MCLK clock source select + 0x2E0 + 32 + read-write + 0x7 + 0x7 + + + SEL + MCLK clock source select. + 0 + 3 + read-write + + + ENUM_0x0 + FRO 96 MHz clock. + 0 + + + ENUM_0x1 + PLL0 clock. + 0x1 + + + ENUM_0x2 + No clock. + 0x2 + + + ENUM_0x3 + No clock. + 0x3 + + + ENUM_0x4 + No clock. + 0x4 + + + ENUM_0x5 + No clock. + 0x5 + + + ENUM_0x6 + No clock. + 0x6 + + + ENUM_0x7 + No clock. + 0x7 + + + + + + + SCTCLKSEL + SCTimer/PWM clock source select + 0x2F0 + 32 + read-write + 0x7 + 0x7 + + + SEL + SCTimer/PWM clock source select. + 0 + 3 + read-write + + + ENUM_0x0 + Main clock. + 0 + + + ENUM_0x1 + PLL0 clock. + 0x1 + + + ENUM_0x2 + CLKIN clock. + 0x2 + + + ENUM_0x3 + FRO 96 MHz clock. + 0x3 + + + ENUM_0x4 + No clock. + 0x4 + + + ENUM_0x5 + MCLK clock. + 0x5 + + + ENUM_0x6 + No clock. + 0x6 + + + ENUM_0x7 + No clock. + 0x7 + + + + + + + SDIOCLKSEL + SDIO clock source select + 0x2F8 + 32 + read-write + 0x7 + 0x7 + + + SEL + SDIO clock source select. + 0 + 3 + read-write + + + ENUM_0x0 + Main clock. + 0 + + + ENUM_0x1 + PLL0 clock. + 0x1 + + + ENUM_0x2 + No clock. + 0x2 + + + ENUM_0x3 + FRO 96 MHz clock. + 0x3 + + + ENUM_0x4 + No clock. + 0x4 + + + ENUM_0x5 + PLL1 clock. + 0x5 + + + ENUM_0x6 + No clock. + 0x6 + + + ENUM_0x7 + No clock. + 0x7 + + + + + + + SYSTICKCLKDIV0 + System Tick Timer divider for CPU0 + 0x300 + 32 + read-write + 0x40000000 + 0xE00000FF + + + DIV + Clock divider value. + 0 + 8 + read-write + + + RESET + Resets the divider counter. + 29 + 1 + write-only + + + RELEASED + Divider is not reset. + 0 + + + ASSERTED + Divider is reset. + 0x1 + + + + + HALT + Halts the divider counter. + 30 + 1 + read-write + + + RUN + Divider clock is running. + 0 + + + HALT + Divider clock is stoped. + 0x1 + + + + + REQFLAG + Divider status flag. + 31 + 1 + read-only + + + STABLE + Divider clock is stable. + 0 + + + ONGOING + Clock frequency is not stable. + 0x1 + + + + + + + SYSTICKCLKDIV1 + System Tick Timer divider for CPU1 + 0x304 + 32 + read-write + 0x40000000 + 0xE00000FF + + + DIV + Clock divider value. + 0 + 8 + read-write + + + RESET + Resets the divider counter. + 29 + 1 + write-only + + + RELEASED + Divider is not reset. + 0 + + + ASSERTED + Divider is reset. + 0x1 + + + + + HALT + Halts the divider counter. + 30 + 1 + read-write + + + RUN + Divider clock is running. + 0 + + + HALT + Divider clock is stoped. + 0x1 + + + + + REQFLAG + Divider status flag. + 31 + 1 + read-only + + + STABLE + Divider clock is stable. + 0 + + + ONGOING + Clock frequency is not stable. + 0x1 + + + + + + + TRACECLKDIV + TRACE clock divider + 0x308 + 32 + read-write + 0x40000000 + 0xE00000FF + + + DIV + Clock divider value. + 0 + 8 + read-write + + + RESET + Resets the divider counter. + 29 + 1 + write-only + + + RELEASED + Divider is not reset. + 0 + + + ASSERTED + Divider is reset. + 0x1 + + + + + HALT + Halts the divider counter. + 30 + 1 + read-write + + + RUN + Divider clock is running. + 0 + + + HALT + Divider clock is stoped. + 0x1 + + + + + REQFLAG + Divider status flag. + 31 + 1 + read-only + + + STABLE + Divider clock is stable. + 0 + + + ONGOING + Clock frequency is not stable. + 0x1 + + + + + + + FLEXFRG0CTRL + Fractional rate divider for flexcomm 0 + FLEXFRGCTRL + 0x320 + 32 + read-write + 0xFF + 0xFFFF + + + DIV + Denominator of the fractional rate divider. + 0 + 8 + read-write + + + MULT + Numerator of the fractional rate divider. + 8 + 8 + read-write + + + + + FLEXFRGXCTRL0 + Peripheral reset control register + FLEXFRGCTRL + 0x320 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + FLEXFRG1CTRL + Fractional rate divider for flexcomm 1 + FLEXFRGCTRL + 0x324 + 32 + read-write + 0xFF + 0xFFFF + + + DIV + Denominator of the fractional rate divider. + 0 + 8 + read-write + + + MULT + Numerator of the fractional rate divider. + 8 + 8 + read-write + + + + + FLEXFRGXCTRL1 + Peripheral reset control register + FLEXFRGCTRL + 0x324 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + FLEXFRG2CTRL + Fractional rate divider for flexcomm 2 + FLEXFRGCTRL + 0x328 + 32 + read-write + 0xFF + 0xFFFF + + + DIV + Denominator of the fractional rate divider. + 0 + 8 + read-write + + + MULT + Numerator of the fractional rate divider. + 8 + 8 + read-write + + + + + FLEXFRGXCTRL2 + Peripheral reset control register + FLEXFRGCTRL + 0x328 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + FLEXFRG3CTRL + Fractional rate divider for flexcomm 3 + FLEXFRGCTRL + 0x32C + 32 + read-write + 0xFF + 0xFFFF + + + DIV + Denominator of the fractional rate divider. + 0 + 8 + read-write + + + MULT + Numerator of the fractional rate divider. + 8 + 8 + read-write + + + + + FLEXFRGXCTRL3 + Peripheral reset control register + FLEXFRGCTRL + 0x32C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + FLEXFRG4CTRL + Fractional rate divider for flexcomm 4 + FLEXFRGCTRL + 0x330 + 32 + read-write + 0xFF + 0xFFFF + + + DIV + Denominator of the fractional rate divider. + 0 + 8 + read-write + + + MULT + Numerator of the fractional rate divider. + 8 + 8 + read-write + + + + + FLEXFRGXCTRL4 + Peripheral reset control register + FLEXFRGCTRL + 0x330 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + FLEXFRG5CTRL + Fractional rate divider for flexcomm 5 + FLEXFRGCTRL + 0x334 + 32 + read-write + 0xFF + 0xFFFF + + + DIV + Denominator of the fractional rate divider. + 0 + 8 + read-write + + + MULT + Numerator of the fractional rate divider. + 8 + 8 + read-write + + + + + FLEXFRGXCTRL5 + Peripheral reset control register + FLEXFRGCTRL + 0x334 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + FLEXFRG6CTRL + Fractional rate divider for flexcomm 6 + FLEXFRGCTRL + 0x338 + 32 + read-write + 0xFF + 0xFFFF + + + DIV + Denominator of the fractional rate divider. + 0 + 8 + read-write + + + MULT + Numerator of the fractional rate divider. + 8 + 8 + read-write + + + + + FLEXFRGXCTRL6 + Peripheral reset control register + FLEXFRGCTRL + 0x338 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + FLEXFRG7CTRL + Fractional rate divider for flexcomm 7 + FLEXFRGCTRL + 0x33C + 32 + read-write + 0xFF + 0xFFFF + + + DIV + Denominator of the fractional rate divider. + 0 + 8 + read-write + + + MULT + Numerator of the fractional rate divider. + 8 + 8 + read-write + + + + + FLEXFRGXCTRL7 + Peripheral reset control register + FLEXFRGCTRL + 0x33C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data array value + 0 + 32 + read-write + + + + + AHBCLKDIV + System clock divider + 0x380 + 32 + read-write + 0 + 0xE00000FF + + + DIV + Clock divider value. + 0 + 8 + read-write + + + RESET + Resets the divider counter. + 29 + 1 + write-only + + + RELEASED + Divider is not reset. + 0 + + + ASSERTED + Divider is reset. + 0x1 + + + + + HALT + Halts the divider counter. + 30 + 1 + read-write + + + RUN + Divider clock is running. + 0 + + + HALT + Divider clock is stoped. + 0x1 + + + + + REQFLAG + Divider status flag. + 31 + 1 + read-only + + + STABLE + Divider clock is stable. + 0 + + + ONGOING + Clock frequency is not stable. + 0x1 + + + + + + + CLKOUTDIV + CLKOUT clock divider + 0x384 + 32 + read-write + 0x40000000 + 0xE00000FF + + + DIV + Clock divider value. + 0 + 8 + read-write + + + RESET + Resets the divider counter. + 29 + 1 + write-only + + + RELEASED + Divider is not reset. + 0 + + + ASSERTED + Divider is reset. + 0x1 + + + + + HALT + Halts the divider counter. + 30 + 1 + read-write + + + RUN + Divider clock is running. + 0 + + + HALT + Divider clock is stoped. + 0x1 + + + + + REQFLAG + Divider status flag. + 31 + 1 + read-only + + + STABLE + Divider clock is stable. + 0 + + + ONGOING + Clock frequency is not stable. + 0x1 + + + + + + + FROHFDIV + FRO_HF (96MHz) clock divider + 0x388 + 32 + read-write + 0x40000000 + 0xE00000FF + + + DIV + Clock divider value. + 0 + 8 + read-write + + + RESET + Resets the divider counter. + 29 + 1 + write-only + + + RELEASED + Divider is not reset. + 0 + + + ASSERTED + Divider is reset. + 0x1 + + + + + HALT + Halts the divider counter. + 30 + 1 + read-write + + + RUN + Divider clock is running. + 0 + + + HALT + Divider clock is stoped. + 0x1 + + + + + REQFLAG + Divider status flag. + 31 + 1 + read-only + + + STABLE + Divider clock is stable. + 0 + + + ONGOING + Clock frequency is not stable. + 0x1 + + + + + + + WDTCLKDIV + WDT clock divider + 0x38C + 32 + read-write + 0x40000000 + 0xE000003F + + + DIV + Clock divider value. + 0 + 6 + read-write + + + RESET + Resets the divider counter. + 29 + 1 + write-only + + + RELEASED + Divider is not reset. + 0 + + + ASSERTED + Divider is reset. + 0x1 + + + + + HALT + Halts the divider counter. + 30 + 1 + read-write + + + RUN + Divider clock is running. + 0 + + + HALT + Divider clock is stoped. + 0x1 + + + + + REQFLAG + Divider status flag. + 31 + 1 + read-only + + + STABLE + Divider clock is stable. + 0 + + + ONGOING + Clock frequency is not stable. + 0x1 + + + + + + + ADCCLKDIV + ADC clock divider + 0x394 + 32 + read-write + 0x40000000 + 0xE0000007 + + + DIV + Clock divider value. + 0 + 3 + read-write + + + RESET + Resets the divider counter. + 29 + 1 + write-only + + + RELEASED + Divider is not reset. + 0 + + + ASSERTED + Divider is reset. + 0x1 + + + + + HALT + Halts the divider counter. + 30 + 1 + read-write + + + RUN + Divider clock is running. + 0 + + + HALT + Divider clock is stoped. + 0x1 + + + + + REQFLAG + Divider status flag. + 31 + 1 + read-only + + + STABLE + Divider clock is stable. + 0 + + + ONGOING + Clock frequency is not stable. + 0x1 + + + + + + + USB0CLKDIV + USB0 Clock divider + 0x398 + 32 + read-write + 0x40000000 + 0xE00000FF + + + DIV + Clock divider value. + 0 + 8 + read-write + + + RESET + Resets the divider counter. + 29 + 1 + write-only + + + RELEASED + Divider is not reset. + 0 + + + ASSERTED + Divider is reset. + 0x1 + + + + + HALT + Halts the divider counter. + 30 + 1 + read-write + + + RUN + Divider clock is running. + 0 + + + HALT + Divider clock is stoped. + 0x1 + + + + + REQFLAG + Divider status flag. + 31 + 1 + read-only + + + STABLE + Divider clock is stable. + 0 + + + ONGOING + Clock frequency is not stable. + 0x1 + + + + + + + MCLKDIV + I2S MCLK clock divider + 0x3AC + 32 + read-write + 0x40000000 + 0xE00000FF + + + DIV + Clock divider value. + 0 + 8 + read-write + + + RESET + Resets the divider counter. + 29 + 1 + write-only + + + RELEASED + Divider is not reset. + 0 + + + ASSERTED + Divider is reset. + 0x1 + + + + + HALT + Halts the divider counter. + 30 + 1 + read-write + + + RUN + Divider clock is running. + 0 + + + HALT + Divider clock is stoped. + 0x1 + + + + + REQFLAG + Divider status flag. + 31 + 1 + read-only + + + STABLE + Divider clock is stable. + 0 + + + ONGOING + Clock frequency is not stable. + 0x1 + + + + + + + SCTCLKDIV + SCT/PWM clock divider + 0x3B4 + 32 + read-write + 0x40000000 + 0xE00000FF + + + DIV + Clock divider value. + 0 + 8 + read-write + + + RESET + Resets the divider counter. + 29 + 1 + write-only + + + RELEASED + Divider is not reset. + 0 + + + ASSERTED + Divider is reset. + 0x1 + + + + + HALT + Halts the divider counter. + 30 + 1 + read-write + + + RUN + Divider clock is running. + 0 + + + HALT + Divider clock is stoped. + 0x1 + + + + + REQFLAG + Divider status flag. + 31 + 1 + read-only + + + STABLE + Divider clock is stable. + 0 + + + ONGOING + Clock frequency is not stable. + 0x1 + + + + + + + SDIOCLKDIV + SDIO clock divider + 0x3BC + 32 + read-write + 0x40000000 + 0xE00000FF + + + DIV + Clock divider value. + 0 + 8 + read-write + + + RESET + Resets the divider counter. + 29 + 1 + write-only + + + RELEASED + Divider is not reset. + 0 + + + ASSERTED + Divider is reset. + 0x1 + + + + + HALT + Halts the divider counter. + 30 + 1 + read-write + + + RUN + Divider clock is running. + 0 + + + HALT + Divider clock is stoped. + 0x1 + + + + + REQFLAG + Divider status flag. + 31 + 1 + read-only + + + STABLE + Divider clock is stable. + 0 + + + ONGOING + Clock frequency is not stable. + 0x1 + + + + + + + PLL0CLKDIV + PLL0 clock divider + 0x3C4 + 32 + read-write + 0x40000000 + 0xE00000FF + + + DIV + Clock divider value. + 0 + 8 + read-write + + + RESET + Resets the divider counter. + 29 + 1 + write-only + + + RELEASED + Divider is not reset. + 0 + + + ASSERTED + Divider is reset. + 0x1 + + + + + HALT + Halts the divider counter. + 30 + 1 + read-write + + + RUN + Divider clock is running. + 0 + + + HALT + Divider clock is stoped. + 0x1 + + + + + REQFLAG + Divider status flag. + 31 + 1 + read-only + + + STABLE + Divider clock is stable. + 0 + + + ONGOING + Clock frequency is not stable. + 0x1 + + + + + + + CLOCKGENUPDATELOCKOUT + Control clock configuration registers access (like xxxDIV, xxxSEL) + 0x3FC + 32 + read-write + 0 + 0xFFFFFFFF + + + CLOCKGENUPDATELOCKOUT + Control clock configuration registers access (like xxxDIV, xxxSEL). + 0 + 32 + read-write + + + FREEZE + all hardware clock configruration are freeze. + 0 + + + ENABLE + update all clock configuration. + 0x1 + + + + + + + FMCCR + FMC configuration register - INTERNAL USE ONLY + 0x400 + 32 + read-write + 0x3000 + 0xFFFFFFFF + + + FETCHCTL + Fetch control + 0 + 2 + read-write + + + NOBUF + No buffering (bypass always used) for Fetch cycles + 0 + + + ONEBUF + One buffer is used for all Fetch cycles + 0x1 + + + ALLBUF + All buffers can be used for Fetch cycles + 0x2 + + + + + DATACTL + Data control + 2 + 2 + read-write + + + NOBUF + No buffering (bypass always used) for Data cycles + 0 + + + ONEBUF + One buffer is used for all Data cycles + 0x1 + + + ALLBUF + All buffers can be used for Data cycles + 0x2 + + + + + ACCEL + ACCEL + 4 + 1 + read-write + + + PREFEN + Pref enable + 5 + 1 + read-write + + + PREFOVR + Pref ovr + 6 + 1 + read-write + + + PREFCRI + Pref CRI + 8 + 3 + read-write + + + FMCTIM + TMC time + 12 + 5 + read-write + + + PFISLRU + When set, prefetch uses LRU buffer replacement policy + 17 + 1 + read-write + + + PFADAP + When set, prefetch will adaptively select between parent and LRU buffer replacement policies. + 18 + 1 + read-write + + + + + USB0CLKCTRL + USB0 clock control + 0x40C + 32 + read-write + 0 + 0x1F + + + AP_FS_DEV_CLK + USB0 Device USB0_NEEDCLK signal control:. + 0 + 1 + read-write + + + HW_CTRL + Under hardware control. + 0 + + + FORCED + Forced high. + 0x1 + + + + + POL_FS_DEV_CLK + USB0 Device USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt:. + 1 + 1 + read-write + + + FALLING + Falling edge of device USB0_NEEDCLK triggers wake-up. + 0 + + + RISING + Rising edge of device USB0_NEEDCLK triggers wake-up. + 0x1 + + + + + AP_FS_HOST_CLK + USB0 Host USB0_NEEDCLK signal control:. + 2 + 1 + read-write + + + HW_CTRL + Under hardware control. + 0 + + + FORCED + Forced high. + 0x1 + + + + + POL_FS_HOST_CLK + USB0 Host USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt:. + 3 + 1 + read-write + + + FALLING + Falling edge of device USB0_NEEDCLK triggers wake-up. + 0 + + + RISING + Rising edge of device USB0_NEEDCLK triggers wake-up. + 0x1 + + + + + PU_DISABLE + Internal pull-up disable control. + 4 + 1 + read-write + + + ENABLE + Internal pull-up enable. + 0 + + + DISABLE + Internal pull-up disable. + 0x1 + + + + + + + USB0CLKSTAT + USB0 clock status + 0x410 + 32 + read-write + 0 + 0x3 + + + DEV_NEED_CLKST + USB0 Device USB0_NEEDCLK signal status:. + 0 + 1 + read-only + + + LOW + USB0 Device clock is low. + 0 + + + HIGH + USB0 Device clock is high. + 0x1 + + + + + HOST_NEED_CLKST + USB0 Host USB0_NEEDCLK signal status:. + 1 + 1 + read-only + + + LOW + USB0 Host clock is low. + 0 + + + HIGH + USB0 Host clock is high. + 0x1 + + + + + + + FMCFLUSH + FMCflush control + 0x41C + 32 + write-only + 0 + 0xFFFFFFFF + + + FLUSH + no description available + 0 + 1 + write-only + + + + + MCLKIO + MCLK control + 0x420 + 32 + read-write + 0 + 0xFFFFFFFF + + + MCLKIO + MCLK control. + 0 + 32 + read-write + + + INPUT + input mode. + 0 + + + OUTPUT + output mode. + 0x1 + + + + + + + USB1CLKCTRL + USB1 clock control + 0x424 + 32 + read-write + 0x10 + 0x1F + + + AP_HS_DEV_CLK + USB1 Device need_clock signal control:. + 0 + 1 + read-write + + + HW_CTRL + Under hardware control. + 0 + + + FORCED + Forced high. + 0x1 + + + + + POL_HS_DEV_CLK + USB1 Device need_clock polarity for triggering the USB1 wake-up interrupt:. + 1 + 1 + read-write + + + FALLING + Falling edge of device need_clock triggers wake-up. + 0 + + + RISING + Rising edge of device need_clock triggers wake-up. + 0x1 + + + + + AP_HS_HOST_CLK + USB1 Host need_clock signal control:. + 2 + 1 + read-write + + + HW_CTRL + Under hardware control. + 0 + + + FORCED + Forced high. + 0x1 + + + + + POL_HS_HOST_CLK + USB1 Host need_clock polarity for triggering the USB1 wake-up interrupt: 0 Falling edge of device need_clock triggers wake-up. + 3 + 1 + read-write + + + FALLING + Falling edge of device need_clock triggers wake-up. + 0 + + + RISING + Rising edge of device need_clock triggers wake-up. + 0x1 + + + + + HS_DEV_WAKEUP_N + External user wake-up signal for device mode; asserting this signal (active low) will result in exiting the low power mode; input to synchronous control logic:. + 4 + 1 + read-write + + + FORCE_WUP + Forces USB1 PHY to wake-up. + 0 + + + NORMAL_WUP + Normal USB1 PHY behavior. + 0x1 + + + + + + + USB1CLKSTAT + USB1 clock status + 0x428 + 32 + read-write + 0 + 0x3 + + + DEV_NEED_CLKST + USB1 Device need_clock signal status:. + 0 + 1 + read-only + + + LOW + USB1 Device clock is low. + 0 + + + HIGH + USB1 Device clock is high. + 0x1 + + + + + HOST_NEED_CLKST + USB1 Host need_clock signal status:. + 1 + 1 + read-only + + + LOW + USB1 Host clock is low. + 0 + + + HIGH + USB1 Host clock is high. + 0x1 + + + + + + + FLASHBANKENABLE + Flash Banks control + 0x450 + 32 + read-write + 0 + 0xFFF + + + BANK0 + Flash Bank0 control. + 0 + 4 + read-write + + + ENABLE + Flash BANK0 checker is enabled (all Flash pages inside this bank cannot be erased nor programmed). + 0 + + + DISABLE + 1010: Flash BANK0 checker is disabled (all Flash pages inside this bank can be erased and programmed). + 0xA + + + + + BANK1 + Flash Bank1 control. + 4 + 4 + read-write + + + ENABLE + Flash BANK1 checker is enabled (all Flash pages inside this bank cannot be erased nor programmed). + 0 + + + DISABLE + 1010: Flash BANK1 checker is disabled (all Flash pages inside this bank can be erased and programmed). + 0xA + + + + + BANK2 + Flash Bank2 control. + 8 + 4 + read-write + + + ENABLE + Flash BANK2 checker is enabled (all Flash pages inside this bank cannot be erased nor programmed). + 0 + + + DISABLE + 1010: Flash BANK2 checker is disabled (all Flash pages inside this bank can be erased and programmed). + 0xA + + + + + + + SDIOCLKCTRL + SDIO CCLKIN phase and delay control + 0x460 + 32 + read-write + 0 + 0x9F9F008F + + + CCLK_DRV_PHASE + Programmable delay value by which cclk_in_drv is phase-shifted with regard to cclk_in. + 0 + 2 + read-write + + + ENUM_0_DEG + 0 degree shift. + 0 + + + ENUM_90_DEG + 90 degree shift. + 0x1 + + + ENUM_180_DEG + 180 degree shift. + 0x2 + + + ENUM_270_DEG + 270 degree shift. + 0x3 + + + + + CCLK_SAMPLE_PHASE + Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in. + 2 + 2 + read-write + + + ENUM_0_DEG + 0 degree shift. + 0 + + + ENUM_90_DEG + 90 degree shift. + 0x1 + + + ENUM_180_DEG + 180 degree shift. + 0x2 + + + ENUM_270_DEG + 270 degree shift. + 0x3 + + + + + PHASE_ACTIVE + Enables the delays CCLK_DRV_PHASE and CCLK_SAMPLE_PHASE. + 7 + 1 + read-write + + + BYPASSED + Bypassed. + 0 + + + PH_SHIFT + Activates phase shift logic. When active, the clock divider is active and phase delays are enabled. + 0x1 + + + + + CCLK_DRV_DELAY + Programmable delay value by which cclk_in_drv is delayed with regard to cclk_in. + 16 + 5 + read-write + + + CCLK_DRV_DELAY_ACTIVE + Enables drive delay, as controlled by the CCLK_DRV_DELAY field. + 23 + 1 + read-write + + + DISABLE + Disable drive delay. + 0 + + + ENABLE + Enable drive delay. + 0x1 + + + + + CCLK_SAMPLE_DELAY + Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in. + 24 + 5 + read-write + + + CCLK_SAMPLE_DELAY_ACTIVE + Enables sample delay, as controlled by the CCLK_SAMPLE_DELAY field. + 31 + 1 + read-write + + + DISABLE + Disables sample delay. + 0 + + + ENABLE + Enables sample delay. + 0x1 + + + + + + + PLL1CTRL + PLL1 550m control + 0x560 + 32 + read-write + 0 + 0x1FFFFFF + + + SELR + Bandwidth select R value. + 0 + 4 + read-write + + + SELI + Bandwidth select I value. + 4 + 6 + read-write + + + SELP + Bandwidth select P value. + 10 + 5 + read-write + + + BYPASSPLL + Bypass PLL input clock is sent directly to the PLL output (default). + 15 + 1 + read-write + + + USED + use PLL. + 0 + + + BYPASSED + PLL input clock is sent directly to the PLL output. + 0x1 + + + + + BYPASSPOSTDIV2 + bypass of the divide-by-2 divider in the post-divider. + 16 + 1 + read-write + + + USED + use the divide-by-2 divider in the post-divider. + 0 + + + BYPASSED + bypass of the divide-by-2 divider in the post-divider. + 0x1 + + + + + LIMUPOFF + limup_off = 1 in spread spectrum and fractional PLL applications. + 17 + 1 + read-write + + + BWDIRECT + control of the bandwidth of the PLL. + 18 + 1 + read-write + + + SYNC + the bandwidth is changed synchronously with the feedback-divider. + 0 + + + DIRECT + modify the bandwidth of the PLL directly. + 0x1 + + + + + BYPASSPREDIV + bypass of the pre-divider. + 19 + 1 + read-write + + + USED + use the pre-divider. + 0 + + + BYPASSED + bypass of the pre-divider. + 0x1 + + + + + BYPASSPOSTDIV + bypass of the post-divider. + 20 + 1 + read-write + + + USED + use the post-divider. + 0 + + + BYPASSED + bypass of the post-divider. + 0x1 + + + + + CLKEN + enable the output clock. + 21 + 1 + read-write + + + DISABLE + Disable the output clock. + 0 + + + ENABLE + Enable the output clock. + 0x1 + + + + + FRMEN + 1: free running mode. + 22 + 1 + read-write + + + FRMCLKSTABLE + free running mode clockstable: Warning: Only make frm_clockstable = 1 after the PLL output frequency is stable. + 23 + 1 + read-write + + + SKEWEN + Skew mode. + 24 + 1 + read-write + + + DISABLE + skewmode is disable. + 0 + + + ENABLE + skewmode is enable. + 0x1 + + + + + + + PLL1STAT + PLL1 550m status + 0x564 + 32 + read-write + 0 + 0x1F + + + LOCK + lock detector output (active high) Warning: The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. + 0 + 1 + read-only + + + PREDIVACK + pre-divider ratio change acknowledge. + 1 + 1 + read-only + + + FEEDDIVACK + feedback divider ratio change acknowledge. + 2 + 1 + read-only + + + POSTDIVACK + post-divider ratio change acknowledge. + 3 + 1 + read-only + + + FRMDET + free running detector output (active high). + 4 + 1 + read-only + + + + + PLL1NDEC + PLL1 550m N divider + 0x568 + 32 + read-write + 0 + 0x1FF + + + NDIV + pre-divider divider ratio (N-divider). + 0 + 8 + read-write + + + NREQ + pre-divider ratio change request. + 8 + 1 + read-write + + + + + PLL1MDEC + PLL1 550m M divider + 0x56C + 32 + read-write + 0 + 0x1FFFF + + + MDIV + feedback divider divider ratio (M-divider). + 0 + 16 + read-write + + + MREQ + feedback ratio change request. + 16 + 1 + read-write + + + + + PLL1PDEC + PLL1 550m P divider + 0x570 + 32 + read-write + 0 + 0x3F + + + PDIV + post-divider divider ratio (P-divider) + 0 + 5 + read-write + + + PREQ + feedback ratio change request. + 5 + 1 + read-write + + + + + PLL0CTRL + PLL0 550m control + 0x580 + 32 + read-write + 0 + 0x1FFFFFF + + + SELR + Bandwidth select R value. + 0 + 4 + read-write + + + SELI + Bandwidth select I value. + 4 + 6 + read-write + + + SELP + Bandwidth select P value. + 10 + 5 + read-write + + + BYPASSPLL + Bypass PLL input clock is sent directly to the PLL output (default). + 15 + 1 + read-write + + + USED + use PLL. + 0 + + + BYPASSED + Bypass PLL input clock is sent directly to the PLL output. + 0x1 + + + + + BYPASSPOSTDIV2 + bypass of the divide-by-2 divider in the post-divider. + 16 + 1 + read-write + + + USED + use the divide-by-2 divider in the post-divider. + 0 + + + BYPASSED + bypass of the divide-by-2 divider in the post-divider. + 0x1 + + + + + LIMUPOFF + limup_off = 1 in spread spectrum and fractional PLL applications. + 17 + 1 + read-write + + + BWDIRECT + Control of the bandwidth of the PLL. + 18 + 1 + read-write + + + SYNC + the bandwidth is changed synchronously with the feedback-divider. + 0 + + + DIRECT + modify the bandwidth of the PLL directly. + 0x1 + + + + + BYPASSPREDIV + bypass of the pre-divider. + 19 + 1 + read-write + + + USED + use the pre-divider. + 0 + + + BYPASSED + bypass of the pre-divider. + 0x1 + + + + + BYPASSPOSTDIV + bypass of the post-divider. + 20 + 1 + read-write + + + USED + use the post-divider. + 0 + + + BYPASSED + bypass of the post-divider. + 0x1 + + + + + CLKEN + enable the output clock. + 21 + 1 + read-write + + + DISABLE + disable the output clock. + 0 + + + ENABLE + enable the output clock. + 0x1 + + + + + FRMEN + free running mode. + 22 + 1 + read-write + + + DISABLE + free running mode is disable. + 0 + + + ENABLE + free running mode is enable. + 0x1 + + + + + FRMCLKSTABLE + free running mode clockstable: Warning: Only make frm_clockstable =1 after the PLL output frequency is stable. + 23 + 1 + read-write + + + SKEWEN + skew mode. + 24 + 1 + read-write + + + DISABLE + skew mode is disable. + 0 + + + ENABLE + skew mode is enable. + 0x1 + + + + + + + PLL0STAT + PLL0 550m status + 0x584 + 32 + read-write + 0 + 0x1F + + + LOCK + lock detector output (active high) Warning: The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. + 0 + 1 + read-only + + + PREDIVACK + pre-divider ratio change acknowledge. + 1 + 1 + read-only + + + FEEDDIVACK + feedback divider ratio change acknowledge. + 2 + 1 + read-only + + + POSTDIVACK + post-divider ratio change acknowledge. + 3 + 1 + read-only + + + FRMDET + free running detector output (active high). + 4 + 1 + read-only + + + + + PLL0NDEC + PLL0 550m N divider + 0x588 + 32 + read-write + 0 + 0x1FF + + + NDIV + pre-divider divider ratio (N-divider). + 0 + 8 + read-write + + + NREQ + pre-divider ratio change request. + 8 + 1 + read-write + + + + + PLL0PDEC + PLL0 550m P divider + 0x58C + 32 + read-write + 0 + 0x3F + + + PDIV + post-divider divider ratio (P-divider) + 0 + 5 + read-write + + + PREQ + feedback ratio change request. + 5 + 1 + read-write + + + + + PLL0SSCG0 + PLL0 Spread Spectrum Wrapper control register 0 + 0x590 + 32 + read-write + 0 + 0xFFFFFFFF + + + MD_LBS + input word of the wrapper bit 31 to 0. + 0 + 32 + read-write + + + + + PLL0SSCG1 + PLL0 Spread Spectrum Wrapper control register 1 + 0x594 + 32 + read-write + 0 + 0x1FFFFFFF + + + MD_MBS + input word of the wrapper bit 32. + 0 + 1 + read-write + + + MD_REQ + md change request. + 1 + 1 + read-write + + + MF + programmable modulation frequency fm = Fref/Nss mf[2:0] = 000 => Nss=512 (fm ~ 3. + 2 + 3 + read-write + + + MR + programmable frequency modulation depth Dfmodpk-pk = Fref*kss/Fcco = kss/(2*md[32:25]dec) mr[2:0] = 000 => kss = 0 (no spread spectrum) mr[2:0] = 001 => kss ~ 1 mr[2:0] = 010 => kss ~ 1. + 5 + 3 + read-write + + + MC + modulation waveform control Compensation for low pass filtering of the PLL to get a triangular modulation at the output of the PLL, giving a flat frequency spectrum. + 8 + 2 + read-write + + + MDIV_EXT + to select an external mdiv value. + 10 + 16 + read-write + + + MREQ + to select an external mreq value. + 26 + 1 + read-write + + + DITHER + dithering between two modulation frequencies in a random way or in a pseudo random way (white noise), in order to decrease the probability that the modulated waveform will occur with the same phase on a particular point on the screen. + 27 + 1 + read-write + + + SEL_EXT + to select mdiv_ext and mreq_ext sel_ext = 0: mdiv ~ md[32:0], mreq = 1 sel_ext = 1 : mdiv = mdiv_ext, mreq = mreq_ext. + 28 + 1 + read-write + + + + + EFUSECLKCTRL + eFUSE controller clock enable + 0x5CC + 32 + read-write + 0x1 + 0xFFFFFFFF + + + EFUSECLKENA + eFUSE controller clock enable. + 0 + 1 + read-write + + + + + STARTER0 + Start logic wake-up enable register + 0x680 + 32 + read-write + 0 + 0xF97FFFFF + + + SYS + SYS interrupt wake-up. + 0 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + SDMA0 + SDMA0 interrupt wake-up. + 1 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + GINT0 + GINT0 interrupt wake-up. + 2 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + GINT1 + GINT1 interrupt wake-up. + 3 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + PIO_INT0 + PIO_INT0 interrupt wake-up. + 4 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + PIO_INT1 + PIO_INT1 interrupt wake-up. + 5 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + PIO_INT2 + PIO_INT2 interrupt wake-up. + 6 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + PIO_INT3 + PIO_INT3 interrupt wake-up. + 7 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + UTICK0 + UTICK0 interrupt wake-up. + 8 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + MRT0 + MRT0 interrupt wake-up. + 9 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + CTIMER0 + CTIMER0 interrupt wake-up. + 10 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + CTIMER1 + CTIMER1 interrupt wake-up. + 11 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + SCT0 + SCT0 interrupt wake-up. + 12 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + CTIMER3 + CTIMER3 interrupt wake-up. + 13 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + FLEXINT0 + FLEXINT0 interrupt wake-up. + 14 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + FLEXINT1 + FLEXINT1 interrupt wake-up. + 15 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + FLEXINT2 + FLEXINT2 interrupt wake-up. + 16 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + FLEXINT3 + FLEXINT3 interrupt wake-up. + 17 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + FLEXINT4 + FLEXINT4 interrupt wake-up. + 18 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + FLEXINT5 + FLEXINT5 interrupt wake-up. + 19 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + FLEXINT6 + FLEXINT6 interrupt wake-up. + 20 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + FLEXINT7 + FLEXINT7 interrupt wake-up. + 21 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + ADC0 + ADC0 interrupt wake-up. + 22 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + ADC0_THCMP_OVR + ADC0_THCMP_OVR interrupt wake-up. + 24 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + USB0_NEEDCLK + USB0_NEEDCLK interrupt wake-up. + 27 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + USB0 + USB0 interrupt wake-up. + 28 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + RTC_LITE0 + RTC_LITE0 interrupt wake-up. + 29 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + EZH_ARCH_B0 + EZH_ARCH_B0 interrupt wake-up. + 30 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + WAKEUP_MAILBOX0 + WAKEUP_MAILBOX0 interrupt wake-up. + 31 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + + + STARTER1 + Start logic wake-up enable register + 0x684 + 32 + read-write + 0 + 0xFFFF847F + + + GPIO_INT04 + GPIO_INT04 interrupt wake-up. + 0 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + GPIO_INT05 + GPIO_INT05 interrupt wake-up. + 1 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + GPIO_INT06 + GPIO_INT06 interrupt wake-up. + 2 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + GPIO_INT07 + GPIO_INT07 interrupt wake-up. + 3 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + CTIMER2 + CTIMER2 interrupt wake-up. + 4 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + CTIMER4 + CTIMER4 interrupt wake-up. + 5 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + OS_EVENT + OS_EVENT interrupt wake-up. + 6 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + SDIO + SDIO interrupt wake-up. + 10 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + USB1 + USB1 interrupt wake-up. + 15 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + USB1_NEEDCLK + USB1_NEEDCLK interrupt wake-up. + 16 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + SEC_HYPERVISOR_CALL + SEC_HYPERVISOR_CALL interrupt wake-up. + 17 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + SEC_GPIO_INT00 + SEC_GPIO_INT00 interrupt wake-up. + 18 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + SEC_GPIO_INT01 + SEC_GPIO_INT01 interrupt wake-up. + 19 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + PLU + PLU interrupt wake-up. + 20 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + SEC_VIO + SEC_VIO interrupt wake-up. + 21 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + SHA + SHA interrupt wake-up. + 22 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + CASER + CASER interrupt wake-up. + 23 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + QDDKEY + QDDKEY interrupt wake-up. + 24 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + PQ + PQ interrupt wake-up. + 25 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + SDMA1 + SDMA1 interrupt wake-up. + 26 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + LSPI_HS + LSPI_HS interrupt wake-up. + 27 + 1 + read-write + + + DISABLE + Wake-up disabled. + 0 + + + ENABLE + Wake-up enabled. + 0x1 + + + + + WAKEUPPADS + WAKEUPPADS interrupt wake-up. + 31 + 1 + read-write + + + + + STARTERSET0 + Set bits in STARTER + 0x6A0 + 32 + write-only + 0 + 0xF97FFFFF + + + SYS_SET + Writing ones to this register sets the corresponding bit in the STARTER0 register. + 0 + 1 + write-only + + + SDMA0_SET + Writing ones to this register sets the corresponding bit in the STARTER0 register. + 1 + 1 + write-only + + + GPIO_GLOBALINT0_SET + Writing ones to this register sets the corresponding bit in the STARTER0 register. + 2 + 1 + write-only + + + GPIO_GLOBALINT1_SET + Writing ones to this register sets the corresponding bit in the STARTER0 register. + 3 + 1 + write-only + + + GPIO_INT00_SET + Writing ones to this register sets the corresponding bit in the STARTER0 register. + 4 + 1 + write-only + + + GPIO_INT01_SET + Writing ones to this register sets the corresponding bit in the STARTER0 register. + 5 + 1 + write-only + + + GPIO_INT02_SET + Writing ones to this register sets the corresponding bit in the STARTER0 register. + 6 + 1 + write-only + + + GPIO_INT03_SET + Writing ones to this register sets the corresponding bit in the STARTER0 register. + 7 + 1 + write-only + + + UTICK0_SET + Writing ones to this register sets the corresponding bit in the STARTER0 register. + 8 + 1 + write-only + + + MRT0_SET + Writing ones to this register sets the corresponding bit in the STARTER0 register. + 9 + 1 + write-only + + + CTIMER0_SET + Writing ones to this register sets the corresponding bit in the STARTER0 register. + 10 + 1 + write-only + + + CTIMER1_SET + Writing ones to this register sets the corresponding bit in the STARTER0 register. + 11 + 1 + write-only + + + SCT0_SET + Writing ones to this register sets the corresponding bit in the STARTER0 register. + 12 + 1 + write-only + + + CTIMER3_SET + Writing ones to this register sets the corresponding bit in the STARTER0 register. + 13 + 1 + write-only + + + FLEXINT0_SET + Writing ones to this register sets the corresponding bit in the STARTER0 register. + 14 + 1 + write-only + + + FLEXINT1_SET + Writing ones to this register sets the corresponding bit in the STARTER0 register. + 15 + 1 + write-only + + + FLEXINT2_SET + Writing ones to this register sets the corresponding bit in the STARTER0 register. + 16 + 1 + write-only + + + FLEXINT3_SET + Writing ones to this register sets the corresponding bit in the STARTER0 register. + 17 + 1 + write-only + + + FLEXINT4_SET + Writing ones to this register sets the corresponding bit in the STARTER0 register. + 18 + 1 + write-only + + + FLEXINT5_SET + Writing ones to this register sets the corresponding bit in the STARTER0 register. + 19 + 1 + write-only + + + FLEXINT6_SET + Writing ones to this register sets the corresponding bit in the STARTER0 register. + 20 + 1 + write-only + + + FLEXINT7_SET + Writing ones to this register sets the corresponding bit in the STARTER0 register. + 21 + 1 + write-only + + + ADC0_SET + Writing ones to this register sets the corresponding bit in the STARTER0 register. + 22 + 1 + write-only + + + ADC0_THCMP_OVR_SET + Writing ones to this register sets the corresponding bit in the STARTER0 register. + 24 + 1 + write-only + + + USB0_NEEDCLK_SET + Writing ones to this register sets the corresponding bit in the STARTER0 register. + 27 + 1 + write-only + + + USB0_SET + Writing ones to this register sets the corresponding bit in the STARTER0 register. + 28 + 1 + write-only + + + RTC_LITE0_SET + Writing ones to this register sets the corresponding bit in the STARTER0 register. + 29 + 1 + write-only + + + EZH_ARCH_B0_SET + Writing ones to this register sets the corresponding bit in the STARTER0 register. + 30 + 1 + write-only + + + WAKEUP_MAILBOX0_SET + Writing ones to this register sets the corresponding bit in the STARTER0 register. + 31 + 1 + write-only + + + + + STARTERSET1 + Set bits in STARTER + 0x6A4 + 32 + write-only + 0 + 0x8FFF847F + + + GPIO_INT04_SET + Writing ones to this register sets the corresponding bit in the STARTER1 register. + 0 + 1 + write-only + + + GPIO_INT05_SET + Writing ones to this register sets the corresponding bit in the STARTER1 register. + 1 + 1 + write-only + + + GPIO_INT06_SET + Writing ones to this register sets the corresponding bit in the STARTER1 register. + 2 + 1 + write-only + + + GPIO_INT07_SET + Writing ones to this register sets the corresponding bit in the STARTER1 register. + 3 + 1 + write-only + + + CTIMER2_SET + Writing ones to this register sets the corresponding bit in the STARTER1 register. + 4 + 1 + write-only + + + CTIMER4_SET + Writing ones to this register sets the corresponding bit in the STARTER1 register. + 5 + 1 + write-only + + + OS_EVENT_SET + Writing ones to this register sets the corresponding bit in the STARTER1 register. + 6 + 1 + write-only + + + SDIO_SET + Writing ones to this register sets the corresponding bit in the STARTER1 register. + 10 + 1 + write-only + + + USB1_SET + Writing ones to this register sets the corresponding bit in the STARTER1 register. + 15 + 1 + write-only + + + USB1_NEEDCLK_SET + Writing ones to this register sets the corresponding bit in the STARTER1 register. + 16 + 1 + write-only + + + SEC_HYPERVISOR_CALL_SET + Writing ones to this register sets the corresponding bit in the STARTER1 register. + 17 + 1 + write-only + + + SEC_GPIO_INT00_SET + Writing ones to this register sets the corresponding bit in the STARTER1 register. + 18 + 1 + write-only + + + SEC_GPIO_INT01_SET + Writing ones to this register sets the corresponding bit in the STARTER1 register. + 19 + 1 + write-only + + + PLU_SET + Writing ones to this register sets the corresponding bit in the STARTER1 register. + 20 + 1 + write-only + + + SEC_VIO_SET + Writing ones to this register sets the corresponding bit in the STARTER1 register. + 21 + 1 + write-only + + + SHA_SET + Writing ones to this register sets the corresponding bit in the STARTER1 register. + 22 + 1 + write-only + + + CASER_SET + Writing ones to this register sets the corresponding bit in the STARTER1 register. + 23 + 1 + write-only + + + QDDKEY_SET + Writing ones to this register sets the corresponding bit in the STARTER1 register. + 24 + 1 + write-only + + + PQ_SET + Writing ones to this register sets the corresponding bit in the STARTER1 register. + 25 + 1 + write-only + + + SDMA1_SET + Writing ones to this register sets the corresponding bit in the STARTER1 register. + 26 + 1 + write-only + + + LSPI_HS_SET + Writing ones to this register sets the corresponding bit in the STARTER1 register. + 27 + 1 + write-only + + + WAKEUPPADS_SET + Writing ones to this register sets the corresponding bit in the STARTER1 register. + 31 + 1 + write-only + + + + + STARTERCLR0 + Clear bits in STARTER + 0x6C0 + 32 + write-only + 0 + 0xF97FFFFF + + + SYS_CLR + Writing ones to this register clears the corresponding bit in the STARTER0 register. + 0 + 1 + write-only + + + SDMA0_CLR + Writing ones to this register clears the corresponding bit in the STARTER0 register. + 1 + 1 + write-only + + + GPIO_GLOBALINT0_CLR + Writing ones to this register clears the corresponding bit in the STARTER0 register. + 2 + 1 + write-only + + + GPIO_GLOBALINT1_CLR + Writing ones to this register clears the corresponding bit in the STARTER0 register. + 3 + 1 + write-only + + + GPIO_INT00_CLR + Writing ones to this register clears the corresponding bit in the STARTER0 register. + 4 + 1 + write-only + + + GPIO_INT01_CLR + Writing ones to this register clears the corresponding bit in the STARTER0 register. + 5 + 1 + write-only + + + GPIO_INT02_CLR + Writing ones to this register clears the corresponding bit in the STARTER0 register. + 6 + 1 + write-only + + + GPIO_INT03_CLR + Writing ones to this register clears the corresponding bit in the STARTER0 register. + 7 + 1 + write-only + + + UTICK0_CLR + Writing ones to this register clears the corresponding bit in the STARTER0 register. + 8 + 1 + write-only + + + MRT0_CLR + Writing ones to this register clears the corresponding bit in the STARTER0 register. + 9 + 1 + write-only + + + CTIMER0_CLR + Writing ones to this register clears the corresponding bit in the STARTER0 register. + 10 + 1 + write-only + + + CTIMER1_CLR + Writing ones to this register clears the corresponding bit in the STARTER0 register. + 11 + 1 + write-only + + + SCT0_CLR + Writing ones to this register clears the corresponding bit in the STARTER0 register. + 12 + 1 + write-only + + + CTIMER3_CLR + Writing ones to this register clears the corresponding bit in the STARTER0 register. + 13 + 1 + write-only + + + FLEXINT0_CLR + Writing ones to this register clears the corresponding bit in the STARTER0 register. + 14 + 1 + write-only + + + FLEXINT1_CLR + Writing ones to this register clears the corresponding bit in the STARTER0 register. + 15 + 1 + write-only + + + FLEXINT2_CLR + Writing ones to this register clears the corresponding bit in the STARTER0 register. + 16 + 1 + write-only + + + FLEXINT3_CLR + Writing ones to this register clears the corresponding bit in the STARTER0 register. + 17 + 1 + write-only + + + FLEXINT4_CLR + Writing ones to this register clears the corresponding bit in the STARTER0 register. + 18 + 1 + write-only + + + FLEXINT5_CLR + Writing ones to this register clears the corresponding bit in the STARTER0 register. + 19 + 1 + write-only + + + FLEXINT6_CLR + Writing ones to this register clears the corresponding bit in the STARTER0 register. + 20 + 1 + write-only + + + FLEXINT7_CLR + Writing ones to this register clears the corresponding bit in the STARTER0 register. + 21 + 1 + write-only + + + ADC0_CLR + Writing ones to this register clears the corresponding bit in the STARTER0 register. + 22 + 1 + write-only + + + ADC0_THCMP_OVR_CLR + Writing ones to this register clears the corresponding bit in the STARTER0 register. + 24 + 1 + write-only + + + USB0_NEEDCLK_CLR + Writing ones to this register clears the corresponding bit in the STARTER0 register. + 27 + 1 + write-only + + + USB0_CLR + Writing ones to this register clears the corresponding bit in the STARTER0 register. + 28 + 1 + write-only + + + RTC_LITE0_CLR + Writing ones to this register clears the corresponding bit in the STARTER0 register. + 29 + 1 + write-only + + + EZH_ARCH_B0_CLR + Writing ones to this register clears the corresponding bit in the STARTER0 register. + 30 + 1 + write-only + + + WAKEUP_MAILBOX0_CLR + Writing ones to this register clears the corresponding bit in the STARTER0 register. + 31 + 1 + write-only + + + + + STARTERCLR1 + Clear bits in STARTER + 0x6C4 + 32 + write-only + 0 + 0x8FFF847F + + + GPIO_INT04_CLR + Writing ones to this register clears the corresponding bit in the STARTER1 register. + 0 + 1 + write-only + + + GPIO_INT05_CLR + Writing ones to this register clears the corresponding bit in the STARTER1 register. + 1 + 1 + write-only + + + GPIO_INT06_CLR + Writing ones to this register clears the corresponding bit in the STARTER1 register. + 2 + 1 + write-only + + + GPIO_INT07_CLR + Writing ones to this register clears the corresponding bit in the STARTER1 register. + 3 + 1 + write-only + + + CTIMER2_CLR + Writing ones to this register clears the corresponding bit in the STARTER1 register. + 4 + 1 + write-only + + + CTIMER4_CLR + Writing ones to this register clears the corresponding bit in the STARTER1 register. + 5 + 1 + write-only + + + OS_EVENT_CLR + Writing ones to this register clears the corresponding bit in the STARTER1 register. + 6 + 1 + write-only + + + SDIO_CLR + Writing ones to this register clears the corresponding bit in the STARTER1 register. + 10 + 1 + write-only + + + USB1_CLR + Writing ones to this register clears the corresponding bit in the STARTER1 register. + 15 + 1 + write-only + + + USB1_NEEDCLK_CLR + Writing ones to this register clears the corresponding bit in the STARTER1 register. + 16 + 1 + write-only + + + SEC_HYPERVISOR_CALL_CLR + Writing ones to this register clears the corresponding bit in the STARTER1 register. + 17 + 1 + write-only + + + SEC_GPIO_INT00_CLR + Writing ones to this register clears the corresponding bit in the STARTER1 register. + 18 + 1 + write-only + + + SEC_GPIO_INT01_CLR + Writing ones to this register clears the corresponding bit in the STARTER1 register. + 19 + 1 + write-only + + + PLU_CLR + Writing ones to this register clears the corresponding bit in the STARTER1 register. + 20 + 1 + write-only + + + SEC_VIO_CLR + Writing ones to this register clears the corresponding bit in the STARTER1 register. + 21 + 1 + write-only + + + SHA_CLR + Writing ones to this register clears the corresponding bit in the STARTER1 register. + 22 + 1 + write-only + + + CASER_CLR + Writing ones to this register clears the corresponding bit in the STARTER1 register. + 23 + 1 + write-only + + + QDDKEY_CLR + Writing ones to this register clears the corresponding bit in the STARTER1 register. + 24 + 1 + write-only + + + PQ_CLR + Writing ones to this register clears the corresponding bit in the STARTER1 register. + 25 + 1 + write-only + + + SDMA1_CLR + Writing ones to this register clears the corresponding bit in the STARTER1 register. + 26 + 1 + write-only + + + LSPI_HS_CLR + Writing ones to this register clears the corresponding bit in the STARTER1 register. + 27 + 1 + write-only + + + WAKEUPPADS_CLR + Writing ones to this register clears the corresponding bit in the STARTER1 register. + 31 + 1 + write-only + + + + + HARDWARESLEEP + Hardware Sleep control + 0x780 + 32 + read-write + 0 + 0x2B + + + FORCED + Force peripheral clocking to stay on during Deep Sleep and Power-down modes. + 0 + 1 + read-write + + + PERIPHERALS + Wake for Flexcomms. + 1 + 1 + read-write + + + SDMA0 + Wake for DMA0. + 3 + 1 + read-write + + + SDMA1 + Wake for DMA1. + 5 + 1 + read-write + + + + + CPUCTRL + CPU Control for multiple processors + 0x800 + 32 + read-write + 0x2C + 0x3D + + + CPU1CLKEN + CPU1 clock enable. + 3 + 1 + read-write + + + DISABLE + The CPU1 clock is not enabled. + 0 + + + ENABLE + The CPU1 clock is enabled. + 0x1 + + + + + CPU1RSTEN + CPU1 reset. + 5 + 1 + read-write + + + RELEASED + The CPU1 is not being reset. + 0 + + + ASSERTED + The CPU1 is being reset. + 0x1 + + + + + + + CPBOOT + Coprocessor Boot Address + 0x804 + 32 + read-write + 0 + 0xFFFFFFFF + + + CPBOOT + Coprocessor Boot Address for CPU1. + 0 + 32 + read-write + + + + + CPSTACK + Coprocessor Stack Address + 0x808 + 32 + read-write + 0 + 0xFFFFFFFF + + + CPSTACK + Coprocessor Stack Address. -- NOT USED + 0 + 32 + read-write + + + + + CPSTAT + CPU Status + 0x80C + 32 + read-write + 0 + 0xF + + + CPU0SLEEPING + The CPU0 sleeping state. + 0 + 1 + read-only + + + AWAKE + the CPU is not sleeping. + 0 + + + SLEEPING + the CPU is sleeping. + 0x1 + + + + + CPU1SLEEPING + The CPU1 sleeping state. + 1 + 1 + read-only + + + AWAKE + the CPU is not sleeping. + 0 + + + SLEEPING + the CPU is sleeping. + 0x1 + + + + + CPU0LOCKUP + The CPU0 lockup state. + 2 + 1 + read-only + + + AWAKE + the CPU is not in lockup. + 0 + + + SLEEPING + the CPU is in lockup. + 0x1 + + + + + CPU1LOCKUP + The CPU1 lockup state. + 3 + 1 + read-only + + + AWAKE + the CPU is not in lockup. + 0 + + + SLEEPING + the CPU is in lockup. + 0x1 + + + + + + + DICE_REG0 + Composite Device Identifier + 0x900 + 32 + read-write + 0 + 0xFFFFFFFF + + + DICE_REG0 + no description available + 0 + 32 + read-write + + + + + DICE_REG1 + Composite Device Identifier + 0x904 + 32 + read-write + 0 + 0xFFFFFFFF + + + DICE_REG1 + no description available + 0 + 32 + read-write + + + + + DICE_REG2 + Composite Device Identifier + 0x908 + 32 + read-write + 0 + 0xFFFFFFFF + + + DICE_REG2 + no description available + 0 + 32 + read-write + + + + + DICE_REG3 + Composite Device Identifier + 0x90C + 32 + read-write + 0 + 0xFFFFFFFF + + + DICE_REG3 + no description available + 0 + 32 + read-write + + + + + DICE_REG4 + Composite Device Identifier + 0x910 + 32 + read-write + 0 + 0xFFFFFFFF + + + DICE_REG4 + no description available + 0 + 32 + read-write + + + + + DICE_REG5 + Composite Device Identifier + 0x914 + 32 + read-write + 0 + 0xFFFFFFFF + + + DICE_REG5 + no description available + 0 + 32 + read-write + + + + + DICE_REG6 + Composite Device Identifier + 0x918 + 32 + read-write + 0 + 0xFFFFFFFF + + + DICE_REG6 + no description available + 0 + 32 + read-write + + + + + DICE_REG7 + Composite Device Identifier + 0x91C + 32 + read-write + 0 + 0xFFFFFFFF + + + DICE_REG7 + no description available + 0 + 32 + read-write + + + + + CLOCK_CTRL + Various system clock controls : Flash clock (48 MHz) control, clocks to Frequency Measures + 0xA18 + 32 + read-write + 0x1 + 0x7F + + + FLASH48MHZ_ENA + Enable Flash 48 MHz clock. + 0 + 1 + read-write + + + DISABLE + The clock is not enabled. + 0 + + + ENABLE + The clock is enabled. + 0x1 + + + + + XTAL32MHZ_FREQM_ENA + Enable XTAL32MHz clock for Frequency Measure module. + 1 + 1 + read-write + + + DISABLE + The clock is not enabled. + 0 + + + ENABLE + The clock is enabled. + 0x1 + + + + + FRO1MHZ_UTICK_ENA + Enable FRO 1MHz clock for Frequency Measure module and for UTICK. + 2 + 1 + read-write + + + DISABLE + The clock is not enabled. + 0 + + + ENABLE + The clock is enabled. + 0x1 + + + + + FRO12MHZ_FREQM_ENA + Enable FRO 12MHz clock for Frequency Measure module. + 3 + 1 + read-write + + + DISABLE + The clock is not enabled. + 0 + + + ENABLE + The clock is enabled. + 0x1 + + + + + FRO_HF_FREQM_ENA + Enable FRO 96MHz clock for Frequency Measure module. + 4 + 1 + read-write + + + DISABLE + The clock is not enabled. + 0 + + + ENABLE + The clock is enabled. + 0x1 + + + + + CLKIN_ENA + Enable clock_in clock for clock module. + 5 + 1 + read-write + + + DISABLE + The clock is not enabled. + 0 + + + ENABLE + The clock is enabled. + 0x1 + + + + + FRO1MHZ_CLK_ENA + Enable FRO 1MHz clock for clock muxing in clock gen. + 6 + 1 + read-write + + + DISABLE + The clock is not enabled. + 0 + + + ENABLE + The clock is enabled. + 0x1 + + + + + ANA_FRO12M_CLK_ENA + Enable FRO 12MHz clock for analog control of the FRO 192MHz. + 7 + 1 + read-write + + + DISABLE + The clock is not enabled. + 0 + + + ENABLE + The clock is enabled. + 0x1 + + + + + XO_CAL_CLK_ENA + Enable clock for cristal oscilator calibration. + 8 + 1 + read-write + + + DISABLE + The clock is not enabled. + 0 + + + ENABLE + The clock is enabled. + 0x1 + + + + + PLU_DEGLITCH_CLK_ENA + Enable clocks FRO_1MHz and FRO_12MHz for PLU deglitching. + 9 + 1 + read-write + + + DISABLE + The clock is not enabled. + 0 + + + ENABLE + The clock is enabled. + 0x1 + + + + + + + COMP_INT_CTRL + Comparator Interrupt control + 0xB10 + 32 + read-write + 0 + 0x3F + + + INT_ENABLE + Analog Comparator interrupt enable control:. + 0 + 1 + read-write + + + INT_DISABLE + interrupt disable. + 0 + + + INT_ENABLE + interrupt enable. + 0x1 + + + + + INT_CLEAR + Analog Comparator interrupt clear. + 1 + 1 + read-write + + + NONE + No effect. + 0 + + + CLEAR + Clear the interrupt. Self-cleared bit. + 0x1 + + + + + INT_CTRL + Comparator interrupt type selector:. + 2 + 3 + read-write + + + EDGE_DISABLE + The analog comparator interrupt edge sensitive is disabled. + 0 + + + LVL_DISABLE + The analog comparator interrupt level sensitive is disabled. + 0x1 + + + EDGE_RISING + analog comparator interrupt is rising edge sensitive. + 0x2 + + + LVL_HIGH + Analog Comparator interrupt is high level sensitive. + 0x3 + + + EDGE_FALLING + analog comparator interrupt is falling edge sensitive. + 0x4 + + + LVL_LOW + Analog Comparator interrupt is low level sensitive. + 0x5 + + + EDGE_BOTH + analog comparator interrupt is rising and falling edge sensitive. + 0x6 + + + LVL_DIS2 + The analog comparator interrupt level sensitive is disabled. + 0x7 + + + + + INT_SOURCE + Select which Analog comparator output (filtered our un-filtered) is used for interrupt detection. + 5 + 1 + read-write + + + FILTER_INT + Select Analog Comparator filtered output as input for interrupt detection. + 0 + + + RAW_INT + Select Analog Comparator raw output (unfiltered) as input for interrupt detection. Must be used when Analog comparator is used as wake up source in Power down mode. + 0x1 + + + + + + + COMP_INT_STATUS + Comparator Interrupt status + 0xB14 + 32 + read-write + 0 + 0x7 + + + STATUS + Interrupt status BEFORE Interrupt Enable. + 0 + 1 + read-only + + + NO_INT + no interrupt pending. + 0 + + + PENDING + interrupt pending. + 0x1 + + + + + INT_STATUS + Interrupt status AFTER Interrupt Enable. + 1 + 1 + read-only + + + NO_INT + no interrupt pending. + 0 + + + PENDING + interrupt pending. + 0x1 + + + + + VAL + comparator analog output. + 2 + 1 + read-only + + + SMALLER + P+ is smaller than P-. + 0 + + + GREATER + P+ is greater than P-. + 0x1 + + + + + + + AUTOCLKGATEOVERRIDE + Control automatic clock gating + 0xE04 + 32 + read-write + 0xFFFF + 0xFFFFFFFF + + + ROM + Control automatic clock gating of ROM controller. + 0 + 1 + read-write + + + DISABLE + Automatic clock gating is not overridden. + 0 + + + ENABLE + Automatic clock gating is overridden (Clock gating is disabled). + 0x1 + + + + + RAMX_CTRL + Control automatic clock gating of RAMX controller. + 1 + 1 + read-write + + + DISABLE + Automatic clock gating is not overridden. + 0 + + + ENABLE + Automatic clock gating is overridden (Clock gating is disabled). + 0x1 + + + + + RAM0_CTRL + Control automatic clock gating of RAM0 controller. + 2 + 1 + read-write + + + DISABLE + Automatic clock gating is not overridden. + 0 + + + ENABLE + Automatic clock gating is overridden (Clock gating is disabled). + 0x1 + + + + + RAM1_CTRL + Control automatic clock gating of RAM1 controller. + 3 + 1 + read-write + + + DISABLE + Automatic clock gating is not overridden. + 0 + + + ENABLE + Automatic clock gating is overridden (Clock gating is disabled). + 0x1 + + + + + RAM2_CTRL + Control automatic clock gating of RAM2 controller. + 4 + 1 + read-write + + + DISABLE + Automatic clock gating is not overridden. + 0 + + + ENABLE + Automatic clock gating is overridden (Clock gating is disabled). + 0x1 + + + + + RAM3_CTRL + Control automatic clock gating of RAM3 controller. + 5 + 1 + read-write + + + DISABLE + Automatic clock gating is not overridden. + 0 + + + ENABLE + Automatic clock gating is overridden (Clock gating is disabled). + 0x1 + + + + + RAM4_CTRL + Control automatic clock gating of RAM4 controller. + 6 + 1 + read-write + + + DISABLE + Automatic clock gating is not overridden. + 0 + + + ENABLE + Automatic clock gating is overridden (Clock gating is disabled). + 0x1 + + + + + SYNC0_APB + Control automatic clock gating of synchronous bridge controller 0. + 7 + 1 + read-write + + + DISABLE + Automatic clock gating is not overridden. + 0 + + + ENABLE + Automatic clock gating is overridden (Clock gating is disabled). + 0x1 + + + + + SYNC1_APB + Control automatic clock gating of synchronous bridge controller 1. + 8 + 1 + read-write + + + DISABLE + Automatic clock gating is not overridden. + 0 + + + ENABLE + Automatic clock gating is overridden (Clock gating is disabled). + 0x1 + + + + + FLASH + Control automatic clock gating of FLASH controller. + 9 + 1 + read-write + + + DISABLE + Automatic clock gating is not overridden. + 0 + + + ENABLE + Automatic clock gating is overridden (Clock gating is disabled). + 0x1 + + + + + FMC + Control automatic clock gating of FMC controller. + 10 + 1 + read-write + + + DISABLE + Automatic clock gating is not overridden. + 0 + + + ENABLE + Automatic clock gating is overridden (Clock gating is disabled). + 0x1 + + + + + CRCGEN + Control automatic clock gating of CRCGEN controller. + 11 + 1 + read-write + + + DISABLE + Automatic clock gating is not overridden. + 0 + + + ENABLE + Automatic clock gating is overridden (Clock gating is disabled). + 0x1 + + + + + SDMA0 + Control automatic clock gating of DMA0 controller. + 12 + 1 + read-write + + + DISABLE + Automatic clock gating is not overridden. + 0 + + + ENABLE + Automatic clock gating is overridden (Clock gating is disabled). + 0x1 + + + + + SDMA1 + Control automatic clock gating of DMA1 controller. + 13 + 1 + read-write + + + DISABLE + Automatic clock gating is not overridden. + 0 + + + ENABLE + Automatic clock gating is overridden (Clock gating is disabled). + 0x1 + + + + + USB + Control automatic clock gating of USB controller. + 14 + 1 + read-write + + + DISABLE + Automatic clock gating is not overridden. + 0 + + + ENABLE + Automatic clock gating is overridden (Clock gating is disabled). + 0x1 + + + + + SYSCON + Control automatic clock gating of synchronous system controller registers bank. + 15 + 1 + read-write + + + DISABLE + Automatic clock gating is not overridden. + 0 + + + ENABLE + Automatic clock gating is overridden (Clock gating is disabled). + 0x1 + + + + + ENABLEUPDATE + The value 0xC0DE must be written for AUTOCLKGATEOVERRIDE registers fields updates to have effect. + 16 + 16 + write-only + + + DISABLE + Automatic clock gating is not overridden. + 0 + + + ENABLE + Automatic clock gating is overridden (Clock gating is disabled). + 0xC0DE + + + + + + + GPIOPSYNC + Enable bypass of the first stage of synchonization inside GPIO_INT module + 0xE08 + 32 + read-write + 0 + 0x1 + + + PSYNC + Enable bypass of the first stage of synchonization inside GPIO_INT module. + 0 + 1 + read-write + + + USED + use the first stage of synchonization inside GPIO_INT module. + 0 + + + BYPASS + bypass of the first stage of synchonization inside GPIO_INT module. + 0x1 + + + + + + + DEBUG_LOCK_EN + Control write access to security registers -- FOR INTERNAl USE ONLY + 0xFA0 + 32 + read-write + 0x5 + 0xF + + + LOCK_ALL + Control write access to CODESECURITYPROTTEST, CODESECURITYPROTCPU0, CODESECURITYPROTCPU1, CM33_DEBUG_FEATURES, MCM33_DEBUG_FEATURES and DBG_AUTH_SCRATCH registers. + 0 + 4 + read-write + + + DISABLE + Any other value than b1010: disable write access to all 6 registers. + 0 + + + ENABLE + 1010: Enable write access to all 6 registers. + 0xA + + + + + + + DEBUG_FEATURES + Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control -- FOR INTERNAl USE ONLY + 0xFA4 + 32 + read-write + 0 + 0xFFF + + + CM33_DBGEN + CM33 (CPU0) Invasive debug control:. + 0 + 2 + read-write + + + DISABLE + Any other value than b10: invasive debug is disable. + 0x1 + + + ENABLE + 10: Invasive debug is enabled. + 0x2 + + + + + CM33_NIDEN + CM33 (CPU0) Non Invasive debug control:. + 2 + 2 + read-write + + + DISABLE + Any other value than b10: invasive debug is disable. + 0x1 + + + ENABLE + 10: Invasive debug is enabled. + 0x2 + + + + + CM33_SPIDEN + CM33 (CPU0) Secure Invasive debug control:. + 4 + 2 + read-write + + + DISABLE + Any other value than b10: invasive debug is disable. + 0x1 + + + ENABLE + 10: Invasive debug is enabled. + 0x2 + + + + + CM33_SPNIDEN + CM33 (CPU0) Secure Non Invasive debug control:. + 6 + 2 + read-write + + + DISABLE + Any other value than b10: invasive debug is disable. + 0x1 + + + ENABLE + 10: Invasive debug is enabled. + 0x2 + + + + + MCM33_DBGEN + Micro-CM33 (CPU1) Invasive debug control:. + 8 + 2 + read-write + + + DISABLE + Any other value than b10: invasive debug is disable. + 0x1 + + + ENABLE + 10: Invasive debug is enabled. + 0x2 + + + + + MCM33_NIDEN + Micro-CM33 (CPU1) Non Invasive debug control:. + 10 + 2 + read-write + + + DISABLE + Any other value than b10: invasive debug is disable. + 0x1 + + + ENABLE + 10: Invasive debug is enabled. + 0x2 + + + + + + + DEBUG_FEATURES_DP + Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control DUPLICATE register -- FOR INTERNAl USE ONLY + 0xFA8 + 32 + read-write + 0x555 + 0xFFF + + + CM33_DBGEN + CM33 (CPU0) Invasive debug control:. + 0 + 2 + read-write + + + DISABLE + Any other value than b10: invasive debug is disable. + 0x1 + + + ENABLE + 10: Invasive debug is enabled. + 0x2 + + + + + CM33_NIDEN + CM33 (CPU0) Non Invasive debug control:. + 2 + 2 + read-write + + + DISABLE + Any other value than b10: invasive debug is disable. + 0x1 + + + ENABLE + 10: Invasive debug is enabled. + 0x2 + + + + + CM33_SPIDEN + CM33 (CPU0) Secure Invasive debug control:. + 4 + 2 + read-write + + + DISABLE + Any other value than b10: invasive debug is disable. + 0x1 + + + ENABLE + 10: Invasive debug is enabled. + 0x2 + + + + + CM33_SPNIDEN + CM33 (CPU0) Secure Non Invasive debug control:. + 6 + 2 + read-write + + + DISABLE + Any other value than b10: invasive debug is disable. + 0x1 + + + ENABLE + 10: Invasive debug is enabled. + 0x2 + + + + + MCM33_DBGEN + Micro-CM33 (CPU1) Invasive debug control:. + 8 + 2 + read-write + + + DISABLE + Any other value than b10: invasive debug is disable. + 0x1 + + + ENABLE + 10: Invasive debug is enabled. + 0x2 + + + + + MCM33_NIDEN + Micro-CM33 (CPU1) Non Invasive debug control:. + 10 + 2 + read-write + + + DISABLE + Any other value than b10: invasive debug is disable. + 0x1 + + + ENABLE + 10: Invasive debug is enabled. + 0x2 + + + + + + + CODESECURITYPROTTEST + Security code to allow test (Design for Testability) access -- FOR INTERNAl USE ONLY + 0xFB0 + 32 + write-only + 0 + 0xFFFFFFFF + + + SEC_CODE + Security code to allow test access : 0x12345678. + 0 + 32 + write-only + + + DISABLE + test access is not allowed. + 0 + + + ENABLE + Security code to allow test access. + 0x12345678 + + + + + + + CODESECURITYPROTCPU0 + Security code to allow CPU0 (CM33) Debug Access Port (DAP) -- FOR INTERNAl USE ONLY + 0xFB4 + 32 + write-only + 0 + 0xFFFFFFFF + + + SEC_CODE + Security code to allow CPU0 DAP: 0x12345678. + 0 + 32 + write-only + + + DISABLE + CPU0 DAP is not allowed. + 0 + + + ENABLE + Security code to allow CPU0 DAP. + 0x12345678 + + + + + + + CODESECURITYPROTCPU1 + Security code to allow CPU1 (Micro CM33) Debug Access Port (DAP) -- FOR INTERNAl USE ONLY + 0xFB8 + 32 + write-only + 0 + 0xFFFFFFFF + + + SEC_CODE + Security code to allow CPU1 DAP: 0x12345678. + 0 + 32 + write-only + + + DISABLE + CPU1 DAP is not allowed. + 0 + + + ENABLE + Security code to allow CPU1 DAP. + 0x12345678 + + + + + + + KEY_BLOCK + block quiddikey/PUF all index. -- FOR INTERNAL USE ONLY + 0xFBC + 32 + write-only + 0x3CC35AA5 + 0xFFFFFFFF + + + KEY_BLOCK + Write a value to block quiddikey/PUF all index. + 0 + 32 + write-only + + + + + DEBUG_AUTH_SCRATCH + Debug authentication scratch registers -- FOR INTERNAL USE ONLY + 0xFC0 + 32 + read-write + 0 + 0xFFFFFFFF + + + SCRATCH + Set by the debug authentication code in ROM to pass the debug beacons (Credential Beacon and Authentication Beacon) to application code. + 0 + 32 + read-write + + + + + CPUCFG + CPUs configuration register + 0xFD4 + 32 + read-write + 0x2 + 0x7 + + + CPU1ENABLE + Enable CPU1. + 2 + 1 + read-write + + + DISABLE + CPU1 is disable (Processor in reset). + 0 + + + ENABLE + CPU1 is enable. + 0x1 + + + + + + + PERIPHENCFG + peripheral enable configuration -- FOR INTERNAL USE ONLY + 0xFEC + 32 + read-write + 0x5C47 + 0x5C47 + + + SCTEN + SCT enable. + 0 + 1 + read-write + + + DISABLE + peripheral is disable. + 0 + + + ENABLE + peripheral is enable. + 0x1 + + + + + ADCEN + ADC enable. + 1 + 1 + read-write + + + DISABLE + peripheral is disable. + 0 + + + ENABLE + peripheral is enable. + 0x1 + + + + + USB0EN + USB0 enable. + 2 + 1 + read-write + + + DISABLE + peripheral is disable. + 0 + + + ENABLE + peripheral is enable. + 0x1 + + + + + PUFFEN + Puff enable. + 6 + 1 + read-write + + + DISABLE + peripheral is disable. + 0 + + + ENABLE + peripheral is enable. + 0x1 + + + + + USB1EN + USB1 enable. + 10 + 1 + read-write + + + DISABLE + peripheral is disable. + 0 + + + ENABLE + peripheral is enable. + 0x1 + + + + + SDIOEN + SDIO enable. + 11 + 1 + read-write + + + DISABLE + peripheral is disable. + 0 + + + ENABLE + peripheral is enable. + 0x1 + + + + + HASHEN + HASH enable. + 12 + 1 + read-write + + + DISABLE + peripheral is disable. + 0 + + + ENABLE + peripheral is enable. + 0x1 + + + + + PRINCEEN + PRINCE enable. + 14 + 1 + read-write + + + DISABLE + peripheral is disable. + 0 + + + ENABLE + peripheral is enable. + 0x1 + + + + + + + DEVICE_ID0 + Device ID + 0xFF8 + 32 + read-only + 0 + 0xFFFFFFFF + + + PARTCONFIG + no description available + 0 + 8 + read-only + + + SRAM_SIZE + no description available + 8 + 4 + read-only + + + FLASH_SIZE + no description available + 12 + 3 + read-only + + + ROM_REV_MINOR + no description available + 20 + 4 + read-only + + + MODELNUM_EXTENTION + no description available + 24 + 3 + read-only + + + + + DIEID + Chip revision ID and Number + 0xFFC + 32 + read-only + 0x426B0 + 0xFFFFFF + + + REV_ID + Chip Metal Revision ID. + 0 + 4 + read-only + + + MCO_NUM_IN_DIE_ID + Chip Number. + 4 + 20 + read-only + + + + + + + IOCON + I/O pin configuration (IOCON) + IOCON + 0x40001000 + + 0 + 0x100 + registers + + + + PIO0_0 + Digital I/O control for port 0 pins PIO0_0 + 0 + 32 + read-write + 0 + 0x7FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + ASW + Analog switch input control. Usable only if DIGIMODE = 0b0 + 10 + 1 + read-write + + + DISABLE + Analog switch is open. + 0 + + + ENABLE + Analog switch is closed. + 0x1 + + + + + + + PIO0_1 + Digital I/O control for port 0 pins PIO0_1 + 0x4 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO0_2 + Digital I/O control for port 0 pins PIO0_2 + 0x8 + 32 + read-write + 0x110 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO0_3 + Digital I/O control for port 0 pins PIO0_3 + 0xC + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO0_4 + Digital I/O control for port 0 pins PIO0_4 + 0x10 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO0_5 + Digital I/O control for port 0 pins PIO0_5 + 0x14 + 32 + read-write + 0x120 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO0_6 + Digital I/O control for port 0 pins PIO0_6 + 0x18 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO0_7 + Digital I/O control for port 0 pins PIO0_7 + 0x1C + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO0_8 + Digital I/O control for port 0 pins PIO0_8 + 0x20 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO0_9 + Digital I/O control for port 0 pins PIO0_9 + 0x24 + 32 + read-write + 0 + 0x7FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + ASW + Analog switch input control. Usable only if DIGIMODE = 0b0 + 10 + 1 + read-write + + + DISABLE + Analog switch is open. + 0 + + + ENABLE + Analog switch is closed. + 0x1 + + + + + + + PIO0_10 + Digital I/O control for port 0 pins PIO0_10 + 0x28 + 32 + read-write + 0 + 0x7FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + ASW + Analog switch input control. Usable only if DIGIMODE = 0b0 + 10 + 1 + read-write + + + DISABLE + Analog switch is open. + 0 + + + ENABLE + Analog switch is closed. + 0x1 + + + + + + + PIO0_11 + Digital I/O control for port 0 pins PIO0_11 + 0x2C + 32 + read-write + 0x116 + 0x7FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + ASW + Analog switch input control. Usable only if DIGIMODE = 0b0 + 10 + 1 + read-write + + + DISABLE + Analog switch is open. + 0 + + + ENABLE + Analog switch is closed. + 0x1 + + + + + + + PIO0_12 + Digital I/O control for port 0 pins PIO0_12 + 0x30 + 32 + read-write + 0x126 + 0x7FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + ASW + Analog switch input control. Usable only if DIGIMODE = 0b0 + 10 + 1 + read-write + + + DISABLE + Analog switch is open. + 0 + + + ENABLE + Analog switch is closed. + 0x1 + + + + + + + PIO0_13 + Digital I/O control for port 0 pins PIO0_13 + 0x34 + 32 + read-write + 0x5000 + 0xFFFF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + SSEL + Supply Selection bit. + 11 + 1 + read-write + + + SEL3V3 + 3V3 Signaling in I2C Mode. + 0 + + + SEL1V8 + 1V8 Signaling in I2C Mode. + 0x1 + + + + + FILTEROFF + Controls input glitch filter. + 12 + 1 + read-write + + + ENABLED + Filter enabled. Noise pulses below approximately 10 ns are filtered out. + 0 + + + DISABLED + Filter disabled. No input filtering is done. + 0x1 + + + + + ECS + Pull-up current source enable in IIC mode. + 13 + 1 + read-write + + + DISABLED + Disabled. IO is in open drain. + 0 + + + ENABLED + Enabled. Pull resistor is conencted. + 0x1 + + + + + EGP + Controls slew rate of I2C pad. + 14 + 1 + read-write + + + I2C_MODE + I2C mode. + 0 + + + GPIO_MODE + GPIO mode. + 0x1 + + + + + I2CFILTER + Configures I2C features for standard mode, fast mode, and Fast Mode Plus operation. + 15 + 1 + read-write + + + FAST_MODE + I2C 50 ns glitch filter enabled. Typically used for Fast-mode and Fast-mode Plus I2C. + 0 + + + STANDARD_MODE + I2C 10 ns glitch filter enabled. Typically used for Standard-mode I2C. + 0x1 + + + + + + + PIO0_14 + Digital I/O control for port 0 pins PIO0_14 + 0x38 + 32 + read-write + 0x5000 + 0xFFFF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + SSEL + Supply Selection bit. + 11 + 1 + read-write + + + SEL3V3 + 3V3 Signaling in I2C Mode. + 0 + + + SEL1V8 + 1V8 Signaling in I2C Mode. + 0x1 + + + + + FILTEROFF + Controls input glitch filter. + 12 + 1 + read-write + + + ENABLED + Filter enabled. Noise pulses below approximately 10 ns are filtered out. + 0 + + + DISABLED + Filter disabled. No input filtering is done. + 0x1 + + + + + ECS + Pull-up current source enable in IIC mode. + 13 + 1 + read-write + + + DISABLED + Disabled. IO is in open drain. + 0 + + + ENABLED + Enabled. Pull resistor is conencted. + 0x1 + + + + + EGP + Controls slew rate of I2C pad. + 14 + 1 + read-write + + + I2C_MODE + I2C mode. + 0 + + + GPIO_MODE + GPIO mode. + 0x1 + + + + + I2CFILTER + Configures I2C features for standard mode, fast mode, and Fast Mode Plus operation. + 15 + 1 + read-write + + + FAST_MODE + I2C 50 ns glitch filter enabled. Typically used for Fast-mode and Fast-mode Plus I2C. + 0 + + + STANDARD_MODE + I2C 10 ns glitch filter enabled. Typically used for Standard-mode I2C. + 0x1 + + + + + + + PIO0_15 + Digital I/O control for port 0 pins PIO0_15 + 0x3C + 32 + read-write + 0 + 0x7FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + ASW + Analog switch input control. Usable only if DIGIMODE = 0b0 + 10 + 1 + read-write + + + DISABLE + Analog switch is open. + 0 + + + ENABLE + Analog switch is closed. + 0x1 + + + + + + + PIO0_16 + Digital I/O control for port 0 pins PIO0_16 + 0x40 + 32 + read-write + 0 + 0x7FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + ASW + Analog switch input control. Usable only if DIGIMODE = 0b0 + 10 + 1 + read-write + + + DISABLE + Analog switch is open. + 0 + + + ENABLE + Analog switch is closed. + 0x1 + + + + + + + PIO0_17 + Digital I/O control for port 0 pins PIO0_17 + 0x44 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO0_18 + Digital I/O control for port 0 pins PIO0_18 + 0x48 + 32 + read-write + 0 + 0x7FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + ASW + Analog switch input control. Usable only if DIGIMODE = 0b0 + 10 + 1 + read-write + + + DISABLE + Analog switch is open. + 0 + + + ENABLE + Analog switch is closed. + 0x1 + + + + + + + PIO0_19 + Digital I/O control for port 0 pins PIO0_19 + 0x4C + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO0_20 + Digital I/O control for port 0 pins PIO0_20 + 0x50 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO0_21 + Digital I/O control for port 0 pins PIO0_21 + 0x54 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO0_22 + Digital I/O control for port 0 pins PIO0_22 + 0x58 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO0_23 + Digital I/O control for port 0 pins PIO0_23 + 0x5C + 32 + read-write + 0 + 0x7FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + ASW + Analog switch input control. Usable only if DIGIMODE = 0b0 + 10 + 1 + read-write + + + DISABLE + Analog switch is open. + 0 + + + ENABLE + Analog switch is closed. + 0x1 + + + + + + + PIO0_24 + Digital I/O control for port 0 pins PIO0_24 + 0x60 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO0_25 + Digital I/O control for port 0 pins PIO0_25 + 0x64 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO0_26 + Digital I/O control for port 0 pins PIO0_26 + 0x68 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO0_27 + Digital I/O control for port 0 pins PIO0_27 + 0x6C + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO0_28 + Digital I/O control for port 0 pins PIO0_28 + 0x70 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO0_29 + Digital I/O control for port 0 pins PIO0_29 + 0x74 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO0_30 + Digital I/O control for port 0 pins PIO0_30 + 0x78 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO0_31 + Digital I/O control for port 0 pins PIO0_31 + 0x7C + 32 + read-write + 0 + 0x7FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + ASW + Analog switch input control. Usable only if DIGIMODE = 0b0 + 10 + 1 + read-write + + + DISABLE + Analog switch is open. + 0 + + + ENABLE + Analog switch is closed. + 0x1 + + + + + + + PIO1_0 + Digital I/O control for port 1 pins PIO1_0 + 0x80 + 32 + read-write + 0 + 0x7FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + ASW + Analog switch input control. Usable only if DIGIMODE = 0b0 + 10 + 1 + read-write + + + DISABLE + Analog switch is open. + 0 + + + ENABLE + Analog switch is closed. + 0x1 + + + + + + + PIO1_1 + Digital I/O control for port 1 pins PIO1_1 + 0x84 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO1_2 + Digital I/O control for port 1 pins PIO1_2 + 0x88 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO1_3 + Digital I/O control for port 1 pins PIO1_3 + 0x8C + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO1_4 + Digital I/O control for port 1 pins PIO1_4 + 0x90 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO1_5 + Digital I/O control for port 1 pins PIO1_5 + 0x94 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO1_6 + Digital I/O control for port 1 pins PIO1_6 + 0x98 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO1_7 + Digital I/O control for port 1 pins PIO1_7 + 0x9C + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO1_8 + Digital I/O control for port 1 pins PIO1_8 + 0xA0 + 32 + read-write + 0 + 0x7FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + ASW + Analog switch input control. Usable only if DIGIMODE = 0b0 + 10 + 1 + read-write + + + DISABLE + Analog switch is open. + 0 + + + ENABLE + Analog switch is closed. + 0x1 + + + + + + + PIO1_9 + Digital I/O control for port 1 pins PIO1_9 + 0xA4 + 32 + read-write + 0 + 0x7FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + ASW + Analog switch input control. Usable only if DIGIMODE = 0b0 + 10 + 1 + read-write + + + DISABLE + Analog switch is open. + 0 + + + ENABLE + Analog switch is closed. + 0x1 + + + + + + + PIO1_10 + Digital I/O control for port 1 pins PIO1_10 + 0xA8 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO1_11 + Digital I/O control for port 1 pins PIO1_11 + 0xAC + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO1_12 + Digital I/O control for port 1 pins PIO1_12 + 0xB0 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO1_13 + Digital I/O control for port 1 pins PIO1_13 + 0xB4 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO1_14 + Digital I/O control for port 1 pins PIO1_14 + 0xB8 + 32 + read-write + 0 + 0x7FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + ASW + Analog switch input control. Usable only if DIGIMODE = 0b0 + 10 + 1 + read-write + + + DISABLE + Analog switch is open. + 0 + + + ENABLE + Analog switch is closed. + 0x1 + + + + + + + PIO1_15 + Digital I/O control for port 1 pins PIO1_15 + 0xBC + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO1_16 + Digital I/O control for port 1 pins PIO1_16 + 0xC0 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO1_17 + Digital I/O control for port 1 pins PIO1_17 + 0xC4 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO1_18 + Digital I/O control for port 1 pins PIO1_18 + 0xC8 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO1_19 + Digital I/O control for port 1 pins PIO1_19 + 0xCC + 32 + read-write + 0 + 0x7FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + ASW + Analog switch input control. Usable only if DIGIMODE = 0b0 + 10 + 1 + read-write + + + DISABLE + Analog switch is open. + 0 + + + ENABLE + Analog switch is closed. + 0x1 + + + + + + + PIO1_20 + Digital I/O control for port 1 pins PIO1_20 + 0xD0 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO1_21 + Digital I/O control for port 1 pins PIO1_21 + 0xD4 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO1_22 + Digital I/O control for port 1 pins PIO1_22 + 0xD8 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO1_23 + Digital I/O control for port 1 pins PIO1_23 + 0xDC + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO1_24 + Digital I/O control for port 1 pins PIO1_24 + 0xE0 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO1_25 + Digital I/O control for port 1 pins PIO1_25 + 0xE4 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO1_26 + Digital I/O control for port 1 pins PIO1_26 + 0xE8 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO1_27 + Digital I/O control for port 1 pins PIO1_27 + 0xEC + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO1_28 + Digital I/O control for port 1 pins PIO1_28 + 0xF0 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO1_29 + Digital I/O control for port 1 pins PIO1_29 + 0xF4 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO1_30 + Digital I/O control for port 1 pins PIO1_30 + 0xF8 + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + PIO1_31 + Digital I/O control for port 1 pins PIO1_31 + 0xFC + 32 + read-write + 0 + 0x3FF + + + FUNC + Selects pin function. + 0 + 4 + read-write + + + ALT0 + Alternative connection 0. + 0 + + + ALT1 + Alternative connection 1. + 0x1 + + + ALT2 + Alternative connection 2. + 0x2 + + + ALT3 + Alternative connection 3. + 0x3 + + + ALT4 + Alternative connection 4. + 0x4 + + + ALT5 + Alternative connection 5. + 0x5 + + + ALT6 + Alternative connection 6. + 0x6 + + + ALT7 + Alternative connection 7. + 0x7 + + + + + MODE + Selects function mode (on-chip pull-up/pull-down resistor control). + 4 + 2 + read-write + + + INACTIVE + Inactive. Inactive (no pull-down/pull-up resistor enabled). + 0 + + + PULL_DOWN + Pull-down. Pull-down resistor enabled. + 0x1 + + + PULL_UP + Pull-up. Pull-up resistor enabled. + 0x2 + + + REPEATER + Repeater. Repeater mode. + 0x3 + + + + + SLEW + Driver slew rate. + 6 + 1 + read-write + + + STANDARD + Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + 0 + + + FAST + Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + 0x1 + + + + + INVERT + Input polarity. + 7 + 1 + read-write + + + DISABLED + Disabled. Input function is not inverted. + 0 + + + ENABLED + Enabled. Input is function inverted. + 0x1 + + + + + DIGIMODE + Select Digital mode. + 8 + 1 + read-write + + + ANALOG + Analog mode, digital input is disabled. + 0 + + + DIGITAL + Digital mode, digital input is enabled. + 0x1 + + + + + OD + Controls open-drain mode. + 9 + 1 + read-write + + + NORMAL + Normal. Normal push-pull output + 0 + + + OPEN_DRAIN + Open-drain. Simulated open-drain output (high drive disabled). + 0x1 + + + + + + + + + GINT0 + Group GPIO input interrupt (GINT0/1) + GINT + GINT + 0x40002000 + + 0 + 0x48 + registers + + + GINT0 + 2 + + + + CTRL + GPIO grouped interrupt control register + 0 + 32 + read-write + 0 + 0x7 + + + INT + Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect. + 0 + 1 + read-write + + + NO_REQUEST + No request. No interrupt request is pending. + 0 + + + REQUEST_ACTIVE + Request active. Interrupt request is active. + 0x1 + + + + + COMB + Combine enabled inputs for group interrupt + 1 + 1 + read-write + + + OR + Or. OR functionality: A grouped interrupt is generated when any one of the enabled inputs is active (based on its programmed polarity). + 0 + + + AND + And. AND functionality: An interrupt is generated when all enabled bits are active (based on their programmed polarity). + 0x1 + + + + + TRIG + Group interrupt trigger + 2 + 1 + read-write + + + EDGE_TRIGGERED + Edge-triggered. + 0 + + + LEVEL_TRIGGERED + Level-triggered. + 0x1 + + + + + + + 2 + 0x4 + PORT_POL[%s] + GPIO grouped interrupt port 0 polarity register + 0x20 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + POL + Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. + 0 + 32 + read-write + + + + + 2 + 0x4 + PORT_ENA[%s] + GPIO grouped interrupt port 0 enable register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENA + Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt. + 0 + 32 + read-write + + + + + + + GINT1 + Group GPIO input interrupt (GINT0/1) + GINT + 0x40003000 + + 0 + 0x48 + registers + + + GINT1 + 3 + + + + PINT + Pin interrupt and pattern match (PINT) + PINT + PINT + 0x40004000 + + 0 + 0x34 + registers + + + PIN_INT0 + 4 + + + PIN_INT1 + 5 + + + PIN_INT2 + 6 + + + PIN_INT3 + 7 + + + PIN_INT4 + 32 + + + PIN_INT5 + 33 + + + PIN_INT6 + 34 + + + PIN_INT7 + 35 + + + + ISEL + Pin Interrupt Mode register + 0 + 32 + read-write + 0 + 0xFF + + + PMODE + Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive + 0 + 8 + read-write + + + + + IENR + Pin interrupt level or rising edge interrupt enable register + 0x4 + 32 + read-write + 0 + 0xFF + + + ENRL + Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt. + 0 + 8 + read-write + + + + + SIENR + Pin interrupt level or rising edge interrupt set register + 0x8 + 32 + write-only + 0 + 0 + + + SETENRL + Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt. + 0 + 8 + write-only + + + + + CIENR + Pin interrupt level (rising edge interrupt) clear register + 0xC + 32 + write-only + 0 + 0 + + + CENRL + Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt. + 0 + 8 + write-only + + + + + IENF + Pin interrupt active level or falling edge interrupt enable register + 0x10 + 32 + read-write + 0 + 0xFF + + + ENAF + Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH. + 0 + 8 + read-write + + + + + SIENF + Pin interrupt active level or falling edge interrupt set register + 0x14 + 32 + write-only + 0 + 0 + + + SETENAF + Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt. + 0 + 8 + write-only + + + + + CIENF + Pin interrupt active level or falling edge interrupt clear register + 0x18 + 32 + write-only + 0 + 0 + + + CENAF + Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled. + 0 + 8 + write-only + + + + + RISE + Pin interrupt rising edge register + 0x1C + 32 + read-write + 0 + 0xFF + + + RDET + Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin. + 0 + 8 + read-write + + + + + FALL + Pin interrupt falling edge register + 0x20 + 32 + read-write + 0 + 0xFF + + + FDET + Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin. + 0 + 8 + read-write + + + + + IST + Pin interrupt status register + 0x24 + 32 + read-write + 0 + 0xFF + + + PSTAT + Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the IENF register). + 0 + 8 + read-write + + + + + PMCTRL + Pattern match interrupt control register + 0x28 + 32 + read-write + 0 + 0xFF000003 + + + SEL_PMATCH + Specifies whether the 8 pin interrupts are controlled by the pin interrupt function or by the pattern match function. + 0 + 1 + read-write + + + PIN_INTERRUPT + Pin interrupt. Interrupts are driven in response to the standard pin interrupt function. + 0 + + + PATTERN_MATCH + Pattern match. Interrupts are driven in response to pattern matches. + 0x1 + + + + + ENA_RXEV + Enables the RXEV output to the CPU and/or to a GPIO output when the specified boolean expression evaluates to true. + 1 + 1 + read-write + + + DISABLED + Disabled. RXEV output to the CPU is disabled. + 0 + + + ENABLED + Enabled. RXEV output to the CPU is enabled. + 0x1 + + + + + PMAT + This field displays the current state of pattern matches. A 1 in any bit of this field indicates that the corresponding product term is matched by the current state of the appropriate inputs. + 24 + 8 + read-write + + + + + PMSRC + Pattern match interrupt bit-slice source register + 0x2C + 32 + read-write + 0 + 0xFFFFFF00 + + + SRC0 + Selects the input source for bit slice 0 + 8 + 3 + read-write + + + INPUT0 + Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 0. + 0 + + + INPUT1 + Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 0. + 0x1 + + + INPUT2 + Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 0. + 0x2 + + + INPUT3 + Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 0. + 0x3 + + + INPUT4 + Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 0. + 0x4 + + + INPUT5 + Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 0. + 0x5 + + + INPUT6 + Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 0. + 0x6 + + + INPUT7 + Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 0. + 0x7 + + + + + SRC1 + Selects the input source for bit slice 1 + 11 + 3 + read-write + + + INPUT0 + Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 1. + 0 + + + INPUT1 + Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 1. + 0x1 + + + INPUT2 + Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 1. + 0x2 + + + INPUT3 + Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 1. + 0x3 + + + INPUT4 + Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 1. + 0x4 + + + INPUT5 + Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 1. + 0x5 + + + INPUT6 + Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 1. + 0x6 + + + INPUT7 + Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 1. + 0x7 + + + + + SRC2 + Selects the input source for bit slice 2 + 14 + 3 + read-write + + + INPUT0 + Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 2. + 0 + + + INPUT1 + Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 2. + 0x1 + + + INPUT2 + Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 2. + 0x2 + + + INPUT3 + Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 2. + 0x3 + + + INPUT4 + Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 2. + 0x4 + + + INPUT5 + Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 2. + 0x5 + + + INPUT6 + Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 2. + 0x6 + + + INPUT7 + Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 2. + 0x7 + + + + + SRC3 + Selects the input source for bit slice 3 + 17 + 3 + read-write + + + INPUT0 + Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 3. + 0 + + + INPUT1 + Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 3. + 0x1 + + + INPUT2 + Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 3. + 0x2 + + + INPUT3 + Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 3. + 0x3 + + + INPUT4 + Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 3. + 0x4 + + + INPUT5 + Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 3. + 0x5 + + + INPUT6 + Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 3. + 0x6 + + + INPUT7 + Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 3. + 0x7 + + + + + SRC4 + Selects the input source for bit slice 4 + 20 + 3 + read-write + + + INPUT0 + Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 4. + 0 + + + INPUT1 + Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 4. + 0x1 + + + INPUT2 + Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 4. + 0x2 + + + INPUT3 + Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 4. + 0x3 + + + INPUT4 + Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 4. + 0x4 + + + INPUT5 + Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 4. + 0x5 + + + INPUT6 + Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 4. + 0x6 + + + INPUT7 + Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 4. + 0x7 + + + + + SRC5 + Selects the input source for bit slice 5 + 23 + 3 + read-write + + + INPUT0 + Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 5. + 0 + + + INPUT1 + Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 5. + 0x1 + + + INPUT2 + Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 5. + 0x2 + + + INPUT3 + Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 5. + 0x3 + + + INPUT4 + Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 5. + 0x4 + + + INPUT5 + Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 5. + 0x5 + + + INPUT6 + Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 5. + 0x6 + + + INPUT7 + Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 5. + 0x7 + + + + + SRC6 + Selects the input source for bit slice 6 + 26 + 3 + read-write + + + INPUT0 + Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 6. + 0 + + + INPUT1 + Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 6. + 0x1 + + + INPUT2 + Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 6. + 0x2 + + + INPUT3 + Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 6. + 0x3 + + + INPUT4 + Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 6. + 0x4 + + + INPUT5 + Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 6. + 0x5 + + + INPUT6 + Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 6. + 0x6 + + + INPUT7 + Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 6. + 0x7 + + + + + SRC7 + Selects the input source for bit slice 7 + 29 + 3 + read-write + + + INPUT0 + Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 7. + 0 + + + INPUT1 + Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 7. + 0x1 + + + INPUT2 + Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 7. + 0x2 + + + INPUT3 + Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 7. + 0x3 + + + INPUT4 + Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 7. + 0x4 + + + INPUT5 + Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 7. + 0x5 + + + INPUT6 + Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 7. + 0x6 + + + INPUT7 + Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 7. + 0x7 + + + + + + + PMCFG + Pattern match interrupt bit slice configuration register + 0x30 + 32 + read-write + 0 + 0xFFFFFF7F + + + PROD_ENDPTS0 + Determines whether slice 0 is an endpoint. + 0 + 1 + read-write + + + NO_EFFECT + No effect. Slice 0 is not an endpoint. + 0 + + + ENDPOINT + endpoint. Slice 0 is the endpoint of a product term (minterm). Pin interrupt 0 in the NVIC is raised if the minterm evaluates as true. + 0x1 + + + + + PROD_ENDPTS1 + Determines whether slice 1 is an endpoint. + 1 + 1 + read-write + + + NO_EFFECT + No effect. Slice 1 is not an endpoint. + 0 + + + ENDPOINT + endpoint. Slice 1 is the endpoint of a product term (minterm). Pin interrupt 1 in the NVIC is raised if the minterm evaluates as true. + 0x1 + + + + + PROD_ENDPTS2 + Determines whether slice 2 is an endpoint. + 2 + 1 + read-write + + + NO_EFFECT + No effect. Slice 2 is not an endpoint. + 0 + + + ENDPOINT + endpoint. Slice 2 is the endpoint of a product term (minterm). Pin interrupt 2 in the NVIC is raised if the minterm evaluates as true. + 0x1 + + + + + PROD_ENDPTS3 + Determines whether slice 3 is an endpoint. + 3 + 1 + read-write + + + NO_EFFECT + No effect. Slice 3 is not an endpoint. + 0 + + + ENDPOINT + endpoint. Slice 3 is the endpoint of a product term (minterm). Pin interrupt 3 in the NVIC is raised if the minterm evaluates as true. + 0x1 + + + + + PROD_ENDPTS4 + Determines whether slice 4 is an endpoint. + 4 + 1 + read-write + + + NO_EFFECT + No effect. Slice 4 is not an endpoint. + 0 + + + ENDPOINT + endpoint. Slice 4 is the endpoint of a product term (minterm). Pin interrupt 4 in the NVIC is raised if the minterm evaluates as true. + 0x1 + + + + + PROD_ENDPTS5 + Determines whether slice 5 is an endpoint. + 5 + 1 + read-write + + + NO_EFFECT + No effect. Slice 5 is not an endpoint. + 0 + + + ENDPOINT + endpoint. Slice 5 is the endpoint of a product term (minterm). Pin interrupt 5 in the NVIC is raised if the minterm evaluates as true. + 0x1 + + + + + PROD_ENDPTS6 + Determines whether slice 6 is an endpoint. + 6 + 1 + read-write + + + NO_EFFECT + No effect. Slice 6 is not an endpoint. + 0 + + + ENDPOINT + endpoint. Slice 6 is the endpoint of a product term (minterm). Pin interrupt 6 in the NVIC is raised if the minterm evaluates as true. + 0x1 + + + + + CFG0 + Specifies the match contribution condition for bit slice 0. + 8 + 3 + read-write + + + CONSTANT_HIGH + Constant HIGH. This bit slice always contributes to a product term match. + 0 + + + STICKY_RISING_EDGE + Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + 0x1 + + + STICKY_FALLING_EDGE + Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + 0x2 + + + STICKY_RISING_FALLING_EDGE + Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + 0x3 + + + HIGH_LEVEL + High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + 0x4 + + + LOW_LEVEL + Low level. Match occurs when there is a low level on the specified input. + 0x5 + + + CONSTANT_ZERO + Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + 0x6 + + + EVENT + Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. + 0x7 + + + + + CFG1 + Specifies the match contribution condition for bit slice 1. + 11 + 3 + read-write + + + CONSTANT_HIGH + Constant HIGH. This bit slice always contributes to a product term match. + 0 + + + STICKY_RISING_EDGE + Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + 0x1 + + + STICKY_FALLING_EDGE + Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + 0x2 + + + STICKY_RISING_FALLING_EDGE + Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + 0x3 + + + HIGH_LEVEL + High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + 0x4 + + + LOW_LEVEL + Low level. Match occurs when there is a low level on the specified input. + 0x5 + + + CONSTANT_ZERO + Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + 0x6 + + + EVENT + Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. + 0x7 + + + + + CFG2 + Specifies the match contribution condition for bit slice 2. + 14 + 3 + read-write + + + CONSTANT_HIGH + Constant HIGH. This bit slice always contributes to a product term match. + 0 + + + STICKY_RISING_EDGE + Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + 0x1 + + + STICKY_FALLING_EDGE + Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + 0x2 + + + STICKY_RISING_FALLING_EDGE + Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + 0x3 + + + HIGH_LEVEL + High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + 0x4 + + + LOW_LEVEL + Low level. Match occurs when there is a low level on the specified input. + 0x5 + + + CONSTANT_ZERO + Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + 0x6 + + + EVENT + Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. + 0x7 + + + + + CFG3 + Specifies the match contribution condition for bit slice 3. + 17 + 3 + read-write + + + CONSTANT_HIGH + Constant HIGH. This bit slice always contributes to a product term match. + 0 + + + STICKY_RISING_EDGE + Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + 0x1 + + + STICKY_FALLING_EDGE + Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + 0x2 + + + STICKY_RISING_FALLING_EDGE + Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + 0x3 + + + HIGH_LEVEL + High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + 0x4 + + + LOW_LEVEL + Low level. Match occurs when there is a low level on the specified input. + 0x5 + + + CONSTANT_ZERO + Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + 0x6 + + + EVENT + Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. + 0x7 + + + + + CFG4 + Specifies the match contribution condition for bit slice 4. + 20 + 3 + read-write + + + CONSTANT_HIGH + Constant HIGH. This bit slice always contributes to a product term match. + 0 + + + STICKY_RISING_EDGE + Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + 0x1 + + + STICKY_FALLING_EDGE + Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + 0x2 + + + STICKY_RISING_FALLING_EDGE + Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + 0x3 + + + HIGH_LEVEL + High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + 0x4 + + + LOW_LEVEL + Low level. Match occurs when there is a low level on the specified input. + 0x5 + + + CONSTANT_ZERO + Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + 0x6 + + + EVENT + Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. + 0x7 + + + + + CFG5 + Specifies the match contribution condition for bit slice 5. + 23 + 3 + read-write + + + CONSTANT_HIGH + Constant HIGH. This bit slice always contributes to a product term match. + 0 + + + STICKY_RISING_EDGE + Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + 0x1 + + + STICKY_FALLING_EDGE + Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + 0x2 + + + STICKY_RISING_FALLING_EDGE + Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + 0x3 + + + HIGH_LEVEL + High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + 0x4 + + + LOW_LEVEL + Low level. Match occurs when there is a low level on the specified input. + 0x5 + + + CONSTANT_ZERO + Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + 0x6 + + + EVENT + Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. + 0x7 + + + + + CFG6 + Specifies the match contribution condition for bit slice 6. + 26 + 3 + read-write + + + CONSTANT_HIGH + Constant HIGH. This bit slice always contributes to a product term match. + 0 + + + STICKY_RISING_EDGE + Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + 0x1 + + + STICKY_FALLING_EDGE + Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + 0x2 + + + STICKY_RISING_FALLING_EDGE + Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + 0x3 + + + HIGH_LEVEL + High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + 0x4 + + + LOW_LEVEL + Low level. Match occurs when there is a low level on the specified input. + 0x5 + + + CONSTANT_ZERO + Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + 0x6 + + + EVENT + Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. + 0x7 + + + + + CFG7 + Specifies the match contribution condition for bit slice 7. + 29 + 3 + read-write + + + CONSTANT_HIGH + Constant HIGH. This bit slice always contributes to a product term match. + 0 + + + STICKY_RISING_EDGE + Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + 0x1 + + + STICKY_FALLING_EDGE + Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + 0x2 + + + STICKY_RISING_FALLING_EDGE + Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + 0x3 + + + HIGH_LEVEL + High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + 0x4 + + + LOW_LEVEL + Low level. Match occurs when there is a low level on the specified input. + 0x5 + + + CONSTANT_ZERO + Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + 0x6 + + + EVENT + Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. + 0x7 + + + + + + + + + SECPINT + Pin interrupt and pattern match (PINT) + PINT + 0x40005000 + + 0 + 0x34 + registers + + + SEC_GPIO_INT0_IRQ0 + 50 + + + SEC_GPIO_INT0_IRQ1 + 51 + + + + INPUTMUX + Input multiplexing (INPUT MUX) + INPUTMUX + 0x40006000 + + 0 + 0x7B4 + registers + + + + 7 + 0x4 + SCT0_INMUX[%s] + Input mux register for SCT0 input + 0 + 32 + read-write + 0x1F + 0x1F + + + INP_N + Input number to SCT0 inputs 0 to 6.. + 0 + 5 + read-write + + + val0 + SCT_GPI0 function selected from IOCON register + 0 + + + val1 + SCT_GPI1 function selected from IOCON register + 0x1 + + + val2 + SCT_GPI2 function selected from IOCON register + 0x2 + + + val3 + SCT_GPI3 function selected from IOCON register + 0x3 + + + val4 + SCT_GPI4 function selected from IOCON register + 0x4 + + + val5 + SCT_GPI5 function selected from IOCON register + 0x5 + + + val6 + SCT_GPI6 function selected from IOCON register + 0x6 + + + val7 + SCT_GPI7 function selected from IOCON register + 0x7 + + + val8 + T0_OUT0 ctimer 0 match[0] output + 0x8 + + + val9 + T1_OUT0 ctimer 1 match[0] output + 0x9 + + + val10 + T2_OUT0 ctimer 2 match[0] output + 0xA + + + val11 + T3_OUT0 ctimer 3 match[0] output + 0xB + + + val12 + T4_OUT0 ctimer 4 match[0] output + 0xC + + + val13 + ADC_IRQ interrupt request from ADC + 0xD + + + val14 + GPIOINT_BMATCH + 0xE + + + val15 + USB0_FRAME_TOGGLE + 0xF + + + val16 + USB1_FRAME_TOGGLE + 0x10 + + + val17 + COMP_OUTPUT output from analog comparator + 0x11 + + + val18 + I2S_SHARED_SCK[0] output from I2S pin sharing + 0x12 + + + val19 + I2S_SHARED_SCK[1] output from I2S pin sharing + 0x13 + + + val20 + I2S_SHARED_WS[0] output from I2S pin sharing + 0x14 + + + val21 + I2S_SHARED_WS[1] output from I2S pin sharing + 0x15 + + + val22 + ARM_TXEV interrupt event from cpu0 or cpu1 + 0x16 + + + val23 + DEBUG_HALTED from cpu0 or cpu1 + 0x17 + + + val24 + None + 0x18 + + + val24 + None + 0x19 + + + val24 + None + 0x1A + + + val24 + None + 0x1B + + + val24 + None + 0x1C + + + val24 + None + 0x1D + + + val24 + None + 0x1E + + + val24 + None + 0x1F + + + + + + + 4 + 0x4 + TIMER0CAPTSEL[%s] + Capture select registers for TIMER0 inputs + 0x20 + 32 + read-write + 0x1F + 0x1F + + + CAPTSEL + Input number to TIMER0 capture inputs 0 to 4 + 0 + 5 + read-write + + + val0 + CT_INP0 function selected from IOCON register + 0 + + + val1 + CT_INP1 function selected from IOCON register + 0x1 + + + val2 + CT_INP2 function selected from IOCON register + 0x2 + + + val3 + CT_INP3 function selected from IOCON register + 0x3 + + + val4 + CT_INP4 function selected from IOCON register + 0x4 + + + val5 + CT_INP5 function selected from IOCON register + 0x5 + + + val6 + CT_INP6 function selected from IOCON register + 0x6 + + + val7 + CT_INP7 function selected from IOCON register + 0x7 + + + val8 + CT_INP8 function selected from IOCON register + 0x8 + + + val9 + CT_INP9 function selected from IOCON register + 0x9 + + + val10 + CT_INP10 function selected from IOCON register + 0xA + + + val11 + CT_INP11 function selected from IOCON register + 0xB + + + val12 + CT_INP12 function selected from IOCON register + 0xC + + + val13 + CT_INP13 function selected from IOCON register + 0xD + + + val14 + CT_INP14 function selected from IOCON register + 0xE + + + val15 + CT_INP15 function selected from IOCON register + 0xF + + + val16 + CT_INP16 function selected from IOCON register + 0x10 + + + val17 + CT_INP17 function selected from IOCON register + 0x11 + + + val18 + CT_INP18 function selected from IOCON register + 0x12 + + + val19 + CT_INP19 function selected from IOCON register + 0x13 + + + val20 + USB0_FRAME_TOGGLE + 0x14 + + + val21 + USB1_FRAME_TOGGLE + 0x15 + + + val22 + COMP_OUTPUT output from analog comparator + 0x16 + + + val23 + I2S_SHARED_WS[0] output from I2S pin sharing + 0x17 + + + val24 + I2S_SHARED_WS[1] output from I2S pin sharing + 0x18 + + + val25 + None + 0x19 + + + val25 + None + 0x1A + + + val25 + None + 0x1B + + + val25 + None + 0x1C + + + val25 + None + 0x1D + + + val25 + None + 0x1E + + + val25 + None + 0x1F + + + + + + + 4 + 0x4 + TIMER1CAPTSEL[%s] + Capture select registers for TIMER1 inputs + 0x40 + 32 + read-write + 0x1F + 0x1F + + + CAPTSEL + Input number to TIMER1 capture inputs 0 to 4 + 0 + 5 + read-write + + + val0 + CT_INP0 function selected from IOCON register + 0 + + + val1 + CT_INP1 function selected from IOCON register + 0x1 + + + val2 + CT_INP2 function selected from IOCON register + 0x2 + + + val3 + CT_INP3 function selected from IOCON register + 0x3 + + + val4 + CT_INP4 function selected from IOCON register + 0x4 + + + val5 + CT_INP5 function selected from IOCON register + 0x5 + + + val6 + CT_INP6 function selected from IOCON register + 0x6 + + + val7 + CT_INP7 function selected from IOCON register + 0x7 + + + val8 + CT_INP8 function selected from IOCON register + 0x8 + + + val9 + CT_INP9 function selected from IOCON register + 0x9 + + + val10 + CT_INP10 function selected from IOCON register + 0xA + + + val11 + CT_INP11 function selected from IOCON register + 0xB + + + val12 + CT_INP12 function selected from IOCON register + 0xC + + + val13 + CT_INP13 function selected from IOCON register + 0xD + + + val14 + CT_INP14 function selected from IOCON register + 0xE + + + val15 + CT_INP15 function selected from IOCON register + 0xF + + + val16 + CT_INP16 function selected from IOCON register + 0x10 + + + val17 + CT_INP17 function selected from IOCON register + 0x11 + + + val18 + CT_INP18 function selected from IOCON register + 0x12 + + + val19 + CT_INP19 function selected from IOCON register + 0x13 + + + val20 + USB0_FRAME_TOGGLE + 0x14 + + + val21 + USB1_FRAME_TOGGLE + 0x15 + + + val22 + COMP_OUTPUT output from analog comparator + 0x16 + + + val23 + I2S_SHARED_WS[0] output from I2S pin sharing + 0x17 + + + val24 + I2S_SHARED_WS[1] output from I2S pin sharing + 0x18 + + + val25 + None + 0x19 + + + val25 + None + 0x1A + + + val25 + None + 0x1B + + + val25 + None + 0x1C + + + val25 + None + 0x1D + + + val25 + None + 0x1E + + + val25 + None + 0x1F + + + + + + + 4 + 0x4 + TIMER2CAPTSEL[%s] + Capture select registers for TIMER2 inputs + 0x60 + 32 + read-write + 0x1F + 0x1F + + + CAPTSEL + Input number to TIMER2 capture inputs 0 to 4 + 0 + 5 + read-write + + + val0 + CT_INP0 function selected from IOCON register + 0 + + + val1 + CT_INP1 function selected from IOCON register + 0x1 + + + val2 + CT_INP2 function selected from IOCON register + 0x2 + + + val3 + CT_INP3 function selected from IOCON register + 0x3 + + + val4 + CT_INP4 function selected from IOCON register + 0x4 + + + val5 + CT_INP5 function selected from IOCON register + 0x5 + + + val6 + CT_INP6 function selected from IOCON register + 0x6 + + + val7 + CT_INP7 function selected from IOCON register + 0x7 + + + val8 + CT_INP8 function selected from IOCON register + 0x8 + + + val9 + CT_INP9 function selected from IOCON register + 0x9 + + + val10 + CT_INP10 function selected from IOCON register + 0xA + + + val11 + CT_INP11 function selected from IOCON register + 0xB + + + val12 + CT_INP12 function selected from IOCON register + 0xC + + + val13 + CT_INP13 function selected from IOCON register + 0xD + + + val14 + CT_INP14 function selected from IOCON register + 0xE + + + val15 + CT_INP15 function selected from IOCON register + 0xF + + + val16 + CT_INP16 function selected from IOCON register + 0x10 + + + val17 + CT_INP17 function selected from IOCON register + 0x11 + + + val18 + CT_INP18 function selected from IOCON register + 0x12 + + + val19 + CT_INP19 function selected from IOCON register + 0x13 + + + val20 + USB0_FRAME_TOGGLE + 0x14 + + + val21 + USB1_FRAME_TOGGLE + 0x15 + + + val22 + COMP_OUTPUT output from analog comparator + 0x16 + + + val23 + I2S_SHARED_WS[0] output from I2S pin sharing + 0x17 + + + val24 + I2S_SHARED_WS[1] output from I2S pin sharing + 0x18 + + + val25 + None + 0x19 + + + val25 + None + 0x1A + + + val25 + None + 0x1B + + + val25 + None + 0x1C + + + val25 + None + 0x1D + + + val25 + None + 0x1E + + + val25 + None + 0x1F + + + + + + + 8 + 0x4 + PINTSEL[%s] + Pin interrupt select register + 0xC0 + 32 + read-write + 0x7F + 0x7F + + + INTPIN + Pin number select for pin interrupt or pattern match engine input. For PIOx_y: INTPIN = (x * 32) + y. PIO0_0 to PIO1_31 correspond to numbers 0 to 63. + 0 + 7 + read-write + + + + + 23 + 0x4 + DMA0_ITRIG_INMUX[%s] + Trigger select register for DMA0 channel + 0xE0 + 32 + read-write + 0x1F + 0x1F + + + INP + Trigger input number (decimal value) for DMA channel n (n = 0 to 22). + 0 + 5 + read-write + + + val0 + Pin interrupt 0 + 0 + + + val1 + Pin interrupt 1 + 0x1 + + + val2 + Pin interrupt 2 + 0x2 + + + val3 + Pin interrupt 3 + 0x3 + + + val4 + Timer CTIMER0 Match 0 + 0x4 + + + val5 + Timer CTIMER0 Match 1 + 0x5 + + + val6 + Timer CTIMER1 Match 0 + 0x6 + + + val7 + Timer CTIMER1 Match 1 + 0x7 + + + val8 + Timer CTIMER2 Match 0 + 0x8 + + + val9 + Timer CTIMER2 Match 1 + 0x9 + + + val10 + Timer CTIMER3 Match 0 + 0xA + + + val11 + Timer CTIMER3 Match 1 + 0xB + + + val12 + Timer CTIMER4 Match 0 + 0xC + + + val13 + Timer CTIMER4 Match 1 + 0xD + + + val14 + COMP_OUTPUT + 0xE + + + val15 + DMA0 output trigger mux 0 + 0xF + + + val16 + DMA0 output trigger mux 1 + 0x10 + + + val17 + DMA0 output trigger mux 1 + 0x11 + + + val18 + DMA0 output trigger mux 3 + 0x12 + + + val19 + SCT0 DMA request 0 + 0x13 + + + val20 + SCT0 DMA request 1 + 0x14 + + + val21 + HASH DMA RX trigger + 0x15 + + + val22 + None + 0x16 + + + val22 + None + 0x17 + + + val22 + None + 0x18 + + + val22 + None + 0x19 + + + val22 + None + 0x1A + + + val22 + None + 0x1B + + + val22 + None + 0x1C + + + val22 + None + 0x1D + + + val22 + None + 0x1E + + + val22 + None + 0x1F + + + + + + + 4 + 0x4 + DMA0_OTRIG_INMUX[%s] + DMA0 output trigger selection to become DMA0 trigger + 0x160 + 32 + read-write + 0x1F + 0x1F + + + INP + DMA trigger output number (decimal value) for DMA channel n (n = 0 to 22). + 0 + 5 + read-write + + + + + FREQMEAS_REF + Selection for frequency measurement reference clock + 0x180 + 32 + read-write + 0x1F + 0x1F + + + CLKIN + Clock source number (decimal value) for frequency measure function target clock: 0 = CLK_IN 1 = FRO 12 MHz oscillator 2 = Watchdog oscillator 3 = 32 kHz RTC oscillator 4 = Main clock (see Section 4.5.23) 5 = PIO0_4 6 = PIO0_20 7 = PIO0_24 8 = PIO1_4 + 0 + 5 + read-write + + + + + FREQMEAS_TARGET + Selection for frequency measurement target clock + 0x184 + 32 + read-write + 0x1F + 0x1F + + + CLKIN + Clock source number (decimal value) for frequency measure function target clock: 0 = CLK_IN 1 = FRO 12 MHz oscillator 2 = Watchdog oscillator 3 = 32 kHz RTC oscillator 4 = Main clock (see Section 4.5.23) 5 = PIO0_4 6 = PIO0_20 7 = PIO0_24 8 = PIO1_4 + 0 + 5 + read-write + + + + + 4 + 0x4 + TIMER3CAPTSEL[%s] + Capture select registers for TIMER3 inputs + 0x1A0 + 32 + read-write + 0x1F + 0x1F + + + CAPTSEL + Input number to TIMER3 capture inputs 0 to 4 + 0 + 5 + read-write + + + val0 + CT_INP0 function selected from IOCON register + 0 + + + val1 + CT_INP1 function selected from IOCON register + 0x1 + + + val2 + CT_INP2 function selected from IOCON register + 0x2 + + + val3 + CT_INP3 function selected from IOCON register + 0x3 + + + val4 + CT_INP4 function selected from IOCON register + 0x4 + + + val5 + CT_INP5 function selected from IOCON register + 0x5 + + + val6 + CT_INP6 function selected from IOCON register + 0x6 + + + val7 + CT_INP7 function selected from IOCON register + 0x7 + + + val8 + CT_INP8 function selected from IOCON register + 0x8 + + + val9 + CT_INP9 function selected from IOCON register + 0x9 + + + val10 + CT_INP10 function selected from IOCON register + 0xA + + + val11 + CT_INP11 function selected from IOCON register + 0xB + + + val12 + CT_INP12 function selected from IOCON register + 0xC + + + val13 + CT_INP13 function selected from IOCON register + 0xD + + + val14 + CT_INP14 function selected from IOCON register + 0xE + + + val15 + CT_INP15 function selected from IOCON register + 0xF + + + val16 + CT_INP16 function selected from IOCON register + 0x10 + + + val17 + CT_INP17 function selected from IOCON register + 0x11 + + + val18 + CT_INP18 function selected from IOCON register + 0x12 + + + val19 + CT_INP19 function selected from IOCON register + 0x13 + + + val20 + USB0_FRAME_TOGGLE + 0x14 + + + val21 + USB1_FRAME_TOGGLE + 0x15 + + + val22 + COMP_OUTPUT output from analog comparator + 0x16 + + + val23 + I2S_SHARED_WS[0] output from I2S pin sharing + 0x17 + + + val24 + I2S_SHARED_WS[1] output from I2S pin sharing + 0x18 + + + val25 + None + 0x19 + + + val25 + None + 0x1A + + + val25 + None + 0x1B + + + val25 + None + 0x1C + + + val25 + None + 0x1D + + + val25 + None + 0x1E + + + val25 + None + 0x1F + + + + + + + 4 + 0x4 + TIMER4CAPTSEL[%s] + Capture select registers for TIMER4 inputs + 0x1C0 + 32 + read-write + 0x1F + 0x1F + + + CAPTSEL + Input number to TIMER4 capture inputs 0 to 4 + 0 + 5 + read-write + + + val0 + CT_INP0 function selected from IOCON register + 0 + + + val1 + CT_INP1 function selected from IOCON register + 0x1 + + + val2 + CT_INP2 function selected from IOCON register + 0x2 + + + val3 + CT_INP3 function selected from IOCON register + 0x3 + + + val4 + CT_INP4 function selected from IOCON register + 0x4 + + + val5 + CT_INP5 function selected from IOCON register + 0x5 + + + val6 + CT_INP6 function selected from IOCON register + 0x6 + + + val7 + CT_INP7 function selected from IOCON register + 0x7 + + + val8 + CT_INP8 function selected from IOCON register + 0x8 + + + val9 + CT_INP9 function selected from IOCON register + 0x9 + + + val10 + CT_INP10 function selected from IOCON register + 0xA + + + val11 + CT_INP11 function selected from IOCON register + 0xB + + + val12 + CT_INP12 function selected from IOCON register + 0xC + + + val13 + CT_INP13 function selected from IOCON register + 0xD + + + val14 + CT_INP14 function selected from IOCON register + 0xE + + + val15 + CT_INP15 function selected from IOCON register + 0xF + + + val16 + CT_INP16 function selected from IOCON register + 0x10 + + + val17 + CT_INP17 function selected from IOCON register + 0x11 + + + val18 + CT_INP18 function selected from IOCON register + 0x12 + + + val19 + CT_INP19 function selected from IOCON register + 0x13 + + + val20 + USB0_FRAME_TOGGLE + 0x14 + + + val21 + USB1_FRAME_TOGGLE + 0x15 + + + val22 + COMP_OUTPUT output from analog comparator + 0x16 + + + val23 + I2S_SHARED_WS[0] output from I2S pin sharing + 0x17 + + + val24 + I2S_SHARED_WS[1] output from I2S pin sharing + 0x18 + + + val25 + None + 0x19 + + + val25 + None + 0x1A + + + val25 + None + 0x1B + + + val25 + None + 0x1C + + + val25 + None + 0x1D + + + val25 + None + 0x1E + + + val25 + None + 0x1F + + + + + + + 2 + 0x4 + PINTSECSEL[%s] + Pin interrupt secure select register + 0x1E0 + 32 + read-write + 0x3F + 0x3F + + + INTPIN + Pin number select for pin interrupt secure or pattern match engine input. For PIO0_x: INTPIN = x. PIO0_0 to PIO0_31 correspond to numbers 0 to 31. + 0 + 6 + read-write + + + + + 10 + 0x4 + DMA1_ITRIG_INMUX[%s] + Trigger select register for DMA1 channel + 0x200 + 32 + read-write + 0xF + 0xF + + + INP + Trigger input number (decimal value) for DMA channel n (n = 0 to 9). + 0 + 4 + read-write + + + val0 + Pin interrupt 0 + 0 + + + val1 + Pin interrupt 1 + 0x1 + + + val2 + Pin interrupt 2 + 0x2 + + + val3 + Pin interrupt 3 + 0x3 + + + val4 + Timer CTIMER0 Match 0 + 0x4 + + + val5 + Timer CTIMER0 Match 1 + 0x5 + + + val6 + Timer CTIMER2 Match 0 + 0x6 + + + val7 + Timer CTIMER4 Match 0 + 0x7 + + + val8 + DMA1 output trigger mux 0 + 0x8 + + + val9 + DMA1 output trigger mux 1 + 0x9 + + + val10 + DMA1 output trigger mux 2 + 0xA + + + val11 + DMA1 output trigger mux 3 + 0xB + + + val12 + SCT0 DMA request 0 + 0xC + + + val13 + SCT0 DMA request 1 + 0xD + + + val14 + HASH DMA RX trigger + 0xE + + + val15 + None + 0xF + + + + + + + 4 + 0x4 + DMA1_OTRIG_INMUX[%s] + DMA1 output trigger selection to become DMA1 trigger + 0x240 + 32 + read-write + 0xF + 0xF + + + INP + DMA trigger output number (decimal value) for DMA channel n (n = 0 to 9). + 0 + 4 + read-write + + + + + DMA0_REQ_ENA + Enable DMA0 requests + 0x740 + 32 + read-write + 0x7FFFFF + 0x7FFFFF + + + REQ_ENA + Controls the 23 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled. + 0 + 23 + read-write + + + + + DMA0_REQ_ENA_SET + Set one or several bits in DMA0_REQ_ENA register + 0x748 + 32 + write-only + 0 + 0x7FFFFF + + + SET + Write : If bit #i = 1, bit #i in DMA0_REQ_ENA register is set to 1; if bit #i = 0 , no change in DMA0_REQ_ENA register + 0 + 23 + write-only + + + + + DMA0_REQ_ENA_CLR + Clear one or several bits in DMA0_REQ_ENA register + 0x750 + 32 + write-only + 0 + 0x7FFFFF + + + CLR + Write : If bit #i = 1, bit #i in DMA0_REQ_ENA register is reset to 0; if bit #i = 0 , no change in DMA0_REQ_ENA register + 0 + 23 + write-only + + + + + DMA1_REQ_ENA + Enable DMA1 requests + 0x760 + 32 + read-write + 0x3FF + 0x3FF + + + REQ_ENA + Controls the 10 request inputs of DMA1. If bit i is '1' the DMA request input #i is enabled. + 0 + 10 + read-write + + + + + DMA1_REQ_ENA_SET + Set one or several bits in DMA1_REQ_ENA register + 0x768 + 32 + write-only + 0 + 0x3FF + + + SET + Write : If bit #i = 1, bit #i in DMA1_REQ_ENA register is set to 1; if bit #i = 0 , no change in DMA1_REQ_ENA register + 0 + 10 + write-only + + + + + DMA1_REQ_ENA_CLR + Clear one or several bits in DMA1_REQ_ENA register + 0x770 + 32 + write-only + 0 + 0x3FF + + + CLR + Write : If bit #i = 1, bit #i in DMA1_REQ_ENA register is reset to 0; if bit #i = 0 , no change in DMA1_REQ_ENA register + 0 + 10 + write-only + + + + + DMA0_ITRIG_ENA + Enable DMA0 triggers + 0x780 + 32 + read-write + 0x3FFFFF + 0x3FFFFF + + + ITRIG_ENA + Controls the 22 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled. + 0 + 22 + read-write + + + + + DMA0_ITRIG_ENA_SET + Set one or several bits in DMA0_ITRIG_ENA register + 0x788 + 32 + write-only + 0 + 0x3FFFFF + + + SET + Write : If bit #i = 1, bit #i in DMA0_ITRIG_ENA register is set to 1; if bit #i = 0 , no change in DMA0_ITRIG_ENA register + 0 + 22 + write-only + + + + + DMA0_ITRIG_ENA_CLR + Clear one or several bits in DMA0_ITRIG_ENA register + 0x790 + 32 + write-only + 0 + 0x3FFFFF + + + CLR + Write : If bit #i = 1, bit #i in DMA0_ITRIG_ENA register is reset to 0; if bit #i = 0 , no change in DMA0_ITRIG_ENA register + 0 + 22 + write-only + + + + + DMA1_ITRIG_ENA + Enable DMA1 triggers + 0x7A0 + 32 + read-write + 0x7FFF + 0x7FFF + + + ITRIG_ENA + Controls the 15 trigger inputs of DMA1. If bit i is '1' the DMA trigger input #i is enabled. + 0 + 15 + read-write + + + + + DMA1_ITRIG_ENA_SET + Set one or several bits in DMA1_ITRIG_ENA register + 0x7A8 + 32 + write-only + 0 + 0x7FFF + + + SET + Write : If bit #i = 1, bit #i in DMA1_ITRIG_ENA register is set to 1; if bit #i = 0 , no change in DMA1_ITRIG_ENA register + 0 + 15 + write-only + + + + + DMA1_ITRIG_ENA_CLR + Clear one or several bits in DMA1_ITRIG_ENA register + 0x7B0 + 32 + write-only + 0 + 0x7FFF + + + CLR + Write : If bit #i = 1, bit #i in DMA1_ITRIG_ENA register is reset to 0; if bit #i = 0 , no change in DMA1_ITRIG_ENA register + 0 + 15 + write-only + + + + + + + CTIMER0 + Standard counter/timers (CTIMER0 to 4) + CTIMER + CTIMER + 0x40008000 + + 0 + 0x88 + registers + + + CTIMER0 + 10 + + + + IR + Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. + 0 + 32 + read-write + 0 + 0xFF + + + MR0INT + Interrupt flag for match channel 0. + 0 + 1 + read-write + + + MR1INT + Interrupt flag for match channel 1. + 1 + 1 + read-write + + + MR2INT + Interrupt flag for match channel 2. + 2 + 1 + read-write + + + MR3INT + Interrupt flag for match channel 3. + 3 + 1 + read-write + + + CR0INT + Interrupt flag for capture channel 0 event. + 4 + 1 + read-write + + + CR1INT + Interrupt flag for capture channel 1 event. + 5 + 1 + read-write + + + CR2INT + Interrupt flag for capture channel 2 event. + 6 + 1 + read-write + + + CR3INT + Interrupt flag for capture channel 3 event. + 7 + 1 + read-write + + + + + TCR + Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. + 0x4 + 32 + read-write + 0 + 0x3 + + + CEN + Counter enable. + 0 + 1 + read-write + + + DISABLED + Disabled.The counters are disabled. + 0 + + + ENABLED + Enabled. The Timer Counter and Prescale Counter are enabled. + 0x1 + + + + + CRST + Counter reset. + 1 + 1 + read-write + + + DISABLED + Disabled. Do nothing. + 0 + + + ENABLED + Enabled. The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of the APB bus clock. The counters remain reset until TCR[1] is returned to zero. + 0x1 + + + + + + + TC + Timer Counter + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + TCVAL + Timer counter value. + 0 + 32 + read-write + + + + + PR + Prescale Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + PRVAL + Prescale counter value. + 0 + 32 + read-write + + + + + PC + Prescale Counter + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + PCVAL + Prescale counter value. + 0 + 32 + read-write + + + + + MCR + Match Control Register + 0x14 + 32 + read-write + 0 + 0xF000FFF + + + MR0I + Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. + 0 + 1 + read-write + + + MR0R + Reset on MR0: the TC will be reset if MR0 matches it. + 1 + 1 + read-write + + + MR0S + Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. + 2 + 1 + read-write + + + MR1I + Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC. + 3 + 1 + read-write + + + MR1R + Reset on MR1: the TC will be reset if MR1 matches it. + 4 + 1 + read-write + + + MR1S + Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. + 5 + 1 + read-write + + + MR2I + Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. + 6 + 1 + read-write + + + MR2R + Reset on MR2: the TC will be reset if MR2 matches it. + 7 + 1 + read-write + + + MR2S + Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC. + 8 + 1 + read-write + + + MR3I + Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC. + 9 + 1 + read-write + + + MR3R + Reset on MR3: the TC will be reset if MR3 matches it. + 10 + 1 + read-write + + + MR3S + Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. + 11 + 1 + read-write + + + MR0RL + Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR). + 24 + 1 + read-write + + + MR1RL + Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR). + 25 + 1 + read-write + + + MR2RL + Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR). + 26 + 1 + read-write + + + MR3RL + Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR). + 27 + 1 + read-write + + + + + 4 + 0x4 + MR[%s] + Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + MATCH + Timer counter match value. + 0 + 32 + read-write + + + + + CCR + Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. + 0x28 + 32 + read-write + 0 + 0xFFF + + + CAP0RE + Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. + 0 + 1 + read-write + + + CAP0FE + Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. + 1 + 1 + read-write + + + CAP0I + Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt. + 2 + 1 + read-write + + + CAP1RE + Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. + 3 + 1 + read-write + + + CAP1FE + Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. + 4 + 1 + read-write + + + CAP1I + Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt. + 5 + 1 + read-write + + + CAP2RE + Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. + 6 + 1 + read-write + + + CAP2FE + Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. + 7 + 1 + read-write + + + CAP2I + Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt. + 8 + 1 + read-write + + + CAP3RE + Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. + 9 + 1 + read-write + + + CAP3FE + Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. + 10 + 1 + read-write + + + CAP3I + Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt. + 11 + 1 + read-write + + + + + 4 + 0x4 + CR[%s] + Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input. + 0x2C + 32 + read-only + 0 + 0xFFFFFFFF + + + CAP + Timer counter capture value. + 0 + 32 + read-only + + + + + EMR + External Match Register. The EMR controls the match function and the external match pins. + 0x3C + 32 + read-write + 0 + 0xFFF + + + EM0 + External Match 0. This bit reflects the state of output MAT0, whether or not this output is connected to a pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by EMR[5:4]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH. + 0 + 1 + read-write + + + EM1 + External Match 1. This bit reflects the state of output MAT1, whether or not this output is connected to a pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by EMR[7:6]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH. + 1 + 1 + read-write + + + EM2 + External Match 2. This bit reflects the state of output MAT2, whether or not this output is connected to a pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by EMR[9:8]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH. + 2 + 1 + read-write + + + EM3 + External Match 3. This bit reflects the state of output MAT3, whether or not this output is connected to a pin. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by MR[11:10]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH. + 3 + 1 + read-write + + + EMC0 + External Match Control 0. Determines the functionality of External Match 0. + 4 + 2 + read-write + + + DO_NOTHING + Do Nothing. + 0 + + + CLEAR + Clear. Clear the corresponding External Match bit/output to 0 (MAT0 pin is LOW if pinned out). + 0x1 + + + SET + Set. Set the corresponding External Match bit/output to 1 (MAT0 pin is HIGH if pinned out). + 0x2 + + + TOGGLE + Toggle. Toggle the corresponding External Match bit/output. + 0x3 + + + + + EMC1 + External Match Control 1. Determines the functionality of External Match 1. + 6 + 2 + read-write + + + DO_NOTHING + Do Nothing. + 0 + + + CLEAR + Clear. Clear the corresponding External Match bit/output to 0 (MAT1 pin is LOW if pinned out). + 0x1 + + + SET + Set. Set the corresponding External Match bit/output to 1 (MAT1 pin is HIGH if pinned out). + 0x2 + + + TOGGLE + Toggle. Toggle the corresponding External Match bit/output. + 0x3 + + + + + EMC2 + External Match Control 2. Determines the functionality of External Match 2. + 8 + 2 + read-write + + + DO_NOTHING + Do Nothing. + 0 + + + CLEAR + Clear. Clear the corresponding External Match bit/output to 0 (MAT2 pin is LOW if pinned out). + 0x1 + + + SET + Set. Set the corresponding External Match bit/output to 1 (MAT2 pin is HIGH if pinned out). + 0x2 + + + TOGGLE + Toggle. Toggle the corresponding External Match bit/output. + 0x3 + + + + + EMC3 + External Match Control 3. Determines the functionality of External Match 3. + 10 + 2 + read-write + + + DO_NOTHING + Do Nothing. + 0 + + + CLEAR + Clear. Clear the corresponding External Match bit/output to 0 (MAT3 pin is LOW if pinned out). + 0x1 + + + SET + Set. Set the corresponding External Match bit/output to 1 (MAT3 pin is HIGH if pinned out). + 0x2 + + + TOGGLE + Toggle. Toggle the corresponding External Match bit/output. + 0x3 + + + + + + + CTCR + Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. + 0x70 + 32 + read-write + 0 + 0xFF + + + CTMODE + Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register. + 0 + 2 + read-write + + + TIMER + Timer Mode. Incremented every rising APB bus clock edge. + 0 + + + COUNTER_RISING_EDGE + Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2. + 0x1 + + + COUNTER_FALLING_EDGE + Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2. + 0x2 + + + COUNTER_DUAL_EDGE + Counter Mode dual edge. TC is incremented on both edges on the CAP input selected by bits 3:2. + 0x3 + + + + + CINSEL + Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer. + 2 + 2 + read-write + + + CHANNEL_0 + Channel 0. CAPn.0 for CTIMERn + 0 + + + CHANNEL_1 + Channel 1. CAPn.1 for CTIMERn + 0x1 + + + CHANNEL_2 + Channel 2. CAPn.2 for CTIMERn + 0x2 + + + CHANNEL_3 + Channel 3. CAPn.3 for CTIMERn + 0x3 + + + + + ENCC + Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs. + 4 + 1 + read-write + + + SELCC + Edge select. When bit 4 is 1, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved. + 5 + 3 + read-write + + + CHANNEL_0_RISING + Channel 0 Rising Edge. Rising edge of the signal on capture channel 0 clears the timer (if bit 4 is set). + 0 + + + CHANNEL_0_FALLING + Channel 0 Falling Edge. Falling edge of the signal on capture channel 0 clears the timer (if bit 4 is set). + 0x1 + + + CHANNEL_1_RISING + Channel 1 Rising Edge. Rising edge of the signal on capture channel 1 clears the timer (if bit 4 is set). + 0x2 + + + CHANNEL_1_FALLING + Channel 1 Falling Edge. Falling edge of the signal on capture channel 1 clears the timer (if bit 4 is set). + 0x3 + + + CHANNEL_2_RISING + Channel 2 Rising Edge. Rising edge of the signal on capture channel 2 clears the timer (if bit 4 is set). + 0x4 + + + CHANNEL_2_FALLING + Channel 2 Falling Edge. Falling edge of the signal on capture channel 2 clears the timer (if bit 4 is set). + 0x5 + + + + + + + PWMC + PWM Control Register. This register enables PWM mode for the external match pins. + 0x74 + 32 + read-write + 0 + 0xF + + + PWMEN0 + PWM mode enable for channel0. + 0 + 1 + read-write + + + MATCH + Match. CTIMERn_MAT0 is controlled by EM0. + 0 + + + PWM + PWM. PWM mode is enabled for CTIMERn_MAT0. + 0x1 + + + + + PWMEN1 + PWM mode enable for channel1. + 1 + 1 + read-write + + + MATCH + Match. CTIMERn_MAT01 is controlled by EM1. + 0 + + + PWM + PWM. PWM mode is enabled for CTIMERn_MAT1. + 0x1 + + + + + PWMEN2 + PWM mode enable for channel2. + 2 + 1 + read-write + + + MATCH + Match. CTIMERn_MAT2 is controlled by EM2. + 0 + + + PWM + PWM. PWM mode is enabled for CTIMERn_MAT2. + 0x1 + + + + + PWMEN3 + PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle. + 3 + 1 + read-write + + + MATCH + Match. CTIMERn_MAT3 is controlled by EM3. + 0 + + + PWM + PWM. PWM mode is enabled for CT132Bn_MAT3. + 0x1 + + + + + + + 4 + 0x4 + MSR[%s] + Match Shadow Register + 0x78 + 32 + read-write + 0 + 0xFFFFFFFF + + + SHADOWW + Timer counter match shadow value. + 0 + 32 + read-write + + + + + + + CTIMER1 + Standard counter/timers (CTIMER0 to 4) + CTIMER + 0x40009000 + + 0 + 0x88 + registers + + + CTIMER1 + 11 + + + + CTIMER2 + Standard counter/timers (CTIMER0 to 4) + CTIMER + 0x40028000 + + 0 + 0x88 + registers + + + CTIMER2 + 36 + + + + CTIMER3 + Standard counter/timers (CTIMER0 to 4) + CTIMER + 0x40029000 + + 0 + 0x88 + registers + + + CTIMER3 + 13 + + + + CTIMER4 + Standard counter/timers (CTIMER0 to 4) + CTIMER + 0x4002A000 + + 0 + 0x88 + registers + + + CTIMER4 + 37 + + + + WWDT + Windowed Watchdog Timer (WWDT) + WWDT + 0x4000C000 + + 0 + 0x1C + registers + + + WDT_BOD + 0 + + + + MOD + Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. + 0 + 32 + read-write + 0 + 0x3F + + + WDEN + Watchdog enable bit. Once this bit is set to one and a watchdog feed is performed, the watchdog timer will run permanently. + 0 + 1 + read-write + + + STOP + Stop. The watchdog timer is stopped. + 0 + + + RUN + Run. The watchdog timer is running. + 0x1 + + + + + WDRESET + Watchdog reset enable bit. Once this bit has been written with a 1 it cannot be re-written with a 0. + 1 + 1 + read-write + + + INTERRUPT + Interrupt. A watchdog time-out will not cause a chip reset. + 0 + + + RESET + Reset. A watchdog time-out will cause a chip reset. + 0x1 + + + + + WDTOF + Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by events associated with WDPROTECT. Cleared by software writing a 0 to this bit position. Causes a chip reset if WDRESET = 1. + 2 + 1 + read-write + + + WDINT + Warning interrupt flag. Set when the timer is at or below the value in WDWARNINT. Cleared by software writing a 1 to this bit position. Note that this bit cannot be cleared while the WARNINT value is equal to the value of the TV register. This can occur if the value of WARNINT is 0 and the WDRESET bit is 0 when TV decrements to 0. + 3 + 1 + read-write + + + WDPROTECT + Watchdog update mode. This bit can be set once by software and is only cleared by a reset. + 4 + 1 + read-write + + + FLEXIBLE + Flexible. The watchdog time-out value (TC) can be changed at any time. + 0 + + + THRESHOLD + Threshold. The watchdog time-out value (TC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW. + 0x1 + + + + + + + TC + Watchdog timer constant register. This 24-bit register determines the time-out value. + 0x4 + 32 + read-write + 0xFF + 0xFFFFFF + + + COUNT + Watchdog time-out value. + 0 + 24 + read-write + + + + + FEED + Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC. + 0x8 + 32 + write-only + 0 + 0 + + + FEED + Feed value should be 0xAA followed by 0x55. + 0 + 8 + write-only + + + + + TV + Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer. + 0xC + 32 + read-only + 0xFF + 0xFFFFFF + + + COUNT + Counter timer value. + 0 + 24 + read-only + + + + + WARNINT + Watchdog Warning Interrupt compare value. + 0x14 + 32 + read-write + 0 + 0x3FF + + + WARNINT + Watchdog warning interrupt compare value. + 0 + 10 + read-write + + + + + WINDOW + Watchdog Window compare value. + 0x18 + 32 + read-write + 0xFFFFFF + 0xFFFFFF + + + WINDOW + Watchdog window value. + 0 + 24 + read-write + + + + + + + MRT0 + Multi-Rate Timer (MRT) + MRT + 0x4000D000 + + 0 + 0xFC + registers + + + MRT0 + 9 + + + + 4 + 0x10 + CHANNEL[%s] + no description available + 0 + + INTVAL + MRT Time interval value register. This value is loaded into the TIMER register. + 0 + 32 + read-write + 0 + 0x80FFFFFF + + + IVALUE + Time interval load value. This value is loaded into the TIMERn register and the MRT channel n starts counting down from IVALUE -1. If the timer is idle, writing a non-zero value to this bit field starts the timer immediately. If the timer is running, writing a zero to this bit field does the following: If LOAD = 1, the timer stops immediately. If LOAD = 0, the timer stops at the end of the time interval. + 0 + 24 + read-write + + + LOAD + Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. This bit is write-only. Reading this bit always returns 0. + 31 + 1 + read-write + + + NO_FORCE_LOAD + No force load. The load from the INTVALn register to the TIMERn register is processed at the end of the time interval if the repeat mode is selected. + 0 + + + FORCE_LOAD + Force load. The INTVALn interval value IVALUE -1 is immediately loaded into the TIMERn register while TIMERn is running. + 0x1 + + + + + + + TIMER + MRT Timer register. This register reads the value of the down-counter. + 0x4 + 32 + read-only + 0xFFFFFF + 0xFFFFFF + + + VALUE + Holds the current timer value of the down-counter. The initial value of the TIMERn register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval or immediately in the following cases: INTVALn register is updated in the idle state. INTVALn register is updated with LOAD = 1. When the timer is in idle state, reading this bit fields returns -1 (0x00FF FFFF). + 0 + 24 + read-only + + + + + CTRL + MRT Control register. This register controls the MRT modes. + 0x8 + 32 + read-write + 0 + 0x7 + + + INTEN + Enable the TIMERn interrupt. + 0 + 1 + read-write + + + DISABLED + Disabled. TIMERn interrupt is disabled. + 0 + + + ENABLED + Enabled. TIMERn interrupt is enabled. + 0x1 + + + + + MODE + Selects timer mode. + 1 + 2 + read-write + + + REPEAT_INTERRUPT_MODE + Repeat interrupt mode. + 0 + + + ONE_SHOT_INTERRUPT_MODE + One-shot interrupt mode. + 0x1 + + + ONE_SHOT_STALL_MODE + One-shot stall mode. + 0x2 + + + + + + + STAT + MRT Status register. + 0xC + 32 + read-write + 0 + 0x7 + + + INTFLAG + Monitors the interrupt flag. + 0 + 1 + read-write + + + NO_PENDING_INTERRUPT + No pending interrupt. Writing a zero is equivalent to no operation. + 0 + + + PENDING_INTERRUPT + Pending interrupt. The interrupt is pending because TIMERn has reached the end of the time interval. If the INTEN bit in the CONTROLn is also set to 1, the interrupt for timer channel n and the global interrupt are raised. Writing a 1 to this bit clears the interrupt request. + 0x1 + + + + + RUN + Indicates the state of TIMERn. This bit is read-only. + 1 + 1 + read-write + + + IDLE_STATE + Idle state. TIMERn is stopped. + 0 + + + RUNNING + Running. TIMERn is running. + 0x1 + + + + + INUSE + Channel In Use flag. Operating details depend on the MULTITASK bit in the MODCFG register, and affects the use of IDLE_CH. See Idle channel register for details of the two operating modes. + 2 + 1 + read-write + + + NO + This channel is not in use. + 0 + + + YES + This channel is in use. + 0x1 + + + + + + + + MODCFG + Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature. + 0xF0 + 32 + read-write + 0x173 + 0x800001FF + + + NOC + Identifies the number of channels in this MRT.(4 channels on this device.) + 0 + 4 + read-write + + + NOB + Identifies the number of timer bits in this MRT. (24 bits wide on this device.) + 4 + 5 + read-write + + + MULTITASK + Selects the operating mode for the INUSE flags and the IDLE_CH register. + 31 + 1 + read-write + + + HARDWARE_STATUS_MODE + Hardware status mode. In this mode, the INUSE(n) flags for all channels are reset. + 0 + + + MULTI_TASK_MODE + Multi-task mode. + 0x1 + + + + + + + IDLE_CH + Idle channel register. This register returns the number of the first idle channel. + 0xF4 + 32 + read-only + 0 + 0xF0 + + + CHAN + Idle channel. Reading the CHAN bits, returns the lowest idle timer channel. The number is positioned such that it can be used as an offset from the MRT base address in order to access the registers for the allocated channel. If all timer channels are running, CHAN = 0xF. See text above for more details. + 4 + 4 + read-only + + + + + IRQ_FLAG + Global interrupt flag register + 0xF8 + 32 + read-write + 0 + 0xF + + + GFLAG0 + Monitors the interrupt flag of TIMER0. + 0 + 1 + read-write + + + NO_PENDING_INTERRUPT + No pending interrupt. Writing a zero is equivalent to no operation. + 0 + + + PENDING_INTERRUPT + Pending interrupt. The interrupt is pending because TIMER0 has reached the end of the time interval. If the INTEN bit in the CONTROL0 register is also set to 1, the interrupt for timer channel 0 and the global interrupt are raised. Writing a 1 to this bit clears the interrupt request. + 0x1 + + + + + GFLAG1 + Monitors the interrupt flag of TIMER1. See description of channel 0. + 1 + 1 + read-write + + + GFLAG2 + Monitors the interrupt flag of TIMER2. See description of channel 0. + 2 + 1 + read-write + + + GFLAG3 + Monitors the interrupt flag of TIMER3. See description of channel 0. + 3 + 1 + read-write + + + + + + + UTICK0 + Micro-tick Timer (UTICK) + UTICK + 0x4000E000 + + 0 + 0x20 + registers + + + UTICK0 + 8 + + + + CTRL + Control register. + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DELAYVAL + Tick interval value. The delay will be equal to DELAYVAL + 1 periods of the timer clock. The minimum usable value is 1, for a delay of 2 timer clocks. A value of 0 stops the timer. + 0 + 31 + read-write + + + REPEAT + Repeat delay. 0 = One-time delay. 1 = Delay repeats continuously. + 31 + 1 + read-write + + + + + STAT + Status register. + 0x4 + 32 + read-write + 0 + 0x3 + + + INTR + Interrupt flag. 0 = No interrupt is pending. 1 = An interrupt is pending. A write of any value to this register clears this flag. + 0 + 1 + read-write + + + ACTIVE + Active flag. 0 = The Micro-Tick Timer is stopped. 1 = The Micro-Tick Timer is currently active. + 1 + 1 + read-write + + + + + CFG + Capture configuration register. + 0x8 + 32 + read-write + 0 + 0xF0F + + + CAPEN0 + Enable Capture 0. 1 = Enabled, 0 = Disabled. + 0 + 1 + read-write + + + CAPEN1 + Enable Capture 1. 1 = Enabled, 0 = Disabled. + 1 + 1 + read-write + + + CAPEN2 + Enable Capture 2. 1 = Enabled, 0 = Disabled. + 2 + 1 + read-write + + + CAPEN3 + Enable Capture 3. 1 = Enabled, 0 = Disabled. + 3 + 1 + read-write + + + CAPPOL0 + Capture Polarity 0. 0 = Positive edge capture, 1 = Negative edge capture. + 8 + 1 + read-write + + + CAPPOL1 + Capture Polarity 1. 0 = Positive edge capture, 1 = Negative edge capture. + 9 + 1 + read-write + + + CAPPOL2 + Capture Polarity 2. 0 = Positive edge capture, 1 = Negative edge capture. + 10 + 1 + read-write + + + CAPPOL3 + Capture Polarity 3. 0 = Positive edge capture, 1 = Negative edge capture. + 11 + 1 + read-write + + + + + CAPCLR + Capture clear register. + 0xC + 32 + write-only + 0 + 0 + + + CAPCLR0 + Clear capture 0. Writing 1 to this bit clears the CAP0 register value. + 0 + 1 + write-only + + + CAPCLR1 + Clear capture 1. Writing 1 to this bit clears the CAP1 register value. + 1 + 1 + write-only + + + CAPCLR2 + Clear capture 2. Writing 1 to this bit clears the CAP2 register value. + 2 + 1 + write-only + + + CAPCLR3 + Clear capture 3. Writing 1 to this bit clears the CAP3 register value. + 3 + 1 + write-only + + + + + 4 + 0x4 + CAP[%s] + Capture register . + 0x10 + 32 + read-only + 0 + 0xFFFFFFFF + + + CAP_VALUE + Capture value for the related capture event (UTICK_CAPn. Note: the value is 1 lower than the actual value of the Micro-tick Timer at the moment of the capture event. + 0 + 31 + read-only + + + VALID + Capture Valid. When 1, a value has been captured based on a transition of the related UTICK_CAPn pin. Cleared by writing to the related bit in the CAPCLR register. + 31 + 1 + read-only + + + + + + + ANACTRL + ANALOGCTRL + ANACTRL + 0x40013000 + + 0 + 0x10C + registers + + + + ANALOG_CTRL_CFG + Various Analog blocks configuration (like FRO 192MHz trimmings source ...) + 0 + 32 + read-write + 0 + 0x1 + + + FRO192M_TRIM_SRC + FRO192M trimming and 'Enable' source. + 0 + 1 + read-write + + + EFUSE + FRO192M trimming and 'Enable' comes from eFUSE. + 0 + + + FRO192MCTRL + FRO192M trimming and 'Enable' comes from FRO192M_CTRL registers. + 0x1 + + + + + + + ANALOG_CTRL_STATUS + Analog Macroblock Identity registers, Flash Status registers + 0x4 + 32 + read-only + 0x50000000 + 0xF0003FFF + + + PMU_ID + Power Management Unit (PMU) Analog macro-bloc identification number : . + 0 + 6 + read-only + + + OSC_ID + Oscillators Analog macro-bloc identification number : . + 6 + 6 + read-only + + + FLASH_PWRDWN + Flash Power Down status. + 12 + 1 + read-only + + + PWRUP + Flash is not in power down mode. + 0 + + + PWRDWN + Flash is in power down mode. + 0x1 + + + + + FLASH_INIT_ERROR + Flash initialization error status. + 13 + 1 + read-only + + + NOERROR + No error. + 0 + + + ERROR + At least one error occured during flash initialization.. + 0x1 + + + + + FINAL_TEST_DONE_VECT + Indicates current status of Final Test. + 28 + 4 + read-only + + + + + FREQ_ME_CTRL + Frequency Measure function control register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPVAL_SCALE + Frequency measure result /Frequency measur scale + 0 + 31 + read-write + + + PROG + Set this bit to one to initiate a frequency measurement cycle. Hardware clears this bit when the measurement cycle has completed and there is valid capture data in the CAPVAL field (bits 30:0). + 31 + 1 + read-write + + + + + FRO192M_CTRL + 192MHz Free Running OScillator (FRO) Control register + 0x10 + 32 + read-write + 0x80D01A + 0xF3FFFFBF + + + BIAS_TRIM + Bias trimming bits (course frequency trimming). + 0 + 6 + read-write + + + TEMP_TRIM + Temperature coefficient trimming bits. + 7 + 7 + read-write + + + ENA_12MHZCLK + 12 MHz clock control. + 14 + 1 + read-write + + + DISABLE + 12 MHz clock is disabled. + 0 + + + ENABLE + 12 MHz clock is enabled. + 0x1 + + + + + ENA_48MHZCLK + 48 MHz clock control. + 15 + 1 + read-write + + + DISABLE + 48 MHz clock is disabled. + 0 + + + ENABLE + 48 MHz clock is enabled. + 0x1 + + + + + DAC_TRIM + Curdac trimming bits (fine frequency trimming) This trim is used to adjust the frequency, given that the bias and temperature trim are set. + 16 + 8 + read-write + + + USBCLKADJ + If this bit is set and the USB peripheral is enabled into full speed device mode, the USB block will provide FRO clock adjustments to lock it to the host clock using the SOF packets. + 24 + 1 + read-write + + + USBMODCHG + If this reads as 1 when reading the DAC_TRIM field and USBCLKADJ=1, it should be reread until it is 0. + 25 + 1 + read-only + + + ATB_CTRL + Analog Test Bus control. + 28 + 2 + read-write + + + ENA_96MHZCLK + 96 MHz clock control. + 30 + 1 + read-write + + + DISABLE + 96 MHz clock is disabled. + 0 + + + ENABLE + 96 MHz clock is enabled. + 0x1 + + + + + WRTRIM + This must be written to 1 to modify the BIAS_TRIM and TEMP_TRIM fields. + 31 + 1 + write-only + + + + + FRO192M_STATUS + 192MHz Free Running OScillator (FRO) Status register + 0x14 + 32 + read-write + 0x3 + 0x3 + + + CLK_VALID + Output clock valid signal. Indicates that CCO clock has settled. + 0 + 1 + read-only + + + NOCLKOUT + No output clock present (None of 12 MHz, 48 MHz or 96 MHz clock is available). + 0 + + + CLKOUT + Clock is present (12 MHz, 48 MHz or 96 MHz can be output if they are enable respectively by FRO192M_CTRL.ENA_12MHZCLK/ENA_48MHZCLK/ENA_96MHZCLK). + 0x1 + + + + + ATB_VCTRL + CCO threshold voltage detector output (signal vcco_ok). Once the CCO voltage crosses the threshold voltage of a SLVT transistor, this output signal will go high. It is also possible to observe the clk_valid signal. + 1 + 1 + read-only + + + + + ADC_CTRL + General Purpose ADC VBAT Divider branch control + 0x18 + 32 + read-write + 0 + 0x1 + + + VBATDIVENABLE + Switch On/Off VBAT divider branch. + 0 + 1 + read-write + + + DISABLE + VBAT divider branch is disabled. + 0 + + + ENABLE + VBAT divider branch is enabled. + 0x1 + + + + + + + XO32M_CTRL + 32 MHz Crystal Oscillator Control register + 0x20 + 32 + read-write + 0x21428A + 0x1FFFFFFE + + + GM + Gm value for Xo. + 1 + 3 + read-write + + + SLAVE + Xo in slave mode. + 4 + 1 + read-write + + + AMP + Amplitude selection , Min amp : 001, Max amp : 110. + 5 + 3 + read-write + + + OSC_CAP_IN + Tune capa banks of Crystal 32-MHz input pin + 8 + 7 + read-write + + + OSC_CAP_OUT + Tune capa banks of Crystal 32-MHz output pin + 15 + 7 + read-write + + + ACBUF_PASS_ENABLE + Bypass enable of XO AC buffer enable in pll and top level. + 22 + 1 + read-write + + + DISABLE + XO AC buffer bypass is disabled. + 0 + + + ENABLE + XO AC buffer bypass is enabled. + 0x1 + + + + + ENABLE_PLL_USB_OUT + Enable XO 32 MHz output to USB HS PLL. + 23 + 1 + read-write + + + DISABLE + XO 32 MHz output to USB HS PLL is disabled. + 0 + + + ENABLE + XO 32 MHz output to USB HS PLL is enabled. + 0x1 + + + + + ENABLE_SYSTEM_CLK_OUT + Enable XO 32 MHz output to CPU system. + 24 + 1 + read-write + + + DISABLE + XO 32 MHz output to CPU system is disabled. + 0 + + + ENABLE + XO 32 MHz output to CPU system is enabled. + 0x1 + + + + + CAPTESTSTARTSRCSEL + Source selection for 'xo32k_captest_start' signal. + 25 + 1 + read-write + + + CAPTEST + Sourced from CAPTESTSTART. + 0 + + + CALIB + Sourced from calibration. + 0x1 + + + + + CAPTESTSTART + 1: Start CapTest. + 26 + 1 + read-write + + + CAPTESTENABLE + Enable signal for captest. + 27 + 1 + read-write + + + DISABLE + Captest is disabled. + 0 + + + ENABLE + Captest is enabled. + 0x1 + + + + + CAPTESTOSCINSEL + Select the input for test. + 28 + 1 + read-write + + + OSCOUT + osc_out (oscillator output) pin. + 0 + + + OSCIN + osc_in (oscillator) pin. + 0x1 + + + + + + + XO32M_STATUS + 32 MHz Crystal Oscillator Status register + 0x24 + 32 + read-only + 0 + 0x1 + + + XO_READY + Indicates XO out frequency statibilty. + 0 + 1 + read-only + + + NOT_STABLE + XO output frequency is not yet stable. + 0 + + + STABLE + XO output frequency is stable. + 0x1 + + + + + + + BOD_DCDC_INT_CTRL + Brown Out Detectors (BoDs) & DCDC interrupts generation control register + 0x30 + 32 + read-write + 0 + 0x3F + + + BODVBAT_INT_ENABLE + BOD VBAT interrupt control. + 0 + 1 + read-write + + + DISABLE + BOD VBAT interrupt is disabled. + 0 + + + ENABLE + BOD VBAT interrupt is enabled. + 0x1 + + + + + BODVBAT_INT_CLEAR + BOD VBAT interrupt clear.1: Clear the interrupt. Self-cleared bit. + 1 + 1 + read-write + + + BODCORE_INT_ENABLE + BOD CORE interrupt control. + 2 + 1 + read-write + + + DISABLE + BOD CORE interrupt is disabled. + 0 + + + ENABLE + BOD CORE interrupt is enabled. + 0x1 + + + + + BODCORE_INT_CLEAR + BOD CORE interrupt clear.1: Clear the interrupt. Self-cleared bit. + 3 + 1 + read-write + + + DCDC_INT_ENABLE + DCDC interrupt control. + 4 + 1 + read-write + + + DISABLE + DCDC interrupt is disabled. + 0 + + + ENABLE + DCDC interrupt is enabled. + 0x1 + + + + + DCDC_INT_CLEAR + DCDC interrupt clear.1: Clear the interrupt. Self-cleared bit. + 5 + 1 + read-write + + + + + BOD_DCDC_INT_STATUS + BoDs & DCDC interrupts status register + 0x34 + 32 + read-only + 0x104 + 0x1FF + + + BODVBAT_STATUS + BOD VBAT Interrupt status before Interrupt Enable. + 0 + 1 + read-only + + + NOT_PENDING + No interrupt pending.. + 0 + + + PENDING + Interrupt pending.. + 0x1 + + + + + BODVBAT_INT_STATUS + BOD VBAT Interrupt status after Interrupt Enable. + 1 + 1 + read-only + + + NOT_PENDING + No interrupt pending.. + 0 + + + PENDING + Interrupt pending.. + 0x1 + + + + + BODVBAT_VAL + Current value of BOD VBAT power status output. + 2 + 1 + read-only + + + NOT_OK + VBAT voltage level is below the threshold. + 0 + + + OK + VBAT voltage level is above the threshold. + 0x1 + + + + + BODCORE_STATUS + BOD CORE Interrupt status before Interrupt Enable. + 3 + 1 + read-only + + + NOT_PENDING + No interrupt pending.. + 0 + + + PENDING + Interrupt pending.. + 0x1 + + + + + BODCORE_INT_STATUS + BOD CORE Interrupt status after Interrupt Enable. + 4 + 1 + read-only + + + NOT_PENDING + No interrupt pending.. + 0 + + + PENDING + Interrupt pending.. + 0x1 + + + + + BODCORE_VAL + Current value of BOD CORE power status output. + 5 + 1 + read-only + + + NOT_OK + CORE voltage level is below the threshold. + 0 + + + OK + CORE voltage level is above the threshold. + 0x1 + + + + + DCDC_STATUS + DCDC Interrupt status before Interrupt Enable. + 6 + 1 + read-only + + + NOT_PENDING + No interrupt pending.. + 0 + + + PENDING + Interrupt pending.. + 0x1 + + + + + DCDC_INT_STATUS + DCDC Interrupt status after Interrupt Enable. + 7 + 1 + read-only + + + NOT_PENDING + No interrupt pending.. + 0 + + + PENDING + Interrupt pending.. + 0x1 + + + + + DCDC_VAL + Current value of DCDC power status output. + 8 + 1 + read-only + + + NOT_OK + DCDC output Voltage is below the targeted regulation level. + 0 + + + OK + DCDC output Voltage is above the targeted regulation level. + 0x1 + + + + + + + RINGO0_CTRL + First Ring Oscillator module control register. + 0x40 + 32 + read-write + 0x40 + 0x803F1FFF + + + SL + Select short or long ringo (for all ringos types). + 0 + 1 + read-write + + + SHORT + Select short ringo (few elements). + 0 + + + LONG + Select long ringo (many elements). + 0x1 + + + + + FS + Ringo frequency output divider. + 1 + 1 + read-write + + + FAST + High frequency output (frequency lower than 100 MHz). + 0 + + + SLOW + Low frequency output (frequency lower than 10 MHz). + 0x1 + + + + + SWN_SWP + PN-Ringos (P-Transistor and N-Transistor processing) control. + 2 + 2 + read-write + + + NORMAL + Normal mode. + 0 + + + P_MONITOR + P-Monitor mode. Measure with weak P transistor. + 0x1 + + + N_MONITOR + P-Monitor mode. Measure with weak N transistor. + 0x2 + + + FORBIDDEN + Don't use. + 0x3 + + + + + PD + Ringo module Power control. + 4 + 1 + read-write + + + POWERED_ON + The Ringo module is enabled. + 0 + + + POWERED_DOWN + The Ringo module is disabled. + 0x1 + + + + + E_ND0 + First NAND2-based ringo control. + 5 + 1 + read-write + + + DISABLE + First NAND2-based ringo is disabled. + 0 + + + ENABLE + First NAND2-based ringo is enabled. + 0x1 + + + + + E_ND1 + Second NAND2-based ringo control. + 6 + 1 + read-write + + + DISABLE + Second NAND2-based ringo is disabled. + 0 + + + ENABLE + Second NAND2-based ringo is enabled. + 0x1 + + + + + E_NR0 + First NOR2-based ringo control. + 7 + 1 + read-write + + + DISABLE + First NOR2-based ringo is disabled. + 0 + + + ENABLE + First NOR2-based ringo is enabled. + 0x1 + + + + + E_NR1 + Second NOR2-based ringo control. + 8 + 1 + read-write + + + DISABLE + Second NORD2-based ringo is disabled. + 0 + + + ENABLE + Second NORD2-based ringo is enabled. + 0x1 + + + + + E_IV0 + First Inverter-based ringo control. + 9 + 1 + read-write + + + DISABLE + First INV-based ringo is disabled. + 0 + + + ENABLE + First INV-based ringo is enabled. + 0x1 + + + + + E_IV1 + Second Inverter-based ringo control. + 10 + 1 + read-write + + + DISABLE + Second INV-based ringo is disabled. + 0 + + + ENABLE + Second INV-based ringo is enabled. + 0x1 + + + + + E_PN0 + First PN (P-Transistor and N-Transistor processing) monitor control. + 11 + 1 + read-write + + + DISABLE + First PN-based ringo is disabled. + 0 + + + ENABLE + First PN-based ringo is enabled. + 0x1 + + + + + E_PN1 + Second PN (P-Transistor and N-Transistor processing) monitor control. + 12 + 1 + read-write + + + DISABLE + Second PN-based ringo is disabled. + 0 + + + ENABLE + Second PN-based ringo is enabled. + 0x1 + + + + + DIVISOR + Ringo out Clock divider value. Frequency Output = Frequency input / (DIViSOR+1). (minimum = Frequency input / 16) + 16 + 4 + read-write + + + DIV_UPDATE_REQ + Ringo clock out Divider status flag. Set when a change is made to the divider value, cleared when the change is complete. + 31 + 1 + read-only + + + + + RINGO1_CTRL + Second Ring Oscillator module control register. + 0x44 + 32 + read-write + 0x40 + 0x803F01FF + + + S + Select short or long ringo (for all ringos types). + 0 + 1 + read-write + + + SHORT + Select short ringo (few elements). + 0 + + + LONG + Select long ringo (many elements). + 0x1 + + + + + FS + Ringo frequency output divider. + 1 + 1 + read-write + + + FAST + High frequency output (frequency lower than 100 MHz). + 0 + + + SLOW + Low frequency output (frequency lower than 10 MHz). + 0x1 + + + + + PD + Ringo module Power control. + 2 + 1 + read-write + + + POWERED_ON + The Ringo module is enabled. + 0 + + + POWERED_DOWN + The Ringo module is disabled. + 0x1 + + + + + E_R24 + . + 3 + 1 + read-write + + + DISABLE + Ringo is disabled. + 0 + + + ENABLE + Ringo is enabled. + 0x1 + + + + + E_R35 + . + 4 + 1 + read-write + + + DISABLE + Ringo is disabled. + 0 + + + ENABLE + Ringo is enabled. + 0x1 + + + + + E_M2 + Metal 2 (M2) monitor control. + 5 + 1 + read-write + + + DISABLE + Ringo is disabled. + 0 + + + ENABLE + Ringo is enabled. + 0x1 + + + + + E_M3 + Metal 3 (M3) monitor control. + 6 + 1 + read-write + + + DISABLE + Ringo is disabled. + 0 + + + ENABLE + Ringo is enabled. + 0x1 + + + + + E_M4 + Metal 4 (M4) monitor control. + 7 + 1 + read-write + + + DISABLE + Ringo is disabled. + 0 + + + ENABLE + Ringo is enabled. + 0x1 + + + + + E_M5 + Metal 5 (M5) monitor control. + 8 + 1 + read-write + + + DISABLE + Ringo is disabled. + 0 + + + ENABLE + Ringo is enabled. + 0x1 + + + + + DIVISOR + Ringo out Clock divider value. Frequency Output = Frequency input / (DIViSOR+1). (minimum = Frequency input / 16) + 16 + 4 + read-write + + + DIV_UPDATE_REQ + Ringo clock out Divider status flag. Set when a change is made to the divider value, cleared when the change is complete. + 31 + 1 + read-only + + + + + RINGO2_CTRL + Third Ring Oscillator module control register. + 0x48 + 32 + read-write + 0x40 + 0x803F01FF + + + S + Select short or long ringo (for all ringos types). + 0 + 1 + read-write + + + SHORT + Select short ringo (few elements). + 0 + + + LONG + Select long ringo (many elements). + 0x1 + + + + + FS + Ringo frequency output divider. + 1 + 1 + read-write + + + FAST + High frequency output (frequency lower than 100 MHz). + 0 + + + SLOW + Low frequency output (frequency lower than 10 MHz). + 0x1 + + + + + PD + Ringo module Power control. + 2 + 1 + read-write + + + POWERED_ON + The Ringo module is enabled. + 0 + + + POWERED_DOWN + The Ringo module is disabled. + 0x1 + + + + + E_R24 + . + 3 + 1 + read-write + + + DISABLE + Ringo is disabled. + 0 + + + ENABLE + Ringo is enabled. + 0x1 + + + + + E_R35 + . + 4 + 1 + read-write + + + DISABLE + Ringo is disabled. + 0 + + + ENABLE + Ringo is enabled. + 0x1 + + + + + E_M2 + Metal 2 (M2) monitor control. + 5 + 1 + read-write + + + DISABLE + Ringo is disabled. + 0 + + + ENABLE + Ringo is enabled. + 0x1 + + + + + E_M3 + Metal 3 (M3) monitor control. + 6 + 1 + read-write + + + DISABLE + Ringo is disabled. + 0 + + + ENABLE + Ringo is enabled. + 0x1 + + + + + E_M4 + Metal 4 (M4) monitor control. + 7 + 1 + read-write + + + DISABLE + Ringo is disabled. + 0 + + + ENABLE + Ringo is enabled. + 0x1 + + + + + E_M5 + Metal 5 (M5) monitor control. + 8 + 1 + read-write + + + DISABLE + Ringo is disabled. + 0 + + + ENABLE + Ringo is enabled. + 0x1 + + + + + DIVISOR + Ringo out Clock divider value. Frequency Output = Frequency input / (DIViSOR+1). (minimum = Frequency input / 16) + 16 + 4 + read-write + + + DIV_UPDATE_REQ + Ringo clock out Divider status flag. Set when a change is made to the divider value, cleared when the change is complete. + 31 + 1 + read-only + + + + + LDO_XO32M + High Speed Crystal Oscillator (12 MHz - 32 MHz) Voltage Source Supply Control register + 0xB0 + 32 + read-write + 0x3A0 + 0x3FE + + + BYPASS + Activate LDO bypass. + 1 + 1 + read-write + + + DISABLE + Disable bypass mode (for normal operations). + 0 + + + ENABLE + Activate LDO bypass. + 0x1 + + + + + HIGHZ + . + 2 + 1 + read-write + + + NORMALMPEDANCE + Output in High normal state. + 0 + + + HIGHIMPEDANCE + Output in High Impedance state. + 0x1 + + + + + VOUT + Sets the LDO output level. + 3 + 3 + read-write + + + V_0P750 + 0.750 V. + 0 + + + V_0P775 + 0.775 V. + 0x1 + + + V_0P800 + 0.800 V. + 0x2 + + + V_0P825 + 0.825 V. + 0x3 + + + V_0P850 + 0.850 V. + 0x4 + + + V_0P875 + 0.875 V. + 0x5 + + + V_0P900 + 0.900 V. + 0x6 + + + V_0P925 + 0.925 V. + 0x7 + + + + + IBIAS + Adjust the biasing current. + 6 + 2 + read-write + + + STABMODE + Stability configuration. + 8 + 2 + read-write + + + + + XO_CAL_CFG + All Crystal Oscillators (both the 32 KHz and the High speed) Capacitive Banks Calibration Configuration register + 0xC0 + 32 + read-write + 0 + 0x3F + + + START_INV + Polarity of the externally applied START signal + 0 + 1 + read-write + + + START_OVR + Override of the START signal. + 1 + 1 + read-write + + + START + Override value of the START signal. + 2 + 1 + read-write + + + STOP_INV + Polarity of the STOP signal. + 3 + 1 + read-write + + + STOP_CNTR_END + Generate the external DONE signal when the counter reaches its end. + 4 + 1 + read-write + + + XO32K_MODE + When 0 : High speed crystal oscillator calibration is used. When 1 : 32 kHz crystal oscillator calibration is used. + 5 + 1 + read-write + + + XO32MHZ + High speed crystal oscillator (12 MHz- 32 MHz) is used + 0 + + + XO32KHZ + 32 kHz crystal oscillator calibration is used. + 0x1 + + + + + + + XO_CAL_CMD + All Crystal Oscillators (both the 32 KHz and the High Speed) Capacitive Banks Calibration Command register. + 0xC4 + 32 + read-write + 0 + 0x7 + + + START + START signal for testing the state machine. + 0 + 1 + read-write + + + STOP + STOP signal for testing the state machine. + 1 + 1 + read-write + + + OVR + Override instructing the state machine to use the START/STOP signals from this register. + 2 + 1 + read-write + + + + + XO_CAL_STATUS + All Crystal Oscillators (both the 32 KHz and the High speed) Capacitive Banks Calibration Status register. + 0xC8 + 32 + read-only + 0 + 0x1FFFF + + + CAL_CNTR + Value of the calibration counter (result of the calibration operation). + 0 + 16 + read-only + + + DONE + Status of the calibration run. 1: Calibration is completed. + 16 + 1 + read-only + + + + + USBHS_PHY_CTRL + USB High Speed Phy Control + 0x100 + 32 + read-write + 0x8 + 0xF + + + usb_vbusvalid_ext + Override value for Vbus if using external detectors. + 0 + 1 + read-write + + + usb_id_ext + Override value for ID if using external detectors. + 1 + 1 + read-write + + + iso_atx + . + 3 + 1 + read-write + + + + + USBHS_PHY_TRIM + USB High Speed Phy Trim values + 0x104 + 32 + read-write + 0 + 0xFFFFFF + + + trim_usb_reg_env_tail_adj_vd + Adjusts time constant of HS RX squelch (envelope) comparator. + 0 + 2 + read-write + + + trim_usbphy_tx_d_cal + . + 2 + 4 + read-write + + + trim_usbphy_tx_cal45dp + . + 6 + 5 + read-write + + + trim_usbphy_tx_cal45dm + . + 11 + 5 + read-write + + + trim_usb2_refbias_tst + . + 16 + 2 + read-write + + + trim_usb2_refbias_vbgadj + . + 18 + 3 + read-write + + + trim_pll_ctrl0_div_sel + . + 21 + 3 + read-write + + + + + USBHS_PHY_STATUS + USB High Speed Phy Status + 0x108 + 32 + read-only + 0 + 0x7F + + + pfd_stable + pfd output is stable. + 0 + 1 + read-only + + + vbusvalid_3vdetect_1p8v + Can be left disconnected if not using High volt interrupts. + 1 + 1 + read-only + + + sess_vld_1p8v + Same as utmi_sessend. + 2 + 1 + read-only + + + usb2_rx_vpin_fs_1p8v + Full speed single ended receiver for 1. + 3 + 1 + read-only + + + usb2_rx_vmin_fs_1p8v + Full speed single ended receiver for 1. + 4 + 1 + read-only + + + usb2_plugged_in_1p8v + this is a proprietary mode described in the reference manual. + 5 + 1 + read-only + + + usb2_iddig_1p8v + ID value in the 1. + 6 + 1 + read-only + + + + + + + PMC + PMC + PMC + 0x40020000 + + 0 + 0xCC + registers + + + + RESETCTRL + Reset Control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] + 0x8 + 32 + read-write + 0 + 0xF + + + DPDWAKEUPRESETENABLE + Wake-up from DEEP POWER DOWN reset event (either from wake up I/O or RTC or OS Event Timer). + 0 + 1 + read-write + + + DISABLE + Reset event from DEEP POWER DOWN mode is disable. + 0 + + + ENABLE + Reset event from DEEP POWER DOWN mode is enable. + 0x1 + + + + + BODVBATRESETENABLE + BOD VBAT reset enable. + 1 + 1 + read-write + + + DISABLE + BOD VBAT reset is disable. + 0 + + + ENABLE + BOD VBAT reset is enable. + 0x1 + + + + + BODCORERESETENABLE + BOD CORE reset enable. + 2 + 1 + read-write + + + DISABLE + BOD CORE reset is disable. + 0 + + + ENABLE + BOD CORE reset is enable. + 0x1 + + + + + SWRRESETENABLE + Software reset enable. + 3 + 1 + read-write + + + DISABLE + Software reset is disable. + 0 + + + ENABLE + Software reset is enable. + 0x1 + + + + + + + RESETCAUSE + Reset Cause register [Reset by: PoR] + 0xC + 32 + read-write + 0x1 + 0x1FF + + + POR + 1 : The last chip reset was caused by a Power On Reset. Write '1' to clear this bit. + 0 + 1 + read-write + oneToClear + + + PADRESET + 1 : The last chip reset was caused by a Pin Reset. Write '1' to clear this bit. + 1 + 1 + read-write + + + BODRESET + 1 : The last chip reset was caused by a Brown Out Detector (BoD), either VBAT BoD or Core Logic BoD. Write '1' to clear this bit. + 2 + 1 + read-write + + + SYSTEMRESET + 1 : The last chip reset was caused by a System Reset requested by the ARM CPU. Write '1' to clear this bit. + 3 + 1 + read-write + + + WDTRESET + 1 : The last chip reset was caused by the Watchdog Timer. Write '1' to clear this bit. + 4 + 1 + read-write + + + SWRRESET + 1 : The last chip reset was caused by a Software. Write '1' to clear this bit. + 5 + 1 + read-write + + + DPDRESET_WAKEUPIO + 1 : The last chip reset was caused by a Wake-up I/O reset event during DEEP POWER DOWN mode. Write '1' to clear this bit. + 6 + 1 + read-write + + + DPDRESET_RTC + 1 : The last chip reset was caused by an RTC (either RTC Alarm or RTC wake up) reset event during DEEP POWER DOWN mode. Write '1' to clear this bit. + 7 + 1 + read-write + + + DPDRESET_OSTIMER + 1 : The last chip reset was caused by a OS Event Timer reset eventduring DEEP POWER DOWN mode. Write '1' to clear this bit. + 8 + 1 + read-write + + + + + BODVBAT + VBAT Brown Out Dectector (BoD) control register [Reset by: PoR, Pin Reset, Software Reset] + 0x30 + 32 + read-write + 0x69 + 0x7F + + + TRIGLVL + BoD trigger level. + 0 + 5 + read-write + + + V_1P00 + 1.00 V. + 0 + + + V_1P10 + 1.10 V. + 0x1 + + + V_1P20 + 1.20 V. + 0x2 + + + V_1P30 + 1.30 V. + 0x3 + + + V_1P40 + 1.40 V. + 0x4 + + + V_1P50 + 1.50 V. + 0x5 + + + V_1P60 + 1.60 V. + 0x6 + + + V_1P65 + 1.65 V. + 0x7 + + + V_1P70 + 1.70 V. + 0x8 + + + V_1P75 + 1.75 V. + 0x9 + + + V_1P80 + 1.80 V. + 0xA + + + V_1P90 + 1.90 V. + 0xB + + + V_2P00 + 2.00 V. + 0xC + + + V_2P10 + 2.10 V. + 0xD + + + V_2P20 + 2.20 V. + 0xE + + + V_2P30 + 2.30 V. + 0xF + + + V_2P40 + 2.40 V. + 0x10 + + + V_2P50 + 2.50 V. + 0x11 + + + V_2P60 + 2.60 V. + 0x12 + + + V_2P70 + 2.70 V. + 0x13 + + + V_2P80 + 2.806 V. + 0x14 + + + V_2P90 + 2.90 V. + 0x15 + + + V_3P00 + 3.00 V. + 0x16 + + + V_3P10 + 3.10 V. + 0x17 + + + V_3P20 + 3.20 V. + 0x18 + + + V_3P30_2 + 3.30 V. + 0x19 + + + V_3P30_3 + 3.30 V. + 0x1A + + + V_3P30_4 + 3.30 V. + 0x1B + + + V_3P30_5 + 3.30 V. + 0x1C + + + V_3P30_6 + 3.30 V. + 0x1D + + + V_3P30_7 + 3.30 V. + 0x1E + + + V_3P30_8 + 3.30 V. + 0x1F + + + + + HYST + BoD Hysteresis control. + 5 + 2 + read-write + + + HYST_25MV + 25 mV. + 0 + + + HYST_50MV + 50 mV. + 0x1 + + + HYST_75MV + 75 mV. + 0x2 + + + HYST_100MV + 100 mV. + 0x3 + + + + + + + BODCORE + Digital Core logic Brown Out Dectector control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] + 0x38 + 32 + read-write + 0x17 + 0x37 + + + TRIGLVL + BoD trigger level. + 0 + 3 + read-write + + + V_0P60 + 0.60 V. + 0 + + + V_0P65 + 0.65 V. + 0x1 + + + V_0P70 + 0.70 V. + 0x2 + + + V_0P75 + 0.75 V. + 0x3 + + + V_0P80 + 0.80 V. + 0x4 + + + V_0P85 + 0.85 V. + 0x5 + + + V_0P90 + 0.90 V. + 0x6 + + + V_0P95 + 0.95 V. + 0x7 + + + + + HYST + BoD Core Hysteresis control. + 4 + 2 + read-write + + + HYST_25MV + 25 mV. + 0 + + + HYST_50MV + 50 mV. + 0x1 + + + HYST_75MV + 75 mV. + 0x2 + + + HYST_100MV + 100 mV. + 0x3 + + + + + + + FRO1M + 1 MHz Free Running Oscillator control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] + 0x44 + 32 + read-write + 0x50 + 0x3FFF + + + FREQSEL + Frequency trimming bits. + 0 + 7 + read-write + + + ATBCTRL + Debug control bits to set the analog/digital test modes. + 7 + 2 + read-write + + + DIVSEL + Divider selection bits. + 9 + 5 + read-write + + + DIV_2 + 2.0. + 0 + + + DIV_4 + 4.0. + 0x1 + + + DIV_6 + 6.0. + 0x2 + + + DIV_8 + 8.0. + 0x3 + + + DIV_10 + 10.0. + 0x4 + + + DIV_12 + 12.0. + 0x5 + + + DIV_14 + 14.0. + 0x6 + + + DIV_16 + 16.0. + 0x7 + + + DIV_18 + 18.0. + 0x8 + + + DIV_20 + 20.0. + 0x9 + + + DIV_22 + 22.0. + 0xA + + + DIV_24 + 24.0. + 0xB + + + DIV_26 + 26.0. + 0xC + + + DIV_28 + 28.0. + 0xD + + + DIV_30 + 30.0. + 0xE + + + DIV_32 + 32.0. + 0xF + + + DIV_34 + 34.0. + 0x10 + + + DIV_36 + 36.0. + 0x11 + + + DIV_38 + 38.0. + 0x12 + + + DIV_40 + 40.0. + 0x13 + + + DIV_42 + 42.0. + 0x14 + + + DIV_44 + 44.0. + 0x15 + + + DIV_46 + 46.0. + 0x16 + + + DIV_48 + 48.0. + 0x17 + + + DIV_50 + 50.0. + 0x18 + + + DIV_52 + 52.0. + 0x19 + + + DIV_54 + 54.0. + 0x1A + + + DIV_56 + 56.0. + 0x1B + + + DIV_58 + 58.0. + 0x1C + + + DIV_60 + 60.0. + 0x1D + + + DIV_62 + 62.0. + 0x1E + + + DIV_1 + 1.0. + 0x1F + + + + + + + FRO32K + 32 KHz Free Running Oscillator (FRO) control register [Reset by: PoR, Brown Out Detectors Reset] + 0x48 + 32 + read-write + 0x90B6 + 0x3FFFE + + + NTAT + Temperature coefficient trimming bits. + 1 + 3 + read-write + + + PTAT + Bias trimming bits (course frequency trimming). + 4 + 3 + read-write + + + CAPCAL + Capacitive dac calibration bits (fine frequency trimming). + 7 + 9 + read-write + + + ATBCTRL + Debug control bits to set the analog/digital test modes. + 16 + 2 + read-write + + + + + XTAL32K + 32 KHz Crystal oscillator (XTAL) control register [Reset by: PoR, Brown Out Detectors Reset] + 0x4C + 32 + read-write + 0x204052 + 0x3FFFFFE + + + IREF + reference output current selection inputs. + 1 + 2 + read-write + + + TEST + Oscillator Test Mode. + 3 + 1 + read-write + + + IBIAS + bias current selection inputs. + 4 + 2 + read-write + + + AMPL + oscillator amplitude selection inputs. + 6 + 2 + read-write + + + CAPBANKIN + Capa bank setting input. + 8 + 7 + read-write + + + CAPBANKOUT + Capa bank setting output. + 15 + 7 + read-write + + + CAPTESTSTARTSRCSEL + Source selection for xo32k_captest_start_ao_set. + 22 + 1 + read-write + + + CAPSTART + Sourced from CAPTESTSTART. + 0 + + + CALIB + Sourced from calibration. + 0x1 + + + + + CAPTESTSTART + Start test. + 23 + 1 + read-write + + + CAPTESTENABLE + Enable signal for cap test. + 24 + 1 + read-write + + + CAPTESTOSCINSEL + Select the input for test. + 25 + 1 + read-write + + + OSCOUT + Oscillator output pin (osc_out). + 0 + + + OSCIN + Oscillator input pin (osc_in). + 0x1 + + + + + + + COMP + Analog Comparator control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] + 0x50 + 32 + read-write + 0xA + 0xFF7FFE + + + HYST + Hysteris when hyst = '1'. + 1 + 1 + read-write + + + DISABLE + Hysteresis is disable. + 0 + + + ENABLE + Hysteresis is enable. + 0x1 + + + + + VREFINPUT + Dedicated control bit to select between internal VREF and VDDA (for the resistive ladder). + 2 + 1 + read-write + + + INTERNALREF + Select internal VREF. + 0 + + + VDDA + Select VDDA. + 0x1 + + + + + LOWPOWER + Low power mode. + 3 + 1 + read-write + + + HIGHSPEED + High speed mode. + 0 + + + LOWSPEED + Low power mode (Low speed). + 0x1 + + + + + PMUX + Control word for P multiplexer:. + 4 + 3 + read-write + + + VREF + VREF (See fiedl VREFINPUT). + 0 + + + CMP0_A + Pin P0_0. + 0x1 + + + CMP0_B + Pin P0_9. + 0x2 + + + CMP0_C + Pin P0_18. + 0x3 + + + CMP0_D + Pin P1_14. + 0x4 + + + CMP0_E + Pin P2_23. + 0x5 + + + + + NMUX + Control word for N multiplexer:. + 7 + 3 + read-write + + + VREF + VREF (See field VREFINPUT). + 0 + + + CMP0_A + Pin P0_0. + 0x1 + + + CMP0_B + Pin P0_9. + 0x2 + + + CMP0_C + Pin P0_18. + 0x3 + + + CMP0_D + Pin P1_14. + 0x4 + + + CMP0_E + Pin P2_23. + 0x5 + + + + + VREF + Control reference voltage step, per steps of (VREFINPUT/31). + 10 + 5 + read-write + + + FILTERCGF_SAMPLEMODE + Filter Sample mode. + 16 + 2 + read-write + + + FILTERCGF_CLKDIV + Filter Clock div . + 18 + 3 + read-write + + + PMUXCAPT + Control word for P multiplexer for Capacitive Touch Controller. + 21 + 3 + read-write + + + + + WAKEIOCAUSE + Allows to identify the Wake-up I/O source from Deep Power Down mode + 0x68 + 32 + read-write + 0 + 0xF + + + WAKEUP0 + Allows to identify Wake up I/O 0 as the wake-up source from Deep Power Down mode. + 0 + 1 + read-only + + + NOEVENT + Last wake up from Deep Power down mode was NOT triggred by wake up I/O 0. + 0 + + + EVENT + Last wake up from Deep Power down mode was triggred by wake up I/O 0. + 0x1 + + + + + WAKEUP1 + Allows to identify Wake up I/O 1 as the wake-up source from Deep Power Down mode. + 1 + 1 + read-write + + + NOEVENT + Last wake up from Deep Power down mode was NOT triggred by wake up I/O 1. + 0 + + + EVENT + Last wake up from Deep Power down mode was triggred by wake up I/O 1. + 0x1 + + + + + WAKEUP2 + Allows to identify Wake up I/O 2 as the wake-up source from Deep Power Down mode. + 2 + 1 + read-write + + + NOEVENT + Last wake up from Deep Power down mode was NOT triggred by wake up I/O 2. + 0 + + + EVENT + Last wake up from Deep Power down mode was triggred by wake up I/O 2. + 0x1 + + + + + WAKEUP3 + Allows to identify Wake up I/O 3 as the wake-up source from Deep Power Down mode. + 3 + 1 + read-write + + + NOEVENT + Last wake up from Deep Power down mode was NOT triggred by wake up I/O 3. + 0 + + + EVENT + Last wake up from Deep Power down mode was triggred by wake up I/O 3. + 0x1 + + + + + + + STATUSCLK + FRO and XTAL status register [Reset by: PoR, Brown Out Detectors Reset] + 0x74 + 32 + read-write + 0x6 + 0x7 + + + XTAL32KOK + XTAL oscillator 32 K OK signal. + 0 + 1 + read-only + + + FRO1MCLKVALID + FRO 1 MHz CCO voltage detector output. + 1 + 1 + read-only + + + XTAL32KOSCFAILURE + XTAL32 KHZ oscillator oscillation failure detection indicator. + 2 + 1 + read-write + + + NOFAIL + No oscillation failure has been detetced since the last time this bit has been cleared.. + 0 + + + FAILURE + At least one oscillation failure has been detetced since the last time this bit has been cleared.. + 0x1 + + + + + + + AOREG1 + General purpose always on domain data storage [Reset by: PoR, Brown Out Detectors Reset] + 0x84 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA31_0 + General purpose always on domain data storage. + 0 + 32 + read-write + + + + + RTCOSC32K + RTC 1 KHZ and 1 Hz clocks source control register [Reset by: PoR, Brown Out Detectors Reset] + 0x98 + 32 + read-write + 0x3FF0008 + 0xC7FF800F + + + SEL + Select the 32K oscillator to be used in Deep Power Down Mode for the RTC (either XTAL32KHz or FRO32KHz) . + 0 + 1 + read-write + + + FRO32K + FRO 32 KHz. + 0 + + + XTAL32K + XTAL 32KHz. + 0x1 + + + + + CLK1KHZDIV + Actual division ratio is : 28 + CLK1KHZDIV. + 1 + 3 + read-write + + + CLK1KHZDIVUPDATEREQ + RTC 1KHz clock Divider status flag. + 15 + 1 + read-write + + + CLK1HZDIV + Actual division ratio is : 31744 + CLK1HZDIV. + 16 + 11 + read-write + + + CLK1HZDIVHALT + Halts the divider counter. + 30 + 1 + read-write + + + CLK1HZDIVUPDATEREQ + RTC 1Hz Divider status flag. + 31 + 1 + read-write + + + + + OSTIMER + OS Timer control register [Reset by: PoR, Brown Out Detectors Reset] + 0x9C + 32 + read-write + 0x8 + 0xF + + + SOFTRESET + Active high reset. + 0 + 1 + read-write + + + CLOCKENABLE + Enable OSTIMER 32 KHz clock. + 1 + 1 + read-write + + + DPDWAKEUPENABLE + Wake up enable in Deep Power Down mode (To be used in Enable Deep Power Down mode). + 2 + 1 + read-write + + + OSC32KPD + Oscilator 32KHz (either FRO32KHz or XTAL32KHz according to RTCOSC32K. + 3 + 1 + read-write + + + + + PDSLEEPCFG0 + Controls the power to various modules during Low Power modes - DEEP SLEEP, POWER DOWN and DEEP POWER DOWN [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Software Reset] + 0xB0 + 32 + read-write + 0xC0 + 0x1FFFFFF + + + PDEN_DCDC + Controls DCDC power during DEEP SLEEP (DCDC is always shut down during POWER DOWN and DEEP POWER DOWN). + 0 + 1 + read-write + + + POWEREDON + DCDC is powered on during low power mode.. + 0 + + + POWEREDOFF + DCDC is powered off during low power mode.. + 0x1 + + + + + PDEN_BIAS + Controls Analog Bias power during DEEP SLEEP and POWER DOWN (always shut down during DEEP POWER DOWN). + 1 + 1 + read-write + + + POWEREDON + Analog Bias is powered on during low power mode.. + 0 + + + POWEREDOFF + Analog Bias is powered off during low power mode.. + 0x1 + + + + + PDEN_BODCORE + Controls Core Logic BoD power during DEEP SLEEP and POWER DOWN (always shut down during DEEP POWER DOWN). + 2 + 1 + read-write + + + POWEREDON + BOD CORE is powered on during low power mode.. + 0 + + + POWEREDOFF + BOD CORE is powered off during low power mode.. + 0x1 + + + + + PDEN_BODVBAT + Controls VBAT BoD power during DEEP SLEEP and POWER DOWN (always shut down during DEEP POWER DOWN). + 3 + 1 + read-write + + + POWEREDON + BOD VBAT is powered on during low power mode.. + 0 + + + POWEREDOFF + BOD VBAT is powered off during low power mode.. + 0x1 + + + + + PDEN_FRO1M + Controls 1 MHz Free Running Oscillator power during DEEP SLEEP, POWER DOWN and DEEP POWER DOWN. + 4 + 1 + read-write + + + POWEREDON + FRO 1MHz is powered on during low power mode.. + 0 + + + POWEREDOFF + FRO 1MHz is powered off during low power mode.. + 0x1 + + + + + PDEN_FRO192M + Controls 192MHz Free Running Oscillator power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). + 5 + 1 + read-write + + + POWEREDON + FRO 192 MHz is powered on during low power mode.. + 0 + + + POWEREDOFF + FRO 192 MHz is powered off during low power mode.. + 0x1 + + + + + PDEN_FRO32K + Controls power during DEEP SLEEP, POWER DOWN and DEEP POWER DOWN. + 6 + 1 + read-write + + + POWEREDON + FRO 32 KHz is powered on during low power mode.. + 0 + + + POWEREDOFF + FRO 32 KHz is powered off during low power mode.. + 0x1 + + + + + PDEN_XTAL32K + Controls crystal 32 KHz power during DEEP SLEEP, POWER DOWN and DEEP POWER DOWN. + 7 + 1 + read-write + + + POWEREDON + crystal 32 KHz is powered on during low power mode.. + 0 + + + POWEREDOFF + crystal 32 KHz is powered off during low power mode.. + 0x1 + + + + + PDEN_XTAL32M + Controls crystal 32 MHz power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). + 8 + 1 + read-write + + + POWEREDON + crystal 32 MHz is powered on during low power mode.. + 0 + + + POWEREDOFF + crystal 32 MHz is powered off during low power mode.. + 0x1 + + + + + PDEN_PLL0 + Controls System PLL (also refered as PLL0) power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). + 9 + 1 + read-write + + + POWEREDON + System PLL (also refered as PLL0) is powered on during low power mode.. + 0 + + + POWEREDOFF + System PLL (also refered as PLL0) is powered off during low power mode.. + 0x1 + + + + + PDEN_PLL1 + Controls USB PLL (also refered as PLL1) power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). + 10 + 1 + read-write + + + POWEREDON + USB PLL (also refered as PLL1) is powered on during low power mode.. + 0 + + + POWEREDOFF + USB PLL (also refered as PLL1) is powered off during low power mode.. + 0x1 + + + + + PDEN_USBFSPHY + Controls USB Full Speed phy power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). + 11 + 1 + read-write + + + POWEREDON + USB Full Speed phy is powered on during low power mode.. + 0 + + + POWEREDOFF + USB Full Speed phy is powered off during low power mode.. + 0x1 + + + + + PDEN_USBHSPHY + Controls USB High Speed Phy power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). + 12 + 1 + read-write + + + POWEREDON + USB High Speed Phy is powered on during low power mode.. + 0 + + + POWEREDOFF + USB High Speed Phy is powered off during low power mode.. + 0x1 + + + + + PDEN_COMP + Controls Analog Comparator power during DEEP SLEEP and POWER DOWN (always shut down during DEEP POWER DOWN). + 13 + 1 + read-write + + + POWEREDON + Analog Comparator is powered on during low power mode.. + 0 + + + POWEREDOFF + Analog Comparator is powered off during low power mode.. + 0x1 + + + + + PDEN_TEMPSENS + Controls Temperature Sensor power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). + 14 + 1 + read-write + + + POWEREDON + Temperature Sensor is powered on during low power mode.. + 0 + + + POWEREDOFF + Temperature Sensor is powered off during low power mode.. + 0x1 + + + + + PDEN_GPADC + Controls General Purpose ADC (GPADC) power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). + 15 + 1 + read-write + + + POWEREDON + General Purpose ADC (GPADC) is powered on during low power mode.. + 0 + + + POWEREDOFF + General Purpose ADC (GPADC) is powered off during low power mode.. + 0x1 + + + + + PDEN_LDOMEM + Controls Memories LDO power during DEEP SLEEP, POWER DOWN and DEEP POWER DOWN. + 16 + 1 + read-write + + + POWEREDON + Memories LDO is powered on during low power mode.. + 0 + + + POWEREDOFF + Memories LDO is powered off during low power mode.. + 0x1 + + + + + PDEN_LDODEEPSLEEP + Controls Deep Sleep LDO power during DEEP SLEEP and POWER DOWN (always shut down during DEEP POWER DOWN). + 17 + 1 + read-write + + + POWEREDON + Deep Sleep LDO is powered on during low power mode.. + 0 + + + POWEREDOFF + Deep Sleep LDO is powered off during low power mode.. + 0x1 + + + + + PDEN_LDOUSBHS + Controls USB high speed LDO power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). + 18 + 1 + read-write + + + POWEREDON + USB high speed LDO is powered on during low power mode.. + 0 + + + POWEREDOFF + USB high speed LDO is powered off during low power mode.. + 0x1 + + + + + PDEN_AUXBIAS + during DEEP SLEEP and POWER DOWN (always shut down during DEEP POWER DOWN). + 19 + 1 + read-write + + + POWEREDON + is powered on during low power mode.. + 0 + + + POWEREDOFF + is powered off during low power mode.. + 0x1 + + + + + PDEN_LDOXO32M + Controls crystal 32 MHz LDO power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). + 20 + 1 + read-write + + + POWEREDON + crystal 32 MHz LDO is powered on during low power mode.. + 0 + + + POWEREDOFF + crystal 32 MHz LDO is powered off during low power mode.. + 0x1 + + + + + PDEN_LDOFLASHNV + Controls Flash NV (high voltage) LDO power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). + 21 + 1 + read-write + + + POWEREDON + Flash NV (high voltage) is powered on during low power mode.. + 0 + + + POWEREDOFF + Flash NV (high voltage) is powered off during low power mode.. + 0x1 + + + + + PDEN_RNG + Controls True Random Number Genetaor (TRNG) clock sources power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). + 22 + 1 + read-write + + + POWEREDON + True Random Number Genetaor (TRNG) clock sources are powered on during low power mode.. + 0 + + + POWEREDOFF + True Random Number Genetaor (TRNG) clock sources are powered off during low power mode.. + 0x1 + + + + + PDEN_PLL0_SSCG + Controls PLL0 Spread Sprectrum module power during DEEP SLEEP (PLL0 Spread Spectrum is always shut down during POWER DOWN and DEEP POWER DOWN). + 23 + 1 + read-write + + + POWEREDON + PLL0 Spread Sprectrum module is powered on during low power mode.. + 0 + + + POWEREDOFF + PLL0 Spread Sprectrum module is powered off during low power mode.. + 0x1 + + + + + PDEN_ROM + Controls ROM power during DEEP SLEEP (ROM is always shut down during POWER DOWN and DEEP POWER DOWN). + 24 + 1 + read-write + + + POWEREDON + ROM is powered on during low power mode.. + 0 + + + POWEREDOFF + ROM is powered off during low power mode.. + 0x1 + + + + + + + PDRUNCFG0 + Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] + 0xB8 + 32 + read-write + 0xDEFFC4 + 0xFFFFEF + + + PDEN_DCDC + Controls power to Bulk DCDC Converter. + 0 + 1 + read-write + + + POWEREDON + DCDC is powered. + 0 + + + POWEREDOFF + DCDC is powered down. + 0x1 + + + + + PDEN_BIAS + Controls power to . + 1 + 1 + read-write + + + POWEREDON + Analog Bias is powered. + 0 + + + POWEREDOFF + Analog Bias is powered down. + 0x1 + + + + + PDEN_BODCORE + Controls power to Core Brown Out Detector (BOD). + 2 + 1 + read-write + + + POWEREDON + BOD CORE is powered. + 0 + + + POWEREDOFF + BOD CORE is powered down. + 0x1 + + + + + PDEN_BODVBAT + Controls power to VBAT Brown Out Detector (BOD). + 3 + 1 + read-write + + + POWEREDON + BOD VBAT is powered. + 0 + + + POWEREDOFF + BOD VBAT is powered down. + 0x1 + + + + + PDEN_FRO192M + Controls power to the Free Running Oscillator (FRO) 192 MHz; The 12MHz, 48 MHz and 96 MHz clocks are derived from this FRO. + 5 + 1 + read-write + + + POWEREDON + FRO 192MHz is powered. + 0 + + + POWEREDOFF + FRO 192MHz is powered down. + 0x1 + + + + + PDEN_FRO32K + Controls power to the Free Running Oscillator (FRO) 32 KHz. + 6 + 1 + read-write + + + POWEREDON + FRO32KHz is powered. + 0 + + + POWEREDOFF + FRO32KHz is powered down. + 0x1 + + + + + PDEN_XTAL32K + Controls power to crystal 32 KHz. + 7 + 1 + read-write + + + POWEREDON + Crystal 32KHz is powered. + 0 + + + POWEREDOFF + Crystal 32KHz is powered down. + 0x1 + + + + + PDEN_XTAL32M + Controls power to crystal 32 MHz. + 8 + 1 + read-write + + + POWEREDON + Crystal 32MHz is powered. + 0 + + + POWEREDOFF + Crystal 32MHz is powered down. + 0x1 + + + + + PDEN_PLL0 + Controls power to System PLL (also refered as PLL0). + 9 + 1 + read-write + + + POWEREDON + PLL0 is powered. + 0 + + + POWEREDOFF + PLL0 is powered down. + 0x1 + + + + + PDEN_PLL1 + Controls power to USB PLL (also refered as PLL1). + 10 + 1 + read-write + + + POWEREDON + PLL1 is powered. + 0 + + + POWEREDOFF + PLL1 is powered down. + 0x1 + + + + + PDEN_USBFSPHY + Controls power to USB Full Speed phy. + 11 + 1 + read-write + + + POWEREDON + USB Full Speed phy is powered. + 0 + + + POWEREDOFF + USB Full Speed phy is powered down. + 0x1 + + + + + PDEN_USBHSPHY + Controls power to USB High Speed Phy. + 12 + 1 + read-write + + + POWEREDON + USB HS phy is powered. + 0 + + + POWEREDOFF + USB HS phy is powered down. + 0x1 + + + + + PDEN_COMP + Controls power to Analog Comparator. + 13 + 1 + read-write + + + POWEREDON + Analog Comparator is powered. + 0 + + + POWEREDOFF + Analog Comparator is powered down. + 0x1 + + + + + PDEN_TEMPSENS + Controls power to Temperature Sensor. + 14 + 1 + read-write + + + POWEREDON + Temperature Sensor is powered. + 0 + + + POWEREDOFF + Temperature Sensor is powered down. + 0x1 + + + + + PDEN_GPADC + Controls power to General Purpose ADC (GPADC). + 15 + 1 + read-write + + + POWEREDON + GPADC is powered. + 0 + + + POWEREDOFF + GPADC is powered down. + 0x1 + + + + + PDEN_LDOMEM + Controls power to Memories LDO. + 16 + 1 + read-write + + + POWEREDON + Memories LDO is powered. + 0 + + + POWEREDOFF + Memories LDO is powered down. + 0x1 + + + + + PDEN_LDODEEPSLEEP + Controls power to Deep Sleep LDO. + 17 + 1 + read-write + + + POWEREDON + Deep Sleep LDO is powered. + 0 + + + POWEREDOFF + Deep Sleep LDO is powered down. + 0x1 + + + + + PDEN_LDOUSBHS + Controls power to USB high speed LDO. + 18 + 1 + read-write + + + POWEREDON + USB high speed LDO is powered. + 0 + + + POWEREDOFF + USB high speed LDO is powered down. + 0x1 + + + + + PDEN_AUXBIAS + Controls power to auxiliary biasing (AUXBIAS) + 19 + 1 + read-write + + + POWEREDON + auxiliary biasing is powered. + 0 + + + POWEREDOFF + auxiliary biasing is powered down. + 0x1 + + + + + PDEN_LDOXO32M + Controls power to crystal 32 MHz LDO. + 20 + 1 + read-write + + + POWEREDON + crystal 32 MHz LDO is powered. + 0 + + + POWEREDOFF + crystal 32 MHz LDO is powered down. + 0x1 + + + + + PDEN_LDOFLASHNV + Controls power to Flasn NV (high voltage) LDO. + 21 + 1 + read-write + + + POWEREDON + Flash NV LDO is powered. + 0 + + + POWEREDOFF + Flash NV LDO is powered down. + 0x1 + + + + + PDEN_RNG + Controls power to all True Random Number Genetaor (TRNG) clock sources. + 22 + 1 + read-write + + + POWEREDON + TRNG clocks are powered. + 0 + + + POWEREDOFF + TRNG clocks are powered down. + 0x1 + + + + + PDEN_PLL0_SSCG + Controls power to System PLL (PLL0) Spread Spectrum module. + 23 + 1 + read-write + + + POWEREDON + PLL0 Sread spectrum module is powered. + 0 + + + POWEREDOFF + PLL0 Sread spectrum module is powered down. + 0x1 + + + + + + + PDRUNCFGSET0 + Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] + 0xC0 + 32 + write-only + 0 + 0xFFFFFFFF + + + PDRUNCFGSET0 + Writing ones to this register sets the corresponding bit or bits in the PDRUNCFG0 register, if they are implemented. + 0 + 32 + write-only + + + + + PDRUNCFGCLR0 + Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] + 0xC8 + 32 + write-only + 0 + 0xFFFFFFFF + + + PDRUNCFGCLR0 + Writing ones to this register clears the corresponding bit or bits in the PDRUNCFG0 register, if they are implemented. + 0 + 32 + write-only + + + + + + + SYSCTL + system controller + SYSCTL + 0x40023000 + + 0 + 0x104 + registers + + + + UPDATELCKOUT + update lock out control + 0 + 32 + read-write + 0 + 0x1 + + + UPDATELCKOUT + All Registers + 0 + 1 + read-write + + + NORMAL_MODE + Normal Mode. Can be written to. + 0 + + + PROTECTED_MODE + Protected Mode. Cannot be written to. + 0x1 + + + + + + + 8 + 0x4 + 0,1,2,3,4,5,6,7 + FCCTRLSEL%s + Selects the source for SCK going into Flexcomm 0 + 0x40 + 32 + read-write + 0 + 0x3030303 + + + SCKINSEL + Selects the source for SCK going into this Flexcomm. + 0 + 2 + read-writeOnce + + + ORIG_FLEX_I2S_SIGNALS + Selects the dedicated FCn_SCK function for this Flexcomm. + 0 + + + SHARED_SET0_I2S_SIGNALS + SCK is taken from shared signal set 0 (defined by SHAREDCTRLSET0). + 0x1 + + + SHARED_SET1_I2S_SIGNALS + SCK is taken from shared signal set 1 (defined by SHAREDCTRLSET1). + 0x2 + + + + + WSINSEL + Selects the source for WS going into this Flexcomm. + 8 + 2 + read-write + + + ORIG_FLEX_I2S_SIGNALS + Selects the dedicated (FCn_TXD_SCL_MISO_WS) function for this Flexcomm. + 0 + + + SHARED_SET0_I2S_SIGNALS + WS is taken from shared signal set 0 (defined by SHAREDCTRLSET0). + 0x1 + + + SHARED_SET1_I2S_SIGNALS + WS is taken from shared signal set 1 (defined by SHAREDCTRLSET1). + 0x2 + + + + + DATAINSEL + Selects the source for DATA input to this Flexcomm. + 16 + 2 + read-write + + + ORIG_FLEX_I2S_SIGNALS + Selects the dedicated FCn_RXD_SDA_MOSI_DATA input for this Flexcomm. + 0 + + + SHARED_SET0_I2S_SIGNALS + Input data is taken from shared signal set 0 (defined by SHAREDCTRLSET0). + 0x1 + + + SHARED_SET1_I2S_SIGNALS + Input data is taken from shared signal set 1 (defined by SHAREDCTRLSET1). + 0x2 + + + + + DATAOUTSEL + Selects the source for DATA output from this Flexcomm. + 24 + 2 + read-write + + + ORIG_FLEX_I2S_SIGNALS + Selects the dedicated FCn_RXD_SDA_MOSI_DATA output from this Flexcomm. + 0 + + + SHARED_SET0_I2S_SIGNALS + Output data is taken from shared signal set 0 (defined by SHAREDCTRLSET0). + 0x1 + + + SHARED_SET1_I2S_SIGNALS + Output data is taken from shared signal set 1 (defined by SHAREDCTRLSET1). + 0x2 + + + + + + + 2 + 0x4 + 0,1 + SHAREDCTRLSET%s + Selects sources and data combinations for shared signal set 0. + 0x80 + 32 + read-write + 0 + 0xFF0777 + + + SHAREDSCKSEL + Selects the source for SCK of this shared signal set. + 0 + 3 + read-write + + + FLEXCOMM0 + SCK for this shared signal set comes from Flexcomm 0. + 0 + + + FLEXCOMM1 + SCK for this shared signal set comes from Flexcomm 1. + 0x1 + + + FLEXCOMM2 + SCK for this shared signal set comes from Flexcomm 2. + 0x2 + + + FLEXCOMM3 + SCK for this shared signal set comes from Flexcomm 3. + 0x3 + + + FLEXCOMM4 + SCK for this shared signal set comes from Flexcomm 4. + 0x4 + + + FLEXCOMM5 + SCK for this shared signal set comes from Flexcomm 5. + 0x5 + + + FLEXCOMM6 + SCK for this shared signal set comes from Flexcomm 6. + 0x6 + + + FLEXCOMM7 + SCK for this shared signal set comes from Flexcomm 7. + 0x7 + + + + + SHAREDWSSEL + Selects the source for WS of this shared signal set. + 4 + 3 + read-write + + + FLEXCOMM0 + WS for this shared signal set comes from Flexcomm 0. + 0 + + + FLEXCOMM1 + WS for this shared signal set comes from Flexcomm 1. + 0x1 + + + FLEXCOMM2 + WS for this shared signal set comes from Flexcomm 2. + 0x2 + + + FLEXCOMM3 + WS for this shared signal set comes from Flexcomm 3. + 0x3 + + + FLEXCOMM4 + WS for this shared signal set comes from Flexcomm 4. + 0x4 + + + FLEXCOMM5 + WS for this shared signal set comes from Flexcomm 5. + 0x5 + + + FLEXCOMM6 + WS for this shared signal set comes from Flexcomm 6. + 0x6 + + + FLEXCOMM7 + WS for this shared signal set comes from Flexcomm 7. + 0x7 + + + + + SHAREDDATASEL + Selects the source for DATA input for this shared signal set. + 8 + 3 + read-write + + + FLEXCOMM0 + DATA input for this shared signal set comes from Flexcomm 0. + 0 + + + FLEXCOMM1 + DATA input for this shared signal set comes from Flexcomm 1. + 0x1 + + + FLEXCOMM2 + DATA input for this shared signal set comes from Flexcomm 2. + 0x2 + + + FLEXCOMM3 + DATA input for this shared signal set comes from Flexcomm 3. + 0x3 + + + FLEXCOMM4 + DATA input for this shared signal set comes from Flexcomm 4. + 0x4 + + + FLEXCOMM5 + DATA input for this shared signal set comes from Flexcomm 5. + 0x5 + + + FLEXCOMM6 + DATA input for this shared signal set comes from Flexcomm 6. + 0x6 + + + FLEXCOMM7 + DATA input for this shared signal set comes from Flexcomm 7. + 0x7 + + + + + FC0DATAOUTEN + Controls FC0 contribution to SHAREDDATAOUT for this shared set. + 16 + 1 + read-write + + + INPUT + Data output from FC0 does not contribute to this shared set. + 0 + + + OUTPUT + Data output from FC0 does contribute to this shared set. + 0x1 + + + + + FC1DATAOUTEN + Controls FC1 contribution to SHAREDDATAOUT for this shared set. + 17 + 1 + read-write + + + INPUT + Data output from FC1 does not contribute to this shared set. + 0 + + + OUTPUT + Data output from FC1 does contribute to this shared set. + 0x1 + + + + + F20DATAOUTEN + Controls FC2 contribution to SHAREDDATAOUT for this shared set. + 18 + 1 + read-write + + + INPUT + Data output from FC2 does not contribute to this shared set. + 0 + + + OUTPUT + Data output from FC2 does contribute to this shared set. + 0x1 + + + + + FC3DATAOUTEN + Controls FC3 contribution to SHAREDDATAOUT for this shared set. + 19 + 1 + read-write + + + INPUT + Data output from FC3 does not contribute to this shared set. + 0 + + + OUTPUT + Data output from FC3 does contribute to this shared set. + 0x1 + + + + + FC4DATAOUTEN + Controls FC4 contribution to SHAREDDATAOUT for this shared set. + 20 + 1 + read-write + + + INPUT + Data output from FC4 does not contribute to this shared set. + 0 + + + OUTPUT + Data output from FC4 does contribute to this shared set. + 0x1 + + + + + FC5DATAOUTEN + Controls FC5 contribution to SHAREDDATAOUT for this shared set. + 21 + 1 + read-write + + + INPUT + Data output from FC5 does not contribute to this shared set. + 0 + + + OUTPUT + Data output from FC5 does contribute to this shared set. + 0x1 + + + + + FC6DATAOUTEN + Controls FC6 contribution to SHAREDDATAOUT for this shared set. + 22 + 1 + read-write + + + INPUT + Data output from FC6 does not contribute to this shared set. + 0 + + + OUTPUT + Data output from FC6 does contribute to this shared set. + 0x1 + + + + + FC7DATAOUTEN + Controls FC7 contribution to SHAREDDATAOUT for this shared set. + 23 + 1 + read-write + + + INPUT + Data output from FC7 does not contribute to this shared set. + 0 + + + OUTPUT + Data output from FC7 does contribute to this shared set. + 0x1 + + + + + + + USB_HS_STATUS + Status register for USB HS + 0x100 + 32 + read-write + 0 + 0x1C0FF00 + + + USBHS_3V_NOK + USB_HS: Low voltage detection on 3.3V supply. + 0 + 1 + read-only + + + SUPPLY_3V_OK + 3v3 supply is good. + 0 + + + SUPPLY_3V_LOW + 3v3 supply is too low. + 0x1 + + + + + + + + + RTC + Real-Time Clock (RTC) + RTC + 0x4002C000 + + 0 + 0x60 + registers + + + RTC + 29 + + + + CTRL + RTC control register + 0 + 32 + read-write + 0x1 + 0x3FD + + + SWRESET + Software reset control + 0 + 1 + read-write + + + NOT_IN_RESET + Not in reset. The RTC is not held in reset. This bit must be cleared prior to configuring or initiating any operation of the RTC. + 0 + + + IN_RESET + In reset. The RTC is held in reset. All register bits within the RTC will be forced to their reset value except the OFD bit. This bit must be cleared before writing to any register in the RTC - including writes to set any of the other bits within this register. Do not attempt to write to any bits of this register at the same time that the reset bit is being cleared. + 0x1 + + + + + ALARM1HZ + RTC 1 Hz timer alarm flag status. + 2 + 1 + read-write + + + NO_MATCH + No match. No match has occurred on the 1 Hz RTC timer. Writing a 0 has no effect. + 0 + + + MATCH + Match. A match condition has occurred on the 1 Hz RTC timer. This flag generates an RTC alarm interrupt request RTC_ALARM which can also wake up the part from any low power mode. Writing a 1 clears this bit. + 0x1 + + + + + WAKE1KHZ + RTC 1 kHz timer wake-up flag status. + 3 + 1 + read-write + + + RUN + Run. The RTC 1 kHz timer is running. Writing a 0 has no effect. + 0 + + + TIMEOUT + Time-out. The 1 kHz high-resolution/wake-up timer has timed out. This flag generates an RTC wake-up interrupt request RTC-WAKE which can also wake up the part from any low power mode. Writing a 1 clears this bit. + 0x1 + + + + + ALARMDPD_EN + RTC 1 Hz timer alarm enable for Deep power-down. + 4 + 1 + read-write + + + DISABLE + Disable. A match on the 1 Hz RTC timer will not bring the part out of Deep power-down mode. + 0 + + + ENABLE + Enable. A match on the 1 Hz RTC timer bring the part out of Deep power-down mode. + 0x1 + + + + + WAKEDPD_EN + RTC 1 kHz timer wake-up enable for Deep power-down. + 5 + 1 + read-write + + + DISABLE + Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode. + 0 + + + ENABLE + Enable. A match on the 1 kHz RTC timer bring the part out of Deep power-down mode. + 0x1 + + + + + RTC1KHZ_EN + RTC 1 kHz clock enable. This bit can be set to 0 to conserve power if the 1 kHz timer is not used. This bit has no effect when the RTC is disabled (bit 7 of this register is 0). + 6 + 1 + read-write + + + DISABLE + Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode. + 0 + + + ENABLE + Enable. The 1 kHz RTC timer is enabled. + 0x1 + + + + + RTC_EN + RTC enable. + 7 + 1 + read-write + + + DISABLE + Disable. The RTC 1 Hz and 1 kHz clocks are shut down and the RTC operation is disabled. This bit should be 0 when writing to load a value in the RTC counter register. + 0 + + + ENABLE + Enable. The 1 Hz RTC clock is running and RTC operation is enabled. This bit must be set to initiate operation of the RTC. The first clock to the RTC counter occurs 1 s after this bit is set. To also enable the high-resolution, 1 kHz clock, set bit 6 in this register. + 0x1 + + + + + RTC_OSC_PD + RTC oscillator power-down control. + 8 + 1 + read-write + + + POWER_UP + See RTC_OSC_BYPASS + 0 + + + POWERED_DOWN + RTC oscillator is powered-down. + 0x1 + + + + + RTC_OSC_BYPASS + RTC oscillator bypass control. + 9 + 1 + read-write + + + USED + The RTC Oscillator operates normally as a crystal oscillator with the crystal connected between the RTC_XTALIN and RTC_XTALOUT pins. + 0 + + + BYPASS + The RTC Oscillator is in bypass mode. In this mode a clock can be directly input into the RTC_XTALIN pin. + 0x1 + + + + + RTC_SUBSEC_ENA + RTC Sub-second counter control. + 10 + 1 + read-write + + + POWER_UP + The sub-second counter (if implemented) is disabled. This bit is cleared by a system-level POR or BOD reset as well as a by the RTC_ENA bit (bit 7 in this register). On modules not equipped with a sub-second counter, this bit will always read-back as a '0'. + 0 + + + POWERED_DOWN + The 32 KHz sub-second counter is enabled (if implemented). Counting commences on the start of the first one-second interval after this bit is set. Note: This bit can only be set after the RTC_ENA bit (bit 7) is set by a previous write operation. Note: The RTC sub-second counter must be re-enabled whenever the chip exits deep power-down mode. + 0x1 + + + + + + + MATCH + RTC match register + 0x4 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + MATVAL + Contains the match value against which the 1 Hz RTC timer will be compared to set the alarm flag RTC_ALARM and generate an alarm interrupt/wake-up if enabled. + 0 + 32 + read-write + + + + + COUNT + RTC counter register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + VAL + A read reflects the current value of the main, 1 Hz RTC timer. A write loads a new initial value into the timer. The RTC counter will count up continuously at a 1 Hz rate once the RTC Software Reset is removed (by clearing bit 0 of the CTRL register). Only write to this register when the RTC_EN bit in the RTC CTRL Register is 0. The counter increments one second after the RTC_EN bit is set. + 0 + 32 + read-write + + + + + WAKE + High-resolution/wake-up timer control register + 0xC + 32 + read-write + 0 + 0xFFFF + + + VAL + A read reflects the current value of the high-resolution/wake-up timer. A write pre-loads a start count value into the wake-up timer and initializes a count-down sequence. Do not write to this register while counting is in progress. + 0 + 16 + read-write + + + + + SUBSEC + RTC Sub-second Counter register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + SUBSEC + A read reflects the current value of the 32Khz sub-second counter. This counter will be cleared whenever the SUBSEC_ENA bit in the RTC_CONTROL register is low. Up-counting at a 32 KHz rate commences at the start of the next one-second interval after the SUBSEC_ENA bit is set. This counter must be re-enabled after exiting deep_powerdown mode or after the main RTC module has been disabled and re-enabled. On modules not equipped with a sub-second counter, this register will read-back as all zeroes. + 0 + 15 + read-only + + + + + 8 + 0x4 + GPREG[%s] + General Purpose register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPDATA + Data retained during Deep power-down mode or loss of main power as long as VBAT is supplied. + 0 + 32 + read-write + + + + + + + OSTIMER + Synchronous OS/Event timer with Wakeup Timer + OSTIMER + 0x4002D000 + + 0 + 0x20 + registers + + + OS_EVENT + 38 + + + + EVTIMERL + EVTIMER Low Register + 0 + 32 + read-only + 0 + 0xFFFFFFFF + + + EVTIMER_COUNT_VALUE + A read reflects the current value of the lower 32 bits of the EVTIMER. Note there is physically only one EVTimer, readable from all domains. + 0 + 32 + read-only + + + + + EVTIMERH + EVTIMER High Register + 0x4 + 32 + read-only + 0 + 0xFFFFFFFF + + + EVTIMER_COUNT_VALUE + A read reflects the current value of the upper 32 bits of the EVTIMER. Note there is physically only one EVTimer, readable from all domains. + 0 + 32 + read-only + + + + + CAPTUREn_L + Local Capture Low Register for CPUn + 0x8 + 32 + read-only + 0 + 0xFFFFFFFF + + + CAPTUREn_VALUE + A read reflects the value of the lower 32 bits of the central EVTIMER at the time the last capture signal was generated by the CPU. A separate pair of CAPTURE registers are implemented for each CPU. Each CPU reads its own capture value at the same pair of addresses. + 0 + 32 + read-only + + + + + CAPTUREn_H + Local Capture High Register for CPUn + 0xC + 32 + read-only + 0 + 0xFFFFFFFF + + + CAPTUREn_VALUE + A read reflects the value of the upper 32 bits of the central EVTIMER at the time the last capture signal was generated by the CPU. A separate pair of CAPTURE registers are implemented for each CPU. Each CPU reads its own capture value at the same pair of addresses. + 0 + 32 + read-only + + + + + MATCHn_L + Local Match Low Register for CPUn + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + MATCHn_VALUE + The value written to the MATCH (L/H) register pair is compared against the central EVTIMER. When a match occurs, an interrupt request is generated if enabled. A separate pair of MATCH registers are implemented for each CPU. Each CPU reads its own local value at the same pair of addresses. + 0 + 32 + read-write + + + + + MATCHn_H + Match High Register for CPUn + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + MATCHn_VALUE + The value written to the MATCH (L/H) register pair is compared against the central EVTIMER. When a match occurs, an interrupt request is generated if enabled. A separate pair of MATCH registers are implemented for each CPU. Each CPU reads its own local value at the same pair of addresses. + 0 + 32 + read-write + + + + + OSEVENT_CTRL + OS_EVENT TIMER Control Register for CPUn + 0x1C + 32 + read-write + 0 + 0x3 + + + OSTIMER_INTRFLAG + This bit is set when a match occurs between the central 64-bit EVTIMER and the value programmed in the Match-register pair for the associated CPU This bit is cleared by writing a '1'. Writes to clear this bit are asynchronous. This should be done before a new match value is written into the MATCH_L/H registers + 0 + 1 + read-write + + + OSTIMER_INTENA + When this bit is '1' an interrupt/wakeup request to the Domainn processor will be asserted when the OSTIMER_INTR flag is set. When this bit is '0', interrupt/wakeup requests due to the OSTIMER_INTR flag are blocked.A separate OSEVENT_CTRL register is implemented for each CPU. Each CPU reads its own local value at the same address. + 1 + 1 + read-write + + + + + + + FLASH + FLASH + FLASH + 0x40034000 + + 0 + 0x1000 + registers + + + + CMD + command register + 0 + 32 + write-only + 0 + 0xFFFFFFFF + + + CMD + command register. + 0 + 32 + write-only + + + + + EVENT + event register + 0x4 + 32 + write-only + 0 + 0x7 + + + RST + When bit is set, the controller and flash are reset. + 0 + 1 + write-only + + + WAKEUP + When bit is set, the controller wakes up from whatever low power or powerdown mode was active. + 1 + 1 + write-only + + + ABORT + When bit is set, a running program/erase command is aborted. + 2 + 1 + write-only + + + + + BURST + read burst register + 0x8 + 32 + read-write + 0x80000000 + 0xFFFFFFFF + + + XOR_MASK + burst 2 XOR mask. + 0 + 20 + read-write + + + DESCR1 + Burst 1 descriptor. + 20 + 4 + read-write + + + DESCR2 + Burst 2 descriptor. + 24 + 4 + read-write + + + DESCR3 + Burst 3 descriptor. + 28 + 4 + read-write + + + + + STARTA + start (or only) address for next flash command + 0x10 + 32 + read-write + 0 + 0x3FFFF + + + STARTA + Address / Start address for commands that take an address (range) as a parameter. + 0 + 18 + read-write + + + + + STOPA + end address for next flash command, if command operates on address ranges + 0x14 + 32 + read-write + 0 + 0x3FFFF + + + STOPA + Stop address for commands that take an address range as a parameter (the word specified by STOPA is included in the address range). + 0 + 18 + read-write + + + + + 8 + 0x4 + DATAW[%s] + data register, word 0-7; Memory data, or command parameter, or command result. + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATAW + no description available + 0 + 32 + read-write + + + + + INT_CLR_ENABLE + Clear interrupt enable bits + 0xFD8 + 32 + write-only + 0 + 0xF + + + FAIL + When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared. + 0 + 1 + write-only + + + ERR + When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared. + 1 + 1 + write-only + + + DONE + When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared. + 2 + 1 + write-only + + + ECC_ERR + When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared. + 3 + 1 + write-only + + + + + INT_SET_ENABLE + Set interrupt enable bits + 0xFDC + 32 + write-only + 0 + 0xF + + + FAIL + When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set. + 0 + 1 + write-only + + + ERR + When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set. + 1 + 1 + write-only + + + DONE + When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set. + 2 + 1 + write-only + + + ECC_ERR + When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set. + 3 + 1 + write-only + + + + + INT_STATUS + Interrupt status bits + 0xFE0 + 32 + read-write + 0 + 0xF + + + FAIL + This status bit is set if execution of a (legal) command failed. + 0 + 1 + read-only + + + ERR + This status bit is set if execution of an illegal command is detected. + 1 + 1 + read-only + + + DONE + This status bit is set at the end of command execution. + 2 + 1 + read-only + + + ECC_ERR + This status bit is set if, during a memory read operation (either a user-requested read, or a speculative read, or reads performed by a controller command), a correctable or uncorrectable error is detected by ECC decoding logic. + 3 + 1 + read-only + + + + + INT_ENABLE + Interrupt enable bits + 0xFE4 + 32 + read-write + 0 + 0xF + + + FAIL + If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high. + 0 + 1 + read-only + + + ERR + If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high. + 1 + 1 + read-only + + + DONE + If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high. + 2 + 1 + read-only + + + ECC_ERR + If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high. + 3 + 1 + read-only + + + + + INT_CLR_STATUS + Clear interrupt status bits + 0xFE8 + 32 + write-only + 0 + 0xF + + + FAIL + When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared. + 0 + 1 + write-only + + + ERR + When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared. + 1 + 1 + write-only + + + DONE + When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared. + 2 + 1 + write-only + + + ECC_ERR + When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared. + 3 + 1 + write-only + + + + + INT_SET_STATUS + Set interrupt status bits + 0xFEC + 32 + write-only + 0 + 0xF + + + FAIL + When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set. + 0 + 1 + write-only + + + ERR + When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set. + 1 + 1 + write-only + + + DONE + When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set. + 2 + 1 + write-only + + + ECC_ERR + When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set. + 3 + 1 + write-only + + + + + MODULE_ID + Controller+Memory module identification + 0xFFC + 32 + read-only + 0xC40F0800 + 0xFFFFFFFF + + + APERTURE + Aperture i. + 0 + 8 + read-only + + + MINOR_REV + Minor revision i. + 8 + 4 + read-only + + + MAJOR_REV + Major revision i. + 12 + 4 + read-only + + + ID + Identifier. + 16 + 16 + read-only + + + + + + + PRINCE + PRINCE + PRINCE + 0x40035000 + + 0 + 0x40 + registers + + + + ENC_ENABLE + Encryption Enable register + 0 + 32 + read-write + 0 + 0x1 + + + EN + Encryption Enable. + 0 + 1 + read-write + + + DISABLED + Encryption of writes to the flash controller DATAW* registers is disabled.. + 0 + + + ENABLED + Encryption of writes to the flash controller DATAW* registers is enabled.. + 0x1 + + + + + + + MASK_LSB + Data Mask register, 32 Least Significant Bits + 0x4 + 32 + write-only + 0 + 0xFFFFFFFF + + + MASKVAL + Value of the 32 Least Significant Bits of the 64-bit data mask. + 0 + 32 + write-only + + + + + MASK_MSB + Data Mask register, 32 Most Significant Bits + 0x8 + 32 + write-only + 0 + 0xFFFFFFFF + + + MASKVAL + Value of the 32 Most Significant Bits of the 64-bit data mask. + 0 + 32 + write-only + + + + + LOCK + Lock register + 0xC + 32 + read-write + 0 + 0x107 + + + LOCKREG0 + Lock Region 0 registers. + 0 + 1 + read-write + + + DISABLED + Disabled. IV_LSB0, IV_MSB0, BASE_ADDR0, and SR_ENABLE0 are writable.. + 0 + + + ENABLED + Enabled. IV_LSB0, IV_MSB0, BASE_ADDR0, and SR_ENABLE0 are not writable.. + 0x1 + + + + + LOCKREG1 + Lock Region 1 registers. + 1 + 1 + read-write + + + DISABLED + Disabled. IV_LSB1, IV_MSB1, BASE_ADDR1, and SR_ENABLE1 are writable.. + 0 + + + ENABLED + Enabled. IV_LSB1, IV_MSB1, BASE_ADDR1, and SR_ENABLE1 are not writable.. + 0x1 + + + + + LOCKREG2 + Lock Region 2 registers. + 2 + 1 + read-write + + + DISABLED + Disabled. IV_LSB2, IV_MSB2, BASE_ADDR2, and SR_ENABLE2 are writable.. + 0 + + + ENABLED + Enabled. IV_LSB2, IV_MSB2, BASE_ADDR2, and SR_ENABLE2 are not writable.. + 0x1 + + + + + LOCKMASK + Lock the Mask registers. + 8 + 1 + read-write + + + DISABLED + Disabled. MASK_LSB, and MASK_MSB are writable.. + 0 + + + ENABLED + Enabled. MASK_LSB, and MASK_MSB are not writable.. + 0x1 + + + + + + + IV_LSB0 + Initial Vector register for region 0, Least Significant Bits + 0x10 + 32 + write-only + 0 + 0xFFFFFFFF + + + IVVAL + Initial Vector value for the 32 Least Significant Bits of the 64-bit Initial Vector. + 0 + 32 + write-only + + + + + IV_MSB0 + Initial Vector register for region 0, Most Significant Bits + 0x14 + 32 + write-only + 0 + 0xFFFFFFFF + + + IVVAL + Initial Vector value for the 32 Most Significant Bits of the 64-bit Initial Vector. + 0 + 32 + write-only + + + + + BASE_ADDR0 + Base Address for region 0 register + 0x18 + 32 + read-write + 0 + 0xFFFFF + + + ADDR_FIXED + Fixed portion of the base address of region 0. + 0 + 18 + read-only + + + ADDR_PRG + Programmable portion of the base address of region 0. + 18 + 2 + read-write + + + + + SR_ENABLE0 + Sub-Region Enable register for region 0 + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + EN + Each bit in this field enables an 8KB subregion for encryption at offset 8KB*bitnum of region 0. + 0 + 32 + read-write + + + + + IV_LSB1 + Initial Vector register for region 1, Least Significant Bits + 0x20 + 32 + write-only + 0 + 0xFFFFFFFF + + + IVVAL + Initial Vector value for the 32 Least Significant Bits of the 64-bit Initial Vector. + 0 + 32 + write-only + + + + + IV_MSB1 + Initial Vector register for region 1, Most Significant Bits + 0x24 + 32 + write-only + 0 + 0xFFFFFFFF + + + IVVAL + Initial Vector value for the 32 Most Significant Bits of the 64-bit Initial Vector. + 0 + 32 + write-only + + + + + BASE_ADDR1 + Base Address for region 1 register + 0x28 + 32 + read-write + 0x40000 + 0xFFFFF + + + ADDR_FIXED + Fixed portion of the base address of region 1. + 0 + 18 + read-only + + + ADDR_PRG + Programmable portion of the base address of region 1. + 18 + 2 + read-write + + + + + SR_ENABLE1 + Sub-Region Enable register for region 1 + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + EN + Each bit in this field enables an 8KB subregion for encryption at offset 8KB*bitnum of region 1. + 0 + 32 + read-write + + + + + IV_LSB2 + Initial Vector register for region 2, Least Significant Bits + 0x30 + 32 + write-only + 0 + 0xFFFFFFFF + + + IVVAL + Initial Vector value for the 32 Least Significant Bits of the 64-bit Initial Vector. + 0 + 32 + write-only + + + + + IV_MSB2 + Initial Vector register for region 2, Most Significant Bits + 0x34 + 32 + write-only + 0 + 0xFFFFFFFF + + + IVVAL + Initial Vector value for the 32 Most Significant Bits of the 64-bit Initial Vector. + 0 + 32 + write-only + + + + + BASE_ADDR2 + Base Address for region 2 register + 0x38 + 32 + read-write + 0x80000 + 0xFFFFF + + + ADDR_FIXED + Fixed portion of the base address of region 2. + 0 + 18 + read-only + + + ADDR_PRG + Programmable portion of the base address of region 2. + 18 + 2 + read-write + + + + + SR_ENABLE2 + Sub-Region Enable register for region 2 + 0x3C + 32 + read-write + 0 + 0xFFFFFFFF + + + EN + Each bit in this field enables an 8KB subregion for encryption at offset 8KB*bitnum of region 2. + 0 + 32 + read-write + + + + + + + USBPHY + Universal System Bus Physical Layer + USBPHY + 0x40038000 + + 0 + 0x110 + registers + + + + PWD + USB PHY Power-Down Register + 0 + 32 + read-write + 0x1E1C00 + 0xFFFFFFFF + + + TXPWDFS + Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled + 10 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the + 0x1 + + + + + TXPWDIBIAS + Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled + 11 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the + 0x1 + + + + + TXPWDV2I + Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled + 12 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Power-down the USB PHY transmit V-to-I converter and the current mirror + 0x1 + + + + + RXPWDENV + Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled + 17 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Power-down the USB high-speed receiver envelope detector (squelch signal) + 0x1 + + + + + RXPWD1PT1 + Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled + 18 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Power-down the USB full-speed differential receiver. + 0x1 + + + + + RXPWDDIFF + Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled + 19 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Power-down the USB high-speed differential receive + 0x1 + + + + + RXPWDRX + This bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled + 20 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Power-down the entire USB PHY receiver block except for the full-speed differential receiver + 0x1 + + + + + + + PWD_SET + USB PHY Power-Down Register + 0x4 + 32 + read-write + 0x1E1C00 + 0xFFFFFFFF + + + TXPWDFS + Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled + 10 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the + 0x1 + + + + + TXPWDIBIAS + Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled + 11 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the + 0x1 + + + + + TXPWDV2I + Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled + 12 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Power-down the USB PHY transmit V-to-I converter and the current mirror + 0x1 + + + + + RXPWDENV + Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled + 17 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Power-down the USB high-speed receiver envelope detector (squelch signal) + 0x1 + + + + + RXPWD1PT1 + Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled + 18 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Power-down the USB full-speed differential receiver. + 0x1 + + + + + RXPWDDIFF + Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled + 19 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Power-down the USB high-speed differential receive + 0x1 + + + + + RXPWDRX + This bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled + 20 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Power-down the entire USB PHY receiver block except for the full-speed differential receiver + 0x1 + + + + + + + PWD_CLR + USB PHY Power-Down Register + 0x8 + 32 + read-write + 0x1E1C00 + 0xFFFFFFFF + + + TXPWDFS + Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled + 10 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the + 0x1 + + + + + TXPWDIBIAS + Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled + 11 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the + 0x1 + + + + + TXPWDV2I + Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled + 12 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Power-down the USB PHY transmit V-to-I converter and the current mirror + 0x1 + + + + + RXPWDENV + Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled + 17 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Power-down the USB high-speed receiver envelope detector (squelch signal) + 0x1 + + + + + RXPWD1PT1 + Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled + 18 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Power-down the USB full-speed differential receiver. + 0x1 + + + + + RXPWDDIFF + Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled + 19 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Power-down the USB high-speed differential receive + 0x1 + + + + + RXPWDRX + This bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled + 20 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Power-down the entire USB PHY receiver block except for the full-speed differential receiver + 0x1 + + + + + + + PWD_TOG + USB PHY Power-Down Register + 0xC + 32 + read-write + 0x1E1C00 + 0xFFFFFFFF + + + TXPWDFS + Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled + 10 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the + 0x1 + + + + + TXPWDIBIAS + Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled + 11 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the + 0x1 + + + + + TXPWDV2I + Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled + 12 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Power-down the USB PHY transmit V-to-I converter and the current mirror + 0x1 + + + + + RXPWDENV + Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled + 17 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Power-down the USB high-speed receiver envelope detector (squelch signal) + 0x1 + + + + + RXPWD1PT1 + Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled + 18 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Power-down the USB full-speed differential receiver. + 0x1 + + + + + RXPWDDIFF + Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled + 19 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Power-down the USB high-speed differential receive + 0x1 + + + + + RXPWDRX + This bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled + 20 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Power-down the entire USB PHY receiver block except for the full-speed differential receiver + 0x1 + + + + + + + TX + USB PHY Transmitter Control Register + 0x10 + 32 + read-write + 0xA000402 + 0xFFFFFFFF + + + D_CAL + Decode to trim the nominal 17 + 0 + 4 + read-write + + + value0 + Maximum current, approximately 19% above nominal. + 0 + + + value7 + Nominal + 0x7 + + + value15 + Minimum current, approximately 19% below nominal. + 0xF + + + + + TXCAL45DM + Decode to trim the nominal 45ohm series termination resistance to the USB_DM output pin + 8 + 4 + read-write + + + TXENCAL45DN + Enable resistance calibration on DN. + 13 + 1 + read-write + + + TXCAL45DP + Decode to trim the nominal 45ohm series termination resistance to the USB_DP output pin + 16 + 4 + read-write + + + TXENCAL45DP + Enable resistance calibration on DP. + 21 + 1 + read-write + + + + + TX_SET + USB PHY Transmitter Control Register + 0x14 + 32 + read-write + 0xA000402 + 0xFFFFFFFF + + + D_CAL + Decode to trim the nominal 17 + 0 + 4 + read-write + + + value0 + Maximum current, approximately 19% above nominal. + 0 + + + value7 + Nominal + 0x7 + + + value15 + Minimum current, approximately 19% below nominal. + 0xF + + + + + TXCAL45DM + Decode to trim the nominal 45ohm series termination resistance to the USB_DM output pin + 8 + 4 + read-write + + + TXENCAL45DN + Enable resistance calibration on DN. + 13 + 1 + read-write + + + TXCAL45DP + Decode to trim the nominal 45ohm series termination resistance to the USB_DP output pin + 16 + 4 + read-write + + + TXENCAL45DP + Enable resistance calibration on DP. + 21 + 1 + read-write + + + + + TX_CLR + USB PHY Transmitter Control Register + 0x18 + 32 + read-write + 0xA000402 + 0xFFFFFFFF + + + D_CAL + Decode to trim the nominal 17 + 0 + 4 + read-write + + + value0 + Maximum current, approximately 19% above nominal. + 0 + + + value7 + Nominal + 0x7 + + + value15 + Minimum current, approximately 19% below nominal. + 0xF + + + + + TXCAL45DM + Decode to trim the nominal 45ohm series termination resistance to the USB_DM output pin + 8 + 4 + read-write + + + TXENCAL45DN + Enable resistance calibration on DN. + 13 + 1 + read-write + + + TXCAL45DP + Decode to trim the nominal 45ohm series termination resistance to the USB_DP output pin + 16 + 4 + read-write + + + TXENCAL45DP + Enable resistance calibration on DP. + 21 + 1 + read-write + + + + + TX_TOG + USB PHY Transmitter Control Register + 0x1C + 32 + read-write + 0xA000402 + 0xFFFFFFFF + + + D_CAL + Decode to trim the nominal 17 + 0 + 4 + read-write + + + value0 + Maximum current, approximately 19% above nominal. + 0 + + + value7 + Nominal + 0x7 + + + value15 + Minimum current, approximately 19% below nominal. + 0xF + + + + + TXCAL45DM + Decode to trim the nominal 45ohm series termination resistance to the USB_DM output pin + 8 + 4 + read-write + + + TXENCAL45DN + Enable resistance calibration on DN. + 13 + 1 + read-write + + + TXCAL45DP + Decode to trim the nominal 45ohm series termination resistance to the USB_DP output pin + 16 + 4 + read-write + + + TXENCAL45DP + Enable resistance calibration on DP. + 21 + 1 + read-write + + + + + RX + USB PHY Receiver Control Register + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENVADJ + The ENVADJ field adjusts the trip point for the envelope detector + 0 + 3 + read-write + + + value0 + Trip-Level Voltage is 0.1000 V + 0 + + + value1 + Trip-Level Voltage is 0.1125 V + 0x1 + + + value2 + Trip-Level Voltage is 0.1250 V + 0x2 + + + value3 + Trip-Level Voltage is 0.0875 V + 0x3 + + + + + DISCONADJ + The DISCONADJ field adjusts the trip point for the disconnect detector. + 4 + 3 + read-write + + + value0 + Trip-Level Voltage is 0.56875 V + 0 + + + value1 + Trip-Level Voltage is 0.55000 V + 0x1 + + + value2 + Trip-Level Voltage is 0.58125 V + 0x2 + + + value3 + Trip-Level Voltage is 0.60000 V + 0x3 + + + + + RXDBYPASS + This test mode is intended for lab use only, replace FS differential receiver with DP single ended receiver + 22 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver + 0x1 + + + + + + + RX_SET + USB PHY Receiver Control Register + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENVADJ + The ENVADJ field adjusts the trip point for the envelope detector + 0 + 3 + read-write + + + value0 + Trip-Level Voltage is 0.1000 V + 0 + + + value1 + Trip-Level Voltage is 0.1125 V + 0x1 + + + value2 + Trip-Level Voltage is 0.1250 V + 0x2 + + + value3 + Trip-Level Voltage is 0.0875 V + 0x3 + + + + + DISCONADJ + The DISCONADJ field adjusts the trip point for the disconnect detector. + 4 + 3 + read-write + + + value0 + Trip-Level Voltage is 0.56875 V + 0 + + + value1 + Trip-Level Voltage is 0.55000 V + 0x1 + + + value2 + Trip-Level Voltage is 0.58125 V + 0x2 + + + value3 + Trip-Level Voltage is 0.60000 V + 0x3 + + + + + RXDBYPASS + This test mode is intended for lab use only, replace FS differential receiver with DP single ended receiver + 22 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver + 0x1 + + + + + + + RX_CLR + USB PHY Receiver Control Register + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENVADJ + The ENVADJ field adjusts the trip point for the envelope detector + 0 + 3 + read-write + + + value0 + Trip-Level Voltage is 0.1000 V + 0 + + + value1 + Trip-Level Voltage is 0.1125 V + 0x1 + + + value2 + Trip-Level Voltage is 0.1250 V + 0x2 + + + value3 + Trip-Level Voltage is 0.0875 V + 0x3 + + + + + DISCONADJ + The DISCONADJ field adjusts the trip point for the disconnect detector. + 4 + 3 + read-write + + + value0 + Trip-Level Voltage is 0.56875 V + 0 + + + value1 + Trip-Level Voltage is 0.55000 V + 0x1 + + + value2 + Trip-Level Voltage is 0.58125 V + 0x2 + + + value3 + Trip-Level Voltage is 0.60000 V + 0x3 + + + + + RXDBYPASS + This test mode is intended for lab use only, replace FS differential receiver with DP single ended receiver + 22 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver + 0x1 + + + + + + + RX_TOG + USB PHY Receiver Control Register + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + ENVADJ + The ENVADJ field adjusts the trip point for the envelope detector + 0 + 3 + read-write + + + value0 + Trip-Level Voltage is 0.1000 V + 0 + + + value1 + Trip-Level Voltage is 0.1125 V + 0x1 + + + value2 + Trip-Level Voltage is 0.1250 V + 0x2 + + + value3 + Trip-Level Voltage is 0.0875 V + 0x3 + + + + + DISCONADJ + The DISCONADJ field adjusts the trip point for the disconnect detector. + 4 + 3 + read-write + + + value0 + Trip-Level Voltage is 0.56875 V + 0 + + + value1 + Trip-Level Voltage is 0.55000 V + 0x1 + + + value2 + Trip-Level Voltage is 0.58125 V + 0x2 + + + value3 + Trip-Level Voltage is 0.60000 V + 0x3 + + + + + RXDBYPASS + This test mode is intended for lab use only, replace FS differential receiver with DP single ended receiver + 22 + 1 + read-write + + + value0 + Normal operation. + 0 + + + value1 + Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver + 0x1 + + + + + + + CTRL + USB PHY General Control Register + 0x30 + 32 + read-write + 0xC0000000 + 0xFFFFFFFF + + + ENHOSTDISCONDETECT + For host mode, enables high-speed disconnect detector + 1 + 1 + read-write + + + HOSTDISCONDETECT_IRQ + Indicates that the device has disconnected in High-Speed mode + 3 + 1 + read-write + + + ENDEVPLUGINDET + Enables non-standard resistive plugged-in detection This bit field controls connection of nominal 200kohm resistors to both the USB_DP and USB_DM pins as one method of detecting when a USB cable is attached in device mode + 4 + 1 + read-write + + + value0 + Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) + 0 + + + value1 + Enables 200kohm pullup resistors on USB_DP and USB_DM pins + 0x1 + + + + + DEVPLUGIN_IRQ + Indicates that the device is connected + 12 + 1 + read-write + + + DATA_ON_LRADC + Data on LR ADC: Enables the LRADC to monitor USB_DP and USB_DM + 13 + 1 + read-write + + + ENUTMILEVEL2 + Enables UTMI+ Level 2 operation for the USB HS PHY + 14 + 1 + read-write + + + ENUTMILEVEL3 + Enables UTMI+ Level 3 operation for the USB HS PHY + 15 + 1 + read-write + + + AUTORESUME_EN + Enable the auto resume feature, when set, HW will use 32KHz clock to send Resume to respond to the device remote wakeup(for host mode only) + 18 + 1 + read-write + + + ENAUTOCLR_CLKGATE + Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended + 19 + 1 + read-write + + + ENAUTOCLR_PHY_PWD + Enables the feature to auto-clear the PWD register bits in PWD if there is wakeup event while USB is suspended + 20 + 1 + read-write + + + FSDLL_RST_EN + Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet. + 24 + 1 + read-write + + + OTG_ID_VALUE + Indicates the results of USB_ID pin while monitoring the cable plugged into the Micro- or Mini-AB receptacle + 27 + 1 + read-write + + + HOST_FORCE_LS_SE0 + Forces the next FS packet that is transmitted to have a EOP with low-speed timing + 28 + 1 + read-write + + + UTMI_SUSPENDM + Used by the PHY to indicate a powered-down state + 29 + 1 + read-write + + + CLKGATE + Gate UTMI Clocks + 30 + 1 + read-write + + + SFTRST + Writing a 1 to this bit will soft-reset the PWD, TX, RX, and CTRL registers + 31 + 1 + read-write + + + + + CTRL_SET + USB PHY General Control Register + 0x34 + 32 + read-write + 0xC0000000 + 0xFFFFFFFF + + + ENHOSTDISCONDETECT + For host mode, enables high-speed disconnect detector + 1 + 1 + read-write + + + HOSTDISCONDETECT_IRQ + Indicates that the device has disconnected in High-Speed mode + 3 + 1 + read-write + + + ENDEVPLUGINDET + Enables non-standard resistive plugged-in detection This bit field controls connection of nominal 200kohm resistors to both the USB_DP and USB_DM pins as one method of detecting when a USB cable is attached in device mode + 4 + 1 + read-write + + + value0 + Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) + 0 + + + value1 + Enables 200kohm pullup resistors on USB_DP and USB_DM pins + 0x1 + + + + + DEVPLUGIN_IRQ + Indicates that the device is connected + 12 + 1 + read-write + + + ENUTMILEVEL2 + Enables UTMI+ Level 2 operation for the USB HS PHY + 14 + 1 + read-write + + + ENUTMILEVEL3 + Enables UTMI+ Level 3 operation for the USB HS PHY + 15 + 1 + read-write + + + AUTORESUME_EN + Enable the auto resume feature, when set, HW will use 32KHz clock to send Resume to respond to the device remote wakeup(for host mode only) + 18 + 1 + read-write + + + ENAUTOCLR_CLKGATE + Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended + 19 + 1 + read-write + + + ENAUTOCLR_PHY_PWD + Enables the feature to auto-clear the PWD register bits in PWD if there is wakeup event while USB is suspended + 20 + 1 + read-write + + + FSDLL_RST_EN + Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet. + 24 + 1 + read-write + + + OTG_ID_VALUE + Indicates the results of USB_ID pin while monitoring the cable plugged into the Micro- or Mini-AB receptacle + 27 + 1 + read-write + + + HOST_FORCE_LS_SE0 + Forces the next FS packet that is transmitted to have a EOP with low-speed timing + 28 + 1 + read-write + + + UTMI_SUSPENDM + Used by the PHY to indicate a powered-down state + 29 + 1 + read-write + + + CLKGATE + Gate UTMI Clocks + 30 + 1 + read-write + + + SFTRST + Writing a 1 to this bit will soft-reset the PWD, TX, RX, and CTRL registers + 31 + 1 + read-write + + + + + CTRL_CLR + USB PHY General Control Register + 0x38 + 32 + read-write + 0xC0000000 + 0xFFFFFFFF + + + ENHOSTDISCONDETECT + For host mode, enables high-speed disconnect detector + 1 + 1 + read-write + + + HOSTDISCONDETECT_IRQ + Indicates that the device has disconnected in High-Speed mode + 3 + 1 + read-write + + + ENDEVPLUGINDET + Enables non-standard resistive plugged-in detection This bit field controls connection of nominal 200kohm resistors to both the USB_DP and USB_DM pins as one method of detecting when a USB cable is attached in device mode + 4 + 1 + read-write + + + value0 + Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) + 0 + + + value1 + Enables 200kohm pullup resistors on USB_DP and USB_DM pins + 0x1 + + + + + DEVPLUGIN_IRQ + Indicates that the device is connected + 12 + 1 + read-write + + + ENUTMILEVEL2 + Enables UTMI+ Level 2 operation for the USB HS PHY + 14 + 1 + read-write + + + ENUTMILEVEL3 + Enables UTMI+ Level 3 operation for the USB HS PHY + 15 + 1 + read-write + + + AUTORESUME_EN + Enable the auto resume feature, when set, HW will use 32KHz clock to send Resume to respond to the device remote wakeup(for host mode only) + 18 + 1 + read-write + + + ENAUTOCLR_CLKGATE + Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended + 19 + 1 + read-write + + + ENAUTOCLR_PHY_PWD + Enables the feature to auto-clear the PWD register bits in PWD if there is wakeup event while USB is suspended + 20 + 1 + read-write + + + FSDLL_RST_EN + Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet. + 24 + 1 + read-write + + + OTG_ID_VALUE + Indicates the results of USB_ID pin while monitoring the cable plugged into the Micro- or Mini-AB receptacle + 27 + 1 + read-write + + + HOST_FORCE_LS_SE0 + Forces the next FS packet that is transmitted to have a EOP with low-speed timing + 28 + 1 + read-write + + + UTMI_SUSPENDM + Used by the PHY to indicate a powered-down state + 29 + 1 + read-write + + + CLKGATE + Gate UTMI Clocks + 30 + 1 + read-write + + + SFTRST + Writing a 1 to this bit will soft-reset the PWD, TX, RX, and CTRL registers + 31 + 1 + read-write + + + + + CTRL_TOG + USB PHY General Control Register + 0x3C + 32 + read-write + 0xC0000000 + 0xFFFFFFFF + + + ENHOSTDISCONDETECT + For host mode, enables high-speed disconnect detector + 1 + 1 + read-write + + + HOSTDISCONDETECT_IRQ + Indicates that the device has disconnected in High-Speed mode + 3 + 1 + read-write + + + ENDEVPLUGINDET + Enables non-standard resistive plugged-in detection This bit field controls connection of nominal 200kohm resistors to both the USB_DP and USB_DM pins as one method of detecting when a USB cable is attached in device mode + 4 + 1 + read-write + + + value0 + Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) + 0 + + + value1 + Enables 200kohm pullup resistors on USB_DP and USB_DM pins + 0x1 + + + + + DEVPLUGIN_IRQ + Indicates that the device is connected + 12 + 1 + read-write + + + ENUTMILEVEL2 + Enables UTMI+ Level 2 operation for the USB HS PHY + 14 + 1 + read-write + + + ENUTMILEVEL3 + Enables UTMI+ Level 3 operation for the USB HS PHY + 15 + 1 + read-write + + + AUTORESUME_EN + Enable the auto resume feature, when set, HW will use 32KHz clock to send Resume to respond to the device remote wakeup(for host mode only) + 18 + 1 + read-write + + + ENAUTOCLR_CLKGATE + Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended + 19 + 1 + read-write + + + ENAUTOCLR_PHY_PWD + Enables the feature to auto-clear the PWD register bits in PWD if there is wakeup event while USB is suspended + 20 + 1 + read-write + + + FSDLL_RST_EN + Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet. + 24 + 1 + read-write + + + OTG_ID_VALUE + Indicates the results of USB_ID pin while monitoring the cable plugged into the Micro- or Mini-AB receptacle + 27 + 1 + read-write + + + HOST_FORCE_LS_SE0 + Forces the next FS packet that is transmitted to have a EOP with low-speed timing + 28 + 1 + read-write + + + UTMI_SUSPENDM + Used by the PHY to indicate a powered-down state + 29 + 1 + read-write + + + CLKGATE + Gate UTMI Clocks + 30 + 1 + read-write + + + SFTRST + Writing a 1 to this bit will soft-reset the PWD, TX, RX, and CTRL registers + 31 + 1 + read-write + + + + + STATUS + USB PHY Status Register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + HOSTDISCONDETECT_STATUS + Indicates at the local host (downstream) port that the remote device has disconnected while in High-Speed mode + 3 + 1 + read-write + + + value0 + USB cable disconnect has not been detected at the local host + 0 + + + value1 + USB cable disconnect has been detected at the local host + 0x1 + + + + + DEVPLUGIN_STATUS + Status indicator for non-standard resistive plugged-in detection Indicates that the device has been connected on the USB_DP and USB_DM lines using the nonstandard resistive plugged-in detection method controlled by CTRL[4] + 6 + 1 + read-write + + + value0 + No attachment to a USB host is detected + 0 + + + value1 + Cable attachment to a USB host is detected + 0x1 + + + + + OTGID_STATUS + Indicates the results of USB_ID pin on the USB cable plugged into the local Micro- or Mini-AB receptacle + 8 + 1 + read-write + + + RESUME_STATUS + Indicates that the host is sending a wake-up after Suspend and has triggered an interrupt. + 10 + 1 + read-write + + + + + DEBUG0 + USB PHY Debug Register 0 + 0x50 + 32 + read-write + 0x7F180000 + 0xFFFFFFFF + + + OTGIDPIOLOCK + Once OTG ID from STATUS_OTGID_STATUS is sampled, use this to hold the value + 0 + 1 + read-write + + + DEBUG_INTERFACE_HOLD + Use holding registers to assist in timing for external UTMI interface. + 1 + 1 + read-write + + + HSTPULLDOWN + This bit field selects whether to connect pulldown resistors on the USB_DP/USB_DM pins if the corresponding pulldown overdrive mode is enabled through DEBUG[5:4} Set bit 3 to value 1'b1 to connect the 15ohm pulldown on USB_DP line + 2 + 2 + read-write + + + ENHSTPULLDOWN + This bit field selects host pulldown overdrive mode + 4 + 2 + read-write + + + TX2RXCOUNT + Delay in between the end of transmit to the beginning of receive + 8 + 4 + read-write + + + ENTX2RXCOUNT + Set this bit to allow a countdown to transition in between TX and RX. + 12 + 1 + read-write + + + SQUELCHRESETCOUNT + Delay in between the detection of squelch to the reset of high-speed RX. + 16 + 5 + read-write + + + ENSQUELCHRESET + Set bit to allow squelch to reset high-speed receive. + 24 + 1 + read-write + + + SQUELCHRESETLENGTH + Duration of RESET in terms of the number of 480-MHz cycles. + 25 + 4 + read-write + + + HOST_RESUME_DEBUG + Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1. + 29 + 1 + read-write + + + CLKGATE + Gate Test Clocks + 30 + 1 + read-write + + + + + DEBUG0_SET + USB PHY Debug Register 0 + 0x54 + 32 + read-write + 0x7F180000 + 0xFFFFFFFF + + + OTGIDPIOLOCK + Once OTG ID from STATUS_OTGID_STATUS is sampled, use this to hold the value + 0 + 1 + read-write + + + DEBUG_INTERFACE_HOLD + Use holding registers to assist in timing for external UTMI interface. + 1 + 1 + read-write + + + HSTPULLDOWN + This bit field selects whether to connect pulldown resistors on the USB_DP/USB_DM pins if the corresponding pulldown overdrive mode is enabled through DEBUG[5:4} Set bit 3 to value 1'b1 to connect the 15ohm pulldown on USB_DP line + 2 + 2 + read-write + + + ENHSTPULLDOWN + This bit field selects host pulldown overdrive mode + 4 + 2 + read-write + + + TX2RXCOUNT + Delay in between the end of transmit to the beginning of receive + 8 + 4 + read-write + + + ENTX2RXCOUNT + Set this bit to allow a countdown to transition in between TX and RX. + 12 + 1 + read-write + + + SQUELCHRESETCOUNT + Delay in between the detection of squelch to the reset of high-speed RX. + 16 + 5 + read-write + + + ENSQUELCHRESET + Set bit to allow squelch to reset high-speed receive. + 24 + 1 + read-write + + + SQUELCHRESETLENGTH + Duration of RESET in terms of the number of 480-MHz cycles. + 25 + 4 + read-write + + + HOST_RESUME_DEBUG + Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1. + 29 + 1 + read-write + + + CLKGATE + Gate Test Clocks + 30 + 1 + read-write + + + + + DEBUG0_CLR + USB PHY Debug Register 0 + 0x58 + 32 + read-write + 0x7F180000 + 0xFFFFFFFF + + + OTGIDPIOLOCK + Once OTG ID from STATUS_OTGID_STATUS is sampled, use this to hold the value + 0 + 1 + read-write + + + DEBUG_INTERFACE_HOLD + Use holding registers to assist in timing for external UTMI interface. + 1 + 1 + read-write + + + HSTPULLDOWN + This bit field selects whether to connect pulldown resistors on the USB_DP/USB_DM pins if the corresponding pulldown overdrive mode is enabled through DEBUG[5:4} Set bit 3 to value 1'b1 to connect the 15ohm pulldown on USB_DP line + 2 + 2 + read-write + + + ENHSTPULLDOWN + This bit field selects host pulldown overdrive mode + 4 + 2 + read-write + + + TX2RXCOUNT + Delay in between the end of transmit to the beginning of receive + 8 + 4 + read-write + + + ENTX2RXCOUNT + Set this bit to allow a countdown to transition in between TX and RX. + 12 + 1 + read-write + + + SQUELCHRESETCOUNT + Delay in between the detection of squelch to the reset of high-speed RX. + 16 + 5 + read-write + + + ENSQUELCHRESET + Set bit to allow squelch to reset high-speed receive. + 24 + 1 + read-write + + + SQUELCHRESETLENGTH + Duration of RESET in terms of the number of 480-MHz cycles. + 25 + 4 + read-write + + + HOST_RESUME_DEBUG + Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1. + 29 + 1 + read-write + + + CLKGATE + Gate Test Clocks + 30 + 1 + read-write + + + + + DEBUG0_TOG + USB PHY Debug Register 0 + 0x5C + 32 + read-write + 0x7F180000 + 0xFFFFFFFF + + + OTGIDPIOLOCK + Once OTG ID from STATUS_OTGID_STATUS is sampled, use this to hold the value + 0 + 1 + read-write + + + DEBUG_INTERFACE_HOLD + Use holding registers to assist in timing for external UTMI interface. + 1 + 1 + read-write + + + HSTPULLDOWN + This bit field selects whether to connect pulldown resistors on the USB_DP/USB_DM pins if the corresponding pulldown overdrive mode is enabled through DEBUG[5:4} Set bit 3 to value 1'b1 to connect the 15ohm pulldown on USB_DP line + 2 + 2 + read-write + + + ENHSTPULLDOWN + This bit field selects host pulldown overdrive mode + 4 + 2 + read-write + + + TX2RXCOUNT + Delay in between the end of transmit to the beginning of receive + 8 + 4 + read-write + + + ENTX2RXCOUNT + Set this bit to allow a countdown to transition in between TX and RX. + 12 + 1 + read-write + + + SQUELCHRESETCOUNT + Delay in between the detection of squelch to the reset of high-speed RX. + 16 + 5 + read-write + + + ENSQUELCHRESET + Set bit to allow squelch to reset high-speed receive. + 24 + 1 + read-write + + + SQUELCHRESETLENGTH + Duration of RESET in terms of the number of 480-MHz cycles. + 25 + 4 + read-write + + + HOST_RESUME_DEBUG + Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1. + 29 + 1 + read-write + + + CLKGATE + Gate Test Clocks + 30 + 1 + read-write + + + + + DEBUG1 + UTMI Debug Status Register 1 + 0x70 + 32 + read-write + 0x1000 + 0xFFFFFFFF + + + ENTAILADJVD + Delay increment of the rise of squelch: + 13 + 2 + read-write + + + value0 + Delay is nominal + 0 + + + value1 + Delay is +20% + 0x1 + + + value2 + Delay is -20% + 0x2 + + + value3 + Delay is -40% + 0x3 + + + + + USB2_REFBIAS_VBGADJ + Adjustment bits on bandgap + 18 + 3 + read-write + + + USB2_REFBIAS_TST + Bias current control for usb2_phy + 21 + 2 + read-write + + + + + DEBUG1_SET + UTMI Debug Status Register 1 + 0x74 + 32 + read-write + 0x1000 + 0xFFFFFFFF + + + ENTAILADJVD + Delay increment of the rise of squelch: + 13 + 2 + read-write + + + value0 + Delay is nominal + 0 + + + value1 + Delay is +20% + 0x1 + + + value2 + Delay is -20% + 0x2 + + + value3 + Delay is -40% + 0x3 + + + + + USB2_REFBIAS_VBGADJ + Adjustment bits on bandgap + 18 + 3 + read-write + + + USB2_REFBIAS_TST + Bias current control for usb2_phy + 21 + 2 + read-write + + + + + DEBUG1_CLR + UTMI Debug Status Register 1 + 0x78 + 32 + read-write + 0x1000 + 0xFFFFFFFF + + + ENTAILADJVD + Delay increment of the rise of squelch: + 13 + 2 + read-write + + + value0 + Delay is nominal + 0 + + + value1 + Delay is +20% + 0x1 + + + value2 + Delay is -20% + 0x2 + + + value3 + Delay is -40% + 0x3 + + + + + USB2_REFBIAS_VBGADJ + Adjustment bits on bandgap + 18 + 3 + read-write + + + USB2_REFBIAS_TST + Bias current control for usb2_phy + 21 + 2 + read-write + + + + + DEBUG1_TOG + UTMI Debug Status Register 1 + 0x7C + 32 + read-write + 0x1000 + 0xFFFFFFFF + + + ENTAILADJVD + Delay increment of the rise of squelch: + 13 + 2 + read-write + + + value0 + Delay is nominal + 0 + + + value1 + Delay is +20% + 0x1 + + + value2 + Delay is -20% + 0x2 + + + value3 + Delay is -40% + 0x3 + + + + + USB2_REFBIAS_VBGADJ + Adjustment bits on bandgap + 18 + 3 + read-write + + + USB2_REFBIAS_TST + Bias current control for usb2_phy + 21 + 2 + read-write + + + + + VERSION + UTMI RTL Version + 0x80 + 32 + read-only + 0x5000000 + 0xFFFFFFFF + + + STEP + Fixed read-only value reflecting the stepping of the RTL version. + 0 + 16 + read-only + + + MINOR + Fixed read-only value reflecting the MINOR field of the RTL version + 16 + 8 + read-only + + + MAJOR + Fixed read-only value reflecting the MAJOR field of the RTL versio + 24 + 8 + read-only + + + + + PLL_SIC + USB PHY PLL Control/Status Register + 0xA0 + 32 + read-write + 0xD12000 + 0xFFFFFFFF + + + MISC2_CONTROL0 + Modifies the operation of the pll_sic_power_int signal + 5 + 1 + read-write + + + PLL_EN_USB_CLKS + Enables the USB clock from PLL to USB PHY + 6 + 1 + read-write + + + PLL_POWER + Power up the USB PLL + 12 + 1 + read-write + + + PLL_ENABLE + Enables the clock output from the USB PLL + 13 + 1 + read-write + + + PLL_BYPASS + Bypass the USB PLL. + 16 + 1 + read-write + + + REFBIAS_PWD_SEL + Reference bias power down select. + 19 + 1 + read-write + + + value0 + Selects PLL_POWER to control the reference bias + 0 + + + value1 + Selects REFBIAS_PWD to control the reference bias + 0x1 + + + + + REFBIAS_PWD + Power down the reference bias This bit is only used when REFBIAS_PWD_SEL is set to 1. + 20 + 1 + read-write + + + PLL_REG_ENABLE + This field controls the USB PLL regulator, set to enable the regulator + 21 + 1 + read-write + + + PLL_DIV_SEL + This field controls the USB PLL feedback loop divider + 22 + 3 + read-write + + + value0 + Divide by 13 + 0 + + + value1 + Divide by 15 + 0x1 + + + value2 + Divide by 16 + 0x2 + + + value3 + Divide by 20 + 0x3 + + + value4 + Divide by 22 + 0x4 + + + value5 + Divide by 25 + 0x5 + + + value6 + Divide by 30 + 0x6 + + + value7 + Divide by 240 + 0x7 + + + + + PLL_LOCK + USB PLL lock status indicator + 31 + 1 + read-write + + + value0 + PLL is not currently locked + 0 + + + value1 + PLL is currently locked + 0x1 + + + + + + + PLL_SIC_SET + USB PHY PLL Control/Status Register + 0xA4 + 32 + read-write + 0xD12000 + 0xFFFFFFFF + + + MISC2_CONTROL0 + Modifies the operation of the pll_sic_power_int signal + 5 + 1 + read-write + + + PLL_EN_USB_CLKS + Enables the USB clock from PLL to USB PHY + 6 + 1 + read-write + + + PLL_POWER + Power up the USB PLL + 12 + 1 + read-write + + + PLL_ENABLE + Enables the clock output from the USB PLL + 13 + 1 + read-write + + + PLL_BYPASS + Bypass the USB PLL. + 16 + 1 + read-write + + + REFBIAS_PWD_SEL + Reference bias power down select. + 19 + 1 + read-write + + + value0 + Selects PLL_POWER to control the reference bias + 0 + + + value1 + Selects REFBIAS_PWD to control the reference bias + 0x1 + + + + + REFBIAS_PWD + Power down the reference bias This bit is only used when REFBIAS_PWD_SEL is set to 1. + 20 + 1 + read-write + + + PLL_REG_ENABLE + This field controls the USB PLL regulator, set to enable the regulator + 21 + 1 + read-write + + + PLL_DIV_SEL + This field controls the USB PLL feedback loop divider + 22 + 3 + read-write + + + value0 + Divide by 13 + 0 + + + value1 + Divide by 15 + 0x1 + + + value2 + Divide by 16 + 0x2 + + + value3 + Divide by 20 + 0x3 + + + value4 + Divide by 22 + 0x4 + + + value5 + Divide by 25 + 0x5 + + + value6 + Divide by 30 + 0x6 + + + value7 + Divide by 240 + 0x7 + + + + + PLL_LOCK + USB PLL lock status indicator + 31 + 1 + read-write + + + value0 + PLL is not currently locked + 0 + + + value1 + PLL is currently locked + 0x1 + + + + + + + PLL_SIC_CLR + USB PHY PLL Control/Status Register + 0xA8 + 32 + read-write + 0xD12000 + 0xFFFFFFFF + + + MISC2_CONTROL0 + Modifies the operation of the pll_sic_power_int signal + 5 + 1 + read-write + + + PLL_EN_USB_CLKS + Enables the USB clock from PLL to USB PHY + 6 + 1 + read-write + + + PLL_POWER + Power up the USB PLL + 12 + 1 + read-write + + + PLL_ENABLE + Enables the clock output from the USB PLL + 13 + 1 + read-write + + + PLL_BYPASS + Bypass the USB PLL. + 16 + 1 + read-write + + + REFBIAS_PWD_SEL + Reference bias power down select. + 19 + 1 + read-write + + + value0 + Selects PLL_POWER to control the reference bias + 0 + + + value1 + Selects REFBIAS_PWD to control the reference bias + 0x1 + + + + + REFBIAS_PWD + Power down the reference bias This bit is only used when REFBIAS_PWD_SEL is set to 1. + 20 + 1 + read-write + + + PLL_REG_ENABLE + This field controls the USB PLL regulator, set to enable the regulator + 21 + 1 + read-write + + + PLL_DIV_SEL + This field controls the USB PLL feedback loop divider + 22 + 3 + read-write + + + value0 + Divide by 13 + 0 + + + value1 + Divide by 15 + 0x1 + + + value2 + Divide by 16 + 0x2 + + + value3 + Divide by 20 + 0x3 + + + value4 + Divide by 22 + 0x4 + + + value5 + Divide by 25 + 0x5 + + + value6 + Divide by 30 + 0x6 + + + value7 + Divide by 240 + 0x7 + + + + + PLL_LOCK + USB PLL lock status indicator + 31 + 1 + read-write + + + value0 + PLL is not currently locked + 0 + + + value1 + PLL is currently locked + 0x1 + + + + + + + PLL_SIC_TOG + USB PHY PLL Control/Status Register + 0xAC + 32 + read-write + 0xD12000 + 0xFFFFFFFF + + + MISC2_CONTROL0 + Modifies the operation of the pll_sic_power_int signal + 5 + 1 + read-write + + + PLL_EN_USB_CLKS + Enables the USB clock from PLL to USB PHY + 6 + 1 + read-write + + + PLL_POWER + Power up the USB PLL + 12 + 1 + read-write + + + PLL_ENABLE + Enables the clock output from the USB PLL + 13 + 1 + read-write + + + PLL_BYPASS + Bypass the USB PLL. + 16 + 1 + read-write + + + REFBIAS_PWD_SEL + Reference bias power down select. + 19 + 1 + read-write + + + value0 + Selects PLL_POWER to control the reference bias + 0 + + + value1 + Selects REFBIAS_PWD to control the reference bias + 0x1 + + + + + REFBIAS_PWD + Power down the reference bias This bit is only used when REFBIAS_PWD_SEL is set to 1. + 20 + 1 + read-write + + + PLL_REG_ENABLE + This field controls the USB PLL regulator, set to enable the regulator + 21 + 1 + read-write + + + PLL_DIV_SEL + This field controls the USB PLL feedback loop divider + 22 + 3 + read-write + + + value0 + Divide by 13 + 0 + + + value1 + Divide by 15 + 0x1 + + + value2 + Divide by 16 + 0x2 + + + value3 + Divide by 20 + 0x3 + + + value4 + Divide by 22 + 0x4 + + + value5 + Divide by 25 + 0x5 + + + value6 + Divide by 30 + 0x6 + + + value7 + Divide by 240 + 0x7 + + + + + PLL_LOCK + USB PLL lock status indicator + 31 + 1 + read-write + + + value0 + PLL is not currently locked + 0 + + + value1 + PLL is currently locked + 0x1 + + + + + + + USB1_VBUS_DETECT + USB PHY VBUS Detect Control Register + 0xC0 + 32 + read-write + 0x700004 + 0xFFFFFFFF + + + VBUSVALID_THRESH + Sets the threshold for the VBUSVALID comparator + 0 + 3 + read-write + + + value0 + 4.0V + 0 + + + value1 + 4.1V + 0x1 + + + value2 + 4.2V + 0x2 + + + value3 + 4.3V + 0x3 + + + value4 + 4.4V(Default) + 0x4 + + + value5 + 4.5V + 0x5 + + + value6 + 4.6V + 0x6 + + + value7 + 4.7V + 0x7 + + + + + VBUS_OVERRIDE_EN + VBUS detect signal override enable + 3 + 1 + read-write + + + value0 + Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) + 0 + + + value1 + Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND + 0x1 + + + + + SESSEND_OVERRIDE + Override value for SESSEND The bit field provides the value for USB1_VBUS_DET_STAT[0] if USB_VBUS_DETECT[3] is set to value 1'b1 + 4 + 1 + read-write + + + BVALID_OVERRIDE + Override value for B-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[1] if USB_VBUS_DETECT[3] is set to value 1'b1 + 5 + 1 + read-write + + + AVALID_OVERRIDE + Override value for A-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[2] if USB_VBUS_DETECT[3] is set to value 1'b1 + 6 + 1 + read-write + + + VBUSVALID_OVERRIDE + Override value for VBUS_VALID signal sent to USB controller The bit field provides the value for VBUS_VALID reported to the USB controller if the value of USB1_VBUS_DETECT[3] is set to 1'b1 + 7 + 1 + read-write + + + VBUSVALID_SEL + Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fields that selects the source of the VBUS_VALID signal reported to the USB controller + 8 + 1 + read-write + + + value0 + Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) + 0 + + + value1 + Use the VBUS_VALID_3V detector results for signal reported to the USB controller + 0x1 + + + + + VBUS_SOURCE_SEL + Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fields that selects the source of the VBUS_VALID signal reported to the USB controller + 9 + 2 + read-write + + + value0 + Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) + 0 + + + value1 + Use the Session Valid comparator results for signal reported to the USB controller + 0x1 + + + value2 + Use the Session Valid comparator results for signal reported to the USB controller + 0x2 + + + + + VBUSVALID_TO_SESSVALID + Selects the comparator used for VBUS_VALID This bit field controls the comparator used to report the VBUS_VALID results in USB1_VBUS_DETECT[3] between the VBUS_VALID comparator and the Session Valid comparator + 18 + 1 + read-write + + + value0 + Use the VBUS_VALID comparator for VBUS_VALID results + 0 + + + value1 + Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. + 0x1 + + + + + PWRUP_CMPS + Enables the VBUS_VALID comparator Powers up the comparator used for the VBUS_VALID detector + 20 + 1 + read-write + + + value0 + Powers down the VBUS_VALID comparator + 0 + + + value1 + Enables the VBUS_VALID comparator (default) + 0x1 + + + + + DISCHARGE_VBUS + Controls VBUS discharge resistor This bit field controls a nominal 22kohm resistor between the USB1_VBUS pin and ground + 26 + 1 + read-write + + + value0 + VBUS discharge resistor is disabled (Default) + 0 + + + value1 + VBUS discharge resistor is enabled + 0x1 + + + + + EN_CHARGER_RESISTOR + Enables resistors used for an older method of resistive battery charger detection + 31 + 1 + read-write + + + value0 + Disable resistive charger detection resistors on USB_DP and USB_DP + 0 + + + value1 + Enable resistive charger detection resistors on USB_DP and USB_DP + 0x1 + + + + + + + USB1_VBUS_DETECT_SET + USB PHY VBUS Detect Control Register + 0xC4 + 32 + read-write + 0x700004 + 0xFFFFFFFF + + + VBUSVALID_THRESH + Sets the threshold for the VBUSVALID comparator + 0 + 3 + read-write + + + value0 + 4.0V + 0 + + + value1 + 4.1V + 0x1 + + + value2 + 4.2V + 0x2 + + + value3 + 4.3V + 0x3 + + + value4 + 4.4V(Default) + 0x4 + + + value5 + 4.5V + 0x5 + + + value6 + 4.6V + 0x6 + + + value7 + 4.7V + 0x7 + + + + + VBUS_OVERRIDE_EN + VBUS detect signal override enable + 3 + 1 + read-write + + + value0 + Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) + 0 + + + value1 + Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND + 0x1 + + + + + SESSEND_OVERRIDE + Override value for SESSEND The bit field provides the value for USB1_VBUS_DET_STAT[0] if USB_VBUS_DETECT[3] is set to value 1'b1 + 4 + 1 + read-write + + + BVALID_OVERRIDE + Override value for B-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[1] if USB_VBUS_DETECT[3] is set to value 1'b1 + 5 + 1 + read-write + + + AVALID_OVERRIDE + Override value for A-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[2] if USB_VBUS_DETECT[3] is set to value 1'b1 + 6 + 1 + read-write + + + VBUSVALID_OVERRIDE + Override value for VBUS_VALID signal sent to USB controller The bit field provides the value for VBUS_VALID reported to the USB controller if the value of USB1_VBUS_DETECT[3] is set to 1'b1 + 7 + 1 + read-write + + + VBUSVALID_SEL + Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fields that selects the source of the VBUS_VALID signal reported to the USB controller + 8 + 1 + read-write + + + value0 + Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) + 0 + + + value1 + Use the VBUS_VALID_3V detector results for signal reported to the USB controller + 0x1 + + + + + VBUS_SOURCE_SEL + Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fields that selects the source of the VBUS_VALID signal reported to the USB controller + 9 + 2 + read-write + + + value0 + Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) + 0 + + + value1 + Use the Session Valid comparator results for signal reported to the USB controller + 0x1 + + + value2 + Use the Session Valid comparator results for signal reported to the USB controller + 0x2 + + + + + VBUSVALID_TO_SESSVALID + Selects the comparator used for VBUS_VALID This bit field controls the comparator used to report the VBUS_VALID results in USB1_VBUS_DETECT[3] between the VBUS_VALID comparator and the Session Valid comparator + 18 + 1 + read-write + + + value0 + Use the VBUS_VALID comparator for VBUS_VALID results + 0 + + + value1 + Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. + 0x1 + + + + + PWRUP_CMPS + Enables the VBUS_VALID comparator Powers up the comparator used for the VBUS_VALID detector + 20 + 1 + read-write + + + value0 + Powers down the VBUS_VALID comparator + 0 + + + value1 + Enables the VBUS_VALID comparator (default) + 0x1 + + + + + DISCHARGE_VBUS + Controls VBUS discharge resistor This bit field controls a nominal 22kohm resistor between the USB1_VBUS pin and ground + 26 + 1 + read-write + + + value0 + VBUS discharge resistor is disabled (Default) + 0 + + + value1 + VBUS discharge resistor is enabled + 0x1 + + + + + EN_CHARGER_RESISTOR + Enables resistors used for an older method of resistive battery charger detection + 31 + 1 + read-write + + + value0 + Disable resistive charger detection resistors on USB_DP and USB_DP + 0 + + + value1 + Enable resistive charger detection resistors on USB_DP and USB_DP + 0x1 + + + + + + + USB1_VBUS_DETECT_CLR + USB PHY VBUS Detect Control Register + 0xC8 + 32 + read-write + 0x700004 + 0xFFFFFFFF + + + VBUSVALID_THRESH + Sets the threshold for the VBUSVALID comparator + 0 + 3 + read-write + + + value0 + 4.0V + 0 + + + value1 + 4.1V + 0x1 + + + value2 + 4.2V + 0x2 + + + value3 + 4.3V + 0x3 + + + value4 + 4.4V(Default) + 0x4 + + + value5 + 4.5V + 0x5 + + + value6 + 4.6V + 0x6 + + + value7 + 4.7V + 0x7 + + + + + VBUS_OVERRIDE_EN + VBUS detect signal override enable + 3 + 1 + read-write + + + value0 + Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) + 0 + + + value1 + Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND + 0x1 + + + + + SESSEND_OVERRIDE + Override value for SESSEND The bit field provides the value for USB1_VBUS_DET_STAT[0] if USB_VBUS_DETECT[3] is set to value 1'b1 + 4 + 1 + read-write + + + BVALID_OVERRIDE + Override value for B-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[1] if USB_VBUS_DETECT[3] is set to value 1'b1 + 5 + 1 + read-write + + + AVALID_OVERRIDE + Override value for A-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[2] if USB_VBUS_DETECT[3] is set to value 1'b1 + 6 + 1 + read-write + + + VBUSVALID_OVERRIDE + Override value for VBUS_VALID signal sent to USB controller The bit field provides the value for VBUS_VALID reported to the USB controller if the value of USB1_VBUS_DETECT[3] is set to 1'b1 + 7 + 1 + read-write + + + VBUSVALID_SEL + Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fields that selects the source of the VBUS_VALID signal reported to the USB controller + 8 + 1 + read-write + + + value0 + Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) + 0 + + + value1 + Use the VBUS_VALID_3V detector results for signal reported to the USB controller + 0x1 + + + + + VBUS_SOURCE_SEL + Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fields that selects the source of the VBUS_VALID signal reported to the USB controller + 9 + 2 + read-write + + + value0 + Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) + 0 + + + value1 + Use the Session Valid comparator results for signal reported to the USB controller + 0x1 + + + value2 + Use the Session Valid comparator results for signal reported to the USB controller + 0x2 + + + + + VBUSVALID_TO_SESSVALID + Selects the comparator used for VBUS_VALID This bit field controls the comparator used to report the VBUS_VALID results in USB1_VBUS_DETECT[3] between the VBUS_VALID comparator and the Session Valid comparator + 18 + 1 + read-write + + + value0 + Use the VBUS_VALID comparator for VBUS_VALID results + 0 + + + value1 + Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. + 0x1 + + + + + PWRUP_CMPS + Enables the VBUS_VALID comparator Powers up the comparator used for the VBUS_VALID detector + 20 + 1 + read-write + + + value0 + Powers down the VBUS_VALID comparator + 0 + + + value1 + Enables the VBUS_VALID comparator (default) + 0x1 + + + + + DISCHARGE_VBUS + Controls VBUS discharge resistor This bit field controls a nominal 22kohm resistor between the USB1_VBUS pin and ground + 26 + 1 + read-write + + + value0 + VBUS discharge resistor is disabled (Default) + 0 + + + value1 + VBUS discharge resistor is enabled + 0x1 + + + + + EN_CHARGER_RESISTOR + Enables resistors used for an older method of resistive battery charger detection + 31 + 1 + read-write + + + value0 + Disable resistive charger detection resistors on USB_DP and USB_DP + 0 + + + value1 + Enable resistive charger detection resistors on USB_DP and USB_DP + 0x1 + + + + + + + USB1_VBUS_DETECT_TOG + USB PHY VBUS Detect Control Register + 0xCC + 32 + read-write + 0x700004 + 0xFFFFFFFF + + + VBUSVALID_THRESH + Sets the threshold for the VBUSVALID comparator + 0 + 3 + read-write + + + value0 + 4.0V + 0 + + + value1 + 4.1V + 0x1 + + + value2 + 4.2V + 0x2 + + + value3 + 4.3V + 0x3 + + + value4 + 4.4V(Default) + 0x4 + + + value5 + 4.5V + 0x5 + + + value6 + 4.6V + 0x6 + + + value7 + 4.7V + 0x7 + + + + + VBUS_OVERRIDE_EN + VBUS detect signal override enable + 3 + 1 + read-write + + + value0 + Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) + 0 + + + value1 + Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND + 0x1 + + + + + SESSEND_OVERRIDE + Override value for SESSEND The bit field provides the value for USB1_VBUS_DET_STAT[0] if USB_VBUS_DETECT[3] is set to value 1'b1 + 4 + 1 + read-write + + + BVALID_OVERRIDE + Override value for B-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[1] if USB_VBUS_DETECT[3] is set to value 1'b1 + 5 + 1 + read-write + + + AVALID_OVERRIDE + Override value for A-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[2] if USB_VBUS_DETECT[3] is set to value 1'b1 + 6 + 1 + read-write + + + VBUSVALID_OVERRIDE + Override value for VBUS_VALID signal sent to USB controller The bit field provides the value for VBUS_VALID reported to the USB controller if the value of USB1_VBUS_DETECT[3] is set to 1'b1 + 7 + 1 + read-write + + + VBUSVALID_SEL + Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fields that selects the source of the VBUS_VALID signal reported to the USB controller + 8 + 1 + read-write + + + value0 + Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) + 0 + + + value1 + Use the VBUS_VALID_3V detector results for signal reported to the USB controller + 0x1 + + + + + VBUS_SOURCE_SEL + Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fields that selects the source of the VBUS_VALID signal reported to the USB controller + 9 + 2 + read-write + + + value0 + Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) + 0 + + + value1 + Use the Session Valid comparator results for signal reported to the USB controller + 0x1 + + + value2 + Use the Session Valid comparator results for signal reported to the USB controller + 0x2 + + + + + VBUSVALID_TO_SESSVALID + Selects the comparator used for VBUS_VALID This bit field controls the comparator used to report the VBUS_VALID results in USB1_VBUS_DETECT[3] between the VBUS_VALID comparator and the Session Valid comparator + 18 + 1 + read-write + + + value0 + Use the VBUS_VALID comparator for VBUS_VALID results + 0 + + + value1 + Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. + 0x1 + + + + + PWRUP_CMPS + Enables the VBUS_VALID comparator Powers up the comparator used for the VBUS_VALID detector + 20 + 1 + read-write + + + value0 + Powers down the VBUS_VALID comparator + 0 + + + value1 + Enables the VBUS_VALID comparator (default) + 0x1 + + + + + DISCHARGE_VBUS + Controls VBUS discharge resistor This bit field controls a nominal 22kohm resistor between the USB1_VBUS pin and ground + 26 + 1 + read-write + + + value0 + VBUS discharge resistor is disabled (Default) + 0 + + + value1 + VBUS discharge resistor is enabled + 0x1 + + + + + EN_CHARGER_RESISTOR + Enables resistors used for an older method of resistive battery charger detection + 31 + 1 + read-write + + + value0 + Disable resistive charger detection resistors on USB_DP and USB_DP + 0 + + + value1 + Enable resistive charger detection resistors on USB_DP and USB_DP + 0x1 + + + + + + + USB1_VBUS_DET_STAT + USB PHY VBUS Detector Status Register + 0xD0 + 32 + read-only + 0 + 0xFFFFFFFF + + + SESSEND + Session End indicator Session End status, value inverted from Session Valid comparator + 0 + 1 + read-only + + + value0 + The VBUS voltage is above the Session Valid threshold + 0 + + + value1 + The VBUS voltage is below the Session Valid threshold + 0x1 + + + + + BVALID + B-Device Session Valid status B-Device Session Valid status, determined by the Session Valid comparator + 1 + 1 + read-only + + + value0 + The VBUS voltage is below the Session Valid threshold + 0 + + + value1 + The VBUS voltage is above the Session Valid threshold + 0x1 + + + + + AVALID + A-Device Session Valid status A-Device Session Valid status, determined by the Session Valid comparator + 2 + 1 + read-only + + + value0 + The VBUS voltage is below the Session Valid threshold + 0 + + + value1 + The VBUS voltage is above the Session Valid threshold + 0x1 + + + + + VBUS_VALID + VBUS voltage status This bit field shows the result of VBUS_VALID detection for the USB1_VBUS pin + 3 + 1 + read-only + + + value0 + VBUS is below the comparator threshold + 0 + + + value1 + VBUS is above the comparator threshold + 0x1 + + + + + VBUS_VALID_3V + VBUS_VALID_3V detector status The VBUS_VALID_3V detector has a lower threshold for the voltage on the USB1_VBUS pin than either the Session Valid or VBUS_VALID comparators + 4 + 1 + read-only + + + value0 + VBUS voltage is below VBUS_VALID_3V threshold + 0 + + + value1 + VBUS voltage is above VBUS_VALID_3V threshold + 0x1 + + + + + + + USB1_CHRG_DETECT + USB PHY Charger Detect Control Register + 0xE0 + 32 + read-write + 0x80180000 + 0xFFFFFFFF + + + PULLUP_DP + This bit is used to pull up DP, for digital charge detect. + 2 + 1 + read-write + + + BGR_IBIAS + USB charge detector bias current reference This bit determines the reference for the bias current of the USB charge detector + 23 + 1 + read-write + + + value0 + Bias current is derived from the USB PHY internal current generator. + 0 + + + value1 + Bias current is derived from the reference generator of the bandgap. + 0x1 + + + + + + + USB1_CHRG_DETECT_SET + USB PHY Charger Detect Control Register + 0xE4 + 32 + read-write + 0x80180000 + 0xFFFFFFFF + + + PULLUP_DP + This bit is used to pull up DP, for digital charge detect. + 2 + 1 + read-write + + + BGR_IBIAS + USB charge detector bias current reference This bit determines the reference for the bias current of the USB charge detector + 23 + 1 + read-write + + + value0 + Bias current is derived from the USB PHY internal current generator. + 0 + + + value1 + Bias current is derived from the reference generator of the bandgap. + 0x1 + + + + + + + USB1_CHRG_DETECT_CLR + USB PHY Charger Detect Control Register + 0xE8 + 32 + read-write + 0x80180000 + 0xFFFFFFFF + + + PULLUP_DP + This bit is used to pull up DP, for digital charge detect. + 2 + 1 + read-write + + + BGR_IBIAS + USB charge detector bias current reference This bit determines the reference for the bias current of the USB charge detector + 23 + 1 + read-write + + + value0 + Bias current is derived from the USB PHY internal current generator. + 0 + + + value1 + Bias current is derived from the reference generator of the bandgap. + 0x1 + + + + + + + USB1_CHRG_DETECT_TOG + USB PHY Charger Detect Control Register + 0xEC + 32 + read-write + 0x80180000 + 0xFFFFFFFF + + + PULLUP_DP + This bit is used to pull up DP, for digital charge detect. + 2 + 1 + read-write + + + BGR_IBIAS + USB charge detector bias current reference This bit determines the reference for the bias current of the USB charge detector + 23 + 1 + read-write + + + value0 + Bias current is derived from the USB PHY internal current generator. + 0 + + + value1 + Bias current is derived from the reference generator of the bandgap. + 0x1 + + + + + + + USB1_CHRG_DET_STAT + USB PHY Charger Detect Status Register + 0xF0 + 32 + read-only + 0 + 0xFFFFFFFF + + + PLUG_CONTACT + Battery Charging Data Contact Detection phase output During the Data Contact Detection phase per the USB Battery Charging Specification Revision 1 + 0 + 1 + read-only + + + value0 + No USB cable attachment has been detected + 0 + + + value1 + A USB cable attachment between the device and host has been detected + 0x1 + + + + + CHRG_DETECTED + Battery Charging Primary Detection phase output During the USB Battery Charging Primary Detection phase using the USBHSDCD module, this bit field indicates whether a Standard Downstream Port or Charging Port was detected + 1 + 1 + read-only + + + value0 + Standard Downstream Port (SDP) has been detected + 0 + + + value1 + Charging Port has been detected + 0x1 + + + + + DM_STATE + Single ended receiver output for the USB_DM pin, from charger detection circuits. + 2 + 1 + read-only + + + value0 + USB_DM pin voltage is < 0.8V + 0 + + + value1 + USB_DM pin voltage is > 2.0V + 0x1 + + + + + DP_STATE + Single ended receiver output for the USB_DP pin, from charger detection circuits. + 3 + 1 + read-only + + + value0 + USB_DP pin voltage is < 0.8V + 0 + + + value1 + USB_DP pin voltage is > 2.0V + 0x1 + + + + + SECDET_DCP + Battery Charging Secondary Detection phase output During the USB Battery Charging Secondary Detection phase using the USBHSDCD module, this bit field indicates which kind of Charging Port was detected + 4 + 1 + read-only + + + value0 + Charging Downstream Port (CDP) has been detected + 0 + + + value1 + Downstream Charging Port (DCP) has been detected + 0x1 + + + + + + + ANACTRL + USB PHY Analog Control Register + 0x100 + 32 + read-write + 0xA000402 + 0xFFFFFFFF + + + DEV_PULLDOWN + Setting this field to 1'b1 will enable the 15kohm pulldown resistors on both USB_DP and USB_DM pins + 10 + 1 + read-write + + + value0 + The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. + 0 + + + value1 + The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. + 0x1 + + + + + + + ANACTRL_SET + USB PHY Analog Control Register + 0x104 + 32 + read-write + 0xA000402 + 0xFFFFFFFF + + + DEV_PULLDOWN + Setting this field to 1'b1 will enable the 15kohm pulldown resistors on both USB_DP and USB_DM pins + 10 + 1 + read-write + + + value0 + The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. + 0 + + + value1 + The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. + 0x1 + + + + + + + ANACTRL_CLR + USB PHY Analog Control Register + 0x108 + 32 + read-write + 0xA000402 + 0xFFFFFFFF + + + DEV_PULLDOWN + Setting this field to 1'b1 will enable the 15kohm pulldown resistors on both USB_DP and USB_DM pins + 10 + 1 + read-write + + + value0 + The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. + 0 + + + value1 + The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. + 0x1 + + + + + + + ANACTRL_TOG + USB PHY Analog Control Register + 0x10C + 32 + read-write + 0xA000402 + 0xFFFFFFFF + + + DEV_PULLDOWN + Setting this field to 1'b1 will enable the 15kohm pulldown resistors on both USB_DP and USB_DM pins + 10 + 1 + read-write + + + value0 + The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. + 0 + + + value1 + The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. + 0x1 + + + + + + + + + RNG + RNG + RNG + 0x4003A000 + + 0 + 0x1000 + registers + + + + RANDOM_NUMBER + This register contains a random 32 bit number which is computed on demand, at each time it is read + 0 + 32 + read-only + 0 + 0xFFFFFFFF + + + RANDOM_NUMBER + This register contains a random 32 bit number which is computed on demand, at each time it is read. + 0 + 32 + read-only + + + + + ENCRYPTED_NUMBER + This register contains a random 32 bit number which is pre-computed + 0x4 + 32 + read-only + 0 + 0xFFFFFFFF + + + ENCRYPTED_NUMBER + This register contains a random 32 bit number which is pre-computed. + 0 + 32 + read-only + + + + + COUNTER_VAL + no description available + 0x8 + 32 + read-write + 0 + 0x1FFF + + + CLK_RATIO + Gives the ratio between the internal clocks frequencies and the register clock frequency for evaluation and certification purposes. + 0 + 8 + read-only + + + REFRESH_CNT + Incremented (till max possible value) each time COUNTER was updated since last reading to any *_NUMBER. + 8 + 5 + read-only + + + + + COUNTER_CFG + no description available + 0xC + 32 + read-write + 0 + 0x3FF + + + MODE + 00: disabled 01: update once. + 0 + 2 + read-write + + + CLOCK_SEL + Selects the internal clock on which to compute statistics. + 2 + 3 + read-write + + + SHIFT4X + To be used to add precision to clock_ratio and determine 'entropy refill'. + 5 + 3 + read-write + + + DIS_ENH_ENTR_REFILL + Disable 'enhanced entropy refill' feature, which is enabled by default when 'mode' > 00. + 8 + 1 + read-write + + + FORCE_ENTR_SPREADING + Forces entropy spreading (interactions between RNGs) even when 'clock_sel'>0. + 9 + 1 + read-write + + + + + ONLINE_TEST_CFG + no description available + 0x10 + 32 + read-write + 0 + 0x7 + + + ACTIVATE + 0: disabled 1: activated Update rythm for VAL depends on COUNTER_CFG if data_sel is set to COUNTER. + 0 + 1 + read-write + + + DATA_SEL + Selects source on which to apply online test: 00: LSB of COUNTER: raw data from one or all sources of entropy 01: MSB of COUNTER: raw data from one or all sources of entropy 10: RANDOM_NUMBER 11: ENCRYPTED_NUMBER 'activate' should be set to 'disabled' before changing this field. + 1 + 2 + read-write + + + + + ONLINE_TEST_VAL + no description available + 0x14 + 32 + read-write + 0 + 0xFFF + + + LIVE_CHI_SQUARED + This value is updated as described in field 'activate'. + 0 + 4 + read-only + + + MIN_CHI_SQUARED + This field is reset when 'activate'==0. + 4 + 4 + read-only + + + MAX_CHI_SQUARED + This field is reset when 'activate'==0. + 8 + 4 + read-only + + + + + MISC_CFG + no description available + 0x18 + 32 + read-write + 0 + 0x3 + + + AES_RESEED + If set, ENCRYPTED_NUMBER generation becomes predictable, provided all secrets and current internal state are known: independant from entropy source. + 0 + 1 + read-write + + + AES_DT_CFG + Set this bit to re-seed AES. + 1 + 1 + read-write + + + + + POWERDOWN + Powerdown mode (standard but certainly useless here) + 0xFF4 + 32 + read-write + 0 + 0x80000003 + + + SOFT_RESET + Request softreset that will go low automaticaly after acknowledge from CORE. + 0 + 1 + read-write + + + FORCE_SOFT_RESET + When used with softreset it forces CORE_RESETN to low on acknowledge from CORE. + 1 + 1 + read-write + + + POWERDOWN + When set all accesses to standard registers are blocked. + 31 + 1 + read-write + + + + + MODULEID + IP identifier + 0xFFC + 32 + read-only + 0xA0B83200 + 0xFFFFFFFF + + + APERTURE + Aperture i. + 0 + 8 + read-only + + + MIN_REV + Minor revision i. + 8 + 4 + read-only + + + MAJ_REV + Major revision i. + 12 + 4 + read-only + + + ID + Identifier. + 16 + 16 + read-only + + + + + + + PUF + PUFCTRL + PUF + 0x4003B000 + + 0 + 0x260 + registers + + + PUF + 56 + + + + CTRL + PUF Control register + 0 + 32 + read-write + 0 + 0x5F + + + zeroize + Begin Zeroize operation for PUF and go to Error state + 0 + 1 + read-write + + + enroll + Begin Enroll operation + 1 + 1 + read-write + + + start + Begin Start operation + 2 + 1 + read-write + + + GENERATEKEY + Begin Set Intrinsic Key operation + 3 + 1 + read-write + + + SETKEY + Begin Set User Key operation + 4 + 1 + read-write + + + GETKEY + Begin Get Key operation + 6 + 1 + read-write + + + + + KEYINDEX + PUF Key Index register + 0x4 + 32 + read-write + 0 + 0xF + + + KEYIDX + Key index for Set Key operations + 0 + 4 + read-write + + + + + KEYSIZE + PUF Key Size register + 0x8 + 32 + read-write + 0 + 0x3F + + + KEYSIZE + Key size for Set Key operations + 0 + 6 + read-write + + + + + STAT + PUF Status register + 0x20 + 32 + read-write + 0x1 + 0xF7 + + + busy + Indicates that operation is in progress + 0 + 1 + read-only + + + SUCCESS + Last operation was successful + 1 + 1 + read-only + + + error + Quiddikey is in the Error state and no operations can be performed + 2 + 1 + read-only + + + KEYINREQ + Request for next part of key + 4 + 1 + read-only + + + KEYOUTAVAIL + Next part of key is available + 5 + 1 + read-only + + + CODEINREQ + Request for next part of AC/KC + 6 + 1 + read-only + + + CODEOUTAVAIL + Next part of AC/KC is available + 7 + 1 + read-only + + + + + ALLOW + PUF Allow register + 0x28 + 32 + read-write + 0 + 0x8F + + + ALLOWENROLL + Enroll operation is allowed + 0 + 1 + read-only + + + ALLOWSTART + Start operation is allowed + 1 + 1 + read-only + + + ALLOWSETKEY + Set Key operations are allowed + 2 + 1 + read-only + + + ALLOWGETKEY + Get Key operation is allowed + 3 + 1 + read-only + + + + + KEYINPUT + PUF Key Input register + 0x40 + 32 + write-only + 0 + 0xFFFFFFFF + + + KEYIN + Key input data + 0 + 32 + write-only + + + + + CODEINPUT + PUF Code Input register + 0x44 + 32 + write-only + 0 + 0xFFFFFFFF + + + CODEIN + AC/KC input data + 0 + 32 + write-only + + + + + CODEOUTPUT + PUF Code Output register + 0x48 + 32 + read-only + 0 + 0xFFFFFFFF + + + CODEOUT + AC/KC output data + 0 + 32 + read-only + + + + + KEYOUTINDEX + PUF Key Output Index register + 0x60 + 32 + read-write + 0 + 0xF + + + KEYOUTIDX + Key index for the key that is currently output via the Key Output register + 0 + 4 + read-only + + + + + KEYOUTPUT + PUF Key Output register + 0x64 + 32 + read-only + 0 + 0xFFFFFFFF + + + KEYOUT + Key output data + 0 + 32 + read-only + + + + + IFSTAT + PUF Interface Status and clear register + 0xDC + 32 + read-write + 0 + 0x1 + + + ERROR + Indicates that an APB error has occurred,Writing logic1 clears the if_error bit + 0 + 1 + read-write + + + + + VERSION + PUF version register. + 0xFC + 32 + read-only + 0 + 0xFFFFFFFF + + + KEYOUT + Version of the PUF module. + 0 + 32 + read-only + + + + + INTEN + PUF Interrupt Enable + 0x100 + 32 + read-write + 0 + 0xF7 + + + READYEN + Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) + 0 + 1 + read-write + + + SUCCESEN + Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) + 1 + 1 + read-write + + + ERROREN + Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) + 2 + 1 + read-write + + + KEYINREQEN + Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) + 4 + 1 + read-write + + + KEYOUTAVAILEN + Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) + 5 + 1 + read-write + + + CODEINREQEN + Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) + 6 + 1 + read-write + + + CODEOUTAVAILEN + Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) + 7 + 1 + read-write + + + + + INTSTAT + PUF interrupt status + 0x104 + 32 + read-write + 0 + 0xF7 + + + READY + Triggers on falling edge of busy, write 1 to clear + 0 + 1 + read-write + + + SUCCESS + Level sensitive interrupt, cleared when interrupt source clears + 1 + 1 + read-write + + + ERROR + Level sensitive interrupt, cleared when interrupt source clears + 2 + 1 + read-write + + + KEYINREQ + Level sensitive interrupt, cleared when interrupt source clears + 4 + 1 + read-write + + + KEYOUTAVAIL + Level sensitive interrupt, cleared when interrupt source clears + 5 + 1 + read-write + + + CODEINREQ + Level sensitive interrupt, cleared when interrupt source clears + 6 + 1 + read-write + + + CODEOUTAVAIL + Level sensitive interrupt, cleared when interrupt source clears + 7 + 1 + read-write + + + + + PWRCTRL + PUF RAM Power Control + 0x108 + 32 + read-write + 0xF8 + 0xFD + + + RAMON + Power on the PUF RAM. + 0 + 1 + read-write + + + RAMSTAT + PUF RAM status. + 1 + 1 + read-write + + + + + CFG + PUF config register for block bits + 0x10C + 32 + read-write + 0 + 0x3 + + + BLOCKENROLL_SETKEY + Block enroll operation. Write 1 to set, cleared on reset. + 0 + 1 + read-write + + + BLOCKKEYOUTPUT + Block set key operation. Write 1 to set, cleared on reset. + 1 + 1 + read-write + + + + + KEYLOCK + Only reset in case of full IC reset + 0x200 + 32 + read-write + 0xAA + 0xFF + + + KEY0 + "10:Write access to KEY0MASK, KEYENABLE.KEY0 and KEYRESET.KEY0 is allowed. 00, 01, 11:Write access to KEY0MASK, KEYENABLE.KEY0 and KEYRESET.KEY0 is NOT allowed. Important Note : Once this field is written with a value different from '10', its value can no longer be modified until un Power On Reset occurs." + 0 + 2 + read-write + + + KEY1 + "10:Write access to KEY1MASK, KEYENABLE.KEY1 and KEYRESET.KEY1 is allowed. 00, 01, 11:Write access to KEY1MASK, KEYENABLE.KEY1 and KEYRESET.KEY1 is NOT allowed. Important Note : Once this field is written with a value different from '10', its value can no longer be modified until un Power On Reset occurs." + 2 + 2 + read-write + + + KEY2 + "10:Write access to KEY2MASK, KEYENABLE.KEY2 and KEYRESET.KEY2 is allowed. 00, 01, 11:Write access to KEY2MASK, KEYENABLE.KEY2 and KEYRESET.KEY2 is NOT allowed. Important Note : Once this field is written with a value different from '10', its value can no longer be modified until un Power On Reset occurs." "10:Write access to KEY3MASK, KEYENABLE.KEY3 and KEYRESET.KEY3 is allowed. 00, 01, 11:Write access to KEY3MASK, KEYENABLE.KEY3 and KEYRESET.KEY3 is NOT allowed. Important Note : Once this field is written with a value different from '10', its value can no longer be modified until un Power On Reset occurs." + 4 + 2 + read-write + + + KEY3 + "10:Write access to KEY3MASK, KEYENABLE.KEY3 and KEYRESET.KEY3 is allowed. 00, 01, 11:Write access to KEY3MASK, KEYENABLE.KEY3 and KEYRESET.KEY3 is NOT allowed. Important Note : Once this field is written with a value different from '10', its value can no longer be modified until un Power On Reset occurs." + 6 + 2 + read-write + + + + + KEYENABLE + no description available + 0x204 + 32 + read-write + 0x55 + 0xFF + + + KEY0 + "10: Data coming out from PUF Index 0 interface are shifted in KEY0 register. 00, 01, 11 : Data coming out from PUF Index 0 interface are NOT shifted in KEY0 register." + 0 + 2 + read-write + + + KEY1 + "10: Data coming out from PUF Index 0 interface are shifted in KEY1 register. 00, 01, 11 : Data coming out from PUF Index 0 interface are NOT shifted in KEY1 register." + 2 + 2 + read-write + + + KEY2 + "10: Data coming out from PUF Index 0 interface are shifted in KEY2 register. 00, 01, 11 : Data coming out from PUF Index 0 interface are NOT shifted in KEY2 register." + 4 + 2 + read-write + + + KEY3 + "10: Data coming out from PUF Index 0 interface are shifted in KEY2 register. 00, 01, 11 : Data coming out from PUF Index 0 interface are NOT shifted in KEY3 register." + 6 + 2 + read-write + + + + + KEYRESET + Reinitialize Keys shift registers counters + 0x208 + 32 + write-only + 0 + 0xFFFFFFFF + + + KEY0 + 10: Reset KEY0 shift register. Self clearing. Must be done before loading any new key. + 0 + 2 + write-only + + + KEY1 + 10: Reset KEY1 shift register. Self clearing. Must be done before loading any new key. + 2 + 2 + write-only + + + KEY2 + 10: Reset KEY2 shift register. Self clearing. Must be done before loading any new key. + 4 + 2 + write-only + + + KEY3 + 10: Reset KEY3 shift register. Self clearing. Must be done before loading any new key. + 6 + 2 + write-only + + + + + IDXBLK_L + no description available + 0x20C + 32 + read-write + 0x8000AAAA + 0xC000FFFF + + + IDX0 + Use to block PUF index 0 + 0 + 2 + read-write + + + IDX1 + Use to block PUF index 1 + 2 + 2 + read-write + + + IDX2 + Use to block PUF index 2 + 4 + 2 + read-write + + + IDX3 + Use to block PUF index 3 + 6 + 2 + read-write + + + IDX4 + Use to block PUF index 4 + 8 + 2 + read-write + + + IDX5 + Use to block PUF index 5 + 10 + 2 + read-write + + + IDX6 + Use to block PUF index 6 + 12 + 2 + read-write + + + IDX7 + Use to block PUF index 7 + 14 + 2 + read-write + + + LOCK_IDX + Lock 0 to 7 PUF key indexes + 30 + 2 + write-only + + + + + IDXBLK_H_DP + no description available + 0x210 + 32 + read-write + 0xAAAA + 0xFFFFFFFF + + + IDX8 + Use to block PUF index 8 + 0 + 2 + read-write + + + IDX9 + Use to block PUF index 9 + 2 + 2 + read-write + + + IDX10 + Use to block PUF index 10 + 4 + 2 + read-write + + + IDX11 + Use to block PUF index 11 + 6 + 2 + read-write + + + IDX12 + Use to block PUF index 12 + 8 + 2 + read-write + + + IDX13 + Use to block PUF index 13 + 10 + 2 + read-write + + + IDX14 + Use to block PUF index 14 + 12 + 2 + read-write + + + IDX15 + Use to block PUF index 15 + 14 + 2 + read-write + + + + + 4 + 0x4 + KEYMASK[%s] + Only reset in case of full IC reset + 0x214 + 32 + write-only + 0 + 0xFFFFFFFF + + + KEYMASK + no description available + 0 + 32 + write-only + + + + + IDXBLK_H + no description available + 0x254 + 32 + read-write + 0x8000AAAA + 0xC000FFFF + + + IDX8 + Use to block PUF index 8 + 0 + 2 + read-write + + + IDX9 + Use to block PUF index 9 + 2 + 2 + read-write + + + IDX10 + Use to block PUF index 10 + 4 + 2 + read-write + + + IDX11 + Use to block PUF index 11 + 6 + 2 + read-write + + + IDX12 + Use to block PUF index 12 + 8 + 2 + read-write + + + IDX13 + Use to block PUF index 13 + 10 + 2 + read-write + + + IDX14 + Use to block PUF index 14 + 12 + 2 + read-write + + + IDX15 + Use to block PUF index 15 + 14 + 2 + read-write + + + LOCK_IDX + Lock 8 to 15 PUF key indexes + 30 + 2 + write-only + + + + + IDXBLK_L_DP + no description available + 0x258 + 32 + read-write + 0xAAAA + 0xFFFF + + + IDX0 + Use to block PUF index 0 + 0 + 2 + read-write + + + IDX1 + Use to block PUF index 1 + 2 + 2 + read-write + + + IDX2 + Use to block PUF index 2 + 4 + 2 + read-write + + + IDX3 + Use to block PUF index 3 + 6 + 2 + read-write + + + IDX4 + Use to block PUF index 4 + 8 + 2 + read-write + + + IDX5 + Use to block PUF index 5 + 10 + 2 + read-write + + + IDX6 + Use to block PUF index 6 + 12 + 2 + read-write + + + IDX7 + Use to block PUF index 7 + 14 + 2 + read-write + + + + + SHIFT_STATUS + no description available + 0x25C + 32 + read-write + 0 + 0xFFFF + + + KEY0 + Index counter from key 0 shift register + 0 + 4 + read-only + + + KEY1 + Index counter from key 1 shift register + 4 + 4 + read-only + + + KEY2 + Index counter from key 2 shift register + 8 + 4 + read-only + + + KEY3 + Index counter from key 3 shift register + 12 + 4 + read-only + + + + + + + PLU + LPC80X Programmable Logic Unit (PLU) + PLU + 0x4003D000 + + 0 + 0xC20 + registers + + + PLU + 52 + + + + 26 + 0x20 + LUT[%s] + no description available + 0 + + 5 + 0x4 + 0,1,2,3,4 + LUT_INP%s + LUT0 input 0 MUX + 0 + 32 + read-write + 0 + 0x3F + + + LUT_INP + Selects the input source to be connected to LUT0 input0. + 0 + 6 + read-write + + + plu_inputs0 + The PLU primary inputs 0. + 0 + + + plu_inputs1 + The PLU primary inputs 1. + 0x1 + + + plu_inputs2 + The PLU primary inputs 2. + 0x2 + + + plu_inputs3 + The PLU primary inputs 3. + 0x3 + + + plu_inputs4 + The PLU primary inputs 4. + 0x4 + + + plu_inputs5 + The PLU primary inputs 5. + 0x5 + + + lut_outputs0 + The output of LUT0. + 0x6 + + + lut_outputs1 + The output of LUT1. + 0x7 + + + lut_outputs2 + The output of LUT2. + 0x8 + + + lut_outputs3 + The output of LUT3. + 0x9 + + + lut_outputs4 + The output of LUT4. + 0xA + + + lut_outputs5 + The output of LUT5. + 0xB + + + lut_outputs6 + The output of LUT6. + 0xC + + + lut_outputs7 + The output of LUT7. + 0xD + + + lut_outputs8 + The output of LUT8. + 0xE + + + lut_outputs9 + The output of LUT9. + 0xF + + + lut_outputs10 + The output of LUT10. + 0x10 + + + lut_outputs11 + The output of LUT11. + 0x11 + + + lut_outputs12 + The output of LUT12. + 0x12 + + + lut_outputs13 + The output of LUT13. + 0x13 + + + lut_outputs14 + The output of LUT14. + 0x14 + + + lut_outputs15 + The output of LUT15. + 0x15 + + + lut_outputs16 + The output of LUT16. + 0x16 + + + lut_outputs17 + The output of LUT17. + 0x17 + + + lut_outputs18 + The output of LUT18. + 0x18 + + + lut_outputs19 + The output of LUT19. + 0x19 + + + lut_outputs20 + The output of LUT20. + 0x1A + + + lut_outputs21 + The output of LUT21. + 0x1B + + + lut_outputs22 + The output of LUT22. + 0x1C + + + lut_outputs23 + The output of LUT23. + 0x1D + + + lut_outputs24 + The output of LUT24. + 0x1E + + + lut_outputs25 + The output of LUT25. + 0x1F + + + state0 + state(0). + 0x20 + + + state1 + state(1). + 0x21 + + + state2 + state(2). + 0x22 + + + state3 + state(3). + 0x23 + + + + + + + + 26 + 0x4 + LUT_TRUTH[%s] + Specifies the Truth Table contents for LUT0 + 0x800 + 32 + read-write + 0 + 0xFFFFFFFF + + + TRUTH_TABLE + Specifies the Truth Table contents for LUT0.. + 0 + 32 + read-write + + + + + OUTPUTS + Provides the current state of the 8 designated PLU Outputs. + 0x900 + 32 + read-write + 0 + 0xFFFFFFFF + + + OUTPUT_STATE + Provides the current state of the 8 designated PLU Outputs.. + 0 + 8 + read-only + + + + + WAKEINT + Wakeup interrupt control for PLU + 0x904 + 32 + read-write + 0 + 0xFFFFFFFF + + + MASK + Interrupt mask (which of the 8 PLU Outputs contribute to interrupt) + 0 + 8 + read-write + + + FILTER_MODE + control input of the PLU, add filtering for glitch + 8 + 2 + read-write + + + BYPASS + Bypass mode. + 0 + + + FILTER1CLK + Filter 1 clock period. + 0x1 + + + FILTER2CLK + Filter 2 clock period. + 0x2 + + + FILTER3CLK + Filter 3 clock period. + 0x3 + + + + + FILTER_CLKSEL + hclk is divided by 2**filter_clksel + 10 + 2 + read-write + + + LATCH_ENABLE + latch the interrupt , then can be cleared with next bit INTR_CLEAR + 12 + 1 + read-write + + + INTR_CLEAR + Write to clear wakeint_latched + 13 + 1 + read-write + oneToClear + + + + + 8 + 0x4 + OUTPUT_MUX[%s] + Selects the source to be connected to PLU Output 0 + 0xC00 + 32 + read-write + 0 + 0xFFFFFFFF + + + OUTPUTn + Selects the source to be connected to PLU Output 0. + 0 + 5 + read-write + + + plu_output0 + The PLU output 0. + 0 + + + plu_output1 + The PLU output 1. + 0x1 + + + plu_output2 + The PLU output 2. + 0x2 + + + plu_output3 + The PLU output 3. + 0x3 + + + plu_output4 + The PLU output 4. + 0x4 + + + plu_output5 + The PLU output 5. + 0x5 + + + plu_output6 + The PLU output 6. + 0x6 + + + plu_output7 + The PLU output 7. + 0x7 + + + plu_output8 + The PLU output 8. + 0x8 + + + plu_output9 + The PLU output 9. + 0x9 + + + plu_output10 + The PLU output 10. + 0xA + + + plu_output11 + The PLU output 11. + 0xB + + + plu_output12 + The PLU output 12. + 0xC + + + plu_output13 + The PLU output 13. + 0xD + + + plu_output14 + The PLU output 14. + 0xE + + + plu_output15 + The PLU output 15. + 0xF + + + plu_output16 + The PLU output 16. + 0x10 + + + plu_output17 + The PLU output 17. + 0x11 + + + plu_output18 + The PLU output 18. + 0x12 + + + plu_output19 + The PLU output 19. + 0x13 + + + plu_output20 + The PLU output 20. + 0x14 + + + plu_output21 + The PLU output 21. + 0x15 + + + plu_output22 + The PLU output 22. + 0x16 + + + plu_output23 + The PLU output 23. + 0x17 + + + plu_output24 + The PLU output 24. + 0x18 + + + plu_output25 + The PLU output 25. + 0x19 + + + state0 + state(0). + 0x1A + + + state1 + state(1). + 0x1B + + + state2 + state(2). + 0x1C + + + state3 + state(3). + 0x1D + + + + + + + + + DMA0 + DMA controller + DMA + DMA + 0x40082000 + + 0 + 0x5DC + registers + + + DMA0 + 1 + + + + CTRL + DMA control. + 0 + 32 + read-write + 0 + 0x1 + + + ENABLE + DMA controller master enable. + 0 + 1 + read-write + + + DISABLED + Disabled. The DMA controller is disabled. This clears any triggers that were asserted at the point when disabled, but does not prevent re-triggering when the DMA controller is re-enabled. + 0 + + + ENABLED + Enabled. The DMA controller is enabled. + 0x1 + + + + + + + INTSTAT + Interrupt status. + 0x4 + 32 + read-only + 0 + 0x6 + + + ACTIVEINT + Summarizes whether any enabled interrupts (other than error interrupts) are pending. + 1 + 1 + read-only + + + NOT_PENDING + Not pending. No enabled interrupts are pending. + 0 + + + PENDING + Pending. At least one enabled interrupt is pending. + 0x1 + + + + + ACTIVEERRINT + Summarizes whether any error interrupts are pending. + 2 + 1 + read-only + + + NOT_PENDING + Not pending. No error interrupts are pending. + 0 + + + PENDING + Pending. At least one error interrupt is pending. + 0x1 + + + + + + + SRAMBASE + SRAM address of the channel configuration table. + 0x8 + 32 + read-write + 0 + 0xFFFFFE00 + + + OFFSET + Address bits 31:9 of the beginning of the DMA descriptor table. For 18 channels, the table must begin on a 512 byte boundary. + 9 + 23 + read-write + + + + + ENABLESET0 + Channel Enable read and Set for all DMA channels. + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENA + Enable for DMA channels. Bit n enables or disables DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = disabled. 1 = enabled. + 0 + 32 + read-write + + + + + ENABLECLR0 + Channel Enable Clear for all DMA channels. + 0x28 + 32 + write-only + 0 + 0 + + + CLR + Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears the channel enable bit n. The number of bits = number of DMA channels in this device. Other bits are reserved. + 0 + 32 + write-only + + + + + ACTIVE0 + Channel Active status for all DMA channels. + 0x30 + 32 + read-only + 0 + 0xFFFFFFFF + + + ACT + Active flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = not active. 1 = active. + 0 + 32 + read-only + + + + + BUSY0 + Channel Busy status for all DMA channels. + 0x38 + 32 + read-only + 0 + 0xFFFFFFFF + + + BSY + Busy flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = not busy. 1 = busy. + 0 + 32 + read-only + + + + + ERRINT0 + Error Interrupt status for all DMA channels. + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + ERR + Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = error interrupt is not active. 1 = error interrupt is active. + 0 + 32 + read-write + + + + + INTENSET0 + Interrupt Enable read and Set for all DMA channels. + 0x48 + 32 + read-write + 0 + 0xFFFFFFFF + + + INTEN + Interrupt Enable read and set for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = interrupt for DMA channel is disabled. 1 = interrupt for DMA channel is enabled. + 0 + 32 + read-write + + + + + INTENCLR0 + Interrupt Enable Clear for all DMA channels. + 0x50 + 32 + write-only + 0 + 0 + + + CLR + Writing ones to this register clears corresponding bits in the INTENSET0. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. + 0 + 32 + write-only + + + + + INTA0 + Interrupt A status for all DMA channels. + 0x58 + 32 + read-write + 0 + 0xFFFFFFFF + + + IA + Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel interrupt A is not active. 1 = the DMA channel interrupt A is active. + 0 + 32 + read-write + + + + + INTB0 + Interrupt B status for all DMA channels. + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + IB + Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel interrupt B is not active. 1 = the DMA channel interrupt B is active. + 0 + 32 + read-write + + + + + SETVALID0 + Set ValidPending control bits for all DMA channels. + 0x68 + 32 + write-only + 0 + 0 + + + SV + SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = sets the VALIDPENDING control bit for DMA channel n + 0 + 32 + write-only + + + + + SETTRIG0 + Set Trigger control bits for all DMA channels. + 0x70 + 32 + write-only + 0 + 0 + + + TRIG + Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = sets the TRIG bit for DMA channel n. + 0 + 32 + write-only + + + + + ABORT0 + Channel Abort control for all DMA channels. + 0x78 + 32 + write-only + 0 + 0 + + + ABORTCTRL + Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = aborts DMA operations on channel n. + 0 + 32 + write-only + + + + + 30 + 0x10 + CHANNEL[%s] + no description available + 0x400 + + CFG + Configuration register for DMA channel . + 0 + 32 + read-write + 0 + 0x7CF73 + + + PERIPHREQEN + Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller. + 0 + 1 + read-write + + + DISABLED + Disabled. Peripheral DMA requests are disabled. + 0 + + + ENABLED + Enabled. Peripheral DMA requests are enabled. + 0x1 + + + + + HWTRIGEN + Hardware Triggering Enable for this channel. + 1 + 1 + read-write + + + DISABLED + Disabled. Hardware triggering is not used. + 0 + + + ENABLED + Enabled. Use hardware triggering. + 0x1 + + + + + TRIGPOL + Trigger Polarity. Selects the polarity of a hardware trigger for this channel. + 4 + 1 + read-write + + + ACTIVE_LOW_FALLING + Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE. + 0 + + + ACTIVE_HIGH_RISING + Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE. + 0x1 + + + + + TRIGTYPE + Trigger Type. Selects hardware trigger as edge triggered or level triggered. + 5 + 1 + read-write + + + EDGE + Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger. + 0 + + + LEVEL + Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed. + 0x1 + + + + + TRIGBURST + Trigger Burst. Selects whether hardware triggers cause a single or burst transfer. + 6 + 1 + read-write + + + SINGLE + Single transfer. Hardware trigger causes a single transfer. + 0 + + + BURST + Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete. + 0x1 + + + + + BURSTPOWER + Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size. + 8 + 4 + read-write + + + SRCBURSTWRAP + Source Burst Wrap. When enabled, the source data address for the DMA is 'wrapped', meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst. + 14 + 1 + read-write + + + DISABLED + Disabled. Source burst wrapping is not enabled for this DMA channel. + 0 + + + ENABLED + Enabled. Source burst wrapping is enabled for this DMA channel. + 0x1 + + + + + DSTBURSTWRAP + Destination Burst Wrap. When enabled, the destination data address for the DMA is 'wrapped', meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst. + 15 + 1 + read-write + + + DISABLED + Disabled. Destination burst wrapping is not enabled for this DMA channel. + 0 + + + ENABLED + Enabled. Destination burst wrapping is enabled for this DMA channel. + 0x1 + + + + + CHPRIORITY + Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported: 0x0 = highest priority. 0x7 = lowest priority. + 16 + 3 + read-write + + + + + CTLSTAT + Control and status register for DMA channel . + 0x4 + 32 + read-only + 0 + 0x5 + + + VALIDPENDING + Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel. + 0 + 1 + read-only + + + NO_EFFECT + No effect. No effect on DMA operation. + 0 + + + VALID_PENDING + Valid pending. + 0x1 + + + + + TRIG + Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1. + 2 + 1 + read-only + + + NOT_TRIGGERED + Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out. + 0 + + + TRIGGERED + Triggered. The trigger for this DMA channel is set. DMA operations will be carried out. + 0x1 + + + + + + + XFERCFG + Transfer configuration register for DMA channel . + 0x8 + 32 + read-write + 0 + 0x3FFF33F + + + CFGVALID + Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled. + 0 + 1 + read-write + + + NOT_VALID + Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting. + 0 + + + VALID + Valid. The current channel descriptor is considered valid. + 0x1 + + + + + RELOAD + Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers. + 1 + 1 + read-write + + + DISABLED + Disabled. Do not reload the channels' control structure when the current descriptor is exhausted. + 0 + + + ENABLED + Enabled. Reload the channels' control structure when the current descriptor is exhausted. + 0x1 + + + + + SWTRIG + Software Trigger. + 2 + 1 + read-write + + + NOT_SET + Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel. + 0 + + + SET + Set. When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0. + 0x1 + + + + + CLRTRIG + Clear Trigger. + 3 + 1 + read-write + + + NOT_CLEARED + Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started. + 0 + + + CLEARED + Cleared. The trigger is cleared when this descriptor is exhausted + 0x1 + + + + + SETINTA + Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed. + 4 + 1 + read-write + + + NO_EFFECT + No effect. + 0 + + + SET + Set. The INTA flag for this channel will be set when the current descriptor is exhausted. + 0x1 + + + + + SETINTB + Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed. + 5 + 1 + read-write + + + NO_EFFECT + No effect. + 0 + + + SET + Set. The INTB flag for this channel will be set when the current descriptor is exhausted. + 0x1 + + + + + WIDTH + Transfer width used for this DMA channel. + 8 + 2 + read-write + + + BIT_8 + 8-bit. 8-bit transfers are performed (8-bit source reads and destination writes). + 0 + + + BIT_16 + 16-bit. 6-bit transfers are performed (16-bit source reads and destination writes). + 0x1 + + + BIT_32 + 32-bit. 32-bit transfers are performed (32-bit source reads and destination writes). + 0x2 + + + + + SRCINC + Determines whether the source address is incremented for each DMA transfer. + 12 + 2 + read-write + + + NO_INCREMENT + No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device. + 0 + + + WIDTH_X_1 + 1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory. + 0x1 + + + WIDTH_X_2 + 2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer. + 0x2 + + + WIDTH_X_4 + 4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer. + 0x3 + + + + + DSTINC + Determines whether the destination address is incremented for each DMA transfer. + 14 + 2 + read-write + + + NO_INCREMENT + No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device. + 0 + + + WIDTH_X_1 + 1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory. + 0x1 + + + WIDTH_X_2 + 2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer. + 0x2 + + + WIDTH_X_4 + 4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer. + 0x3 + + + + + XFERCOUNT + Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of 1,024 transfers will be performed. + 16 + 10 + read-write + + + + + + + + DMA1 + DMA controller + DMA + 0x400A7000 + + 0 + 0x5DC + registers + + + DMA1 + 58 + + + + USB0 + USB 2.0 Device Controller + USB + 0x40084000 + + 0 + 0x38 + registers + + + USB0_NEEDCLK + 27 + + + USB0 + 28 + + + + DEVCMDSTAT + USB Device Command/Status register + 0 + 32 + read-write + 0x800 + 0x171BFBFF + + + DEV_ADDR + USB device address. After bus reset, the address is reset to 0x00. If the enable bit is set, the device will respond on packets for function address DEV_ADDR. When receiving a SetAddress Control Request from the USB host, software must program the new address before completing the status phase of the SetAddress Control Request. + 0 + 7 + read-write + + + DEV_EN + USB device enable. If this bit is set, the HW will start responding on packets for function address DEV_ADDR. + 7 + 1 + read-write + + + SETUP + SETUP token received. If a SETUP token is received and acknowledged by the device, this bit is set. As long as this bit is set all received IN and OUT tokens will be NAKed by HW. SW must clear this bit by writing a one. If this bit is zero, HW will handle the tokens to the CTRL EP0 as indicated by the CTRL EP0 IN and OUT data information programmed by SW. + 8 + 1 + read-write + + + FORCE_NEEDCLK + Forces the NEEDCLK output to always be on: + 9 + 1 + read-write + + + NORMAL + USB_NEEDCLK has normal function. + 0 + + + ALWAYS_ON + USB_NEEDCLK always 1. Clock will not be stopped in case of suspend. + 0x1 + + + + + LPM_SUP + LPM Supported: + 11 + 1 + read-write + + + NO + LPM not supported. + 0 + + + YES + LPM supported. + 0x1 + + + + + INTONNAK_AO + Interrupt on NAK for interrupt and bulk OUT EP + 12 + 1 + read-write + + + DISABLED + Only acknowledged packets generate an interrupt + 0 + + + ENABLED + Both acknowledged and NAKed packets generate interrupts. + 0x1 + + + + + INTONNAK_AI + Interrupt on NAK for interrupt and bulk IN EP + 13 + 1 + read-write + + + DISABLED + Only acknowledged packets generate an interrupt + 0 + + + ENABLED + Both acknowledged and NAKed packets generate interrupts. + 0x1 + + + + + INTONNAK_CO + Interrupt on NAK for control OUT EP + 14 + 1 + read-write + + + DISABLED + Only acknowledged packets generate an interrupt + 0 + + + ENABLED + Both acknowledged and NAKed packets generate interrupts. + 0x1 + + + + + INTONNAK_CI + Interrupt on NAK for control IN EP + 15 + 1 + read-write + + + DISABLED + Only acknowledged packets generate an interrupt + 0 + + + ENABLED + Both acknowledged and NAKed packets generate interrupts. + 0x1 + + + + + DCON + Device status - connect. The connect bit must be set by SW to indicate that the device must signal a connect. The pull-up resistor on USB_DP will be enabled when this bit is set and the VBUSDEBOUNCED bit is one. + 16 + 1 + read-write + + + DSUS + Device status - suspend. The suspend bit indicates the current suspend state. It is set to 1 when the device hasn't seen any activity on its upstream port for more than 3 milliseconds. It is reset to 0 on any activity. When the device is suspended (Suspend bit DSUS = 1) and the software writes a 0 to it, the device will generate a remote wake-up. This will only happen when the device is connected (Connect bit = 1). When the device is not connected or not suspended, a writing a 0 has no effect. Writing a 1 never has an effect. + 17 + 1 + read-write + + + LPM_SUS + Device status - LPM Suspend. This bit represents the current LPM suspend state. It is set to 1 by HW when the device has acknowledged the LPM request from the USB host and the Token Retry Time of 10 ms has elapsed. When the device is in the LPM suspended state (LPM suspend bit = 1) and the software writes a zero to this bit, the device will generate a remote walk-up. Software can only write a zero to this bit when the LPM_REWP bit is set to 1. HW resets this bit when it receives a host initiated resume. HW only updates the LPM_SUS bit when the LPM_SUPP bit is equal to one. + 19 + 1 + read-write + + + LPM_REWP + LPM Remote Wake-up Enabled by USB host. HW sets this bit to one when the bRemoteWake bit in the LPM extended token is set to 1. HW will reset this bit to 0 when it receives the host initiated LPM resume, when a remote wake-up is sent by the device or when a USB bus reset is received. Software can use this bit to check if the remote wake-up feature is enabled by the host for the LPM transaction. + 20 + 1 + read-only + + + DCON_C + Device status - connect change. The Connect Change bit is set when the device's pull-up resistor is disconnected because VBus disappeared. The bit is reset by writing a one to it. + 24 + 1 + read-write + + + DSUS_C + Device status - suspend change. The suspend change bit is set to 1 when the suspend bit toggles. The suspend bit can toggle because: - The device goes in the suspended state - The device is disconnected - The device receives resume signaling on its upstream port. The bit is reset by writing a one to it. + 25 + 1 + read-write + + + DRES_C + Device status - reset change. This bit is set when the device received a bus reset. On a bus reset the device will automatically go to the default state (unconfigured and responding to address 0). The bit is reset by writing a one to it. + 26 + 1 + read-write + + + VBUSDEBOUNCED + This bit indicates if Vbus is detected or not. The bit raises immediately when Vbus becomes high. It drops to zero if Vbus is low for at least 3 ms. If this bit is high and the DCon bit is set, the HW will enable the pull-up resistor to signal a connect. + 28 + 1 + read-only + + + + + INFO + USB Info register + 0x4 + 32 + read-write + 0 + 0x7FFF + + + FRAME_NR + Frame number. This contains the frame number of the last successfully received SOF. In case no SOF was received by the device at the beginning of a frame, the frame number returned is that of the last successfully received SOF. In case the SOF frame number contained a CRC error, the frame number returned will be the corrupted frame number as received by the device. + 0 + 11 + read-only + + + ERR_CODE + The error code which last occurred: + 11 + 4 + read-write + + + NO_ERROR + No error + 0 + + + PID_ENCODING_ERROR + PID encoding error + 0x1 + + + PID_UNKNOWN + PID unknown + 0x2 + + + PACKET_UNEXPECTED + Packet unexpected + 0x3 + + + TOKEN_CRC_ERROR + Token CRC error + 0x4 + + + DATA_CRC_ERROR + Data CRC error + 0x5 + + + TIMEOUT + Time out + 0x6 + + + BABBLE + Babble + 0x7 + + + TRUNCATED_EOP + Truncated EOP + 0x8 + + + SENT_RECEIVED_NAK + Sent/Received NAK + 0x9 + + + SENT_STALL + Sent Stall + 0xA + + + OVERRUN + Overrun + 0xB + + + SENT_EMPTY_PACKET + Sent empty packet + 0xC + + + BITSTUFF_ERROR + Bitstuff error + 0xD + + + SYNC_ERROR + Sync error + 0xE + + + WRONG_DATA_TOGGLE + Wrong data toggle + 0xF + + + + + MINREV + Minor Revision. + 16 + 8 + read-only + + + MAJREV + Major Revision. + 24 + 8 + read-only + + + + + EPLISTSTART + USB EP Command/Status List start address + 0x8 + 32 + read-write + 0 + 0xFFFFFF00 + + + EP_LIST + Start address of the USB EP Command/Status List. + 8 + 24 + read-write + + + + + DATABUFSTART + USB Data buffer start address + 0xC + 32 + read-write + 0 + 0xFFC00000 + + + DA_BUF + Start address of the buffer pointer page where all endpoint data buffers are located. + 22 + 10 + read-write + + + + + LPM + USB Link Power Management register + 0x10 + 32 + read-write + 0 + 0x1FF + + + HIRD_HW + Host Initiated Resume Duration - HW. This is the HIRD value from the last received LPM token + 0 + 4 + read-only + + + HIRD_SW + Host Initiated Resume Duration - SW. This is the time duration required by the USB device system to come out of LPM initiated suspend after receiving the host initiated LPM resume. + 4 + 4 + read-write + + + DATA_PENDING + As long as this bit is set to one and LPM supported bit is set to one, HW will return a NYET handshake on every LPM token it receives. If LPM supported bit is set to one and this bit is zero, HW will return an ACK handshake on every LPM token it receives. If SW has still data pending and LPM is supported, it must set this bit to 1. + 8 + 1 + read-write + + + + + EPSKIP + USB Endpoint skip + 0x14 + 32 + read-write + 0 + 0x3FFFFFFF + + + SKIP + Endpoint skip: Writing 1 to one of these bits, will indicate to HW that it must deactivate the buffer assigned to this endpoint and return control back to software. When HW has deactivated the endpoint, it will clear this bit, but it will not modify the EPINUSE bit. An interrupt will be generated when the Active bit goes from 1 to 0. Note: In case of double-buffering, HW will only clear the Active bit of the buffer indicated by the EPINUSE bit. + 0 + 10 + read-write + + + + + EPINUSE + USB Endpoint Buffer in use + 0x18 + 32 + read-write + 0 + 0x3FC + + + BUF + Buffer in use: This register has one bit per physical endpoint. 0: HW is accessing buffer 0. 1: HW is accessing buffer 1. + 2 + 8 + read-write + + + + + EPBUFCFG + USB Endpoint Buffer Configuration register + 0x1C + 32 + read-write + 0 + 0x3FC + + + BUF_SB + Buffer usage: This register has one bit per physical endpoint. 0: Single-buffer. 1: Double-buffer. If the bit is set to single-buffer (0), it will not toggle the corresponding EPINUSE bit when it clears the active bit. If the bit is set to double-buffer (1), HW will toggle the EPINUSE bit when it clears the Active bit for the buffer. + 2 + 8 + read-write + + + + + INTSTAT + USB interrupt status register + 0x20 + 32 + read-write + 0 + 0xC00003FF + + + EP0OUT + Interrupt status register bit for the Control EP0 OUT direction. This bit will be set if NBytes transitions to zero or the skip bit is set by software or a SETUP packet is successfully received for the control EP0. If the IntOnNAK_CO is set, this bit will also be set when a NAK is transmitted for the Control EP0 OUT direction. Software can clear this bit by writing a one to it. + 0 + 1 + read-write + + + EP0IN + Interrupt status register bit for the Control EP0 IN direction. This bit will be set if NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_CI is set, this bit will also be set when a NAK is transmitted for the Control EP0 IN direction. Software can clear this bit by writing a one to it. + 1 + 1 + read-write + + + EP1OUT + Interrupt status register bit for the EP1 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP1 OUT direction. Software can clear this bit by writing a one to it. + 2 + 1 + read-write + + + EP1IN + Interrupt status register bit for the EP1 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP1 IN direction. Software can clear this bit by writing a one to it. + 3 + 1 + read-write + + + EP2OUT + Interrupt status register bit for the EP2 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP2 OUT direction. Software can clear this bit by writing a one to it. + 4 + 1 + read-write + + + EP2IN + Interrupt status register bit for the EP2 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP2 IN direction. Software can clear this bit by writing a one to it. + 5 + 1 + read-write + + + EP3OUT + Interrupt status register bit for the EP3 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP3 OUT direction. Software can clear this bit by writing a one to it. + 6 + 1 + read-write + + + EP3IN + Interrupt status register bit for the EP3 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP3 IN direction. Software can clear this bit by writing a one to it. + 7 + 1 + read-write + + + EP4OUT + Interrupt status register bit for the EP4 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP4 OUT direction. Software can clear this bit by writing a one to it. + 8 + 1 + read-write + + + EP4IN + Interrupt status register bit for the EP4 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP4 IN direction. Software can clear this bit by writing a one to it. + 9 + 1 + read-write + + + FRAME_INT + Frame interrupt. This bit is set to one every millisecond when the VbusDebounced bit and the DCON bit are set. This bit can be used by software when handling isochronous endpoints. Software can clear this bit by writing a one to it. + 30 + 1 + read-write + + + DEV_INT + Device status interrupt. This bit is set by HW when one of the bits in the Device Status Change register are set. Software can clear this bit by writing a one to it. + 31 + 1 + read-write + + + + + INTEN + USB interrupt enable register + 0x24 + 32 + read-write + 0 + 0xC00003FF + + + EP_INT_EN + If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing bit. + 0 + 10 + read-write + + + FRAME_INT_EN + If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing bit. + 30 + 1 + read-write + + + DEV_INT_EN + If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing bit. + 31 + 1 + read-write + + + + + INTSETSTAT + USB set interrupt status register + 0x28 + 32 + read-write + 0 + 0xC00003FF + + + EP_SET_INT + If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. When this register is read, the same value as the USB interrupt status register is returned. + 0 + 10 + read-write + + + FRAME_SET_INT + If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. When this register is read, the same value as the USB interrupt status register is returned. + 30 + 1 + read-write + + + DEV_SET_INT + If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. When this register is read, the same value as the USB interrupt status register is returned. + 31 + 1 + read-write + + + + + EPTOGGLE + USB Endpoint toggle register + 0x34 + 32 + read-write + 0 + 0x3FF + + + TOGGLE + Endpoint data toggle: This field indicates the current value of the data toggle for the corresponding endpoint. + 0 + 10 + read-write + + + + + + + SCT0 + SCTimer/PWM (SCT) + SCT + 0x40085000 + + 0 + 0x550 + registers + + + SCT0 + 12 + + + + CONFIG + SCT configuration register + 0 + 32 + read-write + 0x1E00 + 0x61FFF + + + UNIFY + SCT operation + 0 + 1 + read-write + + + DUAL_COUNTER + The SCT operates as two 16-bit counters named COUNTER_L and COUNTER_H. + 0 + + + UNIFIED_COUNTER + The SCT operates as a unified 32-bit counter. + 0x1 + + + + + CLKMODE + SCT clock mode + 1 + 2 + read-write + + + SYSTEM_CLOCK_MODE + System Clock Mode. The system clock clocks the entire SCT module including the counter(s) and counter prescalers. + 0 + + + SAMPLED_SYSTEM_CLOCK_MODE + Sampled System Clock Mode. The system clock clocks the SCT module, but the counter and prescalers are only enabled to count when the designated edge is detected on the input selected by the CKSEL field. The minimum pulse width on the selected clock-gate input is 1 bus clock period. This mode is the high-performance, sampled-clock mode. + 0x1 + + + SCT_INPUT_CLOCK_MODE + SCT Input Clock Mode. The input/edge selected by the CKSEL field clocks the SCT module, including the counters and prescalers, after first being synchronized to the system clock. The minimum pulse width on the clock input is 1 bus clock period. This mode is the low-power, sampled-clock mode. + 0x2 + + + ASYNCHRONOUS_MODE + Asynchronous Mode. The entire SCT module is clocked directly by the input/edge selected by the CKSEL field. In this mode, the SCT outputs are switched synchronously to the SCT input clock - not the system clock. The input clock rate must be at least half the system clock rate and can be the same or faster than the system clock. + 0x3 + + + + + CKSEL + SCT clock select. The specific functionality of the designated input/edge is dependent on the CLKMODE bit selection in this register. + 3 + 4 + read-write + + + INPUT_0_RISING_EDGES + Rising edges on input 0. + 0 + + + INPUT_0_FALLING_EDGE + Falling edges on input 0. + 0x1 + + + INPUT_1_RISING_EDGES + Rising edges on input 1. + 0x2 + + + INPUT_1_FALLING_EDGE + Falling edges on input 1. + 0x3 + + + INPUT_2_RISING_EDGES + Rising edges on input 2. + 0x4 + + + INPUT_2_FALLING_EDGE + Falling edges on input 2. + 0x5 + + + INPUT_3_RISING_EDGES + Rising edges on input 3. + 0x6 + + + INPUT_3_FALLING_EDGE + Falling edges on input 3. + 0x7 + + + + + NORELAOD_L + A 1 in this bit prevents the lower match registers from being reloaded from their respective reload registers. Setting this bit eliminates the need to write to the reload registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set. + 7 + 1 + read-write + + + NORELOAD_H + A 1 in this bit prevents the higher match registers from being reloaded from their respective reload registers. Setting this bit eliminates the need to write to the reload registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set. + 8 + 1 + read-write + + + INSYNC + Synchronization for input N (bit 9 = input 0, bit 10 = input 1,, bit 12 = input 3); all other bits are reserved. A 1 in one of these bits subjects the corresponding input to synchronization to the SCT clock, before it is used to create an event. If an input is known to already be synchronous to the SCT clock, this bit may be set to 0 for faster input response. (Note: The SCT clock is the system clock for CKMODEs 0-2. It is the selected, asynchronous SCT input clock for CKMODE3). Note that the INSYNC field only affects inputs used for event generation. It does not apply to the clock input specified in the CKSEL field. + 9 + 4 + read-write + + + AUTOLIMIT_L + A one in this bit causes a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in unidirectional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set. + 17 + 1 + read-write + + + AUTOLIMIT_H + A one in this bit will cause a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in unidirectional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set. + 18 + 1 + read-write + + + + + CTRL + SCT control register + 0x4 + 32 + read-write + 0x40004 + 0x1FFF1FFF + + + DOWN_L + This bit is 1 when the L or unified counter is counting down. Hardware sets this bit when the counter is counting up, counter limit occurs, and BIDIR = 1.Hardware clears this bit when the counter is counting down and a limit condition occurs or when the counter reaches 0. + 0 + 1 + read-write + + + STOP_L + When this bit is 1 and HALT is 0, the L or unified counter does not run, but I/O events related to the counter can occur. If a designated start event occurs, this bit is cleared and counting resumes. + 1 + 1 + read-write + + + HALT_L + When this bit is 1, the L or unified counter does not run and no events can occur. A reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. It is possible to remove the halt condition while keeping the SCT in the stop condition (not running) with a single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set, only software can clear this bit to restore counter operation. This bit is set on reset. + 2 + 1 + read-write + + + CLRCTR_L + Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0. + 3 + 1 + read-write + + + BIDIR_L + L or unified counter direction select + 4 + 1 + read-write + + + UP + Up. The counter counts up to a limit condition, then is cleared to zero. + 0 + + + UP_DOWN + Up-down. The counter counts up to a limit, then counts down to a limit condition or to 0. + 0x1 + + + + + PRE_L + Specifies the factor by which the SCT clock is prescaled to produce the L or unified counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. + 5 + 8 + read-write + + + DOWN_H + This bit is 1 when the H counter is counting down. Hardware sets this bit when the counter is counting, a counter limit condition occurs, and BIDIR is 1. Hardware clears this bit when the counter is counting down and a limit condition occurs or when the counter reaches 0. + 16 + 1 + read-write + + + STOP_H + When this bit is 1 and HALT is 0, the H counter does not, run but I/O events related to the counter can occur. If such an event matches the mask in the Start register, this bit is cleared and counting resumes. + 17 + 1 + read-write + + + HALT_H + When this bit is 1, the H counter does not run and no events can occur. A reset sets this bit. When the HALT_H bit is one, the STOP_H bit is cleared. It is possible to remove the halt condition while keeping the SCT in the stop condition (not running) with a single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set, this bit can only be cleared by software to restore counter operation. This bit is set on reset. + 18 + 1 + read-write + + + CLRCTR_H + Writing a 1 to this bit clears the H counter. This bit always reads as 0. + 19 + 1 + read-write + + + BIDIR_H + Direction select + 20 + 1 + read-write + + + UP + The H counter counts up to its limit condition, then is cleared to zero. + 0 + + + UP_DOWN + The H counter counts up to its limit, then counts down to a limit condition or to 0. + 0x1 + + + + + PRE_H + Specifies the factor by which the SCT clock is prescaled to produce the H counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. + 21 + 8 + read-write + + + + + LIMIT + SCT limit event select register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + LIMMSK_L + If bit n is one, event n is used as a counter limit for the L or unified counter (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. + 0 + 16 + read-write + + + LIMMSK_H + If bit n is one, event n is used as a counter limit for the H counter (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT. + 16 + 16 + read-write + + + + + HALT + SCT halt event select register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + HALTMSK_L + If bit n is one, event n sets the HALT_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. + 0 + 16 + read-write + + + HALTMSK_H + If bit n is one, event n sets the HALT_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT. + 16 + 16 + read-write + + + + + STOP + SCT stop event select register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + STOPMSK_L + If bit n is one, event n sets the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. + 0 + 16 + read-write + + + STOPMSK_H + If bit n is one, event n sets the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT. + 16 + 16 + read-write + + + + + START + SCT start event select register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + STARTMSK_L + If bit n is one, event n clears the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. + 0 + 16 + read-write + + + STARTMSK_H + If bit n is one, event n clears the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT. + 16 + 16 + read-write + + + + + COUNT + SCT counter register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + CTR_L + When UNIFY = 0, read or write the 16-bit L counter value. When UNIFY = 1, read or write the lower 16 bits of the 32-bit unified counter. + 0 + 16 + read-write + + + CTR_H + When UNIFY = 0, read or write the 16-bit H counter value. When UNIFY = 1, read or write the upper 16 bits of the 32-bit unified counter. + 16 + 16 + read-write + + + + + STATE + SCT state register + 0x44 + 32 + read-write + 0 + 0x1F001F + + + STATE_L + State variable. + 0 + 5 + read-write + + + STATE_H + State variable. + 16 + 5 + read-write + + + + + INPUT + SCT input register + 0x48 + 32 + read-only + 0 + 0xFFFFFFFF + + + AIN0 + Input 0 state. Input 0 state on the last SCT clock edge. + 0 + 1 + read-only + + + AIN1 + Input 1 state. Input 1 state on the last SCT clock edge. + 1 + 1 + read-only + + + AIN2 + Input 2 state. Input 2 state on the last SCT clock edge. + 2 + 1 + read-only + + + AIN3 + Input 3 state. Input 3 state on the last SCT clock edge. + 3 + 1 + read-only + + + AIN4 + Input 4 state. Input 4 state on the last SCT clock edge. + 4 + 1 + read-only + + + AIN5 + Input 5 state. Input 5 state on the last SCT clock edge. + 5 + 1 + read-only + + + AIN6 + Input 6 state. Input 6 state on the last SCT clock edge. + 6 + 1 + read-only + + + AIN7 + Input 7 state. Input 7 state on the last SCT clock edge. + 7 + 1 + read-only + + + AIN8 + Input 8 state. Input 8 state on the last SCT clock edge. + 8 + 1 + read-only + + + AIN9 + Input 9 state. Input 9 state on the last SCT clock edge. + 9 + 1 + read-only + + + AIN10 + Input 10 state. Input 10 state on the last SCT clock edge. + 10 + 1 + read-only + + + AIN11 + Input 11 state. Input 11 state on the last SCT clock edge. + 11 + 1 + read-only + + + AIN12 + Input 12 state. Input 12 state on the last SCT clock edge. + 12 + 1 + read-only + + + AIN13 + Input 13 state. Input 13 state on the last SCT clock edge. + 13 + 1 + read-only + + + AIN14 + Input 14 state. Input 14 state on the last SCT clock edge. + 14 + 1 + read-only + + + AIN15 + Input 15 state. Input 15 state on the last SCT clock edge. + 15 + 1 + read-only + + + SIN0 + Input 0 state. Input 0 state following the synchronization specified by INSYNC. + 16 + 1 + read-only + + + SIN1 + Input 1 state. Input 1 state following the synchronization specified by INSYNC. + 17 + 1 + read-only + + + SIN2 + Input 2 state. Input 2 state following the synchronization specified by INSYNC. + 18 + 1 + read-only + + + SIN3 + Input 3 state. Input 3 state following the synchronization specified by INSYNC. + 19 + 1 + read-only + + + SIN4 + Input 4 state. Input 4 state following the synchronization specified by INSYNC. + 20 + 1 + read-only + + + SIN5 + Input 5 state. Input 5 state following the synchronization specified by INSYNC. + 21 + 1 + read-only + + + SIN6 + Input 6 state. Input 6 state following the synchronization specified by INSYNC. + 22 + 1 + read-only + + + SIN7 + Input 7 state. Input 7 state following the synchronization specified by INSYNC. + 23 + 1 + read-only + + + SIN8 + Input 8 state. Input 8 state following the synchronization specified by INSYNC. + 24 + 1 + read-only + + + SIN9 + Input 9 state. Input 9 state following the synchronization specified by INSYNC. + 25 + 1 + read-only + + + SIN10 + Input 10 state. Input 10 state following the synchronization specified by INSYNC. + 26 + 1 + read-only + + + SIN11 + Input 11 state. Input 11 state following the synchronization specified by INSYNC. + 27 + 1 + read-only + + + SIN12 + Input 12 state. Input 12 state following the synchronization specified by INSYNC. + 28 + 1 + read-only + + + SIN13 + Input 13 state. Input 13 state following the synchronization specified by INSYNC. + 29 + 1 + read-only + + + SIN14 + Input 14 state. Input 14 state following the synchronization specified by INSYNC. + 30 + 1 + read-only + + + SIN15 + Input 15 state. Input 15 state following the synchronization specified by INSYNC. + 31 + 1 + read-only + + + + + REGMODE + SCT match/capture mode register + 0x4C + 32 + read-write + 0 + 0xFFFFFFFF + + + REGMOD_L + Each bit controls one match/capture register (register 0 = bit 0, register 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. 0 = register operates as match register. 1 = register operates as capture register. + 0 + 16 + read-write + + + REGMOD_H + Each bit controls one match/capture register (register 0 = bit 16, register 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. 0 = register operates as match registers. 1 = register operates as capture registers. + 16 + 16 + read-write + + + + + OUTPUT + SCT output register + 0x50 + 32 + read-write + 0 + 0xFFFF + + + OUT + Writing a 1 to bit n forces the corresponding output HIGH. Writing a 0 forces the corresponding output LOW (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of outputs in this SCT. + 0 + 16 + read-write + + + + + OUTPUTDIRCTRL + SCT output counter direction control register + 0x54 + 32 + read-write + 0 + 0xFFFFFFFF + + + SETCLR0 + Set/clear operation on output 0. Value 0x3 is reserved. Do not program this value. + 0 + 2 + read-write + + + INDEPENDENT + Set and clear do not depend on the direction of any counter. + 0 + + + L_REVERSED + Set and clear are reversed when counter L or the unified counter is counting down. + 0x1 + + + H_REVERSED + Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + 0x2 + + + + + SETCLR1 + Set/clear operation on output 1. Value 0x3 is reserved. Do not program this value. + 2 + 2 + read-write + + + INDEPENDENT + Set and clear do not depend on the direction of any counter. + 0 + + + L_REVERSED + Set and clear are reversed when counter L or the unified counter is counting down. + 0x1 + + + H_REVERSED + Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + 0x2 + + + + + SETCLR2 + Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value. + 4 + 2 + read-write + + + INDEPENDENT + Set and clear do not depend on the direction of any counter. + 0 + + + L_REVERSED + Set and clear are reversed when counter L or the unified counter is counting down. + 0x1 + + + H_REVERSED + Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + 0x2 + + + + + SETCLR3 + Set/clear operation on output 3. Value 0x3 is reserved. Do not program this value. + 6 + 2 + read-write + + + INDEPENDENT + Set and clear do not depend on the direction of any counter. + 0 + + + L_REVERSED + Set and clear are reversed when counter L or the unified counter is counting down. + 0x1 + + + H_REVERSED + Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + 0x2 + + + + + SETCLR4 + Set/clear operation on output 4. Value 0x3 is reserved. Do not program this value. + 8 + 2 + read-write + + + INDEPENDENT + Set and clear do not depend on the direction of any counter. + 0 + + + L_REVERSED + Set and clear are reversed when counter L or the unified counter is counting down. + 0x1 + + + H_REVERSED + Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + 0x2 + + + + + SETCLR5 + Set/clear operation on output 5. Value 0x3 is reserved. Do not program this value. + 10 + 2 + read-write + + + INDEPENDENT + Set and clear do not depend on the direction of any counter. + 0 + + + L_REVERSED + Set and clear are reversed when counter L or the unified counter is counting down. + 0x1 + + + H_REVERSED + Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + 0x2 + + + + + SETCLR6 + Set/clear operation on output 6. Value 0x3 is reserved. Do not program this value. + 12 + 2 + read-write + + + INDEPENDENT + Set and clear do not depend on the direction of any counter. + 0 + + + L_REVERSED + Set and clear are reversed when counter L or the unified counter is counting down. + 0x1 + + + H_REVERSED + Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + 0x2 + + + + + SETCLR7 + Set/clear operation on output 7. Value 0x3 is reserved. Do not program this value. + 14 + 2 + read-write + + + INDEPENDENT + Set and clear do not depend on the direction of any counter. + 0 + + + L_REVERSED + Set and clear are reversed when counter L or the unified counter is counting down. + 0x1 + + + H_REVERSED + Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + 0x2 + + + + + SETCLR8 + Set/clear operation on output 8. Value 0x3 is reserved. Do not program this value. + 16 + 2 + read-write + + + INDEPENDENT + Set and clear do not depend on the direction of any counter. + 0 + + + L_REVERSED + Set and clear are reversed when counter L or the unified counter is counting down. + 0x1 + + + H_REVERSED + Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + 0x2 + + + + + SETCLR9 + Set/clear operation on output 9. Value 0x3 is reserved. Do not program this value. + 18 + 2 + read-write + + + INDEPENDENT + Set and clear do not depend on the direction of any counter. + 0 + + + L_REVERSED + Set and clear are reversed when counter L or the unified counter is counting down. + 0x1 + + + H_REVERSED + Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + 0x2 + + + + + SETCLR10 + Set/clear operation on output 10. Value 0x3 is reserved. Do not program this value. + 20 + 2 + read-write + + + INDEPENDENT + Set and clear do not depend on the direction of any counter. + 0 + + + L_REVERSED + Set and clear are reversed when counter L or the unified counter is counting down. + 0x1 + + + H_REVERSED + Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + 0x2 + + + + + SETCLR11 + Set/clear operation on output 11. Value 0x3 is reserved. Do not program this value. + 22 + 2 + read-write + + + INDEPENDENT + Set and clear do not depend on the direction of any counter. + 0 + + + L_REVERSED + Set and clear are reversed when counter L or the unified counter is counting down. + 0x1 + + + H_REVERSED + Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + 0x2 + + + + + SETCLR12 + Set/clear operation on output 12. Value 0x3 is reserved. Do not program this value. + 24 + 2 + read-write + + + INDEPENDENT + Set and clear do not depend on the direction of any counter. + 0 + + + L_REVERSED + Set and clear are reversed when counter L or the unified counter is counting down. + 0x1 + + + H_REVERSED + Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + 0x2 + + + + + SETCLR13 + Set/clear operation on output 13. Value 0x3 is reserved. Do not program this value. + 26 + 2 + read-write + + + INDEPENDENT + Set and clear do not depend on the direction of any counter. + 0 + + + L_REVERSED + Set and clear are reversed when counter L or the unified counter is counting down. + 0x1 + + + H_REVERSED + Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + 0x2 + + + + + SETCLR14 + Set/clear operation on output 14. Value 0x3 is reserved. Do not program this value. + 28 + 2 + read-write + + + INDEPENDENT + Set and clear do not depend on the direction of any counter. + 0 + + + L_REVERSED + Set and clear are reversed when counter L or the unified counter is counting down. + 0x1 + + + H_REVERSED + Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + 0x2 + + + + + SETCLR15 + Set/clear operation on output 15. Value 0x3 is reserved. Do not program this value. + 30 + 2 + read-write + + + INDEPENDENT + Set and clear do not depend on the direction of any counter. + 0 + + + L_REVERSED + Set and clear are reversed when counter L or the unified counter is counting down. + 0x1 + + + H_REVERSED + Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + 0x2 + + + + + + + RES + SCT conflict resolution register + 0x58 + 32 + read-write + 0 + 0xFFFFFFFF + + + O0RES + Effect of simultaneous set and clear on output 0. + 0 + 2 + read-write + + + NO_CHANGE + No change. + 0 + + + SET + Set output (or clear based on the SETCLR0 field in the OUTPUTDIRCTRL register). + 0x1 + + + CLEAR + Clear output (or set based on the SETCLR0 field). + 0x2 + + + TOGGLE_OUTPUT + Toggle output. + 0x3 + + + + + O1RES + Effect of simultaneous set and clear on output 1. + 2 + 2 + read-write + + + NO_CHANGE + No change. + 0 + + + SET + Set output (or clear based on the SETCLR1 field in the OUTPUTDIRCTRL register). + 0x1 + + + CLEAR + Clear output (or set based on the SETCLR1 field). + 0x2 + + + TOGGLE_OUTPUT + Toggle output. + 0x3 + + + + + O2RES + Effect of simultaneous set and clear on output 2. + 4 + 2 + read-write + + + NO_CHANGE + No change. + 0 + + + SET + Set output (or clear based on the SETCLR2 field in the OUTPUTDIRCTRL register). + 0x1 + + + CLEAR + Clear output n (or set based on the SETCLR2 field). + 0x2 + + + TOGGLE_OUTPUT + Toggle output. + 0x3 + + + + + O3RES + Effect of simultaneous set and clear on output 3. + 6 + 2 + read-write + + + NO_CHANGE + No change. + 0 + + + SET + Set output (or clear based on the SETCLR3 field in the OUTPUTDIRCTRL register). + 0x1 + + + CLEAR + Clear output (or set based on the SETCLR3 field). + 0x2 + + + TOGGLE_OUTPUT + Toggle output. + 0x3 + + + + + O4RES + Effect of simultaneous set and clear on output 4. + 8 + 2 + read-write + + + NO_CHANGE + No change. + 0 + + + SET + Set output (or clear based on the SETCLR4 field in the OUTPUTDIRCTRL register). + 0x1 + + + CLEAR + Clear output (or set based on the SETCLR4 field). + 0x2 + + + TOGGLE_OUTPUT + Toggle output. + 0x3 + + + + + O5RES + Effect of simultaneous set and clear on output 5. + 10 + 2 + read-write + + + NO_CHANGE + No change. + 0 + + + SET + Set output (or clear based on the SETCLR5 field in the OUTPUTDIRCTRL register). + 0x1 + + + CLEAR + Clear output (or set based on the SETCLR5 field). + 0x2 + + + TOGGLE_OUTPUT + Toggle output. + 0x3 + + + + + O6RES + Effect of simultaneous set and clear on output 6. + 12 + 2 + read-write + + + NO_CHANGE + No change. + 0 + + + SET + Set output (or clear based on the SETCLR6 field in the OUTPUTDIRCTRL register). + 0x1 + + + CLEAR + Clear output (or set based on the SETCLR6 field). + 0x2 + + + TOGGLE_OUTPUT + Toggle output. + 0x3 + + + + + O7RES + Effect of simultaneous set and clear on output 7. + 14 + 2 + read-write + + + NO_CHANGE + No change. + 0 + + + SET + Set output (or clear based on the SETCLR7 field in the OUTPUTDIRCTRL register). + 0x1 + + + CLEAR + Clear output n (or set based on the SETCLR7 field). + 0x2 + + + TOGGLE_OUTPUT + Toggle output. + 0x3 + + + + + O8RES + Effect of simultaneous set and clear on output 8. + 16 + 2 + read-write + + + NO_CHANGE + No change. + 0 + + + SET + Set output (or clear based on the SETCLR8 field in the OUTPUTDIRCTRL register). + 0x1 + + + CLEAR + Clear output (or set based on the SETCLR8 field). + 0x2 + + + TOGGLE_OUTPUT + Toggle output. + 0x3 + + + + + O9RES + Effect of simultaneous set and clear on output 9. + 18 + 2 + read-write + + + NO_CHANGE + No change. + 0 + + + SET + Set output (or clear based on the SETCLR9 field in the OUTPUTDIRCTRL register). + 0x1 + + + CLEAR + Clear output (or set based on the SETCLR9 field). + 0x2 + + + TOGGLE_OUTPUT + Toggle output. + 0x3 + + + + + O10RES + Effect of simultaneous set and clear on output 10. + 20 + 2 + read-write + + + NO_CHANGE + No change. + 0 + + + SET + Set output (or clear based on the SETCLR10 field in the OUTPUTDIRCTRL register). + 0x1 + + + CLEAR + Clear output (or set based on the SETCLR10 field). + 0x2 + + + TOGGLE_OUTPUT + Toggle output. + 0x3 + + + + + O11RES + Effect of simultaneous set and clear on output 11. + 22 + 2 + read-write + + + NO_CHANGE + No change. + 0 + + + SET + Set output (or clear based on the SETCLR11 field in the OUTPUTDIRCTRL register). + 0x1 + + + CLEAR + Clear output (or set based on the SETCLR11 field). + 0x2 + + + TOGGLE_OUTPUT + Toggle output. + 0x3 + + + + + O12RES + Effect of simultaneous set and clear on output 12. + 24 + 2 + read-write + + + NO_CHANGE + No change. + 0 + + + SET + Set output (or clear based on the SETCLR12 field in the OUTPUTDIRCTRL register). + 0x1 + + + CLEAR + Clear output (or set based on the SETCLR12 field). + 0x2 + + + TOGGLE_OUTPUT + Toggle output. + 0x3 + + + + + O13RES + Effect of simultaneous set and clear on output 13. + 26 + 2 + read-write + + + NO_CHANGE + No change. + 0 + + + SET + Set output (or clear based on the SETCLR13 field in the OUTPUTDIRCTRL register). + 0x1 + + + CLEAR + Clear output (or set based on the SETCLR13 field). + 0x2 + + + TOGGLE_OUTPUT + Toggle output. + 0x3 + + + + + O14RES + Effect of simultaneous set and clear on output 14. + 28 + 2 + read-write + + + NO_CHANGE + No change. + 0 + + + SET + Set output (or clear based on the SETCLR14 field in the OUTPUTDIRCTRL register). + 0x1 + + + CLEAR + Clear output (or set based on the SETCLR14 field). + 0x2 + + + TOGGLE_OUTPUT + Toggle output. + 0x3 + + + + + O15RES + Effect of simultaneous set and clear on output 15. + 30 + 2 + read-write + + + NO_CHANGE + No change. + 0 + + + SET + Set output (or clear based on the SETCLR15 field in the OUTPUTDIRCTRL register). + 0x1 + + + CLEAR + Clear output (or set based on the SETCLR15 field). + 0x2 + + + TOGGLE_OUTPUT + Toggle output. + 0x3 + + + + + + + DMA0REQUEST + SCT DMA request 0 register + 0x5C + 32 + read-write + 0 + 0xC000FFFF + + + DEV_0 + If bit n is one, event n triggers DMA request 0 (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. + 0 + 16 + read-write + + + DRL0 + A 1 in this bit triggers DMA request 0 when it loads the MATCH_L/Unified registers from the RELOAD_L/Unified registers. + 30 + 1 + read-write + + + DRQ0 + This read-only bit indicates the state of DMA Request 0. Note that if the related DMA channel is enabled and properly set up, it is unlikely that software will see this flag, it will be cleared rapidly by the DMA service. The flag remaining set could point to an issue with DMA setup. + 31 + 1 + read-write + + + + + DMA1REQUEST + SCT DMA request 1 register + 0x60 + 32 + read-write + 0 + 0xC000FFFF + + + DEV_1 + If bit n is one, event n triggers DMA request 1 (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. + 0 + 16 + read-write + + + DRL1 + A 1 in this bit triggers DMA request 1 when it loads the Match L/Unified registers from the Reload L/Unified registers. + 30 + 1 + read-write + + + DRQ1 + This read-only bit indicates the state of DMA Request 1. Note that if the related DMA channel is enabled and properly set up, it is unlikely that software will see this flag, it will be cleared rapidly by the DMA service. The flag remaining set could point to an issue with DMA setup. + 31 + 1 + read-write + + + + + EVEN + SCT event interrupt enable register + 0xF0 + 32 + read-write + 0 + 0xFFFF + + + IEN + The SCT requests an interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. + 0 + 16 + read-write + + + + + EVFLAG + SCT event flag register + 0xF4 + 32 + read-write + 0 + 0xFFFF + + + FLAG + Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. + 0 + 16 + read-write + + + + + CONEN + SCT conflict interrupt enable register + 0xF8 + 32 + read-write + 0 + 0xFFFF + + + NCEN + The SCT requests an interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of outputs in this SCT. + 0 + 16 + read-write + + + + + CONFLAG + SCT conflict flag register + 0xFC + 32 + read-write + 0 + 0xC000FFFF + + + NCFLAG + Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of outputs in this SCT. + 0 + 16 + read-write + + + BUSERRL + The most recent bus error from this SCT involved writing CTR L/Unified, STATE L/Unified, MATCH L/Unified, or the Output register when the L/U counter was not halted. A word write to certain L and H registers can be half successful and half unsuccessful. + 30 + 1 + read-write + + + BUSERRH + The most recent bus error from this SCT involved writing CTR H, STATE H, MATCH H, or the Output register when the H counter was not halted. + 31 + 1 + read-write + + + + + SCTCAP0 + SCT capture register of capture channel + CAP_MATCH + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPn_L + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. + 0 + 16 + read-write + + + CAPn_H + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. + 16 + 16 + read-write + + + + + SCTMATCH0 + SCT match value register of match channels + CAP_MATCH + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + MATCHn_L + When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. + 0 + 16 + read-write + + + MATCHn_H + When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. + 16 + 16 + read-write + + + + + SCTCAP1 + SCT capture register of capture channel + CAP_MATCH + 0x104 + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPn_L + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. + 0 + 16 + read-write + + + CAPn_H + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. + 16 + 16 + read-write + + + + + SCTMATCH1 + SCT match value register of match channels + CAP_MATCH + 0x104 + 32 + read-write + 0 + 0xFFFFFFFF + + + MATCHn_L + When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. + 0 + 16 + read-write + + + MATCHn_H + When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. + 16 + 16 + read-write + + + + + SCTCAP2 + SCT capture register of capture channel + CAP_MATCH + 0x108 + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPn_L + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. + 0 + 16 + read-write + + + CAPn_H + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. + 16 + 16 + read-write + + + + + SCTMATCH2 + SCT match value register of match channels + CAP_MATCH + 0x108 + 32 + read-write + 0 + 0xFFFFFFFF + + + MATCHn_L + When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. + 0 + 16 + read-write + + + MATCHn_H + When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. + 16 + 16 + read-write + + + + + SCTCAP3 + SCT capture register of capture channel + CAP_MATCH + 0x10C + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPn_L + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. + 0 + 16 + read-write + + + CAPn_H + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. + 16 + 16 + read-write + + + + + SCTMATCH3 + SCT match value register of match channels + CAP_MATCH + 0x10C + 32 + read-write + 0 + 0xFFFFFFFF + + + MATCHn_L + When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. + 0 + 16 + read-write + + + MATCHn_H + When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. + 16 + 16 + read-write + + + + + SCTCAP4 + SCT capture register of capture channel + CAP_MATCH + 0x110 + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPn_L + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. + 0 + 16 + read-write + + + CAPn_H + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. + 16 + 16 + read-write + + + + + SCTMATCH4 + SCT match value register of match channels + CAP_MATCH + 0x110 + 32 + read-write + 0 + 0xFFFFFFFF + + + MATCHn_L + When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. + 0 + 16 + read-write + + + MATCHn_H + When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. + 16 + 16 + read-write + + + + + SCTCAP5 + SCT capture register of capture channel + CAP_MATCH + 0x114 + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPn_L + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. + 0 + 16 + read-write + + + CAPn_H + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. + 16 + 16 + read-write + + + + + SCTMATCH5 + SCT match value register of match channels + CAP_MATCH + 0x114 + 32 + read-write + 0 + 0xFFFFFFFF + + + MATCHn_L + When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. + 0 + 16 + read-write + + + MATCHn_H + When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. + 16 + 16 + read-write + + + + + SCTCAP6 + SCT capture register of capture channel + CAP_MATCH + 0x118 + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPn_L + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. + 0 + 16 + read-write + + + CAPn_H + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. + 16 + 16 + read-write + + + + + SCTMATCH6 + SCT match value register of match channels + CAP_MATCH + 0x118 + 32 + read-write + 0 + 0xFFFFFFFF + + + MATCHn_L + When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. + 0 + 16 + read-write + + + MATCHn_H + When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. + 16 + 16 + read-write + + + + + SCTCAP7 + SCT capture register of capture channel + CAP_MATCH + 0x11C + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPn_L + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. + 0 + 16 + read-write + + + CAPn_H + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. + 16 + 16 + read-write + + + + + SCTMATCH7 + SCT match value register of match channels + CAP_MATCH + 0x11C + 32 + read-write + 0 + 0xFFFFFFFF + + + MATCHn_L + When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. + 0 + 16 + read-write + + + MATCHn_H + When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. + 16 + 16 + read-write + + + + + SCTCAP8 + SCT capture register of capture channel + CAP_MATCH + 0x120 + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPn_L + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. + 0 + 16 + read-write + + + CAPn_H + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. + 16 + 16 + read-write + + + + + SCTMATCH8 + SCT match value register of match channels + CAP_MATCH + 0x120 + 32 + read-write + 0 + 0xFFFFFFFF + + + MATCHn_L + When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. + 0 + 16 + read-write + + + MATCHn_H + When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. + 16 + 16 + read-write + + + + + SCTCAP9 + SCT capture register of capture channel + CAP_MATCH + 0x124 + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPn_L + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. + 0 + 16 + read-write + + + CAPn_H + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. + 16 + 16 + read-write + + + + + SCTMATCH9 + SCT match value register of match channels + CAP_MATCH + 0x124 + 32 + read-write + 0 + 0xFFFFFFFF + + + MATCHn_L + When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. + 0 + 16 + read-write + + + MATCHn_H + When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. + 16 + 16 + read-write + + + + + SCTCAP10 + SCT capture register of capture channel + CAP_MATCH + 0x128 + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPn_L + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. + 0 + 16 + read-write + + + CAPn_H + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. + 16 + 16 + read-write + + + + + SCTMATCH10 + SCT match value register of match channels + CAP_MATCH + 0x128 + 32 + read-write + 0 + 0xFFFFFFFF + + + MATCHn_L + When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. + 0 + 16 + read-write + + + MATCHn_H + When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. + 16 + 16 + read-write + + + + + SCTCAP11 + SCT capture register of capture channel + CAP_MATCH + 0x12C + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPn_L + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. + 0 + 16 + read-write + + + CAPn_H + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. + 16 + 16 + read-write + + + + + SCTMATCH11 + SCT match value register of match channels + CAP_MATCH + 0x12C + 32 + read-write + 0 + 0xFFFFFFFF + + + MATCHn_L + When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. + 0 + 16 + read-write + + + MATCHn_H + When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. + 16 + 16 + read-write + + + + + SCTCAP12 + SCT capture register of capture channel + CAP_MATCH + 0x130 + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPn_L + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. + 0 + 16 + read-write + + + CAPn_H + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. + 16 + 16 + read-write + + + + + SCTMATCH12 + SCT match value register of match channels + CAP_MATCH + 0x130 + 32 + read-write + 0 + 0xFFFFFFFF + + + MATCHn_L + When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. + 0 + 16 + read-write + + + MATCHn_H + When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. + 16 + 16 + read-write + + + + + SCTCAP13 + SCT capture register of capture channel + CAP_MATCH + 0x134 + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPn_L + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. + 0 + 16 + read-write + + + CAPn_H + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. + 16 + 16 + read-write + + + + + SCTMATCH13 + SCT match value register of match channels + CAP_MATCH + 0x134 + 32 + read-write + 0 + 0xFFFFFFFF + + + MATCHn_L + When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. + 0 + 16 + read-write + + + MATCHn_H + When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. + 16 + 16 + read-write + + + + + SCTCAP14 + SCT capture register of capture channel + CAP_MATCH + 0x138 + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPn_L + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. + 0 + 16 + read-write + + + CAPn_H + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. + 16 + 16 + read-write + + + + + SCTMATCH14 + SCT match value register of match channels + CAP_MATCH + 0x138 + 32 + read-write + 0 + 0xFFFFFFFF + + + MATCHn_L + When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. + 0 + 16 + read-write + + + MATCHn_H + When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. + 16 + 16 + read-write + + + + + SCTCAP15 + SCT capture register of capture channel + CAP_MATCH + 0x13C + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPn_L + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. + 0 + 16 + read-write + + + CAPn_H + When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. + 16 + 16 + read-write + + + + + SCTMATCH15 + SCT match value register of match channels + CAP_MATCH + 0x13C + 32 + read-write + 0 + 0xFFFFFFFF + + + MATCHn_L + When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. + 0 + 16 + read-write + + + MATCHn_H + When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. + 16 + 16 + read-write + + + + + SCTCAPCTRL0 + SCT capture control register + CAPCTRL_MATCHREL + 0x200 + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPCONn_L + If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. + 0 + 16 + read-write + + + CAPCONn_H + If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. + 16 + 16 + read-write + + + + + SCTMATCHREL0 + SCT match reload value register + CAPCTRL_MATCHREL + 0x200 + 32 + read-write + 0 + 0xFFFFFFFF + + + RELOADn_L + When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. + 0 + 16 + read-write + + + RELOADn_H + When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. + 16 + 16 + read-write + + + + + SCTCAPCTRL1 + SCT capture control register + CAPCTRL_MATCHREL + 0x204 + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPCONn_L + If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. + 0 + 16 + read-write + + + CAPCONn_H + If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. + 16 + 16 + read-write + + + + + SCTMATCHREL1 + SCT match reload value register + CAPCTRL_MATCHREL + 0x204 + 32 + read-write + 0 + 0xFFFFFFFF + + + RELOADn_L + When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. + 0 + 16 + read-write + + + RELOADn_H + When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. + 16 + 16 + read-write + + + + + SCTCAPCTRL2 + SCT capture control register + CAPCTRL_MATCHREL + 0x208 + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPCONn_L + If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. + 0 + 16 + read-write + + + CAPCONn_H + If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. + 16 + 16 + read-write + + + + + SCTMATCHREL2 + SCT match reload value register + CAPCTRL_MATCHREL + 0x208 + 32 + read-write + 0 + 0xFFFFFFFF + + + RELOADn_L + When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. + 0 + 16 + read-write + + + RELOADn_H + When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. + 16 + 16 + read-write + + + + + SCTCAPCTRL3 + SCT capture control register + CAPCTRL_MATCHREL + 0x20C + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPCONn_L + If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. + 0 + 16 + read-write + + + CAPCONn_H + If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. + 16 + 16 + read-write + + + + + SCTMATCHREL3 + SCT match reload value register + CAPCTRL_MATCHREL + 0x20C + 32 + read-write + 0 + 0xFFFFFFFF + + + RELOADn_L + When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. + 0 + 16 + read-write + + + RELOADn_H + When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. + 16 + 16 + read-write + + + + + SCTCAPCTRL4 + SCT capture control register + CAPCTRL_MATCHREL + 0x210 + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPCONn_L + If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. + 0 + 16 + read-write + + + CAPCONn_H + If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. + 16 + 16 + read-write + + + + + SCTMATCHREL4 + SCT match reload value register + CAPCTRL_MATCHREL + 0x210 + 32 + read-write + 0 + 0xFFFFFFFF + + + RELOADn_L + When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. + 0 + 16 + read-write + + + RELOADn_H + When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. + 16 + 16 + read-write + + + + + SCTCAPCTRL5 + SCT capture control register + CAPCTRL_MATCHREL + 0x214 + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPCONn_L + If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. + 0 + 16 + read-write + + + CAPCONn_H + If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. + 16 + 16 + read-write + + + + + SCTMATCHREL5 + SCT match reload value register + CAPCTRL_MATCHREL + 0x214 + 32 + read-write + 0 + 0xFFFFFFFF + + + RELOADn_L + When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. + 0 + 16 + read-write + + + RELOADn_H + When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. + 16 + 16 + read-write + + + + + SCTCAPCTRL6 + SCT capture control register + CAPCTRL_MATCHREL + 0x218 + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPCONn_L + If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. + 0 + 16 + read-write + + + CAPCONn_H + If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. + 16 + 16 + read-write + + + + + SCTMATCHREL6 + SCT match reload value register + CAPCTRL_MATCHREL + 0x218 + 32 + read-write + 0 + 0xFFFFFFFF + + + RELOADn_L + When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. + 0 + 16 + read-write + + + RELOADn_H + When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. + 16 + 16 + read-write + + + + + SCTCAPCTRL7 + SCT capture control register + CAPCTRL_MATCHREL + 0x21C + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPCONn_L + If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. + 0 + 16 + read-write + + + CAPCONn_H + If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. + 16 + 16 + read-write + + + + + SCTMATCHREL7 + SCT match reload value register + CAPCTRL_MATCHREL + 0x21C + 32 + read-write + 0 + 0xFFFFFFFF + + + RELOADn_L + When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. + 0 + 16 + read-write + + + RELOADn_H + When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. + 16 + 16 + read-write + + + + + SCTCAPCTRL8 + SCT capture control register + CAPCTRL_MATCHREL + 0x220 + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPCONn_L + If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. + 0 + 16 + read-write + + + CAPCONn_H + If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. + 16 + 16 + read-write + + + + + SCTMATCHREL8 + SCT match reload value register + CAPCTRL_MATCHREL + 0x220 + 32 + read-write + 0 + 0xFFFFFFFF + + + RELOADn_L + When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. + 0 + 16 + read-write + + + RELOADn_H + When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. + 16 + 16 + read-write + + + + + SCTCAPCTRL9 + SCT capture control register + CAPCTRL_MATCHREL + 0x224 + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPCONn_L + If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. + 0 + 16 + read-write + + + CAPCONn_H + If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. + 16 + 16 + read-write + + + + + SCTMATCHREL9 + SCT match reload value register + CAPCTRL_MATCHREL + 0x224 + 32 + read-write + 0 + 0xFFFFFFFF + + + RELOADn_L + When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. + 0 + 16 + read-write + + + RELOADn_H + When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. + 16 + 16 + read-write + + + + + SCTCAPCTRL10 + SCT capture control register + CAPCTRL_MATCHREL + 0x228 + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPCONn_L + If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. + 0 + 16 + read-write + + + CAPCONn_H + If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. + 16 + 16 + read-write + + + + + SCTMATCHREL10 + SCT match reload value register + CAPCTRL_MATCHREL + 0x228 + 32 + read-write + 0 + 0xFFFFFFFF + + + RELOADn_L + When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. + 0 + 16 + read-write + + + RELOADn_H + When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. + 16 + 16 + read-write + + + + + SCTCAPCTRL11 + SCT capture control register + CAPCTRL_MATCHREL + 0x22C + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPCONn_L + If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. + 0 + 16 + read-write + + + CAPCONn_H + If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. + 16 + 16 + read-write + + + + + SCTMATCHREL11 + SCT match reload value register + CAPCTRL_MATCHREL + 0x22C + 32 + read-write + 0 + 0xFFFFFFFF + + + RELOADn_L + When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. + 0 + 16 + read-write + + + RELOADn_H + When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. + 16 + 16 + read-write + + + + + SCTCAPCTRL12 + SCT capture control register + CAPCTRL_MATCHREL + 0x230 + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPCONn_L + If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. + 0 + 16 + read-write + + + CAPCONn_H + If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. + 16 + 16 + read-write + + + + + SCTMATCHREL12 + SCT match reload value register + CAPCTRL_MATCHREL + 0x230 + 32 + read-write + 0 + 0xFFFFFFFF + + + RELOADn_L + When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. + 0 + 16 + read-write + + + RELOADn_H + When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. + 16 + 16 + read-write + + + + + SCTCAPCTRL13 + SCT capture control register + CAPCTRL_MATCHREL + 0x234 + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPCONn_L + If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. + 0 + 16 + read-write + + + CAPCONn_H + If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. + 16 + 16 + read-write + + + + + SCTMATCHREL13 + SCT match reload value register + CAPCTRL_MATCHREL + 0x234 + 32 + read-write + 0 + 0xFFFFFFFF + + + RELOADn_L + When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. + 0 + 16 + read-write + + + RELOADn_H + When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. + 16 + 16 + read-write + + + + + SCTCAPCTRL14 + SCT capture control register + CAPCTRL_MATCHREL + 0x238 + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPCONn_L + If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. + 0 + 16 + read-write + + + CAPCONn_H + If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. + 16 + 16 + read-write + + + + + SCTMATCHREL14 + SCT match reload value register + CAPCTRL_MATCHREL + 0x238 + 32 + read-write + 0 + 0xFFFFFFFF + + + RELOADn_L + When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. + 0 + 16 + read-write + + + RELOADn_H + When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. + 16 + 16 + read-write + + + + + SCTCAPCTRL15 + SCT capture control register + CAPCTRL_MATCHREL + 0x23C + 32 + read-write + 0 + 0xFFFFFFFF + + + CAPCONn_L + If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. + 0 + 16 + read-write + + + CAPCONn_H + If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. + 16 + 16 + read-write + + + + + SCTMATCHREL15 + SCT match reload value register + CAPCTRL_MATCHREL + 0x23C + 32 + read-write + 0 + 0xFFFFFFFF + + + RELOADn_L + When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. + 0 + 16 + read-write + + + RELOADn_H + When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. + 16 + 16 + read-write + + + + + 16 + 0x8 + EVENT[%s] + no description available + 0x300 + + STATE + SCT event state register 0 + 0 + 32 + read-write + 0 + 0xFFFF + + + STATEMSKn + If bit m is one, event n happens in state m of the counter selected by the HEVENT bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of bits = number of states in this SCT. + 0 + 16 + read-write + + + + + CTRL + SCT event control register 0 + 0x4 + 32 + read-write + 0 + 0x7FFFFF + + + MATCHSEL + Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running. + 0 + 4 + read-write + + + HEVENT + Select L/H counter. Do not set this bit if UNIFY = 1. + 4 + 1 + read-write + + + L_COUNTER + Selects the L state and the L match register selected by MATCHSEL. + 0 + + + H_COUNTER + Selects the H state and the H match register selected by MATCHSEL. + 0x1 + + + + + OUTSEL + Input/output select + 5 + 1 + read-write + + + INPUT + Selects the inputs selected by IOSEL. + 0 + + + OUTPUT + Selects the outputs selected by IOSEL. + 0x1 + + + + + IOSEL + Selects the input or output signal number associated with this event (if any). Do not select an input in this register if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event. + 6 + 4 + read-write + + + IOCOND + Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period . + 10 + 2 + read-write + + + LOW + LOW + 0 + + + RISE + Rise + 0x1 + + + FALL + Fall + 0x2 + + + HIGH + HIGH + 0x3 + + + + + COMBMODE + Selects how the specified match and I/O condition are used and combined. + 12 + 2 + read-write + + + OR + OR. The event occurs when either the specified match or I/O condition occurs. + 0 + + + MATCH + MATCH. Uses the specified match only. + 0x1 + + + IO + IO. Uses the specified I/O condition only. + 0x2 + + + AND + AND. The event occurs when the specified match and I/O condition occur simultaneously. + 0x3 + + + + + STATELD + This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state. + 14 + 1 + read-write + + + ADD + STATEV value is added into STATE (the carry-out is ignored). + 0 + + + LOAD + STATEV value is loaded into STATE. + 0x1 + + + + + STATEV + This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value. + 15 + 5 + read-write + + + MATCHMEM + If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value. + 20 + 1 + read-write + + + DIRECTION + Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved. + 21 + 2 + read-write + + + DIRECTION_INDEPENDENT + Direction independent. This event is triggered regardless of the count direction. + 0 + + + COUNTING_UP + Counting up. This event is triggered only during up-counting when BIDIR = 1. + 0x1 + + + COUNTING_DOWN + Counting down. This event is triggered only during down-counting when BIDIR = 1. + 0x2 + + + + + + + + 10 + 0x8 + OUT[%s] + no description available + 0x500 + + SET + SCT output 0 set register + 0 + 32 + read-write + 0 + 0xFFFF + + + SET + A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output 0 = bit 0, output 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register. + 0 + 16 + read-write + + + + + CLR + SCT output 0 clear register + 0x4 + 32 + read-write + 0 + 0xFFFF + + + CLR + A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register. + 0 + 16 + read-write + + + + + + + + FLEXCOMM0 + Flexcomm serial communication + FLEXCOMM + FLEXCOMM + 0x40086000 + + 0 + 0x1000 + registers + + + FLEXCOMM0 + 14 + + + + PSELID + Peripheral Select and Flexcomm ID register. + 0xFF8 + 32 + read-write + 0x101000 + 0xFFFFF0FF + + + PERSEL + Peripheral Select. This field is writable by software. + 0 + 3 + read-write + + + NO_PERIPH_SELECTED + No peripheral selected. + 0 + + + USART + USART function selected. + 0x1 + + + SPI + SPI function selected. + 0x2 + + + I2C + I2C function selected. + 0x3 + + + I2S_TRANSMIT + I2S transmit function selected. + 0x4 + + + I2S_RECEIVE + I2S receive function selected. + 0x5 + + + + + LOCK + Lock the peripheral select. This field is writable by software. + 3 + 1 + read-write + + + UNLOCKED + Peripheral select can be changed by software. + 0 + + + LOCKED + Peripheral select is locked and cannot be changed until this Flexcomm or the entire device is reset. + 0x1 + + + + + USARTPRESENT + USART present indicator. This field is Read-only. + 4 + 1 + read-only + + + NOT_PRESENT + This Flexcomm does not include the USART function. + 0 + + + PRESENT + This Flexcomm includes the USART function. + 0x1 + + + + + SPIPRESENT + SPI present indicator. This field is Read-only. + 5 + 1 + read-only + + + NOT_PRESENT + This Flexcomm does not include the SPI function. + 0 + + + PRESENT + This Flexcomm includes the SPI function. + 0x1 + + + + + I2CPRESENT + I2C present indicator. This field is Read-only. + 6 + 1 + read-only + + + NOT_PRESENT + This Flexcomm does not include the I2C function. + 0 + + + PRESENT + This Flexcomm includes the I2C function. + 0x1 + + + + + I2SPRESENT + I 2S present indicator. This field is Read-only. + 7 + 1 + read-only + + + NOT_PRESENT + This Flexcomm does not include the I2S function. + 0 + + + PRESENT + This Flexcomm includes the I2S function. + 0x1 + + + + + ID + Flexcomm ID. + 12 + 20 + read-only + + + + + PID + Peripheral identification register. + 0xFFC + 32 + read-only + 0 + 0xFFFFFFFF + + + Aperture + no description available + 0 + 8 + read-only + + + Minor_Rev + Minor revision of module implementation. + 8 + 4 + read-only + + + Major_Rev + Major revision of module implementation. + 12 + 4 + read-only + + + ID + Module identifier for the selected function. + 16 + 16 + read-only + + + + + + + FLEXCOMM1 + Flexcomm serial communication + FLEXCOMM + 0x40087000 + + 0 + 0x1000 + registers + + + FLEXCOMM1 + 15 + + + + FLEXCOMM2 + Flexcomm serial communication + FLEXCOMM + 0x40088000 + + 0 + 0x1000 + registers + + + FLEXCOMM2 + 16 + + + + FLEXCOMM3 + Flexcomm serial communication + FLEXCOMM + 0x40089000 + + 0 + 0x1000 + registers + + + FLEXCOMM3 + 17 + + + + FLEXCOMM4 + Flexcomm serial communication + FLEXCOMM + 0x4008A000 + + 0 + 0x1000 + registers + + + FLEXCOMM4 + 18 + + + + FLEXCOMM5 + Flexcomm serial communication + FLEXCOMM + 0x40096000 + + 0 + 0x1000 + registers + + + FLEXCOMM5 + 19 + + + + FLEXCOMM6 + Flexcomm serial communication + FLEXCOMM + 0x40097000 + + 0 + 0x1000 + registers + + + FLEXCOMM6 + 20 + + + + FLEXCOMM7 + Flexcomm serial communication + FLEXCOMM + 0x40098000 + + 0 + 0x1000 + registers + + + FLEXCOMM7 + 21 + + + + FLEXCOMM8 + Flexcomm serial communication + FLEXCOMM + 0x4009F000 + + 0 + 0x1000 + registers + + + FLEXCOMM8 + 59 + + + + I2C0 + I2C-bus interfaces + FLEXCOMM0 + I2C + I2C + 0x40086000 + + 0 + 0x1000 + registers + + + FLEXCOMM0 + 14 + + + + CFG + Configuration for shared functions. + 0x800 + 32 + read-write + 0 + 0x3F + + + MSTEN + Master Enable. When disabled, configurations settings for the Master function are not changed, but the Master function is internally reset. + 0 + 1 + read-write + + + DISABLED + Disabled. The I2C Master function is disabled. + 0 + + + ENABLED + Enabled. The I2C Master function is enabled. + 0x1 + + + + + SLVEN + Slave Enable. When disabled, configurations settings for the Slave function are not changed, but the Slave function is internally reset. + 1 + 1 + read-write + + + DISABLED + Disabled. The I2C slave function is disabled. + 0 + + + ENABLED + Enabled. The I2C slave function is enabled. + 0x1 + + + + + MONEN + Monitor Enable. When disabled, configurations settings for the Monitor function are not changed, but the Monitor function is internally reset. + 2 + 1 + read-write + + + DISABLED + Disabled. The I2C Monitor function is disabled. + 0 + + + ENABLED + Enabled. The I2C Monitor function is enabled. + 0x1 + + + + + TIMEOUTEN + I2C bus Time-out Enable. When disabled, the time-out function is internally reset. + 3 + 1 + read-write + + + DISABLED + Disabled. Time-out function is disabled. + 0 + + + ENABLED + Enabled. Time-out function is enabled. Both types of time-out flags will be generated and will cause interrupts if they are enabled. Typically, only one time-out will be used in a system. + 0x1 + + + + + MONCLKSTR + Monitor function Clock Stretching. + 4 + 1 + read-write + + + DISABLED + Disabled. The Monitor function will not perform clock stretching. Software or DMA may not always be able to read data provided by the Monitor function before it is overwritten. This mode may be used when non-invasive monitoring is critical. + 0 + + + ENABLED + Enabled. The Monitor function will perform clock stretching in order to ensure that software or DMA can read all incoming data supplied by the Monitor function. + 0x1 + + + + + HSCAPABLE + High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter, as well as the timing for certain I2C signalling, enabling High-speed mode applies to all functions: Master, Slave, and Monitor. + 5 + 1 + read-write + + + FAST_MODE_PLUS + Fast-mode plus. The I 2C interface will support Standard-mode, Fast-mode, and Fast-mode Plus, to the extent that the pin electronics support these modes. Any changes that need to be made to the pin controls, such as changing the drive strength or filtering, must be made by software via the IOCON register associated with each I2C pin, + 0 + + + HIGH_SPEED + High-speed. In addition to Standard-mode, Fast-mode, and Fast-mode Plus, the I 2C interface will support High-speed mode to the extent that the pin electronics support these modes. See Section 25.7.2.2 for more information. + 0x1 + + + + + + + STAT + Status register for Master, Slave, and Monitor functions. + 0x804 + 32 + read-write + 0x801 + 0x30FFF5F + + + MSTPENDING + Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending, the MSTSTATE bits indicate what type of software service if any the master expects. This flag will cause an interrupt when set if, enabled via the INTENSET register. The MSTPENDING flag is not set when the DMA is handling an event (if the MSTDMA bit in the MSTCTL register is set). If the master is in the idle state, and no communication is needed, mask this interrupt. + 0 + 1 + read-only + + + IN_PROGRESS + In progress. Communication is in progress and the Master function is busy and cannot currently accept a command. + 0 + + + PENDING + Pending. The Master function needs software service or is in the idle state. If the master is not in the idle state, it is waiting to receive or transmit data or the NACK bit. + 0x1 + + + + + MSTSTATE + Master State code. The master state code reflects the master state when the MSTPENDING bit is set, that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All other values are reserved. See Table 400 for details of state values and appropriate responses. + 1 + 3 + read-only + + + IDLE + Idle. The Master function is available to be used for a new transaction. + 0 + + + RECEIVE_READY + Receive ready. Received data available (Master Receiver mode). Address plus Read was previously sent and Acknowledged by slave. + 0x1 + + + TRANSMIT_READY + Transmit ready. Data can be transmitted (Master Transmitter mode). Address plus Write was previously sent and Acknowledged by slave. + 0x2 + + + NACK_ADDRESS + NACK Address. Slave NACKed address. + 0x3 + + + NACK_DATA + NACK Data. Slave NACKed transmitted data. + 0x4 + + + + + MSTARBLOSS + Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE. + 4 + 1 + read-write + + + NO_LOSS + No Arbitration Loss has occurred. + 0 + + + ARBITRATION_LOSS + Arbitration loss. The Master function has experienced an Arbitration Loss. At this point, the Master function has already stopped driving the bus and gone to an idle state. Software can respond by doing nothing, or by sending a Start in order to attempt to gain control of the bus when it next becomes idle. + 0x1 + + + + + MSTSTSTPERR + Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE. + 6 + 1 + read-write + + + NO_ERROR + No Start/Stop Error has occurred. + 0 + + + ERROR + The Master function has experienced a Start/Stop Error. A Start or Stop was detected at a time when it is not allowed by the I2C specification. The Master interface has stopped driving the bus and gone to an idle state, no action is required. A request for a Start could be made, or software could attempt to insure that the bus has not stalled. + 0x1 + + + + + SLVPENDING + Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is handling an event (if the SLVDMA bit in the SLVCTL register is set). The SLVPENDING flag is read-only and is automatically cleared when a 1 is written to the SLVCONTINUE bit in the SLVCTL register. The point in time when SlvPending is set depends on whether the I2C interface is in HSCAPABLE mode. See Section 25.7.2.2.2. When the I2C interface is configured to be HSCAPABLE, HS master codes are detected automatically. Due to the requirements of the HS I2C specification, slave addresses must also be detected automatically, since the address must be acknowledged before the clock can be stretched. + 8 + 1 + read-only + + + IN_PROGRESS + In progress. The Slave function does not currently need service. + 0 + + + PENDING + Pending. The Slave function needs service. Information on what is needed can be found in the adjacent SLVSTATE field. + 0x1 + + + + + SLVSTATE + Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled are affected by DMA mode and Automatic Operation modes. + 9 + 2 + read-only + + + SLAVE_ADDRESS + Slave address. Address plus R/W received. At least one of the four slave addresses has been matched by hardware. + 0 + + + SLAVE_RECEIVE + Slave receive. Received data is available (Slave Receiver mode). + 0x1 + + + SLAVE_TRANSMIT + Slave transmit. Data can be transmitted (Slave Transmitter mode). + 0x2 + + + + + SLVNOTSTR + Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in real time. + 11 + 1 + read-only + + + STRETCHING + Stretching. The slave function is currently stretching the I2C bus clock. Deep-Sleep or Power-down mode cannot be entered at this time. + 0 + + + NOT_STRETCHING + Not stretching. The slave function is not currently stretching the I 2C bus clock. Deep-sleep or Power-down mode could be entered at this time. + 0x1 + + + + + SLVIDX + Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers, and provides an identification of the address that was matched. It is possible that more than one address could be matched, but only one match can be reported here. + 12 + 2 + read-only + + + ADDRESS0 + Address 0. Slave address 0 was matched. + 0 + + + ADDRESS1 + Address 1. Slave address 1 was matched. + 0x1 + + + ADDRESS2 + Address 2. Slave address 2 was matched. + 0x2 + + + ADDRESS3 + Address 3. Slave address 3 was matched. + 0x3 + + + + + SLVSEL + Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address, or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that does not match an enabled address on the Slave function, when slave software decides to NACK a matched address, when there is a Stop detected on the bus, when the master NACKs slave data, and in some combinations of Automatic Operation. SLVSEL is not cleared if software NACKs data. + 14 + 1 + read-only + + + NOT_SELECTED + Not selected. The Slave function is not currently selected. + 0 + + + SELECTED + Selected. The Slave function is currently selected. + 0x1 + + + + + SLVDESEL + Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit. + 15 + 1 + read-write + + + NOT_DESELECTED + Not deselected. The Slave function has not become deselected. This does not mean that it is currently selected. That information can be found in the SLVSEL flag. + 0 + + + DESELECTED + Deselected. The Slave function has become deselected. This is specifically caused by the SLVSEL flag changing from 1 to 0. See the description of SLVSEL for details on when that event occurs. + 0x1 + + + + + MONRDY + Monitor Ready. This flag is cleared when the MONRXDAT register is read. + 16 + 1 + read-only + + + NO_DATA + No data. The Monitor function does not currently have data available. + 0 + + + DATA_WAITING + Data waiting. The Monitor function has data waiting to be read. + 0x1 + + + + + MONOV + Monitor Overflow flag. + 17 + 1 + read-write + + + NO_OVERRUN + No overrun. Monitor data has not overrun. + 0 + + + OVERRUN + Overrun. A Monitor data overrun has occurred. This can only happen when Monitor clock stretching not enabled via the MONCLKSTR bit in the CFG register. Writing 1 to this bit clears the flag. + 0x1 + + + + + MONACTIVE + Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop. + 18 + 1 + read-only + + + INACTIVE + Inactive. The Monitor function considers the I2C bus to be inactive. + 0 + + + ACTIVE + Active. The Monitor function considers the I2C bus to be active. + 0x1 + + + + + MONIDLE + Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when set if enabled via the INTENSET register. The flag can be cleared by writing a 1 to this bit. + 19 + 1 + read-write + + + NOT_IDLE + Not idle. The I2C bus is not idle, or this flag has been cleared by software. + 0 + + + IDLE + Idle. The I2C bus has gone idle at least once since the last time this flag was cleared by software. + 0x1 + + + + + EVENTTIMEOUT + Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start, Stop, and clock edges. The flag is cleared by writing a 1 to this bit. No time-out is created when the I2C-bus is idle. + 24 + 1 + read-write + + + NO_TIMEOUT + No time-out. I2C bus events have not caused a time-out. + 0 + + + EVEN_TIMEOUT + Event time-out. The time between I2C bus events has been longer than the time specified by the TIMEOUT register. + 0x1 + + + + + SCLTIMEOUT + SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit. + 25 + 1 + read-write + + + NO_TIMEOUT + No time-out. SCL low time has not caused a time-out. + 0 + + + TIMEOUT + Time-out. SCL low time has caused a time-out. + 0x1 + + + + + + + INTENSET + Interrupt Enable Set and read register. + 0x808 + 32 + read-write + 0 + 0x30B8951 + + + MSTPENDINGEN + Master Pending interrupt Enable. + 0 + 1 + read-write + + + DISABLED + Disabled. The MstPending interrupt is disabled. + 0 + + + ENABLED + Enabled. The MstPending interrupt is enabled. + 0x1 + + + + + MSTARBLOSSEN + Master Arbitration Loss interrupt Enable. + 4 + 1 + read-write + + + DISABLED + Disabled. The MstArbLoss interrupt is disabled. + 0 + + + ENABLED + Enabled. The MstArbLoss interrupt is enabled. + 0x1 + + + + + MSTSTSTPERREN + Master Start/Stop Error interrupt Enable. + 6 + 1 + read-write + + + DISABLED + Disabled. The MstStStpErr interrupt is disabled. + 0 + + + ENABLED + Enabled. The MstStStpErr interrupt is enabled. + 0x1 + + + + + SLVPENDINGEN + Slave Pending interrupt Enable. + 8 + 1 + read-write + + + DISABLED + Disabled. The SlvPending interrupt is disabled. + 0 + + + ENABLED + Enabled. The SlvPending interrupt is enabled. + 0x1 + + + + + SLVNOTSTREN + Slave Not Stretching interrupt Enable. + 11 + 1 + read-write + + + DISABLED + Disabled. The SlvNotStr interrupt is disabled. + 0 + + + ENABLED + Enabled. The SlvNotStr interrupt is enabled. + 0x1 + + + + + SLVDESELEN + Slave Deselect interrupt Enable. + 15 + 1 + read-write + + + DISABLED + Disabled. The SlvDeSel interrupt is disabled. + 0 + + + ENABLED + Enabled. The SlvDeSel interrupt is enabled. + 0x1 + + + + + MONRDYEN + Monitor data Ready interrupt Enable. + 16 + 1 + read-write + + + DISABLED + Disabled. The MonRdy interrupt is disabled. + 0 + + + ENABLED + Enabled. The MonRdy interrupt is enabled. + 0x1 + + + + + MONOVEN + Monitor Overrun interrupt Enable. + 17 + 1 + read-write + + + DISABLED + Disabled. The MonOv interrupt is disabled. + 0 + + + ENABLED + Enabled. The MonOv interrupt is enabled. + 0x1 + + + + + MONIDLEEN + Monitor Idle interrupt Enable. + 19 + 1 + read-write + + + DISABLED + Disabled. The MonIdle interrupt is disabled. + 0 + + + ENABLED + Enabled. The MonIdle interrupt is enabled. + 0x1 + + + + + EVENTTIMEOUTEN + Event time-out interrupt Enable. + 24 + 1 + read-write + + + DISABLED + Disabled. The Event time-out interrupt is disabled. + 0 + + + ENABLED + Enabled. The Event time-out interrupt is enabled. + 0x1 + + + + + SCLTIMEOUTEN + SCL time-out interrupt Enable. + 25 + 1 + read-write + + + DISABLED + Disabled. The SCL time-out interrupt is disabled. + 0 + + + ENABLED + Enabled. The SCL time-out interrupt is enabled. + 0x1 + + + + + + + INTENCLR + Interrupt Enable Clear register. + 0x80C + 32 + write-only + 0 + 0 + + + MSTPENDINGCLR + Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented. + 0 + 1 + write-only + + + MSTARBLOSSCLR + Master Arbitration Loss interrupt clear. + 4 + 1 + write-only + + + MSTSTSTPERRCLR + Master Start/Stop Error interrupt clear. + 6 + 1 + write-only + + + SLVPENDINGCLR + Slave Pending interrupt clear. + 8 + 1 + write-only + + + SLVNOTSTRCLR + Slave Not Stretching interrupt clear. + 11 + 1 + write-only + + + SLVDESELCLR + Slave Deselect interrupt clear. + 15 + 1 + write-only + + + MONRDYCLR + Monitor data Ready interrupt clear. + 16 + 1 + write-only + + + MONOVCLR + Monitor Overrun interrupt clear. + 17 + 1 + write-only + + + MONIDLECLR + Monitor Idle interrupt clear. + 19 + 1 + write-only + + + EVENTTIMEOUTCLR + Event time-out interrupt clear. + 24 + 1 + write-only + + + SCLTIMEOUTCLR + SCL time-out interrupt clear. + 25 + 1 + write-only + + + + + TIMEOUT + Time-out value register. + 0x810 + 32 + read-write + 0xFFFF + 0xFFFF + + + TOMIN + Time-out time value, bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks. + 0 + 4 + read-write + + + TO + Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks, as defined by the CLKDIV register. To change this value while I2C is in operation, disable all time-outs, write a new value to TIMEOUT, then re-enable time-outs. 0x000 = A time-out will occur after 16 counts of the I2C function clock. 0x001 = A time-out will occur after 32 counts of the I2C function clock. 0xFFF = A time-out will occur after 65,536 counts of the I2C function clock. + 4 + 12 + read-write + + + + + CLKDIV + Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function. + 0x814 + 32 + read-write + 0 + 0xFFFF + + + DIVVAL + This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3 before use. 0xFFFF = FCLK is divided by 65,536 before use. + 0 + 16 + read-write + + + + + INTSTAT + Interrupt Status register for Master, Slave, and Monitor functions. + 0x818 + 32 + read-only + 0x801 + 0x30B8951 + + + MSTPENDING + Master Pending. + 0 + 1 + read-only + + + MSTARBLOSS + Master Arbitration Loss flag. + 4 + 1 + read-only + + + MSTSTSTPERR + Master Start/Stop Error flag. + 6 + 1 + read-only + + + SLVPENDING + Slave Pending. + 8 + 1 + read-only + + + SLVNOTSTR + Slave Not Stretching status. + 11 + 1 + read-only + + + SLVDESEL + Slave Deselected flag. + 15 + 1 + read-only + + + MONRDY + Monitor Ready. + 16 + 1 + read-only + + + MONOV + Monitor Overflow flag. + 17 + 1 + read-only + + + MONIDLE + Monitor Idle flag. + 19 + 1 + read-only + + + EVENTTIMEOUT + Event time-out Interrupt flag. + 24 + 1 + read-only + + + SCLTIMEOUT + SCL time-out Interrupt flag. + 25 + 1 + read-only + + + + + MSTCTL + Master control register. + 0x820 + 32 + read-write + 0 + 0xE + + + MSTCONTINUE + Master Continue. This bit is write-only. + 0 + 1 + write-only + + + NO_EFFECT + No effect. + 0 + + + CONTINUE + Continue. Informs the Master function to continue to the next operation. This must done after writing transmit data, reading received data, or any other housekeeping related to the next bus operation. + 0x1 + + + + + MSTSTART + Master Start control. This bit is write-only. + 1 + 1 + read-write + + + NO_EFFECT + No effect. + 0 + + + START + Start. A Start will be generated on the I2C bus at the next allowed time. + 0x1 + + + + + MSTSTOP + Master Stop control. This bit is write-only. + 2 + 1 + read-write + + + NO_EFFECT + No effect. + 0 + + + STOP + Stop. A Stop will be generated on the I2C bus at the next allowed time, preceded by a NACK to the slave if the master is receiving data from the slave (Master Receiver mode). + 0x1 + + + + + MSTDMA + Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start, address, Stop, and address match must always be done with software, typically via an interrupt. Address acknowledgement must also be done by software except when the I2C is configured to be HSCAPABLE (and address acknowledgement is handled entirely by hardware) or when Automatic Operation is enabled. When a DMA data transfer is complete, MSTDMA must be cleared prior to beginning the next operation, typically a Start or Stop.This bit is read/write. + 3 + 1 + read-write + + + DISABLED + Disable. No DMA requests are generated for master operation. + 0 + + + ENABLED + Enable. A DMA request is generated for I2C master data operations. When this I2C master is generating Acknowledge bits in Master Receiver mode, the acknowledge is generated automatically. + 0x1 + + + + + + + MSTTIME + Master timing configuration. + 0x824 + 32 + read-write + 0x77 + 0x77 + + + MSTSCLLOW + Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C bus specification parameters tBUF and tSU;STA have the same values and are also controlled by MSTSCLLOW. + 0 + 3 + read-write + + + CLOCKS_2 + 2 clocks. Minimum SCL low time is 2 clocks of the I2C clock pre-divider. + 0 + + + CLOCKS_3 + 3 clocks. Minimum SCL low time is 3 clocks of the I2C clock pre-divider. + 0x1 + + + CLOCKS_4 + 4 clocks. Minimum SCL low time is 4 clocks of the I2C clock pre-divider. + 0x2 + + + CLOCKS_5 + 5 clocks. Minimum SCL low time is 5 clocks of the I2C clock pre-divider. + 0x3 + + + CLOCKS_6 + 6 clocks. Minimum SCL low time is 6 clocks of the I2C clock pre-divider. + 0x4 + + + CLOCKS_7 + 7 clocks. Minimum SCL low time is 7 clocks of the I2C clock pre-divider. + 0x5 + + + CLOCKS_8 + 8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider. + 0x6 + + + CLOCKS_9 + 9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider. + 0x7 + + + + + MSTSCLHIGH + Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH. + 4 + 3 + read-write + + + CLOCKS_2 + 2 clocks. Minimum SCL high time is 2 clock of the I2C clock pre-divider. + 0 + + + CLOCKS_3 + 3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider . + 0x1 + + + CLOCKS_4 + 4 clocks. Minimum SCL high time is 4 clock of the I2C clock pre-divider. + 0x2 + + + CLOCKS_5 + 5 clocks. Minimum SCL high time is 5 clock of the I2C clock pre-divider. + 0x3 + + + CLOCKS_6 + 6 clocks. Minimum SCL high time is 6 clock of the I2C clock pre-divider. + 0x4 + + + CLOCKS_7 + 7 clocks. Minimum SCL high time is 7 clock of the I2C clock pre-divider. + 0x5 + + + CLOCKS_8 + 8 clocks. Minimum SCL high time is 8 clock of the I2C clock pre-divider. + 0x6 + + + CLOCKS_9 + 9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider. + 0x7 + + + + + + + MSTDAT + Combined Master receiver and transmitter data register. + 0x828 + 32 + read-write + 0 + 0xFF + + + DATA + Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function. + 0 + 8 + read-write + + + + + SLVCTL + Slave control register. + 0x840 + 32 + read-write + 0 + 0x30B + + + SLVCONTINUE + Slave Continue. + 0 + 1 + read-write + + + NO_EFFECT + No effect. + 0 + + + CONTINUE + Continue. Informs the Slave function to continue to the next operation, by clearing the SLVPENDING flag in the STAT register. This must be done after writing transmit data, reading received data, or any other housekeeping related to the next bus operation. Automatic Operation has different requirements. SLVCONTINUE should not be set unless SLVPENDING = 1. + 0x1 + + + + + SLVNACK + Slave NACK. + 1 + 1 + read-write + + + NO_EFFECT + No effect. + 0 + + + NACK + NACK. Causes the Slave function to NACK the master when the slave is receiving data from the master (Slave Receiver mode). + 0x1 + + + + + SLVDMA + Slave DMA enable. + 3 + 1 + read-write + + + DISABLED + Disabled. No DMA requests are issued for Slave mode operation. + 0 + + + ENABLED + Enabled. DMA requests are issued for I2C slave data transmission and reception. + 0x1 + + + + + AUTOACK + Automatic Acknowledge.When this bit is set, it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit is clear and a header matches SLVADR0, the behavior is controlled by AUTONACK in the SLVADR0 register: allowing NACK or interrupt. + 8 + 1 + read-write + + + NORMAL + Normal, non-automatic operation. If AUTONACK = 0, an SlvPending interrupt is generated when a matching address is received. If AUTONACK = 1, received addresses are NACKed (ignored). + 0 + + + AUTOMATIC_ACK + A header with matching SLVADR0 and matching direction as set by AUTOMATCHREAD will be ACKed immediately, allowing the master to move on to the data bytes. If the address matches SLVADR0, but the direction does not match AUTOMATCHREAD, the behavior will depend on the AUTONACK bit in the SLVADR0 register: if AUTONACK is set, then it will be Nacked; else if AUTONACK is clear, then a SlvPending interrupt is generated. + 0x1 + + + + + AUTOMATCHREAD + When AUTOACK is set, this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction, the direction needs to be specified. This bit allows a direction to be chosen for the next operation. + 9 + 1 + read-write + + + I2C_WRITE + The expected next operation in Automatic Mode is an I2C write. + 0 + + + I2C_READ + The expected next operation in Automatic Mode is an I2C read. + 0x1 + + + + + + + SLVDAT + Combined Slave receiver and transmitter data register. + 0x844 + 32 + read-write + 0 + 0xFF + + + DATA + Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function. + 0 + 8 + read-write + + + + + 4 + 0x4 + SLVADR[%s] + Slave address register. + 0x848 + 32 + read-write + 0x1 + 0xFF + + + SADISABLE + Slave Address n Disable. + 0 + 1 + read-write + + + ENABLED + Enabled. Slave Address n is enabled. + 0 + + + DISABLED + Ignored Slave Address n is ignored. + 0x1 + + + + + SLVADR + Slave Address. Seven bit slave address that is compared to received addresses if enabled. + 1 + 7 + read-write + + + AUTONACK + Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD, allows software to ignore I2C traffic while handling previous I2C data or other operations. + 15 + 1 + read-write + + + NORMAL + Normal operation, matching I2C addresses are not ignored. + 0 + + + AUTOMATIC + Automatic-only mode. All incoming addresses are ignored (NACKed), unless AUTOACK is set, it matches SLVADRn, and AUTOMATCHREAD matches the direction. + 0x1 + + + + + + + SLVQUAL0 + Slave Qualification for address 0. + 0x858 + 32 + read-write + 0 + 0xFF + + + QUALMODE0 + Qualify mode for slave address 0. + 0 + 1 + read-write + + + MASK + Mask. The SLVQUAL0 field is used as a logical mask for matching address 0. + 0 + + + EXTEND + Extend. The SLVQUAL0 field is used to extend address 0 matching in a range of addresses. + 0x1 + + + + + SLVQUAL0 + Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is, assuming that it is enabled. If QUALMODE0 = 0, any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of the received address when it is compared to the SLVADR0 register. If QUALMODE0 = 1, an address range is matched for address 0. This range extends from the value defined by SLVADR0 to the address defined by SLVQUAL0 (address matches when SLVADR0[7:1] <= received address <= SLVQUAL0[7:1]). + 1 + 7 + read-write + + + + + MONRXDAT + Monitor receiver data register. + 0x880 + 32 + read-only + 0 + 0x7FF + + + MONRXDAT + Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins. + 0 + 8 + read-only + + + MONSTART + Monitor Received Start. + 8 + 1 + read-only + + + NO_START_DETECTED + No start detected. The Monitor function has not detected a Start event on the I2C bus. + 0 + + + START_DETECTED + Start detected. The Monitor function has detected a Start event on the I2C bus. + 0x1 + + + + + MONRESTART + Monitor Received Repeated Start. + 9 + 1 + read-only + + + NOT_DETECTED + No repeated start detected. The Monitor function has not detected a Repeated Start event on the I2C bus. + 0 + + + DETECTED + Repeated start detected. The Monitor function has detected a Repeated Start event on the I2C bus. + 0x1 + + + + + MONNACK + Monitor Received NACK. + 10 + 1 + read-only + + + ACKNOWLEDGED + Acknowledged. The data currently being provided by the Monitor function was acknowledged by at least one master or slave receiver. + 0 + + + NOT_ACKNOWLEDGED + Not acknowledged. The data currently being provided by the Monitor function was not acknowledged by any receiver. + 0x1 + + + + + + + ID + Peripheral identification register. + 0xFFC + 32 + read-only + 0 + 0xFFFFFFFF + + + APERTURE + Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture. + 0 + 8 + read-only + + + MINOR_REV + Minor revision of module implementation. + 8 + 4 + read-only + + + MAJOR_REV + Major revision of module implementation. + 12 + 4 + read-only + + + ID + Module identifier for the selected function. + 16 + 16 + read-only + + + + + + + I2C1 + I2C-bus interfaces + FLEXCOMM1 + I2C + 0x40087000 + + 0 + 0x1000 + registers + + + FLEXCOMM1 + 15 + + + + I2C2 + I2C-bus interfaces + FLEXCOMM2 + I2C + 0x40088000 + + 0 + 0x1000 + registers + + + FLEXCOMM2 + 16 + + + + I2C3 + I2C-bus interfaces + FLEXCOMM3 + I2C + 0x40089000 + + 0 + 0x1000 + registers + + + FLEXCOMM3 + 17 + + + + I2C4 + I2C-bus interfaces + FLEXCOMM4 + I2C + 0x4008A000 + + 0 + 0x1000 + registers + + + FLEXCOMM4 + 18 + + + + I2C5 + I2C-bus interfaces + FLEXCOMM5 + I2C + 0x40096000 + + 0 + 0x1000 + registers + + + FLEXCOMM5 + 19 + + + + I2C6 + I2C-bus interfaces + FLEXCOMM6 + I2C + 0x40097000 + + 0 + 0x1000 + registers + + + FLEXCOMM6 + 20 + + + + I2C7 + I2C-bus interfaces + FLEXCOMM7 + I2C + 0x40098000 + + 0 + 0x1000 + registers + + + FLEXCOMM7 + 21 + + + + I2S0 + I2S interface + FLEXCOMM0 + I2S + I2S + 0x40086000 + + 0 + 0x1000 + registers + + + FLEXCOMM0 + 14 + + + + 3 + 0x20 + SECCHANNEL[%s] + no description available + 0 + + PCFG1 + Configuration register 1 for channel pair + 0xC20 + 32 + read-write + 0 + 0x401 + + + PAIRENABLE + Enable for this channel pair.. + 0 + 1 + read-write + + + ONECHANNEL + Single channel mode. + 10 + 1 + read-write + + + + + PCFG2 + Configuration register 2 for channel pair + 0xC24 + 32 + read-write + 0 + 0x1FF0000 + + + POSITION + Data Position. + 16 + 9 + read-write + + + + + PSTAT + Status register for channel pair + 0xC28 + 32 + read-write + 0 + 0xF + + + BUSY + Busy status for this channel pair. + 0 + 1 + read-write + + + SLVFRMERR + Save Frame Error flag. + 1 + 1 + read-write + + + LR + Left/Right indication. + 2 + 1 + read-write + + + DATAPAUSED + Data Paused status flag. + 3 + 1 + read-only + + + + + + CFG1 + Configuration register 1 for the primary channel pair. + 0xC00 + 32 + read-write + 0 + 0x1F3FFF + + + MAINENABLE + Main enable for I 2S function in this Flexcomm + 0 + 1 + read-write + + + DISABLED + All I 2S channel pairs in this Flexcomm are disabled and the internal state machines, counters, and flags are reset. No other channel pairs can be enabled. + 0 + + + ENABLED + This I 2S channel pair is enabled. Other channel pairs in this Flexcomm may be enabled in their individual PAIRENABLE bits. + 0x1 + + + + + DATAPAUSE + Data flow Pause. Allows pausing data flow between the I2S serializer/deserializer and the FIFO. This could be done in order to change streams, or while restarting after a data underflow or overflow. When paused, FIFO operations can be done without corrupting data that is in the process of being sent or received. Once a data pause has been requested, the interface may need to complete sending data that was in progress before interrupting the flow of data. Software must check that the pause is actually in effect before taking action. This is done by monitoring the DATAPAUSED flag in the STAT register. When DATAPAUSE is cleared, data transfer will resume at the beginning of the next frame. + 1 + 1 + read-write + + + NORMAL + Normal operation, or resuming normal operation at the next frame if the I2S has already been paused. + 0 + + + PAUSE + A pause in the data flow is being requested. It is in effect when DATAPAUSED in STAT = 1. + 0x1 + + + + + PAIRCOUNT + Provides the number of I2S channel pairs in this Flexcomm This is a read-only field whose value may be different in other Flexcomms. 00 = there is 1 I2S channel pair in this Flexcomm. 01 = there are 2 I2S channel pairs in this Flexcomm. 10 = there are 3 I2S channel pairs in this Flexcomm. 11 = there are 4 I2S channel pairs in this Flexcomm. + 2 + 2 + read-write + + + PAIRS_1 + 1 I2S channel pairs in this flexcomm + 0 + + + PAIRS_2 + 2 I2S channel pairs in this flexcomm + 0x1 + + + PAIRS_3 + 3 I2S channel pairs in this flexcomm + 0x2 + + + PAIRS_4 + 4 I2S channel pairs in this flexcomm + 0x3 + + + + + MSTSLVCFG + Master / slave configuration selection, determining how SCK and WS are used by all channel pairs in this Flexcomm. + 4 + 2 + read-write + + + NORMAL_SLAVE_MODE + Normal slave mode, the default mode. SCK and WS are received from a master and used to transmit or receive data. + 0 + + + WS_SYNC_MASTER + WS synchronized master. WS is received from another master and used to synchronize the generation of SCK, when divided from the Flexcomm function clock. + 0x1 + + + MASTER_USING_SCK + Master using an existing SCK. SCK is received and used directly to generate WS, as well as transmitting or receiving data. + 0x2 + + + NORMAL_MASTER + Normal master mode. SCK and WS are generated so they can be sent to one or more slave devices. + 0x3 + + + + + MODE + Selects the basic I2S operating mode. Other configurations modify this to obtain all supported cases. See Formats and modes for examples. + 6 + 2 + read-write + + + CLASSIC_MODE + I2S mode a.k.a. 'classic' mode. WS has a 50% duty cycle, with (for each enabled channel pair) one piece of left channel data occurring during the first phase, and one pieces of right channel data occurring during the second phase. In this mode, the data region begins one clock after the leading WS edge for the frame. For a 50% WS duty cycle, FRAMELEN must define an even number of I2S clocks for the frame. If FRAMELEN defines an odd number of clocks per frame, the extra clock will occur on the right. + 0 + + + DSP_MODE_WS_50_DUTYCYCLE + DSP mode where WS has a 50% duty cycle. See remark for mode 0. + 0x1 + + + DSP_MODE_WS_1_CLOCK + DSP mode where WS has a one clock long pulse at the beginning of each data frame. + 0x2 + + + DSP_MODE_WS_1_DATA + DSP mode where WS has a one data slot long pulse at the beginning of each data frame. + 0x3 + + + + + RIGHTLOW + Right channel data is in the Low portion of FIFO data. Essentially, this swaps left and right channel data as it is transferred to or from the FIFO. This bit is not used if the data width is greater than 24 bits or if PDMDATA = 1. Note that if the ONECHANNEL field (bit 10 of this register) = 1, the one channel to be used is the nominally the left channel. POSITION can still place that data in the frame where right channel data is normally located. if all enabled channel pairs have ONECHANNEL = 1, then RIGHTLOW = 1 is not allowed. + 8 + 1 + read-write + + + RIGHT_HIGH + The right channel is taken from the high part of the FIFO data. For example, when data is 16 bits, FIFO bits 31:16 are used for the right channel. + 0 + + + RIGHT_LOW + The right channel is taken from the low part of the FIFO data. For example, when data is 16 bits, FIFO bits 15:0 are used for the right channel. + 0x1 + + + + + LEFTJUST + Left Justify data. + 9 + 1 + read-write + + + RIGHT_JUSTIFIED + Data is transferred between the FIFO and the I2S serializer/deserializer right justified, i.e. starting from bit 0 and continuing to the position defined by DATALEN. This would correspond to right justified data in the stream on the data bus. + 0 + + + LEFT_JUSTIFIED + Data is transferred between the FIFO and the I2S serializer/deserializer left justified, i.e. starting from the MSB of the FIFO entry and continuing for the number of bits defined by DATALEN. This would correspond to left justified data in the stream on the data bus. + 0x1 + + + + + ONECHANNEL + Single channel mode. Applies to both transmit and receive. This configuration bit applies only to the first I2S channel pair. Other channel pairs may select this mode independently in their separate CFG1 registers. + 10 + 1 + read-write + + + DUAL_CHANNEL + I2S data for this channel pair is treated as left and right channels. + 0 + + + SINGLE_CHANNEL + I2S data for this channel pair is treated as a single channel, functionally the left channel for this pair. In mode 0 only, the right side of the frame begins at POSITION = 0x100. This is because mode 0 makes a clear distinction between the left and right sides of the frame. When ONECHANNEL = 1, the single channel of data may be placed on the right by setting POSITION to 0x100 + the data position within the right side (e.g. 0x108 would place data starting at the 8th clock after the middle of the frame). In other modes, data for the single channel of data is placed at the clock defined by POSITION. + 0x1 + + + + + PDMDATA + PDM Data selection. This bit controls the data source for I2S transmit, and cannot be set in Rx mode. This bit only has an effect if the device the Flexcomm resides in includes a D-Mic subsystem. For the LPC55xx, this bit applies only to Flexcomm 6,7. + 11 + 1 + read-write + + + NORMAL + Normal operation, data is transferred to or from the Flexcomm FIFO. + 0 + + + DMIC_SUBSYSTEM + The data source is the D-Mic subsystem. When PDMDATA = 1, only the primary channel pair can be used in this Flexcomm. If ONECHANNEL = 1, only the PDM left data is used. the WS rate must match the Fs (sample rate) of the D-Mic decimator. A rate mismatch will at some point cause the I2S to overrun or underrun. + 0x1 + + + + + SCK_POL + SCK polarity. + 12 + 1 + read-write + + + FALLING_EDGE + Data is launched on SCK falling edges and sampled on SCK rising edges (standard for I2S). + 0 + + + RISING_EDGE + Data is launched on SCK rising edges and sampled on SCK falling edges. + 0x1 + + + + + WS_POL + WS polarity. + 13 + 1 + read-write + + + NOT_INVERTED + Data frames begin at a falling edge of WS (standard for classic I2S). + 0 + + + INVERTED + WS is inverted, resulting in a data frame beginning at a rising edge of WS (standard for most 'non-classic' variations of I2S). + 0x1 + + + + + DATALEN + Data Length, minus 1 encoded, defines the number of data bits to be transmitted or received for all I2S channel pairs in this Flexcomm. Note that data is only driven to or received from SDA for the number of bits defined by DATALEN. DATALEN is also used in these ways by the I2S: Determines the size of data transfers between the FIFO and the I2S serializer/deserializer. See FIFO buffer configurations and usage In mode 1, 2, and 3, determines the location of right data following left data in the frame. In mode 3 (where WS has a one data slot long pulse at the beginning of each data frame) determines the duration of the WS pulse. Values: 0x00 to 0x02 = not supported 0x03 = data is 4 bits in length 0x04 = data is 5 bits in length 0x1F = data is 32 bits in length + 16 + 5 + read-write + + + + + CFG2 + Configuration register 2 for the primary channel pair. + 0xC04 + 32 + read-write + 0 + 0x1FF01FF + + + FRAMELEN + Frame Length, minus 1 encoded, defines the number of clocks and data bits in the frames that this channel pair participates in. See Frame format. 0x000 to 0x002 = not supported 0x003 = frame is 4 bits in total length 0x004 = frame is 5 bits in total length 0x1FF = frame is 512 bits in total length if FRAMELEN is an defines an odd length frame (e.g. 33 clocks) in mode 0 or 1, the extra clock appears in the right half. When MODE = 3, FRAMELEN must be larger than DATALEN in order for the WS pulse to be generated correctly. + 0 + 9 + read-write + + + POSITION + Data Position. Defines the location within the frame of the data for this channel pair. POSITION + DATALEN must be less than FRAMELEN. See Frame format. When MODE = 0, POSITION defines the location of data in both the left phase and right phase, starting one clock after the WS edge. In other modes, POSITION defines the location of data within the entire frame. ONECHANNEL = 1 while MODE = 0 is a special case, see the description of ONECHANNEL. The combination of DATALEN and the POSITION fields of all channel pairs must be made such that the channels do not overlap within the frame. 0x000 = data begins at bit position 0 (the first bit position) within the frame or WS phase. 0x001 = data begins at bit position 1 within the frame or WS phase. 0x002 = data begins at bit position 2 within the frame or WS phase. + 16 + 9 + read-write + + + + + STAT + Status register for the primary channel pair. + 0xC08 + 32 + read-write + 0 + 0xD + + + BUSY + Busy status for the primary channel pair. Other BUSY flags may be found in the STAT register for each channel pair. + 0 + 1 + read-only + + + IDLE + The transmitter/receiver for channel pair is currently idle. + 0 + + + BUSY + The transmitter/receiver for channel pair is currently processing data. + 0x1 + + + + + SLVFRMERR + Slave Frame Error flag. This applies when at least one channel pair is operating as a slave. An error indicates that the incoming WS signal did not transition as expected due to a mismatch between FRAMELEN and the actual incoming I2S stream. + 1 + 1 + write-only + + + NO_ERROR + No error has been recorded. + 0 + + + ERROR + An error has been recorded for some channel pair that is operating in slave mode. ERROR is cleared by writing a 1 to this bit position. + 0x1 + + + + + LR + Left/Right indication. This flag is considered to be a debugging aid and is not expected to be used by an I2S driver. Valid when one channel pair is busy. Indicates left or right data being processed for the currently busy channel pair. + 2 + 1 + read-only + + + LEFT_CHANNEL + Left channel. + 0 + + + RIGHT_CHANNEL + Right channel. + 0x1 + + + + + DATAPAUSED + Data Paused status flag. Applies to all I2S channels + 3 + 1 + read-only + + + NOT_PAUSED + Data is not currently paused. A data pause may have been requested but is not yet in force, waiting for an allowed pause point. Refer to the description of the DATAPAUSE control bit in the CFG1 register. + 0 + + + PAUSED + A data pause has been requested and is now in force. + 0x1 + + + + + + + DIV + Clock divider, used by all channel pairs. + 0xC1C + 32 + read-write + 0 + 0xFFF + + + DIV + This field controls how this I2S block uses the Flexcomm function clock. 0x000 = The Flexcomm function clock is used directly. 0x001 = The Flexcomm function clock is divided by 2. 0x002 = The Flexcomm function clock is divided by 3. 0xFFF = The Flexcomm function clock is divided by 4,096. + 0 + 12 + read-write + + + + + FIFOCFG + FIFO configuration and enable register. + 0xE00 + 32 + read-write + 0 + 0x7F033 + + + ENABLETX + Enable the transmit FIFO. + 0 + 1 + read-write + + + DISABLED + The transmit FIFO is not enabled. + 0 + + + ENABLED + The transmit FIFO is enabled. + 0x1 + + + + + ENABLERX + Enable the receive FIFO. + 1 + 1 + read-write + + + DISABLED + The receive FIFO is not enabled. + 0 + + + ENABLED + The receive FIFO is enabled. + 0x1 + + + + + TXI2SE0 + Transmit I2S empty 0. Determines the value sent by the I2S in transmit mode if the TX FIFO becomes empty. This value is sent repeatedly until the I2S is paused, the error is cleared, new data is provided, and the I2S is un-paused. + 2 + 1 + read-write + + + LAST_VALUE + If the TX FIFO becomes empty, the last value is sent. This setting may be used when the data length is 24 bits or less, or when MONO = 1 for this channel pair. + 0 + + + ZERO + If the TX FIFO becomes empty, 0 is sent. Use if the data length is greater than 24 bits or if zero fill is preferred. + 0x1 + + + + + PACK48 + Packing format for 48-bit data. This relates to how data is entered into or taken from the FIFO by software or DMA. + 3 + 1 + read-write + + + BIT_24 + 48-bit I2S FIFO entries are handled as all 24-bit values. + 0 + + + BIT_32_16 + 48-bit I2S FIFO entries are handled as alternating 32-bit and 16-bit values. + 0x1 + + + + + SIZE + FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART. + 4 + 2 + read-only + + + DMATX + DMA configuration for transmit. + 12 + 1 + read-write + + + DISABLED + DMA is not used for the transmit function. + 0 + + + ENABLED + Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. + 0x1 + + + + + DMARX + DMA configuration for receive. + 13 + 1 + read-write + + + DISABLED + DMA is not used for the receive function. + 0 + + + ENABLED + Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. + 0x1 + + + + + WAKETX + Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register. + 14 + 1 + read-write + + + DISABLED + Only enabled interrupts will wake up the device form reduced power modes. + 0 + + + ENABLED + A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in FIFOTRIG, even when the TXLVL interrupt is not enabled. + 0x1 + + + + + WAKERX + Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register. + 15 + 1 + read-write + + + DISABLED + Only enabled interrupts will wake up the device form reduced power modes. + 0 + + + ENABLED + A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in FIFOTRIG, even when the RXLVL interrupt is not enabled. + 0x1 + + + + + EMPTYTX + Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied. + 16 + 1 + read-write + + + EMPTYRX + Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied. + 17 + 1 + read-write + + + POPDBG + Pop FIFO for debug reads. + 18 + 1 + read-write + + + DO_NOT_POP + Debug reads of the FIFO do not pop the FIFO. + 0 + + + POP + A debug read will cause the FIFO to pop. + 0x1 + + + + + + + FIFOSTAT + FIFO status register. + 0xE04 + 32 + read-write + 0x30 + 0x1F1FFB + + + TXERR + TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit. + 0 + 1 + read-write + + + RXERR + RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit. + 1 + 1 + read-write + + + PERINT + Peripheral interrupt. When 1, this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register. + 3 + 1 + read-only + + + TXEMPTY + Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data. + 4 + 1 + read-only + + + TXNOTFULL + Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be written. When 0, the transmit FIFO is full and another write would cause it to overflow. + 5 + 1 + read-only + + + RXNOTEMPTY + Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty. + 6 + 1 + read-only + + + RXFULL + Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow. + 7 + 1 + read-only + + + TXLVL + Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be 0. + 8 + 5 + read-only + + + RXLVL + Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be 1. + 16 + 5 + read-only + + + + + FIFOTRIG + FIFO trigger settings for interrupt and DMA request. + 0xE08 + 32 + read-write + 0 + 0xF0F03 + + + TXLVLENA + Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set. + 0 + 1 + read-write + + + DISABLED + Transmit FIFO level does not generate a FIFO level trigger. + 0 + + + ENABLED + An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register. + 0x1 + + + + + RXLVLENA + Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. + 1 + 1 + read-write + + + DISABLED + Receive FIFO level does not generate a FIFO level trigger. + 0 + + + ENABLED + An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. + 0x1 + + + + + TXLVL + Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX FIFO level decreases to 15 entries (is no longer full). + 8 + 4 + read-write + + + RXLVL + Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX FIFO has received 16 entries (has become full). + 16 + 4 + read-write + + + + + FIFOINTENSET + FIFO interrupt enable set (enable) and read register. + 0xE10 + 32 + read-write + 0 + 0xF + + + TXERR + Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. + 0 + 1 + read-write + + + DISABLED + No interrupt will be generated for a transmit error. + 0 + + + ENABLED + An interrupt will be generated when a transmit error occurs. + 0x1 + + + + + RXERR + Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. + 1 + 1 + read-write + + + DISABLED + No interrupt will be generated for a receive error. + 0 + + + ENABLED + An interrupt will be generated when a receive error occurs. + 0x1 + + + + + TXLVL + Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. + 2 + 1 + read-write + + + DISABLED + No interrupt will be generated based on the TX FIFO level. + 0 + + + ENABLED + If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases to the level specified by TXLVL in the FIFOTRIG register. + 0x1 + + + + + RXLVL + Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. + 3 + 1 + read-write + + + DISABLED + No interrupt will be generated based on the RX FIFO level. + 0 + + + ENABLED + If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level increases to the level specified by RXLVL in the FIFOTRIG register. + 0x1 + + + + + + + FIFOINTENCLR + FIFO interrupt enable clear (disable) and read register. + 0xE14 + 32 + read-write + 0 + 0xF + + + TXERR + Writing one clears the corresponding bits in the FIFOINTENSET register. + 0 + 1 + read-write + + + RXERR + Writing one clears the corresponding bits in the FIFOINTENSET register. + 1 + 1 + read-write + + + TXLVL + Writing one clears the corresponding bits in the FIFOINTENSET register. + 2 + 1 + read-write + + + RXLVL + Writing one clears the corresponding bits in the FIFOINTENSET register. + 3 + 1 + read-write + + + + + FIFOINTSTAT + FIFO interrupt status register. + 0xE18 + 32 + read-only + 0 + 0x1F + + + TXERR + TX FIFO error. + 0 + 1 + read-only + + + RXERR + RX FIFO error. + 1 + 1 + read-only + + + TXLVL + Transmit FIFO level interrupt. + 2 + 1 + read-only + + + RXLVL + Receive FIFO level interrupt. + 3 + 1 + read-only + + + PERINT + Peripheral interrupt. + 4 + 1 + read-only + + + + + FIFOWR + FIFO write data. + 0xE20 + 32 + write-only + 0 + 0 + + + TXDATA + Transmit data to the FIFO. The number of bits used depends on configuration details. + 0 + 32 + write-only + + + + + FIFOWR48H + FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. + 0xE24 + 32 + write-only + 0 + 0 + + + TXDATA + Transmit data to the FIFO. Whether this register is used and the number of bits used depends on configuration details. + 0 + 24 + write-only + + + + + FIFORD + FIFO read data. + 0xE30 + 32 + read-only + 0 + 0 + + + RXDATA + Received data from the FIFO. The number of bits used depends on configuration details. + 0 + 32 + read-only + + + + + FIFORD48H + FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. + 0xE34 + 32 + read-only + 0 + 0xFFFFFF + + + RXDATA + Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details. + 0 + 24 + read-only + + + + + FIFORDNOPOP + FIFO data read with no FIFO pop. + 0xE40 + 32 + read-only + 0 + 0 + + + RXDATA + Received data from the FIFO. + 0 + 32 + read-only + + + + + FIFORD48HNOPOP + FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. + 0xE44 + 32 + read-only + 0 + 0xFFFFFF + + + RXDATA + Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details. + 0 + 24 + read-only + + + + + ID + I2S Module identification + 0xFFC + 32 + read-only + 0xE0900000 + 0xFFFFFFFF + + + Aperture + Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture. + 0 + 8 + read-only + + + Minor_Rev + Minor revision of module implementation, starting at 0. + 8 + 4 + read-only + + + Major_Rev + Major revision of module implementation, starting at 0. + 12 + 4 + read-only + + + ID + Unique module identifier for this IP block. + 16 + 16 + read-only + + + + + + + I2S1 + I2S interface + FLEXCOMM1 + I2S + 0x40087000 + + 0 + 0x1000 + registers + + + FLEXCOMM1 + 15 + + + + I2S2 + I2S interface + FLEXCOMM2 + I2S + 0x40088000 + + 0 + 0x1000 + registers + + + FLEXCOMM2 + 16 + + + + I2S3 + I2S interface + FLEXCOMM3 + I2S + 0x40089000 + + 0 + 0x1000 + registers + + + FLEXCOMM3 + 17 + + + + I2S4 + I2S interface + FLEXCOMM4 + I2S + 0x4008A000 + + 0 + 0x1000 + registers + + + FLEXCOMM4 + 18 + + + + I2S5 + I2S interface + FLEXCOMM5 + I2S + 0x40096000 + + 0 + 0x1000 + registers + + + FLEXCOMM5 + 19 + + + + I2S6 + I2S interface + FLEXCOMM6 + I2S + 0x40097000 + + 0 + 0x1000 + registers + + + FLEXCOMM6 + 20 + + + + I2S7 + I2S interface + FLEXCOMM7 + I2S + 0x40098000 + + 0 + 0x1000 + registers + + + FLEXCOMM7 + 21 + + + + SPI0 + Serial Peripheral Interfaces (SPI) + FLEXCOMM0 + SPI + SPI + 0x40086000 + + 0 + 0x1000 + registers + + + FLEXCOMM0 + 14 + + + + CFG + SPI Configuration register + 0x400 + 32 + read-write + 0 + 0xFBD + + + ENABLE + SPI enable. + 0 + 1 + read-write + + + DISABLED + Disabled. The SPI is disabled and the internal state machine and counters are reset. + 0 + + + ENABLED + Enabled. The SPI is enabled for operation. + 0x1 + + + + + MASTER + Master mode select. + 2 + 1 + read-write + + + SLAVE_MODE + Slave mode. The SPI will operate in slave mode. SCK, MOSI, and the SSEL signals are inputs, MISO is an output. + 0 + + + MASTER_MODE + Master mode. The SPI will operate in master mode. SCK, MOSI, and the SSEL signals are outputs, MISO is an input. + 0x1 + + + + + LSBF + LSB First mode enable. + 3 + 1 + read-write + + + STANDARD + Standard. Data is transmitted and received in standard MSB first order. + 0 + + + REVERSE + Reverse. Data is transmitted and received in reverse order (LSB first). + 0x1 + + + + + CPHA + Clock Phase select. + 4 + 1 + read-write + + + CHANGE + Change. The SPI captures serial data on the first clock transition of the transfer (when the clock changes away from the rest state). Data is changed on the following edge. + 0 + + + CAPTURE + Capture. The SPI changes serial data on the first clock transition of the transfer (when the clock changes away from the rest state). Data is captured on the following edge. + 0x1 + + + + + CPOL + Clock Polarity select. + 5 + 1 + read-write + + + LOW + Low. The rest state of the clock (between transfers) is low. + 0 + + + HIGH + High. The rest state of the clock (between transfers) is high. + 0x1 + + + + + LOOP + Loopback mode enable. Loopback mode applies only to Master mode, and connects transmit and receive data connected together to allow simple software testing. + 7 + 1 + read-write + + + DISABLED + Disabled. + 0 + + + ENABLED + Enabled. + 0x1 + + + + + SPOL0 + SSEL0 Polarity select. + 8 + 1 + read-write + + + LOW + Low. The SSEL0 pin is active low. + 0 + + + HIGH + High. The SSEL0 pin is active high. + 0x1 + + + + + SPOL1 + SSEL1 Polarity select. + 9 + 1 + read-write + + + LOW + Low. The SSEL1 pin is active low. + 0 + + + HIGH + High. The SSEL1 pin is active high. + 0x1 + + + + + SPOL2 + SSEL2 Polarity select. + 10 + 1 + read-write + + + LOW + Low. The SSEL2 pin is active low. + 0 + + + HIGH + High. The SSEL2 pin is active high. + 0x1 + + + + + SPOL3 + SSEL3 Polarity select. + 11 + 1 + read-write + + + LOW + Low. The SSEL3 pin is active low. + 0 + + + HIGH + High. The SSEL3 pin is active high. + 0x1 + + + + + + + DLY + SPI Delay register + 0x404 + 32 + read-write + 0 + 0xFFFF + + + PRE_DELAY + Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted. + 0 + 4 + read-write + + + POST_DELAY + Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted. + 4 + 4 + read-write + + + FRAME_DELAY + If the EOF flag is set, controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted. + 8 + 4 + read-write + + + TRANSFER_DELAY + Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times. 0x2 = The minimum time that SSEL is deasserted is 3 SPI clock times. 0xF = The minimum time that SSEL is deasserted is 16 SPI clock times. + 12 + 4 + read-write + + + + + STAT + SPI Status. Some status flags can be cleared by writing a 1 to that bit position. + 0x408 + 32 + read-write + 0x100 + 0x1C0 + + + SSA + Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted, in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy, and allows waking up the device from reduced power modes when a slave mode access begins. This flag is cleared by software. + 4 + 1 + write-only + + + SSD + Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted, in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software. + 5 + 1 + write-only + + + STALLED + Stalled status flag. This indicates whether the SPI is currently in a stall condition. + 6 + 1 + read-only + + + ENDTRANSFER + End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress, as if the EOT flag had been set prior to the last transmission. This capability is included to support cases where it is not known when transmit data is written that it will be the end of a transfer. The bit is cleared when the transmitter becomes idle as the transfer comes to an end. Forcing an end of transfer in this manner causes any specified FRAME_DELAY and TRANSFER_DELAY to be inserted. + 7 + 1 + read-write + + + MSTIDLE + Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data. + 8 + 1 + read-only + + + + + INTENSET + SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. + 0x40C + 32 + read-write + 0 + 0x130 + + + SSAEN + Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted. + 4 + 1 + read-write + + + DISABLED + Disabled. No interrupt will be generated when any Slave Select transitions from deasserted to asserted. + 0 + + + ENABLED + Enabled. An interrupt will be generated when any Slave Select transitions from deasserted to asserted. + 0x1 + + + + + SSDEN + Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted. + 5 + 1 + read-write + + + DISABLED + Disabled. No interrupt will be generated when all asserted Slave Selects transition to deasserted. + 0 + + + ENABLED + Enabled. An interrupt will be generated when all asserted Slave Selects transition to deasserted. + 0x1 + + + + + MSTIDLEEN + Master idle interrupt enable. + 8 + 1 + read-write + + + DISABLED + No interrupt will be generated when the SPI master function is idle. + 0 + + + ENABLED + An interrupt will be generated when the SPI master function is fully idle. + 0x1 + + + + + + + INTENCLR + SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared. + 0x410 + 32 + write-only + 0 + 0 + + + SSAEN + Writing 1 clears the corresponding bit in the INTENSET register. + 4 + 1 + write-only + + + SSDEN + Writing 1 clears the corresponding bit in the INTENSET register. + 5 + 1 + write-only + + + MSTIDLE + Writing 1 clears the corresponding bit in the INTENSET register. + 8 + 1 + write-only + + + + + DIV + SPI clock Divider + 0x424 + 32 + read-write + 0 + 0xFFFF + + + DIVVAL + Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1, the value 1 results in FCLK/2, up to the maximum possible divide value of 0xFFFF, which results in FCLK/65536. + 0 + 16 + read-write + + + + + INTSTAT + SPI Interrupt Status + 0x428 + 32 + read-only + 0 + 0x130 + + + SSA + Slave Select Assert. + 4 + 1 + read-only + + + SSD + Slave Select Deassert. + 5 + 1 + read-only + + + MSTIDLE + Master Idle status flag. + 8 + 1 + read-only + + + + + FIFOCFG + FIFO configuration and enable register. + 0xE00 + 32 + read-write + 0 + 0x7F033 + + + ENABLETX + Enable the transmit FIFO. + 0 + 1 + read-write + + + DISABLED + The transmit FIFO is not enabled. + 0 + + + ENABLED + The transmit FIFO is enabled. + 0x1 + + + + + ENABLERX + Enable the receive FIFO. + 1 + 1 + read-write + + + DISABLED + The receive FIFO is not enabled. + 0 + + + ENABLED + The receive FIFO is enabled. + 0x1 + + + + + SIZE + FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART. + 4 + 2 + read-only + + + DMATX + DMA configuration for transmit. + 12 + 1 + read-write + + + DISABLED + DMA is not used for the transmit function. + 0 + + + ENABLED + Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. + 0x1 + + + + + DMARX + DMA configuration for receive. + 13 + 1 + read-write + + + DISABLED + DMA is not used for the receive function. + 0 + + + ENABLED + Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. + 0x1 + + + + + WAKETX + Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register. + 14 + 1 + read-write + + + DISABLED + Only enabled interrupts will wake up the device form reduced power modes. + 0 + + + ENABLED + A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in FIFOTRIG, even when the TXLVL interrupt is not enabled. + 0x1 + + + + + WAKERX + Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register. + 15 + 1 + read-write + + + DISABLED + Only enabled interrupts will wake up the device form reduced power modes. + 0 + + + ENABLED + A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in FIFOTRIG, even when the RXLVL interrupt is not enabled. + 0x1 + + + + + EMPTYTX + Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied. + 16 + 1 + read-write + + + EMPTYRX + Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied. + 17 + 1 + read-write + + + POPDBG + Pop FIFO for debug reads. + 18 + 1 + read-write + + + DO_NOT_POP + Debug reads of the FIFO do not pop the FIFO. + 0 + + + POP + A debug read will cause the FIFO to pop. + 0x1 + + + + + + + FIFOSTAT + FIFO status register. + 0xE04 + 32 + read-write + 0x30 + 0x1F1FFB + + + TXERR + TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit. + 0 + 1 + read-write + + + RXERR + RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit. + 1 + 1 + read-write + + + PERINT + Peripheral interrupt. When 1, this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register. + 3 + 1 + read-only + + + TXEMPTY + Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data. + 4 + 1 + read-only + + + TXNOTFULL + Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be written. When 0, the transmit FIFO is full and another write would cause it to overflow. + 5 + 1 + read-only + + + RXNOTEMPTY + Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty. + 6 + 1 + read-only + + + RXFULL + Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow. + 7 + 1 + read-only + + + TXLVL + Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be 0. + 8 + 5 + read-only + + + RXLVL + Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be 1. + 16 + 5 + read-only + + + + + FIFOTRIG + FIFO trigger settings for interrupt and DMA request. + 0xE08 + 32 + read-write + 0 + 0xF0F03 + + + TXLVLENA + Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set. + 0 + 1 + read-write + + + DISABLED + Transmit FIFO level does not generate a FIFO level trigger. + 0 + + + ENABLED + An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register. + 0x1 + + + + + RXLVLENA + Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. + 1 + 1 + read-write + + + DISABLED + Receive FIFO level does not generate a FIFO level trigger. + 0 + + + ENABLED + An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. + 0x1 + + + + + TXLVL + Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX FIFO level decreases to 15 entries (is no longer full). + 8 + 4 + read-write + + + RXLVL + Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX FIFO has received 16 entries (has become full). + 16 + 4 + read-write + + + + + FIFOINTENSET + FIFO interrupt enable set (enable) and read register. + 0xE10 + 32 + read-write + 0 + 0xF + + + TXERR + Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. + 0 + 1 + read-write + + + DISABLED + No interrupt will be generated for a transmit error. + 0 + + + ENABLED + An interrupt will be generated when a transmit error occurs. + 0x1 + + + + + RXERR + Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. + 1 + 1 + read-write + + + DISABLED + No interrupt will be generated for a receive error. + 0 + + + ENABLED + An interrupt will be generated when a receive error occurs. + 0x1 + + + + + TXLVL + Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. + 2 + 1 + read-write + + + DISABLED + No interrupt will be generated based on the TX FIFO level. + 0 + + + ENABLED + If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases to the level specified by TXLVL in the FIFOTRIG register. + 0x1 + + + + + RXLVL + Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. + 3 + 1 + read-write + + + DISABLED + No interrupt will be generated based on the RX FIFO level. + 0 + + + ENABLED + If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level increases to the level specified by RXLVL in the FIFOTRIG register. + 0x1 + + + + + + + FIFOINTENCLR + FIFO interrupt enable clear (disable) and read register. + 0xE14 + 32 + read-write + 0 + 0xF + + + TXERR + Writing one clears the corresponding bits in the FIFOINTENSET register. + 0 + 1 + read-write + + + RXERR + Writing one clears the corresponding bits in the FIFOINTENSET register. + 1 + 1 + read-write + + + TXLVL + Writing one clears the corresponding bits in the FIFOINTENSET register. + 2 + 1 + read-write + + + RXLVL + Writing one clears the corresponding bits in the FIFOINTENSET register. + 3 + 1 + read-write + + + + + FIFOINTSTAT + FIFO interrupt status register. + 0xE18 + 32 + read-only + 0 + 0x1F + + + TXERR + TX FIFO error. + 0 + 1 + read-only + + + RXERR + RX FIFO error. + 1 + 1 + read-only + + + TXLVL + Transmit FIFO level interrupt. + 2 + 1 + read-only + + + RXLVL + Receive FIFO level interrupt. + 3 + 1 + read-only + + + PERINT + Peripheral interrupt. + 4 + 1 + read-only + + + + + FIFOWR + FIFO write data. + 0xE20 + 32 + read-write + 0 + 0 + + + TXDATA + Transmit data to the FIFO. + 0 + 16 + write-only + + + TXSSEL0_N + Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default. + 16 + 1 + write-only + + + ASSERTED + SSEL0 asserted. + 0 + + + NOT_ASSERTED + SSEL0 not asserted. + 0x1 + + + + + TXSSEL1_N + Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default. + 17 + 1 + write-only + + + ASSERTED + SSEL1 asserted. + 0 + + + NOT_ASSERTED + SSEL1 not asserted. + 0x1 + + + + + TXSSEL2_N + Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default. + 18 + 1 + write-only + + + ASSERTED + SSEL2 asserted. + 0 + + + NOT_ASSERTED + SSEL2 not asserted. + 0x1 + + + + + TXSSEL3_N + Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default. + 19 + 1 + write-only + + + ASSERTED + SSEL3 asserted. + 0 + + + NOT_ASSERTED + SSEL3 not asserted. + 0x1 + + + + + EOT + End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register. + 20 + 1 + write-only + + + NOT_DEASSERTED + SSEL not deasserted. This piece of data is not treated as the end of a transfer. SSEL will not be deasserted at the end of this data. + 0 + + + DEASSERTED + SSEL deasserted. This piece of data is treated as the end of a transfer. SSEL will be deasserted at the end of this piece of data. + 0x1 + + + + + EOF + End of frame. Between frames, a delay may be inserted, as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for frame lengths greater than 16 bits. + 21 + 1 + write-only + + + NOT_EOF + Data not EOF. This piece of data transmitted is not treated as the end of a frame. + 0 + + + EOF + Data EOF. This piece of data is treated as the end of a frame, causing the Frame_delay time to be inserted before subsequent data is transmitted. + 0x1 + + + + + RXIGNORE + Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA. + 22 + 1 + write-only + + + READ + Read received data. Received data must be read in order to allow transmission to progress. SPI transmit will halt when the receive data FIFO is full. In slave mode, an overrun error will occur if received data is not read before new data is received. + 0 + + + IGNORE + Ignore received data. Received data is ignored, allowing transmission without reading unneeded received data. No receiver flags are generated. + 0x1 + + + + + LEN + Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5 bits in length. 0xF = Data transfer is 16 bits in length. + 24 + 4 + write-only + + + + + FIFORD + FIFO read data. + 0xE30 + 32 + read-only + 0 + 0xE1FF + + + RXDATA + Received data from the FIFO. + 0 + 16 + read-only + + + RXSSEL0_N + Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG. + 16 + 1 + read-only + + + RXSSEL1_N + Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG. + 17 + 1 + read-only + + + RXSSEL2_N + Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG. + 18 + 1 + read-only + + + RXSSEL3_N + Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG. + 19 + 1 + read-only + + + SOT + Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e., any previous transfer has ended). This information can be used to identify the first piece of data in cases where the transfer length is greater than 16 bits. + 20 + 1 + read-only + + + + + FIFORDNOPOP + FIFO data read with no FIFO pop. + 0xE40 + 32 + read-only + 0 + 0xE1FF + + + RXDATA + Received data from the FIFO. + 0 + 16 + read-only + + + RXSSEL0_N + Slave Select for receive. + 16 + 1 + read-only + + + RXSSEL1_N + Slave Select for receive. + 17 + 1 + read-only + + + RXSSEL2_N + Slave Select for receive. + 18 + 1 + read-only + + + RXSSEL3_N + Slave Select for receive. + 19 + 1 + read-only + + + SOT + Start of transfer flag. + 20 + 1 + read-only + + + + + ID + Peripheral identification register. + 0xFFC + 32 + read-only + 0 + 0xFFFFFFFF + + + APERTURE + Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture. + 0 + 8 + read-only + + + MINOR_REV + Minor revision of module implementation. + 8 + 4 + read-only + + + MAJOR_REV + Major revision of module implementation. + 12 + 4 + read-only + + + ID + Module identifier for the selected function. + 16 + 16 + read-only + + + + + + + SPI1 + Serial Peripheral Interfaces (SPI) + FLEXCOMM1 + SPI + 0x40087000 + + 0 + 0x1000 + registers + + + FLEXCOMM1 + 15 + + + + SPI2 + Serial Peripheral Interfaces (SPI) + FLEXCOMM2 + SPI + 0x40088000 + + 0 + 0x1000 + registers + + + FLEXCOMM2 + 16 + + + + SPI3 + Serial Peripheral Interfaces (SPI) + FLEXCOMM3 + SPI + 0x40089000 + + 0 + 0x1000 + registers + + + FLEXCOMM3 + 17 + + + + SPI4 + Serial Peripheral Interfaces (SPI) + FLEXCOMM4 + SPI + 0x4008A000 + + 0 + 0x1000 + registers + + + FLEXCOMM4 + 18 + + + + SPI5 + Serial Peripheral Interfaces (SPI) + FLEXCOMM5 + SPI + 0x40096000 + + 0 + 0x1000 + registers + + + FLEXCOMM5 + 19 + + + + SPI6 + Serial Peripheral Interfaces (SPI) + FLEXCOMM6 + SPI + 0x40097000 + + 0 + 0x1000 + registers + + + FLEXCOMM6 + 20 + + + + SPI7 + Serial Peripheral Interfaces (SPI) + FLEXCOMM7 + SPI + 0x40098000 + + 0 + 0x1000 + registers + + + FLEXCOMM7 + 21 + + + + SPI8 + Serial Peripheral Interfaces (SPI) + FLEXCOMM8 + SPI + 0x4009F000 + + 0 + 0x1000 + registers + + + FLEXCOMM8 + 59 + + + + USART0 + USARTs + FLEXCOMM0 + USART + USART + 0x40086000 + + 0 + 0x1000 + registers + + + FLEXCOMM0 + 14 + + + + CFG + USART Configuration register. Basic USART configuration settings that typically are not changed during operation. + 0 + 32 + read-write + 0 + 0xFDDBFD + + + ENABLE + USART Enable. + 0 + 1 + read-write + + + DISABLED + Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0, all USART interrupts and DMA transfers are disabled. When Enable is set again, CFG and most other control bits remain unchanged. When re-enabled, the USART will immediately be ready to transmit because the transmitter has been reset and is therefore available. + 0 + + + ENABLED + Enabled. The USART is enabled for operation. + 0x1 + + + + + DATALEN + Selects the data size for the USART. + 2 + 2 + read-write + + + BIT_7 + 7 bit Data length. + 0 + + + BIT_8 + 8 bit Data length. + 0x1 + + + BIT_9 + 9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET bit in the CTL register. + 0x2 + + + + + PARITYSEL + Selects what type of parity is used by the USART. + 4 + 2 + read-write + + + NO_PARITY + No parity. + 0 + + + EVEN_PARITY + Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even, and the number of 1s in a received character is expected to be even. + 0x2 + + + ODD_PARITY + Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd, and the number of 1s in a received character is expected to be odd. + 0x3 + + + + + STOPLEN + Number of stop bits appended to transmitted data. Only a single stop bit is required for received data. + 6 + 1 + read-write + + + BIT_1 + 1 stop bit. + 0 + + + BITS_2 + 2 stop bits. This setting should only be used for asynchronous communication. + 0x1 + + + + + MODE32K + Selects standard or 32 kHz clocking mode. + 7 + 1 + read-write + + + DISABLED + Disabled. USART uses standard clocking. + 0 + + + ENABLED + Enabled. USART uses the 32 kHz clock from the RTC oscillator as the clock source to the BRG, and uses a special bit clocking scheme. + 0x1 + + + + + LINMODE + LIN break mode enable. + 8 + 1 + read-write + + + DISABLED + Disabled. Break detect and generate is configured for normal operation. + 0 + + + ENABLED + Enabled. Break detect and generate is configured for LIN bus operation. + 0x1 + + + + + CTSEN + CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin, or from the USART's own RTS if loopback mode is enabled. + 9 + 1 + read-write + + + DISABLED + No flow control. The transmitter does not receive any automatic flow control signal. + 0 + + + ENABLED + Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes. + 0x1 + + + + + SYNCEN + Selects synchronous or asynchronous operation. + 11 + 1 + read-write + + + ASYNCHRONOUS_MODE + Asynchronous mode. + 0 + + + SYNCHRONOUS_MODE + Synchronous mode. + 0x1 + + + + + CLKPOL + Selects the clock polarity and sampling edge of received data in synchronous mode. + 12 + 1 + read-write + + + FALLING_EDGE + Falling edge. Un_RXD is sampled on the falling edge of SCLK. + 0 + + + RISING_EDGE + Rising edge. Un_RXD is sampled on the rising edge of SCLK. + 0x1 + + + + + SYNCMST + Synchronous mode Master select. + 14 + 1 + read-write + + + SLAVE + Slave. When synchronous mode is enabled, the USART is a slave. + 0 + + + MASTER + Master. When synchronous mode is enabled, the USART is a master. + 0x1 + + + + + LOOP + Selects data loopback mode. + 15 + 1 + read-write + + + NORMAL + Normal operation. + 0 + + + LOOPBACK + Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD and Un_RTS activity will also appear on external pins if these functions are configured to appear on device pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN. + 0x1 + + + + + OETA + Output Enable Turnaround time enable for RS-485 operation. + 18 + 1 + read-write + + + DISABLED + Disabled. If selected by OESEL, the Output Enable signal deasserted at the end of the last stop bit of a transmission. + 0 + + + ENABLED + Enabled. If selected by OESEL, the Output Enable signal remains asserted for one character time after the end of the last stop bit of a transmission. OE will also remain asserted if another transmit begins before it is deasserted. + 0x1 + + + + + AUTOADDR + Automatic Address matching enable. + 19 + 1 + read-write + + + DISABLED + Disabled. When addressing is enabled by ADDRDET, address matching is done by software. This provides the possibility of versatile addressing (e.g. respond to more than one address). + 0 + + + ENABLED + Enabled. When addressing is enabled by ADDRDET, address matching is done by hardware, using the value in the ADDR register as the address to match. + 0x1 + + + + + OESEL + Output Enable Select. + 20 + 1 + read-write + + + STANDARD + Standard. The RTS signal is used as the standard flow control function. + 0 + + + RS_485 + RS-485. The RTS signal configured to provide an output enable signal to control an RS-485 transceiver. + 0x1 + + + + + OEPOL + Output Enable Polarity. + 21 + 1 + read-write + + + LOW + Low. If selected by OESEL, the output enable is active low. + 0 + + + HIGH + High. If selected by OESEL, the output enable is active high. + 0x1 + + + + + RXPOL + Receive data polarity. + 22 + 1 + read-write + + + STANDARD + Standard. The RX signal is used as it arrives from the pin. This means that the RX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1. + 0 + + + INVERTED + Inverted. The RX signal is inverted before being used by the USART. This means that the RX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0. + 0x1 + + + + + TXPOL + Transmit data polarity. + 23 + 1 + read-write + + + STANDARD + Standard. The TX signal is sent out without change. This means that the TX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1. + 0 + + + INVERTED + Inverted. The TX signal is inverted by the USART before being sent out. This means that the TX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0. + 0x1 + + + + + + + CTL + USART Control register. USART control settings that are more likely to change during operation. + 0x4 + 32 + read-write + 0 + 0x10346 + + + TXBRKEN + Break Enable. + 1 + 1 + read-write + + + NORMAL + Normal operation. + 0 + + + CONTINOUS + Continuous break. Continuous break is sent immediately when this bit is set, and remains until this bit is cleared. A break may be sent without danger of corrupting any currently transmitting character if the transmitter is first disabled (TXDIS in CTL is set) and then waiting for the transmitter to be disabled (TXDISINT in STAT = 1) before writing 1 to TXBRKEN. + 0x1 + + + + + ADDRDET + Enable address detect mode. + 2 + 1 + read-write + + + DISABLED + Disabled. The USART presents all incoming data. + 0 + + + ENABLED + Enabled. The USART receiver ignores incoming data that does not have the most significant bit of the data (typically the 9th bit) = 1. When the data MSB bit = 1, the receiver treats the incoming data normally, generating a received data interrupt. Software can then check the data to see if this is an address that should be handled. If it is, the ADDRDET bit is cleared by software and further incoming data is handled normally. + 0x1 + + + + + TXDIS + Transmit Disable. + 6 + 1 + read-write + + + ENABLED + Not disabled. USART transmitter is not disabled. + 0 + + + DISABLED + Disabled. USART transmitter is disabled after any character currently being transmitted is complete. This feature can be used to facilitate software flow control. + 0x1 + + + + + CC + Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode. + 8 + 1 + read-write + + + CLOCK_ON_CHARACTER + Clock on character. In synchronous mode, SCLK cycles only when characters are being sent on Un_TXD or to complete a character that is being received. + 0 + + + CONTINOUS_CLOCK + Continuous clock. SCLK runs continuously in synchronous mode, allowing characters to be received on Un_RxD independently from transmission on Un_TXD). + 0x1 + + + + + CLRCCONRX + Clear Continuous Clock. + 9 + 1 + read-write + + + NO_EFFECT + No effect. No effect on the CC bit. + 0 + + + AUTO_CLEAR + Auto-clear. The CC bit is automatically cleared when a complete character has been received. This bit is cleared at the same time. + 0x1 + + + + + AUTOBAUD + Autobaud enable. + 16 + 1 + read-write + + + DISABLED + Disabled. USART is in normal operating mode. + 0 + + + ENABLED + Enabled. USART is in autobaud mode. This bit should only be set when the USART receiver is idle. The first start bit of RX is measured and used the update the BRG register to match the received data rate. AUTOBAUD is cleared once this process is complete, or if there is an AERR. + 0x1 + + + + + + + STAT + USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them. + 0x8 + 32 + read-write + 0xA + 0x45A + + + RXIDLE + Receiver Idle. When 0, indicates that the receiver is currently in the process of receiving data. When 1, indicates that the receiver is not currently in the process of receiving data. + 1 + 1 + read-only + + + TXIDLE + Transmitter Idle. When 0, indicates that the transmitter is currently in the process of sending data.When 1, indicate that the transmitter is not currently in the process of sending data. + 3 + 1 + read-only + + + CTS + This bit reflects the current state of the CTS signal, regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled. + 4 + 1 + read-only + + + DELTACTS + This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software. + 5 + 1 + write-only + + + TXDISSTAT + Transmitter Disabled Status flag. When 1, this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1). + 6 + 1 + read-only + + + RXBRK + Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the character would be missing. RXBRK is cleared when the Un_RXD pin goes high. + 10 + 1 + read-only + + + DELTARXBRK + This bit is set when a change in the state of receiver break detection occurs. Cleared by software. + 11 + 1 + write-only + + + START + This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software. + 12 + 1 + write-only + + + FRAMERRINT + Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source. + 13 + 1 + write-only + + + PARITYERRINT + Parity Error interrupt flag. This flag is set when a parity error is detected in a received character. + 14 + 1 + write-only + + + RXNOISEINT + Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit, except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a received data bit contains one disagreeing sample. This could indicate line noise, a baud rate or character format mismatch, or loss of synchronization during data reception. + 15 + 1 + write-only + + + ABERR + Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured, essentially an auto baud time-out. + 16 + 1 + write-only + + + + + INTENSET + Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. + 0xC + 32 + read-write + 0 + 0x1F868 + + + TXIDLEEN + When 1, enables an interrupt when the transmitter becomes idle (TXIDLE = 1). + 3 + 1 + read-write + + + DELTACTSEN + When 1, enables an interrupt when there is a change in the state of the CTS input. + 5 + 1 + read-write + + + TXDISEN + When 1, enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details. + 6 + 1 + read-write + + + DELTARXBRKEN + When 1, enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted). + 11 + 1 + read-write + + + STARTEN + When 1, enables an interrupt when a received start bit has been detected. + 12 + 1 + read-write + + + FRAMERREN + When 1, enables an interrupt when a framing error has been detected. + 13 + 1 + read-write + + + PARITYERREN + When 1, enables an interrupt when a parity error has been detected. + 14 + 1 + read-write + + + RXNOISEEN + When 1, enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354. + 15 + 1 + read-write + + + ABERREN + When 1, enables an interrupt when an auto baud error occurs. + 16 + 1 + read-write + + + + + INTENCLR + Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared. + 0x10 + 32 + write-only + 0 + 0 + + + TXIDLECLR + Writing 1 clears the corresponding bit in the INTENSET register. + 3 + 1 + write-only + + + DELTACTSCLR + Writing 1 clears the corresponding bit in the INTENSET register. + 5 + 1 + write-only + + + TXDISCLR + Writing 1 clears the corresponding bit in the INTENSET register. + 6 + 1 + write-only + + + DELTARXBRKCLR + Writing 1 clears the corresponding bit in the INTENSET register. + 11 + 1 + write-only + + + STARTCLR + Writing 1 clears the corresponding bit in the INTENSET register. + 12 + 1 + write-only + + + FRAMERRCLR + Writing 1 clears the corresponding bit in the INTENSET register. + 13 + 1 + write-only + + + PARITYERRCLR + Writing 1 clears the corresponding bit in the INTENSET register. + 14 + 1 + write-only + + + RXNOISECLR + Writing 1 clears the corresponding bit in the INTENSET register. + 15 + 1 + write-only + + + ABERRCLR + Writing 1 clears the corresponding bit in the INTENSET register. + 16 + 1 + write-only + + + + + BRG + Baud Rate Generator register. 16-bit integer baud rate divisor value. + 0x20 + 32 + read-write + 0 + 0xFFFF + + + BRGVAL + This value is used to divide the USART input clock to determine the baud rate, based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided by 3 before use by the USART function. 0xFFFF = FCLK is divided by 65,536 before use by the USART function. + 0 + 16 + read-write + + + + + INTSTAT + Interrupt status register. Reflects interrupts that are currently enabled. + 0x24 + 32 + read-only + 0 + 0x1F968 + + + TXIDLE + Transmitter Idle status. + 3 + 1 + read-only + + + DELTACTS + This bit is set when a change in the state of the CTS input is detected. + 5 + 1 + read-only + + + TXDISINT + Transmitter Disabled Interrupt flag. + 6 + 1 + read-only + + + DELTARXBRK + This bit is set when a change in the state of receiver break detection occurs. + 11 + 1 + read-only + + + START + This bit is set when a start is detected on the receiver input. + 12 + 1 + read-only + + + FRAMERRINT + Framing Error interrupt flag. + 13 + 1 + read-only + + + PARITYERRINT + Parity Error interrupt flag. + 14 + 1 + read-only + + + RXNOISEINT + Received Noise interrupt flag. + 15 + 1 + read-only + + + ABERRINT + Auto baud Error Interrupt flag. + 16 + 1 + read-only + + + + + OSR + Oversample selection register for asynchronous communication. + 0x28 + 32 + read-write + 0xF + 0xF + + + OSRVAL + Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and receive each data bit. + 0 + 4 + read-write + + + + + ADDR + Address register for automatic address matching. + 0x2C + 32 + read-write + 0 + 0xFF + + + ADDRESS + 8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1). + 0 + 8 + read-write + + + + + FIFOCFG + FIFO configuration and enable register. + 0xE00 + 32 + read-write + 0 + 0x7F033 + + + ENABLETX + Enable the transmit FIFO. + 0 + 1 + read-write + + + DISABLED + The transmit FIFO is not enabled. + 0 + + + ENABLED + The transmit FIFO is enabled. + 0x1 + + + + + ENABLERX + Enable the receive FIFO. + 1 + 1 + read-write + + + DISABLED + The receive FIFO is not enabled. + 0 + + + ENABLED + The receive FIFO is enabled. + 0x1 + + + + + SIZE + FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART. + 4 + 2 + read-only + + + DMATX + DMA configuration for transmit. + 12 + 1 + read-write + + + DISABLED + DMA is not used for the transmit function. + 0 + + + ENABLED + Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. + 0x1 + + + + + DMARX + DMA configuration for receive. + 13 + 1 + read-write + + + DISABLED + DMA is not used for the receive function. + 0 + + + ENABLED + Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. + 0x1 + + + + + WAKETX + Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register. + 14 + 1 + read-write + + + DISABLED + Only enabled interrupts will wake up the device form reduced power modes. + 0 + + + ENABLED + A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in FIFOTRIG, even when the TXLVL interrupt is not enabled. + 0x1 + + + + + WAKERX + Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register. + 15 + 1 + read-write + + + DISABLED + Only enabled interrupts will wake up the device form reduced power modes. + 0 + + + ENABLED + A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in FIFOTRIG, even when the RXLVL interrupt is not enabled. + 0x1 + + + + + EMPTYTX + Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied. + 16 + 1 + read-write + + + EMPTYRX + Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied. + 17 + 1 + read-write + + + POPDBG + Pop FIFO for debug reads. + 18 + 1 + read-write + + + DO_NOT_POP + Debug reads of the FIFO do not pop the FIFO. + 0 + + + POP + A debug read will cause the FIFO to pop. + 0x1 + + + + + + + FIFOSTAT + FIFO status register. + 0xE04 + 32 + read-write + 0x30 + 0x1F1FFB + + + TXERR + TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit. + 0 + 1 + read-write + + + RXERR + RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit. + 1 + 1 + read-write + + + PERINT + Peripheral interrupt. When 1, this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register. + 3 + 1 + read-only + + + TXEMPTY + Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data. + 4 + 1 + read-only + + + TXNOTFULL + Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be written. When 0, the transmit FIFO is full and another write would cause it to overflow. + 5 + 1 + read-only + + + RXNOTEMPTY + Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty. + 6 + 1 + read-only + + + RXFULL + Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow. + 7 + 1 + read-only + + + TXLVL + Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be 0. + 8 + 5 + read-only + + + RXLVL + Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be 1. + 16 + 5 + read-only + + + + + FIFOTRIG + FIFO trigger settings for interrupt and DMA request. + 0xE08 + 32 + read-write + 0 + 0xF0F03 + + + TXLVLENA + Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set. + 0 + 1 + read-write + + + DISABLED + Transmit FIFO level does not generate a FIFO level trigger. + 0 + + + ENABLED + An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register. + 0x1 + + + + + RXLVLENA + Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. + 1 + 1 + read-write + + + DISABLED + Receive FIFO level does not generate a FIFO level trigger. + 0 + + + ENABLED + An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. + 0x1 + + + + + TXLVL + Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX FIFO level decreases to 15 entries (is no longer full). + 8 + 4 + read-write + + + RXLVL + Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX FIFO has received 16 entries (has become full). + 16 + 4 + read-write + + + + + FIFOINTENSET + FIFO interrupt enable set (enable) and read register. + 0xE10 + 32 + read-write + 0 + 0xF + + + TXERR + Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. + 0 + 1 + read-write + + + DISABLED + No interrupt will be generated for a transmit error. + 0 + + + ENABLED + An interrupt will be generated when a transmit error occurs. + 0x1 + + + + + RXERR + Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. + 1 + 1 + read-write + + + DISABLED + No interrupt will be generated for a receive error. + 0 + + + ENABLED + An interrupt will be generated when a receive error occurs. + 0x1 + + + + + TXLVL + Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. + 2 + 1 + read-write + + + DISABLED + No interrupt will be generated based on the TX FIFO level. + 0 + + + ENABLED + If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases to the level specified by TXLVL in the FIFOTRIG register. + 0x1 + + + + + RXLVL + Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. + 3 + 1 + read-write + + + DISABLED + No interrupt will be generated based on the RX FIFO level. + 0 + + + ENABLED + If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level increases to the level specified by RXLVL in the FIFOTRIG register. + 0x1 + + + + + + + FIFOINTENCLR + FIFO interrupt enable clear (disable) and read register. + 0xE14 + 32 + read-write + 0 + 0xF + + + TXERR + Writing one clears the corresponding bits in the FIFOINTENSET register. + 0 + 1 + read-write + + + RXERR + Writing one clears the corresponding bits in the FIFOINTENSET register. + 1 + 1 + read-write + + + TXLVL + Writing one clears the corresponding bits in the FIFOINTENSET register. + 2 + 1 + read-write + + + RXLVL + Writing one clears the corresponding bits in the FIFOINTENSET register. + 3 + 1 + read-write + + + + + FIFOINTSTAT + FIFO interrupt status register. + 0xE18 + 32 + read-only + 0 + 0x1F + + + TXERR + TX FIFO error. + 0 + 1 + read-only + + + RXERR + RX FIFO error. + 1 + 1 + read-only + + + TXLVL + Transmit FIFO level interrupt. + 2 + 1 + read-only + + + RXLVL + Receive FIFO level interrupt. + 3 + 1 + read-only + + + PERINT + Peripheral interrupt. + 4 + 1 + read-only + + + + + FIFOWR + FIFO write data. + 0xE20 + 32 + read-write + 0 + 0 + + + TXDATA + Transmit data to the FIFO. + 0 + 9 + write-only + + + + + FIFORD + FIFO read data. + 0xE30 + 32 + read-only + 0 + 0xE1FF + + + RXDATA + Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings. + 0 + 9 + read-only + + + FRAMERR + Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO, and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source. + 13 + 1 + read-only + + + PARITYERR + Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character. + 14 + 1 + read-only + + + RXNOISE + Received Noise flag. See description of the RxNoiseInt bit in Table 354. + 15 + 1 + read-only + + + + + FIFORDNOPOP + FIFO data read with no FIFO pop. + 0xE40 + 32 + read-only + 0 + 0xE1FF + + + RXDATA + Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings. + 0 + 9 + read-only + + + FRAMERR + Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO, and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source. + 13 + 1 + read-only + + + PARITYERR + Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character. + 14 + 1 + read-only + + + RXNOISE + Received Noise flag. See description of the RxNoiseInt bit in Table 354. + 15 + 1 + read-only + + + + + ID + Peripheral identification register. + 0xFFC + 32 + read-only + 0 + 0xFFFFFFFF + + + APERTURE + Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture. + 0 + 8 + read-only + + + MINOR_REV + Minor revision of module implementation. + 8 + 4 + read-only + + + MAJOR_REV + Major revision of module implementation. + 12 + 4 + read-only + + + ID + Module identifier for the selected function. + 16 + 16 + read-only + + + + + + + USART1 + USARTs + FLEXCOMM1 + USART + 0x40087000 + + 0 + 0x1000 + registers + + + FLEXCOMM1 + 15 + + + + USART2 + USARTs + FLEXCOMM2 + USART + 0x40088000 + + 0 + 0x1000 + registers + + + FLEXCOMM2 + 16 + + + + USART3 + USARTs + FLEXCOMM3 + USART + 0x40089000 + + 0 + 0x1000 + registers + + + FLEXCOMM3 + 17 + + + + USART4 + USARTs + FLEXCOMM4 + USART + 0x4008A000 + + 0 + 0x1000 + registers + + + FLEXCOMM4 + 18 + + + + USART5 + USARTs + FLEXCOMM5 + USART + 0x40096000 + + 0 + 0x1000 + registers + + + FLEXCOMM5 + 19 + + + + USART6 + USARTs + FLEXCOMM6 + USART + 0x40097000 + + 0 + 0x1000 + registers + + + FLEXCOMM6 + 20 + + + + USART7 + USARTs + FLEXCOMM7 + USART + 0x40098000 + + 0 + 0x1000 + registers + + + FLEXCOMM7 + 21 + + + + MAILBOX + Mailbox + MAILBOX + 0x4008B000 + + 0 + 0xFC + registers + + + MAILBOX + 31 + + + + 2 + 0x10 + MBOXIRQ[%s] + no description available + 0 + + IRQ + Interrupt request register for the Cortex-M0+ CPU. + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + INTREQ + If any bit is set, an interrupt request is sent to the Cortex-M0+ interrupt controller. + 0 + 32 + read-write + + + + + IRQSET + Set bits in IRQ0 + 0x4 + 32 + write-only + 0 + 0 + + + INTREQSET + Writing 1 sets the corresponding bit in the IRQ0 register. + 0 + 32 + write-only + + + + + IRQCLR + Clear bits in IRQ0 + 0x8 + 32 + write-only + 0 + 0 + + + INTREQCLR + Writing 1 clears the corresponding bit in the IRQ0 register. + 0 + 32 + write-only + + + + + + MUTEX + Mutual exclusion register[1] + 0xF8 + 32 + read-write + 0x1 + 0x1 + + + EX + Cleared when read, set when written. See usage description above. + 0 + 1 + read-write + + + + + + + GPIO + General Purpose I/O (GPIO) + GPIO + GPIO + 0x4008C000 + + 0 + 0x2490 + registers + + + + 4 + 0x20 + B[%s] + no description available + 0 + + 32 + 0x1 + B_[%s] + Byte pin registers for all port GPIO pins + 0 + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + + 4 + 0x80 + W[%s] + no description available + 0x1000 + + 32 + 0x4 + W_[%s] + Word pin registers for all port GPIO pins + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + + 4 + 0x4 + DIR[%s] + Direction registers for all port GPIO pins + 0x2000 + 32 + read-write + 0 + 0xFFFFFFFF + + + DIRP + Selects pin direction for pin PIOm_n (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = input. 1 = output. + 0 + 32 + read-write + + + + + 4 + 0x4 + MASK[%s] + Mask register for all port GPIO pins + 0x2080 + 32 + read-write + 0 + 0xFFFFFFFF + + + MASKP + Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package.0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. + 0 + 32 + read-write + + + + + 4 + 0x4 + PIN[%s] + Port pin register for all port GPIO pins + 0x2100 + 32 + read-write + 0 + 0xFFFFFFFF + + + PORT + Reads pin states or loads output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. + 0 + 32 + read-write + + + + + 4 + 0x4 + MPIN[%s] + Masked port register for all port GPIO pins + 0x2180 + 32 + read-write + 0 + 0xFFFFFFFF + + + MPORTP + Masked port register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. + 0 + 32 + read-write + + + + + 4 + 0x4 + SET[%s] + Write: Set register for port. Read: output bits for port + 0x2200 + 32 + read-write + 0 + 0xFFFFFFFF + + + SETP + Read or set output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. + 0 + 32 + read-write + + + + + 4 + 0x4 + CLR[%s] + Clear port for all port GPIO pins + 0x2280 + 32 + write-only + 0 + 0 + + + CLRP + Clear output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Clear output bit. + 0 + 32 + write-only + + + + + 4 + 0x4 + NOT[%s] + Toggle port for all port GPIO pins + 0x2300 + 32 + write-only + 0 + 0 + + + NOTP + Toggle output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = no operation. 1 = Toggle output bit. + 0 + 32 + write-only + + + + + 4 + 0x4 + DIRSET[%s] + Set pin direction bits for port + 0x2380 + 32 + write-only + 0 + 0 + + + DIRSETP + Set direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Set direction bit. + 0 + 29 + write-only + + + + + 4 + 0x4 + DIRCLR[%s] + Clear pin direction bits for port + 0x2400 + 32 + write-only + 0 + 0 + + + DIRCLRP + Clear direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Clear direction bit. + 0 + 29 + write-only + + + + + 4 + 0x4 + DIRNOT[%s] + Toggle pin direction bits for port + 0x2480 + 32 + write-only + 0 + 0 + + + DIRNOTP + Toggle direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = no operation. 1 = Toggle direction bit. + 0 + 29 + write-only + + + + + + + SECGPIO + General Purpose I/O (GPIO) + GPIO + 0x400A8000 + + 0 + 0x2490 + registers + + + + USBHSD + USB1 High-speed Device Controller + USBHSD + 0x40094000 + + 0 + 0x40 + registers + + + USB1_UTMI + 46 + + + USB1 + 47 + + + USB1_NEEDCLK + 48 + + + + DEVCMDSTAT + USB Device Command/Status register + 0 + 32 + read-write + 0x800 + 0xF7DBFFFF + + + DEV_ADDR + USB device address. + 0 + 7 + read-write + + + DEV_EN + USB device enable. + 7 + 1 + read-write + + + SETUP + SETUP token received. + 8 + 1 + read-write + + + FORCE_NEEDCLK + Forces the NEEDCLK output to always be on:. + 9 + 1 + read-write + + + FORCE_VBUS + If this bit is set to 1, the VBUS voltage indicators from the PHY are overruled. + 10 + 1 + read-write + + + LPM_SUP + LPM Supported:. + 11 + 1 + read-write + + + INTONNAK_AO + Interrupt on NAK for interrupt and bulk OUT EP:. + 12 + 1 + read-write + + + INTONNAK_AI + Interrupt on NAK for interrupt and bulk IN EP:. + 13 + 1 + read-write + + + INTONNAK_CO + Interrupt on NAK for control OUT EP:. + 14 + 1 + read-write + + + INTONNAK_CI + Interrupt on NAK for control IN EP:. + 15 + 1 + read-write + + + DCON + Device status - connect. + 16 + 1 + read-write + + + DSUS + Device status - suspend. + 17 + 1 + read-write + + + LPM_SUS + Device status - LPM Suspend. + 19 + 1 + read-write + + + LPM_REWP + LPM Remote Wake-up Enabled by USB host. + 20 + 1 + read-only + + + Speed + This field indicates the speed at which the device operates: 00b: reserved 01b: full-speed 10b: high-speed 11b: super-speed (reserved for future use). + 22 + 2 + read-only + + + DCON_C + Device status - connect change. + 24 + 1 + read-write + + + DSUS_C + Device status - suspend change. + 25 + 1 + read-write + + + DRES_C + Device status - reset change. + 26 + 1 + read-write + + + VBUS_DEBOUNCED + This bit indicates if VBUS is detected or not. + 28 + 1 + read-only + + + PHY_TEST_MODE + This field is written by firmware to put the PHY into a test mode as defined by the USB2. + 29 + 3 + read-write + + + + + INFO + USB Info register + 0x4 + 32 + read-only + 0x2000000 + 0xFFFF7FFF + + + FRAME_NR + Frame number. + 0 + 11 + read-only + + + ERR_CODE + The error code which last occurred:. + 11 + 4 + read-only + + + Minrev + Minor revision. + 16 + 8 + read-only + + + Majrev + Major revision. + 24 + 8 + read-only + + + + + EPLISTSTART + USB EP Command/Status List start address + 0x8 + 32 + read-write + 0 + 0xFFFFFF00 + + + EP_LIST_PRG + Programmable portion of the USB EP Command/Status List address. + 8 + 12 + read-write + + + EP_LIST_FIXED + Fixed portion of USB EP Command/Status List address. + 20 + 12 + read-only + + + + + DATABUFSTART + USB Data buffer start address + 0xC + 32 + read-write + 0x41000000 + 0xFFFFFFFF + + + DA_BUF + Start address of the memory page where all endpoint data buffers are located. + 0 + 32 + read-write + + + + + LPM + USB Link Power Management register + 0x10 + 32 + read-write + 0 + 0x1FF + + + HIRD_HW + Host Initiated Resume Duration - HW. + 0 + 4 + read-only + + + HIRD_SW + Host Initiated Resume Duration - SW. + 4 + 4 + read-write + + + DATA_PENDING + As long as this bit is set to one and LPM supported bit is set to one, HW will return a NYET handshake on every LPM token it receives. + 8 + 1 + read-write + + + + + EPSKIP + USB Endpoint skip + 0x14 + 32 + read-write + 0 + 0xFFF + + + SKIP + Endpoint skip: Writing 1 to one of these bits, will indicate to HW that it must deactivate the buffer assigned to this endpoint and return control back to software. + 0 + 12 + read-write + + + + + EPINUSE + USB Endpoint Buffer in use + 0x18 + 32 + read-write + 0 + 0xFFC + + + BUF + Buffer in use: This register has one bit per physical endpoint. + 2 + 10 + read-write + + + + + EPBUFCFG + USB Endpoint Buffer Configuration register + 0x1C + 32 + read-write + 0 + 0xFFC + + + BUF_SB + Buffer usage: This register has one bit per physical endpoint. + 2 + 10 + read-write + + + + + INTSTAT + USB interrupt status register + 0x20 + 32 + read-write + 0 + 0xC0000FFF + + + EP0OUT + Interrupt status register bit for the Control EP0 OUT direction. + 0 + 1 + read-write + + + EP0IN + Interrupt status register bit for the Control EP0 IN direction. + 1 + 1 + read-write + + + EP1OUT + Interrupt status register bit for the EP1 OUT direction. + 2 + 1 + read-write + + + EP1IN + Interrupt status register bit for the EP1 IN direction. + 3 + 1 + read-write + + + EP2OUT + Interrupt status register bit for the EP2 OUT direction. + 4 + 1 + read-write + + + EP2IN + Interrupt status register bit for the EP2 IN direction. + 5 + 1 + read-write + + + EP3OUT + Interrupt status register bit for the EP3 OUT direction. + 6 + 1 + read-write + + + EP3IN + Interrupt status register bit for the EP3 IN direction. + 7 + 1 + read-write + + + EP4OUT + Interrupt status register bit for the EP4 OUT direction. + 8 + 1 + read-write + + + EP4IN + Interrupt status register bit for the EP4 IN direction. + 9 + 1 + read-write + + + EP5OUT + Interrupt status register bit for the EP5 OUT direction. + 10 + 1 + read-write + + + EP5IN + Interrupt status register bit for the EP5 IN direction. + 11 + 1 + read-write + + + FRAME_INT + Frame interrupt. + 30 + 1 + read-write + + + DEV_INT + Device status interrupt. + 31 + 1 + read-write + + + + + INTEN + USB interrupt enable register + 0x24 + 32 + read-write + 0 + 0xC0000FFF + + + EP_INT_EN + If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line. + 0 + 12 + read-write + + + FRAME_INT_EN + If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line. + 30 + 1 + read-write + + + DEV_INT_EN + If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line. + 31 + 1 + read-write + + + + + INTSETSTAT + USB set interrupt status register + 0x28 + 32 + read-write + 0 + 0xC0000FFF + + + EP_SET_INT + If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. + 0 + 12 + read-write + + + FRAME_SET_INT + If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. + 30 + 1 + read-write + + + DEV_SET_INT + If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. + 31 + 1 + read-write + + + + + EPTOGGLE + USB Endpoint toggle register + 0x34 + 32 + read-only + 0 + 0x3FFFFFFF + + + TOGGLE + Endpoint data toggle: This field indicates the current value of the data toggle for the corresponding endpoint. + 0 + 30 + read-only + + + + + ULPIDEBUG + UTMI/ULPI debug register + 0x3C + 32 + read-write + 0 + 0x83FFFFFF + + + PHY_ADDR + ULPI mode: Bits 7:0 are used as the address when doing a register access over the ULPI interface. + 0 + 8 + read-write + + + PHY_WDATA + UTMI+ mode: Reserved. + 8 + 8 + read-write + + + PHY_RDATA + UTMI+ mode: Bits 7:0 contains the value returned by the VStatus signal on Vendor Interface of UTMI+. + 16 + 8 + read-write + + + PHY_RW + UTMI+ mode: Reserved. + 24 + 1 + read-write + + + PHY_ACCESS + Software writes this bit to one to start a read or write operation. + 25 + 1 + read-write + + + PHY_MODE + This bit indicates if the interface between the controller is UTMI+ or ULPI. + 31 + 1 + read-write + + + + + + + CRC_ENGINE + CRC engine + CRC + 0x40095000 + + 0 + 0xC + registers + + + + MODE + CRC mode register + 0 + 32 + read-write + 0 + 0x3F + + + CRC_POLY + CRC polynomial: 1X = CRC-32 polynomial 01 = CRC-16 polynomial 00 = CRC-CCITT polynomial + 0 + 2 + read-write + + + BIT_RVS_WR + Data bit order: 1 = Bit order reverse for CRC_WR_DATA (per byte) 0 = No bit order reverse for CRC_WR_DATA (per byte) + 2 + 1 + read-write + + + CMPL_WR + Data complement: 1 = 1's complement for CRC_WR_DATA 0 = No 1's complement for CRC_WR_DATA + 3 + 1 + read-write + + + BIT_RVS_SUM + CRC sum bit order: 1 = Bit order reverse for CRC_SUM 0 = No bit order reverse for CRC_SUM + 4 + 1 + read-write + + + CMPL_SUM + CRC sum complement: 1 = 1's complement for CRC_SUM 0 = No 1's complement for CRC_SUM + 5 + 1 + read-write + + + + + SEED + CRC seed register + 0x4 + 32 + read-write + 0xFFFF + 0xFFFFFFFF + + + CRC_SEED + A write access to this register will load CRC seed value to CRC_SUM register with selected bit order and 1's complement pre-processes. A write access to this register will overrule the CRC calculation in progresses. + 0 + 32 + read-write + + + + + SUM + CRC checksum register + SUM_WR_DATA + 0x8 + 32 + read-only + 0xFFFF + 0xFFFFFFFF + + + CRC_SUM + The most recent CRC sum can be read through this register with selected bit order and 1's complement post-processes. + 0 + 32 + read-only + + + + + WR_DATA + CRC data register + SUM_WR_DATA + 0x8 + 32 + write-only + 0 + 0 + + + CRC_WR_DATA + Data written to this register will be taken to perform CRC calculation with selected bit order and 1's complement pre-process. Any write size 8, 16 or 32-bit are allowed and accept back-to-back transactions. + 0 + 32 + write-only + + + + + + + SDIF + SDMMC + SDIF + 0x4009B000 + + 0 + 0x300 + registers + + + SDIO + 42 + + + + CTRL + Control register + 0 + 32 + read-write + 0 + 0x2070FD7 + + + CONTROLLER_RESET + Controller reset. + 0 + 1 + read-write + + + FIFO_RESET + Fifo reset. + 1 + 1 + read-write + + + DMA_RESET + DMA reset. + 2 + 1 + read-write + + + INT_ENABLE + Global interrupt enable/disable bit. + 4 + 1 + read-write + + + READ_WAIT + Read/wait. + 6 + 1 + read-write + + + SEND_IRQ_RESPONSE + Send irq response. + 7 + 1 + read-write + + + ABORT_READ_DATA + Abort read data. + 8 + 1 + read-write + + + SEND_CCSD + Send ccsd. + 9 + 1 + read-write + + + SEND_AUTO_STOP_CCSD + Send auto stop ccsd. + 10 + 1 + read-write + + + CEATA_DEVICE_INTERRUPT_STATUS + CEATA device interrupt status. + 11 + 1 + read-write + + + CARD_VOLTAGE_A0 + Controls the state of the SD_VOLT0 pin. + 16 + 1 + read-write + + + CARD_VOLTAGE_A1 + Controls the state of the SD_VOLT1 pin. + 17 + 1 + read-write + + + CARD_VOLTAGE_A2 + Controls the state of the SD_VOLT2 pin. + 18 + 1 + read-write + + + USE_INTERNAL_DMAC + SD/MMC DMA use. + 25 + 1 + read-write + + + + + PWREN + Power Enable register + 0x4 + 32 + read-write + 0 + 0x3 + + + POWER_ENABLE0 + Power on/off switch for card 0; once power is turned on, software should wait for regulator/switch ramp-up time before trying to initialize card 0. + 0 + 1 + read-write + + + POWER_ENABLE1 + Power on/off switch for card 1; once power is turned on, software should wait for regulator/switch ramp-up time before trying to initialize card 1. + 1 + 1 + read-write + + + + + CLKDIV + Clock Divider register + 0x8 + 32 + read-write + 0 + 0xFF + + + CLK_DIVIDER0 + Clock divider-0 value. + 0 + 8 + read-write + + + + + CLKENA + Clock Enable register + 0x10 + 32 + read-write + 0 + 0x30003 + + + CCLK0_ENABLE + Clock-enable control for SD card 0 clock. + 0 + 1 + read-write + + + CCLK1_ENABLE + Clock-enable control for SD card 1 clock. + 1 + 1 + read-write + + + CCLK0_LOW_POWER + Low-power control for SD card 0 clock. + 16 + 1 + read-write + + + CCLK1_LOW_POWER + Low-power control for SD card 1 clock. + 17 + 1 + read-write + + + + + TMOUT + Time-out register + 0x14 + 32 + read-write + 0xFFFFFF40 + 0xFFFFFFFF + + + RESPONSE_TIMEOUT + Response time-out value. + 0 + 8 + read-write + + + DATA_TIMEOUT + Value for card Data Read time-out; same value also used for Data Starvation by Host time-out. + 8 + 24 + read-write + + + + + CTYPE + Card Type register + 0x18 + 32 + read-write + 0 + 0x30003 + + + CARD0_WIDTH0 + Indicates if card 0 is 1-bit or 4-bit: 0 - 1-bit mode 1 - 4-bit mode 1 and 4-bit modes only work when 8-bit mode in CARD0_WIDTH1 is not enabled (bit 16 in this register is set to 0). + 0 + 1 + read-write + + + CARD1_WIDTH0 + Indicates if card 1 is 1-bit or 4-bit: 0 - 1-bit mode 1 - 4-bit mode 1 and 4-bit modes only work when 8-bit mode in CARD1_WIDTH1 is not enabled (bit 16 in this register is set to 0). + 1 + 1 + read-write + + + CARD0_WIDTH1 + Indicates if card 0 is 8-bit: 0 - Non 8-bit mode 1 - 8-bit mode. + 16 + 1 + read-write + + + CARD1_WIDTH1 + Indicates if card 1 is 8-bit: 0 - Non 8-bit mode 1 - 8-bit mode. + 17 + 1 + read-write + + + + + BLKSIZ + Block Size register + 0x1C + 32 + read-write + 0x200 + 0xFFFF + + + BLOCK_SIZE + Block size. + 0 + 16 + read-write + + + + + BYTCNT + Byte Count register + 0x20 + 32 + read-write + 0x200 + 0xFFFFFFFF + + + BYTE_COUNT + Number of bytes to be transferred; should be integer multiple of Block Size for block transfers. + 0 + 32 + read-write + + + + + INTMASK + Interrupt Mask register + 0x24 + 32 + read-write + 0 + 0x1FFFF + + + CDET + Card detect. + 0 + 1 + read-write + + + RE + Response error. + 1 + 1 + read-write + + + CDONE + Command done. + 2 + 1 + read-write + + + DTO + Data transfer over. + 3 + 1 + read-write + + + TXDR + Transmit FIFO data request. + 4 + 1 + read-write + + + RXDR + Receive FIFO data request. + 5 + 1 + read-write + + + RCRC + Response CRC error. + 6 + 1 + read-write + + + DCRC + Data CRC error. + 7 + 1 + read-write + + + RTO + Response time-out. + 8 + 1 + read-write + + + DRTO + Data read time-out. + 9 + 1 + read-write + + + HTO + Data starvation-by-host time-out (HTO). + 10 + 1 + read-write + + + FRUN + FIFO underrun/overrun error. + 11 + 1 + read-write + + + HLE + Hardware locked write error. + 12 + 1 + read-write + + + SBE + Start-bit error. + 13 + 1 + read-write + + + ACD + Auto command done. + 14 + 1 + read-write + + + EBE + End-bit error (read)/Write no CRC. + 15 + 1 + read-write + + + SDIO_INT_MASK + Mask SDIO interrupt. + 16 + 1 + read-write + + + + + CMDARG + Command Argument register + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + CMD_ARG + Value indicates command argument to be passed to card. + 0 + 32 + read-write + + + + + CMD + Command register + 0x2C + 32 + read-write + 0 + 0xBFFFFFFF + + + CMD_INDEX + Command index. + 0 + 6 + read-write + + + RESPONSE_EXPECT + Response expect. + 6 + 1 + read-write + + + RESPONSE_LENGTH + Response length. + 7 + 1 + read-write + + + CHECK_RESPONSE_CRC + Check response CRC. + 8 + 1 + read-write + + + DATA_EXPECTED + Data expected. + 9 + 1 + read-write + + + READ_WRITE + read/write. + 10 + 1 + read-write + + + TRANSFER_MODE + Transfer mode. + 11 + 1 + read-write + + + SEND_AUTO_STOP + Send auto stop. + 12 + 1 + read-write + + + WAIT_PRVDATA_COMPLETE + Wait prvdata complete. + 13 + 1 + read-write + + + STOP_ABORT_CMD + Stop abort command. + 14 + 1 + read-write + + + SEND_INITIALIZATION + Send initialization. + 15 + 1 + read-write + + + CARD_NUMBER + Specifies the card number of SDCARD for which the current Command is being executed + 16 + 5 + read-write + + + CARD0 + Command will be execute on SDCARD 0 + 0 + + + CARD1 + Command will be execute on SDCARD 1 + 0x1 + + + + + UPDATE_CLOCK_REGISTERS_ONLY + Update clock registers only. + 21 + 1 + read-write + + + READ_CEATA_DEVICE + Read ceata device. + 22 + 1 + read-write + + + CCS_EXPECTED + CCS expected. + 23 + 1 + read-write + + + ENABLE_BOOT + Enable Boot - this bit should be set only for mandatory boot mode. + 24 + 1 + read-write + + + EXPECT_BOOT_ACK + Expect Boot Acknowledge. + 25 + 1 + read-write + + + DISABLE_BOOT + Disable Boot. + 26 + 1 + read-write + + + BOOT_MODE + Boot Mode. + 27 + 1 + read-write + + + VOLT_SWITCH + Voltage switch bit. + 28 + 1 + read-write + + + USE_HOLD_REG + Use Hold Register. + 29 + 1 + read-write + + + START_CMD + Start command. + 31 + 1 + read-write + + + + + 4 + 0x4 + RESP[%s] + Response register + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + RESPONSE + Bits of response. + 0 + 32 + read-write + + + + + MINTSTS + Masked Interrupt Status register + 0x40 + 32 + read-write + 0 + 0x1FFFF + + + CDET + Card detect. + 0 + 1 + read-write + + + RE + Response error. + 1 + 1 + read-write + + + CDONE + Command done. + 2 + 1 + read-write + + + DTO + Data transfer over. + 3 + 1 + read-write + + + TXDR + Transmit FIFO data request. + 4 + 1 + read-write + + + RXDR + Receive FIFO data request. + 5 + 1 + read-write + + + RCRC + Response CRC error. + 6 + 1 + read-write + + + DCRC + Data CRC error. + 7 + 1 + read-write + + + RTO + Response time-out. + 8 + 1 + read-write + + + DRTO + Data read time-out. + 9 + 1 + read-write + + + HTO + Data starvation-by-host time-out (HTO). + 10 + 1 + read-write + + + FRUN + FIFO underrun/overrun error. + 11 + 1 + read-write + + + HLE + Hardware locked write error. + 12 + 1 + read-write + + + SBE + Start-bit error. + 13 + 1 + read-write + + + ACD + Auto command done. + 14 + 1 + read-write + + + EBE + End-bit error (read)/write no CRC. + 15 + 1 + read-write + + + SDIO_INTERRUPT + Interrupt from SDIO card. + 16 + 1 + read-write + + + + + RINTSTS + Raw Interrupt Status register + 0x44 + 32 + read-write + 0 + 0x1FFFF + + + CDET + Card detect. + 0 + 1 + read-write + + + RE + Response error. + 1 + 1 + read-write + + + CDONE + Command done. + 2 + 1 + read-write + + + DTO + Data transfer over. + 3 + 1 + read-write + + + TXDR + Transmit FIFO data request. + 4 + 1 + read-write + + + RXDR + Receive FIFO data request. + 5 + 1 + read-write + + + RCRC + Response CRC error. + 6 + 1 + read-write + + + DCRC + Data CRC error. + 7 + 1 + read-write + + + RTO_BAR + Response time-out (RTO)/Boot Ack Received (BAR). + 8 + 1 + read-write + + + DRTO_BDS + Data read time-out (DRTO)/Boot Data Start (BDS). + 9 + 1 + read-write + + + HTO + Data starvation-by-host time-out (HTO). + 10 + 1 + read-write + + + FRUN + FIFO underrun/overrun error. + 11 + 1 + read-write + + + HLE + Hardware locked write error. + 12 + 1 + read-write + + + SBE + Start-bit error. + 13 + 1 + read-write + + + ACD + Auto command done. + 14 + 1 + read-write + + + EBE + End-bit error (read)/write no CRC. + 15 + 1 + read-write + + + SDIO_INTERRUPT + Interrupt from SDIO card. + 16 + 1 + read-write + + + + + STATUS + Status register + 0x48 + 32 + read-write + 0x406 + 0xFFFFFFFF + + + FIFO_RX_WATERMARK + FIFO reached Receive watermark level; not qualified with data transfer. + 0 + 1 + read-write + + + FIFO_TX_WATERMARK + FIFO reached Transmit watermark level; not qualified with data transfer. + 1 + 1 + read-write + + + FIFO_EMPTY + FIFO is empty status. + 2 + 1 + read-write + + + FIFO_FULL + FIFO is full status. + 3 + 1 + read-write + + + CMDFSMSTATES + Command FSM states: 0 - Idle 1 - Send init sequence 2 - Tx cmd start bit 3 - Tx cmd tx bit 4 - Tx cmd index + arg 5 - Tx cmd crc7 6 - Tx cmd end bit 7 - Rx resp start bit 8 - Rx resp IRQ response 9 - Rx resp tx bit 10 - Rx resp cmd idx 11 - Rx resp data 12 - Rx resp crc7 13 - Rx resp end bit 14 - Cmd path wait NCC 15 - Wait; CMD-to-response turnaround NOTE: The command FSM state is represented using 19 bits. + 4 + 4 + read-write + + + DATA_3_STATUS + Raw selected card_data[3]; checks whether card is present 0 - card not present 1 - card present. + 8 + 1 + read-write + + + DATA_BUSY + Inverted version of raw selected card_data[0] 0 - card data not busy 1 - card data busy. + 9 + 1 + read-write + + + DATA_STATE_MC_BUSY + Data transmit or receive state-machine is busy. + 10 + 1 + read-write + + + RESPONSE_INDEX + Index of previous response, including any auto-stop sent by core. + 11 + 6 + read-write + + + FIFO_COUNT + FIFO count - Number of filled locations in FIFO. + 17 + 13 + read-write + + + DMA_ACK + DMA acknowledge signal state. + 30 + 1 + read-write + + + DMA_REQ + DMA request signal state. + 31 + 1 + read-write + + + + + FIFOTH + FIFO Threshold Watermark register + 0x4C + 32 + read-write + 0x1F0000 + 0x7FFF0FFF + + + TX_WMARK + FIFO threshold watermark level when transmitting data to card. + 0 + 12 + read-write + + + RX_WMARK + FIFO threshold watermark level when receiving data to card. + 16 + 12 + read-write + + + DMA_MTS + Burst size of multiple transaction; should be programmed same as DW-DMA controller multiple-transaction-size SRC/DEST_MSIZE. + 28 + 3 + read-write + + + + + CDETECT + Card Detect register + 0x50 + 32 + read-write + 0 + 0x1 + + + CARD0_DETECT + Card 0 detect + 0 + 1 + read-write + + + CARD1_DETECT + Card 1 detect + 1 + 1 + read-write + + + + + WRTPRT + Write Protect register + 0x54 + 32 + read-write + 0 + 0x1 + + + WRITE_PROTECT + Write protect. + 0 + 1 + read-write + + + + + TCBCNT + Transferred CIU Card Byte Count register + 0x5C + 32 + read-write + 0 + 0xFFFFFFFF + + + TRANS_CARD_BYTE_COUNT + Number of bytes transferred by CIU unit to card. + 0 + 32 + read-write + + + + + TBBCNT + Transferred Host to BIU-FIFO Byte Count register + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + TRANS_FIFO_BYTE_COUNT + Number of bytes transferred between Host/DMA memory and BIU FIFO. + 0 + 32 + read-write + + + + + DEBNCE + Debounce Count register + 0x64 + 32 + read-write + 0xFFFFFF + 0xFFFFFF + + + DEBOUNCE_COUNT + Number of host clocks (SD_CLK) used by debounce filter logic for card detect; typical debounce time is 5-25 ms. + 0 + 24 + read-write + + + + + RST_N + Hardware Reset + 0x78 + 32 + read-write + 0x1 + 0x1 + + + CARD_RESET + Hardware reset. + 0 + 1 + read-write + + + + + BMOD + Bus Mode register + 0x80 + 32 + read-write + 0 + 0x7FF + + + SWR + Software Reset. + 0 + 1 + read-write + + + FB + Fixed Burst. + 1 + 1 + read-write + + + DSL + Descriptor Skip Length. + 2 + 5 + read-write + + + DE + SD/MMC DMA Enable. + 7 + 1 + read-write + + + PBL + Programmable Burst Length. + 8 + 3 + read-write + + + + + PLDMND + Poll Demand register + 0x84 + 32 + read-write + 0 + 0xFFFFFFFF + + + PD + Poll Demand. + 0 + 32 + read-write + + + + + DBADDR + Descriptor List Base Address register + 0x88 + 32 + read-write + 0 + 0xFFFFFFFF + + + SDL + Start of Descriptor List. + 0 + 32 + read-write + + + + + IDSTS + Internal DMAC Status register + 0x8C + 32 + read-write + 0 + 0x1FF37 + + + TI + Transmit Interrupt. + 0 + 1 + read-write + + + RI + Receive Interrupt. + 1 + 1 + read-write + + + FBE + Fatal Bus Error Interrupt. + 2 + 1 + read-write + + + DU + Descriptor Unavailable Interrupt. + 4 + 1 + read-write + + + CES + Card Error Summary. + 5 + 1 + read-write + + + NIS + Normal Interrupt Summary. + 8 + 1 + read-write + + + AIS + Abnormal Interrupt Summary. + 9 + 1 + read-write + + + EB + Error Bits. + 10 + 3 + read-write + + + FSM + DMAC state machine present state. + 13 + 4 + read-write + + + + + IDINTEN + Internal DMAC Interrupt Enable register + 0x90 + 32 + read-write + 0 + 0x337 + + + TI + Transmit Interrupt Enable. + 0 + 1 + read-write + + + RI + Receive Interrupt Enable. + 1 + 1 + read-write + + + FBE + Fatal Bus Error Enable. + 2 + 1 + read-write + + + DU + Descriptor Unavailable Interrupt. + 4 + 1 + read-write + + + CES + Card Error summary Interrupt Enable. + 5 + 1 + read-write + + + NIS + Normal Interrupt Summary Enable. + 8 + 1 + read-write + + + AIS + Abnormal Interrupt Summary Enable. + 9 + 1 + read-write + + + + + DSCADDR + Current Host Descriptor Address register + 0x94 + 32 + read-write + 0 + 0xFFFFFFFF + + + HDA + Host Descriptor Address Pointer. + 0 + 32 + read-write + + + + + BUFADDR + Current Buffer Descriptor Address register + 0x98 + 32 + read-write + 0 + 0xFFFFFFFF + + + HBA + Host Buffer Address Pointer. + 0 + 32 + read-write + + + + + CARDTHRCTL + Card Threshold Control + 0x100 + 32 + read-write + 0 + 0xFF0003 + + + CARDRDTHREN + Card Read Threshold Enable. + 0 + 1 + read-write + + + BSYCLRINTEN + Busy Clear Interrupt Enable. + 1 + 1 + read-write + + + CARDTHRESHOLD + Card Threshold size. + 16 + 8 + read-write + + + + + BACKENDPWR + Power control + 0x104 + 32 + read-write + 0 + 0x1 + + + BACKENDPWR + Back-end Power control for card application. + 0 + 1 + read-write + + + + + 64 + 0x4 + FIFO[%s] + SDIF FIFO + 0x200 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + SDIF FIFO. + 0 + 32 + read-write + + + + + + + DGBMAILBOX + MCU Debugger Mailbox + DGBMAILBOX + 0x4009C000 + + 0 + 0x100 + registers + + + + CSW + CRC mode register + 0 + 32 + read-write + 0 + 0x3F + + + RESYNCH_REQ + Debugger will set this bit to 1 to request a resynchronrisation + 0 + 1 + read-write + + + REQ_PENDING + Request is pending from debugger (i.e unread value in REQUEST) + 1 + 1 + read-write + + + DBG_OR_ERR + Debugger overrun error (previous REQUEST overwritten before being picked up by ROM) + 2 + 1 + read-write + + + AHB_OR_ERR + AHB overrun Error (Return value overwritten by ROM) + 3 + 1 + read-write + + + SOFT_RESET + Soft Reset for DM (write-only from AHB, not readable and selfclearing). A write to this bit will cause a soft reset for DM. + 4 + 1 + read-write + + + CHIP_RESET_REQ + Write only bit. Once written will cause the chip to reset (note that the DM is not reset by this reset as it is only resettable by a SOFT reset or a POR/BOD event) + 5 + 1 + write-only + + + + + REQUEST + CRC seed register + 0x4 + 32 + read-write + 0xFFFF + 0xFFFFFFFF + + + REQ + Request Value + 0 + 32 + read-write + + + + + RETURN + Return value from ROM. + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + RET + The Return value from ROM. + 0 + 32 + read-write + + + + + ID + Identification register + 0xFC + 32 + read-only + 0x2A0000 + 0xFFFFFFFF + + + ID + Identification value. + 0 + 32 + read-only + + + + + + + ADC0 + ADC + ADC + 0x400A0000 + + 0 + 0x1000 + registers + + + ADC0 + 22 + + + + VERID + Version ID Register + 0 + 32 + read-only + 0x1002C0B + 0xFFFFFFFF + + + RES + Resolution + 0 + 1 + read-only + + + RES_0 + Up to 13-bit differential/12-bit single ended resolution supported. + 0 + + + RES_1 + Up to 16-bit differential/16-bit single ended resolution supported. + 0x1 + + + + + DIFFEN + Differential Supported + 1 + 1 + read-only + + + DIFFEN_0 + Differential operation not supported. + 0 + + + DIFFEN_1 + Differential operation supported. CMDLa[CTYPE] controls fields implemented. + 0x1 + + + + + MVI + Multi Vref Implemented + 3 + 1 + read-only + + + MVI_0 + Single voltage reference high (VREFH) input supported. + 0 + + + MVI_1 + Multiple voltage reference high (VREFH) inputs supported. + 0x1 + + + + + CSW + Channel Scale Width + 4 + 3 + read-only + + + CSW_0 + Channel scaling not supported. + 0 + + + CSW_1 + Channel scaling supported. 1-bit CSCALE control field. + 0x1 + + + CSW_6 + Channel scaling supported. 6-bit CSCALE control field. + 0x6 + + + + + VR1RNGI + Voltage Reference 1 Range Control Bit Implemented + 8 + 1 + read-only + + + VR1RNGI_0 + Range control not required. CFG[VREF1RNG] is not implemented. + 0 + + + VR1RNGI_1 + Range control required. CFG[VREF1RNG] is implemented. + 0x1 + + + + + IADCKI + Internal ADC Clock implemented + 9 + 1 + read-only + + + IADCKI_0 + Internal clock source not implemented. + 0 + + + IADCKI_1 + Internal clock source (and CFG[ADCKEN]) implemented. + 0x1 + + + + + CALOFSI + Calibration Function Implemented + 10 + 1 + read-only + + + CALOFSI_0 + Calibration Not Implemented. + 0 + + + CALOFSI_1 + Calibration Implemented. + 0x1 + + + + + NUM_SEC + Number of Single Ended Outputs Supported + 11 + 1 + read-only + + + NUM_SEC_0 + This design supports one single ended conversion at a time. + 0 + + + NUM_SEC_1 + This design supports two simultanious single ended conversions. + 0x1 + + + + + NUM_FIFO + Number of FIFOs + 12 + 3 + read-only + + + NUM_FIFO_0 + N/A + 0 + + + NUM_FIFO_1 + This design supports one result FIFO. + 0x1 + + + NUM_FIFO_2 + This design supports two result FIFOs. + 0x2 + + + NUM_FIFO_3 + This design supports three result FIFOs. + 0x3 + + + NUM_FIFO_4 + This design supports four result FIFOs. + 0x4 + + + + + MINOR + Minor Version Number + 16 + 8 + read-only + + + MAJOR + Major Version Number + 24 + 8 + read-only + + + + + PARAM + Parameter Register + 0x4 + 32 + read-only + 0xF041010 + 0xFFFFFFFF + + + TRIG_NUM + Trigger Number + 0 + 8 + read-only + + + FIFOSIZE + Result FIFO Depth + 8 + 8 + read-only + + + FIFOSIZE_1 + Result FIFO depth = 1 dataword. + 0x1 + + + FIFOSIZE_4 + Result FIFO depth = 4 datawords. + 0x4 + + + FIFOSIZE_8 + Result FIFO depth = 8 datawords. + 0x8 + + + FIFOSIZE_16 + Result FIFO depth = 16 datawords. + 0x10 + + + FIFOSIZE_32 + Result FIFO depth = 32 datawords. + 0x20 + + + FIFOSIZE_64 + Result FIFO depth = 64 datawords. + 0x40 + + + + + CV_NUM + Compare Value Number + 16 + 8 + read-only + + + CMD_NUM + Command Buffer Number + 24 + 8 + read-only + + + + + CTRL + ADC Control Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADCEN + ADC Enable + 0 + 1 + read-write + + + ADCEN_0 + ADC is disabled. + 0 + + + ADCEN_1 + ADC is enabled. + 0x1 + + + + + RST + Software Reset + 1 + 1 + read-write + + + RST_0 + ADC logic is not reset. + 0 + + + RST_1 + ADC logic is reset. + 0x1 + + + + + DOZEN + Doze Enable + 2 + 1 + read-write + + + DOZEN_0 + ADC is enabled in Doze mode. + 0 + + + DOZEN_1 + ADC is disabled in Doze mode. + 0x1 + + + + + CAL_REQ + Auto-Calibration Request + 3 + 1 + read-write + + + CAL_REQ_0 + No request for auto-calibration has been made. + 0 + + + CAL_REQ_1 + A request for auto-calibration has been made + 0x1 + + + + + CALOFS + Configure for offset calibration function + 4 + 1 + read-write + + + CALOFS_0 + Calibration function disabled + 0 + + + CALOFS_1 + Request for offset calibration function + 0x1 + + + + + RSTFIFO0 + Reset FIFO 0 + 8 + 1 + read-write + + + RSTFIFO0_0 + No effect. + 0 + + + RSTFIFO0_1 + FIFO 0 is reset. + 0x1 + + + + + RSTFIFO1 + Reset FIFO 1 + 9 + 1 + read-write + + + RSTFIFO1_0 + No effect. + 0 + + + RSTFIFO1_1 + FIFO 1 is reset. + 0x1 + + + + + CAL_AVGS + Auto-Calibration Averages + 16 + 3 + read-write + + + CAL_AVGS_0 + Single conversion. + 0 + + + CAL_AVGS_1 + 2 conversions averaged. + 0x1 + + + CAL_AVGS_2 + 4 conversions averaged. + 0x2 + + + CAL_AVGS_3 + 8 conversions averaged. + 0x3 + + + CAL_AVGS_4 + 16 conversions averaged. + 0x4 + + + CAL_AVGS_5 + 32 conversions averaged. + 0x5 + + + CAL_AVGS_6 + 64 conversions averaged. + 0x6 + + + CAL_AVGS_7 + 128 conversions averaged. + 0x7 + + + + + + + STAT + ADC Status Register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + RDY0 + Result FIFO 0 Ready Flag + 0 + 1 + read-only + + + RDY0_0 + Result FIFO 0 data level not above watermark level. + 0 + + + RDY0_1 + Result FIFO 0 holding data above watermark level. + 0x1 + + + + + FOF0 + Result FIFO 0 Overflow Flag + 1 + 1 + read-write + oneToClear + + + FOF0_0 + No result FIFO 0 overflow has occurred since the last time the flag was cleared. + 0 + + + FOF0_1 + At least one result FIFO 0 overflow has occurred since the last time the flag was cleared. + 0x1 + + + + + RDY1 + Result FIFO1 Ready Flag + 2 + 1 + read-only + + + RDY1_0 + Result FIFO1 data level not above watermark level. + 0 + + + RDY1_1 + Result FIFO1 holding data above watermark level. + 0x1 + + + + + FOF1 + Result FIFO1 Overflow Flag + 3 + 1 + read-write + oneToClear + + + FOF1_0 + No result FIFO1 overflow has occurred since the last time the flag was cleared. + 0 + + + FOF1_1 + At least one result FIFO1 overflow has occurred since the last time the flag was cleared. + 0x1 + + + + + TEXC_INT + Interrupt Flag For High Priority Trigger Exception + 8 + 1 + read-write + oneToClear + + + TEXC_INT_0 + No trigger exceptions have occurred. + 0 + + + TEXC_INT_1 + A trigger exception has occurred and is pending acknowledgement. + 0x1 + + + + + TCOMP_INT + Interrupt Flag For Trigger Completion + 9 + 1 + read-write + oneToClear + + + TCOMP_INT_0 + Either IE[TCOMP_IE] is set to 0, or no trigger sequences have run to completion. + 0 + + + TCOMP_INT_1 + Trigger sequence has been completed and all data is stored in the associated FIFO. + 0x1 + + + + + CAL_RDY + Calibration Ready + 10 + 1 + read-only + + + CAL_RDY_0 + Calibration is incomplete or hasn't been ran. + 0 + + + CAL_RDY_1 + The ADC is calibrated. + 0x1 + + + + + ADC_ACTIVE + ADC Active + 11 + 1 + read-only + + + ADC_ACTIVE_0 + The ADC is IDLE. There are no pending triggers to service and no active commands are being processed. + 0 + + + ADC_ACTIVE_1 + The ADC is processing a conversion, running through the power up delay, or servicing a trigger. + 0x1 + + + + + TRGACT + Trigger Active + 16 + 4 + read-only + + + TRGACT_0 + Command (sequence) associated with Trigger 0 currently being executed. + 0 + + + TRGACT_1 + Command (sequence) associated with Trigger 1 currently being executed. + 0x1 + + + TRGACT_2 + Command (sequence) associated with Trigger 2 currently being executed. + 0x2 + + + TRGACT_3 + Command (sequence) from the associated Trigger number is currently being executed. + 0x3 + + + TRGACT_4 + Command (sequence) from the associated Trigger number is currently being executed. + 0x4 + + + TRGACT_5 + Command (sequence) from the associated Trigger number is currently being executed. + 0x5 + + + TRGACT_6 + Command (sequence) from the associated Trigger number is currently being executed. + 0x6 + + + TRGACT_7 + Command (sequence) from the associated Trigger number is currently being executed. + 0x7 + + + TRGACT_8 + Command (sequence) from the associated Trigger number is currently being executed. + 0x8 + + + TRGACT_9 + Command (sequence) from the associated Trigger number is currently being executed. + 0x9 + + + + + CMDACT + Command Active + 24 + 4 + read-only + + + CMDACT_0 + No command is currently in progress. + 0 + + + CMDACT_1 + Command 1 currently being executed. + 0x1 + + + CMDACT_2 + Command 2 currently being executed. + 0x2 + + + CMDACT_3 + Associated command number is currently being executed. + 0x3 + + + CMDACT_4 + Associated command number is currently being executed. + 0x4 + + + CMDACT_5 + Associated command number is currently being executed. + 0x5 + + + CMDACT_6 + Associated command number is currently being executed. + 0x6 + + + CMDACT_7 + Associated command number is currently being executed. + 0x7 + + + CMDACT_8 + Associated command number is currently being executed. + 0x8 + + + CMDACT_9 + Associated command number is currently being executed. + 0x9 + + + + + + + IE + Interrupt Enable Register + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + FWMIE0 + FIFO 0 Watermark Interrupt Enable + 0 + 1 + read-write + + + FWMIE0_0 + FIFO 0 watermark interrupts are not enabled. + 0 + + + FWMIE0_1 + FIFO 0 watermark interrupts are enabled. + 0x1 + + + + + FOFIE0 + Result FIFO 0 Overflow Interrupt Enable + 1 + 1 + read-write + + + FOFIE0_0 + FIFO 0 overflow interrupts are not enabled. + 0 + + + FOFIE0_1 + FIFO 0 overflow interrupts are enabled. + 0x1 + + + + + FWMIE1 + FIFO1 Watermark Interrupt Enable + 2 + 1 + read-write + + + FWMIE1_0 + FIFO1 watermark interrupts are not enabled. + 0 + + + FWMIE1_1 + FIFO1 watermark interrupts are enabled. + 0x1 + + + + + FOFIE1 + Result FIFO1 Overflow Interrupt Enable + 3 + 1 + read-write + + + FOFIE1_0 + No result FIFO1 overflow has occurred since the last time the flag was cleared. + 0 + + + FOFIE1_1 + At least one result FIFO1 overflow has occurred since the last time the flag was cleared. + 0x1 + + + + + TEXC_IE + Trigger Exception Interrupt Enable + 8 + 1 + read-write + + + TEXC_IE_0 + Trigger exception interrupts are disabled. + 0 + + + TEXC_IE_1 + Trigger exception interrupts are enabled. + 0x1 + + + + + TCOMP_IE + Trigger Completion Interrupt Enable + 16 + 16 + read-write + + + TCOMP_IE_0 + Trigger completion interrupts are disabled. + 0 + + + TCOMP_IE_1 + Trigger completion interrupts are enabled for trigger source 0 only. + 0x1 + + + TCOMP_IE_2 + Trigger completion interrupts are enabled for trigger source 1 only. + 0x2 + + + TCOMP_IE_3 + Associated trigger completion interrupts are enabled. + 0x3 + + + TCOMP_IE_4 + Associated trigger completion interrupts are enabled. + 0x4 + + + TCOMP_IE_5 + Associated trigger completion interrupts are enabled. + 0x5 + + + TCOMP_IE_6 + Associated trigger completion interrupts are enabled. + 0x6 + + + TCOMP_IE_7 + Associated trigger completion interrupts are enabled. + 0x7 + + + TCOMP_IE_8 + Associated trigger completion interrupts are enabled. + 0x8 + + + TCOMP_IE_9 + Associated trigger completion interrupts are enabled. + 0x9 + + + TCOMP_IE_65535 + Trigger completion interrupts are enabled for every trigger source. + 0xFFFF + + + + + + + DE + DMA Enable Register + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + FWMDE0 + FIFO 0 Watermark DMA Enable + 0 + 1 + read-write + + + FWMDE0_0 + DMA request disabled. + 0 + + + FWMDE0_1 + DMA request enabled. + 0x1 + + + + + FWMDE1 + FIFO1 Watermark DMA Enable + 1 + 1 + read-write + + + FWMDE1_0 + DMA request disabled. + 0 + + + FWMDE1_1 + DMA request enabled. + 0x1 + + + + + + + CFG + ADC Configuration Register + 0x20 + 32 + read-write + 0x800000 + 0xFFFFFFFF + + + TPRICTRL + ADC trigger priority control + 0 + 2 + read-write + + + TPRICTRL_0 + If a higher priority trigger is detected during command processing, the current conversion is aborted and the new command specified by the trigger is started. + 0 + + + TPRICTRL_1 + If a higher priority trigger is received during command processing, the current command is stopped after after completing the current conversion. If averaging is enabled, the averaging loop will be completed. However, CMDHa[LOOP] will be ignored and the higher priority trigger will be serviced. + 0x1 + + + TPRICTRL_2 + If a higher priority trigger is received during command processing, the current command will be completed (averaging, looping, compare) before servicing the higher priority trigger. + 0x2 + + + + + PWRSEL + Power Configuration Select + 4 + 2 + read-write + + + PWRSEL_0 + Lowest power setting. + 0 + + + PWRSEL_1 + Higher power setting than 0b0. + 0x1 + + + PWRSEL_2 + Higher power setting than 0b1. + 0x2 + + + PWRSEL_3 + Highest power setting. + 0x3 + + + + + REFSEL + Voltage Reference Selection + 6 + 2 + read-write + + + REFSEL_0 + (Default) Option 1 setting. + 0 + + + REFSEL_1 + Option 2 setting. + 0x1 + + + REFSEL_2 + Option 3 setting. + 0x2 + + + + + TRES + Trigger Resume Enable + 8 + 1 + read-write + + + TRES_0 + Trigger sequences interrupted by a high priority trigger exception will not be automatically resumed or restarted. + 0 + + + TRES_1 + Trigger sequences interrupted by a high priority trigger exception will be automatically resumed or restarted. + 0x1 + + + + + TCMDRES + Trigger Command Resume + 9 + 1 + read-write + + + TCMDRES_0 + Trigger sequences interrupted by a high priority trigger exception will be automatically restarted. + 0 + + + TCMDRES_1 + Trigger sequences interrupted by a high priority trigger exception will be resumed from the command executing before the exception. + 0x1 + + + + + HPT_EXDI + High Priority Trigger Exception Disable + 10 + 1 + read-write + + + HPT_EXDI_0 + High priority trigger exceptions are enabled. + 0 + + + HPT_EXDI_1 + High priority trigger exceptions are disabled. + 0x1 + + + + + PUDLY + Power Up Delay + 16 + 8 + read-write + + + PWREN + ADC Analog Pre-Enable + 28 + 1 + read-write + + + PWREN_0 + ADC analog circuits are only enabled while conversions are active. Performance is affected due to analog startup delays. + 0 + + + PWREN_1 + ADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the cost of higher DC current consumption). A single power up delay (CFG[PUDLY]) is executed immediately once PWREN is set, and any detected trigger does not begin ADC operation until the power up delay time has passed. After this initial delay expires the analog will remain pre-enabled, and no additional delays will be executed. + 0x1 + + + + + + + PAUSE + ADC Pause Register + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + PAUSEDLY + Pause Delay + 0 + 9 + read-write + + + PAUSEEN + PAUSE Option Enable + 31 + 1 + read-write + + + PAUSEEN_0 + Pause operation disabled + 0 + + + PAUSEEN_1 + Pause operation enabled + 0x1 + + + + + + + SWTRIG + Software Trigger Register + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + SWT0 + Software trigger 0 event + 0 + 1 + read-write + + + SWT0_0 + No trigger 0 event generated. + 0 + + + SWT0_1 + Trigger 0 event generated. + 0x1 + + + + + SWT1 + Software trigger 1 event + 1 + 1 + read-write + + + SWT1_0 + No trigger 1 event generated. + 0 + + + SWT1_1 + Trigger 1 event generated. + 0x1 + + + + + SWT2 + Software trigger 2 event + 2 + 1 + read-write + + + SWT2_0 + No trigger 2 event generated. + 0 + + + SWT2_1 + Trigger 2 event generated. + 0x1 + + + + + SWT3 + Software trigger 3 event + 3 + 1 + read-write + + + SWT3_0 + No trigger 3 event generated. + 0 + + + SWT3_1 + Trigger 3 event generated. + 0x1 + + + + + SWT4 + Software trigger 4 event + 4 + 1 + read-write + + + SWT4_0 + No trigger 4 event generated. + 0 + + + SWT4_1 + Trigger 4 event generated. + 0x1 + + + + + SWT5 + Software trigger 5 event + 5 + 1 + read-write + + + SWT5_0 + No trigger 5 event generated. + 0 + + + SWT5_1 + Trigger 5 event generated. + 0x1 + + + + + SWT6 + Software trigger 6 event + 6 + 1 + read-write + + + SWT6_0 + No trigger 6 event generated. + 0 + + + SWT6_1 + Trigger 6 event generated. + 0x1 + + + + + SWT7 + Software trigger 7 event + 7 + 1 + read-write + + + SWT7_0 + No trigger 7 event generated. + 0 + + + SWT7_1 + Trigger 7 event generated. + 0x1 + + + + + SWT8 + Software trigger 8 event + 8 + 1 + read-write + + + SWT8_0 + No trigger 8 event generated. + 0 + + + SWT8_1 + Trigger 8 event generated. + 0x1 + + + + + SWT9 + Software trigger 9 event + 9 + 1 + read-write + + + SWT9_0 + No trigger 9 event generated. + 0 + + + SWT9_1 + Trigger 9 event generated. + 0x1 + + + + + SWT10 + Software trigger 10 event + 10 + 1 + read-write + + + SWT10_0 + No trigger 10 event generated. + 0 + + + SWT10_1 + Trigger 10 event generated. + 0x1 + + + + + SWT11 + Software trigger 11 event + 11 + 1 + read-write + + + SWT11_0 + No trigger 11 event generated. + 0 + + + SWT11_1 + Trigger 11 event generated. + 0x1 + + + + + SWT12 + Software trigger 12 event + 12 + 1 + read-write + + + SWT12_0 + No trigger 12 event generated. + 0 + + + SWT12_1 + Trigger 12 event generated. + 0x1 + + + + + SWT13 + Software trigger 13 event + 13 + 1 + read-write + + + SWT13_0 + No trigger 13 event generated. + 0 + + + SWT13_1 + Trigger 13 event generated. + 0x1 + + + + + SWT14 + Software trigger 14 event + 14 + 1 + read-write + + + SWT14_0 + No trigger 14 event generated. + 0 + + + SWT14_1 + Trigger 14 event generated. + 0x1 + + + + + SWT15 + Software trigger 15 event + 15 + 1 + read-write + + + SWT15_0 + No trigger 15 event generated. + 0 + + + SWT15_1 + Trigger 15 event generated. + 0x1 + + + + + + + TSTAT + Trigger Status Register + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + TEXC_NUM + Trigger Exception Number + 0 + 16 + read-write + oneToClear + + + TEXC_NUM_0 + No triggers have been interrupted by a high priority exception. Or CFG[TRES] = 1. + 0 + + + TEXC_NUM_1 + Trigger 0 has been interrupted by a high priority exception. + 0x1 + + + TEXC_NUM_2 + Trigger 1 has been interrupted by a high priority exception. + 0x2 + + + TEXC_NUM_3 + Associated trigger sequence has interrupted by a high priority exception. + 0x3 + + + TEXC_NUM_4 + Associated trigger sequence has interrupted by a high priority exception. + 0x4 + + + TEXC_NUM_5 + Associated trigger sequence has interrupted by a high priority exception. + 0x5 + + + TEXC_NUM_6 + Associated trigger sequence has interrupted by a high priority exception. + 0x6 + + + TEXC_NUM_7 + Associated trigger sequence has interrupted by a high priority exception. + 0x7 + + + TEXC_NUM_8 + Associated trigger sequence has interrupted by a high priority exception. + 0x8 + + + TEXC_NUM_9 + Associated trigger sequence has interrupted by a high priority exception. + 0x9 + + + TEXC_NUM_65535 + Every trigger sequence has been interrupted by a high priority exception. + 0xFFFF + + + + + TCOMP_FLAG + Trigger Completion Flag + 16 + 16 + read-write + oneToClear + + + TCOMP_FLAG_0 + No triggers have been completed. Trigger completion interrupts are disabled. + 0 + + + TCOMP_FLAG_1 + Trigger 0 has been completed and triger 0 has enabled completion interrupts. + 0x1 + + + TCOMP_FLAG_2 + Trigger 1 has been completed and triger 1 has enabled completion interrupts. + 0x2 + + + TCOMP_FLAG_3 + Associated trigger sequence has completed and has enabled completion interrupts. + 0x3 + + + TCOMP_FLAG_4 + Associated trigger sequence has completed and has enabled completion interrupts. + 0x4 + + + TCOMP_FLAG_5 + Associated trigger sequence has completed and has enabled completion interrupts. + 0x5 + + + TCOMP_FLAG_6 + Associated trigger sequence has completed and has enabled completion interrupts. + 0x6 + + + TCOMP_FLAG_7 + Associated trigger sequence has completed and has enabled completion interrupts. + 0x7 + + + TCOMP_FLAG_8 + Associated trigger sequence has completed and has enabled completion interrupts. + 0x8 + + + TCOMP_FLAG_9 + Associated trigger sequence has completed and has enabled completion interrupts. + 0x9 + + + TCOMP_FLAG_65535 + Every trigger sequence has been completed and every trigger has enabled completion interrupts. + 0xFFFF + + + + + + + OFSTRIM + ADC Offset Trim Register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + OFSTRIM_A + Trim for offset + 0 + 5 + read-write + + + OFSTRIM_B + Trim for offset + 16 + 5 + read-write + + + + + 16 + 0x4 + TCTRL[%s] + Trigger Control Register + 0xA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + HTEN + Trigger enable + 0 + 1 + read-write + + + HTEN_0 + Hardware trigger source disabled + 0 + + + HTEN_1 + Hardware trigger source enabled + 0x1 + + + + + FIFO_SEL_A + SAR Result Destination For Channel A + 1 + 1 + read-write + + + FIFO_SEL_A_0 + Result written to FIFO 0 + 0 + + + FIFO_SEL_A_1 + Result written to FIFO 1 + 0x1 + + + + + FIFO_SEL_B + SAR Result Destination For Channel B + 2 + 1 + read-write + + + FIFO_SEL_B_0 + Result written to FIFO 0 + 0 + + + FIFO_SEL_B_1 + Result written to FIFO 1 + 0x1 + + + + + TPRI + Trigger priority setting + 8 + 4 + read-write + + + TPRI_0 + Set to highest priority, Level 1 + 0 + + + TPRI_1 + Set to corresponding priority level + 0x1 + + + TPRI_2 + Set to corresponding priority level + 0x2 + + + TPRI_3 + Set to corresponding priority level + 0x3 + + + TPRI_4 + Set to corresponding priority level + 0x4 + + + TPRI_5 + Set to corresponding priority level + 0x5 + + + TPRI_6 + Set to corresponding priority level + 0x6 + + + TPRI_7 + Set to corresponding priority level + 0x7 + + + TPRI_8 + Set to corresponding priority level + 0x8 + + + TPRI_9 + Set to corresponding priority level + 0x9 + + + TPRI_15 + Set to lowest priority, Level 16 + 0xF + + + + + RSYNC + Trigger Resync + 15 + 1 + read-write + + + TDLY + Trigger delay select + 16 + 4 + read-write + + + TCMD + Trigger command select + 24 + 4 + read-write + + + TCMD_0 + Not a valid selection from the command buffer. Trigger event is ignored. + 0 + + + TCMD_1 + CMD1 is executed + 0x1 + + + TCMD_2 + Corresponding CMD is executed + 0x2 + + + TCMD_3 + Corresponding CMD is executed + 0x3 + + + TCMD_4 + Corresponding CMD is executed + 0x4 + + + TCMD_5 + Corresponding CMD is executed + 0x5 + + + TCMD_6 + Corresponding CMD is executed + 0x6 + + + TCMD_7 + Corresponding CMD is executed + 0x7 + + + TCMD_8 + Corresponding CMD is executed + 0x8 + + + TCMD_9 + Corresponding CMD is executed + 0x9 + + + TCMD_15 + CMD15 is executed + 0xF + + + + + + + 2 + 0x4 + FCTRL[%s] + FIFO Control Register + 0xE0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FCOUNT + Result FIFO counter + 0 + 5 + read-only + + + FWMARK + Watermark level selection + 16 + 4 + read-write + + + + + 2 + 0x4 + GCC[%s] + Gain Calibration Control + 0xF0 + 32 + read-only + 0 + 0xFFFFFFFF + + + GAIN_CAL + Gain Calibration Value + 0 + 16 + read-only + + + RDY + Gain Calibration Value Valid + 24 + 1 + read-only + + + RDY_0 + The gain calibration value is invalid. Run the auto-calibration routine for this value to be written. + 0 + + + RDY_1 + The gain calibration value is valid. It should be used to update the GCRa[GCALR] register field. + 0x1 + + + + + + + 2 + 0x4 + GCR[%s] + Gain Calculation Result + 0xF8 + 32 + read-write + 0 + 0xFFFFFFFF + + + GCALR + Gain Calculation Result + 0 + 16 + read-write + + + RDY + Gain Calculation Ready + 24 + 1 + read-write + + + RDY_0 + The gain offset calculation value is invalid. + 0 + + + RDY_1 + The gain calibration value is valid. + 0x1 + + + + + + + CMDL1 + ADC Command Low Buffer Register + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADCH + Input channel select + 0 + 5 + read-write + + + ADCH_0 + Select CH0A or CH0B or CH0A/CH0B pair. + 0 + + + ADCH_1 + Select CH1A or CH1B or CH1A/CH1B pair. + 0x1 + + + ADCH_2 + Select CH2A or CH2B or CH2A/CH2B pair. + 0x2 + + + ADCH_3 + Select CH3A or CH3B or CH3A/CH3B pair. + 0x3 + + + ADCH_4 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x4 + + + ADCH_5 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x5 + + + ADCH_6 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x6 + + + ADCH_7 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x7 + + + ADCH_8 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x8 + + + ADCH_9 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x9 + + + ADCH_30 + Select CH30A or CH30B or CH30A/CH30B pair. + 0x1E + + + ADCH_31 + Select CH31A or CH31B or CH31A/CH31B pair. + 0x1F + + + + + CTYPE + Conversion Type + 5 + 2 + read-write + + + CTYPE_0 + Single-Ended Mode. Only A side channel is converted. + 0 + + + CTYPE_1 + Single-Ended Mode. Only B side channel is converted. + 0x1 + + + CTYPE_2 + Differential Mode. A-B. + 0x2 + + + CTYPE_3 + Dual-Single-Ended Mode. Both A side and B side channels are converted independently. + 0x3 + + + + + MODE + Select resolution of conversions + 7 + 1 + read-write + + + MODE_0 + Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. + 0 + + + MODE_1 + High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. + 0x1 + + + + + + + CMDH1 + ADC Command High Buffer Register + 0x104 + 32 + read-write + 0 + 0xFFFFFFFF + + + CMPEN + Compare Function Enable + 0 + 2 + read-write + + + CMPEN_0 + Compare disabled. + 0 + + + CMPEN_2 + Compare enabled. Store on true. + 0x2 + + + CMPEN_3 + Compare enabled. Repeat channel acquisition (sample/convert/compare) until true. + 0x3 + + + + + WAIT_TRIG + Wait for trigger assertion before execution. + 2 + 1 + read-write + + + WAIT_TRIG_0 + This command will be automatically executed. + 0 + + + WAIT_TRIG_1 + The active trigger must be asserted again before executing this command. + 0x1 + + + + + LWI + Loop with Increment + 7 + 1 + read-write + + + LWI_0 + Auto channel increment disabled + 0 + + + LWI_1 + Auto channel increment enabled + 0x1 + + + + + STS + Sample Time Select + 8 + 3 + read-write + + + STS_0 + Minimum sample time of 3 ADCK cycles. + 0 + + + STS_1 + 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. + 0x1 + + + STS_2 + 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. + 0x2 + + + STS_3 + 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. + 0x3 + + + STS_4 + 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. + 0x4 + + + STS_5 + 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. + 0x5 + + + STS_6 + 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. + 0x6 + + + STS_7 + 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. + 0x7 + + + + + AVGS + Hardware Average Select + 12 + 3 + read-write + + + AVGS_0 + Single conversion. + 0 + + + AVGS_1 + 2 conversions averaged. + 0x1 + + + AVGS_2 + 4 conversions averaged. + 0x2 + + + AVGS_3 + 8 conversions averaged. + 0x3 + + + AVGS_4 + 16 conversions averaged. + 0x4 + + + AVGS_5 + 32 conversions averaged. + 0x5 + + + AVGS_6 + 64 conversions averaged. + 0x6 + + + AVGS_7 + 128 conversions averaged. + 0x7 + + + + + LOOP + Loop Count Select + 16 + 4 + read-write + + + LOOP_0 + Looping not enabled. Command executes 1 time. + 0 + + + LOOP_1 + Loop 1 time. Command executes 2 times. + 0x1 + + + LOOP_2 + Loop 2 times. Command executes 3 times. + 0x2 + + + LOOP_3 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x3 + + + LOOP_4 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x4 + + + LOOP_5 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x5 + + + LOOP_6 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x6 + + + LOOP_7 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x7 + + + LOOP_8 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x8 + + + LOOP_9 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x9 + + + LOOP_15 + Loop 15 times. Command executes 16 times. + 0xF + + + + + NEXT + Next Command Select + 24 + 4 + read-write + + + NEXT_0 + No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. + 0 + + + NEXT_1 + Select CMD1 command buffer register as next command. + 0x1 + + + NEXT_2 + Select corresponding CMD command buffer register as next command + 0x2 + + + NEXT_3 + Select corresponding CMD command buffer register as next command + 0x3 + + + NEXT_4 + Select corresponding CMD command buffer register as next command + 0x4 + + + NEXT_5 + Select corresponding CMD command buffer register as next command + 0x5 + + + NEXT_6 + Select corresponding CMD command buffer register as next command + 0x6 + + + NEXT_7 + Select corresponding CMD command buffer register as next command + 0x7 + + + NEXT_8 + Select corresponding CMD command buffer register as next command + 0x8 + + + NEXT_9 + Select corresponding CMD command buffer register as next command + 0x9 + + + NEXT_15 + Select CMD15 command buffer register as next command. + 0xF + + + + + + + CMDL2 + ADC Command Low Buffer Register + 0x108 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADCH + Input channel select + 0 + 5 + read-write + + + ADCH_0 + Select CH0A or CH0B or CH0A/CH0B pair. + 0 + + + ADCH_1 + Select CH1A or CH1B or CH1A/CH1B pair. + 0x1 + + + ADCH_2 + Select CH2A or CH2B or CH2A/CH2B pair. + 0x2 + + + ADCH_3 + Select CH3A or CH3B or CH3A/CH3B pair. + 0x3 + + + ADCH_4 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x4 + + + ADCH_5 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x5 + + + ADCH_6 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x6 + + + ADCH_7 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x7 + + + ADCH_8 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x8 + + + ADCH_9 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x9 + + + ADCH_30 + Select CH30A or CH30B or CH30A/CH30B pair. + 0x1E + + + ADCH_31 + Select CH31A or CH31B or CH31A/CH31B pair. + 0x1F + + + + + CTYPE + Conversion Type + 5 + 2 + read-write + + + CTYPE_0 + Single-Ended Mode. Only A side channel is converted. + 0 + + + CTYPE_1 + Single-Ended Mode. Only B side channel is converted. + 0x1 + + + CTYPE_2 + Differential Mode. A-B. + 0x2 + + + CTYPE_3 + Dual-Single-Ended Mode. Both A side and B side channels are converted independently. + 0x3 + + + + + MODE + Select resolution of conversions + 7 + 1 + read-write + + + MODE_0 + Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. + 0 + + + MODE_1 + High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. + 0x1 + + + + + + + CMDH2 + ADC Command High Buffer Register + 0x10C + 32 + read-write + 0 + 0xFFFFFFFF + + + CMPEN + Compare Function Enable + 0 + 2 + read-write + + + CMPEN_0 + Compare disabled. + 0 + + + CMPEN_2 + Compare enabled. Store on true. + 0x2 + + + CMPEN_3 + Compare enabled. Repeat channel acquisition (sample/convert/compare) until true. + 0x3 + + + + + WAIT_TRIG + Wait for trigger assertion before execution. + 2 + 1 + read-write + + + WAIT_TRIG_0 + This command will be automatically executed. + 0 + + + WAIT_TRIG_1 + The active trigger must be asserted again before executing this command. + 0x1 + + + + + LWI + Loop with Increment + 7 + 1 + read-write + + + LWI_0 + Auto channel increment disabled + 0 + + + LWI_1 + Auto channel increment enabled + 0x1 + + + + + STS + Sample Time Select + 8 + 3 + read-write + + + STS_0 + Minimum sample time of 3 ADCK cycles. + 0 + + + STS_1 + 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. + 0x1 + + + STS_2 + 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. + 0x2 + + + STS_3 + 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. + 0x3 + + + STS_4 + 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. + 0x4 + + + STS_5 + 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. + 0x5 + + + STS_6 + 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. + 0x6 + + + STS_7 + 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. + 0x7 + + + + + AVGS + Hardware Average Select + 12 + 3 + read-write + + + AVGS_0 + Single conversion. + 0 + + + AVGS_1 + 2 conversions averaged. + 0x1 + + + AVGS_2 + 4 conversions averaged. + 0x2 + + + AVGS_3 + 8 conversions averaged. + 0x3 + + + AVGS_4 + 16 conversions averaged. + 0x4 + + + AVGS_5 + 32 conversions averaged. + 0x5 + + + AVGS_6 + 64 conversions averaged. + 0x6 + + + AVGS_7 + 128 conversions averaged. + 0x7 + + + + + LOOP + Loop Count Select + 16 + 4 + read-write + + + LOOP_0 + Looping not enabled. Command executes 1 time. + 0 + + + LOOP_1 + Loop 1 time. Command executes 2 times. + 0x1 + + + LOOP_2 + Loop 2 times. Command executes 3 times. + 0x2 + + + LOOP_3 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x3 + + + LOOP_4 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x4 + + + LOOP_5 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x5 + + + LOOP_6 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x6 + + + LOOP_7 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x7 + + + LOOP_8 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x8 + + + LOOP_9 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x9 + + + LOOP_15 + Loop 15 times. Command executes 16 times. + 0xF + + + + + NEXT + Next Command Select + 24 + 4 + read-write + + + NEXT_0 + No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. + 0 + + + NEXT_1 + Select CMD1 command buffer register as next command. + 0x1 + + + NEXT_2 + Select corresponding CMD command buffer register as next command + 0x2 + + + NEXT_3 + Select corresponding CMD command buffer register as next command + 0x3 + + + NEXT_4 + Select corresponding CMD command buffer register as next command + 0x4 + + + NEXT_5 + Select corresponding CMD command buffer register as next command + 0x5 + + + NEXT_6 + Select corresponding CMD command buffer register as next command + 0x6 + + + NEXT_7 + Select corresponding CMD command buffer register as next command + 0x7 + + + NEXT_8 + Select corresponding CMD command buffer register as next command + 0x8 + + + NEXT_9 + Select corresponding CMD command buffer register as next command + 0x9 + + + NEXT_15 + Select CMD15 command buffer register as next command. + 0xF + + + + + + + CMDL3 + ADC Command Low Buffer Register + 0x110 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADCH + Input channel select + 0 + 5 + read-write + + + ADCH_0 + Select CH0A or CH0B or CH0A/CH0B pair. + 0 + + + ADCH_1 + Select CH1A or CH1B or CH1A/CH1B pair. + 0x1 + + + ADCH_2 + Select CH2A or CH2B or CH2A/CH2B pair. + 0x2 + + + ADCH_3 + Select CH3A or CH3B or CH3A/CH3B pair. + 0x3 + + + ADCH_4 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x4 + + + ADCH_5 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x5 + + + ADCH_6 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x6 + + + ADCH_7 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x7 + + + ADCH_8 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x8 + + + ADCH_9 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x9 + + + ADCH_30 + Select CH30A or CH30B or CH30A/CH30B pair. + 0x1E + + + ADCH_31 + Select CH31A or CH31B or CH31A/CH31B pair. + 0x1F + + + + + CTYPE + Conversion Type + 5 + 2 + read-write + + + CTYPE_0 + Single-Ended Mode. Only A side channel is converted. + 0 + + + CTYPE_1 + Single-Ended Mode. Only B side channel is converted. + 0x1 + + + CTYPE_2 + Differential Mode. A-B. + 0x2 + + + CTYPE_3 + Dual-Single-Ended Mode. Both A side and B side channels are converted independently. + 0x3 + + + + + MODE + Select resolution of conversions + 7 + 1 + read-write + + + MODE_0 + Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. + 0 + + + MODE_1 + High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. + 0x1 + + + + + + + CMDH3 + ADC Command High Buffer Register + 0x114 + 32 + read-write + 0 + 0xFFFFFFFF + + + CMPEN + Compare Function Enable + 0 + 2 + read-write + + + CMPEN_0 + Compare disabled. + 0 + + + CMPEN_2 + Compare enabled. Store on true. + 0x2 + + + CMPEN_3 + Compare enabled. Repeat channel acquisition (sample/convert/compare) until true. + 0x3 + + + + + WAIT_TRIG + Wait for trigger assertion before execution. + 2 + 1 + read-write + + + WAIT_TRIG_0 + This command will be automatically executed. + 0 + + + WAIT_TRIG_1 + The active trigger must be asserted again before executing this command. + 0x1 + + + + + LWI + Loop with Increment + 7 + 1 + read-write + + + LWI_0 + Auto channel increment disabled + 0 + + + LWI_1 + Auto channel increment enabled + 0x1 + + + + + STS + Sample Time Select + 8 + 3 + read-write + + + STS_0 + Minimum sample time of 3 ADCK cycles. + 0 + + + STS_1 + 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. + 0x1 + + + STS_2 + 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. + 0x2 + + + STS_3 + 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. + 0x3 + + + STS_4 + 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. + 0x4 + + + STS_5 + 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. + 0x5 + + + STS_6 + 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. + 0x6 + + + STS_7 + 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. + 0x7 + + + + + AVGS + Hardware Average Select + 12 + 3 + read-write + + + AVGS_0 + Single conversion. + 0 + + + AVGS_1 + 2 conversions averaged. + 0x1 + + + AVGS_2 + 4 conversions averaged. + 0x2 + + + AVGS_3 + 8 conversions averaged. + 0x3 + + + AVGS_4 + 16 conversions averaged. + 0x4 + + + AVGS_5 + 32 conversions averaged. + 0x5 + + + AVGS_6 + 64 conversions averaged. + 0x6 + + + AVGS_7 + 128 conversions averaged. + 0x7 + + + + + LOOP + Loop Count Select + 16 + 4 + read-write + + + LOOP_0 + Looping not enabled. Command executes 1 time. + 0 + + + LOOP_1 + Loop 1 time. Command executes 2 times. + 0x1 + + + LOOP_2 + Loop 2 times. Command executes 3 times. + 0x2 + + + LOOP_3 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x3 + + + LOOP_4 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x4 + + + LOOP_5 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x5 + + + LOOP_6 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x6 + + + LOOP_7 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x7 + + + LOOP_8 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x8 + + + LOOP_9 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x9 + + + LOOP_15 + Loop 15 times. Command executes 16 times. + 0xF + + + + + NEXT + Next Command Select + 24 + 4 + read-write + + + NEXT_0 + No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. + 0 + + + NEXT_1 + Select CMD1 command buffer register as next command. + 0x1 + + + NEXT_2 + Select corresponding CMD command buffer register as next command + 0x2 + + + NEXT_3 + Select corresponding CMD command buffer register as next command + 0x3 + + + NEXT_4 + Select corresponding CMD command buffer register as next command + 0x4 + + + NEXT_5 + Select corresponding CMD command buffer register as next command + 0x5 + + + NEXT_6 + Select corresponding CMD command buffer register as next command + 0x6 + + + NEXT_7 + Select corresponding CMD command buffer register as next command + 0x7 + + + NEXT_8 + Select corresponding CMD command buffer register as next command + 0x8 + + + NEXT_9 + Select corresponding CMD command buffer register as next command + 0x9 + + + NEXT_15 + Select CMD15 command buffer register as next command. + 0xF + + + + + + + CMDL4 + ADC Command Low Buffer Register + 0x118 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADCH + Input channel select + 0 + 5 + read-write + + + ADCH_0 + Select CH0A or CH0B or CH0A/CH0B pair. + 0 + + + ADCH_1 + Select CH1A or CH1B or CH1A/CH1B pair. + 0x1 + + + ADCH_2 + Select CH2A or CH2B or CH2A/CH2B pair. + 0x2 + + + ADCH_3 + Select CH3A or CH3B or CH3A/CH3B pair. + 0x3 + + + ADCH_4 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x4 + + + ADCH_5 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x5 + + + ADCH_6 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x6 + + + ADCH_7 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x7 + + + ADCH_8 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x8 + + + ADCH_9 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x9 + + + ADCH_30 + Select CH30A or CH30B or CH30A/CH30B pair. + 0x1E + + + ADCH_31 + Select CH31A or CH31B or CH31A/CH31B pair. + 0x1F + + + + + CTYPE + Conversion Type + 5 + 2 + read-write + + + CTYPE_0 + Single-Ended Mode. Only A side channel is converted. + 0 + + + CTYPE_1 + Single-Ended Mode. Only B side channel is converted. + 0x1 + + + CTYPE_2 + Differential Mode. A-B. + 0x2 + + + CTYPE_3 + Dual-Single-Ended Mode. Both A side and B side channels are converted independently. + 0x3 + + + + + MODE + Select resolution of conversions + 7 + 1 + read-write + + + MODE_0 + Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. + 0 + + + MODE_1 + High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. + 0x1 + + + + + + + CMDH4 + ADC Command High Buffer Register + 0x11C + 32 + read-write + 0 + 0xFFFFFFFF + + + CMPEN + Compare Function Enable + 0 + 2 + read-write + + + CMPEN_0 + Compare disabled. + 0 + + + CMPEN_2 + Compare enabled. Store on true. + 0x2 + + + CMPEN_3 + Compare enabled. Repeat channel acquisition (sample/convert/compare) until true. + 0x3 + + + + + WAIT_TRIG + Wait for trigger assertion before execution. + 2 + 1 + read-write + + + WAIT_TRIG_0 + This command will be automatically executed. + 0 + + + WAIT_TRIG_1 + The active trigger must be asserted again before executing this command. + 0x1 + + + + + LWI + Loop with Increment + 7 + 1 + read-write + + + LWI_0 + Auto channel increment disabled + 0 + + + LWI_1 + Auto channel increment enabled + 0x1 + + + + + STS + Sample Time Select + 8 + 3 + read-write + + + STS_0 + Minimum sample time of 3 ADCK cycles. + 0 + + + STS_1 + 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. + 0x1 + + + STS_2 + 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. + 0x2 + + + STS_3 + 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. + 0x3 + + + STS_4 + 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. + 0x4 + + + STS_5 + 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. + 0x5 + + + STS_6 + 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. + 0x6 + + + STS_7 + 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. + 0x7 + + + + + AVGS + Hardware Average Select + 12 + 3 + read-write + + + AVGS_0 + Single conversion. + 0 + + + AVGS_1 + 2 conversions averaged. + 0x1 + + + AVGS_2 + 4 conversions averaged. + 0x2 + + + AVGS_3 + 8 conversions averaged. + 0x3 + + + AVGS_4 + 16 conversions averaged. + 0x4 + + + AVGS_5 + 32 conversions averaged. + 0x5 + + + AVGS_6 + 64 conversions averaged. + 0x6 + + + AVGS_7 + 128 conversions averaged. + 0x7 + + + + + LOOP + Loop Count Select + 16 + 4 + read-write + + + LOOP_0 + Looping not enabled. Command executes 1 time. + 0 + + + LOOP_1 + Loop 1 time. Command executes 2 times. + 0x1 + + + LOOP_2 + Loop 2 times. Command executes 3 times. + 0x2 + + + LOOP_3 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x3 + + + LOOP_4 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x4 + + + LOOP_5 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x5 + + + LOOP_6 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x6 + + + LOOP_7 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x7 + + + LOOP_8 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x8 + + + LOOP_9 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x9 + + + LOOP_15 + Loop 15 times. Command executes 16 times. + 0xF + + + + + NEXT + Next Command Select + 24 + 4 + read-write + + + NEXT_0 + No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. + 0 + + + NEXT_1 + Select CMD1 command buffer register as next command. + 0x1 + + + NEXT_2 + Select corresponding CMD command buffer register as next command + 0x2 + + + NEXT_3 + Select corresponding CMD command buffer register as next command + 0x3 + + + NEXT_4 + Select corresponding CMD command buffer register as next command + 0x4 + + + NEXT_5 + Select corresponding CMD command buffer register as next command + 0x5 + + + NEXT_6 + Select corresponding CMD command buffer register as next command + 0x6 + + + NEXT_7 + Select corresponding CMD command buffer register as next command + 0x7 + + + NEXT_8 + Select corresponding CMD command buffer register as next command + 0x8 + + + NEXT_9 + Select corresponding CMD command buffer register as next command + 0x9 + + + NEXT_15 + Select CMD15 command buffer register as next command. + 0xF + + + + + + + CMDL5 + ADC Command Low Buffer Register + 0x120 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADCH + Input channel select + 0 + 5 + read-write + + + ADCH_0 + Select CH0A or CH0B or CH0A/CH0B pair. + 0 + + + ADCH_1 + Select CH1A or CH1B or CH1A/CH1B pair. + 0x1 + + + ADCH_2 + Select CH2A or CH2B or CH2A/CH2B pair. + 0x2 + + + ADCH_3 + Select CH3A or CH3B or CH3A/CH3B pair. + 0x3 + + + ADCH_4 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x4 + + + ADCH_5 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x5 + + + ADCH_6 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x6 + + + ADCH_7 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x7 + + + ADCH_8 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x8 + + + ADCH_9 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x9 + + + ADCH_30 + Select CH30A or CH30B or CH30A/CH30B pair. + 0x1E + + + ADCH_31 + Select CH31A or CH31B or CH31A/CH31B pair. + 0x1F + + + + + CTYPE + Conversion Type + 5 + 2 + read-write + + + CTYPE_0 + Single-Ended Mode. Only A side channel is converted. + 0 + + + CTYPE_1 + Single-Ended Mode. Only B side channel is converted. + 0x1 + + + CTYPE_2 + Differential Mode. A-B. + 0x2 + + + CTYPE_3 + Dual-Single-Ended Mode. Both A side and B side channels are converted independently. + 0x3 + + + + + MODE + Select resolution of conversions + 7 + 1 + read-write + + + MODE_0 + Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. + 0 + + + MODE_1 + High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. + 0x1 + + + + + + + CMDH5 + ADC Command High Buffer Register + 0x124 + 32 + read-write + 0 + 0xFFFFFFFF + + + WAIT_TRIG + Wait for trigger assertion before execution. + 2 + 1 + read-write + + + WAIT_TRIG_0 + This command will be automatically executed. + 0 + + + WAIT_TRIG_1 + The active trigger must be asserted again before executing this command. + 0x1 + + + + + LWI + Loop with Increment + 7 + 1 + read-write + + + LWI_0 + Auto channel increment disabled + 0 + + + LWI_1 + Auto channel increment enabled + 0x1 + + + + + STS + Sample Time Select + 8 + 3 + read-write + + + STS_0 + Minimum sample time of 3 ADCK cycles. + 0 + + + STS_1 + 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. + 0x1 + + + STS_2 + 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. + 0x2 + + + STS_3 + 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. + 0x3 + + + STS_4 + 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. + 0x4 + + + STS_5 + 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. + 0x5 + + + STS_6 + 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. + 0x6 + + + STS_7 + 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. + 0x7 + + + + + AVGS + Hardware Average Select + 12 + 3 + read-write + + + AVGS_0 + Single conversion. + 0 + + + AVGS_1 + 2 conversions averaged. + 0x1 + + + AVGS_2 + 4 conversions averaged. + 0x2 + + + AVGS_3 + 8 conversions averaged. + 0x3 + + + AVGS_4 + 16 conversions averaged. + 0x4 + + + AVGS_5 + 32 conversions averaged. + 0x5 + + + AVGS_6 + 64 conversions averaged. + 0x6 + + + AVGS_7 + 128 conversions averaged. + 0x7 + + + + + LOOP + Loop Count Select + 16 + 4 + read-write + + + LOOP_0 + Looping not enabled. Command executes 1 time. + 0 + + + LOOP_1 + Loop 1 time. Command executes 2 times. + 0x1 + + + LOOP_2 + Loop 2 times. Command executes 3 times. + 0x2 + + + LOOP_3 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x3 + + + LOOP_4 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x4 + + + LOOP_5 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x5 + + + LOOP_6 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x6 + + + LOOP_7 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x7 + + + LOOP_8 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x8 + + + LOOP_9 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x9 + + + LOOP_15 + Loop 15 times. Command executes 16 times. + 0xF + + + + + NEXT + Next Command Select + 24 + 4 + read-write + + + NEXT_0 + No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. + 0 + + + NEXT_1 + Select CMD1 command buffer register as next command. + 0x1 + + + NEXT_2 + Select corresponding CMD command buffer register as next command + 0x2 + + + NEXT_3 + Select corresponding CMD command buffer register as next command + 0x3 + + + NEXT_4 + Select corresponding CMD command buffer register as next command + 0x4 + + + NEXT_5 + Select corresponding CMD command buffer register as next command + 0x5 + + + NEXT_6 + Select corresponding CMD command buffer register as next command + 0x6 + + + NEXT_7 + Select corresponding CMD command buffer register as next command + 0x7 + + + NEXT_8 + Select corresponding CMD command buffer register as next command + 0x8 + + + NEXT_9 + Select corresponding CMD command buffer register as next command + 0x9 + + + NEXT_15 + Select CMD15 command buffer register as next command. + 0xF + + + + + + + CMDL6 + ADC Command Low Buffer Register + 0x128 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADCH + Input channel select + 0 + 5 + read-write + + + ADCH_0 + Select CH0A or CH0B or CH0A/CH0B pair. + 0 + + + ADCH_1 + Select CH1A or CH1B or CH1A/CH1B pair. + 0x1 + + + ADCH_2 + Select CH2A or CH2B or CH2A/CH2B pair. + 0x2 + + + ADCH_3 + Select CH3A or CH3B or CH3A/CH3B pair. + 0x3 + + + ADCH_4 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x4 + + + ADCH_5 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x5 + + + ADCH_6 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x6 + + + ADCH_7 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x7 + + + ADCH_8 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x8 + + + ADCH_9 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x9 + + + ADCH_30 + Select CH30A or CH30B or CH30A/CH30B pair. + 0x1E + + + ADCH_31 + Select CH31A or CH31B or CH31A/CH31B pair. + 0x1F + + + + + CTYPE + Conversion Type + 5 + 2 + read-write + + + CTYPE_0 + Single-Ended Mode. Only A side channel is converted. + 0 + + + CTYPE_1 + Single-Ended Mode. Only B side channel is converted. + 0x1 + + + CTYPE_2 + Differential Mode. A-B. + 0x2 + + + CTYPE_3 + Dual-Single-Ended Mode. Both A side and B side channels are converted independently. + 0x3 + + + + + MODE + Select resolution of conversions + 7 + 1 + read-write + + + MODE_0 + Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. + 0 + + + MODE_1 + High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. + 0x1 + + + + + + + CMDH6 + ADC Command High Buffer Register + 0x12C + 32 + read-write + 0 + 0xFFFFFFFF + + + WAIT_TRIG + Wait for trigger assertion before execution. + 2 + 1 + read-write + + + WAIT_TRIG_0 + This command will be automatically executed. + 0 + + + WAIT_TRIG_1 + The active trigger must be asserted again before executing this command. + 0x1 + + + + + LWI + Loop with Increment + 7 + 1 + read-write + + + LWI_0 + Auto channel increment disabled + 0 + + + LWI_1 + Auto channel increment enabled + 0x1 + + + + + STS + Sample Time Select + 8 + 3 + read-write + + + STS_0 + Minimum sample time of 3 ADCK cycles. + 0 + + + STS_1 + 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. + 0x1 + + + STS_2 + 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. + 0x2 + + + STS_3 + 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. + 0x3 + + + STS_4 + 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. + 0x4 + + + STS_5 + 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. + 0x5 + + + STS_6 + 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. + 0x6 + + + STS_7 + 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. + 0x7 + + + + + AVGS + Hardware Average Select + 12 + 3 + read-write + + + AVGS_0 + Single conversion. + 0 + + + AVGS_1 + 2 conversions averaged. + 0x1 + + + AVGS_2 + 4 conversions averaged. + 0x2 + + + AVGS_3 + 8 conversions averaged. + 0x3 + + + AVGS_4 + 16 conversions averaged. + 0x4 + + + AVGS_5 + 32 conversions averaged. + 0x5 + + + AVGS_6 + 64 conversions averaged. + 0x6 + + + AVGS_7 + 128 conversions averaged. + 0x7 + + + + + LOOP + Loop Count Select + 16 + 4 + read-write + + + LOOP_0 + Looping not enabled. Command executes 1 time. + 0 + + + LOOP_1 + Loop 1 time. Command executes 2 times. + 0x1 + + + LOOP_2 + Loop 2 times. Command executes 3 times. + 0x2 + + + LOOP_3 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x3 + + + LOOP_4 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x4 + + + LOOP_5 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x5 + + + LOOP_6 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x6 + + + LOOP_7 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x7 + + + LOOP_8 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x8 + + + LOOP_9 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x9 + + + LOOP_15 + Loop 15 times. Command executes 16 times. + 0xF + + + + + NEXT + Next Command Select + 24 + 4 + read-write + + + NEXT_0 + No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. + 0 + + + NEXT_1 + Select CMD1 command buffer register as next command. + 0x1 + + + NEXT_2 + Select corresponding CMD command buffer register as next command + 0x2 + + + NEXT_3 + Select corresponding CMD command buffer register as next command + 0x3 + + + NEXT_4 + Select corresponding CMD command buffer register as next command + 0x4 + + + NEXT_5 + Select corresponding CMD command buffer register as next command + 0x5 + + + NEXT_6 + Select corresponding CMD command buffer register as next command + 0x6 + + + NEXT_7 + Select corresponding CMD command buffer register as next command + 0x7 + + + NEXT_8 + Select corresponding CMD command buffer register as next command + 0x8 + + + NEXT_9 + Select corresponding CMD command buffer register as next command + 0x9 + + + NEXT_15 + Select CMD15 command buffer register as next command. + 0xF + + + + + + + CMDL7 + ADC Command Low Buffer Register + 0x130 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADCH + Input channel select + 0 + 5 + read-write + + + ADCH_0 + Select CH0A or CH0B or CH0A/CH0B pair. + 0 + + + ADCH_1 + Select CH1A or CH1B or CH1A/CH1B pair. + 0x1 + + + ADCH_2 + Select CH2A or CH2B or CH2A/CH2B pair. + 0x2 + + + ADCH_3 + Select CH3A or CH3B or CH3A/CH3B pair. + 0x3 + + + ADCH_4 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x4 + + + ADCH_5 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x5 + + + ADCH_6 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x6 + + + ADCH_7 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x7 + + + ADCH_8 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x8 + + + ADCH_9 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x9 + + + ADCH_30 + Select CH30A or CH30B or CH30A/CH30B pair. + 0x1E + + + ADCH_31 + Select CH31A or CH31B or CH31A/CH31B pair. + 0x1F + + + + + CTYPE + Conversion Type + 5 + 2 + read-write + + + CTYPE_0 + Single-Ended Mode. Only A side channel is converted. + 0 + + + CTYPE_1 + Single-Ended Mode. Only B side channel is converted. + 0x1 + + + CTYPE_2 + Differential Mode. A-B. + 0x2 + + + CTYPE_3 + Dual-Single-Ended Mode. Both A side and B side channels are converted independently. + 0x3 + + + + + MODE + Select resolution of conversions + 7 + 1 + read-write + + + MODE_0 + Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. + 0 + + + MODE_1 + High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. + 0x1 + + + + + + + CMDH7 + ADC Command High Buffer Register + 0x134 + 32 + read-write + 0 + 0xFFFFFFFF + + + WAIT_TRIG + Wait for trigger assertion before execution. + 2 + 1 + read-write + + + WAIT_TRIG_0 + This command will be automatically executed. + 0 + + + WAIT_TRIG_1 + The active trigger must be asserted again before executing this command. + 0x1 + + + + + LWI + Loop with Increment + 7 + 1 + read-write + + + LWI_0 + Auto channel increment disabled + 0 + + + LWI_1 + Auto channel increment enabled + 0x1 + + + + + STS + Sample Time Select + 8 + 3 + read-write + + + STS_0 + Minimum sample time of 3 ADCK cycles. + 0 + + + STS_1 + 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. + 0x1 + + + STS_2 + 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. + 0x2 + + + STS_3 + 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. + 0x3 + + + STS_4 + 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. + 0x4 + + + STS_5 + 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. + 0x5 + + + STS_6 + 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. + 0x6 + + + STS_7 + 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. + 0x7 + + + + + AVGS + Hardware Average Select + 12 + 3 + read-write + + + AVGS_0 + Single conversion. + 0 + + + AVGS_1 + 2 conversions averaged. + 0x1 + + + AVGS_2 + 4 conversions averaged. + 0x2 + + + AVGS_3 + 8 conversions averaged. + 0x3 + + + AVGS_4 + 16 conversions averaged. + 0x4 + + + AVGS_5 + 32 conversions averaged. + 0x5 + + + AVGS_6 + 64 conversions averaged. + 0x6 + + + AVGS_7 + 128 conversions averaged. + 0x7 + + + + + LOOP + Loop Count Select + 16 + 4 + read-write + + + LOOP_0 + Looping not enabled. Command executes 1 time. + 0 + + + LOOP_1 + Loop 1 time. Command executes 2 times. + 0x1 + + + LOOP_2 + Loop 2 times. Command executes 3 times. + 0x2 + + + LOOP_3 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x3 + + + LOOP_4 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x4 + + + LOOP_5 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x5 + + + LOOP_6 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x6 + + + LOOP_7 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x7 + + + LOOP_8 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x8 + + + LOOP_9 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x9 + + + LOOP_15 + Loop 15 times. Command executes 16 times. + 0xF + + + + + NEXT + Next Command Select + 24 + 4 + read-write + + + NEXT_0 + No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. + 0 + + + NEXT_1 + Select CMD1 command buffer register as next command. + 0x1 + + + NEXT_2 + Select corresponding CMD command buffer register as next command + 0x2 + + + NEXT_3 + Select corresponding CMD command buffer register as next command + 0x3 + + + NEXT_4 + Select corresponding CMD command buffer register as next command + 0x4 + + + NEXT_5 + Select corresponding CMD command buffer register as next command + 0x5 + + + NEXT_6 + Select corresponding CMD command buffer register as next command + 0x6 + + + NEXT_7 + Select corresponding CMD command buffer register as next command + 0x7 + + + NEXT_8 + Select corresponding CMD command buffer register as next command + 0x8 + + + NEXT_9 + Select corresponding CMD command buffer register as next command + 0x9 + + + NEXT_15 + Select CMD15 command buffer register as next command. + 0xF + + + + + + + CMDL8 + ADC Command Low Buffer Register + 0x138 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADCH + Input channel select + 0 + 5 + read-write + + + ADCH_0 + Select CH0A or CH0B or CH0A/CH0B pair. + 0 + + + ADCH_1 + Select CH1A or CH1B or CH1A/CH1B pair. + 0x1 + + + ADCH_2 + Select CH2A or CH2B or CH2A/CH2B pair. + 0x2 + + + ADCH_3 + Select CH3A or CH3B or CH3A/CH3B pair. + 0x3 + + + ADCH_4 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x4 + + + ADCH_5 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x5 + + + ADCH_6 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x6 + + + ADCH_7 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x7 + + + ADCH_8 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x8 + + + ADCH_9 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x9 + + + ADCH_30 + Select CH30A or CH30B or CH30A/CH30B pair. + 0x1E + + + ADCH_31 + Select CH31A or CH31B or CH31A/CH31B pair. + 0x1F + + + + + CTYPE + Conversion Type + 5 + 2 + read-write + + + CTYPE_0 + Single-Ended Mode. Only A side channel is converted. + 0 + + + CTYPE_1 + Single-Ended Mode. Only B side channel is converted. + 0x1 + + + CTYPE_2 + Differential Mode. A-B. + 0x2 + + + CTYPE_3 + Dual-Single-Ended Mode. Both A side and B side channels are converted independently. + 0x3 + + + + + MODE + Select resolution of conversions + 7 + 1 + read-write + + + MODE_0 + Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. + 0 + + + MODE_1 + High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. + 0x1 + + + + + + + CMDH8 + ADC Command High Buffer Register + 0x13C + 32 + read-write + 0 + 0xFFFFFFFF + + + WAIT_TRIG + Wait for trigger assertion before execution. + 2 + 1 + read-write + + + WAIT_TRIG_0 + This command will be automatically executed. + 0 + + + WAIT_TRIG_1 + The active trigger must be asserted again before executing this command. + 0x1 + + + + + LWI + Loop with Increment + 7 + 1 + read-write + + + LWI_0 + Auto channel increment disabled + 0 + + + LWI_1 + Auto channel increment enabled + 0x1 + + + + + STS + Sample Time Select + 8 + 3 + read-write + + + STS_0 + Minimum sample time of 3 ADCK cycles. + 0 + + + STS_1 + 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. + 0x1 + + + STS_2 + 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. + 0x2 + + + STS_3 + 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. + 0x3 + + + STS_4 + 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. + 0x4 + + + STS_5 + 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. + 0x5 + + + STS_6 + 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. + 0x6 + + + STS_7 + 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. + 0x7 + + + + + AVGS + Hardware Average Select + 12 + 3 + read-write + + + AVGS_0 + Single conversion. + 0 + + + AVGS_1 + 2 conversions averaged. + 0x1 + + + AVGS_2 + 4 conversions averaged. + 0x2 + + + AVGS_3 + 8 conversions averaged. + 0x3 + + + AVGS_4 + 16 conversions averaged. + 0x4 + + + AVGS_5 + 32 conversions averaged. + 0x5 + + + AVGS_6 + 64 conversions averaged. + 0x6 + + + AVGS_7 + 128 conversions averaged. + 0x7 + + + + + LOOP + Loop Count Select + 16 + 4 + read-write + + + LOOP_0 + Looping not enabled. Command executes 1 time. + 0 + + + LOOP_1 + Loop 1 time. Command executes 2 times. + 0x1 + + + LOOP_2 + Loop 2 times. Command executes 3 times. + 0x2 + + + LOOP_3 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x3 + + + LOOP_4 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x4 + + + LOOP_5 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x5 + + + LOOP_6 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x6 + + + LOOP_7 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x7 + + + LOOP_8 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x8 + + + LOOP_9 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x9 + + + LOOP_15 + Loop 15 times. Command executes 16 times. + 0xF + + + + + NEXT + Next Command Select + 24 + 4 + read-write + + + NEXT_0 + No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. + 0 + + + NEXT_1 + Select CMD1 command buffer register as next command. + 0x1 + + + NEXT_2 + Select corresponding CMD command buffer register as next command + 0x2 + + + NEXT_3 + Select corresponding CMD command buffer register as next command + 0x3 + + + NEXT_4 + Select corresponding CMD command buffer register as next command + 0x4 + + + NEXT_5 + Select corresponding CMD command buffer register as next command + 0x5 + + + NEXT_6 + Select corresponding CMD command buffer register as next command + 0x6 + + + NEXT_7 + Select corresponding CMD command buffer register as next command + 0x7 + + + NEXT_8 + Select corresponding CMD command buffer register as next command + 0x8 + + + NEXT_9 + Select corresponding CMD command buffer register as next command + 0x9 + + + NEXT_15 + Select CMD15 command buffer register as next command. + 0xF + + + + + + + CMDL9 + ADC Command Low Buffer Register + 0x140 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADCH + Input channel select + 0 + 5 + read-write + + + ADCH_0 + Select CH0A or CH0B or CH0A/CH0B pair. + 0 + + + ADCH_1 + Select CH1A or CH1B or CH1A/CH1B pair. + 0x1 + + + ADCH_2 + Select CH2A or CH2B or CH2A/CH2B pair. + 0x2 + + + ADCH_3 + Select CH3A or CH3B or CH3A/CH3B pair. + 0x3 + + + ADCH_4 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x4 + + + ADCH_5 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x5 + + + ADCH_6 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x6 + + + ADCH_7 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x7 + + + ADCH_8 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x8 + + + ADCH_9 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x9 + + + ADCH_30 + Select CH30A or CH30B or CH30A/CH30B pair. + 0x1E + + + ADCH_31 + Select CH31A or CH31B or CH31A/CH31B pair. + 0x1F + + + + + CTYPE + Conversion Type + 5 + 2 + read-write + + + CTYPE_0 + Single-Ended Mode. Only A side channel is converted. + 0 + + + CTYPE_1 + Single-Ended Mode. Only B side channel is converted. + 0x1 + + + CTYPE_2 + Differential Mode. A-B. + 0x2 + + + CTYPE_3 + Dual-Single-Ended Mode. Both A side and B side channels are converted independently. + 0x3 + + + + + MODE + Select resolution of conversions + 7 + 1 + read-write + + + MODE_0 + Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. + 0 + + + MODE_1 + High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. + 0x1 + + + + + + + CMDH9 + ADC Command High Buffer Register + 0x144 + 32 + read-write + 0 + 0xFFFFFFFF + + + WAIT_TRIG + Wait for trigger assertion before execution. + 2 + 1 + read-write + + + WAIT_TRIG_0 + This command will be automatically executed. + 0 + + + WAIT_TRIG_1 + The active trigger must be asserted again before executing this command. + 0x1 + + + + + LWI + Loop with Increment + 7 + 1 + read-write + + + LWI_0 + Auto channel increment disabled + 0 + + + LWI_1 + Auto channel increment enabled + 0x1 + + + + + STS + Sample Time Select + 8 + 3 + read-write + + + STS_0 + Minimum sample time of 3 ADCK cycles. + 0 + + + STS_1 + 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. + 0x1 + + + STS_2 + 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. + 0x2 + + + STS_3 + 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. + 0x3 + + + STS_4 + 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. + 0x4 + + + STS_5 + 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. + 0x5 + + + STS_6 + 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. + 0x6 + + + STS_7 + 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. + 0x7 + + + + + AVGS + Hardware Average Select + 12 + 3 + read-write + + + AVGS_0 + Single conversion. + 0 + + + AVGS_1 + 2 conversions averaged. + 0x1 + + + AVGS_2 + 4 conversions averaged. + 0x2 + + + AVGS_3 + 8 conversions averaged. + 0x3 + + + AVGS_4 + 16 conversions averaged. + 0x4 + + + AVGS_5 + 32 conversions averaged. + 0x5 + + + AVGS_6 + 64 conversions averaged. + 0x6 + + + AVGS_7 + 128 conversions averaged. + 0x7 + + + + + LOOP + Loop Count Select + 16 + 4 + read-write + + + LOOP_0 + Looping not enabled. Command executes 1 time. + 0 + + + LOOP_1 + Loop 1 time. Command executes 2 times. + 0x1 + + + LOOP_2 + Loop 2 times. Command executes 3 times. + 0x2 + + + LOOP_3 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x3 + + + LOOP_4 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x4 + + + LOOP_5 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x5 + + + LOOP_6 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x6 + + + LOOP_7 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x7 + + + LOOP_8 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x8 + + + LOOP_9 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x9 + + + LOOP_15 + Loop 15 times. Command executes 16 times. + 0xF + + + + + NEXT + Next Command Select + 24 + 4 + read-write + + + NEXT_0 + No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. + 0 + + + NEXT_1 + Select CMD1 command buffer register as next command. + 0x1 + + + NEXT_2 + Select corresponding CMD command buffer register as next command + 0x2 + + + NEXT_3 + Select corresponding CMD command buffer register as next command + 0x3 + + + NEXT_4 + Select corresponding CMD command buffer register as next command + 0x4 + + + NEXT_5 + Select corresponding CMD command buffer register as next command + 0x5 + + + NEXT_6 + Select corresponding CMD command buffer register as next command + 0x6 + + + NEXT_7 + Select corresponding CMD command buffer register as next command + 0x7 + + + NEXT_8 + Select corresponding CMD command buffer register as next command + 0x8 + + + NEXT_9 + Select corresponding CMD command buffer register as next command + 0x9 + + + NEXT_15 + Select CMD15 command buffer register as next command. + 0xF + + + + + + + CMDL10 + ADC Command Low Buffer Register + 0x148 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADCH + Input channel select + 0 + 5 + read-write + + + ADCH_0 + Select CH0A or CH0B or CH0A/CH0B pair. + 0 + + + ADCH_1 + Select CH1A or CH1B or CH1A/CH1B pair. + 0x1 + + + ADCH_2 + Select CH2A or CH2B or CH2A/CH2B pair. + 0x2 + + + ADCH_3 + Select CH3A or CH3B or CH3A/CH3B pair. + 0x3 + + + ADCH_4 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x4 + + + ADCH_5 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x5 + + + ADCH_6 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x6 + + + ADCH_7 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x7 + + + ADCH_8 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x8 + + + ADCH_9 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x9 + + + ADCH_30 + Select CH30A or CH30B or CH30A/CH30B pair. + 0x1E + + + ADCH_31 + Select CH31A or CH31B or CH31A/CH31B pair. + 0x1F + + + + + CTYPE + Conversion Type + 5 + 2 + read-write + + + CTYPE_0 + Single-Ended Mode. Only A side channel is converted. + 0 + + + CTYPE_1 + Single-Ended Mode. Only B side channel is converted. + 0x1 + + + CTYPE_2 + Differential Mode. A-B. + 0x2 + + + CTYPE_3 + Dual-Single-Ended Mode. Both A side and B side channels are converted independently. + 0x3 + + + + + MODE + Select resolution of conversions + 7 + 1 + read-write + + + MODE_0 + Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. + 0 + + + MODE_1 + High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. + 0x1 + + + + + + + CMDH10 + ADC Command High Buffer Register + 0x14C + 32 + read-write + 0 + 0xFFFFFFFF + + + WAIT_TRIG + Wait for trigger assertion before execution. + 2 + 1 + read-write + + + WAIT_TRIG_0 + This command will be automatically executed. + 0 + + + WAIT_TRIG_1 + The active trigger must be asserted again before executing this command. + 0x1 + + + + + LWI + Loop with Increment + 7 + 1 + read-write + + + LWI_0 + Auto channel increment disabled + 0 + + + LWI_1 + Auto channel increment enabled + 0x1 + + + + + STS + Sample Time Select + 8 + 3 + read-write + + + STS_0 + Minimum sample time of 3 ADCK cycles. + 0 + + + STS_1 + 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. + 0x1 + + + STS_2 + 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. + 0x2 + + + STS_3 + 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. + 0x3 + + + STS_4 + 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. + 0x4 + + + STS_5 + 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. + 0x5 + + + STS_6 + 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. + 0x6 + + + STS_7 + 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. + 0x7 + + + + + AVGS + Hardware Average Select + 12 + 3 + read-write + + + AVGS_0 + Single conversion. + 0 + + + AVGS_1 + 2 conversions averaged. + 0x1 + + + AVGS_2 + 4 conversions averaged. + 0x2 + + + AVGS_3 + 8 conversions averaged. + 0x3 + + + AVGS_4 + 16 conversions averaged. + 0x4 + + + AVGS_5 + 32 conversions averaged. + 0x5 + + + AVGS_6 + 64 conversions averaged. + 0x6 + + + AVGS_7 + 128 conversions averaged. + 0x7 + + + + + LOOP + Loop Count Select + 16 + 4 + read-write + + + LOOP_0 + Looping not enabled. Command executes 1 time. + 0 + + + LOOP_1 + Loop 1 time. Command executes 2 times. + 0x1 + + + LOOP_2 + Loop 2 times. Command executes 3 times. + 0x2 + + + LOOP_3 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x3 + + + LOOP_4 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x4 + + + LOOP_5 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x5 + + + LOOP_6 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x6 + + + LOOP_7 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x7 + + + LOOP_8 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x8 + + + LOOP_9 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x9 + + + LOOP_15 + Loop 15 times. Command executes 16 times. + 0xF + + + + + NEXT + Next Command Select + 24 + 4 + read-write + + + NEXT_0 + No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. + 0 + + + NEXT_1 + Select CMD1 command buffer register as next command. + 0x1 + + + NEXT_2 + Select corresponding CMD command buffer register as next command + 0x2 + + + NEXT_3 + Select corresponding CMD command buffer register as next command + 0x3 + + + NEXT_4 + Select corresponding CMD command buffer register as next command + 0x4 + + + NEXT_5 + Select corresponding CMD command buffer register as next command + 0x5 + + + NEXT_6 + Select corresponding CMD command buffer register as next command + 0x6 + + + NEXT_7 + Select corresponding CMD command buffer register as next command + 0x7 + + + NEXT_8 + Select corresponding CMD command buffer register as next command + 0x8 + + + NEXT_9 + Select corresponding CMD command buffer register as next command + 0x9 + + + NEXT_15 + Select CMD15 command buffer register as next command. + 0xF + + + + + + + CMDL11 + ADC Command Low Buffer Register + 0x150 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADCH + Input channel select + 0 + 5 + read-write + + + ADCH_0 + Select CH0A or CH0B or CH0A/CH0B pair. + 0 + + + ADCH_1 + Select CH1A or CH1B or CH1A/CH1B pair. + 0x1 + + + ADCH_2 + Select CH2A or CH2B or CH2A/CH2B pair. + 0x2 + + + ADCH_3 + Select CH3A or CH3B or CH3A/CH3B pair. + 0x3 + + + ADCH_4 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x4 + + + ADCH_5 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x5 + + + ADCH_6 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x6 + + + ADCH_7 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x7 + + + ADCH_8 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x8 + + + ADCH_9 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x9 + + + ADCH_30 + Select CH30A or CH30B or CH30A/CH30B pair. + 0x1E + + + ADCH_31 + Select CH31A or CH31B or CH31A/CH31B pair. + 0x1F + + + + + CTYPE + Conversion Type + 5 + 2 + read-write + + + CTYPE_0 + Single-Ended Mode. Only A side channel is converted. + 0 + + + CTYPE_1 + Single-Ended Mode. Only B side channel is converted. + 0x1 + + + CTYPE_2 + Differential Mode. A-B. + 0x2 + + + CTYPE_3 + Dual-Single-Ended Mode. Both A side and B side channels are converted independently. + 0x3 + + + + + MODE + Select resolution of conversions + 7 + 1 + read-write + + + MODE_0 + Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. + 0 + + + MODE_1 + High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. + 0x1 + + + + + + + CMDH11 + ADC Command High Buffer Register + 0x154 + 32 + read-write + 0 + 0xFFFFFFFF + + + WAIT_TRIG + Wait for trigger assertion before execution. + 2 + 1 + read-write + + + WAIT_TRIG_0 + This command will be automatically executed. + 0 + + + WAIT_TRIG_1 + The active trigger must be asserted again before executing this command. + 0x1 + + + + + LWI + Loop with Increment + 7 + 1 + read-write + + + LWI_0 + Auto channel increment disabled + 0 + + + LWI_1 + Auto channel increment enabled + 0x1 + + + + + STS + Sample Time Select + 8 + 3 + read-write + + + STS_0 + Minimum sample time of 3 ADCK cycles. + 0 + + + STS_1 + 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. + 0x1 + + + STS_2 + 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. + 0x2 + + + STS_3 + 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. + 0x3 + + + STS_4 + 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. + 0x4 + + + STS_5 + 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. + 0x5 + + + STS_6 + 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. + 0x6 + + + STS_7 + 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. + 0x7 + + + + + AVGS + Hardware Average Select + 12 + 3 + read-write + + + AVGS_0 + Single conversion. + 0 + + + AVGS_1 + 2 conversions averaged. + 0x1 + + + AVGS_2 + 4 conversions averaged. + 0x2 + + + AVGS_3 + 8 conversions averaged. + 0x3 + + + AVGS_4 + 16 conversions averaged. + 0x4 + + + AVGS_5 + 32 conversions averaged. + 0x5 + + + AVGS_6 + 64 conversions averaged. + 0x6 + + + AVGS_7 + 128 conversions averaged. + 0x7 + + + + + LOOP + Loop Count Select + 16 + 4 + read-write + + + LOOP_0 + Looping not enabled. Command executes 1 time. + 0 + + + LOOP_1 + Loop 1 time. Command executes 2 times. + 0x1 + + + LOOP_2 + Loop 2 times. Command executes 3 times. + 0x2 + + + LOOP_3 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x3 + + + LOOP_4 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x4 + + + LOOP_5 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x5 + + + LOOP_6 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x6 + + + LOOP_7 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x7 + + + LOOP_8 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x8 + + + LOOP_9 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x9 + + + LOOP_15 + Loop 15 times. Command executes 16 times. + 0xF + + + + + NEXT + Next Command Select + 24 + 4 + read-write + + + NEXT_0 + No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. + 0 + + + NEXT_1 + Select CMD1 command buffer register as next command. + 0x1 + + + NEXT_2 + Select corresponding CMD command buffer register as next command + 0x2 + + + NEXT_3 + Select corresponding CMD command buffer register as next command + 0x3 + + + NEXT_4 + Select corresponding CMD command buffer register as next command + 0x4 + + + NEXT_5 + Select corresponding CMD command buffer register as next command + 0x5 + + + NEXT_6 + Select corresponding CMD command buffer register as next command + 0x6 + + + NEXT_7 + Select corresponding CMD command buffer register as next command + 0x7 + + + NEXT_8 + Select corresponding CMD command buffer register as next command + 0x8 + + + NEXT_9 + Select corresponding CMD command buffer register as next command + 0x9 + + + NEXT_15 + Select CMD15 command buffer register as next command. + 0xF + + + + + + + CMDL12 + ADC Command Low Buffer Register + 0x158 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADCH + Input channel select + 0 + 5 + read-write + + + ADCH_0 + Select CH0A or CH0B or CH0A/CH0B pair. + 0 + + + ADCH_1 + Select CH1A or CH1B or CH1A/CH1B pair. + 0x1 + + + ADCH_2 + Select CH2A or CH2B or CH2A/CH2B pair. + 0x2 + + + ADCH_3 + Select CH3A or CH3B or CH3A/CH3B pair. + 0x3 + + + ADCH_4 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x4 + + + ADCH_5 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x5 + + + ADCH_6 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x6 + + + ADCH_7 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x7 + + + ADCH_8 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x8 + + + ADCH_9 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x9 + + + ADCH_30 + Select CH30A or CH30B or CH30A/CH30B pair. + 0x1E + + + ADCH_31 + Select CH31A or CH31B or CH31A/CH31B pair. + 0x1F + + + + + CTYPE + Conversion Type + 5 + 2 + read-write + + + CTYPE_0 + Single-Ended Mode. Only A side channel is converted. + 0 + + + CTYPE_1 + Single-Ended Mode. Only B side channel is converted. + 0x1 + + + CTYPE_2 + Differential Mode. A-B. + 0x2 + + + CTYPE_3 + Dual-Single-Ended Mode. Both A side and B side channels are converted independently. + 0x3 + + + + + MODE + Select resolution of conversions + 7 + 1 + read-write + + + MODE_0 + Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. + 0 + + + MODE_1 + High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. + 0x1 + + + + + + + CMDH12 + ADC Command High Buffer Register + 0x15C + 32 + read-write + 0 + 0xFFFFFFFF + + + WAIT_TRIG + Wait for trigger assertion before execution. + 2 + 1 + read-write + + + WAIT_TRIG_0 + This command will be automatically executed. + 0 + + + WAIT_TRIG_1 + The active trigger must be asserted again before executing this command. + 0x1 + + + + + LWI + Loop with Increment + 7 + 1 + read-write + + + LWI_0 + Auto channel increment disabled + 0 + + + LWI_1 + Auto channel increment enabled + 0x1 + + + + + STS + Sample Time Select + 8 + 3 + read-write + + + STS_0 + Minimum sample time of 3 ADCK cycles. + 0 + + + STS_1 + 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. + 0x1 + + + STS_2 + 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. + 0x2 + + + STS_3 + 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. + 0x3 + + + STS_4 + 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. + 0x4 + + + STS_5 + 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. + 0x5 + + + STS_6 + 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. + 0x6 + + + STS_7 + 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. + 0x7 + + + + + AVGS + Hardware Average Select + 12 + 3 + read-write + + + AVGS_0 + Single conversion. + 0 + + + AVGS_1 + 2 conversions averaged. + 0x1 + + + AVGS_2 + 4 conversions averaged. + 0x2 + + + AVGS_3 + 8 conversions averaged. + 0x3 + + + AVGS_4 + 16 conversions averaged. + 0x4 + + + AVGS_5 + 32 conversions averaged. + 0x5 + + + AVGS_6 + 64 conversions averaged. + 0x6 + + + AVGS_7 + 128 conversions averaged. + 0x7 + + + + + LOOP + Loop Count Select + 16 + 4 + read-write + + + LOOP_0 + Looping not enabled. Command executes 1 time. + 0 + + + LOOP_1 + Loop 1 time. Command executes 2 times. + 0x1 + + + LOOP_2 + Loop 2 times. Command executes 3 times. + 0x2 + + + LOOP_3 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x3 + + + LOOP_4 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x4 + + + LOOP_5 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x5 + + + LOOP_6 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x6 + + + LOOP_7 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x7 + + + LOOP_8 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x8 + + + LOOP_9 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x9 + + + LOOP_15 + Loop 15 times. Command executes 16 times. + 0xF + + + + + NEXT + Next Command Select + 24 + 4 + read-write + + + NEXT_0 + No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. + 0 + + + NEXT_1 + Select CMD1 command buffer register as next command. + 0x1 + + + NEXT_2 + Select corresponding CMD command buffer register as next command + 0x2 + + + NEXT_3 + Select corresponding CMD command buffer register as next command + 0x3 + + + NEXT_4 + Select corresponding CMD command buffer register as next command + 0x4 + + + NEXT_5 + Select corresponding CMD command buffer register as next command + 0x5 + + + NEXT_6 + Select corresponding CMD command buffer register as next command + 0x6 + + + NEXT_7 + Select corresponding CMD command buffer register as next command + 0x7 + + + NEXT_8 + Select corresponding CMD command buffer register as next command + 0x8 + + + NEXT_9 + Select corresponding CMD command buffer register as next command + 0x9 + + + NEXT_15 + Select CMD15 command buffer register as next command. + 0xF + + + + + + + CMDL13 + ADC Command Low Buffer Register + 0x160 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADCH + Input channel select + 0 + 5 + read-write + + + ADCH_0 + Select CH0A or CH0B or CH0A/CH0B pair. + 0 + + + ADCH_1 + Select CH1A or CH1B or CH1A/CH1B pair. + 0x1 + + + ADCH_2 + Select CH2A or CH2B or CH2A/CH2B pair. + 0x2 + + + ADCH_3 + Select CH3A or CH3B or CH3A/CH3B pair. + 0x3 + + + ADCH_4 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x4 + + + ADCH_5 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x5 + + + ADCH_6 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x6 + + + ADCH_7 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x7 + + + ADCH_8 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x8 + + + ADCH_9 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x9 + + + ADCH_30 + Select CH30A or CH30B or CH30A/CH30B pair. + 0x1E + + + ADCH_31 + Select CH31A or CH31B or CH31A/CH31B pair. + 0x1F + + + + + CTYPE + Conversion Type + 5 + 2 + read-write + + + CTYPE_0 + Single-Ended Mode. Only A side channel is converted. + 0 + + + CTYPE_1 + Single-Ended Mode. Only B side channel is converted. + 0x1 + + + CTYPE_2 + Differential Mode. A-B. + 0x2 + + + CTYPE_3 + Dual-Single-Ended Mode. Both A side and B side channels are converted independently. + 0x3 + + + + + MODE + Select resolution of conversions + 7 + 1 + read-write + + + MODE_0 + Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. + 0 + + + MODE_1 + High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. + 0x1 + + + + + + + CMDH13 + ADC Command High Buffer Register + 0x164 + 32 + read-write + 0 + 0xFFFFFFFF + + + WAIT_TRIG + Wait for trigger assertion before execution. + 2 + 1 + read-write + + + WAIT_TRIG_0 + This command will be automatically executed. + 0 + + + WAIT_TRIG_1 + The active trigger must be asserted again before executing this command. + 0x1 + + + + + LWI + Loop with Increment + 7 + 1 + read-write + + + LWI_0 + Auto channel increment disabled + 0 + + + LWI_1 + Auto channel increment enabled + 0x1 + + + + + STS + Sample Time Select + 8 + 3 + read-write + + + STS_0 + Minimum sample time of 3 ADCK cycles. + 0 + + + STS_1 + 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. + 0x1 + + + STS_2 + 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. + 0x2 + + + STS_3 + 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. + 0x3 + + + STS_4 + 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. + 0x4 + + + STS_5 + 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. + 0x5 + + + STS_6 + 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. + 0x6 + + + STS_7 + 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. + 0x7 + + + + + AVGS + Hardware Average Select + 12 + 3 + read-write + + + AVGS_0 + Single conversion. + 0 + + + AVGS_1 + 2 conversions averaged. + 0x1 + + + AVGS_2 + 4 conversions averaged. + 0x2 + + + AVGS_3 + 8 conversions averaged. + 0x3 + + + AVGS_4 + 16 conversions averaged. + 0x4 + + + AVGS_5 + 32 conversions averaged. + 0x5 + + + AVGS_6 + 64 conversions averaged. + 0x6 + + + AVGS_7 + 128 conversions averaged. + 0x7 + + + + + LOOP + Loop Count Select + 16 + 4 + read-write + + + LOOP_0 + Looping not enabled. Command executes 1 time. + 0 + + + LOOP_1 + Loop 1 time. Command executes 2 times. + 0x1 + + + LOOP_2 + Loop 2 times. Command executes 3 times. + 0x2 + + + LOOP_3 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x3 + + + LOOP_4 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x4 + + + LOOP_5 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x5 + + + LOOP_6 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x6 + + + LOOP_7 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x7 + + + LOOP_8 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x8 + + + LOOP_9 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x9 + + + LOOP_15 + Loop 15 times. Command executes 16 times. + 0xF + + + + + NEXT + Next Command Select + 24 + 4 + read-write + + + NEXT_0 + No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. + 0 + + + NEXT_1 + Select CMD1 command buffer register as next command. + 0x1 + + + NEXT_2 + Select corresponding CMD command buffer register as next command + 0x2 + + + NEXT_3 + Select corresponding CMD command buffer register as next command + 0x3 + + + NEXT_4 + Select corresponding CMD command buffer register as next command + 0x4 + + + NEXT_5 + Select corresponding CMD command buffer register as next command + 0x5 + + + NEXT_6 + Select corresponding CMD command buffer register as next command + 0x6 + + + NEXT_7 + Select corresponding CMD command buffer register as next command + 0x7 + + + NEXT_8 + Select corresponding CMD command buffer register as next command + 0x8 + + + NEXT_9 + Select corresponding CMD command buffer register as next command + 0x9 + + + NEXT_15 + Select CMD15 command buffer register as next command. + 0xF + + + + + + + CMDL14 + ADC Command Low Buffer Register + 0x168 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADCH + Input channel select + 0 + 5 + read-write + + + ADCH_0 + Select CH0A or CH0B or CH0A/CH0B pair. + 0 + + + ADCH_1 + Select CH1A or CH1B or CH1A/CH1B pair. + 0x1 + + + ADCH_2 + Select CH2A or CH2B or CH2A/CH2B pair. + 0x2 + + + ADCH_3 + Select CH3A or CH3B or CH3A/CH3B pair. + 0x3 + + + ADCH_4 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x4 + + + ADCH_5 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x5 + + + ADCH_6 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x6 + + + ADCH_7 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x7 + + + ADCH_8 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x8 + + + ADCH_9 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x9 + + + ADCH_30 + Select CH30A or CH30B or CH30A/CH30B pair. + 0x1E + + + ADCH_31 + Select CH31A or CH31B or CH31A/CH31B pair. + 0x1F + + + + + CTYPE + Conversion Type + 5 + 2 + read-write + + + CTYPE_0 + Single-Ended Mode. Only A side channel is converted. + 0 + + + CTYPE_1 + Single-Ended Mode. Only B side channel is converted. + 0x1 + + + CTYPE_2 + Differential Mode. A-B. + 0x2 + + + CTYPE_3 + Dual-Single-Ended Mode. Both A side and B side channels are converted independently. + 0x3 + + + + + MODE + Select resolution of conversions + 7 + 1 + read-write + + + MODE_0 + Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. + 0 + + + MODE_1 + High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. + 0x1 + + + + + + + CMDH14 + ADC Command High Buffer Register + 0x16C + 32 + read-write + 0 + 0xFFFFFFFF + + + WAIT_TRIG + Wait for trigger assertion before execution. + 2 + 1 + read-write + + + WAIT_TRIG_0 + This command will be automatically executed. + 0 + + + WAIT_TRIG_1 + The active trigger must be asserted again before executing this command. + 0x1 + + + + + LWI + Loop with Increment + 7 + 1 + read-write + + + LWI_0 + Auto channel increment disabled + 0 + + + LWI_1 + Auto channel increment enabled + 0x1 + + + + + STS + Sample Time Select + 8 + 3 + read-write + + + STS_0 + Minimum sample time of 3 ADCK cycles. + 0 + + + STS_1 + 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. + 0x1 + + + STS_2 + 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. + 0x2 + + + STS_3 + 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. + 0x3 + + + STS_4 + 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. + 0x4 + + + STS_5 + 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. + 0x5 + + + STS_6 + 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. + 0x6 + + + STS_7 + 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. + 0x7 + + + + + AVGS + Hardware Average Select + 12 + 3 + read-write + + + AVGS_0 + Single conversion. + 0 + + + AVGS_1 + 2 conversions averaged. + 0x1 + + + AVGS_2 + 4 conversions averaged. + 0x2 + + + AVGS_3 + 8 conversions averaged. + 0x3 + + + AVGS_4 + 16 conversions averaged. + 0x4 + + + AVGS_5 + 32 conversions averaged. + 0x5 + + + AVGS_6 + 64 conversions averaged. + 0x6 + + + AVGS_7 + 128 conversions averaged. + 0x7 + + + + + LOOP + Loop Count Select + 16 + 4 + read-write + + + LOOP_0 + Looping not enabled. Command executes 1 time. + 0 + + + LOOP_1 + Loop 1 time. Command executes 2 times. + 0x1 + + + LOOP_2 + Loop 2 times. Command executes 3 times. + 0x2 + + + LOOP_3 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x3 + + + LOOP_4 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x4 + + + LOOP_5 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x5 + + + LOOP_6 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x6 + + + LOOP_7 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x7 + + + LOOP_8 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x8 + + + LOOP_9 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x9 + + + LOOP_15 + Loop 15 times. Command executes 16 times. + 0xF + + + + + NEXT + Next Command Select + 24 + 4 + read-write + + + NEXT_0 + No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. + 0 + + + NEXT_1 + Select CMD1 command buffer register as next command. + 0x1 + + + NEXT_2 + Select corresponding CMD command buffer register as next command + 0x2 + + + NEXT_3 + Select corresponding CMD command buffer register as next command + 0x3 + + + NEXT_4 + Select corresponding CMD command buffer register as next command + 0x4 + + + NEXT_5 + Select corresponding CMD command buffer register as next command + 0x5 + + + NEXT_6 + Select corresponding CMD command buffer register as next command + 0x6 + + + NEXT_7 + Select corresponding CMD command buffer register as next command + 0x7 + + + NEXT_8 + Select corresponding CMD command buffer register as next command + 0x8 + + + NEXT_9 + Select corresponding CMD command buffer register as next command + 0x9 + + + NEXT_15 + Select CMD15 command buffer register as next command. + 0xF + + + + + + + CMDL15 + ADC Command Low Buffer Register + 0x170 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADCH + Input channel select + 0 + 5 + read-write + + + ADCH_0 + Select CH0A or CH0B or CH0A/CH0B pair. + 0 + + + ADCH_1 + Select CH1A or CH1B or CH1A/CH1B pair. + 0x1 + + + ADCH_2 + Select CH2A or CH2B or CH2A/CH2B pair. + 0x2 + + + ADCH_3 + Select CH3A or CH3B or CH3A/CH3B pair. + 0x3 + + + ADCH_4 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x4 + + + ADCH_5 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x5 + + + ADCH_6 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x6 + + + ADCH_7 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x7 + + + ADCH_8 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x8 + + + ADCH_9 + Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + 0x9 + + + ADCH_30 + Select CH30A or CH30B or CH30A/CH30B pair. + 0x1E + + + ADCH_31 + Select CH31A or CH31B or CH31A/CH31B pair. + 0x1F + + + + + CTYPE + Conversion Type + 5 + 2 + read-write + + + CTYPE_0 + Single-Ended Mode. Only A side channel is converted. + 0 + + + CTYPE_1 + Single-Ended Mode. Only B side channel is converted. + 0x1 + + + CTYPE_2 + Differential Mode. A-B. + 0x2 + + + CTYPE_3 + Dual-Single-Ended Mode. Both A side and B side channels are converted independently. + 0x3 + + + + + MODE + Select resolution of conversions + 7 + 1 + read-write + + + MODE_0 + Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. + 0 + + + MODE_1 + High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. + 0x1 + + + + + + + CMDH15 + ADC Command High Buffer Register + 0x174 + 32 + read-write + 0 + 0xFFFFFFFF + + + WAIT_TRIG + Wait for trigger assertion before execution. + 2 + 1 + read-write + + + WAIT_TRIG_0 + This command will be automatically executed. + 0 + + + WAIT_TRIG_1 + The active trigger must be asserted again before executing this command. + 0x1 + + + + + LWI + Loop with Increment + 7 + 1 + read-write + + + LWI_0 + Auto channel increment disabled + 0 + + + LWI_1 + Auto channel increment enabled + 0x1 + + + + + STS + Sample Time Select + 8 + 3 + read-write + + + STS_0 + Minimum sample time of 3 ADCK cycles. + 0 + + + STS_1 + 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. + 0x1 + + + STS_2 + 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. + 0x2 + + + STS_3 + 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. + 0x3 + + + STS_4 + 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. + 0x4 + + + STS_5 + 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. + 0x5 + + + STS_6 + 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. + 0x6 + + + STS_7 + 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. + 0x7 + + + + + AVGS + Hardware Average Select + 12 + 3 + read-write + + + AVGS_0 + Single conversion. + 0 + + + AVGS_1 + 2 conversions averaged. + 0x1 + + + AVGS_2 + 4 conversions averaged. + 0x2 + + + AVGS_3 + 8 conversions averaged. + 0x3 + + + AVGS_4 + 16 conversions averaged. + 0x4 + + + AVGS_5 + 32 conversions averaged. + 0x5 + + + AVGS_6 + 64 conversions averaged. + 0x6 + + + AVGS_7 + 128 conversions averaged. + 0x7 + + + + + LOOP + Loop Count Select + 16 + 4 + read-write + + + LOOP_0 + Looping not enabled. Command executes 1 time. + 0 + + + LOOP_1 + Loop 1 time. Command executes 2 times. + 0x1 + + + LOOP_2 + Loop 2 times. Command executes 3 times. + 0x2 + + + LOOP_3 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x3 + + + LOOP_4 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x4 + + + LOOP_5 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x5 + + + LOOP_6 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x6 + + + LOOP_7 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x7 + + + LOOP_8 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x8 + + + LOOP_9 + Loop corresponding number of times. Command executes LOOP+1 times. + 0x9 + + + LOOP_15 + Loop 15 times. Command executes 16 times. + 0xF + + + + + NEXT + Next Command Select + 24 + 4 + read-write + + + NEXT_0 + No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. + 0 + + + NEXT_1 + Select CMD1 command buffer register as next command. + 0x1 + + + NEXT_2 + Select corresponding CMD command buffer register as next command + 0x2 + + + NEXT_3 + Select corresponding CMD command buffer register as next command + 0x3 + + + NEXT_4 + Select corresponding CMD command buffer register as next command + 0x4 + + + NEXT_5 + Select corresponding CMD command buffer register as next command + 0x5 + + + NEXT_6 + Select corresponding CMD command buffer register as next command + 0x6 + + + NEXT_7 + Select corresponding CMD command buffer register as next command + 0x7 + + + NEXT_8 + Select corresponding CMD command buffer register as next command + 0x8 + + + NEXT_9 + Select corresponding CMD command buffer register as next command + 0x9 + + + NEXT_15 + Select CMD15 command buffer register as next command. + 0xF + + + + + + + 4 + 0x4 + 1,2,3,4 + CV%s + Compare Value Register + 0x200 + 32 + read-write + 0 + 0xFFFFFFFF + + + CVL + Compare Value Low. + 0 + 16 + read-write + + + CVH + Compare Value High. + 16 + 16 + read-write + + + + + 2 + 0x4 + RESFIFO[%s] + ADC Data Result FIFO Register + 0x300 + 32 + read-only + 0 + 0xFFFFFFFF + + + D + Data result + 0 + 16 + read-only + + + TSRC + Trigger Source + 16 + 4 + read-only + + + TSRC_0 + Trigger source 0 initiated this conversion. + 0 + + + TSRC_1 + Trigger source 1 initiated this conversion. + 0x1 + + + TSRC_2 + Corresponding trigger source initiated this conversion. + 0x2 + + + TSRC_3 + Corresponding trigger source initiated this conversion. + 0x3 + + + TSRC_4 + Corresponding trigger source initiated this conversion. + 0x4 + + + TSRC_5 + Corresponding trigger source initiated this conversion. + 0x5 + + + TSRC_6 + Corresponding trigger source initiated this conversion. + 0x6 + + + TSRC_7 + Corresponding trigger source initiated this conversion. + 0x7 + + + TSRC_8 + Corresponding trigger source initiated this conversion. + 0x8 + + + TSRC_9 + Corresponding trigger source initiated this conversion. + 0x9 + + + TSRC_15 + Trigger source 15 initiated this conversion. + 0xF + + + + + LOOPCNT + Loop count value + 20 + 4 + read-only + + + LOOPCNT_0 + Result is from initial conversion in command. + 0 + + + LOOPCNT_1 + Result is from second conversion in command. + 0x1 + + + LOOPCNT_2 + Result is from LOOPCNT+1 conversion in command. + 0x2 + + + LOOPCNT_3 + Result is from LOOPCNT+1 conversion in command. + 0x3 + + + LOOPCNT_4 + Result is from LOOPCNT+1 conversion in command. + 0x4 + + + LOOPCNT_5 + Result is from LOOPCNT+1 conversion in command. + 0x5 + + + LOOPCNT_6 + Result is from LOOPCNT+1 conversion in command. + 0x6 + + + LOOPCNT_7 + Result is from LOOPCNT+1 conversion in command. + 0x7 + + + LOOPCNT_8 + Result is from LOOPCNT+1 conversion in command. + 0x8 + + + LOOPCNT_9 + Result is from LOOPCNT+1 conversion in command. + 0x9 + + + LOOPCNT_15 + Result is from 16th conversion in command. + 0xF + + + + + CMDSRC + Command Buffer Source + 24 + 4 + read-only + + + CMDSRC_0 + Not a valid value CMDSRC value for a dataword in RESFIFO. 0x0 is only found in initial FIFO state prior to an ADC conversion result dataword being stored to a RESFIFO buffer. + 0 + + + CMDSRC_1 + CMD1 buffer used as control settings for this conversion. + 0x1 + + + CMDSRC_2 + Corresponding command buffer used as control settings for this conversion. + 0x2 + + + CMDSRC_3 + Corresponding command buffer used as control settings for this conversion. + 0x3 + + + CMDSRC_4 + Corresponding command buffer used as control settings for this conversion. + 0x4 + + + CMDSRC_5 + Corresponding command buffer used as control settings for this conversion. + 0x5 + + + CMDSRC_6 + Corresponding command buffer used as control settings for this conversion. + 0x6 + + + CMDSRC_7 + Corresponding command buffer used as control settings for this conversion. + 0x7 + + + CMDSRC_8 + Corresponding command buffer used as control settings for this conversion. + 0x8 + + + CMDSRC_9 + Corresponding command buffer used as control settings for this conversion. + 0x9 + + + CMDSRC_15 + CMD15 buffer used as control settings for this conversion. + 0xF + + + + + VALID + FIFO entry is valid + 31 + 1 + read-only + + + VALID_0 + FIFO is empty. Discard any read from RESFIFO. + 0 + + + VALID_1 + FIFO record read from RESFIFO is valid. + 0x1 + + + + + + + 33 + 0x4 + CAL_GAR[%s] + Calibration General A-Side Registers + 0x400 + 32 + read-write + 0 + 0xFFFFFFFF + + + CAL_GAR_VAL + Calibration General A Side Register Element + 0 + 16 + read-write + + + + + 33 + 0x4 + CAL_GBR[%s] + Calibration General B-Side Registers + 0x500 + 32 + read-write + 0 + 0xFFFFFFFF + + + CAL_GBR_VAL + Calibration General B Side Register Element + 0 + 16 + read-write + + + + + TST + ADC Test Register + 0xFFC + 32 + read-write + 0 + 0xFFFFFFFF + + + CST_LONG + Calibration Sample Time Long + 0 + 1 + read-write + + + CST_LONG_0 + Normal sample time. Minimum sample time of 3 ADCK cycles. + 0 + + + CST_LONG_1 + Increased sample time. 67 ADCK cycles total sample time. + 0x1 + + + + + FOFFM + Force M-side positive offset + 8 + 1 + read-write + + + FOFFM_0 + Normal operation. No forced offset. + 0 + + + FOFFM_1 + Test configuration. Forced positive offset on MDAC. + 0x1 + + + + + FOFFP + Force P-side positive offset + 9 + 1 + read-write + + + FOFFP_0 + Normal operation. No forced offset. + 0 + + + FOFFP_1 + Test configuration. Forced positive offset on PDAC. + 0x1 + + + + + FOFFM2 + Force M-side negative offset + 10 + 1 + read-write + + + FOFFM2_0 + Normal operation. No forced offset. + 0 + + + FOFFM2_1 + Test configuration. Forced negative offset on MDAC. + 0x1 + + + + + FOFFP2 + Force P-side negative offset + 11 + 1 + read-write + + + FOFFP2_0 + Normal operation. No forced offset. + 0 + + + FOFFP2_1 + Test configuration. Forced negative offset on PDAC. + 0x1 + + + + + TESTEN + Enable test configuration + 23 + 1 + read-write + + + TESTEN_0 + Normal operation. Test configuration not enabled. + 0 + + + TESTEN_1 + Hardware BIST Test in progress. + 0x1 + + + + + + + + + USBFSH + USB0 Full-speed Host controller + USBFSH + 0x400A2000 + + 0 + 0x60 + registers + + + USB0_NEEDCLK + 27 + + + USB0 + 28 + + + + HCREVISION + BCD representation of the version of the HCI specification that is implemented by the Host Controller (HC) + 0 + 32 + read-only + 0x10 + 0xFF + + + REV + Revision. + 0 + 8 + read-only + + + + + HCCONTROL + Defines the operating modes of the HC + 0x4 + 32 + read-write + 0 + 0x7FF + + + CBSR + ControlBulkServiceRatio. + 0 + 2 + read-write + + + PLE + PeriodicListEnable. + 2 + 1 + read-write + + + IE + IsochronousEnable. + 3 + 1 + read-write + + + CLE + ControlListEnable. + 4 + 1 + read-write + + + BLE + BulkListEnable This bit is set to enable the processing of the Bulk list in the next Frame. + 5 + 1 + read-write + + + HCFS + HostControllerFunctionalState for USB 00b: USBRESET 01b: USBRESUME 10b: USBOPERATIONAL 11b: USBSUSPEND A transition to USBOPERATIONAL from another state causes SOFgeneration to begin 1 ms later. + 6 + 2 + read-write + + + IR + InterruptRouting This bit determines the routing of interrupts generated by events registered in HcInterruptStatus. + 8 + 1 + read-write + + + RWC + RemoteWakeupConnected This bit indicates whether HC supports remote wake-up signaling. + 9 + 1 + read-write + + + RWE + RemoteWakeupEnable This bit is used by HCD to enable or disable the remote wake-up feature upon the detection of upstream resume signaling. + 10 + 1 + read-write + + + + + HCCOMMANDSTATUS + This register is used to receive the commands from the Host Controller Driver (HCD) + 0x8 + 32 + read-write + 0 + 0xCF + + + HCR + HostControllerReset This bit is set by HCD to initiate a software reset of HC. + 0 + 1 + read-write + + + CLF + ControlListFilled This bit is used to indicate whether there are any TDs on the Control list. + 1 + 1 + read-write + + + BLF + BulkListFilled This bit is used to indicate whether there are any TDs on the Bulk list. + 2 + 1 + read-write + + + OCR + OwnershipChangeRequest This bit is set by an OS HCD to request a change of control of the HC. + 3 + 1 + read-write + + + SOC + SchedulingOverrunCount These bits are incremented on each scheduling overrun error. + 6 + 2 + read-write + + + + + HCINTERRUPTSTATUS + Indicates the status on various events that cause hardware interrupts by setting the appropriate bits + 0xC + 32 + read-write + 0 + 0xFFFFFC7F + + + SO + SchedulingOverrun This bit is set when the USB schedule for the current Frame overruns and after the update of HccaFrameNumber. + 0 + 1 + read-write + + + WDH + WritebackDoneHead This bit is set immediately after HC has written HcDoneHead to HccaDoneHead. + 1 + 1 + read-write + + + SF + StartofFrame This bit is set by HC at each start of a frame and after the update of HccaFrameNumber. + 2 + 1 + read-write + + + RD + ResumeDetected This bit is set when HC detects that a device on the USB is asserting resume signaling. + 3 + 1 + read-write + + + UE + UnrecoverableError This bit is set when HC detects a system error not related to USB. + 4 + 1 + read-write + + + FNO + FrameNumberOverflow This bit is set when the MSb of HcFmNumber (bit 15) changes value, from 0 to 1 or from 1 to 0, and after HccaFrameNumber has been updated. + 5 + 1 + read-write + + + RHSC + RootHubStatusChange This bit is set when the content of HcRhStatus or the content of any of HcRhPortStatus[NumberofDownstreamPort] has changed. + 6 + 1 + read-write + + + OC + OwnershipChange This bit is set by HC when HCD sets the OwnershipChangeRequest field in HcCommandStatus. + 10 + 22 + read-write + + + + + HCINTERRUPTENABLE + Controls the bits in the HcInterruptStatus register and indicates which events will generate a hardware interrupt + 0x10 + 32 + read-write + 0 + 0xC000007F + + + SO + Scheduling Overrun interrupt. + 0 + 1 + read-write + + + WDH + HcDoneHead Writeback interrupt. + 1 + 1 + read-write + + + SF + Start of Frame interrupt. + 2 + 1 + read-write + + + RD + Resume Detect interrupt. + 3 + 1 + read-write + + + UE + Unrecoverable Error interrupt. + 4 + 1 + read-write + + + FNO + Frame Number Overflow interrupt. + 5 + 1 + read-write + + + RHSC + Root Hub Status Change interrupt. + 6 + 1 + read-write + + + OC + Ownership Change interrupt. + 30 + 1 + read-write + + + MIE + Master Interrupt Enable. + 31 + 1 + read-write + + + + + HCINTERRUPTDISABLE + The bits in this register are used to disable corresponding bits in the HCInterruptStatus register and in turn disable that event leading to hardware interrupt + 0x14 + 32 + read-write + 0 + 0xC000007F + + + SO + Scheduling Overrun interrupt. + 0 + 1 + read-write + + + WDH + HcDoneHead Writeback interrupt. + 1 + 1 + read-write + + + SF + Start of Frame interrupt. + 2 + 1 + read-write + + + RD + Resume Detect interrupt. + 3 + 1 + read-write + + + UE + Unrecoverable Error interrupt. + 4 + 1 + read-write + + + FNO + Frame Number Overflow interrupt. + 5 + 1 + read-write + + + RHSC + Root Hub Status Change interrupt. + 6 + 1 + read-write + + + OC + Ownership Change interrupt. + 30 + 1 + read-write + + + MIE + A 0 written to this field is ignored by HC. + 31 + 1 + read-write + + + + + HCHCCA + Contains the physical address of the host controller communication area + 0x18 + 32 + read-write + 0 + 0xFFFFFF00 + + + HCCA + Base address of the Host Controller Communication Area. + 8 + 24 + read-write + + + + + HCPERIODCURRENTED + Contains the physical address of the current isochronous or interrupt endpoint descriptor + 0x1C + 32 + read-write + 0 + 0xFFFFFFF0 + + + PCED + The content of this register is updated by HC after a periodic ED is processed. + 4 + 28 + read-write + + + + + HCCONTROLHEADED + Contains the physical address of the first endpoint descriptor of the control list + 0x20 + 32 + read-write + 0 + 0xFFFFFFF0 + + + CHED + HC traverses the Control list starting with the HcControlHeadED pointer. + 4 + 28 + read-write + + + + + HCCONTROLCURRENTED + Contains the physical address of the current endpoint descriptor of the control list + 0x24 + 32 + read-write + 0 + 0xFFFFFFF0 + + + CCED + ControlCurrentED. + 4 + 28 + read-write + + + + + HCBULKHEADED + Contains the physical address of the first endpoint descriptor of the bulk list + 0x28 + 32 + read-write + 0 + 0xFFFFFFF0 + + + BHED + BulkHeadED HC traverses the bulk list starting with the HcBulkHeadED pointer. + 4 + 28 + read-write + + + + + HCBULKCURRENTED + Contains the physical address of the current endpoint descriptor of the bulk list + 0x2C + 32 + read-write + 0 + 0xFFFFFFF0 + + + BCED + BulkCurrentED This is advanced to the next ED after the HC has served the current one. + 4 + 28 + read-write + + + + + HCDONEHEAD + Contains the physical address of the last transfer descriptor added to the 'Done' queue + 0x30 + 32 + read-write + 0 + 0xFFFFFFF0 + + + DH + DoneHead When a TD is completed, HC writes the content of HcDoneHead to the NextTD field of the TD. + 4 + 28 + read-write + + + + + HCFMINTERVAL + Defines the bit time interval in a frame and the full speed maximum packet size which would not cause an overrun + 0x34 + 32 + read-write + 0x2EDF + 0xFFFF3FFF + + + FI + FrameInterval This specifies the interval between two consecutive SOFs in bit times. + 0 + 14 + read-write + + + FSMPS + FSLargestDataPacket This field specifies a value which is loaded into the Largest Data Packet Counter at the beginning of each frame. + 16 + 15 + read-write + + + FIT + FrameIntervalToggle HCD toggles this bit whenever it loads a new value to FrameInterval. + 31 + 1 + read-write + + + + + HCFMREMAINING + A 14-bit counter showing the bit time remaining in the current frame + 0x38 + 32 + read-write + 0 + 0x80003FFF + + + FR + FrameRemaining This counter is decremented at each bit time. + 0 + 14 + read-write + + + FRT + FrameRemainingToggle This bit is loaded from the FrameIntervalToggle field of HcFmInterval whenever FrameRemaining reaches 0. + 31 + 1 + read-write + + + + + HCFMNUMBER + Contains a 16-bit counter and provides the timing reference among events happening in the HC and the HCD + 0x3C + 32 + read-write + 0 + 0xFFFF + + + FN + FrameNumber This is incremented when HcFmRemaining is re-loaded. + 0 + 16 + read-write + + + + + HCPERIODICSTART + Contains a programmable 14-bit value which determines the earliest time HC should start processing a periodic list + 0x40 + 32 + read-write + 0 + 0x3FFF + + + PS + PeriodicStart After a hardware reset, this field is cleared and then set by HCD during the HC initialization. + 0 + 14 + read-write + + + + + HCLSTHRESHOLD + Contains 11-bit value which is used by the HC to determine whether to commit to transfer a maximum of 8-byte LS packet before EOF + 0x44 + 32 + read-write + 0x628 + 0xFFF + + + LST + LSThreshold This field contains a value which is compared to the FrameRemaining field prior to initiating a Low Speed transaction. + 0 + 12 + read-write + + + + + HCRHDESCRIPTORA + First of the two registers which describes the characteristics of the root hub + 0x48 + 32 + read-write + 0xFF000902 + 0xFF001FFF + + + NDP + NumberDownstreamPorts These bits specify the number of downstream ports supported by the root hub. + 0 + 8 + read-write + + + PSM + PowerSwitchingMode This bit is used to specify how the power switching of the root hub ports is controlled. + 8 + 1 + read-write + + + NPS + NoPowerSwitching These bits are used to specify whether power switching is supported or port are always powered. + 9 + 1 + read-write + + + DT + DeviceType This bit specifies that the root hub is not a compound device. + 10 + 1 + read-write + + + OCPM + OverCurrentProtectionMode This bit describes how the overcurrent status for the root hub ports are reported. + 11 + 1 + read-write + + + NOCP + NoOverCurrentProtection This bit describes how the overcurrent status for the root hub ports are reported. + 12 + 1 + read-write + + + POTPGT + PowerOnToPowerGoodTime This byte specifies the duration the HCD has to wait before accessing a powered-on port of the root hub. + 24 + 8 + read-write + + + + + HCRHDESCRIPTORB + Second of the two registers which describes the characteristics of the Root Hub + 0x4C + 32 + read-write + 0 + 0x3FFFFFFF + + + DR + DeviceRemovable Each bit is dedicated to a port of the Root Hub. + 0 + 16 + read-write + + + PPCM + PortPowerControlMask Each bit indicates if a port is affected by a global power control command when PowerSwitchingMode is set. + 16 + 16 + read-write + + + + + HCRHSTATUS + This register is divided into two parts + 0x50 + 32 + read-write + 0 + 0x80038003 + + + LPS + (read) LocalPowerStatus The Root Hub does not support the local power status feature; thus, this bit is always read as 0. + 0 + 1 + read-write + + + OCI + OverCurrentIndicator This bit reports overcurrent conditions when the global reporting is implemented. + 1 + 1 + read-write + + + DRWE + (read) DeviceRemoteWakeupEnable This bit enables a ConnectStatusChange bit as a resume event, causing a USBSUSPEND to USBRESUME state transition and setting the ResumeDetected interrupt. + 15 + 1 + read-write + + + LPSC + (read) LocalPowerStatusChange The root hub does not support the local power status feature. + 16 + 1 + read-write + + + OCIC + OverCurrentIndicatorChange This bit is set by hardware when a change has occurred to the OCI field of this register. + 17 + 1 + read-write + + + CRWE + (write) ClearRemoteWakeupEnable Writing a 1 clears DeviceRemoveWakeupEnable. + 31 + 1 + read-write + + + + + HCRHPORTSTATUS + Controls and reports the port events on a per-port basis + 0x54 + 32 + read-write + 0 + 0x1F031F + + + CCS + (read) CurrentConnectStatus This bit reflects the current state of the downstream port. + 0 + 1 + read-write + + + PES + (read) PortEnableStatus This bit indicates whether the port is enabled or disabled. + 1 + 1 + read-write + + + PSS + (read) PortSuspendStatus This bit indicates the port is suspended or in the resume sequence. + 2 + 1 + read-write + + + POCI + (read) PortOverCurrentIndicator This bit is only valid when the Root Hub is configured in such a way that overcurrent conditions are reported on a per-port basis. + 3 + 1 + read-write + + + PRS + (read) PortResetStatus When this bit is set by a write to SetPortReset, port reset signaling is asserted. + 4 + 1 + read-write + + + PPS + (read) PortPowerStatus This bit reflects the porta's power status, regardless of the type of power switching implemented. + 8 + 1 + read-write + + + LSDA + (read) LowSpeedDeviceAttached This bit indicates the speed of the device attached to this port. + 9 + 1 + read-write + + + CSC + ConnectStatusChange This bit is set whenever a connect or disconnect event occurs. + 16 + 1 + read-write + + + PESC + PortEnableStatusChange This bit is set when hardware events cause the PortEnableStatus bit to be cleared. + 17 + 1 + read-write + + + PSSC + PortSuspendStatusChange This bit is set when the full resume sequence is completed. + 18 + 1 + read-write + + + OCIC + PortOverCurrentIndicatorChange This bit is valid only if overcurrent conditions are reported on a per-port basis. + 19 + 1 + read-write + + + PRSC + PortResetStatusChange This bit is set at the end of the 10 ms port reset signal. + 20 + 1 + read-write + + + + + PORTMODE + Controls the port if it is attached to the host block or the device block + 0x5C + 32 + read-write + 0 + 0x10101 + + + ID + Port ID pin value. + 0 + 1 + read-write + + + ID_EN + Port ID pin pull-up enable. + 8 + 1 + read-write + + + DEV_ENABLE + 1: device 0: host. + 16 + 1 + read-write + + + + + + + USBHSH + USB1 High-speed Host Controller + USBHSH + 0x400A3000 + + 0 + 0x54 + registers + + + USB1_UTMI + 46 + + + USB1 + 47 + + + USB1_NEEDCLK + 48 + + + + CAPLENGTH_CHIPID + This register contains the offset value towards the start of the operational register space and the version number of the IP block + 0 + 32 + read-only + 0x1010010 + 0xFFFF00FF + + + CAPLENGTH + Capability Length: This is used as an offset. + 0 + 8 + read-only + + + CHIPID + Chip identification: indicates major and minor revision of the IP: [31:24] = Major revision [23:16] = Minor revision Major revisions used: 0x01: USB2. + 16 + 16 + read-only + + + + + HCSPARAMS + Host Controller Structural Parameters + 0x4 + 32 + read-only + 0x10011 + 0x1001F + + + N_PORTS + This register specifies the number of physical downstream ports implemented on this host controller. + 0 + 4 + read-only + + + PPC + This field indicates whether the host controller implementation includes port power control. + 4 + 1 + read-only + + + P_INDICATOR + This bit indicates whether the ports support port indicator control. + 16 + 1 + read-only + + + + + HCCPARAMS + Host Controller Capability Parameters + 0x8 + 32 + read-only + 0x20006 + 0xFFFFFFFF + + + LPMC + Link Power Management Capability. + 17 + 1 + read-only + + + + + FLADJ_FRINDEX + Frame Length Adjustment + 0xC + 32 + read-write + 0x20 + 0x3FFF003F + + + FLADJ + Frame Length Timing Value. + 0 + 6 + read-write + + + FRINDEX + Frame Index: Bits 29 to16 in this register are used for the frame number field in the SOF packet. + 16 + 14 + read-write + + + + + ATL_PTD_BASE_ADDR + Memory base address where ATL PTD0 is stored + 0x10 + 32 + read-write + 0 + 0xFFFFFFF0 + + + ATL_CUR + This indicates the current PTD that is used by the hardware when it is processing the ATL list. + 4 + 5 + read-write + + + ATL_BASE + Base address to be used by the hardware to find the start of the ATL list. + 9 + 23 + read-write + + + + + ISO_PTD_BASE_ADDR + Memory base address where ISO PTD0 is stored + 0x14 + 32 + read-write + 0 + 0xFFFFFFE0 + + + ISO_FIRST + This indicates the first PTD that is used by the hardware when it is processing the ISO list. + 5 + 5 + read-write + + + ISO_BASE + Base address to be used by the hardware to find the start of the ISO list. + 10 + 22 + read-write + + + + + INT_PTD_BASE_ADDR + Memory base address where INT PTD0 is stored + 0x18 + 32 + read-write + 0 + 0xFFFFFFE0 + + + INT_FIRST + This indicates the first PTD that is used by the hardware when it is processing the INT list. + 5 + 5 + read-write + + + INT_BASE + Base address to be used by the hardware to find the start of the INT list. + 10 + 22 + read-write + + + + + DATA_PAYLOAD_BASE_ADDR + Memory base address that indicates the start of the data payload buffers + 0x1C + 32 + read-write + 0 + 0xFFFF0000 + + + DAT_BASE + Base address to be used by the hardware to find the start of the data payload section. + 16 + 16 + read-write + + + + + USBCMD + USB Command register + 0x20 + 32 + read-write + 0 + 0x1F00078F + + + RS + Run/Stop: 1b = Run. + 0 + 1 + read-write + + + HCRESET + Host Controller Reset: This control bit is used by the software to reset the host controller. + 1 + 1 + read-write + + + FLS + Frame List Size: This field specifies the size of the frame list. + 2 + 2 + read-write + + + LHCR + Light Host Controller Reset: This bit allows the driver software to reset the host controller without affecting the state of the ports. + 7 + 1 + read-write + + + ATL_EN + ATL List enabled. + 8 + 1 + read-write + + + ISO_EN + ISO List enabled. + 9 + 1 + read-write + + + INT_EN + INT List enabled. + 10 + 1 + read-write + + + HIRD + Host-Initiated Resume Duration. + 24 + 4 + read-write + + + LPM_RWU + bRemoteWake field. + 28 + 1 + read-write + + + + + USBSTS + USB Interrupt Status register + 0x24 + 32 + read-write + 0 + 0xF000C + + + PCD + Port Change Detect: The host controller sets this bit to logic 1 when any port has a change bit transition from a 0 to a one or a Force Port Resume bit transition from a 0 to a 1 as a result of a J-K transition detected on a suspended port. + 2 + 1 + read-write + + + FLR + Frame List Rollover: The host controller sets this bit to logic 1 when the frame list index rolls over its maximum value to 0. + 3 + 1 + read-write + + + ATL_IRQ + ATL IRQ: Indicates that an ATL PTD (with I-bit set) was completed. + 16 + 1 + read-write + + + ISO_IRQ + ISO IRQ: Indicates that an ISO PTD (with I-bit set) was completed. + 17 + 1 + read-write + + + INT_IRQ + INT IRQ: Indicates that an INT PTD (with I-bit set) was completed. + 18 + 1 + read-write + + + SOF_IRQ + SOF interrupt: Every time when the host sends a Start of Frame token on the USB bus, this bit is set. + 19 + 1 + read-write + + + + + USBINTR + USB Interrupt Enable register + 0x28 + 32 + read-write + 0 + 0xF000C + + + PCDE + Port Change Detect Interrupt Enable: 1: enable 0: disable. + 2 + 1 + read-write + + + FLRE + Frame List Rollover Interrupt Enable: 1: enable 0: disable. + 3 + 1 + read-write + + + ATL_IRQ_E + ATL IRQ Enable bit: 1: enable 0: disable. + 16 + 1 + read-write + + + ISO_IRQ_E + ISO IRQ Enable bit: 1: enable 0: disable. + 17 + 1 + read-write + + + INT_IRQ_E + INT IRQ Enable bit: 1: enable 0: disable. + 18 + 1 + read-write + + + SOF_E + SOF Interrupt Enable bit: 1: enable 0: disable. + 19 + 1 + read-write + + + + + PORTSC1 + Port Status and Control register + 0x2C + 32 + read-write + 0 + 0xFFFFDFFF + + + CCS + Current Connect Status: Logic 1 indicates a device is present on the port. + 0 + 1 + read-write + + + CSC + Connect Status Change: Logic 1 means that the value of CCS has changed. + 1 + 1 + read-write + + + PED + Port Enabled/Disabled. + 2 + 1 + read-write + + + PEDC + Port Enabled/Disabled Change: Logic 1 means that the value of PED has changed. + 3 + 1 + read-write + + + OCA + Over-current active: Logic 1 means that this port has an over-current condition. + 4 + 1 + read-write + + + OCC + Over-current change: Logic 1 means that the value of OCA has changed. + 5 + 1 + read-write + + + FPR + Force Port Resume: Logic 1 means resume (K-state) detected or driven on the port. + 6 + 1 + read-write + + + SUSP + Suspend: Logic 1 means port is in the suspend state. + 7 + 1 + read-write + + + PR + Port Reset: Logic 1 means the port is in the reset state. + 8 + 1 + read-write + + + SUS_L1 + Suspend using L1 0b = Suspend using L2 1b = Suspend using L1 When this bit is set to a 1 and a non-zero value is specified in the Device Address field, the host controller will generate an LPM Token to enter the L1 state whenever software writes a one to the Suspend bit, as well as L1 exit timing during any device or host-initiated resume. + 9 + 1 + read-write + + + LS + Line Status: This field reflects the current logical levels of the DP (bit 11) and DM (bit 10) signal lines. + 10 + 2 + read-only + + + PP + Port Power: The function of this bit depends on the value of the Port Power Control (PPC) bit in the HCSPARAMS register. + 12 + 1 + read-write + + + PIC + Port Indicator Control : Writing to this field has no effect if the P_INDICATOR bit in the HCSPARAMS register is logic 0. + 14 + 2 + read-write + + + PTC + Port Test Control: A non-zero value indicates that the port is operating in the test mode as indicated by the value. + 16 + 4 + read-write + + + PSPD + Port Speed: 00b: Low-speed 01b: Full-speed 10b: High-speed 11b: Reserved. + 20 + 2 + read-write + + + WOO + Wake on overcurrent enable: Writing this bit to a one enables the port to be sensitive to overcurrent conditions as wake-up events. + 22 + 1 + read-write + + + SUS_STAT + These two bits are used by software to determine whether the most recent L1 suspend request was successful: 00b: Success-state transition was successful (ACK) 01b: Not Yet - Device was unable to enter the L1 state at this time (NYET) 10b: Not supported - Device does not support the L1 state (STALL) 11b: Timeout/Error - Device failed to respond or an error occurred. + 23 + 2 + read-write + + + DEV_ADD + Device Address for LPM tokens. + 25 + 7 + read-write + + + + + ATL_PTD_DONE_MAP + Done map for each ATL PTD + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + ATL_DONE + The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed. + 0 + 32 + read-write + + + + + ATL_PTD_SKIP_MAP + Skip map for each ATL PTD + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + ATL_SKIP + When a bit in the PTD Skip Map is set to logic 1, the corresponding PTD will be skipped, independent of the V bit setting. + 0 + 32 + read-write + + + + + ISO_PTD_DONE_MAP + Done map for each ISO PTD + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + ISO_DONE + The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed. + 0 + 32 + read-write + + + + + ISO_PTD_SKIP_MAP + Skip map for each ISO PTD + 0x3C + 32 + read-write + 0 + 0xFFFFFFFF + + + ISO_SKIP + The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed. + 0 + 32 + read-write + + + + + INT_PTD_DONE_MAP + Done map for each INT PTD + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + INT_DONE + The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed. + 0 + 32 + read-write + + + + + INT_PTD_SKIP_MAP + Skip map for each INT PTD + 0x44 + 32 + read-write + 0 + 0xFFFFFFFF + + + INT_SKIP + When a bit in the PTD Skip Map is set to logic 1, the corresponding PTD will be skipped, independent of the V bit setting. + 0 + 32 + read-write + + + + + LAST_PTD_INUSE + Marks the last PTD in the list for ISO, INT and ATL + 0x48 + 32 + read-write + 0 + 0x1F1F1F + + + ATL_LAST + If hardware has reached this PTD and the J bit is not set, it will go to PTD0 as the next PTD to be processed. + 0 + 5 + read-write + + + ISO_LAST + This indicates the last PTD in the ISO list. + 8 + 5 + read-write + + + INT_LAST + This indicates the last PTD in the INT list. + 16 + 5 + read-write + + + + + UTMIPLUS_ULPI_DEBUG + Register to read/write registers in the attached USB PHY + 0x4C + 32 + read-write + 0 + 0x83FFFFFF + + + PHY_ADDR + UTMI+ mode: Bits 3:0 are used to control VControl signal on Vendor Interface of UTMI+ ULPI mode: Bits 7:0 are used as the address when doing a register access over the ULPI interface. + 0 + 8 + read-write + + + PHY_WDATA + UTMI+ mode: Reserved. + 8 + 8 + read-write + + + PHY_RDATA + UTMI+ mode: Bits 7:0 contains the value returned by the VStatus signal on Vendor Interface of UTMI+ ULPI mode: Bits 7:0 are used for the read data when reading a value to a ULPI PHY register. + 16 + 8 + read-write + + + PHY_RW + UTMI+ mode: Reserved. + 24 + 1 + read-write + + + PHY_ACCESS + Software writes this bit to one to start a read or write operation. + 25 + 1 + read-write + + + PHY_MODE + This bit indicates if the interface between the controller is UTMI+ or ULPI 0b: UTMI+ 1b: ULPI If the hardware supports both modes, this bit is RW by SW. + 31 + 1 + read-write + + + + + PORTMODE + Controls the port if it is attached to the host block or the device block + 0x50 + 32 + read-write + 0x40000 + 0xD0101 + + + ID0 + Port 0 ID pin value. + 0 + 1 + read-write + + + ID0_EN + Port 0 ID pin pull-up enable. + 8 + 1 + read-write + + + DEV_ENABLE + If this bit is set to one, one of the ports will behave as a USB device. + 16 + 1 + read-write + + + SW_CTRL_PDCOM + This bit indicates if the PHY power-down input is controlled by software or by hardware. + 18 + 1 + read-write + + + SW_PDCOM + This bit is only used when SW_CTRL_PDCOM is set to 1b. + 19 + 1 + read-write + + + + + + + HASHCRYPT + Hash-Crypt peripheral + HASHCRYPT + 0x400A4000 + + 0 + 0xA0 + registers + + + HASHCRYPT + 54 + + + + CTRL + Is control register to enable and operate Hash and Crypto + 0 + 32 + read-write + 0 + 0x1317 + + + Mode + The operational mode to use, or 0 if none. Note that the CONFIG register will indicate if specific modes beyond SHA1 and SHA2-256 are available. + 0 + 3 + read-write + + + DISABLED + Disabled + 0 + + + SHA1 + SHA1 is enabled + 0x1 + + + SHA2_256 + SHA2-256 is enabled + 0x2 + + + SHA2_512 + SHA2-512 is enabled (if available) + 0x3 + + + AES + AES if available (see also CRYPTCFG register for more controls) + 0x4 + + + ICB_AES + ICB-AES if available (see also CRYPTCFG register for more controls) + 0x5 + + + SALSA20 + Salsa20/20 if available (including XSalsa - see also CRYPTCFG register) + 0x6 + + + CHACHA20 + ChaCha20 if available (see also CRYPTCFG register for more controls) + 0x7 + + + + + New_Hash + Written with 1 when starting a new Hash/Crypto. It self clears. Note that the WAITING Status bit will clear for a cycle during the initialization from New=1. + 4 + 1 + read-write + + + START + Starts a new Hash/Crypto and initializes the Digest/Result. + 0x1 + + + + + DMA_I + Written with 1 to use DMA to fill INDATA. If Hash, will request from DMA for 16 words and then will process the Hash. If Cryptographic, it will load as many words as needed, including key if not already loaded. It will then request again. Normal model is that the DMA interrupts the processor when its length expires. Note that if the processor will write the key and optionally IV, it should not enable this until it has done so. Otherwise, the DMA will be expected to load those for the 1st block (when needed). + 8 + 1 + read-write + + + NOT_USED + DMA is not used. Processor writes the necessary words when WAITING is set (interrupts), unless AHB Master is used. + 0 + + + PUSH + DMA will push in the data. + 0x1 + + + + + DMA_O + Written to 1 to use DMA to drain the digest/output. If both DMA_I and DMA_O are set, the DMA has to know to switch direction and the locations. This can be used for crypto uses. + 9 + 1 + read-write + + + NOTUSED + DMA is not used. Processor reads the digest/output in response to DIGEST interrupt. + 0 + + + + + HASHSWPB + If 1, will swap bytes in the word for SHA hashing. The default is byte order (so LSB is 1st byte) but this allows swapping to MSB is 1st such as is shown in SHS spec. For cryptographic swapping, see the CRYPTCFG register. + 12 + 1 + read-write + + + + + STATUS + Indicates status of Hash peripheral. + 0x4 + 32 + read-write + 0 + 0x3F0037 + + + WAITING + If 1, the block is waiting for more data to process. + 0 + 1 + read-only + + + NOT_WAITING + Not waiting for data - may be disabled or may be busy. Note that for cryptographic uses, this is not set if IsLast is set nor will it set until at least 1 word is read of the output. + 0 + + + WAITING + Waiting for data to be written in (16 words) + 0x1 + + + + + DIGEST_aka_OUTDATA + For Hash, if 1 then a DIGEST is ready and waiting and there is no active next block already started. For Cryptographic uses, this will be set for each block processed, indicating OUTDATA (and OUTDATA2 if larger output) contains the next value to read out. This is cleared when any data is written, when New is written, for Cryptographic uses when the last word is read out, or when the block is disabled. + 1 + 1 + read-only + + + NOT_READY + No Digest is ready + 0 + + + READY + Digest is ready. Application may read it or may write more data + 0x1 + + + + + ERROR + If 1, an error occurred. For normal uses, this is due to an attempted overrun: INDATA was written when it was not appropriate. For Master cases, this is an AHB bus error; the COUNT field will indicate which block it was on. + 2 + 1 + read-write + oneToClear + + + NO_ERROR + No error. + 0 + + + ERROR + An error occurred since last cleared (written 1 to clear). + 0x1 + + + + + NEEDKEY + Indicates the block wants the key to be written in (set along with WAITING) + 4 + 1 + read-only + + + NOT_NEED + No Key is needed and writes will not be treated as Key + 0 + + + NEED + Key is needed and INDATA/ALIAS will be accepted as Key. Will also set WAITING. + 0x1 + + + + + NEEDIV + Indicates the block wants an IV/NONE to be written in (set along with WAITING) + 5 + 1 + read-only + + + NOT_NEED + No IV/Nonce is needed, either because written already or because not needed. + 0 + + + NEED + IV/Nonce is needed and INDATA/ALIAS will be accepted as IV/Nonce. Will also set WAITING. + 0x1 + + + + + ICBIDX + If ICB-AES is selected, then reads as the ICB index count based on ICBSTRM (from CRYPTCFG). That is, if 3 bits of ICBSTRM, then this will count from 0 to 7 and then back to 0. On 0, it has to compute the full ICB, quicker when not 0. + 16 + 6 + read-only + + + + + INTENSET + Write 1 to enable interrupts; reads back with which are set. + 0x8 + 32 + read-write + 0 + 0x7 + + + WAITING + Indicates if should interrupt when waiting for data input. + 0 + 1 + read-write + + + NO_INTERRUPT + Will not interrupt when waiting. + 0 + + + INTERRUPT + Will interrupt when waiting + 0x1 + + + + + DIGEST + Indicates if should interrupt when Digest (or Outdata) is ready (completed a hash/crypto or completed a full sequence). + 1 + 1 + read-write + + + NO_INTERRUPT + Will not interrupt when Digest is ready + 0 + + + INTERRUPT + Will interrupt when Digest is ready. Interrupt cleared by writing more data, starting a new Hash, or disabling (done). + 0x1 + + + + + ERROR + Indicates if should interrupt on an ERROR (as defined in Status) + 2 + 1 + read-write + + + NOT_INTERRUPT + Will not interrupt on Error. + 0 + + + INTERRUPT + Will interrupt on Error (until cleared). + 0x1 + + + + + + + INTENCLR + Write 1 to clear interrupts. + 0xC + 32 + read-write + 0 + 0 + + + WAITING + Write 1 to clear mask. + 0 + 1 + read-write + oneToClear + + + DIGEST + Write 1 to clear mask. + 1 + 1 + read-write + oneToClear + + + ERROR + Write 1 to clear mask. + 2 + 1 + read-write + oneToClear + + + + + MEMCTRL + Setup Master to access memory (if available) + 0x10 + 32 + read-write + 0 + 0x7FF0001 + + + MASTER + no description available + 0 + 1 + read-write + + + NOT_USED + Mastering is not used and the normal DMA or Interrupt based model is used with INDATA. + 0 + + + ENABLED + Mastering is enabled and DMA and INDATA should not be used. + 0x1 + + + + + COUNT + Number of 512-bit (128-bit if AES, except 1st block which may include key and IV) blocks to copy starting at MEMADDR. This register will decrement after each block is copied, ending in 0. For Hash, the DIGEST interrupt will occur when it reaches 0. Fro AES, the DIGEST/OUTDATA interrupt will occur on ever block. If a bus error occurs, it will stop with this field set to the block that failed. 0:Done - nothing to process. 1 to 2K: Number of 512-bit (or 128bit) blocks to hash. + 16 + 11 + read-write + + + + + MEMADDR + Address to start memory access from (if available). + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + BASE + Address base to start copying from, word aligned (so bits 1:0 must be 0). This field will advance as it processes the words. If it fails with a bus error, the register will contain the failing word. N:Address in Flash or RAM space; RAM only as mapped in this part. May also be able to address SPIFI. + 0 + 32 + read-write + + + + + INDATA + Input of 16 words at a time to load up buffer. + 0x20 + 32 + write-only + 0 + 0 + + + DATA + Write next word in little-endian form. The hash requires big endian word data, but this block swaps the bytes automatically. That is, SHA assumes the data coming in is treated as bytes (e.g. "abcd") and since the ARM core will treat "abcd" as a word as 0x64636261, the block will swap the word to restore into big endian. + 0 + 32 + write-only + + + + + 7 + 0x4 + ALIAS[%s] + no description available + 0x24 + 32 + write-only + 0 + 0 + + + DATA + Write next word in little-endian form. The hash requires big endian word data, but this block swaps the bytes automatically. That is, SHA assumes the data coming in is treated as bytes (e.g. "abcd") and since the ARM core will treat "abcd" as a word as 0x64636261, the block will swap the word to restore into big endian. + 0 + 32 + write-only + + + + + 8 + 0x4 + OUTDATA0[%s] + no description available + 0x40 + 32 + read-only + 0 + 0xFFFFFFFF + + + DIGEST_OUTPUT + One word of the Digest or output. Note that only 1st 4 are populated for AES and 1st 5 are populated for SHA1. + 0 + 32 + read-only + + + + + 8 + 0x4 + OUTDATA1[%s] + no description available + 0x60 + 32 + read-only + 0 + 0xFFFFFFFF + + + OUTPUT + One word of the 2nd half of the output when used. + 0 + 32 + read-only + + + + + CRYPTCFG + Crypto settings for AES and Salsa and ChaCha + 0x80 + 32 + read-write + 0 + 0xF31FFF + + + MSW1ST_OUT + If 1, OUTDATA0 will be read Most significant word 1st for AES. Else it will be read in normal little endian - Least significant word 1st. Note: only if allowed by configuration. + 0 + 1 + read-write + + + SWAPKEY + If 1, will Swap the key input (bytes in each word). + 1 + 1 + read-write + + + SWAPDAT + If 1, will SWAP the data and IV inputs (bytes in each word). + 2 + 1 + read-write + + + MSW1ST + If 1, load of key, IV, and data is MSW 1st for AES. Else, the words are little endian. Note: only if allowed by configuration. + 3 + 1 + read-write + + + AESMODE + AES Cipher mode to use if plain AES + 4 + 2 + read-write + + + ECB + ECB - used as is + 0 + + + CBC + CBC mode (see details on IV/nonce) + 0x1 + + + CTR + CTR mode (see details on IV/nonce). See also AESCTRPOS. + 0x2 + + + + + AESDECRYPT + AES ECB direction. Only encryption used if CTR mode or manual modes such as CFB + 6 + 1 + read-write + + + AESDECRYPT_0 + Encrypt + 0 + + + DECRYPT + Decrypt + 0x1 + + + + + AESSECRET + Selects the Hidden Secret key vs. User key, if provided. If security levels are used, only the highest level is permitted to select this. + 7 + 1 + read-write + + + NORMAL_WAY + User key provided in normal way + 0 + + + AESSECRET_1 + Secret key provided in hidden way by HW + 0x1 + + + + + AESKEYSZ + Sets the AES key size + 8 + 2 + read-write + + + BITS_128 + 128 bit key + 0 + + + BITS_192 + 192 bit key + 0x1 + + + BITS_256 + 256 bit key + 0x2 + + + + + AESCTRPOS + Halfword position of 16b counter in IV if AESMODE is CTR (position is fixed for Salsa and ChaCha). Only supports 16b counter, so application must control any additional bytes if using more. The 16-bit counter is read from the IV and incremented by 1 each time. Any other use CTR should use ECB directly and do its own XOR and so on. + 10 + 3 + read-write + + + STREAMLAST + Is 1 if last stream block. If not 1, then the engine will compute the next "hash". + 16 + 1 + read-write + + + XSALSA + Is 1 if XSalsa 128b NONCE to be used vs. 64b + 17 + 1 + read-write + + + ICBSZ + This sets the ICB size between 32 and 128 bits, using the following rules. Note that the counter is assumed to occupy the low order bits of the IV. + 20 + 2 + read-write + + + BITS_32 + 32 bits of the IV/ctr are used (from 127:96) + 0 + + + BITS_64 + 64 bits of the IV/ctr are used (from 127:64) + 0x1 + + + BITS_96 + 96 bits of the IV/ctr are used (from 127:32) + 0x2 + + + BIT_128 + All 128 bits of the IV/ctr are used + 0x3 + + + + + ICBSTRM + The size of the ICB-AES stream that can be pushed before needing to compute a new IV/ctr (counter start). This optimizes the performance of the stream of blocks after the 1st. + 22 + 2 + read-write + + + BLOCKS_8 + 8 blocks + 0 + + + BLOCKS_16 + 16 blocks + 0x1 + + + BLOCKS_32 + 32 blocks + 0x2 + + + BLOCKS_64 + 64 blocks + 0x3 + + + + + + + CONFIG + Returns the configuration of this block in this chip - indicates what services are available. + 0x84 + 32 + read-write + 0 + 0 + + + DUAL + 1 if 2 x 512 bit buffers, 0 if only 1 x 512 bit + 0 + 1 + read-only + + + DMA + 1 if DMA is connected + 1 + 1 + read-only + + + AHB + 1 if AHB Master is enabled + 3 + 1 + read-only + + + SHA512 + 1 if SHA2-512 included + 5 + 1 + read-only + + + AES + 1 if AES 128 included + 6 + 1 + read-only + + + AESKEY + 1 if AES 192 and 256 also included + 7 + 1 + read-only + + + SECRET + 1 if AES Secret key available + 8 + 1 + read-only + + + SALSA + 1 if Salsa included + 9 + 1 + read-only + + + CHACHA + 1 if ChaCha included + 10 + 1 + read-only + + + ICB + 1 if ICB over AES included + 11 + 1 + read-only + + + + + LOCK + Lock register allows locking to the current security level or unlocking by the lock holding level. + 0x8C + 32 + read-write + 0 + 0xFFF3 + + + SECLOCK + Write 1 to secure-lock this block (if running in a security state). Write 0 to unlock. If locked already, may only write if at same or higher security level as lock. Reads as: 0 if unlocked, else 1, 2, 3 to indicate security level it is locked at. NOTE: this and ID are the only readable registers if locked and current state is lower than lock level. + 0 + 2 + read-write + + + UNLOCK + Unlocks, so block is open to all. But, AHB Master will only issue non-secure requests. + 0 + + + LOCK + Locks to the current security level. AHB Master will issue requests at this level. + 0x1 + + + + + PATTERN + Must write 0xA75 to change lock state. A75:Pattern needed to change bits 1:0 + 4 + 12 + read-write + + + + + 4 + 0x4 + MASK[%s] + no description available + 0x90 + 32 + write-only + 0 + 0 + + + MASK + A random word. + 0 + 32 + write-only + + + + + + + CASPER + CASPER + CASPER + 0x400A5000 + + 0 + 0x84 + registers + + + + CTRL0 + Contains the offsets of AB and CD in the RAM. + 0 + 32 + read-write + 0 + 0x1FFD0005 + + + ABBPAIR + Which bank-pair the offset ABOFF is within. This must be 0 if only 2-up + 0 + 1 + read-write + + + PAIR0 + Bank-pair 0 (1st) + 0 + + + PAIR1 + Bank-pair 1 (2nd) + 0x1 + + + + + ABOFF + Word or DWord Offset of AB values, with B at [2]=0 and A at [2]=1 as far as the code sees (normally will be an interleaved bank so only sequential to AHB). Word offset only allowed if 32 bit operation. Ideally not in the same RAM as the CD values if 4-up + 2 + 1 + read-write + + + CDBPAIR + Which bank-pair the offset CDOFF is within. This must be 0 if only 2-up + 16 + 1 + read-write + + + PAIR0 + Bank-pair 0 (1st) + 0 + + + PAIR1 + Bank-pair 1 (2nd) + 0x1 + + + + + CDOFF + Word or DWord Offset of CD, with D at [2]=0 and C at [2]=1 as far as the code sees (normally will be an interleaved bank so only sequential to AHB). Word offset only allowed if 32 bit operation. Ideally not in the same RAM as the AB values + 18 + 11 + read-write + + + + + CTRL1 + Contains the opcode mode, iteration count, and result offset (in RAM) and also launches the accelerator. Note: with CP version: CTRL0 and CRTL1 can be written in one go with MCRR. + 0x4 + 32 + read-write + 0 + 0xDFFDFFFF + + + ITER + Iteration counter. Is number_cycles - 1. write 0 means Does one cycle - does not iterate. + 0 + 8 + read-write + + + MODE + Operation mode to perform. write 0 means Accelerator is inactive. write others means accelerator is active. + 8 + 8 + read-write + + + RESBPAIR + Which bank-pair the offset RESOFF is within. This must be 0 if only 2-up. Ideally this is not the same bank as ABBPAIR (when 4-up supported) + 16 + 1 + read-write + + + PAIR0 + Bank-pair 0 (1st) + 0 + + + PAIR1 + Bank-pair 1 (2nd) + 0x1 + + + + + RESOFF + Word or DWord Offset of result. Word offset only allowed if 32 bit operation. Ideally not in the same RAM as the AB and CD values + 18 + 11 + read-write + + + CSKIP + Skip rules on Carry if needed. This operation will be skipped based on Carry value (from previous operation) if not 0: + 30 + 2 + read-write + + + NO_SKIP + No Skip + 0 + + + SKIP_IF_1 + Skip if Carry is 1 + 0x1 + + + SKIP_IF_0 + Skip if Carry is 0 + 0x2 + + + SET_AND_SKIP + Set CTRLOFF to CDOFF and Skip + 0x3 + + + + + + + LOADER + Contains an optional loader to load into CTRL0/1 in steps to perform a set of operations. + 0x8 + 32 + read-write + 0 + 0x1FFD00FF + + + COUNT + Number of control pairs to load 0 relative (so 1 means load 1). write 1 means Does one op - does not iterate, write N means N control pairs to load + 0 + 8 + read-write + + + CTRLBPAIR + Which bank-pair the offset CTRLOFF is within. This must be 0 if only 2-up. Does not matter which bank is used as this is loaded when not performing an operation. + 16 + 1 + read-write + + + PAIR0 + Bank-pair 0 (1st) + 0 + + + PAIR1 + Bank-pair 1 (2nd) + 0x1 + + + + + CTRLOFF + DWord Offset of CTRL pair to load next. + 18 + 11 + read-write + + + + + STATUS + Indicates operational status and would contain the carry bit if used. + 0xC + 32 + read-write + 0 + 0x31 + + + DONE + Indicates if the accelerator has finished an operation. Write 1 to clear, or write CTRL1 to clear. + 0 + 1 + read-write + + + BUSY + Busy or just cleared + 0 + + + COMPLETED + Completed last operation + 0x1 + + + + + CARRY + Last carry value if operation produced a carry bit + 4 + 1 + read-only + + + NO_CARRY + Carry was 0 or no carry + 0 + + + CARRY + Carry was 1 + 0x1 + + + + + BUSY + Indicates if the accelerator is busy performing an operation + 5 + 1 + read-only + + + IDLE + Not busy - is idle + 0 + + + BUSY + Is busy + 0x1 + + + + + + + INTENSET + Sets interrupts + 0x10 + 32 + read-write + 0 + 0x1 + + + DONE + Set if the accelerator should interrupt when done. + 0 + 1 + read-write + + + NO_INTERRUPT + Do not interrupt when done + 0 + + + INTERRUPT + Interrupt when done + 0x1 + + + + + + + INTENCLR + Clears interrupts + 0x14 + 32 + read-write + 0 + 0x1 + + + DONE + Written to clear an interrupt set with INTENSET. + 0 + 1 + read-write + oneToClear + + + IGNORED + If written 0, ignored + 0 + + + NO_INTERRUPT + If written 1, do not Interrupt when done + 0x1 + + + + + + + INTSTAT + Interrupt status bits (mask of INTENSET and STATUS) + 0x18 + 32 + read-write + 0 + 0x1 + + + DONE + If set, interrupt is caused by accelerator being done. + 0 + 1 + read-only + + + NOT_CAUSED + Not caused by accelerator being done + 0 + + + CAUSED + Caused by accelerator being done + 0x1 + + + + + + + AREG + A register + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + REG_VALUE + Register to be fed into Multiplier. Is not normally written or read by application, but is available when accelerator not busy. + 0 + 32 + read-write + + + + + BREG + B register + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + REG_VALUE + Register to be fed into Multiplier. Is not normally written or read by application, but is available when accelerator not busy. + 0 + 32 + read-write + + + + + CREG + C register + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + REG_VALUE + Register to be fed into Multiplier. Is not normally written or read by application, but is available when accelerator not busy. + 0 + 32 + read-write + + + + + DREG + D register + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + REG_VALUE + Register to be fed into Multiplier. Is not normally written or read by application, but is available when accelerator not busy. + 0 + 32 + read-write + + + + + RES0 + Result register 0 + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + REG_VALUE + Register to hold working result (from multiplier, adder/xor, etc). Is not normally written or read by application, but is available when accelerator not busy. + 0 + 32 + read-write + + + + + RES1 + Result register 1 + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + REG_VALUE + Register to hold working result (from multiplier, adder/xor, etc). Is not normally written or read by application, but is available when accelerator not busy. + 0 + 32 + read-write + + + + + RES2 + Result register 2 + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + REG_VALUE + Register to hold working result (from multiplier, adder/xor, etc). Is not normally written or read by application, but is available when accelerator not busy. + 0 + 32 + read-write + + + + + RES3 + Result register 3 + 0x3C + 32 + read-write + 0 + 0xFFFFFFFF + + + REG_VALUE + Register to hold working result (from multiplier, adder/xor, etc). Is not normally written or read by application, but is available when accelerator not busy. + 0 + 32 + read-write + + + + + MASK + Optional mask register + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + MASK + Mask to apply as side channel countermeasure. 0: No mask to be used. N: Mask to XOR onto values + 0 + 32 + read-write + + + + + REMASK + Optional re-mask register + 0x64 + 32 + read-write + 0 + 0xFFFFFFFF + + + MASK + Mask to apply as side channel countermeasure. 0: No mask to be used. N: Mask to XOR onto values + 0 + 32 + read-write + + + + + LOCK + Security lock register + 0x80 + 32 + read-write + 0 + 0x1FFFF + + + LOCK + Reads back with security level locked to, or 0. Writes as 0 to unlock, 1 to lock. + 0 + 1 + read-write + + + UNLOCK + unlock + 0 + + + LOCK + Lock to current security level + 0x1 + + + + + KEY + Must be written as 0x73D to change the register. + 4 + 13 + read-write + + + KWY_VALUE + If set during write, will allow lock or unlock + 0x73D + + + + + + + + + POWERQUAD + Digital Signal Co-Processing companion to a Cortex-M v8M CPU core + POWERQUAD + 0x400A6000 + + 0 + 0x260 + registers + + + + OUTBASE + Base address register for output region + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + outbase + Base address register for the output region + 0 + 32 + read-write + + + + + OUTFORMAT + Output format + 0x4 + 32 + read-write + 0 + 0xFF33 + + + out_formatint + Output Internal format (00: q15; 01:q31; 10:float) + 0 + 2 + read-write + + + out_formatext + Output External format (00: q15; 01:q31; 10:float) + 4 + 2 + read-write + + + out_scaler + Output Scaler value (for scaled 'q31' formats) + 8 + 8 + read-write + + + + + TMPBASE + Base address register for temp region + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + tmpbase + Base address register for the temporary region + 0 + 32 + read-write + + + + + TMPFORMAT + Temp format + 0xC + 32 + read-write + 0 + 0xFF33 + + + tmp_formatint + Temp Internal format (00: q15; 01:q31; 10:float) + 0 + 2 + read-write + + + tmp_formatext + Temp External format (00: q15; 01:q31; 10:float) + 4 + 2 + read-write + + + tmp_scaler + Temp Scaler value (for scaled 'q31' formats) + 8 + 8 + read-write + + + + + INABASE + Base address register for input A region + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + inabase + Base address register for the input A region + 0 + 32 + read-write + + + + + INAFORMAT + Input A format + 0x14 + 32 + read-write + 0 + 0xFF33 + + + ina_formatint + Input A Internal format (00: q15; 01:q31; 10:float) + 0 + 2 + read-write + + + ina_formatext + Input A External format (00: q15; 01:q31; 10:float) + 4 + 2 + read-write + + + ina_scaler + Input A Scaler value (for scaled 'q31' formats) + 8 + 8 + read-write + + + + + INBBASE + Base address register for input B region + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + inbbase + Base address register for the input B region + 0 + 32 + read-write + + + + + INBFORMAT + Input B format + 0x1C + 32 + read-write + 0 + 0xFF33 + + + inb_formatint + Input B Internal format (00: q15; 01:q31; 10:float) + 0 + 2 + read-write + + + inb_formatext + Input B External format (00: q15; 01:q31; 10:float) + 4 + 2 + read-write + + + inb_scaler + Input B Scaler value (for scaled 'q31' formats) + 8 + 8 + read-write + + + + + CONTROL + PowerQuad Control register + 0x100 + 32 + read-write + 0 + 0x8000FFFF + + + decode_opcode + opcode specific to decode_machine + 0 + 4 + read-write + + + decode_machine + 0 : Coprocessor , 1 : matrix , 2 : fft , 3 : fir , 4 : stat , 5 : cordic , 6 -15 : NA + 4 + 4 + read-write + + + inst_busy + Instruction busy signal when high indicates processing is on + 31 + 1 + read-only + + + + + LENGTH + Length register + 0x104 + 32 + read-write + 0 + 0xFFFFFFFF + + + inst_length + Length register. When FIR : fir_xlength = inst_length[15:0] , fir_tlength = inst_len[31:16]. When MTX : rows_a = inst_length[4:0] , cols_a = inst_length[12:8] , cols_b = inst_length[20:16] + 0 + 32 + read-write + + + + + CPPRE + Pre-scale register + 0x108 + 32 + read-write + 0 + 0x3FFFF + + + cppre_in + co-processor scaling of input + 0 + 8 + read-write + + + cppre_out + co-processor fixed point output + 8 + 8 + read-write + + + cppre_sat + 1 : forces sub-32 bit saturation + 16 + 1 + read-write + + + cppre_sat8 + 0 = 8bits, 1 = 16bits + 17 + 1 + read-write + + + + + MISC + Misc register + 0x10C + 32 + read-write + 0 + 0xFFFFFFFF + + + inst_misc + Misc register. For Matrix : Used for scale factor + 0 + 32 + read-write + + + + + CURSORY + Cursory register + 0x110 + 32 + read-write + 0 + 0x1 + + + cursory + 1 : Enable cursory mode + 0 + 1 + read-write + + + + + CORDIC_X + Cordic input X register + 0x180 + 32 + read-write + 0 + 0xFFFFFFFF + + + cordic_x + Cordic input x + 0 + 32 + read-write + + + + + CORDIC_Y + Cordic input Y register + 0x184 + 32 + read-write + 0 + 0xFFFFFFFF + + + cordic_y + Cordic input y + 0 + 32 + read-write + + + + + CORDIC_Z + Cordic input Z register + 0x188 + 32 + read-write + 0 + 0xFFFFFFFF + + + cordic_z + Cordic input z + 0 + 32 + read-write + + + + + ERRSTAT + Read/Write register where error statuses are captured (sticky) + 0x18C + 32 + read-write + 0 + 0x1F + + + OVERFLOW + overflow + 0 + 1 + read-write + + + NAN + nan + 1 + 1 + read-write + + + FIXEDOVERFLOW + fixed_pt_overflow + 2 + 1 + read-write + + + UNDERFLOW + underflow + 3 + 1 + read-write + + + BUSERROR + bus_error + 4 + 1 + read-write + + + + + INTREN + INTERRUPT enable register + 0x190 + 32 + read-write + 0 + 0x7F + + + intr_oflow + 1 : Enable interrupt on Floating point overflow + 0 + 1 + read-write + + + intr_nan + 1 : Enable interrupt on Floating point NaN + 1 + 1 + read-write + + + intr_fixed + 1: Enable interrupt on Fixed point Overflow + 2 + 1 + read-write + + + intr_uflow + 1 : Enable interrupt on Subnormal truncation + 3 + 1 + read-write + + + intr_berr + 1: Enable interrupt on AHBM Buss Error + 4 + 1 + read-write + + + intr_comp + 1: Enable interrupt on instruction completion + 7 + 1 + read-write + + + + + EVENTEN + Event Enable register + 0x194 + 32 + read-write + 0 + 0xFFFFFFFF + + + event_oflow + 1 : Enable event trigger on Floating point overflow + 0 + 1 + read-write + + + event_nan + 1 : Enable event trigger on Floating point NaN + 1 + 1 + read-write + + + event_fixed + 1: Enable event trigger on Fixed point Overflow + 2 + 1 + read-write + + + event_uflow + 1 : Enable event trigger on Subnormal truncation + 3 + 1 + read-write + + + event_berr + 1: Enable event trigger on AHBM Buss Error + 4 + 1 + read-write + + + event_comp + 1: Enable event trigger on instruction completion + 7 + 1 + read-write + + + + + INTRSTAT + INTERRUPT STATUS register + 0x198 + 32 + read-write + 0 + 0x1 + + + intr_stat + Intr status ( 1 bit to indicate interrupt captured, 0 means no new interrupt), write any value will clear this bit + 0 + 1 + read-write + + + + + 16 + 0x4 + gpreg[%s] + General purpose register bank N. + 0x200 + 32 + read-write + 0 + 0x7CF73 + + + gpreg + General purpose register bank + 0 + 32 + read-write + + + + + 8 + 0x4 + compreg[%s] + Compute register bank + 0x240 + 32 + read-write + 0 + 0xFFFFFFFF + + + compreg + Compute register bank + 0 + 32 + read-write + + + + + + + AHB_SECURE_CTRL + AHB secure controller + AHB_SECURE_CTRL + 0x400AC000 + + 0 + 0x1000 + registers + + + + SEC_CTRL_FLASH_ROM_SLAVE_RULE + Security access rules for Flash and ROM slaves. + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FLASH_RULE + Security access rules for the whole FLASH : 0x0000_0000 - 0x0009_FFFF + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + ROM_RULE + Security access rules for the whole ROM : 0x0300_0000 - 0x0301_FFFF + 4 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_FLASH_MEM_RULE0 + Security access rules for FLASH sector 0 to sector 20. Each Flash sector is 32 Kbytes. There are 20 FLASH sectors in total. + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + RULE0 + secure control rule0. it can be set when check_reg's write_lock is '0' + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE1 + secure control rule1. it can be set when check_reg's write_lock is '0' + 4 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE2 + secure control rule2. it can be set when check_reg's write_lock is '0' + 8 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE3 + secure control rule3. it can be set when check_reg's write_lock is '0' + 12 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE4 + secure control rule4. it can be set when check_reg's write_lock is '0' + 16 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE5 + secure control rule5. it can be set when check_reg's write_lock is '0' + 20 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE6 + secure control rule6. it can be set when check_reg's write_lock is '0' + 24 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE7 + secure control rule7. it can be set when check_reg's write_lock is '0' + 28 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_FLASH_MEM_RULE1 + Security access rules for FLASH sector 0 to sector 20. Each Flash sector is 32 Kbytes. There are 20 FLASH sectors in total. + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + RULE0 + secure control rule0. it can be set when check_reg's write_lock is '0' + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE1 + secure control rule1. it can be set when check_reg's write_lock is '0' + 4 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE2 + secure control rule2. it can be set when check_reg's write_lock is '0' + 8 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE3 + secure control rule3. it can be set when check_reg's write_lock is '0' + 12 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE4 + secure control rule4. it can be set when check_reg's write_lock is '0' + 16 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE5 + secure control rule5. it can be set when check_reg's write_lock is '0' + 20 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE6 + secure control rule6. it can be set when check_reg's write_lock is '0' + 24 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE7 + secure control rule7. it can be set when check_reg's write_lock is '0' + 28 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_FLASH_MEM_RULE2 + Security access rules for FLASH sector 0 to sector 20. Each Flash sector is 32 Kbytes. There are 20 FLASH sectors in total. + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + RULE0 + secure control rule0. it can be set when check_reg's write_lock is '0' + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE1 + secure control rule1. it can be set when check_reg's write_lock is '0' + 4 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE2 + secure control rule2. it can be set when check_reg's write_lock is '0' + 8 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE3 + secure control rule3. it can be set when check_reg's write_lock is '0' + 12 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE4 + secure control rule4. it can be set when check_reg's write_lock is '0' + 16 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE5 + secure control rule5. it can be set when check_reg's write_lock is '0' + 20 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE6 + secure control rule6. it can be set when check_reg's write_lock is '0' + 24 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE7 + secure control rule7. it can be set when check_reg's write_lock is '0' + 28 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_ROM_MEM_RULE0 + Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total. + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + RULE0 + secure control rule0. it can be set when check_reg's write_lock is '0' + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE1 + secure control rule1. it can be set when check_reg's write_lock is '0' + 4 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE2 + secure control rule2. it can be set when check_reg's write_lock is '0' + 8 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE3 + secure control rule3. it can be set when check_reg's write_lock is '0' + 12 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE4 + secure control rule4. it can be set when check_reg's write_lock is '0' + 16 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE5 + secure control rule5. it can be set when check_reg's write_lock is '0' + 20 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE6 + secure control rule6. it can be set when check_reg's write_lock is '0' + 24 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE7 + secure control rule7. it can be set when check_reg's write_lock is '0' + 28 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_ROM_MEM_RULE1 + Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total. + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + RULE0 + secure control rule0. it can be set when check_reg's write_lock is '0' + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE1 + secure control rule1. it can be set when check_reg's write_lock is '0' + 4 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE2 + secure control rule2. it can be set when check_reg's write_lock is '0' + 8 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE3 + secure control rule3. it can be set when check_reg's write_lock is '0' + 12 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE4 + secure control rule4. it can be set when check_reg's write_lock is '0' + 16 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE5 + secure control rule5. it can be set when check_reg's write_lock is '0' + 20 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE6 + secure control rule6. it can be set when check_reg's write_lock is '0' + 24 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE7 + secure control rule7. it can be set when check_reg's write_lock is '0' + 28 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_ROM_MEM_RULE2 + Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total. + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + RULE0 + secure control rule0. it can be set when check_reg's write_lock is '0' + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE1 + secure control rule1. it can be set when check_reg's write_lock is '0' + 4 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE2 + secure control rule2. it can be set when check_reg's write_lock is '0' + 8 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE3 + secure control rule3. it can be set when check_reg's write_lock is '0' + 12 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE4 + secure control rule4. it can be set when check_reg's write_lock is '0' + 16 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE5 + secure control rule5. it can be set when check_reg's write_lock is '0' + 20 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE6 + secure control rule6. it can be set when check_reg's write_lock is '0' + 24 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE7 + secure control rule7. it can be set when check_reg's write_lock is '0' + 28 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_ROM_MEM_RULE3 + Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total. + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + RULE0 + secure control rule0. it can be set when check_reg's write_lock is '0' + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE1 + secure control rule1. it can be set when check_reg's write_lock is '0' + 4 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE2 + secure control rule2. it can be set when check_reg's write_lock is '0' + 8 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE3 + secure control rule3. it can be set when check_reg's write_lock is '0' + 12 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE4 + secure control rule4. it can be set when check_reg's write_lock is '0' + 16 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE5 + secure control rule5. it can be set when check_reg's write_lock is '0' + 20 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE6 + secure control rule6. it can be set when check_reg's write_lock is '0' + 24 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE7 + secure control rule7. it can be set when check_reg's write_lock is '0' + 28 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_RAMX_SLAVE_RULE + Security access rules for RAMX slaves. + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + RAMX_RULE + Security access rules for the whole RAMX : 0x0400_0000 - 0x0400_7FFF + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_RAMX_MEM_RULE0 + Security access rules for RAMX slaves. + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + RULE0 + secure control rule0. it can be set when check_reg's write_lock is '0' + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE1 + secure control rule1. it can be set when check_reg's write_lock is '0' + 4 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE2 + secure control rule2. it can be set when check_reg's write_lock is '0' + 8 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE3 + secure control rule3. it can be set when check_reg's write_lock is '0' + 12 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE4 + secure control rule4. it can be set when check_reg's write_lock is '0' + 16 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE5 + secure control rule5. it can be set when check_reg's write_lock is '0' + 20 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE6 + secure control rule6. it can be set when check_reg's write_lock is '0' + 24 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE7 + secure control rule7. it can be set when check_reg's write_lock is '0' + 28 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_RAM0_SLAVE_RULE + Security access rules for RAM0 slaves. + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + RAM0_RULE + Security access rules for the whole RAM0 : 0x2000_0000 - 0x2000_FFFF + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_RAM0_MEM_RULE0 + Security access rules for RAM0 slaves. + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + RULE0 + secure control rule0. it can be set when check_reg's write_lock is '0' + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE1 + secure control rule1. it can be set when check_reg's write_lock is '0' + 4 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE2 + secure control rule2. it can be set when check_reg's write_lock is '0' + 8 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE3 + secure control rule3. it can be set when check_reg's write_lock is '0' + 12 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE4 + secure control rule4. it can be set when check_reg's write_lock is '0' + 16 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE5 + secure control rule5. it can be set when check_reg's write_lock is '0' + 20 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE6 + secure control rule6. it can be set when check_reg's write_lock is '0' + 24 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE7 + secure control rule7. it can be set when check_reg's write_lock is '0' + 28 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_RAM0_MEM_RULE1 + Security access rules for RAM0 slaves. + 0x64 + 32 + read-write + 0 + 0xFFFFFFFF + + + RULE0 + secure control rule0. it can be set when check_reg's write_lock is '0' + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE1 + secure control rule1. it can be set when check_reg's write_lock is '0' + 4 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE2 + secure control rule2. it can be set when check_reg's write_lock is '0' + 8 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE3 + secure control rule3. it can be set when check_reg's write_lock is '0' + 12 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE4 + secure control rule4. it can be set when check_reg's write_lock is '0' + 16 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE5 + secure control rule5. it can be set when check_reg's write_lock is '0' + 20 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE6 + secure control rule6. it can be set when check_reg's write_lock is '0' + 24 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE7 + secure control rule7. it can be set when check_reg's write_lock is '0' + 28 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_RAM1_SLAVE_RULE + Security access rules for RAM1 slaves. + 0x70 + 32 + read-write + 0 + 0xFFFFFFFF + + + RAM0_RULE + Security access rules for the whole RAM1 : 0x2001_0000 - 0x2001_FFFF" name="0 + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_RAM1_MEM_RULE0 + Security access rules for RAM1 slaves. + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + RULE0 + secure control rule0. it can be set when check_reg's write_lock is '0' + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE1 + secure control rule1. it can be set when check_reg's write_lock is '0' + 4 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE2 + secure control rule2. it can be set when check_reg's write_lock is '0' + 8 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE3 + secure control rule3. it can be set when check_reg's write_lock is '0' + 12 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE4 + secure control rule4. it can be set when check_reg's write_lock is '0' + 16 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE5 + secure control rule5. it can be set when check_reg's write_lock is '0' + 20 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE6 + secure control rule6. it can be set when check_reg's write_lock is '0' + 24 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE7 + secure control rule7. it can be set when check_reg's write_lock is '0' + 28 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_RAM1_MEM_RULE1 + Security access rules for RAM1 slaves. + 0x84 + 32 + read-write + 0 + 0xFFFFFFFF + + + RULE0 + secure control rule0. it can be set when check_reg's write_lock is '0' + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE1 + secure control rule1. it can be set when check_reg's write_lock is '0' + 4 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE2 + secure control rule2. it can be set when check_reg's write_lock is '0' + 8 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE3 + secure control rule3. it can be set when check_reg's write_lock is '0' + 12 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE4 + secure control rule4. it can be set when check_reg's write_lock is '0' + 16 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE5 + secure control rule5. it can be set when check_reg's write_lock is '0' + 20 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE6 + secure control rule6. it can be set when check_reg's write_lock is '0' + 24 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE7 + secure control rule7. it can be set when check_reg's write_lock is '0' + 28 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_RAM2_SLAVE_RULE + Security access rules for RAM2 slaves. + 0x90 + 32 + read-write + 0 + 0xFFFFFFFF + + + RAM2_RULE + Security access rules for the whole RAM2 : 0x2002_0000 - 0x2002_FFFF + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_RAM2_MEM_RULE0 + Security access rules for RAM2 slaves. + 0xA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + RULE0 + secure control rule0. it can be set when check_reg's write_lock is '0' + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE1 + secure control rule1. it can be set when check_reg's write_lock is '0' + 4 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE2 + secure control rule2. it can be set when check_reg's write_lock is '0' + 8 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE3 + secure control rule3. it can be set when check_reg's write_lock is '0' + 12 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE4 + secure control rule4. it can be set when check_reg's write_lock is '0' + 16 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE5 + secure control rule5. it can be set when check_reg's write_lock is '0' + 20 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE6 + secure control rule6. it can be set when check_reg's write_lock is '0' + 24 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE7 + secure control rule7. it can be set when check_reg's write_lock is '0' + 28 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_RAM2_MEM_RULE1 + Security access rules for RAM2 slaves. + 0xA4 + 32 + read-write + 0 + 0xFFFFFFFF + + + RULE0 + secure control rule0. it can be set when check_reg's write_lock is '0' + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE1 + secure control rule1. it can be set when check_reg's write_lock is '0' + 4 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE2 + secure control rule2. it can be set when check_reg's write_lock is '0' + 8 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE3 + secure control rule3. it can be set when check_reg's write_lock is '0' + 12 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE4 + secure control rule4. it can be set when check_reg's write_lock is '0' + 16 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE5 + secure control rule5. it can be set when check_reg's write_lock is '0' + 20 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE6 + secure control rule6. it can be set when check_reg's write_lock is '0' + 24 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE7 + secure control rule7. it can be set when check_reg's write_lock is '0' + 28 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_RAM3_SLAVE_RULE + Security access rules for RAM3 slaves. + 0xB0 + 32 + read-write + 0 + 0xFFFFFFFF + + + RAM3_RULE + Security access rules for the whole RAM3: 0x2003_0000 - 0x2003_FFFF + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_RAM3_MEM_RULE0 + Security access rules for RAM3 slaves. + 0xC0 + 32 + read-write + 0 + 0xFFFFFFFF + + + RULE0 + secure control rule0. it can be set when check_reg's write_lock is '0' + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE1 + secure control rule1. it can be set when check_reg's write_lock is '0' + 4 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE2 + secure control rule2. it can be set when check_reg's write_lock is '0' + 8 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE3 + secure control rule3. it can be set when check_reg's write_lock is '0' + 12 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE4 + secure control rule4. it can be set when check_reg's write_lock is '0' + 16 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE5 + secure control rule5. it can be set when check_reg's write_lock is '0' + 20 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE6 + secure control rule6. it can be set when check_reg's write_lock is '0' + 24 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE7 + secure control rule7. it can be set when check_reg's write_lock is '0' + 28 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_RAM3_MEM_RULE1 + Security access rules for RAM3 slaves. + 0xC4 + 32 + read-write + 0 + 0xFFFFFFFF + + + RULE0 + secure control rule0. it can be set when check_reg's write_lock is '0' + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE1 + secure control rule1. it can be set when check_reg's write_lock is '0' + 4 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE2 + secure control rule2. it can be set when check_reg's write_lock is '0' + 8 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE3 + secure control rule3. it can be set when check_reg's write_lock is '0' + 12 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE4 + secure control rule4. it can be set when check_reg's write_lock is '0' + 16 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE5 + secure control rule5. it can be set when check_reg's write_lock is '0' + 20 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE6 + secure control rule6. it can be set when check_reg's write_lock is '0' + 24 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE7 + secure control rule7. it can be set when check_reg's write_lock is '0' + 28 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_RAM4_SLAVE_RULE + Security access rules for RAM4 slaves. + 0xD0 + 32 + read-write + 0 + 0xFFFFFFFF + + + RAM4_RULE + Security access rules for the whole RAM4 : 0x2004_0000 - 0x2004_3FFF + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_RAM4_MEM_RULE0 + Security access rules for RAM4 slaves. + 0xE0 + 32 + read-write + 0 + 0xFFFFFFFF + + + RULE0 + secure control rule0. it can be set when check_reg's write_lock is '0' + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE1 + secure control rule1. it can be set when check_reg's write_lock is '0' + 4 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE2 + secure control rule2. it can be set when check_reg's write_lock is '0' + 8 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RULE3 + secure control rule3. it can be set when check_reg's write_lock is '0' + 12 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_APB_BRIDGE_SLAVE_RULE + Security access rules for both APB Bridges slaves. + 0xF0 + 32 + read-write + 0 + 0xFFFFFFFF + + + APBBRIDGE0_RULE + Security access rules for the whole APB Bridge 0 + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + APBBRIDGE1_RULE + Security access rules for the whole APB Bridge 1 + 4 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_APB_BRIDGE0_MEM_CTRL0 + Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + SYSCON_RULE + System Configuration + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + IOCON_RULE + I/O Configuration + 4 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + GINT0_RULE + GPIO input Interrupt 0 + 8 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + GINT1_RULE + GPIO input Interrupt 1 + 12 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + PINT_RULE + Pin Interrupt and Pattern match + 16 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + SEC_PINT_RULE + Secure Pin Interrupt and Pattern match + 20 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + PMUX_RULE + Peripherals mux + 24 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_APB_BRIDGE0_MEM_CTRL1 + Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. + 0x104 + 32 + read-write + 0 + 0xFFFFFFFF + + + CTIMER0_RULE + Standard counter/Timer 0 + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + CTIMER1_RULE + Standard counter/Timer 1 + 4 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + WWDT_RULE + Windiwed wtachdog Timer + 16 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + MRT_RULE + Multi-rate Timer + 20 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + UTICK_RULE + Micro-Timer + 24 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_APB_BRIDGE0_MEM_CTRL2 + Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. + 0x108 + 32 + read-write + 0 + 0xFFFFFFFF + + + ANACTRL_RULE + Analog Modules controller + 12 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + EFUSE_RULE + eFUSE (One Time Programmable) memory controller + 20 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_APB_BRIDGE0_MEM_CTRL3 + Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. + 0x10C + 32 + write-only + 0 + 0xFFFFFFFF + + + SEC_CTRL_APB_BRIDGE1_MEM_CTRL0 + Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. + 0x110 + 32 + read-write + 0 + 0xFFFFFFFF + + + PMC_RULE + Power Management Controller + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + SYSCTRL_RULE + System Controller + 12 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_APB_BRIDGE1_MEM_CTRL1 + Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. + 0x114 + 32 + read-write + 0 + 0xFFFFFFFF + + + CTIMER2_RULE + Standard counter/Timer 2 + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + CTIMER3_RULE + Standard counter/Timer 3 + 4 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + CTIMER4_RULE + Standard counter/Timer 4 + 8 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RTC_RULE + Real Time Counter + 16 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + OSEVENT_RULE + OS Event Timer + 20 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_APB_BRIDGE1_MEM_CTRL2 + Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. + 0x118 + 32 + read-write + 0 + 0xFFFFFFFF + + + FLASH_CTRL_RULE + Flash Controller + 16 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + PRINCE_RULE + Prince + 20 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_APB_BRIDGE1_MEM_CTRL3 + Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. + 0x11C + 32 + read-write + 0 + 0xFFFFFFFF + + + USBHPHY_RULE + USB High Speed Phy controller + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + RNG_RULE + True Random Number Generator + 8 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + PUFF_RULE + PUF + 12 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + PLU_RULE + Programmable Look-Up logic + 20 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_AHB0_0_SLAVE_RULE + Security access rules for AHB peripherals. + 0x120 + 32 + read-write + 0 + 0xFFFFFFFF + + + DMA0_RULE + DMA Controller + 8 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + FS_USB_DEV_RULE + USB Full-speed device + 16 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + SCT_RULE + SCTimer + 20 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + FLEXCOMM0_RULE + Flexcomm interface 0 + 24 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + FLEXCOMM1_RULE + Flexcomm interface 1 + 28 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_AHB0_1_SLAVE_RULE + Security access rules for AHB peripherals. + 0x124 + 32 + read-write + 0 + 0xFFFFFFFF + + + FLEXCOMM2_RULE + Flexcomm interface 2 + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + FLEXCOMM3_RULE + Flexcomm interface 3 + 4 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + FLEXCOMM4_RULE + Flexcomm interface 4 + 8 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + MAILBOX_RULE + Inter CPU communication Mailbox + 12 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + GPIO0_RULE + High Speed GPIO + 16 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_AHB1_0_SLAVE_RULE + Security access rules for AHB peripherals. + 0x130 + 32 + read-write + 0 + 0xFFFFFFFF + + + USB_HS_DEV_RULE + USB high Speed device registers + 16 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + CRC_RULE + CRC engine + 20 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + FLEXCOMM5_RULE + Flexcomm interface 5 + 24 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + FLEXCOMM6_RULE + Flexcomm interface 6 + 28 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_AHB1_1_SLAVE_RULE + Security access rules for AHB peripherals. + 0x134 + 32 + read-write + 0 + 0xFFFFFFFF + + + FLEXCOMM7_RULE + Flexcomm interface 7 + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + SDIO_RULE + SDMMC card interface + 12 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + DBG_MAILBOX_RULE + Debug mailbox (aka ISP-AP) + 16 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + HS_LSPI_RULE + High Speed SPI + 28 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_AHB2_0_SLAVE_RULE + Security access rules for AHB peripherals. + 0x140 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADC_RULE + ADC + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + USB_FS_HOST_RULE + USB Full Speed Host registers. + 8 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + USB_HS_HOST_RULE + USB High speed host registers + 12 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + HASH_RULE + SHA-2 crypto registers + 16 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + CASPER_RULE + RSA/ECC crypto accelerator + 20 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + PQ_RULE + Power Quad (CM33 processor hardware accelerator) + 24 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + DMA1_RULE + DMA Controller (Secure) + 28 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_AHB2_1_SLAVE_RULE + Security access rules for AHB peripherals. + 0x144 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPIO1_RULE + Secure High Speed GPIO + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + AHB_SEC_CTRL_RULE + AHB Secure Controller + 4 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_AHB2_0_MEM_RULE + Security access rules for AHB_SEC_CTRL_AHB. + 0x150 + 32 + read-write + 0 + 0xFFFFFFFF + + + AHB_SEC_CTRL_SECT_0_RULE + Address space: 0x400A_0000 - 0x400A_CFFF + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + AHB_SEC_CTRL_SECT_1_RULE + Address space: 0x400A_D000 - 0x400A_DFFF + 4 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + AHB_SEC_CTRL_SECT_2_RULE + Address space: 0x400A_E000 - 0x400A_EFFF + 8 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + AHB_SEC_CTRL_SECT_3_RULE + Address space: 0x400A_F000 - 0x400A_FFFF + 12 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_USB_HS_SLAVE_RULE + Security access rules for USB High speed RAM slaves. + 0x160 + 32 + read-write + 0 + 0xFFFFFFFF + + + RAM_USB_HS_RULE + Security access rules for the whole USB High Speed RAM : 0x4010_0000 - 0x4010_3FFF + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + SEC_CTRL_USB_HS_MEM_RULE + Security access rules for RAM_USB_HS. + 0x170 + 32 + read-write + 0 + 0xFFFFFFFF + + + SRAM_SECT_0_RULE + Address space: 0x4010_0000 - 0x4010_0FFF + 0 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + SRAM_SECT_1_RULE + Address space: 0x4010_1000 - 0x4010_1FFF + 4 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + SRAM_SECT_2_RULE + Address space: 0x4010_2000 - 0x4010_2FFF + 8 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + SRAM_SECT_3_RULE + Address space: 0x4010_3000 - 0x4010_3FFF + 12 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + + + 12 + 0x4 + sec_vio_addr[%s] + most recent security violation address for AHB layer n + 0xE00 + 32 + read-only + 0 + 0xFFFFFFFF + + + SEC_VIO_ADDR + security violation address for AHB layer + 0 + 32 + read-only + + + + + 12 + 0x4 + sec_vio_misc_info[%s] + most recent security violation miscellaneous information for AHB layer n + 0xE80 + 32 + read-only + 0 + 0xFF3 + + + SEC_VIO_INFO_WRITE + security violation access read/write indicator. + 0 + 1 + read-only + + + READ + Read access. + 0 + + + WRITE + Write access. + 0x1 + + + + + SEC_VIO_INFO_DATA_ACCESS + security violation access data/code indicator. + 1 + 1 + read-only + + + CODE + Code access. + 0 + + + DATA + Data access. + 0x1 + + + + + SEC_VIO_INFO_MASTER_SEC_LEVEL + bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and privilege level + 4 + 4 + read-only + + + SEC_VIO_INFO_MASTER + security violation master number + 8 + 4 + read-only + + + VALUE_0 + CPU0 Code. + 0 + + + VALUE_1 + CPU0 System. + 0x1 + + + VALUE_2 + CPU1 Data. + 0x2 + + + VALUE_3 + CPU1 System. + 0x3 + + + VALUE_4 + USB-HS Device. + 0x4 + + + VALUE_5 + SDMA0. + 0x5 + + + VALUE_8 + SDIO. + 0x8 + + + VALUE_9 + PowerQuad. + 0x9 + + + VALUE_10 + HASH. + 0xA + + + VALUE_11 + USB-FS Host. + 0xB + + + VALUE_12 + SDMA1. + 0xC + + + + + + + SEC_VIO_INFO_VALID + security violation address/information registers valid flags + 0xF00 + 32 + read-write + 0 + 0x3FFFF + + + VIO_INFO_VALID0 + violation information valid flag for AHB layer 0. Write 1 to clear. + 0 + 1 + read-write + + + NOT_VALID + Not valid. + 0 + + + VALID + Valid (violation occurred). + 0x1 + + + + + VIO_INFO_VALID1 + violation information valid flag for AHB layer 1. Write 1 to clear. + 1 + 1 + read-write + + + NOT_VALID + Not valid. + 0 + + + VALID + Valid (violation occurred). + 0x1 + + + + + VIO_INFO_VALID2 + violation information valid flag for AHB layer 2. Write 1 to clear. + 2 + 1 + read-write + + + NOT_VALID + Not valid. + 0 + + + VALID + Valid (violation occurred). + 0x1 + + + + + VIO_INFO_VALID3 + violation information valid flag for AHB layer 3. Write 1 to clear. + 3 + 1 + read-write + + + NOT_VALID + Not valid. + 0 + + + VALID + Valid (violation occurred). + 0x1 + + + + + VIO_INFO_VALID4 + violation information valid flag for AHB layer 4. Write 1 to clear. + 4 + 1 + read-write + + + NOT_VALID + Not valid. + 0 + + + VALID + Valid (violation occurred). + 0x1 + + + + + VIO_INFO_VALID5 + violation information valid flag for AHB layer 5. Write 1 to clear. + 5 + 1 + read-write + + + NOT_VALID + Not valid. + 0 + + + VALID + Valid (violation occurred). + 0x1 + + + + + VIO_INFO_VALID6 + violation information valid flag for AHB layer 6. Write 1 to clear. + 6 + 1 + read-write + + + NOT_VALID + Not valid. + 0 + + + VALID + Valid (violation occurred). + 0x1 + + + + + VIO_INFO_VALID7 + violation information valid flag for AHB layer 7. Write 1 to clear. + 7 + 1 + read-write + + + NOT_VALID + Not valid. + 0 + + + VALID + Valid (violation occurred). + 0x1 + + + + + VIO_INFO_VALID8 + violation information valid flag for AHB layer 8. Write 1 to clear. + 8 + 1 + read-write + + + NOT_VALID + Not valid. + 0 + + + VALID + Valid (violation occurred). + 0x1 + + + + + VIO_INFO_VALID9 + violation information valid flag for AHB layer 9. Write 1 to clear. + 9 + 1 + read-write + + + NOT_VALID + Not valid. + 0 + + + VALID + Valid (violation occurred). + 0x1 + + + + + VIO_INFO_VALID10 + violation information valid flag for AHB layer 10. Write 1 to clear. + 10 + 1 + read-write + + + NOT_VALID + Not valid. + 0 + + + VALID + Valid (violation occurred). + 0x1 + + + + + VIO_INFO_VALID11 + violation information valid flag for AHB layer 11. Write 1 to clear. + 11 + 1 + read-write + + + NOT_VALID + Not valid. + 0 + + + VALID + Valid (violation occurred). + 0x1 + + + + + + + SEC_GPIO_MASK0 + Secure GPIO mask for port 0 pins. + 0xF80 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + PIO0_PIN0_SEC_MASK + Secure mask for pin P0_0 + 0 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN1_SEC_MASK + Secure mask for pin P0_1 + 1 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN2_SEC_MASK + Secure mask for pin P0_2 + 2 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN3_SEC_MASK + Secure mask for pin P0_3 + 3 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN4_SEC_MASK + Secure mask for pin P0_4 + 4 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN5_SEC_MASK + Secure mask for pin P0_5 + 5 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN6_SEC_MASK + Secure mask for pin P0_6 + 6 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN7_SEC_MASK + Secure mask for pin P0_7 + 7 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN8_SEC_MASK + Secure mask for pin P0_8 + 8 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN9_SEC_MASK + Secure mask for pin P0_9 + 9 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN10_SEC_MASK + Secure mask for pin P0_10 + 10 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN11_SEC_MASK + Secure mask for pin P0_11 + 11 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN12_SEC_MASK + Secure mask for pin P0_12 + 12 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN13_SEC_MASK + Secure mask for pin P0_13 + 13 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN14_SEC_MASK + Secure mask for pin P0_14 + 14 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN15_SEC_MASK + Secure mask for pin P0_15 + 15 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN16_SEC_MASK + Secure mask for pin P0_16 + 16 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN17_SEC_MASK + Secure mask for pin P0_17 + 17 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN18_SEC_MASK + Secure mask for pin P0_18 + 18 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN19_SEC_MASK + Secure mask for pin P0_19 + 19 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN20_SEC_MASK + Secure mask for pin P0_20 + 20 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN21_SEC_MASK + Secure mask for pin P0_21 + 21 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN22_SEC_MASK + Secure mask for pin P0_22 + 22 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN23_SEC_MASK + Secure mask for pin P0_23 + 23 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN24_SEC_MASK + Secure mask for pin P0_24 + 24 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN25_SEC_MASK + Secure mask for pin P0_25 + 25 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN26_SEC_MASK + Secure mask for pin P0_26 + 26 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN27_SEC_MASK + Secure mask for pin P0_27 + 27 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN28_SEC_MASK + Secure mask for pin P0_28 + 28 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN29_SEC_MASK + Secure mask for pin P0_29 + 29 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN30_SEC_MASK + Secure mask for pin P0_30 + 30 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO0_PIN31_SEC_MASK + Secure mask for pin P0_31 + 31 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + + + SEC_GPIO_MASK1 + Secure GPIO mask for port 1 pins. + 0xF84 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + PIO1_PIN0_SEC_MASK + Secure mask for pin P1_0 + 0 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN1_SEC_MASK + Secure mask for pin P1_1 + 1 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN2_SEC_MASK + Secure mask for pin P1_2 + 2 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN3_SEC_MASK + Secure mask for pin P1_3 + 3 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN4_SEC_MASK + Secure mask for pin P1_4 + 4 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN5_SEC_MASK + Secure mask for pin P1_5 + 5 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN6_SEC_MASK + Secure mask for pin P1_6 + 6 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN7_SEC_MASK + Secure mask for pin P1_7 + 7 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN8_SEC_MASK + Secure mask for pin P1_8 + 8 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN9_SEC_MASK + Secure mask for pin P1_9 + 9 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN10_SEC_MASK + Secure mask for pin P1_10 + 10 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN11_SEC_MASK + Secure mask for pin P1_11 + 11 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN12_SEC_MASK + Secure mask for pin P1_12 + 12 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN13_SEC_MASK + Secure mask for pin P1_13 + 13 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN14_SEC_MASK + Secure mask for pin P1_14 + 14 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN15_SEC_MASK + Secure mask for pin P1_15 + 15 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN16_SEC_MASK + Secure mask for pin P1_16 + 16 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN17_SEC_MASK + Secure mask for pin P1_17 + 17 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN18_SEC_MASK + Secure mask for pin P1_18 + 18 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN19_SEC_MASK + Secure mask for pin P1_19 + 19 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN20_SEC_MASK + Secure mask for pin P1_20 + 20 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN21_SEC_MASK + Secure mask for pin P1_21 + 21 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN22_SEC_MASK + Secure mask for pin P1_22 + 22 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN23_SEC_MASK + Secure mask for pin P1_23 + 23 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN24_SEC_MASK + Secure mask for pin P1_24 + 24 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN25_SEC_MASK + Secure mask for pin P1_25 + 25 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN26_SEC_MASK + Secure mask for pin P1_26 + 26 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN27_SEC_MASK + Secure mask for pin P1_27 + 27 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN28_SEC_MASK + Secure mask for pin P1_28 + 28 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN29_SEC_MASK + Secure mask for pin P1_29 + 29 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN30_SEC_MASK + Secure mask for pin P1_30 + 30 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + PIO1_PIN31_SEC_MASK + Secure mask for pin P1_31 + 31 + 1 + read-write + + + BLOCKED + Pin state is blocked to non-secure world. + 0 + + + READABLE + Pin state is readable by non-secure world. + 0x1 + + + + + + + SEC_CPU_INT_MASK0 + Secure Interrupt mask for CPU1 + 0xF90 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + SYS_IRQ + Watchdog Timer, Brown Out Detectors and Flash Controller interrupts + 0 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + SDMA0_IRQ + System DMA 0 (non-secure) interrupt. + 1 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + GPIO_GLOBALINT0_IRQ + GPIO Group 0 interrupt. + 2 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + GPIO_GLOBALINT1_IRQ + GPIO Group 1 interrupt. + 3 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + GPIO_INT0_IRQ0 + Pin interrupt 0 or pattern match engine slice 0 interrupt. + 4 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + GPIO_INT0_IRQ1 + Pin interrupt 1 or pattern match engine slice 1 interrupt. + 5 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + GPIO_INT0_IRQ2 + Pin interrupt 2 or pattern match engine slice 2 interrupt. + 6 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + GPIO_INT0_IRQ3 + Pin interrupt 3 or pattern match engine slice 3 interrupt. + 7 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + UTICK_IRQ + Micro Tick Timer interrupt. + 8 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + MRT_IRQ + Multi-Rate Timer interrupt. + 9 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + CTIMER0_IRQ + Standard counter/timer 0 interrupt. + 10 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + CTIMER1_IRQ + Standard counter/timer 1 interrupt. + 11 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + SCT_IRQ + SCTimer/PWM interrupt. + 12 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + CTIMER3_IRQ + Standard counter/timer 3 interrupt. + 13 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + FLEXCOMM0_IRQ + Flexcomm 0 interrupt (USART, SPI, I2C, I2S). + 14 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + FLEXCOMM1_IRQ + Flexcomm 1 interrupt (USART, SPI, I2C, I2S). + 15 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + FLEXCOMM2_IRQ + Flexcomm 2 interrupt (USART, SPI, I2C, I2S). + 16 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + FLEXCOMM3_IRQ + Flexcomm 3 interrupt (USART, SPI, I2C, I2S). + 17 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + FLEXCOMM4_IRQ + Flexcomm 4 interrupt (USART, SPI, I2C, I2S). + 18 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + FLEXCOMM5_IRQ + Flexcomm 5 interrupt (USART, SPI, I2C, I2S). + 19 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + FLEXCOMM6_IRQ + Flexcomm 6 interrupt (USART, SPI, I2C, I2S). + 20 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + FLEXCOMM7_IRQ + Flexcomm 7 interrupt (USART, SPI, I2C, I2S). + 21 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + ADC_IRQ + General Purpose ADC interrupt. + 22 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + RESERVED0 + Reserved. Read value is undefined, only zero should be written. + 23 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + ACMP_CAPT0_IRQ + Analog Comparator interrupt. + 24 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + RESERVED1 + Reserved. Read value is undefined, only zero should be written. + 25 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + RESERVED2 + Reserved. Read value is undefined, only zero should be written. + 26 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + USB0_NEEDCLK + USB Full Speed Controller Clock request interrupt. + 27 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + USB0_IRQ + USB High Speed Controller interrupt. + 28 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + RTC_IRQ + RTC_LITE0_ALARM_IRQ, RTC_LITE0_WAKEUP_IRQ + 29 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + RESERVED3 + Reserved. Read value is undefined, only zero should be written. + 30 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + MAILBOX_IRQ + Mailbox interrupt. + 31 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + + + SEC_CPU_INT_MASK1 + Secure Interrupt mask for CPU1 + 0xF94 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + GPIO_INT0_IRQ4 + Pin interrupt 4 or pattern match engine slice 4 interrupt. + 0 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + GPIO_INT0_IRQ5 + Pin interrupt 5 or pattern match engine slice 5 interrupt. + 1 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + GPIO_INT0_IRQ6 + Pin interrupt 6 or pattern match engine slice 6 interrupt. + 2 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + GPIO_INT0_IRQ7 + Pin interrupt 7 or pattern match engine slice 7 interrupt. + 3 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + CTIMER2_IRQ + Standard counter/timer 2 interrupt. + 4 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + CTIMER4_IRQ + Standard counter/timer 4 interrupt. + 5 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + OS_EVENT_TIMER_IRQ + OS Event Timer and OS Event Timer Wakeup interrupts + 6 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + RESERVED0 + Reserved. Read value is undefined, only zero should be written. + 7 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + RESERVED1 + Reserved. Read value is undefined, only zero should be written. + 8 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + RESERVED2 + Reserved. Read value is undefined, only zero should be written. + 9 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + SDIO_IRQ + SDIO Controller interrupt. + 10 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + RESERVED3 + Reserved. Read value is undefined, only zero should be written. + 11 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + RESERVED4 + Reserved. Read value is undefined, only zero should be written. + 12 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + RESERVED5 + Reserved. Read value is undefined, only zero should be written. + 13 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + USB1_UTMI_IRQ + USB High Speed Controller UTMI interrupt. + 14 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + USB1_IRQ + USB High Speed Controller interrupt. + 15 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + USB1_NEEDCLK + USB High Speed Controller Clock request interrupt. + 16 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + SEC_HYPERVISOR_CALL_IRQ + Secure fault Hyper Visor call interrupt. + 17 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + SEC_GPIO_INT0_IRQ0 + Secure Pin interrupt 0 or pattern match engine slice 0 interrupt. + 18 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + SEC_GPIO_INT0_IRQ1 + Secure Pin interrupt 1 or pattern match engine slice 1 interrupt. + 19 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + PLU_IRQ + Programmable Look-Up Controller interrupt. + 20 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + SEC_VIO_IRQ + Security Violation interrupt. + 21 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + SHA_IRQ + HASH-AES interrupt. + 22 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + CASPER_IRQ + CASPER interrupt. + 23 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + QDDKEY_IRQ + PUF interrupt. + 24 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + PQ_IRQ + Power Quad interrupt. + 25 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + SDMA1_IRQ + System DMA 1 (Secure) interrupt + 26 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + LSPI_HS_IRQ + High Speed SPI interrupt + 27 + 1 + read-write + + + INVISIBLE + no description available + 0 + + + VISIBLE + no description available + 0x1 + + + + + + + SEC_MASK_LOCK + Security General Purpose register access control. + 0xFBC + 32 + read-write + 0xAAA + 0xFFF + + + SEC_GPIO_MASK0_LOCK + SEC_GPIO_MASK0 register write-lock. + 0 + 2 + read-write + + + BLOCKED + Restricted mode. + 0x1 + + + WRITABLE + Writable. + 0x2 + + + + + SEC_GPIO_MASK1_LOCK + SEC_GPIO_MASK1 register write-lock. + 2 + 2 + read-write + + + BLOCKED + Restricted mode. + 0x1 + + + WRITABLE + Writable. + 0x2 + + + + + SEC_CPU1_INT_MASK0_LOCK + SEC_CPU_INT_MASK0 register write-lock. + 8 + 2 + read-write + + + BLOCKED + Restricted mode. + 0x1 + + + WRITABLE + Writable. + 0x2 + + + + + SEC_CPU1_INT_MASK1_LOCK + SEC_CPU_INT_MASK1 register write-lock. + 10 + 2 + read-write + + + BLOCKED + Restricted mode. + 0x1 + + + WRITABLE + Writable. + 0x2 + + + + + + + MASTER_SEC_LEVEL + master secure level register + 0xFD0 + 32 + read-write + 0x80000000 + 0xFFFFFFFF + + + MCM33C + Micro-CM33 (CPU1) Code bus. + 4 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + MCM33S + Micro-CM33 (CPU1) System bus. + 6 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + USBFSD + USB Full Speed Device. + 8 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + SDMA0 + System DMA 0. + 10 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + SDIO + SDIO. + 16 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + PQ + Power Quad. + 18 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + HASH + Hash. + 20 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + USBFSH + USB Full speed Host. + 22 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + SDMA1 + System DMA 1 security level. + 24 + 2 + read-write + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x1 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x2 + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0x3 + + + + + MASTER_SEC_LEVEL_LOCK + MASTER_SEC_LEVEL write-lock. + 30 + 2 + read-write + + + BLOCKED + Restricted mode. + 0x1 + + + WRITABLE + Writable. + 0x2 + + + + + + + MASTER_SEC_ANTI_POL_REG + master secure level anti-pole register + 0xFD4 + 32 + read-write + 0xBFFFFFFF + 0xFFFFFFFF + + + MCM33C + Micro-CM33 (CPU1) Code bus. Must be equal to NOT(MASTER_SEC_LEVEL.MCM33C) + 4 + 2 + read-write + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x1 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x2 + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0x3 + + + + + MCM33S + Micro-CM33 (CPU1) System bus. Must be equal to NOT(MASTER_SEC_LEVEL.MCM33S) + 6 + 2 + read-write + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x1 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x2 + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0x3 + + + + + USBFSD + USB Full Speed Device. Must be equal to NOT(MASTER_SEC_LEVEL.USBFSD) + 8 + 2 + read-write + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x1 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x2 + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0x3 + + + + + SDMA0 + System DMA 0. Must be equal to NOT(MASTER_SEC_LEVEL.SDMA0) + 10 + 2 + read-write + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x1 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x2 + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0x3 + + + + + SDIO + SDIO. Must be equal to NOT(MASTER_SEC_LEVEL.SDIO) + 16 + 2 + read-write + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x1 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x2 + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0x3 + + + + + PQ + Power Quad. Must be equal to NOT(MASTER_SEC_LEVEL.PQ) + 18 + 2 + read-write + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x1 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x2 + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0x3 + + + + + HASH + Hash. Must be equal to NOT(MASTER_SEC_LEVEL.HASH) + 20 + 2 + read-write + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x1 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x2 + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0x3 + + + + + USBFSH + USB Full speed Host. Must be equal to NOT(MASTER_SEC_LEVEL.USBFSH) + 22 + 2 + read-write + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x1 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x2 + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0x3 + + + + + SDMA1 + System DMA 1 security level. Must be equal to NOT(MASTER_SEC_LEVEL.SDMA1) + 24 + 2 + read-write + + + ENUM_S_P + Secure and Priviledge user access allowed. + 0 + + + ENUM_S_NP + Secure and Non-priviledge user access allowed. + 0x1 + + + ENUM_NS_P + Non-secure and Privilege access allowed. + 0x2 + + + ENUM_NS_NP + Non-secure and Non-priviledge user access allowed. + 0x3 + + + + + MASTER_SEC_LEVEL_ANTIPOL_LOCK + MASTER_SEC_ANTI_POL_REG register write-lock. + 30 + 2 + read-write + + + BLOCKED + Restricted mode. + 0x1 + + + WRITABLE + Writable. + 0x2 + + + + + + + CM33_LOCK_REG + Miscalleneous control signals for in CM33 (CPU0) + 0xFEC + 32 + read-write + 0x800002AA + 0xC00003FF + + + LOCK_NS_VTOR + CM33 (CPU0) VTOR_NS register write-lock. + 0 + 2 + read-write + + + BLOCKED + Restricted mode. + 0x1 + + + WRITABLE + Writable. + 0x2 + + + + + LOCK_NS_MPU + CM33 (CPU0) non-secure MPU register write-lock. + 2 + 2 + read-write + + + BLOCKED + Restricted mode. + 0x1 + + + WRITABLE + Writable. + 0x2 + + + + + LOCK_S_VTAIRCR + CM33 (CPU0) VTOR_S, AIRCR.PRIS, IRCR.BFHFNMINS registers write-lock. + 4 + 2 + read-write + + + BLOCKED + Restricted mode. + 0x1 + + + WRITABLE + Writable. + 0x2 + + + + + LOCK_S_MPU + CM33 (CPU0) Secure MPU registers write-lock. + 6 + 2 + read-write + + + BLOCKED + Restricted mode. + 0x1 + + + WRITABLE + Writable. + 0x2 + + + + + LOCK_SAU + CM33 (CPU0) SAU registers write-lock. + 8 + 2 + read-write + + + BLOCKED + Restricted mode. + 0x1 + + + WRITABLE + Writable. + 0x2 + + + + + CM33_LOCK_REG_LOCK + CM33_LOCK_REG write-lock. + 30 + 2 + read-write + + + BLOCKED + Restricted mode. + 0x1 + + + WRITABLE + Writable. + 0x2 + + + + + + + MCM33_LOCK_REG + Miscalleneous control signals for in micro-CM33 (CPU1) + 0xFF0 + 32 + read-write + 0x8000000A + 0xC000000F + + + LOCK_NS_VTOR + micro-CM33 (CPU1) VTOR_NS register write-lock. + 0 + 2 + read-write + + + BLOCKED + Restricted mode. + 0x1 + + + WRITABLE + Writable. + 0x2 + + + + + LOCK_NS_MPU + micro-CM33 (CPU1) non-secure MPU register write-lock. + 2 + 2 + read-write + + + BLOCKED + Restricted mode. + 0x1 + + + WRITABLE + Writable. + 0x2 + + + + + MCM33_LOCK_REG_LOCK + MCM33_LOCK_REG write-lock. + 30 + 2 + read-write + + + BLOCKED + Restricted mode. + 0x1 + + + WRITABLE + Writable. + 0x2 + + + + + + + MISC_CTRL_DP_REG + secure control duplicate register + 0xFF8 + 32 + read-write + 0xAAAA + 0xFFFF + + + WRITE_LOCK + write lock. + 0 + 2 + read-write + + + RESTRICTED + Restricted mode. + 0x1 + + + ACCESSIBLE + Secure control registers can be written. + 0x2 + + + + + ENABLE_SECURE_CHECKING + AHB bus matrix enable secure check. + 2 + 2 + read-write + + + ENABLE + Restricted mode. + 0x1 + + + DISABLE + Disable check. + 0x2 + + + + + ENABLE_S_PRIV_CHECK + AHB bus matrix enable secure privilege check. + 4 + 2 + read-write + + + ENABLE + Restricted mode. + 0x1 + + + DISABLE + Disable check. + 0x2 + + + + + ENABLE_NS_PRIV_CHECK + AHB bus matrix enable non-secure privilege check. + 6 + 2 + read-write + + + ENABLE + Restricted mode. + 0x1 + + + DISABLE + Disable check. + 0x2 + + + + + DISABLE_VIOLATION_ABORT + Disable secure violation abort. + 8 + 2 + read-write + + + DISABLE + Disable abort fort secure checker. + 0x1 + + + ENABLE + Enable abort fort secure checker. + 0x2 + + + + + DISABLE_SIMPLE_MASTER_STRICT_MODE + Disable simple master strict mode. + 10 + 2 + read-write + + + TIER_MODE + Simple master in tier mode. + 0x1 + + + STRICT_MODE + Simple master in strict mode. + 0x2 + + + + + DISABLE_SMART_MASTER_STRICT_MODE + Disable smart master strict mode. + 12 + 2 + read-write + + + TIER_MODE + Smart master in tier mode. + 0x1 + + + STRICT_MODE + Smart master in strict mode. + 0x2 + + + + + IDAU_ALL_NS + Disable IDAU. + 14 + 2 + read-write + + + DISABLE + IDAU is disable. + 0x1 + + + ENABLE + IDAU is enabled. + 0x2 + + + + + + + MISC_CTRL_REG + secure control register + 0xFFC + 32 + read-write + 0xAAAA + 0xFFFF + + + WRITE_LOCK + write lock. + 0 + 2 + read-write + + + RESTRICTED + Restricted mode. + 0x1 + + + ACCESSIBLE + Secure control registers can be written. + 0x2 + + + + + ENABLE_SECURE_CHECKING + AHB bus matrix enable secure check. + 2 + 2 + read-write + + + ENABLE + Restricted mode. + 0x1 + + + DISABLE + Disable check. + 0x2 + + + + + ENABLE_S_PRIV_CHECK + AHB bus matrix enable secure privilege check. + 4 + 2 + read-write + + + ENABLE + Restricted mode. + 0x1 + + + DISABLE + Disable check. + 0x2 + + + + + ENABLE_NS_PRIV_CHECK + AHB bus matrix enable non-secure privilege check. + 6 + 2 + read-write + + + ENABLE + Restricted mode. + 0x1 + + + DISABLE + Disable check. + 0x2 + + + + + DISABLE_VIOLATION_ABORT + Disable secure violation abort. + 8 + 2 + read-write + + + DISABLE + Disable abort fort secure checker. + 0x1 + + + ENABLE + Enable abort fort secure checker. + 0x2 + + + + + DISABLE_SIMPLE_MASTER_STRICT_MODE + Disable simple master strict mode. + 10 + 2 + read-write + + + TIER_MODE + Simple master in tier mode. + 0x1 + + + STRICT_MODE + Simple master in strict mode. + 0x2 + + + + + DISABLE_SMART_MASTER_STRICT_MODE + Disable smart master strict mode. + 12 + 2 + read-write + + + TIER_MODE + Smart master in tier mode. + 0x1 + + + STRICT_MODE + Smart master in strict mode. + 0x2 + + + + + IDAU_ALL_NS + Disable IDAU. + 14 + 2 + read-write + + + DISABLE + IDAU is disable. + 0x1 + + + ENABLE + IDAU is enabled. + 0x2 + + + + + + + + + SCnSCB + no description available + SCNSCB + 0xE000E000 + + 0 + 0x10 + registers + + + + CPPWR + Coprocessor Power Control Register + 0xC + 32 + read-write + 0 + 0 + + + SU0 + State UNKNOWN 0. + 0 + 1 + read-write + + + UNKNOWN_NOT_PERMITTED + The coprocessor state is not permitted to become UNKNOWN. + 0 + + + UNKNOWN_PERMITTED + The coprocessor state is permitted to become UNKNOWN. + 0x1 + + + + + SUS0 + State UNKNOWN Secure only 0. + 1 + 1 + read-write + + + SECURE_AND_NON_SECURE + The SU0 field is accessible from both Security states. + 0 + + + SECURE_ONLY + The SU0 field is only accessible from the Secure state. + 0x1 + + + + + SU1 + State UNKNOWN 1. + 2 + 1 + read-write + + + UNKNOWN_NOT_PERMITTED + The coprocessor state is not permitted to become UNKNOWN. + 0 + + + UNKNOWN_PERMITTED + The coprocessor state is permitted to become UNKNOWN. + 0x1 + + + + + SUS1 + State UNKNOWN Secure only 1. + 3 + 1 + read-write + + + SECURE_AND_NON_SECURE + The SU7 field is accessible from both Security states. + 0 + + + SECURE_ONLY + The SU7 field is only accessible from the Secure state. + 0x1 + + + + + SU2 + State UNKNOWN 2. + 4 + 1 + read-write + + + UNKNOWN_NOT_PERMITTED + The coprocessor state is not permitted to become UNKNOWN. + 0 + + + UNKNOWN_PERMITTED + The coprocessor state is permitted to become UNKNOWN. + 0x1 + + + + + SUS2 + State UNKNOWN Secure only 2. + 5 + 1 + read-write + + + SECURE_AND_NON_SECURE + The SU2 field is accessible from both Security states. + 0 + + + SECURE_ONLY + The SU2 field is only accessible from the Secure state. + 0x1 + + + + + SU3 + State UNKNOWN 3. + 6 + 1 + read-write + + + UNKNOWN_NOT_PERMITTED + The coprocessor state is not permitted to become UNKNOWN. + 0 + + + UNKNOWN_PERMITTED + The coprocessor state is permitted to become UNKNOWN. + 0x1 + + + + + SUS3 + State UNKNOWN Secure only 3. + 7 + 1 + read-write + + + SECURE_AND_NON_SECURE + The SU3 field is accessible from both Security states. + 0 + + + SECURE_ONLY + The SU3 field is only accessible from the Secure state. + 0x1 + + + + + SU4 + State UNKNOWN 4. + 8 + 1 + read-write + + + UNKNOWN_NOT_PERMITTED + The coprocessor state is not permitted to become UNKNOWN. + 0 + + + UNKNOWN_PERMITTED + The coprocessor state is permitted to become UNKNOWN. + 0x1 + + + + + SUS4 + State UNKNOWN Secure only 4. + 9 + 1 + read-write + + + SECURE_AND_NON_SECURE + The SU4 field is accessible from both Security states. + 0 + + + SECURE_ONLY + The SU4 field is only accessible from the Secure state. + 0x1 + + + + + SU5 + State UNKNOWN 5. + 10 + 1 + read-write + + + UNKNOWN_NOT_PERMITTED + The coprocessor state is not permitted to become UNKNOWN. + 0 + + + UNKNOWN_PERMITTED + The coprocessor state is permitted to become UNKNOWN. + 0x1 + + + + + SUS5 + State UNKNOWN Secure only 5. + 11 + 1 + read-write + + + SECURE_AND_NON_SECURE + The SU5 field is accessible from both Security states. + 0 + + + SECURE_ONLY + The SU5 field is only accessible from the Secure state. + 0x1 + + + + + SU6 + State UNKNOWN 6. + 12 + 1 + read-write + + + UNKNOWN_NOT_PERMITTED + The coprocessor state is not permitted to become UNKNOWN. + 0 + + + UNKNOWN_PERMITTED + The coprocessor state is permitted to become UNKNOWN. + 0x1 + + + + + SUS6 + State UNKNOWN Secure only 6. + 13 + 1 + read-write + + + SECURE_AND_NON_SECURE + The SU6 field is accessible from both Security states. + 0 + + + SECURE_ONLY + The SU6 field is only accessible from the Secure state. + 0x1 + + + + + SU7 + State UNKNOWN 7. + 14 + 1 + read-write + + + UNKNOWN_NOT_PERMITTED + The coprocessor state is not permitted to become UNKNOWN. + 0 + + + UNKNOWN_PERMITTED + The coprocessor state is permitted to become UNKNOWN. + 0x1 + + + + + SUS7 + State UNKNOWN Secure only 7. + 15 + 1 + read-write + + + SECURE_AND_NON_SECURE + The SU7 field is accessible from both Security states. + 0 + + + SECURE_ONLY + The SU7 field is only accessible from the Secure state. + 0x1 + + + + + SU10 + State UNKNOWN 10. + 20 + 1 + read-write + + + UNKNOWN_NOT_PERMITTED + The floating-point state is not permitted to become UNKNOWN. + 0 + + + UNKNOWN_PERMITTED + The floating-point state is permitted to become UNKNOWN + 0x1 + + + + + SUS10 + State UNKNOWN Secure only 10. + 21 + 1 + read-write + + + SECURE_AND_NON_SECURE + The SU10 field is accessible from both Security states. + 0 + + + SECURE_ONLY + The SU10 field is only accessible from the Secure state. + 0x1 + + + + + SU11 + State UNKNOWN 11. + 22 + 1 + read-write + + + SUS11 + State UNKNOWN Secure only 11. + 23 + 1 + read-write + + + + + + + NVIC + no description available + NVIC + 0xE000E100 + + 0 + 0xE04 + registers + + + + 16 + 0x4 + ISER[%s] + Interrupt Set Enable Register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + SETENA0 + Interrupt set-enable bits. + 0 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA1 + Interrupt set-enable bits. + 1 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA2 + Interrupt set-enable bits. + 2 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA3 + Interrupt set-enable bits. + 3 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA4 + Interrupt set-enable bits. + 4 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA5 + Interrupt set-enable bits. + 5 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA6 + Interrupt set-enable bits. + 6 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA7 + Interrupt set-enable bits. + 7 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA8 + Interrupt set-enable bits. + 8 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA9 + Interrupt set-enable bits. + 9 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA10 + Interrupt set-enable bits. + 10 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA11 + Interrupt set-enable bits. + 11 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA12 + Interrupt set-enable bits. + 12 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA13 + Interrupt set-enable bits. + 13 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA14 + Interrupt set-enable bits. + 14 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA15 + Interrupt set-enable bits. + 15 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA16 + Interrupt set-enable bits. + 16 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA17 + Interrupt set-enable bits. + 17 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA18 + Interrupt set-enable bits. + 18 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA19 + Interrupt set-enable bits. + 19 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA20 + Interrupt set-enable bits. + 20 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA21 + Interrupt set-enable bits. + 21 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA22 + Interrupt set-enable bits. + 22 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA23 + Interrupt set-enable bits. + 23 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA24 + Interrupt set-enable bits. + 24 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA25 + Interrupt set-enable bits. + 25 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA26 + Interrupt set-enable bits. + 26 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA27 + Interrupt set-enable bits. + 27 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA28 + Interrupt set-enable bits. + 28 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA29 + Interrupt set-enable bits. + 29 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA30 + Interrupt set-enable bits. + 30 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + SETENA31 + Interrupt set-enable bits. + 31 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + + + 16 + 0x4 + ICER[%s] + Interrupt Clear Enable Register + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + CLRENA0 + Interrupt clear-enable bits. + 0 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA1 + Interrupt clear-enable bits. + 1 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA2 + Interrupt clear-enable bits. + 2 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA3 + Interrupt clear-enable bits. + 3 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA4 + Interrupt clear-enable bits. + 4 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA5 + Interrupt clear-enable bits. + 5 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA6 + Interrupt clear-enable bits. + 6 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA7 + Interrupt clear-enable bits. + 7 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA8 + Interrupt clear-enable bits. + 8 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA9 + Interrupt clear-enable bits. + 9 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA10 + Interrupt clear-enable bits. + 10 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA11 + Interrupt clear-enable bits. + 11 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA12 + Interrupt clear-enable bits. + 12 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA13 + Interrupt clear-enable bits. + 13 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA14 + Interrupt clear-enable bits. + 14 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA15 + Interrupt clear-enable bits. + 15 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA16 + Interrupt clear-enable bits. + 16 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA17 + Interrupt clear-enable bits. + 17 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA18 + Interrupt clear-enable bits. + 18 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA19 + Interrupt clear-enable bits. + 19 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA20 + Interrupt clear-enable bits. + 20 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA21 + Interrupt clear-enable bits. + 21 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA22 + Interrupt clear-enable bits. + 22 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA23 + Interrupt clear-enable bits. + 23 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA24 + Interrupt clear-enable bits. + 24 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA25 + Interrupt clear-enable bits. + 25 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA26 + Interrupt clear-enable bits. + 26 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA27 + Interrupt clear-enable bits. + 27 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA28 + Interrupt clear-enable bits. + 28 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA29 + Interrupt clear-enable bits. + 29 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA30 + Interrupt clear-enable bits. + 30 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + CLRENA31 + Interrupt clear-enable bits. + 31 + 1 + read-write + + + DISABLED + Write: No effect; Read: Interrupt 32n+m disabled + 0 + + + ENABLED + Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled + 0x1 + + + + + + + 16 + 0x4 + ISPR[%s] + Interrupt Set Pending Register + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + SETPEND0 + Interrupt set-pending bits. + 0 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND1 + Interrupt set-pending bits. + 1 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND2 + Interrupt set-pending bits. + 2 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND3 + Interrupt set-pending bits. + 3 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND4 + Interrupt set-pending bits. + 4 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND5 + Interrupt set-pending bits. + 5 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND6 + Interrupt set-pending bits. + 6 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND7 + Interrupt set-pending bits. + 7 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND8 + Interrupt set-pending bits. + 8 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND9 + Interrupt set-pending bits. + 9 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND10 + Interrupt set-pending bits. + 10 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND11 + Interrupt set-pending bits. + 11 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND12 + Interrupt set-pending bits. + 12 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND13 + Interrupt set-pending bits. + 13 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND14 + Interrupt set-pending bits. + 14 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND15 + Interrupt set-pending bits. + 15 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND16 + Interrupt set-pending bits. + 16 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND17 + Interrupt set-pending bits. + 17 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND18 + Interrupt set-pending bits. + 18 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND19 + Interrupt set-pending bits. + 19 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND20 + Interrupt set-pending bits. + 20 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND21 + Interrupt set-pending bits. + 21 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND22 + Interrupt set-pending bits. + 22 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND23 + Interrupt set-pending bits. + 23 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND24 + Interrupt set-pending bits. + 24 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND25 + Interrupt set-pending bits. + 25 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND26 + Interrupt set-pending bits. + 26 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND27 + Interrupt set-pending bits. + 27 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND28 + Interrupt set-pending bits. + 28 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND29 + Interrupt set-pending bits. + 29 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND30 + Interrupt set-pending bits. + 30 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + SETPEND31 + Interrupt set-pending bits. + 31 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending + 0x1 + + + + + + + 16 + 0x4 + ICPR[%s] + Interrupt Clear Pending Register + 0x180 + 32 + read-write + 0 + 0xFFFFFFFF + + + CLRPEND0 + Interrupt clear-pending bits. + 0 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND1 + Interrupt clear-pending bits. + 1 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND2 + Interrupt clear-pending bits. + 2 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND3 + Interrupt clear-pending bits. + 3 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND4 + Interrupt clear-pending bits. + 4 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND5 + Interrupt clear-pending bits. + 5 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND6 + Interrupt clear-pending bits. + 6 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND7 + Interrupt clear-pending bits. + 7 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND8 + Interrupt clear-pending bits. + 8 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND9 + Interrupt clear-pending bits. + 9 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND10 + Interrupt clear-pending bits. + 10 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND11 + Interrupt clear-pending bits. + 11 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND12 + Interrupt clear-pending bits. + 12 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND13 + Interrupt clear-pending bits. + 13 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND14 + Interrupt clear-pending bits. + 14 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND15 + Interrupt clear-pending bits. + 15 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND16 + Interrupt clear-pending bits. + 16 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND17 + Interrupt clear-pending bits. + 17 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND18 + Interrupt clear-pending bits. + 18 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND19 + Interrupt clear-pending bits. + 19 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND20 + Interrupt clear-pending bits. + 20 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND21 + Interrupt clear-pending bits. + 21 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND22 + Interrupt clear-pending bits. + 22 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND23 + Interrupt clear-pending bits. + 23 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND24 + Interrupt clear-pending bits. + 24 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND25 + Interrupt clear-pending bits. + 25 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND26 + Interrupt clear-pending bits. + 26 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND27 + Interrupt clear-pending bits. + 27 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND28 + Interrupt clear-pending bits. + 28 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND29 + Interrupt clear-pending bits. + 29 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND30 + Interrupt clear-pending bits. + 30 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + CLRPEND31 + Interrupt clear-pending bits. + 31 + 1 + read-write + + + NOT_PENDING + Write: No effect; Read: Interrupt 32n+m is not pending + 0 + + + PENDING + Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending + 0x1 + + + + + + + 16 + 0x4 + IABR[%s] + Interrupt Active Bit Register + 0x200 + 32 + read-write + 0 + 0 + + + ACTIVE0 + Active state bits. + 0 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE1 + Active state bits. + 1 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE2 + Active state bits. + 2 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE3 + Active state bits. + 3 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE4 + Active state bits. + 4 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE5 + Active state bits. + 5 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE6 + Active state bits. + 6 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE7 + Active state bits. + 7 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE8 + Active state bits. + 8 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE9 + Active state bits. + 9 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE10 + Active state bits. + 10 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE11 + Active state bits. + 11 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE12 + Active state bits. + 12 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE13 + Active state bits. + 13 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE14 + Active state bits. + 14 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE15 + Active state bits. + 15 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE16 + Active state bits. + 16 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE17 + Active state bits. + 17 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE18 + Active state bits. + 18 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE19 + Active state bits. + 19 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE20 + Active state bits. + 20 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE21 + Active state bits. + 21 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE22 + Active state bits. + 22 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE23 + Active state bits. + 23 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE24 + Active state bits. + 24 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE25 + Active state bits. + 25 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE26 + Active state bits. + 26 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE27 + Active state bits. + 27 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE28 + Active state bits. + 28 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE29 + Active state bits. + 29 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE30 + Active state bits. + 30 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + ACTIVE31 + Active state bits. + 31 + 1 + read-write + + + NOT_ACTIVE + The interrupt is not active. + 0 + + + ACTIVE + The interrupt is active. + 0x1 + + + + + + + 16 + 0x4 + ITNS[%s] + Interrupt Target Non-secure Register + 0x280 + 32 + read-write + 0 + 0 + + + INTS0 + Interrupt Targets Non-secure bits. + 0 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS1 + Interrupt Targets Non-secure bits. + 1 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS2 + Interrupt Targets Non-secure bits. + 2 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS3 + Interrupt Targets Non-secure bits. + 3 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS4 + Interrupt Targets Non-secure bits. + 4 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS5 + Interrupt Targets Non-secure bits. + 5 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS6 + Interrupt Targets Non-secure bits. + 6 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS7 + Interrupt Targets Non-secure bits. + 7 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS8 + Interrupt Targets Non-secure bits. + 8 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS9 + Interrupt Targets Non-secure bits. + 9 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS10 + Interrupt Targets Non-secure bits. + 10 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS11 + Interrupt Targets Non-secure bits. + 11 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS12 + Interrupt Targets Non-secure bits. + 12 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS13 + Interrupt Targets Non-secure bits. + 13 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS14 + Interrupt Targets Non-secure bits. + 14 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS15 + Interrupt Targets Non-secure bits. + 15 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS16 + Interrupt Targets Non-secure bits. + 16 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS17 + Interrupt Targets Non-secure bits. + 17 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS18 + Interrupt Targets Non-secure bits. + 18 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS19 + Interrupt Targets Non-secure bits. + 19 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS20 + Interrupt Targets Non-secure bits. + 20 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS21 + Interrupt Targets Non-secure bits. + 21 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS22 + Interrupt Targets Non-secure bits. + 22 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS23 + Interrupt Targets Non-secure bits. + 23 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS24 + Interrupt Targets Non-secure bits. + 24 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS25 + Interrupt Targets Non-secure bits. + 25 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS26 + Interrupt Targets Non-secure bits. + 26 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS27 + Interrupt Targets Non-secure bits. + 27 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS28 + Interrupt Targets Non-secure bits. + 28 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS29 + Interrupt Targets Non-secure bits. + 29 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS30 + Interrupt Targets Non-secure bits. + 30 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + INTS31 + Interrupt Targets Non-secure bits. + 31 + 1 + read-write + + + SECURE_STATE + The interrupt targets Secure state. + 0 + + + NON_SECURE_STATE + The interrupt targets Non-secure state. + 0x1 + + + + + + + 120 + 0x4 + IPR[%s] + Interrupt Priority Register + 0x300 + 32 + read-write + 0 + 0 + + + PRI_0 + no description available + 0 + 8 + read-write + + + PRI_1 + no description available + 8 + 8 + read-write + + + PRI_2 + no description available + 16 + 8 + read-write + + + PRI_3 + no description available + 24 + 8 + read-write + + + + + STIR + Software Trigger Interrupt Register + 0xE00 + 32 + read-write + 0 + 0xFFFFFFFF + + + INTID + Interrupt ID of the interrupt to trigger, in the range 0-479. + 0 + 9 + write-only + + + + + + + SCB + no description available + SCB + 0xE000ED00 + + 0 + 0x90 + registers + + + + AIRCR + Application Interrupt and Reset Control Register + 0xC + 32 + read-write + 0xFA050000 + 0xFFFFFFFF + + + VECTCLRACTIVE + Reserved for Debug use. This bit reads as 0. When writing to the register you must write 0 to this bit, otherwise behavior is UNPREDICTABLE. This bit is not banked between Security states. + 1 + 1 + write-only + + + SYSRESETREQ + System reset request. This bit allows software or a debugger to request a system reset. This bit is not banked between Security states. RW if SYSRESETREQS is 0. When SYSRESETREQS is set to 1, from Non-secure state this bit acts as RAZ/WI. + 2 + 1 + read-write + + + NO_REQUEST + Do not request a system reset. + 0 + + + REQUEST_RESET + Request a system reset. + 0x1 + + + + + SYSRESETREQS + System reset request, Secure state only. The value of this bit defines whether the SYSRESETREQ bit is functional for Non-secure use. This bit is not banked between Security states. RW from Secure State and RAZ/WI from Non-secure state. + 3 + 1 + read-write + + + SECURE_AND_NON_SECURE + SYSRESETREQ functionality is available to both Security states. + 0 + + + SECURE_ONLY + SYSRESETREQ functionality is only available to Secure state. + 0x1 + + + + + PRIGROUP + Interrupt priority grouping field. This field determines the split of group priority from subpriority. This bit is banked between Security states + 8 + 3 + read-write + + + BFHFNMINS + BusFault, HardFault, and NMI Non-secure enable. The value of this bit defines whether BusFault and NMI exceptions are Non-secure, and whether exceptions target the Non-secure HardFault exception. This bit is not banked between Security states. RW from Secure-state and RO from Non-secure state. + 13 + 1 + read-write + + + SECURE + BusFault, HardFault, and NMI are Secure. + 0 + + + NON_SECURE + BusFault and NMI are Non-secure and exceptions can target Non-secure HardFault. + 0x1 + + + + + PRIS + Prioritize Secure exceptions. The value of this bit defines whether Secure exception priority boosting is enabled. This bit is not banked between Security states. RW from Secure state and RAZ/WI from Non-secure state. + 14 + 1 + read-write + + + SAME_PRIORITY + Priority ranges of Secure and Non-secure exceptions are identical + 0 + + + SECURE_PRIORITIZED + Non-secure exceptions are de-prioritized + 0x1 + + + + + ENDIANNESS + Data endianness bit. This bit is not banked between Security states. + 15 + 1 + read-only + + + LITTLE_ENDIAN + Little-endian. + 0 + + + BIG_ENDIAN + Big-endian + 0x1 + + + + + VECTKEY + Register key: Reads as 0xFA05. On writes, write 0x5FA to VECTKEY, otherwise the write is ignored. This Field is not banked between Security states. + 16 + 16 + read-only + + + + + SCR + The SCR controls features of entry to and exit from low-power state. + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + SLEEPONEXIT + Indicates sleep-on-exit when returning from Handler mode to Thread mode. Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application. This bit is banked between Security states. + 1 + 1 + read-write + + + NOT_SLEEP + Do not sleep when returning to Thread mode. + 0 + + + SLEEP + Enter sleep, or deep sleep, on return from an ISR + 0x1 + + + + + SLEEPDEEP + Controls whether the processor uses sleep or deep sleep as its low-power mode. This bit is not banked between Security states. + 2 + 1 + read-write + + + SLEEP + Sleep. + 0 + + + DEEP_SLEEP + Deep sleep. + 0x1 + + + + + SLEEPDEEPS + Controls whether the SLEEPDEEP bit is only accessible from the Secure state. This bit in only accessible from the Secure state, and behaves as RAZ/WI when accessed from the Nonsecure state. This bit is not banked between Security states. + 3 + 1 + read-write + + + SECURE_AND_NON_SECURE + The SLEEPDEEP bit is accessible from both Security states. + 0 + + + SECURE_ONLY + The SLEEPDEEP bit behaves as RAZ/WI when accessed from the Non-secure state. + 0x1 + + + + + SEVONPEND + Send Event on Pending bit. When an event or interrupt enters pending state, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE. The processor also wakes up on execution of an SEV instruction or an external event. This bit is banked between Security states. + 4 + 1 + read-write + + + EXCLUDE_DISABLED_INTERRUPTS + Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded. + 0 + + + INCLUDE_DISABLED_INTERRUPTS + Enabled events and all interrupts, including disabled interrupts, can wakeup the processor + 0x1 + + + + + + + SHCSR + System Handler Control and State Register + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + MEMFAULTACT + MemManage exception active. + 0 + 1 + read-write + + + NOT_ACTIVE + MemManage exception is not active. + 0 + + + ACTIVE + MemManage exception is active. + 0x1 + + + + + BUSFAULTACT + BusFault exception active. + 1 + 1 + read-write + + + NOT_ACTIVE + BusFault exception is not active. + 0 + + + ACTIVE + BusFault exception is active. + 0x1 + + + + + HARDFAULTACT + HardFault exception active. + 2 + 1 + read-write + + + NOT_ACTIVE + HardFault exception is not active. + 0 + + + ACTIVE + HardFault exception is active. + 0x1 + + + + + USGFAULTACT + UsageFault exception active. + 3 + 1 + read-write + + + NOT_ACTIVE + UsageFault exception is not active. + 0 + + + ACTIVE + UsageFault exception is active. + 0x1 + + + + + SECUREFAULTACT + SecureFault exception active + 4 + 1 + read-write + + + NOT_ACTIVE + SecureFault exception is not active. + 0 + + + ACTIVE + SecureFault exception is active. + 0x1 + + + + + NMIACT + NMI exception active. + 5 + 1 + read-write + + + NOT_ACTIVE + NMI exception is not active. + 0 + + + ACTIVE + NMI exception is active. + 0x1 + + + + + SVCALLACT + SVCall active. + 7 + 1 + read-write + + + NOT_ACTIVE + SVCall exception is not active. + 0 + + + ACTIVE + SVCall exception is active. + 0x1 + + + + + MONITORACT + Debug monitor active. + 8 + 1 + read-write + + + NOT_ACTIVE + Debug monitor exception is not active. + 0 + + + ACTIVE + Debug monitor exception is active. + 0x1 + + + + + PENDSVACT + PendSV exception active. + 10 + 1 + read-write + + + NOT_ACTIVE + PendSV exception is not active. + 0 + + + ACTIVE + PendSV exception is active. + 0x1 + + + + + SYSTICKACT + SysTick exception active. + 11 + 1 + read-write + + + NOT_ACTIVE + SysTick exception is not active. + 0 + + + ACTIVE + SysTick exception is active. + 0x1 + + + + + USGFAULTPENDED + UsageFault exception pending. + 12 + 1 + read-write + + + NOT_PENDING + UsageFault exception is not pending. + 0 + + + PENDING + UsageFault exception is pending. + 0x1 + + + + + MEMFAULTPENDED + MemManage exception pending. + 13 + 1 + read-write + + + NOT_PENDING + MemManage exception is not pending. + 0 + + + PENDING + MemManage exception is pending. + 0x1 + + + + + BUSFAULTPENDED + BusFault exception pending. + 14 + 1 + read-write + + + NOT_PENDING + BusFault exception is pending. + 0 + + + PENDING + BusFault exception is not pending. + 0x1 + + + + + SVCALLPENDED + SVCall pending. + 15 + 1 + read-write + + + NOT_PENDING + SVCall exception is not pending. + 0 + + + PENDING + SVCall exception is pending. + 0x1 + + + + + MEMFAULTENA + MemManage enable. + 16 + 1 + read-write + + + DISABLED + MemManage exception is disabled. + 0 + + + ENABLED + MemManage exception is enabled. + 0x1 + + + + + BUSFAULTENA + BusFault enable. + 17 + 1 + read-write + + + DISABLED + BusFault is disabled. + 0 + + + ENABLED + BusFault is enabled. + 0x1 + + + + + USGFAULTENA + UsageFault enable. + 18 + 1 + read-write + + + DISABLED + UsageFault is disabled. + 0 + + + ENABLED + UsageFault is enabled. + 0x1 + + + + + SECUREFAULTENA + SecureFault exception enable. + 19 + 1 + read-write + + + DISABLED + SecureFault exception is disabled. + 0 + + + ENABLED + SecureFault exception is enabled. + 0x1 + + + + + SECUREFAULTPENDED + SecureFault exception pended state bit. + 20 + 1 + read-write + + + DISABLED + SecureFault exception modification is disabled. + 0 + + + ENABLED + SecureFault exception modification is enabled. + 0x1 + + + + + HARDFAULTPENDED + HardFault exception pended state + 21 + 1 + read-write + + + DISABLED + HardFault exception modification is disabled. + 0 + + + ENABLED + HardFault exception modification is enabled. + 0x1 + + + + + + + NSACR + Non-secure Access Control Register + 0x8C + 32 + read-write + 0 + 0 + + + CP0 + CP0 access. + 0 + 1 + read-write + + + NOT_PERMITTED + Non-secure accesses to this coprocessor generate a NOCP UsageFault. + 0 + + + PERMITTED + Non-secure access to this coprocessor permitted. + 0x1 + + + + + CP1 + CP1 access. + 1 + 1 + read-write + + + NOT_PERMITTED + Non-secure accesses to this coprocessor generate a NOCP UsageFault. + 0 + + + PERMITTED + Non-secure access to this coprocessor permitted. + 0x1 + + + + + CP2 + CP2 access. + 2 + 1 + read-write + + + NOT_PERMITTED + Non-secure accesses to this coprocessor generate a NOCP UsageFault. + 0 + + + PERMITTED + Non-secure access to this coprocessor permitted. + 0x1 + + + + + CP3 + CP3 access. + 3 + 1 + read-write + + + NOT_PERMITTED + Non-secure accesses to this coprocessor generate a NOCP UsageFault. + 0 + + + PERMITTED + Non-secure access to this coprocessor permitted. + 0x1 + + + + + CP4 + CP4 access. + 4 + 1 + read-write + + + NOT_PERMITTED + Non-secure accesses to this coprocessor generate a NOCP UsageFault. + 0 + + + PERMITTED + Non-secure access to this coprocessor permitted. + 0x1 + + + + + CP5 + CP5 access. + 5 + 1 + read-write + + + NOT_PERMITTED + Non-secure accesses to this coprocessor generate a NOCP UsageFault. + 0 + + + PERMITTED + Non-secure access to this coprocessor permitted. + 0x1 + + + + + CP6 + CP6 access. + 6 + 1 + read-write + + + NOT_PERMITTED + Non-secure accesses to this coprocessor generate a NOCP UsageFault. + 0 + + + PERMITTED + Non-secure access to this coprocessor permitted. + 0x1 + + + + + CP7 + CP7 access. + 7 + 1 + read-write + + + NOT_PERMITTED + Non-secure accesses to this coprocessor generate a NOCP UsageFault. + 0 + + + PERMITTED + Non-secure access to this coprocessor permitted. + 0x1 + + + + + CP10 + CP10 access. + 10 + 1 + read-write + + + NOT_PERMITTED + Non-secure accesses to the Floating-point Extension generate a NOCP UsageFault. + 0 + + + PERMITTED + Non-secure access to the Floatingpoint Extension permitted. + 0x1 + + + + + CP11 + CP11 access. + 11 + 1 + read-write + + + + + + + SAU + no description available + SAU + 0xE000EDD0 + + 0 + 0xEC + registers + + + + SAU_CTRL + Security Attribution Unit Control Register + 0xD0 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENABLE + Enable. Enables the SAU. This bit is RAZ/WI when the Security Extension is implemented without an SAU region. + 0 + 1 + read-write + + + DISABLED + The SAU is disabled. + 0 + + + ENABLED + The SAU is enabled. + 0x1 + + + + + ALLNS + All Non-secure. + 1 + 1 + read-write + + + SECURED_MEMORY + Memory is marked as Secure and is not Non-secure callable. + 0 + + + NON_SECURED_MEMORY + Memory is marked as Non-secure. + 0x1 + + + + + + + SAU_TYPE + Security Attribution Unit Type Register + 0xD4 + 32 + read-write + 0 + 0xFFFFFFFF + + + SREGION + SAU regions. The number of implemented SAU regions. + 0 + 8 + read-write + + + + + SAU_RNR + Security Attribution Unit Region Number Register + 0xD8 + 32 + read-write + 0 + 0 + + + REGION + Region number. + 0 + 8 + read-write + + + + + SAU_RBAR + Security Attribution Unit Region Base Address Register + 0xDC + 32 + read-write + 0 + 0 + + + BADDR + Base address. Holds bits[31:5] of the base address for the selected SAU region. Bits[4:0] of the base address are defined as 0x00. + 5 + 27 + read-write + + + + + SAU_RLAR + Security Attribution Unit Region Limit Address Register + 0xE0 + 32 + read-write + 0 + 0 + + + ENABLE + Enable. SAU region enable. + 0 + 1 + read-write + + + ENABLED + SAU region is enabled. + 0 + + + DISABLED + SAU region is disabled. + 0x1 + + + + + NSC + Non-secure callable. Controls whether Non-secure state is permitted to execute an SG instruction from this region. + 1 + 1 + read-write + + + NOT_NON_SECURE_CALLABLE + Region is not Non-secure callable. + 0 + + + NON_SECURE_CALLABLE + Region is Non-secure callable. + 0x1 + + + + + LADDR + Limit address. Holds bits[31:5] of the limit address for the selected SAU region. Bits[4:0] of the limit address are defined as 0x1F. + 5 + 27 + read-write + + + + + SFSR + Secure Fault Status Register + 0xE4 + 32 + read-write + 0 + 0xFFFFFFFF + + + INVEP + Invalid entry point. + 0 + 1 + read-write + + + NO_ERROR + Error has not occurred. + 0 + + + ERROR + Error has occurred. + 0x1 + + + + + INVIS + Invalid integrity signature flag. + 1 + 1 + read-write + + + NO_ERROR + Error has not occurred. + 0 + + + ERROR + Error has occurred. + 0x1 + + + + + INVER + Invalid exception return flag. + 2 + 1 + read-write + + + NO_ERROR + Error has not occurred. + 0 + + + ERROR + Error has occurred. + 0x1 + + + + + AUVIOL + Attribution unit violation flag. + 3 + 1 + read-write + + + NO_ERROR + Error has not occurred. + 0 + + + ERROR + Error has occurred. + 0x1 + + + + + INVTRAN + Invalid transition flag. + 4 + 1 + read-write + + + NO_ERROR + Error has not occurred. + 0 + + + ERROR + Error has occurred. + 0x1 + + + + + LSPERR + Lazy state preservation error flag. + 5 + 1 + read-write + + + NO_ERROR + Error has not occurred. + 0 + + + ERROR + Error has occurred. + 0x1 + + + + + SFARVALID + Secure fault address valid. + 6 + 1 + read-write + + + NOT_VALID + SFAR content not valid. + 0 + + + VALID + SFAR content valid. + 0x1 + + + + + LSERR + Lazy state error flag. + 7 + 1 + read-write + + + NO_ERROR + Error has not occurred + 0 + + + ERROR + Error has occurred. + 0x1 + + + + + + + SFAR + Secure Fault Address Register + 0xE8 + 32 + read-write + 0 + 0 + + + ADDRESS + When the SFARVALID bit of the SFSR is set to 1, this field holds the address of an access that caused an SAU violation. + 0 + 32 + read-write + + + + + + + \ No newline at end of file diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/LPC55S69_cm33_core1_features.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/LPC55S69_cm33_core1_features.h new file mode 100644 index 000000000..91cf68b23 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/LPC55S69_cm33_core1_features.h @@ -0,0 +1,305 @@ +/* +** ################################################################### +** Version: rev. 1.0, 2018-08-22 +** Build: b190418 +** +** Abstract: +** Chip specific module features. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2019 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2018-08-22) +** Initial version based on v0.2UM +** +** ################################################################### +*/ + +#ifndef _LPC55S69_cm33_core1_FEATURES_H_ +#define _LPC55S69_cm33_core1_FEATURES_H_ + +/* SOC module features */ + +/* @brief CASPER availability on the SoC. */ +#define FSL_FEATURE_SOC_CASPER_COUNT (1) +/* @brief CRC availability on the SoC. */ +#define FSL_FEATURE_SOC_CRC_COUNT (1) +/* @brief CTIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_CTIMER_COUNT (5) +/* @brief DMA availability on the SoC. */ +#define FSL_FEATURE_SOC_DMA_COUNT (2) +/* @brief FLASH availability on the SoC. */ +#define FSL_FEATURE_SOC_FLASH_COUNT (1) +/* @brief FLEXCOMM availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXCOMM_COUNT (9) +/* @brief GINT availability on the SoC. */ +#define FSL_FEATURE_SOC_GINT_COUNT (2) +/* @brief GPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_GPIO_COUNT (1) +/* @brief SECGPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_SECGPIO_COUNT (1) +/* @brief HASHCRYPT availability on the SoC. */ +#define FSL_FEATURE_SOC_HASHCRYPT_COUNT (1) +/* @brief I2C availability on the SoC. */ +#define FSL_FEATURE_SOC_I2C_COUNT (8) +/* @brief I2S availability on the SoC. */ +#define FSL_FEATURE_SOC_I2S_COUNT (8) +/* @brief INPUTMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) +/* @brief IOCON availability on the SoC. */ +#define FSL_FEATURE_SOC_IOCON_COUNT (1) +/* @brief LPADC availability on the SoC. */ +#define FSL_FEATURE_SOC_LPADC_COUNT (1) +/* @brief MAILBOX availability on the SoC. */ +#define FSL_FEATURE_SOC_MAILBOX_COUNT (1) +/* @brief MRT availability on the SoC. */ +#define FSL_FEATURE_SOC_MRT_COUNT (1) +/* @brief OSTIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_OSTIMER_COUNT (1) +/* @brief PINT availability on the SoC. */ +#define FSL_FEATURE_SOC_PINT_COUNT (1) +/* @brief SECPINT availability on the SoC. */ +#define FSL_FEATURE_SOC_SECPINT_COUNT (1) +/* @brief PMC availability on the SoC. */ +#define FSL_FEATURE_SOC_PMC_COUNT (1) +/* @brief POWERQUAD availability on the SoC. */ +#define FSL_FEATURE_SOC_POWERQUAD_COUNT (1) +/* @brief PUF availability on the SoC. */ +#define FSL_FEATURE_SOC_PUF_COUNT (1) +/* @brief RNG1 availability on the SoC. */ +#define FSL_FEATURE_SOC_LPC_RNG1_COUNT (1) +/* @brief RTC availability on the SoC. */ +#define FSL_FEATURE_SOC_RTC_COUNT (1) +/* @brief SCT availability on the SoC. */ +#define FSL_FEATURE_SOC_SCT_COUNT (1) +/* @brief SDIF availability on the SoC. */ +#define FSL_FEATURE_SOC_SDIF_COUNT (1) +/* @brief SPI availability on the SoC. */ +#define FSL_FEATURE_SOC_SPI_COUNT (9) +/* @brief SYSCON availability on the SoC. */ +#define FSL_FEATURE_SOC_SYSCON_COUNT (1) +/* @brief SYSCTL1 availability on the SoC. */ +#define FSL_FEATURE_SOC_SYSCTL1_COUNT (1) +/* @brief USART availability on the SoC. */ +#define FSL_FEATURE_SOC_USART_COUNT (8) +/* @brief USB availability on the SoC. */ +#define FSL_FEATURE_SOC_USB_COUNT (1) +/* @brief USBFSH availability on the SoC. */ +#define FSL_FEATURE_SOC_USBFSH_COUNT (1) +/* @brief USBHSD availability on the SoC. */ +#define FSL_FEATURE_SOC_USBHSD_COUNT (1) +/* @brief USBHSH availability on the SoC. */ +#define FSL_FEATURE_SOC_USBHSH_COUNT (1) +/* @brief USBPHY availability on the SoC. */ +#define FSL_FEATURE_SOC_USBPHY_COUNT (1) +/* @brief UTICK availability on the SoC. */ +#define FSL_FEATURE_SOC_UTICK_COUNT (1) +/* @brief WWDT availability on the SoC. */ +#define FSL_FEATURE_SOC_WWDT_COUNT (1) + +/* LPADC module features */ + +/* @brief FIFO availability on the SoC. */ +#define FSL_FEATURE_LPADC_FIFO_COUNT (2) +/* @brief Has subsequent trigger priority (bitfield CFG[TPRICTRL]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY (1) +/* @brief Has differential mode (bitfield CMDLn[DIFF]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (0) +/* @brief Has channel scale (bitfield CMDLn[CSCALE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_CSCALE (0) +/* @brief Has conversion type select (bitfield CMDLn[CTYPE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (1) +/* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_MODE (1) +/* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */ +#define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1) +/* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */ +#define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (1) +/* @brief Has offset calibration (bitfield CTRL[CALOFS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFS (1) +/* @brief Has gain calibration (bitfield CTRL[CAL_REQ]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ (1) +/* @brief Has calibration average (bitfield CTRL[CAL_AVGS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS (1) +/* @brief Has internal clock (bitfield CFG[ADCKEN]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (0) +/* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG (0) +/* @brief Has calibration (bitfield CFG[CALOFS]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0) +/* @brief Has offset trim (register OFSTRIM). */ +#define FSL_FEATURE_LPADC_HAS_OFSTRIM (1) + +/* CASPER module features */ + +/* @brief Base address of the CASPER dedicated RAM */ +#define FSL_FEATURE_CASPER_RAM_BASE_ADDRESS (0x04000000) +/* @brief Interleaving of the CASPER dedicated RAM */ +#define FSL_FEATURE_CASPER_RAM_IS_INTERLEAVED (1) + +/* DMA module features */ + +/* @brief Number of channels */ +#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (30) +/* @brief Align size of DMA descriptor */ +#define FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE (512) +/* @brief DMA head link descriptor table align size */ +#define FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE (16U) + +/* FLEXCOMM module features */ + +/* @brief I2S has DMIC interconnection */ +#define FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_HAS_DMIC_INTERCONNECTIONn(x) (0) + +/* HASHCRYPT module features */ + +/* @brief the address of alias offset */ +#define FSL_FEATURE_HASHCRYPT_ALIAS_OFFSET (0x00000000) + +/* I2S module features */ + +/* @brief I2S support dual channel transfer. */ +#define FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL (1) +/* @brief I2S has DMIC interconnection. */ +#define FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION (0) + +/* IOCON module features */ + +/* @brief Func bit field width */ +#define FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH (4) + +/* MAILBOX module features */ + +/* @brief Mailbox side for current core */ +#define FSL_FEATURE_MAILBOX_SIDE_B (1) + +/* MRT module features */ + +/* @brief number of channels. */ +#define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4) + +/* PINT module features */ + +/* @brief Number of connected outputs */ +#define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8) + +/* POWERLIB module features */ + +/* @brief LPC55XX's Powerlib API is different with other LPC series devices. */ +#define FSL_FEATURE_POWERLIB_LPC55XX_EXTEND (1) + +/* POWERQUAD module features */ + +/* @brief Sine and Cossine fix errata */ +#define FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA (1) + +/* PUF module features */ + +/* @brief Number of PUF key slots available on device. */ +#define FSL_FEATURE_PUF_HAS_KEYSLOTS (4) +/* @brief the shift status value */ +#define FSL_FEATURE_PUF_HAS_SHIFT_STATUS (1) + +/* SCT module features */ + +/* @brief Number of events */ +#define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (16) +/* @brief Number of states */ +#define FSL_FEATURE_SCT_NUMBER_OF_STATES (32) +/* @brief Number of match capture */ +#define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) +/* @brief Number of outputs */ +#define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) + +/* SDIF module features */ + +/* @brief FIFO depth, every location is a WORD */ +#define FSL_FEATURE_SDIF_FIFO_DEPTH_64_32BITS (64) +/* @brief Max DMA buffer size */ +#define FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE (4096) +/* @brief Max source clock in HZ */ +#define FSL_FEATURE_SDIF_MAX_SOURCE_CLOCK (52000000) +/* @brief support 2 cards */ +#define FSL_FEATURE_SDIF_ONE_INSTANCE_SUPPORT_TWO_CARD (1) + +/* SECPINT module features */ + +/* @brief Number of connected outputs */ +#define FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS (2) + +/* SYSCON module features */ + +/* @brief Pointer to ROM IAP entry functions */ +#define FSL_FEATURE_SYSCON_IAP_ENTRY_LOCATION (0x03000205) +/* @brief Flash page size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (512) +/* @brief Flash sector size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (32768) +/* @brief Flash size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (622592) +/* @brief Has Power Down mode */ +#define FSL_FEATURE_SYSCON_HAS_POWERDOWN_MODE (1) +/* @brief CCM_ANALOG availability on the SoC. */ +#define FSL_FEATURE_SOC_CCM_ANALOG_COUNT (1) + +/* USB module features */ + +/* @brief Size of the USB dedicated RAM */ +#define FSL_FEATURE_USB_USB_RAM (0x00004000) +/* @brief Base address of the USB dedicated RAM */ +#define FSL_FEATURE_USB_USB_RAM_BASE_ADDRESS (0x40100000) +/* @brief USB version */ +#define FSL_FEATURE_USB_VERSION (200) +/* @brief Number of the endpoint in USB FS */ +#define FSL_FEATURE_USB_EP_NUM (5) + +/* USBFSH module features */ + +/* @brief Size of the USB dedicated RAM */ +#define FSL_FEATURE_USBFSH_USB_RAM (0x00004000) +/* @brief Base address of the USB dedicated RAM */ +#define FSL_FEATURE_USBFSH_USB_RAM_BASE_ADDRESS (0x40100000) +/* @brief USBFSH version */ +#define FSL_FEATURE_USBFSH_VERSION (200) + +/* USBHSD module features */ + +/* @brief Size of the USB dedicated RAM */ +#define FSL_FEATURE_USBHSD_USB_RAM (0x00004000) +/* @brief Base address of the USB dedicated RAM */ +#define FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS (0x40100000) +/* @brief USBHSD version */ +#define FSL_FEATURE_USBHSD_VERSION (300) +/* @brief Number of the endpoint in USB HS */ +#define FSL_FEATURE_USBHSD_EP_NUM (6) + +/* USBHSH module features */ + +/* @brief Size of the USB dedicated RAM */ +#define FSL_FEATURE_USBHSH_USB_RAM (0x00004000) +/* @brief Base address of the USB dedicated RAM */ +#define FSL_FEATURE_USBHSH_USB_RAM_BASE_ADDRESS (0x40100000) +/* @brief USBHSH version */ +#define FSL_FEATURE_USBHSH_VERSION (300) + +/* UTICK module features */ + +/* @brief UTICK does not support PD configure. */ +#define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1) + +/* WWDT module features */ + +/* @brief WWDT does not support oscillator lock. */ +#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (1) +/* @brief WWDT does not support power down configure */ +#define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1) + +#endif /* _LPC55S69_cm33_core1_FEATURES_H_ */ + diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55S69_cm33_core0_flash.scf b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55S69_cm33_core0_flash.scf new file mode 100644 index 000000000..e9c4063e4 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55S69_cm33_core0_flash.scf @@ -0,0 +1,104 @@ +#!armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -x c +/* +** ################################################################### +** Processors: LPC55S69JBD100_cm33_core0 +** LPC55S69JET98_cm33_core0 +** +** Compiler: Keil ARM C/C++ Compiler +** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.2 15 Aug 2018 +** Version: rev. 1.0, 2018-08-22 +** Build: b181008 +** +** Abstract: +** Linker file for the Keil ARM C/C++ Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + + +/* USB BDT size */ +#define usb_bdt_size 0x0 +/* Sizes */ +#if (defined(__stack_size__)) + #define Stack_Size __stack_size__ +#else + #define Stack_Size 0x0400 +#endif + +#if (defined(__heap_size__)) + #define Heap_Size __heap_size__ +#else + #define Heap_Size 0x0400 +#endif + +#define m_interrupts_start 0x00000000 +#define m_interrupts_size 0x00000200 + +#define m_text_start 0x00000200 +#define m_text_size 0x00071E00 + +#define m_core1_image_start 0x00072000 +#define m_core1_image_size 0x00026000 + +#if (defined(__use_shmem__)) + #define m_data_start 0x20000000 + #define m_data_size 0x00031800 + #define m_rpmsg_sh_mem_start 0x20031800 + #define m_rpmsg_sh_mem_size 0x00001800 +#else + #define m_data_start 0x20000000 + #define m_data_size 0x00033000 +#endif + +#define m_usb_sram_start 0x40100000 +#define m_usb_sram_size 0x00004000 + + +LR_m_text m_interrupts_start m_interrupts_size+m_text_size { ; load region size_region + + VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address + * (RESET,+FIRST) + } + + ER_m_text m_text_start FIXED m_text_size { ; load address = execution address + * (InRoot$$Sections) + * (+RO) + } + +#if (defined(__use_shmem__)) + RPMSG_SH_MEM m_rpmsg_sh_mem_start UNINIT m_rpmsg_sh_mem_size { ; Shared memory used by RPMSG + * (rpmsg_sh_mem_section) + } +#endif + + RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data + * (+RW +ZI) + } + ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up + } + ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down + } + + RW_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size { + * (m_usb_bdt) + } + + RW_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) { + * (m_usb_global) + } +} + +LR_CORE1_IMAGE m_core1_image_start { + CORE1_REGION m_core1_image_start m_core1_image_size { + *(M0CODE) + } +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55S69_cm33_core0_flash_ns.scf b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55S69_cm33_core0_flash_ns.scf new file mode 100644 index 000000000..22b5cf6b6 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55S69_cm33_core0_flash_ns.scf @@ -0,0 +1,111 @@ +#!armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -x c +/* +** ################################################################### +** Processors: LPC55S69JBD100_cm33_core0 +** LPC55S69JET98_cm33_core0 +** +** Compiler: Keil ARM C/C++ Compiler +** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.2 15 Aug 2018 +** Version: rev. 1.0, 2018-08-22 +** Build: b180921 +** +** Abstract: +** Linker file for the Keil ARM C/C++ Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + + +/* USB BDT size */ +#define usb_bdt_size 0x0 +/* Sizes */ +#if (defined(__stack_size__)) + #define Stack_Size __stack_size__ +#else + #define Stack_Size 0x0400 +#endif + +#if (defined(__heap_size__)) + #define Heap_Size __heap_size__ +#else + #define Heap_Size 0x0400 +#endif + +/* The first 64kB of FLASH is used as secure memory. The rest of FLASH memory is non-secure memory. */ +#define m_interrupts_start 0x00010000 +#define m_interrupts_size 0x00000140 + +#define m_text_start 0x00010140 +#define m_text_size 0x00061EC0 + +#define m_core1_image_start 0x00072000 +#define m_core1_image_size 0x00026000 + +/* The first 32kB of data RAM is used as secure memory. The rest of data RAM memory is non-secure memory. */ +#if (defined(__use_shmem__)) + #define m_data_start 0x20008000 + #define m_data_size 0x00028000 + #define m_rpmsg_sh_mem_start 0x20031800 + #define m_rpmsg_sh_mem_size 0x00001800 +#else + #define m_data_start 0x20008000 + #define m_data_size 0x0002B000 +#endif + +#define m_usb_sram_start 0x40100000 +#define m_usb_sram_size 0x00004000 + + +LR_m_text m_text_start m_text_size { ; load region size_region + ER_m_text m_text_start FIXED m_text_size { ; load address = execution address + * (InRoot$$Sections) + * (+RO) + } + +#if (defined(__use_shmem__)) + RPMSG_SH_MEM m_rpmsg_sh_mem_start UNINIT m_rpmsg_sh_mem_size { ; Shared memory used by RPMSG + * (rpmsg_sh_mem_section) + } +#endif + + RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data + * (+RW +ZI) + } + ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up + } + ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down + } +} + +LR_m_interrupts m_interrupts_start m_interrupts_size { + VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address + * (RESET,+FIRST) + } +} + +LR_m_usb_bdt m_usb_sram_start usb_bdt_size { + ER_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size { + * (m_usb_bdt) + } +} + +LR_m_usb_ram (m_usb_sram_start + usb_bdt_size) (m_usb_sram_size - usb_bdt_size) { + ER_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) { + * (m_usb_global) + } +} + +LR_CORE1_IMAGE m_core1_image_start { + CORE1_REGION m_core1_image_start m_core1_image_size { + *(M0CODE) + } +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55S69_cm33_core0_flash_s.scf b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55S69_cm33_core0_flash_s.scf new file mode 100644 index 000000000..94fca1816 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55S69_cm33_core0_flash_s.scf @@ -0,0 +1,122 @@ +#!armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -x c +/* +** ################################################################### +** Processors: LPC55S69JBD100_cm33_core0 +** LPC55S69JET98_cm33_core0 +** +** Compiler: Keil ARM C/C++ Compiler +** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.2 15 Aug 2018 +** Version: rev. 1.0, 2018-08-22 +** Build: b180921 +** +** Abstract: +** Linker file for the Keil ARM C/C++ Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + + +/* USB BDT size */ +#define usb_bdt_size 0x0 +/* Sizes */ +#if (defined(__stack_size__)) + #define Stack_Size __stack_size__ +#else + #define Stack_Size 0x0400 +#endif + +#if (defined(__heap_size__)) + #define Heap_Size __heap_size__ +#else + #define Heap_Size 0x0400 +#endif + +/* Only the first 64kB of flash is used as secure memory. */ +#define m_interrupts_start 0x10000000 +#define m_interrupts_size 0x00000140 + +#define m_text_start 0x10000140 +#define m_text_size 0x0000FCC0 + +#define m_core1_image_start 0x10072000 +#define m_core1_image_size 0x00026000 + +/* Only first 32kB of data RAM is used as secure memory. */ +#if (defined(__use_shmem__)) + #define m_data_start 0x30000000 + #define m_data_size 0x00008000 + #define m_rpmsg_sh_mem_start 0x30031800 + #define m_rpmsg_sh_mem_size 0x00001800 +#else + #define m_data_start 0x30000000 + #define m_data_size 0x00008000 +#endif + +/* 512B - memory for veneer table (NSC - secure, non-secure callable memory) */ +#define m_veneer_table_start 0x1000FE00 +#define m_veneer_table_size 0x200 + + +#define m_usb_sram_start 0x50100000 +#define m_usb_sram_size 0x00004000 + + +LR_m_text m_text_start m_text_size { ; load region size_region + ER_m_text m_text_start FIXED m_text_size { ; load address = execution address + * (InRoot$$Sections) + * (+RO) + } + +#if (defined(__use_shmem__)) + RPMSG_SH_MEM m_rpmsg_sh_mem_start UNINIT m_rpmsg_sh_mem_size { ; Shared memory used by RPMSG + * (rpmsg_sh_mem_section) + } +#endif + + RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data + * (+RW +ZI) + } + ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up + } + ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down + } +} + +LR_m_interrupts m_interrupts_start m_interrupts_size { + VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address + * (RESET,+FIRST) + } +} + +LR_m_veneer_table m_veneer_table_start m_veneer_table_size { + ER_m_veneer_table m_veneer_table_start m_veneer_table_size {; veneer table + *(Veneer$$CMSE) + } +} + +LR_m_usb_bdt m_usb_sram_start usb_bdt_size { + ER_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size { + * (m_usb_bdt) + } +} + +LR_m_usb_ram (m_usb_sram_start + usb_bdt_size) (m_usb_sram_size - usb_bdt_size) { + ER_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) { + * (m_usb_global) + } +} + +LR_CORE1_IMAGE m_core1_image_start { + CORE1_REGION m_core1_image_start m_core1_image_size { + *(M0CODE) + } +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55S69_cm33_core0_ram.scf b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55S69_cm33_core0_ram.scf new file mode 100644 index 000000000..c5a71fc76 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55S69_cm33_core0_ram.scf @@ -0,0 +1,104 @@ +#!armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -x c +/* +** ################################################################### +** Processors: LPC55S69JBD100_cm33_core0 +** LPC55S69JET98_cm33_core0 +** +** Compiler: Keil ARM C/C++ Compiler +** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.2 15 Aug 2018 +** Version: rev. 1.0, 2018-08-22 +** Build: b181008 +** +** Abstract: +** Linker file for the Keil ARM C/C++ Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + + +/* USB BDT size */ +#define usb_bdt_size 0x0 +/* Sizes */ +#if (defined(__stack_size__)) + #define Stack_Size __stack_size__ +#else + #define Stack_Size 0x0400 +#endif + +#if (defined(__heap_size__)) + #define Heap_Size __heap_size__ +#else + #define Heap_Size 0x0400 +#endif + +#define m_interrupts_start 0x04000000 +#define m_interrupts_size 0x00000200 + +#define m_text_start 0x04000200 +#define m_text_size 0x00007E00 + +#define m_core1_image_start 0x20033000 +#define m_core1_image_size 0x00008800 + +#if (defined(__use_shmem__)) + #define m_data_start 0x20000000 + #define m_data_size 0x00031800 + #define m_rpmsg_sh_mem_start 0x20031800 + #define m_rpmsg_sh_mem_size 0x00001800 +#else + #define m_data_start 0x20000000 + #define m_data_size 0x00033000 +#endif + +#define m_usb_sram_start 0x40100000 +#define m_usb_sram_size 0x00004000 + + +LR_m_text m_interrupts_start m_interrupts_size+m_text_size { ; load region size_region + + VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address + * (RESET,+FIRST) + } + + ER_m_text m_text_start FIXED m_text_size { ; load address = execution address + * (InRoot$$Sections) + * (+RO) + } + +#if (defined(__use_shmem__)) + RPMSG_SH_MEM m_rpmsg_sh_mem_start UNINIT m_rpmsg_sh_mem_size { ; Shared memory used by RPMSG + * (rpmsg_sh_mem_section) + } +#endif + + RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data + * (+RW +ZI) + } + ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up + } + ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down + } + + RW_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size { + * (m_usb_bdt) + } + + RW_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) { + * (m_usb_global) + } +} + +LR_CORE1_IMAGE m_core1_image_start { + CORE1_REGION m_core1_image_start m_core1_image_size { + *(M0CODE) + } +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55S69_cm33_core1_flash.scf b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55S69_cm33_core1_flash.scf new file mode 100644 index 000000000..74e2a9384 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55S69_cm33_core1_flash.scf @@ -0,0 +1,90 @@ +#!armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -x c +/* +** ################################################################### +** Processors: LPC55S69JBD100_cm33_core1 +** LPC55S69JET98_cm33_core1 +** +** Compiler: Keil ARM C/C++ Compiler +** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.2 15 Aug 2018 +** Version: rev. 1.0, 2018-08-22 +** Build: b181008 +** +** Abstract: +** Linker file for the Keil ARM C/C++ Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + + +/* USB BDT size */ +#define usb_bdt_size 0x0 +/* Sizes */ +#if (defined(__stack_size__)) + #define Stack_Size __stack_size__ +#else + #define Stack_Size 0x0400 +#endif + +#if (defined(__heap_size__)) + #define Heap_Size __heap_size__ +#else + #define Heap_Size 0x0400 +#endif + +#define m_interrupts_start 0x00072000 +#define m_interrupts_size 0x00000200 + +#define m_text_start 0x00072200 +#define m_text_size 0x00025E00 + + +#define m_data_start 0x20033000 +#define m_data_size 0x00011000 + +#if (defined(__use_shmem__)) + #define m_rpmsg_sh_mem_start 0x20031800 + #define m_rpmsg_sh_mem_size 0x00001800 +#endif + +#define m_usb_sram_start 0x40100000 +#define m_usb_sram_size 0x00004000 + + +LR_m_text m_interrupts_start m_interrupts_size+m_text_size { ; load region size_region + + VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address + * (RESET,+FIRST) + } + + ER_m_text m_text_start FIXED m_text_size { ; load address = execution address + * (InRoot$$Sections) + * (+RO) + } + + + RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data + * (+RW +ZI) + } + ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up + } + ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down + } + + RW_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size { + * (m_usb_bdt) + } + + RW_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) { + * (m_usb_global) + } +} + diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55S69_cm33_core1_ram.scf b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55S69_cm33_core1_ram.scf new file mode 100644 index 000000000..73393e3d6 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55S69_cm33_core1_ram.scf @@ -0,0 +1,95 @@ +#!armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -x c +/* +** ################################################################### +** Processors: LPC55S69JBD100_cm33_core1 +** LPC55S69JET98_cm33_core1 +** +** Compiler: Keil ARM C/C++ Compiler +** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.2 15 Aug 2018 +** Version: rev. 1.0, 2018-08-22 +** Build: b181008 +** +** Abstract: +** Linker file for the Keil ARM C/C++ Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + + +/* USB BDT size */ +#define usb_bdt_size 0x0 +/* Sizes */ +#if (defined(__stack_size__)) + #define Stack_Size __stack_size__ +#else + #define Stack_Size 0x0400 +#endif + +#if (defined(__heap_size__)) + #define Heap_Size __heap_size__ +#else + #define Heap_Size 0x0400 +#endif + +#define m_interrupts_start 0x20033000 +#define m_interrupts_size 0x00000200 + +#define m_text_start 0x20033200 +#define m_text_size 0x0000B600 + + +#define m_data_start 0x2003E800 +#define m_data_size 0x00005800 + +#if (defined(__use_shmem__)) + #define m_rpmsg_sh_mem_start 0x20031800 + #define m_rpmsg_sh_mem_size 0x00001800 +#endif + +#define m_usb_sram_start 0x40100000 +#define m_usb_sram_size 0x00004000 + + +LR_m_text m_interrupts_start m_interrupts_size+m_text_size { ; load region size_region + + VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address + * (RESET,+FIRST) + } + + ER_m_text m_text_start FIXED m_text_size { ; load address = execution address + * (InRoot$$Sections) + * (+RO) + } + + + RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data + * (+RW +ZI) + } + ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up + } + ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down + } + + RW_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size { + * (m_usb_bdt) + } + + RW_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) { + * (m_usb_global) + } +#if (defined(__use_shmem__)) + RPMSG_SH_MEM m_rpmsg_sh_mem_start UNINIT m_rpmsg_sh_mem_size { ; Shared memory used by RPMSG + * (rpmsg_sh_mem_section) + } +#endif +} + diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55S69_cm33_core1_ram_s.scf b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55S69_cm33_core1_ram_s.scf new file mode 100644 index 000000000..a9f6e92dc --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55S69_cm33_core1_ram_s.scf @@ -0,0 +1,95 @@ +#!armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -x c +/* +** ################################################################### +** Processors: LPC55S69JBD100_cm33_core1 +** LPC55S69JET98_cm33_core1 +** +** Compiler: Keil ARM C/C++ Compiler +** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.2 15 Aug 2018 +** Version: rev. 1.0, 2018-08-22 +** Build: b181008 +** +** Abstract: +** Linker file for the Keil ARM C/C++ Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + + +/* USB BDT size */ +#define usb_bdt_size 0x0 +/* Sizes */ +#if (defined(__stack_size__)) + #define Stack_Size __stack_size__ +#else + #define Stack_Size 0x0400 +#endif + +#if (defined(__heap_size__)) + #define Heap_Size __heap_size__ +#else + #define Heap_Size 0x0400 +#endif + +#define m_interrupts_start 0x30033000 +#define m_interrupts_size 0x00000200 + +#define m_text_start 0x30033200 +#define m_text_size 0x0000B600 + + +#define m_data_start 0x3003E800 +#define m_data_size 0x00005800 + +#if (defined(__use_shmem__)) + #define m_rpmsg_sh_mem_start 0x30031800 + #define m_rpmsg_sh_mem_size 0x00001800 +#endif + +#define m_usb_sram_start 0x50100000 +#define m_usb_sram_size 0x00004000 + + +LR_m_text m_interrupts_start m_interrupts_size+m_text_size { ; load region size_region + + VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address + * (RESET,+FIRST) + } + + ER_m_text m_text_start FIXED m_text_size { ; load address = execution address + * (InRoot$$Sections) + * (+RO) + } + + + RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data + * (+RW +ZI) + } + ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up + } + ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down + } + + RW_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size { + * (m_usb_bdt) + } + + RW_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) { + * (m_usb_global) + } +#if (defined(__use_shmem__)) + RPMSG_SH_MEM m_rpmsg_sh_mem_start UNINIT m_rpmsg_sh_mem_size { ; Shared memory used by RPMSG + * (rpmsg_sh_mem_section) + } +#endif +} + diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55XX_640.FLM b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55XX_640.FLM new file mode 100644 index 0000000000000000000000000000000000000000..9313a011e436135bc1ab9b95ce56ab8ca48321ed GIT binary patch literal 23308 zcmeHP33wdUeSfpNvxip4%90N(*;$(f8*IyxFN`rpw=G+?Wl25=Qr4^0NLp*PT6R~m zO#`@Kj`Smx7)WV=#Ly&7nl>1UQ%W#bfslrP-B2J6P{>DU5|YLU1L8>3-|x+_qm@h` z{nGDi>#=9%{r=bczyEvlu9?;44b6>;q6qVFi21@qA8r?7^$u`cLR}_;g1jlBSnNAo zJ>n7%j|frw&MT3oQ4y#f5y8iS#hiyn_XQpv-H&r$@!EGjxLDa){f=wr*c@`78hKe! zc5Xg?u-Y+4Nmh^KOB?Iz#qr@$F@MHGN^sv15lpV7eVx}h5|6H{f8rf&shG3*#EiM( z_?217hxQ!~9#7Uxl-+zn)QaN?OEP)5pmFUxV;7e;dTXK4Sa57|ovKE0ylwRG+v0Na zZ+QrIhN>D_&UN*38yA2ZH*6-496Fres5Zh{b#dcdaDMTgnD2e)jQaVFhmPz!oJWr3 z8B4g^@K8|aq*W-()k~=ETuB2&qq%wCD)U}#NHv-!F~&S#$j-84AAszAIkLW8lzlCzN8rslW(58TvUgI}R{o22$?_Yrk6W_;4B6`_ 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a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/startup_LPC55S69_cm33_core0.s b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/startup_LPC55S69_cm33_core0.s new file mode 100644 index 000000000..9bd615d07 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/startup_LPC55S69_cm33_core0.s @@ -0,0 +1,732 @@ +;/***************************************************************************** +; * @file: startup_LPC55S69_cm33_core0.s +; * @purpose: CMSIS Cortex-M33 Core Device Startup File for the +; * LPC55S69_cm33_core0 +; * @version: 1.1 +; * @date: 2019-5-16 +; * +; * Copyright 1997-2016 Freescale Semiconductor, Inc. +; * Copyright 2016-2019 NXP +; * All rights reserved. +; * +; * SPDX-License-Identifier: BSD-3-Clause +; * +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; * +; *****************************************************************************/ + + + PRESERVE8 + THUMB + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| + +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler + DCD HardFault_Handler + DCD MemManage_Handler + DCD BusFault_Handler + DCD UsageFault_Handler +__vector_table_0x1c + DCD SecureFault_Handler + DCD 0 + DCD 0 ; Enhanced image marker, set to 0x0 for legacy boot + DCD 0 ; Pointer to enhanced boot block, set to 0x0 for legacy boot + DCD SVC_Handler + DCD DebugMon_Handler + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External Interrupts + DCD WDT_BOD_IRQHandler ; Windowed watchdog timer, Brownout detect, Flash interrupt + DCD DMA0_IRQHandler ; DMA0 controller + DCD GINT0_IRQHandler ; GPIO group 0 + DCD GINT1_IRQHandler ; GPIO group 1 + DCD PIN_INT0_IRQHandler ; Pin interrupt 0 or pattern match engine slice 0 + DCD PIN_INT1_IRQHandler ; Pin interrupt 1or pattern match engine slice 1 + DCD PIN_INT2_IRQHandler ; Pin interrupt 2 or pattern match engine slice 2 + DCD PIN_INT3_IRQHandler ; Pin interrupt 3 or pattern match engine slice 3 + DCD UTICK0_IRQHandler ; Micro-tick Timer + DCD MRT0_IRQHandler ; Multi-rate timer + DCD CTIMER0_IRQHandler ; Standard counter/timer CTIMER0 + DCD CTIMER1_IRQHandler ; Standard counter/timer CTIMER1 + DCD SCT0_IRQHandler ; SCTimer/PWM + DCD CTIMER3_IRQHandler ; Standard counter/timer CTIMER3 + DCD FLEXCOMM0_IRQHandler ; Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) + DCD FLEXCOMM1_IRQHandler ; Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) + DCD FLEXCOMM2_IRQHandler ; Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) + DCD FLEXCOMM3_IRQHandler ; Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) + DCD FLEXCOMM4_IRQHandler ; Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) + DCD FLEXCOMM5_IRQHandler ; Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) + DCD FLEXCOMM6_IRQHandler ; Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) + DCD FLEXCOMM7_IRQHandler ; Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) + DCD ADC0_IRQHandler ; ADC0 + DCD Reserved39_IRQHandler ; Reserved interrupt + DCD ACMP_IRQHandler ; ACMP interrupts + DCD Reserved41_IRQHandler ; Reserved interrupt + DCD Reserved42_IRQHandler ; Reserved interrupt + DCD USB0_NEEDCLK_IRQHandler ; USB Activity Wake-up Interrupt + DCD USB0_IRQHandler ; USB device + DCD RTC_IRQHandler ; RTC alarm and wake-up interrupts + DCD Reserved46_IRQHandler ; Reserved interrupt + DCD MAILBOX_IRQHandler ; WAKEUP,Mailbox interrupt (present on selected devices) + DCD PIN_INT4_IRQHandler ; Pin interrupt 4 or pattern match engine slice 4 int + DCD PIN_INT5_IRQHandler ; Pin interrupt 5 or pattern match engine slice 5 int + DCD PIN_INT6_IRQHandler ; Pin interrupt 6 or pattern match engine slice 6 int + DCD PIN_INT7_IRQHandler ; Pin interrupt 7 or pattern match engine slice 7 int + DCD CTIMER2_IRQHandler ; Standard counter/timer CTIMER2 + DCD CTIMER4_IRQHandler ; Standard counter/timer CTIMER4 + DCD OS_EVENT_IRQHandler ; OSEVTIMER0 and OSEVTIMER0_WAKEUP interrupts + DCD Reserved55_IRQHandler ; Reserved interrupt + DCD Reserved56_IRQHandler ; Reserved interrupt + DCD Reserved57_IRQHandler ; Reserved interrupt + DCD SDIO_IRQHandler ; SD/MMC + DCD Reserved59_IRQHandler ; Reserved interrupt + DCD Reserved60_IRQHandler ; Reserved interrupt + DCD Reserved61_IRQHandler ; Reserved interrupt + DCD USB1_UTMI_IRQHandler ; USB1_UTMI + DCD USB1_IRQHandler ; USB1 interrupt + DCD USB1_NEEDCLK_IRQHandler ; USB1 activity + DCD SEC_HYPERVISOR_CALL_IRQHandler ; SEC_HYPERVISOR_CALL interrupt + DCD SEC_GPIO_INT0_IRQ0_IRQHandler ; SEC_GPIO_INT0_IRQ0 interrupt + DCD SEC_GPIO_INT0_IRQ1_IRQHandler ; SEC_GPIO_INT0_IRQ1 interrupt + DCD PLU_IRQHandler ; PLU interrupt + DCD SEC_VIO_IRQHandler ; SEC_VIO interrupt + DCD HASHCRYPT_IRQHandler ; HASHCRYPT interrupt + DCD CASER_IRQHandler ; CASPER interrupt + DCD PUF_IRQHandler ; PUF interrupt + DCD PQ_IRQHandler ; PQ interrupt + DCD DMA1_IRQHandler ; DMA1 interrupt + DCD FLEXCOMM8_IRQHandler ; Flexcomm Interface 8 (SPI, , FLEXCOMM) + + + AREA |.text|, CODE, READONLY + +; Reset Handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Base| + + CPSID I ; Mask interrupts + LDR R0, =|Image$$ARM_LIB_STACK$$ZI$$Base| + MSR MSPLIM, R0 + LDR R0, =SystemInit + BLX R0 + CPSIE I ; Unmask interrupts + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler \ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +MemManage_Handler PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP + +BusFault_Handler PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP + +UsageFault_Handler PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP + +SecureFault_Handler PROC + EXPORT SecureFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +DebugMon_Handler PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +WDT_BOD_IRQHandler\ + PROC + EXPORT WDT_BOD_IRQHandler [WEAK] + LDR R0, =WDT_BOD_DriverIRQHandler + BX R0 + ENDP + +DMA0_IRQHandler\ + PROC + EXPORT DMA0_IRQHandler [WEAK] + LDR R0, =DMA0_DriverIRQHandler + BX R0 + ENDP + +GINT0_IRQHandler\ + PROC + EXPORT GINT0_IRQHandler [WEAK] + LDR R0, =GINT0_DriverIRQHandler + BX R0 + ENDP + +GINT1_IRQHandler\ + PROC + EXPORT GINT1_IRQHandler [WEAK] + LDR R0, =GINT1_DriverIRQHandler + BX R0 + ENDP + +PIN_INT0_IRQHandler\ + PROC + EXPORT PIN_INT0_IRQHandler [WEAK] + LDR R0, =PIN_INT0_DriverIRQHandler + BX R0 + ENDP + +PIN_INT1_IRQHandler\ + PROC + EXPORT PIN_INT1_IRQHandler [WEAK] + LDR R0, =PIN_INT1_DriverIRQHandler + BX R0 + ENDP + +PIN_INT2_IRQHandler\ + PROC + EXPORT PIN_INT2_IRQHandler [WEAK] + LDR R0, =PIN_INT2_DriverIRQHandler + BX R0 + ENDP + +PIN_INT3_IRQHandler\ + PROC + EXPORT PIN_INT3_IRQHandler [WEAK] + LDR R0, =PIN_INT3_DriverIRQHandler + BX R0 + ENDP + +UTICK0_IRQHandler\ + PROC + EXPORT UTICK0_IRQHandler [WEAK] + LDR R0, =UTICK0_DriverIRQHandler + BX R0 + ENDP + +MRT0_IRQHandler\ + PROC + EXPORT MRT0_IRQHandler [WEAK] + LDR R0, =MRT0_DriverIRQHandler + BX R0 + ENDP + +CTIMER0_IRQHandler\ + PROC + EXPORT CTIMER0_IRQHandler [WEAK] + LDR R0, =CTIMER0_DriverIRQHandler + BX R0 + ENDP + +CTIMER1_IRQHandler\ + PROC + EXPORT CTIMER1_IRQHandler [WEAK] + LDR R0, =CTIMER1_DriverIRQHandler + BX R0 + ENDP + +SCT0_IRQHandler\ + PROC + EXPORT SCT0_IRQHandler [WEAK] + LDR R0, =SCT0_DriverIRQHandler + BX R0 + ENDP + +CTIMER3_IRQHandler\ + PROC + EXPORT CTIMER3_IRQHandler [WEAK] + LDR R0, =CTIMER3_DriverIRQHandler + BX R0 + ENDP + +FLEXCOMM0_IRQHandler\ + PROC + EXPORT FLEXCOMM0_IRQHandler [WEAK] + LDR R0, =FLEXCOMM0_DriverIRQHandler + BX R0 + ENDP + +FLEXCOMM1_IRQHandler\ + PROC + EXPORT FLEXCOMM1_IRQHandler [WEAK] + LDR R0, =FLEXCOMM1_DriverIRQHandler + BX R0 + ENDP + +FLEXCOMM2_IRQHandler\ + PROC + EXPORT FLEXCOMM2_IRQHandler [WEAK] + LDR R0, =FLEXCOMM2_DriverIRQHandler + BX R0 + ENDP + +FLEXCOMM3_IRQHandler\ + PROC + EXPORT FLEXCOMM3_IRQHandler [WEAK] + LDR R0, =FLEXCOMM3_DriverIRQHandler + BX R0 + ENDP + +FLEXCOMM4_IRQHandler\ + PROC + EXPORT FLEXCOMM4_IRQHandler [WEAK] + LDR R0, =FLEXCOMM4_DriverIRQHandler + BX R0 + ENDP + +FLEXCOMM5_IRQHandler\ + PROC + EXPORT FLEXCOMM5_IRQHandler [WEAK] + LDR R0, =FLEXCOMM5_DriverIRQHandler + BX R0 + ENDP + +FLEXCOMM6_IRQHandler\ + PROC + EXPORT FLEXCOMM6_IRQHandler [WEAK] + LDR R0, =FLEXCOMM6_DriverIRQHandler + BX R0 + ENDP + +FLEXCOMM7_IRQHandler\ + PROC + EXPORT FLEXCOMM7_IRQHandler [WEAK] + LDR R0, =FLEXCOMM7_DriverIRQHandler + BX R0 + ENDP + +ADC0_IRQHandler\ + PROC + EXPORT ADC0_IRQHandler [WEAK] + LDR R0, =ADC0_DriverIRQHandler + BX R0 + ENDP + +Reserved39_IRQHandler\ + PROC + EXPORT Reserved39_IRQHandler [WEAK] + LDR R0, =Reserved39_DriverIRQHandler + BX R0 + ENDP + +ACMP_IRQHandler\ + PROC + EXPORT ACMP_IRQHandler [WEAK] + LDR R0, =ACMP_DriverIRQHandler + BX R0 + ENDP + +Reserved41_IRQHandler\ + PROC + EXPORT Reserved41_IRQHandler [WEAK] + LDR R0, =Reserved41_DriverIRQHandler + BX R0 + ENDP + +Reserved42_IRQHandler\ + PROC + EXPORT Reserved42_IRQHandler [WEAK] + LDR R0, =Reserved42_DriverIRQHandler + BX R0 + ENDP + +USB0_NEEDCLK_IRQHandler\ + PROC + EXPORT USB0_NEEDCLK_IRQHandler [WEAK] + LDR R0, =USB0_NEEDCLK_DriverIRQHandler + BX R0 + ENDP + +USB0_IRQHandler\ + PROC + EXPORT USB0_IRQHandler [WEAK] + LDR R0, =USB0_DriverIRQHandler + BX R0 + ENDP + +RTC_IRQHandler\ + PROC + EXPORT RTC_IRQHandler [WEAK] + LDR R0, =RTC_DriverIRQHandler + BX R0 + ENDP + +Reserved46_IRQHandler\ + PROC + EXPORT Reserved46_IRQHandler [WEAK] + LDR R0, =Reserved46_DriverIRQHandler + BX R0 + ENDP + +MAILBOX_IRQHandler\ + PROC + EXPORT MAILBOX_IRQHandler [WEAK] + LDR R0, =MAILBOX_DriverIRQHandler + BX R0 + ENDP + +PIN_INT4_IRQHandler\ + PROC + EXPORT PIN_INT4_IRQHandler [WEAK] + LDR R0, =PIN_INT4_DriverIRQHandler + BX R0 + ENDP + +PIN_INT5_IRQHandler\ + PROC + EXPORT PIN_INT5_IRQHandler [WEAK] + LDR R0, =PIN_INT5_DriverIRQHandler + BX R0 + ENDP + +PIN_INT6_IRQHandler\ + PROC + EXPORT PIN_INT6_IRQHandler [WEAK] + LDR R0, =PIN_INT6_DriverIRQHandler + BX R0 + ENDP + +PIN_INT7_IRQHandler\ + PROC + EXPORT PIN_INT7_IRQHandler [WEAK] + LDR R0, =PIN_INT7_DriverIRQHandler + BX R0 + ENDP + +CTIMER2_IRQHandler\ + PROC + EXPORT CTIMER2_IRQHandler [WEAK] + LDR R0, =CTIMER2_DriverIRQHandler + BX R0 + ENDP + +CTIMER4_IRQHandler\ + PROC + EXPORT CTIMER4_IRQHandler [WEAK] + LDR R0, =CTIMER4_DriverIRQHandler + BX R0 + ENDP + +OS_EVENT_IRQHandler\ + PROC + EXPORT OS_EVENT_IRQHandler [WEAK] + LDR R0, =OS_EVENT_DriverIRQHandler + BX R0 + ENDP + +Reserved55_IRQHandler\ + PROC + EXPORT Reserved55_IRQHandler [WEAK] + LDR R0, =Reserved55_DriverIRQHandler + BX R0 + ENDP + +Reserved56_IRQHandler\ + PROC + EXPORT Reserved56_IRQHandler [WEAK] + LDR R0, =Reserved56_DriverIRQHandler + BX R0 + ENDP + +Reserved57_IRQHandler\ + PROC + EXPORT Reserved57_IRQHandler [WEAK] + LDR R0, =Reserved57_DriverIRQHandler + BX R0 + ENDP + +SDIO_IRQHandler\ + PROC + EXPORT SDIO_IRQHandler [WEAK] + LDR R0, =SDIO_DriverIRQHandler + BX R0 + ENDP + +Reserved59_IRQHandler\ + PROC + EXPORT Reserved59_IRQHandler [WEAK] + LDR R0, =Reserved59_DriverIRQHandler + BX R0 + ENDP + +Reserved60_IRQHandler\ + PROC + EXPORT Reserved60_IRQHandler [WEAK] + LDR R0, =Reserved60_DriverIRQHandler + BX R0 + ENDP + +Reserved61_IRQHandler\ + PROC + EXPORT Reserved61_IRQHandler [WEAK] + LDR R0, =Reserved61_DriverIRQHandler + BX R0 + ENDP + +USB1_UTMI_IRQHandler\ + PROC + EXPORT USB1_UTMI_IRQHandler [WEAK] + LDR R0, =USB1_UTMI_DriverIRQHandler + BX R0 + ENDP + +USB1_IRQHandler\ + PROC + EXPORT USB1_IRQHandler [WEAK] + LDR R0, =USB1_DriverIRQHandler + BX R0 + ENDP + +USB1_NEEDCLK_IRQHandler\ + PROC + EXPORT USB1_NEEDCLK_IRQHandler [WEAK] + LDR R0, =USB1_NEEDCLK_DriverIRQHandler + BX R0 + ENDP + +SEC_HYPERVISOR_CALL_IRQHandler\ + PROC + EXPORT SEC_HYPERVISOR_CALL_IRQHandler [WEAK] + LDR R0, =SEC_HYPERVISOR_CALL_DriverIRQHandler + BX R0 + ENDP + +SEC_GPIO_INT0_IRQ0_IRQHandler\ + PROC + EXPORT SEC_GPIO_INT0_IRQ0_IRQHandler [WEAK] + LDR R0, =SEC_GPIO_INT0_IRQ0_DriverIRQHandler + BX R0 + ENDP + +SEC_GPIO_INT0_IRQ1_IRQHandler\ + PROC + EXPORT SEC_GPIO_INT0_IRQ1_IRQHandler [WEAK] + LDR R0, =SEC_GPIO_INT0_IRQ1_DriverIRQHandler + BX R0 + ENDP + +PLU_IRQHandler\ + PROC + EXPORT PLU_IRQHandler [WEAK] + LDR R0, =PLU_DriverIRQHandler + BX R0 + ENDP + +SEC_VIO_IRQHandler\ + PROC + EXPORT SEC_VIO_IRQHandler [WEAK] + LDR R0, =SEC_VIO_DriverIRQHandler + BX R0 + ENDP + +HASHCRYPT_IRQHandler\ + PROC + EXPORT HASHCRYPT_IRQHandler [WEAK] + LDR R0, =HASHCRYPT_DriverIRQHandler + BX R0 + ENDP + +CASER_IRQHandler\ + PROC + EXPORT CASER_IRQHandler [WEAK] + LDR R0, =CASER_DriverIRQHandler + BX R0 + ENDP + +PUF_IRQHandler\ + PROC + EXPORT PUF_IRQHandler [WEAK] + LDR R0, =PUF_DriverIRQHandler + BX R0 + ENDP + +PQ_IRQHandler\ + PROC + EXPORT PQ_IRQHandler [WEAK] + LDR R0, =PQ_DriverIRQHandler + BX R0 + ENDP + +DMA1_IRQHandler\ + PROC + EXPORT DMA1_IRQHandler [WEAK] + LDR R0, =DMA1_DriverIRQHandler + BX R0 + ENDP + +FLEXCOMM8_IRQHandler\ + PROC + EXPORT FLEXCOMM8_IRQHandler [WEAK] + LDR R0, =FLEXCOMM8_DriverIRQHandler + BX R0 + ENDP + +Default_Handler PROC + EXPORT WDT_BOD_DriverIRQHandler [WEAK] + EXPORT DMA0_DriverIRQHandler [WEAK] + EXPORT GINT0_DriverIRQHandler [WEAK] + EXPORT GINT1_DriverIRQHandler [WEAK] + EXPORT PIN_INT0_DriverIRQHandler [WEAK] + EXPORT PIN_INT1_DriverIRQHandler [WEAK] + EXPORT PIN_INT2_DriverIRQHandler [WEAK] + EXPORT PIN_INT3_DriverIRQHandler [WEAK] + EXPORT UTICK0_DriverIRQHandler [WEAK] + EXPORT MRT0_DriverIRQHandler [WEAK] + EXPORT CTIMER0_DriverIRQHandler [WEAK] + EXPORT CTIMER1_DriverIRQHandler [WEAK] + EXPORT SCT0_DriverIRQHandler [WEAK] + EXPORT CTIMER3_DriverIRQHandler [WEAK] + EXPORT FLEXCOMM0_DriverIRQHandler [WEAK] + EXPORT FLEXCOMM1_DriverIRQHandler [WEAK] + EXPORT FLEXCOMM2_DriverIRQHandler [WEAK] + EXPORT FLEXCOMM3_DriverIRQHandler [WEAK] + EXPORT FLEXCOMM4_DriverIRQHandler [WEAK] + EXPORT FLEXCOMM5_DriverIRQHandler [WEAK] + EXPORT FLEXCOMM6_DriverIRQHandler [WEAK] + EXPORT FLEXCOMM7_DriverIRQHandler [WEAK] + EXPORT ADC0_DriverIRQHandler [WEAK] + EXPORT Reserved39_DriverIRQHandler [WEAK] + EXPORT ACMP_DriverIRQHandler [WEAK] + EXPORT Reserved41_DriverIRQHandler [WEAK] + EXPORT Reserved42_DriverIRQHandler [WEAK] + EXPORT USB0_NEEDCLK_DriverIRQHandler [WEAK] + EXPORT USB0_DriverIRQHandler [WEAK] + EXPORT RTC_DriverIRQHandler [WEAK] + EXPORT Reserved46_DriverIRQHandler [WEAK] + EXPORT MAILBOX_DriverIRQHandler [WEAK] + EXPORT PIN_INT4_DriverIRQHandler [WEAK] + EXPORT PIN_INT5_DriverIRQHandler [WEAK] + EXPORT PIN_INT6_DriverIRQHandler [WEAK] + EXPORT PIN_INT7_DriverIRQHandler [WEAK] + EXPORT CTIMER2_DriverIRQHandler [WEAK] + EXPORT CTIMER4_DriverIRQHandler [WEAK] + EXPORT OS_EVENT_DriverIRQHandler [WEAK] + EXPORT Reserved55_DriverIRQHandler [WEAK] + EXPORT Reserved56_DriverIRQHandler [WEAK] + EXPORT Reserved57_DriverIRQHandler [WEAK] + EXPORT SDIO_DriverIRQHandler [WEAK] + EXPORT Reserved59_DriverIRQHandler [WEAK] + EXPORT Reserved60_DriverIRQHandler [WEAK] + EXPORT Reserved61_DriverIRQHandler [WEAK] + EXPORT USB1_UTMI_DriverIRQHandler [WEAK] + EXPORT USB1_DriverIRQHandler [WEAK] + EXPORT USB1_NEEDCLK_DriverIRQHandler [WEAK] + EXPORT SEC_HYPERVISOR_CALL_DriverIRQHandler [WEAK] + EXPORT SEC_GPIO_INT0_IRQ0_DriverIRQHandler [WEAK] + EXPORT SEC_GPIO_INT0_IRQ1_DriverIRQHandler [WEAK] + EXPORT PLU_DriverIRQHandler [WEAK] + EXPORT SEC_VIO_DriverIRQHandler [WEAK] + EXPORT HASHCRYPT_DriverIRQHandler [WEAK] + EXPORT CASER_DriverIRQHandler [WEAK] + EXPORT PUF_DriverIRQHandler [WEAK] + EXPORT PQ_DriverIRQHandler [WEAK] + EXPORT DMA1_DriverIRQHandler [WEAK] + EXPORT FLEXCOMM8_DriverIRQHandler [WEAK] + +WDT_BOD_DriverIRQHandler +DMA0_DriverIRQHandler +GINT0_DriverIRQHandler +GINT1_DriverIRQHandler +PIN_INT0_DriverIRQHandler +PIN_INT1_DriverIRQHandler +PIN_INT2_DriverIRQHandler +PIN_INT3_DriverIRQHandler +UTICK0_DriverIRQHandler +MRT0_DriverIRQHandler +CTIMER0_DriverIRQHandler +CTIMER1_DriverIRQHandler +SCT0_DriverIRQHandler +CTIMER3_DriverIRQHandler +FLEXCOMM0_DriverIRQHandler +FLEXCOMM1_DriverIRQHandler +FLEXCOMM2_DriverIRQHandler +FLEXCOMM3_DriverIRQHandler +FLEXCOMM4_DriverIRQHandler +FLEXCOMM5_DriverIRQHandler +FLEXCOMM6_DriverIRQHandler +FLEXCOMM7_DriverIRQHandler +ADC0_DriverIRQHandler +Reserved39_DriverIRQHandler +ACMP_DriverIRQHandler +Reserved41_DriverIRQHandler +Reserved42_DriverIRQHandler +USB0_NEEDCLK_DriverIRQHandler +USB0_DriverIRQHandler +RTC_DriverIRQHandler +Reserved46_DriverIRQHandler +MAILBOX_DriverIRQHandler +PIN_INT4_DriverIRQHandler +PIN_INT5_DriverIRQHandler +PIN_INT6_DriverIRQHandler +PIN_INT7_DriverIRQHandler +CTIMER2_DriverIRQHandler +CTIMER4_DriverIRQHandler +OS_EVENT_DriverIRQHandler +Reserved55_DriverIRQHandler +Reserved56_DriverIRQHandler +Reserved57_DriverIRQHandler +SDIO_DriverIRQHandler +Reserved59_DriverIRQHandler +Reserved60_DriverIRQHandler +Reserved61_DriverIRQHandler +USB1_UTMI_DriverIRQHandler +USB1_DriverIRQHandler +USB1_NEEDCLK_DriverIRQHandler +SEC_HYPERVISOR_CALL_DriverIRQHandler +SEC_GPIO_INT0_IRQ0_DriverIRQHandler +SEC_GPIO_INT0_IRQ1_DriverIRQHandler +PLU_DriverIRQHandler +SEC_VIO_DriverIRQHandler +HASHCRYPT_DriverIRQHandler +CASER_DriverIRQHandler +PUF_DriverIRQHandler +PQ_DriverIRQHandler +DMA1_DriverIRQHandler +FLEXCOMM8_DriverIRQHandler + + B . + + ENDP + + + ALIGN + + + END + diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/startup_LPC55S69_cm33_core0_ns.s b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/startup_LPC55S69_cm33_core0_ns.s new file mode 100644 index 000000000..575e0dda6 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/startup_LPC55S69_cm33_core0_ns.s @@ -0,0 +1,732 @@ +;/***************************************************************************** +; * @file: startup_LPC55S69_cm33_core0.s +; * @purpose: CMSIS Cortex-M33 Core Device Startup File for the +; * LPC55S69_cm33_core0 +; * @version: 1.1 +; * @date: 2019-5-16 +; * +; * Copyright 1997-2016 Freescale Semiconductor, Inc. +; * Copyright 2016-2019 NXP +; * All rights reserved. +; * +; * SPDX-License-Identifier: BSD-3-Clause +; * +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; * +; *****************************************************************************/ + + + PRESERVE8 + THUMB + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| + +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler + DCD HardFault_Handler + DCD MemManage_Handler + DCD BusFault_Handler + DCD UsageFault_Handler +__vector_table_0x1c + DCD SecureFault_Handler + DCD 0 + DCD 0 ; Enhanced image marker, set to 0x0 for legacy boot + DCD 0 ; Pointer to enhanced boot block, set to 0x0 for legacy boot + DCD SVC_Handler + DCD DebugMon_Handler + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External Interrupts + DCD WDT_BOD_IRQHandler ; Windowed watchdog timer, Brownout detect, Flash interrupt + DCD DMA0_IRQHandler ; DMA0 controller + DCD GINT0_IRQHandler ; GPIO group 0 + DCD GINT1_IRQHandler ; GPIO group 1 + DCD PIN_INT0_IRQHandler ; Pin interrupt 0 or pattern match engine slice 0 + DCD PIN_INT1_IRQHandler ; Pin interrupt 1or pattern match engine slice 1 + DCD PIN_INT2_IRQHandler ; Pin interrupt 2 or pattern match engine slice 2 + DCD PIN_INT3_IRQHandler ; Pin interrupt 3 or pattern match engine slice 3 + DCD UTICK0_IRQHandler ; Micro-tick Timer + DCD MRT0_IRQHandler ; Multi-rate timer + DCD CTIMER0_IRQHandler ; Standard counter/timer CTIMER0 + DCD CTIMER1_IRQHandler ; Standard counter/timer CTIMER1 + DCD SCT0_IRQHandler ; SCTimer/PWM + DCD CTIMER3_IRQHandler ; Standard counter/timer CTIMER3 + DCD FLEXCOMM0_IRQHandler ; Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) + DCD FLEXCOMM1_IRQHandler ; Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) + DCD FLEXCOMM2_IRQHandler ; Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) + DCD FLEXCOMM3_IRQHandler ; Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) + DCD FLEXCOMM4_IRQHandler ; Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) + DCD FLEXCOMM5_IRQHandler ; Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) + DCD FLEXCOMM6_IRQHandler ; Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) + DCD FLEXCOMM7_IRQHandler ; Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) + DCD ADC0_IRQHandler ; ADC0 + DCD Reserved39_IRQHandler ; Reserved interrupt + DCD ACMP_IRQHandler ; ACMP interrupts + DCD Reserved41_IRQHandler ; Reserved interrupt + DCD Reserved42_IRQHandler ; Reserved interrupt + DCD USB0_NEEDCLK_IRQHandler ; USB Activity Wake-up Interrupt + DCD USB0_IRQHandler ; USB device + DCD RTC_IRQHandler ; RTC alarm and wake-up interrupts + DCD Reserved46_IRQHandler ; Reserved interrupt + DCD MAILBOX_IRQHandler ; WAKEUP,Mailbox interrupt (present on selected devices) + DCD PIN_INT4_IRQHandler ; Pin interrupt 4 or pattern match engine slice 4 int + DCD PIN_INT5_IRQHandler ; Pin interrupt 5 or pattern match engine slice 5 int + DCD PIN_INT6_IRQHandler ; Pin interrupt 6 or pattern match engine slice 6 int + DCD PIN_INT7_IRQHandler ; Pin interrupt 7 or pattern match engine slice 7 int + DCD CTIMER2_IRQHandler ; Standard counter/timer CTIMER2 + DCD CTIMER4_IRQHandler ; Standard counter/timer CTIMER4 + DCD OS_EVENT_IRQHandler ; OSEVTIMER0 and OSEVTIMER0_WAKEUP interrupts + DCD Reserved55_IRQHandler ; Reserved interrupt + DCD Reserved56_IRQHandler ; Reserved interrupt + DCD Reserved57_IRQHandler ; Reserved interrupt + DCD SDIO_IRQHandler ; SD/MMC + DCD Reserved59_IRQHandler ; Reserved interrupt + DCD Reserved60_IRQHandler ; Reserved interrupt + DCD Reserved61_IRQHandler ; Reserved interrupt + DCD USB1_UTMI_IRQHandler ; USB1_UTMI + DCD USB1_IRQHandler ; USB1 interrupt + DCD USB1_NEEDCLK_IRQHandler ; USB1 activity + DCD SEC_HYPERVISOR_CALL_IRQHandler ; SEC_HYPERVISOR_CALL interrupt + DCD SEC_GPIO_INT0_IRQ0_IRQHandler ; SEC_GPIO_INT0_IRQ0 interrupt + DCD SEC_GPIO_INT0_IRQ1_IRQHandler ; SEC_GPIO_INT0_IRQ1 interrupt + DCD PLU_IRQHandler ; PLU interrupt + DCD SEC_VIO_IRQHandler ; SEC_VIO interrupt + DCD HASHCRYPT_IRQHandler ; HASHCRYPT interrupt + DCD CASER_IRQHandler ; CASPER interrupt + DCD PUF_IRQHandler ; PUF interrupt + DCD PQ_IRQHandler ; PQ interrupt + DCD DMA1_IRQHandler ; DMA1 interrupt + DCD FLEXCOMM8_IRQHandler ; Flexcomm Interface 8 (SPI, , FLEXCOMM) + + + AREA |.text|, CODE, READONLY + +; Reset Handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Base| + + CPSID I ; Mask interrupts + LDR R0, =|Image$$ARM_LIB_STACK$$ZI$$Base| + MSR MSPLIM, R0 + ;LDR R0, =SystemInit + ;BLX R0 + CPSIE I ; Unmask interrupts + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler \ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +MemManage_Handler PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP + +BusFault_Handler PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP + +UsageFault_Handler PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP + +SecureFault_Handler PROC + EXPORT SecureFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +DebugMon_Handler PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +WDT_BOD_IRQHandler\ + PROC + EXPORT WDT_BOD_IRQHandler [WEAK] + LDR R0, =WDT_BOD_DriverIRQHandler + BX R0 + ENDP + +DMA0_IRQHandler\ + PROC + EXPORT DMA0_IRQHandler [WEAK] + LDR R0, =DMA0_DriverIRQHandler + BX R0 + ENDP + +GINT0_IRQHandler\ + PROC + EXPORT GINT0_IRQHandler [WEAK] + LDR R0, =GINT0_DriverIRQHandler + BX R0 + ENDP + +GINT1_IRQHandler\ + PROC + EXPORT GINT1_IRQHandler [WEAK] + LDR R0, =GINT1_DriverIRQHandler + BX R0 + ENDP + +PIN_INT0_IRQHandler\ + PROC + EXPORT PIN_INT0_IRQHandler [WEAK] + LDR R0, =PIN_INT0_DriverIRQHandler + BX R0 + ENDP + +PIN_INT1_IRQHandler\ + PROC + EXPORT PIN_INT1_IRQHandler [WEAK] + LDR R0, =PIN_INT1_DriverIRQHandler + BX R0 + ENDP + +PIN_INT2_IRQHandler\ + PROC + EXPORT PIN_INT2_IRQHandler [WEAK] + LDR R0, =PIN_INT2_DriverIRQHandler + BX R0 + ENDP + +PIN_INT3_IRQHandler\ + PROC + EXPORT PIN_INT3_IRQHandler [WEAK] + LDR R0, =PIN_INT3_DriverIRQHandler + BX R0 + ENDP + +UTICK0_IRQHandler\ + PROC + EXPORT UTICK0_IRQHandler [WEAK] + LDR R0, =UTICK0_DriverIRQHandler + BX R0 + ENDP + +MRT0_IRQHandler\ + PROC + EXPORT MRT0_IRQHandler [WEAK] + LDR R0, =MRT0_DriverIRQHandler + BX R0 + ENDP + +CTIMER0_IRQHandler\ + PROC + EXPORT CTIMER0_IRQHandler [WEAK] + LDR R0, =CTIMER0_DriverIRQHandler + BX R0 + ENDP + +CTIMER1_IRQHandler\ + PROC + EXPORT CTIMER1_IRQHandler [WEAK] + LDR R0, =CTIMER1_DriverIRQHandler + BX R0 + ENDP + +SCT0_IRQHandler\ + PROC + EXPORT SCT0_IRQHandler [WEAK] + LDR R0, =SCT0_DriverIRQHandler + BX R0 + ENDP + +CTIMER3_IRQHandler\ + PROC + EXPORT CTIMER3_IRQHandler [WEAK] + LDR R0, =CTIMER3_DriverIRQHandler + BX R0 + ENDP + +FLEXCOMM0_IRQHandler\ + PROC + EXPORT FLEXCOMM0_IRQHandler [WEAK] + LDR R0, =FLEXCOMM0_DriverIRQHandler + BX R0 + ENDP + +FLEXCOMM1_IRQHandler\ + PROC + EXPORT FLEXCOMM1_IRQHandler [WEAK] + LDR R0, =FLEXCOMM1_DriverIRQHandler + BX R0 + ENDP + +FLEXCOMM2_IRQHandler\ + PROC + EXPORT FLEXCOMM2_IRQHandler [WEAK] + LDR R0, =FLEXCOMM2_DriverIRQHandler + BX R0 + ENDP + +FLEXCOMM3_IRQHandler\ + PROC + EXPORT FLEXCOMM3_IRQHandler [WEAK] + LDR R0, =FLEXCOMM3_DriverIRQHandler + BX R0 + ENDP + +FLEXCOMM4_IRQHandler\ + PROC + EXPORT FLEXCOMM4_IRQHandler [WEAK] + LDR R0, =FLEXCOMM4_DriverIRQHandler + BX R0 + ENDP + +FLEXCOMM5_IRQHandler\ + PROC + EXPORT FLEXCOMM5_IRQHandler [WEAK] + LDR R0, =FLEXCOMM5_DriverIRQHandler + BX R0 + ENDP + +FLEXCOMM6_IRQHandler\ + PROC + EXPORT FLEXCOMM6_IRQHandler [WEAK] + LDR R0, =FLEXCOMM6_DriverIRQHandler + BX R0 + ENDP + +FLEXCOMM7_IRQHandler\ + PROC + EXPORT FLEXCOMM7_IRQHandler [WEAK] + LDR R0, =FLEXCOMM7_DriverIRQHandler + BX R0 + ENDP + +ADC0_IRQHandler\ + PROC + EXPORT ADC0_IRQHandler [WEAK] + LDR R0, =ADC0_DriverIRQHandler + BX R0 + ENDP + +Reserved39_IRQHandler\ + PROC + EXPORT Reserved39_IRQHandler [WEAK] + LDR R0, =Reserved39_DriverIRQHandler + BX R0 + ENDP + +ACMP_IRQHandler\ + PROC + EXPORT ACMP_IRQHandler [WEAK] + LDR R0, =ACMP_DriverIRQHandler + BX R0 + ENDP + +Reserved41_IRQHandler\ + PROC + EXPORT Reserved41_IRQHandler [WEAK] + LDR R0, =Reserved41_DriverIRQHandler + BX R0 + ENDP + +Reserved42_IRQHandler\ + PROC + EXPORT Reserved42_IRQHandler [WEAK] + LDR R0, =Reserved42_DriverIRQHandler + BX R0 + ENDP + +USB0_NEEDCLK_IRQHandler\ + PROC + EXPORT USB0_NEEDCLK_IRQHandler [WEAK] + LDR R0, =USB0_NEEDCLK_DriverIRQHandler + BX R0 + ENDP + +USB0_IRQHandler\ + PROC + EXPORT USB0_IRQHandler [WEAK] + LDR R0, =USB0_DriverIRQHandler + BX R0 + ENDP + +RTC_IRQHandler\ + PROC + EXPORT RTC_IRQHandler [WEAK] + LDR R0, =RTC_DriverIRQHandler + BX R0 + ENDP + +Reserved46_IRQHandler\ + PROC + EXPORT Reserved46_IRQHandler [WEAK] + LDR R0, =Reserved46_DriverIRQHandler + BX R0 + ENDP + +MAILBOX_IRQHandler\ + PROC + EXPORT MAILBOX_IRQHandler [WEAK] + LDR R0, =MAILBOX_DriverIRQHandler + BX R0 + ENDP + +PIN_INT4_IRQHandler\ + PROC + EXPORT PIN_INT4_IRQHandler [WEAK] + LDR R0, =PIN_INT4_DriverIRQHandler + BX R0 + ENDP + +PIN_INT5_IRQHandler\ + PROC + EXPORT PIN_INT5_IRQHandler [WEAK] + LDR R0, =PIN_INT5_DriverIRQHandler + BX R0 + ENDP + +PIN_INT6_IRQHandler\ + PROC + EXPORT PIN_INT6_IRQHandler [WEAK] + LDR R0, =PIN_INT6_DriverIRQHandler + BX R0 + ENDP + +PIN_INT7_IRQHandler\ + PROC + EXPORT PIN_INT7_IRQHandler [WEAK] + LDR R0, =PIN_INT7_DriverIRQHandler + BX R0 + ENDP + +CTIMER2_IRQHandler\ + PROC + EXPORT CTIMER2_IRQHandler [WEAK] + LDR R0, =CTIMER2_DriverIRQHandler + BX R0 + ENDP + +CTIMER4_IRQHandler\ + PROC + EXPORT CTIMER4_IRQHandler [WEAK] + LDR R0, =CTIMER4_DriverIRQHandler + BX R0 + ENDP + +OS_EVENT_IRQHandler\ + PROC + EXPORT OS_EVENT_IRQHandler [WEAK] + LDR R0, =OS_EVENT_DriverIRQHandler + BX R0 + ENDP + +Reserved55_IRQHandler\ + PROC + EXPORT Reserved55_IRQHandler [WEAK] + LDR R0, =Reserved55_DriverIRQHandler + BX R0 + ENDP + +Reserved56_IRQHandler\ + PROC + EXPORT Reserved56_IRQHandler [WEAK] + LDR R0, =Reserved56_DriverIRQHandler + BX R0 + ENDP + +Reserved57_IRQHandler\ + PROC + EXPORT Reserved57_IRQHandler [WEAK] + LDR R0, =Reserved57_DriverIRQHandler + BX R0 + ENDP + +SDIO_IRQHandler\ + PROC + EXPORT SDIO_IRQHandler [WEAK] + LDR R0, =SDIO_DriverIRQHandler + BX R0 + ENDP + +Reserved59_IRQHandler\ + PROC + EXPORT Reserved59_IRQHandler [WEAK] + LDR R0, =Reserved59_DriverIRQHandler + BX R0 + ENDP + +Reserved60_IRQHandler\ + PROC + EXPORT Reserved60_IRQHandler [WEAK] + LDR R0, =Reserved60_DriverIRQHandler + BX R0 + ENDP + +Reserved61_IRQHandler\ + PROC + EXPORT Reserved61_IRQHandler [WEAK] + LDR R0, =Reserved61_DriverIRQHandler + BX R0 + ENDP + +USB1_UTMI_IRQHandler\ + PROC + EXPORT USB1_UTMI_IRQHandler [WEAK] + LDR R0, =USB1_UTMI_DriverIRQHandler + BX R0 + ENDP + +USB1_IRQHandler\ + PROC + EXPORT USB1_IRQHandler [WEAK] + LDR R0, =USB1_DriverIRQHandler + BX R0 + ENDP + +USB1_NEEDCLK_IRQHandler\ + PROC + EXPORT USB1_NEEDCLK_IRQHandler [WEAK] + LDR R0, =USB1_NEEDCLK_DriverIRQHandler + BX R0 + ENDP + +SEC_HYPERVISOR_CALL_IRQHandler\ + PROC + EXPORT SEC_HYPERVISOR_CALL_IRQHandler [WEAK] + LDR R0, =SEC_HYPERVISOR_CALL_DriverIRQHandler + BX R0 + ENDP + +SEC_GPIO_INT0_IRQ0_IRQHandler\ + PROC + EXPORT SEC_GPIO_INT0_IRQ0_IRQHandler [WEAK] + LDR R0, =SEC_GPIO_INT0_IRQ0_DriverIRQHandler + BX R0 + ENDP + +SEC_GPIO_INT0_IRQ1_IRQHandler\ + PROC + EXPORT SEC_GPIO_INT0_IRQ1_IRQHandler [WEAK] + LDR R0, =SEC_GPIO_INT0_IRQ1_DriverIRQHandler + BX R0 + ENDP + +PLU_IRQHandler\ + PROC + EXPORT PLU_IRQHandler [WEAK] + LDR R0, =PLU_DriverIRQHandler + BX R0 + ENDP + +SEC_VIO_IRQHandler\ + PROC + EXPORT SEC_VIO_IRQHandler [WEAK] + LDR R0, =SEC_VIO_DriverIRQHandler + BX R0 + ENDP + +HASHCRYPT_IRQHandler\ + PROC + EXPORT HASHCRYPT_IRQHandler [WEAK] + LDR R0, =HASHCRYPT_DriverIRQHandler + BX R0 + ENDP + +CASER_IRQHandler\ + PROC + EXPORT CASER_IRQHandler [WEAK] + LDR R0, =CASER_DriverIRQHandler + BX R0 + ENDP + +PUF_IRQHandler\ + PROC + EXPORT PUF_IRQHandler [WEAK] + LDR R0, =PUF_DriverIRQHandler + BX R0 + ENDP + +PQ_IRQHandler\ + PROC + EXPORT PQ_IRQHandler [WEAK] + LDR R0, =PQ_DriverIRQHandler + BX R0 + ENDP + +DMA1_IRQHandler\ + PROC + EXPORT DMA1_IRQHandler [WEAK] + LDR R0, =DMA1_DriverIRQHandler + BX R0 + ENDP + +FLEXCOMM8_IRQHandler\ + PROC + EXPORT FLEXCOMM8_IRQHandler [WEAK] + LDR R0, =FLEXCOMM8_DriverIRQHandler + BX R0 + ENDP + +Default_Handler PROC + EXPORT WDT_BOD_DriverIRQHandler [WEAK] + EXPORT DMA0_DriverIRQHandler [WEAK] + EXPORT GINT0_DriverIRQHandler [WEAK] + EXPORT GINT1_DriverIRQHandler [WEAK] + EXPORT PIN_INT0_DriverIRQHandler [WEAK] + EXPORT PIN_INT1_DriverIRQHandler [WEAK] + EXPORT PIN_INT2_DriverIRQHandler [WEAK] + EXPORT PIN_INT3_DriverIRQHandler [WEAK] + EXPORT UTICK0_DriverIRQHandler [WEAK] + EXPORT MRT0_DriverIRQHandler [WEAK] + EXPORT CTIMER0_DriverIRQHandler [WEAK] + EXPORT CTIMER1_DriverIRQHandler [WEAK] + EXPORT SCT0_DriverIRQHandler [WEAK] + EXPORT CTIMER3_DriverIRQHandler [WEAK] + EXPORT FLEXCOMM0_DriverIRQHandler [WEAK] + EXPORT FLEXCOMM1_DriverIRQHandler [WEAK] + EXPORT FLEXCOMM2_DriverIRQHandler [WEAK] + EXPORT FLEXCOMM3_DriverIRQHandler [WEAK] + EXPORT FLEXCOMM4_DriverIRQHandler [WEAK] + EXPORT FLEXCOMM5_DriverIRQHandler [WEAK] + EXPORT FLEXCOMM6_DriverIRQHandler [WEAK] + EXPORT FLEXCOMM7_DriverIRQHandler [WEAK] + EXPORT ADC0_DriverIRQHandler [WEAK] + EXPORT Reserved39_DriverIRQHandler [WEAK] + EXPORT ACMP_DriverIRQHandler [WEAK] + EXPORT Reserved41_DriverIRQHandler [WEAK] + EXPORT Reserved42_DriverIRQHandler [WEAK] + EXPORT USB0_NEEDCLK_DriverIRQHandler [WEAK] + EXPORT USB0_DriverIRQHandler [WEAK] + EXPORT RTC_DriverIRQHandler [WEAK] + EXPORT Reserved46_DriverIRQHandler [WEAK] + EXPORT MAILBOX_DriverIRQHandler [WEAK] + EXPORT PIN_INT4_DriverIRQHandler [WEAK] + EXPORT PIN_INT5_DriverIRQHandler [WEAK] + EXPORT PIN_INT6_DriverIRQHandler [WEAK] + EXPORT PIN_INT7_DriverIRQHandler [WEAK] + EXPORT CTIMER2_DriverIRQHandler [WEAK] + EXPORT CTIMER4_DriverIRQHandler [WEAK] + EXPORT OS_EVENT_DriverIRQHandler [WEAK] + EXPORT Reserved55_DriverIRQHandler [WEAK] + EXPORT Reserved56_DriverIRQHandler [WEAK] + EXPORT Reserved57_DriverIRQHandler [WEAK] + EXPORT SDIO_DriverIRQHandler [WEAK] + EXPORT Reserved59_DriverIRQHandler [WEAK] + EXPORT Reserved60_DriverIRQHandler [WEAK] + EXPORT Reserved61_DriverIRQHandler [WEAK] + EXPORT USB1_UTMI_DriverIRQHandler [WEAK] + EXPORT USB1_DriverIRQHandler [WEAK] + EXPORT USB1_NEEDCLK_DriverIRQHandler [WEAK] + EXPORT SEC_HYPERVISOR_CALL_DriverIRQHandler [WEAK] + EXPORT SEC_GPIO_INT0_IRQ0_DriverIRQHandler [WEAK] + EXPORT SEC_GPIO_INT0_IRQ1_DriverIRQHandler [WEAK] + EXPORT PLU_DriverIRQHandler [WEAK] + EXPORT SEC_VIO_DriverIRQHandler [WEAK] + EXPORT HASHCRYPT_DriverIRQHandler [WEAK] + EXPORT CASER_DriverIRQHandler [WEAK] + EXPORT PUF_DriverIRQHandler [WEAK] + EXPORT PQ_DriverIRQHandler [WEAK] + EXPORT DMA1_DriverIRQHandler [WEAK] + EXPORT FLEXCOMM8_DriverIRQHandler [WEAK] + +WDT_BOD_DriverIRQHandler +DMA0_DriverIRQHandler +GINT0_DriverIRQHandler +GINT1_DriverIRQHandler +PIN_INT0_DriverIRQHandler +PIN_INT1_DriverIRQHandler +PIN_INT2_DriverIRQHandler +PIN_INT3_DriverIRQHandler +UTICK0_DriverIRQHandler +MRT0_DriverIRQHandler +CTIMER0_DriverIRQHandler +CTIMER1_DriverIRQHandler +SCT0_DriverIRQHandler +CTIMER3_DriverIRQHandler +FLEXCOMM0_DriverIRQHandler +FLEXCOMM1_DriverIRQHandler +FLEXCOMM2_DriverIRQHandler +FLEXCOMM3_DriverIRQHandler +FLEXCOMM4_DriverIRQHandler +FLEXCOMM5_DriverIRQHandler +FLEXCOMM6_DriverIRQHandler +FLEXCOMM7_DriverIRQHandler +ADC0_DriverIRQHandler +Reserved39_DriverIRQHandler +ACMP_DriverIRQHandler +Reserved41_DriverIRQHandler +Reserved42_DriverIRQHandler +USB0_NEEDCLK_DriverIRQHandler +USB0_DriverIRQHandler +RTC_DriverIRQHandler +Reserved46_DriverIRQHandler +MAILBOX_DriverIRQHandler +PIN_INT4_DriverIRQHandler +PIN_INT5_DriverIRQHandler +PIN_INT6_DriverIRQHandler +PIN_INT7_DriverIRQHandler +CTIMER2_DriverIRQHandler +CTIMER4_DriverIRQHandler +OS_EVENT_DriverIRQHandler +Reserved55_DriverIRQHandler +Reserved56_DriverIRQHandler +Reserved57_DriverIRQHandler +SDIO_DriverIRQHandler +Reserved59_DriverIRQHandler +Reserved60_DriverIRQHandler +Reserved61_DriverIRQHandler +USB1_UTMI_DriverIRQHandler +USB1_DriverIRQHandler +USB1_NEEDCLK_DriverIRQHandler +SEC_HYPERVISOR_CALL_DriverIRQHandler +SEC_GPIO_INT0_IRQ0_DriverIRQHandler +SEC_GPIO_INT0_IRQ1_DriverIRQHandler +PLU_DriverIRQHandler +SEC_VIO_DriverIRQHandler +HASHCRYPT_DriverIRQHandler +CASER_DriverIRQHandler +PUF_DriverIRQHandler +PQ_DriverIRQHandler +DMA1_DriverIRQHandler +FLEXCOMM8_DriverIRQHandler + + B . + + ENDP + + + ALIGN + + + END + diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/startup_LPC55S69_cm33_core1.s b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/startup_LPC55S69_cm33_core1.s new file mode 100644 index 000000000..08696146b --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/startup_LPC55S69_cm33_core1.s @@ -0,0 +1,732 @@ +;/***************************************************************************** +; * @file: startup_LPC55S69_cm33_core1.s +; * @purpose: CMSIS Cortex-M33 Core Device Startup File for the +; * LPC55S69_cm33_core1 +; * @version: 1.1 +; * @date: 2019-5-16 +; * +; * Copyright 1997-2016 Freescale Semiconductor, Inc. +; * Copyright 2016-2019 NXP +; * All rights reserved. +; * +; * SPDX-License-Identifier: BSD-3-Clause +; * +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; * +; *****************************************************************************/ + + + PRESERVE8 + THUMB + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| + +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler + DCD HardFault_Handler + DCD MemManage_Handler + DCD BusFault_Handler + DCD UsageFault_Handler +__vector_table_0x1c + DCD SecureFault_Handler + DCD 0 + DCD 0 ; Enhanced image marker, set to 0x0 for legacy boot + DCD 0 ; Pointer to enhanced boot block, set to 0x0 for legacy boot + DCD SVC_Handler + DCD DebugMon_Handler + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External Interrupts + DCD WDT_BOD_IRQHandler ; Windowed watchdog timer, Brownout detect, Flash interrupt + DCD DMA0_IRQHandler ; DMA0 controller + DCD GINT0_IRQHandler ; GPIO group 0 + DCD GINT1_IRQHandler ; GPIO group 1 + DCD PIN_INT0_IRQHandler ; Pin interrupt 0 or pattern match engine slice 0 + DCD PIN_INT1_IRQHandler ; Pin interrupt 1or pattern match engine slice 1 + DCD PIN_INT2_IRQHandler ; Pin interrupt 2 or pattern match engine slice 2 + DCD PIN_INT3_IRQHandler ; Pin interrupt 3 or pattern match engine slice 3 + DCD UTICK0_IRQHandler ; Micro-tick Timer + DCD MRT0_IRQHandler ; Multi-rate timer + DCD CTIMER0_IRQHandler ; Standard counter/timer CTIMER0 + DCD CTIMER1_IRQHandler ; Standard counter/timer CTIMER1 + DCD SCT0_IRQHandler ; SCTimer/PWM + DCD CTIMER3_IRQHandler ; Standard counter/timer CTIMER3 + DCD FLEXCOMM0_IRQHandler ; Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) + DCD FLEXCOMM1_IRQHandler ; Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) + DCD FLEXCOMM2_IRQHandler ; Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) + DCD FLEXCOMM3_IRQHandler ; Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) + DCD FLEXCOMM4_IRQHandler ; Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) + DCD FLEXCOMM5_IRQHandler ; Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) + DCD FLEXCOMM6_IRQHandler ; Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) + DCD FLEXCOMM7_IRQHandler ; Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) + DCD ADC0_IRQHandler ; ADC0 + DCD Reserved39_IRQHandler ; Reserved interrupt + DCD ACMP_IRQHandler ; ACMP interrupts + DCD Reserved41_IRQHandler ; Reserved interrupt + DCD Reserved42_IRQHandler ; Reserved interrupt + DCD USB0_NEEDCLK_IRQHandler ; USB Activity Wake-up Interrupt + DCD USB0_IRQHandler ; USB device + DCD RTC_IRQHandler ; RTC alarm and wake-up interrupts + DCD Reserved46_IRQHandler ; Reserved interrupt + DCD MAILBOX_IRQHandler ; WAKEUP,Mailbox interrupt (present on selected devices) + DCD PIN_INT4_IRQHandler ; Pin interrupt 4 or pattern match engine slice 4 int + DCD PIN_INT5_IRQHandler ; Pin interrupt 5 or pattern match engine slice 5 int + DCD PIN_INT6_IRQHandler ; Pin interrupt 6 or pattern match engine slice 6 int + DCD PIN_INT7_IRQHandler ; Pin interrupt 7 or pattern match engine slice 7 int + DCD CTIMER2_IRQHandler ; Standard counter/timer CTIMER2 + DCD CTIMER4_IRQHandler ; Standard counter/timer CTIMER4 + DCD OS_EVENT_IRQHandler ; OSEVTIMER0 and OSEVTIMER0_WAKEUP interrupts + DCD Reserved55_IRQHandler ; Reserved interrupt + DCD Reserved56_IRQHandler ; Reserved interrupt + DCD Reserved57_IRQHandler ; Reserved interrupt + DCD SDIO_IRQHandler ; SD/MMC + DCD Reserved59_IRQHandler ; Reserved interrupt + DCD Reserved60_IRQHandler ; Reserved interrupt + DCD Reserved61_IRQHandler ; Reserved interrupt + DCD USB1_UTMI_IRQHandler ; USB1_UTMI + DCD USB1_IRQHandler ; USB1 interrupt + DCD USB1_NEEDCLK_IRQHandler ; USB1 activity + DCD SEC_HYPERVISOR_CALL_IRQHandler ; SEC_HYPERVISOR_CALL interrupt + DCD SEC_GPIO_INT0_IRQ0_IRQHandler ; SEC_GPIO_INT0_IRQ0 interrupt + DCD SEC_GPIO_INT0_IRQ1_IRQHandler ; SEC_GPIO_INT0_IRQ1 interrupt + DCD PLU_IRQHandler ; PLU interrupt + DCD SEC_VIO_IRQHandler ; SEC_VIO interrupt + DCD HASHCRYPT_IRQHandler ; HASHCRYPT interrupt + DCD CASER_IRQHandler ; CASPER interrupt + DCD PUF_IRQHandler ; PUF interrupt + DCD PQ_IRQHandler ; PQ interrupt + DCD DMA1_IRQHandler ; DMA1 interrupt + DCD FLEXCOMM8_IRQHandler ; Flexcomm Interface 8 (SPI, , FLEXCOMM) + + + AREA |.text|, CODE, READONLY + +; Reset Handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Base| + + CPSID I ; Mask interrupts + LDR R0, =|Image$$ARM_LIB_STACK$$ZI$$Base| + MSR MSPLIM, R0 + LDR R0, =SystemInit + BLX R0 + CPSIE I ; Unmask interrupts + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler \ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +MemManage_Handler PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP + +BusFault_Handler PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP + +UsageFault_Handler PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP + +SecureFault_Handler PROC + EXPORT SecureFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +DebugMon_Handler PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +WDT_BOD_IRQHandler\ + PROC + EXPORT WDT_BOD_IRQHandler [WEAK] + LDR R0, =WDT_BOD_DriverIRQHandler + BX R0 + ENDP + +DMA0_IRQHandler\ + PROC + EXPORT DMA0_IRQHandler [WEAK] + LDR R0, =DMA0_DriverIRQHandler + BX R0 + ENDP + +GINT0_IRQHandler\ + PROC + EXPORT GINT0_IRQHandler [WEAK] + LDR R0, =GINT0_DriverIRQHandler + BX R0 + ENDP + +GINT1_IRQHandler\ + PROC + EXPORT GINT1_IRQHandler [WEAK] + LDR R0, =GINT1_DriverIRQHandler + BX R0 + ENDP + +PIN_INT0_IRQHandler\ + PROC + EXPORT PIN_INT0_IRQHandler [WEAK] + LDR R0, =PIN_INT0_DriverIRQHandler + BX R0 + ENDP + +PIN_INT1_IRQHandler\ + PROC + EXPORT PIN_INT1_IRQHandler [WEAK] + LDR R0, =PIN_INT1_DriverIRQHandler + BX R0 + ENDP + +PIN_INT2_IRQHandler\ + PROC + EXPORT PIN_INT2_IRQHandler [WEAK] + LDR R0, =PIN_INT2_DriverIRQHandler + BX R0 + ENDP + +PIN_INT3_IRQHandler\ + PROC + EXPORT PIN_INT3_IRQHandler [WEAK] + LDR R0, =PIN_INT3_DriverIRQHandler + BX R0 + ENDP + +UTICK0_IRQHandler\ + PROC + EXPORT UTICK0_IRQHandler [WEAK] + LDR R0, =UTICK0_DriverIRQHandler + BX R0 + ENDP + +MRT0_IRQHandler\ + PROC + EXPORT MRT0_IRQHandler [WEAK] + LDR R0, =MRT0_DriverIRQHandler + BX R0 + ENDP + +CTIMER0_IRQHandler\ + PROC + EXPORT CTIMER0_IRQHandler [WEAK] + LDR R0, =CTIMER0_DriverIRQHandler + BX R0 + ENDP + +CTIMER1_IRQHandler\ + PROC + EXPORT CTIMER1_IRQHandler [WEAK] + LDR R0, =CTIMER1_DriverIRQHandler + BX R0 + ENDP + +SCT0_IRQHandler\ + PROC + EXPORT SCT0_IRQHandler [WEAK] + LDR R0, =SCT0_DriverIRQHandler + BX R0 + ENDP + +CTIMER3_IRQHandler\ + PROC + EXPORT CTIMER3_IRQHandler [WEAK] + LDR R0, =CTIMER3_DriverIRQHandler + BX R0 + ENDP + +FLEXCOMM0_IRQHandler\ + PROC + EXPORT FLEXCOMM0_IRQHandler [WEAK] + LDR R0, =FLEXCOMM0_DriverIRQHandler + BX R0 + ENDP + +FLEXCOMM1_IRQHandler\ + PROC + EXPORT FLEXCOMM1_IRQHandler [WEAK] + LDR R0, =FLEXCOMM1_DriverIRQHandler + BX R0 + ENDP + +FLEXCOMM2_IRQHandler\ + PROC + EXPORT FLEXCOMM2_IRQHandler [WEAK] + LDR R0, =FLEXCOMM2_DriverIRQHandler + BX R0 + ENDP + +FLEXCOMM3_IRQHandler\ + PROC + EXPORT FLEXCOMM3_IRQHandler [WEAK] + LDR R0, =FLEXCOMM3_DriverIRQHandler + BX R0 + ENDP + +FLEXCOMM4_IRQHandler\ + PROC + EXPORT FLEXCOMM4_IRQHandler [WEAK] + LDR R0, =FLEXCOMM4_DriverIRQHandler + BX R0 + ENDP + +FLEXCOMM5_IRQHandler\ + PROC + EXPORT FLEXCOMM5_IRQHandler [WEAK] + LDR R0, =FLEXCOMM5_DriverIRQHandler + BX R0 + ENDP + +FLEXCOMM6_IRQHandler\ + PROC + EXPORT FLEXCOMM6_IRQHandler [WEAK] + LDR R0, =FLEXCOMM6_DriverIRQHandler + BX R0 + ENDP + +FLEXCOMM7_IRQHandler\ + PROC + EXPORT FLEXCOMM7_IRQHandler [WEAK] + LDR R0, =FLEXCOMM7_DriverIRQHandler + BX R0 + ENDP + +ADC0_IRQHandler\ + PROC + EXPORT ADC0_IRQHandler [WEAK] + LDR R0, =ADC0_DriverIRQHandler + BX R0 + ENDP + +Reserved39_IRQHandler\ + PROC + EXPORT Reserved39_IRQHandler [WEAK] + LDR R0, =Reserved39_DriverIRQHandler + BX R0 + ENDP + +ACMP_IRQHandler\ + PROC + EXPORT ACMP_IRQHandler [WEAK] + LDR R0, =ACMP_DriverIRQHandler + BX R0 + ENDP + +Reserved41_IRQHandler\ + PROC + EXPORT Reserved41_IRQHandler [WEAK] + LDR R0, =Reserved41_DriverIRQHandler + BX R0 + ENDP + +Reserved42_IRQHandler\ + PROC + EXPORT Reserved42_IRQHandler [WEAK] + LDR R0, =Reserved42_DriverIRQHandler + BX R0 + ENDP + +USB0_NEEDCLK_IRQHandler\ + PROC + EXPORT USB0_NEEDCLK_IRQHandler [WEAK] + LDR R0, =USB0_NEEDCLK_DriverIRQHandler + BX R0 + ENDP + +USB0_IRQHandler\ + PROC + EXPORT USB0_IRQHandler [WEAK] + LDR R0, =USB0_DriverIRQHandler + BX R0 + ENDP + +RTC_IRQHandler\ + PROC + EXPORT RTC_IRQHandler [WEAK] + LDR R0, =RTC_DriverIRQHandler + BX R0 + ENDP + +Reserved46_IRQHandler\ + PROC + EXPORT Reserved46_IRQHandler [WEAK] + LDR R0, =Reserved46_DriverIRQHandler + BX R0 + ENDP + +MAILBOX_IRQHandler\ + PROC + EXPORT MAILBOX_IRQHandler [WEAK] + LDR R0, =MAILBOX_DriverIRQHandler + BX R0 + ENDP + +PIN_INT4_IRQHandler\ + PROC + EXPORT PIN_INT4_IRQHandler [WEAK] + LDR R0, =PIN_INT4_DriverIRQHandler + BX R0 + ENDP + +PIN_INT5_IRQHandler\ + PROC + EXPORT PIN_INT5_IRQHandler [WEAK] + LDR R0, =PIN_INT5_DriverIRQHandler + BX R0 + ENDP + +PIN_INT6_IRQHandler\ + PROC + EXPORT PIN_INT6_IRQHandler [WEAK] + LDR R0, =PIN_INT6_DriverIRQHandler + BX R0 + ENDP + +PIN_INT7_IRQHandler\ + PROC + EXPORT PIN_INT7_IRQHandler [WEAK] + LDR R0, =PIN_INT7_DriverIRQHandler + BX R0 + ENDP + +CTIMER2_IRQHandler\ + PROC + EXPORT CTIMER2_IRQHandler [WEAK] + LDR R0, =CTIMER2_DriverIRQHandler + BX R0 + ENDP + +CTIMER4_IRQHandler\ + PROC + EXPORT CTIMER4_IRQHandler [WEAK] + LDR R0, =CTIMER4_DriverIRQHandler + BX R0 + ENDP + +OS_EVENT_IRQHandler\ + PROC + EXPORT OS_EVENT_IRQHandler [WEAK] + LDR R0, =OS_EVENT_DriverIRQHandler + BX R0 + ENDP + +Reserved55_IRQHandler\ + PROC + EXPORT Reserved55_IRQHandler [WEAK] + LDR R0, =Reserved55_DriverIRQHandler + BX R0 + ENDP + +Reserved56_IRQHandler\ + PROC + EXPORT Reserved56_IRQHandler [WEAK] + LDR R0, =Reserved56_DriverIRQHandler + BX R0 + ENDP + +Reserved57_IRQHandler\ + PROC + EXPORT Reserved57_IRQHandler [WEAK] + LDR R0, =Reserved57_DriverIRQHandler + BX R0 + ENDP + +SDIO_IRQHandler\ + PROC + EXPORT SDIO_IRQHandler [WEAK] + LDR R0, =SDIO_DriverIRQHandler + BX R0 + ENDP + +Reserved59_IRQHandler\ + PROC + EXPORT Reserved59_IRQHandler [WEAK] + LDR R0, =Reserved59_DriverIRQHandler + BX R0 + ENDP + +Reserved60_IRQHandler\ + PROC + EXPORT Reserved60_IRQHandler [WEAK] + LDR R0, =Reserved60_DriverIRQHandler + BX R0 + ENDP + +Reserved61_IRQHandler\ + PROC + EXPORT Reserved61_IRQHandler [WEAK] + LDR R0, =Reserved61_DriverIRQHandler + BX R0 + ENDP + +USB1_UTMI_IRQHandler\ + PROC + EXPORT USB1_UTMI_IRQHandler [WEAK] + LDR R0, =USB1_UTMI_DriverIRQHandler + BX R0 + ENDP + +USB1_IRQHandler\ + PROC + EXPORT USB1_IRQHandler [WEAK] + LDR R0, =USB1_DriverIRQHandler + BX R0 + ENDP + +USB1_NEEDCLK_IRQHandler\ + PROC + EXPORT USB1_NEEDCLK_IRQHandler [WEAK] + LDR R0, =USB1_NEEDCLK_DriverIRQHandler + BX R0 + ENDP + +SEC_HYPERVISOR_CALL_IRQHandler\ + PROC + EXPORT SEC_HYPERVISOR_CALL_IRQHandler [WEAK] + LDR R0, =SEC_HYPERVISOR_CALL_DriverIRQHandler + BX R0 + ENDP + +SEC_GPIO_INT0_IRQ0_IRQHandler\ + PROC + EXPORT SEC_GPIO_INT0_IRQ0_IRQHandler [WEAK] + LDR R0, =SEC_GPIO_INT0_IRQ0_DriverIRQHandler + BX R0 + ENDP + +SEC_GPIO_INT0_IRQ1_IRQHandler\ + PROC + EXPORT SEC_GPIO_INT0_IRQ1_IRQHandler [WEAK] + LDR R0, =SEC_GPIO_INT0_IRQ1_DriverIRQHandler + BX R0 + ENDP + +PLU_IRQHandler\ + PROC + EXPORT PLU_IRQHandler [WEAK] + LDR R0, =PLU_DriverIRQHandler + BX R0 + ENDP + +SEC_VIO_IRQHandler\ + PROC + EXPORT SEC_VIO_IRQHandler [WEAK] + LDR R0, =SEC_VIO_DriverIRQHandler + BX R0 + ENDP + +HASHCRYPT_IRQHandler\ + PROC + EXPORT HASHCRYPT_IRQHandler [WEAK] + LDR R0, =HASHCRYPT_DriverIRQHandler + BX R0 + ENDP + +CASER_IRQHandler\ + PROC + EXPORT CASER_IRQHandler [WEAK] + LDR R0, =CASER_DriverIRQHandler + BX R0 + ENDP + +PUF_IRQHandler\ + PROC + EXPORT PUF_IRQHandler [WEAK] + LDR R0, =PUF_DriverIRQHandler + BX R0 + ENDP + +PQ_IRQHandler\ + PROC + EXPORT PQ_IRQHandler [WEAK] + LDR R0, =PQ_DriverIRQHandler + BX R0 + ENDP + +DMA1_IRQHandler\ + PROC + EXPORT DMA1_IRQHandler [WEAK] + LDR R0, =DMA1_DriverIRQHandler + BX R0 + ENDP + +FLEXCOMM8_IRQHandler\ + PROC + EXPORT FLEXCOMM8_IRQHandler [WEAK] + LDR R0, =FLEXCOMM8_DriverIRQHandler + BX R0 + ENDP + +Default_Handler PROC + EXPORT WDT_BOD_DriverIRQHandler [WEAK] + EXPORT DMA0_DriverIRQHandler [WEAK] + EXPORT GINT0_DriverIRQHandler [WEAK] + EXPORT GINT1_DriverIRQHandler [WEAK] + EXPORT PIN_INT0_DriverIRQHandler [WEAK] + EXPORT PIN_INT1_DriverIRQHandler [WEAK] + EXPORT PIN_INT2_DriverIRQHandler [WEAK] + EXPORT PIN_INT3_DriverIRQHandler [WEAK] + EXPORT UTICK0_DriverIRQHandler [WEAK] + EXPORT MRT0_DriverIRQHandler [WEAK] + EXPORT CTIMER0_DriverIRQHandler [WEAK] + EXPORT CTIMER1_DriverIRQHandler [WEAK] + EXPORT SCT0_DriverIRQHandler [WEAK] + EXPORT CTIMER3_DriverIRQHandler [WEAK] + EXPORT FLEXCOMM0_DriverIRQHandler [WEAK] + EXPORT FLEXCOMM1_DriverIRQHandler [WEAK] + EXPORT FLEXCOMM2_DriverIRQHandler [WEAK] + EXPORT FLEXCOMM3_DriverIRQHandler [WEAK] + EXPORT FLEXCOMM4_DriverIRQHandler [WEAK] + EXPORT FLEXCOMM5_DriverIRQHandler [WEAK] + EXPORT FLEXCOMM6_DriverIRQHandler [WEAK] + EXPORT FLEXCOMM7_DriverIRQHandler [WEAK] + EXPORT ADC0_DriverIRQHandler [WEAK] + EXPORT Reserved39_DriverIRQHandler [WEAK] + EXPORT ACMP_DriverIRQHandler [WEAK] + EXPORT Reserved41_DriverIRQHandler [WEAK] + EXPORT Reserved42_DriverIRQHandler [WEAK] + EXPORT USB0_NEEDCLK_DriverIRQHandler [WEAK] + EXPORT USB0_DriverIRQHandler [WEAK] + EXPORT RTC_DriverIRQHandler [WEAK] + EXPORT Reserved46_DriverIRQHandler [WEAK] + EXPORT MAILBOX_DriverIRQHandler [WEAK] + EXPORT PIN_INT4_DriverIRQHandler [WEAK] + EXPORT PIN_INT5_DriverIRQHandler [WEAK] + EXPORT PIN_INT6_DriverIRQHandler [WEAK] + EXPORT PIN_INT7_DriverIRQHandler [WEAK] + EXPORT CTIMER2_DriverIRQHandler [WEAK] + EXPORT CTIMER4_DriverIRQHandler [WEAK] + EXPORT OS_EVENT_DriverIRQHandler [WEAK] + EXPORT Reserved55_DriverIRQHandler [WEAK] + EXPORT Reserved56_DriverIRQHandler [WEAK] + EXPORT Reserved57_DriverIRQHandler [WEAK] + EXPORT SDIO_DriverIRQHandler [WEAK] + EXPORT Reserved59_DriverIRQHandler [WEAK] + EXPORT Reserved60_DriverIRQHandler [WEAK] + EXPORT Reserved61_DriverIRQHandler [WEAK] + EXPORT USB1_UTMI_DriverIRQHandler [WEAK] + EXPORT USB1_DriverIRQHandler [WEAK] + EXPORT USB1_NEEDCLK_DriverIRQHandler [WEAK] + EXPORT SEC_HYPERVISOR_CALL_DriverIRQHandler [WEAK] + EXPORT SEC_GPIO_INT0_IRQ0_DriverIRQHandler [WEAK] + EXPORT SEC_GPIO_INT0_IRQ1_DriverIRQHandler [WEAK] + EXPORT PLU_DriverIRQHandler [WEAK] + EXPORT SEC_VIO_DriverIRQHandler [WEAK] + EXPORT HASHCRYPT_DriverIRQHandler [WEAK] + EXPORT CASER_DriverIRQHandler [WEAK] + EXPORT PUF_DriverIRQHandler [WEAK] + EXPORT PQ_DriverIRQHandler [WEAK] + EXPORT DMA1_DriverIRQHandler [WEAK] + EXPORT FLEXCOMM8_DriverIRQHandler [WEAK] + +WDT_BOD_DriverIRQHandler +DMA0_DriverIRQHandler +GINT0_DriverIRQHandler +GINT1_DriverIRQHandler +PIN_INT0_DriverIRQHandler +PIN_INT1_DriverIRQHandler +PIN_INT2_DriverIRQHandler +PIN_INT3_DriverIRQHandler +UTICK0_DriverIRQHandler +MRT0_DriverIRQHandler +CTIMER0_DriverIRQHandler +CTIMER1_DriverIRQHandler +SCT0_DriverIRQHandler +CTIMER3_DriverIRQHandler +FLEXCOMM0_DriverIRQHandler +FLEXCOMM1_DriverIRQHandler +FLEXCOMM2_DriverIRQHandler +FLEXCOMM3_DriverIRQHandler +FLEXCOMM4_DriverIRQHandler +FLEXCOMM5_DriverIRQHandler +FLEXCOMM6_DriverIRQHandler +FLEXCOMM7_DriverIRQHandler +ADC0_DriverIRQHandler +Reserved39_DriverIRQHandler +ACMP_DriverIRQHandler +Reserved41_DriverIRQHandler +Reserved42_DriverIRQHandler +USB0_NEEDCLK_DriverIRQHandler +USB0_DriverIRQHandler +RTC_DriverIRQHandler +Reserved46_DriverIRQHandler +MAILBOX_DriverIRQHandler +PIN_INT4_DriverIRQHandler +PIN_INT5_DriverIRQHandler +PIN_INT6_DriverIRQHandler +PIN_INT7_DriverIRQHandler +CTIMER2_DriverIRQHandler +CTIMER4_DriverIRQHandler +OS_EVENT_DriverIRQHandler +Reserved55_DriverIRQHandler +Reserved56_DriverIRQHandler +Reserved57_DriverIRQHandler +SDIO_DriverIRQHandler +Reserved59_DriverIRQHandler +Reserved60_DriverIRQHandler +Reserved61_DriverIRQHandler +USB1_UTMI_DriverIRQHandler +USB1_DriverIRQHandler +USB1_NEEDCLK_DriverIRQHandler +SEC_HYPERVISOR_CALL_DriverIRQHandler +SEC_GPIO_INT0_IRQ0_DriverIRQHandler +SEC_GPIO_INT0_IRQ1_DriverIRQHandler +PLU_DriverIRQHandler +SEC_VIO_DriverIRQHandler +HASHCRYPT_DriverIRQHandler +CASER_DriverIRQHandler +PUF_DriverIRQHandler +PQ_DriverIRQHandler +DMA1_DriverIRQHandler +FLEXCOMM8_DriverIRQHandler + + B . + + ENDP + + + ALIGN + + + END + diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_anactrl.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_anactrl.c new file mode 100644 index 000000000..08eb3b738 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_anactrl.c @@ -0,0 +1,320 @@ +/* + * Copyright 2018, NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include "fsl_anactrl.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.anactrl" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Get instance number for ANACTRL module. + * + * @param base ANACTRL peripheral base address + */ +static uint32_t ANACTRL_GetInstance(ANACTRL_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to ANACTRL bases for each instance. */ +static ANACTRL_Type *const s_anactrlBases[] = ANACTRL_BASE_PTRS; +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to ANACTRL clocks for each instance. */ +static const clock_ip_name_t s_anactrlClocks[] = ANALOGCTRL_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Code + ******************************************************************************/ +/*! + * brief Get the ANACTRL instance from peripheral base address. + * + * param base ANACTRL peripheral base address. + * return ANACTRL instance. + */ +static uint32_t ANACTRL_GetInstance(ANACTRL_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_anactrlBases); instance++) + { + if (s_anactrlBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_anactrlBases)); + + return instance; +} + +/*! + * @brief Enable the access to ANACTRL registers and initialize ANACTRL module. + * + * @param base ANACTRL peripheral base address. + */ +void ANACTRL_Init(ANACTRL_Type *base) +{ + assert(NULL != base); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock for ANACTRL instance. */ + CLOCK_EnableClock(s_anactrlClocks[ANACTRL_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * @brief De-initialize ANACTRL module. + * + * @param base ANACTRL peripheral base address. + */ +void ANACTRL_Deinit(ANACTRL_Type *base) +{ + assert(NULL != base); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable the clock for ANACTRL instance. */ + CLOCK_DisableClock(s_anactrlClocks[ANACTRL_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * @brief Set the on-chip high-speed Free Running Oscillator. + * + * @param base ANACTRL peripheral base address. + * @param config Pointer to FRO192M configuration structure. Refer to "anactrl_fro192M_config_t" structure. + */ +void ANACTRL_SetFro192M(ANACTRL_Type *base, anactrl_fro192M_config_t *config) +{ + assert(NULL != config); + + uint32_t tmp32 = 0; + + /* Set FRO trim values. */ + base->FRO192M_CTRL |= ANACTRL_FRO192M_CTRL_WRTRIM_MASK; + tmp32 |= ANACTRL_FRO192M_CTRL_BIAS_TRIM(config->biasTrim) | ANACTRL_FRO192M_CTRL_TEMP_TRIM(config->tempTrim) | + ANACTRL_FRO192M_CTRL_DAC_TRIM(config->dacTrim); + + if (config->enable12MHzClk) + { + tmp32 |= ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK; + } + if (config->enable48MhzClk) + { + tmp32 |= ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_MASK; + } + if (config->enable96MHzClk) + { + tmp32 |= ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK; + } + + if (config->enableAnalogTestBus) + { + tmp32 |= ANACTRL_FRO192M_CTRL_ATB_CTRL_MASK; + } + + base->FRO192M_CTRL |= tmp32; +} + +/*! + * @brief Get the default configuration of FRO192M. + * The default values are: + * code + * config->biasTrim = 0x1AU; + * config->tempTrim = 0x20U; + * config->enable12MHzClk = true; + * config->enable48MhzClk = true; + * config->dacTrim = 0x80U; + * config->enableAnalogTestBus = false; + * config->enable96MHzClk = false; + * encode + * @param config Pointer to FRO192M configuration structure. Refer to "anactrl_fro192M_config_t" structure. + */ +void ANACTRL_GetDefaultFro192MConfig(anactrl_fro192M_config_t *config) +{ + assert(NULL != config); + + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + + config->biasTrim = 0x1AU; + config->tempTrim = 0x20U; + config->enable12MHzClk = true; + config->enable48MhzClk = true; + config->dacTrim = 0x80U; + config->enableAnalogTestBus = false; + config->enable96MHzClk = false; +} + +/*! + * @brief Set the 32 MHz Crystal oscillator. + * + * @param base ANACTRL peripheral base address. + * @param config Pointer to XO32M configuration structure. Refer to "anactrl_xo32M_config_t" structure. + */ +void ANACTRL_SetXo32M(ANACTRL_Type *base, anactrl_xo32M_config_t *config) +{ + assert(NULL != config); + + uint32_t tmp32 = 0U; + + /* Set XO32M CTRL. */ + if (config->enableACBufferBypass) + { + tmp32 |= ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK; + } + if (config->enablePllUsbOutput) + { + tmp32 |= ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK; + } + if (config->enableSysCLkOutput) + { + tmp32 |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; + } + base->XO32M_CTRL = tmp32; + + /* Set LDO XO32M. */ + tmp32 = ANACTRL_LDO_XO32M_HIGHZ(config->LDOOutputMode) | ANACTRL_LDO_XO32M_VOUT(config->LDOOutputLevel) | + ANACTRL_LDO_XO32M_IBIAS(config->bias) | ANACTRL_LDO_XO32M_STABMODE(config->stability); + if (config->enableLDOBypass) + { + tmp32 |= ANACTRL_LDO_XO32M_BYPASS_MASK; + } + + base->LDO_XO32M = tmp32; +} + +/*! + * @brief Get the default configuration of XO32M. + * The default values are: + * code + * config->enableACBufferBypass = false; + * config->enablePllUsbOutput = false; + * config->enableSysCLkOutput = false; + * config->enableLDOBypass = false; + * config->LDOOutputMode = kANACTRL_LDOOutputHighNormalMode; + * config->LDOOutputLevel = kANACTRL_LDOOutputLevel4; + * config->bias = 2U; + * config->stability = 3U; + * encode + * @param config Pointer to XO32M configuration structure. Refer to "anactrl_xo32M_config_t" structure. + */ +void ANACTRL_GetDefaultXo32MConfig(anactrl_xo32M_config_t *config) +{ + assert(NULL != config); + + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + + config->enableACBufferBypass = false; + config->enablePllUsbOutput = false; + config->enableSysCLkOutput = false; + config->enableLDOBypass = false; + config->LDOOutputMode = kANACTRL_LDOOutputHighNormalMode; + config->LDOOutputLevel = kANACTRL_LDOOutputLevel4; + config->bias = 2U; + config->stability = 3U; +} + +/*! + * @brief Set the ring oscillators. + * + * @param base ANACTRL peripheral base address. + * @param config Pointer to ring osc configuration structure. Refer to "anactrl_ring_osc_config_t" structure. + */ +void ANACTRL_SetRingOsc(ANACTRL_Type *base, anactrl_ring_osc_config_t *config) +{ + assert(NULL != config); + + uint32_t tmp32 = 0U; + + /* Configure the first ring oscillator. */ + tmp32 = ANACTRL_RINGO0_CTRL_SL(config->ringOscSel) | ANACTRL_RINGO0_CTRL_FS(config->ringOscFreqOutputDiv) | + ANACTRL_RINGO0_CTRL_SWN_SWP(config->pnRingOscMode) | ANACTRL_RINGO0_CTRL_E_ND0_MASK | + ANACTRL_RINGO0_CTRL_E_ND1_MASK | ANACTRL_RINGO0_CTRL_E_NR0_MASK | ANACTRL_RINGO0_CTRL_E_NR1_MASK | + ANACTRL_RINGO0_CTRL_E_IV0_MASK | ANACTRL_RINGO0_CTRL_E_IV1_MASK | ANACTRL_RINGO0_CTRL_E_PN0_MASK | + ANACTRL_RINGO0_CTRL_E_PN1_MASK | ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_MASK | + ANACTRL_RINGO0_CTRL_DIVISOR(config->ringOscOutClkDiv); + base->RINGO0_CTRL = tmp32; + + /* Configure the second and third ring oscillator. */ + tmp32 = ANACTRL_RINGO1_CTRL_S(config->ringOscSel) | ANACTRL_RINGO1_CTRL_FS(config->ringOscFreqOutputDiv) | + ANACTRL_RINGO1_CTRL_E_R24_MASK | ANACTRL_RINGO1_CTRL_E_R35_MASK | ANACTRL_RINGO1_CTRL_E_M2_MASK | + ANACTRL_RINGO1_CTRL_E_M3_MASK | ANACTRL_RINGO1_CTRL_E_M4_MASK | ANACTRL_RINGO1_CTRL_E_M5_MASK | + ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_MASK | ANACTRL_RINGO1_CTRL_DIVISOR(config->ringOscOutClkDiv); + base->RINGO1_CTRL = tmp32; + base->RINGO2_CTRL = tmp32; + + /* Ensure the Riongo module is enabled. */ + base->RINGO0_CTRL &= ~ANACTRL_RINGO0_CTRL_PD_MASK; + base->RINGO1_CTRL &= ~ANACTRL_RINGO1_CTRL_PD_MASK; + base->RINGO2_CTRL &= ~ANACTRL_RINGO2_CTRL_PD_MASK; +} + +/*! + * @brief Get the default configuration of ring oscillators. + * The default values are: + * code + * config->ringOscSel = kANACTRL_ShortRingOsc; + * config->ringOscFreqOutputDiv = kANACTRL_HighFreqOutput; + * config->pnRingOscMode = kANACTRL_NormalMode; + * config->ringOscOutClkDiv = 0U; + * encode + * @param config Pointer to ring oscillator configuration structure. Refer to "anactrl_ring_osc_config_t" structure. + */ +void ANACTRL_GetDefaultRingOscConfig(anactrl_ring_osc_config_t *config) +{ + assert(NULL != config); + + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + + config->ringOscSel = kANACTRL_ShortRingOsc; + config->ringOscFreqOutputDiv = kANACTRL_HighFreqOutput; + config->pnRingOscMode = kANACTRL_NormalMode; + config->ringOscOutClkDiv = 0U; +} + +/*! + * @brief Measure Frequency + * + * This function measures target frequency according to a accurate reference frequency.The formula is: + * Ftarget = (CAPVAL * Freference) / ((1<= 2U); + + uint32_t targetClkFreq = 0U; + uint32_t capval = 0U; + + /* Init a measurement cycle. */ + base->FREQ_ME_CTRL = ANACTRL_FREQ_ME_CTRL_PROG_MASK + ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE(scale); + while (ANACTRL_FREQ_ME_CTRL_PROG_MASK == (base->FREQ_ME_CTRL & ANACTRL_FREQ_ME_CTRL_PROG_MASK)) + { + } + + /* Calculate the target clock frequency. */ + capval = (base->FREQ_ME_CTRL & ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_MASK); + targetClkFreq = (capval * refClkFreq) / ((1 << scale) - 1); + + return targetClkFreq; +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_anactrl.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_anactrl.h new file mode 100644 index 000000000..bf55295bf --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_anactrl.h @@ -0,0 +1,458 @@ +/* + * Copyright 2018, NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __FSL_ANACTRL_H__ +#define __FSL_ANACTRL_H__ + +#include "fsl_common.h" + +/*! + * @addtogroup anactrl + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief ANACTRL driver version. */ +#define FSL_ANACTRL_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */` + +/*! + * @brief ANACTRL interrupt flags + */ +enum _anactrl_interrupt_flags +{ + kANACTRL_BodVbatFlag = + ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_MASK, /*!< BOD VBAT Interrupt status before Interrupt Enable. */ + kANACTRL_BodVbatInterruptFlag = + ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_MASK, /*!< BOD VBAT Interrupt status after Interrupt Enable. */ + kANACTRL_BodVbatPowerFlag = + ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_MASK, /*!< Current value of BOD VBAT power status output. */ + kANACTRL_BodCoreFlag = + ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_MASK, /*!< BOD CORE Interrupt status before Interrupt Enable. */ + kANACTRL_BodCoreInterruptFlag = + ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_MASK, /*!< BOD CORE Interrupt status after Interrupt Enable. */ + kANACTRL_BodCorePowerFlag = + ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_MASK, /*!< Current value of BOD CORE power status output. */ + kANACTRL_DcdcFlag = + ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_MASK, /*!< DCDC Interrupt status before Interrupt Enable. */ + kANACTRL_DcdcInterruptFlag = + ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_MASK, /*!< DCDC Interrupt status after Interrupt Enable. */ + kANACTRL_DcdcPowerFlag = + ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_MASK, /*!< Current value of DCDC power status output. */ +}; + +/*! + * @brief ANACTRL interrupt control + */ +enum _anactrl_interrupt +{ + kANACTRL_BodVbatInterruptEnable = + ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_MASK, /*!< BOD VBAT interrupt control. */ + kANACTRL_BodCoreInterruptEnable = + ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_MASK, /*!< BOD CORE interrupt control. */ + kANACTRL_DcdcInterruptEnable = ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_MASK, /*!< DCDC interrupt control. */ + kANACTRL_BodVbatInterruptClear = + ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_MASK, /*!< BOD VBAT interrupt clear.1: Clear the interrupt. + Self-cleared bit. */ + kANACTRL_BodCoreInterruptClear = + ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_MASK, /*!< BOD CORE interrupt clear.1: Clear the interrupt. + Self-cleared bit. */ + kANACTRL_DcdcInterruptClear = ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_MASK, /*!< DCDC interrupt clear.1: Clear the + interrupt. Self-cleared bit. */ +}; + +/*! + * @brief ANACTRL status flags + */ +enum _anactrl_flags +{ + kANACTRL_PMUId = ANACTRL_ANALOG_CTRL_STATUS_PMU_ID_MASK, /*!< Power Management Unit (PMU) analog macro-bloc + identification number. */ + kANACTRL_OSCId = + ANACTRL_ANALOG_CTRL_STATUS_OSC_ID_MASK, /*!< Oscillators analog macro-bloc identification number. */ + kANACTRL_FlashPowerDownFlag = ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_MASK, /*!< Flash power-down status. */ + kANACTRL_FlashInitErrorFlag = + ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_MASK, /*!< Flash initialization error status. */ + kANACTRL_FinalTestFlag = + ANACTRL_ANALOG_CTRL_STATUS_FINAL_TEST_DONE_VECT_MASK, /*!< Indicates current status of final test. */ +}; + +/*! + * @brief ANACTRL FRO192M and XO32M status flags + */ +enum _anactrl_osc_flags +{ + kANACTRL_OutputClkValidFlag = ANACTRL_FRO192M_STATUS_CLK_VALID_MASK, /*!< Output clock valid signal. */ + kANACTRL_CCOThresholdVoltageFlag = + ANACTRL_FRO192M_STATUS_ATB_VCTRL_MASK, /*!< CCO threshold voltage detector output (signal vcco_ok). */ + kANACTRL_XO32MOutputReadyFlag = ANACTRL_XO32M_STATUS_XO_READY_MASK + << 16U, /*!< Indicates XO out frequency statibilty. */ +}; + +/*! + * @brief LDO output mode + */ +typedef enum _anactrl_ldo_output_mode +{ + kANACTRL_LDOOutputHighNormalMode = 0U, /*!< Output in High normal state. */ + kANACTRL_LDOOutputHighImpedanceMode = 1U, /*!< Output in High Impedance state. */ +} anactrl_ldo_output_mode_t; + +/*! + * @brief LDO output level + */ +typedef enum _anactrl_ldo_output_level +{ + kANACTRL_LDOOutputLevel0 = 0U, /*!< Output level 0.750 V. */ + kANACTRL_LDOOutputLevel1, /*!< Output level 0.775 V. */ + kANACTRL_LDOOutputLevel2, /*!< Output level 0.800 V. */ + kANACTRL_LDOOutputLevel3, /*!< Output level 0.825 V. */ + kANACTRL_LDOOutputLevel4, /*!< Output level 0.850 V. */ + kANACTRL_LDOOutputLevel5, /*!< Output level 0.875 V. */ + kANACTRL_LDOOutputLevel6, /*!< Output level 0.900 V. */ + kANACTRL_LDOOutputLevel7, /*!< Output level 0.925 V. */ +} anactrl_ldo_output_level_t; + +/*! + * @brief Select short or long ring osc + */ +typedef enum _anactrl_ring_osc_selector +{ + kANACTRL_ShortRingOsc = 0U, /*!< Select short ring osc (few elements). */ + kANACTRL_LongRingOsc = 1U, /*!< Select long ring osc (many elements). */ +} anactrl_ring_osc_selector_t; + +/*! + * @brief Ring osc frequency output divider + */ +typedef enum _anactrl_ring_osc_freq_output_divider +{ + kANACTRL_HighFreqOutput = 0U, /*!< High frequency output (frequency lower than 100 MHz). */ + kANACTRL_LowFreqOutput = 1U, /*!< Low frequency output (frequency lower than 10 MHz). */ +} anactrl_ring_osc_freq_output_divider_t; + +/*! + * @brief PN-Ring osc (P-Transistor and N-Transistor processing) control. + */ +typedef enum _anactrl_pn_ring_osc_mode +{ + kANACTRL_NormalMode = 0U, /*!< Normal mode. */ + kANACTRL_PMonitorPTransistorMode = 1U, /*!< P-Monitor mode. Measure with weak P transistor. */ + kANACTRL_PMonitorNTransistorMode = 2U, /*!< P-Monitor mode. Measure with weak N transistor. */ + kANACTRL_NotUse = 3U, /*!< Do not use. */ +} anactrl_pn_ring_osc_mode_t; + +/*! + * @breif Configuration for FRO192M + * + * This structure holds the configuration settings for the on-chip high-speed Free Running Oscillator. To initialize + * this structure to reasonable defaults, call the ANACTRL_GetDefaultFro192MConfig() function and pass a + * pointer to your config structure instance. + */ +typedef struct _anactrl_fro192M_config +{ + uint8_t biasTrim; /*!< Set bias trimming value (course frequency trimming). */ + uint8_t tempTrim; /*!< Set temperature coefficient trimming value. */ + uint8_t dacTrim; /*!< Set curdac trimming value (fine frequency trimming) This trim is used to + adjust the frequency, given that the bias and temperature trim are set. */ + bool enable12MHzClk; /*!< Enable 12MHz clock. */ + bool enable48MhzClk; /*!< Enable 48MHz clock. */ + bool enable96MHzClk; /*!< Enable 96MHz clock. */ + bool enableAnalogTestBus; /*!< Enable analog test bus. */ +} anactrl_fro192M_config_t; + +/*! + * @breif Configuration for XO32M + * + * This structure holds the configuration settings for the 32 MHz crystal oscillator. To initialize this + * structure to reasonable defaults, call the ANACTRL_GetDefaultXo32MConfig() function and pass a + * pointer to your config structure instance. + */ +typedef struct _anactrl_xo32M_config +{ + bool enableACBufferBypass; /*!< Enable XO AC buffer bypass in pll and top level. */ + bool enablePllUsbOutput; /*!< Enable XO 32 MHz output to USB HS PLL. */ + bool enableSysCLkOutput; /*!< Enable XO 32 MHz output to CPU system, SCT, and CLKOUT */ + bool enableLDOBypass; /*!< Activate LDO bypass. */ + anactrl_ldo_output_mode_t LDOOutputMode; /*!< Set LDO output mode. */ + anactrl_ldo_output_level_t LDOOutputLevel; /*!< Set LDO output level. */ + uint8_t bias; /*!< Adjust the biasing current. */ + uint8_t stability; /*!< Stability configuration. */ +} anactrl_xo32M_config_t; + +/*! + * @breif Configuration for ring oscillator + * + * This structure holds the configuration settings for the three ring oscillators. To initialize this + * structure to reasonable defaults, call the ANACTRL_GetDefaultRingOscConfig() function and pass a + * pointer to your config structure instance. + */ +typedef struct _anactrl_ring_osc_config +{ + anactrl_ring_osc_selector_t ringOscSel; + anactrl_ring_osc_freq_output_divider_t ringOscFreqOutputDiv; + anactrl_pn_ring_osc_mode_t pnRingOscMode; + uint8_t ringOscOutClkDiv; +} anactrl_ring_osc_config_t; +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Enable the access to ANACTRL registers and initialize ANACTRL module. + * + * @param base ANACTRL peripheral base address. + */ +void ANACTRL_Init(ANACTRL_Type *base); + +/*! + * @brief De-initialize ANACTRL module. + * + * @param base ANACTRL peripheral base address. + */ +void ANACTRL_Deinit(ANACTRL_Type *base); +/* @} */ + +/*! + * @name Set oscillators + * @{ + */ + +/*! + * @brief Set the on-chip high-speed Free Running Oscillator. + * + * @param base ANACTRL peripheral base address. + * @param config Pointer to FRO192M configuration structure. Refer to "anactrl_fro192M_config_t" structure. + */ +void ANACTRL_SetFro192M(ANACTRL_Type *base, anactrl_fro192M_config_t *config); + +/*! + * @brief Get the default configuration of FRO192M. + * The default values are: + * code + * config->biasTrim = 0x1AU; + * config->tempTrim = 0x20U; + * config->enable12MHzClk = true; + * config->enable48MhzClk = true; + * config->dacTrim = 0x80U; + * config->enableAnalogTestBus = false; + * config->enable96MHzClk = false; + * encode + * @param config Pointer to FRO192M configuration structure. Refer to "anactrl_fro192M_config_t" structure. + */ +void ANACTRL_GetDefaultFro192MConfig(anactrl_fro192M_config_t *config); + +/*! + * @brief Set the 32 MHz Crystal oscillator. + * + * @param base ANACTRL peripheral base address. + * @param config Pointer to XO32M configuration structure. Refer to "anactrl_xo32M_config_t" structure. + */ +void ANACTRL_SetXo32M(ANACTRL_Type *base, anactrl_xo32M_config_t *config); + +/*! + * @brief Get the default configuration of XO32M. + * The default values are: + * code + * config->enableACBufferBypass = false; + * config->enablePllUsbOutput = false; + * config->enableSysCLkOutput = false; + * config->enableLDOBypass = false; + * config->LDOOutputMode = kANACTRL_LDOOutputHighNormalMode; + * config->LDOOutputLevel = kANACTRL_LDOOutputLevel4; + * config->bias = 2U; + * config->stability = 3U; + * encode + * @param config Pointer to XO32M configuration structure. Refer to "anactrl_xo32M_config_t" structure. + */ +void ANACTRL_GetDefaultXo32MConfig(anactrl_xo32M_config_t *config); + +/*! + * @brief Set the ring oscillators. + * + * @param base ANACTRL peripheral base address. + * @param config Pointer to ring osc configuration structure. Refer to "anactrl_ring_osc_config_t" structure. + */ +void ANACTRL_SetRingOsc(ANACTRL_Type *base, anactrl_ring_osc_config_t *config); + +/*! + * @brief Get the default configuration of ring oscillators. + * The default values are: + * code + * config->ringOscSel = kANACTRL_ShortRingOsc; + * config->ringOscFreqOutputDiv = kANACTRL_HighFreqOutput; + * config->pnRingOscMode = kANACTRL_NormalMode; + * config->ringOscOutClkDiv = 0U; + * encode + * @param config Pointer to ring oscillator configuration structure. Refer to "anactrl_ring_osc_config_t" structure. + */ +void ANACTRL_GetDefaultRingOscConfig(anactrl_ring_osc_config_t *config); +/* @} */ + +/*! + * @name ADC control + * @{ + */ + +/*! + * @brief Enable VBAT divider branch. + * + * @param base ANACTRL peripheral base address. + * @param enable switcher to the function. + */ +static inline void ANACTRL_EnableAdcVBATDivider(ANACTRL_Type *base, bool enable) +{ + if (enable) + { + base->ADC_CTRL |= ANACTRL_ADC_CTRL_VBATDIVENABLE_MASK; + } + else + { + base->ADC_CTRL &= ~ANACTRL_ADC_CTRL_VBATDIVENABLE_MASK; + } +} +/* @} */ + +/*! + * @name Measure Frequency + * @{ + */ + +/*! + * @brief Measure Frequency + * + * This function measures target frequency according to a accurate reference frequency.The formula is: + * Ftarget = (CAPVAL * Freference) / ((1<BOD_DCDC_INT_CTRL |= (0x15U & mask); +} + +/*! + * @brief Disable the ANACTRL interrupts. + * + * @param bas ANACTRL peripheral base address. + * @param mask The interrupt mask. Refer to "_anactrl_interrupt" enumeration. + */ +static inline void ANACTRL_DisableInterrupt(ANACTRL_Type *base, uint32_t mask) +{ + base->BOD_DCDC_INT_CTRL = (base->BOD_DCDC_INT_CTRL & ~0x2AU) | (mask & 0x2AU); +} +/* @} */ + +/*! + * @name Status Interface + * @{ + */ + +/*! + * @brief Get ANACTRL status flags. + * + * This function gets Analog control status flags. The flags are returned as the logical + * OR value of the enumerators @ref _anactrl_flags. To check for a specific status, + * compare the return value with enumerators in the @ref _anactrl_flags. + * For example, to check whether the flash is in power down mode: + * @code + * if (kANACTRL_FlashPowerDownFlag & ANACTRL_ANACTRL_GetStatusFlags(ANACTRL)) + * { + * ... + * } + * @endcode + * + * @param base ANACTRL peripheral base address. + * @return ANACTRL status flags which are given in the enumerators in the @ref _anactrl_flags. + */ +static inline uint32_t ANACTRL_GetStatusFlags(ANACTRL_Type *base) +{ + return base->ANALOG_CTRL_STATUS; +} + +/*! + * @brief Get ANACTRL oscillators status flags. + * + * This function gets Anactrl oscillators status flags. The flags are returned as the logical + * OR value of the enumerators @ref _anactrl_osc_flags. To check for a specific status, + * compare the return value with enumerators in the @ref _anactrl_osc_flags. + * For example, to check whether the FRO192M clock output is valid: + * @code + * if (kANACTRL_OutputClkValidFlag & ANACTRL_ANACTRL_GetOscStatusFlags(ANACTRL)) + * { + * ... + * } + * @endcode + * + * @param base ANACTRL peripheral base address. + * @return ANACTRL oscillators status flags which are given in the enumerators in the @ref _anactrl_osc_flags. + */ +static inline uint32_t ANACTRL_GetOscStatusFlags(ANACTRL_Type *base) +{ + return (base->FRO192M_STATUS & 0xFFU) | ((base->XO32M_STATUS & 0xFFU) << 16U); +} + +/*! + * @brief Get ANACTRL interrupt status flags. + * + * This function gets Anactrl interrupt status flags. The flags are returned as the logical + * OR value of the enumerators @ref _anactrl_interrupt_flags. To check for a specific status, + * compare the return value with enumerators in the @ref _anactrl_interrupt_flags. + * For example, to check whether the VBAT voltage level is above the threshold: + * @code + * if (kANACTRL_BodVbatPowerFlag & ANACTRL_ANACTRL_GetInterruptStatusFlags(ANACTRL)) + * { + * ... + * } + * @endcode + * + * @param base ANACTRL peripheral base address. + * @return ANACTRL oscillators status flags which are given in the enumerators in the @ref _anactrl_osc_flags. + */ +static inline uint32_t ANACTRL_GetInterruptStatusFlags(ANACTRL_Type *base) +{ + return base->BOD_DCDC_INT_STATUS & 0x1FFU; +} +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/* @}*/ + +#endif /* __FSL_ANACTRL_H__ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_casper.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_casper.c new file mode 100644 index 000000000..543869bd8 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_casper.c @@ -0,0 +1,2662 @@ +/* + * Copyright 2018 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_casper.h" +#include /* ceil TODO check if really need it */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.casper" +#endif + +#define CASPER_RAM_BASE_NS (FSL_FEATURE_CASPER_RAM_BASE_ADDRESS) + +#if defined(FSL_FEATURE_CASPER_RAM_IS_INTERLEAVED) && FSL_FEATURE_CASPER_RAM_IS_INTERLEAVED +#define CASPER_RAM_OFFSET (0xE) +#define INTERLEAVE(addr) \ + (((((((addr) >> 2) & 0x00000001) << CASPER_RAM_OFFSET) + (((addr) >> 3) << 2) + ((addr)&0x00000003)) & 0xFFFF) | \ + s_casperRamBase) +#define DEINTERLEAVE(addr) INTERLEAVE(addr) +#define GET_WORD(addr) (*((uint32_t *)DEINTERLEAVE((uint32_t)(addr)))) +#define GET_DWORD(addr) (((uint64_t)GET_WORD(addr)) | (((uint64_t)GET_WORD(((uint32_t)(addr)) + 4)) << 32)) +#define SET_WORD(addr, value) *((uint32_t *)INTERLEAVE((uint32_t)(addr))) = ((uint32_t)(value)) +#define SET_DWORD(addr, value) \ + do \ + { \ + SET_WORD(addr, (uint32_t)(value & 0xFFFFFFFF)); \ + SET_WORD(((uint32_t)(addr)) + 4, (uint32_t)((value & 0xFFFFFFFF00000000) >> 32)); \ + } while (0) + +/* memcopy is always word aligned */ +/* interleaved to interleaved + static void CASPER_MEMCPY_I2I(void *dst, const void *src, size_t siz) + */ +#define CASPER_MEMCPY_I2I(dst, src, siz) \ + \ +{ \ + uint32_t *dst32 = (uint32_t *)dst, *src32 = (uint32_t *)src; \ + int i; \ + for (i = 0; i < siz / 4; i++) \ + { \ + SET_WORD(&dst32[i], GET_WORD(&src32[i])); \ + } \ + \ +} + +/* interleaved to non-interleaved + static void CASPER_MEMCPY_I2N(void *dst, const void *src, size_t siz) + */ +#define CASPER_MEMCPY_I2N(dst, src, siz) \ + \ +{ \ + uint32_t *dst32 = (uint32_t *)dst, *src32 = (uint32_t *)src; \ + int i; \ + for (i = 0; i < siz / 4; i++) \ + { \ + dst32[i] = GET_WORD(&src32[i]); \ + } \ + \ +} + +/* non-interleaved to interleaved + static void CASPER_MEMCPY_N2I(void *dst, const void *src, size_t siz) + */ +#define CASPER_MEMCPY_N2I(dst, src, siz) \ + \ +{ \ + volatile uint32_t *dst32 = (uint32_t *)dst, *src32 = (uint32_t *)src; \ + volatile int i; \ + for (i = 0; i < siz / 4; i++) \ + { \ + SET_WORD(&dst32[i], src32[i]); \ + } \ + \ +} +#else +#define GET_WORD(addr) (*((uint32_t *)(addr))) +#define GET_DWORD(addr) (*((uint64_t *)(addr))) +#define SET_WORD(addr, value) *((uint32_t *)(addr)) = ((uint32_t)(value)) +#define SET_DWORD(addr, value) *((uint64_t *)(addr)) = ((uint64_t)(value)) + +#define CASPER_MEMCPY_I2I(dst, src, siz) memcpy(dst, src, siz) +#define CASPER_MEMCPY_I2N(dst, src, siz) memcpy(dst, src, siz) +#define CASPER_MEMCPY_N2I(dst, src, siz) memcpy(dst, src, siz) +#endif + +#define WORK_BUFF_MUL4 (N_wordlen_max * 4 + 2) /* ! working buffer is 4xN_wordlen to allow in place math */ +#define N_bytelen (N_wordlen * 4) /* for memory copy and the like */ +#define N_dwordlen (N_wordlen / 2) + +#define PreZeroW(i, w_out) \ + for (i = 0; i < N_wordlen; i += 4) \ + { \ + SET_WORD(&w_out[i + 0], 0); \ + SET_WORD(&w_out[i + 1], 0); \ + SET_WORD(&w_out[i + 2], 0); \ + SET_WORD(&w_out[i + 3], 0); \ + } /* unrolled partly */ +#define PreZeroW2up(i, w_out) \ + for (i = N_wordlen; i <= N_wordlen * 2; i += 4) \ + { \ + SET_WORD(&w_out[i + 0], 0); \ + SET_WORD(&w_out[i + 1], 0); \ + SET_WORD(&w_out[i + 2], 0); \ + SET_WORD(&w_out[i + 3], 0); \ + } /* unrolled partly */ + +/* Macros for the ECC component in Casper */ + +/* CASPER memory layout for ECC */ +#define CASPER_NUM_LIMBS (NUM_LIMBS + 4) // number of limbs needed by CASPER is 2 double words longer + +#define CASPER_MEM ((uint32_t *)msg_ret) +#define CASPER_OFFSET CASPER_NUM_LIMBS // offset in the CASPER memory where we can start writing + +#define MOD_SCRATCH_START (CASPER_OFFSET) +#define MOD_SCRATCH_SIZE (1 * CASPER_NUM_LIMBS) + +#define INOUT_SCRATCH_START (MOD_SCRATCH_START + MOD_SCRATCH_SIZE) +#define INOUT_SCRATCH_SIZE ((3 * 3) * CASPER_NUM_LIMBS) + +#define ECC_SCRATCH_START (INOUT_SCRATCH_START + INOUT_SCRATCH_SIZE) +#define ECC_SCRATCH_SIZE (9 * CASPER_NUM_LIMBS) + +#define LUT_SCRATCH_START (ECC_SCRATCH_START + ECC_SCRATCH_SIZE) +#define LUT_SCRATCH_SIZE (48 * NUM_LIMBS + 3 * CASPER_NUM_LIMBS) + +/* Currently these macros work on 32-bit platforms */ + +#define add(c1, c0, a, b) \ + \ +do \ + { \ + uint32_t _t; \ + _t = a + b; \ + c1 = (_t < a); \ + c0 = _t; \ + \ +} \ + while (0) + +#define add_cout(carry, c, a, b) add(carry, c, a, b) + +#define add_cout_cin(carryout, c, a, b, carryin) \ + do \ + { \ + uint64_t _t = (uint64_t)a + b + carryin; \ + c = (uint32_t)_t; \ + carryout = (uint32_t)(_t >> 32); \ + } while (0) + +#define sub_borrowout(borrow, c, a, b) \ + do \ + { \ + uint32_t _b = (b > a); \ + c = a - b; \ + borrow = _b; \ + } while (0) + +#define sub_borrowin_borrowout(borrowout, c, a, b, borrowin) \ + do \ + { \ + uint32_t _t, _borrow1, _borrow2; \ + sub_borrowout(_borrow1, _t, a, b); \ + sub_borrowout(_borrow2, c, _t, borrowin); \ + borrowout = _borrow1 + _borrow2; \ + } while (0) + +#define sub_borrowout_1(borrow, c, a) \ + do \ + { \ + uint32_t _b = 0; \ + c = a - b; \ + borrow = _b; \ + } while (0) + +#define sub_borrowin_borrowout_1(borrowout, c, a, borrowin) \ + do \ + { \ + uint32_t _t, _borrow1, _borrow2; \ + sub_borrowout_1(_borrow1, _t, a); \ + sub_borrowout(_borrow2, c, _t, borrowin); \ + borrowout = _borrow1 + _borrow2; \ + } while (0) + +/* 32 x 32 --> 64-bit multiplication +* (c1,c0) = a * b +*/ +#define mul(c1, c0, a, b) \ + \ +do \ + { \ + uint64_t __m; \ + __m = (uint64_t)a * (uint64_t)b; \ + c0 = (uint32_t)__m; \ + c1 = (uint32_t)(__m >> (uint64_t)32); \ + \ +} \ + while (0) + +/* Multiply-and-accumulate +* (c1,c0) = a*b+c0 + */ +#define muladd(c1, c0, a, b) \ + \ +do \ + { \ + uint32_t __ma = c0; \ + mul(c1, c0, a, b); \ + c0 = c0 + __ma; \ + c1 = c1 + (c0 < __ma); \ + \ +} \ + while (0) + +/* Multiply-and-accumulate-accumulate +* (c1,c0) = a*b+c0+c1 +*/ +#define muladdadd(c1, c0, a, b) \ + \ +do \ + { \ + uint32_t __maa0 = c0, __maa1 = c1; \ + mul(c1, c0, a, b); \ + c0 = c0 + __maa0; \ + c1 = c1 + (c0 < __maa0); \ + c0 = c0 + __maa1; \ + c1 = c1 + (c0 < __maa1); \ + \ +} \ + while (0) + +#if CASPER_ECC_P256 + +/* Recoding length for the secure scalar multiplication: +* Use n=256 and w=4 --> compute ciel(384/3) = 86 + 1 digits +*/ +#define CASPER_RECODE_LENGTH 87 +#define invert(c, a) invert_mod_p256(c, a) +#define ONE NISTr256 + +/* Shift right by 1 <= c <= 31. z[] and x[] in system RAM, no interleaving macros used. */ +#define shiftrightSysram(z, x, c) \ + do \ + { \ + z[0] = (x[1] << (32 - (c))) | (x[0] >> (c)); \ + z[1] = (x[2] << (32 - (c))) | (x[1] >> (c)); \ + z[2] = (x[3] << (32 - (c))) | (x[2] >> (c)); \ + z[3] = (x[4] << (32 - (c))) | (x[3] >> (c)); \ + z[4] = (x[5] << (32 - (c))) | (x[4] >> (c)); \ + z[5] = (x[6] << (32 - (c))) | (x[5] >> (c)); \ + z[6] = (x[7] << (32 - (c))) | (x[6] >> (c)); \ + z[7] = (x[7] >> (c)); \ + } while (0) + +#elif CASPER_ECC_P384 + +/* Recoding length for the secure scalar multiplication: + * Use n=384 and w=4 --> compute ciel(384/3) = 128 + 1 digits + */ +#define CASPER_RECODE_LENGTH 129 +#define invert(c, a) invert_mod_p384(c, a) +#define ONE NISTr384 + +/* Shift right by 1 <= c <= 31. z[] and x[] in system RAM, no interleaving macros used. */ +#define shiftrightSysram(z, x, c) \ + do \ + { \ + z[0] = (x[1] << (32 - (c))) | (x[0] >> (c)); \ + z[1] = (x[2] << (32 - (c))) | (x[1] >> (c)); \ + z[2] = (x[3] << (32 - (c))) | (x[2] >> (c)); \ + z[3] = (x[4] << (32 - (c))) | (x[3] >> (c)); \ + z[4] = (x[5] << (32 - (c))) | (x[4] >> (c)); \ + z[5] = (x[6] << (32 - (c))) | (x[5] >> (c)); \ + z[6] = (x[7] << (32 - (c))) | (x[6] >> (c)); \ + z[7] = (x[8] << (32 - (c))) | (x[7] >> (c)); \ + z[8] = (x[9] << (32 - (c))) | (x[8] >> (c)); \ + z[9] = (x[10] << (32 - (c))) | (x[9] >> (c)); \ + z[10] = (x[11] << (32 - (c))) | (x[10] >> (c)); \ + z[11] = (x[11] >> (c)); \ + } while (0) + +#else +#error "Define proper NIST curve" +#endif + +#define multiply_casper(c, a, b) MultprecCiosMul_ct(c, a, b, &CASPER_MEM[MOD_SCRATCH_START], Np) +#define square_casper(c, a) multiply_casper(c, a, a) +#define sub_casper(c, a, b) CASPER_montsub(c, a, b, &CASPER_MEM[MOD_SCRATCH_START]) +#define add_casper(c, a, b) CASPER_montadd(c, a, b, &CASPER_MEM[MOD_SCRATCH_START]) +#define mul2_casper(c, a) add_casper(c, a, a) +#define half(c, a, b) CASPER_half(c, a, b) +#define copy(c, a) CASPER_MEMCPY(c, a, NUM_LIMBS * sizeof(uint32_t)) + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/* The model for this algo is that it can be implemented for a fixed size RSA key */ +/* for max speed. If this is made into a variable (to allow varying size), then */ +/* it will be slower by a bit. */ +/* The file is compiled with N_bitlen passed in as number of bits of the RSA key */ +/* #define N_bitlen 2048 */ +static size_t N_wordlen = 0; /* ! number of words (e.g. 4096/32 is 128 words) */ + +static uint32_t s_casperRamBase = CASPER_RAM_BASE_NS; +static unsigned *msg_ret = (unsigned *)CASPER_RAM_BASE_NS; + +#if CASPER_ECC_P256 +/* NISTp-256 = 2^256-2^224+2^192+2^96-1 */ +static uint32_t NISTp256[NUM_LIMBS] = {0xffffffff, 0xffffffff, 0xffffffff, 0x00000000, + 0x00000000, 0x00000000, 0x00000001, 0xffffffff}; + +/* The cardinality of the curve E(F_p) */ +static uint32_t NISTp256_q[NUM_LIMBS] = {0xfc632551, 0xf3b9cac2, 0xa7179e84, 0xbce6faad, + 0xffffffff, 0xffffffff, 0x00000000, 0xffffffff}; + +/* R = 2^256 mod p, the value "1" in Montgomery form. */ +static uint32_t NISTr256[NUM_LIMBS] = {0x00000001, 0x00000000, 0x00000000, 0xffffffff, + 0xffffffff, 0xffffffff, 0xfffffffe, 0x00000000}; + +static uint32_t Np[2] = {1, 0}; +#endif /* CASPER_ECC_P256 */ + +#if CASPER_ECC_P384 +/* NISTp-384 = 2^384 - 2^128 - 2^96 + 2^32 - 1 */ +static uint32_t NISTp384[NUM_LIMBS] = {0xffffffff, 0x00000000, 0x00000000, 0xffffffff, 0xfffffffe, 0xffffffff, + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff}; + +/* The cardinality of the curve E(F_p) */ +static uint32_t NISTp384_q[NUM_LIMBS] = {0xccc52973, 0xecec196a, 0x48b0a77a, 0x581a0db2, 0xf4372ddf, 0xc7634d81, + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff}; + +/* R = 2^256 mod p, the value "1" in Montgomery form. */ +static uint32_t NISTr384[NUM_LIMBS] = {0x00000001, 0xffffffff, 0xffffffff, 0x00000000, 0x1, 0, 0, 0, 0, 0, 0, 0}; + +// -p^-1 mod 2^64 = 0x100000001 +static uint32_t Np[2] = {1, 1}; +#endif /* CASPER_ECC_P384 */ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/* Convert a projective point (X1 : Y1 : Z1) + * to the affine point (X3, Y3) = (X1/Z1^2,Y1/Z1^3) + * The memory of (X3, Y3) and (X1 : Y1 : Z1) should not overlap + */ +void Jac_toAffine(uint32_t *X3, uint32_t *Y3, uint32_t *X1, uint32_t *Y1, uint32_t *Z1); + +/* Return 1 if (X1: Y1: Z1) is on the curve +* Y^2 = X^3 -3XZ^4 + bZ^6 +* and return 0 otherwise. +*/ +int Jac_oncurve(uint32_t *X1, uint32_t *Y1, uint32_t *Z1, uint32_t *b); + +/* Compute (X3 : Y3: Z3) = (X1: Y1: Z1) + (X2 : Y2 : Z2) + * where (X1: Y1: Z1) != (X2 : Y2 : Z2) + * (X3 : Y3: Z3) may be the same as one of the inputs. + */ +void Jac_addition(uint32_t *X3, + uint32_t *Y3, + uint32_t *Z3, + uint32_t *X1, + uint32_t *Y1, + uint32_t *Z1, + uint32_t *X2, + uint32_t *Y2, + uint32_t *Z2); + +/* Compute (X3 : Y3: Z3) = (X1: Y1: Z1) + (X2, Y2) + * where (X1: Y1: Z1) != (X2, Y2) + * (X3 : Y3: Z3) may not overlap with (X1: Y1: Z1). + * Source: 2004 Hankerson–Menezes–Vanstone, page 91. + */ +void Jac_add_affine( + uint32_t *X3, uint32_t *Y3, uint32_t *Z3, uint32_t *X1, uint32_t *Y1, uint32_t *Z1, uint32_t *X2, uint32_t *Y2); + +/* Point doubling from: 2004 Hankerson–Menezes–Vanstone, page 91. + * Compute (X3 : Y3: Z3) = (X1: Y1: Z1) + (X1 : Y1 : Z1) + * (X3 : Y3: Z3) may be the same as the input. + */ +void Jac_double(uint32_t *X3, uint32_t *Y3, uint32_t *Z3, uint32_t *X1, uint32_t *Y1, uint32_t *Z1); + +/* Constant time elliptic curve scalar multiplication. + * Source: https://eprint.iacr.org/2014/130.pdf + * when using w = 4. + * Computes (X3 : Y3 : Z3) = k * (X1, Y1) \in E(F_p) + * p is the prime used to define the finite field F_p + * q is the (prime) order of the curve + */ +void Jac_scalar_multiplication( + uint32_t *X3, uint32_t *Y3, uint32_t *Z3, uint32_t *X1, uint32_t *Y1, uint32_t *k, uint32_t *p, uint32_t *q); + +/* Compute the double scalar multiplication +* (X3 : Y3 : Z3) = k1 * (X1, Y1) + k2 * (X2, Y2) +* Using Shamir's trick and precomputing 16 points. +* This code is *not* constant time since this is used +* for verification only. +*/ +void double_scalar_multiplication(uint32_t *X3, + uint32_t *Y3, + uint32_t *Z3, + uint32_t *X1, + uint32_t *Y1, + uint32_t *k1, + uint32_t *X2, + uint32_t *Y2, + uint32_t *k2); + +#if CASPER_ECC_P384 +/* Compute inversion modulo NIST-p384 using Fermats little theorem. + * Using c = a^(p-2) = a^(-1) mod p. + * This computes the modular inversion if all arithmetic is "regular" + * modular arithmetic or computes automatically the Montgomery inverse + * if all arithmetic is Montgomery arithmetic. + */ +static void invert_mod_p384(uint32_t *c, uint32_t *a); +#endif /* CASPER_ECC_P384 */ + +#if CASPER_ECC_P256 +/* Modular inversion for NIST-P256 */ +static void invert_mod_p256(uint32_t *c, uint32_t *a); +#endif /* CASPER_ECC_P256 */ + +// A and C do not need to be in Casper memory +static void toMontgomery(uint32_t *C, uint32_t *A); + +static void CASPER_montsub(uint32_t *C, uint32_t *A, uint32_t *B, uint32_t *mod); +static void CASPER_montadd(uint32_t *C, uint32_t *A, uint32_t *B, uint32_t *mod); + +/* Compute c = a/2 mod p where b is scratch space. */ +static void CASPER_half(uint32_t *c, uint32_t *a, uint32_t *b); + +static uint8_t int8abs(int8_t v); + +/* Constant time select c = a if m = 0 or +* c = b if m = 1 +* a, b, c are n words +*/ +static void casper_select(uint32_t *c, uint32_t *a, uint32_t *b, int m, int n); + +/* Dumb n-limb addition of c=a+b, return carry. */ +static uint32_t add_n_1(uint32_t *c, uint32_t *a, uint32_t b, int n); + +#if 0 +/* Dumb n-limb addition of c=a+b, return carry. */ +static uint32_t add_n(uint32_t *c, uint32_t *a, uint32_t *b, int n); + +/* Dumb n-limb subtraction of c=a-b, return borrow. */ +static uint32_t sub_n_1(uint32_t *c, uint32_t *a, uint32_t b, int n); +#endif + +/* Dumb n-limb subtraction of c=a-b, return borrow. */ +static uint32_t sub_n(uint32_t *c, uint32_t *a, uint32_t *b, int n); + +static void MultprecCiosMul_ct( + uint32_t w_out[], const uint32_t a[], const uint32_t b[], const uint32_t Nmod[], const uint32_t *Np); + +static void shiftright(uint32_t *z, uint32_t *x, int c); +static void shiftleft(uint32_t *z, uint32_t *x, int c); + +/******************************************************************************* + * Code + ******************************************************************************/ + +__STATIC_FORCEINLINE uint32_t CA_MK_OFF(const void *addr) +{ + return ((uint32_t)addr - s_casperRamBase); +} + +#if 1 +__STATIC_FORCEINLINE void Accel_done(void) +{ + register uint32_t status; + do + { + status = CASPER->STATUS; + } while (0 == (status & CASPER_STATUS_DONE_MASK)); +} + +__STATIC_FORCEINLINE void Accel_SetABCD_Addr(uint32_t ab, uint32_t cd) +{ + CASPER->CTRL0 = ab | (cd << 16); /* CDoffset << 16 | ABoffset */ +} + +__STATIC_FORCEINLINE void Accel_crypto_mul(uint32_t ctrl1) +{ + CASPER->CTRL1 = ctrl1; +} +#else +#include "intrinsics.h" +#define Accel_done() \ + { \ + register uint32_t status; \ + do \ + { \ + status = CASPER_Rd32b(CASPER_CP_STATUS); \ + } while (0 == (status & CASPER_STATUS_DONE_MASK)); \ + } +#if 0 +__STATIC_FORCEINLINE void Accel_done(void) +{ + register uint32_t status; + do + { + status = CASPER->STATUS; + } while (0 == (status & CASPER_STATUS_DONE_MASK)); +} +#endif +#define Accel_SetABCD_Addr(ab, cd) CASPER_Wr32b((uint32_t)ab | ((uint32_t)cd << 16), CASPER_CP_CTRL0); +#define Accel_crypto_mul(ctrl1) CASPER_Wr32b((uint32_t)ctrl1, CASPER_CP_CTRL1); +#endif + +__STATIC_FORCEINLINE uint32_t Accel_IterOpcodeResaddr(uint32_t iter, uint32_t opcode, uint32_t resAddr) +{ + return CASPER_CTRL1_ITER(iter) | CASPER_CTRL1_MODE(opcode) | (resAddr << 16); +} + +void CASPER_MEMCPY(void *dst, const void *src, size_t siz) +{ + bool bdst = ((((uint32_t)dst) | 0x10000000u) >= (FSL_FEATURE_CASPER_RAM_BASE_ADDRESS | 0x10000000u) && + (((uint32_t)dst) | 0x10000000u) < (FSL_FEATURE_CASPER_RAM_BASE_ADDRESS | 0x10000000u) + 8u * 1024u); + + bool bsrc = ((((uint32_t)src) | 0x10000000u) >= (FSL_FEATURE_CASPER_RAM_BASE_ADDRESS | 0x10000000u) && + (((uint32_t)src) | 0x10000000u) < (FSL_FEATURE_CASPER_RAM_BASE_ADDRESS | 0x10000000u) + 8u * 1024u); + + if (bdst && bsrc) + { + CASPER_MEMCPY_I2I(dst, src, siz); + } + else if (bdst && !bsrc) + { + CASPER_MEMCPY_N2I(dst, src, siz); + } + else if (!bdst && bsrc) + { + CASPER_MEMCPY_I2N(dst, src, siz); + } + else + { + memcpy(dst, src, siz); + } +} + +/* Constant time select c = a if m = 0 or + * c = b if m = 1 + * a, b, c are n words + */ +static void casper_select(uint32_t *c, uint32_t *a, uint32_t *b, int m, int n) +{ + uint32_t m1 = 0 - m, m2 = ~m1; + int i; + + for (i = 0; i < n; i++) + { + SET_WORD(&c[i], (GET_WORD(&a[i]) & m2) | (GET_WORD(&b[i]) & m1)); + } +} + +/* Compute R`, which is R mod N. This is done using subtraction */ +/* R has 1 in N_wordlen, but we do not fill it in since borrowed. */ +/* Exp-pubkey only used to optimize for exp=3 */ +void MultprecMontCalcRp(unsigned Rp[], const unsigned exp_pubkey, const unsigned Nmod[]) +{ + int i; + + /* R is 2^n where n is 1 bit longer than Nmod, so 1 followed by 32 or 64 0 words for example */ + /* Note that Nmod's upper most bit has to be 1 by definition, so one subtract is enough. We */ + /* do not set the 1 since it is "borrowed" so no point */ + PreZeroW(i, Rp); + Accel_SetABCD_Addr(CA_MK_OFF(Nmod), 0); + Accel_crypto_mul(Accel_IterOpcodeResaddr(N_dwordlen - 1, kCASPER_OpSub64, CA_MK_OFF(Rp))); + Accel_done(); + /* final borrow cannot happen since we know we started with a larger number */ +} + +/* MultprecMultiply - multiple w=u*v (per Knuth) */ +/* w_out is 2x the size of u and v */ +void MultprecMultiply(unsigned w_out[], const unsigned u[], const unsigned v[]) +{ + int i, j; + + /* Knuth 4.3.1 - Algorithm M */ + /* Compute w = u * v */ + /* u and v are N bits long in 32 bit word form */ + /* w is 2*N bits long in 32 bit word form */ + /* Note: We just multiply in place */ + + /* Step 1. Fill w[t-1:0] with 0s, the upper half will be written as we go */ + PreZeroW(i, w_out); + + /* We do 1st pass NOSUM so we do not have to 0 output */ + Accel_SetABCD_Addr(CA_MK_OFF(&v[0]), CA_MK_OFF(u)); + Accel_crypto_mul(Accel_IterOpcodeResaddr(N_wordlen / 2 - 1, kCASPER_OpMul6464NoSum, CA_MK_OFF(&w_out[0]))); + Accel_done(); + /* Step 2. iterate over N words of v using j */ + for (j = 2; j < N_wordlen; j += 2) + { + /* Step 2b. Check for 0 on v word - skip if so since we 0ed already */ + /* Step 3. Iterate over N words of u using i - perform Multiply-accumulate */ + if (GET_WORD(&v[j]) || GET_WORD(&v[j + 1])) + { + Accel_SetABCD_Addr(CA_MK_OFF(&v[j]), CA_MK_OFF(u)); + Accel_crypto_mul(Accel_IterOpcodeResaddr(N_wordlen / 2 - 1, kCASPER_OpMul6464Sum, CA_MK_OFF(&w_out[j]))); + Accel_done(); + } + } +} + +/* MultprecModulo performs divide to get remainer as needed for RSA */ +/* This performs (q,r) = u/v, but we do not keep q */ +/* r_out is module (remainder) and is 2*N */ +/* u is in r_out (1st N) at start (passed in) */ +/* v is N long */ +void MultprecModulo(unsigned r_out[], const unsigned v[], int top) +{ + uint64_t u64; /* use 64 bit math mixed with 32 bit */ + unsigned u32; /* allows us to work on U in 32 bit */ + unsigned u_n, ul16, uh16, *u_shft; /* u_shft is because r_out is u initially */ + unsigned vl16, vh16, v_Nm1; + unsigned q_hat, r_hat, q_over; + unsigned borrow, carry; + int i, j, tmp; + + /* Knuth 4.3.1 - Algorithm D */ + /* Compute q = u / v giving remainder r = u mod v */ + /* -- we only want r, so we build qhat but do not store the Qs */ + /* v is N long, with u,q,r 2N long because u is slowly replavced by r. */ + /* We normalize/unnormlize per Knuth in the buffer (not copied) */ + + /* Step 1. Normalize value so MSb is in v[n-1]. Remember that v is */ + /* the public key - to call it a 2048 bit number, they cannot have 0 */ + /* in the MSb (or it would be less than 2048 bits) and so we know we */ + /* are normalized already. Therefore, u is effectively shifted already. */ + /* For u, we have it in r_out. u[n] holds any overflow */ + /* Since divide on CM3/4 is 32/32=32, we break into 16 bit halves, but */ + /* multiply can be 32x32=64. */ + u_n = 0; + u_shft = r_out; /* u (shifted) is in r_out */ + + v_Nm1 = GET_WORD(&v[N_wordlen - 1]); /* MSw of public key */ + vl16 = v_Nm1 & 0xFFFF; /* lower 16 */ + vh16 = v_Nm1 >> 16; /* upper 16 */ + /* Step 2. Iterate j from m-n down to 0 (M selected per Knuth as 2*N) */ + for (j = top; j >= 0; j--) + { + /* Step 3. estimate q_hat as (U[j+n]*B + U[j+n-1]) / V[n-1] */ + /* Note: using subset of Knuth algo since v is 1/2 len of u (which is */ + /* from multiply or x^2 leading into this). */ + u32 = u_n; /* pickup u4u3u2, knowing u4 is 0 */ + u64 = ((uint64_t)u_n << 32) | GET_WORD(&u_shft[j + N_wordlen - 1]); + ul16 = u64 & 0xFFFF; /* lower 16 */ + uh16 = (u64 >> 16) & 0xFFFF; /* upper 16 */ + + /* we see if even possible (u large enough relative to v) */ + if ((u32 - v_Nm1) <= u32) + { + u32 -= v_Nm1; + q_over = 1; /* overflow from the sub */ + } + else + q_over = 0; + + /* q_hat = u32 / vh16 -- is the upper partial value */ + /* estimate; if too much, then back down by 1 or 2 */ + q_hat = u32 / vh16; + r_hat = u32 - (q_hat * vh16); + /* see if Q is more than 16 bits or remainder is too large (over div) */ + if ((q_hat == 0x10000) || ((q_hat * vl16) > ((r_hat << 16) | uh16))) + { + /* too much - undo a division */ + q_hat--; + r_hat += vh16; + /* check if still too much */ + if ((r_hat < 0x10000) && ((q_hat * vl16) > ((r_hat << 16) | uh16))) + q_hat--; /* yes, so undo a 2nd */ + } + + /* compose u3u2uh16, then sub q_hat*v if OK */ + u64 = (((uint64_t)u32 << 16) | uh16) - ((uint64_t)q_hat * v_Nm1); + if (u64 >> 48) + { + /* no, so add v back */ + u32 = (unsigned)(u64 + v_Nm1); + q_hat--; + } + else + u32 = (unsigned)u64; + + tmp = q_hat << 16; /* quotient upper part */ + + /* divide lower part: q = u2uh16ul16 / v. */ + /* estimate and add back if over divdied */ + q_hat = u32 / vh16; + r_hat = u32 - (q_hat * vh16); + if ((q_hat == 0x10000) || ((q_hat * vl16) > ((r_hat << 16) | ul16))) + { + /* too much - undo a division */ + q_hat--; + r_hat += vh16; + /* check if still too much */ + if ((r_hat < 0x10000) && ((q_hat * vl16) > ((r_hat << 16) | ul16))) + q_hat--; /* yes, so undo a 2nd */ + } + + /* compose u2uh16ul16, then sub q_hat*v if OK */ + u64 = (((uint64_t)u32 << 16) | ul16) - ((uint64_t)q_hat * v_Nm1); + if (u64 >> 48) + { + /* no, so add v back */ + r_hat = (unsigned)(u64 + v_Nm1); + q_hat--; + } + else + r_hat = (unsigned)u64; + + q_hat |= tmp; /* other half of the quotient */ + while (q_over || + ((uint64_t)q_hat * GET_WORD(&v[N_wordlen - 2])) > + ((1LL << 32) * r_hat) + (uint64_t)GET_WORD(&u_shft[j + N_wordlen - 2])) + { /* if Qhat>b, then reduce to b-1, then adjust up Rhat */ + q_hat--; + r_hat += v_Nm1; + if (r_hat < v_Nm1) + break; /* no overflow */ + /* else repeat since Rhat >= b */ + } + + /* Step 4. Multiply and subtract. We know the amount, */ + /* so we do the schoolboy math. Have to do on */ + /* the large value. */ + if (q_hat) + { + borrow = 0; + for (i = 0; i < N_wordlen; i++) + { + u64 = (uint64_t)q_hat * GET_WORD(&v[i]) + borrow; + borrow = (unsigned)(u64 >> 32); + if (GET_WORD(&u_shft[i + j]) < (unsigned)u64) + borrow++; /* carry the overflow */ + SET_WORD(&u_shft[i + j], GET_WORD(&u_shft[i + j]) - (unsigned)u64); + } + u_n -= borrow; /* overflow from shift left does not fit otherwise */ + } + + /* Store 5. (update Q - we don't), and add back V to remainder if we over-subtracted */ + /* That restores remainder to correct (we could only be off by 1) */ + /* This should happen very rarely. */ + if (u_n) + { + carry = 0; + for (i = 0; i < N_wordlen; i++) + { + SET_WORD(&u_shft[i + j], GET_WORD(&u_shft[i + j]) + carry); + carry = (GET_WORD(&u_shft[i + j]) < carry) ? 1 : 0; + SET_WORD(&u_shft[i + j], GET_WORD(&u_shft[i + j]) + GET_WORD(&v[i])); + if (GET_WORD(&u_shft[i + j]) < GET_WORD(&v[i])) + carry++; + } + } + u_n = GET_WORD(&u_shft[j + N_wordlen - 1]); /* hold upper part of u to catch overflow (to borrow from) */ + } + /* low N bits of r are valid as remainder */ +} + +/* We convert X into a Mont form number. Note length of arrays: */ +/* x is N_wordlen, Nmod is N_wordlen */ +/* Rp is N_wordlen (it is R` which is R mod N) */ +/* Xmont_out is N_wordlen*2+1 */ +void MultprecMontPrepareX(unsigned Xmont_out[], const unsigned x[], const unsigned Rp[], const unsigned Nmod[]) +{ + MultprecMultiply(Xmont_out, x, Rp); + MultprecModulo(Xmont_out, Nmod, N_wordlen); +} + +void MultprecGenNp64(const unsigned *Nmod, unsigned *np64_ret) /* only pass the low order double word */ +{ + uint64_t nprime, Nmod_0; + Nmod_0 = GET_WORD(&Nmod[0]) | ((uint64_t)GET_WORD(&Nmod[1]) << 32); + +#define COMP_NPN_1 ((2 - Nmod_0 * nprime) * nprime) /* computes N`*N0=1 mod 2^P where P is the partial built up */ + nprime = (((2 + Nmod_0) & 4) << 1) + Nmod_0; /* mod 2^4 */ + nprime = COMP_NPN_1; + nprime = COMP_NPN_1; + nprime = COMP_NPN_1; + nprime = COMP_NPN_1; + /* 8 multiplies of uint64_t */ + *((uint64_t *)np64_ret) = (~0LL - nprime) + 1LL; +} + +/* CIOS Multiply. This is the Coarse Integrated form where the values are */ +/* multiplied and reduced for each step of "i". This uses less memory and */ +/* is faster as a result. Note that this is used to square as well as mul, */ +/* so not as fast as pure squaring could be. */ +void MultprecCiosMul( + unsigned w_out[], const unsigned a[], const unsigned b[], const unsigned Nmod[], const unsigned *Np) +{ + int i, j; + uint64_t *m64 = (uint64_t *)&msg_ret[kCASPER_RamOffset_M64]; + uint64_t Np64; + uint64_t carry; + uint64_t *a64, *b64, *w64, *N64; + + Np64 = *(uint64_t *)Np; + + a64 = (uint64_t *)a; + b64 = (uint64_t *)b; + w64 = (uint64_t *)w_out; + N64 = (uint64_t *)Nmod; + + if (a) + { /* if !a, we are reducing only */ + PreZeroW(i, w_out); + } + SET_DWORD(&w64[N_dwordlen], 0); + SET_DWORD(&w64[N_dwordlen + 1], 0); + /* with accelerator */ + + /* loop i and then reduce after each j round */ + for (i = 0; i < N_dwordlen; i++) + { + /* Step 3. Iterate over N words of u using i - perform Multiply-accumulate */ + /* push-pull: we do a*b and then separately m*n (reduce) */ + if (a) + { /* if mul&reduce vs. reduce only */ + carry = GET_DWORD(&w64[N_dwordlen]); + Accel_SetABCD_Addr(CA_MK_OFF(&b64[i]), CA_MK_OFF(a64)); + Accel_crypto_mul(Accel_IterOpcodeResaddr(N_dwordlen - 1, kCASPER_OpMul6464FullSum, CA_MK_OFF(w64))); + Accel_done(); + /* max carry is contained since ~0*~0=0xFFFE0001+0xFFFF=0xFFFF0000, */ + /* so max carry is 0xFFFF and 0xFFFF0000+0xFFFF=0xFFFFFFFF */ + /* accel took care of w_out[N_wordlen] & +1, so we just take care of the next double word if carry=1 */ + /* w64[N_dwordlen+1] = g_carry; */ + carry = (GET_DWORD(&w64[N_dwordlen]) < carry); + SET_DWORD(&w64[N_dwordlen + 1], carry); + } + SET_DWORD(&m64[0], GET_DWORD(&w64[0]) * Np64); /* prime for 1st; modulo a double-word */ + + /* we are reducing, so the 1st [0th] 64 bit value product is tossed, but we */ + /* need its carry. We let the accel do this separately - really need a mode to */ + /* do this "reduce" since it is natural */ + carry = GET_DWORD(&w64[N_dwordlen]); + Accel_SetABCD_Addr(CA_MK_OFF(m64), CA_MK_OFF(&N64[0])); + Accel_crypto_mul(Accel_IterOpcodeResaddr(N_dwordlen - 1, kCASPER_OpMul6464FullSum, CA_MK_OFF(&w64[0]))); + Accel_done(); + carry = (GET_DWORD(&w64[N_dwordlen]) < carry); + + Accel_SetABCD_Addr(CA_MK_OFF(&w64[1]), 0); + Accel_crypto_mul(Accel_IterOpcodeResaddr(N_dwordlen - 1, kCASPER_OpCopy, CA_MK_OFF(&w64[0]))); + + Accel_done(); + SET_DWORD(&w64[N_dwordlen], (GET_DWORD(&w64[N_dwordlen + 1]) + carry)); + } + + /* now check if need to subtract Nmod */ + if (GET_WORD(&w_out[N_wordlen])) + j = 1; /* we have to subtract for sure if carry up */ + else + { + j = 0; + for (i = N_wordlen - 1; i >= 0; i--) + if (GET_WORD(&w_out[i]) != GET_WORD(&Nmod[i])) + { + j = GET_WORD(&w_out[i]) > GET_WORD(&Nmod[i]); /* if larger sub */ + break; /* we would remove the break if worrying about side channel */ + } + } + if (!j) + return; /* Is smaller than Nmod, so done. */ + Accel_SetABCD_Addr(CA_MK_OFF(Nmod), 0); + Accel_crypto_mul(Accel_IterOpcodeResaddr(N_dwordlen - 1, kCASPER_OpSub64, CA_MK_OFF(w_out))); + Accel_done(); + /* last borrow is OK since we know it could only be <2N and */ +} + +/* RSA_MontSignatureToPlaintextFast: */ +/* MsgRet[] = Message return buffer - must be large enough to hold input and output (4*N+2) */ +/* exp_pubkey = the "e" that the value is raised to. Usually 3 or 0x10001. */ +/* signature = N bitpos len long "message" to process in Montgomery form - so saving conversion (divide) */ +/* pubkey = N bitpos len long public key to process signature with */ +/* returns: 0 */ +/* */ +/* Algo: compute M = signaturen^e mod public_key */ +/* where M is original plaintext, signature is signed value */ +/* note: e is usually either 0x3 or 0x10001 */ +int RSA_MontSignatureToPlaintextFast(const unsigned mont_signature[N_wordlen_max], + const unsigned exp_pubkey, + const unsigned pubkey[N_wordlen_max], + unsigned MsgRet[WORK_BUFF_MUL4]) +{ + int bidx = 0; + int bitpos; + unsigned np64[2]; + + /* MsgRet working area: */ + /* 0..N = RESULT, starting with S` */ + /* N..N*2 = S` and then working BASE during math. */ + /* N*2..N*4+2 = temp working area for Mont mul */ + + /* 1. Copy sig into MsgRet so we have one working result buffer */ + CASPER_MEMCPY_I2I(&MsgRet[kCASPER_RamOffset_Result], mont_signature, N_bytelen); + MultprecGenNp64(pubkey, np64); /* Generate N` from LSW of N (LSW being lowest 64b word) */ + bitpos = 31 - __CLZ(exp_pubkey); /* count of bits after the left most 1 */ + while (--bitpos >= 0) + { + /* This operates on: */ + /* result = 1; */ + /* base = signature */ + /* loop while exponent bits from MSb to LSb */ + /* if (exp bit is 1) */ + /* result = result * base */ + /* base = base^2 */ + /* Because the MSb of exp is always 1 by definition, we can invert this a bit: */ + /* base = signature` */ + /* result = base; equivalent to result = 1*base from 1st pass, but now square is needed 1st */ + /* loop while exponent bits from MSb-1 to LSb */ + /* base = base^2 */ + /* if (exp bit is 1) */ + /* result = result * base */ + /* This ends up doing the same thing but skips two wasteful steps of multiplying by 1 and */ + /* a final squaring never used. */ + /* */ + /* Next we have the problem that CIOS mul needs a separate dest buffer. So, we bounce */ + /* base between base and temp, and likewise for result. */ + MultprecCiosMul(&MsgRet[bidx ? kCASPER_RamOffset_Base : kCASPER_RamOffset_TempBase], + &MsgRet[bidx ? kCASPER_RamOffset_TempBase : kCASPER_RamOffset_Base], + &MsgRet[bidx ? kCASPER_RamOffset_TempBase : kCASPER_RamOffset_Base], pubkey, np64); + if (exp_pubkey & (1 << bitpos)) /* where e is 1 */ + { + /* result has result, so we need to work into other temp area */ + MultprecCiosMul(&MsgRet[bidx ? kCASPER_RamOffset_TempBase : kCASPER_RamOffset_Base], + &MsgRet[kCASPER_RamOffset_Result], + &MsgRet[bidx ? kCASPER_RamOffset_Base : kCASPER_RamOffset_TempBase], pubkey, np64); + /* we have to copy back to result */ + + // CASPER_MEMCPY_I2I(&MsgRet[kCASPER_RamOffset_Result], + // &MsgRet[bidx ? kCASPER_RamOffset_TempBase : kCASPER_RamOffset_Base], N_bytelen); + } + else + bidx = ~bidx; + } + + CASPER_MEMCPY_I2I(&MsgRet[kCASPER_RamOffset_Result], + &MsgRet[bidx ? kCASPER_RamOffset_TempBase : kCASPER_RamOffset_Base], N_bytelen); + + /* final step is one more reduction to get back to normal form (ie. divide R out) */ + MultprecCiosMul(&MsgRet[kCASPER_RamOffset_Result], NULL, NULL, pubkey, np64); + return (0); /* always 0 */ +} + +/* RSA_SignatureToPlaintextFast: */ +/* MsgRet[] = Message return buffer - must be large enough to hold input and output (4*N+2) */ +/* exp_pubkey = the "e" that the value is raised to. Usually 3 or 0x10001. */ +/* signature = N bitpos len long "message" to process in normal form - so converted to Mont form */ +/* pubkey = N bitpos len long public key to process signature with */ +/* returns: 0 */ +/* */ +/* Algo: compute M = signaturen^e mod public_key */ +/* where M is original plaintext, signature is signed value */ +/* note: e is usually either 0x3 or 0x10001 */ +int RSA_SignatureToPlaintextFast(const unsigned signature[N_wordlen_max], + const unsigned exp_pubkey, + const unsigned pubkey[N_wordlen_max], + unsigned MsgRet[WORK_BUFF_MUL4]) +{ + /* MsgRet working area: */ + /* 0..N = RESULT, starting with S`; it is used for R` just during creation of S` */ + /* N..N*2 = S` and then working BASE during math. Note overflow beyond N*2 when making S` */ + /* N*2..N*4+2 = temp working area for Mont mul */ + + MultprecMontCalcRp(&MsgRet[kCASPER_RamOffset_Result], exp_pubkey, pubkey); /* calculate R` (=R mod N) */ + MultprecMontPrepareX(&MsgRet[kCASPER_RamOffset_Base], signature, &MsgRet[kCASPER_RamOffset_Result], + pubkey); /* X*R1` mod N */ + return (RSA_MontSignatureToPlaintextFast(&MsgRet[kCASPER_RamOffset_Base], exp_pubkey, pubkey, MsgRet)); +} + +/*! + * brief Performs modular exponentiation - (A^E) mod N. + * + * This function performs modular exponentiation. + * + * param base CASPER base address + * param signature first addend (in little endian format) + * param pubN modulus (in little endian format) + * param wordLen Size of pubN in bytes + * param pubE exponent + * param[out] plaintext Output array to store result of operation (in little endian format) + */ +void CASPER_ModExp( + CASPER_Type *base, const uint8_t *signature, const uint8_t *pubN, size_t wordLen, uint32_t pubE, uint8_t *plaintext) +{ +#define PK_LOC &msg_ret[kCASPER_RamOffset_Modulus] +#define SIG_LOC &msg_ret[kCASPER_RamOffset_Modulus + N_wordlen_max] + + N_wordlen = wordLen; /* set global variable for key length - used by RSA_SignatureToPlaintextFast() */ + CASPER_MEMCPY_N2I(PK_LOC, pubN, N_bytelen); + CASPER_MEMCPY_N2I(SIG_LOC, signature, N_bytelen); + RSA_SignatureToPlaintextFast((const unsigned *)(SIG_LOC), pubE, (const unsigned *)(PK_LOC), msg_ret); + + CASPER_MEMCPY_I2N(plaintext, msg_ret, N_bytelen); +} + +/*! + * brief Enables clock and disables reset for CASPER peripheral. + * + * Enable clock and disable reset for CASPER. + * + * param base CASPER base address + */ +void CASPER_Init(CASPER_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + CLOCK_EnableClock(kCLOCK_Casper); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + RESET_PeripheralReset(kCASPER_RST_SHIFT_RSTn); + /* If Casper init is called with secure address, use secure addres also for accessing Casper RAM. */ + s_casperRamBase = CASPER_RAM_BASE_NS | ((uint32_t)base & 0x10000000u); + msg_ret = (unsigned *)s_casperRamBase; +} + +/*! + * brief Disables clock for CASPER peripheral. + * + * Disable clock and enable reset. + * + * param base CASPER base address + */ +void CASPER_Deinit(CASPER_Type *base) +{ + RESET_SetPeripheralReset(kCASPER_RST_SHIFT_RSTn); +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + CLOCK_DisableClock(kCLOCK_Casper); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/* New ECC code which uses Casper. */ + +/* Set the prime modulus mod in Casper memory. + */ +void CASPER_ecc_init(void) +{ +#if CASPER_ECC_P256 + N_wordlen = 256 / 32; + uint32_t *mod = NISTp256; +#elif CASPER_ECC_P384 + N_wordlen = 384 / 32; + uint32_t *mod = NISTp384; +#endif + CASPER_MEMCPY(&CASPER_MEM[MOD_SCRATCH_START], mod, NUM_LIMBS * sizeof(uint32_t)); + uint8_t a[(CASPER_NUM_LIMBS - NUM_LIMBS) * sizeof(uint32_t)] = {0}; + CASPER_MEMCPY(&CASPER_MEM[MOD_SCRATCH_START + NUM_LIMBS], a, (CASPER_NUM_LIMBS - NUM_LIMBS) * sizeof(uint32_t)); +} + +void CASPER_ECC_equal(int *res, uint32_t *op1, uint32_t *op2) +{ + uint32_t a[NUM_LIMBS]; + uint32_t b[NUM_LIMBS]; + int c = 0; + CASPER_MEMCPY(a, op1, NUM_LIMBS * sizeof(uint32_t)); + CASPER_MEMCPY(b, op2, NUM_LIMBS * sizeof(uint32_t)); + + do + { + int _i; + c = a[0] ^ b[0]; + for (_i = 1; _i < NUM_LIMBS; _i++) + { + c |= (a[_i] ^ b[_i]); + } + } while (0); + + *res = c; +} + +void CASPER_ECC_equal_to_zero(int *res, uint32_t *op1) +{ + uint32_t a[NUM_LIMBS]; + int c = 0; + CASPER_MEMCPY(a, op1, NUM_LIMBS * sizeof(uint32_t)); + + do + { + int _i; + c = a[0]; + for (_i = 1; _i < NUM_LIMBS; _i++) + { + c |= a[_i]; + } + } while (0); + + *res = c; +} + +#if CASPER_ECC_P256 +void CASPER_ECC_SECP256R1_Mul( + CASPER_Type *base, uint32_t resX[8], uint32_t resY[8], uint32_t X[8], uint32_t Y[8], uint32_t scalar[8]) +{ + uint32_t X1[8] = {0}; + uint32_t Y1[8] = {0}; + toMontgomery(X1, X); + toMontgomery(Y1, Y); + + CASPER_MEMCPY(&CASPER_MEM[INOUT_SCRATCH_START + 0 * CASPER_NUM_LIMBS], X1, NUM_LIMBS * sizeof(uint32_t)); + CASPER_MEMCPY(&CASPER_MEM[INOUT_SCRATCH_START + 1 * CASPER_NUM_LIMBS], Y1, NUM_LIMBS * sizeof(uint32_t)); + + Jac_scalar_multiplication(&CASPER_MEM[INOUT_SCRATCH_START + 6 * CASPER_NUM_LIMBS], + &CASPER_MEM[INOUT_SCRATCH_START + 7 * CASPER_NUM_LIMBS], + &CASPER_MEM[INOUT_SCRATCH_START + 8 * CASPER_NUM_LIMBS], + &CASPER_MEM[INOUT_SCRATCH_START + 0 * CASPER_NUM_LIMBS], + &CASPER_MEM[INOUT_SCRATCH_START + 1 * CASPER_NUM_LIMBS], scalar, NISTp256, NISTp256_q); + + Jac_toAffine(&CASPER_MEM[INOUT_SCRATCH_START + 3 * CASPER_NUM_LIMBS], + &CASPER_MEM[INOUT_SCRATCH_START + 4 * CASPER_NUM_LIMBS], + &CASPER_MEM[INOUT_SCRATCH_START + 6 * CASPER_NUM_LIMBS], + &CASPER_MEM[INOUT_SCRATCH_START + 7 * CASPER_NUM_LIMBS], + &CASPER_MEM[INOUT_SCRATCH_START + 8 * CASPER_NUM_LIMBS]); + + /* Montgomery to Normal */ + /* X_normal = 1 * X_montgomery; Y_normal = 1 * Y_montgomery */ + uint32_t one[CASPER_NUM_LIMBS] = {0x0}; + one[0] = 0x1u; + CASPER_MEMCPY(&CASPER_MEM[INOUT_SCRATCH_START + 0 * CASPER_NUM_LIMBS], one, CASPER_NUM_LIMBS * sizeof(uint32_t)); + multiply_casper(&CASPER_MEM[INOUT_SCRATCH_START + 5 * CASPER_NUM_LIMBS], + &CASPER_MEM[INOUT_SCRATCH_START + 3 * CASPER_NUM_LIMBS], + &CASPER_MEM[INOUT_SCRATCH_START + 0 * CASPER_NUM_LIMBS]); + multiply_casper(&CASPER_MEM[INOUT_SCRATCH_START + 6 * CASPER_NUM_LIMBS], + &CASPER_MEM[INOUT_SCRATCH_START + 4 * CASPER_NUM_LIMBS], + &CASPER_MEM[INOUT_SCRATCH_START + 0 * CASPER_NUM_LIMBS]); + + /* copy out to result */ + CASPER_MEMCPY(resX, &CASPER_MEM[INOUT_SCRATCH_START + 5 * CASPER_NUM_LIMBS], NUM_LIMBS * sizeof(uint32_t)); + CASPER_MEMCPY(resY, &CASPER_MEM[INOUT_SCRATCH_START + 6 * CASPER_NUM_LIMBS], NUM_LIMBS * sizeof(uint32_t)); +} + +void CASPER_ECC_SECP256R1_MulAdd(CASPER_Type *base, + uint32_t resX[8], + uint32_t resY[8], + uint32_t X1[8], + uint32_t Y1[8], + uint32_t scalar1[8], + uint32_t X2[8], + uint32_t Y2[8], + uint32_t scalar2[8]) +{ + uint32_t zeroes[CASPER_NUM_LIMBS] = {0}; + + CASPER_MEMCPY(&CASPER_MEM[INOUT_SCRATCH_START + 0 * CASPER_NUM_LIMBS], X1, NUM_LIMBS * sizeof(uint32_t)); + CASPER_MEMCPY(&CASPER_MEM[INOUT_SCRATCH_START + 1 * CASPER_NUM_LIMBS], Y1, NUM_LIMBS * sizeof(uint32_t)); + + CASPER_MEMCPY(&CASPER_MEM[INOUT_SCRATCH_START + 2 * CASPER_NUM_LIMBS], X2, NUM_LIMBS * sizeof(uint32_t)); + CASPER_MEMCPY(&CASPER_MEM[INOUT_SCRATCH_START + 3 * CASPER_NUM_LIMBS], Y2, NUM_LIMBS * sizeof(uint32_t)); + + toMontgomery(&CASPER_MEM[INOUT_SCRATCH_START + 0 * CASPER_NUM_LIMBS], + &CASPER_MEM[INOUT_SCRATCH_START + 0 * CASPER_NUM_LIMBS]); + toMontgomery(&CASPER_MEM[INOUT_SCRATCH_START + 1 * CASPER_NUM_LIMBS], + &CASPER_MEM[INOUT_SCRATCH_START + 1 * CASPER_NUM_LIMBS]); + toMontgomery(&CASPER_MEM[INOUT_SCRATCH_START + 2 * CASPER_NUM_LIMBS], + &CASPER_MEM[INOUT_SCRATCH_START + 2 * CASPER_NUM_LIMBS]); + toMontgomery(&CASPER_MEM[INOUT_SCRATCH_START + 3 * CASPER_NUM_LIMBS], + &CASPER_MEM[INOUT_SCRATCH_START + 3 * CASPER_NUM_LIMBS]); + + CASPER_MEMCPY(&CASPER_MEM[INOUT_SCRATCH_START + 4 * CASPER_NUM_LIMBS], zeroes, CASPER_NUM_LIMBS * sizeof(uint32_t)); + CASPER_MEMCPY(&CASPER_MEM[INOUT_SCRATCH_START + 5 * CASPER_NUM_LIMBS], zeroes, CASPER_NUM_LIMBS * sizeof(uint32_t)); + CASPER_MEMCPY(&CASPER_MEM[INOUT_SCRATCH_START + 6 * CASPER_NUM_LIMBS], zeroes, CASPER_NUM_LIMBS * sizeof(uint32_t)); + double_scalar_multiplication(&CASPER_MEM[INOUT_SCRATCH_START + 4 * CASPER_NUM_LIMBS], + &CASPER_MEM[INOUT_SCRATCH_START + 5 * CASPER_NUM_LIMBS], + &CASPER_MEM[INOUT_SCRATCH_START + 6 * CASPER_NUM_LIMBS], + &CASPER_MEM[INOUT_SCRATCH_START + 0 * CASPER_NUM_LIMBS], + &CASPER_MEM[INOUT_SCRATCH_START + 1 * CASPER_NUM_LIMBS], scalar1, + &CASPER_MEM[INOUT_SCRATCH_START + 2 * CASPER_NUM_LIMBS], + &CASPER_MEM[INOUT_SCRATCH_START + 3 * CASPER_NUM_LIMBS], scalar2); + + Jac_toAffine(&CASPER_MEM[LUT_SCRATCH_START + 0 * CASPER_NUM_LIMBS], + &CASPER_MEM[LUT_SCRATCH_START + 1 * CASPER_NUM_LIMBS], + &CASPER_MEM[INOUT_SCRATCH_START + 4 * CASPER_NUM_LIMBS], + &CASPER_MEM[INOUT_SCRATCH_START + 5 * CASPER_NUM_LIMBS], + &CASPER_MEM[INOUT_SCRATCH_START + 6 * CASPER_NUM_LIMBS]); + + uint32_t one[CASPER_NUM_LIMBS] = {0x0}; + one[0] = 0x1u; + CASPER_MEMCPY(&CASPER_MEM[INOUT_SCRATCH_START + 0 * CASPER_NUM_LIMBS], one, CASPER_NUM_LIMBS * sizeof(uint32_t)); + multiply_casper(&CASPER_MEM[INOUT_SCRATCH_START + 1 * CASPER_NUM_LIMBS], + &CASPER_MEM[LUT_SCRATCH_START + 0 * CASPER_NUM_LIMBS], + &CASPER_MEM[INOUT_SCRATCH_START + 0 * CASPER_NUM_LIMBS]); + multiply_casper(&CASPER_MEM[INOUT_SCRATCH_START + 2 * CASPER_NUM_LIMBS], + &CASPER_MEM[LUT_SCRATCH_START + 1 * CASPER_NUM_LIMBS], + &CASPER_MEM[INOUT_SCRATCH_START + 0 * CASPER_NUM_LIMBS]); + + CASPER_MEMCPY(resX, (&CASPER_MEM[INOUT_SCRATCH_START + 1 * CASPER_NUM_LIMBS]), NUM_LIMBS * sizeof(uint32_t)); + CASPER_MEMCPY(resY, (&CASPER_MEM[INOUT_SCRATCH_START + 2 * CASPER_NUM_LIMBS]), NUM_LIMBS * sizeof(uint32_t)); +} +#endif /* CASPER_ECC_P256 */ + +#if CASPER_ECC_P384 +void CASPER_ECC_SECP384R1_Mul( + CASPER_Type *base, uint32_t resX[12], uint32_t resY[12], uint32_t X[12], uint32_t Y[12], uint32_t scalar[12]) +{ + uint32_t X1[12] = {0}; + uint32_t Y1[12] = {0}; + toMontgomery(X1, X); + toMontgomery(Y1, Y); + + CASPER_MEMCPY(&CASPER_MEM[INOUT_SCRATCH_START + 0 * CASPER_NUM_LIMBS], X1, NUM_LIMBS * sizeof(uint32_t)); + CASPER_MEMCPY(&CASPER_MEM[INOUT_SCRATCH_START + 1 * CASPER_NUM_LIMBS], Y1, NUM_LIMBS * sizeof(uint32_t)); + + Jac_scalar_multiplication(&CASPER_MEM[INOUT_SCRATCH_START + 6 * CASPER_NUM_LIMBS], + &CASPER_MEM[INOUT_SCRATCH_START + 7 * CASPER_NUM_LIMBS], + &CASPER_MEM[INOUT_SCRATCH_START + 8 * CASPER_NUM_LIMBS], + &CASPER_MEM[INOUT_SCRATCH_START + 0 * CASPER_NUM_LIMBS], + &CASPER_MEM[INOUT_SCRATCH_START + 1 * CASPER_NUM_LIMBS], scalar, NISTp384, NISTp384_q); + + Jac_toAffine(&CASPER_MEM[INOUT_SCRATCH_START + 3 * CASPER_NUM_LIMBS], + &CASPER_MEM[INOUT_SCRATCH_START + 4 * CASPER_NUM_LIMBS], + &CASPER_MEM[INOUT_SCRATCH_START + 6 * CASPER_NUM_LIMBS], + &CASPER_MEM[INOUT_SCRATCH_START + 7 * CASPER_NUM_LIMBS], + &CASPER_MEM[INOUT_SCRATCH_START + 8 * CASPER_NUM_LIMBS]); + + /* Montgomery to Normal */ + /* X_normal = 1 * X_montgomery; Y_normal = 1 * Y_montgomery */ + uint32_t one[12] = {0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; + CASPER_MEMCPY(&CASPER_MEM[INOUT_SCRATCH_START + 0 * CASPER_NUM_LIMBS], one, NUM_LIMBS * sizeof(uint32_t)); + multiply_casper(&CASPER_MEM[INOUT_SCRATCH_START + 5 * CASPER_NUM_LIMBS], + &CASPER_MEM[INOUT_SCRATCH_START + 3 * CASPER_NUM_LIMBS], + &CASPER_MEM[INOUT_SCRATCH_START + 0 * CASPER_NUM_LIMBS]); + multiply_casper(&CASPER_MEM[INOUT_SCRATCH_START + 6 * CASPER_NUM_LIMBS], + &CASPER_MEM[INOUT_SCRATCH_START + 4 * CASPER_NUM_LIMBS], + &CASPER_MEM[INOUT_SCRATCH_START + 0 * CASPER_NUM_LIMBS]); + + /* copy out to result */ + CASPER_MEMCPY(resX, &CASPER_MEM[INOUT_SCRATCH_START + 5 * CASPER_NUM_LIMBS], NUM_LIMBS * sizeof(uint32_t)); + CASPER_MEMCPY(resY, &CASPER_MEM[INOUT_SCRATCH_START + 6 * CASPER_NUM_LIMBS], NUM_LIMBS * sizeof(uint32_t)); +} + +void CASPER_ECC_SECP384R1_MulAdd(CASPER_Type *base, + uint32_t resX[12], + uint32_t resY[12], + uint32_t X1[12], + uint32_t Y1[12], + uint32_t scalar1[12], + uint32_t X2[12], + uint32_t Y2[12], + uint32_t scalar2[12]) +{ + CASPER_MEMCPY(&CASPER_MEM[INOUT_SCRATCH_START + 0 * CASPER_NUM_LIMBS], X1, NUM_LIMBS * sizeof(uint32_t)); + CASPER_MEMCPY(&CASPER_MEM[INOUT_SCRATCH_START + 1 * CASPER_NUM_LIMBS], Y1, NUM_LIMBS * sizeof(uint32_t)); + + CASPER_MEMCPY(&CASPER_MEM[INOUT_SCRATCH_START + 2 * CASPER_NUM_LIMBS], X2, NUM_LIMBS * sizeof(uint32_t)); + CASPER_MEMCPY(&CASPER_MEM[INOUT_SCRATCH_START + 3 * CASPER_NUM_LIMBS], Y2, NUM_LIMBS * sizeof(uint32_t)); + + toMontgomery(&CASPER_MEM[INOUT_SCRATCH_START + 0 * CASPER_NUM_LIMBS], + &CASPER_MEM[INOUT_SCRATCH_START + 0 * CASPER_NUM_LIMBS]); + toMontgomery(&CASPER_MEM[INOUT_SCRATCH_START + 1 * CASPER_NUM_LIMBS], + &CASPER_MEM[INOUT_SCRATCH_START + 1 * CASPER_NUM_LIMBS]); + toMontgomery(&CASPER_MEM[INOUT_SCRATCH_START + 2 * CASPER_NUM_LIMBS], + &CASPER_MEM[INOUT_SCRATCH_START + 2 * CASPER_NUM_LIMBS]); + toMontgomery(&CASPER_MEM[INOUT_SCRATCH_START + 3 * CASPER_NUM_LIMBS], + &CASPER_MEM[INOUT_SCRATCH_START + 3 * CASPER_NUM_LIMBS]); + + double_scalar_multiplication(&CASPER_MEM[INOUT_SCRATCH_START + 4 * CASPER_NUM_LIMBS], + &CASPER_MEM[INOUT_SCRATCH_START + 5 * CASPER_NUM_LIMBS], + &CASPER_MEM[INOUT_SCRATCH_START + 6 * CASPER_NUM_LIMBS], + &CASPER_MEM[INOUT_SCRATCH_START + 0 * CASPER_NUM_LIMBS], + &CASPER_MEM[INOUT_SCRATCH_START + 1 * CASPER_NUM_LIMBS], scalar1, + &CASPER_MEM[INOUT_SCRATCH_START + 2 * CASPER_NUM_LIMBS], + &CASPER_MEM[INOUT_SCRATCH_START + 3 * CASPER_NUM_LIMBS], scalar2); + + Jac_toAffine(&CASPER_MEM[LUT_SCRATCH_START + 0 * CASPER_NUM_LIMBS], + &CASPER_MEM[LUT_SCRATCH_START + 1 * CASPER_NUM_LIMBS], + &CASPER_MEM[INOUT_SCRATCH_START + 4 * CASPER_NUM_LIMBS], + &CASPER_MEM[INOUT_SCRATCH_START + 5 * CASPER_NUM_LIMBS], + &CASPER_MEM[INOUT_SCRATCH_START + 6 * CASPER_NUM_LIMBS]); + + uint32_t one[12] = {0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; + CASPER_MEMCPY(&CASPER_MEM[INOUT_SCRATCH_START + 0 * CASPER_NUM_LIMBS], one, NUM_LIMBS * sizeof(uint32_t)); + multiply_casper(&CASPER_MEM[INOUT_SCRATCH_START + 1 * CASPER_NUM_LIMBS], + &CASPER_MEM[LUT_SCRATCH_START + 0 * CASPER_NUM_LIMBS], + &CASPER_MEM[INOUT_SCRATCH_START + 0 * CASPER_NUM_LIMBS]); + multiply_casper(&CASPER_MEM[INOUT_SCRATCH_START + 2 * CASPER_NUM_LIMBS], + &CASPER_MEM[LUT_SCRATCH_START + 1 * CASPER_NUM_LIMBS], + &CASPER_MEM[INOUT_SCRATCH_START + 0 * CASPER_NUM_LIMBS]); + + CASPER_MEMCPY(resX, (&CASPER_MEM[INOUT_SCRATCH_START + 1 * CASPER_NUM_LIMBS]), NUM_LIMBS * sizeof(uint32_t)); + CASPER_MEMCPY(resY, (&CASPER_MEM[INOUT_SCRATCH_START + 2 * CASPER_NUM_LIMBS]), NUM_LIMBS * sizeof(uint32_t)); +} +#endif /* CASPER_ECC_P384 */ + +// CIOS Multiply. This is the Coarse Integrated form where the values are +// multiplied and reduced for each step of "i". This uses less memory and +// is faster as a result. Note that this is used to square as well as mul, +// so not as fast as pure squaring could be. +static void MultprecCiosMul_ct( + uint32_t w_out[], const uint32_t a[], const uint32_t b[], const uint32_t Nmod[], const uint32_t *Np) +{ + int i; + uint64_t *m64 = (uint64_t *)&msg_ret[kCASPER_RamOffset_M64]; + uint64_t Np64; + uint64_t carry; + uint64_t *a64, *b64, *w64, *N64; + uint32_t *T1 = &CASPER_MEM[0], borrow; + + Np64 = *(uint64_t *)Np; + + a64 = (uint64_t *)a; + b64 = (uint64_t *)b; + w64 = (uint64_t *)w_out; + N64 = (uint64_t *)Nmod; + + if (a) + { /* if !a, we are reducing only */ + PreZeroW(i, w_out); + } + SET_DWORD(&w64[N_dwordlen], 0); + SET_DWORD(&w64[N_dwordlen + 1], 0); + /* with accelerator */ + + /* loop i and then reduce after each j round */ + for (i = 0; i < N_dwordlen; i++) + { + /* Step 3. Iterate over N words of u using i - perform Multiply-accumulate */ + /* push-pull: we do a*b and then separately m*n (reduce) */ + if (a) + { /* if mul&reduce vs. reduce only */ + carry = GET_DWORD(&w64[N_dwordlen]); + Accel_SetABCD_Addr(CA_MK_OFF(&b64[i]), CA_MK_OFF(a64)); + Accel_crypto_mul(Accel_IterOpcodeResaddr(N_dwordlen - 1, kCASPER_OpMul6464FullSum, CA_MK_OFF(w64))); + Accel_done(); + /* max carry is contained since ~0*~0=0xFFFE0001+0xFFFF=0xFFFF0000, */ + /* so max carry is 0xFFFF and 0xFFFF0000+0xFFFF=0xFFFFFFFF */ + /* accel took care of w_out[N_wordlen] & +1, so we just take care of the next double word if carry=1 */ + /* w64[N_dwordlen+1] = g_carry; */ + carry = (GET_DWORD(&w64[N_dwordlen]) < carry); + SET_DWORD(&w64[N_dwordlen + 1], carry); + } + SET_DWORD(&m64[0], GET_DWORD(&w64[0]) * Np64); /* prime for 1st; modulo a double-word */ + + /* we are reducing, so the 1st [0th] 64 bit value product is tossed, but we */ + /* need its carry. We let the accel do this separately - really need a mode to */ + /* do this "reduce" since it is natural */ + carry = GET_DWORD(&w64[N_dwordlen]); + Accel_SetABCD_Addr(CA_MK_OFF(m64), CA_MK_OFF(&N64[0])); + Accel_crypto_mul(Accel_IterOpcodeResaddr(N_dwordlen - 1, kCASPER_OpMul6464FullSum, CA_MK_OFF(&w64[0]))); + Accel_done(); + carry = (GET_DWORD(&w64[N_dwordlen]) < carry); + + Accel_SetABCD_Addr(CA_MK_OFF(&w64[1]), 0); + Accel_crypto_mul(Accel_IterOpcodeResaddr(N_dwordlen - 1, kCASPER_OpCopy, CA_MK_OFF(&w64[0]))); + + Accel_done(); + SET_DWORD(&w64[N_dwordlen], (GET_DWORD(&w64[N_dwordlen + 1]) + carry)); + } + + /* now check if need to subtract Nmod */ + CASPER_MEMCPY_I2I(T1, w_out, (NUM_LIMBS + 1) * sizeof(uint32_t)); + + /* Compute w = w - N */ + Accel_SetABCD_Addr(CA_MK_OFF(Nmod), 0); + Accel_crypto_mul(Accel_IterOpcodeResaddr(N_dwordlen, kCASPER_OpSub64, CA_MK_OFF(w_out))); + Accel_done(); + + // if w_out > T1 then there was a borrow + borrow = (GET_WORD(&((uint32_t *)w_out)[NUM_LIMBS]) > GET_WORD(&T1[NUM_LIMBS])); + + SET_WORD(&w_out[NUM_LIMBS + 1], 0); + SET_WORD(&w_out[NUM_LIMBS], 0); + casper_select(w_out, w_out, T1, borrow, NUM_LIMBS); +} + +/* Compute C = A - B % mod +* Assumes all operand have two extra limbs to store carry. +*/ +void CASPER_montsub(uint32_t *C, uint32_t *A, uint32_t *B, uint32_t *mod) +{ + uint64_t *b64, *c64, *m64, *tmp; + int borrow; + + b64 = (uint64_t *)B; + c64 = (uint64_t *)C; + m64 = (uint64_t *)mod; + + tmp = (uint64_t *)&CASPER_MEM[0]; + + CASPER_MEMCPY(tmp, A, NUM_LIMBS * sizeof(uint32_t)); + // uint32_t temp32 = GET_WORD(&tmp[NUM_LIMBS - 1]); + + /* Compute tmp = A - B. */ + Accel_SetABCD_Addr(CA_MK_OFF(b64), 0); + + Accel_crypto_mul(Accel_IterOpcodeResaddr(NUM_LIMBS / 2 - 1, kCASPER_OpSub64, CA_MK_OFF(tmp))); + Accel_done(); + + // borrow = (GET_WORD(&((uint32_t*)tmp)[NUM_LIMBS - 1]) > temp32); + borrow = ((GET_WORD(&((uint32_t *)tmp)[NUM_LIMBS - 1])) > GET_WORD(&A[NUM_LIMBS - 1])); + CASPER_MEMCPY(c64, tmp, NUM_LIMBS * sizeof(uint32_t)); + + /* Compute C = Mod + tmp */ + Accel_SetABCD_Addr(CA_MK_OFF(m64), 0); + Accel_crypto_mul(Accel_IterOpcodeResaddr(NUM_LIMBS / 2 - 1, kCASPER_OpAdd64, CA_MK_OFF(c64))); + Accel_done(); + + casper_select(C, (uint32_t *)tmp, C, borrow, NUM_LIMBS); +} + +/* Compute C = A + B % mod +* Assumes all operand have two extra limbs to store carry. +*/ +void CASPER_montadd(uint32_t *C, uint32_t *A, uint32_t *B, uint32_t *mod) +{ + uint64_t *b64, *c64, *m64, *tmp; + int borrow; + + b64 = (uint64_t *)B; + c64 = (uint64_t *)C; + m64 = (uint64_t *)mod; + + tmp = (uint64_t *)&CASPER_MEM[0]; + + CASPER_MEMCPY(tmp, A, NUM_LIMBS * sizeof(uint32_t)); + SET_DWORD(&tmp[NUM_LIMBS / 2], 0); + SET_DWORD(&b64[NUM_LIMBS / 2], 0); + SET_DWORD(&m64[NUM_LIMBS / 2], 0); + + /* Compute tmp = A + B using one additonal double-length limb. */ + Accel_SetABCD_Addr(CA_MK_OFF(b64), 0); + + Accel_crypto_mul(Accel_IterOpcodeResaddr(NUM_LIMBS / 2, kCASPER_OpAdd64, CA_MK_OFF(tmp))); + Accel_done(); + + CASPER_MEMCPY(c64, tmp, (NUM_LIMBS + 2) * sizeof(uint32_t)); + + /* Compute C = Mod - tmp */ + Accel_SetABCD_Addr(CA_MK_OFF(m64), 0); + Accel_crypto_mul(Accel_IterOpcodeResaddr(NUM_LIMBS / 2, kCASPER_OpSub64, CA_MK_OFF(c64))); + Accel_done(); + + // borrow = g_carry; + borrow = (GET_WORD(&C[NUM_LIMBS]) > GET_WORD(&(((uint32_t *)tmp)[NUM_LIMBS]))); + casper_select(C, C, (uint32_t *)tmp, borrow, NUM_LIMBS); +} + +/* Compute c = a/2 mod p where b is scratch space. */ +void CASPER_half(uint32_t *c, uint32_t *a, uint32_t *b) +{ + shiftright(b, a, 1); /* Compute a/2 and (a+p)/2 */ + + /* Compute tmp = a + p using one additonal double-length limb. */ + CASPER_MEMCPY(c, a, NUM_LIMBS * sizeof(uint32_t)); + SET_WORD(&c[NUM_LIMBS], 0); + SET_WORD(&c[NUM_LIMBS + 1], 0); + + Accel_SetABCD_Addr(CA_MK_OFF(((uint64_t *)&CASPER_MEM[MOD_SCRATCH_START])), 0); + Accel_crypto_mul(Accel_IterOpcodeResaddr(NUM_LIMBS / 2, kCASPER_OpAdd64, CA_MK_OFF(((uint64_t *)c)))); + Accel_done(); + + shiftright(c, c, 1); + SET_WORD(&c[NUM_LIMBS - 1], GET_WORD(&c[NUM_LIMBS - 1]) | (GET_WORD(&c[NUM_LIMBS]) << 31)); + SET_WORD(&c[NUM_LIMBS], 0); + casper_select(c, b, c, (GET_WORD(&a[0]) & 1), NUM_LIMBS); +} + +static uint32_t casper_get_word(uint32_t *addr) +{ + return GET_WORD(addr); +} + +#if CASPER_ECC_P256 +/* Shift right by 1 <= c <= 31. */ +static void shiftright(uint32_t *z, uint32_t *x, int c) +{ + do + { + SET_WORD((&z[0]), (GET_WORD(&x[1]) << (32 - (c))) | (GET_WORD(&x[0]) >> (c))); + SET_WORD((&z[1]), (GET_WORD(&x[2]) << (32 - (c))) | (GET_WORD(&x[1]) >> (c))); + SET_WORD((&z[2]), (GET_WORD(&x[3]) << (32 - (c))) | (GET_WORD(&x[2]) >> (c))); + SET_WORD((&z[3]), (GET_WORD(&x[4]) << (32 - (c))) | (GET_WORD(&x[3]) >> (c))); + SET_WORD((&z[4]), (GET_WORD(&x[5]) << (32 - (c))) | (GET_WORD(&x[4]) >> (c))); + SET_WORD((&z[5]), (GET_WORD(&x[6]) << (32 - (c))) | (GET_WORD(&x[5]) >> (c))); + SET_WORD((&z[6]), (GET_WORD(&x[7]) << (32 - (c))) | (GET_WORD(&x[6]) >> (c))); + SET_WORD((&z[7]), (GET_WORD(&x[7]) >> (c))); + + } while (0); +} + +/* Shift left by 1 <= c <= 31. */ +static void shiftleft(uint32_t *z, uint32_t *x, int c) +{ + do + { + SET_WORD(&z[7], (GET_WORD(&x[7]) << (c)) | GET_WORD(&z[6]) >> (32 - (c))); + SET_WORD(&z[6], (GET_WORD(&x[6]) << (c)) | GET_WORD(&z[5]) >> (32 - (c))); + SET_WORD(&z[5], (GET_WORD(&x[5]) << (c)) | GET_WORD(&z[4]) >> (32 - (c))); + SET_WORD(&z[4], (GET_WORD(&x[4]) << (c)) | GET_WORD(&z[3]) >> (32 - (c))); + SET_WORD(&z[3], (GET_WORD(&x[3]) << (c)) | GET_WORD(&z[2]) >> (32 - (c))); + SET_WORD(&z[2], (GET_WORD(&x[2]) << (c)) | GET_WORD(&z[1]) >> (32 - (c))); + SET_WORD(&z[1], (GET_WORD(&x[1]) << (c)) | GET_WORD(&z[0]) >> (32 - (c))); + SET_WORD(&z[0], (GET_WORD(&x[0]) << (c))); + } while (0); +} +#else +/* Shift right by 1 <= c <= 31. */ +static void shiftright(uint32_t *z, uint32_t *x, int c) +{ + do + { + SET_WORD(&z[0], (GET_WORD(&x[1]) << (32 - (c))) | (GET_WORD(&x[0]) >> (c))); + SET_WORD(&z[1], (GET_WORD(&x[2]) << (32 - (c))) | (GET_WORD(&x[1]) >> (c))); + SET_WORD(&z[2], (GET_WORD(&x[3]) << (32 - (c))) | (GET_WORD(&x[2]) >> (c))); + SET_WORD(&z[3], (GET_WORD(&x[4]) << (32 - (c))) | (GET_WORD(&x[3]) >> (c))); + SET_WORD(&z[4], (GET_WORD(&x[5]) << (32 - (c))) | (GET_WORD(&x[4]) >> (c))); + SET_WORD(&z[5], (GET_WORD(&x[6]) << (32 - (c))) | (GET_WORD(&x[5]) >> (c))); + SET_WORD(&z[6], (GET_WORD(&x[7]) << (32 - (c))) | (GET_WORD(&x[6]) >> (c))); + SET_WORD(&z[7], (GET_WORD(&x[8]) << (32 - (c))) | (GET_WORD(&x[7]) >> (c))); + SET_WORD(&z[8], (GET_WORD(&x[9]) << (32 - (c))) | (GET_WORD(&x[8]) >> (c))); + SET_WORD(&z[9], (GET_WORD(&x[10]) << (32 - (c))) | (GET_WORD(&x[9]) >> (c))); + SET_WORD(&z[10], (GET_WORD(&x[11]) << (32 - (c))) | (GET_WORD(&x[10]) >> (c))); + SET_WORD(&z[11], (GET_WORD(&x[11]) >> (c))); + } while (0); +} + +/* Shift left by 1 <= c <= 31. */ +static void shiftleft(uint32_t *z, uint32_t *x, int c) +{ + do + { + SET_WORD(&z[11], (GET_WORD(&x[11]) << (c)) | GET_WORD(&z[10]) >> (32 - (c))); + SET_WORD(&z[10], (GET_WORD(&x[10]) << (c)) | GET_WORD(&z[9]) >> (32 - (c))); + SET_WORD(&z[9], (GET_WORD(&x[9]) << (c)) | GET_WORD(&z[8]) >> (32 - (c))); + SET_WORD(&z[8], (GET_WORD(&x[8]) << (c)) | GET_WORD(&z[7]) >> (32 - (c))); + SET_WORD(&z[7], (GET_WORD(&x[7]) << (c)) | GET_WORD(&z[6]) >> (32 - (c))); + SET_WORD(&z[6], (GET_WORD(&x[6]) << (c)) | GET_WORD(&z[5]) >> (32 - (c))); + SET_WORD(&z[5], (GET_WORD(&x[5]) << (c)) | GET_WORD(&z[4]) >> (32 - (c))); + SET_WORD(&z[4], (GET_WORD(&x[4]) << (c)) | GET_WORD(&z[3]) >> (32 - (c))); + SET_WORD(&z[3], (GET_WORD(&x[3]) << (c)) | GET_WORD(&z[2]) >> (32 - (c))); + SET_WORD(&z[2], (GET_WORD(&x[2]) << (c)) | GET_WORD(&z[1]) >> (32 - (c))); + SET_WORD(&z[1], (GET_WORD(&x[1]) << (c)) | GET_WORD(&z[0]) >> (32 - (c))); + SET_WORD(&z[0], (GET_WORD(&x[0]) << (c))); + } while (0); +} +#endif + +/* Convert a projective point (X1 : Y1 : Z1) + * to the affine point (X3, Y3) = (X1/Z1^2,Y1/Z1^3) + * The memory of (X3, Y3) and (X1 : Y1 : Z1) should not overlap + */ +void Jac_toAffine(uint32_t *X3, uint32_t *Y3, uint32_t *X1, uint32_t *Y1, uint32_t *Z1) +{ + uint32_t *T1, *T2; + + T1 = &CASPER_MEM[ECC_SCRATCH_START + 0 * CASPER_NUM_LIMBS]; + T2 = &CASPER_MEM[ECC_SCRATCH_START + 1 * CASPER_NUM_LIMBS]; + + square_casper(T1, Z1); // Z^2 + multiply_casper(T2, T1, Z1); // Z^3 + + // Montgomery inverse + invert(T1, T2); // Z^-3 + + multiply_casper(Y3, Y1, T1); // Y3 = Y/Z^3 + multiply_casper(T2, T1, Z1); // Z^-2 + multiply_casper(X3, X1, T2); // X3 = X/Z^2 +} + +/* Return 1 if (X1: Y1: Z1) is on the curve + * Y^2 = X^3 -3XZ^4 + bZ^6 + * and return 0 otherwise. + */ +int Jac_oncurve(uint32_t *X1, uint32_t *Y1, uint32_t *Z1, uint32_t *b) +{ + uint32_t *T1, *T2, *T3, *T4, *T5, *T6; + int m; + + T1 = &CASPER_MEM[ECC_SCRATCH_START + 0 * CASPER_NUM_LIMBS]; + T2 = &CASPER_MEM[ECC_SCRATCH_START + 1 * CASPER_NUM_LIMBS]; + T3 = &CASPER_MEM[ECC_SCRATCH_START + 2 * CASPER_NUM_LIMBS]; + T4 = &CASPER_MEM[ECC_SCRATCH_START + 3 * CASPER_NUM_LIMBS]; + T5 = &CASPER_MEM[ECC_SCRATCH_START + 4 * CASPER_NUM_LIMBS]; + T6 = &CASPER_MEM[ECC_SCRATCH_START + 5 * CASPER_NUM_LIMBS]; + + square_casper(T1, Y1); // Y^2 + square_casper(T6, X1); // X^2 + multiply_casper(T2, T6, X1); // X^3 + + square_casper(T3, Z1); // Z^2 + square_casper(T4, T3); // Z^4 + multiply_casper(T6, T4, T3); // Z^6 + multiply_casper(T3, b, T6); // bZ^6 + + multiply_casper(T6, T4, X1); // XZ^4 + + mul2_casper(T5, T6); + add_casper(T4, T5, T6); // 3XZ^4 + + sub_casper(T2, T2, T4); // X^3-3XZ^4 + add_casper(T2, T2, T3); // X^3-3XZ^4+bZ^6 + + CASPER_ECC_equal(&m, T1, T2); + if (m != 0) + { + return 0; + } + return 1; +} + +/* Compute (X3 : Y3: Z3) = (X1: Y1: Z1) + (X2 : Y2 : Z2) + * where (X1: Y1: Z1) != (X2 : Y2 : Z2) + * (X3 : Y3: Z3) may be the same as one of the inputs. + */ +void Jac_addition(uint32_t *X3, + uint32_t *Y3, + uint32_t *Z3, + uint32_t *X1, + uint32_t *Y1, + uint32_t *Z1, + uint32_t *X2, + uint32_t *Y2, + uint32_t *Z2) +{ + uint32_t *Z1Z1, *Z2Z2, *U1, *S1, *J, *H, *V, *t0, *t1; + int m1, m2; + + Z1Z1 = &CASPER_MEM[ECC_SCRATCH_START + 0 * CASPER_NUM_LIMBS]; + Z2Z2 = &CASPER_MEM[ECC_SCRATCH_START + 1 * CASPER_NUM_LIMBS]; + U1 = &CASPER_MEM[ECC_SCRATCH_START + 2 * CASPER_NUM_LIMBS]; + S1 = &CASPER_MEM[ECC_SCRATCH_START + 3 * CASPER_NUM_LIMBS]; + J = &CASPER_MEM[ECC_SCRATCH_START + 4 * CASPER_NUM_LIMBS]; + H = &CASPER_MEM[ECC_SCRATCH_START + 5 * CASPER_NUM_LIMBS]; + V = &CASPER_MEM[ECC_SCRATCH_START + 6 * CASPER_NUM_LIMBS]; + t0 = &CASPER_MEM[ECC_SCRATCH_START + 7 * CASPER_NUM_LIMBS]; + t1 = &CASPER_MEM[ECC_SCRATCH_START + 8 * CASPER_NUM_LIMBS]; + + CASPER_ECC_equal_to_zero(&m1, Z1); + CASPER_ECC_equal_to_zero(&m2, Z2); + if (m1 == 0) + { + CASPER_MEMCPY(X3, X2, NUM_LIMBS * 4); + CASPER_MEMCPY(Y3, Y2, NUM_LIMBS * 4); + CASPER_MEMCPY(Z3, Z2, NUM_LIMBS * 4); + return; + } + if (m2 == 0) + { + CASPER_MEMCPY(X3, X1, NUM_LIMBS * 4); + CASPER_MEMCPY(Y3, Y1, NUM_LIMBS * 4); + CASPER_MEMCPY(Z3, Z1, NUM_LIMBS * 4); + return; + } + + square_casper(Z1Z1, Z1); + square_casper(Z2Z2, Z2); + multiply_casper(U1, X1, Z2Z2); + multiply_casper(H, X2, Z1Z1); /* if H equals U1 then X's are the same */ + multiply_casper(t0, Z2, Z2Z2); + multiply_casper(S1, Y1, t0); + multiply_casper(t0, Z1, Z1Z1); + multiply_casper(J, Y2, t0); /* if (S1 == J) then Y's are the same */ + + CASPER_ECC_equal(&m1, H, U1); /* If H and U1 match then the X-coordinates are the same. */ + CASPER_ECC_equal(&m2, S1, J); /* If S1 and J match then the Y-coordinates are the same. */ + if (m1 == 0) + { + if (m2 == 0) + { + Jac_double(X3, Y3, Z3, X1, Y1, Z1); + return; + } + /* else { + We work with the point at infinity. + The Z-coordinate will be set to zero in this function. + } */ + } + + sub_casper(H, H, U1); + mul2_casper(t0, H); + square_casper(t1, t0); + sub_casper(t0, J, S1); + multiply_casper(J, H, t1); + multiply_casper(V, U1, t1); + mul2_casper(U1, t0); + square_casper(t0, U1); + mul2_casper(t1, V); + sub_casper(t0, t0, J); + sub_casper(X3, t0, t1); + sub_casper(t0, V, X3); + multiply_casper(t1, S1, J); + mul2_casper(t1, t1); + multiply_casper(V, U1, t0); + sub_casper(Y3, V, t1); + add_casper(V, Z1, Z2); + square_casper(t1, V); + sub_casper(t1, t1, Z1Z1); + sub_casper(t1, t1, Z2Z2); + multiply_casper(Z3, t1, H); +} + +/* Compute (X3 : Y3: Z3) = (X1: Y1: Z1) + (X2, Y2) + * where (X1: Y1: Z1) != (X2, Y2) + * (X3 : Y3: Z3) may not overlap with (X1: Y1: Z1). + * Source: 2004 Hankerson–Menezes–Vanstone, page 91. + */ +void Jac_add_affine( + uint32_t *X3, uint32_t *Y3, uint32_t *Z3, uint32_t *X1, uint32_t *Y1, uint32_t *Z1, uint32_t *X2, uint32_t *Y2) +{ + uint32_t *T1, *T2, *T3, *T4, *T5; + int m1, m2; + + T1 = &CASPER_MEM[ECC_SCRATCH_START + 0 * CASPER_NUM_LIMBS]; + T2 = &CASPER_MEM[ECC_SCRATCH_START + 1 * CASPER_NUM_LIMBS]; + T3 = &CASPER_MEM[ECC_SCRATCH_START + 2 * CASPER_NUM_LIMBS]; + T4 = &CASPER_MEM[ECC_SCRATCH_START + 3 * CASPER_NUM_LIMBS]; + T5 = &CASPER_MEM[ECC_SCRATCH_START + 4 * CASPER_NUM_LIMBS]; + + CASPER_ECC_equal_to_zero(&m1, Z1); + if (m1 == 0) + { + CASPER_MEMCPY(X3, X2, NUM_LIMBS * 4); + CASPER_MEMCPY(Y3, Y2, NUM_LIMBS * 4); + CASPER_MEMCPY(Z3, ONE, NUM_LIMBS * 4); + return; + } + + copy(T5, Z1); + square_casper(T3, Z1); + multiply_casper(T2, T3, Z1); + multiply_casper(T4, T3, X2); + multiply_casper(T3, T2, Y2); + + CASPER_ECC_equal(&m1, T4, X1); + CASPER_ECC_equal(&m2, T3, Y1); + if (m1 == 0) + { + if (m2 == 0) + { + Jac_double(X3, Y3, Z3, X1, Y1, Z1); + return; + } + /* else { + We work with the point at infinity. + The Z-coordinate will be set to zero in this function. + } */ + } + + sub_casper(T1, T4, X1); + sub_casper(T2, T3, Y1); + multiply_casper(Z3, T5, T1); + square_casper(T3, T1); + multiply_casper(T4, T3, T1); + multiply_casper(T5, T3, X1); + mul2_casper(T1, T5); + square_casper(X3, T2); + sub_casper(X3, X3, T1); + sub_casper(X3, X3, T4); + sub_casper(T3, T5, X3); + multiply_casper(T1, T3, T2); + multiply_casper(T2, T4, Y1); + sub_casper(Y3, T1, T2); +} + +extern uint32_t casper_get_word(uint32_t *addr); + +/* Point doubling from: 2004 Hankerson–Menezes–Vanstone, page 91. + * Compute (X3 : Y3: Z3) = (X1: Y1: Z1) + (X1 : Y1 : Z1) + * (X3 : Y3: Z3) may be the same as the input. + */ +void Jac_double(uint32_t *X3, uint32_t *Y3, uint32_t *Z3, uint32_t *X1, uint32_t *Y1, uint32_t *Z1) +{ + uint32_t *T1, *T2, *T3, *T4, *T5; + + T1 = &CASPER_MEM[ECC_SCRATCH_START + 0 * CASPER_NUM_LIMBS]; + T2 = &CASPER_MEM[ECC_SCRATCH_START + 1 * CASPER_NUM_LIMBS]; + T3 = &CASPER_MEM[ECC_SCRATCH_START + 2 * CASPER_NUM_LIMBS]; + T4 = &CASPER_MEM[ECC_SCRATCH_START + 3 * CASPER_NUM_LIMBS]; + T5 = &CASPER_MEM[ECC_SCRATCH_START + 4 * CASPER_NUM_LIMBS]; + + square_casper(T1, Z1); + sub_casper(T3, X1, T1); + add_casper(T1, X1, T1); + multiply_casper(T4, T3, T1); + + mul2_casper(T3, T4); + + add_casper(T2, T3, T4); + + mul2_casper(Y3, Y1); + + copy(T5, Z1); + multiply_casper(Z3, Y3, T5); + + square_casper(T5, Y3); + + multiply_casper(T3, T5, X1); + + square_casper(Y3, T5); + + half(T5, Y3, T4); + + square_casper(X3, T2); + + mul2_casper(T1, T3); + + sub_casper(X3, X3, T1); + + sub_casper(T1, T3, X3); + + multiply_casper(T3, T1, T2); + + sub_casper(Y3, T3, T5); +} + +/* Recoding for a signed fixed window. + * Source: https://eprint.iacr.org/2014/130.pdf, Algorithm 6 + * Recode the n-bit integer k into ciel(log2(n)/(w-1)) digits + * where each digit is in + * { +/- 1, +/- 3, ..., +/- 2^(w-1)-1 } + * and put the result in c. + */ +static void recode(int8_t *c, uint32_t *k, int n, int w) +{ + int i, t; + uint32_t K[NUM_LIMBS] = {0}; + memcpy(K, k, (size_t)ceil(n / 8.)); + t = (n + (w - 2)) / (w - 1); + for (i = 0; i < t; i++) + { + c[i] = (K[0] & ((1 << w) - 1)) - (1 << (w - 1)); + shiftrightSysram(K, K, w - 1); + add_n_1(K, K, (uint32_t)c[i] >> 31, NUM_LIMBS); + } + c[t] = K[0]; +} + +static uint32_t sub_n(uint32_t *c, uint32_t *a, uint32_t *b, int n) +{ + int i; + uint32_t borrow; + sub_borrowout(borrow, GET_WORD(&c[0]), a[0], GET_WORD(&b[0])); + for (i = 1; i < n; i++) + { + sub_borrowin_borrowout(borrow, GET_WORD(&c[i]), a[i], GET_WORD(&b[i]), borrow); + } + return borrow; +} + +#if 0 +/* Dumb n-limb subtraction of c=a-b, return borrow. */ +static uint32_t sub_n_1(uint32_t *c, uint32_t *a, uint32_t b, int n) { + int i; + uint32_t borrow; + sub_borrowout(borrow, c[0], a[0], b); + for (i = 1; i < n; i++) { + sub_borrowin_borrowout_1(borrow, c[i], a[i], borrow); + } + return borrow; +} + +/* Dumb n-limb addition of c=a+b, return carry. */ +static uint32_t add_n(uint32_t *c, uint32_t *a, uint32_t *b, int n) { + int i; + uint32_t carry; + add_cout(carry, c[0], a[0], b[0]); + for (i = 1; i < n; i++) { + add_cout_cin(carry, c[i], a[i], b[i], carry); + } + return carry; +} +#endif + +/* Dumb n-limb addition of c=a+b, return carry. */ +static uint32_t add_n_1(uint32_t *c, uint32_t *a, uint32_t b, int n) +{ + int i; + uint32_t carry; + add_cout(carry, c[0], a[0], b); + for (i = 1; i < n; i++) + { + add_cout_cin(carry, c[i], a[i], 0, carry); + } + return carry; +} + +// http://graphics.stanford.edu/~seander/bithacks.html#IntegerAbs +static uint8_t int8abs(int8_t v) +{ + int8_t const mask = v >> 7; + return (v + mask) ^ mask; +} + +/* Constant time elliptic curve scalar multiplication. + * Source: https://eprint.iacr.org/2014/130.pdf + * when using w = 4. + * Computes (X3 : Y3 : Z3) = k * (X1, Y1) \in E(F_p) + * p is the prime used to define the finite field F_p + * q is the (prime) order of the curve + */ +void Jac_scalar_multiplication( + uint32_t *X3, uint32_t *Y3, uint32_t *Z3, uint32_t *X1, uint32_t *Y1, uint32_t *k, uint32_t *p, uint32_t *q) +{ + uint32_t *scalar, *M, *X, *Y, *Z, *mem; + int i, sign, odd; + // int8_t *rec; + uint8_t index; + + /* Point to the start of the LUT table space. */ + mem = &CASPER_MEM[LUT_SCRATCH_START]; + + scalar = &CASPER_MEM[LUT_SCRATCH_START + 12 * CASPER_NUM_LIMBS]; + X = &CASPER_MEM[LUT_SCRATCH_START + 13 * CASPER_NUM_LIMBS]; + Y = &CASPER_MEM[LUT_SCRATCH_START + 14 * CASPER_NUM_LIMBS]; + Z = &CASPER_MEM[LUT_SCRATCH_START + 15 * CASPER_NUM_LIMBS]; + M = &CASPER_MEM[LUT_SCRATCH_START + 16 * CASPER_NUM_LIMBS]; + + /* Point to memory the recoded scalar. + * CASPER_RECODE_LENGTH bytes is needed. + */ + // rec = (int8_t*)&CASPER_MEM[LUT_SCRATCH_START + 17 * CASPER_NUM_LIMBS]; + int8_t rec[CASPER_RECODE_LENGTH]; + + CASPER_MEMCPY(scalar, k, sizeof(uint32_t) * NUM_LIMBS); + +/* Precomputation: compute 1*P, 3*P, 5*P, and 7*P */ +#define LUT(P, x) (mem + (3 * ((P)-1) / 2 + (x)) * CASPER_NUM_LIMBS) + + /* Set 1*P */ + copy(Z3, ONE); + copy(LUT(1, 0), X1); + copy(LUT(1, 1), Y1); + copy(LUT(1, 2), Z3); + + /* Compute 2*P */ + Jac_double(X3, Y3, Z3, X1, Y1, Z3); + + /* Compute 3*P = 2P + P */ + Jac_add_affine(LUT(3, 0), LUT(3, 1), LUT(3, 2), X3, Y3, Z3, X1, Y1); + + /* Compute 5*P = 3P + 2P */ + Jac_addition(LUT(5, 0), LUT(5, 1), LUT(5, 2), LUT(3, 0), LUT(3, 1), LUT(3, 2), X3, Y3, Z3); + + /* Compute 7*P = 5P + 2P */ + Jac_addition(LUT(7, 0), LUT(7, 1), LUT(7, 2), LUT(5, 0), LUT(5, 1), LUT(5, 2), X3, Y3, Z3); + + /* Recode the scalar */ + odd = casper_get_word(&scalar[0]) & 1u; + sub_n(M, q, scalar, NUM_LIMBS); // todo!!! + casper_select(scalar, M, scalar, odd, NUM_LIMBS); + + /* Use n=384 and w=4 --> compute ciel(384/3) = 128 + 1 digits */ + uint32_t scalarSysram[/*CASPER_*/ NUM_LIMBS]; + CASPER_MEMCPY(scalarSysram, scalar, /*CASPER_*/ NUM_LIMBS * sizeof(uint32_t)); + recode(rec, scalarSysram, N_bitlen, 4); + + /* Set the first value. */ + index = int8abs(rec[CASPER_RECODE_LENGTH - 1]); + sign = ((uint8_t)rec[CASPER_RECODE_LENGTH - 1]) >> 7; + copy(X3, LUT(index, 0)); + copy(Y3, LUT(index, 1)); + copy(Z3, LUT(index, 2)); + +/* Get the correct LUT element in constant time by touching + * all elements and masking out the correct one. + */ + +#define GET_LUT(x, y, z, index) \ + do \ + { \ + int m; \ + copy(x, LUT(1, 0)); \ + copy(y, LUT(1, 1)); \ + copy(z, LUT(1, 2)); \ + m = (index == 3); \ + casper_select(x, x, LUT(3, 0), m, NUM_LIMBS); \ + casper_select(y, y, LUT(3, 1), m, NUM_LIMBS); \ + casper_select(z, z, LUT(3, 2), m, NUM_LIMBS); \ + m = (index == 5); \ + casper_select(x, x, LUT(5, 0), m, NUM_LIMBS); \ + casper_select(y, y, LUT(5, 1), m, NUM_LIMBS); \ + casper_select(z, z, LUT(5, 2), m, NUM_LIMBS); \ + m = (index == 7); \ + casper_select(x, x, LUT(7, 0), m, NUM_LIMBS); \ + casper_select(y, y, LUT(7, 1), m, NUM_LIMBS); \ + casper_select(z, z, LUT(7, 2), m, NUM_LIMBS); \ + } while (0) + + GET_LUT(X3, Y3, Z3, index); + + /* Compute -y and select the positive or negative point. */ + sub_n(M, p, Y3, NUM_LIMBS); // todo!!! + casper_select(Y3, Y3, M, sign, NUM_LIMBS); + + for (i = CASPER_RECODE_LENGTH - 2; i >= 0; i--) + { + Jac_double(X3, Y3, Z3, X3, Y3, Z3); + Jac_double(X3, Y3, Z3, X3, Y3, Z3); + Jac_double(X3, Y3, Z3, X3, Y3, Z3); + + index = int8abs(rec[i]); + sign = ((uint8_t)rec[i]) >> 7; + + GET_LUT(X, Y, Z, index); + + /* Compute -y and select the positive or negative point. */ + sub_n(scalar, p, Y, NUM_LIMBS); // todo!!! + casper_select(scalar, Y, scalar, sign, NUM_LIMBS); + + Jac_addition(X3, Y3, Z3, X3, Y3, Z3, X, scalar, Z); + } + + sub_n(M, p, Y3, NUM_LIMBS); // todo!!! + + casper_select(Y3, M, Y3, odd, NUM_LIMBS); +} + +#undef LUT +#undef GET_LUT + +/* + * Pre-compute the following 16 points: + * 00 00 = 0*P + 0*Q <-- Not needed when using sliding windows + * 00 01 = 0*P + 1*Q <-- Not needed when using sliding windows + * 00 10 = 0*P + 2*Q + * 00 11 = 0*P + 3*Q + * + * 01 00 = 1*P + 0*Q <-- Not needed when using sliding windows + * 01 01 = 1*P + 1*Q <-- Not needed when using sliding windows + * 01 10 = 1*P + 2*Q + * 01 11 = 1*P + 3*Q + * + * 10 00 = 2*P + 0*Q + * 10 01 = 2*P + 1*Q + * 10 10 = 2*P + 2*Q + * 10 11 = 2*P + 3*Q + * + * 11 00 = 3*P + 0*Q + * 11 01 = 3*P + 1*Q + * 11 10 = 3*P + 2*Q + * 11 11 = 3*P + 3*Q + * + * index = (bitsi||bitsj)-2 - (biti != 0)*2 + * + * Input: P = (X1 : Y1 : Z1) and + * Q = (X2 : Y2 : Z2) + * Output: mem, memory location for the LUT. + */ + +#define LUT_LIMBS NUM_LIMBS + +static void precompute_double_scalar_LUT(uint32_t *Px, uint32_t *Py, uint32_t *Qx, uint32_t *Qy) +{ + uint32_t *Q2x, *Q2y, *Q2z, *P2x, *P2y, *P2z, *Z, *mem; + int index = 0; + + Q2x = &CASPER_MEM[LUT_SCRATCH_START + 48 * LUT_LIMBS + 0 * CASPER_NUM_LIMBS]; + Q2y = &CASPER_MEM[LUT_SCRATCH_START + 48 * LUT_LIMBS + 1 * CASPER_NUM_LIMBS]; + Q2z = &CASPER_MEM[LUT_SCRATCH_START + 48 * LUT_LIMBS + 2 * CASPER_NUM_LIMBS]; + + /* Re-use memory from different scratch space since no + * projective point addition is used below. */ + P2x = &CASPER_MEM[ECC_SCRATCH_START + 5 * CASPER_NUM_LIMBS]; + P2z = &CASPER_MEM[ECC_SCRATCH_START + 6 * CASPER_NUM_LIMBS]; + P2y = &CASPER_MEM[ECC_SCRATCH_START + 7 * CASPER_NUM_LIMBS]; + Z = &CASPER_MEM[ECC_SCRATCH_START + 8 * CASPER_NUM_LIMBS]; + + mem = &CASPER_MEM[LUT_SCRATCH_START]; + + copy(Z, ONE); + + // 00 10 = 0*P + 2*Q + Jac_double(Q2x, Q2y, Q2z, Qx, Qy, Z); + copy(&mem[index], Q2x); + index += LUT_LIMBS; + copy(&mem[index], Q2y); + index += LUT_LIMBS; + copy(&mem[index], Q2z); + index += LUT_LIMBS; + + // 00 11 = 0*P + 3*Q + Jac_add_affine(P2x, P2y, P2z, Q2x, Q2y, Q2z, Qx, Qy); + copy(&mem[index], P2x); + index += LUT_LIMBS; + copy(&mem[index], P2y); + index += LUT_LIMBS; + copy(&mem[index], P2z); + index += LUT_LIMBS; + + // 01 10 = 1*P + 2*Q + Jac_add_affine(P2x, P2y, P2z, Q2x, Q2y, Q2z, Px, Py); + copy(&mem[index], P2x); + index += LUT_LIMBS; + copy(&mem[index], P2y); + index += LUT_LIMBS; + copy(&mem[index], P2z); + index += LUT_LIMBS; + + // 01 11 = 1*P + 3*Q + Jac_add_affine(P2x, P2y, P2z, P2x, P2y, P2z, Qx, Qy); + copy(&mem[index], P2x); + index += LUT_LIMBS; + copy(&mem[index], P2y); + index += LUT_LIMBS; + copy(&mem[index], P2z); + index += LUT_LIMBS; + + // 10 00 = 2*P + 0*Q + Jac_double(P2x, P2y, P2z, Px, Py, Z); + copy(&mem[index], P2x); + index += LUT_LIMBS; + copy(&mem[index], P2y); + index += LUT_LIMBS; + copy(&mem[index], P2z); + index += LUT_LIMBS; + + // 10 01 = 2*P + 1*Q + Jac_add_affine(Q2x, Q2y, Q2z, P2x, P2y, P2z, Qx, Qy); + copy(&mem[index], Q2x); + index += LUT_LIMBS; + copy(&mem[index], Q2y); + index += LUT_LIMBS; + copy(&mem[index], Q2z); + index += LUT_LIMBS; + + // 10 10 = 2*P + 2*Q + Jac_add_affine(Q2x, Q2y, Q2z, Q2x, Q2y, Q2z, Qx, Qy); + copy(&mem[index], Q2x); + index += LUT_LIMBS; + copy(&mem[index], Q2y); + index += LUT_LIMBS; + copy(&mem[index], Q2z); + index += LUT_LIMBS; + + // 10 11 = 2*P + 3*Q + Jac_add_affine(Q2x, Q2y, Q2z, Q2x, Q2y, Q2z, Qx, Qy); + copy(&mem[index], Q2x); + index += LUT_LIMBS; + copy(&mem[index], Q2y); + index += LUT_LIMBS; + copy(&mem[index], Q2z); + index += LUT_LIMBS; + + // 11 00 = 3*P + 0*Q + Jac_add_affine(P2x, P2y, P2z, P2x, P2y, P2z, Px, Py); + copy(&mem[index], P2x); + index += LUT_LIMBS; + copy(&mem[index], P2y); + index += LUT_LIMBS; + copy(&mem[index], P2z); + index += LUT_LIMBS; + + // 11 01 = 3*P + 1*Q + Jac_add_affine(Q2x, Q2y, Q2z, P2x, P2y, P2z, Qx, Qy); + copy(&mem[index], Q2x); + index += LUT_LIMBS; + copy(&mem[index], Q2y); + index += LUT_LIMBS; + copy(&mem[index], Q2z); + index += LUT_LIMBS; + + // 11 10 = 3*P + 2*Q + Jac_add_affine(Q2x, Q2y, Q2z, Q2x, Q2y, Q2z, Qx, Qy); + copy(&mem[index], Q2x); + index += LUT_LIMBS; + copy(&mem[index], Q2y); + index += LUT_LIMBS; + copy(&mem[index], Q2z); + index += LUT_LIMBS; + + // 11 11 = 3*P + 3*Q + Jac_add_affine(Q2x, Q2y, Q2z, Q2x, Q2y, Q2z, Qx, Qy); + copy(&mem[index], Q2x); + index += LUT_LIMBS; + copy(&mem[index], Q2y); + index += LUT_LIMBS; + copy(&mem[index], Q2z); + index += LUT_LIMBS; +} + +#define GETLUTX(x) (3 * (x)*LUT_LIMBS) +#define GETLUTY(x) (3 * (x)*LUT_LIMBS + 1 * LUT_LIMBS) +#define GETLUTZ(x) (3 * (x)*LUT_LIMBS + 2 * LUT_LIMBS) + +/* Compute the double scalar multiplication + * (X3 : Y3 : Z3) = k1 * (X1, Y1) + k2 * (X2, Y2) + * Using Shamir's trick and precomputing 16 points. + * This code is *not* constant time since this is used + * for verification only. + */ +void double_scalar_multiplication(uint32_t *X3, + uint32_t *Y3, + uint32_t *Z3, + uint32_t *X1, + uint32_t *Y1, + uint32_t *k1, + uint32_t *X2, + uint32_t *Y2, + uint32_t *k2) +{ + uint32_t index, c = 0; + uint32_t *p1, *p2, x1, x2, *lut, *Tx, *Ty, *Tz; + + precompute_double_scalar_LUT(X1, Y1, X2, Y2); + + lut = &CASPER_MEM[LUT_SCRATCH_START]; + p1 = &CASPER_MEM[LUT_SCRATCH_START + 48 * LUT_LIMBS]; + p2 = &CASPER_MEM[LUT_SCRATCH_START + 48 * LUT_LIMBS + 1 * CASPER_NUM_LIMBS]; + + Tx = &CASPER_MEM[LUT_SCRATCH_START + 48 * LUT_LIMBS + 2 * CASPER_NUM_LIMBS]; + Ty = &CASPER_MEM[LUT_SCRATCH_START + 48 * LUT_LIMBS + 3 * CASPER_NUM_LIMBS]; + Tz = &CASPER_MEM[LUT_SCRATCH_START + 48 * LUT_LIMBS + 4 * CASPER_NUM_LIMBS]; + + CASPER_MEMCPY(p1, k1, sizeof(uint32_t) * NUM_LIMBS); + CASPER_MEMCPY(p2, k2, sizeof(uint32_t) * NUM_LIMBS); + + /* Check if we can slide. */ + while (((casper_get_word(&p1[NUM_LIMBS - 1]) | casper_get_word(&p2[NUM_LIMBS - 1])) >> 31) == 0 && c < 256) + { + shiftleft(p1, p1, 1); + shiftleft(p2, p2, 1); + c++; + /* No doubling needed. */ + } + + /* Set the first value. */ + x1 = casper_get_word(&p1[NUM_LIMBS - 1]) >> 30; + x2 = casper_get_word(&p2[NUM_LIMBS - 1]) >> 30; + index = (x2 | (x1 << 2)) - 2 - (x1 != 0) * 2; + shiftleft(p1, p1, 2); + shiftleft(p2, p2, 2); + + copy(X3, &lut[GETLUTX(index)]); + copy(Y3, &lut[GETLUTY(index)]); + copy(Z3, &lut[GETLUTZ(index)]); + c += 2; + +// todo: create an is_zero function +#if CASPER_ECC_P256 + while ((casper_get_word(&p1[0]) | casper_get_word(&p1[1]) | casper_get_word(&p1[2]) | casper_get_word(&p1[3]) | + casper_get_word(&p1[4]) | casper_get_word(&p1[5]) | casper_get_word(&p1[6]) | casper_get_word(&p1[7]) | + casper_get_word(&p2[0]) | casper_get_word(&p2[1]) | casper_get_word(&p2[2]) | casper_get_word(&p2[3]) | + casper_get_word(&p2[4]) | casper_get_word(&p2[5]) | casper_get_word(&p2[6]) | casper_get_word(&p2[7])) != 0) + { +#elif CASPER_ECC_P384 + while ((casper_get_word(&p1[0]) | casper_get_word(&p1[1]) | casper_get_word(&p1[2]) | casper_get_word(&p1[3]) | + casper_get_word(&p1[4]) | casper_get_word(&p1[5]) | casper_get_word(&p1[6]) | casper_get_word(&p1[7]) | + casper_get_word(&p1[8]) | casper_get_word(&p1[9]) | casper_get_word(&p1[10]) | casper_get_word(&p1[11]) | + casper_get_word(&p2[0]) | casper_get_word(&p2[1]) | casper_get_word(&p2[2]) | casper_get_word(&p2[3]) | + casper_get_word(&p2[4]) | casper_get_word(&p2[5]) | casper_get_word(&p2[6]) | casper_get_word(&p2[7]) | + casper_get_word(&p2[8]) | casper_get_word(&p2[9]) | casper_get_word(&p2[10]) | casper_get_word(&p2[11])) != + 0) + { +#endif + /* Check if we can slide. */ + while (((casper_get_word(&p1[NUM_LIMBS - 1]) | casper_get_word(&p2[NUM_LIMBS - 1])) >> 31) == 0 && c < N_bitlen) + { + shiftleft(p1, p1, 1); + shiftleft(p2, p2, 1); + Jac_double(X3, Y3, Z3, X3, Y3, Z3); + c++; + } + + if (c >= (N_bitlen - 1)) + break; + + /* Double twice. */ + Jac_double(X3, Y3, Z3, X3, Y3, Z3); + Jac_double(X3, Y3, Z3, X3, Y3, Z3); + + /* Add in the correct value. */ + x1 = casper_get_word(&p1[NUM_LIMBS - 1]) >> 30; + x2 = casper_get_word(&p2[NUM_LIMBS - 1]) >> 30; + index = (x2 | (x1 << 2)) - 2 - (x1 != 0) * 2; + + shiftleft(p1, p1, 2); + shiftleft(p2, p2, 2); + + copy(Tx, &lut[GETLUTX(index)]); + copy(Ty, &lut[GETLUTY(index)]); + copy(Tz, &lut[GETLUTZ(index)]); + + Jac_addition(X3, Y3, Z3, X3, Y3, Z3, Tx, Ty, + Tz); //&lut[GETLUTX(index)], &lut[GETLUTY(index)], &lut[GETLUTZ(index)]); + c += 2; + } + + /* Special case in the end. */ + if (c == (N_bitlen - 1)) + { + Jac_double(X3, Y3, Z3, X3, Y3, Z3); + x1 = casper_get_word(&p1[NUM_LIMBS - 1]) >> 31; + x2 = casper_get_word(&p2[NUM_LIMBS - 1]) >> 31; + if (x1) + { + Jac_add_affine(X3, Y3, Z3, X3, Y3, Z3, X1, Y1); + } + if (x2) + { + Jac_add_affine(X3, Y3, Z3, X3, Y3, Z3, X2, Y2); + } + c++; + } + + while (c < N_bitlen) + { + Jac_double(X3, Y3, Z3, X3, Y3, Z3); + c++; + } +} + +#if CASPER_ECC_P256 +static void invert_mod_p256(uint32_t *c, uint32_t *a) +{ + int i; + uint32_t *t, *t2, *s1, *s2, *s4, *s8, *tmp; + + /* Assuming it is safe to use the ECC scratch size. */ + t = &CASPER_MEM[ECC_SCRATCH_START + 2 * CASPER_NUM_LIMBS]; + t2 = &CASPER_MEM[ECC_SCRATCH_START + 3 * CASPER_NUM_LIMBS]; + s1 = &CASPER_MEM[ECC_SCRATCH_START + 4 * CASPER_NUM_LIMBS]; + s2 = &CASPER_MEM[ECC_SCRATCH_START + 5 * CASPER_NUM_LIMBS]; + s4 = &CASPER_MEM[ECC_SCRATCH_START + 6 * CASPER_NUM_LIMBS]; + s8 = &CASPER_MEM[ECC_SCRATCH_START + 7 * CASPER_NUM_LIMBS]; + tmp = &CASPER_MEM[ECC_SCRATCH_START + 8 * CASPER_NUM_LIMBS]; + + // t2 = n^(2^1)*n # 11 + square_casper(tmp, a); + multiply_casper(t2, tmp, a); + + // s1 = t2^(2^2)*t2 # F + square_casper(s1, t2); + square_casper(tmp, s1); + multiply_casper(s1, tmp, t2); + + // s2 = s1^(2^4)*s1 # FF + square_casper(s2, s1); + // for (i = 1; i < 4; i++) square(s2, s2); + square_casper(tmp, s2); + square_casper(s2, tmp); + square_casper(tmp, s2); + multiply_casper(s2, tmp, s1); + + // s4 = s2^(2^8)*s2 # FFFF + square_casper(s4, s2); + for (i = 1; i < 7; i += 2) + { + square_casper(tmp, s4); + square_casper(s4, tmp); + } + square_casper(tmp, s4); + multiply_casper(s4, tmp, s2); + + // s8 = s4^(2^16)*s4 # FFFFFFFF + square_casper(s8, s4); + for (i = 1; i < 15; i += 2) + { + square_casper(tmp, s8); + square_casper(s8, tmp); + } + square_casper(tmp, s8); + multiply_casper(s8, tmp, s4); + + // t = s8^(2^32)*n # ffffffff00000001 + square_casper(tmp, s8); + for (i = 1; i < 31; i += 2) + { + square_casper(t, tmp); + square_casper(tmp, t); + } + square_casper(t, tmp); + multiply_casper(tmp, t, a); + + // t = t^(2^128)*s8 # ffffffff00000001000000000000000000000000ffffffff + for (i = 0; i < 128; i += 2) + { + square_casper(t, tmp); + square_casper(tmp, t); + } + multiply_casper(t, tmp, s8); + + // t = t^(2^32)*s8 # ffffffff00000001000000000000000000000000ffffffffffffffff + for (i = 0; i < 32; i += 2) + { + square_casper(tmp, t); + square_casper(t, tmp); + } + multiply_casper(tmp, t, s8); + + // t = t^(2^16)*s4 # ffffffff00000001000000000000000000000000ffffffffffffffffffff + for (i = 0; i < 16; i += 2) + { + square_casper(t, tmp); + square_casper(tmp, t); + } + multiply_casper(t, tmp, s4); + + // t = t^(2^8)*s2 # ffffffff00000001000000000000000000000000ffffffffffffffffffffff + for (i = 0; i < 8; i += 2) + { + square_casper(tmp, t); + square_casper(t, tmp); + } + multiply_casper(tmp, t, s2); + + // t = t^(2^4)*s1 # ffffffff00000001000000000000000000000000fffffffffffffffffffffff + for (i = 0; i < 4; i += 2) + { + square_casper(t, tmp); + square_casper(tmp, t); + } + multiply_casper(t, tmp, s1); + + // t = t^(2^2)*t2 + square_casper(tmp, t); + square_casper(t, tmp); + multiply_casper(tmp, t, t2); + + // t = t^(2^2)*n # ffffffff00000001000000000000000000000000fffffffffffffffffffffffd + square_casper(t, tmp); + square_casper(tmp, t); + multiply_casper(c, tmp, a); +} + +// A and C do not need to be in Casper memory +static void toMontgomery(uint32_t *C, uint32_t *A) +{ + /* R^2 = 2^512 mod p, used to convert values to Montgomery form. */ + uint32_t R2[NUM_LIMBS] = {0x00000003, 0x00000000, 0xffffffff, 0xfffffffb, 0xfffffffe, 0xffffffff, 0xfffffffd, 0x4}; + uint32_t *T1, *T2, *T3; + T1 = &CASPER_MEM[ECC_SCRATCH_START + 0 * CASPER_NUM_LIMBS]; + T2 = &CASPER_MEM[ECC_SCRATCH_START + 1 * CASPER_NUM_LIMBS]; + T3 = &CASPER_MEM[ECC_SCRATCH_START + 2 * CASPER_NUM_LIMBS]; + + CASPER_MEMCPY(T1, R2, NUM_LIMBS * sizeof(uint32_t)); + CASPER_MEMCPY(T2, A, NUM_LIMBS * sizeof(uint32_t)); + + multiply_casper(T3, T2, T1); + CASPER_MEMCPY(C, T3, NUM_LIMBS * sizeof(uint32_t)); +} +#endif /* CASPER_ECC_P256 */ + +/* Compute inversion modulo NIST-p384 using Fermats little theorem. + * Using c = a^(p-2) = a^(-1) mod p. + * This computes the modular inversion if all arithmetic is "regular" + * modular arithmetic or computes automatically the Montgomery inverse + * if all arithmetic is Montgomery arithmetic. + */ +#if CASPER_ECC_P384 +static void invert_mod_p384(uint32_t *c, uint32_t *a) +{ + int i; + uint32_t *e, *d, *tmp, *t0, *t1, *t2, *t3, *t4, *t5, *t6; // 10 residues needed + + /* Assuming it is safe to use the LUT scratch size. + * Hence, do not invert while elements in the LUT are needed. + */ + e = &CASPER_MEM[LUT_SCRATCH_START + 0 * CASPER_NUM_LIMBS]; + d = &CASPER_MEM[LUT_SCRATCH_START + 1 * CASPER_NUM_LIMBS]; + tmp = &CASPER_MEM[LUT_SCRATCH_START + 2 * CASPER_NUM_LIMBS]; + t0 = &CASPER_MEM[LUT_SCRATCH_START + 3 * CASPER_NUM_LIMBS]; + t1 = &CASPER_MEM[LUT_SCRATCH_START + 4 * CASPER_NUM_LIMBS]; + t2 = &CASPER_MEM[LUT_SCRATCH_START + 5 * CASPER_NUM_LIMBS]; + t3 = &CASPER_MEM[LUT_SCRATCH_START + 6 * CASPER_NUM_LIMBS]; + t4 = &CASPER_MEM[LUT_SCRATCH_START + 7 * CASPER_NUM_LIMBS]; + t5 = &CASPER_MEM[LUT_SCRATCH_START + 8 * CASPER_NUM_LIMBS]; + t6 = &CASPER_MEM[LUT_SCRATCH_START + 9 * CASPER_NUM_LIMBS]; + + square_casper(tmp, a); // 2 + square_casper(t1, tmp); // 4 + square_casper(tmp, t1); // 8 + multiply_casper(t2, tmp, t1); // 12 + multiply_casper(d, a, t2); // 13 + multiply_casper(e, d, a); // 14 + multiply_casper(t0, e, a); // 15 + + // t1 = t0^(2^4)*t0 # ff + square_casper(tmp, t0); + square_casper(t1, tmp); + square_casper(tmp, t1); + square_casper(t2, tmp); + multiply_casper(t1, t2, t0); + + // t2 = t1^(2^8)*t1 # 4f + square_casper(tmp, t1); + for (i = 0; i < 3; i++) + { + square_casper(t3, tmp); + square_casper(tmp, t3); + } + square_casper(t3, tmp); + multiply_casper(t2, t3, t1); + + // t3 = t2^(2^16)*t2 # 8f + square_casper(tmp, t2); + for (i = 0; i < 7; i++) + { + square_casper(t4, tmp); + square_casper(tmp, t4); + } + square_casper(t4, tmp); + multiply_casper(t3, t4, t2); + + // t4 = t3^(2^32)*t3 # 16f + square_casper(tmp, t3); + for (i = 0; i < 15; i++) + { + square_casper(t5, tmp); + square_casper(tmp, t5); + } + square_casper(t5, tmp); + multiply_casper(t4, t5, t3); + + // t5 = t4^(2^64)*t4 # 32f + square_casper(tmp, t4); + for (i = 0; i < 31; i++) + { + square_casper(t6, tmp); + square_casper(tmp, t6); + } + square_casper(t6, tmp); + multiply_casper(t5, t6, t4); + + // t5 = t5^(2^64)*t4 # 48f + square_casper(tmp, t5); + for (i = 0; i < 31; i++) + { + square_casper(t6, tmp); + square_casper(tmp, t6); + } + square_casper(t6, tmp); + multiply_casper(t5, t6, t4); + + // t5 = t5^(2^32)*t3 # 56f + square_casper(tmp, t5); + for (i = 0; i < 15; i++) + { + square_casper(t6, tmp); + square_casper(tmp, t6); + } + square_casper(t6, tmp); + multiply_casper(t5, t6, t3); + + // t5 = t5^(2^16)*t2 # 60f + square_casper(tmp, t5); + for (i = 0; i < 7; i++) + { + square_casper(t6, tmp); + square_casper(tmp, t6); + } + square_casper(t6, tmp); + multiply_casper(t5, t6, t2); + + // t5 = t5^(2^8)*t1 # 62f + square_casper(tmp, t5); + for (i = 0; i < 3; i++) + { + square_casper(t6, tmp); + square_casper(tmp, t6); + } + square_casper(t6, tmp); + multiply_casper(t5, t6, t1); + + // n = t5^(2^4)*t0 # 63f + square_casper(tmp, t5); + for (i = 0; i < 1; i++) + { + square_casper(t6, tmp); + square_casper(tmp, t6); + } + square_casper(t6, tmp); + multiply_casper(t5, t6, t0); + + // n = n^(2^4)*e + square_casper(tmp, t5); + for (i = 0; i < 1; i++) + { + square_casper(t6, tmp); + square_casper(tmp, t6); + } + square_casper(t6, tmp); + multiply_casper(t5, t6, e); + + // n = n^(2^32)*t3 + square_casper(tmp, t5); + for (i = 0; i < 15; i++) + { + square_casper(t6, tmp); + square_casper(tmp, t6); + } + square_casper(t6, tmp); + multiply_casper(t5, t6, t3); + + // n = n^(2^64) + square_casper(tmp, t5); + for (i = 0; i < 31; i++) + { + square_casper(t6, tmp); + square_casper(tmp, t6); + } + square_casper(t5, tmp); + + // n = n^(2^16)*t2 + square_casper(tmp, t5); + for (i = 0; i < 7; i++) + { + square_casper(t6, tmp); + square_casper(tmp, t6); + } + square_casper(t6, tmp); + multiply_casper(t5, t6, t2); + + // n = n^(2^8)*t1 + square_casper(tmp, t5); + for (i = 0; i < 3; i++) + { + square_casper(t6, tmp); + square_casper(tmp, t6); + } + square_casper(t6, tmp); + multiply_casper(t5, t6, t1); + + // n = n^(2^4)*t0 + square_casper(tmp, t5); + for (i = 0; i < 1; i++) + { + square_casper(t6, tmp); + square_casper(tmp, t6); + } + square_casper(t6, tmp); + multiply_casper(t5, t6, t0); + + // n = n^(2^4)*d + square_casper(tmp, t5); + for (i = 0; i < 1; i++) + { + square_casper(t6, tmp); + square_casper(tmp, t6); + } + square_casper(t6, tmp); + multiply_casper(c, t6, d); +} + +// A and C do not need to be in Casper memory +static void toMontgomery(uint32_t *C, uint32_t *A) +{ + /* R^2 = 2^768 mod p, used to convert values to Montgomery form. */ + uint32_t R2[NUM_LIMBS] = {0x00000001, 0xfffffffe, 0x00000000, 0x00000002, 0x00000000, 0xfffffffe, + 0x00000000, 0x00000002, 0x1, 0x0, 0x0, 0x0}; + uint32_t *T1, *T2, *T3; + T1 = &CASPER_MEM[ECC_SCRATCH_START + 0 * CASPER_NUM_LIMBS]; + T2 = &CASPER_MEM[ECC_SCRATCH_START + 1 * CASPER_NUM_LIMBS]; + T3 = &CASPER_MEM[ECC_SCRATCH_START + 2 * CASPER_NUM_LIMBS]; + + CASPER_MEMCPY(T1, R2, NUM_LIMBS * sizeof(uint32_t)); + CASPER_MEMCPY(T2, A, NUM_LIMBS * sizeof(uint32_t)); + + multiply_casper(T3, T2, T1); + CASPER_MEMCPY(C, T3, NUM_LIMBS * sizeof(uint32_t)); +} +#endif /* CASPER_ECC_P384 */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_casper.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_casper.h new file mode 100644 index 000000000..b7cc9dbe0 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_casper.h @@ -0,0 +1,301 @@ +/* + * Copyright 2018 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_CASPER_H_ +#define _FSL_CASPER_H_ + +#include "fsl_common.h" + +/*! @file */ + +/******************************************************************************* + * Definitions + *******************************************************************************/ + +/*! + * @addtogroup casper_driver + * @{ + */ +/*! @name Driver version */ +/*@{*/ +/*! @brief CASPER driver version. Version 2.0.2. + * + * Current version: 2.0.2 + * + * Change log: + * - Version 2.0.0 + * - Initial version + * - Version 2.0.1 + * - Bug fix KPSDK-24531 double_scalar_multiplication() result may be all zeroes for some specific input + * - Version 2.0.2 + * - Bug fix KPSDK-25015 CASPER_MEMCPY hard-fault on LPC55xx when both source and destination buffers are outside of CASPER_RAM + */ +#define FSL_CASPER_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) +/*@}*/ + +/*! @brief CASPER operation + * + */ +typedef enum _casper_operation +{ + kCASPER_OpMul6464NoSum = 0x01, /*! Walking 1 or more of J loop, doing r=a*b using 64x64=128*/ + kCASPER_OpMul6464Sum = + 0x02, /*! Walking 1 or more of J loop, doing c,r=r+a*b using 64x64=128, but assume inner j loop*/ + kCASPER_OpMul6464FullSum = + 0x03, /*! Walking 1 or more of J loop, doing c,r=r+a*b using 64x64=128, but sum all of w. */ + kCASPER_OpMul6464Reduce = + 0x04, /*! Walking 1 or more of J loop, doing c,r[-1]=r+a*b using 64x64=128, but skip 1st write*/ + kCASPER_OpAdd64 = 0x08, /*! Walking add with off_AB, and in/out off_RES doing c,r=r+a+c using 64+64=65*/ + kCASPER_OpSub64 = 0x09, /*! Walking subtract with off_AB, and in/out off_RES doing r=r-a uding 64-64=64, with last + borrow implicit if any*/ + kCASPER_OpDouble64 = 0x0A, /*! Walking add to self with off_RES doing c,r=r+r+c using 64+64=65*/ + kCASPER_OpXor64 = 0x0B, /*! Walking XOR with off_AB, and in/out off_RES doing r=r^a using 64^64=64*/ + kCASPER_OpShiftLeft32 = + 0x10, /*! Walking shift left doing r1,r=(b*D)|r1, where D is 2^amt and is loaded by app (off_CD not used)*/ + kCASPER_OpShiftRight32 = 0x11, /*! Walking shift right doing r,r1=(b*D)|r1, where D is 2^(32-amt) and is loaded by + app (off_CD not used) and off_RES starts at MSW*/ + kCASPER_OpCopy = 0x14, /*! Copy from ABoff to resoff, 64b at a time*/ + kCASPER_OpRemask = 0x15, /*! Copy and mask from ABoff to resoff, 64b at a time*/ + kCASPER_OpCompare = 0x16, /*! Compare two arrays, running all the way to the end*/ + kCASPER_OpCompareFast = 0x17, /*! Compare two arrays, stopping on 1st !=*/ +} casper_operation_t; + +#define CASPER_CP 1 +#define CASPER_CP_CTRL0 (0x0 >> 2) +#define CASPER_CP_CTRL1 (0x4 >> 2) +#define CASPER_CP_LOADER (0x8 >> 2) +#define CASPER_CP_STATUS (0xC >> 2) +#define CASPER_CP_INTENSET (0x10 >> 2) +#define CASPER_CP_INTENCLR (0x14 >> 2) +#define CASPER_CP_INTSTAT (0x18 >> 2) +#define CASPER_CP_AREG (0x20 >> 2) +#define CASPER_CP_BREG (0x24 >> 2) +#define CASPER_CP_CREG (0x28 >> 2) +#define CASPER_CP_DREG (0x2C >> 2) +#define CASPER_CP_RES0 (0x30 >> 2) +#define CASPER_CP_RES1 (0x34 >> 2) +#define CASPER_CP_RES2 (0x38 >> 2) +#define CASPER_CP_RES3 (0x3C >> 2) +#define CASPER_CP_MASK (0x60 >> 2) +#define CASPER_CP_REMASK (0x64 >> 2) +#define CASPER_CP_LOCK (0x80 >> 2) +#define CASPER_CP_ID (0xFFC >> 2) +/* mcr (cp, opc1, value, CRn, CRm, opc2) */ +#define CASPER_Wr32b(value, off) __arm_mcr(CASPER_CP, 0, value, ((off >> 4)), (off), 0) +/* mcrr(coproc, opc1, value, CRm) */ +#define CASPER_Wr64b(value, off) __arm_mcrr(CASPER_CP, 0, value, off) +/* mrc(coproc, opc1, CRn, CRm, opc2) */ +#define CASPER_Rd32b(off) __arm_mrc(CASPER_CP, 0, ((off >> 4)), (off), 0) + +/* The model for this algo is that it can be implemented for a fixed size RSA key */ +/* for max speed. If this is made into a variable (to allow varying size), then */ +/* it will be slower by a bit. */ +/* The file is compiled with N_bitlen passed in as number of bits of the RSA key */ +/* #define N_bitlen 2048 */ +#define N_wordlen_max (4096 / 32) + +#define CASPER_ECC_P256 1 +#define CASPER_ECC_P384 0 + +#if CASPER_ECC_P256 +#define N_bitlen 256 +#endif /* CASPER_ECC_P256 */ + +#if CASPER_ECC_P384 +#define N_bitlen 384 +#endif /* CASPER_ECC_P256 */ + +#define NUM_LIMBS (N_bitlen / 32) + +enum +{ + kCASPER_RamOffset_Result = 0x0u, + kCASPER_RamOffset_Base = (N_wordlen_max + 8u), + kCASPER_RamOffset_TempBase = (2u * N_wordlen_max + 16u), + kCASPER_RamOffset_Modulus = (kCASPER_RamOffset_TempBase + N_wordlen_max + 4u), + kCASPER_RamOffset_M64 = 1022, +}; + +/*! @} */ + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @addtogroup casper_driver + * @{ + */ + +/*! + * @brief Enables clock and disables reset for CASPER peripheral. + * + * Enable clock and disable reset for CASPER. + * + * @param base CASPER base address + */ +void CASPER_Init(CASPER_Type *base); + +/*! + * @brief Disables clock for CASPER peripheral. + * + * Disable clock and enable reset. + * + * @param base CASPER base address + */ +void CASPER_Deinit(CASPER_Type *base); + +/*! + *@} + */ /* end of casper_driver */ + +/******************************************************************************* + * PKHA API + ******************************************************************************/ + +/*! + * @addtogroup casper_driver_pkha + * @{ + */ + +/*! + * @brief Performs modular exponentiation - (A^E) mod N. + * + * This function performs modular exponentiation. + * + * @param base CASPER base address + * @param signature first addend (in little endian format) + * @param pubN modulus (in little endian format) + * @param wordLen Size of pubN in bytes + * @param pubE exponent + * @param[out] plaintext Output array to store result of operation (in little endian format) + */ +void CASPER_ModExp(CASPER_Type *base, + const uint8_t *signature, + const uint8_t *pubN, + size_t wordLen, + uint32_t pubE, + uint8_t *plaintext); + +void CASPER_ecc_init(void); + +/*! + * @brief Performs ECC secp256r1 point single scalar multiplication + * + * This function performs ECC secp256r1 point single scalar multiplication + * [resX; resY] = scalar * [X; Y] + * Coordinates are affine in normal form, little endian. + * Scalars are little endian. + * All arrays are little endian byte arrays, uint32_t type is used + * only to enforce the 32-bit alignment (0-mod-4 address). + * + * @param base CASPER base address + * @param[out] resX Output X affine coordinate in normal form, little endian. + * @param[out] resY Output Y affine coordinate in normal form, little endian. + * @param X Input X affine coordinate in normal form, little endian. + * @param Y Input Y affine coordinate in normal form, little endian. + * @param scalar Input scalar integer, in normal form, little endian. + */ +void CASPER_ECC_SECP256R1_Mul( + CASPER_Type *base, uint32_t resX[8], uint32_t resY[8], uint32_t X[8], uint32_t Y[8], uint32_t scalar[8]); + +/*! + * @brief Performs ECC secp256r1 point double scalar multiplication + * + * This function performs ECC secp256r1 point double scalar multiplication + * [resX; resY] = scalar1 * [X1; Y1] + scalar2 * [X2; Y2] + * Coordinates are affine in normal form, little endian. + * Scalars are little endian. + * All arrays are little endian byte arrays, uint32_t type is used + * only to enforce the 32-bit alignment (0-mod-4 address). + * + * @param base CASPER base address + * @param[out] resX Output X affine coordinate. + * @param[out] resY Output Y affine coordinate. + * @param X1 Input X1 affine coordinate. + * @param Y1 Input Y1 affine coordinate. + * @param scalar1 Input scalar1 integer. + * @param X2 Input X2 affine coordinate. + * @param Y2 Input Y2 affine coordinate. + * @param scalar2 Input scalar2 integer. + */ +void CASPER_ECC_SECP256R1_MulAdd(CASPER_Type *base, + uint32_t resX[8], + uint32_t resY[8], + uint32_t X1[8], + uint32_t Y1[8], + uint32_t scalar1[8], + uint32_t X2[8], + uint32_t Y2[8], + uint32_t scalar2[8]); + +/*! + * @brief Performs ECC secp384r1 point single scalar multiplication + * + * This function performs ECC secp384r1 point single scalar multiplication + * [resX; resY] = scalar * [X; Y] + * Coordinates are affine in normal form, little endian. + * Scalars are little endian. + * All arrays are little endian byte arrays, uint32_t type is used + * only to enforce the 32-bit alignment (0-mod-4 address). + * + * @param base CASPER base address + * @param[out] resX Output X affine coordinate in normal form, little endian. + * @param[out] resY Output Y affine coordinate in normal form, little endian. + * @param X Input X affine coordinate in normal form, little endian. + * @param Y Input Y affine coordinate in normal form, little endian. + * @param scalar Input scalar integer, in normal form, little endian. + */ +void CASPER_ECC_SECP384R1_Mul( + CASPER_Type *base, uint32_t resX[12], uint32_t resY[12], uint32_t X[12], uint32_t Y[12], uint32_t scalar[12]); + +/*! + * @brief Performs ECC secp384r1 point double scalar multiplication + * + * This function performs ECC secp384r1 point double scalar multiplication + * [resX; resY] = scalar1 * [X1; Y1] + scalar2 * [X2; Y2] + * Coordinates are affine in normal form, little endian. + * Scalars are little endian. + * All arrays are little endian byte arrays, uint32_t type is used + * only to enforce the 32-bit alignment (0-mod-4 address). + * + * @param base CASPER base address + * @param[out] resX Output X affine coordinate. + * @param[out] resY Output Y affine coordinate. + * @param X1 Input X1 affine coordinate. + * @param Y1 Input Y1 affine coordinate. + * @param scalar1 Input scalar1 integer. + * @param X2 Input X2 affine coordinate. + * @param Y2 Input Y2 affine coordinate. + * @param scalar2 Input scalar2 integer. + */ +void CASPER_ECC_SECP384R1_MulAdd(CASPER_Type *base, + uint32_t resX[12], + uint32_t resY[12], + uint32_t X1[12], + uint32_t Y1[12], + uint32_t scalar1[12], + uint32_t X2[12], + uint32_t Y2[12], + uint32_t scalar2[12]); + +void CASPER_ECC_equal(int *res, uint32_t *op1, uint32_t *op2); +void CASPER_ECC_equal_to_zero(int *res, uint32_t *op1); + +/*! + *@} + */ /* end of casper_driver_pkha */ + +#if defined(__cplusplus) +} +#endif + +#endif /* _FSL_CASPER_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_clock.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_clock.c new file mode 100644 index 000000000..b221bd7e2 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_clock.c @@ -0,0 +1,2099 @@ +/* + * Copyright 2017 - 2019 , NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_clock.h" +#include "fsl_power.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.clock" +#endif +#define NVALMAX (0x100U) +#define PVALMAX (0x20U) +#define MVALMAX (0x10000U) + +#define PLL_MAX_N_DIV 0x100U + +/*-------------------------------------------------------------------------- +!!! If required these #defines can be moved to chip library file +----------------------------------------------------------------------------*/ + +#define PLL_SSCG1_MDEC_VAL_P (10U) /* MDEC is in bits 16 downto 0 */ +#define PLL_SSCG1_MDEC_VAL_M (0x3FFFC00ULL << PLL_SSCG1_MDEC_VAL_P) /* NDEC is in bits 9 downto 0 */ +#define PLL_NDEC_VAL_P (0U) /* NDEC is in bits 9:0 */ +#define PLL_NDEC_VAL_M (0xFFUL << PLL_NDEC_VAL_P) +#define PLL_PDEC_VAL_P (0U) /*!< PDEC is in bits 6:0 */ +#define PLL_PDEC_VAL_M (0x1FUL << PLL_PDEC_VAL_P) + +#define PLL_MIN_CCO_FREQ_MHZ (275000000U) +#define PLL_MAX_CCO_FREQ_MHZ (550000000U) +#define PLL_LOWER_IN_LIMIT (2000U) /*!< Minimum PLL input rate */ +#define PLL_HIGHER_IN_LIMIT (150000000U) /*!< Maximum PLL input rate */ +#define PLL_MIN_IN_SSMODE (3000000U) +#define PLL_MAX_IN_SSMODE \ + (100000000U) /*!< Not find the value in UM, Just use the maximum frequency which device support */ + +/* PLL NDEC reg */ +#define PLL_NDEC_VAL_SET(value) (((unsigned long)(value) << PLL_NDEC_VAL_P) & PLL_NDEC_VAL_M) +/* PLL PDEC reg */ +#define PLL_PDEC_VAL_SET(value) (((unsigned long)(value) << PLL_PDEC_VAL_P) & PLL_PDEC_VAL_M) +/* SSCG control0 */ +#define PLL_SSCG1_MDEC_VAL_SET(value) (((unsigned long)(value) << PLL_SSCG1_MDEC_VAL_P) & PLL_SSCG1_MDEC_VAL_M) + +/* PLL0 SSCG control1 */ +#define PLL0_SSCG_MD_FRACT_P 0U +#define PLL0_SSCG_MD_INT_P 25U +#define PLL0_SSCG_MD_FRACT_M (0x1FFFFFFUL << PLL0_SSCG_MD_FRACT_P) +#define PLL0_SSCG_MD_INT_M ((uint64_t)0xFFUL << PLL0_SSCG_MD_INT_P) + +#define PLL0_SSCG_MD_FRACT_SET(value) (((uint64_t)(value) << PLL0_SSCG_MD_FRACT_P) & PLL0_SSCG_MD_FRACT_M) +#define PLL0_SSCG_MD_INT_SET(value) (((uint64_t)(value) << PLL0_SSCG_MD_INT_P) & PLL0_SSCG_MD_INT_M) + +/* Saved value of PLL output rate, computed whenever needed to save run-time + computation on each call to retrive the PLL rate. */ +static uint32_t s_Pll0_Freq; +static uint32_t s_Pll1_Freq; + +/** External clock rate on the CLKIN pin in Hz. If not used, + set this to 0. Otherwise, set it to the exact rate in Hz this pin is + being driven at. */ +static uint32_t s_Ext_Clk_Freq = 16000000U; +static uint32_t s_I2S_Mclk_Freq = 0U; + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/* Find SELP, SELI, and SELR values for raw M value, max M = MVALMAX */ +static void pllFindSel(uint32_t M, uint32_t *pSelP, uint32_t *pSelI, uint32_t *pSelR); +/* Get predivider (N) from PLL0 NDEC setting */ +static uint32_t findPll0PreDiv(void); +/* Get predivider (N) from PLL1 NDEC setting */ +static uint32_t findPll1PreDiv(void); +/* Get postdivider (P) from PLL0 PDEC setting */ +static uint32_t findPll0PostDiv(void); +/* Get multiplier (M) from PLL0 MDEC and SSCG settings */ +static float findPll0MMult(void); +/* Get the greatest common divisor */ +static uint32_t FindGreatestCommonDivisor(uint32_t m, uint32_t n); +/* Set PLL output based on desired output rate */ +static pll_error_t CLOCK_GetPll0Config(uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup, bool useSS); +/* Update local PLL rate variable */ +static void CLOCK_GetPLL0OutFromSetupUpdate(pll_setup_t *pSetup); + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* Clock Selection for IP */ +/** + * brief Configure the clock selection muxes. + * param connection : Clock to be configured. + * return Nothing + */ +void CLOCK_AttachClk(clock_attach_id_t connection) +{ + uint8_t mux; + uint8_t sel; + uint16_t item; + uint32_t tmp32 = (uint32_t)connection; + uint32_t i; + volatile uint32_t *pClkSel; + + pClkSel = &(SYSCON->SYSTICKCLKSELX[0]); + + if (kNONE_to_NONE != connection) + { + for (i = 0U; i < 2U; i++) + { + if (tmp32 == 0U) + { + break; + } + item = (uint16_t)GET_ID_ITEM(tmp32); + if (item) + { + mux = GET_ID_ITEM_MUX(item); + sel = GET_ID_ITEM_SEL(item); + if (mux == CM_RTCOSC32KCLKSEL) + { + PMC->RTCOSC32K |= sel; + } + else + { + pClkSel[mux] = sel; + } + } + tmp32 = GET_ID_NEXT_ITEM(tmp32); /* pick up next descriptor */ + } + } +} + +/* Return the actual clock attach id */ +/** + * brief Get the actual clock attach id. + * This fuction uses the offset in input attach id, then it reads the actual source value in + * the register and combine the offset to obtain an actual attach id. + * param attachId : Clock attach id to get. + * return Clock source value. + */ +clock_attach_id_t CLOCK_GetClockAttachId(clock_attach_id_t attachId) +{ + uint8_t mux; + uint8_t actualSel; + uint32_t tmp32 = (uint32_t)attachId; + uint32_t i; + uint32_t actualAttachId = 0U; + uint32_t selector = GET_ID_SELECTOR(tmp32); + volatile uint32_t *pClkSel; + + pClkSel = &(SYSCON->SYSTICKCLKSELX[0]); + + if (kNONE_to_NONE == attachId) + { + return kNONE_to_NONE; + } + + for (i = 0U; i < 2U; i++) + { + mux = GET_ID_ITEM_MUX(tmp32); + if (tmp32) + { + if (mux == CM_RTCOSC32KCLKSEL) + { + actualSel = PMC->RTCOSC32K; + } + else + { + actualSel = pClkSel[mux]; + } + + /* Consider the combination of two registers */ + actualAttachId |= CLK_ATTACH_ID(mux, actualSel, i); + } + tmp32 = GET_ID_NEXT_ITEM(tmp32); /*!< pick up next descriptor */ + } + + actualAttachId |= selector; + + return (clock_attach_id_t)actualAttachId; +} + +/* Set IP Clock Divider */ +/** + * brief Setup peripheral clock dividers. + * param div_name : Clock divider name + * param divided_by_value: Value to be divided + * param reset : Whether to reset the divider counter. + * return Nothing + */ +void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool reset) +{ + volatile uint32_t *pClkDiv; + + pClkDiv = &(SYSCON->SYSTICKCLKDIV0); + if (reset) + { + pClkDiv[div_name] = 1U << 29U; + } + if (divided_by_value == 0U) /*!< halt */ + { + pClkDiv[div_name] = 1U << 30U; + } + else + { + pClkDiv[div_name] = (divided_by_value - 1U); + } +} + +/* Set RTC 1KHz Clock Divider */ +/** + * brief Setup rtc 1khz clock divider. + * param divided_by_value: Value to be divided + * return Nothing + */ +void CLOCK_SetRtc1khzClkDiv(uint32_t divided_by_value) +{ + PMC->RTCOSC32K |= (((divided_by_value - 28U) << PMC_RTCOSC32K_CLK1KHZDIV_SHIFT) | PMC_RTCOSC32K_CLK1KHZDIV_MASK); +} + +/* Set RTC 1KHz Clock Divider */ +/** + * brief Setup rtc 1hz clock divider. + * param divided_by_value: Value to be divided + * return Nothing + */ +void CLOCK_SetRtc1hzClkDiv(uint32_t divided_by_value) +{ + if (divided_by_value == 0U) /*!< halt */ + { + PMC->RTCOSC32K |= (1U << PMC_RTCOSC32K_CLK1HZDIVHALT_SHIFT); + } + else + { + PMC->RTCOSC32K |= + (((divided_by_value - 31744U) << PMC_RTCOSC32K_CLK1HZDIV_SHIFT) | PMC_RTCOSC32K_CLK1HZDIV_MASK); + } +} + +/* Set FRO Clocking */ +/** + * brief Initialize the Core clock to given frequency (12, 48 or 96 MHz). + * Turns on FRO and uses default CCO, if freq is 12000000, then high speed output is off, else high speed output is + * enabled. + * param iFreq : Desired frequency (must be one of #CLK_FRO_12MHZ or #CLK_FRO_48MHZ or #CLK_FRO_96MHZ) + * return returns success or fail status. + */ +status_t CLOCK_SetupFROClocking(uint32_t iFreq) +{ + if ((iFreq != 12000000U) && (iFreq != 48000000U) && (iFreq != 96000000U)) + { + return kStatus_Fail; + } + /* Enable Analog Control module */ + SYSCON->PRESETCTRLCLR[2] = (1U << SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_SHIFT); + SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_ANALOG_CTRL_MASK; + /* Power up the FRO192M */ + POWER_DisablePD(kPDRUNCFG_PD_FRO192M); + + if (iFreq == 96000000U) + { + ANACTRL->FRO192M_CTRL |= ANACTRL_FRO192M_CTRL_ENA_96MHZCLK(1); + } + else if (iFreq == 48000000U) + { + ANACTRL->FRO192M_CTRL |= ANACTRL_FRO192M_CTRL_ENA_48MHZCLK(1); + } + else + { + ANACTRL->FRO192M_CTRL |= ANACTRL_FRO192M_CTRL_ENA_12MHZCLK(1); + } + return 0U; +} + +/* Set the FLASH wait states for the passed frequency */ +/** + * brief Set the flash wait states for the input freuqency. + * param iFreq : Input frequency + * return Nothing + */ +void CLOCK_SetFLASHAccessCyclesForFreq(uint32_t iFreq) +{ + uint32_t num_wait_states; /* Flash Controller & FMC internal number of Wait States (minus 1) */ + + if (iFreq <= 11000000) + { + /* [0 - 11 MHz] */ + num_wait_states = 0; + } + else if (iFreq <= 22000000) + { + /* [11 MHz - 22 MHz] */ + num_wait_states = 1; + } + else if (iFreq <= 33000000) + { + /* [22 MHz - 33 MHz] */ + num_wait_states = 2; + } + else if (iFreq <= 44000000) + { + /* [33 MHz - 44 MHz] */ + num_wait_states = 3; + } + else if (iFreq <= 55000000) + { + /* [44 MHz - 55 MHz] */ + num_wait_states = 4; + } + else if (iFreq <= 66000000) + { + /* [55 MHz - 662 MHz] */ + num_wait_states = 5; + } + else if (iFreq <= 77000000) + { + /* [66 MHz - 77 MHz] */ + num_wait_states = 6; + } + else if (iFreq <= 88000000) + { + /* [77 MHz - 88 MHz] */ + num_wait_states = 7; + } + else if (iFreq <= 100000000) + { + /* [88 MHz - 100 MHz] */ + num_wait_states = 8; + } + else if (iFreq <= 115000000) + { + /* [100 MHz - 115 MHz] */ + num_wait_states = 9; + } + else if (iFreq <= 130000000) + { + /* [115 MHz - 130 MHz] */ + num_wait_states = 10; + } + else if (iFreq <= 150000000) + { + /* [130 MHz - 150 MHz] */ + num_wait_states = 11; + } + else + { + /* Above 150 MHz */ + num_wait_states = 12; + } + + FLASH->INT_CLR_STATUS = 0x1F; /* Clear all status flags */ + + FLASH->DATAW[0] = (FLASH->DATAW[0] & 0xFFFFFFF0) | ( num_wait_states & (SYSCON_FMCCR_FLASHTIM_MASK >> SYSCON_FMCCR_FLASHTIM_SHIFT)); + + FLASH->CMD = 0x2; /* CMD_SET_READ_MODE */ + + /* Wait until the cmd is completed (without error) */ + while ( !(FLASH->INT_STATUS & FLASH_INT_STATUS_DONE_MASK) ); + + /* Adjust FMC waiting time cycles (num_wait_states) */ + SYSCON->FMCCR = (SYSCON->FMCCR & ~SYSCON_FMCCR_FLASHTIM_MASK) | ((num_wait_states << SYSCON_FMCCR_FLASHTIM_SHIFT) & SYSCON_FMCCR_FLASHTIM_MASK); +} + +/* Set EXT OSC Clk */ +/** + * brief Initialize the external osc clock to given frequency. + * param iFreq : Desired frequency (must be equal to exact rate in Hz) + * return returns success or fail status. + */ +status_t CLOCK_SetupExtClocking(uint32_t iFreq) +{ + if (iFreq >= 32000000U) + { + return kStatus_Fail; + } + /* Turn on power for crystal 32 MHz */ + POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); + POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); + /* Enable clock_in clock for clock module. */ + SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; + + s_Ext_Clk_Freq = iFreq; + return 0U; +} + +/* Set I2S MCLK Clk */ +/** + * brief Initialize the I2S MCLK clock to given frequency. + * param iFreq : Desired frequency (must be equal to exact rate in Hz) + * return returns success or fail status. + */ +status_t CLOCK_SetupI2SMClkClocking(uint32_t iFreq) +{ + s_I2S_Mclk_Freq = iFreq; + return 0U; +} + +/* Get CLOCK OUT Clk */ +/*! brief Return Frequency of ClockOut + * return Frequency of ClockOut + */ +uint32_t CLOCK_GetClockOutClkFreq(void) +{ + uint32_t freq = 0U; + + switch (SYSCON->CLKOUTSEL) + { + case 0U: + freq = CLOCK_GetCoreSysClkFreq(); + break; + + case 1U: + freq = CLOCK_GetPll0OutFreq(); + break; + + case 2U: + freq = CLOCK_GetExtClkFreq(); + break; + + case 3U: + freq = CLOCK_GetFroHfFreq(); + break; + + case 4U: + freq = CLOCK_GetFro1MFreq(); + break; + + case 5U: + freq = CLOCK_GetPll1OutFreq(); + break; + + case 6U: + freq = CLOCK_GetOsc32KFreq(); + break; + + case 7U: + freq = 0U; + break; + + default: + break; + } + return freq / ((SYSCON->CLKOUTDIV & 0xffU) + 1U); +} + +/* Get ADC Clk */ +/*! brief Return Frequency of Adc Clock + * return Frequency of Adc. + */ +uint32_t CLOCK_GetAdcClkFreq(void) +{ + uint32_t freq = 0U; + + switch (SYSCON->ADCCLKSEL) + { + case 0U: + freq = CLOCK_GetCoreSysClkFreq(); + break; + case 1U: + freq = CLOCK_GetPll0OutFreq(); + break; + case 2U: + freq = CLOCK_GetFroHfFreq(); + break; + case 7U: + freq = 0U; + break; + + default: + break; + } + + return freq / ((SYSCON->ADCCLKDIV & SYSCON_ADCCLKDIV_DIV_MASK) + 1U); +} + +/* Get USB0 Clk */ +/*! brief Return Frequency of Usb0 Clock + * return Frequency of Usb0 Clock. + */ +uint32_t CLOCK_GetUsb0ClkFreq(void) +{ + uint32_t freq = 0U; + + switch (SYSCON->USB0CLKSEL) + { + case 0U: + freq = CLOCK_GetCoreSysClkFreq(); + break; + case 1U: + freq = CLOCK_GetPll0OutFreq(); + break; + case 3U: + freq = CLOCK_GetFroHfFreq(); + break; + case 5U: + freq = CLOCK_GetPll1OutFreq(); + break; + case 7U: + freq = 0U; + break; + + default: + break; + } + + return freq / ((SYSCON->USB0CLKDIV & 0xffU) + 1U); +} + +/* Get USB1 Clk */ +/*! brief Return Frequency of Usb1 Clock + * return Frequency of Usb1 Clock. + */ +uint32_t CLOCK_GetUsb1ClkFreq(void) +{ + return (ANACTRL->XO32M_CTRL & ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK) ? s_Ext_Clk_Freq : 0U; +} + +/* Get MCLK Clk */ +/*! brief Return Frequency of MClk Clock + * return Frequency of MClk Clock. + */ +uint32_t CLOCK_GetMclkClkFreq(void) +{ + uint32_t freq = 0U; + + switch (SYSCON->MCLKCLKSEL) + { + case 0U: + freq = CLOCK_GetFroHfFreq(); + break; + case 1U: + freq = CLOCK_GetPll0OutFreq(); + break; + case 7U: + freq = 0U; + break; + + default: + break; + } + + return freq / ((SYSCON->MCLKDIV & 0xffU) + 1U); +} + +/* Get SCTIMER Clk */ +/*! brief Return Frequency of SCTimer Clock + * return Frequency of SCTimer Clock. + */ +uint32_t CLOCK_GetSctClkFreq(void) +{ + uint32_t freq = 0U; + + switch (SYSCON->SCTCLKSEL) + { + case 0U: + freq = CLOCK_GetCoreSysClkFreq(); + break; + case 1U: + freq = CLOCK_GetPll0OutFreq(); + break; + case 2U: + freq = CLOCK_GetExtClkFreq(); + break; + case 3U: + freq = CLOCK_GetFroHfFreq(); + break; + case 5U: + freq = CLOCK_GetI2SMClkFreq(); + break; + case 7U: + freq = 0U; + break; + + default: + break; + } + + return freq / ((SYSCON->SCTCLKDIV & 0xffU) + 1U); +} + +/* Get SDIO Clk */ +/*! brief Return Frequency of SDIO Clock + * return Frequency of SDIO Clock. + */ +uint32_t CLOCK_GetSdioClkFreq(void) +{ + uint32_t freq = 0U; + + switch (SYSCON->SDIOCLKSEL) + { + case 0U: + freq = CLOCK_GetCoreSysClkFreq(); + break; + case 1U: + freq = CLOCK_GetPll0OutFreq(); + break; + case 3U: + freq = CLOCK_GetFroHfFreq(); + break; + case 5U: + freq = CLOCK_GetPll1OutFreq(); + break; + case 7U: + freq = 0U; + break; + default: + break; + } + + return freq / ((SYSCON->SDIOCLKDIV & 0xffU) + 1U); +} + +/* Get FRO 12M Clk */ +/*! brief Return Frequency of FRO 12MHz + * return Frequency of FRO 12MHz + */ +uint32_t CLOCK_GetFro12MFreq(void) +{ + return (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_FRO192M_MASK) ? + 0 : + (ANACTRL->FRO192M_CTRL & ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK) ? 12000000U : 0U; +} + +/* Get FRO 1M Clk */ +/*! brief Return Frequency of FRO 1MHz + * return Frequency of FRO 1MHz + */ +uint32_t CLOCK_GetFro1MFreq(void) +{ + return (SYSCON->CLOCK_CTRL & SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK) ? 1000000U : 0U; +} + +/* Get EXT OSC Clk */ +/*! brief Return Frequency of External Clock + * return Frequency of External Clock. If no external clock is used returns 0. + */ +uint32_t CLOCK_GetExtClkFreq(void) +{ + return (ANACTRL->XO32M_CTRL & ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK) ? s_Ext_Clk_Freq : 0U; +} + +/* Get WATCH DOG Clk */ +/*! brief Return Frequency of Watchdog + * return Frequency of Watchdog + */ +uint32_t CLOCK_GetWdtClkFreq(void) +{ + return CLOCK_GetFro1MFreq() / ((SYSCON->WDTCLKDIV & SYSCON_WDTCLKDIV_DIV_MASK) + 1U); +} + +/* Get HF FRO Clk */ +/*! brief Return Frequency of High-Freq output of FRO + * return Frequency of High-Freq output of FRO + */ +uint32_t CLOCK_GetFroHfFreq(void) +{ + return (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_FRO192M_MASK) ? + 0 : + (ANACTRL->FRO192M_CTRL & ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK) ? 96000000U : 0U; +} + +/* Get SYSTEM PLL Clk */ +/*! brief Return Frequency of PLL + * return Frequency of PLL + */ +uint32_t CLOCK_GetPll0OutFreq(void) +{ + return s_Pll0_Freq; +} + +/* Get USB PLL Clk */ +/*! brief Return Frequency of USB PLL + * return Frequency of PLL + */ +uint32_t CLOCK_GetPll1OutFreq(void) +{ + return s_Pll1_Freq; +} + +/* Get RTC OSC Clk */ +/*! brief Return Frequency of 32kHz osc + * return Frequency of 32kHz osc + */ +uint32_t CLOCK_GetOsc32KFreq(void) +{ + return ((!(PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_FRO32K_MASK)) && (!(PMC->RTCOSC32K & PMC_RTCOSC32K_SEL_MASK))) ? + CLK_RTC_32K_CLK : + ((!(PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_XTAL32K_MASK)) && (PMC->RTCOSC32K & PMC_RTCOSC32K_SEL_MASK)) ? + CLK_RTC_32K_CLK : + 0U; +} + +/* Get MAIN Clk */ +/*! brief Return Frequency of Core System + * return Frequency of Core System + */ +uint32_t CLOCK_GetCoreSysClkFreq(void) +{ + uint32_t freq = 0U; + + switch (SYSCON->MAINCLKSELB) + { + case 0U: + if (SYSCON->MAINCLKSELA == 0U) + { + freq = CLOCK_GetFro12MFreq(); + } + else if (SYSCON->MAINCLKSELA == 1U) + { + freq = CLOCK_GetExtClkFreq(); + } + else if (SYSCON->MAINCLKSELA == 2U) + { + freq = CLOCK_GetFro1MFreq(); + } + else if (SYSCON->MAINCLKSELA == 3U) + { + freq = CLOCK_GetFroHfFreq(); + } + else + { + } + break; + case 1U: + freq = CLOCK_GetPll0OutFreq(); + break; + case 2U: + freq = CLOCK_GetPll1OutFreq(); + break; + + case 3U: + freq = CLOCK_GetOsc32KFreq(); + break; + + default: + break; + } + + return freq; +} + +/* Get I2S MCLK Clk */ +/*! brief Return Frequency of I2S MCLK Clock + * return Frequency of I2S MCLK Clock + */ +uint32_t CLOCK_GetI2SMClkFreq(void) +{ + return s_I2S_Mclk_Freq; +} + +/* Get FLEXCOMM input clock */ +/*! brief Return Frequency of flexcomm input clock + * param id : flexcomm instance id + * return Frequency value + */ +uint32_t CLOCK_GetFlexCommInputClock(uint32_t id) +{ + uint32_t freq = 0U; + + switch (SYSCON->FCCLKSELX[id]) + { + case 0U: + freq = CLOCK_GetCoreSysClkFreq(); + break; + case 1U: + freq = CLOCK_GetPll0OutFreq() / ((SYSCON->PLL0CLKDIV & 0xffU) + 1U); + break; + case 2U: + freq = CLOCK_GetFro12MFreq(); + break; + case 3U: + freq = CLOCK_GetFroHfFreq() / ((SYSCON->FROHFDIV & 0xffU) + 1U); + break; + case 4U: + freq = CLOCK_GetFro1MFreq(); + break; + case 5U: + freq = CLOCK_GetI2SMClkFreq(); + break; + case 6U: + freq = CLOCK_GetOsc32KFreq(); + break; + case 7U: + freq = 0U; + break; + + default: + break; + } + + return freq; +} + +/* Get FLEXCOMM Clk */ +uint32_t CLOCK_GetFlexCommClkFreq(uint32_t id) +{ + uint32_t freq = 0U; + + freq = CLOCK_GetFlexCommInputClock(id); + return freq / (1 + (SYSCON->FLEXFRGXCTRL[id] & SYSCON_FLEXFRG0CTRL_MULT_MASK) / + ((SYSCON->FLEXFRGXCTRL[id] & SYSCON_FLEXFRG0CTRL_DIV_MASK) + 1U)); +} + +/* Get HS_LPSI Clk */ +uint32_t CLOCK_GetHsLspiClkFreq(void) +{ + uint32_t freq = 0U; + + switch (SYSCON->HSLSPICLKSEL) + { + case 0U: + freq = CLOCK_GetCoreSysClkFreq(); + break; + case 1U: + freq = CLOCK_GetPll0OutFreq() / ((SYSCON->PLL0CLKDIV & 0xffU) + 1U); + break; + case 2U: + freq = CLOCK_GetFro12MFreq(); + break; + case 3U: + freq = CLOCK_GetFroHfFreq() / ((SYSCON->FROHFDIV & 0xffU) + 1U); + break; + case 4U: + freq = CLOCK_GetFro1MFreq(); + break; + case 6U: + freq = CLOCK_GetOsc32KFreq(); + break; + case 7U: + freq = 0U; + break; + + default: + break; + } + + return freq; +} + +/* Get CTimer Clk */ +/*! brief Return Frequency of CTimer functional Clock + * return Frequency of CTimer functional Clock + */ +uint32_t CLOCK_GetCTimerClkFreq(uint32_t id) +{ + uint32_t freq = 0U; + + switch (SYSCON->CTIMERCLKSELX[id]) + { + case 0U: + freq = CLOCK_GetCoreSysClkFreq(); + break; + case 1U: + freq = CLOCK_GetPll0OutFreq(); + break; + case 3U: + freq = CLOCK_GetFroHfFreq(); + break; + case 4U: + freq = CLOCK_GetFro1MFreq(); + break; + case 5U: + freq = CLOCK_GetI2SMClkFreq(); + break; + case 6U: + freq = CLOCK_GetOsc32KFreq(); + break; + case 7U: + freq = 0U; + break; + + default: + break; + } + + return freq; +} + +/* Get Systick Clk */ +/*! brief Return Frequency of SystickClock + * return Frequency of Systick Clock + */ +uint32_t CLOCK_GetSystickClkFreq(uint32_t id) +{ + volatile uint32_t *pSystickClkDiv; + pSystickClkDiv = &(SYSCON->SYSTICKCLKDIV0); + uint32_t freq = 0U; + + switch (SYSCON->SYSTICKCLKSELX[id]) + { + case 0U: + freq = CLOCK_GetCoreSysClkFreq() / ((pSystickClkDiv[id] & 0xffU) + 1U); + break; + case 1U: + freq = CLOCK_GetFro1MFreq(); + break; + case 2U: + freq = CLOCK_GetOsc32KFreq(); + break; + case 7U: + freq = 0U; + break; + + default: + break; + } + + return freq; +} + +/* Set FlexComm Clock */ +/** + * brief Set the flexcomm output frequency. + * param id : flexcomm instance id + * freq : output frequency + * return 0 : the frequency range is out of range. + * 1 : switch successfully. + */ +uint32_t CLOCK_SetFlexCommClock(uint32_t id, uint32_t freq) +{ + uint32_t input = CLOCK_GetFlexCommClkFreq(id); + uint32_t mul; + + if ((freq > 48000000) || (freq > input) || (input / freq >= 2)) + { + /* FRG output frequency should be less than equal to 48MHz */ + return 0; + } + else + { + mul = ((uint64_t)(input - freq) * 256) / ((uint64_t)freq); + SYSCON->FLEXFRGXCTRL[id] = (mul << 8U) | 0xFFU; + return 1; + } +} + +/* Get IP Clk */ +/*! brief Return Frequency of selected clock + * return Frequency of selected clock + */ +uint32_t CLOCK_GetFreq(clock_name_t clockName) +{ + uint32_t freq; + switch (clockName) + { + case kCLOCK_CoreSysClk: + freq = CLOCK_GetCoreSysClkFreq(); + break; + case kCLOCK_BusClk: + freq = CLOCK_GetCoreSysClkFreq() / ((SYSCON->AHBCLKDIV & 0xffU) + 1U); + break; + case kCLOCK_ClockOut: + freq = CLOCK_GetClockOutClkFreq(); + break; + case kCLOCK_Adc: + freq = CLOCK_GetAdcClkFreq(); + break; + case kCLOCK_Usb0: + freq = CLOCK_GetUsb0ClkFreq(); + break; + case kCLOCK_Usb1: + freq = CLOCK_GetUsb1ClkFreq(); + break; + case kCLOCK_Pll1Out: + freq = CLOCK_GetPll1OutFreq(); + break; + case kCLOCK_Mclk: + freq = CLOCK_GetMclkClkFreq(); + break; + case kCLOCK_FroHf: + freq = CLOCK_GetFroHfFreq(); + break; + case kCLOCK_Fro12M: + freq = CLOCK_GetFro12MFreq(); + break; + case kCLOCK_ExtClk: + freq = CLOCK_GetExtClkFreq(); + break; + case kCLOCK_Pll0Out: + freq = CLOCK_GetPll0OutFreq(); + break; + case kCLOCK_WdtClk: + freq = CLOCK_GetWdtClkFreq(); + break; + case kCLOCK_Sct: + freq = CLOCK_GetSctClkFreq(); + break; + case kCLOCK_SDio: + freq = CLOCK_GetSdioClkFreq(); + break; + case kCLOCK_FlexI2S: + freq = CLOCK_GetI2SMClkFreq(); + break; + case kCLOCK_Flexcomm0: + freq = CLOCK_GetFlexCommClkFreq(0U); + break; + case kCLOCK_Flexcomm1: + freq = CLOCK_GetFlexCommClkFreq(1U); + break; + case kCLOCK_Flexcomm2: + freq = CLOCK_GetFlexCommClkFreq(2U); + break; + case kCLOCK_Flexcomm3: + freq = CLOCK_GetFlexCommClkFreq(3U); + break; + case kCLOCK_Flexcomm4: + freq = CLOCK_GetFlexCommClkFreq(4U); + break; + case kCLOCK_Flexcomm5: + freq = CLOCK_GetFlexCommClkFreq(5U); + break; + case kCLOCK_Flexcomm6: + freq = CLOCK_GetFlexCommClkFreq(6U); + break; + case kCLOCK_Flexcomm7: + freq = CLOCK_GetFlexCommClkFreq(7U); + break; + case kCLOCK_HsLspi: + freq = CLOCK_GetHsLspiClkFreq(); + break; + case kCLOCK_CTimer0: + freq = CLOCK_GetCTimerClkFreq(0U); + break; + case kCLOCK_CTimer1: + freq = CLOCK_GetCTimerClkFreq(1U); + break; + case kCLOCK_CTimer2: + freq = CLOCK_GetCTimerClkFreq(2U); + break; + case kCLOCK_CTimer3: + freq = CLOCK_GetCTimerClkFreq(3U); + break; + case kCLOCK_CTimer4: + freq = CLOCK_GetCTimerClkFreq(4U); + break; + case kCLOCK_Systick0: + freq = CLOCK_GetSystickClkFreq(0U); + break; + case kCLOCK_Systick1: + freq = CLOCK_GetSystickClkFreq(1U); + break; + default: + freq = 0U; + break; + } + return freq; +} + +/* Find SELP, SELI, and SELR values for raw M value, max M = MVALMAX */ +static void pllFindSel(uint32_t M, uint32_t *pSelP, uint32_t *pSelI, uint32_t *pSelR) +{ + uint32_t seli, selp; + /* bandwidth: compute selP from Multiplier */ + if (SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) + { + selp = (M >> 2U) + 1U; + if (selp >= 31U) + { + selp = 31U; + } + *pSelP = selp; + + if (M >= 32768) + { + seli = 1; + } + else if (M >= 16384) + { + seli = 2; + } + else if (M >= 4096) + { + seli = 4; + } + else if (M >= 1002) + { + seli = 8; + } + else if (M >= 120) + { + seli = 4 * ((1024 / (M / 2 + 9)) + 1); + } + else + { + seli = 4 * (M / 8 + 1); + } + + if (seli >= 63) + { + seli = 63; + } + *pSelI = seli; + + *pSelR = 0U; + } + else + { + *pSelP = 3U; + *pSelI = 4U; + *pSelR = 4U; + } +} + +/* Get predivider (N) from PLL0 NDEC setting */ +static uint32_t findPll0PreDiv(void) +{ + uint32_t preDiv = 1; + + /* Direct input is not used? */ + if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPREDIV_MASK) == 0) + { + preDiv = SYSCON->PLL0NDEC & SYSCON_PLL0NDEC_NDIV_MASK; + if (preDiv == 0) + { + preDiv = 1; + } + } + return preDiv; +} + +/* Get predivider (N) from PLL1 NDEC setting */ +static uint32_t findPll1PreDiv(void) +{ + uint32_t preDiv = 1; + + /* Direct input is not used? */ + if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPREDIV_MASK) == 0) + { + preDiv = SYSCON->PLL1NDEC & SYSCON_PLL1NDEC_NDIV_MASK; + if (preDiv == 0) + { + preDiv = 1; + } + } + return preDiv; +} + +/* Get postdivider (P) from PLL0 PDEC setting */ +static uint32_t findPll0PostDiv(void) +{ + uint32_t postDiv = 1; + + if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK) == 0) + { + if (SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK) + { + postDiv = SYSCON->PLL0PDEC & SYSCON_PLL0PDEC_PDIV_MASK; + } + else + { + postDiv = 2 * (SYSCON->PLL0PDEC & SYSCON_PLL0PDEC_PDIV_MASK); + } + if (postDiv == 0) + { + postDiv = 2; + } + } + return postDiv; +} + +/* Get multiplier (M) from PLL0 SSCG and SEL_EXT settings */ +static float findPll0MMult(void) +{ + float mMult = 1; + float mMult_fract; + uint32_t mMult_int; + + if (SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_SEL_EXT_MASK) + { + mMult = (SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) >> SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT; + } + else + { + mMult_int = + ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MD_MBS_MASK) << 7U) | ((SYSCON->PLL0SSCG0) >> PLL0_SSCG_MD_INT_P); + mMult_fract = ((float)((SYSCON->PLL0SSCG0) & PLL0_SSCG_MD_FRACT_M) / (1 << PLL0_SSCG_MD_INT_P)); + mMult = (float)mMult_int + mMult_fract; + } + if (mMult == 0) + { + mMult = 1; + } + return mMult; +} + +/* Find greatest common divisor between m and n */ +static uint32_t FindGreatestCommonDivisor(uint32_t m, uint32_t n) +{ + uint32_t tmp; + + while (n != 0U) + { + tmp = n; + n = m % n; + m = tmp; + } + + return m; +} + +/* + * Set PLL0 output based on desired output rate. + * In this function, the it calculates the PLL0 setting for output frequency from input clock + * frequency. The calculation would cost a few time. So it is not recommaned to use it frequently. + * the "pllctrl", "pllndec", "pllpdec", "pllmdec" would updated in this function. + */ +static pll_error_t CLOCK_GetPll0ConfigInternal(uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup, bool useSS) +{ + uint32_t nDivOutHz, fccoHz; + uint32_t pllPreDivider, pllMultiplier, pllPostDivider; + uint32_t pllDirectInput, pllDirectOutput; + uint32_t pllSelP, pllSelI, pllSelR, uplimoff; + + /* Baseline parameters (no input or output dividers) */ + pllPreDivider = 1U; /* 1 implies pre-divider will be disabled */ + pllPostDivider = 1U; /* 1 implies post-divider will be disabled */ + pllDirectOutput = 1U; + + /* Verify output rate parameter */ + if (foutHz > PLL_MAX_CCO_FREQ_MHZ) + { + /* Maximum PLL output with post divider=1 cannot go above this frequency */ + return kStatus_PLL_OutputTooHigh; + } + if (foutHz < (PLL_MIN_CCO_FREQ_MHZ / (PVALMAX << 1U))) + { + /* Minmum PLL output with maximum post divider cannot go below this frequency */ + return kStatus_PLL_OutputTooLow; + } + + /* If using SS mode, input clock needs to be between 3MHz and 20MHz */ + if (useSS) + { + /* Verify input rate parameter */ + if (finHz < PLL_MIN_IN_SSMODE) + { + /* Input clock into the PLL cannot be lower than this */ + return kStatus_PLL_InputTooLow; + } + /* PLL input in SS mode must be under 20MHz */ + if (finHz > (PLL_MAX_IN_SSMODE * NVALMAX)) + { + return kStatus_PLL_InputTooHigh; + } + } + else + { + /* Verify input rate parameter */ + if (finHz < PLL_LOWER_IN_LIMIT) + { + /* Input clock into the PLL cannot be lower than this */ + return kStatus_PLL_InputTooLow; + } + if (finHz > PLL_HIGHER_IN_LIMIT) + { + /* Input clock into the PLL cannot be higher than this */ + return kStatus_PLL_InputTooHigh; + } + } + + /* Find the optimal CCO frequency for the output and input that + will keep it inside the PLL CCO range. This may require + tweaking the post-divider for the PLL. */ + fccoHz = foutHz; + while (fccoHz < PLL_MIN_CCO_FREQ_MHZ) + { + /* CCO output is less than minimum CCO range, so the CCO output + needs to be bumped up and the post-divider is used to bring + the PLL output back down. */ + pllPostDivider++; + if (pllPostDivider > PVALMAX) + { + return kStatus_PLL_OutsideIntLimit; + } + + /* Target CCO goes up, PLL output goes down */ + /* divide-by-2 divider in the post-divider is always work*/ + fccoHz = foutHz * (pllPostDivider * 2U); + pllDirectOutput = 0U; + } + + /* Determine if a pre-divider is needed to get the best frequency */ + if ((finHz > PLL_LOWER_IN_LIMIT) && (fccoHz >= finHz) && (useSS == false)) + { + uint32_t a = FindGreatestCommonDivisor(fccoHz, finHz); + + if (a > PLL_LOWER_IN_LIMIT) + { + a = finHz / a; + if ((a != 0U) && (a < PLL_MAX_N_DIV)) + { + pllPreDivider = a; + } + } + } + + /* Bypass pre-divider hardware if pre-divider is 1 */ + if (pllPreDivider > 1U) + { + pllDirectInput = 0U; + } + else + { + pllDirectInput = 1U; + } + + /* Determine PLL multipler */ + nDivOutHz = (finHz / pllPreDivider); + pllMultiplier = (fccoHz / nDivOutHz); + + /* Find optimal values for filter */ + if (useSS == false) + { + /* Will bumping up M by 1 get us closer to the desired CCO frequency? */ + if ((nDivOutHz * ((pllMultiplier * 2U) + 1U)) < (fccoHz * 2U)) + { + pllMultiplier++; + } + + /* Setup filtering */ + pllFindSel(pllMultiplier, &pllSelP, &pllSelI, &pllSelR); + uplimoff = 0U; + + /* Get encoded value for M (mult) and use manual filter, disable SS mode */ + pSetup->pllsscg[1] = (PLL_SSCG1_MDEC_VAL_SET(pllMultiplier)) | (1U << SYSCON_PLL0SSCG1_SEL_EXT_SHIFT); + } + else + { + uint64_t fc; + + /* Filtering will be handled by SSC */ + pllSelR = pllSelI = pllSelP = 0U; + uplimoff = 1U; + + /* The PLL multiplier will get very close and slightly under the + desired target frequency. A small fractional component can be + added to fine tune the frequency upwards to the target. */ + fc = ((uint64_t)(fccoHz % nDivOutHz) << 25U) / nDivOutHz; + + /* Set multiplier */ + pSetup->pllsscg[0] = (uint32_t)(PLL0_SSCG_MD_INT_SET(pllMultiplier) | PLL0_SSCG_MD_FRACT_SET((uint32_t)fc)); + pSetup->pllsscg[1] = PLL0_SSCG_MD_INT_SET(pllMultiplier) >> 32U; + } + + /* Get encoded values for N (prediv) and P (postdiv) */ + pSetup->pllndec = PLL_NDEC_VAL_SET(pllPreDivider); + pSetup->pllpdec = PLL_PDEC_VAL_SET(pllPostDivider); + + /* PLL control */ + pSetup->pllctrl = (pllSelR << SYSCON_PLL0CTRL_SELR_SHIFT) | /* Filter coefficient */ + (pllSelI << SYSCON_PLL0CTRL_SELI_SHIFT) | /* Filter coefficient */ + (pllSelP << SYSCON_PLL0CTRL_SELP_SHIFT) | /* Filter coefficient */ + (0 << SYSCON_PLL0CTRL_BYPASSPLL_SHIFT) | /* PLL bypass mode disabled */ + (uplimoff << SYSCON_PLL0CTRL_LIMUPOFF_SHIFT) | /* SS/fractional mode disabled */ + (pllDirectInput << SYSCON_PLL0CTRL_BYPASSPREDIV_SHIFT) | /* Bypass pre-divider? */ + (pllDirectOutput << SYSCON_PLL0CTRL_BYPASSPOSTDIV_SHIFT) | /* Bypass post-divider? */ + (1 << SYSCON_PLL0CTRL_CLKEN_SHIFT); /* Ensure the PLL clock output */ + + return kStatus_PLL_Success; +} + +#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) +/* Alloct the static buffer for cache. */ +static pll_setup_t s_PllSetupCacheStruct[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT]; +static uint32_t s_FinHzCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {0}; +static uint32_t s_FoutHzCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {0}; +static bool s_UseSSCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {false}; +static uint32_t s_PllSetupCacheIdx = 0U; +#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */ + +/* + * Calculate the PLL setting values from input clock freq to output freq. + */ +static pll_error_t CLOCK_GetPll0Config(uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup, bool useSS) +{ + pll_error_t retErr; +#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) + uint32_t i; + + for (i = 0U; i < CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT; i++) + { + if ((finHz == s_FinHzCache[i]) && (foutHz == s_FoutHzCache[i]) && (useSS == s_UseSSCache[i])) + { + /* Hit the target in cache buffer. */ + pSetup->pllctrl = s_PllSetupCacheStruct[i].pllctrl; + pSetup->pllndec = s_PllSetupCacheStruct[i].pllndec; + pSetup->pllpdec = s_PllSetupCacheStruct[i].pllpdec; + pSetup->pllsscg[0] = s_PllSetupCacheStruct[i].pllsscg[0]; + pSetup->pllsscg[1] = s_PllSetupCacheStruct[i].pllsscg[1]; + retErr = kStatus_PLL_Success; + break; + } + } + + if (i < CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) + { + return retErr; + } +#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */ + + retErr = CLOCK_GetPll0ConfigInternal(finHz, foutHz, pSetup, useSS); + +#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) + /* Cache the most recent calulation result into buffer. */ + s_FinHzCache[s_PllSetupCacheIdx] = finHz; + s_FoutHzCache[s_PllSetupCacheIdx] = foutHz; + s_UseSSCache[s_PllSetupCacheIdx] = useSS; + + s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllctrl = pSetup->pllctrl; + s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllndec = pSetup->pllndec; + s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllpdec = pSetup->pllpdec; + s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllsscg[0] = pSetup->pllsscg[0]; + s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllsscg[1] = pSetup->pllsscg[1]; + /* Update the index for next available buffer. */ + s_PllSetupCacheIdx = (s_PllSetupCacheIdx + 1U) % CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT; +#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */ + + return retErr; +} + +/* Update local PLL rate variable */ +static void CLOCK_GetPLL0OutFromSetupUpdate(pll_setup_t *pSetup) +{ + s_Pll0_Freq = CLOCK_GetPLL0OutFromSetup(pSetup); +} + +/* Return System PLL input clock rate */ +/*! brief Return PLL0 input clock rate + * return PLL0 input clock rate + */ +uint32_t CLOCK_GetPLL0InClockRate(void) +{ + uint32_t clkRate = 0U; + + switch ((SYSCON->PLL0CLKSEL & SYSCON_PLL0CLKSEL_SEL_MASK)) + { + case 0x00U: + clkRate = CLK_FRO_12MHZ; + break; + + case 0x01U: + clkRate = CLOCK_GetExtClkFreq(); + break; + + case 0x02U: + clkRate = CLOCK_GetFro1MFreq(); + break; + + case 0x03U: + clkRate = CLOCK_GetOsc32KFreq(); + break; + + default: + clkRate = 0U; + break; + } + + return clkRate; +} + +/* Return PLL1 input clock rate */ +uint32_t CLOCK_GetPLL1InClockRate(void) +{ + uint32_t clkRate = 0U; + + switch ((SYSCON->PLL1CLKSEL & SYSCON_PLL1CLKSEL_SEL_MASK)) + { + case 0x00U: + clkRate = CLK_FRO_12MHZ; + break; + + case 0x01U: + clkRate = CLOCK_GetExtClkFreq(); + break; + + case 0x02U: + clkRate = CLOCK_GetFro1MFreq(); + break; + + case 0x03U: + clkRate = CLOCK_GetOsc32KFreq(); + break; + + default: + clkRate = 0U; + break; + } + + return clkRate; +} + +/* Return PLL0 output clock rate from setup structure */ +/*! brief Return PLL0 output clock rate from setup structure + * param pSetup : Pointer to a PLL setup structure + * return PLL0 output clock rate the setup structure will generate + */ +uint32_t CLOCK_GetPLL0OutFromSetup(pll_setup_t *pSetup) +{ + uint32_t clkRate = 0; + uint32_t prediv, postdiv; + float workRate = 0; + + /* Get the input clock frequency of PLL. */ + clkRate = CLOCK_GetPLL0InClockRate(); + + if (((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPLL_MASK) == 0) && (SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_CLKEN_MASK) && + ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_MASK) == 0) && + ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK) == 0)) + { + prediv = findPll0PreDiv(); + postdiv = findPll0PostDiv(); + /* Adjust input clock */ + clkRate = clkRate / prediv; + /* MDEC used for rate */ + workRate = (float)clkRate * (float)findPll0MMult(); + clkRate = (uint32_t)(workRate / ((float)postdiv)); + } + + return (uint32_t)workRate; +} + +/* Set the current PLL0 Rate */ +/*! brief Store the current PLL rate + * param rate: Current rate of the PLL + * return Nothing + **/ +void CLOCK_SetStoredPLL0ClockRate(uint32_t rate) +{ + s_Pll0_Freq = rate; +} + +/* Return PLL0 output clock rate */ +/*! brief Return PLL0 output clock rate + * param recompute : Forces a PLL rate recomputation if true + * return PLL0 output clock rate + * note The PLL rate is cached in the driver in a variable as + * the rate computation function can take some time to perform. It + * is recommended to use 'false' with the 'recompute' parameter. + */ +uint32_t CLOCK_GetPLL0OutClockRate(bool recompute) +{ + pll_setup_t Setup; + uint32_t rate; + + if ((recompute) || (s_Pll0_Freq == 0U)) + { + Setup.pllctrl = SYSCON->PLL0CTRL; + Setup.pllndec = SYSCON->PLL0NDEC; + Setup.pllpdec = SYSCON->PLL0PDEC; + Setup.pllsscg[0] = SYSCON->PLL0SSCG0; + Setup.pllsscg[1] = SYSCON->PLL0SSCG1; + + CLOCK_GetPLL0OutFromSetupUpdate(&Setup); + } + + rate = s_Pll0_Freq; + + return rate; +} + +/* Set PLL0 output based on the passed PLL setup data */ +/*! brief Set PLL output based on the passed PLL setup data + * param pControl : Pointer to populated PLL control structure to generate setup with + * param pSetup : Pointer to PLL setup structure to be filled + * return PLL_ERROR_SUCCESS on success, or PLL setup error code + * note Actual frequency for setup may vary from the desired frequency based on the + * accuracy of input clocks, rounding, non-fractional PLL mode, etc. + */ +pll_error_t CLOCK_SetupPLL0Data(pll_config_t *pControl, pll_setup_t *pSetup) +{ + uint32_t inRate; + bool useSS = (bool)((pControl->flags & PLL_CONFIGFLAG_FORCENOFRACT) == 0U); + + pll_error_t pllError; + + /* Determine input rate for the PLL */ + if ((pControl->flags & PLL_CONFIGFLAG_USEINRATE) != 0U) + { + inRate = pControl->inputRate; + } + else + { + inRate = CLOCK_GetPLL0InClockRate(); + } + + /* PLL flag options */ + pllError = CLOCK_GetPll0Config(inRate, pControl->desiredRate, pSetup, useSS); + if ((useSS) && (pllError == kStatus_PLL_Success)) + { + /* If using SS mode, then some tweaks are made to the generated setup */ + pSetup->pllsscg[1] |= (uint32_t)pControl->ss_mf | (uint32_t)pControl->ss_mr | (uint32_t)pControl->ss_mc; + if (pControl->mfDither) + { + pSetup->pllsscg[1] |= (1U << SYSCON_PLL0SSCG1_DITHER_SHIFT); + } + } + + return pllError; +} + +/* Set PLL0 output from PLL setup structure */ +/*! brief Set PLL output from PLL setup structure (precise frequency) + * param pSetup : Pointer to populated PLL setup structure + * param flagcfg : Flag configuration for PLL config structure + * return PLL_ERROR_SUCCESS on success, or PLL setup error code + * note This function will power off the PLL, setup the PLL with the + * new setup data, and then optionally powerup the PLL, wait for PLL lock, + * and adjust system voltages to the new PLL rate. The function will not + * alter any source clocks (ie, main systen clock) that may use the PLL, + * so these should be setup prior to and after exiting the function. + */ +pll_error_t CLOCK_SetupPLL0Prec(pll_setup_t *pSetup, uint32_t flagcfg) +{ + uint32_t inRate, clkRate, prediv; + + /* Power off PLL during setup changes */ + POWER_EnablePD(kPDRUNCFG_PD_PLL0); + POWER_EnablePD(kPDRUNCFG_PD_PLL0_SSCG); + + pSetup->flags = flagcfg; + + /* Write PLL setup data */ + SYSCON->PLL0CTRL = pSetup->pllctrl; + SYSCON->PLL0NDEC = pSetup->pllndec; + SYSCON->PLL0NDEC = pSetup->pllndec | (1U << SYSCON_PLL0NDEC_NREQ_SHIFT); /* latch */ + SYSCON->PLL0PDEC = pSetup->pllpdec; + SYSCON->PLL0PDEC = pSetup->pllpdec | (1U << SYSCON_PLL0PDEC_PREQ_SHIFT); /* latch */ + SYSCON->PLL0SSCG0 = pSetup->pllsscg[0]; + SYSCON->PLL0SSCG1 = pSetup->pllsscg[1]; + SYSCON->PLL0SSCG1 = + pSetup->pllsscg[1] | (1U << SYSCON_PLL0SSCG1_MREQ_SHIFT) | (1U << SYSCON_PLL0SSCG1_MD_REQ_SHIFT); /* latch */ + + POWER_DisablePD(kPDRUNCFG_PD_PLL0); + POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG); + + if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0U) + { + inRate = CLOCK_GetPLL0InClockRate(); + prediv = findPll0PreDiv(); + /* Adjust input clock */ + clkRate = inRate / prediv; + /* The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. */ + if ((clkRate >= 100000) && (clkRate <= 20000000)) + { + while (CLOCK_IsPLL0Locked() == false) + { + } + } + } + + /* Update current programmed PLL rate var */ + CLOCK_GetPLL0OutFromSetupUpdate(pSetup); + + /* System voltage adjustment, occurs prior to setting main system clock */ + if ((pSetup->flags & PLL_SETUPFLAG_ADGVOLT) != 0U) + { + POWER_SetVoltageForFreq(s_Pll0_Freq); + } + + return kStatus_PLL_Success; +} + +/* Setup PLL Frequency from pre-calculated value */ +/** + * brief Set PLL0 output from PLL setup structure (precise frequency) + * param pSetup : Pointer to populated PLL setup structure + * return kStatus_PLL_Success on success, or PLL setup error code + * note This function will power off the PLL, setup the PLL with the + * new setup data, and then optionally powerup the PLL, wait for PLL lock, + * and adjust system voltages to the new PLL rate. The function will not + * alter any source clocks (ie, main systen clock) that may use the PLL, + * so these should be setup prior to and after exiting the function. + */ +pll_error_t CLOCK_SetPLL0Freq(const pll_setup_t *pSetup) +{ + uint32_t inRate, clkRate, prediv; + /* Power off PLL during setup changes */ + POWER_EnablePD(kPDRUNCFG_PD_PLL0); + POWER_EnablePD(kPDRUNCFG_PD_PLL0_SSCG); + + /* Write PLL setup data */ + SYSCON->PLL0CTRL = pSetup->pllctrl; + SYSCON->PLL0NDEC = pSetup->pllndec; + SYSCON->PLL0NDEC = pSetup->pllndec | (1U << SYSCON_PLL0NDEC_NREQ_SHIFT); /* latch */ + SYSCON->PLL0PDEC = pSetup->pllpdec; + SYSCON->PLL0PDEC = pSetup->pllpdec | (1U << SYSCON_PLL0PDEC_PREQ_SHIFT); /* latch */ + SYSCON->PLL0SSCG0 = pSetup->pllsscg[0]; + SYSCON->PLL0SSCG1 = pSetup->pllsscg[1]; + SYSCON->PLL0SSCG1 = + pSetup->pllsscg[1] | (1U << SYSCON_PLL0SSCG1_MD_REQ_SHIFT) | (1U << SYSCON_PLL0SSCG1_MREQ_SHIFT); /* latch */ + + POWER_DisablePD(kPDRUNCFG_PD_PLL0); + POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG); + + if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0U) + { + inRate = CLOCK_GetPLL0InClockRate(); + prediv = findPll0PreDiv(); + /* Adjust input clock */ + clkRate = inRate / prediv; + /* The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. */ + if ((clkRate >= 100000) && (clkRate <= 20000000)) + { + while (CLOCK_IsPLL0Locked() == false) + { + } + } + } + + /* Update current programmed PLL rate var */ + s_Pll0_Freq = pSetup->pllRate; + + return kStatus_PLL_Success; +} + +/* Setup PLL1 Frequency from pre-calculated value */ +/** + * brief Set PLL1 output from PLL setup structure (precise frequency) + * param pSetup : Pointer to populated PLL setup structure + * return kStatus_PLL_Success on success, or PLL setup error code + * note This function will power off the PLL, setup the PLL with the + * new setup data, and then optionally powerup the PLL, wait for PLL lock, + * and adjust system voltages to the new PLL rate. The function will not + * alter any source clocks (ie, main systen clock) that may use the PLL, + * so these should be setup prior to and after exiting the function. + */ +pll_error_t CLOCK_SetPLL1Freq(const pll_setup_t *pSetup) +{ + uint32_t inRate, clkRate, prediv; + /* Power off PLL during setup changes */ + POWER_EnablePD(kPDRUNCFG_PD_PLL1); + + /* Write PLL setup data */ + SYSCON->PLL1CTRL = pSetup->pllctrl; + SYSCON->PLL1NDEC = pSetup->pllndec; + SYSCON->PLL1NDEC = pSetup->pllndec | (1U << SYSCON_PLL1NDEC_NREQ_SHIFT); /* latch */ + SYSCON->PLL1PDEC = pSetup->pllpdec; + SYSCON->PLL1PDEC = pSetup->pllpdec | (1U << SYSCON_PLL1PDEC_PREQ_SHIFT); /* latch */ + SYSCON->PLL1MDEC = pSetup->pllmdec; + SYSCON->PLL1MDEC = pSetup->pllmdec | (1U << SYSCON_PLL1MDEC_MREQ_SHIFT); /* latch */ + + POWER_DisablePD(kPDRUNCFG_PD_PLL1); + + if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0U) + { + inRate = CLOCK_GetPLL1InClockRate(); + prediv = findPll1PreDiv(); + /* Adjust input clock */ + clkRate = inRate / prediv; + /* The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. */ + if ((clkRate >= 100000) && (clkRate <= 20000000)) + { + while (CLOCK_IsPLL1Locked() == false) + { + } + } + } + + /* Update current programmed PLL rate var */ + s_Pll0_Freq = pSetup->pllRate; + + return kStatus_PLL_Success; +} + +/* Set PLL0 clock based on the input frequency and multiplier */ +/*! brief Set PLL0 output based on the multiplier and input frequency + * param multiply_by : multiplier + * param input_freq : Clock input frequency of the PLL + * return Nothing + * note Unlike the Chip_Clock_SetupSystemPLLPrec() function, this + * function does not disable or enable PLL power, wait for PLL lock, + * or adjust system voltages. These must be done in the application. + * The function will not alter any source clocks (ie, main systen clock) + * that may use the PLL, so these should be setup prior to and after + * exiting the function. + */ +void CLOCK_SetupPLL0Mult(uint32_t multiply_by, uint32_t input_freq) +{ + uint32_t cco_freq = input_freq * multiply_by; + uint32_t pdec = 1U; + uint32_t selr; + uint32_t seli; + uint32_t selp; + uint32_t mdec, ndec; + + while (cco_freq < 275000000U) + { + multiply_by <<= 1U; /* double value in each iteration */ + pdec <<= 1U; /* correspondingly double pdec to cancel effect of double msel */ + cco_freq = input_freq * multiply_by; + } + + selr = 0U; + + if (multiply_by >= 32768) + { + seli = 1; + } + else if (multiply_by >= 16384) + { + seli = 2; + } + else if (multiply_by >= 4096) + { + seli = 4; + } + else if (multiply_by >= 1002) + { + seli = 8; + } + else if (multiply_by >= 120) + { + seli = 4 * ((1024 / (multiply_by / 2 + 9)) + 1); + } + else + { + seli = 4 * (multiply_by / 8 + 1); + } + + if (seli >= 63U) + { + seli = 63U; + } + selp = (multiply_by >> 2U) + 1U; + { + selp = 31U; + } + + if (pdec > 1U) + { + pdec = pdec / 2U; /* Account for minus 1 encoding */ + /* Translate P value */ + } + + mdec = PLL_SSCG1_MDEC_VAL_SET(multiply_by); + ndec = 0x1U; /* pre divide by 1 (hardcoded) */ + + SYSCON->PLL0CTRL = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_BYPASSPOSTDIV(0) | + SYSCON_PLL0CTRL_BYPASSPOSTDIV2(0) | (selr << SYSCON_PLL0CTRL_SELR_SHIFT) | + (seli << SYSCON_PLL0CTRL_SELI_SHIFT) | (selp << SYSCON_PLL0CTRL_SELP_SHIFT); + SYSCON->PLL0PDEC = pdec | (1U << SYSCON_PLL0PDEC_PREQ_SHIFT); /* set Pdec value and assert preq */ + SYSCON->PLL0NDEC = ndec | (1U << SYSCON_PLL0NDEC_NREQ_SHIFT); /* set Pdec value and assert preq */ + SYSCON->PLL0SSCG1 = + mdec | (1U << SYSCON_PLL0SSCG1_MREQ_SHIFT); /* select non sscg MDEC value, assert mreq and select mdec value */ +} + +/* Enable USB DEVICE FULL SPEED clock */ +/*! brief Enable USB Device FS clock. + * param src : clock source + * param freq: clock frequency + * Enable USB Device Full Speed clock. + */ +bool CLOCK_EnableUsbfs0DeviceClock(clock_usbfs_src_t src, uint32_t freq) +{ + bool ret = true; + + CLOCK_DisableClock(kCLOCK_Usbd0); + + if (kCLOCK_UsbfsSrcFro == src) + { + switch (freq) + { + case 96000000U: + CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */ + break; + + default: + ret = false; + break; + } + /* Turn ON FRO HF */ + POWER_DisablePD(kPDRUNCFG_PD_FRO192M); + /* Enable FRO 96MHz output */ + ANACTRL->FRO192M_CTRL = ANACTRL->FRO192M_CTRL | ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK; + /* Select FRO 96 or 48 MHz */ + CLOCK_AttachClk(kFRO_HF_to_USB0_CLK); + } + else + { + /*Set the USB PLL as the Usb0 CLK*/ + POWER_DisablePD(kPDRUNCFG_PD_PLL1); + POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /*!< Ensure XTAL32K is on */ + POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /*!< Ensure XTAL32K is on */ + SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /*!< Ensure CLK_IN is on */ + ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; + + CLOCK_AttachClk(kEXT_CLK_to_PLL1); /*!< Switch PLL0 clock source selector to XTAL16M */ + + const pll_setup_t pll1Setup = { + .pllctrl = SYSCON_PLL1CTRL_CLKEN_MASK | SYSCON_PLL1CTRL_SELI(16U) | SYSCON_PLL1CTRL_SELP(7U), + .pllndec = SYSCON_PLL1NDEC_NDIV(1U), + .pllpdec = SYSCON_PLL1PDEC_PDIV(4U), + .pllmdec = SYSCON_PLL1MDEC_MDIV(24U), + .pllRate = 48000000U, + .flags = PLL_SETUPFLAG_WAITLOCK, + }; + + CLOCK_SetPLL1Freq(&pll1Setup); /*!< Configure PLL1 to the desired values */ + + CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); + CLOCK_AttachClk(kPLL1_to_USB0_CLK); + uint32_t delay = 100000; + while (delay--) + { + __asm("nop"); + } + } + CLOCK_EnableClock(kCLOCK_Usbd0); + CLOCK_EnableClock(kCLOCK_UsbRam1); + + return ret; +} + +/* Enable USB HOST FULL SPEED clock */ +/*! brief Enable USB HOST FS clock. + * param src : clock source + * param freq: clock frequency + * Enable USB HOST Full Speed clock. + */ +bool CLOCK_EnableUsbfs0HostClock(clock_usbfs_src_t src, uint32_t freq) +{ + bool ret = true; + + CLOCK_DisableClock(kCLOCK_Usbhmr0); + CLOCK_DisableClock(kCLOCK_Usbhsl0); + + if (kCLOCK_UsbfsSrcFro == src) + { + switch (freq) + { + case 96000000U: + CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */ + break; + + default: + ret = false; + break; + } + /* Turn ON FRO HF */ + POWER_DisablePD(kPDRUNCFG_PD_FRO192M); + /* Enable FRO 96MHz output */ + ANACTRL->FRO192M_CTRL = ANACTRL->FRO192M_CTRL | ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK; + /* Select FRO 96 MHz */ + CLOCK_AttachClk(kFRO_HF_to_USB0_CLK); + } + else + { + /*Set the USB PLL as the Usb0 CLK*/ + POWER_DisablePD(kPDRUNCFG_PD_PLL1); + POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /*!< Ensure XTAL32K is on */ + POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /*!< Ensure XTAL32K is on */ + SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /*!< Ensure CLK_IN is on */ + ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; + + CLOCK_AttachClk(kEXT_CLK_to_PLL1); /*!< Switch PLL0 clock source selector to XTAL16M */ + + const pll_setup_t pll1Setup = { + .pllctrl = SYSCON_PLL1CTRL_CLKEN_MASK | SYSCON_PLL1CTRL_SELI(16U) | SYSCON_PLL1CTRL_SELP(7U), + .pllndec = SYSCON_PLL1NDEC_NDIV(1U), + .pllpdec = SYSCON_PLL1PDEC_PDIV(4U), + .pllmdec = SYSCON_PLL1MDEC_MDIV(24U), + .pllRate = 48000000U, + .flags = PLL_SETUPFLAG_WAITLOCK, + }; + + CLOCK_SetPLL1Freq(&pll1Setup); /*!< Configure PLL1 to the desired values */ + + CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); + CLOCK_AttachClk(kPLL1_to_USB0_CLK); + uint32_t delay = 100000; + while (delay--) + { + __asm("nop"); + } + } + CLOCK_EnableClock(kCLOCK_Usbhmr0); + CLOCK_EnableClock(kCLOCK_Usbhsl0); + CLOCK_EnableClock(kCLOCK_UsbRam1); + + return ret; +} + +/* Enable USB PHY clock */ +bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq) +{ + volatile uint32_t i; + + POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); + POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); + POWER_DisablePD(kPDRUNCFG_PD_FRO32K); /*!< Ensure FRO32k is on */ + POWER_DisablePD(kPDRUNCFG_PD_XTAL32K); /*!< Ensure xtal32k is on */ + POWER_DisablePD(kPDRUNCFG_PD_USB1_PHY); /*!< Ensure xtal32k is on */ + POWER_DisablePD(kPDRUNCFG_PD_LDOUSBHS); /*!< Ensure xtal32k is on */ + + /* wait to make sure PHY power is fully up */ + i = 100000; + while (i--) + { + __asm("nop"); + } + + SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_ANALOG_CTRL(1); + SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_USB1_PHY(1); + + USBPHY->CTRL_CLR = USBPHY_CTRL_SFTRST_MASK; + USBPHY->PLL_SIC = (USBPHY->PLL_SIC & ~USBPHY_PLL_SIC_PLL_DIV_SEL(0x7)) | USBPHY_PLL_SIC_PLL_DIV_SEL(0x06); + USBPHY->PLL_SIC_SET = USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK; + USBPHY->PLL_SIC_CLR = USBPHY_PLL_SIC_SET_PLL_BYPASS_MASK; + USBPHY->PLL_SIC_SET = USBPHY_PLL_SIC_SET_PLL_POWER_MASK; + USBPHY->PLL_SIC_SET = USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK; + USBPHY->PLL_SIC_SET = + USBPHY_PLL_SIC_SET_MISC2_CONTROL0_MASK; /* enables auto power down of PHY PLL during suspend */ + + USBPHY->CTRL_CLR = USBPHY_CTRL_CLR_CLKGATE_MASK; + USBPHY->PWD_SET = 0x0; + + return true; +} + +/* Enable USB DEVICE HIGH SPEED clock */ +bool CLOCK_EnableUsbhs0DeviceClock(clock_usbhs_src_t src, uint32_t freq) +{ + SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_USB1_RAM(1); + SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_USB1_DEV(1); + + /* 16 MHz will be driven by the tb on the xtal1 pin of XTAL32M */ + SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clock_in clock for clock module. */ + ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT(1); + return true; +} + +/* Enable USB HOST HIGH SPEED clock */ +bool CLOCK_EnableUsbhs0HostClock(clock_usbhs_src_t src, uint32_t freq) +{ + SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_USB1_RAM(1); + SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_USB1_HOST(1); + + /* 16 MHz will be driven by the tb on the xtal1 pin of XTAL32M */ + SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clock_in clock for clock module. */ + ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT(1); + + return true; +} + +/*! + * brief Use DWT to delay at least for some time. + * Please note that, this API will calculate the microsecond period with the maximum devices + * supported CPU frequency, so this API will only delay for at least the given microseconds, if precise + * delay count was needed, please implement a new timer count to achieve this function. + * + * param delay_us Delay time in unit of microsecond. + */ +__attribute__((weak)) void SDK_DelayAtLeastUs(uint32_t delay_us) +{ + assert(0U != delay_us); + uint64_t count = 0U; + uint32_t period = SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY / 1000000; + + /* Make sure the DWT trace fucntion is enabled. */ + if (CoreDebug_DEMCR_TRCENA_Msk != (CoreDebug_DEMCR_TRCENA_Msk & CoreDebug->DEMCR)) + { + CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; + } + + /* CYCCNT not supported on this device. */ + assert(DWT_CTRL_NOCYCCNT_Msk != (DWT->CTRL & DWT_CTRL_NOCYCCNT_Msk)); + + /* If CYCCENT has already been enabled, read directly, otherwise, need enable it. */ + if (DWT_CTRL_CYCCNTENA_Msk != (DWT_CTRL_CYCCNTENA_Msk & DWT->CTRL)) + { + DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk; + } + + /* Calculate the count ticks. */ + count = DWT->CYCCNT; + count += (uint64_t)period * delay_us; + + if (count > 0xFFFFFFFFUL) + { + count -= 0xFFFFFFFFUL; + /* wait for cyccnt overflow. */ + while (count < DWT->CYCCNT) + { + } + } + + /* Wait for cyccnt reach count value. */ + while (count > DWT->CYCCNT) + { + } +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_clock.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_clock.h new file mode 100644 index 000000000..95799bcab --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_clock.h @@ -0,0 +1,1300 @@ +/* + * Copyright 2017 - 2019 , NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_CLOCK_H_ +#define _FSL_CLOCK_H_ + +#include "fsl_common.h" + +/*! @addtogroup clock */ +/*! @{ */ + +/*! @file */ + +/******************************************************************************* + * Definitions + *****************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief CLOCK driver version 2.1.0. */ +#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) +/*@}*/ + +/*! @brief Configure whether driver controls clock + * + * When set to 0, peripheral drivers will enable clock in initialize function + * and disable clock in de-initialize function. When set to 1, peripheral + * driver will not control the clock, application could control the clock out of + * the driver. + * + * @note All drivers share this feature switcher. If it is set to 1, application + * should handle clock enable and disable for all drivers. + */ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)) +#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0 +#endif + +/*! + * @brief User-defined the size of cache for CLOCK_PllGetConfig() function. + * + * Once define this MACRO to be non-zero value, CLOCK_PllGetConfig() function + * would cache the recent calulation and accelerate the execution to get the + * right settings. + */ +#ifndef CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT +#define CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT 2U +#endif + +/* Definition for delay API in clock driver, users can redefine it to the real application. */ +#ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY +#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (100000000UL) +#endif + +/*! @brief Clock ip name array for ROM. */ +#define ROM_CLOCKS \ + { \ + kCLOCK_Rom \ + } +/*! @brief Clock ip name array for SRAM. */ +#define SRAM_CLOCKS \ + { \ + kCLOCK_Sram1, kCLOCK_Sram2, kCLOCK_Sram3, kCLOCK_Sram4 \ + } +/*! @brief Clock ip name array for FLASH. */ +#define FLASH_CLOCKS \ + { \ + kCLOCK_Flash \ + } +/*! @brief Clock ip name array for FMC. */ +#define FMC_CLOCKS \ + { \ + kCLOCK_Fmc \ + } +/*! @brief Clock ip name array for INPUTMUX. */ +#define INPUTMUX_CLOCKS \ + { \ + kCLOCK_InputMux0, kCLOCK_InputMux1 \ + } +/*! @brief Clock ip name array for IOCON. */ +#define IOCON_CLOCKS \ + { \ + kCLOCK_Iocon \ + } +/*! @brief Clock ip name array for GPIO. */ +#define GPIO_CLOCKS \ + { \ + kCLOCK_Gpio0, kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3, kCLOCK_Gpio4, kCLOCK_Gpio5 \ + } +/*! @brief Clock ip name array for PINT. */ +#define PINT_CLOCKS \ + { \ + kCLOCK_Pint \ + } +/*! @brief Clock ip name array for GINT. */ +#define GINT_CLOCKS \ + { \ + kCLOCK_Gint, kCLOCK_Gint \ + } +/*! @brief Clock ip name array for DMA. */ +#define DMA_CLOCKS \ + { \ + kCLOCK_Dma0, kCLOCK_Dma1 \ + } +/*! @brief Clock ip name array for CRC. */ +#define CRC_CLOCKS \ + { \ + kCLOCK_Crc \ + } +/*! @brief Clock ip name array for WWDT. */ +#define WWDT_CLOCKS \ + { \ + kCLOCK_Wwdt \ + } +/*! @brief Clock ip name array for RTC. */ +#define RTC_CLOCKS \ + { \ + kCLOCK_Rtc \ + } +/*! @brief Clock ip name array for Mailbox. */ +#define MAILBOX_CLOCKS \ + { \ + kCLOCK_Mailbox \ + } +/*! @brief Clock ip name array for LPADC. */ +#define LPADC_CLOCKS \ + { \ + kCLOCK_Adc0 \ + } +/*! @brief Clock ip name array for MRT. */ +#define MRT_CLOCKS \ + { \ + kCLOCK_Mrt \ + } +/*! @brief Clock ip name array for OSTIMER. */ +#define OSTIMER_CLOCKS \ + { \ + kCLOCK_OsTimer0 \ + } +/*! @brief Clock ip name array for SCT0. */ +#define SCT_CLOCKS \ + { \ + kCLOCK_Sct0 \ + } +/*! @brief Clock ip name array for SCTIPU. */ +#define SCTIPU_CLOCKS \ + { \ + kCLOCK_Sctipu \ + } +/*! @brief Clock ip name array for UTICK. */ +#define UTICK_CLOCKS \ + { \ + kCLOCK_Utick0 \ + } +/*! @brief Clock ip name array for FLEXCOMM. */ +#define FLEXCOMM_CLOCKS \ + { \ + kCLOCK_FlexComm0, kCLOCK_FlexComm1, kCLOCK_FlexComm2, kCLOCK_FlexComm3, kCLOCK_FlexComm4, kCLOCK_FlexComm5, \ + kCLOCK_FlexComm6, kCLOCK_FlexComm7, kCLOCK_Hs_Lspi \ + } +/*! @brief Clock ip name array for LPUART. */ +#define LPUART_CLOCKS \ + { \ + kCLOCK_MinUart0, kCLOCK_MinUart1, kCLOCK_MinUart2, kCLOCK_MinUart3, kCLOCK_MinUart4, kCLOCK_MinUart5, \ + kCLOCK_MinUart6, kCLOCK_MinUart7 \ + } + +/*! @brief Clock ip name array for BI2C. */ +#define BI2C_CLOCKS \ + { \ + kCLOCK_BI2c0, kCLOCK_BI2c1, kCLOCK_BI2c2, kCLOCK_BI2c3, kCLOCK_BI2c4, kCLOCK_BI2c5, kCLOCK_BI2c6, kCLOCK_BI2c7 \ + } +/*! @brief Clock ip name array for LSPI. */ +#define LPSPI_CLOCKS \ + { \ + kCLOCK_LSpi0, kCLOCK_LSpi1, kCLOCK_LSpi2, kCLOCK_LSpi3, kCLOCK_LSpi4, kCLOCK_LSpi5, kCLOCK_LSpi6, kCLOCK_LSpi7 \ + } +/*! @brief Clock ip name array for FLEXI2S. */ +#define FLEXI2S_CLOCKS \ + { \ + kCLOCK_FlexI2s0, kCLOCK_FlexI2s1, kCLOCK_FlexI2s2, kCLOCK_FlexI2s3, kCLOCK_FlexI2s4, kCLOCK_FlexI2s5, \ + kCLOCK_FlexI2s6, kCLOCK_FlexI2s7 \ + } +/*! @brief Clock ip name array for USBTYPC. */ +#define USBTYPC_CLOCKS \ + { \ + kCLOCK_UsbTypc \ + } +/*! @brief Clock ip name array for CTIMER. */ +#define CTIMER_CLOCKS \ + { \ + kCLOCK_Timer0, kCLOCK_Timer1, kCLOCK_Timer2, kCLOCK_Timer3, kCLOCK_Timer4 \ + } +/*! @brief Clock ip name array for PVT */ +#define PVT_CLOCKS \ + { \ + kCLOCK_Pvt \ + } +/*! @brief Clock ip name array for EZHA */ +#define EZHA_CLOCKS \ + { \ + kCLOCK_Ezha \ + } +/*! @brief Clock ip name array for EZHB */ +#define EZHB_CLOCKS \ + { \ + kCLOCK_Ezhb \ + } +/*! @brief Clock ip name array for COMP */ +#define COMP_CLOCKS \ + { \ + kCLOCK_Comp \ + } +/*! @brief Clock ip name array for SDIO. */ +#define SDIO_CLOCKS \ + { \ + kCLOCK_Sdio \ + } +/*! @brief Clock ip name array for USB1CLK. */ +#define USB1CLK_CLOCKS \ + { \ + kCLOCK_Usb1Clk \ + } +/*! @brief Clock ip name array for FREQME. */ +#define FREQME_CLOCKS \ + { \ + kCLOCK_Freqme \ + } +/*! @brief Clock ip name array for USBRAM. */ +#define USBRAM_CLOCKS \ + { \ + kCLOCK_UsbRam1 \ + } +/*! @brief Clock ip name array for OTP. */ +#define OTP_CLOCKS \ + { \ + kCLOCK_Otp \ + } +/*! @brief Clock ip name array for RNG. */ +#define RNG_CLOCKS \ + { \ + kCLOCK_Rng \ + } +/*! @brief Clock ip name array for USBHMR0. */ +#define USBHMR0_CLOCKS \ + { \ + kCLOCK_Usbhmr0 \ + } +/*! @brief Clock ip name array for USBHSL0. */ +#define USBHSL0_CLOCKS \ + { \ + kCLOCK_Usbhsl0 \ + } +/*! @brief Clock ip name array for HashCrypt. */ +#define HASHCRYPT_CLOCKS \ + { \ + kCLOCK_HashCrypt \ + } +/*! @brief Clock ip name array for PowerQuad. */ +#define POWERQUAD_CLOCKS \ + { \ + kCLOCK_PowerQuad \ + } +/*! @brief Clock ip name array for PLULUT. */ +#define PLULUT_CLOCKS \ + { \ + kCLOCK_PluLut \ + } +/*! @brief Clock ip name array for PUF. */ +#define PUF_CLOCKS \ + { \ + kCLOCK_Puf \ + } +/*! @brief Clock ip name array for CASPER. */ +#define CASPER_CLOCKS \ + { \ + kCLOCK_Casper \ + } +/*! @brief Clock ip name array for ANALOGCTRL. */ +#define ANALOGCTRL_CLOCKS \ + { \ + kCLOCK_AnalogCtrl \ + } +/*! @brief Clock ip name array for HS_LSPI. */ +#define HS_LSPI_CLOCKS \ + { \ + kCLOCK_Hs_Lspi \ + } +/*! @brief Clock ip name array for GPIO_SEC. */ +#define GPIO_SEC_CLOCKS \ + { \ + kCLOCK_Gpio_Sec \ + } +/*! @brief Clock ip name array for GPIO_SEC_INT. */ +#define GPIO_SEC_INT_CLOCKS \ + { \ + kCLOCK_Gpio_Sec_Int \ + } +/*! @brief Clock ip name array for USBD. */ +#define USBD_CLOCKS \ + { \ + kCLOCK_Usbd0, kCLOCK_Usbh1, kCLOCK_Usbd1 \ + } +/*! @brief Clock ip name array for USBH. */ +#define USBH_CLOCKS \ + { \ + kCLOCK_Usbh1 \ + } +#define PLU_CLOCKS \ + { \ + kCLOCK_PluLut \ + } +#define SYSCTL_CLOCKS \ + { \ + kCLOCK_Sysctl \ + } +/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */ +/*------------------------------------------------------------------------------ + clock_ip_name_t definition: +------------------------------------------------------------------------------*/ + +#define CLK_GATE_REG_OFFSET_SHIFT 8U +#define CLK_GATE_REG_OFFSET_MASK 0xFFFFFF00U +#define CLK_GATE_BIT_SHIFT_SHIFT 0U +#define CLK_GATE_BIT_SHIFT_MASK 0x000000FFU + +#define CLK_GATE_DEFINE(reg_offset, bit_shift) \ + ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \ + (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK)) + +#define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((uint32_t)(x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT) +#define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((uint32_t)(x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT) + +#define AHB_CLK_CTRL0 0 +#define AHB_CLK_CTRL1 1 +#define AHB_CLK_CTRL2 2 + +/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */ +typedef enum _clock_ip_name +{ + kCLOCK_IpInvalid = 0U, + kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 1), + kCLOCK_Sram1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 3), + kCLOCK_Sram2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 4), + kCLOCK_Sram3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 5), + kCLOCK_Sram4 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 6), + kCLOCK_Flash = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 7), + kCLOCK_Fmc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 8), + kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 11), + kCLOCK_Iocon = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 13), + kCLOCK_Gpio0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 14), + kCLOCK_Gpio1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 15), + kCLOCK_Gpio2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 16), + kCLOCK_Gpio3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 17), + kCLOCK_Pint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 18), + kCLOCK_Gint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 19), + kCLOCK_Dma0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 20), + kCLOCK_Crc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 21), + kCLOCK_Wwdt = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 22), + kCLOCK_Rtc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 23), + kCLOCK_Mailbox = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 26), + kCLOCK_Adc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 27), + kCLOCK_Mrt = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 0), + kCLOCK_OsTimer0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 1), + kCLOCK_Sct0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 2), + kCLOCK_Sctipu = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 6), + kCLOCK_Utick0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 10), + kCLOCK_FlexComm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), + kCLOCK_FlexComm1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), + kCLOCK_FlexComm2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), + kCLOCK_FlexComm3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), + kCLOCK_FlexComm4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), + kCLOCK_FlexComm5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), + kCLOCK_FlexComm6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), + kCLOCK_FlexComm7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), + kCLOCK_MinUart0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), + kCLOCK_MinUart1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), + kCLOCK_MinUart2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), + kCLOCK_MinUart3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), + kCLOCK_MinUart4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), + kCLOCK_MinUart5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), + kCLOCK_MinUart6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), + kCLOCK_MinUart7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), + kCLOCK_LSpi0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), + kCLOCK_LSpi1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), + kCLOCK_LSpi2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), + kCLOCK_LSpi3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), + kCLOCK_LSpi4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), + kCLOCK_LSpi5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), + kCLOCK_LSpi6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), + kCLOCK_LSpi7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), + kCLOCK_BI2c0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), + kCLOCK_BI2c1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), + kCLOCK_BI2c2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), + kCLOCK_BI2c3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), + kCLOCK_BI2c4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), + kCLOCK_BI2c5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), + kCLOCK_BI2c6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), + kCLOCK_BI2c7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), + kCLOCK_FlexI2s0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), + kCLOCK_FlexI2s1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), + kCLOCK_FlexI2s2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), + kCLOCK_FlexI2s3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), + kCLOCK_FlexI2s4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), + kCLOCK_FlexI2s5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), + kCLOCK_FlexI2s6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), + kCLOCK_FlexI2s7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), + kCLOCK_UsbTypc = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 20), + kCLOCK_Timer2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 22), + kCLOCK_Usbd0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 25), + kCLOCK_Timer0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 26), + kCLOCK_Timer1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 27), + kCLOCK_Pvt = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 28), + kCLOCK_Ezha = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 30), + kCLOCK_Ezhb = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 31), + kCLOCK_Dma1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 1), + kCLOCK_Comp = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 2), + kCLOCK_Sdio = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 3), + kCLOCK_Usbh1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 4), + kCLOCK_Usbd1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 5), + kCLOCK_UsbRam1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 6), + kCLOCK_Usb1Clk = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 7), + kCLOCK_Freqme = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 8), + kCLOCK_Gpio4 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 9), + kCLOCK_Gpio5 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 10), + kCLOCK_Otp = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 12), + kCLOCK_Rng = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 13), + kCLOCK_InputMux1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14), + kCLOCK_Sysctl = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15), + kCLOCK_Usbhmr0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 16), + kCLOCK_Usbhsl0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 17), + kCLOCK_HashCrypt = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 18), + kCLOCK_PowerQuad = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 19), + kCLOCK_PluLut = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 20), + kCLOCK_Timer3 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 21), + kCLOCK_Timer4 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 22), + kCLOCK_Puf = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 23), + kCLOCK_Casper = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 24), + kCLOCK_AnalogCtrl = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 27), + kCLOCK_Hs_Lspi = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 28), + kCLOCK_Gpio_Sec = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 29), + kCLOCK_Gpio_sec_Int = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 30) +} clock_ip_name_t; + +/*! @brief Peripherals clock source definition. */ +#define BUS_CLK kCLOCK_BusClk + +#define I2C0_CLK_SRC BUS_CLK + +/*! @brief Clock name used to get clock frequency. */ +typedef enum _clock_name +{ + kCLOCK_CoreSysClk, /*!< Core/system clock (aka MAIN_CLK) */ + kCLOCK_BusClk, /*!< Bus clock (AHB clock) */ + kCLOCK_ClockOut, /*!< CLOCKOUT */ + kCLOCK_FroHf, /*!< FRO48/96 */ + kCLOCK_Adc, /*!< ADC */ + kCLOCK_Usb0, /*!< USB0 */ + kCLOCK_Usb1, /*!< USB1 */ + kCLOCK_Pll1Out, /*!< PLL1 Output */ + kCLOCK_Mclk, /*!< MCLK */ + kCLOCK_Sct, /*!< SCT */ + kCLOCK_SDio, /*!< SDIO */ + kCLOCK_Fro12M, /*!< FRO12M */ + kCLOCK_ExtClk, /*!< External Clock */ + kCLOCK_Pll0Out, /*!< PLL0 Output */ + kCLOCK_WdtClk, /*!< Watchdog clock */ + kCLOCK_FlexI2S, /*!< FlexI2S clock */ + kCLOCK_Flexcomm0, /*!< Flexcomm0Clock */ + kCLOCK_Flexcomm1, /*!< Flexcomm1Clock */ + kCLOCK_Flexcomm2, /*!< Flexcomm2Clock */ + kCLOCK_Flexcomm3, /*!< Flexcomm3Clock */ + kCLOCK_Flexcomm4, /*!< Flexcomm4Clock */ + kCLOCK_Flexcomm5, /*!< Flexcomm5Clock */ + kCLOCK_Flexcomm6, /*!< Flexcomm6Clock */ + kCLOCK_Flexcomm7, /*!< Flexcomm7Clock */ + kCLOCK_HsLspi, /*!< HS LPSPI Clock */ + kCLOCK_CTimer0, /*!< CTimer0Clock */ + kCLOCK_CTimer1, /*!< CTimer1Clock */ + kCLOCK_CTimer2, /*!< CTimer2Clock */ + kCLOCK_CTimer3, /*!< CTimer3Clock */ + kCLOCK_CTimer4, /*!< CTimer4Clock */ + kCLOCK_Systick0, /*!< System Tick 0 Clock */ + kCLOCK_Systick1, /*!< System Tick 1 Clock */ + +} clock_name_t; + +/*! @brief Clock Mux Switches + * The encoding is as follows each connection identified is 32bits wide while 24bits are valuable + * starting from LSB upwards + * + * [4 bits for choice, 0 means invalid choice] [8 bits mux ID]* + * + */ + +#define CLK_ATTACH_ID(mux, sel, pos) (((mux << 0U) | ((sel + 1) & 0xFU) << 8U) << (pos * 12U)) +#define MUX_A(mux, sel) CLK_ATTACH_ID(mux, sel, 0U) +#define MUX_B(mux, sel, selector) (CLK_ATTACH_ID(mux, sel, 1U) | (selector << 24U)) + +#define GET_ID_ITEM(connection) ((connection)&0xFFFU) +#define GET_ID_NEXT_ITEM(connection) ((connection) >> 12U) +#define GET_ID_ITEM_MUX(connection) ((connection)&0xFFU) +#define GET_ID_ITEM_SEL(connection) ((((connection)&0xF00U) >> 8U) - 1U) +#define GET_ID_SELECTOR(connection) ((connection)&0xF000000U) + +#define CM_SYSTICKCLKSEL0 0 +#define CM_SYSTICKCLKSEL1 1 +#define CM_TRACECLKSEL 2 +#define CM_CTIMERCLKSEL0 3 +#define CM_CTIMERCLKSEL1 4 +#define CM_CTIMERCLKSEL2 5 +#define CM_CTIMERCLKSEL3 6 +#define CM_CTIMERCLKSEL4 7 +#define CM_MAINCLKSELA 8 +#define CM_MAINCLKSELB 9 +#define CM_CLKOUTCLKSEL 10 +#define CM_PLL0CLKSEL 12 +#define CM_PLL1CLKSEL 13 +#define CM_ADCASYNCCLKSEL 17 +#define CM_USB0CLKSEL 18 +#define CM_FXCOMCLKSEL0 20 +#define CM_FXCOMCLKSEL1 21 +#define CM_FXCOMCLKSEL2 22 +#define CM_FXCOMCLKSEL3 23 +#define CM_FXCOMCLKSEL4 24 +#define CM_FXCOMCLKSEL5 25 +#define CM_FXCOMCLKSEL6 26 +#define CM_FXCOMCLKSEL7 27 +#define CM_HSLSPICLKSEL 28 +#define CM_MCLKCLKSEL 32 +#define CM_SCTCLKSEL 36 +#define CM_SDIOCLKSEL 38 + +#define CM_RTCOSC32KCLKSEL 63 + +typedef enum _clock_attach_id +{ + + kFRO12M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 0, 0), + kEXT_CLK_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 1) | MUX_B(CM_MAINCLKSELB, 0, 0), + kFRO1M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 2) | MUX_B(CM_MAINCLKSELB, 0, 0), + kFRO_HF_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 3) | MUX_B(CM_MAINCLKSELB, 0, 0), + kPLL0_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 1, 0), + kPLL1_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 2, 0), + kOSC32K_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 3, 0), + + kMAIN_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 0), + kPLL0_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 1), + kEXT_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 2), + kFRO_HF_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 3), + kFRO1M_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 4), + kPLL1_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 5), + kOSC32K_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 6), + kNONE_to_SYS_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 7), + + kFRO12M_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 0), + kEXT_CLK_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 1), + kFRO1M_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 2), + kOSC32K_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 3), + kNONE_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 7), + + kMAIN_CLK_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 0), + kPLL0_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 1), + kFRO_HF_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 2), + kFRO1M_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 3), /* Need confirm */ + kNONE_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 7), + + kMAIN_CLK_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 0), + kPLL0_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 1), + kFRO_HF_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 3), + kPLL1_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 5), + kNONE_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 7), + + kMAIN_CLK_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 0), + kPLL0_DIV_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 1), + kFRO12M_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 2), + kFRO_HF_DIV_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 3), + kFRO1M_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 4), + kMCLK_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 5), + kOSC32K_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 6), + kNONE_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 7), + + kMAIN_CLK_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 0), + kPLL0_DIV_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 1), + kFRO12M_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 2), + kFRO_HF_DIV_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 3), + kFRO1M_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 4), + kMCLK_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 5), + kOSC32K_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 6), + kNONE_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 7), + + kMAIN_CLK_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 0), + kPLL0_DIV_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 1), + kFRO12M_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 2), + kFRO_HF_DIV_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 3), + kFRO1M_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 4), + kMCLK_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 5), + kOSC32K_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 6), + kNONE_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 7), + + kMAIN_CLK_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 0), + kPLL0_DIV_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 1), + kFRO12M_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 2), + kFRO_HF_DIV_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 3), + kFRO1M_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 4), + kMCLK_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 5), + kOSC32K_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 6), + kNONE_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 7), + + kMAIN_CLK_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 0), + kPLL0_DIV_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 1), + kFRO12M_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 2), + kFRO_HF_DIV_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 3), + kFRO1M_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 4), + kMCLK_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 5), + kOSC32K_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 6), + kNONE_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 7), + + kMAIN_CLK_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 0), + kPLL0_DIV_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 1), + kFRO12M_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 2), + kFRO_HF_DIV_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 3), + kFRO1M_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 4), + kMCLK_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 5), + kOSC32K_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 6), + kNONE_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 7), + + kMAIN_CLK_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 0), + kPLL0_DIV_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 1), + kFRO12M_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 2), + kFRO_HF_DIV_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 3), + kFRO1M_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 4), + kMCLK_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 5), + kOSC32K_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 6), + kNONE_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 7), + + kMAIN_CLK_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 0), + kPLL0_DIV_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 1), + kFRO12M_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 2), + kFRO_HF_DIV_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 3), + kFRO1M_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 4), + kMCLK_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 5), + kOSC32K_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 6), + kNONE_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 7), + + kMAIN_CLK_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 0), + kPLL0_DIV_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 1), + kFRO12M_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 2), + kFRO_HF_DIV_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 3), + kFRO1M_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 4), + kOSC32K_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 6), + kNONE_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 7), + + kFRO_HF_to_MCLK = MUX_A(CM_MCLKCLKSEL, 0), + kPLL0_to_MCLK = MUX_A(CM_MCLKCLKSEL, 1), + kFRO1M_to_MCLK = MUX_A(CM_MCLKCLKSEL, 2), /* Need confirm */ + kMAIN_CLK_to_MCLK = MUX_A(CM_MCLKCLKSEL, 3), /* Need confirm */ + kNONE_to_MCLK = MUX_A(CM_MCLKCLKSEL, 7), + + kMAIN_CLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 0), + kPLL0_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 1), + kEXT_CLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 2), + kFRO_HF_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 3), + kMCLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 5), + kNONE_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 7), + + kMAIN_CLK_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 0), + kPLL0_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 1), + kFRO_HF_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 3), + kPLL1_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 5), + kNONE_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 7), + + kFRO32K_to_OSC32K = MUX_A(CM_RTCOSC32KCLKSEL, 0), + kXTAL32K_to_OSC32K = MUX_A(CM_RTCOSC32KCLKSEL, 1), + + kTRACE_DIV_to_TRACE = MUX_A(CM_TRACECLKSEL, 0), + kFRO1M_to_TRACE = MUX_A(CM_TRACECLKSEL, 1), + kOSC32K_to_TRACE = MUX_A(CM_TRACECLKSEL, 2), + kNONE_to_TRACE = MUX_A(CM_TRACECLKSEL, 7), + + kSYSTICK_DIV0_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 0), + kFRO1M_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 1), + kOSC32K_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 2), + kNONE_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 7), + + kSYSTICK_DIV1_to_SYSTICK1 = MUX_A(CM_SYSTICKCLKSEL1, 0), + kFRO1M_to_SYSTICK1 = MUX_A(CM_SYSTICKCLKSEL1, 1), + kOSC32K_to_SYSTICK1 = MUX_A(CM_SYSTICKCLKSEL1, 2), + kNONE_to_SYSTICK1 = MUX_A(CM_SYSTICKCLKSEL1, 7), + + kFRO12M_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 0), + kEXT_CLK_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 1), + kFRO1M_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 2), + kOSC32K_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 3), + kNONE_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 7), + + kMAIN_CLK_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 0), + kPLL0_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 1), + kFRO_HF_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 3), + kFRO1M_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 4), + kMCLK_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 5), + kOSC32K_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 6), + kNONE_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 7), + + kMAIN_CLK_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 0), + kPLL0_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 1), + kFRO_HF_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 3), + kFRO1M_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 4), + kMCLK_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 5), + kOSC32K_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 6), + kNONE_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 7), + + kMAIN_CLK_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 0), + kPLL0_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 1), + kFRO_HF_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 3), + kFRO1M_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 4), + kMCLK_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 5), + kOSC32K_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 6), + kNONE_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 7), + + kMAIN_CLK_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 0), + kPLL0_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 1), + kFRO_HF_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 3), + kFRO1M_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 4), + kMCLK_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 5), + kOSC32K_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 6), + kNONE_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 7), + + kMAIN_CLK_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 0), + kPLL0_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 1), + kFRO_HF_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 3), + kFRO1M_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 4), + kMCLK_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 5), + kOSC32K_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 6), + kNONE_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 7), + kNONE_to_NONE = (int)0x80000000U, +} clock_attach_id_t; + +/* Clock dividers */ +typedef enum _clock_div_name +{ + kCLOCK_DivSystickClk0 = 0, + kCLOCK_DivSystickClk1 = 1, + kCLOCK_DivArmTrClkDiv = 2, + kCLOCK_DivFlexFrg0 = 8, + kCLOCK_DivFlexFrg1 = 9, + kCLOCK_DivFlexFrg2 = 10, + kCLOCK_DivFlexFrg3 = 11, + kCLOCK_DivFlexFrg4 = 12, + kCLOCK_DivFlexFrg5 = 13, + kCLOCK_DivFlexFrg6 = 14, + kCLOCK_DivFlexFrg7 = 15, + kCLOCK_DivAhbClk = 32, + kCLOCK_DivClkOut = 33, + kCLOCK_DivFrohfClk = 34, + kCLOCK_DivWdtClk = 35, + kCLOCK_DivAdcAsyncClk = 37, + kCLOCK_DivUsb0Clk = 38, + kCLOCK_DivMClk = 43, + kCLOCK_DivSctClk = 45, + kCLOCK_DivSdioClk = 47, + kCLOCK_DivPll0Clk = 49 +} clock_div_name_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/** + * @brief Enable the clock for specific IP. + * @param name : Clock to be enabled. + * @return Nothing + */ +static inline void CLOCK_EnableClock(clock_ip_name_t clk) +{ + uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk); + SYSCON->AHBCLKCTRLSET[index] = (1U << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); +} +/** + * @brief Disable the clock for specific IP. + * @param name : Clock to be Disabled. + * @return Nothing + */ +static inline void CLOCK_DisableClock(clock_ip_name_t clk) +{ + uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk); + SYSCON->AHBCLKCTRLCLR[index] = (1U << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); +} +/** + * @brief Initialize the Core clock to given frequency (12, 48 or 96 MHz). + * Turns on FRO and uses default CCO, if freq is 12000000, then high speed output is off, else high speed output is + * enabled. + * @param iFreq : Desired frequency (must be one of #CLK_FRO_12MHZ or #CLK_FRO_48MHZ or #CLK_FRO_96MHZ) + * @return returns success or fail status. + */ +status_t CLOCK_SetupFROClocking(uint32_t iFreq); +/** + * @brief Set the flash wait states for the input freuqency. + * @param iFreq : Input frequency + * @return Nothing + */ +void CLOCK_SetFLASHAccessCyclesForFreq(uint32_t iFreq); +/** + * @brief Initialize the external osc clock to given frequency. + * @param iFreq : Desired frequency (must be equal to exact rate in Hz) + * @return returns success or fail status. + */ +status_t CLOCK_SetupExtClocking(uint32_t iFreq); +/** + * @brief Initialize the I2S MCLK clock to given frequency. + * @param iFreq : Desired frequency (must be equal to exact rate in Hz) + * @return returns success or fail status. + */ +status_t CLOCK_SetupI2SMClkClocking(uint32_t iFreq); +/** + * @brief Configure the clock selection muxes. + * @param connection : Clock to be configured. + * @return Nothing + */ +void CLOCK_AttachClk(clock_attach_id_t connection); +/** + * @brief Get the actual clock attach id. + * This fuction uses the offset in input attach id, then it reads the actual source value in + * the register and combine the offset to obtain an actual attach id. + * @param attachId : Clock attach id to get. + * @return Clock source value. + */ +clock_attach_id_t CLOCK_GetClockAttachId(clock_attach_id_t attachId); +/** + * @brief Setup peripheral clock dividers. + * @param div_name : Clock divider name + * @param divided_by_value: Value to be divided + * @param reset : Whether to reset the divider counter. + * @return Nothing + */ +void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool reset); +/** + * @brief Setup rtc 1khz clock divider. + * @param divided_by_value: Value to be divided + * @return Nothing + */ +void CLOCK_SetRtc1khzClkDiv(uint32_t divided_by_value); +/** + * @brief Setup rtc 1hz clock divider. + * @param divided_by_value: Value to be divided + * @return Nothing + */ +void CLOCK_SetRtc1hzClkDiv(uint32_t divided_by_value); + +/** + * @brief Set the flexcomm output frequency. + * @param id : flexcomm instance id + * freq : output frequency + * @return 0 : the frequency range is out of range. + * 1 : switch successfully. + */ +uint32_t CLOCK_SetFlexCommClock(uint32_t id, uint32_t freq); + +/*! @brief Return Frequency of flexcomm input clock + * @param id : flexcomm instance id + * @return Frequency value + */ +uint32_t CLOCK_GetFlexCommInputClock(uint32_t id); + +/*! @brief Return Frequency of selected clock + * @return Frequency of selected clock + */ +uint32_t CLOCK_GetFreq(clock_name_t clockName); +/*! @brief Return Frequency of FRO 12MHz + * @return Frequency of FRO 12MHz + */ +uint32_t CLOCK_GetFro12MFreq(void); +/*! @brief Return Frequency of FRO 1MHz + * @return Frequency of FRO 1MHz + */ +uint32_t CLOCK_GetFro1MFreq(void); +/*! @brief Return Frequency of ClockOut + * @return Frequency of ClockOut + */ +uint32_t CLOCK_GetClockOutClkFreq(void); +/*! @brief Return Frequency of Adc Clock + * @return Frequency of Adc. + */ +uint32_t CLOCK_GetAdcClkFreq(void); +/*! @brief Return Frequency of Usb0 Clock + * @return Frequency of Usb0 Clock. + */ +uint32_t CLOCK_GetUsb0ClkFreq(void); +/*! @brief Return Frequency of Usb1 Clock + * @return Frequency of Usb1 Clock. + */ +uint32_t CLOCK_GetUsb1ClkFreq(void); +/*! @brief Return Frequency of MClk Clock + * @return Frequency of MClk Clock. + */ +uint32_t CLOCK_GetMclkClkFreq(void); +/*! @brief Return Frequency of SCTimer Clock + * @return Frequency of SCTimer Clock. + */ +uint32_t CLOCK_GetSctClkFreq(void); +/*! @brief Return Frequency of SDIO Clock + * @return Frequency of SDIO Clock. + */ +uint32_t CLOCK_GetSdioClkFreq(void); +/*! @brief Return Frequency of External Clock + * @return Frequency of External Clock. If no external clock is used returns 0. + */ +uint32_t CLOCK_GetExtClkFreq(void); +/*! @brief Return Frequency of Watchdog + * @return Frequency of Watchdog + */ +uint32_t CLOCK_GetWdtClkFreq(void); +/*! @brief Return Frequency of High-Freq output of FRO + * @return Frequency of High-Freq output of FRO + */ +uint32_t CLOCK_GetFroHfFreq(void); +/*! @brief Return Frequency of PLL + * @return Frequency of PLL + */ +uint32_t CLOCK_GetPll0OutFreq(void); +/*! @brief Return Frequency of USB PLL + * @return Frequency of PLL + */ +uint32_t CLOCK_GetPll1OutFreq(void); +/*! @brief Return Frequency of 32kHz osc + * @return Frequency of 32kHz osc + */ +uint32_t CLOCK_GetOsc32KFreq(void); +/*! @brief Return Frequency of Core System + * @return Frequency of Core System + */ +uint32_t CLOCK_GetCoreSysClkFreq(void); +/*! @brief Return Frequency of I2S MCLK Clock + * @return Frequency of I2S MCLK Clock + */ +uint32_t CLOCK_GetI2SMClkFreq(void); +/*! @brief Return Frequency of CTimer functional Clock + * @return Frequency of CTimer functional Clock + */ +uint32_t CLOCK_GetCTimerClkFreq(uint32_t id); +/*! @brief Return Frequency of SystickClock + * @return Frequency of Systick Clock + */ +uint32_t CLOCK_GetSystickClkFreq(uint32_t id); + +/*! @brief Return PLL0 input clock rate + * @return PLL0 input clock rate + */ +uint32_t CLOCK_GetPLL0InClockRate(void); + +/*! @brief Return PLL1 input clock rate + * @return PLL1 input clock rate + */ +uint32_t CLOCK_GetPLL1InClockRate(void); + +/*! @brief Return PLL0 output clock rate + * @param recompute : Forces a PLL rate recomputation if true + * @return PLL0 output clock rate + * @note The PLL rate is cached in the driver in a variable as + * the rate computation function can take some time to perform. It + * is recommended to use 'false' with the 'recompute' parameter. + */ +uint32_t CLOCK_GetPLL0OutClockRate(bool recompute); + +/*! @brief Return PLL1 output clock rate + * @param recompute : Forces a PLL rate recomputation if true + * @return PLL1 output clock rate + * @note The PLL rate is cached in the driver in a variable as + * the rate computation function can take some time to perform. It + * is recommended to use 'false' with the 'recompute' parameter. + */ +uint32_t CLOCK_GetPLL1OutClockRate(bool recompute); + +/*! @brief Enables and disables PLL0 bypass mode + * @brief bypass : true to bypass PLL0 (PLL0 output = PLL0 input, false to disable bypass + * @return PLL0 output clock rate + */ +__STATIC_INLINE void CLOCK_SetBypassPLL0(bool bypass) +{ + if (bypass) + { + SYSCON->PLL0CTRL |= (1UL << SYSCON_PLL0CTRL_BYPASSPLL_SHIFT); + } + else + { + SYSCON->PLL0CTRL &= ~(1UL << SYSCON_PLL0CTRL_BYPASSPLL_SHIFT); + } +} + +/*! @brief Enables and disables PLL1 bypass mode + * @brief bypass : true to bypass PLL1 (PLL1 output = PLL1 input, false to disable bypass + * @return PLL1 output clock rate + */ +__STATIC_INLINE void CLOCK_SetBypassPLL1(bool bypass) +{ + if (bypass) + { + SYSCON->PLL1CTRL |= (1UL << SYSCON_PLL1CTRL_BYPASSPLL_SHIFT); + } + else + { + SYSCON->PLL1CTRL &= ~(1UL << SYSCON_PLL1CTRL_BYPASSPLL_SHIFT); + } +} + +/*! @brief Check if PLL is locked or not + * @return true if the PLL is locked, false if not locked + */ +__STATIC_INLINE bool CLOCK_IsPLL0Locked(void) +{ + return (bool)((SYSCON->PLL0STAT & SYSCON_PLL0STAT_LOCK_MASK) != 0); +} + +/*! @brief Check if PLL1 is locked or not + * @return true if the PLL1 is locked, false if not locked + */ +__STATIC_INLINE bool CLOCK_IsPLL1Locked(void) +{ + return (bool)((SYSCON->PLL1STAT & SYSCON_PLL1STAT_LOCK_MASK) != 0); +} + +/*! @brief Store the current PLL0 rate + * @param rate: Current rate of the PLL0 + * @return Nothing + **/ +void CLOCK_SetStoredPLL0ClockRate(uint32_t rate); + +/*! @brief PLL configuration structure flags for 'flags' field + * These flags control how the PLL configuration function sets up the PLL setup structure.
+ * + * When the PLL_CONFIGFLAG_USEINRATE flag is selected, the 'InputRate' field in the + * configuration structure must be assigned with the expected PLL frequency. If the + * PLL_CONFIGFLAG_USEINRATE is not used, 'InputRate' is ignored in the configuration + * function and the driver will determine the PLL rate from the currently selected + * PLL source. This flag might be used to configure the PLL input clock more accurately + * when using the WDT oscillator or a more dyanmic CLKIN source.
+ * + * When the PLL_CONFIGFLAG_FORCENOFRACT flag is selected, the PLL hardware for the + * automatic bandwidth selection, Spread Spectrum (SS) support, and fractional M-divider + * are not used.
+ */ +#define PLL_CONFIGFLAG_USEINRATE (1 << 0) /*!< Flag to use InputRate in PLL configuration structure for setup */ +#define PLL_CONFIGFLAG_FORCENOFRACT (1 << 2) +/*!< Force non-fractional output mode, PLL output will not use the fractional, automatic bandwidth, or SS hardware */ + +/*! @brief PLL Spread Spectrum (SS) Programmable modulation frequency + * See (MF) field in the PLL0SSCG1 register in the UM. + */ +typedef enum _ss_progmodfm +{ + kSS_MF_512 = (0 << 20), /*!< Nss = 512 (fm ? 3.9 - 7.8 kHz) */ + kSS_MF_384 = (1 << 20), /*!< Nss ?= 384 (fm ? 5.2 - 10.4 kHz) */ + kSS_MF_256 = (2 << 20), /*!< Nss = 256 (fm ? 7.8 - 15.6 kHz) */ + kSS_MF_128 = (3 << 20), /*!< Nss = 128 (fm ? 15.6 - 31.3 kHz) */ + kSS_MF_64 = (4 << 20), /*!< Nss = 64 (fm ? 32.3 - 64.5 kHz) */ + kSS_MF_32 = (5 << 20), /*!< Nss = 32 (fm ? 62.5- 125 kHz) */ + kSS_MF_24 = (6 << 20), /*!< Nss ?= 24 (fm ? 83.3- 166.6 kHz) */ + kSS_MF_16 = (7 << 20) /*!< Nss = 16 (fm ? 125- 250 kHz) */ +} ss_progmodfm_t; + +/*! @brief PLL Spread Spectrum (SS) Programmable frequency modulation depth + * See (MR) field in the PLL0SSCG1 register in the UM. + */ +typedef enum _ss_progmoddp +{ + kSS_MR_K0 = (0 << 23), /*!< k = 0 (no spread spectrum) */ + kSS_MR_K1 = (1 << 23), /*!< k = 1 */ + kSS_MR_K1_5 = (2 << 23), /*!< k = 1.5 */ + kSS_MR_K2 = (3 << 23), /*!< k = 2 */ + kSS_MR_K3 = (4 << 23), /*!< k = 3 */ + kSS_MR_K4 = (5 << 23), /*!< k = 4 */ + kSS_MR_K6 = (6 << 23), /*!< k = 6 */ + kSS_MR_K8 = (7 << 23) /*!< k = 8 */ +} ss_progmoddp_t; + +/*! @brief PLL Spread Spectrum (SS) Modulation waveform control + * See (MC) field in the PLL0SSCG1 register in the UM.
+ * Compensation for low pass filtering of the PLL to get a triangular + * modulation at the output of the PLL, giving a flat frequency spectrum. + */ +typedef enum _ss_modwvctrl +{ + kSS_MC_NOC = (0 << 26), /*!< no compensation */ + kSS_MC_RECC = (2 << 26), /*!< recommended setting */ + kSS_MC_MAXC = (3 << 26), /*!< max. compensation */ +} ss_modwvctrl_t; + +/*! @brief PLL configuration structure + * + * This structure can be used to configure the settings for a PLL + * setup structure. Fill in the desired configuration for the PLL + * and call the PLL setup function to fill in a PLL setup structure. + */ +typedef struct _pll_config +{ + uint32_t desiredRate; /*!< Desired PLL rate in Hz */ + uint32_t inputRate; /*!< PLL input clock in Hz, only used if PLL_CONFIGFLAG_USEINRATE flag is set */ + uint32_t flags; /*!< PLL configuration flags, Or'ed value of PLL_CONFIGFLAG_* definitions */ + ss_progmodfm_t ss_mf; /*!< SS Programmable modulation frequency, only applicable when not using + PLL_CONFIGFLAG_FORCENOFRACT flag */ + ss_progmoddp_t ss_mr; /*!< SS Programmable frequency modulation depth, only applicable when not using + PLL_CONFIGFLAG_FORCENOFRACT flag */ + ss_modwvctrl_t + ss_mc; /*!< SS Modulation waveform control, only applicable when not using PLL_CONFIGFLAG_FORCENOFRACT flag */ + bool mfDither; /*!< false for fixed modulation frequency or true for dithering, only applicable when not using + PLL_CONFIGFLAG_FORCENOFRACT flag */ + +} pll_config_t; + +/*! @brief PLL setup structure flags for 'flags' field + * These flags control how the PLL setup function sets up the PLL + */ +#define PLL_SETUPFLAG_POWERUP (1 << 0) /*!< Setup will power on the PLL after setup */ +#define PLL_SETUPFLAG_WAITLOCK (1 << 1) /*!< Setup will wait for PLL lock, implies the PLL will be pwoered on */ +#define PLL_SETUPFLAG_ADGVOLT (1 << 2) /*!< Optimize system voltage for the new PLL rate */ +#define PLL_SETUPFLAG_USEFEEDBACKDIV2 (1 << 3) /*!< Use feedback divider by 2 in divider path */ + +/*! @brief PLL0 setup structure + * This structure can be used to pre-build a PLL setup configuration + * at run-time and quickly set the PLL to the configuration. It can be + * populated with the PLL setup function. If powering up or waiting + * for PLL lock, the PLL input clock source should be configured prior + * to PLL setup. + */ +typedef struct _pll_setup +{ + uint32_t pllctrl; /*!< PLL control register PLL0CTRL */ + uint32_t pllndec; /*!< PLL NDEC register PLL0NDEC */ + uint32_t pllpdec; /*!< PLL PDEC register PLL0PDEC */ + uint32_t pllmdec; /*!< PLL MDEC registers PLL0PDEC */ + uint32_t pllsscg[2]; /*!< PLL SSCTL registers PLL0SSCG*/ + uint32_t pllRate; /*!< Acutal PLL rate */ + uint32_t flags; /*!< PLL setup flags, Or'ed value of PLL_SETUPFLAG_* definitions */ +} pll_setup_t; + +/*! @brief PLL status definitions + */ +typedef enum _pll_error +{ + kStatus_PLL_Success = MAKE_STATUS(kStatusGroup_Generic, 0), /*!< PLL operation was successful */ + kStatus_PLL_OutputTooLow = MAKE_STATUS(kStatusGroup_Generic, 1), /*!< PLL output rate request was too low */ + kStatus_PLL_OutputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 2), /*!< PLL output rate request was too high */ + kStatus_PLL_InputTooLow = MAKE_STATUS(kStatusGroup_Generic, 3), /*!< PLL input rate is too low */ + kStatus_PLL_InputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 4), /*!< PLL input rate is too high */ + kStatus_PLL_OutsideIntLimit = MAKE_STATUS(kStatusGroup_Generic, 5), /*!< Requested output rate isn't possible */ + kStatus_PLL_CCOTooLow = MAKE_STATUS(kStatusGroup_Generic, 6), /*!< Requested CCO rate isn't possible */ + kStatus_PLL_CCOTooHigh = MAKE_STATUS(kStatusGroup_Generic, 7) /*!< Requested CCO rate isn't possible */ +} pll_error_t; + +/*! @brief USB FS clock source definition. */ +typedef enum _clock_usbfs_src +{ + kCLOCK_UsbfsSrcFro = (uint32_t)kCLOCK_FroHf, /*!< Use FRO 96 MHz. */ + kCLOCK_UsbfsSrcPll0 = (uint32_t)kCLOCK_Pll0Out, /*!< Use PLL0 output. */ + kCLOCK_UsbfsSrcMainClock = (uint32_t)kCLOCK_CoreSysClk, /*!< Use Main clock. */ + kCLOCK_UsbfsSrcPll1 = (uint32_t)kCLOCK_Pll1Out, /*!< Use PLL1 clock. */ + + kCLOCK_UsbfsSrcNone = + SYSCON_USB0CLKSEL_SEL(7) /*!COMP &= ~(PMC_COMP_LOWPOWER_MASK | PMC_COMP_HYST_MASK | PMC_COMP_PMUX_MASK | PMC_COMP_NMUX_MASK); + + PMC->COMP |= (config->enLowPower << PMC_COMP_LOWPOWER_SHIFT) /*Select if enter low power mode*/ + | (config->enHysteris << PMC_COMP_HYST_SHIFT) /*select if enable hysteresis*/ + | config->pmuxInput /*pmux input source select*/ + | config->nmuxInput; /*nmux input source select */ +} + +void CMP_Deinit(void) +{ +/*disable the clock to the register interface*/ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + CLOCK_DisableClock(kCLOCK_Comp); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_cmp.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_cmp.h new file mode 100644 index 000000000..f0990cf66 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_cmp.h @@ -0,0 +1,293 @@ +/* + * Copyright 2018 NXP +* All rights reserved. +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef __FSL_CMP_H_ +#define __FSL_CMP_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup cmp_1 + * @{ + */ + +/****************************************************************************** + * Definitions. + *****************************************************************************/ +/*! @name Driver version */ +/*@{*/ +/*! @brief Driver version 2.0.0. */ +#define FSL_CMP_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 0U)) +/*@}*/ + +/*! @brief VREF select */ +enum _cmp_vref_select +{ + KCMP_VREFSelectVDDA = 1U, /*!< Select VDDA as VREF*/ + KCMP_VREFSelectInternalVREF = 0U, /*!< select internal VREF as VREF*/ +}; + +/*! @brief cmp interrupt type */ +typedef enum _cmp_interrupt_type +{ + kCMP_EdgeDisable = 0U << SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT, /*!< disable edge sensitive */ + kCMP_EdgeRising = 2U << SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT, /*!< Edge sensitive, falling edge */ + kCMP_EdgeFalling = 4U << SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT, /*!< Edge sensitive, rising edge */ + kCMP_EdgeRisingFalling = 6U << SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT, /*!< Edge sensitive, rising and falling edge */ + + kCMP_LevelDisable = 1U << SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT, /*!< disable level sensitive */ + kCMP_LevelHigh = 3U << SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT, /*!< Level sensitive, high level */ + kCMP_LevelLow = 5U << SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT, /*!< Level sensitive, low level */ + kCMP_LevelDisable1 = 7U << SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT, /*!< disable level sensitive */ +} cmp_interrupt_type_t; + +/*! @brief cmp Pmux input source */ +typedef enum _cmp_pmux_input +{ + kCMP_PInputVREF = 0U << PMC_COMP_PMUX_SHIFT, /*!< Cmp Pmux input from VREF */ + kCMP_PInputP0_0 = 1U << PMC_COMP_PMUX_SHIFT, /*!< Cmp Pmux input from P0_0 */ + kCMP_PInputP0_9 = 2U << PMC_COMP_PMUX_SHIFT, /*!< Cmp Pmux input from P0_9 */ + kCMP_PInputP0_18 = 3U << PMC_COMP_PMUX_SHIFT, /*!< Cmp Pmux input from P0_18 */ + kCMP_PInputP1_14 = 4U << PMC_COMP_PMUX_SHIFT, /*!< Cmp Pmux input from P1_14 */ + kCMP_PInputP2_23 = 5U << PMC_COMP_PMUX_SHIFT, /*!< Cmp Pmux input from P2_23 */ +} cmp_pmux_input_t; + +/*! @brief cmp Nmux input source */ +typedef enum _cmp_nmux_input +{ + kCMP_NInputVREF = 0U << PMC_COMP_NMUX_SHIFT, /*!< Cmp Nmux input from VREF */ + kCMP_NInputP0_0 = 1U << PMC_COMP_NMUX_SHIFT, /*!< Cmp Nmux input from P0_0 */ + kCMP_NInputP0_9 = 2U << PMC_COMP_NMUX_SHIFT, /*!< Cmp Nmux input from P0_9 */ + kCMP_NInputP0_18 = 3U << PMC_COMP_NMUX_SHIFT, /*!< Cmp Nmux input from P0_18 */ + kCMP_NInputP1_14 = 4U << PMC_COMP_NMUX_SHIFT, /*!< Cmp Nmux input from P1_14 */ + kCMP_NInputP2_23 = 5U << PMC_COMP_NMUX_SHIFT, /*!< Cmp Nmux input from P2_23 */ +} cmp_nmux_input_t; + +/*! @brief cmp configurataions */ +typedef struct _cmp_config +{ + bool enHysteris; /*!< low hysteresis */ + bool enLowPower; /*!COMP &= ~PMC_COMP_PMUX_MASK; + PMC->COMP |= pmux_select_source; +} + +/*! + * @brief select input source for nmux. + * + * @param nmux_select_source reference cmp_nmux_input_t above. + */ +static inline void CMP_NmuxSelect(cmp_nmux_input_t nmux_select_source) +{ + PMC->COMP &= ~PMC_COMP_NMUX_MASK; + PMC->COMP |= nmux_select_source; +} + +/*! + * @brief switch cmp work mode. + * + * @param enable true is enter low power mode, false is enter fast mode + */ +static inline void CMP_EnableLowePowerMode(bool enable) +{ + if (enable) + { + PMC->COMP |= PMC_COMP_LOWPOWER_MASK; + } + else + { + PMC->COMP &= ~PMC_COMP_LOWPOWER_MASK; + } +} + +/*! + * @brief Control reference voltage step, per steps of (VREFINPUT/31). + * + * @param step reference voltage step, per steps of (VREFINPUT/31). + */ +static inline void CMP_SetRefStep(uint32_t step) +{ + PMC->COMP |= step << PMC_COMP_VREF_SHIFT; +} + +/*! + * @brief cmp enable hysteresis. + * + */ +static inline void CMP_EnableHysteresis(bool enable) +{ + if (enable) + { + PMC->COMP |= PMC_COMP_HYST_MASK; + } + else + { + PMC->COMP &= ~PMC_COMP_HYST_MASK; + } +} + +/*! + * @brief VREF select between internal VREF and VDDA (for the resistive ladder). + * + * @param select 1 is Select VDDA, 0 is Select internal VREF. + */ +static inline void CMP_VREFSelect(uint32_t select) +{ + if (select) + { + PMC->COMP |= PMC_COMP_VREFINPUT_MASK; + } + else + { + PMC->COMP &= ~PMC_COMP_VREFINPUT_MASK; + } +} + +/*! + * @brief comparator analog output. + * + * @return 1 indicates p is greater than n, 0 indicates n is greater than p. + */ +static inline uint32_t CMP_GetOutput(void) +{ + return (SYSCON->COMP_INT_STATUS & SYSCON_COMP_INT_STATUS_VAL_MASK) ? 1 : 0; +} + +/* @} */ + +/*! + * @name cmp interrupt + * @{ + */ + +/*! + * @brief cmp enable interrupt. + * + */ +static inline void CMP_EnableInterrupt(void) +{ + SYSCON->COMP_INT_CTRL |= SYSCON_COMP_INT_CTRL_INT_ENABLE_MASK; +} + +/*! + * @brief cmp disable interrupt. + * + */ +static inline void CMP_DisableInterrupt(void) +{ + SYSCON->COMP_INT_CTRL &= ~SYSCON_COMP_INT_CTRL_INT_ENABLE_MASK; +} + +/*! + * @brief Select which Analog comparator output (filtered or un-filtered) is used for interrupt detection. + * + * @param enable true is Select Analog Comparator raw output (unfiltered) as input for interrupt detection. + * false is Select Analog Comparator filtered output as input for interrupt detection. + */ +static inline void CMP_InterruptSourceSelect(bool enable) +{ + if (enable) + { + SYSCON->COMP_INT_CTRL |= SYSCON_COMP_INT_CTRL_INT_SOURCE_MASK; + } + else + { + SYSCON->COMP_INT_CTRL &= ~SYSCON_COMP_INT_CTRL_INT_SOURCE_MASK; + } +} + +/*! + * @brief cmp get status. + * + * @return true is interrupt pending, false is no interrupt pending. + */ +static inline bool CMP_GetStatus(void) +{ + return (SYSCON->COMP_INT_STATUS & SYSCON_COMP_INT_STATUS_STATUS_MASK) ? true : false; +} + +/*! + * @brief cmp clear interrupt status. + * + */ +static inline void CMP_ClearStatus(void) +{ + SYSCON->COMP_INT_CTRL |= SYSCON_COMP_INT_CTRL_INT_CLEAR_MASK; +} + +/*! + * @brief Comparator interrupt type select. + * + * @param type reference cmp_interrupt_type_t. + */ +static inline void CMP_InterruptTypeSelect(cmp_interrupt_type_t cmp_interrupt_type) +{ + SYSCON->COMP_INT_CTRL &= ~SYSCON_COMP_INT_CTRL_INT_CTRL_MASK; + SYSCON->COMP_INT_CTRL |= cmp_interrupt_type; +} + +/*! + * @brief cmp get interrupt status. + * + * @return true is interrupt pending, false is no interrupt pending. + */ +static inline bool CMP_GetInterruptStatus(void) +{ + return (SYSCON->COMP_INT_STATUS & SYSCON_COMP_INT_STATUS_INT_STATUS_MASK) ? true : false; +} +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @} */ +#endif /* __FSL_CMP_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_common.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_common.c new file mode 100644 index 000000000..deca9c626 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_common.c @@ -0,0 +1,147 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" +#define SDK_MEM_MAGIC_NUMBER 12345U + +typedef struct _mem_align_control_block +{ + uint16_t identifier; /*!< Identifier for the memory control block. */ + uint16_t offset; /*!< offset from aligned address to real address */ +} mem_align_cb_t; + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.common" +#endif + +#ifndef __GIC_PRIO_BITS +#if defined(ENABLE_RAM_VECTOR_TABLE) +uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler) +{ +/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */ +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + extern uint32_t Image$$VECTOR_ROM$$Base[]; + extern uint32_t Image$$VECTOR_RAM$$Base[]; + extern uint32_t Image$$RW_m_data$$Base[]; + +#define __VECTOR_TABLE Image$$VECTOR_ROM$$Base +#define __VECTOR_RAM Image$$VECTOR_RAM$$Base +#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base)) +#elif defined(__ICCARM__) + extern uint32_t __RAM_VECTOR_TABLE_SIZE[]; + extern uint32_t __VECTOR_TABLE[]; + extern uint32_t __VECTOR_RAM[]; +#elif defined(__GNUC__) + extern uint32_t __VECTOR_TABLE[]; + extern uint32_t __VECTOR_RAM[]; + extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[]; + uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES); +#endif /* defined(__CC_ARM) || defined(__ARMCC_VERSION) */ + uint32_t n; + uint32_t ret; + uint32_t irqMaskValue; + + irqMaskValue = DisableGlobalIRQ(); + if (SCB->VTOR != (uint32_t)__VECTOR_RAM) + { + /* Copy the vector table from ROM to RAM */ + for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++) + { + __VECTOR_RAM[n] = __VECTOR_TABLE[n]; + } + /* Point the VTOR to the position of vector table */ + SCB->VTOR = (uint32_t)__VECTOR_RAM; + } + + ret = __VECTOR_RAM[irq + 16]; + /* make sure the __VECTOR_RAM is noncachable */ + __VECTOR_RAM[irq + 16] = irqHandler; + + EnableGlobalIRQ(irqMaskValue); + +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif + + return ret; +} +#endif /* ENABLE_RAM_VECTOR_TABLE. */ +#endif /* __GIC_PRIO_BITS. */ + +#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) +#if !(defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) + +void EnableDeepSleepIRQ(IRQn_Type interrupt) +{ + uint32_t intNumber = (uint32_t)interrupt; + + uint32_t index = 0; + + while (intNumber >= 32u) + { + index++; + intNumber -= 32u; + } + + SYSCON->STARTERSET[index] = 1u << intNumber; + EnableIRQ(interrupt); /* also enable interrupt at NVIC */ +} + +void DisableDeepSleepIRQ(IRQn_Type interrupt) +{ + uint32_t intNumber = (uint32_t)interrupt; + + DisableIRQ(interrupt); /* also disable interrupt at NVIC */ + uint32_t index = 0; + + while (intNumber >= 32u) + { + index++; + intNumber -= 32u; + } + + SYSCON->STARTERCLR[index] = 1u << intNumber; +} +#endif /* FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS */ +#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */ + +void *SDK_Malloc(size_t size, size_t alignbytes) +{ + mem_align_cb_t *p_cb = NULL; + uint32_t alignedsize = SDK_SIZEALIGN(size, alignbytes) + alignbytes + sizeof(mem_align_cb_t); + void *p_align_addr, *p_addr = malloc(alignedsize); + + if (!p_addr) + { + return NULL; + } + + p_align_addr = (void *)SDK_SIZEALIGN((uint32_t)p_addr + sizeof(mem_align_cb_t), alignbytes); + + p_cb = (mem_align_cb_t *)((uint32_t)p_align_addr - 4U); + p_cb->identifier = SDK_MEM_MAGIC_NUMBER; + p_cb->offset = (uint32_t)p_align_addr - (uint32_t)p_addr; + + return (void *)p_align_addr; +} + +void SDK_Free(void *ptr) +{ + mem_align_cb_t *p_cb = (mem_align_cb_t *)((uint32_t)ptr - 4U); + + if (p_cb->identifier != SDK_MEM_MAGIC_NUMBER) + { + return; + } + + free((void *)((uint32_t)ptr - p_cb->offset)); +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_common.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_common.h new file mode 100644 index 000000000..65bc0acce --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_common.h @@ -0,0 +1,597 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_COMMON_H_ +#define _FSL_COMMON_H_ + +#include +#include +#include +#include +#include + +#if defined(__ICCARM__) +#include +#endif + +#include "fsl_device_registers.h" + +/*! + * @addtogroup ksdk_common + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Construct a status code value from a group and code number. */ +#define MAKE_STATUS(group, code) ((((group)*100) + (code))) + +/*! @brief Construct the version number for drivers. */ +#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix)) + +/*! @name Driver version */ +/*@{*/ +/*! @brief common driver version 2.0.1. */ +#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) +/*@}*/ + +/* Debug console type definition. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U /*!< No debug console. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U /*!< Debug console based on UART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U /*!< Debug console based on LPUART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U /*!< Debug console based on LPSCI. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U /*!< Debug console based on USBCDC. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5U /*!< Debug console based on FLEXCOMM. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_IUART 6U /*!< Debug console based on i.MX UART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_VUSART 7U /*!< Debug console based on LPC_VUSART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_MINI_USART 8U /*!< Debug console based on LPC_USART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_SWO 9U /*!< Debug console based on SWO. */ + +/*! @brief Status group numbers. */ +enum _status_groups +{ + kStatusGroup_Generic = 0, /*!< Group number for generic status codes. */ + kStatusGroup_FLASH = 1, /*!< Group number for FLASH status codes. */ + kStatusGroup_LPSPI = 4, /*!< Group number for LPSPI status codes. */ + kStatusGroup_FLEXIO_SPI = 5, /*!< Group number for FLEXIO SPI status codes. */ + kStatusGroup_DSPI = 6, /*!< Group number for DSPI status codes. */ + kStatusGroup_FLEXIO_UART = 7, /*!< Group number for FLEXIO UART status codes. */ + kStatusGroup_FLEXIO_I2C = 8, /*!< Group number for FLEXIO I2C status codes. */ + kStatusGroup_LPI2C = 9, /*!< Group number for LPI2C status codes. */ + kStatusGroup_UART = 10, /*!< Group number for UART status codes. */ + kStatusGroup_I2C = 11, /*!< Group number for UART status codes. */ + kStatusGroup_LPSCI = 12, /*!< Group number for LPSCI status codes. */ + kStatusGroup_LPUART = 13, /*!< Group number for LPUART status codes. */ + kStatusGroup_SPI = 14, /*!< Group number for SPI status code.*/ + kStatusGroup_XRDC = 15, /*!< Group number for XRDC status code.*/ + kStatusGroup_SEMA42 = 16, /*!< Group number for SEMA42 status code.*/ + kStatusGroup_SDHC = 17, /*!< Group number for SDHC status code */ + kStatusGroup_SDMMC = 18, /*!< Group number for SDMMC status code */ + kStatusGroup_SAI = 19, /*!< Group number for SAI status code */ + kStatusGroup_MCG = 20, /*!< Group number for MCG status codes. */ + kStatusGroup_SCG = 21, /*!< Group number for SCG status codes. */ + kStatusGroup_SDSPI = 22, /*!< Group number for SDSPI status codes. */ + kStatusGroup_FLEXIO_I2S = 23, /*!< Group number for FLEXIO I2S status codes */ + kStatusGroup_FLEXIO_MCULCD = 24, /*!< Group number for FLEXIO LCD status codes */ + kStatusGroup_FLASHIAP = 25, /*!< Group number for FLASHIAP status codes */ + kStatusGroup_FLEXCOMM_I2C = 26, /*!< Group number for FLEXCOMM I2C status codes */ + kStatusGroup_I2S = 27, /*!< Group number for I2S status codes */ + kStatusGroup_IUART = 28, /*!< Group number for IUART status codes */ + kStatusGroup_CSI = 29, /*!< Group number for CSI status codes */ + kStatusGroup_MIPI_DSI = 30, /*!< Group number for MIPI DSI status codes */ + kStatusGroup_SDRAMC = 35, /*!< Group number for SDRAMC status codes. */ + kStatusGroup_POWER = 39, /*!< Group number for POWER status codes. */ + kStatusGroup_ENET = 40, /*!< Group number for ENET status codes. */ + kStatusGroup_PHY = 41, /*!< Group number for PHY status codes. */ + kStatusGroup_TRGMUX = 42, /*!< Group number for TRGMUX status codes. */ + kStatusGroup_SMARTCARD = 43, /*!< Group number for SMARTCARD status codes. */ + kStatusGroup_LMEM = 44, /*!< Group number for LMEM status codes. */ + kStatusGroup_QSPI = 45, /*!< Group number for QSPI status codes. */ + kStatusGroup_DMA = 50, /*!< Group number for DMA status codes. */ + kStatusGroup_EDMA = 51, /*!< Group number for EDMA status codes. */ + kStatusGroup_DMAMGR = 52, /*!< Group number for DMAMGR status codes. */ + kStatusGroup_FLEXCAN = 53, /*!< Group number for FlexCAN status codes. */ + kStatusGroup_LTC = 54, /*!< Group number for LTC status codes. */ + kStatusGroup_FLEXIO_CAMERA = 55, /*!< Group number for FLEXIO CAMERA status codes. */ + kStatusGroup_LPC_SPI = 56, /*!< Group number for LPC_SPI status codes. */ + kStatusGroup_LPC_USART = 57, /*!< Group number for LPC_USART status codes. */ + kStatusGroup_DMIC = 58, /*!< Group number for DMIC status codes. */ + kStatusGroup_SDIF = 59, /*!< Group number for SDIF status codes.*/ + kStatusGroup_SPIFI = 60, /*!< Group number for SPIFI status codes. */ + kStatusGroup_OTP = 61, /*!< Group number for OTP status codes. */ + kStatusGroup_MCAN = 62, /*!< Group number for MCAN status codes. */ + kStatusGroup_CAAM = 63, /*!< Group number for CAAM status codes. */ + kStatusGroup_ECSPI = 64, /*!< Group number for ECSPI status codes. */ + kStatusGroup_USDHC = 65, /*!< Group number for USDHC status codes.*/ + kStatusGroup_LPC_I2C = 66, /*!< Group number for LPC_I2C status codes.*/ + kStatusGroup_DCP = 67, /*!< Group number for DCP status codes.*/ + kStatusGroup_MSCAN = 68, /*!< Group number for MSCAN status codes.*/ + kStatusGroup_ESAI = 69, /*!< Group number for ESAI status codes. */ + kStatusGroup_FLEXSPI = 70, /*!< Group number for FLEXSPI status codes. */ + kStatusGroup_MMDC = 71, /*!< Group number for MMDC status codes. */ + kStatusGroup_PDM = 72, /*!< Group number for MIC status codes. */ + kStatusGroup_SDMA = 73, /*!< Group number for SDMA status codes. */ + kStatusGroup_ICS = 74, /*!< Group number for ICS status codes. */ + kStatusGroup_SPDIF = 75, /*!< Group number for SPDIF status codes. */ + kStatusGroup_LPC_MINISPI = 76, /*!< Group number for LPC_MINISPI status codes. */ + kStatusGroup_HASHCRYPT = 77, /*!< Group number for Hashcrypt status codes */ + kStatusGroup_LPC_SPI_SSP = 78, /*!< Group number for LPC_SPI_SSP status codes. */ + kStatusGroup_I3C = 79, /*!< Group number for I3C status codes */ + kStatusGroup_LPC_I2C_1 = 97, /*!< Group number for LPC_I2C_1 status codes. */ + kStatusGroup_NOTIFIER = 98, /*!< Group number for NOTIFIER status codes. */ + kStatusGroup_DebugConsole = 99, /*!< Group number for debug console status codes. */ + kStatusGroup_SEMC = 100, /*!< Group number for SEMC status codes. */ + kStatusGroup_ApplicationRangeStart = 101, /*!< Starting number for application groups. */ + kStatusGroup_IAP = 102, /*!< Group number for IAP status codes */ + + kStatusGroup_HAL_GPIO = 121, /*!< Group number for HAL GPIO status codes. */ + kStatusGroup_HAL_UART = 122, /*!< Group number for HAL UART status codes. */ + kStatusGroup_HAL_TIMER = 123, /*!< Group number for HAL TIMER status codes. */ + kStatusGroup_HAL_SPI = 124, /*!< Group number for HAL SPI status codes. */ + kStatusGroup_HAL_I2C = 125, /*!< Group number for HAL I2C status codes. */ + kStatusGroup_HAL_FLASH = 126, /*!< Group number for HAL FLASH status codes. */ + kStatusGroup_HAL_PWM = 127, /*!< Group number for HAL PWM status codes. */ + kStatusGroup_HAL_RNG = 128, /*!< Group number for HAL RNG status codes. */ + kStatusGroup_TIMERMANAGER = 135, /*!< Group number for TiMER MANAGER status codes. */ + kStatusGroup_SERIALMANAGER = 136, /*!< Group number for SERIAL MANAGER status codes. */ + kStatusGroup_LED = 137, /*!< Group number for LED status codes. */ + kStatusGroup_BUTTON = 138, /*!< Group number for BUTTON status codes. */ + kStatusGroup_EXTERN_EEPROM = 139, /*!< Group number for EXTERN EEPROM status codes. */ + kStatusGroup_SHELL = 140, /*!< Group number for SHELL status codes. */ + kStatusGroup_MEM_MANAGER = 141, /*!< Group number for MEM MANAGER status codes. */ + kStatusGroup_LIST = 142, /*!< Group number for List status codes. */ + kStatusGroup_OSA = 143, /*!< Group number for OSA status codes. */ + kStatusGroup_COMMON_TASK = 144, /*!< Group number for Common task status codes. */ + kStatusGroup_MSG = 145, /*!< Group number for messaging status codes. */ + kStatusGroup_SDK_OCOTP = 146, /*!< Group number for OCOTP status codes. */ + kStatusGroup_SDK_FLEXSPINOR = 147, /*!< Group number for FLEXSPINOR status codes.*/ + kStatusGroup_CODEC = 148, /*!< Group number for codec status codes. */ +}; + +/*! @brief Generic status return codes. */ +enum _generic_status +{ + kStatus_Success = MAKE_STATUS(kStatusGroup_Generic, 0), + kStatus_Fail = MAKE_STATUS(kStatusGroup_Generic, 1), + kStatus_ReadOnly = MAKE_STATUS(kStatusGroup_Generic, 2), + kStatus_OutOfRange = MAKE_STATUS(kStatusGroup_Generic, 3), + kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4), + kStatus_Timeout = MAKE_STATUS(kStatusGroup_Generic, 5), + kStatus_NoTransferInProgress = MAKE_STATUS(kStatusGroup_Generic, 6), +}; + +/*! @brief Type used for all status and error return values. */ +typedef int32_t status_t; + +/* + * Macro guard for whether to use default weak IRQ implementation in drivers + */ +#ifndef FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ +#define FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ 1 +#endif + +/*! @name Min/max macros */ +/* @{ */ +#if !defined(MIN) +#define MIN(a, b) (((a) < (b)) ? (a) : (b)) +#endif + +#if !defined(MAX) +#define MAX(a, b) (((a) > (b)) ? (a) : (b)) +#endif +/* @} */ + +/*! @brief Computes the number of elements in an array. */ +#if !defined(ARRAY_SIZE) +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) +#endif + +/*! @name UINT16_MAX/UINT32_MAX value */ +/* @{ */ +#if !defined(UINT16_MAX) +#define UINT16_MAX ((uint16_t)-1) +#endif + +#if !defined(UINT32_MAX) +#define UINT32_MAX ((uint32_t)-1) +#endif +/* @} */ + +/*! @name Timer utilities */ +/* @{ */ +/*! Macro to convert a microsecond period to raw count value */ +#define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)((uint64_t)us * clockFreqInHz / 1000000U) +/*! Macro to convert a raw count value to microsecond */ +#define COUNT_TO_USEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000000U / clockFreqInHz) + +/*! Macro to convert a millisecond period to raw count value */ +#define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)ms * clockFreqInHz / 1000U) +/*! Macro to convert a raw count value to millisecond */ +#define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000U / clockFreqInHz) +/* @} */ + +/*! @name Alignment variable definition macros */ +/* @{ */ +#if (defined(__ICCARM__)) +/** + * Workaround to disable MISRA C message suppress warnings for IAR compiler. + * http://supp.iar.com/Support/?note=24725 + */ +_Pragma("diag_suppress=Pm120") +#define SDK_PRAGMA(x) _Pragma(#x) + _Pragma("diag_error=Pm120") +/*! Macro to define a variable with alignbytes alignment */ +#define SDK_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var +/*! Macro to define a variable with L1 d-cache line size alignment */ +#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#define SDK_L1DCACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) var +#endif +/*! Macro to define a variable with L2 cache line size alignment */ +#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) +#define SDK_L2CACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L2CACHE_LINESIZE_BYTE) var +#endif +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +/*! Macro to define a variable with alignbytes alignment */ +#define SDK_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var +/*! Macro to define a variable with L1 d-cache line size alignment */ +#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#define SDK_L1DCACHE_ALIGN(var) __attribute__((aligned(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE))) var +#endif +/*! Macro to define a variable with L2 cache line size alignment */ +#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) +#define SDK_L2CACHE_ALIGN(var) __attribute__((aligned(FSL_FEATURE_L2CACHE_LINESIZE_BYTE))) var +#endif +#elif defined(__GNUC__) +/*! Macro to define a variable with alignbytes alignment */ +#define SDK_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes))) +/*! Macro to define a variable with L1 d-cache line size alignment */ +#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#define SDK_L1DCACHE_ALIGN(var) var __attribute__((aligned(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE))) +#endif +/*! Macro to define a variable with L2 cache line size alignment */ +#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) +#define SDK_L2CACHE_ALIGN(var) var __attribute__((aligned(FSL_FEATURE_L2CACHE_LINESIZE_BYTE))) +#endif +#else +#error Toolchain not supported +#define SDK_ALIGN(var, alignbytes) var +#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#define SDK_L1DCACHE_ALIGN(var) var +#endif +#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) +#define SDK_L2CACHE_ALIGN(var) var +#endif +#endif + +/*! Macro to change a value to a given size aligned value */ +#define SDK_SIZEALIGN(var, alignbytes) \ + ((unsigned int)((var) + ((alignbytes)-1)) & (unsigned int)(~(unsigned int)((alignbytes)-1))) +/* @} */ + +/*! @name Non-cacheable region definition macros */ +/* For initialized non-zero non-cacheable variables, please using "AT_NONCACHEABLE_SECTION_INIT(var) ={xx};" or + * "AT_NONCACHEABLE_SECTION_ALIGN_INIT(var) ={xx};" in your projects to define them, for zero-inited non-cacheable variables, + * please using "AT_NONCACHEABLE_SECTION(var);" or "AT_NONCACHEABLE_SECTION_ALIGN(var);" to define them, these zero-inited variables + * will be initialized to zero in system startup. + */ +/* @{ */ +#if (defined(__ICCARM__)) +#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)) +#define AT_NONCACHEABLE_SECTION(var) var @"NonCacheable" +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable" +#define AT_NONCACHEABLE_SECTION_INIT(var) var @"NonCacheable.init" +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable.init" +#else +#define AT_NONCACHEABLE_SECTION(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var +#define AT_NONCACHEABLE_SECTION_INIT(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var +#endif +#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION)) +#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)) +#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"), zero_init)) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ + __attribute__((section("NonCacheable"), zero_init)) __attribute__((aligned(alignbytes))) var +#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \ + __attribute__((section("NonCacheable.init"))) __attribute__((aligned(alignbytes))) var +#else +#define AT_NONCACHEABLE_SECTION(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var +#define AT_NONCACHEABLE_SECTION_INIT(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) __attribute__((aligned(alignbytes))) var +#endif +#elif(defined(__GNUC__)) +/* For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA" + * in your projects to make sure the non-cacheable section variables will be initialized in system startup. + */ +#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)) +#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \ + __attribute__((section("NonCacheable.init"))) var __attribute__((aligned(alignbytes))) +#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ + __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var __attribute__((aligned(alignbytes))) +#else +#define AT_NONCACHEABLE_SECTION(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes))) +#define AT_NONCACHEABLE_SECTION_INIT(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) var __attribute__((aligned(alignbytes))) +#endif +#else +#error Toolchain not supported. +#define AT_NONCACHEABLE_SECTION(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var +#define AT_NONCACHEABLE_SECTION_INIT(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) var +#endif +/* @} */ + +/*! @name Time sensitive region */ +/* @{ */ +#if defined(FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE) && FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE +#if (defined(__ICCARM__)) +#define AT_QUICKACCESS_SECTION_CODE(func) func @"CodeQuickAccess" +#define AT_QUICKACCESS_SECTION_DATA(func) func @"DataQuickAccess" +#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION)) +#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"))) func +#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func +#elif(defined(__GNUC__)) +#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"))) func +#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func +#else +#error Toolchain not supported. +#endif /* defined(__ICCARM__) */ +#else +#if (defined(__ICCARM__)) +#define AT_QUICKACCESS_SECTION_CODE(func) func +#define AT_QUICKACCESS_SECTION_DATA(func) func +#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION)) +#define AT_QUICKACCESS_SECTION_CODE(func) func +#define AT_QUICKACCESS_SECTION_DATA(func) func +#elif(defined(__GNUC__)) +#define AT_QUICKACCESS_SECTION_CODE(func) func +#define AT_QUICKACCESS_SECTION_DATA(func) func +#else +#error Toolchain not supported. +#endif +#endif /* __FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE */ +/* @} */ + +/*! @name Ram Function */ +#if (defined(__ICCARM__)) +#define RAMFUNCTION_SECTION_CODE(func) func @"RamFunction" +#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION)) +#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func +#elif(defined(__GNUC__)) +#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func +#else +#error Toolchain not supported. +#endif /* defined(__ICCARM__) */ +/* @} */ + +/* + * The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t + * defined in previous of this file. + */ +#include "fsl_clock.h" + +/* + * Chip level peripheral reset API, for MCUs that implement peripheral reset control external to a peripheral + */ +#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \ + (defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0))) +#include "fsl_reset.h" +#endif + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) + extern "C" +{ +#endif + + /*! + * @brief Enable specific interrupt. + * + * Enable LEVEL1 interrupt. For some devices, there might be multiple interrupt + * levels. For example, there are NVIC and intmux. Here the interrupts connected + * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. + * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed + * to NVIC first then routed to core. + * + * This function only enables the LEVEL1 interrupts. The number of LEVEL1 interrupts + * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS. + * + * @param interrupt The IRQ number. + * @retval kStatus_Success Interrupt enabled successfully + * @retval kStatus_Fail Failed to enable the interrupt + */ + static inline status_t EnableIRQ(IRQn_Type interrupt) + { + if (NotAvail_IRQn == interrupt) + { + return kStatus_Fail; + } + +#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) + if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) + { + return kStatus_Fail; + } +#endif + +#if defined(__GIC_PRIO_BITS) + GIC_EnableIRQ(interrupt); +#else + NVIC_EnableIRQ(interrupt); +#endif + return kStatus_Success; + } + + /*! + * @brief Disable specific interrupt. + * + * Disable LEVEL1 interrupt. For some devices, there might be multiple interrupt + * levels. For example, there are NVIC and intmux. Here the interrupts connected + * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. + * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed + * to NVIC first then routed to core. + * + * This function only disables the LEVEL1 interrupts. The number of LEVEL1 interrupts + * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS. + * + * @param interrupt The IRQ number. + * @retval kStatus_Success Interrupt disabled successfully + * @retval kStatus_Fail Failed to disable the interrupt + */ + static inline status_t DisableIRQ(IRQn_Type interrupt) + { + if (NotAvail_IRQn == interrupt) + { + return kStatus_Fail; + } + +#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) + if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) + { + return kStatus_Fail; + } +#endif + +#if defined(__GIC_PRIO_BITS) + GIC_DisableIRQ(interrupt); +#else + NVIC_DisableIRQ(interrupt); +#endif + return kStatus_Success; + } + + /*! + * @brief Disable the global IRQ + * + * Disable the global interrupt and return the current primask register. User is required to provided the primask + * register for the EnableGlobalIRQ(). + * + * @return Current primask value. + */ + static inline uint32_t DisableGlobalIRQ(void) + { +#if defined (__XCC__) + return 0; +#else +#if defined(CPSR_I_Msk) + uint32_t cpsr = __get_CPSR() & CPSR_I_Msk; + + __disable_irq(); + + return cpsr; +#else + uint32_t regPrimask = __get_PRIMASK(); + + __disable_irq(); + + return regPrimask; +#endif +#endif + } + + /*! + * @brief Enable the global IRQ + * + * Set the primask register with the provided primask value but not just enable the primask. The idea is for the + * convenience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to + * use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair. + * + * @param primask value of primask register to be restored. The primask value is supposed to be provided by the + * DisableGlobalIRQ(). + */ + static inline void EnableGlobalIRQ(uint32_t primask) + { +#if defined (__XCC__) +#else +#if defined(CPSR_I_Msk) + __set_CPSR((__get_CPSR() & ~CPSR_I_Msk) | primask); +#else + __set_PRIMASK(primask); +#endif +#endif + } + +#if defined(ENABLE_RAM_VECTOR_TABLE) + /*! + * @brief install IRQ handler + * + * @param irq IRQ number + * @param irqHandler IRQ handler address + * @return The old IRQ handler address + */ + uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler); +#endif /* ENABLE_RAM_VECTOR_TABLE. */ + +#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) + /*! + * @brief Enable specific interrupt for wake-up from deep-sleep mode. + * + * Enable the interrupt for wake-up from deep sleep mode. + * Some interrupts are typically used in sleep mode only and will not occur during + * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable + * those clocks (significantly increasing power consumption in the reduced power mode), + * making these wake-ups possible. + * + * @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internaly). + * + * @param interrupt The IRQ number. + */ + void EnableDeepSleepIRQ(IRQn_Type interrupt); + + /*! + * @brief Disable specific interrupt for wake-up from deep-sleep mode. + * + * Disable the interrupt for wake-up from deep sleep mode. + * Some interrupts are typically used in sleep mode only and will not occur during + * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable + * those clocks (significantly increasing power consumption in the reduced power mode), + * making these wake-ups possible. + * + * @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internaly). + * + * @param interrupt The IRQ number. + */ + void DisableDeepSleepIRQ(IRQn_Type interrupt); +#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */ + + /*! + * @brief Allocate memory with given alignment and aligned size. + * + * This is provided to support the dynamically allocated memory + * used in cache-able region. + * @param size The length required to malloc. + * @param alignbytes The alignment size. + * @retval The allocated memory. + */ + void *SDK_Malloc(size_t size, size_t alignbytes); + + /*! + * @brief Free memory. + * + * @param ptr The memory to be release. + */ + void SDK_Free(void *ptr); + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /* _FSL_COMMON_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_crc.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_crc.c new file mode 100644 index 000000000..4e88cf5c6 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_crc.c @@ -0,0 +1,172 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include "fsl_crc.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpc_crc" +#endif + +#if defined(CRC_DRIVER_USE_CRC16_CCITT_FALSE_AS_DEFAULT) && CRC_DRIVER_USE_CRC16_CCITT_FALSE_AS_DEFAULT +/* @brief Default user configuration structure for CRC-CCITT */ +#define CRC_DRIVER_DEFAULT_POLYNOMIAL kCRC_Polynomial_CRC_CCITT +/*< CRC-CCIT polynomial x^16 + x^12 + x^5 + x^0 */ +#define CRC_DRIVER_DEFAULT_REVERSE_IN false +/*< Default is no bit reverse */ +#define CRC_DRIVER_DEFAULT_COMPLEMENT_IN false +/*< Default is without complement of written data */ +#define CRC_DRIVER_DEFAULT_REVERSE_OUT false +/*< Default is no bit reverse */ +#define CRC_DRIVER_DEFAULT_COMPLEMENT_OUT false +/*< Default is without complement of CRC data register read data */ +#define CRC_DRIVER_DEFAULT_SEED 0xFFFFU +/*< Default initial checksum */ +#endif /* CRC_DRIVER_USE_CRC16_CCITT_FALSE_AS_DEFAULT */ + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * brief Enables and configures the CRC peripheral module. + * + * This functions enables the CRC peripheral clock in the LPC SYSCON block. + * It also configures the CRC engine and starts checksum computation by writing the seed. + * + * param base CRC peripheral address. + * param config CRC module configuration structure. + */ +void CRC_Init(CRC_Type *base, const crc_config_t *config) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* enable clock to CRC */ + CLOCK_EnableClock(kCLOCK_Crc); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_FEATURE_CRC_HAS_NO_RESET) && FSL_FEATURE_CRC_HAS_NO_RESET) + RESET_PeripheralReset(kCRC_RST_SHIFT_RSTn); +#endif + + /* configure CRC module and write the seed */ + base->MODE = 0 | CRC_MODE_CRC_POLY(config->polynomial) | CRC_MODE_BIT_RVS_WR(config->reverseIn) | + CRC_MODE_CMPL_WR(config->complementIn) | CRC_MODE_BIT_RVS_SUM(config->reverseOut) | + CRC_MODE_CMPL_SUM(config->complementOut); + base->SEED = config->seed; +} + +/*! + * brief Loads default values to CRC protocol configuration structure. + * + * Loads default values to CRC protocol configuration structure. The default values are: + * code + * config->polynomial = kCRC_Polynomial_CRC_CCITT; + * config->reverseIn = false; + * config->complementIn = false; + * config->reverseOut = false; + * config->complementOut = false; + * config->seed = 0xFFFFU; + * endcode + * + * param config CRC protocol configuration structure + */ +void CRC_GetDefaultConfig(crc_config_t *config) +{ + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + + static const crc_config_t default_config = {CRC_DRIVER_DEFAULT_POLYNOMIAL, CRC_DRIVER_DEFAULT_REVERSE_IN, + CRC_DRIVER_DEFAULT_COMPLEMENT_IN, CRC_DRIVER_DEFAULT_REVERSE_OUT, + CRC_DRIVER_DEFAULT_COMPLEMENT_OUT, CRC_DRIVER_DEFAULT_SEED}; + + *config = default_config; +} + +/*! + * brief resets CRC peripheral module. + * + * param base CRC peripheral address. + */ +void CRC_Reset(CRC_Type *base) +{ + crc_config_t config; + CRC_GetDefaultConfig(&config); + CRC_Init(base, &config); +} + +/*! + * brief Loads actual values configured in CRC peripheral to CRC protocol configuration structure. + * + * The values, including seed, can be used to resume CRC calculation later. + + * param base CRC peripheral address. + * param config CRC protocol configuration structure + */ +void CRC_GetConfig(CRC_Type *base, crc_config_t *config) +{ + /* extract CRC mode settings */ + uint32_t mode = base->MODE; + config->polynomial = (crc_polynomial_t)((mode & CRC_MODE_CRC_POLY_MASK) >> CRC_MODE_CRC_POLY_SHIFT); + config->reverseIn = (bool)(mode & CRC_MODE_BIT_RVS_WR_MASK); + config->complementIn = (bool)(mode & CRC_MODE_CMPL_WR_MASK); + config->reverseOut = (bool)(mode & CRC_MODE_BIT_RVS_SUM_MASK); + config->complementOut = (bool)(mode & CRC_MODE_CMPL_SUM_MASK); + + /* reset CRC sum bit reverse and 1's complement setting, so its value can be used as a seed */ + base->MODE = mode & ~((1U << CRC_MODE_BIT_RVS_SUM_SHIFT) | (1U << CRC_MODE_CMPL_SUM_SHIFT)); + + /* now we can obtain intermediate raw CRC sum value */ + config->seed = base->SUM; + + /* restore original CRC sum bit reverse and 1's complement setting */ + base->MODE = mode; +} + +/*! + * brief Writes data to the CRC module. + * + * Writes input data buffer bytes to CRC data register. + * + * param base CRC peripheral address. + * param data Input data stream, MSByte in data[0]. + * param dataSize Size of the input data buffer in bytes. + */ +void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize) +{ + const uint32_t *data32; + + /* 8-bit reads and writes till source address is aligned 4 bytes */ + while ((dataSize) && ((uint32_t)data & 3U)) + { + *((__O uint8_t *)&(base->WR_DATA)) = *data; + data++; + dataSize--; + } + + /* use 32-bit reads and writes as long as possible */ + data32 = (const uint32_t *)data; + while (dataSize >= sizeof(uint32_t)) + { + *((__O uint32_t *)&(base->WR_DATA)) = *data32; + data32++; + dataSize -= sizeof(uint32_t); + } + + data = (const uint8_t *)data32; + + /* 8-bit reads and writes till end of data buffer */ + while (dataSize) + { + *((__O uint8_t *)&(base->WR_DATA)) = *data; + data++; + dataSize--; + } +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_crc.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_crc.h new file mode 100644 index 000000000..0ef6b700e --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_crc.h @@ -0,0 +1,181 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_CRC_H_ +#define _FSL_CRC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup crc + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief CRC driver version. Version 2.0.1. + * + * Current version: 2.0.1 + * + * Change log: + * - Version 2.0.0 + * - initial version + * - Version 2.0.1 + * - add explicit type cast when writing to WR_DATA + */ +#define FSL_CRC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +#ifndef CRC_DRIVER_CUSTOM_DEFAULTS +/*! @brief Default configuration structure filled by CRC_GetDefaultConfig(). Uses CRC-16/CCITT-FALSE as default. */ +#define CRC_DRIVER_USE_CRC16_CCITT_FALSE_AS_DEFAULT 1 +#endif + +/*! @brief CRC polynomials to use. */ +typedef enum _crc_polynomial +{ + kCRC_Polynomial_CRC_CCITT = 0U, /*!< x^16+x^12+x^5+1 */ + kCRC_Polynomial_CRC_16 = 1U, /*!< x^16+x^15+x^2+1 */ + kCRC_Polynomial_CRC_32 = 2U /*!< x^32+x^26+x^23+x^22+x^16+x^12+x^11+x^10+x^8+x^7+x^5+x^4+x^2+x+1 */ +} crc_polynomial_t; + +/*! + * @brief CRC protocol configuration. + * + * This structure holds the configuration for the CRC protocol. + * + */ +typedef struct _crc_config +{ + crc_polynomial_t polynomial; /*!< CRC polynomial. */ + bool reverseIn; /*!< Reverse bits on input. */ + bool complementIn; /*!< Perform 1's complement on input. */ + bool reverseOut; /*!< Reverse bits on output. */ + bool complementOut; /*!< Perform 1's complement on output. */ + uint32_t seed; /*!< Starting checksum value. */ +} crc_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Enables and configures the CRC peripheral module. + * + * This functions enables the CRC peripheral clock in the LPC SYSCON block. + * It also configures the CRC engine and starts checksum computation by writing the seed. + * + * @param base CRC peripheral address. + * @param config CRC module configuration structure. + */ +void CRC_Init(CRC_Type *base, const crc_config_t *config); + +/*! + * @brief Disables the CRC peripheral module. + * + * This functions disables the CRC peripheral clock in the LPC SYSCON block. + * + * @param base CRC peripheral address. + */ +static inline void CRC_Deinit(CRC_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* disable clock to CRC */ + CLOCK_DisableClock(kCLOCK_Crc); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * @brief resets CRC peripheral module. + * + * @param base CRC peripheral address. + */ +void CRC_Reset(CRC_Type *base); + +/*! + * @brief Loads default values to CRC protocol configuration structure. + * + * Loads default values to CRC protocol configuration structure. The default values are: + * @code + * config->polynomial = kCRC_Polynomial_CRC_CCITT; + * config->reverseIn = false; + * config->complementIn = false; + * config->reverseOut = false; + * config->complementOut = false; + * config->seed = 0xFFFFU; + * @endcode + * + * @param config CRC protocol configuration structure + */ +void CRC_GetDefaultConfig(crc_config_t *config); + +/*! + * @brief Loads actual values configured in CRC peripheral to CRC protocol configuration structure. + * + * The values, including seed, can be used to resume CRC calculation later. + + * @param base CRC peripheral address. + * @param config CRC protocol configuration structure + */ +void CRC_GetConfig(CRC_Type *base, crc_config_t *config); + +/*! + * @brief Writes data to the CRC module. + * + * Writes input data buffer bytes to CRC data register. + * + * @param base CRC peripheral address. + * @param data Input data stream, MSByte in data[0]. + * @param dataSize Size of the input data buffer in bytes. + */ +void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize); + +/*! + * @brief Reads 32-bit checksum from the CRC module. + * + * Reads CRC data register. + * + * @param base CRC peripheral address. + * @return final 32-bit checksum, after configured bit reverse and complement operations. + */ +static inline uint32_t CRC_Get32bitResult(CRC_Type *base) +{ + return base->SUM; +} + +/*! + * @brief Reads 16-bit checksum from the CRC module. + * + * Reads CRC data register. + * + * @param base CRC peripheral address. + * @return final 16-bit checksum, after configured bit reverse and complement operations. + */ +static inline uint16_t CRC_Get16bitResult(CRC_Type *base) +{ + return (uint16_t)base->SUM; +} + +#if defined(__cplusplus) +} +#endif + +/*! + *@} + */ + +#endif /* _FSL_CRC_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_ctimer.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_ctimer.c new file mode 100644 index 000000000..590ab321c --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_ctimer.c @@ -0,0 +1,544 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_ctimer.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.ctimer" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Gets the instance from the base address + * + * @param base Ctimer peripheral base address + * + * @return The Timer instance + */ +static uint32_t CTIMER_GetInstance(CTIMER_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to Timer bases for each instance. */ +static CTIMER_Type *const s_ctimerBases[] = CTIMER_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to Timer clocks for each instance. */ +static const clock_ip_name_t s_ctimerClocks[] = CTIMER_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_RESET) && (FSL_FEATURE_CTIMER_HAS_NO_RESET)) +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) +#if defined(FSL_FEATURE_CTIMER_WRITE_ZERO_ASSERT_RESET) && FSL_FEATURE_CTIMER_WRITE_ZERO_ASSERT_RESET +/*! @brief Pointers to Timer resets for each instance, writing a zero asserts the reset */ +static const reset_ip_name_t s_ctimerResets[] = CTIMER_RSTS_N; +#else +/*! @brief Pointers to Timer resets for each instance, writing a one asserts the reset */ +static const reset_ip_name_t s_ctimerResets[] = CTIMER_RSTS; +#endif +#endif +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + +/*! @brief Pointers real ISRs installed by drivers for each instance. */ +static ctimer_callback_t *s_ctimerCallback[FSL_FEATURE_SOC_CTIMER_COUNT] = {0}; + +/*! @brief Callback type installed by drivers for each instance. */ +static ctimer_callback_type_t ctimerCallbackType[FSL_FEATURE_SOC_CTIMER_COUNT] = {kCTIMER_SingleCallback}; + +/*! @brief Array to map timer instance to IRQ number. */ +static const IRQn_Type s_ctimerIRQ[] = CTIMER_IRQS; + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t CTIMER_GetInstance(CTIMER_Type *base) +{ + uint32_t instance; + uint32_t ctimerArrayCount = (sizeof(s_ctimerBases) / sizeof(s_ctimerBases[0])); + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ctimerArrayCount; instance++) + { + if (s_ctimerBases[instance] == base) + { + break; + } + } + + assert(instance < ctimerArrayCount); + + return instance; +} + +/*! + * brief Ungates the clock and configures the peripheral for basic operation. + * + * note This API should be called at the beginning of the application before using the driver. + * + * param base Ctimer peripheral base address + * param config Pointer to the user configuration structure. + */ +void CTIMER_Init(CTIMER_Type *base, const ctimer_config_t *config) +{ + assert(config); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the timer clock*/ + CLOCK_EnableClock(s_ctimerClocks[CTIMER_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) +/* Reset the module. */ +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_RESET) && (FSL_FEATURE_CTIMER_HAS_NO_RESET)) + RESET_PeripheralReset(s_ctimerResets[CTIMER_GetInstance(base)]); +#endif +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + +/* Setup the cimer mode and count select */ +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) + base->CTCR = CTIMER_CTCR_CTMODE(config->mode) | CTIMER_CTCR_CINSEL(config->input); +#endif + /* Setup the timer prescale value */ + base->PR = CTIMER_PR_PRVAL(config->prescale); +} + +/*! + * brief Gates the timer clock. + * + * param base Ctimer peripheral base address + */ +void CTIMER_Deinit(CTIMER_Type *base) +{ + uint32_t index = CTIMER_GetInstance(base); + /* Stop the timer */ + base->TCR &= ~CTIMER_TCR_CEN_MASK; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable the timer clock*/ + CLOCK_DisableClock(s_ctimerClocks[index]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Disable IRQ at NVIC Level */ + DisableIRQ(s_ctimerIRQ[index]); +} + +/*! + * brief Fills in the timers configuration structure with the default settings. + * + * The default values are: + * code + * config->mode = kCTIMER_TimerMode; + * config->input = kCTIMER_Capture_0; + * config->prescale = 0; + * endcode + * param config Pointer to the user configuration structure. + */ +void CTIMER_GetDefaultConfig(ctimer_config_t *config) +{ + assert(config); + + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + + /* Run as a timer */ + config->mode = kCTIMER_TimerMode; + /* This field is ignored when mode is timer */ + config->input = kCTIMER_Capture_0; + /* Timer counter is incremented on every APB bus clock */ + config->prescale = 0; +} + +/*! + * brief Configures the PWM signal parameters. + * + * Enables PWM mode on the match channel passed in and will then setup the match value + * and other match parameters to generate a PWM signal. + * This function will assign match channel 3 to set the PWM cycle. + * + * note When setting PWM output from multiple output pins, all should use the same PWM + * frequency. Please use CTIMER_SetupPwmPeriod to set up the PWM with high resolution. + * + * param base Ctimer peripheral base address + * param matchChannel Match pin to be used to output the PWM signal + * param dutyCyclePercent PWM pulse width; the value should be between 0 to 100 + * param pwmFreq_Hz PWM signal frequency in Hz + * param srcClock_Hz Timer counter clock in Hz + * param enableInt Enable interrupt when the timer value reaches the match value of the PWM pulse, + * if it is 0 then no interrupt is generated + * + * return kStatus_Success on success + * kStatus_Fail If matchChannel passed in is 3; this channel is reserved to set the PWM cycle + */ +status_t CTIMER_SetupPwm(CTIMER_Type *base, + ctimer_match_t matchChannel, + uint8_t dutyCyclePercent, + uint32_t pwmFreq_Hz, + uint32_t srcClock_Hz, + bool enableInt) +{ + assert(pwmFreq_Hz > 0); + + uint32_t reg; + uint32_t period, pulsePeriod = 0; + uint32_t timerClock = srcClock_Hz / (base->PR + 1); + uint32_t index = CTIMER_GetInstance(base); + + if (matchChannel == kCTIMER_Match_3) + { + return kStatus_Fail; + } + + /* Enable PWM mode on the channel */ + base->PWMC |= (1U << matchChannel); + + /* Clear the stop, reset and interrupt bits for this channel */ + reg = base->MCR; + reg &= ~((CTIMER_MCR_MR0R_MASK | CTIMER_MCR_MR0S_MASK | CTIMER_MCR_MR0I_MASK) << (matchChannel * 3)); + + /* If call back function is valid then enable match interrupt for the channel */ + if (enableInt) + { + reg |= (CTIMER_MCR_MR0I_MASK << (CTIMER_MCR_MR0I_SHIFT + (matchChannel * 3))); + } + + /* Reset the counter when match on channel 3 */ + reg |= CTIMER_MCR_MR3R_MASK; + + base->MCR = reg; + + /* Calculate PWM period match value */ + period = (timerClock / pwmFreq_Hz) - 1; + + /* Calculate pulse width match value */ + if (dutyCyclePercent == 0) + { + pulsePeriod = period + 1; + } + else + { + pulsePeriod = (period * (100 - dutyCyclePercent)) / 100; + } + + /* Match on channel 3 will define the PWM period */ + base->MR[kCTIMER_Match_3] = period; + + /* This will define the PWM pulse period */ + base->MR[matchChannel] = pulsePeriod; + /* Clear status flags */ + CTIMER_ClearStatusFlags(base, CTIMER_IR_MR0INT_MASK << matchChannel); + /* If call back function is valid then enable interrupt and update the call back function */ + if (enableInt) + { + EnableIRQ(s_ctimerIRQ[index]); + } + + return kStatus_Success; +} + +/*! + * brief Configures the PWM signal parameters. + * + * Enables PWM mode on the match channel passed in and will then setup the match value + * and other match parameters to generate a PWM signal. + * This function will assign match channel 3 to set the PWM cycle. + * + * note When setting PWM output from multiple output pins, all should use the same PWM + * period + * + * param base Ctimer peripheral base address + * param matchChannel Match pin to be used to output the PWM signal + * param pwmPeriod PWM period match value + * param pulsePeriod Pulse width match value + * param enableInt Enable interrupt when the timer value reaches the match value of the PWM pulse, + * if it is 0 then no interrupt is generated + * + * return kStatus_Success on success + * kStatus_Fail If matchChannel passed in is 3; this channel is reserved to set the PWM period + */ +status_t CTIMER_SetupPwmPeriod( + CTIMER_Type *base, ctimer_match_t matchChannel, uint32_t pwmPeriod, uint32_t pulsePeriod, bool enableInt) +{ +/* Some CTimers only have 16bits , so the value is limited*/ +#if defined(FSL_FEATURE_SOC_CTIMER16B) && FSL_FEATURE_SOC_CTIMER16B + assert(!((FSL_FEATURE_CTIMER_BIT_SIZEn(base) < 32) && (pulsePeriod > 0xFFFFU))); +#endif + + uint32_t reg; + uint32_t index = CTIMER_GetInstance(base); + + if (matchChannel == kCTIMER_Match_3) + { + return kStatus_Fail; + } + + /* Enable PWM mode on the channel */ + base->PWMC |= (1U << matchChannel); + + /* Clear the stop, reset and interrupt bits for this channel */ + reg = base->MCR; + reg &= ~((CTIMER_MCR_MR0R_MASK | CTIMER_MCR_MR0S_MASK | CTIMER_MCR_MR0I_MASK) << (matchChannel * 3)); + + /* If call back function is valid then enable match interrupt for the channel */ + if (enableInt) + { + reg |= (CTIMER_MCR_MR0I_MASK << (CTIMER_MCR_MR0I_SHIFT + (matchChannel * 3))); + } + + /* Reset the counter when match on channel 3 */ + reg |= CTIMER_MCR_MR3R_MASK; + + base->MCR = reg; + + /* Match on channel 3 will define the PWM period */ + base->MR[kCTIMER_Match_3] = pwmPeriod; + + /* This will define the PWM pulse period */ + base->MR[matchChannel] = pulsePeriod; + /* Clear status flags */ + CTIMER_ClearStatusFlags(base, CTIMER_IR_MR0INT_MASK << matchChannel); + /* If call back function is valid then enable interrupt and update the call back function */ + if (enableInt) + { + EnableIRQ(s_ctimerIRQ[index]); + } + + return kStatus_Success; +} + +/*! + * brief Updates the duty cycle of an active PWM signal. + * + * note Please use CTIMER_UpdatePwmPulsePeriod to update the PWM with high resolution. + * + * param base Ctimer peripheral base address + * param matchChannel Match pin to be used to output the PWM signal + * param dutyCyclePercent New PWM pulse width; the value should be between 0 to 100 + */ +void CTIMER_UpdatePwmDutycycle(CTIMER_Type *base, ctimer_match_t matchChannel, uint8_t dutyCyclePercent) +{ + uint32_t pulsePeriod = 0, period; + + /* Match channel 3 defines the PWM period */ + period = base->MR[kCTIMER_Match_3]; + + /* Calculate pulse width match value */ + pulsePeriod = (period * dutyCyclePercent) / 100; + + /* For 0% dutycyle, make pulse period greater than period so the event will never occur */ + if (dutyCyclePercent == 0) + { + pulsePeriod = period + 1; + } + else + { + pulsePeriod = (period * (100 - dutyCyclePercent)) / 100; + } + + /* Update dutycycle */ + base->MR[matchChannel] = pulsePeriod; +} + +/*! + * brief Setup the match register. + * + * User configuration is used to setup the match value and action to be taken when a match occurs. + * + * param base Ctimer peripheral base address + * param matchChannel Match register to configure + * param config Pointer to the match configuration structure + */ +void CTIMER_SetupMatch(CTIMER_Type *base, ctimer_match_t matchChannel, const ctimer_match_config_t *config) +{ +/* Some CTimers only have 16bits , so the value is limited*/ +#if defined(FSL_FEATURE_SOC_CTIMER16B) && FSL_FEATURE_SOC_CTIMER16B + assert(!(FSL_FEATURE_CTIMER_BIT_SIZEn(base) < 32 && config->matchValue > 0xFFFFU)); +#endif + uint32_t reg; + uint32_t index = CTIMER_GetInstance(base); + + /* Set the counter operation when a match on this channel occurs */ + reg = base->MCR; + reg &= ~((CTIMER_MCR_MR0R_MASK | CTIMER_MCR_MR0S_MASK | CTIMER_MCR_MR0I_MASK) << (matchChannel * 3)); + reg |= (uint32_t)((uint32_t)(config->enableCounterReset) << (CTIMER_MCR_MR0R_SHIFT + (matchChannel * 3))); + reg |= (uint32_t)((uint32_t)(config->enableCounterStop) << (CTIMER_MCR_MR0S_SHIFT + (matchChannel * 3))); + reg |= (uint32_t)((uint32_t)(config->enableInterrupt) << (CTIMER_MCR_MR0I_SHIFT + (matchChannel * 3))); + base->MCR = reg; + + reg = base->EMR; + /* Set the match output operation when a match on this channel occurs */ + reg &= ~(CTIMER_EMR_EMC0_MASK << (matchChannel * 2)); + reg |= (uint32_t)config->outControl << (CTIMER_EMR_EMC0_SHIFT + (matchChannel * 2)); + + /* Set the initial state of the EM bit/output */ + reg &= ~(CTIMER_EMR_EM0_MASK << matchChannel); + reg |= (uint32_t)config->outPinInitState << matchChannel; + base->EMR = reg; + + /* Set the match value */ + base->MR[matchChannel] = config->matchValue; + /* Clear status flags */ + CTIMER_ClearStatusFlags(base, CTIMER_IR_MR0INT_MASK << matchChannel); + /* If interrupt is enabled then enable interrupt and update the call back function */ + if (config->enableInterrupt) + { + EnableIRQ(s_ctimerIRQ[index]); + } +} + +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) +/*! + * brief Setup the capture. + * + * param base Ctimer peripheral base address + * param capture Capture channel to configure + * param edge Edge on the channel that will trigger a capture + * param enableInt Flag to enable channel interrupts, if enabled then the registered call back + * is called upon capture + */ +void CTIMER_SetupCapture(CTIMER_Type *base, + ctimer_capture_channel_t capture, + ctimer_capture_edge_t edge, + bool enableInt) +{ + uint32_t reg = base->CCR; + uint32_t index = CTIMER_GetInstance(base); + + /* Set the capture edge */ + reg &= ~((CTIMER_CCR_CAP0RE_MASK | CTIMER_CCR_CAP0FE_MASK | CTIMER_CCR_CAP0I_MASK) << (capture * 3)); + reg |= (uint32_t)edge << (CTIMER_CCR_CAP0RE_SHIFT + (capture * 3)); + /* Clear status flags */ + CTIMER_ClearStatusFlags(base, (kCTIMER_Capture0Flag << capture)); + /* If call back function is valid then enable capture interrupt for the channel and update the call back function */ + if (enableInt) + { + reg |= CTIMER_CCR_CAP0I_MASK << (capture * 3); + EnableIRQ(s_ctimerIRQ[index]); + } + base->CCR = reg; +} +#endif + +/*! + * brief Register callback. + * + * param base Ctimer peripheral base address + * param cb_func callback function + * param cb_type callback function type, singular or multiple + */ +void CTIMER_RegisterCallBack(CTIMER_Type *base, ctimer_callback_t *cb_func, ctimer_callback_type_t cb_type) +{ + uint32_t index = CTIMER_GetInstance(base); + s_ctimerCallback[index] = cb_func; + ctimerCallbackType[index] = cb_type; +} + +void CTIMER_GenericIRQHandler(uint32_t index) +{ + uint32_t int_stat, i, mask; + /* Get Interrupt status flags */ + int_stat = CTIMER_GetStatusFlags(s_ctimerBases[index]); + /* Clear the status flags that were set */ + CTIMER_ClearStatusFlags(s_ctimerBases[index], int_stat); + if (ctimerCallbackType[index] == kCTIMER_SingleCallback) + { + if (s_ctimerCallback[index][0]) + { + s_ctimerCallback[index][0](int_stat); + } + } + else + { +#if defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE + for (i = 0; i <= CTIMER_IR_MR3INT_SHIFT; i++) +#else +#if defined(FSL_FEATURE_CTIMER_HAS_IR_CR3INT) && FSL_FEATURE_CTIMER_HAS_IR_CR3INT + for (i = 0; i <= CTIMER_IR_CR3INT_SHIFT; i++) +#else + for (i = 0; i <= CTIMER_IR_CR2INT_SHIFT; i++) +#endif /* FSL_FEATURE_CTIMER_HAS_IR_CR3INT */ +#endif + { + mask = 0x01 << i; + /* For each status flag bit that was set call the callback function if it is valid */ + if ((int_stat & mask) && (s_ctimerCallback[index][i])) + { + s_ctimerCallback[index][i](int_stat); + } + } + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +/* IRQ handler functions overloading weak symbols in the startup */ +#if defined(CTIMER0) +void CTIMER0_DriverIRQHandler(void) +{ + CTIMER_GenericIRQHandler(0); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(CTIMER1) +void CTIMER1_DriverIRQHandler(void) +{ + CTIMER_GenericIRQHandler(1); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(CTIMER2) +void CTIMER2_DriverIRQHandler(void) +{ + CTIMER_GenericIRQHandler(2); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(CTIMER3) +void CTIMER3_DriverIRQHandler(void) +{ + CTIMER_GenericIRQHandler(3); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(CTIMER4) +void CTIMER4_DriverIRQHandler(void) +{ + CTIMER_GenericIRQHandler(4); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_ctimer.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_ctimer.h new file mode 100644 index 000000000..8ae0d886a --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_ctimer.h @@ -0,0 +1,488 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_CTIMER_H_ +#define _FSL_CTIMER_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup ctimer + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_CTIMER_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) /*!< Version 2.0.2 */ +/*@}*/ + +/*! @brief List of Timer capture channels */ +typedef enum _ctimer_capture_channel +{ + kCTIMER_Capture_0 = 0U, /*!< Timer capture channel 0 */ + kCTIMER_Capture_1, /*!< Timer capture channel 1 */ + kCTIMER_Capture_2, /*!< Timer capture channel 2 */ +#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 + kCTIMER_Capture_3 /*!< Timer capture channel 3 */ +#endif /* FSL_FEATURE_CTIMER_HAS_IR_CR3INT */ +} ctimer_capture_channel_t; + +/*! @brief List of capture edge options */ +typedef enum _ctimer_capture_edge +{ + kCTIMER_Capture_RiseEdge = 1U, /*!< Capture on rising edge */ + kCTIMER_Capture_FallEdge = 2U, /*!< Capture on falling edge */ + kCTIMER_Capture_BothEdge = 3U, /*!< Capture on rising and falling edge */ +} ctimer_capture_edge_t; + +/*! @brief List of Timer match registers */ +typedef enum _ctimer_match +{ + kCTIMER_Match_0 = 0U, /*!< Timer match register 0 */ + kCTIMER_Match_1, /*!< Timer match register 1 */ + kCTIMER_Match_2, /*!< Timer match register 2 */ + kCTIMER_Match_3 /*!< Timer match register 3 */ +} ctimer_match_t; + +/*! @brief List of output control options */ +typedef enum _ctimer_match_output_control +{ + kCTIMER_Output_NoAction = 0U, /*!< No action is taken */ + kCTIMER_Output_Clear, /*!< Clear the EM bit/output to 0 */ + kCTIMER_Output_Set, /*!< Set the EM bit/output to 1 */ + kCTIMER_Output_Toggle /*!< Toggle the EM bit/output */ +} ctimer_match_output_control_t; + +/*! @brief List of Timer modes */ +typedef enum _ctimer_timer_mode +{ + kCTIMER_TimerMode = 0U, /* TC is incremented every rising APB bus clock edge */ + kCTIMER_IncreaseOnRiseEdge, /* TC is incremented on rising edge of input signal */ + kCTIMER_IncreaseOnFallEdge, /* TC is incremented on falling edge of input signal */ + kCTIMER_IncreaseOnBothEdge /* TC is incremented on both edges of input signal */ +} ctimer_timer_mode_t; + +/*! @brief List of Timer interrupts */ +typedef enum _ctimer_interrupt_enable +{ + kCTIMER_Match0InterruptEnable = CTIMER_MCR_MR0I_MASK, /*!< Match 0 interrupt */ + kCTIMER_Match1InterruptEnable = CTIMER_MCR_MR1I_MASK, /*!< Match 1 interrupt */ + kCTIMER_Match2InterruptEnable = CTIMER_MCR_MR2I_MASK, /*!< Match 2 interrupt */ + kCTIMER_Match3InterruptEnable = CTIMER_MCR_MR3I_MASK, /*!< Match 3 interrupt */ +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) + kCTIMER_Capture0InterruptEnable = CTIMER_CCR_CAP0I_MASK, /*!< Capture 0 interrupt */ + kCTIMER_Capture1InterruptEnable = CTIMER_CCR_CAP1I_MASK, /*!< Capture 1 interrupt */ + kCTIMER_Capture2InterruptEnable = CTIMER_CCR_CAP2I_MASK, /*!< Capture 2 interrupt */ +#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 + kCTIMER_Capture3InterruptEnable = CTIMER_CCR_CAP3I_MASK, /*!< Capture 3 interrupt */ +#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ +#endif +} ctimer_interrupt_enable_t; + +/*! @brief List of Timer flags */ +typedef enum _ctimer_status_flags +{ + kCTIMER_Match0Flag = CTIMER_IR_MR0INT_MASK, /*!< Match 0 interrupt flag */ + kCTIMER_Match1Flag = CTIMER_IR_MR1INT_MASK, /*!< Match 1 interrupt flag */ + kCTIMER_Match2Flag = CTIMER_IR_MR2INT_MASK, /*!< Match 2 interrupt flag */ + kCTIMER_Match3Flag = CTIMER_IR_MR3INT_MASK, /*!< Match 3 interrupt flag */ +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) + kCTIMER_Capture0Flag = CTIMER_IR_CR0INT_MASK, /*!< Capture 0 interrupt flag */ + kCTIMER_Capture1Flag = CTIMER_IR_CR1INT_MASK, /*!< Capture 1 interrupt flag */ + kCTIMER_Capture2Flag = CTIMER_IR_CR2INT_MASK, /*!< Capture 2 interrupt flag */ +#if defined(FSL_FEATURE_CTIMER_HAS_IR_CR3INT) && FSL_FEATURE_CTIMER_HAS_IR_CR3INT + kCTIMER_Capture3Flag = CTIMER_IR_CR3INT_MASK, /*!< Capture 3 interrupt flag */ +#endif /* FSL_FEATURE_CTIMER_HAS_IR_CR3INT */ +#endif +} ctimer_status_flags_t; + +typedef void (*ctimer_callback_t)(uint32_t flags); + +/*! @brief Callback type when registering for a callback. When registering a callback + * an array of function pointers is passed the size could be 1 or 8, the callback + * type will tell that. + */ +typedef enum +{ + kCTIMER_SingleCallback, /*!< Single Callback type where there is only one callback for the timer. + based on the status flags different channels needs to be handled differently */ + kCTIMER_MultipleCallback /*!< Multiple Callback type where there can be 8 valid callbacks, one per channel. + for both match/capture */ +} ctimer_callback_type_t; + +/*! + * @brief Match configuration + * + * This structure holds the configuration settings for each match register. + */ +typedef struct _ctimer_match_config +{ + uint32_t matchValue; /*!< This is stored in the match register */ + bool enableCounterReset; /*!< true: Match will reset the counter + false: Match will not reser the counter */ + bool enableCounterStop; /*!< true: Match will stop the counter + false: Match will not stop the counter */ + ctimer_match_output_control_t outControl; /*!< Action to be taken on a match on the EM bit/output */ + bool outPinInitState; /*!< Initial value of the EM bit/output */ + bool enableInterrupt; /*!< true: Generate interrupt upon match + false: Do not generate interrupt on match */ + +} ctimer_match_config_t; + +/*! + * @brief Timer configuration structure + * + * This structure holds the configuration settings for the Timer peripheral. To initialize this + * structure to reasonable defaults, call the CTIMER_GetDefaultConfig() function and pass a + * pointer to the configuration structure instance. + * + * The configuration structure can be made constant so as to reside in flash. + */ +typedef struct _ctimer_config +{ + ctimer_timer_mode_t mode; /*!< Timer mode */ + ctimer_capture_channel_t input; /*!< Input channel to increment the timer, used only in timer + modes that rely on this input signal to increment TC */ + uint32_t prescale; /*!< Prescale value */ +} ctimer_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Ungates the clock and configures the peripheral for basic operation. + * + * @note This API should be called at the beginning of the application before using the driver. + * + * @param base Ctimer peripheral base address + * @param config Pointer to the user configuration structure. + */ +void CTIMER_Init(CTIMER_Type *base, const ctimer_config_t *config); + +/*! + * @brief Gates the timer clock. + * + * @param base Ctimer peripheral base address + */ +void CTIMER_Deinit(CTIMER_Type *base); + +/*! + * @brief Fills in the timers configuration structure with the default settings. + * + * The default values are: + * @code + * config->mode = kCTIMER_TimerMode; + * config->input = kCTIMER_Capture_0; + * config->prescale = 0; + * @endcode + * @param config Pointer to the user configuration structure. + */ +void CTIMER_GetDefaultConfig(ctimer_config_t *config); + +/*! @}*/ + +/*! + * @name PWM setup operations + * @{ + */ + +/*! + * @brief Configures the PWM signal parameters. + * + * Enables PWM mode on the match channel passed in and will then setup the match value + * and other match parameters to generate a PWM signal. + * This function will assign match channel 3 to set the PWM cycle. + * + * @note When setting PWM output from multiple output pins, all should use the same PWM + * period + * + * @param base Ctimer peripheral base address + * @param matchChannel Match pin to be used to output the PWM signal + * @param pwmPeriod PWM period match value + * @param pulsePeriod Pulse width match value + * @param enableInt Enable interrupt when the timer value reaches the match value of the PWM pulse, + * if it is 0 then no interrupt is generated + * + * @return kStatus_Success on success + * kStatus_Fail If matchChannel passed in is 3; this channel is reserved to set the PWM period + */ +status_t CTIMER_SetupPwmPeriod( + CTIMER_Type *base, ctimer_match_t matchChannel, uint32_t pwmPeriod, uint32_t pulsePeriod, bool enableInt); + +/*! + * @brief Configures the PWM signal parameters. + * + * Enables PWM mode on the match channel passed in and will then setup the match value + * and other match parameters to generate a PWM signal. + * This function will assign match channel 3 to set the PWM cycle. + * + * @note When setting PWM output from multiple output pins, all should use the same PWM + * frequency. Please use CTIMER_SetupPwmPeriod to set up the PWM with high resolution. + * + * @param base Ctimer peripheral base address + * @param matchChannel Match pin to be used to output the PWM signal + * @param dutyCyclePercent PWM pulse width; the value should be between 0 to 100 + * @param pwmFreq_Hz PWM signal frequency in Hz + * @param srcClock_Hz Timer counter clock in Hz + * @param enableInt Enable interrupt when the timer value reaches the match value of the PWM pulse, + * if it is 0 then no interrupt is generated + * + * @return kStatus_Success on success + * kStatus_Fail If matchChannel passed in is 3; this channel is reserved to set the PWM cycle + */ +status_t CTIMER_SetupPwm(CTIMER_Type *base, + ctimer_match_t matchChannel, + uint8_t dutyCyclePercent, + uint32_t pwmFreq_Hz, + uint32_t srcClock_Hz, + bool enableInt); + +/*! + * @brief Updates the pulse period of an active PWM signal. + * + * @param base Ctimer peripheral base address + * @param matchChannel Match pin to be used to output the PWM signal + * @param pulsePeriod New PWM pulse width match value + */ +static inline void CTIMER_UpdatePwmPulsePeriod(CTIMER_Type *base, ctimer_match_t matchChannel, uint32_t pulsePeriod) +{ + /* Update PWM pulse period match value */ + base->MR[matchChannel] = pulsePeriod; +} + +/*! + * @brief Updates the duty cycle of an active PWM signal. + * + * @note Please use CTIMER_UpdatePwmPulsePeriod to update the PWM with high resolution. + * + * @param base Ctimer peripheral base address + * @param matchChannel Match pin to be used to output the PWM signal + * @param dutyCyclePercent New PWM pulse width; the value should be between 0 to 100 + */ +void CTIMER_UpdatePwmDutycycle(CTIMER_Type *base, ctimer_match_t matchChannel, uint8_t dutyCyclePercent); + +/*! @}*/ + +/*! + * @brief Setup the match register. + * + * User configuration is used to setup the match value and action to be taken when a match occurs. + * + * @param base Ctimer peripheral base address + * @param matchChannel Match register to configure + * @param config Pointer to the match configuration structure + */ +void CTIMER_SetupMatch(CTIMER_Type *base, ctimer_match_t matchChannel, const ctimer_match_config_t *config); + +/*! + * @brief Setup the capture. + * + * @param base Ctimer peripheral base address + * @param capture Capture channel to configure + * @param edge Edge on the channel that will trigger a capture + * @param enableInt Flag to enable channel interrupts, if enabled then the registered call back + * is called upon capture + */ +void CTIMER_SetupCapture(CTIMER_Type *base, + ctimer_capture_channel_t capture, + ctimer_capture_edge_t edge, + bool enableInt); + +/*! + * @brief Get the timer count value from TC register. + * + * @param base Ctimer peripheral base address. + * @return return the timer count value. + */ +static inline uint32_t CTIMER_GetTimerCountValue(CTIMER_Type *base) +{ + return (base->TC); +} + +/*! + * @brief Register callback. + * + * @param base Ctimer peripheral base address + * @param cb_func callback function + * @param cb_type callback function type, singular or multiple + */ +void CTIMER_RegisterCallBack(CTIMER_Type *base, ctimer_callback_t *cb_func, ctimer_callback_type_t cb_type); + +/*! + * @name Interrupt Interface + * @{ + */ + +/*! + * @brief Enables the selected Timer interrupts. + * + * @param base Ctimer peripheral base address + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::ctimer_interrupt_enable_t + */ +static inline void CTIMER_EnableInterrupts(CTIMER_Type *base, uint32_t mask) +{ + /* Enable match interrupts */ + base->MCR |= mask & (CTIMER_MCR_MR0I_MASK | CTIMER_MCR_MR1I_MASK | CTIMER_MCR_MR2I_MASK | CTIMER_MCR_MR3I_MASK); + +/* Enable capture interrupts */ +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) + base->CCR |= mask & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK | CTIMER_CCR_CAP2I_MASK +#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 + | CTIMER_CCR_CAP3I_MASK +#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ + ); +#endif +} + +/*! + * @brief Disables the selected Timer interrupts. + * + * @param base Ctimer peripheral base address + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::ctimer_interrupt_enable_t + */ +static inline void CTIMER_DisableInterrupts(CTIMER_Type *base, uint32_t mask) +{ + /* Disable match interrupts */ + base->MCR &= ~(mask & (CTIMER_MCR_MR0I_MASK | CTIMER_MCR_MR1I_MASK | CTIMER_MCR_MR2I_MASK | CTIMER_MCR_MR3I_MASK)); + +/* Disable capture interrupts */ +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) + base->CCR &= ~(mask & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK | CTIMER_CCR_CAP2I_MASK +#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 + | CTIMER_CCR_CAP3I_MASK +#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ + )); +#endif +} + +/*! + * @brief Gets the enabled Timer interrupts. + * + * @param base Ctimer peripheral base address + * + * @return The enabled interrupts. This is the logical OR of members of the + * enumeration ::ctimer_interrupt_enable_t + */ +static inline uint32_t CTIMER_GetEnabledInterrupts(CTIMER_Type *base) +{ + uint32_t enabledIntrs = 0; + + /* Get all the match interrupts enabled */ + enabledIntrs = + base->MCR & (CTIMER_MCR_MR0I_MASK | CTIMER_MCR_MR1I_MASK | CTIMER_MCR_MR2I_MASK | CTIMER_MCR_MR3I_MASK); + +/* Get all the capture interrupts enabled */ +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) + enabledIntrs |= base->CCR & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK | CTIMER_CCR_CAP2I_MASK +#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 + | CTIMER_CCR_CAP3I_MASK +#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ + ); +#endif + + return enabledIntrs; +} + +/*! @}*/ + +/*! + * @name Status Interface + * @{ + */ + +/*! + * @brief Gets the Timer status flags. + * + * @param base Ctimer peripheral base address + * + * @return The status flags. This is the logical OR of members of the + * enumeration ::ctimer_status_flags_t + */ +static inline uint32_t CTIMER_GetStatusFlags(CTIMER_Type *base) +{ + return base->IR; +} + +/*! + * @brief Clears the Timer status flags. + * + * @param base Ctimer peripheral base address + * @param mask The status flags to clear. This is a logical OR of members of the + * enumeration ::ctimer_status_flags_t + */ +static inline void CTIMER_ClearStatusFlags(CTIMER_Type *base, uint32_t mask) +{ + base->IR = mask; +} + +/*! @}*/ + +/*! + * @name Counter Start and Stop + * @{ + */ + +/*! + * @brief Starts the Timer counter. + * + * @param base Ctimer peripheral base address + */ +static inline void CTIMER_StartTimer(CTIMER_Type *base) +{ + base->TCR |= CTIMER_TCR_CEN_MASK; +} + +/*! + * @brief Stops the Timer counter. + * + * @param base Ctimer peripheral base address + */ +static inline void CTIMER_StopTimer(CTIMER_Type *base) +{ + base->TCR &= ~CTIMER_TCR_CEN_MASK; +} + +/*! @}*/ + +/*! + * @brief Reset the counter. + * + * The timer counter and prescale counter are reset on the next positive edge of the APB clock. + * + * @param base Ctimer peripheral base address + */ +static inline void CTIMER_Reset(CTIMER_Type *base) +{ + base->TCR |= CTIMER_TCR_CRST_MASK; + base->TCR &= ~CTIMER_TCR_CRST_MASK; +} + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_CTIMER_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_dma.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_dma.c new file mode 100644 index 000000000..e4b401336 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_dma.c @@ -0,0 +1,954 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_dma.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpc_dma" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Get instance number for DMA. + * + * @param base DMA peripheral base address. + */ +static uint32_t DMA_GetInstance(DMA_Type *base); + +/*! + * @brief Get virtual channel number. + * + * @param base DMA peripheral base address. + */ +static uint32_t DMA_GetVirtualStartChannel(DMA_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief Array to map DMA instance number to base pointer. */ +static DMA_Type *const s_dmaBases[] = DMA_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Array to map DMA instance number to clock name. */ +static const clock_ip_name_t s_dmaClockName[] = DMA_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_FEATURE_DMA_HAS_NO_RESET) && FSL_FEATURE_DMA_HAS_NO_RESET) +/*! @brief Pointers to DMA resets for each instance. */ +static const reset_ip_name_t s_dmaResets[] = DMA_RSTS_N; +#endif /*! @brief Array to map DMA instance number to IRQ number. */ +static const IRQn_Type s_dmaIRQNumber[] = DMA_IRQS; + +/*! @brief Pointers to transfer handle for each DMA channel. */ +static dma_handle_t *s_DMAHandle[FSL_FEATURE_DMA_ALL_CHANNELS]; +/*! @brief DMA driver internal descriptor table */ +DMA_ALLOCATE_HEAD_DESCRIPTORS(s_dma_descriptor_table0, FSL_FEATURE_DMA_MAX_CHANNELS); +#if defined(DMA1) +DMA_ALLOCATE_HEAD_DESCRIPTORS(s_dma_descriptor_table1, FSL_FEATURE_DMA_MAX_CHANNELS); +static dma_descriptor_t *s_dma_descriptor_table[] = {s_dma_descriptor_table0, s_dma_descriptor_table1}; +#else +static dma_descriptor_t *s_dma_descriptor_table[] = {s_dma_descriptor_table0}; +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ + +static uint32_t DMA_GetInstance(DMA_Type *base) +{ + int32_t instance; + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_dmaBases); instance++) + { + if (s_dmaBases[instance] == base) + { + break; + } + } + assert(instance < ARRAY_SIZE(s_dmaBases)); + + return instance; +} + +static uint32_t DMA_GetVirtualStartChannel(DMA_Type *base) +{ + uint32_t startChannel = 0, instance = 0; + uint32_t i = 0; + + instance = DMA_GetInstance(base); + + /* Compute start channel */ + for (i = 0; i < instance; i++) + { + startChannel += FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(s_dmaBases[i]); + } + + return startChannel; +} + +/*! + * brief Initializes DMA peripheral. + * + * This function enable the DMA clock, set descriptor table and + * enable DMA peripheral. + * + * param base DMA peripheral base address. + */ +void DMA_Init(DMA_Type *base) +{ + uint32_t instance = DMA_GetInstance(base); +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* enable dma clock gate */ + CLOCK_EnableClock(s_dmaClockName[DMA_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_FEATURE_DMA_HAS_NO_RESET) && FSL_FEATURE_DMA_HAS_NO_RESET) + /* Reset the DMA module */ + RESET_PeripheralReset(s_dmaResets[DMA_GetInstance(base)]); +#endif + /* set descriptor table */ + base->SRAMBASE = (uint32_t)s_dma_descriptor_table[instance]; + /* enable dma peripheral */ + base->CTRL |= DMA_CTRL_ENABLE_MASK; +} + +/*! + * brief Deinitializes DMA peripheral. + * + * This function gates the DMA clock. + * + * param base DMA peripheral base address. + */ +void DMA_Deinit(DMA_Type *base) +{ + /* Disable DMA peripheral */ + base->CTRL &= ~(DMA_CTRL_ENABLE_MASK); +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + CLOCK_DisableClock(s_dmaClockName[DMA_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Set trigger settings of DMA channel. + * deprecated Do not use this function. It has been superceded by @ref DMA_SetChannelConfig. + * + * param base DMA peripheral base address. + * param channel DMA channel number. + * param trigger trigger configuration. + */ +void DMA_ConfigureChannelTrigger(DMA_Type *base, uint32_t channel, dma_channel_trigger_t *trigger) +{ + assert((channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)) && (NULL != trigger)); + + uint32_t tmp = (DMA_CHANNEL_CFG_HWTRIGEN_MASK | DMA_CHANNEL_CFG_TRIGPOL_MASK | DMA_CHANNEL_CFG_TRIGTYPE_MASK | + DMA_CHANNEL_CFG_TRIGBURST_MASK | DMA_CHANNEL_CFG_BURSTPOWER_MASK | + DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK | DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK); + tmp = base->CHANNEL[channel].CFG & (~tmp); + tmp |= (uint32_t)(trigger->type) | (uint32_t)(trigger->burst) | (uint32_t)(trigger->wrap); + base->CHANNEL[channel].CFG = tmp; +} + +/*! + * brief Gets the remaining bytes of the current DMA descriptor transfer. + * + * param base DMA peripheral base address. + * param channel DMA channel number. + * return The number of bytes which have not been transferred yet. + */ +uint32_t DMA_GetRemainingBytes(DMA_Type *base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)); + + /* NOTE: when descriptors are chained, ACTIVE bit is set for whole chain. It makes + * impossible to distinguish between: + * - transfer finishes (represented by value '0x3FF') + * - and remaining 1024 bytes to transfer (value 0x3FF) + * for all descriptor in chain, except the last one. + * If you decide to use this function, please use 1023 transfers as maximal value */ + + /* Channel not active (transfer finished) and value is 0x3FF - nothing to transfer */ + if ((!DMA_ChannelIsActive(base, channel)) && + (0x3FF == ((base->CHANNEL[channel].XFERCFG & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) >> + DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT))) + { + return 0; + } + + return ((base->CHANNEL[channel].XFERCFG & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) >> + DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT) + + 1; +} + +/* Verify and convert dma_xfercfg_t to XFERCFG register */ +static void DMA_SetupXferCFG(dma_xfercfg_t *xfercfg, uint32_t *xfercfg_addr) +{ + assert(xfercfg != NULL); + /* check source increment */ + assert((xfercfg->srcInc <= kDMA_AddressInterleave4xWidth) && (xfercfg->dstInc <= kDMA_AddressInterleave4xWidth)); + /* check data width */ + assert(xfercfg->byteWidth <= kDMA_Transfer32BitWidth); + /* check transfer count */ + assert(xfercfg->transferCount <= DMA_MAX_TRANSFER_COUNT); + + uint32_t xfer = 0; + + /* set valid flag - descriptor is ready now */ + xfer |= DMA_CHANNEL_XFERCFG_CFGVALID(xfercfg->valid); + /* set reload - allow link to next descriptor */ + xfer |= DMA_CHANNEL_XFERCFG_RELOAD(xfercfg->reload); + /* set swtrig flag - start transfer */ + xfer |= DMA_CHANNEL_XFERCFG_SWTRIG(xfercfg->swtrig); + /* set transfer count */ + xfer |= DMA_CHANNEL_XFERCFG_CLRTRIG(xfercfg->clrtrig); + /* set INTA */ + xfer |= DMA_CHANNEL_XFERCFG_SETINTA(xfercfg->intA); + /* set INTB */ + xfer |= DMA_CHANNEL_XFERCFG_SETINTB(xfercfg->intB); + /* set data width */ + xfer |= DMA_CHANNEL_XFERCFG_WIDTH(xfercfg->byteWidth == 4 ? 2 : xfercfg->byteWidth - 1); + /* set source increment value */ + xfer |= DMA_CHANNEL_XFERCFG_SRCINC((xfercfg->srcInc == kDMA_AddressInterleave4xWidth) ? (xfercfg->srcInc - 1) : + xfercfg->srcInc); + /* set destination increment value */ + xfer |= DMA_CHANNEL_XFERCFG_DSTINC((xfercfg->dstInc == kDMA_AddressInterleave4xWidth) ? (xfercfg->dstInc - 1) : + xfercfg->dstInc); + /* set transfer count */ + xfer |= DMA_CHANNEL_XFERCFG_XFERCOUNT(xfercfg->transferCount - 1); + + /* store xferCFG */ + *xfercfg_addr = xfer; +} + +/*! + * brief setup dma descriptor + * Note: This function do not support configure wrap descriptor. + * param desc DMA descriptor address. + * param xfercfg Transfer configuration for DMA descriptor. + * param srcStartAddr Start address of source address. + * param dstStartAddr Start address of destination address. + * param nextDesc Address of next descriptor in chain. + */ +void DMA_SetupDescriptor( + dma_descriptor_t *desc, uint32_t xfercfg, void *srcStartAddr, void *dstStartAddr, void *nextDesc) +{ + assert(((uint32_t)nextDesc & (FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE - 1)) == 0U); + + uint32_t width = 0, srcInc = 0, dstInc = 0, transferCount = 0; + + width = (xfercfg & DMA_CHANNEL_XFERCFG_WIDTH_MASK) >> DMA_CHANNEL_XFERCFG_WIDTH_SHIFT; + srcInc = (xfercfg & DMA_CHANNEL_XFERCFG_SRCINC_MASK) >> DMA_CHANNEL_XFERCFG_SRCINC_SHIFT; + dstInc = (xfercfg & DMA_CHANNEL_XFERCFG_DSTINC_MASK) >> DMA_CHANNEL_XFERCFG_DSTINC_SHIFT; + transferCount = ((xfercfg & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) >> DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT) + 1U; + + /* covert register value to actual value */ + if (width == 2U) + { + width = kDMA_Transfer32BitWidth; + } + else + { + width += 1U; + } + + if (srcInc == 3U) + { + srcInc = kDMA_AddressInterleave4xWidth; + } + + if (dstInc == 3U) + { + dstInc = kDMA_AddressInterleave4xWidth; + } + + desc->xfercfg = xfercfg; + desc->srcEndAddr = DMA_DESCRIPTOR_END_ADDRESS(srcStartAddr, srcInc, transferCount * width, width); + desc->dstEndAddr = DMA_DESCRIPTOR_END_ADDRESS(dstStartAddr, dstInc, transferCount * width, width); + desc->linkToNextDesc = nextDesc; +} + +/*! + * brief setup dma channel descriptor + * Note: This function support configure wrap descriptor. + * param desc DMA descriptor address. + * param xfercfg Transfer configuration for DMA descriptor. + * param srcStartAddr Start address of source address. + * param dstStartAddr Start address of destination address. + * param nextDesc Address of next descriptor in chain. + * param wrapType burst wrap type. + * param burstSize burst size, reference _dma_burst_size. + */ +void DMA_SetupChannelDescriptor(dma_descriptor_t *desc, + uint32_t xfercfg, + void *srcStartAddr, + void *dstStartAddr, + void *nextDesc, + dma_burst_wrap_t wrapType, + uint32_t burstSize) +{ + assert(((uint32_t)nextDesc & (FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE - 1)) == 0U); + + uint32_t width = 0, srcInc = 0, dstInc = 0, transferCount = 0; + + width = (xfercfg & DMA_CHANNEL_XFERCFG_WIDTH_MASK) >> DMA_CHANNEL_XFERCFG_WIDTH_SHIFT; + srcInc = (xfercfg & DMA_CHANNEL_XFERCFG_SRCINC_MASK) >> DMA_CHANNEL_XFERCFG_SRCINC_SHIFT; + dstInc = (xfercfg & DMA_CHANNEL_XFERCFG_DSTINC_MASK) >> DMA_CHANNEL_XFERCFG_DSTINC_SHIFT; + transferCount = ((xfercfg & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) >> DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT) + 1U; + + /* covert register value to actual value */ + if (width == 2U) + { + width = kDMA_Transfer32BitWidth; + } + else + { + width += 1U; + } + + if (srcInc == 3U) + { + srcInc = kDMA_AddressInterleave4xWidth; + } + + if (dstInc == 3U) + { + dstInc = kDMA_AddressInterleave4xWidth; + } + + desc->xfercfg = xfercfg; + + if (wrapType == kDMA_NoWrap) + { + desc->srcEndAddr = DMA_DESCRIPTOR_END_ADDRESS(srcStartAddr, srcInc, transferCount * width, width); + desc->dstEndAddr = DMA_DESCRIPTOR_END_ADDRESS(dstStartAddr, dstInc, transferCount * width, width); + } + /* for the wrap transfer, the destination address should be determined by the burstSize/width/interleave size */ + if (wrapType == kDMA_SrcWrap) + { + desc->srcEndAddr = (void *)((uint32_t)srcStartAddr + ((1U << burstSize) - 1U) * width * srcInc); + desc->dstEndAddr = DMA_DESCRIPTOR_END_ADDRESS(dstStartAddr, dstInc, transferCount * width, width); + } + if (wrapType == kDMA_DstWrap) + { + desc->srcEndAddr = DMA_DESCRIPTOR_END_ADDRESS(srcStartAddr, srcInc, transferCount * width, width); + desc->dstEndAddr = (void *)((uint32_t)dstStartAddr + ((1U << burstSize) - 1U) * width * dstInc); + } + if (wrapType == kDMA_SrcAndDstWrap) + { + desc->srcEndAddr = (void *)((uint32_t)srcStartAddr + ((1U << burstSize) - 1U) * width * srcInc); + desc->dstEndAddr = (void *)((uint32_t)dstStartAddr + ((1U << burstSize) - 1U) * width * dstInc); + } + + desc->linkToNextDesc = nextDesc; +} + +/*! + * brief Create application specific DMA descriptor + * to be used in a chain in transfer + * deprecated Do not use this function. It has been superceded by @ref DMA_SetupDescriptor + * param desc DMA descriptor address. + * param xfercfg Transfer configuration for DMA descriptor. + * param srcAddr Address of last item to transmit + * param dstAddr Address of last item to receive. + * param nextDesc Address of next descriptor in chain. + */ +void DMA_CreateDescriptor(dma_descriptor_t *desc, dma_xfercfg_t *xfercfg, void *srcAddr, void *dstAddr, void *nextDesc) +{ + assert(((uint32_t)nextDesc & (FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE - 1)) == 0U); + assert((NULL != srcAddr) && (0 == (uint32_t)srcAddr % xfercfg->byteWidth)); + assert((NULL != dstAddr) && (0 == (uint32_t)dstAddr % xfercfg->byteWidth)); + + uint32_t xfercfg_reg = 0; + + DMA_SetupXferCFG(xfercfg, &xfercfg_reg); + + /* Set descriptor structure */ + DMA_SetupDescriptor(desc, xfercfg_reg, srcAddr, dstAddr, nextDesc); +} + +/*! + * brief Abort running transfer by handle. + * + * This function aborts DMA transfer specified by handle. + * + * param handle DMA handle pointer. + */ +void DMA_AbortTransfer(dma_handle_t *handle) +{ + assert(NULL != handle); + + DMA_DisableChannel(handle->base, handle->channel); + while (DMA_COMMON_CONST_REG_GET(handle->base, handle->channel, BUSY) & (1U << DMA_CHANNEL_INDEX(handle->channel))) + { + } + DMA_COMMON_REG_GET(handle->base, handle->channel, ABORT) |= 1U << DMA_CHANNEL_INDEX(handle->channel); + DMA_EnableChannel(handle->base, handle->channel); +} + +/*! + * brief Creates the DMA handle. + * + * This function is called if using transaction API for DMA. This function + * initializes the internal state of DMA handle. + * + * param handle DMA handle pointer. The DMA handle stores callback function and + * parameters. + * param base DMA peripheral base address. + * param channel DMA channel number. + */ +void DMA_CreateHandle(dma_handle_t *handle, DMA_Type *base, uint32_t channel) +{ + assert((NULL != handle) && (channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); + + int32_t dmaInstance; + uint32_t startChannel = 0; + /* base address is invalid DMA instance */ + dmaInstance = DMA_GetInstance(base); + startChannel = DMA_GetVirtualStartChannel(base); + + memset(handle, 0, sizeof(*handle)); + handle->base = base; + handle->channel = channel; + s_DMAHandle[startChannel + channel] = handle; + /* Enable NVIC interrupt */ + EnableIRQ(s_dmaIRQNumber[dmaInstance]); + /* Enable channel interrupt */ + DMA_EnableChannelInterrupts(handle->base, channel); +} + +/*! + * brief Installs a callback function for the DMA transfer. + * + * This callback is called in DMA IRQ handler. Use the callback to do something after + * the current major loop transfer completes. + * + * param handle DMA handle pointer. + * param callback DMA callback function pointer. + * param userData Parameter for callback function. + */ +void DMA_SetCallback(dma_handle_t *handle, dma_callback callback, void *userData) +{ + assert(handle != NULL); + + handle->callback = callback; + handle->userData = userData; +} + +/*! + * brief Prepares the DMA transfer structure. + * deprecated Do not use this function. It has been superceded by @ref DMA_PrepareChannelTransfer and + * DMA_PrepareChannelXfer. + * This function prepares the transfer configuration structure according to the user input. + * + * param config The user configuration structure of type dma_transfer_t. + * param srcAddr DMA transfer source address. + * param dstAddr DMA transfer destination address. + * param byteWidth DMA transfer destination address width(bytes). + * param transferBytes DMA transfer bytes to be transferred. + * param type DMA transfer type. + * param nextDesc Chain custom descriptor to transfer. + * note The data address and the data width must be consistent. For example, if the SRC + * is 4 bytes, so the source address must be 4 bytes aligned, or it shall result in + * source address error(SAE). + */ +void DMA_PrepareTransfer(dma_transfer_config_t *config, + void *srcAddr, + void *dstAddr, + uint32_t byteWidth, + uint32_t transferBytes, + dma_transfer_type_t type, + void *nextDesc) +{ + uint32_t xfer_count; + assert((NULL != config) && (NULL != srcAddr) && (NULL != dstAddr)); + assert((byteWidth == 1) || (byteWidth == 2) || (byteWidth == 4)); + assert(((uint32_t)nextDesc & (FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE - 1)) == 0U); + + /* check max */ + xfer_count = transferBytes / byteWidth; + assert((xfer_count <= DMA_MAX_TRANSFER_COUNT) && (0 == transferBytes % byteWidth)); + + memset(config, 0, sizeof(*config)); + switch (type) + { + case kDMA_MemoryToMemory: + config->xfercfg.srcInc = 1; + config->xfercfg.dstInc = 1; + config->isPeriph = false; + break; + case kDMA_PeripheralToMemory: + /* Peripheral register - source doesn't increment */ + config->xfercfg.srcInc = 0; + config->xfercfg.dstInc = 1; + config->isPeriph = true; + break; + case kDMA_MemoryToPeripheral: + /* Peripheral register - destination doesn't increment */ + config->xfercfg.srcInc = 1; + config->xfercfg.dstInc = 0; + config->isPeriph = true; + break; + case kDMA_StaticToStatic: + config->xfercfg.srcInc = 0; + config->xfercfg.dstInc = 0; + config->isPeriph = true; + break; + default: + return; + } + + config->dstAddr = (uint8_t *)dstAddr; + config->srcAddr = (uint8_t *)srcAddr; + config->nextDesc = (uint8_t *)nextDesc; + config->xfercfg.transferCount = xfer_count; + config->xfercfg.byteWidth = byteWidth; + config->xfercfg.intA = true; + config->xfercfg.reload = nextDesc != NULL; + config->xfercfg.valid = true; +} + +/*! + * brief set channel config. + * + * This function provide a interface to configure channel configuration reisters. + * + * param base DMA base address. + * param channel DMA channel number. + * param config channel configurations structure. + */ +void DMA_SetChannelConfig(DMA_Type *base, uint32_t channel, dma_channel_trigger_t *trigger, bool isPeriph) +{ + assert(channel <= FSL_FEATURE_DMA_MAX_CHANNELS); + + uint32_t tmp = DMA_CHANNEL_CFG_PERIPHREQEN_MASK; + + if (trigger != NULL) + { + tmp |= DMA_CHANNEL_CFG_HWTRIGEN_MASK | DMA_CHANNEL_CFG_TRIGPOL_MASK | DMA_CHANNEL_CFG_TRIGTYPE_MASK | + DMA_CHANNEL_CFG_TRIGBURST_MASK | DMA_CHANNEL_CFG_BURSTPOWER_MASK | DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK | + DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK; + } + + tmp = base->CHANNEL[channel].CFG & (~tmp); + + if (trigger != NULL) + { + tmp |= (uint32_t)(trigger->type) | (uint32_t)(trigger->burst) | (uint32_t)(trigger->wrap); + } + + tmp |= DMA_CHANNEL_CFG_PERIPHREQEN(isPeriph); + + base->CHANNEL[channel].CFG = tmp; +} + +/*! + * brief Prepare channel transfer configurations. + * + * This function used to prepare channel transfer configurations. + * + * param config Pointer to DMA channel transfer configuration structure. + * param srcStartAddr source start address. + * param dstStartAddr destination start address. + * param xferCfg xfer configuration, user can reference DMA_CHANNEL_XFER about to how to get xferCfg value. + * param type transfer type. + * param trigger DMA channel trigger configurations. + * param nextDesc address of next descriptor. + */ +void DMA_PrepareChannelTransfer(dma_channel_config_t *config, + void *srcStartAddr, + void *dstStartAddr, + uint32_t xferCfg, + dma_transfer_type_t type, + dma_channel_trigger_t *trigger, + void *nextDesc) +{ + assert((NULL != config) && (NULL != srcStartAddr) && (NULL != dstStartAddr)); + assert(((uint32_t)nextDesc & (FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE - 1)) == 0U); + + /* check max */ + memset(config, 0, sizeof(*config)); + + switch (type) + { + case kDMA_MemoryToMemory: + config->isPeriph = false; + break; + case kDMA_PeripheralToMemory: + config->isPeriph = true; + break; + case kDMA_MemoryToPeripheral: + config->isPeriph = true; + break; + case kDMA_StaticToStatic: + config->isPeriph = true; + break; + default: + return; + } + + config->dstStartAddr = (uint8_t *)dstStartAddr; + config->srcStartAddr = (uint8_t *)srcStartAddr; + config->nextDesc = (uint8_t *)nextDesc; + config->trigger = trigger; + config->xferCfg = xferCfg; +} + +/*! + * brief Install DMA descriptor memory. + * + * This function used to register DMA descriptor memory for linked transfer, a typical case is ping pong + * transfer which will request more than one DMA descriptor memory space, althrough current DMA driver has + * a default DMA descriptor buffer, but it support one DMA descriptor for one channel only. + * User should be take care about the address of DMA descriptor pool which required align with 512BYTE. + * + * param handle Pointer to DMA channel transfer handle. + * param addr DMA descriptor address + * param num DMA descriptor number. + */ +void DMA_InstallDescriptorMemory(DMA_Type *base, void *addr) +{ + assert(addr != NULL); + assert(((uint32_t)addr & (FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE - 1U)) == 0U); + + /* reconfigure the DMA descriptor base address */ + base->SRAMBASE = (uint32_t)addr; +} + +/*! + * brief Submit channel transfer paramter directly. + * + * This function used to configue channel head descriptor that is used to start DMA transfer, the head descriptor table + * is defined in DMA driver, it is useful for the case: + * 1. for the single transfer, application doesn't need to allocate descriptor table, the head descriptor can be used + for it. + * code + DMA_SetChannelConfig(base, channel, trigger, isPeriph); + DMA_CreateHandle(handle, base, channel) + DMA_SubmitChannelTransferParameter(handle, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, + bytes), srcStartAddr, dstStartAddr, NULL); + DMA_StartTransfer(handle) + * endcode + * + * 2. for the linked transfer, application should responsible for link descriptor, for example, if 4 transfer is + required, then application should prepare + * three descriptor table with macro , the head descriptor in driver can be used for the first transfer descriptor. + * code + //define link descriptor table in application with macro + DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc[3]); + + DMA_SetupDescriptor(nextDesc0, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), + srcStartAddr, dstStartAddr, nextDesc1); + DMA_SetupDescriptor(nextDesc1, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), + srcStartAddr, dstStartAddr, nextDesc2); + DMA_SetupDescriptor(nextDesc2, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), + srcStartAddr, dstStartAddr, NULL); + DMA_SetChannelConfig(base, channel, trigger, isPeriph); + DMA_CreateHandle(handle, base, channel) + DMA_SubmitChannelTransferParameter(handle, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, + bytes), srcStartAddr, dstStartAddr, nextDesc0); + DMA_StartTransfer(handle); + * endcode + * + * param handle Pointer to DMA handle. + * param xferCfg xfer configuration, user can reference DMA_CHANNEL_XFER about to how to get xferCfg value. + * param srcStartAddr source start address. + * param dstStartAddr destination start address. + * param nextDesc address of next descriptor. + */ +void DMA_SubmitChannelTransferParameter( + dma_handle_t *handle, uint32_t xfercfg, void *srcStartAddr, void *dstStartAddr, void *nextDesc) +{ + assert((NULL != srcStartAddr) && (NULL != dstStartAddr)); + assert(handle->channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base)); + + uint32_t instance = DMA_GetInstance(handle->base); + dma_descriptor_t *descriptor = (dma_descriptor_t *)(&s_dma_descriptor_table[instance][handle->channel]); + + DMA_SetupDescriptor(descriptor, xfercfg, srcStartAddr, dstStartAddr, nextDesc); + + /* Set channel XFERCFG register according first channel descriptor. */ + handle->base->CHANNEL[handle->channel].XFERCFG = xfercfg; +} + +/*! + * brief Submit channel descriptor. + * + * This function used to configue channel head descriptor that is used to start DMA transfer, the head descriptor table + is defined in + * DMA driver, this functiono is typical for the ping pong case: + * + * 1. for the ping pong case, application should responsible for the descriptor, for example, application should + * prepare two descriptor table with macro. + * code + //define link descriptor table in application with macro + DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc[2]); + + DMA_SetupDescriptor(nextDesc0, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), + srcStartAddr, dstStartAddr, nextDesc1); + DMA_SetupDescriptor(nextDesc1, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), + srcStartAddr, dstStartAddr, nextDesc0); + DMA_SetChannelConfig(base, channel, trigger, isPeriph); + DMA_CreateHandle(handle, base, channel) + DMA_SubmitChannelDescriptor(handle, nextDesc0); + DMA_StartTransfer(handle); + * endcode + * + * param handle Pointer to DMA handle. + * param descriptor descriptor to submit. + */ +void DMA_SubmitChannelDescriptor(dma_handle_t *handle, dma_descriptor_t *descriptor) +{ + assert((NULL != handle) && (NULL != descriptor)); + + uint32_t instance = DMA_GetInstance(handle->base); + dma_descriptor_t *channelDescriptor = (dma_descriptor_t *)(&s_dma_descriptor_table[instance][handle->channel]); + + channelDescriptor->xfercfg = descriptor->xfercfg; + channelDescriptor->srcEndAddr = descriptor->srcEndAddr; + channelDescriptor->dstEndAddr = descriptor->dstEndAddr; + channelDescriptor->linkToNextDesc = descriptor->linkToNextDesc; + + /* Set channel XFERCFG register according first channel descriptor. */ + handle->base->CHANNEL[handle->channel].XFERCFG = descriptor->xfercfg; +} + +/*! + * brief Submits the DMA channel transfer request. + * + * This function submits the DMA transfer request according to the transfer configuration structure. + * If the user submits the transfer request repeatedly, this function packs an unprocessed request as + * a TCD and enables scatter/gather feature to process it in the next time. + * It is used for the case: + * 1. for the single transfer, application doesn't need to allocate descriptor table, the head descriptor can be used + for it. + * code + DMA_CreateHandle(handle, base, channel) + DMA_PrepareChannelTransfer(config,srcStartAddr,dstStartAddr,xferCfg,type,trigger,NULL); + DMA_SubmitChannelTransfer(handle, config) + DMA_StartTransfer(handle) + * endcode + * + * 2. for the linked transfer, application should responsible for link descriptor, for example, if 4 transfer is + required, then application should prepare + * three descriptor table with macro , the head descriptor in driver can be used for the first transfer descriptor. + * code + //define link descriptor table in application with macro + DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc); + + DMA_SetupDescriptor(nextDesc0, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), + srcStartAddr, dstStartAddr, nextDesc1); + DMA_SetupDescriptor(nextDesc1, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), + srcStartAddr, dstStartAddr, nextDesc2); + DMA_SetupDescriptor(nextDesc2, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), + srcStartAddr, dstStartAddr, NULL); + DMA_CreateHandle(handle, base, channel) + DMA_PrepareChannelTransfer(config,srcStartAddr,dstStartAddr,xferCfg,type,trigger,nextDesc0); + DMA_SubmitChannelTransfer(handle, config) + DMA_StartTransfer(handle) + * endcode + * + * 3. for the ping pong case, application should responsible for link descriptor, for example, application should + prepare + * two descriptor table with macro , the head descriptor in driver can be used for the first transfer descriptor. + * code + //define link descriptor table in application with macro + DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc); + + DMA_SetupDescriptor(nextDesc0, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), + srcStartAddr, dstStartAddr, nextDesc1); + DMA_SetupDescriptor(nextDesc1, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), + srcStartAddr, dstStartAddr, nextDesc0); + DMA_CreateHandle(handle, base, channel) + DMA_PrepareChannelTransfer(config,srcStartAddr,dstStartAddr,xferCfg,type,trigger,nextDesc0); + DMA_SubmitChannelTransfer(handle, config) + DMA_StartTransfer(handle) + * endcode + * param handle DMA handle pointer. + * param config Pointer to DMA transfer configuration structure. + * retval kStatus_DMA_Success It means submit transfer request succeed. + * retval kStatus_DMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed. + * retval kStatus_DMA_Busy It means the given channel is busy, need to submit request later. + */ +status_t DMA_SubmitChannelTransfer(dma_handle_t *handle, dma_channel_config_t *config) +{ + assert((NULL != handle) && (NULL != config)); + assert(handle->channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base)); + uint32_t instance = DMA_GetInstance(handle->base); + dma_descriptor_t *descriptor = (dma_descriptor_t *)(&s_dma_descriptor_table[instance][handle->channel]); + + /* Previous transfer has not finished */ + if (DMA_ChannelIsActive(handle->base, handle->channel)) + { + return kStatus_DMA_Busy; + } + + /* setup channgel trigger configurations */ + DMA_SetChannelConfig(handle->base, handle->channel, config->trigger, config->isPeriph); + + DMA_SetupChannelDescriptor( + descriptor, config->xferCfg, config->srcStartAddr, config->dstStartAddr, config->nextDesc, + config->trigger == NULL ? kDMA_NoWrap : config->trigger->wrap, + (config->trigger == NULL ? + kDMA_BurstSize1 : + (config->trigger->burst & (DMA_CHANNEL_CFG_BURSTPOWER_MASK)) >> DMA_CHANNEL_CFG_BURSTPOWER_SHIFT)); + + /* Set channel XFERCFG register according first channel descriptor. */ + handle->base->CHANNEL[handle->channel].XFERCFG = config->xferCfg; + + return kStatus_Success; +} + +/*! + * brief Submits the DMA transfer request. + * deprecated Do not use this function. It has been superceded by @ref DMA_SubmitChannelTransfer. + * + * This function submits the DMA transfer request according to the transfer configuration structure. + * If the user submits the transfer request repeatedly, this function packs an unprocessed request as + * a TCD and enables scatter/gather feature to process it in the next time. + * + * param handle DMA handle pointer. + * param config Pointer to DMA transfer configuration structure. + * retval kStatus_DMA_Success It means submit transfer request succeed. + * retval kStatus_DMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed. + * retval kStatus_DMA_Busy It means the given channel is busy, need to submit request later. + */ +status_t DMA_SubmitTransfer(dma_handle_t *handle, dma_transfer_config_t *config) +{ + assert((NULL != handle) && (NULL != config)); + assert(handle->channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base)); + + uint32_t instance = DMA_GetInstance(handle->base); + dma_descriptor_t *descriptor = (dma_descriptor_t *)(&s_dma_descriptor_table[instance][handle->channel]); + + /* Previous transfer has not finished */ + if (DMA_ChannelIsActive(handle->base, handle->channel)) + { + return kStatus_DMA_Busy; + } + + /* enable/disable peripheral request */ + if (config->isPeriph) + { + DMA_EnableChannelPeriphRq(handle->base, handle->channel); + } + else + { + DMA_DisableChannelPeriphRq(handle->base, handle->channel); + } + + DMA_CreateDescriptor(descriptor, &config->xfercfg, config->srcAddr, config->dstAddr, config->nextDesc); + /* Set channel XFERCFG register according first channel descriptor. */ + handle->base->CHANNEL[handle->channel].XFERCFG = descriptor->xfercfg; + + return kStatus_Success; +} + +/*! + * brief DMA start transfer. + * + * This function enables the channel request. User can call this function after submitting the transfer request + * It will trigger transfer start with software trigger only when hardware trigger is not used. + * + * param handle DMA handle pointer. + */ +void DMA_StartTransfer(dma_handle_t *handle) +{ + assert(NULL != handle); + + uint32_t channel = handle->channel; + assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base)); + + /* enable channel */ + DMA_EnableChannel(handle->base, channel); + + /* Do software trigger only when HW trigger is not enabled. */ + if ((handle->base->CHANNEL[handle->channel].CFG & DMA_CHANNEL_CFG_HWTRIGEN_MASK) == 0U) + { + handle->base->CHANNEL[channel].XFERCFG |= DMA_CHANNEL_XFERCFG_SWTRIG_MASK; + } +} + +void DMA_IRQHandle(DMA_Type *base) +{ + dma_handle_t *handle; + int32_t channel_index; + uint32_t startChannel = DMA_GetVirtualStartChannel(base); + uint32_t i = 0; + + /* Find channels that have completed transfer */ + for (i = 0; i < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base); i++) + { + handle = s_DMAHandle[i + startChannel]; + /* Handle is not present */ + if (NULL == handle) + { + continue; + } + channel_index = DMA_CHANNEL_INDEX(handle->channel); + /* Channel uses INTA flag */ + if (DMA_COMMON_REG_GET(handle->base, handle->channel, INTA) & (1U << channel_index)) + { + /* Clear INTA flag */ + DMA_COMMON_REG_SET(handle->base, handle->channel, INTA, (1U << channel_index)); + if (handle->callback) + { + (handle->callback)(handle, handle->userData, true, kDMA_IntA); + } + } + /* Channel uses INTB flag */ + if (DMA_COMMON_REG_GET(handle->base, handle->channel, INTB) & (1U << channel_index)) + { + /* Clear INTB flag */ + DMA_COMMON_REG_SET(handle->base, handle->channel, INTB, (1U << channel_index)); + if (handle->callback) + { + (handle->callback)(handle, handle->userData, true, kDMA_IntB); + } + } + /* Error flag */ + if (DMA_COMMON_REG_GET(handle->base, handle->channel, ERRINT) & (1U << channel_index)) + { + /* Clear error flag */ + DMA_COMMON_REG_SET(handle->base, handle->channel, ERRINT, (1U << channel_index)); + if (handle->callback) + { + (handle->callback)(handle, handle->userData, false, kDMA_IntError); + } + } + } +} + +void DMA0_DriverIRQHandler(void) +{ + DMA_IRQHandle(DMA0); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +#if defined(DMA1) +void DMA1_DriverIRQHandler(void) +{ + DMA_IRQHandle(DMA1); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_dma.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_dma.h new file mode 100644 index 000000000..db1da29fa --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_dma.h @@ -0,0 +1,823 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_DMA_H_ +#define _FSL_DMA_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup dma + * @{ + */ + +/*! @file */ +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief DMA driver version */ +#define FSL_DMA_DRIVER_VERSION (MAKE_VERSION(2, 3, 0)) /*!< Version 2.3.0. */ +/*@}*/ + +/*! @brief DMA max transfer size */ +#define DMA_MAX_TRANSFER_COUNT 0x400 +/*! @brief DMA channel numbers */ +#if defined FSL_FEATURE_DMA_NUMBER_OF_CHANNELS +#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(x) FSL_FEATURE_DMA_NUMBER_OF_CHANNELS +#define FSL_FEATURE_DMA_MAX_CHANNELS FSL_FEATURE_DMA_NUMBER_OF_CHANNELS +#define FSL_FEATURE_DMA_ALL_CHANNELS (FSL_FEATURE_DMA_NUMBER_OF_CHANNELS * FSL_FEATURE_SOC_DMA_COUNT) +#endif +/*! @brief DMA head link descriptor table align size */ +#define FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE (16U) +/*! @brief DMA head descriptor table allocate macro + * To simplify user interface, this macro will help allocate descriptor memory, + * user just need to provide the name and the number for the allocate descriptor. + * + * @param name, allocate decriptor name. + * @param number, number of descriptor to be allocated. + */ +#define DMA_ALLOCATE_HEAD_DESCRIPTORS(name, number) \ + SDK_ALIGN(dma_descriptor_t name[number], FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE) +/*! @brief DMA link descriptor table allocate macro + * To simplify user interface, this macro will help allocate descriptor memory, + * user just need to provide the name and the number for the allocate descriptor. + * + * @param name, allocate decriptor name. + * @param number, number of descriptor to be allocated. + */ +#define DMA_ALLOCATE_LINK_DESCRIPTORS(name, number) \ + SDK_ALIGN(dma_descriptor_t name[number], FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE) + +/* Channel group consists of 32 channels. channel_group = (channel / 32) */ +#define DMA_CHANNEL_GROUP(channel) (((uint8_t)(channel)) >> 5U) +/* Channel index in channel group. channel_index = (channel % 32) */ +#define DMA_CHANNEL_INDEX(channel) (((uint8_t)(channel)) & 0x1F) +/*! @brief DMA linked descriptor address algin size */ +#define DMA_COMMON_REG_GET(base, channel, reg) \ + (((volatile uint32_t *)(&((base)->COMMON[0].reg)))[DMA_CHANNEL_GROUP(channel)]) +#define DMA_COMMON_CONST_REG_GET(base, channel, reg) \ + (((volatile const uint32_t *)(&((base)->COMMON[0].reg)))[DMA_CHANNEL_GROUP(channel)]) +#define DMA_COMMON_REG_SET(base, channel, reg, value) \ + (((volatile uint32_t *)(&((base)->COMMON[0].reg)))[DMA_CHANNEL_GROUP(channel)] = (value)) + +/*! @brief DMA descriptor end address calculate + * @param start, start address + * @param inc, address interleave size + * @param bytes, transfer bytes + * @param width, transfer width + */ +#define DMA_DESCRIPTOR_END_ADDRESS(start, inc, bytes, width) ((void *)((uint32_t)(start) + inc * bytes - inc * width)) + +/*! @brief DMA channel transfer configurations macro + * @param reload, true is reload link descriptor after current exhaust, false is not + * @param clrTrig, true is clear trigger status, wait software trigger, false is not + * @param intA, enable interruptA + * @param intB, enable interruptB + * @param width,transfer width + * @param srcInc, source address interleave size + * @param dstInc, destination address interleave size + * @param bytes, transfer bytes + */ +#define DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes) \ + DMA_CHANNEL_XFERCFG_CFGVALID_MASK | DMA_CHANNEL_XFERCFG_RELOAD(reload) | DMA_CHANNEL_XFERCFG_CLRTRIG(clrTrig) | \ + DMA_CHANNEL_XFERCFG_SETINTA(intA) | DMA_CHANNEL_XFERCFG_SETINTB(intB) | \ + DMA_CHANNEL_XFERCFG_WIDTH(width == 4 ? 2 : (width - 1)) | \ + DMA_CHANNEL_XFERCFG_SRCINC(srcInc == 4 ? (srcInc - 1) : srcInc) | \ + DMA_CHANNEL_XFERCFG_DSTINC(dstInc == 4 ? (dstInc - 1) : dstInc) | \ + DMA_CHANNEL_XFERCFG_XFERCOUNT(bytes / width - 1) + +/*! @brief DMA transfer status */ +enum _dma_transfer_status +{ + kStatus_DMA_Busy = MAKE_STATUS(kStatusGroup_DMA, 0), /*!< Channel is busy and can't handle the + transfer request. */ +}; + +/*! @brief dma address interleave size */ +enum _dma_addr_interleave_size +{ + kDMA_AddressInterleave0xWidth = 0U, /*!< dma source/destination address no interleave */ + kDMA_AddressInterleave1xWidth = 1U, /*!< dma source/destination address interleave 1xwidth */ + kDMA_AddressInterleave2xWidth = 2U, /*!< dma source/destination address interleave 2xwidth */ + kDMA_AddressInterleave4xWidth = 4U, /*!< dma source/destination address interleave 3xwidth */ +}; + +/*! @brief dma transfer width */ +enum _dma_transfer_width +{ + kDMA_Transfer8BitWidth = 1U, /*!< dma channel transfer bit width is 8 bit */ + kDMA_Transfer16BitWidth = 2U, /*!< dma channel transfer bit width is 16 bit */ + kDMA_Transfer32BitWidth = 4U, /*!< dma channel transfer bit width is 32 bit */ +}; + +/*! @brief DMA descriptor structure */ +typedef struct _dma_descriptor +{ + volatile uint32_t xfercfg; /*!< Transfer configuration */ + void *srcEndAddr; /*!< Last source address of DMA transfer */ + void *dstEndAddr; /*!< Last destination address of DMA transfer */ + void *linkToNextDesc; /*!< Address of next DMA descriptor in chain */ +} dma_descriptor_t; + +/*! @brief DMA transfer configuration */ +typedef struct _dma_xfercfg +{ + bool valid; /*!< Descriptor is ready to transfer */ + bool reload; /*!< Reload channel configuration register after + current descriptor is exhausted */ + bool swtrig; /*!< Perform software trigger. Transfer if fired + when 'valid' is set */ + bool clrtrig; /*!< Clear trigger */ + bool intA; /*!< Raises IRQ when transfer is done and set IRQA status register flag */ + bool intB; /*!< Raises IRQ when transfer is done and set IRQB status register flag */ + uint8_t byteWidth; /*!< Byte width of data to transfer */ + uint8_t srcInc; /*!< Increment source address by 'srcInc' x 'byteWidth' */ + uint8_t dstInc; /*!< Increment destination address by 'dstInc' x 'byteWidth' */ + uint16_t transferCount; /*!< Number of transfers */ +} dma_xfercfg_t; + +/*! @brief DMA channel priority */ +typedef enum _dma_priority +{ + kDMA_ChannelPriority0 = 0, /*!< Highest channel priority - priority 0 */ + kDMA_ChannelPriority1, /*!< Channel priority 1 */ + kDMA_ChannelPriority2, /*!< Channel priority 2 */ + kDMA_ChannelPriority3, /*!< Channel priority 3 */ + kDMA_ChannelPriority4, /*!< Channel priority 4 */ + kDMA_ChannelPriority5, /*!< Channel priority 5 */ + kDMA_ChannelPriority6, /*!< Channel priority 6 */ + kDMA_ChannelPriority7, /*!< Lowest channel priority - priority 7 */ +} dma_priority_t; + +/*! @brief DMA interrupt flags */ +typedef enum _dma_int +{ + kDMA_IntA, /*!< DMA interrupt flag A */ + kDMA_IntB, /*!< DMA interrupt flag B */ + kDMA_IntError, /*!< DMA interrupt flag error */ +} dma_irq_t; + +/*! @brief DMA trigger type*/ +typedef enum _dma_trigger_type +{ + kDMA_NoTrigger = 0, /*!< Trigger is disabled */ + kDMA_LowLevelTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1) | DMA_CHANNEL_CFG_TRIGTYPE(1), /*!< Low level active trigger */ + kDMA_HighLevelTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1) | DMA_CHANNEL_CFG_TRIGTYPE(1) | + DMA_CHANNEL_CFG_TRIGPOL(1), /*!< High level active trigger */ + kDMA_FallingEdgeTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1), /*!< Falling edge active trigger */ + kDMA_RisingEdgeTrigger = + DMA_CHANNEL_CFG_HWTRIGEN(1) | DMA_CHANNEL_CFG_TRIGPOL(1), /*!< Rising edge active trigger */ +} dma_trigger_type_t; + +/*! @brief DMA burst size*/ +enum _dma_burst_size +{ + kDMA_BurstSize1 = 0U, /*!< burst size 1 transfer */ + kDMA_BurstSize2 = 1U, /*!< burst size 2 transfer */ + kDMA_BurstSize4 = 2U, /*!< burst size 4 transfer */ + kDMA_BurstSize8 = 3U, /*!< burst size 8 transfer */ + kDMA_BurstSize16 = 4U, /*!< burst size 16 transfer */ + kDMA_BurstSize32 = 5U, /*!< burst size 32 transfer */ + kDMA_BurstSize64 = 6U, /*!< burst size 64 transfer */ + kDMA_BurstSize128 = 7U, /*!< burst size 128 transfer */ + kDMA_BurstSize256 = 8U, /*!< burst size 256 transfer */ + kDMA_BurstSize512 = 9U, /*!< burst size 512 transfer */ + kDMA_BurstSize1024 = 10U, /*!< burst size 1024 transfer */ +}; + +/*! @brief DMA trigger burst */ +typedef enum _dma_trigger_burst +{ + kDMA_SingleTransfer = 0, /*!< Single transfer */ + kDMA_LevelBurstTransfer = DMA_CHANNEL_CFG_TRIGBURST(1), /*!< Burst transfer driven by level trigger */ + kDMA_EdgeBurstTransfer1 = DMA_CHANNEL_CFG_TRIGBURST(1), /*!< Perform 1 transfer by edge trigger */ + kDMA_EdgeBurstTransfer2 = + DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(1), /*!< Perform 2 transfers by edge trigger */ + kDMA_EdgeBurstTransfer4 = + DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(2), /*!< Perform 4 transfers by edge trigger */ + kDMA_EdgeBurstTransfer8 = + DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(3), /*!< Perform 8 transfers by edge trigger */ + kDMA_EdgeBurstTransfer16 = + DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(4), /*!< Perform 16 transfers by edge trigger */ + kDMA_EdgeBurstTransfer32 = + DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(5), /*!< Perform 32 transfers by edge trigger */ + kDMA_EdgeBurstTransfer64 = + DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(6), /*!< Perform 64 transfers by edge trigger */ + kDMA_EdgeBurstTransfer128 = + DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(7), /*!< Perform 128 transfers by edge trigger */ + kDMA_EdgeBurstTransfer256 = + DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(8), /*!< Perform 256 transfers by edge trigger */ + kDMA_EdgeBurstTransfer512 = + DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(9), /*!< Perform 512 transfers by edge trigger */ + kDMA_EdgeBurstTransfer1024 = + DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(10), /*!< Perform 1024 transfers by edge trigger */ +} dma_trigger_burst_t; + +/*! @brief DMA burst wrapping */ +typedef enum _dma_burst_wrap +{ + kDMA_NoWrap = 0, /*!< Wrapping is disabled */ + kDMA_SrcWrap = DMA_CHANNEL_CFG_SRCBURSTWRAP(1), /*!< Wrapping is enabled for source */ + kDMA_DstWrap = DMA_CHANNEL_CFG_DSTBURSTWRAP(1), /*!< Wrapping is enabled for destination */ + kDMA_SrcAndDstWrap = DMA_CHANNEL_CFG_SRCBURSTWRAP(1) | + DMA_CHANNEL_CFG_DSTBURSTWRAP(1), /*!< Wrapping is enabled for source and destination */ +} dma_burst_wrap_t; + +/*! @brief DMA transfer type */ +typedef enum _dma_transfer_type +{ + kDMA_MemoryToMemory = 0x0U, /*!< Transfer from memory to memory (increment source and destination) */ + kDMA_PeripheralToMemory, /*!< Transfer from peripheral to memory (increment only destination) */ + kDMA_MemoryToPeripheral, /*!< Transfer from memory to peripheral (increment only source)*/ + kDMA_StaticToStatic, /*!< Peripheral to static memory (do not increment source or destination) */ +} dma_transfer_type_t; + +/*! @brief DMA channel trigger */ +typedef struct _dma_channel_trigger +{ + dma_trigger_type_t type; /*!< Select hardware trigger as edge triggered or level triggered. */ + dma_trigger_burst_t burst; /*!< Select whether hardware triggers cause a single or burst transfer. */ + dma_burst_wrap_t wrap; /*!< Select wrap type, source wrap or dest wrap, or both. */ +} dma_channel_trigger_t; + +/*! @brief DMA channel trigger */ +typedef struct _dma_channel_config +{ + void *srcStartAddr; /*!< Source data address */ + void *dstStartAddr; /*!< Destination data address */ + void *nextDesc; /*!< Chain custom descriptor */ + uint32_t xferCfg; /*!< channel transfer configurations */ + dma_channel_trigger_t *trigger; /*!< DMA trigger type */ + bool isPeriph; /*!< select the request type */ +} dma_channel_config_t; + +/*! @brief DMA transfer configuration */ +typedef struct _dma_transfer_config +{ + uint8_t *srcAddr; /*!< Source data address */ + uint8_t *dstAddr; /*!< Destination data address */ + uint8_t *nextDesc; /*!< Chain custom descriptor */ + dma_xfercfg_t xfercfg; /*!< Transfer options */ + bool isPeriph; /*!< DMA transfer is driven by peripheral */ +} dma_transfer_config_t; + +/*! @brief Callback for DMA */ +struct _dma_handle; + +/*! @brief Define Callback function for DMA. */ +typedef void (*dma_callback)(struct _dma_handle *handle, void *userData, bool transferDone, uint32_t intmode); + +/*! @brief DMA transfer handle structure */ +typedef struct _dma_handle +{ + dma_callback callback; /*!< Callback function. Invoked when transfer + of descriptor with interrupt flag finishes */ + void *userData; /*!< Callback function parameter */ + DMA_Type *base; /*!< DMA peripheral base address */ + uint8_t channel; /*!< DMA channel number */ +} dma_handle_t; + +/******************************************************************************* + * APIs + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @name DMA initialization and De-initialization + * @{ + */ + +/*! + * @brief Initializes DMA peripheral. + * + * This function enable the DMA clock, set descriptor table and + * enable DMA peripheral. + * + * @param base DMA peripheral base address. + */ +void DMA_Init(DMA_Type *base); + +/*! + * @brief Deinitializes DMA peripheral. + * + * This function gates the DMA clock. + * + * @param base DMA peripheral base address. + */ +void DMA_Deinit(DMA_Type *base); + +/*! + * @brief Install DMA descriptor memory. + * + * This function used to register DMA descriptor memory for linked transfer, a typical case is ping pong + * transfer which will request more than one DMA descriptor memory space, althrough current DMA driver has + * a default DMA descriptor buffer, but it support one DMA descriptor for one channel only. + * + * @param base DMA base address. + * @param addr DMA descriptor address + */ +void DMA_InstallDescriptorMemory(DMA_Type *base, void *addr); + +/* @} */ +/*! + * @name DMA Channel Operation + * @{ + */ + +/*! + * @brief Return whether DMA channel is processing transfer + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + * @return True for active state, false otherwise. + */ +static inline bool DMA_ChannelIsActive(DMA_Type *base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)); + return (DMA_COMMON_CONST_REG_GET(base, channel, ACTIVE) & (1U << DMA_CHANNEL_INDEX(channel))) ? true : false; +} + +/*! + * @brief Enables the interrupt source for the DMA transfer. + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + */ +static inline void DMA_EnableChannelInterrupts(DMA_Type *base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)); + DMA_COMMON_REG_GET(base, channel, INTENSET) |= 1U << DMA_CHANNEL_INDEX(channel); +} + +/*! + * @brief Disables the interrupt source for the DMA transfer. + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + */ +static inline void DMA_DisableChannelInterrupts(DMA_Type *base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)); + DMA_COMMON_REG_GET(base, channel, INTENCLR) |= 1U << DMA_CHANNEL_INDEX(channel); +} + +/*! + * @brief Enable DMA channel. + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + */ +static inline void DMA_EnableChannel(DMA_Type *base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)); + DMA_COMMON_REG_GET(base, channel, ENABLESET) |= 1U << DMA_CHANNEL_INDEX(channel); +} + +/*! + * @brief Disable DMA channel. + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + */ +static inline void DMA_DisableChannel(DMA_Type *base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)); + DMA_COMMON_REG_GET(base, channel, ENABLECLR) |= 1U << DMA_CHANNEL_INDEX(channel); +} + +/*! + * @brief Set PERIPHREQEN of channel configuration register. + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + */ +static inline void DMA_EnableChannelPeriphRq(DMA_Type *base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)); + base->CHANNEL[channel].CFG |= DMA_CHANNEL_CFG_PERIPHREQEN_MASK; +} + +/*! + * @brief Get PERIPHREQEN value of channel configuration register. + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + * @return True for enabled PeriphRq, false for disabled. + */ +static inline void DMA_DisableChannelPeriphRq(DMA_Type *base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)); + base->CHANNEL[channel].CFG &= ~DMA_CHANNEL_CFG_PERIPHREQEN_MASK; +} + +/*! + * @brief Set trigger settings of DMA channel. + * @deprecated Do not use this function. It has been superceded by @ref DMA_SetChannelConfig. + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + * @param trigger trigger configuration. + */ +void DMA_ConfigureChannelTrigger(DMA_Type *base, uint32_t channel, dma_channel_trigger_t *trigger); + +/*! + * @brief set channel config. + * + * This function provide a interface to configure channel configuration reisters. + * + * @param base DMA base address. + * @param channel DMA channel number. + * @param trigger channel configurations structure. + * @param isPeriph true is periph request, false is not. + */ +void DMA_SetChannelConfig(DMA_Type *base, uint32_t channel, dma_channel_trigger_t *trigger, bool isPeriph); + +/*! + * @brief Gets the remaining bytes of the current DMA descriptor transfer. + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + * @return The number of bytes which have not been transferred yet. + */ +uint32_t DMA_GetRemainingBytes(DMA_Type *base, uint32_t channel); + +/*! + * @brief Set priority of channel configuration register. + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + * @param priority Channel priority value. + */ +static inline void DMA_SetChannelPriority(DMA_Type *base, uint32_t channel, dma_priority_t priority) +{ + assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)); + base->CHANNEL[channel].CFG = + (base->CHANNEL[channel].CFG & (~(DMA_CHANNEL_CFG_CHPRIORITY_MASK))) | DMA_CHANNEL_CFG_CHPRIORITY(priority); +} + +/*! + * @brief Get priority of channel configuration register. + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + * @return Channel priority value. + */ +static inline dma_priority_t DMA_GetChannelPriority(DMA_Type *base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)); + return (dma_priority_t)((base->CHANNEL[channel].CFG & DMA_CHANNEL_CFG_CHPRIORITY_MASK) >> + DMA_CHANNEL_CFG_CHPRIORITY_SHIFT); +} + +/*! + * @brief Set channel configuration valid.. + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + */ +static inline void DMA_SetChannelConfigValid(DMA_Type *base, uint32_t channel) +{ + base->CHANNEL[channel].XFERCFG |= DMA_CHANNEL_XFERCFG_CFGVALID_MASK; +} + +/*! + * @brief Do software trigger for the channel. + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + */ +static inline void DMA_DoChannelSoftwareTrigger(DMA_Type *base, uint32_t channel) +{ + base->CHANNEL[channel].XFERCFG |= DMA_CHANNEL_XFERCFG_SWTRIG_MASK; +} + +/*! + * @brief Load channel transfer configurations. + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + * @param xfer transfer configurations. + */ +static inline void DMA_LoadChannelTransferConfig(DMA_Type *base, uint32_t channel, uint32_t xfer) +{ + base->CHANNEL[channel].XFERCFG = xfer; +} + +/*! + * @brief Create application specific DMA descriptor + * to be used in a chain in transfer + * @deprecated Do not use this function. It has been superceded by @ref DMA_SetupDescriptor. + * @param desc DMA descriptor address. + * @param xfercfg Transfer configuration for DMA descriptor. + * @param srcAddr Address of last item to transmit + * @param dstAddr Address of last item to receive. + * @param nextDesc Address of next descriptor in chain. + */ +void DMA_CreateDescriptor(dma_descriptor_t *desc, dma_xfercfg_t *xfercfg, void *srcAddr, void *dstAddr, void *nextDesc); + +/*! + * @brief setup dma descriptor + * + * Note: This function do not support configure wrap descriptor. + * + * @param desc DMA descriptor address. + * @param xfercfg Transfer configuration for DMA descriptor. + * @param srcStartAddr Start address of source address. + * @param dstStartAddr Start address of destination address. + * @param nextDesc Address of next descriptor in chain. + */ +void DMA_SetupDescriptor( + dma_descriptor_t *desc, uint32_t xfercfg, void *srcStartAddr, void *dstStartAddr, void *nextDesc); + +/*! + * @brief setup dma channel descriptor + * + * Note: This function support configure wrap descriptor. + * + * @param desc DMA descriptor address. + * @param xfercfg Transfer configuration for DMA descriptor. + * @param srcStartAddr Start address of source address. + * @param dstStartAddr Start address of destination address. + * @param nextDesc Address of next descriptor in chain. + * @param wrapType burst wrap type. + * @param burstSize burst size, reference _dma_burst_size. + */ +void DMA_SetupChannelDescriptor(dma_descriptor_t *desc, + uint32_t xfercfg, + void *srcStartAddr, + void *dstStartAddr, + void *nextDesc, + dma_burst_wrap_t wrapType, + uint32_t burstSize); + +/* @} */ + +/*! + * @name DMA Transactional Operation + * @{ + */ + +/*! + * @brief Abort running transfer by handle. + * + * This function aborts DMA transfer specified by handle. + * + * @param handle DMA handle pointer. + */ +void DMA_AbortTransfer(dma_handle_t *handle); + +/*! + * @brief Creates the DMA handle. + * + * This function is called if using transaction API for DMA. This function + * initializes the internal state of DMA handle. + * + * @param handle DMA handle pointer. The DMA handle stores callback function and + * parameters. + * @param base DMA peripheral base address. + * @param channel DMA channel number. + */ +void DMA_CreateHandle(dma_handle_t *handle, DMA_Type *base, uint32_t channel); + +/*! + * @brief Installs a callback function for the DMA transfer. + * + * This callback is called in DMA IRQ handler. Use the callback to do something after + * the current major loop transfer completes. + * + * @param handle DMA handle pointer. + * @param callback DMA callback function pointer. + * @param userData Parameter for callback function. + */ +void DMA_SetCallback(dma_handle_t *handle, dma_callback callback, void *userData); + +/*! + * @brief Prepares the DMA transfer structure. + * @deprecated Do not use this function. It has been superceded by @ref DMA_PrepareChannelTransfer. + * This function prepares the transfer configuration structure according to the user input. + * + * @param config The user configuration structure of type dma_transfer_t. + * @param srcAddr DMA transfer source address. + * @param dstAddr DMA transfer destination address. + * @param byteWidth DMA transfer destination address width(bytes). + * @param transferBytes DMA transfer bytes to be transferred. + * @param type DMA transfer type. + * @param nextDesc Chain custom descriptor to transfer. + * @note The data address and the data width must be consistent. For example, if the SRC + * is 4 bytes, so the source address must be 4 bytes aligned, or it shall result in + * source address error(SAE). + */ +void DMA_PrepareTransfer(dma_transfer_config_t *config, + void *srcAddr, + void *dstAddr, + uint32_t byteWidth, + uint32_t transferBytes, + dma_transfer_type_t type, + void *nextDesc); + +/*! + * @brief Prepare channel transfer configurations. + * + * This function used to prepare channel transfer configurations. + * + * @param config Pointer to DMA channel transfer configuration structure. + * @param srcStartAddr source start address. + * @param dstStartAddr destination start address. + * @param xferCfg xfer configuration, user can reference DMA_CHANNEL_XFER about to how to get xferCfg value. + * @param type transfer type. + * @param trigger DMA channel trigger configurations. + * @param nextDesc address of next descriptor. + */ +void DMA_PrepareChannelTransfer(dma_channel_config_t *config, + void *srcStartAddr, + void *dstStartAddr, + uint32_t xferCfg, + dma_transfer_type_t type, + dma_channel_trigger_t *trigger, + void *nextDesc); + +/*! + * @brief Submits the DMA transfer request. + * @deprecated Do not use this function. It has been superceded by @ref DMA_SubmitChannelTransfer. + * + * This function submits the DMA transfer request according to the transfer configuration structure. + * If the user submits the transfer request repeatedly, this function packs an unprocessed request as + * a TCD and enables scatter/gather feature to process it in the next time. + * + * @param handle DMA handle pointer. + * @param config Pointer to DMA transfer configuration structure. + * @retval kStatus_DMA_Success It means submit transfer request succeed. + * @retval kStatus_DMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed. + * @retval kStatus_DMA_Busy It means the given channel is busy, need to submit request later. + */ +status_t DMA_SubmitTransfer(dma_handle_t *handle, dma_transfer_config_t *config); + +/*! + * @brief Submit channel transfer paramter directly. + * + * This function used to configue channel head descriptor that is used to start DMA transfer, the head descriptor table + * is defined in DMA driver, it is useful for the case: + * 1. for the single transfer, application doesn't need to allocate descriptor table, the head descriptor can be used + for it. + * @code + DMA_SetChannelConfig(base, channel, trigger, isPeriph); + DMA_CreateHandle(handle, base, channel) + DMA_SubmitChannelTransferParameter(handle, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, + bytes), srcStartAddr, dstStartAddr, NULL); + DMA_StartTransfer(handle) + * @endcode + * + * 2. for the linked transfer, application should responsible for link descriptor, for example, if 4 transfer is + required, then application should prepare + * three descriptor table with macro , the head descriptor in driver can be used for the first transfer descriptor. + * @code + //define link descriptor table in application with macro + DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc[3]); + + DMA_SetupDescriptor(nextDesc0, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), + srcStartAddr, dstStartAddr, nextDesc1); + DMA_SetupDescriptor(nextDesc1, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), + srcStartAddr, dstStartAddr, nextDesc2); + DMA_SetupDescriptor(nextDesc2, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), + srcStartAddr, dstStartAddr, NULL); + DMA_SetChannelConfig(base, channel, trigger, isPeriph); + DMA_CreateHandle(handle, base, channel) + DMA_SubmitChannelTransferParameter(handle, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, + bytes), srcStartAddr, dstStartAddr, nextDesc0); + DMA_StartTransfer(handle); + * @endcode + * + * @param handle Pointer to DMA handle. + * @param xferCfg xfer configuration, user can reference DMA_CHANNEL_XFER about to how to get xferCfg value. + * @param srcStartAddr source start address. + * @param dstStartAddr destination start address. + * @param nextDesc address of next descriptor. + */ +void DMA_SubmitChannelTransferParameter( + dma_handle_t *handle, uint32_t xfercfg, void *srcStartAddr, void *dstStartAddr, void *nextDesc); + +/*! + * @brief Submit channel descriptor. + * + * This function used to configue channel head descriptor that is used to start DMA transfer, the head descriptor table + is defined in + * DMA driver, this functiono is typical for the ping pong case: + * + * 1. for the ping pong case, application should responsible for the descriptor, for example, application should + * prepare two descriptor table with macro. + * @code + //define link descriptor table in application with macro + DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc[2]); + + DMA_SetupDescriptor(nextDesc0, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), + srcStartAddr, dstStartAddr, nextDesc1); + DMA_SetupDescriptor(nextDesc1, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), + srcStartAddr, dstStartAddr, nextDesc0); + DMA_SetChannelConfig(base, channel, trigger, isPeriph); + DMA_CreateHandle(handle, base, channel) + DMA_SubmitChannelDescriptor(handle, nextDesc0); + DMA_StartTransfer(handle); + * @endcode + * + * @param handle Pointer to DMA handle. + * @param descriptor descriptor to submit. + */ +void DMA_SubmitChannelDescriptor(dma_handle_t *handle, dma_descriptor_t *descriptor); + +/*! + * @brief Submits the DMA channel transfer request. + * + * This function submits the DMA transfer request according to the transfer configuration structure. + * If the user submits the transfer request repeatedly, this function packs an unprocessed request as + * a TCD and enables scatter/gather feature to process it in the next time. + * It is used for the case: + * 1. for the single transfer, application doesn't need to allocate descriptor table, the head descriptor can be used + for it. + * @code + DMA_CreateHandle(handle, base, channel) + DMA_PrepareChannelTransfer(config,srcStartAddr,dstStartAddr,xferCfg,type,trigger,NULL); + DMA_SubmitChannelTransfer(handle, config) + DMA_StartTransfer(handle) + * @endcode + * + * 2. for the linked transfer, application should responsible for link descriptor, for example, if 4 transfer is + required, then application should prepare + * three descriptor table with macro , the head descriptor in driver can be used for the first transfer descriptor. + * @code + //define link descriptor table in application with macro + DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc); + DMA_SetupDescriptor(nextDesc0, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), + srcStartAddr, dstStartAddr, nextDesc1); + DMA_SetupDescriptor(nextDesc1, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), + srcStartAddr, dstStartAddr, nextDesc2); + DMA_SetupDescriptor(nextDesc2, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), + srcStartAddr, dstStartAddr, NULL); + DMA_CreateHandle(handle, base, channel) + DMA_PrepareChannelTransfer(config,srcStartAddr,dstStartAddr,xferCfg,type,trigger,nextDesc0); + DMA_SubmitChannelTransfer(handle, config) + DMA_StartTransfer(handle) + * @endcode + * + * 3. for the ping pong case, application should responsible for link descriptor, for example, application should + prepare + * two descriptor table with macro , the head descriptor in driver can be used for the first transfer descriptor. + * @code + //define link descriptor table in application with macro + DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc); + + DMA_SetupDescriptor(nextDesc0, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), + srcStartAddr, dstStartAddr, nextDesc1); + DMA_SetupDescriptor(nextDesc1, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), + srcStartAddr, dstStartAddr, nextDesc0); + DMA_CreateHandle(handle, base, channel) + DMA_PrepareChannelTransfer(config,srcStartAddr,dstStartAddr,xferCfg,type,trigger,nextDesc0); + DMA_SubmitChannelTransfer(handle, config) + DMA_StartTransfer(handle) + * @endcode + * @param handle DMA handle pointer. + * @param config Pointer to DMA transfer configuration structure. + * @retval kStatus_DMA_Success It means submit transfer request succeed. + * @retval kStatus_DMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed. + * @retval kStatus_DMA_Busy It means the given channel is busy, need to submit request later. + */ +status_t DMA_SubmitChannelTransfer(dma_handle_t *handle, dma_channel_config_t *config); + +/*! + * @brief DMA start transfer. + * + * This function enables the channel request. User can call this function after submitting the transfer request + * It will trigger transfer start with software trigger only when hardware trigger is not used. + * + * @param handle DMA handle pointer. + */ +void DMA_StartTransfer(dma_handle_t *handle); + +/*! + * @brief DMA IRQ handler for descriptor transfer complete. + * + * This function clears the channel major interrupt flag and call + * the callback function if it is not NULL. + * + * @param base DMA base address. + */ +void DMA_IRQHandle(DMA_Type *base); + +/* @} */ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/* @} */ + +#endif /*_FSL_DMA_H_*/ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_flexcomm.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_flexcomm.c new file mode 100644 index 000000000..b392bc388 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_flexcomm.c @@ -0,0 +1,400 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" +#include "fsl_flexcomm.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexcomm" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! @brief Set the FLEXCOMM mode . */ +static status_t FLEXCOMM_SetPeriph(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph, int lock); + +/*! @brief check whether flexcomm supports peripheral type */ +static bool FLEXCOMM_PeripheralIsPresent(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief Pointers to real IRQ handlers installed by drivers for each instance. */ +static flexcomm_irq_handler_t s_flexcommIrqHandler[FSL_FEATURE_SOC_FLEXCOMM_COUNT]; + +/*! @brief Pointers to handles for each instance to provide context to interrupt routines */ +static void *s_flexcommHandle[FSL_FEATURE_SOC_FLEXCOMM_COUNT]; + +/*! @brief Array to map FLEXCOMM instance number to IRQ number. */ +IRQn_Type const kFlexcommIrqs[] = FLEXCOMM_IRQS; + +/*! @brief Array to map FLEXCOMM instance number to base address. */ +static const uint32_t s_flexcommBaseAddrs[FSL_FEATURE_SOC_FLEXCOMM_COUNT] = FLEXCOMM_BASE_ADDRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief IDs of clock for each FLEXCOMM module */ +static const clock_ip_name_t s_flexcommClocks[] = FLEXCOMM_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_FEATURE_FLEXCOMM_HAS_NO_RESET) && FSL_FEATURE_FLEXCOMM_HAS_NO_RESET) +/*! @brief Pointers to FLEXCOMM resets for each instance. */ +static const reset_ip_name_t s_flexcommResets[] = FLEXCOMM_RSTS; +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* check whether flexcomm supports peripheral type */ +static bool FLEXCOMM_PeripheralIsPresent(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph) +{ + if (periph == FLEXCOMM_PERIPH_NONE) + { + return true; + } + else if (periph <= FLEXCOMM_PERIPH_I2S_TX) + { + return (base->PSELID & (uint32_t)(1 << ((uint32_t)periph + 3))) > (uint32_t)0 ? true : false; + } + else if (periph == FLEXCOMM_PERIPH_I2S_RX) + { + return (base->PSELID & (1 << 7)) > (uint32_t)0 ? true : false; + } + else + { + return false; + } +} + +/* Get the index corresponding to the FLEXCOMM */ +/*! brief Returns instance number for FLEXCOMM module with given base address. */ +uint32_t FLEXCOMM_GetInstance(void *base) +{ + int i; + + for (i = 0; i < FSL_FEATURE_SOC_FLEXCOMM_COUNT; i++) + { + if ((uint32_t)base == s_flexcommBaseAddrs[i]) + { + return i; + } + } + + assert(false); + return 0; +} + +/* Changes FLEXCOMM mode */ +static status_t FLEXCOMM_SetPeriph(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph, int lock) +{ + /* Check whether peripheral type is present */ + if (!FLEXCOMM_PeripheralIsPresent(base, periph)) + { + return kStatus_OutOfRange; + } + + /* Flexcomm is locked to different peripheral type than expected */ + if ((base->PSELID & FLEXCOMM_PSELID_LOCK_MASK) && ((base->PSELID & FLEXCOMM_PSELID_PERSEL_MASK) != periph)) + { + return kStatus_Fail; + } + + /* Check if we are asked to lock */ + if (lock) + { + base->PSELID = (uint32_t)periph | FLEXCOMM_PSELID_LOCK_MASK; + } + else + { + base->PSELID = (uint32_t)periph; + } + + return kStatus_Success; +} + +/*! brief Initializes FLEXCOMM and selects peripheral mode according to the second parameter. */ +status_t FLEXCOMM_Init(void *base, FLEXCOMM_PERIPH_T periph) +{ + int idx = FLEXCOMM_GetInstance(base); + + if (idx < 0) + { + return kStatus_InvalidArgument; + } + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the peripheral clock */ + CLOCK_EnableClock(s_flexcommClocks[idx]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_FEATURE_FLEXCOMM_HAS_NO_RESET) && FSL_FEATURE_FLEXCOMM_HAS_NO_RESET) + /* Reset the FLEXCOMM module */ + RESET_PeripheralReset(s_flexcommResets[idx]); +#endif + + /* Set the FLEXCOMM to given peripheral */ + return FLEXCOMM_SetPeriph((FLEXCOMM_Type *)base, periph, 0); +} + +/*! brief Sets IRQ handler for given FLEXCOMM module. It is used by drivers register IRQ handler according to FLEXCOMM + * mode */ +void FLEXCOMM_SetIRQHandler(void *base, flexcomm_irq_handler_t handler, void *handle) +{ + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(base); + + /* Clear handler first to avoid execution of the handler with wrong handle */ + s_flexcommIrqHandler[instance] = NULL; + s_flexcommHandle[instance] = handle; + s_flexcommIrqHandler[instance] = handler; +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +/* IRQ handler functions overloading weak symbols in the startup */ +#if defined(FLEXCOMM0) +void FLEXCOMM0_DriverIRQHandler(void) +{ + assert(s_flexcommIrqHandler[0]); + s_flexcommIrqHandler[0]((void *)s_flexcommBaseAddrs[0], s_flexcommHandle[0]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(FLEXCOMM1) +void FLEXCOMM1_DriverIRQHandler(void) +{ + assert(s_flexcommIrqHandler[1]); + s_flexcommIrqHandler[1]((void *)s_flexcommBaseAddrs[1], s_flexcommHandle[1]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(FLEXCOMM2) +void FLEXCOMM2_DriverIRQHandler(void) +{ + assert(s_flexcommIrqHandler[2]); + s_flexcommIrqHandler[2]((void *)s_flexcommBaseAddrs[2], s_flexcommHandle[2]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(FLEXCOMM3) +void FLEXCOMM3_DriverIRQHandler(void) +{ + assert(s_flexcommIrqHandler[3]); + s_flexcommIrqHandler[3]((void *)s_flexcommBaseAddrs[3], s_flexcommHandle[3]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(FLEXCOMM4) +void FLEXCOMM4_DriverIRQHandler(void) +{ + assert(s_flexcommIrqHandler[4]); + s_flexcommIrqHandler[4]((void *)s_flexcommBaseAddrs[4], s_flexcommHandle[4]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +#endif + +#if defined(FLEXCOMM5) +void FLEXCOMM5_DriverIRQHandler(void) +{ + assert(s_flexcommIrqHandler[5]); + s_flexcommIrqHandler[5]((void *)s_flexcommBaseAddrs[5], s_flexcommHandle[5]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(FLEXCOMM6) +void FLEXCOMM6_DriverIRQHandler(void) +{ + assert(s_flexcommIrqHandler[6]); + s_flexcommIrqHandler[6]((void *)s_flexcommBaseAddrs[6], s_flexcommHandle[6]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(FLEXCOMM7) +void FLEXCOMM7_DriverIRQHandler(void) +{ + assert(s_flexcommIrqHandler[7]); + s_flexcommIrqHandler[7]((void *)s_flexcommBaseAddrs[7], s_flexcommHandle[7]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(FLEXCOMM8) +void FLEXCOMM8_DriverIRQHandler(void) +{ + assert(s_flexcommIrqHandler[8]); + s_flexcommIrqHandler[8]((void *)s_flexcommBaseAddrs[8], s_flexcommHandle[8]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(FLEXCOMM9) +void FLEXCOMM9_DriverIRQHandler(void) +{ + assert(s_flexcommIrqHandler[9]); + s_flexcommIrqHandler[9]((void *)s_flexcommBaseAddrs[9], s_flexcommHandle[9]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(FLEXCOMM10) +void FLEXCOMM10_DriverIRQHandler(void) +{ + assert(s_flexcommIrqHandler[10]); + s_flexcommIrqHandler[10]((void *)s_flexcommBaseAddrs[10], s_flexcommHandle[10]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(FLEXCOMM11) +void FLEXCOMM11_DriverIRQHandler(void) +{ + assert(s_flexcommIrqHandler[11]); + s_flexcommIrqHandler[11]((void *)s_flexcommBaseAddrs[11], s_flexcommHandle[11]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(FLEXCOMM12) +void FLEXCOMM12_DriverIRQHandler(void) +{ + assert(s_flexcommIrqHandler[12]); + s_flexcommIrqHandler[12]((void *)s_flexcommBaseAddrs[12], s_flexcommHandle[12]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(FLEXCOMM13) +void FLEXCOMM13_DriverIRQHandler(void) +{ + assert(s_flexcommIrqHandler[13]); + s_flexcommIrqHandler[13]((void *)s_flexcommBaseAddrs[13], s_flexcommHandle[13]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(FLEXCOMM14) +void FLEXCOMM14_DriverIRQHandler(void) +{ + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM14); + assert(s_flexcommIrqHandler[instance]); + s_flexcommIrqHandler[instance]((void *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(FLEXCOMM15) +void FLEXCOMM15_DriverIRQHandler(void) +{ + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM14); + assert(s_flexcommIrqHandler[instance]); + s_flexcommIrqHandler[instance]((void *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(FLEXCOMM16) +void FLEXCOMM16_DriverIRQHandler(void) +{ + assert(s_flexcommIrqHandler[16]); + s_flexcommIrqHandler[16]((void *)s_flexcommBaseAddrs[16], s_flexcommHandle[16]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_flexcomm.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_flexcomm.h new file mode 100644 index 000000000..91c90c289 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_flexcomm.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_FLEXCOMM_H_ +#define _FSL_FLEXCOMM_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup flexcomm_driver + * @{ + */ + +/*! @name Driver version */ +/*@{*/ +/*! @brief FlexCOMM driver version 2.0.1. */ +#define FSL_FLEXCOMM_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/*! @brief FLEXCOMM peripheral modes. */ +typedef enum +{ + FLEXCOMM_PERIPH_NONE, /*!< No peripheral */ + FLEXCOMM_PERIPH_USART, /*!< USART peripheral */ + FLEXCOMM_PERIPH_SPI, /*!< SPI Peripheral */ + FLEXCOMM_PERIPH_I2C, /*!< I2C Peripheral */ + FLEXCOMM_PERIPH_I2S_TX, /*!< I2S TX Peripheral */ + FLEXCOMM_PERIPH_I2S_RX, /*!< I2S RX Peripheral */ +} FLEXCOMM_PERIPH_T; + +/*! @brief Typedef for interrupt handler. */ +typedef void (*flexcomm_irq_handler_t)(void *base, void *handle); + +/*! @brief Array with IRQ number for each FLEXCOMM module. */ +extern IRQn_Type const kFlexcommIrqs[]; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! @brief Returns instance number for FLEXCOMM module with given base address. */ +uint32_t FLEXCOMM_GetInstance(void *base); + +/*! @brief Initializes FLEXCOMM and selects peripheral mode according to the second parameter. */ +status_t FLEXCOMM_Init(void *base, FLEXCOMM_PERIPH_T periph); + +/*! @brief Sets IRQ handler for given FLEXCOMM module. It is used by drivers register IRQ handler according to FLEXCOMM + * mode */ +void FLEXCOMM_SetIRQHandler(void *base, flexcomm_irq_handler_t handler, void *handle); + +#if defined(__cplusplus) +} +#endif + +/*@}*/ + +#endif /* _FSL_FLEXCOMM_H_*/ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_gint.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_gint.c new file mode 100644 index 000000000..dec822dec --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_gint.c @@ -0,0 +1,392 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_gint.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.gint" +#endif + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to GINT bases for each instance. */ +static GINT_Type *const s_gintBases[FSL_FEATURE_SOC_GINT_COUNT] = GINT_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Clocks for each instance. */ +static const clock_ip_name_t s_gintClocks[FSL_FEATURE_SOC_GINT_COUNT] = GINT_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) +/*! @brief Resets for each instance. */ +static const reset_ip_name_t s_gintResets[FSL_FEATURE_SOC_GINT_COUNT] = GINT_RSTS; +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + +/* @brief Irq number for each instance */ +static const IRQn_Type s_gintIRQ[FSL_FEATURE_SOC_GINT_COUNT] = GINT_IRQS; + +/*! @brief Callback function array for GINT(s). */ +static gint_cb_t s_gintCallback[FSL_FEATURE_SOC_GINT_COUNT]; + +/******************************************************************************* + * Code + ******************************************************************************/ + +static uint32_t GINT_GetInstance(GINT_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_gintBases); instance++) + { + if (s_gintBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_gintBases)); + + return instance; +} + +/*! + * brief Initialize GINT peripheral. + + * This function initializes the GINT peripheral and enables the clock. + * + * param base Base address of the GINT peripheral. + * + * retval None. + */ +void GINT_Init(GINT_Type *base) +{ + uint32_t instance; + + instance = GINT_GetInstance(base); + + s_gintCallback[instance] = NULL; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the peripheral clock */ + CLOCK_EnableClock(s_gintClocks[instance]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) + /* Reset the module. */ + RESET_PeripheralReset(s_gintResets[instance]); +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ +} + +/*! + * brief Setup GINT peripheral control parameters. + + * This function sets the control parameters of GINT peripheral. + * + * param base Base address of the GINT peripheral. + * param comb Controls if the enabled inputs are logically ORed or ANDed for interrupt generation. + * param trig Controls if the enabled inputs are level or edge sensitive based on polarity. + * param callback This function is called when configured group interrupt is generated. + * + * retval None. + */ +void GINT_SetCtrl(GINT_Type *base, gint_comb_t comb, gint_trig_t trig, gint_cb_t callback) +{ + uint32_t instance; + + instance = GINT_GetInstance(base); + + base->CTRL = (GINT_CTRL_COMB(comb) | GINT_CTRL_TRIG(trig)); + + /* Save callback pointer */ + s_gintCallback[instance] = callback; +} + +/*! + * brief Get GINT peripheral control parameters. + + * This function returns the control parameters of GINT peripheral. + * + * param base Base address of the GINT peripheral. + * param comb Pointer to store combine input value. + * param trig Pointer to store trigger value. + * param callback Pointer to store callback function. + * + * retval None. + */ +void GINT_GetCtrl(GINT_Type *base, gint_comb_t *comb, gint_trig_t *trig, gint_cb_t *callback) +{ + uint32_t instance; + + instance = GINT_GetInstance(base); + + *comb = (gint_comb_t)((base->CTRL & GINT_CTRL_COMB_MASK) >> GINT_CTRL_COMB_SHIFT); + *trig = (gint_trig_t)((base->CTRL & GINT_CTRL_TRIG_MASK) >> GINT_CTRL_TRIG_SHIFT); + *callback = s_gintCallback[instance]; +} + +/*! + * brief Configure GINT peripheral pins. + + * This function enables and controls the polarity of enabled pin(s) of a given port. + * + * param base Base address of the GINT peripheral. + * param port Port number. + * param polarityMask Each bit position selects the polarity of the corresponding enabled pin. + * 0 = The pin is active LOW. 1 = The pin is active HIGH. + * param enableMask Each bit position selects if the corresponding pin is enabled or not. + * 0 = The pin is disabled. 1 = The pin is enabled. + * + * retval None. + */ +void GINT_ConfigPins(GINT_Type *base, gint_port_t port, uint32_t polarityMask, uint32_t enableMask) +{ + base->PORT_POL[port] = polarityMask; + base->PORT_ENA[port] = enableMask; +} + +/*! + * brief Get GINT peripheral pin configuration. + + * This function returns the pin configuration of a given port. + * + * param base Base address of the GINT peripheral. + * param port Port number. + * param polarityMask Pointer to store the polarity mask Each bit position indicates the polarity of the corresponding + enabled pin. + * 0 = The pin is active LOW. 1 = The pin is active HIGH. + * param enableMask Pointer to store the enable mask. Each bit position indicates if the corresponding pin is enabled + or not. + * 0 = The pin is disabled. 1 = The pin is enabled. + * + * retval None. + */ +void GINT_GetConfigPins(GINT_Type *base, gint_port_t port, uint32_t *polarityMask, uint32_t *enableMask) +{ + *polarityMask = base->PORT_POL[port]; + *enableMask = base->PORT_ENA[port]; +} + +/*! + * brief Enable callback. + + * This function enables the interrupt for the selected GINT peripheral. Although the pin(s) are monitored + * as soon as they are enabled, the callback function is not enabled until this function is called. + * + * param base Base address of the GINT peripheral. + * + * retval None. + */ +void GINT_EnableCallback(GINT_Type *base) +{ + uint32_t instance; + + instance = GINT_GetInstance(base); + /* If GINT is configured in "AND" mode a spurious interrupt is generated. + Clear status and pending interrupt before enabling the irq in NVIC. */ + GINT_ClrStatus(base); + NVIC_ClearPendingIRQ(s_gintIRQ[instance]); + EnableIRQ(s_gintIRQ[instance]); +} + +/*! + * brief Disable callback. + + * This function disables the interrupt for the selected GINT peripheral. Although the pins are still + * being monitored but the callback function is not called. + * + * param base Base address of the peripheral. + * + * retval None. + */ +void GINT_DisableCallback(GINT_Type *base) +{ + uint32_t instance; + + instance = GINT_GetInstance(base); + DisableIRQ(s_gintIRQ[instance]); + GINT_ClrStatus(base); + NVIC_ClearPendingIRQ(s_gintIRQ[instance]); +} + +/*! + * brief Deinitialize GINT peripheral. + + * This function disables the GINT clock. + * + * param base Base address of the GINT peripheral. + * + * retval None. + */ +void GINT_Deinit(GINT_Type *base) +{ + uint32_t instance; + + instance = GINT_GetInstance(base); + + /* Cleanup */ + GINT_DisableCallback(base); + s_gintCallback[instance] = NULL; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) + /* Reset the module. */ + RESET_PeripheralReset(s_gintResets[instance]); +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable the peripheral clock */ + CLOCK_DisableClock(s_gintClocks[instance]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/* IRQ handler functions overloading weak symbols in the startup */ +#if defined(GINT0) +void GINT0_DriverIRQHandler(void) +{ + /* Clear interrupt before callback */ + s_gintBases[0]->CTRL |= GINT_CTRL_INT_MASK; + /* Call user function */ + if (s_gintCallback[0] != NULL) + { + s_gintCallback[0](); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(GINT1) +void GINT1_DriverIRQHandler(void) +{ + /* Clear interrupt before callback */ + s_gintBases[1]->CTRL |= GINT_CTRL_INT_MASK; + /* Call user function */ + if (s_gintCallback[1] != NULL) + { + s_gintCallback[1](); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(GINT2) +void GINT2_DriverIRQHandler(void) +{ + /* Clear interrupt before callback */ + s_gintBases[2]->CTRL |= GINT_CTRL_INT_MASK; + /* Call user function */ + if (s_gintCallback[2] != NULL) + { + s_gintCallback[2](); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(GINT3) +void GINT3_DriverIRQHandler(void) +{ + /* Clear interrupt before callback */ + s_gintBases[3]->CTRL |= GINT_CTRL_INT_MASK; + /* Call user function */ + if (s_gintCallback[3] != NULL) + { + s_gintCallback[3](); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(GINT4) +void GINT4_DriverIRQHandler(void) +{ + /* Clear interrupt before callback */ + s_gintBases[4]->CTRL |= GINT_CTRL_INT_MASK; + /* Call user function */ + if (s_gintCallback[4] != NULL) + { + s_gintCallback[4](); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(GINT5) +void GINT5_DriverIRQHandler(void) +{ + /* Clear interrupt before callback */ + s_gintBases[5]->CTRL |= GINT_CTRL_INT_MASK; + /* Call user function */ + if (s_gintCallback[5] != NULL) + { + s_gintCallback[5](); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(GINT6) +void GINT6_DriverIRQHandler(void) +{ + /* Clear interrupt before callback */ + s_gintBases[6]->CTRL |= GINT_CTRL_INT_MASK; + /* Call user function */ + if (s_gintCallback[6] != NULL) + { + s_gintCallback[6](); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(GINT7) +void GINT7_DriverIRQHandler(void) +{ + /* Clear interrupt before callback */ + s_gintBases[7]->CTRL |= GINT_CTRL_INT_MASK; + /* Call user function */ + if (s_gintCallback[7] != NULL) + { + s_gintCallback[7](); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_gint.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_gint.h new file mode 100644 index 000000000..10203874f --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_gint.h @@ -0,0 +1,222 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_GINT_H_ +#define _FSL_GINT_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup gint_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_GINT_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*!< Version 2.0.1. */ +/*@}*/ + +/*! @brief GINT combine inputs type */ +typedef enum _gint_comb +{ + kGINT_CombineOr = 0U, /*!< A grouped interrupt is generated when any one of the enabled inputs is active */ + kGINT_CombineAnd = 1U /*!< A grouped interrupt is generated when all enabled inputs are active */ +} gint_comb_t; + +/*! @brief GINT trigger type */ +typedef enum _gint_trig +{ + kGINT_TrigEdge = 0U, /*!< Edge triggered based on polarity */ + kGINT_TrigLevel = 1U /*!< Level triggered based on polarity */ +} gint_trig_t; + +/* @brief GINT port type */ +typedef enum _gint_port +{ + kGINT_Port0 = 0U, + kGINT_Port1 = 1U, +#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 2U) + kGINT_Port2 = 2U, +#endif +#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 3U) + kGINT_Port3 = 3U, +#endif +#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 4U) + kGINT_Port4 = 4U, +#endif +#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 5U) + kGINT_Port5 = 5U, +#endif +#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 6U) + kGINT_Port6 = 6U, +#endif +#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 7U) + kGINT_Port7 = 7U, +#endif +} gint_port_t; + +/*! @brief GINT Callback function. */ +typedef void (*gint_cb_t)(void); + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Initialize GINT peripheral. + + * This function initializes the GINT peripheral and enables the clock. + * + * @param base Base address of the GINT peripheral. + * + * @retval None. + */ +void GINT_Init(GINT_Type *base); + +/*! + * @brief Setup GINT peripheral control parameters. + + * This function sets the control parameters of GINT peripheral. + * + * @param base Base address of the GINT peripheral. + * @param comb Controls if the enabled inputs are logically ORed or ANDed for interrupt generation. + * @param trig Controls if the enabled inputs are level or edge sensitive based on polarity. + * @param callback This function is called when configured group interrupt is generated. + * + * @retval None. + */ +void GINT_SetCtrl(GINT_Type *base, gint_comb_t comb, gint_trig_t trig, gint_cb_t callback); + +/*! + * @brief Get GINT peripheral control parameters. + + * This function returns the control parameters of GINT peripheral. + * + * @param base Base address of the GINT peripheral. + * @param comb Pointer to store combine input value. + * @param trig Pointer to store trigger value. + * @param callback Pointer to store callback function. + * + * @retval None. + */ +void GINT_GetCtrl(GINT_Type *base, gint_comb_t *comb, gint_trig_t *trig, gint_cb_t *callback); + +/*! + * @brief Configure GINT peripheral pins. + + * This function enables and controls the polarity of enabled pin(s) of a given port. + * + * @param base Base address of the GINT peripheral. + * @param port Port number. + * @param polarityMask Each bit position selects the polarity of the corresponding enabled pin. + * 0 = The pin is active LOW. 1 = The pin is active HIGH. + * @param enableMask Each bit position selects if the corresponding pin is enabled or not. + * 0 = The pin is disabled. 1 = The pin is enabled. + * + * @retval None. + */ +void GINT_ConfigPins(GINT_Type *base, gint_port_t port, uint32_t polarityMask, uint32_t enableMask); + +/*! + * @brief Get GINT peripheral pin configuration. + + * This function returns the pin configuration of a given port. + * + * @param base Base address of the GINT peripheral. + * @param port Port number. + * @param polarityMask Pointer to store the polarity mask Each bit position indicates the polarity of the corresponding + enabled pin. + * 0 = The pin is active LOW. 1 = The pin is active HIGH. + * @param enableMask Pointer to store the enable mask. Each bit position indicates if the corresponding pin is enabled + or not. + * 0 = The pin is disabled. 1 = The pin is enabled. + * + * @retval None. + */ +void GINT_GetConfigPins(GINT_Type *base, gint_port_t port, uint32_t *polarityMask, uint32_t *enableMask); + +/*! + * @brief Enable callback. + + * This function enables the interrupt for the selected GINT peripheral. Although the pin(s) are monitored + * as soon as they are enabled, the callback function is not enabled until this function is called. + * + * @param base Base address of the GINT peripheral. + * + * @retval None. + */ +void GINT_EnableCallback(GINT_Type *base); + +/*! + * @brief Disable callback. + + * This function disables the interrupt for the selected GINT peripheral. Although the pins are still + * being monitored but the callback function is not called. + * + * @param base Base address of the peripheral. + * + * @retval None. + */ +void GINT_DisableCallback(GINT_Type *base); + +/*! + * @brief Clear GINT status. + + * This function clears the GINT status bit. + * + * @param base Base address of the GINT peripheral. + * + * @retval None. + */ +static inline void GINT_ClrStatus(GINT_Type *base) +{ + base->CTRL |= GINT_CTRL_INT_MASK; +} + +/*! + * @brief Get GINT status. + + * This function returns the GINT status. + * + * @param base Base address of the GINT peripheral. + * + * @retval status = 0 No group interrupt request. = 1 Group interrupt request active. + */ +static inline uint32_t GINT_GetStatus(GINT_Type *base) +{ + return (base->CTRL & GINT_CTRL_INT_MASK); +} + +/*! + * @brief Deinitialize GINT peripheral. + + * This function disables the GINT clock. + * + * @param base Base address of the GINT peripheral. + * + * @retval None. + */ +void GINT_Deinit(GINT_Type *base); + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _FSL_GINT_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_gpio.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_gpio.c new file mode 100644 index 000000000..926880f2c --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_gpio.c @@ -0,0 +1,303 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_gpio.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpc_gpio" +#endif + +/******************************************************************************* + * Variables + ******************************************************************************/ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Array to map FGPIO instance number to clock name. */ +static const clock_ip_name_t s_gpioClockName[] = GPIO_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_FEATURE_GPIO_HAS_NO_RESET) && FSL_FEATURE_GPIO_HAS_NO_RESET) +/*! @brief Pointers to GPIO resets for each instance. */ +static const reset_ip_name_t s_gpioResets[] = GPIO_RSTS_N; +#endif +/******************************************************************************* + * Prototypes + ************ ******************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +/*! + * brief Initializes the GPIO peripheral. + * + * This function ungates the GPIO clock. + * + * param base GPIO peripheral base pointer. + * param port GPIO port number. + */ +void GPIO_PortInit(GPIO_Type *base, uint32_t port) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + assert(port < ARRAY_SIZE(s_gpioClockName)); + + /* Upgate the GPIO clock */ + CLOCK_EnableClock(s_gpioClockName[port]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#if !(defined(FSL_FEATURE_GPIO_HAS_NO_RESET) && FSL_FEATURE_GPIO_HAS_NO_RESET) + /* Reset the GPIO module */ + RESET_PeripheralReset(s_gpioResets[port]); +#endif +} + +/*! + * brief Initializes a GPIO pin used by the board. + * + * To initialize the GPIO, define a pin configuration, either input or output, in the user file. + * Then, call the GPIO_PinInit() function. + * + * This is an example to define an input pin or output pin configuration: + * code + * // Define a digital input pin configuration, + * gpio_pin_config_t config = + * { + * kGPIO_DigitalInput, + * 0, + * } + * //Define a digital output pin configuration, + * gpio_pin_config_t config = + * { + * kGPIO_DigitalOutput, + * 0, + * } + * endcode + * + * param base GPIO peripheral base pointer(Typically GPIO) + * param port GPIO port number + * param pin GPIO pin number + * param config GPIO pin configuration pointer + */ +void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_config_t *config) +{ + if (config->pinDirection == kGPIO_DigitalInput) + { +#if defined(FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) && (FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) + base->DIRCLR[port] = 1U << pin; +#else + base->DIR[port] &= ~(1U << pin); +#endif /*FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR*/ + } + else + { + /* Set default output value */ + if (config->outputLogic == 0U) + { + base->CLR[port] = (1U << pin); + } + else + { + base->SET[port] = (1U << pin); + } +/* Set pin direction */ +#if defined(FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) && (FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) + base->DIRSET[port] = 1U << pin; +#else + base->DIR[port] |= 1U << pin; +#endif /*FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR*/ + } +} + +#if defined(FSL_FEATURE_GPIO_HAS_INTERRUPT) && FSL_FEATURE_GPIO_HAS_INTERRUPT +/*! + * @brief Configures the gpio pin interrupt. + * + * @param base GPIO base pointer. + * @param port GPIO port number + * @param pin GPIO pin number. + * @param config GPIO pin interrupt configuration.. + */ +void GPIO_SetPinInterruptConfig(GPIO_Type *base, uint32_t port, uint32_t pin, gpio_interrupt_config_t *config) +{ + base->INTEDG[port] = base->INTEDG[port] | (config->mode << pin); + + base->INTPOL[port] = base->INTPOL[port] | (config->polarity << pin); +} + +/*! + * @brief Enables multiple pins interrupt. + * + * @param base GPIO base pointer. + * @param port GPIO port number. + * @param index GPIO interrupt number. + * @param mask GPIO pin number macro. + */ +void GPIO_PortEnableInterrupts(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask) +{ + if (kGPIO_InterruptA == index) + { + base->INTENA[port] = base->INTENA[port] | mask; + } + else if (kGPIO_InterruptB == index) + { + base->INTENB[port] = base->INTENB[port] | mask; + } + else + { + /*Should not enter here*/ + } +} + +/*! + * @brief Disables multiple pins interrupt. + * + * @param base GPIO base pointer. + * @param port GPIO port number. + * @param index GPIO interrupt number. + * @param mask GPIO pin number macro. + */ +void GPIO_PortDisableInterrupts(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask) +{ + if (kGPIO_InterruptA == index) + { + base->INTENA[port] = base->INTENA[port] & ~mask; + } + else if (kGPIO_InterruptB == index) + { + base->INTENB[port] = base->INTENB[port] & ~mask; + } + else + { + /*Should not enter here*/ + } +} + +/*! + * @brief Clears multiple pins interrupt flag. Status flags are cleared by + * writing a 1 to the corresponding bit position. + * + * @param base GPIO base pointer. + * @param port GPIO port number. + * @param index GPIO interrupt number. + * @param mask GPIO pin number macro. + */ +void GPIO_PortClearInterruptFlags(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask) +{ + if (kGPIO_InterruptA == index) + { + base->INTSTATA[port] = mask; + } + else if (kGPIO_InterruptB == index) + { + base->INTSTATB[port] = mask; + } + else + { + /*Should not enter here*/ + } +} + +/*! + * @ Read port interrupt status. + * + * @param base GPIO base pointer. + * @param port GPIO port number + * @param index GPIO interrupt number. + * @retval masked GPIO status value + */ +uint32_t GPIO_PortGetInterruptStatus(GPIO_Type *base, uint32_t port, uint32_t index) +{ + uint32_t status = 0U; + + if (kGPIO_InterruptA == index) + { + status = base->INTSTATA[port]; + } + else if (kGPIO_InterruptB == index) + { + status = base->INTSTATB[port]; + } + else + { + /*Should not enter here*/ + } + return status; + +} + +/*! + * @brief Enables the specific pin interrupt. + * + * @param base GPIO base pointer. + * @param port GPIO port number. + * @param pin GPIO pin number. + * @param index GPIO interrupt number. + */ +void GPIO_PinEnableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index) +{ + if (kGPIO_InterruptA == index) + { + base->INTENA[port] = base->INTENA[port] | (1U << pin); + } + else if (kGPIO_InterruptB == index) + { + base->INTENB[port] = base->INTENB[port] | (1U << pin); + } + else + { + /*Should not enter here*/ + } +} + +/*! + * @brief Disables the specific pin interrupt. + * + * @param base GPIO base pointer. + * @param port GPIO port number. + * @param pin GPIO pin number. + * @param index GPIO interrupt number. + */ +void GPIO_PinDisableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index) +{ + if (kGPIO_InterruptA == index) + { + base->INTENA[port] = base->INTENA[port] & ~(1U << pin); + } + else if (kGPIO_InterruptB == index) + { + base->INTENB[port] = base->INTENB[port] & ~(1U << pin); + } + else + { + /*Should not enter here*/ + } +} + +/*! + * @brief Clears the specific pin interrupt flag. Status flags are cleared by + * writing a 1 to the corresponding bit position. + * + * @param base GPIO base pointer. + * @param port GPIO port number. + * @param index GPIO interrupt number. + * @param mask GPIO pin number macro. + */ +void GPIO_PinClearInterruptFlag(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index) +{ + if (kGPIO_InterruptA == index) + { + base->INTSTATA[port] = 1U << pin; + } + else if (kGPIO_InterruptB == index) + { + base->INTSTATB[port] = 1U << pin; + } + else + { + /*Should not enter here*/ + } +} +#endif /* FSL_FEATURE_GPIO_HAS_INTERRUPT */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_gpio.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_gpio.h new file mode 100644 index 000000000..71c7091ec --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_gpio.h @@ -0,0 +1,365 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _LPC_GPIO_H_ +#define _LPC_GPIO_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup lpc_gpio + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief LPC GPIO driver version 2.1.3. */ +#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 1, 4)) +/*@}*/ + +/*! @brief LPC GPIO direction definition */ +typedef enum _gpio_pin_direction +{ + kGPIO_DigitalInput = 0U, /*!< Set current pin as digital input*/ + kGPIO_DigitalOutput = 1U, /*!< Set current pin as digital output*/ +} gpio_pin_direction_t; + +/*! + * @brief The GPIO pin configuration structure. + * + * Every pin can only be configured as either output pin or input pin at a time. + * If configured as a input pin, then leave the outputConfig unused. + */ +typedef struct _gpio_pin_config +{ + gpio_pin_direction_t pinDirection; /*!< GPIO direction, input or output */ + /* Output configurations, please ignore if configured as a input one */ + uint8_t outputLogic; /*!< Set default output logic, no use in input */ +} gpio_pin_config_t; + +#if (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT) && FSL_FEATURE_GPIO_HAS_INTERRUPT) +#define GPIO_PIN_INT_LEVEL 0x00U +#define GPIO_PIN_INT_EDGE 0x01U + +#define PINT_PIN_INT_HIGH_OR_RISE_TRIGGER 0x00U +#define PINT_PIN_INT_LOW_OR_FALL_TRIGGER 0x01U + +/*! @brief GPIO Pin Interrupt enable mode */ +typedef enum _gpio_pin_enable_mode +{ + kGPIO_PinIntEnableLevel = GPIO_PIN_INT_LEVEL, /*!< Generate Pin Interrupt on level mode */ + kGPIO_PinIntEnableEdge = GPIO_PIN_INT_EDGE /*!< Generate Pin Interrupt on edge mode */ +} gpio_pin_enable_mode_t; + +/*! @brief GPIO Pin Interrupt enable polarity */ +typedef enum _gpio_pin_enable_polarity +{ + kGPIO_PinIntEnableHighOrRise = + PINT_PIN_INT_HIGH_OR_RISE_TRIGGER, /*!< Generate Pin Interrupt on high level or rising edge */ + kGPIO_PinIntEnableLowOrFall = + PINT_PIN_INT_LOW_OR_FALL_TRIGGER /*!< Generate Pin Interrupt on low level or falling edge */ +} gpio_pin_enable_polarity_t; + +/*! @brief LPC GPIO interrupt index definition */ +typedef enum _gpio_interrupt_index +{ + kGPIO_InterruptA = 0U, /*!< Set current pin as interrupt A*/ + kGPIO_InterruptB = 1U, /*!< Set current pin as interrupt B*/ +} gpio_interrupt_index_t; + +/*! @brief Configures the interrupt generation condition. */ +typedef struct _gpio_interrupt_config +{ + uint8_t mode; /* The trigger mode of GPIO interrupts */ + uint8_t polarity; /* The polarity of GPIO interrupts */ +} gpio_interrupt_config_t; +#endif + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" +{ +#endif + +/*! @name GPIO Configuration */ +/*@{*/ + +/*! + * @brief Initializes the GPIO peripheral. + * + * This function ungates the GPIO clock. + * + * @param base GPIO peripheral base pointer. + * @param port GPIO port number. + */ +void GPIO_PortInit(GPIO_Type *base, uint32_t port); + +/*! + * @brief Initializes a GPIO pin used by the board. + * + * To initialize the GPIO, define a pin configuration, either input or output, in the user file. + * Then, call the GPIO_PinInit() function. + * + * This is an example to define an input pin or output pin configuration: + * @code + * // Define a digital input pin configuration, + * gpio_pin_config_t config = + * { + * kGPIO_DigitalInput, + * 0, + * } + * //Define a digital output pin configuration, + * gpio_pin_config_t config = + * { + * kGPIO_DigitalOutput, + * 0, + * } + * @endcode + * + * @param base GPIO peripheral base pointer(Typically GPIO) + * @param port GPIO port number + * @param pin GPIO pin number + * @param config GPIO pin configuration pointer + */ +void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_config_t *config); + +/*@}*/ + +/*! @name GPIO Output Operations */ +/*@{*/ + +/*! + * @brief Sets the output level of the one GPIO pin to the logic 1 or 0. + * + * @param base GPIO peripheral base pointer(Typically GPIO) + * @param port GPIO port number + * @param pin GPIO pin number + * @param output GPIO pin output logic level. + * - 0: corresponding pin output low-logic level. + * - 1: corresponding pin output high-logic level. + */ +static inline void GPIO_PinWrite(GPIO_Type *base, uint32_t port, uint32_t pin, uint8_t output) +{ + base->B[port][pin] = output; +} + +/*@}*/ +/*! @name GPIO Input Operations */ +/*@{*/ + +/*! + * @brief Reads the current input value of the GPIO PIN. + * + * @param base GPIO peripheral base pointer(Typically GPIO) + * @param port GPIO port number + * @param pin GPIO pin number + * @retval GPIO port input value + * - 0: corresponding pin input low-logic level. + * - 1: corresponding pin input high-logic level. + */ +static inline uint32_t GPIO_PinRead(GPIO_Type *base, uint32_t port, uint32_t pin) +{ + return (uint32_t)base->B[port][pin]; +} + +/*@}*/ + +/*! + * @brief Sets the output level of the multiple GPIO pins to the logic 1. + * + * @param base GPIO peripheral base pointer(Typically GPIO) + * @param port GPIO port number + * @param mask GPIO pin number macro + */ +static inline void GPIO_PortSet(GPIO_Type *base, uint32_t port, uint32_t mask) +{ + base->SET[port] = mask; +} + +/*! + * @brief Sets the output level of the multiple GPIO pins to the logic 0. + * + * @param base GPIO peripheral base pointer(Typically GPIO) + * @param port GPIO port number + * @param mask GPIO pin number macro + */ +static inline void GPIO_PortClear(GPIO_Type *base, uint32_t port, uint32_t mask) +{ + base->CLR[port] = mask; +} + +/*! + * @brief Reverses current output logic of the multiple GPIO pins. + * + * @param base GPIO peripheral base pointer(Typically GPIO) + * @param port GPIO port number + * @param mask GPIO pin number macro + */ +static inline void GPIO_PortToggle(GPIO_Type *base, uint32_t port, uint32_t mask) +{ + base->NOT[port] = mask; +} + +/*@}*/ + +/*! + * @brief Reads the current input value of the whole GPIO port. + * + * @param base GPIO peripheral base pointer(Typically GPIO) + * @param port GPIO port number + */ +static inline uint32_t GPIO_PortRead(GPIO_Type *base, uint32_t port) +{ + return (uint32_t)base->PIN[port]; +} + +/*@}*/ +/*! @name GPIO Mask Operations */ +/*@{*/ + +/*! + * @brief Sets port mask, 0 - enable pin, 1 - disable pin. + * + * @param base GPIO peripheral base pointer(Typically GPIO) + * @param port GPIO port number + * @param mask GPIO pin number macro + */ +static inline void GPIO_PortMaskedSet(GPIO_Type *base, uint32_t port, uint32_t mask) +{ + base->MASK[port] = mask; +} + +/*! + * @brief Sets the output level of the masked GPIO port. Only pins enabled by GPIO_SetPortMask() will be affected. + * + * @param base GPIO peripheral base pointer(Typically GPIO) + * @param port GPIO port number + * @param output GPIO port output value. + */ +static inline void GPIO_PortMaskedWrite(GPIO_Type *base, uint32_t port, uint32_t output) +{ + base->MPIN[port] = output; +} + +/*! + * @brief Reads the current input value of the masked GPIO port. Only pins enabled by GPIO_SetPortMask() will be + * affected. + * + * @param base GPIO peripheral base pointer(Typically GPIO) + * @param port GPIO port number + * @retval masked GPIO port value + */ +static inline uint32_t GPIO_PortMaskedRead(GPIO_Type *base, uint32_t port) +{ + return (uint32_t)base->MPIN[port]; +} + +#if defined(FSL_FEATURE_GPIO_HAS_INTERRUPT) && FSL_FEATURE_GPIO_HAS_INTERRUPT +/*! + * @brief Configures the gpio pin interrupt. + * + * @param base GPIO base pointer. + * @param port GPIO port number + * @param pin GPIO pin number. + * @param config GPIO pin interrupt configuration.. + */ +void GPIO_SetPinInterruptConfig(GPIO_Type *base, uint32_t port, uint32_t pin, gpio_interrupt_config_t *config); + +/*! + * @brief Enables multiple pins interrupt. + * + * @param base GPIO base pointer. + * @param port GPIO port number. + * @param index GPIO interrupt number. + * @param mask GPIO pin number macro. + */ +void GPIO_PortEnableInterrupts(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask); + +/*! + * @brief Disables multiple pins interrupt. + * + * @param base GPIO base pointer. + * @param port GPIO port number. + * @param index GPIO interrupt number. + * @param mask GPIO pin number macro. + */ +void GPIO_PortDisableInterrupts(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask); + +/*! + * @brief Clears pin interrupt flag. Status flags are cleared by + * writing a 1 to the corresponding bit position. + * + * @param base GPIO base pointer. + * @param port GPIO port number. + * @param index GPIO interrupt number. + * @param mask GPIO pin number macro. + */ +void GPIO_PortClearInterruptFlags(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask); + +/*! + * @ Read port interrupt status. + * + * @param base GPIO base pointer. + * @param port GPIO port number + * @param index GPIO interrupt number. + * @retval masked GPIO status value + */ +uint32_t GPIO_PortGetInterruptStatus(GPIO_Type *base, uint32_t port, uint32_t index); + +/*! + * @brief Enables the specific pin interrupt. + * + * @param base GPIO base pointer. + * @param port GPIO port number. + * @param pin GPIO pin number. + * @param index GPIO interrupt number. + */ +void GPIO_PinEnableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index); + +/*! + * @brief Disables the specific pin interrupt. + * + * @param base GPIO base pointer. + * @param port GPIO port number. + * @param pin GPIO pin number. + * @param index GPIO interrupt number. + */ +void GPIO_PinDisableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index); + +/*! + * @brief Clears the specific pin interrupt flag. Status flags are cleared by + * writing a 1 to the corresponding bit position. + * + * @param base GPIO base pointer. + * @param port GPIO port number. + * @param pin GPIO pin number. + * @param index GPIO interrupt number. + */ +void GPIO_PinClearInterruptFlag(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index); + +#endif /* FSL_FEATURE_GPIO_HAS_INTERRUPT */ + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ + +#endif /* _LPC_GPIO_H_*/ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_hashcrypt.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_hashcrypt.c new file mode 100644 index 000000000..b90a6a906 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_hashcrypt.c @@ -0,0 +1,1198 @@ +/* + * Copyright 2017-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_hashcrypt.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.hashcrypt" +#endif + +/******************************************************************************* + * Definitions + *******************************************************************************/ + +/*!< SHA-1 and SHA-256 block size */ +#define SHA_BLOCK_SIZE 64 +/*!< max number of blocks that can be proccessed in one run (master mode) */ +#define SHA_MASTER_MAX_BLOCKS 2048 + +/*!< Use standard C library memcpy */ +#define hashcrypt_memcpy memcpy + +/*! Internal states of the HASH creation process */ +typedef enum _hashcrypt_sha_algo_state +{ + kHASHCRYPT_HashInit = 1u, /*!< Init state, the NEW bit in SHA Control register has not been written yet. */ + kHASHCRYPT_HashUpdate, /*!< Update state, DIGEST registers contain running hash, NEW bit in SHA control register has + been written. */ +} hashcrypt_sha_algo_state_t; + +/*! 64-byte block represented as byte array of 16 32-bit words */ +typedef union _sha_hash_block +{ + uint32_t w[SHA_BLOCK_SIZE / 4]; /*!< array of 32-bit words */ + uint8_t b[SHA_BLOCK_SIZE]; /*!< byte array */ +} hashcrypt_sha_block_t; + +/*! internal sha context structure */ +typedef struct _hashcrypt_sha_ctx_internal +{ + hashcrypt_sha_block_t blk; /*!< memory buffer. only full 64-byte blocks are written to SHA during hash updates */ + size_t blksz; /*!< number of valid bytes in memory buffer */ + hashcrypt_algo_t algo; /*!< selected algorithm from the set of supported algorithms */ + hashcrypt_sha_algo_state_t state; /*!< finite machine state of the hash software process */ + size_t fullMessageSize; /*!< track message size during SHA_Update(). The value is used for padding. */ + uint32_t remainingBlcks; /*!< number of remaining blocks to process in AHB master mode */ + hashcrypt_callback_t hashCallback; /*!< pointer to HASH callback function */ + void + *userData; /*!< user data to be passed as an argument to callback function, once callback is invoked from isr */ +} hashcrypt_sha_ctx_internal_t; + +/*!< SHA-1 and SHA-256 digest length in bytes */ +enum _hashcrypt_sha_digest_len +{ + kHASHCRYPT_OutLenSha1 = 20u, + kHASHCRYPT_OutLenSha256 = 32u, +}; + +/*!< pointer to hash context structure used by isr */ +static hashcrypt_hash_ctx_t *s_ctx; + +/*!< macro for checking build time condition. It is used to assure the hashcrypt_sha_ctx_internal_t can fit into + * hashcrypt_hash_ctx_t */ +#define BUILD_ASSERT(condition, msg) extern int msg[1 - 2 * (!(condition))] __attribute__((unused)) + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * @brief Swap bytes withing 32-bit word. + * + * This function changes endianess of a 32-bit word. + * + * @param in 32-bit unsigned integer + * @return 32-bit unsigned integer with different endianess (big endian to little endian and vice versa). + */ + +#define swap_bytes(in) __REV(in) + +/*! + * @brief Increment a 16 byte integer. + * + * This function increments by one a 16 byte integer. + * + * @param input Pointer to a 16 byte integer to be incremented by one. + */ +static void ctrIncrement(uint8_t *input) +{ + int i = 15; + while (input[i] == (uint8_t)0xFFu) + { + input[i] = (uint8_t)0x00u; + i--; + if (i < 0) + { + return; + } + } + + if (i >= 0) + { + input[i] += (uint8_t)1u; + } +} + +/*! + * @brief Reads an unaligned word. + * + * This function creates a 32-bit word from an input array of four bytes. + * + * @param src Input array of four bytes. The array can start at any address in memory. + * @return 32-bit unsigned int created from the input byte array. + */ + +/* Force lower optimization for Keil, otherwise it replaces inline LDR with LDM */ +#if defined(__CC_ARM) +#pragma push +#pragma O0 +#endif + +static inline uint32_t hashcrypt_get_word_from_unaligned(const uint8_t *srcAddr) +{ +#if (!(defined(__CORTEX_M)) || (defined(__CORTEX_M) && (__CORTEX_M == 0))) + register const uint8_t *src = srcAddr; + /* Cortex M0 does not support misaligned loads */ + if (0U != ((uint32_t)src & 0x3u)) + { + union _align_bytes_t + { + uint32_t word; + uint8_t byte[sizeof(uint32_t)]; + } my_bytes; + + my_bytes.byte[0] = *src; + my_bytes.byte[1] = src[1]; + my_bytes.byte[2] = src[2]; + my_bytes.byte[3] = src[3]; + return my_bytes.word; + } + else + { + /* addr aligned to 0-modulo-4 so it is safe to type cast */ + return *((const uint32_t *)(uint32_t)src); + } +#elif defined(__CC_ARM) + /* -O3 optimization in Keil 5.15 and 5.16a uses LDM instruction here (LDM r4!, {r0}) + * which is wrong, because srcAddr might be unaligned. + * LDM on unaligned address causes hard-fault. in contrary, + * LDR supports unaligned address on Cortex M4 */ + + register uint32_t retVal; + __asm + { + LDR retVal, [srcAddr] + } + return retVal; +#else + return *((const uint32_t *)srcAddr); +#endif +} + +/* End lower optimization */ +#if defined(__CC_ARM) +#pragma pop +#endif + +static status_t hashcrypt_get_key_from_unaligned_src(uint8_t *dest, const uint8_t *src, size_t size) +{ + status_t retVal = kStatus_InvalidArgument; + uint32_t i; + + /* destination is SDK driver internal workspace and it must be aligned */ + assert(0x0 == ((uint32_t)dest & 0x1u)); + if ((uint32_t)dest & 0x1u) + { + return retVal; + } + + for (i = 0; i < ((uint32_t)size / 4u); i++) + { + ((uint32_t *)dest)[i] = hashcrypt_get_word_from_unaligned(&src[i * sizeof(uint32_t)]); + } + + return kStatus_Success; +} + +/*! + * @brief LDM to SHA engine INDATA and ALIAS registers. + * + * This function writes 16 words starting from the src address (must be word aligned) + * to the dst address. Dst address does not increment (destination is peripheral module register INDATA). + * Src address increments to load 16 consecutive words. + * + * @param dst peripheral register address (word aligned) + * @param src address of the input 512-bit block (16 words) (word aligned) + * + */ +__STATIC_FORCEINLINE void hashcrypt_sha_ldm_stm_16_words(HASHCRYPT_Type *base, const uint32_t *src) +{ + /* + typedef struct _one_block + { + uint32_t a[8]; + } one_block_t; + + volatile one_block_t *ldst = (void *)(uintptr_t)(&base->INDATA); + one_block_t *lsrc = (void *)(uintptr_t)src; + *ldst = lsrc[0]; + *ldst = lsrc[1]; + */ + base->MEMADDR = HASHCRYPT_MEMADDR_BASE(src); + base->MEMCTRL = HASHCRYPT_MEMCTRL_MASTER(1) | HASHCRYPT_MEMCTRL_COUNT(1); +} + +/*! + * @brief Loads data to Hashcrypt engine INDATA register. + * + * This function writes desired number of bytes starting from the src address (must be word aligned) + * to the dst address. Dst address does not increment (destination is peripheral module register INDATA). + * Src address increments to load consecutive words. + * + * @param dst peripheral register address (word aligned) + * @param src address of the input block (word aligned) + * @param size number of bytes to write (word aligned) + * + */ +__STATIC_INLINE void hashcrypt_load_data(HASHCRYPT_Type *base, const uint32_t *src, size_t size) +{ + if (size >= sizeof(uint32_t)) + { + base->INDATA = src[0]; + size -= sizeof(uint32_t); + } + + for (int i = 0; i < size / 4; i++) + { + base->ALIAS[i] = src[i + 1]; + } +} + +/*! + * @brief Read OUTDATA registers. + * + * This function copies OUTDATA to output buffer. + * + * @param base Hachcrypt peripheral base address. + * @param[out] output Output buffer. + * @param Number of bytes to copy. + */ +static void hashcrypt_get_data(HASHCRYPT_Type *base, uint32_t *output, size_t outputSize) +{ + uint32_t digest[8]; + + while (0 == (base->STATUS & HASHCRYPT_STATUS_DIGEST_AKA_OUTDATA_MASK)) + { + } + + for (int i = 0; i < 8; i++) + { + digest[i] = swap_bytes(base->OUTDATA0[i]); + } + + if (outputSize > sizeof(digest)) + { + outputSize = sizeof(digest); + } + hashcrypt_memcpy(output, digest, outputSize); +} + +/*! + * @brief Initialize the Hashcrypt engine for new operation. + * + * This function sets NEW and MODE fields in Hashcrypt Control register to start new operation. + * + * @param base Hashcrypt peripheral base address. + * @param hashcrypt_algo_t Internal context. + */ +static void hashcrypt_engine_init(HASHCRYPT_Type *base, hashcrypt_algo_t algo) +{ + /* NEW bit must be set before we switch from previous mode otherwise new mode will not work correctly */ + base->CTRL = HASHCRYPT_CTRL_NEW_HASH(1); + base->CTRL = HASHCRYPT_CTRL_MODE(algo) | HASHCRYPT_CTRL_NEW_HASH(1); +} + +/*! + * @brief Loads user key to INDATA register. + * + * This function writes user key stored in handle into HashCrypt INDATA register. + * + * @param base Hashcrypt peripheral base address. + * @param handle Handle used for this request. + */ +static void hashcrypt_aes_load_userKey(HASHCRYPT_Type *base, hashcrypt_handle_t *handle) +{ + size_t keySize = 0; + + switch (handle->keySize) + { + case kHASHCRYPT_Aes128: + keySize = 16; + break; + case kHASHCRYPT_Aes192: + keySize = 24; + break; + case kHASHCRYPT_Aes256: + keySize = 32; + break; + default: + break; + } + if (keySize == 0) + { + return; + } + hashcrypt_load_data(base, &handle->keyWord[0], keySize); +} + +/*! + * @brief Performs AES encryption/decryption of one data block. + * + * This function encrypts/decrypts one block of data with specified size. + * + * @param base Hashcrypt peripheral base address. + * @param input input data + * @param output output data + * @param size size of data block to process in bytes (must be 16bytes multiple). + */ +static status_t hashcrypt_aes_one_block(HASHCRYPT_Type *base, const uint8_t *input, uint8_t *output, size_t size) +{ + status_t status = kStatus_Fail; + int idx = 0; + + /* we use AHB master mode as much as possible */ + /* however, it can work only with aligned input data */ + /* so, if unaligned, we do memcpy to temp buffer on stack, which is aligned, and use AHB mode to read data in */ + /* then we read data back to it and do memcpy to the output buffer */ + if (((uint32_t)input & 0x3u) || ((uint32_t)output & 0x3u)) + { + uint32_t temp[256 / sizeof(uint32_t)]; + int cnt = 0; + while (size) + { + size_t actSz = size >= 256u ? 256u : size; + size_t actSzOrig = actSz; + memcpy(temp, input + 256 * cnt, actSz); + size -= actSz; + base->MEMADDR = HASHCRYPT_MEMADDR_BASE(temp); + base->MEMCTRL = HASHCRYPT_MEMCTRL_MASTER(1) | HASHCRYPT_MEMCTRL_COUNT(actSz / 16); + int outidx = 0; + while (actSz) + { + while (0 == (base->STATUS & HASHCRYPT_STATUS_DIGEST_AKA_OUTDATA_MASK)) + { + } + for (int i = 0; i < 4; i++) + { + (temp + outidx)[i] = swap_bytes(base->OUTDATA0[i]); + } + outidx += HASHCRYPT_AES_BLOCK_SIZE / 4; + actSz -= HASHCRYPT_AES_BLOCK_SIZE; + } + memcpy(output + 256 * cnt, temp, actSzOrig); + cnt++; + } + } + else + { + base->MEMADDR = HASHCRYPT_MEMADDR_BASE(input); + base->MEMCTRL = HASHCRYPT_MEMCTRL_MASTER(1) | HASHCRYPT_MEMCTRL_COUNT(size / 16); + while (size >= HASHCRYPT_AES_BLOCK_SIZE) + { + /* Get result */ + while (0 == (base->STATUS & HASHCRYPT_STATUS_DIGEST_AKA_OUTDATA_MASK)) + { + } + + for (int i = 0; i < 4; i++) + { + ((uint32_t *)output + idx)[i] = swap_bytes(base->OUTDATA0[i]); + } + + idx += HASHCRYPT_AES_BLOCK_SIZE / 4; + size -= HASHCRYPT_AES_BLOCK_SIZE; + } + } + + if (0 == (base->STATUS & HASHCRYPT_STATUS_ERROR_MASK)) + { + status = kStatus_Success; + } + + return status; +} + +/*! + * @brief Check validity of algoritm. + * + * This function checks the validity of input argument. + * + * @param algo Tested algorithm value. + * @return kStatus_Success if valid, kStatus_InvalidArgument otherwise. + */ +static status_t hashcrypt_sha_check_input_alg(HASHCRYPT_Type *base, hashcrypt_algo_t algo) +{ + if ((algo == kHASHCRYPT_Sha1) || (algo == kHASHCRYPT_Sha256)) + { + return kStatus_Success; + } + + if ((algo == kHASHCRYPT_Sha512) && (base->CONFIG & HASHCRYPT_CONFIG_SHA512_MASK)) + { + return kStatus_Success; + } + + return kStatus_InvalidArgument; +} + +/*! + * @brief Check validity of input arguments. + * + * This function checks the validity of input arguments. + * + * @param base SHA peripheral base address. + * @param ctx Memory buffer given by user application where the SHA_Init/SHA_Update/SHA_Finish store context. + * @param algo Tested algorithm value. + * @return kStatus_Success if valid, kStatus_InvalidArgument otherwise. + */ +static status_t hashcrypt_sha_check_input_args(HASHCRYPT_Type *base, hashcrypt_hash_ctx_t *ctx, hashcrypt_algo_t algo) +{ + /* Check validity of input algorithm */ + if (kStatus_Success != hashcrypt_sha_check_input_alg(base, algo)) + { + return kStatus_InvalidArgument; + } + + if ((NULL == ctx) || (NULL == base)) + { + return kStatus_InvalidArgument; + } + + return kStatus_Success; +} + +/*! + * @brief Check validity of internal software context. + * + * This function checks if the internal context structure looks correct. + * + * @param ctxInternal Internal context. + * @return kStatus_Success if valid, kStatus_InvalidArgument otherwise. + */ +static status_t hashcrypt_sha_check_context(HASHCRYPT_Type *base, hashcrypt_sha_ctx_internal_t *ctxInternal) +{ + if ((NULL == ctxInternal) || (kStatus_Success != hashcrypt_sha_check_input_alg(base, ctxInternal->algo))) + { + return kStatus_InvalidArgument; + } + return kStatus_Success; +} + +/*! + * @brief Load 512-bit block (16 words) into SHA engine. + * + * This function aligns the input block and moves it into SHA engine INDATA. + * CPU polls the WAITING bit and then moves data by using LDM and STM instructions. + * + * @param base SHA peripheral base address. + * @param blk 512-bit block + */ +static void hashcrypt_sha_one_block(HASHCRYPT_Type *base, const uint8_t *blk) +{ + uint32_t temp[SHA_BLOCK_SIZE / sizeof(uint32_t)]; + const uint32_t *actBlk; + + /* make sure the 512-bit block is word aligned */ + if ((uintptr_t)blk & 0x3u) + { + hashcrypt_memcpy(temp, blk, SHA_BLOCK_SIZE); + actBlk = (const uint32_t *)(uintptr_t)temp; + } + else + { + actBlk = (const uint32_t *)(uintptr_t)blk; + } + + /* poll waiting. */ + while (0 == (base->STATUS & HASHCRYPT_STATUS_WAITING_MASK)) + { + } + /* feed INDATA (and ALIASes). use STM instruction. */ + hashcrypt_sha_ldm_stm_16_words(base, actBlk); +} + +/*! + * @brief Adds message to current hash. + * + * This function merges the message to fill the internal buffer, empties the internal buffer if + * it becomes full, then process all remaining message data. + * + * + * @param base SHA peripheral base address. + * @param ctxInternal Internal context. + * @param message Input message. + * @param messageSize Size of input message in bytes. + * @return kStatus_Success. + */ +static status_t hashcrypt_sha_process_message_data(HASHCRYPT_Type *base, + hashcrypt_sha_ctx_internal_t *ctxInternal, + const uint8_t *message, + size_t messageSize) +{ + /* first fill the internal buffer to full block */ + if (ctxInternal->blksz) + { + size_t toCopy = SHA_BLOCK_SIZE - ctxInternal->blksz; + hashcrypt_memcpy(&ctxInternal->blk.b[ctxInternal->blksz], message, toCopy); + message += toCopy; + messageSize -= toCopy; + + /* process full internal block */ + hashcrypt_sha_one_block(base, &ctxInternal->blk.b[0]); + } + + /* process all full blocks in message[] */ + if (messageSize >= SHA_BLOCK_SIZE) + { + if ((uintptr_t)message & 0x3u) + { + while (messageSize >= SHA_BLOCK_SIZE) + { + hashcrypt_sha_one_block(base, message); + message += SHA_BLOCK_SIZE; + messageSize -= SHA_BLOCK_SIZE; + } + } + else + { + /* poll waiting. */ + while (0 == (base->STATUS & HASHCRYPT_STATUS_WAITING_MASK)) + { + } + uint32_t blkNum = (messageSize >> 6); /* div by 64 bytes */ + uint32_t blkBytes = blkNum * 64u; /* number of bytes in 64 bytes blocks */ + base->MEMADDR = HASHCRYPT_MEMADDR_BASE(message); + base->MEMCTRL = HASHCRYPT_MEMCTRL_MASTER(1) | HASHCRYPT_MEMCTRL_COUNT(blkNum); + message += blkBytes; + messageSize -= blkBytes; + while (0 == (base->STATUS & HASHCRYPT_STATUS_DIGEST_AKA_OUTDATA_MASK)) + { + } + } + } + + /* copy last incomplete message bytes into internal block */ + hashcrypt_memcpy(&ctxInternal->blk.b[0], message, messageSize); + ctxInternal->blksz = messageSize; + return kStatus_Success; +} + +/*! + * @brief Finalize the running hash to make digest. + * + * This function empties the internal buffer, adds padding bits, and generates final digest. + * + * @param base SHA peripheral base address. + * @param ctxInternal Internal context. + * @return kStatus_Success. + */ +static status_t hashcrypt_sha_finalize(HASHCRYPT_Type *base, hashcrypt_sha_ctx_internal_t *ctxInternal) +{ + hashcrypt_sha_block_t lastBlock; + + memset(&lastBlock, 0, sizeof(hashcrypt_sha_block_t)); + + /* this is last call, so need to flush buffered message bytes along with padding */ + if (ctxInternal->blksz <= 55u) + { + /* last data is 440 bits or less. */ + hashcrypt_memcpy(&lastBlock.b[0], &ctxInternal->blk.b[0], ctxInternal->blksz); + lastBlock.b[ctxInternal->blksz] = (uint8_t)0x80U; + lastBlock.w[SHA_BLOCK_SIZE / 4 - 1] = swap_bytes(8u * ctxInternal->fullMessageSize); + hashcrypt_sha_one_block(base, &lastBlock.b[0]); + } + else + { + if (ctxInternal->blksz < SHA_BLOCK_SIZE) + { + ctxInternal->blk.b[ctxInternal->blksz] = (uint8_t)0x80U; + for (uint32_t i = ctxInternal->blksz + 1u; i < SHA_BLOCK_SIZE; i++) + { + ctxInternal->blk.b[i] = 0; + } + } + else + { + lastBlock.b[0] = (uint8_t)0x80U; + } + + hashcrypt_sha_one_block(base, &ctxInternal->blk.b[0]); + lastBlock.w[SHA_BLOCK_SIZE / 4 - 1] = swap_bytes(8u * ctxInternal->fullMessageSize); + hashcrypt_sha_one_block(base, &lastBlock.b[0]); + } + /* poll wait for final digest */ + while (0 == (base->STATUS & HASHCRYPT_STATUS_DIGEST_AKA_OUTDATA_MASK)) + { + } + return kStatus_Success; +} + +status_t HASHCRYPT_SHA(HASHCRYPT_Type *base, + hashcrypt_algo_t algo, + const uint8_t *input, + size_t inputSize, + uint8_t *output, + size_t *outputSize) +{ + hashcrypt_hash_ctx_t hashCtx; + status_t status; + + status = HASHCRYPT_SHA_Init(base, &hashCtx, algo); + if (status != kStatus_Success) + { + return status; + } + + status = HASHCRYPT_SHA_Update(base, &hashCtx, input, inputSize); + if (status != kStatus_Success) + { + return status; + } + + status = HASHCRYPT_SHA_Finish(base, &hashCtx, output, outputSize); + + return status; +} + +status_t HASHCRYPT_SHA_Init(HASHCRYPT_Type *base, hashcrypt_hash_ctx_t *ctx, hashcrypt_algo_t algo) +{ + status_t status; + + hashcrypt_sha_ctx_internal_t *ctxInternal; + /* compile time check for the correct structure size */ + BUILD_ASSERT(sizeof(hashcrypt_hash_ctx_t) >= sizeof(hashcrypt_sha_ctx_internal_t), hashcrypt_hash_ctx_t_size); + + status = hashcrypt_sha_check_input_args(base, ctx, algo); + if (status != kStatus_Success) + { + return status; + } + + /* set algorithm in context struct for later use */ + ctxInternal = (hashcrypt_sha_ctx_internal_t *)ctx; + ctxInternal->algo = algo; + ctxInternal->blksz = 0u; +#ifdef HASHCRYPT_SHA_DO_WIPE_CONTEXT + for (int i = 0; i < sizeof(ctxInternal->blk.w) / sizeof(ctxInternal->blk.w[0]); i++) + { + ctxInternal->blk.w[i] = 0u; + } +#endif /* HASHCRYPT_SHA_DO_WIPE_CONTEXT */ + ctxInternal->state = kHASHCRYPT_HashInit; + ctxInternal->fullMessageSize = 0; + return kStatus_Success; +} + +status_t HASHCRYPT_SHA_Update(HASHCRYPT_Type *base, hashcrypt_hash_ctx_t *ctx, const uint8_t *input, size_t inputSize) +{ + bool isUpdateState; + status_t status; + hashcrypt_sha_ctx_internal_t *ctxInternal; + size_t blockSize; + + if (inputSize == 0) + { + return kStatus_Success; + } + + ctxInternal = (hashcrypt_sha_ctx_internal_t *)ctx; +#ifdef HASHCRYPT_SHA_DO_CHECK_CONTEXT + status = hashcrypt_sha_check_context(base, ctxInternal); + if (kStatus_Success != status) + { + return status; + } +#endif /* HASHCRYPT_SHA_DO_CHECK_CONTEXT */ + + ctxInternal->fullMessageSize += inputSize; + blockSize = SHA_BLOCK_SIZE; + /* if we are still less than 64 bytes, keep only in context */ + if ((ctxInternal->blksz + inputSize) <= blockSize) + { + hashcrypt_memcpy((&ctxInternal->blk.b[0]) + ctxInternal->blksz, input, inputSize); + ctxInternal->blksz += inputSize; + return kStatus_Success; + } + else + { + isUpdateState = ctxInternal->state == kHASHCRYPT_HashUpdate; + if (!isUpdateState) + { + /* start NEW hash */ + hashcrypt_engine_init(base, ctxInternal->algo); + ctxInternal->state = kHASHCRYPT_HashUpdate; + } + } + + /* process message data */ + status = hashcrypt_sha_process_message_data(base, ctxInternal, input, inputSize); + return status; +} + +status_t HASHCRYPT_SHA_Finish(HASHCRYPT_Type *base, hashcrypt_hash_ctx_t *ctx, uint8_t *output, size_t *outputSize) +{ + size_t algOutSize = 0; + status_t status; + hashcrypt_sha_ctx_internal_t *ctxInternal; +#ifdef HASHCRYPT_SHA_DO_CHECK_CONTEXT + uint32_t *ctxW; + uint32_t i; +#endif /* HASHCRYPT_SHA_DO_CHECK_CONTEXT */ + + if (output == NULL) + { + return kStatus_InvalidArgument; + } + + ctxInternal = (hashcrypt_sha_ctx_internal_t *)ctx; +#ifdef HASHCRYPT_SHA_DO_CHECK_CONTEXT + status = hashcrypt_sha_check_context(base, ctxInternal); + if (kStatus_Success != status) + { + return status; + } +#endif /* HASHCRYPT_SHA_DO_CHECK_CONTEXT */ + + if (ctxInternal->state == kHASHCRYPT_HashInit) + { + hashcrypt_engine_init(base, ctxInternal->algo); + } + + size_t outSize = 0u; + + /* compute algorithm output length */ + switch (ctxInternal->algo) + { + case kHASHCRYPT_Sha1: + outSize = kHASHCRYPT_OutLenSha1; + break; + case kHASHCRYPT_Sha256: + outSize = kHASHCRYPT_OutLenSha256; + break; + default: + break; + } + algOutSize = outSize; + + /* flush message last incomplete block, if there is any, and add padding bits */ + status = hashcrypt_sha_finalize(base, ctxInternal); + + if (outputSize) + { + if (algOutSize < *outputSize) + { + *outputSize = algOutSize; + } + else + { + algOutSize = *outputSize; + } + } + + hashcrypt_get_data(base, (uint32_t *)output, algOutSize); + +#ifdef HASHCRYPT_SHA_DO_WIPE_CONTEXT + ctxW = (uint32_t *)ctx; + for (i = 0; i < HASHCRYPT_HASH_CTX_SIZE; i++) + { + ctxW[i] = 0u; + } +#endif /* HASHCRYPT_SHA_DO_WIPE_CONTEXT */ + return status; +} + +void HASHCRYPT_SHA_SetCallback(HASHCRYPT_Type *base, + hashcrypt_hash_ctx_t *ctx, + hashcrypt_callback_t callback, + void *userData) +{ + hashcrypt_sha_ctx_internal_t *ctxInternal; + + s_ctx = ctx; + ctxInternal = (hashcrypt_sha_ctx_internal_t *)ctx; + ctxInternal->hashCallback = callback; + ctxInternal->userData = userData; + + EnableIRQ(HASHCRYPT_IRQn); +} + +status_t HASHCRYPT_SHA_UpdateNonBlocking(HASHCRYPT_Type *base, + hashcrypt_hash_ctx_t *ctx, + const uint8_t *input, + size_t inputSize) +{ + hashcrypt_sha_ctx_internal_t *ctxInternal; + uint32_t numBlocks; + status_t status; + + if (inputSize == 0) + { + return kStatus_Success; + } + + if ((uintptr_t)input & 0x3U) + { + return kStatus_Fail; + } + + ctxInternal = (hashcrypt_sha_ctx_internal_t *)ctx; + status = hashcrypt_sha_check_context(base, ctxInternal); + if (kStatus_Success != status) + { + return status; + } + + ctxInternal->fullMessageSize = inputSize; + ctxInternal->remainingBlcks = inputSize / SHA_BLOCK_SIZE; + ctxInternal->blksz = inputSize % SHA_BLOCK_SIZE; + + /* copy last incomplete block to context */ + if ((ctxInternal->blksz > 0) && (ctxInternal->blksz <= SHA_BLOCK_SIZE)) + { + hashcrypt_memcpy((&ctxInternal->blk.b[0]), input + SHA_BLOCK_SIZE * ctxInternal->remainingBlcks, + ctxInternal->blksz); + } + + if (ctxInternal->remainingBlcks >= SHA_MASTER_MAX_BLOCKS) + { + numBlocks = SHA_MASTER_MAX_BLOCKS - 1; + } + else + { + numBlocks = ctxInternal->remainingBlcks; + } + /* update remainingBlks so that ISR can run another hash if necessary */ + ctxInternal->remainingBlcks -= numBlocks; + + /* compute hash using AHB Master mode for full blocks */ + if (numBlocks > 0) + { + ctxInternal->state = kHASHCRYPT_HashUpdate; + hashcrypt_engine_init(base, ctxInternal->algo); + + /* Enable digest and error interrupts and start hash */ + base->INTENSET = HASHCRYPT_INTENCLR_DIGEST_MASK | HASHCRYPT_INTENCLR_ERROR_MASK; + base->MEMADDR = HASHCRYPT_MEMADDR_BASE(input); + base->MEMCTRL = HASHCRYPT_MEMCTRL_MASTER(1) | HASHCRYPT_MEMCTRL_COUNT(numBlocks); + } + /* no full blocks, invoke callback directly */ + else + { + ctxInternal->hashCallback(HASHCRYPT, ctx, status, ctxInternal->userData); + } + + return status; +} + +status_t HASHCRYPT_AES_SetKey(HASHCRYPT_Type *base, hashcrypt_handle_t *handle, const uint8_t *key, size_t keySize) +{ + status_t retVal = kStatus_InvalidArgument; + + switch (keySize) + { + case 16: + handle->keySize = kHASHCRYPT_Aes128; + break; + case 24: + handle->keySize = kHASHCRYPT_Aes192; + break; + case 32: + handle->keySize = kHASHCRYPT_Aes256; + break; + default: + handle->keySize = kHASHCRYPT_InvalidKey; + break; + } + + if (handle->keySize == kHASHCRYPT_InvalidKey) + { + return retVal; + } + + if (handle->keyType == kHASHCRYPT_SecretKey) + { + /* for kHASHCRYPT_SecretKey just return Success */ + retVal = kStatus_Success; + } + else if (handle->keyType == kHASHCRYPT_UserKey) + { + retVal = hashcrypt_get_key_from_unaligned_src((uint8_t *)&handle->keyWord[0], key, keySize); + } + else + { + retVal = kStatus_InvalidArgument; + } + + return retVal; +} + +status_t HASHCRYPT_AES_EncryptEcb( + HASHCRYPT_Type *base, hashcrypt_handle_t *handle, const uint8_t *plaintext, uint8_t *ciphertext, size_t size) +{ + status_t status = kStatus_Fail; + + if ((size % 16u) || (handle->keySize == kHASHCRYPT_InvalidKey)) + { + return kStatus_InvalidArgument; + } + + uint32_t keyType = (handle->keyType == kHASHCRYPT_UserKey) ? 0 : 1u; + base->CRYPTCFG = HASHCRYPT_CRYPTCFG_AESMODE(kHASHCRYPT_AesEcb) | HASHCRYPT_CRYPTCFG_AESDECRYPT(AES_ENCRYPT) | + HASHCRYPT_CRYPTCFG_AESSECRET(keyType) | HASHCRYPT_CRYPTCFG_AESKEYSZ(handle->keySize) | + HASHCRYPT_CRYPTCFG_MSW1ST_OUT(1) | HASHCRYPT_CRYPTCFG_SWAPKEY(1) | HASHCRYPT_CRYPTCFG_SWAPDAT(1) | + HASHCRYPT_CRYPTCFG_MSW1ST(1); + + hashcrypt_engine_init(base, kHASHCRYPT_Aes); + + /* load key if kHASHCRYPT_UserKey is selected */ + if (handle->keyType == kHASHCRYPT_UserKey) + { + hashcrypt_aes_load_userKey(base, handle); + } + + /* load message and get result */ + status = hashcrypt_aes_one_block(base, plaintext, ciphertext, size); + + return status; +} + +status_t HASHCRYPT_AES_DecryptEcb( + HASHCRYPT_Type *base, hashcrypt_handle_t *handle, const uint8_t *ciphertext, uint8_t *plaintext, size_t size) +{ + status_t status = kStatus_Fail; + + if ((size % 16u) || (handle->keySize == kHASHCRYPT_InvalidKey)) + { + return kStatus_InvalidArgument; + } + + uint32_t keyType = (handle->keyType == kHASHCRYPT_UserKey) ? 0 : 1u; + base->CRYPTCFG = HASHCRYPT_CRYPTCFG_AESMODE(kHASHCRYPT_AesEcb) | HASHCRYPT_CRYPTCFG_AESDECRYPT(AES_DECRYPT) | + HASHCRYPT_CRYPTCFG_AESSECRET(keyType) | HASHCRYPT_CRYPTCFG_AESKEYSZ(handle->keySize) | + HASHCRYPT_CRYPTCFG_MSW1ST_OUT(1) | HASHCRYPT_CRYPTCFG_SWAPKEY(1) | HASHCRYPT_CRYPTCFG_SWAPDAT(1) | + HASHCRYPT_CRYPTCFG_MSW1ST(1); + + hashcrypt_engine_init(base, kHASHCRYPT_Aes); + + /* load key if kHASHCRYPT_UserKey is selected */ + if (handle->keyType == kHASHCRYPT_UserKey) + { + hashcrypt_aes_load_userKey(base, handle); + } + + /* load message and get result */ + status = hashcrypt_aes_one_block(base, ciphertext, plaintext, size); + + return status; +} + +status_t HASHCRYPT_AES_EncryptCbc(HASHCRYPT_Type *base, + hashcrypt_handle_t *handle, + const uint8_t *plaintext, + uint8_t *ciphertext, + size_t size, + const uint8_t iv[16]) +{ + status_t status = kStatus_Fail; + + if ((size % 16u) || (handle->keySize == kHASHCRYPT_InvalidKey)) + { + return kStatus_InvalidArgument; + } + + uint32_t keyType = (handle->keyType == kHASHCRYPT_UserKey) ? 0 : 1u; + base->CRYPTCFG = HASHCRYPT_CRYPTCFG_AESMODE(kHASHCRYPT_AesCbc) | HASHCRYPT_CRYPTCFG_AESDECRYPT(AES_ENCRYPT) | + HASHCRYPT_CRYPTCFG_AESSECRET(keyType) | HASHCRYPT_CRYPTCFG_AESKEYSZ(handle->keySize) | + HASHCRYPT_CRYPTCFG_MSW1ST_OUT(1) | HASHCRYPT_CRYPTCFG_SWAPKEY(1) | HASHCRYPT_CRYPTCFG_SWAPDAT(1) | + HASHCRYPT_CRYPTCFG_MSW1ST(1); + + hashcrypt_engine_init(base, kHASHCRYPT_Aes); + + /* load key if kHASHCRYPT_UserKey is selected */ + if (handle->keyType == kHASHCRYPT_UserKey) + { + hashcrypt_aes_load_userKey(base, handle); + } + + /* load 16b iv */ + hashcrypt_load_data(base, (uint32_t *)iv, 16); + + /* load message and get result */ + status = hashcrypt_aes_one_block(base, plaintext, ciphertext, size); + + return status; +} + +status_t HASHCRYPT_AES_DecryptCbc(HASHCRYPT_Type *base, + hashcrypt_handle_t *handle, + const uint8_t *ciphertext, + uint8_t *plaintext, + size_t size, + const uint8_t iv[16]) +{ + status_t status = kStatus_Fail; + + if ((size % 16u) || (handle->keySize == kHASHCRYPT_InvalidKey)) + { + return kStatus_InvalidArgument; + } + + uint32_t keyType = (handle->keyType == kHASHCRYPT_UserKey) ? 0 : 1u; + base->CRYPTCFG = HASHCRYPT_CRYPTCFG_AESMODE(kHASHCRYPT_AesCbc) | HASHCRYPT_CRYPTCFG_AESDECRYPT(AES_DECRYPT) | + HASHCRYPT_CRYPTCFG_AESSECRET(keyType) | HASHCRYPT_CRYPTCFG_AESKEYSZ(handle->keySize) | + HASHCRYPT_CRYPTCFG_MSW1ST_OUT(1) | HASHCRYPT_CRYPTCFG_SWAPKEY(1) | HASHCRYPT_CRYPTCFG_SWAPDAT(1) | + HASHCRYPT_CRYPTCFG_MSW1ST(1); + + hashcrypt_engine_init(base, kHASHCRYPT_Aes); + + /* load key if kHASHCRYPT_UserKey is selected */ + if (handle->keyType == kHASHCRYPT_UserKey) + { + hashcrypt_aes_load_userKey(base, handle); + } + + /* load iv */ + hashcrypt_load_data(base, (uint32_t *)iv, 16); + + /* load message and get result */ + status = hashcrypt_aes_one_block(base, ciphertext, plaintext, size); + + return status; +} + +status_t HASHCRYPT_AES_CryptCtr(HASHCRYPT_Type *base, + hashcrypt_handle_t *handle, + const uint8_t *input, + uint8_t *output, + size_t size, + uint8_t counter[HASHCRYPT_AES_BLOCK_SIZE], + uint8_t counterlast[HASHCRYPT_AES_BLOCK_SIZE], + size_t *szLeft) +{ + uint32_t lastSize; + uint8_t lastBlock[HASHCRYPT_AES_BLOCK_SIZE] = {0}; + uint8_t *lastEncryptedCounter; + status_t status = kStatus_Fail; + + if (handle->keySize == kHASHCRYPT_InvalidKey) + { + return kStatus_InvalidArgument; + } + + uint32_t keyType = (handle->keyType == kHASHCRYPT_UserKey) ? 0 : 1u; + base->CRYPTCFG = HASHCRYPT_CRYPTCFG_AESMODE(kHASHCRYPT_AesCtr) | HASHCRYPT_CRYPTCFG_AESDECRYPT(AES_ENCRYPT) | + HASHCRYPT_CRYPTCFG_AESSECRET(keyType) | HASHCRYPT_CRYPTCFG_AESKEYSZ(handle->keySize) | + HASHCRYPT_CRYPTCFG_MSW1ST_OUT(1) | HASHCRYPT_CRYPTCFG_SWAPKEY(1) | HASHCRYPT_CRYPTCFG_SWAPDAT(1) | + HASHCRYPT_CRYPTCFG_MSW1ST(1); + + hashcrypt_engine_init(base, kHASHCRYPT_Aes); + + /* load key if kHASHCRYPT_UserKey is selected */ + if (handle->keyType == kHASHCRYPT_UserKey) + { + hashcrypt_aes_load_userKey(base, handle); + } + + /* load nonce */ + hashcrypt_load_data(base, (uint32_t *)counter, 16); + + lastSize = size % HASHCRYPT_AES_BLOCK_SIZE; + size -= lastSize; + + /* encrypt full 16byte blocks */ + hashcrypt_aes_one_block(base, input, output, size); + + while (size) + { + ctrIncrement(counter); + size -= 16u; + input += 16; + output += 16; + } + + if (lastSize) + { + if (counterlast) + { + lastEncryptedCounter = counterlast; + } + else + { + lastEncryptedCounter = lastBlock; + } + + /* Perform encryption with all zeros to get last counter. XOR with zeros doesn't change. */ + status = hashcrypt_aes_one_block(base, lastBlock, lastEncryptedCounter, HASHCRYPT_AES_BLOCK_SIZE); + if (status != kStatus_Success) + { + return status; + } + /* remain output = input XOR counterlast */ + for (uint32_t i = 0; i < lastSize; i++) + { + output[i] = input[i] ^ lastEncryptedCounter[i]; + } + /* Increment counter parameter */ + ctrIncrement(counter); + } + else + { + lastSize = HASHCRYPT_AES_BLOCK_SIZE; + /* no remaining bytes in couterlast so clearing it */ + if (counterlast) + { + memset(counterlast, 0, HASHCRYPT_AES_BLOCK_SIZE); + } + } + + if (szLeft) + { + *szLeft = HASHCRYPT_AES_BLOCK_SIZE - lastSize; + } + + return kStatus_Success; +} + +void HASHCRYPT_IRQHandler(void) +{ + hashcrypt_sha_ctx_internal_t *ctxInternal; + HASHCRYPT_Type *base = HASHCRYPT; + uint32_t numBlocks; + status_t status; + + ctxInternal = (hashcrypt_sha_ctx_internal_t *)s_ctx; + + if (0 == (base->STATUS & HASHCRYPT_STATUS_ERROR_MASK)) + { + if (ctxInternal->remainingBlcks > 0) + { + if (ctxInternal->remainingBlcks >= SHA_MASTER_MAX_BLOCKS) + { + numBlocks = SHA_MASTER_MAX_BLOCKS - 1; + } + else + { + numBlocks = ctxInternal->remainingBlcks; + } + /* some blocks still remaining, update remainingBlcks for next ISR and start another hash */ + ctxInternal->remainingBlcks -= numBlocks; + base->MEMCTRL = HASHCRYPT_MEMCTRL_MASTER(1) | HASHCRYPT_MEMCTRL_COUNT(numBlocks); + return; + } + /* no full blocks left, disable interrupts and AHB master mode */ + base->INTENCLR = HASHCRYPT_INTENCLR_DIGEST_MASK | HASHCRYPT_INTENCLR_ERROR_MASK; + base->MEMCTRL = HASHCRYPT_MEMCTRL_MASTER(0); + status = kStatus_Success; + } + else + { + status = kStatus_Fail; + } + + /* Invoke callback if there is one */ + if (NULL != ctxInternal->hashCallback) + { + ctxInternal->hashCallback(HASHCRYPT, s_ctx, status, ctxInternal->userData); + } +} + +void HASHCRYPT_Init(HASHCRYPT_Type *base) +{ + RESET_PeripheralReset(kHASHCRYPT_RST_SHIFT_RSTn); +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + CLOCK_EnableClock(kCLOCK_HashCrypt); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +void HASHCRYPT_Deinit(HASHCRYPT_Type *base) +{ + RESET_SetPeripheralReset(kHASHCRYPT_RST_SHIFT_RSTn); +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + CLOCK_DisableClock(kCLOCK_HashCrypt); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_hashcrypt.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_hashcrypt.h new file mode 100644 index 000000000..5c188563d --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_hashcrypt.h @@ -0,0 +1,425 @@ +/* + * Copyright 2017-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_HASHCRYPT_H_ +#define _FSL_HASHCRYPT_H_ + +#include "fsl_common.h" + +/*! @brief HASHCRYPT status return codes. */ +enum _hashcrypt_status +{ + kStatus_HASHCRYPT_Again = + MAKE_STATUS(kStatusGroup_HASHCRYPT, 0), /*!< Non-blocking function shall be called again. */ +}; + +/******************************************************************************* + * Definitions + *******************************************************************************/ + +/*! + * @addtogroup hashcrypt_driver + * @{ + */ +/*! @name Driver version */ +/*@{*/ +/*! @brief HASHCRYPT driver version. Version 2.0.2. + * + * Current version: 2.0.2 + * + * Change log: + * - Version 2.0.0 + * - Initial version + * - Version 2.0.1 + * - Support loading AES key from unaligned address + * - Version 2.0.2 + * - Support loading AES key from unaligned address for different compiler and core variants + */ +#define FSL_HASHCRYPT_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) +/*@}*/ + +/*! @brief Algorithm used for Hashcrypt operation */ +typedef enum _hashcrypt_algo_t +{ + kHASHCRYPT_Sha1 = 1, /*!< SHA_1 */ + kHASHCRYPT_Sha256 = 2, /*!< SHA_256 */ + kHASHCRYPT_Sha512 = 3, /*!< SHA_512 */ + kHASHCRYPT_Aes = 4, /*!< AES */ + kHASHCRYPT_AesIcb = 5, /*!< AES_ICB */ +} hashcrypt_algo_t; + +/*! @} */ + +/******************************************************************************* + * AES Definitions + *******************************************************************************/ + +/*! + * @addtogroup hashcrypt_driver_aes + * @{ + */ + +/*! AES block size in bytes */ +#define HASHCRYPT_AES_BLOCK_SIZE 16 +#define AES_ENCRYPT 0 +#define AES_DECRYPT 1 + +/*! @brief AES mode */ +typedef enum _hashcrypt_aes_mode_t +{ + kHASHCRYPT_AesEcb = 0U, /*!< AES ECB mode */ + kHASHCRYPT_AesCbc = 1U, /*!< AES CBC mode */ + kHASHCRYPT_AesCtr = 2U, /*!< AES CTR mode */ +} hashcrypt_aes_mode_t; + +/*! @brief Size of AES key */ +typedef enum _hashcrypt_aes_keysize_t +{ + kHASHCRYPT_Aes128 = 0U, /*!< AES 128 bit key */ + kHASHCRYPT_Aes192 = 1U, /*!< AES 192 bit key */ + kHASHCRYPT_Aes256 = 2U, /*!< AES 256 bit key */ + kHASHCRYPT_InvalidKey = 3U, /*!< AES invalid key */ +} hashcrypt_aes_keysize_t; + +/*! @brief HASHCRYPT key source selection. + * + */ +typedef enum _hashcrypt_key +{ + kHASHCRYPT_UserKey = 0xc3c3U, /*!< HASHCRYPT user key */ + kHASHCRYPT_SecretKey = 0x3c3cU, /*!< HASHCRYPT secret key (dedicated hw bus from PUF) */ +} hashcrypt_key_t; + +/*! @brief Specify HASHCRYPT's key resource. */ +struct _hashcrypt_handle +{ + uint32_t keyWord[8]; /*!< Copy of user key (set by HASHCRYPT_AES_SetKey(). */ + hashcrypt_aes_keysize_t keySize; + hashcrypt_key_t keyType; /*!< For operations with key (such as AES encryption/decryption), specify key type. */ +} __attribute__((aligned)); + +typedef struct _hashcrypt_handle hashcrypt_handle_t; + +/*! + *@} + */ /* end of hashcrypt_driver_aes */ + +/******************************************************************************* + * HASH Definitions + ******************************************************************************/ +/*! + * @addtogroup hashcrypt_driver_hash + * @{ + */ + +/*! @brief HASHCRYPT HASH Context size. */ +#define HASHCRYPT_HASH_CTX_SIZE 22 + +/*! @brief Storage type used to save hash context. */ +typedef struct _hashcrypt_hash_ctx_t +{ + uint32_t x[HASHCRYPT_HASH_CTX_SIZE]; /*!< storage */ +} hashcrypt_hash_ctx_t; + +/*! @brief HASHCRYPT background hash callback function. */ +typedef void (*hashcrypt_callback_t)(HASHCRYPT_Type *base, hashcrypt_hash_ctx_t *ctx, status_t status, void *userData); + +/*! + *@} + */ /* end of hashcrypt_driver_hash */ + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @addtogroup hashcrypt_driver + * @{ + */ + +/*! + * @brief Enables clock and disables reset for HASHCRYPT peripheral. + * + * Enable clock and disable reset for HASHCRYPT. + * + * @param base HASHCRYPT base address + */ +void HASHCRYPT_Init(HASHCRYPT_Type *base); + +/*! + * @brief Disables clock for HASHCRYPT peripheral. + * + * Disable clock and enable reset. + * + * @param base HASHCRYPT base address + */ +void HASHCRYPT_Deinit(HASHCRYPT_Type *base); + +/*! + *@} + */ /* end of hashcrypt_driver */ + +/******************************************************************************* + * AES API + ******************************************************************************/ + +/*! + * @addtogroup hashcrypt_driver_aes + * @{ + */ + +/*! + * @brief Set AES key to hashcrypt_handle_t struct and optionally to HASHCRYPT. + * + * Sets the AES key for encryption/decryption with the hashcrypt_handle_t structure. + * The hashcrypt_handle_t input argument specifies key source. + * + * @param base HASHCRYPT peripheral base address. + * @param handle Handle used for the request. + * @param key 0-mod-4 aligned pointer to AES key. + * @param keySize AES key size in bytes. Shall equal 16, 24 or 32. + * @return status from set key operation + */ +status_t HASHCRYPT_AES_SetKey(HASHCRYPT_Type *base, hashcrypt_handle_t *handle, const uint8_t *key, size_t keySize); + +/*! + * @brief Encrypts AES on one or multiple 128-bit block(s). + * + * Encrypts AES. + * The source plaintext and destination ciphertext can overlap in system memory. + * + * @param base HASHCRYPT peripheral base address + * @param handle Handle used for this request. + * @param plaintext Input plain text to encrypt + * @param[out] ciphertext Output cipher text + * @param size Size of input and output data in bytes. Must be multiple of 16 bytes. + * @return Status from encrypt operation + */ +status_t HASHCRYPT_AES_EncryptEcb( + HASHCRYPT_Type *base, hashcrypt_handle_t *handle, const uint8_t *plaintext, uint8_t *ciphertext, size_t size); + +/*! + * @brief Decrypts AES on one or multiple 128-bit block(s). + * + * Decrypts AES. + * The source ciphertext and destination plaintext can overlap in system memory. + * + * @param base HASHCRYPT peripheral base address + * @param handle Handle used for this request. + * @param ciphertext Input plain text to encrypt + * @param[out] plaintext Output cipher text + * @param size Size of input and output data in bytes. Must be multiple of 16 bytes. + * @return Status from decrypt operation + */ +status_t HASHCRYPT_AES_DecryptEcb( + HASHCRYPT_Type *base, hashcrypt_handle_t *handle, const uint8_t *ciphertext, uint8_t *plaintext, size_t size); + +/*! + * @brief Encrypts AES using CBC block mode. + * + * @param base HASHCRYPT peripheral base address + * @param handle Handle used for this request. + * @param plaintext Input plain text to encrypt + * @param[out] ciphertext Output cipher text + * @param size Size of input and output data in bytes. Must be multiple of 16 bytes. + * @param iv Input initial vector to combine with the first input block. + * @return Status from encrypt operation + */ +status_t HASHCRYPT_AES_EncryptCbc(HASHCRYPT_Type *base, + hashcrypt_handle_t *handle, + const uint8_t *plaintext, + uint8_t *ciphertext, + size_t size, + const uint8_t iv[16]); + +/*! + * @brief Decrypts AES using CBC block mode. + * + * @param base HASHCRYPT peripheral base address + * @param handle Handle used for this request. + * @param ciphertext Input cipher text to decrypt + * @param[out] plaintext Output plain text + * @param size Size of input and output data in bytes. Must be multiple of 16 bytes. + * @param iv Input initial vector to combine with the first input block. + * @return Status from decrypt operation + */ +status_t HASHCRYPT_AES_DecryptCbc(HASHCRYPT_Type *base, + hashcrypt_handle_t *handle, + const uint8_t *ciphertext, + uint8_t *plaintext, + size_t size, + const uint8_t iv[16]); + +/*! + * @brief Encrypts or decrypts AES using CTR block mode. + * + * Encrypts or decrypts AES using CTR block mode. + * AES CTR mode uses only forward AES cipher and same algorithm for encryption and decryption. + * The only difference between encryption and decryption is that, for encryption, the input argument + * is plain text and the output argument is cipher text. For decryption, the input argument is cipher text + * and the output argument is plain text. + * + * @param base HASHCRYPT peripheral base address + * @param handle Handle used for this request. + * @param input Input data for CTR block mode + * @param[out] output Output data for CTR block mode + * @param size Size of input and output data in bytes + * @param[in,out] counter Input counter (updates on return) + * @param[out] counterlast Output cipher of last counter, for chained CTR calls (statefull encryption). NULL can be + * passed if chained calls are + * not used. + * @param[out] szLeft Output number of bytes in left unused in counterlast block. NULL can be passed if chained calls + * are not used. + * @return Status from encrypt operation + */ +status_t HASHCRYPT_AES_CryptCtr(HASHCRYPT_Type *base, + hashcrypt_handle_t *handle, + const uint8_t *input, + uint8_t *output, + size_t size, + uint8_t counter[HASHCRYPT_AES_BLOCK_SIZE], + uint8_t counterlast[HASHCRYPT_AES_BLOCK_SIZE], + size_t *szLeft); + +/*! + *@} + */ /* end of hashcrypt_driver_aes */ + +/******************************************************************************* + * HASH API + ******************************************************************************/ + +/*! + * @addtogroup hashcrypt_driver_hash + * @{ + */ + +/*! + * @brief Create HASH on given data + * + * Perform the full SHA in one function call. The function is blocking. + * + * @param base HASHCRYPT peripheral base address + * @param algo Underlaying algorithm to use for hash computation. + * @param input Input data + * @param inputSize Size of input data in bytes + * @param[out] output Output hash data + * @param[out] outputSize Output parameter storing the size of the output hash in bytes + * @return Status of the one call hash operation. + */ +status_t HASHCRYPT_SHA(HASHCRYPT_Type *base, + hashcrypt_algo_t algo, + const uint8_t *input, + size_t inputSize, + uint8_t *output, + size_t *outputSize); + +/*! + * @brief Initialize HASH context + * + * This function initializes the HASH. + * + * @param base HASHCRYPT peripheral base address + * @param[out] ctx Output hash context + * @param algo Underlaying algorithm to use for hash computation. + * @return Status of initialization + */ +status_t HASHCRYPT_SHA_Init(HASHCRYPT_Type *base, hashcrypt_hash_ctx_t *ctx, hashcrypt_algo_t algo); + +/*! + * @brief Add data to current HASH + * + * Add data to current HASH. This can be called repeatedly with an arbitrary amount of data to be + * hashed. The functions blocks. If it returns kStatus_Success, the running hash + * has been updated (HASHCRYPT has processed the input data), so the memory at \p input pointer + * can be released back to system. The HASHCRYPT context buffer is updated with the running hash + * and with all necessary information to support possible context switch. + * + * @param base HASHCRYPT peripheral base address + * @param[in,out] ctx HASH context + * @param input Input data + * @param inputSize Size of input data in bytes + * @return Status of the hash update operation + */ +status_t HASHCRYPT_SHA_Update(HASHCRYPT_Type *base, hashcrypt_hash_ctx_t *ctx, const uint8_t *input, size_t inputSize); + +/*! + * @brief Finalize hashing + * + * Outputs the final hash (computed by HASHCRYPT_HASH_Update()) and erases the context. + * + * @param base HASHCRYPT peripheral base address + * @param[in,out] ctx Input hash context + * @param[out] output Output hash data + * @param[in,out] outputSize Optional parameter (can be passed as NULL). On function entry, it specifies the size of + * output[] buffer. On function return, it stores the number of updated output bytes. + * @return Status of the hash finish operation + */ +status_t HASHCRYPT_SHA_Finish(HASHCRYPT_Type *base, hashcrypt_hash_ctx_t *ctx, uint8_t *output, size_t *outputSize); + +/*! + *@} + */ /* end of hashcrypt_driver_hash */ + +/*! + * @addtogroup hashcrypt_background_driver_hash + * @{ + */ + +/*! + * @brief Initializes the HASHCRYPT handle for background hashing. + * + * This function initializes the hash context for background hashing + * (Non-blocking) APIs. This is less typical interface to hash function, but can be used + * for parallel processing, when main CPU has something else to do. + * Example is digital signature RSASSA-PKCS1-V1_5-VERIFY((n,e),M,S) algorithm, where + * background hashing of M can be started, then CPU can compute S^e mod n + * (in parallel with background hashing) and once the digest becomes available, + * CPU can proceed to comparison of EM with EM'. + * + * @param base HASHCRYPT peripheral base address. + * @param[out] ctx Hash context. + * @param callback Callback function. + * @param userData User data (to be passed as an argument to callback function, once callback is invoked from isr). + */ +void HASHCRYPT_SHA_SetCallback(HASHCRYPT_Type *base, + hashcrypt_hash_ctx_t *ctx, + hashcrypt_callback_t callback, + void *userData); + +/*! + * @brief Create running hash on given data. + * + * Configures the HASHCRYPT to compute new running hash as AHB master + * and returns immediately. HASHCRYPT AHB Master mode supports only aligned \p input + * address and can be called only once per continuous block of data. Every call to this function + * must be preceded with HASHCRYPT_SHA_Init() and finished with HASHCRYPT_SHA_Finish(). + * Once callback function is invoked by HASHCRYPT isr, it should set a flag + * for the main application to finalize the hashing (padding) and to read out the final digest + * by calling HASHCRYPT_SHA_Finish(). + * + * @param base HASHCRYPT peripheral base address + * @param ctx Specifies callback. Last incomplete 512-bit block of the input is copied into clear buffer for padding. + * @param input 32-bit word aligned pointer to Input data. + * @param inputSize Size of input data in bytes (must be word aligned) + * @return Status of the hash update operation. + */ +status_t HASHCRYPT_SHA_UpdateNonBlocking(HASHCRYPT_Type *base, + hashcrypt_hash_ctx_t *ctx, + const uint8_t *input, + size_t inputSize); +/*! + *@} + */ /* end of hashcrypt_background_driver_hash */ + +#if defined(__cplusplus) +} +#endif + +#endif /* _FSL_HASHCRYPT_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2c.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2c.c new file mode 100644 index 000000000..26b14083f --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2c.c @@ -0,0 +1,1869 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_i2c.h" +#include "fsl_flexcomm.h" +#include +#include + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexcomm_i2c" +#endif + +/*! @brief Common sets of flags used by the driver. */ +enum _i2c_flag_constants +{ + kI2C_MasterIrqFlags = I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_MSTARBLOSS_MASK | I2C_INTSTAT_MSTSTSTPERR_MASK, + kI2C_SlaveIrqFlags = I2C_INTSTAT_SLVPENDING_MASK | I2C_INTSTAT_SLVDESEL_MASK, +}; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +static status_t I2C_InitTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer); +static void I2C_SlaveInternalStateMachineReset(I2C_Type *base); +static status_t I2C_SlaveDivVal(uint32_t srcClock_Hz, i2c_slave_bus_speed_t busSpeed, uint32_t *divVal); +static uint32_t I2C_SlavePollPending(I2C_Type *base); +static void I2C_SlaveInvokeEvent(I2C_Type *base, i2c_slave_handle_t *handle, i2c_slave_transfer_event_t event); +static bool I2C_SlaveAddressIRQ(I2C_Type *base, i2c_slave_handle_t *handle); +static status_t I2C_SlaveTransferNonBlockingInternal(I2C_Type *base, + i2c_slave_handle_t *handle, + const void *txData, + size_t txSize, + void *rxData, + size_t rxSize, + uint32_t eventMask); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief Array to map i2c instance number to base address. */ +static const uint32_t s_i2cBaseAddrs[FSL_FEATURE_SOC_I2C_COUNT] = I2C_BASE_ADDRS; + +/*! @brief IRQ name array */ +static const IRQn_Type s_i2cIRQ[] = I2C_IRQS; + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * @brief Returns an instance number given a base address. + * + * If an invalid base address is passed, debug builds will assert. Release builds will just return + * instance number 0. + * + * @param base The I2C peripheral base address. + * @return I2C instance number starting from 0. + */ +/*! + * brief Returns an instance number given a base address. + * + * If an invalid base address is passed, debug builds will assert. Release builds will just return + * instance number 0. + * + * param base The I2C peripheral base address. + * return I2C instance number starting from 0. + */ +uint32_t I2C_GetInstance(I2C_Type *base) +{ + int i; + for (i = 0; i < FSL_FEATURE_SOC_I2C_COUNT; i++) + { + if ((uint32_t)base == s_i2cBaseAddrs[i]) + { + return i; + } + } + assert(false); + return 0; +} + +/*! + * brief Provides a default configuration for the I2C master peripheral. + * + * This function provides the following default configuration for the I2C master peripheral: + * code + * masterConfig->enableMaster = true; + * masterConfig->baudRate_Bps = 100000U; + * masterConfig->enableTimeout = false; + * endcode + * + * After calling this function, you can override any settings in order to customize the configuration, + * prior to initializing the master driver with I2C_MasterInit(). + * + * param[out] masterConfig User provided configuration structure for default values. Refer to #i2c_master_config_t. + */ +void I2C_MasterGetDefaultConfig(i2c_master_config_t *masterConfig) +{ + /* Initializes the configure structure to zero. */ + memset(masterConfig, 0, sizeof(*masterConfig)); + + masterConfig->enableMaster = true; + masterConfig->baudRate_Bps = 100000U; + masterConfig->enableTimeout = false; +} + +/*! + * brief Initializes the I2C master peripheral. + * + * This function enables the peripheral clock and initializes the I2C master peripheral as described by the user + * provided configuration. A software reset is performed prior to configuration. + * + * param base The I2C peripheral base address. + * param masterConfig User provided peripheral configuration. Use I2C_MasterGetDefaultConfig() to get a set of + * defaults + * that you can override. + * param srcClock_Hz Frequency in Hertz of the I2C functional clock. Used to calculate the baud rate divisors, + * filter widths, and timeout periods. + */ +void I2C_MasterInit(I2C_Type *base, const i2c_master_config_t *masterConfig, uint32_t srcClock_Hz) +{ + FLEXCOMM_Init(base, FLEXCOMM_PERIPH_I2C); + I2C_MasterEnable(base, masterConfig->enableMaster); + I2C_MasterSetBaudRate(base, masterConfig->baudRate_Bps, srcClock_Hz); +} + +/*! + * brief Deinitializes the I2C master peripheral. + * + * This function disables the I2C master peripheral and gates the clock. It also performs a software + * reset to restore the peripheral to reset conditions. + * + * param base The I2C peripheral base address. + */ +void I2C_MasterDeinit(I2C_Type *base) +{ + I2C_MasterEnable(base, false); +} + +/*! + * brief Sets the I2C bus frequency for master transactions. + * + * The I2C master is automatically disabled and re-enabled as necessary to configure the baud + * rate. Do not call this function during a transfer, or the transfer is aborted. + * + * param base The I2C peripheral base address. + * param srcClock_Hz I2C functional clock frequency in Hertz. + * param baudRate_Bps Requested bus frequency in bits per second. + */ +void I2C_MasterSetBaudRate(I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz) +{ + uint32_t scl, divider; + uint32_t err, best_err; + uint32_t best_scl = 0; + uint32_t best_div = 0; + +#if defined(FSL_FEATURE_I2C_PREPCLKFRG_8MHZ) && (FSL_FEATURE_I2C_PREPCLKFRG_8MHZ) + /* + * RFT1717/RFT1437: workaround for hardware bug when using DMA + * I2C peripheral clock frequency has to be fixed at 8MHz + * source clock is 32MHz or 48MHz so divider is a round integer value + */ + best_div = srcClock_Hz / 8000000; + best_scl = 8000000 / (2 * baudRate_Bps); + + if (((8000000 / (2 * best_scl)) - baudRate_Bps) > (baudRate_Bps - (8000000 / (2 * (best_scl + 1))))) + { + best_scl = best_scl + 1; + } + + /* + * If master SCL frequency does not fit in workaround range, fallback to + * usual baudrate computation method + */ + if ((best_scl > 9) || ((best_scl < 2))) + { +#endif /*FSL_FEATURE_I2C_PREPCLKFRG_8MHZ*/ + + best_err = 0; + + for (scl = 9; scl >= 2; scl--) + { + /* calculated ideal divider value for given scl */ + divider = srcClock_Hz / (baudRate_Bps * scl * 2u); + + /* adjust it if it is out of range */ + divider = (divider > 0x10000u) ? 0x10000 : divider; + + /* calculate error */ + err = srcClock_Hz - (baudRate_Bps * scl * 2u * divider); + if ((err < best_err) || (best_err == 0)) + { + best_div = divider; + best_scl = scl; + best_err = err; + } + + if ((err == 0) || (divider >= 0x10000u)) + { + /* either exact value was found + or divider is at its max (it would even greater in the next iteration for sure) */ + break; + } + } +#if defined(FSL_FEATURE_I2C_PREPCLKFRG_8MHZ) && (FSL_FEATURE_I2C_PREPCLKFRG_8MHZ) + } +#endif /*FSL_FEATURE_I2C_PREPCLKFRG_8MHZ*/ + base->CLKDIV = I2C_CLKDIV_DIVVAL(best_div - 1); + base->MSTTIME = I2C_MSTTIME_MSTSCLLOW(best_scl - 2u) | I2C_MSTTIME_MSTSCLHIGH(best_scl - 2u); +} + +static uint32_t I2C_PendingStatusWait(I2C_Type *base) +{ + uint32_t status; + +#if I2C_RETRY_TIMES + uint32_t waitTimes = I2C_RETRY_TIMES; +#endif + + do + { + status = I2C_GetStatusFlags(base); +#if I2C_RETRY_TIMES + } while (((status & I2C_STAT_MSTPENDING_MASK) == 0) && (--waitTimes)); + + if (waitTimes == 0) + { + return kStatus_I2C_Timeout; + } +#else + } while ((status & I2C_STAT_MSTPENDING_MASK) == 0); +#endif + + /* Clear controller state. */ + I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK); + + return status; +} + +/*! + * brief Sends a START on the I2C bus. + * + * This function is used to initiate a new master mode transfer by sending the START signal. + * The slave address is sent following the I2C START signal. + * + * param base I2C peripheral base pointer + * param address 7-bit slave device address. + * param direction Master transfer directions(transmit/receive). + * retval kStatus_Success Successfully send the start signal. + * retval kStatus_I2C_Busy Current bus is busy. + */ +status_t I2C_MasterStart(I2C_Type *base, uint8_t address, i2c_direction_t direction) +{ + status_t result; + result = I2C_PendingStatusWait(base); + if (result == kStatus_I2C_Timeout) + { + return kStatus_I2C_Timeout; + } + + /* Write Address and RW bit to data register */ + base->MSTDAT = ((uint32_t)address << 1) | ((uint32_t)direction & 1u); + /* Start the transfer */ + base->MSTCTL = I2C_MSTCTL_MSTSTART_MASK; + + return kStatus_Success; +} + +/*! + * brief Sends a STOP signal on the I2C bus. + * + * retval kStatus_Success Successfully send the stop signal. + * retval kStatus_I2C_Timeout Send stop signal failed, timeout. + */ +status_t I2C_MasterStop(I2C_Type *base) +{ + status_t result; + result = I2C_PendingStatusWait(base); + if (result == kStatus_I2C_Timeout) + { + return kStatus_I2C_Timeout; + } + + base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; + return kStatus_Success; +} + +/*! + * brief Performs a polling send transfer on the I2C bus. + * + * Sends up to a txSize number of bytes to the previously addressed slave device. The slave may + * reply with a NAK to any byte in order to terminate the transfer early. If this happens, this + * function returns #kStatus_I2C_Nak. + * + * param base The I2C peripheral base address. + * param txBuff The pointer to the data to be transferred. + * param txSize The length in bytes of the data to be transferred. + * param flags Transfer control flag to control special behavior like suppressing start or stop, for normal transfers + * use kI2C_TransferDefaultFlag + * retval kStatus_Success Data was sent successfully. + * retval #kStatus_I2C_Busy Another master is currently utilizing the bus. + * retval #kStatus_I2C_Nak The slave device sent a NAK in response to a byte. + * retval #kStatus_I2C_ArbitrationLost Arbitration lost error. + */ +status_t I2C_MasterWriteBlocking(I2C_Type *base, const void *txBuff, size_t txSize, uint32_t flags) +{ + uint32_t status; + uint32_t master_state; + status_t err; + + const uint8_t *buf = (const uint8_t *)(uintptr_t)txBuff; + + assert(txBuff); + + err = kStatus_Success; + while (txSize) + { + status = I2C_PendingStatusWait(base); + +#if I2C_RETRY_TIMES + if (status == kStatus_I2C_Timeout) + { + return kStatus_I2C_Timeout; + } +#endif + + if (status & I2C_STAT_MSTARBLOSS_MASK) + { + return kStatus_I2C_ArbitrationLost; + } + + if (status & I2C_STAT_MSTSTSTPERR_MASK) + { + return kStatus_I2C_StartStopError; + } + + master_state = (status & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; + switch (master_state) + { + case I2C_STAT_MSTCODE_TXREADY: + /* ready to send next byte */ + base->MSTDAT = *buf++; + txSize--; + base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK; + break; + + case I2C_STAT_MSTCODE_NACKADR: + case I2C_STAT_MSTCODE_NACKDAT: + /* slave nacked the last byte */ + err = kStatus_I2C_Nak; + break; + + default: + /* unexpected state */ + err = kStatus_I2C_UnexpectedState; + break; + } + + if (err != kStatus_Success) + { + return err; + } + } + + status = I2C_PendingStatusWait(base); + +#if I2C_RETRY_TIMES + if (status == kStatus_I2C_Timeout) + { + return kStatus_I2C_Timeout; + } +#endif + + if ((status & (I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK)) == 0) + { + if (!(flags & kI2C_TransferNoStopFlag)) + { + /* Initiate stop */ + base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; + status = I2C_PendingStatusWait(base); + if (status == kStatus_I2C_Timeout) + { + return kStatus_I2C_Timeout; + } + } + } + + if (status & I2C_STAT_MSTARBLOSS_MASK) + { + return kStatus_I2C_ArbitrationLost; + } + + if (status & I2C_STAT_MSTSTSTPERR_MASK) + { + return kStatus_I2C_StartStopError; + } + + return kStatus_Success; +} + +/*! + * brief Performs a polling receive transfer on the I2C bus. + * + * param base The I2C peripheral base address. + * param rxBuff The pointer to the data to be transferred. + * param rxSize The length in bytes of the data to be transferred. + * param flags Transfer control flag to control special behavior like suppressing start or stop, for normal transfers + * use kI2C_TransferDefaultFlag + * retval kStatus_Success Data was received successfully. + * retval #kStatus_I2C_Busy Another master is currently utilizing the bus. + * retval #kStatus_I2C_Nak The slave device sent a NAK in response to a byte. + * retval #kStatus_I2C_ArbitrationLost Arbitration lost error. + */ +status_t I2C_MasterReadBlocking(I2C_Type *base, void *rxBuff, size_t rxSize, uint32_t flags) +{ + uint32_t status = 0; + uint32_t master_state; + status_t err; + + uint8_t *buf = (uint8_t *)(rxBuff); + + assert(rxBuff); + + err = kStatus_Success; + while (rxSize) + { + status = I2C_PendingStatusWait(base); + +#if I2C_RETRY_TIMES + if (status == kStatus_I2C_Timeout) + { + return kStatus_I2C_Timeout; + } +#endif + + if (status & (I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK)) + { + break; + } + + master_state = (status & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; + switch (master_state) + { + case I2C_STAT_MSTCODE_RXREADY: + /* ready to send next byte */ + *(buf++) = base->MSTDAT; + if (--rxSize) + { + base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK; + } + else + { + if ((flags & kI2C_TransferNoStopFlag) == 0) + { + /* initiate NAK and stop */ + base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; + status = I2C_PendingStatusWait(base); + +#if I2C_RETRY_TIMES + if (status == kStatus_I2C_Timeout) + { + return kStatus_I2C_Timeout; + } +#endif + } + } + break; + + case I2C_STAT_MSTCODE_NACKADR: + case I2C_STAT_MSTCODE_NACKDAT: + /* slave nacked the last byte */ + err = kStatus_I2C_Nak; + break; + + default: + /* unexpected state */ + err = kStatus_I2C_UnexpectedState; + break; + } + + if (err != kStatus_Success) + { + return err; + } + } + + if (status & I2C_STAT_MSTARBLOSS_MASK) + { + return kStatus_I2C_ArbitrationLost; + } + + if (status & I2C_STAT_MSTSTSTPERR_MASK) + { + return kStatus_I2C_StartStopError; + } + + return kStatus_Success; +} + +/*! + * brief Performs a master polling transfer on the I2C bus. + * + * note The API does not return until the transfer succeeds or fails due + * to arbitration lost or receiving a NAK. + * + * param base I2C peripheral base address. + * param xfer Pointer to the transfer structure. + * retval kStatus_Success Successfully complete the data transmission. + * retval kStatus_I2C_Busy Previous transmission still not finished. + * retval kStatus_I2C_Timeout Transfer error, wait signal timeout. + * retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. + * retval kStataus_I2C_Nak Transfer error, receive NAK during transfer. + */ +status_t I2C_MasterTransferBlocking(I2C_Type *base, i2c_master_transfer_t *xfer) +{ + status_t result = kStatus_Success; + uint32_t subaddress; + uint8_t subaddrBuf[4]; + int i; + + assert(xfer); + + /* If repeated start is requested, send repeated start. */ + if (!(xfer->flags & kI2C_TransferNoStartFlag)) + { + if (xfer->subaddressSize) + { + result = I2C_MasterStart(base, xfer->slaveAddress, kI2C_Write); + if (result == kStatus_Success) + { + /* Prepare subaddress transmit buffer, most significant byte is stored at the lowest address */ + subaddress = xfer->subaddress; + for (i = xfer->subaddressSize - 1; i >= 0; i--) + { + subaddrBuf[i] = subaddress & 0xff; + subaddress >>= 8; + } + /* Send subaddress. */ + result = I2C_MasterWriteBlocking(base, subaddrBuf, xfer->subaddressSize, kI2C_TransferNoStopFlag); + if ((result == kStatus_Success) && (xfer->direction == kI2C_Read)) + { + result = I2C_MasterRepeatedStart(base, xfer->slaveAddress, xfer->direction); + } + } + } + else if (xfer->flags & kI2C_TransferRepeatedStartFlag) + { + result = I2C_MasterRepeatedStart(base, xfer->slaveAddress, xfer->direction); + } + else + { + result = I2C_MasterStart(base, xfer->slaveAddress, xfer->direction); + } + } + + if (result == kStatus_Success) + { + if ((xfer->direction == kI2C_Write) && (xfer->dataSize > 0)) + { + /* Transmit data. */ + result = I2C_MasterWriteBlocking(base, xfer->data, xfer->dataSize, xfer->flags); + } + else + { + if ((xfer->direction == kI2C_Read) && (xfer->dataSize > 0)) + { + /* Receive Data. */ + result = I2C_MasterReadBlocking(base, xfer->data, xfer->dataSize, xfer->flags); + } + } + } + + if (result == kStatus_I2C_Nak) + { + I2C_MasterStop(base); + } + + return result; +} + +/*! + * brief Creates a new handle for the I2C master non-blocking APIs. + * + * The creation of a handle is for use with the non-blocking APIs. Once a handle + * is created, there is not a corresponding destroy handle. If the user wants to + * terminate a transfer, the I2C_MasterTransferAbort() API shall be called. + * + * param base The I2C peripheral base address. + * param[out] handle Pointer to the I2C master driver handle. + * param callback User provided pointer to the asynchronous callback function. + * param userData User provided pointer to the application callback data. + */ +void I2C_MasterTransferCreateHandle(I2C_Type *base, + i2c_master_handle_t *handle, + i2c_master_transfer_callback_t callback, + void *userData) +{ + uint32_t instance; + + assert(handle); + + /* Clear out the handle. */ + memset(handle, 0, sizeof(*handle)); + + /* Look up instance number */ + instance = I2C_GetInstance(base); + + /* Save base and instance. */ + handle->completionCallback = callback; + handle->userData = userData; + + FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)I2C_MasterTransferHandleIRQ, handle); + + /* Clear internal IRQ enables and enable NVIC IRQ. */ + I2C_DisableInterrupts(base, kI2C_MasterIrqFlags); + EnableIRQ(s_i2cIRQ[instance]); +} + +/*! + * brief Performs a non-blocking transaction on the I2C bus. + * + * param base The I2C peripheral base address. + * param handle Pointer to the I2C master driver handle. + * param xfer The pointer to the transfer descriptor. + * retval kStatus_Success The transaction was started successfully. + * retval #kStatus_I2C_Busy Either another master is currently utilizing the bus, or a non-blocking + * transaction is already in progress. + */ +status_t I2C_MasterTransferNonBlocking(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer) +{ + status_t result; + + assert(handle); + assert(xfer); + assert(xfer->subaddressSize <= sizeof(xfer->subaddress)); + + /* Return busy if another transaction is in progress. */ + if (handle->state != kIdleState) + { + return kStatus_I2C_Busy; + } + + /* Disable I2C IRQ sources while we configure stuff. */ + I2C_DisableInterrupts(base, kI2C_MasterIrqFlags); + + /* Prepare transfer state machine. */ + result = I2C_InitTransferStateMachine(base, handle, xfer); + + /* Clear error flags. */ + I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK); + + /* Enable I2C internal IRQ sources. */ + I2C_EnableInterrupts(base, kI2C_MasterIrqFlags); + + return result; +} + +/*! + * brief Returns number of bytes transferred so far. + * param base The I2C peripheral base address. + * param handle Pointer to the I2C master driver handle. + * param[out] count Number of bytes transferred so far by the non-blocking transaction. + * retval kStatus_Success + * retval #kStatus_I2C_Busy + */ +status_t I2C_MasterTransferGetCount(I2C_Type *base, i2c_master_handle_t *handle, size_t *count) +{ + assert(handle); + + if (!count) + { + return kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + if (handle->state == kIdleState) + { + *count = 0; + return kStatus_NoTransferInProgress; + } + + /* There is no necessity to disable interrupts as we read a single integer value */ + *count = handle->transferCount; + return kStatus_Success; +} + +/*! + * brief Terminates a non-blocking I2C master transmission early. + * + * note It is not safe to call this function from an IRQ handler that has a higher priority than the + * I2C peripheral's IRQ priority. + * + * param base The I2C peripheral base address. + * param handle Pointer to the I2C master driver handle. + * retval kStatus_Success A transaction was successfully aborted. + * retval #kStatus_I2C_Timeout Timeout during polling for flags. + */ +status_t I2C_MasterTransferAbort(I2C_Type *base, i2c_master_handle_t *handle) +{ + uint32_t status; + uint32_t master_state; + + if (handle->state != kIdleState) + { + /* Disable internal IRQ enables. */ + I2C_DisableInterrupts(base, kI2C_MasterIrqFlags); + + /* Wait until module is ready */ + status = I2C_PendingStatusWait(base); + +#if I2C_RETRY_TIMES + if (status == kStatus_I2C_Timeout) + { + /* Reset handle to idle state. */ + handle->state = kIdleState; + return kStatus_I2C_Timeout; + } +#endif + + /* Get the state of the I2C module */ + master_state = (status & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; + + if (master_state != I2C_STAT_MSTCODE_IDLE) + { + /* Send a stop command to finalize the transfer. */ + base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; + + /* Wait until the STOP is completed */ + status = I2C_PendingStatusWait(base); + if (status == kStatus_I2C_Timeout) + { + return kStatus_I2C_Timeout; + } + } + + /* Reset handle. */ + handle->state = kIdleState; + } + return kStatus_Success; +} + +/*! + * @brief Prepares the transfer state machine and fills in the command buffer. + * @param handle Master nonblocking driver handle. + */ +static status_t I2C_InitTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer) +{ + struct _i2c_master_transfer *transfer; + + handle->transfer = *xfer; + transfer = &(handle->transfer); + + handle->transferCount = 0; + handle->remainingBytes = transfer->dataSize; + handle->buf = (uint8_t *)transfer->data; + handle->remainingSubaddr = 0; + + if (transfer->flags & kI2C_TransferNoStartFlag) + { + /* Start condition shall be ommited, switch directly to next phase */ + if (transfer->dataSize == 0) + { + handle->state = kStopState; + } + else if (handle->transfer.direction == kI2C_Write) + { + handle->state = kTransmitDataState; + } + else if (handle->transfer.direction == kI2C_Read) + { + handle->state = kReceiveDataState; + } + else + { + return kStatus_I2C_InvalidParameter; + } + } + else + { + if (transfer->subaddressSize != 0) + { + int i; + uint32_t subaddress; + + if (transfer->subaddressSize > sizeof(handle->subaddrBuf)) + { + return kStatus_I2C_InvalidParameter; + } + + /* Prepare subaddress transmit buffer, most significant byte is stored at the lowest address */ + subaddress = xfer->subaddress; + for (i = xfer->subaddressSize - 1; i >= 0; i--) + { + handle->subaddrBuf[i] = subaddress & 0xff; + subaddress >>= 8; + } + handle->remainingSubaddr = transfer->subaddressSize; + } + handle->state = kStartState; + } + + return kStatus_Success; +} + +/*! + * @brief Execute states until FIFOs are exhausted. + * @param handle Master nonblocking driver handle. + * @param[out] isDone Set to true if the transfer has completed. + * @retval #kStatus_Success + * @retval #kStatus_I2C_ArbitrationLost + * @retval #kStatus_I2C_Nak + */ +static status_t I2C_RunTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, bool *isDone) +{ + uint32_t status; + uint32_t master_state; + struct _i2c_master_transfer *transfer; + status_t err; + + transfer = &(handle->transfer); + bool ignoreNak = ((handle->state == kStopState) && (handle->remainingBytes == 0U)) || + ((handle->state == kWaitForCompletionState) && (handle->remainingBytes == 0U)); + + *isDone = false; + + status = I2C_GetStatusFlags(base); + + if (status & I2C_STAT_MSTARBLOSS_MASK) + { + I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK); + return kStatus_I2C_ArbitrationLost; + } + + if (status & I2C_STAT_MSTSTSTPERR_MASK) + { + I2C_MasterClearStatusFlags(base, I2C_STAT_MSTSTSTPERR_MASK); + return kStatus_I2C_StartStopError; + } + + if ((status & I2C_STAT_MSTPENDING_MASK) == 0) + { + return kStatus_I2C_Busy; + } + + /* Get the state of the I2C module */ + master_state = (status & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; + + if (((master_state == I2C_STAT_MSTCODE_NACKADR) || (master_state == I2C_STAT_MSTCODE_NACKDAT)) && + (ignoreNak != true)) + { + /* Slave NACKed last byte, issue stop and return error */ + base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; + handle->state = kWaitForCompletionState; + return kStatus_I2C_Nak; + } + + err = kStatus_Success; + switch (handle->state) + { + case kStartState: + if (handle->remainingSubaddr) + { + /* Subaddress takes precedence over the data transfer, direction is always "write" in this case */ + base->MSTDAT = (uint32_t)transfer->slaveAddress << 1; + handle->state = kTransmitSubaddrState; + } + else if (transfer->direction == kI2C_Write) + { + base->MSTDAT = (uint32_t)transfer->slaveAddress << 1; + handle->state = handle->remainingBytes ? kTransmitDataState : kStopState; + } + else + { + base->MSTDAT = ((uint32_t)transfer->slaveAddress << 1) | 1u; + handle->state = handle->remainingBytes ? kReceiveDataState : kStopState; + } + /* Send start condition */ + base->MSTCTL = I2C_MSTCTL_MSTSTART_MASK; + break; + + case kTransmitSubaddrState: + if (master_state != I2C_STAT_MSTCODE_TXREADY) + { + return kStatus_I2C_UnexpectedState; + } + + /* Most significant subaddress byte comes first */ + base->MSTDAT = handle->subaddrBuf[handle->transfer.subaddressSize - handle->remainingSubaddr]; + base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK; + if (--(handle->remainingSubaddr)) + { + /* There are still subaddress bytes to be transmitted */ + break; + } + if (handle->remainingBytes) + { + /* There is data to be transferred, if there is write to read turnaround it is necessary to perform + * repeated start */ + handle->state = (transfer->direction == kI2C_Read) ? kStartState : kTransmitDataState; + } + else + { + /* No more data, schedule stop condition */ + handle->state = kStopState; + } + break; + + case kTransmitDataState: + if (master_state != I2C_STAT_MSTCODE_TXREADY) + { + return kStatus_I2C_UnexpectedState; + } + base->MSTDAT = *(handle->buf)++; + base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK; + if (--handle->remainingBytes == 0) + { + /* No more data, schedule stop condition */ + handle->state = kStopState; + } + handle->transferCount++; + break; + + case kReceiveDataState: + if (master_state != I2C_STAT_MSTCODE_RXREADY) + { + return kStatus_I2C_UnexpectedState; + } + *(handle->buf)++ = base->MSTDAT; + if (--handle->remainingBytes) + { + base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK; + } + else + { + /* No more data expected, issue NACK and STOP right away */ + base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; + handle->state = kWaitForCompletionState; + } + handle->transferCount++; + break; + + case kStopState: + if (transfer->flags & kI2C_TransferNoStopFlag) + { + /* Stop condition is omitted, we are done */ + *isDone = true; + handle->state = kIdleState; + break; + } + /* Send stop condition */ + base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; + handle->state = kWaitForCompletionState; + break; + + case kWaitForCompletionState: + *isDone = true; + handle->state = kIdleState; + break; + + case kIdleState: + default: + /* State machine shall not be invoked again once it enters the idle state */ + err = kStatus_I2C_UnexpectedState; + break; + } + + return err; +} + +/*! + * brief Reusable routine to handle master interrupts. + * note This function does not need to be called unless you are reimplementing the + * nonblocking API's interrupt handler routines to add special functionality. + * param base The I2C peripheral base address. + * param handle Pointer to the I2C master driver handle. + */ +void I2C_MasterTransferHandleIRQ(I2C_Type *base, i2c_master_handle_t *handle) +{ + bool isDone; + status_t result; + + /* Don't do anything if we don't have a valid handle. */ + if (!handle) + { + return; + } + + result = I2C_RunTransferStateMachine(base, handle, &isDone); + + if (isDone || (result != kStatus_Success)) + { + /* Restore handle to idle state. */ + handle->state = kIdleState; + + /* Disable internal IRQ enables. */ + I2C_DisableInterrupts(base, kI2C_MasterIrqFlags); + + /* Invoke callback. */ + if (handle->completionCallback) + { + handle->completionCallback(base, handle, result, handle->userData); + } + } +} + +/*! + * @brief Sets the hardware slave state machine to reset + * + * Per documentation, the only the state machine is reset, the configuration settings remain. + * + * @param base The I2C peripheral base address. + */ +static void I2C_SlaveInternalStateMachineReset(I2C_Type *base) +{ + I2C_SlaveEnable(base, false); /* clear SLVEN Slave enable bit */ +} + +/*! + * @brief Compute CLKDIV + * + * This function computes CLKDIV value according to the given bus speed and Flexcomm source clock frequency. + * This setting is used by hardware during slave clock stretching. + * + * @param base The I2C peripheral base address. + * @return status of the operation + */ +static status_t I2C_SlaveDivVal(uint32_t srcClock_Hz, i2c_slave_bus_speed_t busSpeed, uint32_t *divVal) +{ + uint32_t dataSetupTime_ns; + + switch (busSpeed) + { + case kI2C_SlaveStandardMode: + dataSetupTime_ns = 250u; + break; + + case kI2C_SlaveFastMode: + dataSetupTime_ns = 100u; + break; + + case kI2C_SlaveFastModePlus: + dataSetupTime_ns = 50u; + break; + + case kI2C_SlaveHsMode: + dataSetupTime_ns = 10u; + break; + + default: + dataSetupTime_ns = 0; + break; + } + + if (0 == dataSetupTime_ns) + { + return kStatus_InvalidArgument; + } + + /* divVal = (sourceClock_Hz / 1000000) * (dataSetupTime_ns / 1000) */ + *divVal = srcClock_Hz / 1000u; + *divVal = (*divVal) * dataSetupTime_ns; + *divVal = (*divVal) / 1000000u; + + if ((*divVal) > I2C_CLKDIV_DIVVAL_MASK) + { + *divVal = I2C_CLKDIV_DIVVAL_MASK; + } + + return kStatus_Success; +} + +/*! + * @brief Poll wait for the SLVPENDING flag. + * + * Wait for the pending status to be set (SLVPENDING = 1) by polling the STAT register. + * + * @param base The I2C peripheral base address. + * @return status register at time the SLVPENDING bit is read as set + */ +static uint32_t I2C_SlavePollPending(I2C_Type *base) +{ + uint32_t stat; + +#if I2C_RETRY_TIMES + uint32_t waitTimes = I2C_RETRY_TIMES; +#endif + do + { + stat = base->STAT; +#if I2C_RETRY_TIMES + } while ((0u == (stat & I2C_STAT_SLVPENDING_MASK)) && (--waitTimes)); + + if (waitTimes == 0u) + { + return kStatus_I2C_Timeout; + } +#else + } while (0u == (stat & I2C_STAT_SLVPENDING_MASK)); +#endif + + return stat; +} + +/*! + * @brief Invoke event from I2C_SlaveTransferHandleIRQ(). + * + * Sets the event type to transfer structure and invokes the event callback, if it has been + * enabled by eventMask. + * + * @param base The I2C peripheral base address. + * @param handle The I2C slave handle for non-blocking APIs. + * @param event The I2C slave event to invoke. + */ +static void I2C_SlaveInvokeEvent(I2C_Type *base, i2c_slave_handle_t *handle, i2c_slave_transfer_event_t event) +{ + handle->transfer.event = event; + if ((handle->callback) && (handle->transfer.eventMask & event)) + { + handle->callback(base, &handle->transfer, handle->userData); + + /* if after event callback we have data buffer (callback func has added new data), keep transfer busy */ + if (false == handle->isBusy) + { + if (((handle->transfer.txData) && (handle->transfer.txSize)) || + ((handle->transfer.rxData) && (handle->transfer.rxSize))) + { + handle->isBusy = true; + } + } + + /* Clear the transferred count now that we have a new buffer. */ + if ((event == kI2C_SlaveReceiveEvent) || (event == kI2C_SlaveTransmitEvent)) + { + handle->transfer.transferredCount = 0; + } + } +} + +/*! + * @brief Handle slave address match event. + * + * Called by Slave interrupt routine to ACK or NACK the matched address. + * It also determines master direction (read or write). + * + * @param base The I2C peripheral base address. + * @return true if the matched address is ACK'ed + * @return false if the matched address is NACK'ed + */ +static bool I2C_SlaveAddressIRQ(I2C_Type *base, i2c_slave_handle_t *handle) +{ + uint8_t addressByte0; + + addressByte0 = (uint8_t)base->SLVDAT; + + /* store the matched address */ + handle->transfer.receivedAddress = addressByte0; + + /* R/nW */ + if (addressByte0 & 1u) + { + /* if we have no data in this transfer, call callback to get new */ + if ((handle->transfer.txData == NULL) || (handle->transfer.txSize == 0)) + { + I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveTransmitEvent); + } + + /* NACK if we have no data in this transfer. */ + if ((handle->transfer.txData == NULL) || (handle->transfer.txSize == 0)) + { + base->SLVCTL = I2C_SLVCTL_SLVNACK_MASK; + return false; + } + + /* master wants to read, so slave transmit is next state */ + handle->slaveFsm = kI2C_SlaveFsmTransmit; + } + else + { + /* if we have no receive buffer in this transfer, call callback to get new */ + if ((handle->transfer.rxData == NULL) || (handle->transfer.rxSize == 0)) + { + I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveReceiveEvent); + } + + /* NACK if we have no data in this transfer */ + if ((handle->transfer.rxData == NULL) || (handle->transfer.rxSize == 0)) + { + base->SLVCTL = I2C_SLVCTL_SLVNACK_MASK; + return false; + } + + /* master wants write, so slave receive is next state */ + handle->slaveFsm = kI2C_SlaveFsmReceive; + } + + /* continue transaction */ + base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; + + return true; +} + +/*! + * @brief Starts accepting slave transfers. + * + * Call this API after calling I2C_SlaveInit() and I2C_SlaveTransferCreateHandle() to start processing + * transactions driven by an I2C master. The slave monitors the I2C bus and pass events to the + * callback that was passed into the call to I2C_SlaveTransferCreateHandle(). The callback is always invoked + * from the interrupt context. + * + * @param base The I2C peripheral base address. + * @param handle Pointer to #i2c_slave_handle_t structure which stores the transfer state. + * @param txData Data to be transmitted to master in response to master read from slave requests. NULL if slave RX only. + * @param txSize Size of txData buffer in bytes. + * @param rxData Data where received data from master will be stored in response to master write to slave requests. NULL + * if slave TX only. + * @param rxSize Size of rxData buffer in bytes. + * + * @retval #kStatus_Success Slave transfers were successfully started. + * @retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. + */ +static status_t I2C_SlaveTransferNonBlockingInternal(I2C_Type *base, + i2c_slave_handle_t *handle, + const void *txData, + size_t txSize, + void *rxData, + size_t rxSize, + uint32_t eventMask) +{ + status_t status; + + assert(handle); + + status = kStatus_Success; + + /* Disable I2C IRQ sources while we configure stuff. */ + I2C_DisableInterrupts(base, kI2C_SlaveIrqFlags); + + /* Return busy if another transaction is in progress. */ + if (handle->isBusy) + { + status = kStatus_I2C_Busy; + } + + /* Save transfer into handle. */ + handle->transfer.txData = (const uint8_t *)(uintptr_t)txData; + handle->transfer.txSize = txSize; + handle->transfer.rxData = (uint8_t *)rxData; + handle->transfer.rxSize = rxSize; + handle->transfer.transferredCount = 0; + handle->transfer.eventMask = eventMask | kI2C_SlaveTransmitEvent | kI2C_SlaveReceiveEvent; + handle->isBusy = true; + + /* Set the SLVEN bit to 1 in the CFG register. */ + I2C_SlaveEnable(base, true); + + /* Clear w1c flags. */ + base->STAT |= 0u; + + /* Enable I2C internal IRQ sources. */ + I2C_EnableInterrupts(base, kI2C_SlaveIrqFlags); + + return status; +} + +/*! + * brief Starts accepting master read from slave requests. + * + * The function can be called in response to #kI2C_SlaveTransmitEvent callback to start a new slave Tx transfer + * from within the transfer callback. + * + * The set of events received by the callback is customizable. To do so, set the a eventMask parameter to + * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive. + * The #kI2C_SlaveTransmitEvent and #kI2C_SlaveReceiveEvent events are always enabled and do not need + * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and + * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as + * a convenient way to enable all events. + * + * param base The I2C peripheral base address. + * param transfer Pointer to #i2c_slave_transfer_t structure. + * param txData Pointer to data to send to master. + * param txSize Size of txData in bytes. + * param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify + * which events to send to the callback. Other accepted values are 0 to get a default set of + * only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events. + * + * retval kStatus_Success Slave transfers were successfully started. + * retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. + */ +status_t I2C_SlaveSetSendBuffer( + I2C_Type *base, volatile i2c_slave_transfer_t *transfer, const void *txData, size_t txSize, uint32_t eventMask) +{ + return I2C_SlaveTransferNonBlockingInternal(base, transfer->handle, txData, txSize, NULL, 0u, eventMask); +} + +/*! + * brief Starts accepting master write to slave requests. + * + * The function can be called in response to #kI2C_SlaveReceiveEvent callback to start a new slave Rx transfer + * from within the transfer callback. + * + * The set of events received by the callback is customizable. To do so, set the a eventMask parameter to + * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive. + * The #kI2C_SlaveTransmitEvent and #kI2C_SlaveReceiveEvent events are always enabled and do not need + * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and + * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as + * a convenient way to enable all events. + * + * param base The I2C peripheral base address. + * param transfer Pointer to #i2c_slave_transfer_t structure. + * param rxData Pointer to data to store data from master. + * param rxSize Size of rxData in bytes. + * param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify + * which events to send to the callback. Other accepted values are 0 to get a default set of + * only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events. + * + * retval kStatus_Success Slave transfers were successfully started. + * retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. + */ +status_t I2C_SlaveSetReceiveBuffer( + I2C_Type *base, volatile i2c_slave_transfer_t *transfer, void *rxData, size_t rxSize, uint32_t eventMask) +{ + return I2C_SlaveTransferNonBlockingInternal(base, transfer->handle, NULL, 0u, rxData, rxSize, eventMask); +} + +/*! + * brief Configures Slave Address n register. + * + * This function writes new value to Slave Address register. + * + * param base The I2C peripheral base address. + * param addressRegister The module supports multiple address registers. The parameter determines which one shall be + * changed. + * param address The slave address to be stored to the address register for matching. + * param addressDisable Disable matching of the specified address register. + */ +void I2C_SlaveSetAddress(I2C_Type *base, + i2c_slave_address_register_t addressRegister, + uint8_t address, + bool addressDisable) +{ + base->SLVADR[addressRegister] = I2C_SLVADR_SLVADR(address) | I2C_SLVADR_SADISABLE(addressDisable); +} + +/*! + * brief Provides a default configuration for the I2C slave peripheral. + * + * This function provides the following default configuration for the I2C slave peripheral: + * code + * slaveConfig->enableSlave = true; + * slaveConfig->address0.disable = false; + * slaveConfig->address0.address = 0u; + * slaveConfig->address1.disable = true; + * slaveConfig->address2.disable = true; + * slaveConfig->address3.disable = true; + * slaveConfig->busSpeed = kI2C_SlaveStandardMode; + * endcode + * + * After calling this function, override any settings to customize the configuration, + * prior to initializing the master driver with I2C_SlaveInit(). Be sure to override at least the a + * address0.address member of the configuration structure with the desired slave address. + * + * param[out] slaveConfig User provided configuration structure that is set to default values. Refer to + * #i2c_slave_config_t. + */ +void I2C_SlaveGetDefaultConfig(i2c_slave_config_t *slaveConfig) +{ + assert(slaveConfig); + + i2c_slave_config_t mySlaveConfig = {0}; + + /* default config enables slave address 0 match to general I2C call address zero */ + mySlaveConfig.enableSlave = true; + mySlaveConfig.address1.addressDisable = true; + mySlaveConfig.address2.addressDisable = true; + mySlaveConfig.address3.addressDisable = true; + + *slaveConfig = mySlaveConfig; +} + +/*! + * brief Initializes the I2C slave peripheral. + * + * This function enables the peripheral clock and initializes the I2C slave peripheral as described by the user + * provided configuration. + * + * param base The I2C peripheral base address. + * param slaveConfig User provided peripheral configuration. Use I2C_SlaveGetDefaultConfig() to get a set of defaults + * that you can override. + * param srcClock_Hz Frequency in Hertz of the I2C functional clock. Used to calculate CLKDIV value to provide + * enough + * data setup time for master when slave stretches the clock. + */ +status_t I2C_SlaveInit(I2C_Type *base, const i2c_slave_config_t *slaveConfig, uint32_t srcClock_Hz) +{ + status_t status; + uint32_t divVal = 0; + + /* configure data setup time used when slave stretches clock */ + status = I2C_SlaveDivVal(srcClock_Hz, slaveConfig->busSpeed, &divVal); + if (kStatus_Success != status) + { + return status; + } + + FLEXCOMM_Init(base, FLEXCOMM_PERIPH_I2C); + + /* I2C Clock Divider register */ + base->CLKDIV = divVal; + + /* set Slave address */ + I2C_SlaveSetAddress(base, kI2C_SlaveAddressRegister0, slaveConfig->address0.address, + slaveConfig->address0.addressDisable); + I2C_SlaveSetAddress(base, kI2C_SlaveAddressRegister1, slaveConfig->address1.address, + slaveConfig->address1.addressDisable); + I2C_SlaveSetAddress(base, kI2C_SlaveAddressRegister2, slaveConfig->address2.address, + slaveConfig->address2.addressDisable); + I2C_SlaveSetAddress(base, kI2C_SlaveAddressRegister3, slaveConfig->address3.address, + slaveConfig->address3.addressDisable); + + /* set Slave address 0 qual */ + base->SLVQUAL0 = I2C_SLVQUAL0_QUALMODE0(slaveConfig->qualMode) | I2C_SLVQUAL0_SLVQUAL0(slaveConfig->qualAddress); + + /* set Slave enable */ + base->CFG = I2C_CFG_SLVEN(slaveConfig->enableSlave); + + return status; +} + +/*! + * brief Deinitializes the I2C slave peripheral. + * + * This function disables the I2C slave peripheral and gates the clock. It also performs a software + * reset to restore the peripheral to reset conditions. + * + * param base The I2C peripheral base address. + */ +void I2C_SlaveDeinit(I2C_Type *base) +{ + I2C_SlaveEnable(base, false); +} + +/*! + * brief Performs a polling send transfer on the I2C bus. + * + * The function executes blocking address phase and blocking data phase. + * + * param base The I2C peripheral base address. + * param txBuff The pointer to the data to be transferred. + * param txSize The length in bytes of the data to be transferred. + * return kStatus_Success Data has been sent. + * return kStatus_Fail Unexpected slave state (master data write while master read from slave is expected). + */ +status_t I2C_SlaveWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize) +{ + const uint8_t *buf = txBuff; + uint32_t stat; + bool slaveAddress; + bool slaveTransmit; + + /* Set the SLVEN bit to 1 in the CFG register. */ + I2C_SlaveEnable(base, true); + + /* wait for SLVPENDING */ + stat = I2C_SlavePollPending(base); + if (stat == kStatus_I2C_Timeout) + { + return kStatus_I2C_Timeout; + } + + /* Get slave machine state */ + slaveAddress = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_ADDR); + slaveTransmit = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_TX); + + /* in I2C_SlaveSend() it shall be either slaveAddress or slaveTransmit */ + if (!(slaveAddress || slaveTransmit)) + { + I2C_SlaveInternalStateMachineReset(base); + return kStatus_Fail; + } + + if (slaveAddress) + { + /* Acknowledge (ack) the address by setting SLVCONTINUE = 1 in the slave control register */ + base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; + + /* wait for SLVPENDING */ + stat = I2C_SlavePollPending(base); + if (stat == kStatus_I2C_Timeout) + { + return kStatus_I2C_Timeout; + } + } + + /* send bytes up to txSize */ + while (txSize) + { + slaveTransmit = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_TX); + + if (!slaveTransmit) + { + I2C_SlaveInternalStateMachineReset(base); + return kStatus_Fail; + } + + /* Write 8 bits of data to the SLVDAT register */ + base->SLVDAT = I2C_SLVDAT_DATA(*buf); + + /* continue transaction */ + base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; + + /* advance counters and pointers for next data */ + buf++; + txSize--; + + if (txSize) + { + /* wait for SLVPENDING */ + stat = I2C_SlavePollPending(base); + if (stat == kStatus_I2C_Timeout) + { + return kStatus_I2C_Timeout; + } + } + } + + return kStatus_Success; +} + +/*! + * brief Performs a polling receive transfer on the I2C bus. + * + * The function executes blocking address phase and blocking data phase. + * + * param base The I2C peripheral base address. + * param rxBuff The pointer to the data to be transferred. + * param rxSize The length in bytes of the data to be transferred. + * return kStatus_Success Data has been received. + * return kStatus_Fail Unexpected slave state (master data read while master write to slave is expected). + */ +status_t I2C_SlaveReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize) +{ + uint8_t *buf = rxBuff; + uint32_t stat; + bool slaveAddress; + bool slaveReceive; + + /* Set the SLVEN bit to 1 in the CFG register. */ + I2C_SlaveEnable(base, true); + + /* wait for SLVPENDING */ + stat = I2C_SlavePollPending(base); + if (stat == kStatus_I2C_Timeout) + { + return kStatus_I2C_Timeout; + } + + /* Get slave machine state */ + slaveAddress = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_ADDR); + slaveReceive = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_RX); + + /* in I2C_SlaveReceive() it shall be either slaveAddress or slaveReceive */ + if (!(slaveAddress || slaveReceive)) + { + I2C_SlaveInternalStateMachineReset(base); + return kStatus_Fail; + } + + if (slaveAddress) + { + /* Acknowledge (ack) the address by setting SLVCONTINUE = 1 in the slave control register */ + base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; + + /* wait for SLVPENDING */ + stat = I2C_SlavePollPending(base); + if (stat == kStatus_I2C_Timeout) + { + return kStatus_I2C_Timeout; + } + } + + /* receive bytes up to rxSize */ + while (rxSize) + { + slaveReceive = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_RX); + + if (!slaveReceive) + { + I2C_SlaveInternalStateMachineReset(base); + return kStatus_Fail; + } + + /* Read 8 bits of data from the SLVDAT register */ + *buf = (uint8_t)base->SLVDAT; + + /* continue transaction */ + base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; + + /* advance counters and pointers for next data */ + buf++; + rxSize--; + + if (rxSize) + { + /* wait for SLVPENDING */ + stat = I2C_SlavePollPending(base); + if (stat == kStatus_I2C_Timeout) + { + return kStatus_I2C_Timeout; + } + } + } + + return kStatus_Success; +} + +/*! + * brief Creates a new handle for the I2C slave non-blocking APIs. + * + * The creation of a handle is for use with the non-blocking APIs. Once a handle + * is created, there is not a corresponding destroy handle. If the user wants to + * terminate a transfer, the I2C_SlaveTransferAbort() API shall be called. + * + * param base The I2C peripheral base address. + * param[out] handle Pointer to the I2C slave driver handle. + * param callback User provided pointer to the asynchronous callback function. + * param userData User provided pointer to the application callback data. + */ +void I2C_SlaveTransferCreateHandle(I2C_Type *base, + i2c_slave_handle_t *handle, + i2c_slave_transfer_callback_t callback, + void *userData) +{ + uint32_t instance; + + assert(handle); + + /* Clear out the handle. */ + memset(handle, 0, sizeof(*handle)); + + /* Look up instance number */ + instance = I2C_GetInstance(base); + + /* Save base and instance. */ + handle->callback = callback; + handle->userData = userData; + + /* initialize fsm */ + handle->slaveFsm = kI2C_SlaveFsmAddressMatch; + + /* store pointer to handle into transfer struct */ + handle->transfer.handle = handle; + + FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)I2C_SlaveTransferHandleIRQ, handle); + + /* Clear internal IRQ enables and enable NVIC IRQ. */ + I2C_DisableInterrupts(base, kI2C_SlaveIrqFlags); + EnableIRQ(s_i2cIRQ[instance]); +} + +/*! + * brief Starts accepting slave transfers. + * + * Call this API after calling I2C_SlaveInit() and I2C_SlaveTransferCreateHandle() to start processing + * transactions driven by an I2C master. The slave monitors the I2C bus and pass events to the + * callback that was passed into the call to I2C_SlaveTransferCreateHandle(). The callback is always invoked + * from the interrupt context. + * + * If no slave Tx transfer is busy, a master read from slave request invokes #kI2C_SlaveTransmitEvent callback. + * If no slave Rx transfer is busy, a master write to slave request invokes #kI2C_SlaveReceiveEvent callback. + * + * The set of events received by the callback is customizable. To do so, set the a eventMask parameter to + * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive. + * The #kI2C_SlaveTransmitEvent and #kI2C_SlaveReceiveEvent events are always enabled and do not need + * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and + * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as + * a convenient way to enable all events. + * + * param base The I2C peripheral base address. + * param handle Pointer to i2c_slave_handle_t structure which stores the transfer state. + * param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify + * which events to send to the callback. Other accepted values are 0 to get a default set of + * only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events. + * + * retval kStatus_Success Slave transfers were successfully started. + * retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. + */ +status_t I2C_SlaveTransferNonBlocking(I2C_Type *base, i2c_slave_handle_t *handle, uint32_t eventMask) +{ + return I2C_SlaveTransferNonBlockingInternal(base, handle, NULL, 0u, NULL, 0u, eventMask); +} + +/*! + * brief Gets the slave transfer remaining bytes during a interrupt non-blocking transfer. + * + * param base I2C base pointer. + * param handle pointer to i2c_slave_handle_t structure. + * param count Number of bytes transferred so far by the non-blocking transaction. + * retval kStatus_InvalidArgument count is Invalid. + * retval kStatus_Success Successfully return the count. + */ +status_t I2C_SlaveTransferGetCount(I2C_Type *base, i2c_slave_handle_t *handle, size_t *count) +{ + assert(handle); + + if (!count) + { + return kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + if (!handle->isBusy) + { + *count = 0; + return kStatus_NoTransferInProgress; + } + + /* For an active transfer, just return the count from the handle. */ + *count = handle->transfer.transferredCount; + + return kStatus_Success; +} + +/*! + * brief Aborts the slave non-blocking transfers. + * note This API could be called at any time to stop slave for handling the bus events. + * param base The I2C peripheral base address. + * param handle Pointer to i2c_slave_handle_t structure which stores the transfer state. + * retval kStatus_Success + * retval #kStatus_I2C_Idle + */ +void I2C_SlaveTransferAbort(I2C_Type *base, i2c_slave_handle_t *handle) +{ + /* Disable I2C IRQ sources while we configure stuff. */ + I2C_DisableInterrupts(base, kI2C_SlaveIrqFlags); + + /* Set the SLVEN bit to 0 in the CFG register. */ + I2C_SlaveEnable(base, false); + + handle->isBusy = false; + handle->transfer.txSize = 0; + handle->transfer.rxSize = 0; +} + +/*! + * brief Reusable routine to handle slave interrupts. + * note This function does not need to be called unless you are reimplementing the + * non blocking API's interrupt handler routines to add special functionality. + * param base The I2C peripheral base address. + * param handle Pointer to i2c_slave_handle_t structure which stores the transfer state. + */ +void I2C_SlaveTransferHandleIRQ(I2C_Type *base, i2c_slave_handle_t *handle) +{ + uint32_t i2cStatus = base->STAT; + + if (i2cStatus & I2C_STAT_SLVDESEL_MASK) + { + I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveDeselectedEvent); + I2C_SlaveClearStatusFlags(base, I2C_STAT_SLVDESEL_MASK); + } + + /* SLVPENDING flag is cleared by writing I2C_SLVCTL_SLVCONTINUE_MASK to SLVCTL register */ + if (i2cStatus & I2C_STAT_SLVPENDING_MASK) + { + bool slaveAddress = (((i2cStatus & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_ADDR); + + if (slaveAddress) + { + I2C_SlaveAddressIRQ(base, handle); + I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveAddressMatchEvent); + } + else + { + switch (handle->slaveFsm) + { + case kI2C_SlaveFsmReceive: + { + bool slaveReceive = + (((i2cStatus & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_RX); + + if (slaveReceive) + { + /* if we have no receive buffer in this transfer, call callback to get new */ + if ((handle->transfer.rxData == NULL) || (handle->transfer.rxSize == 0)) + { + I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveReceiveEvent); + } + + /* receive a byte */ + if ((handle->transfer.rxData) && (handle->transfer.rxSize)) + { + /* continue transaction */ + base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; + *(handle->transfer.rxData) = (uint8_t)base->SLVDAT; + (handle->transfer.rxSize)--; + (handle->transfer.rxData)++; + (handle->transfer.transferredCount)++; + } + + /* is this last transaction for this transfer? allow next transaction */ + if ((0 == handle->transfer.rxSize) && (0 == handle->transfer.txSize)) + { + handle->isBusy = false; + I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveCompletionEvent); + } + } + else + { + base->SLVCTL = I2C_SLVCTL_SLVNACK_MASK; + } + } + break; + + case kI2C_SlaveFsmTransmit: + { + bool slaveTransmit = + (((i2cStatus & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_TX); + + if (slaveTransmit) + { + /* if we have no data in this transfer, call callback to get new */ + if ((handle->transfer.txData == NULL) || (handle->transfer.txSize == 0)) + { + I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveTransmitEvent); + } + + /* transmit a byte */ + if ((handle->transfer.txData) && (handle->transfer.txSize)) + { + base->SLVDAT = *(handle->transfer.txData); + /* continue transaction */ + base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; + (handle->transfer.txSize)--; + (handle->transfer.txData)++; + (handle->transfer.transferredCount)++; + } + + /* is this last transaction for this transfer? allow next transaction */ + if ((0 == handle->transfer.rxSize) && (0 == handle->transfer.txSize)) + { + handle->isBusy = false; + I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveCompletionEvent); + } + } + else + { + base->SLVCTL = I2C_SLVCTL_SLVNACK_MASK; + } + } + break; + + default: + /* incorrect state, slv_abort()? */ + break; + } + } + } +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2c.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2c.h new file mode 100644 index 000000000..50bc3588c --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2c.h @@ -0,0 +1,1042 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_I2C_H_ +#define _FSL_I2C_H_ + +#include +#include "fsl_device_registers.h" +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +#define I2C_CFG_MASK 0x1f + +/*! + * @addtogroup i2c_driver + * @{ + */ + +/*! @file */ + +/*! @name Driver version */ +/*@{*/ +/*! @brief I2C driver version 2.0.5. */ +#define FSL_I2C_DRIVER_VERSION (MAKE_VERSION(2, 0, 5)) +/*@}*/ + +/*! @brief Retry times for waiting flag. */ +#ifndef I2C_RETRY_TIMES +#define I2C_RETRY_TIMES 0U /* Define to zero means keep waiting until the flag is assert/deassert. */ +#endif + +/* definitions for MSTCODE bits in I2C Status register STAT */ +#define I2C_STAT_MSTCODE_IDLE (0) /*!< Master Idle State Code */ +#define I2C_STAT_MSTCODE_RXREADY (1) /*!< Master Receive Ready State Code */ +#define I2C_STAT_MSTCODE_TXREADY (2) /*!< Master Transmit Ready State Code */ +#define I2C_STAT_MSTCODE_NACKADR (3) /*!< Master NACK by slave on address State Code */ +#define I2C_STAT_MSTCODE_NACKDAT (4) /*!< Master NACK by slave on data State Code */ + +/* definitions for SLVSTATE bits in I2C Status register STAT */ +#define I2C_STAT_SLVST_ADDR (0) +#define I2C_STAT_SLVST_RX (1) +#define I2C_STAT_SLVST_TX (2) + +/*! @brief I2C status return codes. */ +enum _i2c_status +{ + kStatus_I2C_Busy = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 0), /*!< The master is already performing a transfer. */ + kStatus_I2C_Idle = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 1), /*!< The slave driver is idle. */ + kStatus_I2C_Nak = + MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 2), /*!< The slave device sent a NAK in response to a byte. */ + kStatus_I2C_InvalidParameter = + MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 3), /*!< Unable to proceed due to invalid parameter. */ + kStatus_I2C_BitError = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 4), /*!< Transferred bit was not seen on the bus. */ + kStatus_I2C_ArbitrationLost = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 5), /*!< Arbitration lost error. */ + kStatus_I2C_NoTransferInProgress = + MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 6), /*!< Attempt to abort a transfer when one is not in progress. */ + kStatus_I2C_DmaRequestFail = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 7), /*!< DMA request failed. */ + kStatus_I2C_StartStopError = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 8), + kStatus_I2C_UnexpectedState = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 9), + kStatus_I2C_Timeout = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 10), /*!< Timeout poling status flags. */ + kStatus_I2C_Addr_Nak = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 11), /*!< NAK received for Address */ +}; + +/*! @} */ + +/*! + * @addtogroup i2c_master_driver + * @{ + */ + +/*! + * @brief I2C master peripheral flags. + * + * @note These enums are meant to be OR'd together to form a bit mask. + */ +enum _i2c_master_flags +{ + kI2C_MasterPendingFlag = I2C_STAT_MSTPENDING_MASK, /*!< The I2C module is waiting for software interaction. */ + kI2C_MasterArbitrationLostFlag = + I2C_STAT_MSTARBLOSS_MASK, /*!< The arbitration of the bus was lost. There was collision on the bus */ + kI2C_MasterStartStopErrorFlag = + I2C_STAT_MSTSTSTPERR_MASK /*!< There was an error during start or stop phase of the transaction. */ +}; + +/*! @brief Direction of master and slave transfers. */ +typedef enum _i2c_direction +{ + kI2C_Write = 0U, /*!< Master transmit. */ + kI2C_Read = 1U /*!< Master receive. */ +} i2c_direction_t; + +/*! + * @brief Structure with settings to initialize the I2C master module. + * + * This structure holds configuration settings for the I2C peripheral. To initialize this + * structure to reasonable defaults, call the I2C_MasterGetDefaultConfig() function and + * pass a pointer to your configuration structure instance. + * + * The configuration structure can be made constant so it resides in flash. + */ +typedef struct _i2c_master_config +{ + bool enableMaster; /*!< Whether to enable master mode. */ + uint32_t baudRate_Bps; /*!< Desired baud rate in bits per second. */ + bool enableTimeout; /*!< Enable internal timeout function. */ +} i2c_master_config_t; + +/* Forward declaration of the transfer descriptor and handle typedefs. */ +/*! @brief I2C master transfer typedef */ +typedef struct _i2c_master_transfer i2c_master_transfer_t; + +/*! @brief I2C master handle typedef */ +typedef struct _i2c_master_handle i2c_master_handle_t; + +/*! + * @brief Master completion callback function pointer type. + * + * This callback is used only for the non-blocking master transfer API. Specify the callback you wish to use + * in the call to I2C_MasterTransferCreateHandle(). + * + * @param base The I2C peripheral base address. + * @param completionStatus Either kStatus_Success or an error code describing how the transfer completed. + * @param userData Arbitrary pointer-sized value passed from the application. + */ +typedef void (*i2c_master_transfer_callback_t)(I2C_Type *base, + i2c_master_handle_t *handle, + status_t completionStatus, + void *userData); + +/*! + * @brief Transfer option flags. + * + * @note These enumerations are intended to be OR'd together to form a bit mask of options for + * the #_i2c_master_transfer::flags field. + */ +enum _i2c_master_transfer_flags +{ + kI2C_TransferDefaultFlag = 0x00U, /*!< Transfer starts with a start signal, stops with a stop signal. */ + kI2C_TransferNoStartFlag = 0x01U, /*!< Don't send a start condition, address, and sub address */ + kI2C_TransferRepeatedStartFlag = 0x02U, /*!< Send a repeated start condition */ + kI2C_TransferNoStopFlag = 0x04U, /*!< Don't send a stop condition. */ +}; + +/*! @brief States for the state machine used by transactional APIs. */ +enum _i2c_transfer_states +{ + kIdleState = 0, + kTransmitSubaddrState, + kTransmitDataState, + kReceiveDataState, + kReceiveLastDataState, + kStartState, + kStopState, + kWaitForCompletionState +}; + +/*! + * @brief Non-blocking transfer descriptor structure. + * + * This structure is used to pass transaction parameters to the I2C_MasterTransferNonBlocking() API. + */ +struct _i2c_master_transfer +{ + uint32_t flags; /*!< Bit mask of options for the transfer. See enumeration #_i2c_master_transfer_flags for available + options. Set to 0 or #kI2C_TransferDefaultFlag for normal transfers. */ + uint16_t slaveAddress; /*!< The 7-bit slave address. */ + i2c_direction_t direction; /*!< Either #kI2C_Read or #kI2C_Write. */ + uint32_t subaddress; /*!< Sub address. Transferred MSB first. */ + size_t subaddressSize; /*!< Length of sub address to send in bytes. Maximum size is 4 bytes. */ + void *data; /*!< Pointer to data to transfer. */ + size_t dataSize; /*!< Number of bytes to transfer. */ +}; + +/*! + * @brief Driver handle for master non-blocking APIs. + * @note The contents of this structure are private and subject to change. + */ +struct _i2c_master_handle +{ + uint8_t state; /*!< Transfer state machine current state. */ + uint32_t transferCount; /*!< Indicates progress of the transfer */ + uint32_t remainingBytes; /*!< Remaining byte count in current state. */ + uint8_t *buf; /*!< Buffer pointer for current state. */ + uint32_t remainingSubaddr; + uint8_t subaddrBuf[4]; + i2c_master_transfer_t transfer; /*!< Copy of the current transfer info. */ + i2c_master_transfer_callback_t completionCallback; /*!< Callback function pointer. */ + void *userData; /*!< Application data passed to callback. */ +}; + +/*! @} */ + +/*! + * @addtogroup i2c_slave_driver + * @{ + */ + +/*! + * @brief I2C slave peripheral flags. + * + * @note These enums are meant to be OR'd together to form a bit mask. + */ +enum _i2c_slave_flags +{ + kI2C_SlavePendingFlag = I2C_STAT_SLVPENDING_MASK, /*!< The I2C module is waiting for software interaction. */ + kI2C_SlaveNotStretching = + I2C_STAT_SLVNOTSTR_MASK, /*!< Indicates whether the slave is currently stretching clock (0 = yes, 1 = no). */ + kI2C_SlaveSelected = I2C_STAT_SLVSEL_MASK, /*!< Indicates whether the slave is selected by an address match. */ + kI2C_SaveDeselected = + I2C_STAT_SLVDESEL_MASK /*!< Indicates that slave was previously deselected (deselect event took place, w1c). */ +}; + +/*! @brief I2C slave address register. */ +typedef enum _i2c_slave_address_register +{ + kI2C_SlaveAddressRegister0 = 0U, /*!< Slave Address 0 register. */ + kI2C_SlaveAddressRegister1 = 1U, /*!< Slave Address 1 register. */ + kI2C_SlaveAddressRegister2 = 2U, /*!< Slave Address 2 register. */ + kI2C_SlaveAddressRegister3 = 3U, /*!< Slave Address 3 register. */ +} i2c_slave_address_register_t; + +/*! @brief Data structure with 7-bit Slave address and Slave address disable. */ +typedef struct _i2c_slave_address +{ + uint8_t address; /*!< 7-bit Slave address SLVADR. */ + bool addressDisable; /*!< Slave address disable SADISABLE. */ +} i2c_slave_address_t; + +/*! @brief I2C slave address match options. */ +typedef enum _i2c_slave_address_qual_mode +{ + kI2C_QualModeMask = 0U, /*!< The SLVQUAL0 field (qualAddress) is used as a logical mask for matching address0. */ + kI2C_QualModeExtend = + 1U, /*!< The SLVQUAL0 (qualAddress) field is used to extend address 0 matching in a range of addresses. */ +} i2c_slave_address_qual_mode_t; + +/*! @brief I2C slave bus speed options. */ +typedef enum _i2c_slave_bus_speed +{ + kI2C_SlaveStandardMode = 0U, + kI2C_SlaveFastMode = 1U, + kI2C_SlaveFastModePlus = 2U, + kI2C_SlaveHsMode = 3U, +} i2c_slave_bus_speed_t; + +/*! + * @brief Structure with settings to initialize the I2C slave module. + * + * This structure holds configuration settings for the I2C slave peripheral. To initialize this + * structure to reasonable defaults, call the I2C_SlaveGetDefaultConfig() function and + * pass a pointer to your configuration structure instance. + * + * The configuration structure can be made constant so it resides in flash. + */ +typedef struct _i2c_slave_config +{ + i2c_slave_address_t address0; /*!< Slave's 7-bit address and disable. */ + i2c_slave_address_t address1; /*!< Alternate slave 7-bit address and disable. */ + i2c_slave_address_t address2; /*!< Alternate slave 7-bit address and disable. */ + i2c_slave_address_t address3; /*!< Alternate slave 7-bit address and disable. */ + i2c_slave_address_qual_mode_t qualMode; /*!< Qualify mode for slave address 0. */ + uint8_t qualAddress; /*!< Slave address qualifier for address 0. */ + i2c_slave_bus_speed_t + busSpeed; /*!< Slave bus speed mode. If the slave function stretches SCL to allow for software response, it must + provide sufficient data setup time to the master before releasing the stretched clock. + This is accomplished by inserting one clock time of CLKDIV at that point. + The #busSpeed value is used to configure CLKDIV + such that one clock time is greater than the tSU;DAT value noted + in the I2C bus specification for the I2C mode that is being used. + If the #busSpeed mode is unknown at compile time, use the longest data setup time + kI2C_SlaveStandardMode (250 ns) */ + bool enableSlave; /*!< Enable slave mode. */ +} i2c_slave_config_t; + +/*! + * @brief Set of events sent to the callback for non blocking slave transfers. + * + * These event enumerations are used for two related purposes. First, a bit mask created by OR'ing together + * events is passed to I2C_SlaveTransferNonBlocking() in order to specify which events to enable. + * Then, when the slave callback is invoked, it is passed the current event through its @a transfer + * parameter. + * + * @note These enumerations are meant to be OR'd together to form a bit mask of events. + */ +typedef enum _i2c_slave_transfer_event +{ + kI2C_SlaveAddressMatchEvent = 0x01U, /*!< Received the slave address after a start or repeated start. */ + kI2C_SlaveTransmitEvent = 0x02U, /*!< Callback is requested to provide data to transmit + (slave-transmitter role). */ + kI2C_SlaveReceiveEvent = 0x04U, /*!< Callback is requested to provide a buffer in which to place received + data (slave-receiver role). */ + kI2C_SlaveCompletionEvent = 0x20U, /*!< All data in the active transfer have been consumed. */ + kI2C_SlaveDeselectedEvent = + 0x40U, /*!< The slave function has become deselected (SLVSEL flag changing from 1 to 0. */ + + /*! Bit mask of all available events. */ + kI2C_SlaveAllEvents = kI2C_SlaveAddressMatchEvent | kI2C_SlaveTransmitEvent | kI2C_SlaveReceiveEvent | + kI2C_SlaveCompletionEvent | kI2C_SlaveDeselectedEvent, +} i2c_slave_transfer_event_t; + +/*! @brief I2C slave handle typedef. */ +typedef struct _i2c_slave_handle i2c_slave_handle_t; + +/*! @brief I2C slave transfer structure */ +typedef struct _i2c_slave_transfer +{ + i2c_slave_handle_t *handle; /*!< Pointer to handle that contains this transfer. */ + i2c_slave_transfer_event_t event; /*!< Reason the callback is being invoked. */ + uint8_t receivedAddress; /*!< Matching address send by master. 7-bits plus R/nW bit0 */ + uint32_t eventMask; /*!< Mask of enabled events. */ + uint8_t *rxData; /*!< Transfer buffer for receive data */ + const uint8_t *txData; /*!< Transfer buffer for transmit data */ + size_t txSize; /*!< Transfer size */ + size_t rxSize; /*!< Transfer size */ + size_t transferredCount; /*!< Number of bytes transferred during this transfer. */ + status_t completionStatus; /*!< Success or error code describing how the transfer completed. Only applies for + #kI2C_SlaveCompletionEvent. */ +} i2c_slave_transfer_t; + +/*! + * @brief Slave event callback function pointer type. + * + * This callback is used only for the slave non-blocking transfer API. To install a callback, + * use the I2C_SlaveSetCallback() function after you have created a handle. + * + * @param base Base address for the I2C instance on which the event occurred. + * @param transfer Pointer to transfer descriptor containing values passed to and/or from the callback. + * @param userData Arbitrary pointer-sized value passed from the application. + */ +typedef void (*i2c_slave_transfer_callback_t)(I2C_Type *base, volatile i2c_slave_transfer_t *transfer, void *userData); + +/*! + * @brief I2C slave software finite state machine states. + */ +typedef enum _i2c_slave_fsm +{ + kI2C_SlaveFsmAddressMatch = 0u, + kI2C_SlaveFsmReceive = 2u, + kI2C_SlaveFsmTransmit = 3u, +} i2c_slave_fsm_t; + +/*! + * @brief I2C slave handle structure. + * @note The contents of this structure are private and subject to change. + */ +struct _i2c_slave_handle +{ + volatile i2c_slave_transfer_t transfer; /*!< I2C slave transfer. */ + volatile bool isBusy; /*!< Whether transfer is busy. */ + volatile i2c_slave_fsm_t slaveFsm; /*!< slave transfer state machine. */ + i2c_slave_transfer_callback_t callback; /*!< Callback function called at transfer event. */ + void *userData; /*!< Callback parameter passed to callback. */ +}; + +/*! @} */ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @addtogroup i2c_master_driver + * @{ + */ + +/*! @name Initialization and deinitialization */ +/*@{*/ + +/*! + * @brief Provides a default configuration for the I2C master peripheral. + * + * This function provides the following default configuration for the I2C master peripheral: + * @code + * masterConfig->enableMaster = true; + * masterConfig->baudRate_Bps = 100000U; + * masterConfig->enableTimeout = false; + * @endcode + * + * After calling this function, you can override any settings in order to customize the configuration, + * prior to initializing the master driver with I2C_MasterInit(). + * + * @param[out] masterConfig User provided configuration structure for default values. Refer to #i2c_master_config_t. + */ +void I2C_MasterGetDefaultConfig(i2c_master_config_t *masterConfig); + +/*! + * @brief Initializes the I2C master peripheral. + * + * This function enables the peripheral clock and initializes the I2C master peripheral as described by the user + * provided configuration. A software reset is performed prior to configuration. + * + * @param base The I2C peripheral base address. + * @param masterConfig User provided peripheral configuration. Use I2C_MasterGetDefaultConfig() to get a set of + * defaults + * that you can override. + * @param srcClock_Hz Frequency in Hertz of the I2C functional clock. Used to calculate the baud rate divisors, + * filter widths, and timeout periods. + */ +void I2C_MasterInit(I2C_Type *base, const i2c_master_config_t *masterConfig, uint32_t srcClock_Hz); + +/*! + * @brief Deinitializes the I2C master peripheral. + * + * This function disables the I2C master peripheral and gates the clock. It also performs a software + * reset to restore the peripheral to reset conditions. + * + * @param base The I2C peripheral base address. + */ +void I2C_MasterDeinit(I2C_Type *base); + +/*! + * @brief Returns an instance number given a base address. + * + * If an invalid base address is passed, debug builds will assert. Release builds will just return + * instance number 0. + * + * @param base The I2C peripheral base address. + * @return I2C instance number starting from 0. + */ +uint32_t I2C_GetInstance(I2C_Type *base); + +/*! + * @brief Performs a software reset. + * + * Restores the I2C master peripheral to reset conditions. + * + * @param base The I2C peripheral base address. + */ +static inline void I2C_MasterReset(I2C_Type *base) +{ +} + +/*! + * @brief Enables or disables the I2C module as master. + * + * @param base The I2C peripheral base address. + * @param enable Pass true to enable or false to disable the specified I2C as master. + */ +static inline void I2C_MasterEnable(I2C_Type *base, bool enable) +{ + if (enable) + { + base->CFG = (base->CFG & I2C_CFG_MASK) | I2C_CFG_MSTEN_MASK; + } + else + { + base->CFG = (base->CFG & I2C_CFG_MASK) & ~I2C_CFG_MSTEN_MASK; + } +} + +/*@}*/ + +/*! @name Status */ +/*@{*/ + +/*! + * @brief Gets the I2C status flags. + * + * A bit mask with the state of all I2C status flags is returned. For each flag, the corresponding bit + * in the return value is set if the flag is asserted. + * + * @param base The I2C peripheral base address. + * @return State of the status flags: + * - 1: related status flag is set. + * - 0: related status flag is not set. + * @see _i2c_master_flags + */ +static inline uint32_t I2C_GetStatusFlags(I2C_Type *base) +{ + return base->STAT; +} + +/*! + * @brief Clears the I2C master status flag state. + * + * The following status register flags can be cleared: + * - #kI2C_MasterArbitrationLostFlag + * - #kI2C_MasterStartStopErrorFlag + * + * Attempts to clear other flags has no effect. + * + * @param base The I2C peripheral base address. + * @param statusMask A bitmask of status flags that are to be cleared. The mask is composed of + * #_i2c_master_flags enumerators OR'd together. You may pass the result of a previous call to + * I2C_GetStatusFlags(). + * @see _i2c_master_flags. + */ +static inline void I2C_MasterClearStatusFlags(I2C_Type *base, uint32_t statusMask) +{ + /* Allow clearing just master status flags */ + base->STAT = statusMask & (I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK); +} + +/*@}*/ + +/*! @name Interrupts */ +/*@{*/ + +/*! + * @brief Enables the I2C master interrupt requests. + * + * @param base The I2C peripheral base address. + * @param interruptMask Bit mask of interrupts to enable. See #_i2c_master_flags for the set + * of constants that should be OR'd together to form the bit mask. + */ +static inline void I2C_EnableInterrupts(I2C_Type *base, uint32_t interruptMask) +{ + base->INTENSET = interruptMask; +} + +/*! + * @brief Disables the I2C master interrupt requests. + * + * @param base The I2C peripheral base address. + * @param interruptMask Bit mask of interrupts to disable. See #_i2c_master_flags for the set + * of constants that should be OR'd together to form the bit mask. + */ +static inline void I2C_DisableInterrupts(I2C_Type *base, uint32_t interruptMask) +{ + base->INTENCLR = interruptMask; +} + +/*! + * @brief Returns the set of currently enabled I2C master interrupt requests. + * + * @param base The I2C peripheral base address. + * @return A bitmask composed of #_i2c_master_flags enumerators OR'd together to indicate the + * set of enabled interrupts. + */ +static inline uint32_t I2C_GetEnabledInterrupts(I2C_Type *base) +{ + return base->INTSTAT; +} + +/*@}*/ + +/*! @name Bus operations */ +/*@{*/ + +/*! + * @brief Sets the I2C bus frequency for master transactions. + * + * The I2C master is automatically disabled and re-enabled as necessary to configure the baud + * rate. Do not call this function during a transfer, or the transfer is aborted. + * + * @param base The I2C peripheral base address. + * @param srcClock_Hz I2C functional clock frequency in Hertz. + * @param baudRate_Bps Requested bus frequency in bits per second. + */ +void I2C_MasterSetBaudRate(I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz); + +/*! + * @brief Returns whether the bus is idle. + * + * Requires the master mode to be enabled. + * + * @param base The I2C peripheral base address. + * @retval true Bus is busy. + * @retval false Bus is idle. + */ +static inline bool I2C_MasterGetBusIdleState(I2C_Type *base) +{ + /* True if MSTPENDING flag is set and MSTSTATE is zero == idle */ + return ((base->STAT & (I2C_STAT_MSTPENDING_MASK | I2C_STAT_MSTSTATE_MASK)) == I2C_STAT_MSTPENDING_MASK); +} + +/*! + * @brief Sends a START on the I2C bus. + * + * This function is used to initiate a new master mode transfer by sending the START signal. + * The slave address is sent following the I2C START signal. + * + * @param base I2C peripheral base pointer + * @param address 7-bit slave device address. + * @param direction Master transfer directions(transmit/receive). + * @retval kStatus_Success Successfully send the start signal. + * @retval kStatus_I2C_Busy Current bus is busy. + */ +status_t I2C_MasterStart(I2C_Type *base, uint8_t address, i2c_direction_t direction); + +/*! + * @brief Sends a STOP signal on the I2C bus. + * + * @retval kStatus_Success Successfully send the stop signal. + * @retval kStatus_I2C_Timeout Send stop signal failed, timeout. + */ +status_t I2C_MasterStop(I2C_Type *base); + +/*! + * @brief Sends a REPEATED START on the I2C bus. + * + * @param base I2C peripheral base pointer + * @param address 7-bit slave device address. + * @param direction Master transfer directions(transmit/receive). + * @retval kStatus_Success Successfully send the start signal. + * @retval kStatus_I2C_Busy Current bus is busy but not occupied by current I2C master. + */ +static inline status_t I2C_MasterRepeatedStart(I2C_Type *base, uint8_t address, i2c_direction_t direction) +{ + return I2C_MasterStart(base, address, direction); +} + +/*! + * @brief Performs a polling send transfer on the I2C bus. + * + * Sends up to @a txSize number of bytes to the previously addressed slave device. The slave may + * reply with a NAK to any byte in order to terminate the transfer early. If this happens, this + * function returns #kStatus_I2C_Nak. + * + * @param base The I2C peripheral base address. + * @param txBuff The pointer to the data to be transferred. + * @param txSize The length in bytes of the data to be transferred. + * @param flags Transfer control flag to control special behavior like suppressing start or stop, for normal transfers + * use kI2C_TransferDefaultFlag + * @retval kStatus_Success Data was sent successfully. + * @retval #kStatus_I2C_Busy Another master is currently utilizing the bus. + * @retval #kStatus_I2C_Nak The slave device sent a NAK in response to a byte. + * @retval #kStatus_I2C_ArbitrationLost Arbitration lost error. + */ +status_t I2C_MasterWriteBlocking(I2C_Type *base, const void *txBuff, size_t txSize, uint32_t flags); + +/*! + * @brief Performs a polling receive transfer on the I2C bus. + * + * @param base The I2C peripheral base address. + * @param rxBuff The pointer to the data to be transferred. + * @param rxSize The length in bytes of the data to be transferred. + * @param flags Transfer control flag to control special behavior like suppressing start or stop, for normal transfers + * use kI2C_TransferDefaultFlag + * @retval kStatus_Success Data was received successfully. + * @retval #kStatus_I2C_Busy Another master is currently utilizing the bus. + * @retval #kStatus_I2C_Nak The slave device sent a NAK in response to a byte. + * @retval #kStatus_I2C_ArbitrationLost Arbitration lost error. + */ +status_t I2C_MasterReadBlocking(I2C_Type *base, void *rxBuff, size_t rxSize, uint32_t flags); + +/*! + * @brief Performs a master polling transfer on the I2C bus. + * + * @note The API does not return until the transfer succeeds or fails due + * to arbitration lost or receiving a NAK. + * + * @param base I2C peripheral base address. + * @param xfer Pointer to the transfer structure. + * @retval kStatus_Success Successfully complete the data transmission. + * @retval kStatus_I2C_Busy Previous transmission still not finished. + * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout. + * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. + * @retval kStataus_I2C_Nak Transfer error, receive NAK during transfer. + */ +status_t I2C_MasterTransferBlocking(I2C_Type *base, i2c_master_transfer_t *xfer); + +/*@}*/ + +/*! @name Non-blocking */ +/*@{*/ + +/*! + * @brief Creates a new handle for the I2C master non-blocking APIs. + * + * The creation of a handle is for use with the non-blocking APIs. Once a handle + * is created, there is not a corresponding destroy handle. If the user wants to + * terminate a transfer, the I2C_MasterTransferAbort() API shall be called. + * + * @param base The I2C peripheral base address. + * @param[out] handle Pointer to the I2C master driver handle. + * @param callback User provided pointer to the asynchronous callback function. + * @param userData User provided pointer to the application callback data. + */ +void I2C_MasterTransferCreateHandle(I2C_Type *base, + i2c_master_handle_t *handle, + i2c_master_transfer_callback_t callback, + void *userData); + +/*! + * @brief Performs a non-blocking transaction on the I2C bus. + * + * @param base The I2C peripheral base address. + * @param handle Pointer to the I2C master driver handle. + * @param xfer The pointer to the transfer descriptor. + * @retval kStatus_Success The transaction was started successfully. + * @retval #kStatus_I2C_Busy Either another master is currently utilizing the bus, or a non-blocking + * transaction is already in progress. + */ +status_t I2C_MasterTransferNonBlocking(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer); + +/*! + * @brief Returns number of bytes transferred so far. + * @param base The I2C peripheral base address. + * @param handle Pointer to the I2C master driver handle. + * @param[out] count Number of bytes transferred so far by the non-blocking transaction. + * @retval kStatus_Success + * @retval #kStatus_I2C_Busy + */ +status_t I2C_MasterTransferGetCount(I2C_Type *base, i2c_master_handle_t *handle, size_t *count); + +/*! + * @brief Terminates a non-blocking I2C master transmission early. + * + * @note It is not safe to call this function from an IRQ handler that has a higher priority than the + * I2C peripheral's IRQ priority. + * + * @param base The I2C peripheral base address. + * @param handle Pointer to the I2C master driver handle. + * @retval kStatus_Success A transaction was successfully aborted. + * @retval #kStatus_I2C_Timeout Timeout during polling for flags. + */ +status_t I2C_MasterTransferAbort(I2C_Type *base, i2c_master_handle_t *handle); + +/*@}*/ + +/*! @name IRQ handler */ +/*@{*/ + +/*! + * @brief Reusable routine to handle master interrupts. + * @note This function does not need to be called unless you are reimplementing the + * nonblocking API's interrupt handler routines to add special functionality. + * @param base The I2C peripheral base address. + * @param handle Pointer to the I2C master driver handle. + */ +void I2C_MasterTransferHandleIRQ(I2C_Type *base, i2c_master_handle_t *handle); + +/*@}*/ + +/*! @} */ /* end of i2c_master_driver */ + +/*! + * @addtogroup i2c_slave_driver + * @{ + */ + +/*! @name Slave initialization and deinitialization */ +/*@{*/ + +/*! + * @brief Provides a default configuration for the I2C slave peripheral. + * + * This function provides the following default configuration for the I2C slave peripheral: + * @code + * slaveConfig->enableSlave = true; + * slaveConfig->address0.disable = false; + * slaveConfig->address0.address = 0u; + * slaveConfig->address1.disable = true; + * slaveConfig->address2.disable = true; + * slaveConfig->address3.disable = true; + * slaveConfig->busSpeed = kI2C_SlaveStandardMode; + * @endcode + * + * After calling this function, override any settings to customize the configuration, + * prior to initializing the master driver with I2C_SlaveInit(). Be sure to override at least the @a + * address0.address member of the configuration structure with the desired slave address. + * + * @param[out] slaveConfig User provided configuration structure that is set to default values. Refer to + * #i2c_slave_config_t. + */ +void I2C_SlaveGetDefaultConfig(i2c_slave_config_t *slaveConfig); + +/*! + * @brief Initializes the I2C slave peripheral. + * + * This function enables the peripheral clock and initializes the I2C slave peripheral as described by the user + * provided configuration. + * + * @param base The I2C peripheral base address. + * @param slaveConfig User provided peripheral configuration. Use I2C_SlaveGetDefaultConfig() to get a set of defaults + * that you can override. + * @param srcClock_Hz Frequency in Hertz of the I2C functional clock. Used to calculate CLKDIV value to provide + * enough + * data setup time for master when slave stretches the clock. + */ +status_t I2C_SlaveInit(I2C_Type *base, const i2c_slave_config_t *slaveConfig, uint32_t srcClock_Hz); + +/*! + * @brief Configures Slave Address n register. + * + * This function writes new value to Slave Address register. + * + * @param base The I2C peripheral base address. + * @param addressRegister The module supports multiple address registers. The parameter determines which one shall be + * changed. + * @param address The slave address to be stored to the address register for matching. + * @param addressDisable Disable matching of the specified address register. + */ +void I2C_SlaveSetAddress(I2C_Type *base, + i2c_slave_address_register_t addressRegister, + uint8_t address, + bool addressDisable); + +/*! + * @brief Deinitializes the I2C slave peripheral. + * + * This function disables the I2C slave peripheral and gates the clock. It also performs a software + * reset to restore the peripheral to reset conditions. + * + * @param base The I2C peripheral base address. + */ +void I2C_SlaveDeinit(I2C_Type *base); + +/*! + * @brief Enables or disables the I2C module as slave. + * + * @param base The I2C peripheral base address. + * @param enable True to enable or flase to disable. + */ +static inline void I2C_SlaveEnable(I2C_Type *base, bool enable) +{ + /* Set or clear the SLVEN bit in the CFG register. */ + base->CFG = I2C_CFG_SLVEN(enable); +} + +/*@}*/ /* end of Slave initialization and deinitialization */ + +/*! @name Slave status */ +/*@{*/ + +/*! + * @brief Clears the I2C status flag state. + * + * The following status register flags can be cleared: + * - slave deselected flag + * + * Attempts to clear other flags has no effect. + * + * @param base The I2C peripheral base address. + * @param statusMask A bitmask of status flags that are to be cleared. The mask is composed of + * #_i2c_slave_flags enumerators OR'd together. You may pass the result of a previous call to + * I2C_SlaveGetStatusFlags(). + * @see _i2c_slave_flags. + */ +static inline void I2C_SlaveClearStatusFlags(I2C_Type *base, uint32_t statusMask) +{ + /* Allow clearing just slave status flags */ + base->STAT = statusMask & I2C_STAT_SLVDESEL_MASK; +} + +/*@}*/ /* end of Slave status */ + +/*! @name Slave bus operations */ +/*@{*/ + +/*! + * @brief Performs a polling send transfer on the I2C bus. + * + * The function executes blocking address phase and blocking data phase. + * + * @param base The I2C peripheral base address. + * @param txBuff The pointer to the data to be transferred. + * @param txSize The length in bytes of the data to be transferred. + * @return kStatus_Success Data has been sent. + * @return kStatus_Fail Unexpected slave state (master data write while master read from slave is expected). + */ +status_t I2C_SlaveWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize); + +/*! + * @brief Performs a polling receive transfer on the I2C bus. + * + * The function executes blocking address phase and blocking data phase. + * + * @param base The I2C peripheral base address. + * @param rxBuff The pointer to the data to be transferred. + * @param rxSize The length in bytes of the data to be transferred. + * @return kStatus_Success Data has been received. + * @return kStatus_Fail Unexpected slave state (master data read while master write to slave is expected). + */ +status_t I2C_SlaveReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize); + +/*@}*/ /* end of Slave bus operations */ + +/*! @name Slave non-blocking */ +/*@{*/ + +/*! + * @brief Creates a new handle for the I2C slave non-blocking APIs. + * + * The creation of a handle is for use with the non-blocking APIs. Once a handle + * is created, there is not a corresponding destroy handle. If the user wants to + * terminate a transfer, the I2C_SlaveTransferAbort() API shall be called. + * + * @param base The I2C peripheral base address. + * @param[out] handle Pointer to the I2C slave driver handle. + * @param callback User provided pointer to the asynchronous callback function. + * @param userData User provided pointer to the application callback data. + */ +void I2C_SlaveTransferCreateHandle(I2C_Type *base, + i2c_slave_handle_t *handle, + i2c_slave_transfer_callback_t callback, + void *userData); + +/*! + * @brief Starts accepting slave transfers. + * + * Call this API after calling I2C_SlaveInit() and I2C_SlaveTransferCreateHandle() to start processing + * transactions driven by an I2C master. The slave monitors the I2C bus and pass events to the + * callback that was passed into the call to I2C_SlaveTransferCreateHandle(). The callback is always invoked + * from the interrupt context. + * + * If no slave Tx transfer is busy, a master read from slave request invokes #kI2C_SlaveTransmitEvent callback. + * If no slave Rx transfer is busy, a master write to slave request invokes #kI2C_SlaveReceiveEvent callback. + * + * The set of events received by the callback is customizable. To do so, set the @a eventMask parameter to + * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive. + * The #kI2C_SlaveTransmitEvent and #kI2C_SlaveReceiveEvent events are always enabled and do not need + * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and + * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as + * a convenient way to enable all events. + * + * @param base The I2C peripheral base address. + * @param handle Pointer to i2c_slave_handle_t structure which stores the transfer state. + * @param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify + * which events to send to the callback. Other accepted values are 0 to get a default set of + * only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events. + * + * @retval kStatus_Success Slave transfers were successfully started. + * @retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. + */ +status_t I2C_SlaveTransferNonBlocking(I2C_Type *base, i2c_slave_handle_t *handle, uint32_t eventMask); + +/*! + * @brief Starts accepting master read from slave requests. + * + * The function can be called in response to #kI2C_SlaveTransmitEvent callback to start a new slave Tx transfer + * from within the transfer callback. + * + * The set of events received by the callback is customizable. To do so, set the @a eventMask parameter to + * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive. + * The #kI2C_SlaveTransmitEvent and #kI2C_SlaveReceiveEvent events are always enabled and do not need + * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and + * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as + * a convenient way to enable all events. + * + * @param base The I2C peripheral base address. + * @param transfer Pointer to #i2c_slave_transfer_t structure. + * @param txData Pointer to data to send to master. + * @param txSize Size of txData in bytes. + * @param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify + * which events to send to the callback. Other accepted values are 0 to get a default set of + * only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events. + * + * @retval kStatus_Success Slave transfers were successfully started. + * @retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. + */ +status_t I2C_SlaveSetSendBuffer( + I2C_Type *base, volatile i2c_slave_transfer_t *transfer, const void *txData, size_t txSize, uint32_t eventMask); + +/*! + * @brief Starts accepting master write to slave requests. + * + * The function can be called in response to #kI2C_SlaveReceiveEvent callback to start a new slave Rx transfer + * from within the transfer callback. + * + * The set of events received by the callback is customizable. To do so, set the @a eventMask parameter to + * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive. + * The #kI2C_SlaveTransmitEvent and #kI2C_SlaveReceiveEvent events are always enabled and do not need + * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and + * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as + * a convenient way to enable all events. + * + * @param base The I2C peripheral base address. + * @param transfer Pointer to #i2c_slave_transfer_t structure. + * @param rxData Pointer to data to store data from master. + * @param rxSize Size of rxData in bytes. + * @param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify + * which events to send to the callback. Other accepted values are 0 to get a default set of + * only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events. + * + * @retval kStatus_Success Slave transfers were successfully started. + * @retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. + */ +status_t I2C_SlaveSetReceiveBuffer( + I2C_Type *base, volatile i2c_slave_transfer_t *transfer, void *rxData, size_t rxSize, uint32_t eventMask); + +/*! + * @brief Returns the slave address sent by the I2C master. + * + * This function should only be called from the address match event callback #kI2C_SlaveAddressMatchEvent. + * + * @param base The I2C peripheral base address. + * @param transfer The I2C slave transfer. + * @return The 8-bit address matched by the I2C slave. Bit 0 contains the R/w direction bit, and + * the 7-bit slave address is in the upper 7 bits. + */ +static inline uint32_t I2C_SlaveGetReceivedAddress(I2C_Type *base, volatile i2c_slave_transfer_t *transfer) +{ + return transfer->receivedAddress; +} + +/*! + * @brief Aborts the slave non-blocking transfers. + * @note This API could be called at any time to stop slave for handling the bus events. + * @param base The I2C peripheral base address. + * @param handle Pointer to i2c_slave_handle_t structure which stores the transfer state. + * @retval kStatus_Success + * @retval #kStatus_I2C_Idle + */ +void I2C_SlaveTransferAbort(I2C_Type *base, i2c_slave_handle_t *handle); + +/*! + * @brief Gets the slave transfer remaining bytes during a interrupt non-blocking transfer. + * + * @param base I2C base pointer. + * @param handle pointer to i2c_slave_handle_t structure. + * @param count Number of bytes transferred so far by the non-blocking transaction. + * @retval kStatus_InvalidArgument count is Invalid. + * @retval kStatus_Success Successfully return the count. + */ +status_t I2C_SlaveTransferGetCount(I2C_Type *base, i2c_slave_handle_t *handle, size_t *count); + +/*@}*/ /* end of Slave non-blocking */ + +/*! @name Slave IRQ handler */ +/*@{*/ + +/*! + * @brief Reusable routine to handle slave interrupts. + * @note This function does not need to be called unless you are reimplementing the + * non blocking API's interrupt handler routines to add special functionality. + * @param base The I2C peripheral base address. + * @param handle Pointer to i2c_slave_handle_t structure which stores the transfer state. + */ +void I2C_SlaveTransferHandleIRQ(I2C_Type *base, i2c_slave_handle_t *handle); + +/*@}*/ /* end of Slave IRQ handler */ + +/*! @} */ /* end of i2c_slave_driver */ + +#if defined(__cplusplus) +} +#endif + +#endif /* _FSL_I2C_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2c_dma.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2c_dma.c new file mode 100644 index 000000000..98cb88f28 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2c_dma.c @@ -0,0 +1,588 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_i2c_dma.h" +#include "fsl_flexcomm.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexcomm_i2c_dma" +#endif + +/*transfer = *xfer; + transfer = &(handle->transfer); + + handle->transferCount = 0; + handle->remainingBytesDMA = 0; + handle->buf = (uint8_t *)transfer->data; + handle->remainingSubaddr = 0; + + if (transfer->flags & kI2C_TransferNoStartFlag) + { + /* Start condition shall be ommited, switch directly to next phase */ + if (transfer->dataSize == 0) + { + handle->state = kStopState; + } + else if (handle->transfer.direction == kI2C_Write) + { + handle->state = xfer->dataSize = kTransmitDataState; + } + else if (handle->transfer.direction == kI2C_Read) + { + handle->state = (xfer->dataSize == 1) ? kReceiveLastDataState : kReceiveDataState; + } + else + { + return kStatus_I2C_InvalidParameter; + } + } + else + { + if (transfer->subaddressSize != 0) + { + int i; + uint32_t subaddress; + + if (transfer->subaddressSize > sizeof(handle->subaddrBuf)) + { + return kStatus_I2C_InvalidParameter; + } + + /* Prepare subaddress transmit buffer, most significant byte is stored at the lowest address */ + subaddress = xfer->subaddress; + for (i = xfer->subaddressSize - 1; i >= 0; i--) + { + handle->subaddrBuf[i] = subaddress & 0xff; + subaddress >>= 8; + } + handle->remainingSubaddr = transfer->subaddressSize; + } + + handle->state = kStartState; + } + + return kStatus_Success; +} + +static void I2C_RunDMATransfer(I2C_Type *base, i2c_master_dma_handle_t *handle) +{ + int transfer_size; + dma_transfer_config_t xferConfig; + + /* Update transfer count */ + handle->transferCount = handle->buf - (uint8_t *)handle->transfer.data; + + /* Check if there is anything to be transferred at all */ + if (handle->remainingBytesDMA == 0) + { + /* No data to be transferrred, disable DMA */ + base->MSTCTL = 0; + return; + } + + /* Calculate transfer size */ + transfer_size = handle->remainingBytesDMA; + if (transfer_size > I2C_MAX_DMA_TRANSFER_COUNT) + { + transfer_size = I2C_MAX_DMA_TRANSFER_COUNT; + } + + switch (handle->transfer.direction) + { + case kI2C_Write: + DMA_PrepareTransfer(&xferConfig, handle->buf, (void *)&base->MSTDAT, sizeof(uint8_t), transfer_size, + kDMA_MemoryToPeripheral, NULL); + break; + + case kI2C_Read: + DMA_PrepareTransfer(&xferConfig, (void *)&base->MSTDAT, handle->buf, sizeof(uint8_t), transfer_size, + kDMA_PeripheralToMemory, NULL); + break; + + default: + /* This should never happen */ + assert(0); + break; + } + + DMA_SubmitTransfer(handle->dmaHandle, &xferConfig); + DMA_StartTransfer(handle->dmaHandle); + + handle->remainingBytesDMA -= transfer_size; + handle->buf += transfer_size; +} + +/*! + * @brief Execute states until the transfer is done. + * @param handle Master nonblocking driver handle. + * @param[out] isDone Set to true if the transfer has completed. + * @retval #kStatus_Success + * @retval #kStatus_I2C_ArbitrationLost + * @retval #kStatus_I2C_Nak + */ +static status_t I2C_RunTransferStateMachineDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, bool *isDone) +{ + uint32_t status; + uint32_t master_state; + struct _i2c_master_transfer *transfer; + dma_transfer_config_t xferConfig; + status_t err; + uint32_t start_flag = 0; + + transfer = &(handle->transfer); + + *isDone = false; + + status = I2C_GetStatusFlags(base); + + if (status & I2C_STAT_MSTARBLOSS_MASK) + { + I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK); + DMA_AbortTransfer(handle->dmaHandle); + base->MSTCTL = 0; + return kStatus_I2C_ArbitrationLost; + } + + if (status & I2C_STAT_MSTSTSTPERR_MASK) + { + I2C_MasterClearStatusFlags(base, I2C_STAT_MSTSTSTPERR_MASK); + DMA_AbortTransfer(handle->dmaHandle); + base->MSTCTL = 0; + return kStatus_I2C_StartStopError; + } + + if ((status & I2C_STAT_MSTPENDING_MASK) == 0) + { + return kStatus_I2C_Busy; + } + + /* Get the state of the I2C module */ + master_state = (status & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; + + if ((master_state == I2C_STAT_MSTCODE_NACKADR) || (master_state == I2C_STAT_MSTCODE_NACKDAT)) + { + /* Slave NACKed last byte, issue stop and return error */ + DMA_AbortTransfer(handle->dmaHandle); + base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; + handle->state = kWaitForCompletionState; + return kStatus_I2C_Nak; + } + + err = kStatus_Success; + + if (handle->state == kStartState) + { + /* set start flag for later use */ + start_flag = I2C_MSTCTL_MSTSTART_MASK; + + if (handle->remainingSubaddr) + { + base->MSTDAT = (uint32_t)transfer->slaveAddress << 1; + handle->state = kTransmitSubaddrState; + } + else if (transfer->direction == kI2C_Write) + { + base->MSTDAT = (uint32_t)transfer->slaveAddress << 1; + if (transfer->dataSize == 0) + { + /* No data to be transferred, initiate start and schedule stop */ + base->MSTCTL = I2C_MSTCTL_MSTSTART_MASK; + handle->state = kStopState; + return err; + } + handle->state = kTransmitDataState; + } + else if ((transfer->direction == kI2C_Read) && (transfer->dataSize > 0)) + { + base->MSTDAT = ((uint32_t)transfer->slaveAddress << 1) | 1u; + if (transfer->dataSize == 1) + { + /* The very last byte is always received by means of SW */ + base->MSTCTL = I2C_MSTCTL_MSTSTART_MASK; + handle->state = kReceiveLastDataState; + return err; + } + handle->state = kReceiveDataState; + } + else + { + handle->state = kIdleState; + err = kStatus_I2C_UnexpectedState; + return err; + } + } + + switch (handle->state) + { + case kTransmitSubaddrState: + if ((master_state != I2C_STAT_MSTCODE_TXREADY) && (!start_flag)) + { + return kStatus_I2C_UnexpectedState; + } + + base->MSTCTL = start_flag | I2C_MSTCTL_MSTDMA_MASK; + + /* Prepare and submit DMA transfer. */ + DMA_PrepareTransfer(&xferConfig, handle->subaddrBuf, (void *)&base->MSTDAT, sizeof(uint8_t), + handle->remainingSubaddr, kDMA_MemoryToPeripheral, NULL); + DMA_SubmitTransfer(handle->dmaHandle, &xferConfig); + DMA_StartTransfer(handle->dmaHandle); + handle->remainingSubaddr = 0; + if (transfer->dataSize) + { + /* There is data to be transferred, if there is write to read turnaround it is necessary to perform + * repeated start */ + handle->state = (transfer->direction == kI2C_Read) ? kStartState : kTransmitDataState; + } + else + { + /* No more data, schedule stop condition */ + handle->state = kStopState; + } + break; + + case kTransmitDataState: + if ((master_state != I2C_STAT_MSTCODE_TXREADY) && (!start_flag)) + { + return kStatus_I2C_UnexpectedState; + } + + base->MSTCTL = start_flag | I2C_MSTCTL_MSTDMA_MASK; + handle->remainingBytesDMA = handle->transfer.dataSize; + + I2C_RunDMATransfer(base, handle); + + /* Schedule stop condition */ + handle->state = kStopState; + break; + + case kReceiveDataState: + if ((master_state != I2C_STAT_MSTCODE_RXREADY) && (!start_flag)) + { + return kStatus_I2C_UnexpectedState; + } + + base->MSTCTL = start_flag | I2C_MSTCTL_MSTDMA_MASK; + handle->remainingBytesDMA = handle->transfer.dataSize - 1; + + I2C_RunDMATransfer(base, handle); + + /* Schedule reception of last data byte */ + handle->state = kReceiveLastDataState; + break; + + case kReceiveLastDataState: + if (master_state != I2C_STAT_MSTCODE_RXREADY) + { + return kStatus_I2C_UnexpectedState; + } + + ((uint8_t *)transfer->data)[transfer->dataSize - 1] = base->MSTDAT; + handle->transferCount++; + + /* No more data expected, issue NACK and STOP right away */ + base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; + handle->state = kWaitForCompletionState; + break; + + case kStopState: + if (transfer->flags & kI2C_TransferNoStopFlag) + { + /* Stop condition is omitted, we are done */ + *isDone = true; + handle->state = kIdleState; + break; + } + /* Send stop condition */ + base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; + handle->state = kWaitForCompletionState; + break; + + case kWaitForCompletionState: + *isDone = true; + handle->state = kIdleState; + break; + + case kStartState: + case kIdleState: + default: + /* State machine shall not be invoked again once it enters the idle state */ + err = kStatus_I2C_UnexpectedState; + break; + } + + return err; +} + +void I2C_MasterTransferDMAHandleIRQ(I2C_Type *base, i2c_master_dma_handle_t *handle) +{ + bool isDone; + status_t result; + + /* Don't do anything if we don't have a valid handle. */ + if (!handle) + { + return; + } + + result = I2C_RunTransferStateMachineDMA(base, handle, &isDone); + + if (isDone || (result != kStatus_Success)) + { + /* Disable internal IRQ enables. */ + I2C_DisableInterrupts(base, + I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_MSTARBLOSS_MASK | I2C_INTSTAT_MSTSTSTPERR_MASK); + + /* Invoke callback. */ + if (handle->completionCallback) + { + handle->completionCallback(base, handle, result, handle->userData); + } + } +} + +static void I2C_MasterTransferCallbackDMA(dma_handle_t *handle, void *userData) +{ + i2c_master_dma_private_handle_t *dmaPrivateHandle; + + /* Don't do anything if we don't have a valid handle. */ + if (!handle) + { + return; + } + + dmaPrivateHandle = (i2c_master_dma_private_handle_t *)userData; + I2C_RunDMATransfer(dmaPrivateHandle->base, dmaPrivateHandle->handle); +} + +/*! + * brief Init the I2C handle which is used in transactional functions + * + * param base I2C peripheral base address + * param handle pointer to i2c_master_dma_handle_t structure + * param callback pointer to user callback function + * param userData user param passed to the callback function + * param dmaHandle DMA handle pointer + */ +void I2C_MasterTransferCreateHandleDMA(I2C_Type *base, + i2c_master_dma_handle_t *handle, + i2c_master_dma_transfer_callback_t callback, + void *userData, + dma_handle_t *dmaHandle) +{ + uint32_t instance; + + assert(handle); + assert(dmaHandle); + + /* Zero handle. */ + memset(handle, 0, sizeof(*handle)); + + /* Look up instance number */ + instance = I2C_GetInstance(base); + + /* Set the user callback and userData. */ + handle->completionCallback = callback; + handle->userData = userData; + + FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)I2C_MasterTransferDMAHandleIRQ, handle); + + /* Clear internal IRQ enables and enable NVIC IRQ. */ + I2C_DisableInterrupts(base, + I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_MSTARBLOSS_MASK | I2C_INTSTAT_MSTSTSTPERR_MASK); + EnableIRQ(s_i2cIRQ[instance]); + + /* Set the handle for DMA. */ + handle->dmaHandle = dmaHandle; + + s_dmaPrivateHandle[instance].base = base; + s_dmaPrivateHandle[instance].handle = handle; + + DMA_SetCallback(dmaHandle, (dma_callback)I2C_MasterTransferCallbackDMA, &s_dmaPrivateHandle[instance]); +} + +/*! + * brief Performs a master dma non-blocking transfer on the I2C bus + * + * param base I2C peripheral base address + * param handle pointer to i2c_master_dma_handle_t structure + * param xfer pointer to transfer structure of i2c_master_transfer_t + * retval kStatus_Success Sucessully complete the data transmission. + * retval kStatus_I2C_Busy Previous transmission still not finished. + * retval kStatus_I2C_Timeout Transfer error, wait signal timeout. + * retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. + * retval kStataus_I2C_Nak Transfer error, receive Nak during transfer. + */ +status_t I2C_MasterTransferDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, i2c_master_transfer_t *xfer) +{ + status_t result; + + assert(handle); + assert(xfer); + assert(xfer->subaddressSize <= sizeof(xfer->subaddress)); + + /* Return busy if another transaction is in progress. */ + if (handle->state != kIdleState) + { + return kStatus_I2C_Busy; + } + + /* Prepare transfer state machine. */ + result = I2C_InitTransferStateMachineDMA(base, handle, xfer); + + /* Clear error flags. */ + I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK); + + /* Enable I2C internal IRQ sources */ + I2C_EnableInterrupts(base, + I2C_INTSTAT_MSTARBLOSS_MASK | I2C_INTSTAT_MSTSTSTPERR_MASK | I2C_INTSTAT_MSTPENDING_MASK); + + return result; +} + +/*! + * brief Get master transfer status during a dma non-blocking transfer + * + * param base I2C peripheral base address + * param handle pointer to i2c_master_dma_handle_t structure + * param count Number of bytes transferred so far by the non-blocking transaction. + */ +status_t I2C_MasterTransferGetCountDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, size_t *count) +{ + assert(handle); + + if (!count) + { + return kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + if (handle->state == kIdleState) + { + *count = 0; + return kStatus_NoTransferInProgress; + } + + /* There is no necessity to disable interrupts as we read a single integer value */ + *count = handle->transferCount; + return kStatus_Success; +} + +/*! + * brief Abort a master dma non-blocking transfer in a early time + * + * param base I2C peripheral base address + * param handle pointer to i2c_master_dma_handle_t structure + */ +void I2C_MasterTransferAbortDMA(I2C_Type *base, i2c_master_dma_handle_t *handle) +{ + uint32_t status; + uint32_t master_state; + + if (handle->state != kIdleState) + { + DMA_AbortTransfer(handle->dmaHandle); + + /* Disable DMA */ + base->MSTCTL = 0; + + /* Disable internal IRQ enables. */ + I2C_DisableInterrupts(base, + I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_MSTARBLOSS_MASK | I2C_INTSTAT_MSTSTSTPERR_MASK); + + /* Wait until module is ready */ + do + { + status = I2C_GetStatusFlags(base); + } while ((status & I2C_STAT_MSTPENDING_MASK) == 0); + + /* Clear controller state. */ + I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK); + + /* Get the state of the I2C module */ + master_state = (status & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; + + if (master_state != I2C_STAT_MSTCODE_IDLE) + { + /* Send a stop command to finalize the transfer. */ + base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; + + /* Wait until module is ready */ + do + { + status = I2C_GetStatusFlags(base); + } while ((status & I2C_STAT_MSTPENDING_MASK) == 0); + + /* Clear controller state. */ + I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK); + } + + /* Reset the state to idle. */ + handle->state = kIdleState; + } +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2c_dma.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2c_dma.h new file mode 100644 index 000000000..1e0d5eb71 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2c_dma.h @@ -0,0 +1,120 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_I2C_DMA_H_ +#define _FSL_I2C_DMA_H_ + +#include "fsl_i2c.h" +#include "fsl_dma.h" + +/*! + * @addtogroup i2c_dma_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief I2C DMA driver version 2.0.3. */ +#define FSL_I2C_DMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) +/*@}*/ + +/*! @brief Maximum lenght of single DMA transfer (determined by capability of the DMA engine) */ +#define I2C_MAX_DMA_TRANSFER_COUNT 1024 + +/*! @brief I2C master dma handle typedef. */ +typedef struct _i2c_master_dma_handle i2c_master_dma_handle_t; + +/*! @brief I2C master dma transfer callback typedef. */ +typedef void (*i2c_master_dma_transfer_callback_t)(I2C_Type *base, + i2c_master_dma_handle_t *handle, + status_t status, + void *userData); + +/*! @brief I2C master dma transfer structure. */ +struct _i2c_master_dma_handle +{ + uint8_t state; /*!< Transfer state machine current state. */ + uint32_t transferCount; /*!< Indicates progress of the transfer */ + uint32_t remainingBytesDMA; /*!< Remaining byte count to be transferred using DMA. */ + uint8_t *buf; /*!< Buffer pointer for current state. */ + uint32_t remainingSubaddr; + uint8_t subaddrBuf[4]; + dma_handle_t *dmaHandle; /*!< The DMA handler used. */ + i2c_master_transfer_t transfer; /*!< Copy of the current transfer info. */ + i2c_master_dma_transfer_callback_t completionCallback; /*!< Callback function called after dma transfer finished. */ + void *userData; /*!< Callback parameter passed to callback function. */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /*_cplusplus. */ + +/*! + * @name I2C Block DMA Transfer Operation + * @{ + */ + +/*! + * @brief Init the I2C handle which is used in transactional functions + * + * @param base I2C peripheral base address + * @param handle pointer to i2c_master_dma_handle_t structure + * @param callback pointer to user callback function + * @param userData user param passed to the callback function + * @param dmaHandle DMA handle pointer + */ +void I2C_MasterTransferCreateHandleDMA(I2C_Type *base, + i2c_master_dma_handle_t *handle, + i2c_master_dma_transfer_callback_t callback, + void *userData, + dma_handle_t *dmaHandle); + +/*! + * @brief Performs a master dma non-blocking transfer on the I2C bus + * + * @param base I2C peripheral base address + * @param handle pointer to i2c_master_dma_handle_t structure + * @param xfer pointer to transfer structure of i2c_master_transfer_t + * @retval kStatus_Success Sucessully complete the data transmission. + * @retval kStatus_I2C_Busy Previous transmission still not finished. + * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout. + * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. + * @retval kStataus_I2C_Nak Transfer error, receive Nak during transfer. + */ +status_t I2C_MasterTransferDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, i2c_master_transfer_t *xfer); + +/*! + * @brief Get master transfer status during a dma non-blocking transfer + * + * @param base I2C peripheral base address + * @param handle pointer to i2c_master_dma_handle_t structure + * @param count Number of bytes transferred so far by the non-blocking transaction. + */ +status_t I2C_MasterTransferGetCountDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, size_t *count); + +/*! + * @brief Abort a master dma non-blocking transfer in a early time + * + * @param base I2C peripheral base address + * @param handle pointer to i2c_master_dma_handle_t structure + */ +void I2C_MasterTransferAbortDMA(I2C_Type *base, i2c_master_dma_handle_t *handle); + +/* @} */ +#if defined(__cplusplus) +} +#endif /*_cplusplus. */ +/*@}*/ +#endif /*_FSL_I2C_DMA_H_*/ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2s.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2s.c new file mode 100644 index 000000000..d3c6206b4 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2s.c @@ -0,0 +1,886 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_i2s.h" +#include "fsl_flexcomm.h" +#include + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexcomm_i2s" +#endif + +/* TODO - absent in device header files, should be there */ +#define I2S_FIFOCFG_TXI2SE0_MASK (0x4U) +#define I2S_FIFOCFG_TXI2SE0_SHIFT (2U) +#define I2S_FIFOCFG_TXI2SE0(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_TXI2SE0_SHIFT)) & I2S_FIFOCFG_TXI2SE0_MASK) +#define I2S_FIFOCFG_PACK48_MASK (0x8U) +#define I2S_FIFOCFG_PACK48_SHIFT (3U) +#define I2S_FIFOCFG_PACK48(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_PACK48_SHIFT)) & I2S_FIFOCFG_PACK48_MASK) + +/*! @brief I2S states. */ +enum _i2s_state +{ + kI2S_StateIdle = 0x0, /*!< Not performing transfer */ + kI2S_StateTx, /*!< Performing transmit */ + kI2S_StateTxWaitToWriteDummyData, /*!< Wait on FIFO in order to write final dummy data there */ + kI2S_StateTxWaitForEmptyFifo, /*!< Wait for FIFO to be flushed */ + kI2S_StateRx, /*!< Performing receive */ +}; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +static void I2S_Config(I2S_Type *base, const i2s_config_t *config); +static void I2S_TxEnable(I2S_Type *base, bool enable); +static void I2S_RxEnable(I2S_Type *base, bool enable); +static status_t I2S_ValidateBuffer(i2s_handle_t *handle, i2s_transfer_t *transfer); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief Array to map i2c instance number to base address. */ +static const uint32_t s_i2sBaseAddrs[FSL_FEATURE_SOC_I2S_COUNT] = I2S_BASE_ADDRS; + +/*! @brief IRQ name array */ +static const IRQn_Type s_i2sIRQ[] = I2S_IRQS; + +/******************************************************************************* + * Code + ******************************************************************************/ +/*! + * @brief Returns an instance number given a base address. + * + * If an invalid base address is passed, debug builds will assert. Release builds will just return + * instance number 0. + * + * @param base The I2S peripheral base address. + * @return I2S instance number starting from 0. + */ +uint32_t I2S_GetInstance(I2S_Type *base) +{ + int i; + for (i = 0; i < FSL_FEATURE_SOC_I2S_COUNT; i++) + { + if ((uint32_t)base == s_i2sBaseAddrs[i]) + { + return i; + } + } + assert(false); + return 0; +} + +void I2S_TxInit(I2S_Type *base, const i2s_config_t *config) +{ + uint32_t cfg = 0U; + uint32_t trig = 0U; + + FLEXCOMM_Init(base, FLEXCOMM_PERIPH_I2S_TX); + I2S_Config(base, config); + + /* Configure FIFO */ + + cfg |= I2S_FIFOCFG_ENABLETX(1U); /* enable TX FIFO */ + cfg |= I2S_FIFOCFG_EMPTYTX(1U); /* empty TX FIFO */ + cfg |= I2S_FIFOCFG_TXI2SE0(config->txEmptyZero); /* transmit zero when buffer becomes empty or last item */ + cfg |= I2S_FIFOCFG_PACK48(config->pack48); /* set pack 48-bit format or not */ + trig |= I2S_FIFOTRIG_TXLVLENA(1U); /* enable TX FIFO trigger */ + trig |= I2S_FIFOTRIG_TXLVL(config->watermark); /* set TX FIFO trigger level */ + + base->FIFOCFG = cfg; + base->FIFOTRIG = trig; +} + +void I2S_RxInit(I2S_Type *base, const i2s_config_t *config) +{ + uint32_t cfg = 0U; + uint32_t trig = 0U; + + FLEXCOMM_Init(base, FLEXCOMM_PERIPH_I2S_RX); + I2S_Config(base, config); + + /* Configure FIFO */ + + cfg |= I2S_FIFOCFG_ENABLERX(1U); /* enable RX FIFO */ + cfg |= I2S_FIFOCFG_EMPTYRX(1U); /* empty RX FIFO */ + cfg |= I2S_FIFOCFG_PACK48(config->pack48); /* set pack 48-bit format or not */ + trig |= I2S_FIFOTRIG_RXLVLENA(1U); /* enable RX FIFO trigger */ + trig |= I2S_FIFOTRIG_RXLVL(config->watermark); /* set RX FIFO trigger level */ + + base->FIFOCFG = cfg; + base->FIFOTRIG = trig; +} + +void I2S_TxGetDefaultConfig(i2s_config_t *config) +{ + config->masterSlave = kI2S_MasterSlaveNormalMaster; + config->mode = kI2S_ModeI2sClassic; + config->rightLow = false; + config->leftJust = false; +#if (defined(FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION) && FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION) + config->pdmData = false; +#endif + config->sckPol = false; + config->wsPol = false; + config->divider = 1U; + config->oneChannel = false; + config->dataLength = 16U; + config->frameLength = 32U; + config->position = 0U; + config->watermark = 4U; + config->txEmptyZero = true; + config->pack48 = false; +} + +void I2S_RxGetDefaultConfig(i2s_config_t *config) +{ + config->masterSlave = kI2S_MasterSlaveNormalSlave; + config->mode = kI2S_ModeI2sClassic; + config->rightLow = false; + config->leftJust = false; +#if (defined(FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION) && FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION) + config->pdmData = false; +#endif + config->sckPol = false; + config->wsPol = false; + config->divider = 1U; + config->oneChannel = false; + config->dataLength = 16U; + config->frameLength = 32U; + config->position = 0U; + config->watermark = 4U; + config->txEmptyZero = false; + config->pack48 = false; +} + +static void I2S_Config(I2S_Type *base, const i2s_config_t *config) +{ + assert(config); + + uint32_t cfg1 = 0U; + uint32_t cfg2 = 0U; + + /* set master/slave configuration */ + cfg1 |= I2S_CFG1_MSTSLVCFG(config->masterSlave); + + /* set I2S mode */ + cfg1 |= I2S_CFG1_MODE(config->mode); + + /* set right low (channel swap) */ + cfg1 |= I2S_CFG1_RIGHTLOW(config->rightLow); + + /* set data justification */ + cfg1 |= I2S_CFG1_LEFTJUST(config->leftJust); + +#if (defined(FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION) && FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION) + if (FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_HAS_DMIC_INTERCONNECTIONn((FLEXCOMM_Type *)base) > 0) + { + /* set source to PDM dmic */ + cfg1 |= I2S_CFG1_PDMDATA(config->pdmData); + } +#endif + + /* set SCLK polarity */ + cfg1 |= I2S_CFG1_SCK_POL(config->sckPol); + + /* set WS polarity */ + cfg1 |= I2S_CFG1_WS_POL(config->wsPol); + + /* set mono mode */ + cfg1 |= I2S_CFG1_ONECHANNEL(config->oneChannel); + + /* set data length */ + cfg1 |= I2S_CFG1_DATALEN(config->dataLength - 1U); + + /* set frame length */ + cfg2 |= I2S_CFG2_FRAMELEN(config->frameLength - 1U); + + /* set data position of this channel pair within the frame */ + cfg2 |= I2S_CFG2_POSITION(config->position); + + /* write to registers */ + base->CFG1 = cfg1; + base->CFG2 = cfg2; + + /* set the clock divider */ + base->DIV = I2S_DIV_DIV(config->divider - 1U); +} + +void I2S_Deinit(I2S_Type *base) +{ + /* TODO gate FLEXCOMM clock via FLEXCOMM driver */ +} + +static void I2S_TxEnable(I2S_Type *base, bool enable) +{ + if (enable) + { + I2S_EnableInterrupts(base, kI2S_TxErrorFlag | kI2S_TxLevelFlag); + I2S_Enable(base); + } + else + { + I2S_DisableInterrupts(base, kI2S_TxErrorFlag | kI2S_TxLevelFlag); + I2S_Disable(base); + base->FIFOCFG |= I2S_FIFOCFG_EMPTYTX_MASK; + } +} + +static void I2S_RxEnable(I2S_Type *base, bool enable) +{ + if (enable) + { + I2S_EnableInterrupts(base, kI2S_RxErrorFlag | kI2S_RxLevelFlag); + I2S_Enable(base); + } + else + { + I2S_DisableInterrupts(base, kI2S_RxErrorFlag | kI2S_RxLevelFlag); + I2S_Disable(base); + base->FIFOCFG |= I2S_FIFOCFG_EMPTYRX_MASK; + } +} + +static status_t I2S_ValidateBuffer(i2s_handle_t *handle, i2s_transfer_t *transfer) +{ + assert(transfer->data); + if (!transfer->data) + { + return kStatus_InvalidArgument; + } + + assert(transfer->dataSize > 0U); + if (transfer->dataSize <= 0U) + { + return kStatus_InvalidArgument; + } + + if (handle->dataLength == 4U) + { + /* No alignment and data length requirements */ + } + else if ((handle->dataLength >= 5U) && (handle->dataLength <= 8U)) + { + assert((((uint32_t)transfer->data) % 2U) == 0U); + if ((((uint32_t)transfer->data) % 2U) != 0U) + { + /* Data not 2-bytes aligned */ + return kStatus_InvalidArgument; + } + + assert((transfer->dataSize % 2U) == 0U); + if ((transfer->dataSize % 2U) != 0U) + { + /* Data not in pairs of left/right channel bytes */ + return kStatus_InvalidArgument; + } + } + else if ((handle->dataLength >= 9U) && (handle->dataLength <= 16U)) + { + assert((((uint32_t)transfer->data) % 4U) == 0U); + if ((((uint32_t)transfer->data) % 4U) != 0U) + { + /* Data not 4-bytes aligned */ + return kStatus_InvalidArgument; + } + + assert((transfer->dataSize % 4U) == 0U); + if ((transfer->dataSize % 4U) != 0U) + { + /* Data lenght not multiply of 4 */ + return kStatus_InvalidArgument; + } + } + else if ((handle->dataLength >= 17U) && (handle->dataLength <= 24U)) + { + assert((transfer->dataSize % 6U) == 0U); + if ((transfer->dataSize % 6U) != 0U) + { + /* Data lenght not multiply of 6 */ + return kStatus_InvalidArgument; + } + + assert(!((handle->pack48) && ((((uint32_t)transfer->data) % 4U) != 0U))); + if ((handle->pack48) && ((((uint32_t)transfer->data) % 4U) != 0U)) + { + /* Data not 4-bytes aligned */ + return kStatus_InvalidArgument; + } + } + else /* if (handle->dataLength >= 25U) */ + { + assert((((uint32_t)transfer->data) % 4U) == 0U); + if ((((uint32_t)transfer->data) % 4U) != 0U) + { + /* Data not 4-bytes aligned */ + return kStatus_InvalidArgument; + } + + if (handle->oneChannel) + { + assert((transfer->dataSize % 4U) == 0U); + if ((transfer->dataSize % 4U) != 0U) + { + /* Data lenght not multiply of 4 */ + return kStatus_InvalidArgument; + } + } + else + { + assert((transfer->dataSize % 8U) == 0U); + if ((transfer->dataSize % 8U) != 0U) + { + /* Data lenght not multiply of 8 */ + return kStatus_InvalidArgument; + } + } + } + + return kStatus_Success; +} + +#if (defined(FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL) && FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL) +void I2S_EnableSecondaryChannel(I2S_Type *base, uint32_t channel, bool oneChannel, uint32_t position) +{ + assert(channel <= kI2S_SecondaryChannel3); + + uint32_t pcfg1 = base->SECCHANNEL[channel].PCFG1; + uint32_t pcfg2 = base->SECCHANNEL[channel].PCFG2; + + pcfg1 &= ~I2S_CFG1_ONECHANNEL_MASK; + pcfg1 |= I2S_CFG1_MAINENABLE_MASK | I2S_CFG1_ONECHANNEL(oneChannel); + + pcfg2 &= ~I2S_CFG2_POSITION_MASK; + pcfg2 |= I2S_CFG2_POSITION(position); + + base->SECCHANNEL[channel].PCFG1 = pcfg1; + base->SECCHANNEL[channel].PCFG2 = pcfg2; +} +#endif +void I2S_TxTransferCreateHandle(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_callback_t callback, void *userData) +{ + uint32_t instance; + + assert(handle); + + /* Clear out the handle */ + memset(handle, 0U, sizeof(*handle)); + + /* Look up instance number */ + instance = I2S_GetInstance(base); + + /* Save callback and user data */ + handle->completionCallback = callback; + handle->userData = userData; + + /* Remember some items set previously by configuration */ + handle->watermark = ((base->FIFOTRIG & I2S_FIFOTRIG_TXLVL_MASK) >> I2S_FIFOTRIG_TXLVL_SHIFT); + handle->oneChannel = ((base->CFG1 & I2S_CFG1_ONECHANNEL_MASK) >> I2S_CFG1_ONECHANNEL_SHIFT); + handle->dataLength = ((base->CFG1 & I2S_CFG1_DATALEN_MASK) >> I2S_CFG1_DATALEN_SHIFT) + 1U; + handle->pack48 = ((base->FIFOCFG & I2S_FIFOCFG_PACK48_MASK) >> I2S_FIFOCFG_PACK48_SHIFT); + + handle->useFifo48H = false; + + /* Register IRQ handling */ + FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)I2S_TxHandleIRQ, handle); + /* Clear internal IRQ enables and enable NVIC IRQ. */ + I2S_DisableInterrupts(base, kI2S_TxErrorFlag | kI2S_TxLevelFlag); + EnableIRQ(s_i2sIRQ[instance]); +} + +status_t I2S_TxTransferNonBlocking(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_t transfer) +{ + assert(handle); + if (!handle) + { + return kStatus_InvalidArgument; + } + + status_t result; + + result = I2S_ValidateBuffer(handle, &transfer); + if (result != kStatus_Success) + { + return result; + } + + if (handle->i2sQueue[handle->queueUser].dataSize) + { + /* Previously prepared buffers not processed yet */ + return kStatus_I2S_Busy; + } + + handle->state = kI2S_StateTx; + handle->i2sQueue[handle->queueUser].data = transfer.data; + handle->i2sQueue[handle->queueUser].dataSize = transfer.dataSize; + handle->queueUser = (handle->queueUser + 1U) % I2S_NUM_BUFFERS; + + base->FIFOTRIG = (base->FIFOTRIG & (~I2S_FIFOTRIG_TXLVL_MASK)) | I2S_FIFOTRIG_TXLVL(handle->watermark); + I2S_TxEnable(base, true); + + return kStatus_Success; +} + +void I2S_TxTransferAbort(I2S_Type *base, i2s_handle_t *handle) +{ + assert(handle); + + /* Disable I2S operation and interrupts */ + I2S_TxEnable(base, false); + + /* Reset state */ + handle->state = kI2S_StateIdle; + + /* Clear transfer queue */ + memset((void *)&handle->i2sQueue, 0U, sizeof(i2s_transfer_t) * I2S_NUM_BUFFERS); + handle->queueDriver = 0U; + handle->queueUser = 0U; +} + +void I2S_RxTransferCreateHandle(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_callback_t callback, void *userData) +{ + uint32_t instance; + + assert(handle); + + /* Clear out the handle */ + memset(handle, 0U, sizeof(*handle)); + + /* Look up instance number */ + instance = I2S_GetInstance(base); + + /* Save callback and user data */ + handle->completionCallback = callback; + handle->userData = userData; + + /* Remember some items set previously by configuration */ + handle->watermark = ((base->FIFOTRIG & I2S_FIFOTRIG_RXLVL_MASK) >> I2S_FIFOTRIG_RXLVL_SHIFT); + handle->oneChannel = ((base->CFG1 & I2S_CFG1_ONECHANNEL_MASK) >> I2S_CFG1_ONECHANNEL_SHIFT); + handle->dataLength = ((base->CFG1 & I2S_CFG1_DATALEN_MASK) >> I2S_CFG1_DATALEN_SHIFT) + 1U; + handle->pack48 = ((base->FIFOCFG & I2S_FIFOCFG_PACK48_MASK) >> I2S_FIFOCFG_PACK48_SHIFT); + + handle->useFifo48H = false; + + /* Register IRQ handling */ + FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)I2S_RxHandleIRQ, handle); + /* Clear internal IRQ enables and enable NVIC IRQ. */ + I2S_DisableInterrupts(base, kI2S_RxErrorFlag | kI2S_RxLevelFlag); + EnableIRQ(s_i2sIRQ[instance]); +} + +status_t I2S_RxTransferNonBlocking(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_t transfer) +{ + assert(handle); + if (!handle) + { + return kStatus_InvalidArgument; + } + + status_t result; + + result = I2S_ValidateBuffer(handle, &transfer); + if (result != kStatus_Success) + { + return result; + } + + if (handle->i2sQueue[handle->queueUser].dataSize) + { + /* Previously prepared buffers not processed yet */ + return kStatus_I2S_Busy; + } + + handle->state = kI2S_StateRx; + handle->i2sQueue[handle->queueUser].data = transfer.data; + handle->i2sQueue[handle->queueUser].dataSize = transfer.dataSize; + handle->queueUser = (handle->queueUser + 1U) % I2S_NUM_BUFFERS; + + base->FIFOTRIG = (base->FIFOTRIG & (~I2S_FIFOTRIG_RXLVL_MASK)) | I2S_FIFOTRIG_RXLVL(handle->watermark); + I2S_RxEnable(base, true); + + return kStatus_Success; +} + +void I2S_RxTransferAbort(I2S_Type *base, i2s_handle_t *handle) +{ + assert(handle); + + /* Disable I2S operation and interrupts */ + I2S_RxEnable(base, false); + + /* Reset state */ + handle->state = kI2S_StateIdle; + + /* Clear transfer queue */ + memset((void *)&handle->i2sQueue, 0U, sizeof(i2s_transfer_t) * I2S_NUM_BUFFERS); + handle->queueDriver = 0U; + handle->queueUser = 0U; +} + +status_t I2S_TransferGetCount(I2S_Type *base, i2s_handle_t *handle, size_t *count) +{ + assert(handle); + if (!handle) + { + return kStatus_InvalidArgument; + } + + assert(count); + if (!count) + { + return kStatus_InvalidArgument; + } + + if (handle->state == kI2S_StateIdle) + { + return kStatus_NoTransferInProgress; + } + + *count = handle->transferCount; + + return kStatus_Success; +} + +status_t I2S_TransferGetErrorCount(I2S_Type *base, i2s_handle_t *handle, size_t *count) +{ + assert(handle); + if (!handle) + { + return kStatus_InvalidArgument; + } + + assert(count); + if (!count) + { + return kStatus_InvalidArgument; + } + + if (handle->state == kI2S_StateIdle) + { + return kStatus_NoTransferInProgress; + } + + *count = handle->errorCount; + + return kStatus_Success; +} + +void I2S_TxHandleIRQ(I2S_Type *base, i2s_handle_t *handle) +{ + uint32_t intstat = base->FIFOINTSTAT; + uint32_t data; + + if (intstat & I2S_FIFOINTSTAT_TXERR_MASK) + { + handle->errorCount++; + + /* Clear TX error interrupt flag */ + base->FIFOSTAT = I2S_FIFOSTAT_TXERR(1U); + } + + if (intstat & I2S_FIFOINTSTAT_TXLVL_MASK) + { + if (handle->state == kI2S_StateTx) + { + /* Send data */ + + while ((base->FIFOSTAT & I2S_FIFOSTAT_TXNOTFULL_MASK) && + (handle->i2sQueue[handle->queueDriver].dataSize > 0U)) + { + /* Write output data */ + if (handle->dataLength == 4U) + { + data = *(handle->i2sQueue[handle->queueDriver].data); + base->FIFOWR = ((data & 0xF0U) << 12U) | (data & 0xFU); + handle->i2sQueue[handle->queueDriver].data++; + handle->transferCount++; + handle->i2sQueue[handle->queueDriver].dataSize--; + } + else if (handle->dataLength <= 8U) + { + data = *((volatile uint16_t *)handle->i2sQueue[handle->queueDriver].data); + base->FIFOWR = ((data & 0xFF00U) << 8U) | (data & 0xFFU); + handle->i2sQueue[handle->queueDriver].data += sizeof(uint16_t); + handle->transferCount += sizeof(uint16_t); + handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint16_t); + } + else if (handle->dataLength <= 16U) + { + base->FIFOWR = *((volatile uint32_t *)(handle->i2sQueue[handle->queueDriver].data)); + handle->i2sQueue[handle->queueDriver].data += sizeof(uint32_t); + handle->transferCount += sizeof(uint32_t); + handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint32_t); + } + else if (handle->dataLength <= 24U) + { + if (handle->pack48) + { + if (handle->useFifo48H) + { + base->FIFOWR48H = *((volatile uint16_t *)(handle->i2sQueue[handle->queueDriver].data)); + handle->i2sQueue[handle->queueDriver].data += sizeof(uint16_t); + handle->transferCount += sizeof(uint16_t); + handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint16_t); + handle->useFifo48H = false; + } + else + { + base->FIFOWR = *((volatile uint32_t *)(handle->i2sQueue[handle->queueDriver].data)); + handle->i2sQueue[handle->queueDriver].data += sizeof(uint32_t); + handle->transferCount += sizeof(uint32_t); + handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint32_t); + handle->useFifo48H = true; + } + } + else + { + data = (uint32_t)(*(handle->i2sQueue[handle->queueDriver].data++)); + data |= ((uint32_t)(*(handle->i2sQueue[handle->queueDriver].data++))) << 8U; + data |= ((uint32_t)(*(handle->i2sQueue[handle->queueDriver].data++))) << 16U; + if (handle->useFifo48H) + { + base->FIFOWR48H = data; + handle->useFifo48H = false; + } + else + { + base->FIFOWR = data; + handle->useFifo48H = true; + } + handle->transferCount += 3U; + handle->i2sQueue[handle->queueDriver].dataSize -= 3U; + } + } + else /* if (handle->dataLength <= 32U) */ + { + base->FIFOWR = *((volatile uint32_t *)(handle->i2sQueue[handle->queueDriver].data)); + handle->i2sQueue[handle->queueDriver].data += sizeof(uint32_t); + handle->transferCount += sizeof(uint32_t); + handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint32_t); + } + + if (handle->i2sQueue[handle->queueDriver].dataSize == 0U) + { + /* Actual data buffer sent out, switch to a next one */ + handle->queueDriver = (handle->queueDriver + 1U) % I2S_NUM_BUFFERS; + + /* Notify user */ + if (handle->completionCallback) + { + handle->completionCallback(base, handle, kStatus_I2S_BufferComplete, handle->userData); + } + + /* Check if the next buffer contains anything to send */ + if (handle->i2sQueue[handle->queueDriver].dataSize == 0U) + { + /* Everything has been written to FIFO */ + handle->state = kI2S_StateTxWaitToWriteDummyData; + break; + } + } + } + } + else if (handle->state == kI2S_StateTxWaitToWriteDummyData) + { + /* Write dummy data */ + if ((handle->dataLength > 16U) && (handle->dataLength < 25U)) + { + if (handle->useFifo48H) + { + base->FIFOWR48H = 0U; + handle->useFifo48H = false; + } + else + { + base->FIFOWR = 0U; + base->FIFOWR48H = 0U; + } + } + else + { + base->FIFOWR = 0U; + } + + /* Next time invoke this handler when FIFO becomes empty (TX level 0) */ + base->FIFOTRIG &= ~I2S_FIFOTRIG_TXLVL_MASK; + handle->state = kI2S_StateTxWaitForEmptyFifo; + } + else if (handle->state == kI2S_StateTxWaitForEmptyFifo) + { + /* FIFO, including additional dummy data, has been emptied now, + * all relevant data should have been output from peripheral */ + + /* Stop transfer */ + I2S_Disable(base); + I2S_DisableInterrupts(base, kI2S_TxErrorFlag | kI2S_TxLevelFlag); + base->FIFOCFG |= I2S_FIFOCFG_EMPTYTX_MASK; + + /* Reset state */ + handle->state = kI2S_StateIdle; + + /* Notify user */ + if (handle->completionCallback) + { + handle->completionCallback(base, handle, kStatus_I2S_Done, handle->userData); + } + } + else + { + /* Do nothing */ + } + + /* Clear TX level interrupt flag */ + base->FIFOSTAT = I2S_FIFOSTAT_TXLVL(1U); + } +} + +void I2S_RxHandleIRQ(I2S_Type *base, i2s_handle_t *handle) +{ + uint32_t intstat = base->FIFOINTSTAT; + uint32_t data; + + if (intstat & I2S_FIFOINTSTAT_RXERR_MASK) + { + handle->errorCount++; + + /* Clear RX error interrupt flag */ + base->FIFOSTAT = I2S_FIFOSTAT_RXERR(1U); + } + + if (intstat & I2S_FIFOINTSTAT_RXLVL_MASK) + { + while ((base->FIFOSTAT & I2S_FIFOSTAT_RXNOTEMPTY_MASK) && (handle->i2sQueue[handle->queueDriver].dataSize > 0U)) + { + /* Read input data */ + if (handle->dataLength == 4U) + { + data = base->FIFORD; + *(handle->i2sQueue[handle->queueDriver].data) = ((data & 0x000F0000U) >> 12U) | (data & 0x0000000FU); + handle->i2sQueue[handle->queueDriver].data++; + handle->transferCount++; + handle->i2sQueue[handle->queueDriver].dataSize--; + } + else if (handle->dataLength <= 8U) + { + data = base->FIFORD; + *((volatile uint16_t *)handle->i2sQueue[handle->queueDriver].data) = + ((data >> 8U) & 0xFF00U) | (data & 0xFFU); + handle->i2sQueue[handle->queueDriver].data += sizeof(uint16_t); + handle->transferCount += sizeof(uint16_t); + handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint16_t); + } + else if (handle->dataLength <= 16U) + { + data = base->FIFORD; + *((volatile uint32_t *)handle->i2sQueue[handle->queueDriver].data) = data; + handle->i2sQueue[handle->queueDriver].data += sizeof(uint32_t); + handle->transferCount += sizeof(uint32_t); + handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint32_t); + } + else if (handle->dataLength <= 24U) + { + if (handle->pack48) + { + if (handle->useFifo48H) + { + data = base->FIFORD48H; + handle->useFifo48H = false; + + *((volatile uint16_t *)handle->i2sQueue[handle->queueDriver].data) = data; + handle->i2sQueue[handle->queueDriver].data += sizeof(uint16_t); + handle->transferCount += sizeof(uint16_t); + handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint16_t); + } + else + { + data = base->FIFORD; + handle->useFifo48H = true; + + *((volatile uint32_t *)handle->i2sQueue[handle->queueDriver].data) = data; + handle->i2sQueue[handle->queueDriver].data += sizeof(uint32_t); + handle->transferCount += sizeof(uint32_t); + handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint32_t); + } + } + else + { + if (handle->useFifo48H) + { + data = base->FIFORD48H; + handle->useFifo48H = false; + } + else + { + data = base->FIFORD; + handle->useFifo48H = true; + } + + *(handle->i2sQueue[handle->queueDriver].data++) = data & 0xFFU; + *(handle->i2sQueue[handle->queueDriver].data++) = (data >> 8U) & 0xFFU; + *(handle->i2sQueue[handle->queueDriver].data++) = (data >> 16U) & 0xFFU; + handle->transferCount += 3U; + handle->i2sQueue[handle->queueDriver].dataSize -= 3U; + } + } + else /* if (handle->dataLength <= 32U) */ + { + data = base->FIFORD; + *((volatile uint32_t *)handle->i2sQueue[handle->queueDriver].data) = data; + handle->i2sQueue[handle->queueDriver].data += sizeof(uint32_t); + handle->transferCount += sizeof(uint32_t); + handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint32_t); + } + + if (handle->i2sQueue[handle->queueDriver].dataSize == 0U) + { + /* Actual data buffer filled with input data, switch to a next one */ + handle->queueDriver = (handle->queueDriver + 1U) % I2S_NUM_BUFFERS; + + /* Notify user */ + if (handle->completionCallback) + { + handle->completionCallback(base, handle, kStatus_I2S_BufferComplete, handle->userData); + } + + if (handle->i2sQueue[handle->queueDriver].dataSize == 0U) + { + /* No other buffer prepared to receive data into */ + + /* Disable I2S operation and interrupts */ + I2S_Disable(base); + I2S_DisableInterrupts(base, kI2S_RxErrorFlag | kI2S_RxLevelFlag); + base->FIFOCFG |= I2S_FIFOCFG_EMPTYRX_MASK; + + /* Reset state */ + handle->state = kI2S_StateIdle; + + /* Notify user */ + if (handle->completionCallback) + { + handle->completionCallback(base, handle, kStatus_I2S_Done, handle->userData); + } + + /* Clear RX level interrupt flag */ + base->FIFOSTAT = I2S_FIFOSTAT_RXLVL(1U); + + return; + } + } + } + + /* Clear RX level interrupt flag */ + base->FIFOSTAT = I2S_FIFOSTAT_RXLVL(1U); + } +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2s.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2s.h new file mode 100644 index 000000000..4af608c28 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2s.h @@ -0,0 +1,488 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_I2S_H_ +#define _FSL_I2S_H_ + +#include "fsl_device_registers.h" +#include "fsl_common.h" +#include "fsl_flexcomm.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @addtogroup i2s_driver + * @{ + */ + +/*! @file */ + +/*! @name Driver version */ +/*@{*/ + +/*! @brief I2S driver version 2.1.0. */ +#define FSL_I2S_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) +/*@}*/ + +#ifndef I2S_NUM_BUFFERS + +/*! @brief Number of buffers . */ +#define I2S_NUM_BUFFERS (4) + +#endif + +/*! @brief I2S status codes. */ +enum _i2s_status +{ + kStatus_I2S_BufferComplete = + MAKE_STATUS(kStatusGroup_I2S, 0), /*!< Transfer from/into a single buffer has completed */ + kStatus_I2S_Done = MAKE_STATUS(kStatusGroup_I2S, 1), /*!< All buffers transfers have completed */ + kStatus_I2S_Busy = + MAKE_STATUS(kStatusGroup_I2S, 2), /*!< Already performing a transfer and cannot queue another buffer */ +}; + +/*! + * @brief I2S flags. + * + * @note These enums are meant to be OR'd together to form a bit mask. + */ +typedef enum _i2s_flags +{ + kI2S_TxErrorFlag = I2S_FIFOINTENSET_TXERR_MASK, /*!< TX error interrupt */ + kI2S_TxLevelFlag = I2S_FIFOINTENSET_TXLVL_MASK, /*!< TX level interrupt */ + kI2S_RxErrorFlag = I2S_FIFOINTENSET_RXERR_MASK, /*!< RX error interrupt */ + kI2S_RxLevelFlag = I2S_FIFOINTENSET_RXLVL_MASK /*!< RX level interrupt */ +} i2s_flags_t; + +/*! @brief Master / slave mode. */ +typedef enum _i2s_master_slave +{ + kI2S_MasterSlaveNormalSlave = 0x0, /*!< Normal slave */ + kI2S_MasterSlaveWsSyncMaster = 0x1, /*!< WS synchronized master */ + kI2S_MasterSlaveExtSckMaster = 0x2, /*!< Master using existing SCK */ + kI2S_MasterSlaveNormalMaster = 0x3 /*!< Normal master */ +} i2s_master_slave_t; + +/*! @brief I2S mode. */ +typedef enum _i2s_mode +{ + kI2S_ModeI2sClassic = 0x0, /*!< I2S classic mode */ + kI2S_ModeDspWs50 = 0x1, /*!< DSP mode, WS having 50% duty cycle */ + kI2S_ModeDspWsShort = 0x2, /*!< DSP mode, WS having one clock long pulse */ + kI2S_ModeDspWsLong = 0x3 /*!< DSP mode, WS having one data slot long pulse */ +} i2s_mode_t; + +/*! @brief I2S secondary channel. */ +enum _i2s_secondary_channel +{ + kI2S_SecondaryChannel1 = 0U, /*!< secondary channel 1 */ + kI2S_SecondaryChannel2 = 1U, /*!< secondary channel 2 */ + kI2S_SecondaryChannel3 = 2U, /*!< secondary channel 3 */ +}; + +/*! @brief I2S configuration structure. */ +typedef struct _i2s_config +{ + i2s_master_slave_t masterSlave; /*!< Master / slave configuration */ + i2s_mode_t mode; /*!< I2S mode */ + bool rightLow; /*!< Right channel data in low portion of FIFO */ + bool leftJust; /*!< Left justify data in FIFO */ +#if (defined(FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION) && FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION) + bool pdmData; /*!< Data source is the D-Mic subsystem */ +#endif + bool sckPol; /*!< SCK polarity */ + bool wsPol; /*!< WS polarity */ + uint16_t divider; /*!< Flexcomm function clock divider (1 - 4096) */ + bool oneChannel; /*!< true mono, false stereo */ + uint8_t dataLength; /*!< Data length (4 - 32) */ + uint16_t frameLength; /*!< Frame width (4 - 512) */ + uint16_t position; /*!< Data position in the frame */ + uint8_t watermark; /*!< FIFO trigger level */ + bool txEmptyZero; /*!< Transmit zero when buffer becomes empty or last item */ + bool pack48; /*!< Packing format for 48-bit data (false - 24 bit values, true - alternating 32-bit and 16-bit + values) */ +} i2s_config_t; + +/*! @brief Buffer to transfer from or receive audio data into. */ +typedef struct _i2s_transfer +{ + volatile uint8_t *data; /*!< Pointer to data buffer. */ + volatile size_t dataSize; /*!< Buffer size in bytes. */ +} i2s_transfer_t; + +/*! @brief Transactional state of the intialized transfer or receive I2S operation. */ +typedef struct _i2s_handle i2s_handle_t; + +/*! + * @brief Callback function invoked from transactional API + * on completion of a single buffer transfer. + * + * @param base I2S base pointer. + * @param handle pointer to I2S transaction. + * @param completionStatus status of the transaction. + * @param userData optional pointer to user arguments data. + */ +typedef void (*i2s_transfer_callback_t)(I2S_Type *base, + i2s_handle_t *handle, + status_t completionStatus, + void *userData); + +/*! @brief Members not to be accessed / modified outside of the driver. */ +struct _i2s_handle +{ + uint32_t state; /*!< State of transfer */ + i2s_transfer_callback_t completionCallback; /*!< Callback function pointer */ + void *userData; /*!< Application data passed to callback */ + bool oneChannel; /*!< true mono, false stereo */ + uint8_t dataLength; /*!< Data length (4 - 32) */ + bool pack48; /*!< Packing format for 48-bit data (false - 24 bit values, true - alternating 32-bit and 16-bit + values) */ + bool useFifo48H; /*!< When dataLength 17-24: true use FIFOWR48H, false use FIFOWR */ + volatile i2s_transfer_t i2sQueue[I2S_NUM_BUFFERS]; /*!< Transfer queue storing transfer buffers */ + volatile uint8_t queueUser; /*!< Queue index where user's next transfer will be stored */ + volatile uint8_t queueDriver; /*!< Queue index of buffer actually used by the driver */ + volatile uint32_t errorCount; /*!< Number of buffer underruns/overruns */ + volatile uint32_t transferCount; /*!< Number of bytes transferred */ + volatile uint8_t watermark; /*!< FIFO trigger level */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initializes the FLEXCOMM peripheral for I2S transmit functionality. + * + * Ungates the FLEXCOMM clock and configures the module + * for I2S transmission using a configuration structure. + * The configuration structure can be custom filled or set with default values by + * I2S_TxGetDefaultConfig(). + * + * @note This API should be called at the beginning of the application to use + * the I2S driver. + * + * @param base I2S base pointer. + * @param config pointer to I2S configuration structure. + */ +void I2S_TxInit(I2S_Type *base, const i2s_config_t *config); + +/*! + * @brief Initializes the FLEXCOMM peripheral for I2S receive functionality. + * + * Ungates the FLEXCOMM clock and configures the module + * for I2S receive using a configuration structure. + * The configuration structure can be custom filled or set with default values by + * I2S_RxGetDefaultConfig(). + * + * @note This API should be called at the beginning of the application to use + * the I2S driver. + * + * @param base I2S base pointer. + * @param config pointer to I2S configuration structure. + */ +void I2S_RxInit(I2S_Type *base, const i2s_config_t *config); + +/*! + * @brief Sets the I2S Tx configuration structure to default values. + * + * This API initializes the configuration structure for use in I2S_TxInit(). + * The initialized structure can remain unchanged in I2S_TxInit(), or it can be modified + * before calling I2S_TxInit(). + * Example: + @code + i2s_config_t config; + I2S_TxGetDefaultConfig(&config); + @endcode + * + * Default values: + * @code + * config->masterSlave = kI2S_MasterSlaveNormalMaster; + * config->mode = kI2S_ModeI2sClassic; + * config->rightLow = false; + * config->leftJust = false; + * config->pdmData = false; + * config->sckPol = false; + * config->wsPol = false; + * config->divider = 1; + * config->oneChannel = false; + * config->dataLength = 16; + * config->frameLength = 32; + * config->position = 0; + * config->watermark = 4; + * config->txEmptyZero = true; + * config->pack48 = false; + * @endcode + * + * @param config pointer to I2S configuration structure. + */ +void I2S_TxGetDefaultConfig(i2s_config_t *config); + +/*! + * @brief Sets the I2S Rx configuration structure to default values. + * + * This API initializes the configuration structure for use in I2S_RxInit(). + * The initialized structure can remain unchanged in I2S_RxInit(), or it can be modified + * before calling I2S_RxInit(). + * Example: + @code + i2s_config_t config; + I2S_RxGetDefaultConfig(&config); + @endcode + * + * Default values: + * @code + * config->masterSlave = kI2S_MasterSlaveNormalSlave; + * config->mode = kI2S_ModeI2sClassic; + * config->rightLow = false; + * config->leftJust = false; + * config->pdmData = false; + * config->sckPol = false; + * config->wsPol = false; + * config->divider = 1; + * config->oneChannel = false; + * config->dataLength = 16; + * config->frameLength = 32; + * config->position = 0; + * config->watermark = 4; + * config->txEmptyZero = false; + * config->pack48 = false; + * @endcode + * + * @param config pointer to I2S configuration structure. + */ +void I2S_RxGetDefaultConfig(i2s_config_t *config); + +/*! + * @brief De-initializes the I2S peripheral. + * + * This API gates the FLEXCOMM clock. The I2S module can't operate unless I2S_TxInit + * or I2S_RxInit is called to enable the clock. + * + * @param base I2S base pointer. + */ +void I2S_Deinit(I2S_Type *base); + +/*! @} */ + +/*! + * @name Non-blocking API + * @{ + */ + +/*! + * @brief Initializes handle for transfer of audio data. + * + * @param base I2S base pointer. + * @param handle pointer to handle structure. + * @param callback function to be called back when transfer is done or fails. + * @param userData pointer to data passed to callback. + */ +void I2S_TxTransferCreateHandle(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_callback_t callback, void *userData); + +/*! + * @brief Begins or queue sending of the given data. + * + * @param base I2S base pointer. + * @param handle pointer to handle structure. + * @param transfer data buffer. + * + * @retval kStatus_Success + * @retval kStatus_I2S_Busy if all queue slots are occupied with unsent buffers. + */ +status_t I2S_TxTransferNonBlocking(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_t transfer); + +/*! + * @brief Aborts sending of data. + * + * @param base I2S base pointer. + * @param handle pointer to handle structure. + */ +void I2S_TxTransferAbort(I2S_Type *base, i2s_handle_t *handle); + +/*! + * @brief Initializes handle for reception of audio data. + * + * @param base I2S base pointer. + * @param handle pointer to handle structure. + * @param callback function to be called back when transfer is done or fails. + * @param userData pointer to data passed to callback. + */ +void I2S_RxTransferCreateHandle(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_callback_t callback, void *userData); + +/*! + * @brief Begins or queue reception of data into given buffer. + * + * @param base I2S base pointer. + * @param handle pointer to handle structure. + * @param transfer data buffer. + * + * @retval kStatus_Success + * @retval kStatus_I2S_Busy if all queue slots are occupied with buffers which are not full. + */ +status_t I2S_RxTransferNonBlocking(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_t transfer); + +/*! + * @brief Aborts receiving of data. + * + * @param base I2S base pointer. + * @param handle pointer to handle structure. + */ +void I2S_RxTransferAbort(I2S_Type *base, i2s_handle_t *handle); + +/*! + * @brief Returns number of bytes transferred so far. + * + * @param base I2S base pointer. + * @param handle pointer to handle structure. + * @param[out] count number of bytes transferred so far by the non-blocking transaction. + * + * @retval kStatus_Success + * @retval kStatus_NoTransferInProgress there is no non-blocking transaction currently in progress. + */ +status_t I2S_TransferGetCount(I2S_Type *base, i2s_handle_t *handle, size_t *count); + +/*! + * @brief Returns number of buffer underruns or overruns. + * + * @param base I2S base pointer. + * @param handle pointer to handle structure. + * @param[out] count number of transmit errors encountered so far by the non-blocking transaction. + * + * @retval kStatus_Success + * @retval kStatus_NoTransferInProgress there is no non-blocking transaction currently in progress. + */ +status_t I2S_TransferGetErrorCount(I2S_Type *base, i2s_handle_t *handle, size_t *count); + +/*! @} */ + +/*! + * @name Enable / disable + * @{ + */ + +/*! + * @brief Enables I2S operation. + * + * @param base I2S base pointer. + */ +static inline void I2S_Enable(I2S_Type *base) +{ + base->CFG1 |= I2S_CFG1_MAINENABLE(1U); +} + +#if (defined(FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL) && FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL) +/*! + * @brief Enables I2S secondary channel. + * + * @param base I2S base pointer. + * @param channel seondary channel channel number, reference _i2s_secondary_channel. + * @param oneChannel true is treated as single channel, functionality left channel for this pair. + * @param position define the location within the frame of the data, should not bigger than 0x1FFU. + */ +void I2S_EnableSecondaryChannel(I2S_Type *base, uint32_t channel, bool oneChannel, uint32_t position); + +/*! + * @brief Disables I2S secondary channel. + * + * @param base I2S base pointer. + * @param channel seondary channel channel number, reference _i2s_secondary_channel. + */ +static inline void I2S_DisableSecondaryChannel(I2S_Type *base, uint32_t channel) +{ + base->SECCHANNEL[channel].PCFG1 &= ~I2S_CFG1_MAINENABLE_MASK; +} +#endif +/*! + * @brief Disables I2S operation. + * + * @param base I2S base pointer. + */ +static inline void I2S_Disable(I2S_Type *base) +{ + base->CFG1 &= (~I2S_CFG1_MAINENABLE(1U)); +} + +/*! @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables I2S FIFO interrupts. + * + * @param base I2S base pointer. + * @param interruptMask bit mask of interrupts to enable. See #i2s_flags_t for the set + * of constants that should be OR'd together to form the bit mask. + */ +static inline void I2S_EnableInterrupts(I2S_Type *base, uint32_t interruptMask) +{ + base->FIFOINTENSET = interruptMask; +} + +/*! + * @brief Disables I2S FIFO interrupts. + * + * @param base I2S base pointer. + * @param interruptMask bit mask of interrupts to enable. See #i2s_flags_t for the set + * of constants that should be OR'd together to form the bit mask. + */ +static inline void I2S_DisableInterrupts(I2S_Type *base, uint32_t interruptMask) +{ + base->FIFOINTENCLR = interruptMask; +} + +/*! + * @brief Returns the set of currently enabled I2S FIFO interrupts. + * + * @param base I2S base pointer. + * + * @return A bitmask composed of #i2s_flags_t enumerators OR'd together + * to indicate the set of enabled interrupts. + */ +static inline uint32_t I2S_GetEnabledInterrupts(I2S_Type *base) +{ + return base->FIFOINTENSET; +} + +/*! + * @brief Invoked from interrupt handler when transmit FIFO level decreases. + * + * @param base I2S base pointer. + * @param handle pointer to handle structure. + */ +void I2S_TxHandleIRQ(I2S_Type *base, i2s_handle_t *handle); + +/*! + * @brief Invoked from interrupt handler when receive FIFO level decreases. + * + * @param base I2S base pointer. + * @param handle pointer to handle structure. + */ +void I2S_RxHandleIRQ(I2S_Type *base, i2s_handle_t *handle); + +/*! @} */ + +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +#endif /* _FSL_I2S_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2s_dma.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2s_dma.c new file mode 100644 index 000000000..f3bf1773c --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2s_dma.c @@ -0,0 +1,619 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_dma.h" +#include "fsl_i2s_dma.h" +#include "fsl_flexcomm.h" +#include + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexcomm_i2s_dma" +#endif + +#define DMA_MAX_TRANSFER_BYTES (DMA_MAX_TRANSFER_COUNT * sizeof(uint32_t)) +#define DMA_DESCRIPTORS (2U) + +/*i2sQueue[handle->queueUser].dataSize) + { + /* Previously prepared buffers not processed yet, reject request */ + return kStatus_I2S_Busy; + } + + /* Enqueue data */ + privateHandle->descriptorQueue[handle->queueUser].data = transfer.data; + privateHandle->descriptorQueue[handle->queueUser].dataSize = transfer.dataSize; + handle->i2sQueue[handle->queueUser].data = transfer.data; + handle->i2sQueue[handle->queueUser].dataSize = transfer.dataSize; + handle->queueUser = (handle->queueUser + 1U) % I2S_NUM_BUFFERS; + + return kStatus_Success; +} + +static uint32_t I2S_GetInstance(I2S_Type *base) +{ + uint32_t i; + + for (i = 0U; i < ARRAY_SIZE(s_I2sBaseAddrs); i++) + { + if ((uint32_t)base == s_I2sBaseAddrs[i]) + { + return i; + } + } + + assert(false); + return 0U; +} + +static inline void I2S_DisableDMAInterrupts(i2s_dma_handle_t *handle) +{ + DMA_DisableChannelInterrupts(handle->dmaHandle->base, handle->dmaHandle->channel); +} + +static inline void I2S_EnableDMAInterrupts(i2s_dma_handle_t *handle) +{ + if (handle->state != kI2S_DmaStateIdle) + { + DMA_EnableChannelInterrupts(handle->dmaHandle->base, handle->dmaHandle->channel); + } +} + +/*! + * brief Initializes handle for transfer of audio data. + * + * param base I2S base pointer. + * param handle pointer to handle structure. + * param dmaHandle pointer to dma handle structure. + * param callback function to be called back when transfer is done or fails. + * param userData pointer to data passed to callback. + */ +void I2S_TxTransferCreateHandleDMA(I2S_Type *base, + i2s_dma_handle_t *handle, + dma_handle_t *dmaHandle, + i2s_dma_transfer_callback_t callback, + void *userData) +{ + assert(handle); + assert(dmaHandle); + + uint32_t instance = I2S_GetInstance(base); + i2s_dma_private_handle_t *privateHandle = &(s_DmaPrivateHandle[instance]); + + memset(handle, 0U, sizeof(*handle)); + handle->state = kI2S_DmaStateIdle; + handle->dmaHandle = dmaHandle; + handle->completionCallback = callback; + handle->userData = userData; + + handle->bytesPerFrame = (((base->CFG1 & I2S_CFG1_DATALEN_MASK) >> I2S_CFG1_DATALEN_SHIFT) + 1U) / 8U; + /* if one channel is disabled, bytesPerFrame should be 4U, user should pay attention that when data length is + * shorter than 16, the data format: left data put in 0-15 bit and right data should put in 16-31 + */ + if (((base->CFG1 & I2S_CFG1_ONECHANNEL_MASK) == 0U)) + { + handle->bytesPerFrame = 4U; + } + /* since DMA do not support 24bit transfer width, use 32bit instead */ + if (handle->bytesPerFrame == 3U) + { + handle->bytesPerFrame = 4U; + } + + memset(privateHandle, 0U, sizeof(*privateHandle)); + privateHandle->base = base; + privateHandle->handle = handle; + + DMA_SetCallback(dmaHandle, I2S_DMACallback, privateHandle); +} + +/*! + * brief Begins or queue sending of the given data. + * + * param base I2S base pointer. + * param handle pointer to handle structure. + * param transfer data buffer. + * + * retval kStatus_Success + * retval kStatus_I2S_Busy if all queue slots are occupied with unsent buffers. + */ +status_t I2S_TxTransferSendDMA(I2S_Type *base, i2s_dma_handle_t *handle, i2s_transfer_t transfer) +{ + status_t status; + + I2S_DisableDMAInterrupts(handle); + + /* Enqueue transfer buffer */ + status = I2S_EnqueueUserBuffer(base, handle, transfer); + if (status != kStatus_Success) + { + I2S_EnableDMAInterrupts(handle); + return status; + } + + /* Initialize DMA transfer */ + if (handle->state == kI2S_DmaStateIdle) + { + handle->state = kI2S_DmaStateTx; + status = I2S_StartTransferDMA(base, handle); + if (status != kStatus_Success) + { + I2S_EnableDMAInterrupts(handle); + return status; + } + } + + I2S_AddTransferDMA(base, handle); + I2S_EnableDMAInterrupts(handle); + + return kStatus_Success; +} + +/*! + * brief Aborts transfer of data. + * + * param base I2S base pointer. + * param handle pointer to handle structure. + */ +void I2S_TransferAbortDMA(I2S_Type *base, i2s_dma_handle_t *handle) +{ + assert(handle); + assert(handle->dmaHandle); + + uint32_t instance = I2S_GetInstance(base); + i2s_dma_private_handle_t *privateHandle = &(s_DmaPrivateHandle[instance]); + + I2S_DisableDMAInterrupts(handle); + + /* Abort operation */ + DMA_AbortTransfer(handle->dmaHandle); + + if (handle->state == kI2S_DmaStateTx) + { + /* Wait until all transmitted data get out of FIFO */ + while ((base->FIFOSTAT & I2S_FIFOSTAT_TXEMPTY_MASK) == 0U) + { + } + /* The last piece of valid data can be still being transmitted from I2S at this moment */ + + /* Write additional data to FIFO */ + base->FIFOWR = 0U; + while ((base->FIFOSTAT & I2S_FIFOSTAT_TXEMPTY_MASK) == 0U) + { + } + /* At this moment the additional data are out of FIFO, starting being transmitted. + * This means the preceding valid data has been just transmitted and we can stop I2S. */ + I2S_TxEnableDMA(base, false); + } + else + { + I2S_RxEnableDMA(base, false); + } + + I2S_Disable(base); + + /* Reset state */ + handle->state = kI2S_DmaStateIdle; + + /* Clear transfer queue */ + memset((void *)&(handle->i2sQueue), 0U, sizeof(handle->i2sQueue)); + handle->queueDriver = 0U; + handle->queueUser = 0U; + + /* Clear internal state */ + memset((void *)&(privateHandle->descriptorQueue), 0U, sizeof(privateHandle->descriptorQueue)); + memset((void *)&(privateHandle->enqueuedBytes), 0U, sizeof(privateHandle->enqueuedBytes)); + privateHandle->enqueuedBytesStart = 0U; + privateHandle->enqueuedBytesEnd = 0U; + privateHandle->dmaDescriptorsUsed = 0U; + privateHandle->descriptor = 0U; + privateHandle->queueDescriptor = 0U; + privateHandle->intA = false; +} + +/*! + * brief Initializes handle for reception of audio data. + * + * param base I2S base pointer. + * param handle pointer to handle structure. + * param dmaHandle pointer to dma handle structure. + * param callback function to be called back when transfer is done or fails. + * param userData pointer to data passed to callback. + */ +void I2S_RxTransferCreateHandleDMA(I2S_Type *base, + i2s_dma_handle_t *handle, + dma_handle_t *dmaHandle, + i2s_dma_transfer_callback_t callback, + void *userData) +{ + I2S_TxTransferCreateHandleDMA(base, handle, dmaHandle, callback, userData); +} + +/*! + * brief Begins or queue reception of data into given buffer. + * + * param base I2S base pointer. + * param handle pointer to handle structure. + * param transfer data buffer. + * + * retval kStatus_Success + * retval kStatus_I2S_Busy if all queue slots are occupied with buffers + * which are not full. + */ +status_t I2S_RxTransferReceiveDMA(I2S_Type *base, i2s_dma_handle_t *handle, i2s_transfer_t transfer) +{ + status_t status; + + I2S_DisableDMAInterrupts(handle); + + /* Enqueue transfer buffer */ + status = I2S_EnqueueUserBuffer(base, handle, transfer); + if (status != kStatus_Success) + { + I2S_EnableDMAInterrupts(handle); + return status; + } + + /* Initialize DMA transfer */ + if (handle->state == kI2S_DmaStateIdle) + { + handle->state = kI2S_DmaStateRx; + status = I2S_StartTransferDMA(base, handle); + if (status != kStatus_Success) + { + I2S_EnableDMAInterrupts(handle); + return status; + } + } + + I2S_AddTransferDMA(base, handle); + I2S_EnableDMAInterrupts(handle); + + return kStatus_Success; +} + +static void I2S_TxEnableDMA(I2S_Type *base, bool enable) +{ + if (enable) + { + base->FIFOCFG |= I2S_FIFOCFG_DMATX_MASK; + } + else + { + base->FIFOCFG &= (~I2S_FIFOCFG_DMATX_MASK); + base->FIFOCFG |= I2S_FIFOCFG_EMPTYTX_MASK; + } +} + +static void I2S_RxEnableDMA(I2S_Type *base, bool enable) +{ + if (enable) + { + base->FIFOCFG |= I2S_FIFOCFG_DMARX_MASK; + } + else + { + base->FIFOCFG &= (~I2S_FIFOCFG_DMARX_MASK); + base->FIFOCFG |= I2S_FIFOCFG_EMPTYRX_MASK; + } +} + +static uint16_t I2S_GetTransferBytes(volatile i2s_transfer_t *transfer) +{ + assert(transfer); + + uint16_t transferBytes; + + if (transfer->dataSize >= (2 * DMA_MAX_TRANSFER_BYTES)) + { + transferBytes = DMA_MAX_TRANSFER_BYTES; + } + else if (transfer->dataSize > DMA_MAX_TRANSFER_BYTES) + { + transferBytes = transfer->dataSize / 2U; + if ((transferBytes % 4U) != 0U) + { + transferBytes -= (transferBytes % 4U); + } + } + else + { + transferBytes = transfer->dataSize; + } + + return transferBytes; +} + +static status_t I2S_StartTransferDMA(I2S_Type *base, i2s_dma_handle_t *handle) +{ + uint32_t instance = I2S_GetInstance(base); + i2s_dma_private_handle_t *privateHandle = &(s_DmaPrivateHandle[instance]); + volatile i2s_transfer_t *transfer = &(privateHandle->descriptorQueue[privateHandle->queueDescriptor]); + uint16_t transferBytes = I2S_GetTransferBytes(transfer); + int i = 0U; + uint32_t xferConfig = 0U; + + /* Initial descriptor is stored in another place in memory, but treat it as another descriptor for simplicity */ + privateHandle->dmaDescriptorsUsed = 1U; + privateHandle->intA = false; + + /* submit transfer parameter directly */ + xferConfig = DMA_CHANNEL_XFER(true, false, privateHandle->intA, !privateHandle->intA, handle->bytesPerFrame, + (handle->state == kI2S_DmaStateTx) ? 1U : 0U, + (handle->state == kI2S_DmaStateTx) ? 0U : 1U, transferBytes); + DMA_SubmitChannelTransferParameter( + handle->dmaHandle, xferConfig, + (void *)((handle->state == kI2S_DmaStateTx) ? (uint32_t)transfer->data : (uint32_t)(&(base->FIFORD))), + (void *)((handle->state == kI2S_DmaStateTx) ? (uint32_t)(&(base->FIFOWR)) : (uint32_t)transfer->data), + (void *)&(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + 0U])); + + privateHandle->enqueuedBytes[privateHandle->enqueuedBytesEnd] = transferBytes; + privateHandle->enqueuedBytesEnd = (privateHandle->enqueuedBytesEnd + 1U) % DMA_DESCRIPTORS; + + transfer->dataSize -= transferBytes; + transfer->data += transferBytes; + + if (transfer->dataSize == 0U) + { + transfer->data = NULL; + privateHandle->queueDescriptor = (privateHandle->queueDescriptor + 1U) % I2S_NUM_BUFFERS; + } + + /* Link the DMA descriptors for the case when no additional transfer is queued before the initial one finishes + * The configuration for the DMA dummy descriptor make no sense to tx or rx transfer, since it will be overwritten + * when another transfer request comes before the previous finished. + * To make sure the audio data transfer continuously, application must request another transfer by call + * I2S_RxTransferReceiveDMA or I2S_TxTransferSendDMA before previous transfer finished. + */ + for (i = 0; i < DMA_DESCRIPTORS; i++) + { + DMA_SetupDescriptor(&(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + i]), + DMA_CHANNEL_XFER(true, false, false, false, sizeof(uint32_t), 0U, 0U, 8U), + ((handle->state == kI2S_DmaStateTx) ? (void *)(uint32_t)&s_DummyBufferTx : + (void *)(uint32_t)(&(base->FIFORD))), + ((handle->state == kI2S_DmaStateTx) ? (void *)(uint32_t)(&(base->FIFOWR)) : + (void *)(uint32_t)&s_DummyBufferRx), + &(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + ((i + 1) % DMA_DESCRIPTORS)])); + } + + /* Submit and start initial DMA transfer */ + if (handle->state == kI2S_DmaStateTx) + { + I2S_TxEnableDMA(base, true); + } + else + { + I2S_RxEnableDMA(base, true); + } + /* enable I2S peripheral request and put the channel into triggered status */ + DMA_EnableChannelPeriphRq(handle->dmaHandle->base, handle->dmaHandle->channel); + DMA_StartTransfer(handle->dmaHandle); + + I2S_Enable(base); + + return kStatus_Success; +} + +static void I2S_AddTransferDMA(I2S_Type *base, i2s_dma_handle_t *handle) +{ + volatile i2s_transfer_t *transfer; + uint16_t transferBytes; + uint32_t instance; + i2s_dma_private_handle_t *privateHandle; + dma_descriptor_t *descriptor; + dma_descriptor_t *nextDescriptor; + uint32_t xferConfig = 0U; + + instance = I2S_GetInstance(base); + privateHandle = &(s_DmaPrivateHandle[instance]); + + while (privateHandle->dmaDescriptorsUsed < DMA_DESCRIPTORS) + { + transfer = &(privateHandle->descriptorQueue[privateHandle->queueDescriptor]); + + if (transfer->dataSize == 0U) + { + /* Nothing to be added */ + return; + } + + /* Determine currently configured descriptor and the other which it will link to */ + descriptor = &(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + privateHandle->descriptor]); + privateHandle->descriptor = (privateHandle->descriptor + 1U) % DMA_DESCRIPTORS; + nextDescriptor = &(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + privateHandle->descriptor]); + + transferBytes = I2S_GetTransferBytes(transfer); + privateHandle->enqueuedBytes[privateHandle->enqueuedBytesEnd] = transferBytes; + privateHandle->enqueuedBytesEnd = (privateHandle->enqueuedBytesEnd + 1U) % DMA_DESCRIPTORS; + + xferConfig = DMA_CHANNEL_XFER(true, false, !privateHandle->intA, privateHandle->intA, handle->bytesPerFrame, + (handle->state == kI2S_DmaStateTx) ? 1U : 0U, + (handle->state == kI2S_DmaStateTx) ? 0U : 1U, transferBytes); + + DMA_SetupDescriptor(descriptor, xferConfig, + ((handle->state == kI2S_DmaStateTx) ? (void *)(uint32_t)transfer->data : + (void *)(uint32_t) & (base->FIFORD)), + ((handle->state == kI2S_DmaStateTx) ? (void *)(uint32_t) & (base->FIFOWR) : + (void *)(uint32_t)transfer->data), + nextDescriptor); + + /* Advance internal state */ + privateHandle->dmaDescriptorsUsed++; + privateHandle->intA = !privateHandle->intA; + + transfer->dataSize -= transferBytes; + transfer->data += transferBytes; + if (transfer->dataSize == 0U) + { + transfer->data = NULL; + privateHandle->queueDescriptor = (privateHandle->queueDescriptor + 1U) % I2S_NUM_BUFFERS; + } + } +} + +/*! + * brief Invoked from DMA interrupt handler. + * + * param handle pointer to DMA handle structure. + * param userData argument for user callback. + * param transferDone if transfer was done. + * param tcds + */ +void I2S_DMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t tcds) +{ + i2s_dma_private_handle_t *privateHandle = (i2s_dma_private_handle_t *)userData; + i2s_dma_handle_t *i2sHandle = privateHandle->handle; + I2S_Type *base = privateHandle->base; + + if ((!transferDone) || (i2sHandle->state == kI2S_DmaStateIdle)) + { + return; + } + + if (privateHandle->dmaDescriptorsUsed > 0U) + { + /* Finished descriptor, decrease amount of data to be processed */ + + i2sHandle->i2sQueue[i2sHandle->queueDriver].dataSize -= + privateHandle->enqueuedBytes[privateHandle->enqueuedBytesStart]; + i2sHandle->i2sQueue[i2sHandle->queueDriver].data += + privateHandle->enqueuedBytes[privateHandle->enqueuedBytesStart]; + privateHandle->enqueuedBytes[privateHandle->enqueuedBytesStart] = 0U; + privateHandle->enqueuedBytesStart = (privateHandle->enqueuedBytesStart + 1U) % DMA_DESCRIPTORS; + privateHandle->dmaDescriptorsUsed--; + } + + if (i2sHandle->i2sQueue[i2sHandle->queueDriver].dataSize == 0U) + { + /* Entire user buffer sent or received - advance to next one */ + i2sHandle->i2sQueue[i2sHandle->queueDriver].data = NULL; + i2sHandle->queueDriver = (i2sHandle->queueDriver + 1U) % I2S_NUM_BUFFERS; + /* Notify user about buffer completion */ + if (i2sHandle->completionCallback) + { + (i2sHandle->completionCallback)(base, i2sHandle, kStatus_I2S_BufferComplete, i2sHandle->userData); + } + } + /* check next buffer queue is avaliable or not */ + if (i2sHandle->i2sQueue[i2sHandle->queueDriver].dataSize == 0U) + { + /* All user buffers processed */ + I2S_TransferAbortDMA(base, i2sHandle); + } + else + { + /* Enqueue another user buffer to DMA if it could not be done when in I2S_Rx/TxTransferSendDMA */ + I2S_AddTransferDMA(base, i2sHandle); + } +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2s_dma.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2s_dma.h new file mode 100644 index 000000000..b2b0e5e2f --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2s_dma.h @@ -0,0 +1,162 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_I2S_DMA_H_ +#define _FSL_I2S_DMA_H_ + +#include "fsl_device_registers.h" +#include "fsl_common.h" +#include "fsl_flexcomm.h" + +#include "fsl_dma.h" +#include "fsl_i2s.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @addtogroup i2s_dma_driver + * @{ + */ + +/*! @name Driver version */ +/*@{*/ +/*! @brief I2S DMA driver version 2.1.0. */ +#define FSL_I2S_DMA_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) +/*@}*/ + +/*! @brief Members not to be accessed / modified outside of the driver. */ +typedef struct _i2s_dma_handle i2s_dma_handle_t; + +/*! + * @brief Callback function invoked from DMA API on completion. + * + * @param base I2S base pointer. + * @param handle pointer to I2S transaction. + * @param completionStatus status of the transaction. + * @param userData optional pointer to user arguments data. + */ +typedef void (*i2s_dma_transfer_callback_t)(I2S_Type *base, + i2s_dma_handle_t *handle, + status_t completionStatus, + void *userData); +/*! @brief i2s dma handle */ +struct _i2s_dma_handle +{ + uint32_t state; /*!< Internal state of I2S DMA transfer */ + uint8_t bytesPerFrame; /*!< bytes per frame */ + i2s_dma_transfer_callback_t completionCallback; /*!< Callback function pointer */ + void *userData; /*!< Application data passed to callback */ + dma_handle_t *dmaHandle; /*!< DMA handle */ + volatile i2s_transfer_t i2sQueue[I2S_NUM_BUFFERS]; /*!< Transfer queue storing transfer buffers */ + volatile uint8_t queueUser; /*!< Queue index where user's next transfer will be stored */ + volatile uint8_t queueDriver; /*!< Queue index of buffer actually used by the driver */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! @} */ + +/*! + * @name DMA API + * @{ + */ + +/*! + * @brief Initializes handle for transfer of audio data. + * + * @param base I2S base pointer. + * @param handle pointer to handle structure. + * @param dmaHandle pointer to dma handle structure. + * @param callback function to be called back when transfer is done or fails. + * @param userData pointer to data passed to callback. + */ +void I2S_TxTransferCreateHandleDMA(I2S_Type *base, + i2s_dma_handle_t *handle, + dma_handle_t *dmaHandle, + i2s_dma_transfer_callback_t callback, + void *userData); + +/*! + * @brief Begins or queue sending of the given data. + * + * @param base I2S base pointer. + * @param handle pointer to handle structure. + * @param transfer data buffer. + * + * @retval kStatus_Success + * @retval kStatus_I2S_Busy if all queue slots are occupied with unsent buffers. + */ +status_t I2S_TxTransferSendDMA(I2S_Type *base, i2s_dma_handle_t *handle, i2s_transfer_t transfer); + +/*! + * @brief Aborts transfer of data. + * + * @param base I2S base pointer. + * @param handle pointer to handle structure. + */ +void I2S_TransferAbortDMA(I2S_Type *base, i2s_dma_handle_t *handle); + +/*! + * @brief Initializes handle for reception of audio data. + * + * @param base I2S base pointer. + * @param handle pointer to handle structure. + * @param dmaHandle pointer to dma handle structure. + * @param callback function to be called back when transfer is done or fails. + * @param userData pointer to data passed to callback. + */ +void I2S_RxTransferCreateHandleDMA(I2S_Type *base, + i2s_dma_handle_t *handle, + dma_handle_t *dmaHandle, + i2s_dma_transfer_callback_t callback, + void *userData); + +/*! + * @brief Begins or queue reception of data into given buffer. + * + * @param base I2S base pointer. + * @param handle pointer to handle structure. + * @param transfer data buffer. + * + * @retval kStatus_Success + * @retval kStatus_I2S_Busy if all queue slots are occupied with buffers + * which are not full. + */ +status_t I2S_RxTransferReceiveDMA(I2S_Type *base, i2s_dma_handle_t *handle, i2s_transfer_t transfer); + +/*! + * @brief Invoked from DMA interrupt handler. + * + * @param handle pointer to DMA handle structure. + * @param userData argument for user callback. + * @param transferDone if transfer was done. + * @param tcds + */ +void I2S_DMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t tcds); + +/*! @} */ + +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +#endif /* _FSL_I2S_DMA_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_iap.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_iap.c new file mode 100644 index 000000000..7114b07c7 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_iap.c @@ -0,0 +1,285 @@ +/* + * Copyright 2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "fsl_iap.h" +#include "fsl_iap_ffr.h" +#include "fsl_device_registers.h" +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.iap1" +#endif + +/*! + * @addtogroup flash_driver_api + * @{ + */ + +#define ROM_API_TREE ((uint32_t *)0x130010f0) +#define BOOTLOADER_API_TREE_POINTER ((bootloader_tree_t *)ROM_API_TREE) + +static uint32_t S_VersionMajor = 0; + +typedef status_t (*EraseCommend_t)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key); +typedef status_t (*ProgramCommend_t)(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes); +typedef status_t (*VerifyProgramCommend_t)(flash_config_t *config, + uint32_t start, + uint32_t lengthInBytes, + const uint8_t *expectedData, + uint32_t *failedAddress, + uint32_t *failedData); +/* + *!@brief Structure of version property. + * + *!@ingroup bl_core + */ +typedef union StandardVersion +{ + struct + { + uint32_t bugfix : 8; /*!< bugfix version [7:0] */ + uint32_t minor : 8; /*!< minor version [15:8] */ + uint32_t major : 8; /*!< major version [23:16] */ + uint32_t name : 8; /*!< name [31:24] */ + }; + uint32_t version; /*!< combined version numbers. */ +#if defined(__cplusplus) + StandardVersion() : version(0) + { + } + StandardVersion(uint32_t version) : version(version) + { + } +#endif +} standard_version_t; + +/*! @brief Interface for the flash driver.*/ +typedef struct FlashDriverInterface +{ + standard_version_t version; /*!< flash driver API version number.*/ + + /*!< Flash driver.*/ + status_t (*flash_init)(flash_config_t *config); + status_t (*flash_erase)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key); + status_t (*flash_program)(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes); + status_t (*flash_verify_erase)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes); + status_t (*flash_verify_program)(flash_config_t *config, + uint32_t start, + uint32_t lengthInBytes, + const uint8_t *expectedData, + uint32_t *failedAddress, + uint32_t *failedData); + status_t (*flash_get_property)(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value); + status_t (*flash_erase_with_checker)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key); + status_t (*flash_program_with_checker)(flash_config_t *config, + uint32_t start, + uint8_t *src, + uint32_t lengthInBytes); + status_t (*flash_verify_program_with_checker)(flash_config_t *config, + uint32_t start, + uint32_t lengthInBytes, + const uint8_t *expectedData, + uint32_t *failedAddress, + uint32_t *failedData); + /*!< Flash FFR driver*/ + status_t (*ffr_init)(flash_config_t *config); + status_t (*ffr_deinit)(flash_config_t *config); + status_t (*ffr_cust_factory_page_write)(flash_config_t *config, uint8_t *page_data, bool seal_part); + status_t (*ffr_get_uuid)(flash_config_t *config, uint8_t *uuid); + status_t (*ffr_get_customer_data)(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); + status_t (*ffr_keystore_write)(flash_config_t *config, ffr_key_store_t *pKeyStore); + status_t (*ffr_keystore_get_ac)(flash_config_t *config, uint8_t *pActivationCode); + status_t (*ffr_keystore_get_kc)(flash_config_t *config, uint8_t *pKeyCode, ffr_key_type_t keyIndex); + status_t (*ffr_infield_page_write)(flash_config_t *config, uint8_t *page_data, uint32_t valid_len); + status_t (*ffr_get_customer_infield_data)(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); +} flash_driver_interface_t; + +/*! + * @brief Root of the bootloader API tree. + * + * An instance of this struct resides in read-only memory in the bootloader. It + * provides a user application access to APIs exported by the bootloader. + * + * @note The order of existing fields must not be changed. + */ +typedef struct BootloaderTree +{ + void (*runBootloader)(void *arg); /*!< Function to start the bootloader executing. */ + standard_version_t bootloader_version; /*!< Bootloader version number. */ + const char *copyright; /*!< Copyright string. */ + const uint32_t *reserved; /*!< Do NOT use. */ + const flash_driver_interface_t *flashDriver; /*!< Flash driver API. */ +} bootloader_tree_t; + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief Global pointer to the flash driver API table in ROM. */ +flash_driver_interface_t *FLASH_API_TREE; +/*! Get pointer to flash driver API table in ROM. */ +#define FLASH_API_TREE BOOTLOADER_API_TREE_POINTER->flashDriver +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! See fsl_flash.h for documentation of this function. */ +status_t FLASH_Init(flash_config_t *config) +{ + assert(FLASH_API_TREE); + config->modeConfig.sysFreqInMHz = kSysToFlashFreq_defaultInMHz; + S_VersionMajor = BOOTLOADER_API_TREE_POINTER->bootloader_version.major; + return FLASH_API_TREE->flash_init(config); +} + +/*! See fsl_flash.h for documentation of this function. */ +status_t FLASH_Erase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key) +{ + if (S_VersionMajor == 2) + { + EraseCommend_t EraseCommand = + (EraseCommend_t)(0x1300413b); /*!< get the flash erase api location adress int rom */ + return EraseCommand(config, start, lengthInBytes, key); + } + else + { + assert(FLASH_API_TREE); + return FLASH_API_TREE->flash_erase(config, start, lengthInBytes, key); + } +} + +/*! See fsl_flash.h for documentation of this function. */ +status_t FLASH_Program(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes) +{ + if (S_VersionMajor == 2) + { + ProgramCommend_t ProgramCommend = + (ProgramCommend_t)(0x1300419d); /*!< get the flash program api location adress in rom*/ + return ProgramCommend(config, start, src, lengthInBytes); + } + else + { + assert(FLASH_API_TREE); + return FLASH_API_TREE->flash_program(config, start, src, lengthInBytes); + } +} + +/*! See fsl_flash.h for documentation of this function. */ +status_t FLASH_VerifyErase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes) +{ + assert(FLASH_API_TREE); + return FLASH_API_TREE->flash_verify_erase(config, start, lengthInBytes); +} + +/*! See fsl_flash.h for documentation of this function. */ +status_t FLASH_VerifyProgram(flash_config_t *config, + uint32_t start, + uint32_t lengthInBytes, + const uint8_t *expectedData, + uint32_t *failedAddress, + uint32_t *failedData) +{ + if (S_VersionMajor == 2) + { + VerifyProgramCommend_t VerifyProgramCommend = + (VerifyProgramCommend_t)(0x1300427d); /*!< get the flash verify program api location adress in + rom*/ + return VerifyProgramCommend(config, start, lengthInBytes, expectedData, failedAddress, failedData); + } + else + { + assert(FLASH_API_TREE); + return FLASH_API_TREE->flash_verify_program(config, start, lengthInBytes, expectedData, failedAddress, + failedData); + } +} + +/*! See fsl_flash.h for documentation of this function.*/ +status_t FLASH_GetProperty(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value) +{ + assert(FLASH_API_TREE); + return FLASH_API_TREE->flash_get_property(config, whichProperty, value); +} +/******************************************************************************** + * fsl iap ffr CODE + *******************************************************************************/ + +/*! See fsl_iap_ffr.h for documentation of this function. */ +status_t FFR_Init(flash_config_t *config) +{ + assert(FLASH_API_TREE); + return FLASH_API_TREE->ffr_init(config); +} + +/*! See fsl_iap_ffr.h for documentation of this function. */ +status_t FFR_Deinit(flash_config_t *config) +{ + assert(FLASH_API_TREE); + return FLASH_API_TREE->ffr_deinit(config); +} + +/*! See fsl_iap_ffr.h for documentation of this function. */ +status_t FFR_CustFactoryPageWrite(flash_config_t *config, uint8_t *page_data, bool seal_part) +{ + assert(FLASH_API_TREE); + return FLASH_API_TREE->ffr_cust_factory_page_write(config, page_data, seal_part); +} + +/*! See fsl_iap_ffr.h for documentation of this function. */ +status_t FFR_GetUUID(flash_config_t *config, uint8_t *uuid) +{ + assert(FLASH_API_TREE); + return FLASH_API_TREE->ffr_get_uuid(config, uuid); +} + +/*! See fsl_iap_ffr.h for documentation of this function. */ +status_t FFR_GetCustomerData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len) +{ + assert(FLASH_API_TREE); + return FLASH_API_TREE->ffr_get_customer_data(config, pData, offset, len); +} + +/*! See fsl_iap_ffr.h for documentation of this function. */ +status_t FFR_KeystoreWrite(flash_config_t *config, ffr_key_store_t *pKeyStore) +{ + assert(FLASH_API_TREE); + return FLASH_API_TREE->ffr_keystore_write(config, pKeyStore); +} + +/*! See fsl_iap_ffr.h for documentation of this function. */ +status_t FFR_KeystoreGetAC(flash_config_t *config, uint8_t *pActivationCode) +{ + assert(FLASH_API_TREE); + return FLASH_API_TREE->ffr_keystore_get_ac(config, pActivationCode); +} + +/*! See fsl_iap_ffr.h for documentation of this function. */ +status_t FFR_KeystoreGetKC(flash_config_t *config, uint8_t *pKeyCode, ffr_key_type_t keyIndex) +{ + assert(FLASH_API_TREE); + return FLASH_API_TREE->ffr_keystore_get_kc(config, pKeyCode, keyIndex); +} + +/*! See fsl_iap_ffr.h for documentation of this function. */ +status_t FFR_InfieldPageWrite(flash_config_t *config, uint8_t *page_data, uint32_t valid_len) +{ + assert(FLASH_API_TREE); + return FLASH_API_TREE->ffr_infield_page_write(config, page_data, valid_len); +} + +/*! See fsl_iap_ffr.h for documentation of this function. */ +status_t FFR_GetCustomerInfieldData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len) +{ + assert(FLASH_API_TREE); + return FLASH_API_TREE->ffr_get_customer_infield_data(config, pData, offset, len); +} + +/*! @}*/ + +/******************************************************************************** + * EOF + *******************************************************************************/ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_iap.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_iap.h new file mode 100644 index 000000000..c57f66707 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_iap.h @@ -0,0 +1,498 @@ +/* + * Copyright 2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef __FSL_IAP_H_ +#define __FSL_IAP_H_ + +#include "fsl_common.h" +/*! + * @addtogroup flash_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! + * @name Flash version + * @{ + */ +/*! @brief Constructs the version number for drivers. */ +#if !defined(MAKE_VERSION) +#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix)) +#endif + +/*! @brief Flash driver version for SDK*/ +#define FSL_FLASH_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */ + +/*! @brief Flash driver version for ROM*/ +enum _flash_driver_version_constants +{ + kFLASH_DriverVersionName = 'F', /*!< Flash driver version name.*/ + kFLASH_DriverVersionMajor = 2, /*!< Major flash driver version.*/ + kFLASH_DriverVersionMinor = 0, /*!< Minor flash driver version.*/ + kFLASH_DriverVersionBugfix = 0 /*!< Bugfix for flash driver version.*/ +}; + +/*@}*/ + +/*! + * @name Flash configuration + * @{ + */ +/*! @brief Flash IP Type. */ +#if !defined(FSL_FEATURE_FLASH_IP_IS_C040HD_ATFC) +#define FSL_FEATURE_FLASH_IP_IS_C040HD_ATFC (1) +#endif +#if !defined(FSL_FEATURE_FLASH_IP_IS_C040HD_FC) +#define FSL_FEATURE_FLASH_IP_IS_C040HD_FC (0) +#endif + +/*! + * @name Flash status + * @{ + */ +/*! @brief Flash driver status group. */ +#if defined(kStatusGroup_FlashDriver) +#define kStatusGroupGeneric kStatusGroup_Generic +#define kStatusGroupFlashDriver kStatusGroup_FlashDriver +#elif defined(kStatusGroup_FLASHIAP) +#define kStatusGroupGeneric kStatusGroup_Generic +#define kStatusGroupFlashDriver kStatusGroup_FLASH +#else +#define kStatusGroupGeneric 0 +#define kStatusGroupFlashDriver 1 +#endif + +/*! @brief Constructs a status code value from a group and a code number. */ +#if !defined(MAKE_STATUS) +#define MAKE_STATUS(group, code) ((((group)*100) + (code))) +#endif + +/*! + * @brief Flash driver status codes. + */ +enum _flash_status +{ + kStatus_FLASH_Success = MAKE_STATUS(kStatusGroupGeneric, 0), /*!< API is executed successfully*/ + kStatus_FLASH_InvalidArgument = MAKE_STATUS(kStatusGroupGeneric, 4), /*!< Invalid argument*/ + kStatus_FLASH_SizeError = MAKE_STATUS(kStatusGroupFlashDriver, 0), /*!< Error size*/ + kStatus_FLASH_AlignmentError = + MAKE_STATUS(kStatusGroupFlashDriver, 1), /*!< Parameter is not aligned with the specified baseline*/ + kStatus_FLASH_AddressError = MAKE_STATUS(kStatusGroupFlashDriver, 2), /*!< Address is out of range */ + kStatus_FLASH_AccessError = + MAKE_STATUS(kStatusGroupFlashDriver, 3), /*!< Invalid instruction codes and out-of bound addresses */ + kStatus_FLASH_ProtectionViolation = MAKE_STATUS( + kStatusGroupFlashDriver, 4), /*!< The program/erase operation is requested to execute on protected areas */ + kStatus_FLASH_CommandFailure = + MAKE_STATUS(kStatusGroupFlashDriver, 5), /*!< Run-time error during command execution. */ + kStatus_FLASH_UnknownProperty = MAKE_STATUS(kStatusGroupFlashDriver, 6), /*!< Unknown property.*/ + kStatus_FLASH_EraseKeyError = MAKE_STATUS(kStatusGroupFlashDriver, 7), /*!< API erase key is invalid.*/ + kStatus_FLASH_RegionExecuteOnly = + MAKE_STATUS(kStatusGroupFlashDriver, 8), /*!< The current region is execute-only.*/ + kStatus_FLASH_ExecuteInRamFunctionNotReady = + MAKE_STATUS(kStatusGroupFlashDriver, 9), /*!< Execute-in-RAM function is not available.*/ + + kStatus_FLASH_CommandNotSupported = MAKE_STATUS(kStatusGroupFlashDriver, 11), /*!< Flash API is not supported.*/ + kStatus_FLASH_ReadOnlyProperty = MAKE_STATUS(kStatusGroupFlashDriver, 12), /*!< The flash property is read-only.*/ + kStatus_FLASH_InvalidPropertyValue = + MAKE_STATUS(kStatusGroupFlashDriver, 13), /*!< The flash property value is out of range.*/ + kStatus_FLASH_InvalidSpeculationOption = + MAKE_STATUS(kStatusGroupFlashDriver, 14), /*!< The option of flash prefetch speculation is invalid.*/ + kStatus_FLASH_EccError = MAKE_STATUS(kStatusGroupFlashDriver, + 0x10), /*!< A correctable or uncorrectable error during command execution. */ + kStatus_FLASH_CompareError = + MAKE_STATUS(kStatusGroupFlashDriver, 0x11), /*!< Destination and source memory contents do not match. */ + kStatus_FLASH_RegulationLoss = MAKE_STATUS(kStatusGroupFlashDriver, 0x12), /*!< A loss of regulation during read. */ + kStatus_FLASH_InvalidWaitStateCycles = + MAKE_STATUS(kStatusGroupFlashDriver, 0x13), /*!< The wait state cycle set to r/w mode is invalid. */ + + kStatus_FLASH_OutOfDateCfpaPage = + MAKE_STATUS(kStatusGroupFlashDriver, 0x20), /*!< CFPA page version is out of date. */ + kStatus_FLASH_BlankIfrPageData = MAKE_STATUS(kStatusGroupFlashDriver, 0x21), /*!< Blank page cannnot be read. */ + kStatus_FLASH_EncryptedRegionsEraseNotDoneAtOnce = + MAKE_STATUS(kStatusGroupFlashDriver, 0x22), /*!< Encrypted flash subregions are not erased at once. */ + kStatus_FLASH_ProgramVerificationNotAllowed = MAKE_STATUS( + kStatusGroupFlashDriver, 0x23), /*!< Program verification is not allowed when the encryption is enabled. */ + kStatus_FLASH_HashCheckError = + MAKE_STATUS(kStatusGroupFlashDriver, 0x24), /*!< Hash check of page data is failed. */ + kStatus_FLASH_SealedFfrRegion = MAKE_STATUS(kStatusGroupFlashDriver, 0x25), /*!< The FFR region is sealed. */ + kStatus_FLASH_FfrRegionWriteBroken = MAKE_STATUS( + kStatusGroupFlashDriver, 0x26), /*!< The FFR Spec region is not allowed to be written discontinuously. */ + kStatus_FLASH_NmpaAccessNotAllowed = + MAKE_STATUS(kStatusGroupFlashDriver, 0x27), /*!< The NMPA region is not allowed to be read/written/erased. */ + kStatus_FLASH_CmpaCfgDirectEraseNotAllowed = + MAKE_STATUS(kStatusGroupFlashDriver, 0x28), /*!< The CMPA Cfg region is not allowed to be erased directly. */ + kStatus_FLASH_FfrBankIsLocked = MAKE_STATUS(kStatusGroupFlashDriver, 0x29), /*!< The FFR bank region is locked. */ +}; +/*@}*/ + +/*! + * @name Flash API key + * @{ + */ +/*! @brief Constructs the four character code for the Flash driver API key. */ +#if !defined(FOUR_CHAR_CODE) +#define FOUR_CHAR_CODE(a, b, c, d) (((d) << 24) | ((c) << 16) | ((b) << 8) | ((a))) +#endif + +/*! + * @brief Enumeration for Flash driver API keys. + * + * @note The resulting value is built with a byte order such that the string + * being readable in expected order when viewed in a hex editor, if the value + * is treated as a 32-bit little endian value. + */ +enum _flash_driver_api_keys +{ + kFLASH_ApiEraseKey = FOUR_CHAR_CODE('l', 'f', 'e', 'k') /*!< Key value used to validate all flash erase APIs.*/ +}; +/*@}*/ + +/*! + * @brief Enumeration for various flash properties. + */ +typedef enum _flash_property_tag +{ + kFLASH_PropertyPflashSectorSize = 0x00U, /*!< Pflash sector size property.*/ + kFLASH_PropertyPflashTotalSize = 0x01U, /*!< Pflash total size property.*/ + kFLASH_PropertyPflashBlockSize = 0x02U, /*!< Pflash block size property.*/ + kFLASH_PropertyPflashBlockCount = 0x03U, /*!< Pflash block count property.*/ + kFLASH_PropertyPflashBlockBaseAddr = 0x04U, /*!< Pflash block base address property.*/ + + kFLASH_PropertyPflashPageSize = 0x30U, /*!< Pflash page size property.*/ + kFLASH_PropertyPflashSystemFreq = 0x31U, /*!< System Frequency System Frequency.*/ + + kFLASH_PropertyFfrSectorSize = 0x40U, /*!< FFR sector size property.*/ + kFLASH_PropertyFfrTotalSize = 0x41U, /*!< FFR total size property.*/ + kFLASH_PropertyFfrBlockBaseAddr = 0x42U, /*!< FFR block base address property.*/ + kFLASH_PropertyFfrPageSize = 0x43U, /*!< FFR page size property.*/ +} flash_property_tag_t; + +/*! + * @brief Enumeration for flash max pages to erase. + */ +enum _flash_max_erase_page_value +{ + kFLASH_MaxPagesToErase = 100U /*!< The max value in pages to erase. */ +}; + +/*! + * @brief Enumeration for flash alignment property. + */ +enum _flash_alignment_property +{ + kFLASH_AlignementUnitVerifyErase = 4, /*!< The alignment unit in bytes used for verify erase operation.*/ + kFLASH_AlignementUnitProgram = 512, /*!< The alignment unit in bytes used for program operation.*/ + /*kFLASH_AlignementUnitVerifyProgram = 4,*/ /*!< The alignment unit in bytes used for verify program operation.*/ + kFLASH_AlignementUnitSingleWordRead = 16 /*!< The alignment unit in bytes used for SingleWordRead command.*/ +}; + +/*! + * @brief Enumeration for flash read ecc option + */ +enum _flash_read_ecc_option +{ + kFLASH_ReadWithEccOn = 0, /*! ECC is on */ + kFLASH_ReadWithEccOff = 1, /*! ECC is off */ +}; + +/* set flash Controller timing before flash init */ +enum _flash_freq_tag +{ + kSysToFlashFreq_lowInMHz = 12u, + kSysToFlashFreq_defaultInMHz = 96u, +}; + +/*! + * @brief Enumeration for flash read margin option + */ +enum _flash_read_margin_option +{ + kFLASH_ReadMarginNormal = 0, /*!< Normal read */ + kFLASH_ReadMarginVsProgram = 1, /*!< Margin vs. program */ + kFLASH_ReadMarginVsErase = 2, /*!< Margin vs. erase */ + kFLASH_ReadMarginIllegalBitCombination = 3 /*!< Illegal bit combination */ +}; + +/*! + * @brief Enumeration for flash read dmacc option + */ +enum _flash_read_dmacc_option +{ + kFLASH_ReadDmaccDisabled = 0, /*!< Memory word */ + kFLASH_ReadDmaccEnabled = 1, /*!< DMACC word */ +}; + +/*! + * @brief Enumeration for flash ramp control option + */ +enum _flash_ramp_control_option +{ + kFLASH_RampControlDivisionFactorReserved = 0, /*!< Reserved */ + kFLASH_RampControlDivisionFactor256 = 1, /*!< clk48mhz / 256 = 187.5KHz */ + kFLASH_RampControlDivisionFactor128 = 2, /*!< clk48mhz / 128 = 375KHz */ + kFLASH_RampControlDivisionFactor64 = 3 /*!< clk48mhz / 64 = 750KHz */ +}; + +/*! @brief Flash ECC log info. */ +typedef struct _flash_ecc_log +{ + uint32_t firstEccEventAddress; + uint32_t eccErrorCount; + uint32_t eccCorrectionCount; + uint32_t reserved; +} flash_ecc_log_t; + +/*! @brief Flash controller paramter config. */ +typedef struct _flash_mode_config +{ + uint32_t sysFreqInMHz; + /* ReadSingleWord parameter. */ + struct + { + uint8_t readWithEccOff : 1; + uint8_t readMarginLevel : 2; + uint8_t readDmaccWord : 1; + uint8_t reserved0 : 4; + uint8_t reserved1[3]; + } readSingleWord; + /* SetWriteMode parameter. */ + struct + { + uint8_t programRampControl; + uint8_t eraseRampControl; + uint8_t reserved[2]; + } setWriteMode; + /* SetReadMode parameter. */ + struct + { + uint16_t readInterfaceTimingTrim; + uint16_t readControllerTimingTrim; + uint8_t readWaitStates; + uint8_t reserved[3]; + } setReadMode; +} flash_mode_config_t; + +/*! @brief Flash controller paramter config. */ +typedef struct _flash_ffr_config +{ + uint32_t ffrBlockBase; + uint32_t ffrTotalSize; + uint32_t ffrPageSize; + uint32_t cfpaPageVersion; + uint32_t cfpaPageOffset; +} flash_ffr_config_t; + +/*! @brief Flash driver state information. + * + * An instance of this structure is allocated by the user of the flash driver and + * passed into each of the driver APIs. + */ +typedef struct _flash_config +{ + uint32_t PFlashBlockBase; /*!< A base address of the first PFlash block */ + uint32_t PFlashTotalSize; /*!< The size of the combined PFlash block. */ + uint32_t PFlashBlockCount; /*!< A number of PFlash blocks. */ + uint32_t PFlashPageSize; /*!< The size in bytes of a page of PFlash. */ + uint32_t PFlashSectorSize; /*!< The size in bytes of a sector of PFlash. */ + flash_ffr_config_t ffrConfig; + flash_mode_config_t modeConfig; +} flash_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization + * @{ + */ + +/*! + * @brief Initializes the global flash properties structure members. + * + * This function checks and initializes the Flash module for the other Flash APIs. + * + * @param config Pointer to the storage for the driver runtime state. + * + * @retval #kStatus_FLASH_Success API was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. + * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. + */ +status_t FLASH_Init(flash_config_t *config); + +/*@}*/ + +/*! + * @name Erasing + * @{ + */ + +/*! + * @brief Erases the flash sectors encompassed by parameters passed into function. + * + * This function erases the appropriate number of flash sectors based on the + * desired start address and length. + * + * @param config The pointer to the storage for the driver runtime state. + * @param start The start address of the desired flash memory to be erased. + * The start address does not need to be sector-aligned. + * @param lengthInBytes The length, given in bytes (not words or long-words) + * to be erased. Must be word-aligned. + * @param key The value used to validate all flash erase APIs. + * + * @retval #kStatus_FLASH_Success API was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FLASH_AlignmentError The parameter is not aligned with the specified baseline. + * @retval #kStatus_FLASH_AddressError The address is out of range. + * @retval #kStatus_FLASH_EraseKeyError The API erase key is invalid. + * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. + * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. + */ +status_t FLASH_Erase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key); + +/*@}*/ + +/*! + * @name Programming + * @{ + */ + +/*! + * @brief Programs flash with data at locations passed in through parameters. + * + * This function programs the flash memory with the desired data for a given + * flash area as determined by the start address and the length. + * + * @param config A pointer to the storage for the driver runtime state. + * @param start The start address of the desired flash memory to be programmed. Must be + * word-aligned. + * @param src A pointer to the source buffer of data that is to be programmed + * into the flash. + * @param lengthInBytes The length, given in bytes (not words or long-words), + * to be programmed. Must be word-aligned. + * + * @retval #kStatus_FLASH_Success API was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline. + * @retval #kStatus_FLASH_AddressError Address is out of range. + * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. + * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. + */ +status_t FLASH_Program(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes); + +/*@}*/ + +/*! + * @name Verification + * @{ + */ + +/*! + * @brief Verifies an erasure of the desired flash area at a specified margin level. + * + * This function checks the appropriate number of flash sectors based on + * the desired start address and length to check whether the flash is erased + * to the specified read margin level. + * + * @param config A pointer to the storage for the driver runtime state. + * @param start The start address of the desired flash memory to be verified. + * The start address does not need to be sector-aligned but must be word-aligned. + * @param lengthInBytes The length, given in bytes (not words or long-words), + * to be verified. Must be word-aligned. + * @param margin Read margin choice. + * + * @retval #kStatus_FLASH_Success API was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline. + * @retval #kStatus_FLASH_AddressError Address is out of range. + * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. + * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. + */ +status_t FLASH_VerifyErase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes); + +/*! + * @brief Verifies programming of the desired flash area at a specified margin level. + * + * This function verifies the data programed in the flash memory using the + * Flash Program Check Command and compares it to the expected data for a given + * flash area as determined by the start address and length. + * + * @param config A pointer to the storage for the driver runtime state. + * @param start The start address of the desired flash memory to be verified. Must be word-aligned. + * @param lengthInBytes The length, given in bytes (not words or long-words), + * to be verified. Must be word-aligned. + * @param expectedData A pointer to the expected data that is to be + * verified against. + * @param margin Read margin choice. + * @param failedAddress A pointer to the returned failing address. + * @param failedData A pointer to the returned failing data. Some derivatives do + * not include failed data as part of the FCCOBx registers. In this + * case, zeros are returned upon failure. + * + * @retval #kStatus_FLASH_Success API was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline. + * @retval #kStatus_FLASH_AddressError Address is out of range. + * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. + * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. + */ +status_t FLASH_VerifyProgram(flash_config_t *config, + uint32_t start, + uint32_t lengthInBytes, + const uint8_t *expectedData, + uint32_t *failedAddress, + uint32_t *failedData); + +/*@}*/ + +/*! + * @name Properties + * @{ + */ + +/*! + * @brief Returns the desired flash property. + * + * @param config A pointer to the storage for the driver runtime state. + * @param whichProperty The desired property from the list of properties in + * enum flash_property_tag_t + * @param value A pointer to the value returned for the desired flash property. + * + * @retval #kStatus_FLASH_Success API was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FLASH_UnknownProperty An unknown property tag. + */ +status_t FLASH_GetProperty(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value); + +/*@}*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __FLASH_FLASH_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_iap_ffr.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_iap_ffr.h new file mode 100644 index 000000000..1f366868d --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_iap_ffr.h @@ -0,0 +1,261 @@ +/* + * Copyright 2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef __FSL_IAP_FFR_H_ +#define __FSL_IAP_FFR_H_ + +#include "fsl_iap.h" + +/*! + * @addtogroup flash_ifr_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! + * @name Flash IFR version + * @{ + */ +/*! @brief Flash IFR driver version for SDK*/ +#define FSL_FLASH_IFR_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */ +/*@}*/ + +/*! @brief Alignment(down) utility. */ +#if !defined(ALIGN_DOWN) +#define ALIGN_DOWN(x, a) ((x) & (uint32_t)(-((int32_t)(a)))) +#endif + +/*! @brief Alignment(up) utility. */ +#if !defined(ALIGN_UP) +#define ALIGN_UP(x, a) (-((int32_t)((uint32_t)(-((int32_t)(x))) & (uint32_t)(-((int32_t)(a)))))) +#endif + +#define FLASH_FFR_MAX_PAGE_SIZE (512u) +#define FLASH_FFR_HASH_DIGEST_SIZE (32u) +#define FLASH_FFR_IV_CODE_SIZE (52u) + +enum _flash_ffr_page_offset +{ + kFfrPageOffset_CFPA = 0, /*!< Customer In-Field programmed area*/ + kFfrPageOffset_CFPA_Scratch = 0, /*!< CFPA Scratch page */ + kFfrPageOffset_CFPA_Cfg = 1, /*!< CFPA Configuration area (Ping page)*/ + kFfrPageOffset_CFPA_CfgPong = 2, /*!< Same as CFPA page (Pong page)*/ + + kFfrPageOffset_CMPA = 3, /*!< Customer Manufacturing programmed area*/ + kFfrPageOffset_CMPA_Cfg = 3, /*!< CMPA Configuration area (Part of CMPA)*/ + kFfrPageOffset_CMPA_Key = 4, /*!< Key Store area (Part of CMPA)*/ + + kFfrPageOffset_NMPA = 7, /*!< NXP Manufacturing programmed area*/ + kFfrPageOffset_NMPA_Romcp = 7, /*!< ROM patch area (Part of NMPA)*/ + kFfrPageOffset_NMPA_Repair = 9, /*!< Repair area (Part of NMPA)*/ + kFfrPageOffset_NMPA_Cfg = 15, /*!< NMPA configuration area (Part of NMPA)*/ + kFfrPageOffset_NMPA_End = 16, /*!< Reserved (Part of NMPA)*/ +}; + +enum _flash_ffr_page_num +{ + kFfrPageNum_CFPA = 3, /*!< Customer In-Field programmed area*/ + kFfrPageNum_CMPA = 4, /*!< Customer Manufacturing programmed area*/ + kFfrPageNum_NMPA = 10, /*!< NXP Manufacturing programmed area*/ + + kFfrPageNum_CMPA_Cfg = 1, + kFfrPageNum_CMPA_Key = 3, + kFfrPageNum_NMPA_Romcp = 2, + + kFfrPageNum_SpecArea = kFfrPageNum_CFPA + kFfrPageNum_CMPA, + kFfrPageNum_Total = (kFfrPageNum_CFPA + kFfrPageNum_CMPA + kFfrPageNum_NMPA), +}; + +enum _flash_ffr_block_size +{ + kFfrBlockSize_Key = 52u, + kFfrBlockSize_ActivationCode = 1192u, +}; + +typedef enum _cfpa_cfg_cmpa_prog_process +{ + kFfrCmpaProgProcess_Pre = 0x0u, + kFfrCmpaProgProcess_Post = 0xFFFFFFFFu, +} cmpa_prog_process_t; + +typedef struct _cfpa_cfg_iv_code +{ + uint32_t keycodeHeader; + uint8_t reserved[FLASH_FFR_IV_CODE_SIZE]; +} cfpa_cfg_iv_code_t; + +typedef struct _cfpa_cfg_info +{ + uint32_t header; /*!< [0x000-0x003] */ + uint32_t version; /*!< [0x004-0x007 */ + uint32_t secureFwVersion; /*!< [0x008-0x00b */ + uint32_t nsFwVersion; /*!< [0x00c-0x00f] */ + uint32_t imageKeyRevoke; /*!< [0x010-0x013] */ + uint8_t reserved0[4]; /*!< [0x014-0x017] */ + uint32_t rotkhRevoke; /*!< [0x018-0x01b] */ + uint32_t vendorUsage; /*!< [0x01c-0x01f] */ + uint32_t dcfgNsPin; /*!< [0x020-0x013] */ + uint32_t dcfgNsDflt; /*!< [0x024-0x017] */ + uint32_t enableFaMode; /*!< [0x028-0x02b] */ + uint8_t reserved1[4]; /*!< [0x02c-0x02f] */ + cfpa_cfg_iv_code_t ivCodePrinceRegion[3]; /*!< [0x030-0x0d7] */ + uint8_t reserved2[264]; /*!< [0x0d8-0x1df] */ + uint8_t sha256[32]; /*!< [0x1e0-0x1ff] */ +} cfpa_cfg_info_t; + +#define FFR_BOOTCFG_BOOTSPEED_MASK (0x18U) +#define FFR_BOOTCFG_BOOTSPEED_SHIFT (7U) +#define FFR_BOOTCFG_BOOTSPEED_48MHZ (0x0U) +#define FFR_BOOTCFG_BOOTSPEED_96MHZ (0x1U) + +#define FFR_USBID_VENDORID_MASK (0xFFFFU) +#define FFR_USBID_VENDORID_SHIFT (0U) +#define FFR_USBID_PRODUCTID_MASK (0xFFFF0000U) +#define FFR_USBID_PRODUCTID_SHIFT (16U) + +typedef struct _cmpa_cfg_info +{ + uint32_t bootCfg; /*!< [0x000-0x003] */ + uint32_t spiFlashCfg; /*!< [0x004-0x007] */ + struct + { + uint16_t vid; + uint16_t pid; + } usbId; /*!< [0x008-0x00b] */ + uint32_t sdioCfg; /*!< [0x00c-0x00f] */ + uint32_t dcfgPin; /*!< [0x010-0x013] */ + uint32_t dcfgDflt; /*!< [0x014-0x017] */ + uint32_t dapVendorUsage; /*!< [0x018-0x01b] */ + uint32_t secureBootCfg; /*!< [0x01c-0x01f] */ + uint32_t princeBaseAddr; /*!< [0x020-0x023] */ + uint32_t princeSr[3]; /*!< [0x024-0x02f] */ + uint8_t reserved0[32]; /*!< [0x030-0x04f] */ + uint32_t rotkh[8]; /*!< [0x050-0x06f] */ + uint8_t reserved1[368]; /*!< [0x070-0x1df] */ + uint8_t sha256[32]; /*!< [0x1e0-0x1ff] */ +} cmpa_cfg_info_t; + +typedef struct _cmpa_key_store_header +{ + uint32_t header; + uint8_t reserved[4]; +} cmpa_key_store_header_t; + +#define FFR_SYSTEM_SPEED_CODE_MASK (0x3U) +#define FFR_SYSTEM_SPEED_CODE_SHIFT (0U) +#define FFR_SYSTEM_SPEED_CODE_FRO12MHZ_12MHZ (0x0U) +#define FFR_SYSTEM_SPEED_CODE_FROHF96MHZ_24MHZ (0x1U) +#define FFR_SYSTEM_SPEED_CODE_FROHF96MHZ_48MHZ (0x2U) +#define FFR_SYSTEM_SPEED_CODE_FROHF96MHZ_96MHZ (0x3U) + +#define FFR_PERIPHERALCFG_PERI_MASK (0x7FFFFFFFU) +#define FFR_PERIPHERALCFG_PERI_SHIFT (0U) +#define FFR_PERIPHERALCFG_COREEN_MASK (0x10000000U) +#define FFR_PERIPHERALCFG_COREEN_SHIFT (31U) + +typedef struct _nmpa_cfg_info +{ + uint16_t fro32kCfg; /*!< [0x000-0x001] */ + uint8_t reserved0[6]; /*!< [0x002-0x007] */ + uint8_t sysCfg; /*!< [0x008-0x008] */ + uint8_t reserved1[7]; /*!< [0x009-0x00f] */ + struct + { + uint32_t data; + uint32_t reserved[3]; + } GpoInitData[3]; /*!< [0x010-0x03f] */ + uint32_t GpoDataChecksum[4]; /*!< [0x040-0x04f] */ + uint32_t finalTestBatchId[4]; /*!< [0x050-0x05f] */ + uint32_t deviceType; /*!< [0x060-0x063] */ + uint32_t finalTestProgVersion; /*!< [0x064-0x067] */ + uint32_t finalTestDate; /*!< [0x068-0x06b] */ + uint32_t finalTestTime; /*!< [0x06c-0x06f] */ + uint32_t uuid[4]; /*!< [0x070-0x07f] */ + uint8_t reserved2[32]; /*!< [0x080-0x09f] */ + uint32_t peripheralCfg; /*!< [0x0a0-0x0a3] */ + uint32_t ramSizeCfg; /*!< [0x0a4-0x0a7] */ + uint32_t flashSizeCfg; /*!< [0x0a8-0x0ab] */ + uint8_t reserved3[36]; /*!< [0x0ac-0x0cf] */ + uint8_t fro1mCfg; /*!< [0x0d0-0x0d0] */ + uint8_t reserved4[15]; /*!< [0x0d1-0x0df] */ + uint32_t dcdc[4]; /*!< [0x0e0-0x0ef] */ + uint32_t bod; /*!< [0x0f0-0x0f3] */ + uint8_t reserved5[12]; /*!< [0x0f4-0x0ff] */ + uint8_t calcHashReserved[192]; /*!< [0x100-0x1bf] */ + uint8_t sha256[32]; /*!< [0x1c0-0x1df] */ + uint32_t ecidBackup[4]; /*!< [0x1e0-0x1ef] */ + uint32_t pageChecksum[4]; /*!< [0x1f0-0x1ff] */ +} nmpa_cfg_info_t; + +typedef struct _ffr_key_store +{ + uint8_t reserved[3][FLASH_FFR_MAX_PAGE_SIZE]; +} ffr_key_store_t; + +typedef enum _ffr_key_type +{ + kFFR_KeyTypeSbkek = 0x00U, + kFFR_KeyTypeUser = 0x01U, + kFFR_KeyTypeUds = 0x02U, + kFFR_KeyTypePrinceRegion0 = 0x03U, + kFFR_KeyTypePrinceRegion1 = 0x04U, + kFFR_KeyTypePrinceRegion2 = 0x05U, +} ffr_key_type_t; + +typedef enum _ffr_bank_type +{ + kFFR_BankTypeBank0_NMPA = 0x00U, + kFFR_BankTypeBank1_CMPA = 0x01U, + kFFR_BankTypeBank2_CFPA = 0x02U +} ffr_bank_type_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! Generic APIs for FFR */ +status_t FFR_Init(flash_config_t *config); +status_t FFR_Deinit(flash_config_t *config); + +/*! APIs to access CFPA pages */ +status_t FFR_CustomerPagesInit(flash_config_t *config); +status_t FFR_InfieldPageWrite(flash_config_t *config, uint8_t *page_data, uint32_t valid_len); +/*! Read data stored in 'Customer In-field Page'. */ +status_t FFR_GetCustomerInfieldData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); + +/*! APIs to access CMPA pages */ +bool FFR_IsCmpaCfgPageUpdateInProgress(flash_config_t *config); +status_t FFR_RecoverCmpaCfgPage(flash_config_t *config); +status_t FFR_ProcessCmpaCfgPageUpdate(flash_config_t *config, cmpa_prog_process_t option); +status_t FFR_CustFactoryPageWrite(flash_config_t *config, uint8_t *page_data, bool seal_part); +/*! Read data stored in 'Customer Factory CFG Page'. */ +status_t FFR_GetCustomerData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); +status_t FFR_KeystoreWrite(flash_config_t *config, ffr_key_store_t *pKeyStore); +status_t FFR_KeystoreGetAC(flash_config_t *config, uint8_t *pActivationCode); +status_t FFR_KeystoreGetKC(flash_config_t *config, uint8_t *pKeyCode, ffr_key_type_t keyIndex); + +/*! APIs to access NMPA pages */ +status_t FFR_NxpAreaCheckIntegrity(flash_config_t *config); +status_t FFR_GetRompatchData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); +/*! Read data stored in 'NXP Manufacuring Programmed CFG Page'. */ +status_t FFR_GetManufactureData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); +status_t FFR_GetUUID(flash_config_t *config, uint8_t *uuid); + +#ifdef __cplusplus +} +#endif + +#endif /*! __FSL_FLASH_FFR_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_inputmux.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_inputmux.c new file mode 100644 index 000000000..b2f10a7c6 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_inputmux.c @@ -0,0 +1,121 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_inputmux.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.inputmux" +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * brief Initialize INPUTMUX peripheral. + + * This function enables the INPUTMUX clock. + * + * param base Base address of the INPUTMUX peripheral. + * + * retval None. + */ +void INPUTMUX_Init(INPUTMUX_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +#if defined(FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE) && FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE + CLOCK_EnableClock(kCLOCK_Sct); + CLOCK_EnableClock(kCLOCK_Dma); +#else + CLOCK_EnableClock(kCLOCK_InputMux); +#endif /* FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE */ +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Attaches a signal + * + * This function gates the INPUTPMUX clock. + * + * param base Base address of the INPUTMUX peripheral. + * param index Destination peripheral to attach the signal to. + * param connection Selects connection. + * + * retval None. + */ +void INPUTMUX_AttachSignal(INPUTMUX_Type *base, uint32_t index, inputmux_connection_t connection) +{ + uint32_t pmux_id; + uint32_t output_id; + + /* extract pmux to be used */ + pmux_id = ((uint32_t)(connection)) >> PMUX_SHIFT; + /* extract function number */ + output_id = ((uint32_t)(connection)) & 0xffffU; + /* programm signal */ + *(volatile uint32_t *)(((uint32_t)base) + pmux_id + (index * 4)) = output_id; +} + +#if defined(FSL_FEATURE_INPUTMUX_HAS_SIGNAL_ENA) +/*! + * brief Enable/disable a signal + * + * This function gates the INPUTPMUX clock. + * + * param base Base address of the INPUTMUX peripheral. + * param signal Enable signal register id and bit offset. + * param enable Selects enable or disable. + * + * retval None. + */ +void INPUTMUX_EnableSignal(INPUTMUX_Type *base, inputmux_signal_t signal, bool enable) +{ + uint32_t ena_id; + uint32_t bit_offset; + + /* extract enable register to be used */ + ena_id = ((uint32_t)(signal)) >> ENA_SHIFT; + /* extract enable bit offset */ + bit_offset = ((uint32_t)(signal)) & 0xfU; + /* set signal */ + if (enable) + { + *(volatile uint32_t *)(((uint32_t)base) + ena_id) |= (1U << bit_offset); + } + else + { + *(volatile uint32_t *)(((uint32_t)base) + ena_id) &= ~(1U << bit_offset); + } +} +#endif + +/*! + * brief Deinitialize INPUTMUX peripheral. + + * This function disables the INPUTMUX clock. + * + * param base Base address of the INPUTMUX peripheral. + * + * retval None. + */ +void INPUTMUX_Deinit(INPUTMUX_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +#if defined(FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE) && FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE + CLOCK_DisableClock(kCLOCK_Sct); + CLOCK_DisableClock(kCLOCK_Dma); +#else + CLOCK_DisableClock(kCLOCK_InputMux); +#endif /* FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE */ +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_inputmux.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_inputmux.h new file mode 100644 index 000000000..edf4ffa3c --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_inputmux.h @@ -0,0 +1,97 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_INPUTMUX_H_ +#define _FSL_INPUTMUX_H_ + +#include "fsl_inputmux_connections.h" +#include "fsl_common.h" + +/*! + * @addtogroup inputmux_driver + * @{ + */ + +/*! @file */ +/*! @file fsl_inputmux_connections.h */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief Group interrupt driver version for SDK */ +#define FSL_INPUTMUX_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */ + /*@}*/ + +/******************************************************************************* + * API + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * @brief Initialize INPUTMUX peripheral. + + * This function enables the INPUTMUX clock. + * + * @param base Base address of the INPUTMUX peripheral. + * + * @retval None. + */ +void INPUTMUX_Init(INPUTMUX_Type *base); + +/*! + * @brief Attaches a signal + * + * This function gates the INPUTPMUX clock. + * + * @param base Base address of the INPUTMUX peripheral. + * @param index Destination peripheral to attach the signal to. + * @param connection Selects connection. + * + * @retval None. + */ +void INPUTMUX_AttachSignal(INPUTMUX_Type *base, uint32_t index, inputmux_connection_t connection); + +#if defined(FSL_FEATURE_INPUTMUX_HAS_SIGNAL_ENA) +/*! + * @brief Enable/disable a signal + * + * This function gates the INPUTPMUX clock. + * + * @param base Base address of the INPUTMUX peripheral. + * @param signal Enable signal register id and bit offset. + * @param enable Selects enable or disable. + * + * @retval None. + */ +void INPUTMUX_EnableSignal(INPUTMUX_Type *base, inputmux_signal_t signal, bool enable); +#endif + +/*! + * @brief Deinitialize INPUTMUX peripheral. + + * This function disables the INPUTMUX clock. + * + * @param base Base address of the INPUTMUX peripheral. + * + * @retval None. + */ +void INPUTMUX_Deinit(INPUTMUX_Type *base); + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _FSL_INPUTMUX_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_inputmux_connections.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_inputmux_connections.h new file mode 100644 index 000000000..189ad093e --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_inputmux_connections.h @@ -0,0 +1,409 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016, NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_INPUTMUX_CONNECTIONS_ +#define _FSL_INPUTMUX_CONNECTIONS_ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.inputmux_connections" +#endif + +/*! + * @addtogroup inputmux_driver + * @{ + */ + +/*! + * @name Input multiplexing connections + * @{ + */ + +/*! @brief Periphinmux IDs */ +#define SCT0_INMUX0 0x00U +#define TIMER0CAPTSEL0 0x20U +#define TIMER1CAPTSEL0 0x40U +#define TIMER2CAPTSEL0 0x60U +#define PINTSEL0 0xC0U +#define DMA0_ITRIG_INMUX0 0xE0U +#define DMA0_OTRIG_INMUX0 0x160U +#define FREQMEAS_REF_REG 0x180U +#define FREQMEAS_TARGET_REG 0x184U +#define TIMER3CAPTSEL0 0x1A0U +#define TIMER4CAPTSEL0 0x1C0U +#define PINTSECSEL0 0x1E0U +#define DMA1_ITRIG_INMUX0 0x200U +#define DMA1_OTRIG_INMUX0 0x240U +#define PMUX_SHIFT 20U + +/*! @brief INPUTMUX connections type */ +typedef enum _inputmux_connection_t +{ + /*!< SCT0 INMUX. */ + kINPUTMUX_SctGpi0ToSct0 = 0U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_SctGpi1ToSct0 = 1U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_SctGpi2ToSct0 = 2U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_SctGpi3ToSct0 = 3U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_SctGpi4ToSct0 = 4U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_SctGpi5ToSct0 = 5U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_SctGpi6ToSct0 = 6U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_SctGpi7ToSct0 = 7U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer0M0ToSct0 = 8U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToSct0 = 9U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToSct0 = 10U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToSct0 = 11U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToSct0 = 12U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_AdcIrqToSct0 = 13U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_GpiointBmatchToSct0 = 14U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Usb0FrameToggleToSct0 = 15U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Usb1FrameToggleToSct0 = 16U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_CompOutToSct0 = 17U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_I2sSharedSck0ToSct0 = 18U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_I2sSharedSck1ToSct0 = 19U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_I2sSharedWs0ToSct0 = 20U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_I2sSharedWs1ToSct0 = 21U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_ArmTxevToSct0 = 22U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_DebugHaltedToSct0 = 23U + (SCT0_INMUX0 << PMUX_SHIFT), + + /*!< TIMER0 CAPTSEL. */ + kINPUTMUX_CtimerInp0ToTimer0Captsel = 0U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp1ToTimer0Captsel = 1U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp2ToTimer0Captsel = 2U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp3ToTimer0Captsel = 3U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp4ToTimer0Captsel = 4U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp5ToTimer0Captsel = 5U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp6ToTimer0Captsel = 6U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp7ToTimer0Captsel = 7U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp8ToTimer0Captsel = 8U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp9ToTimer0Captsel = 9U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp10ToTimer0Captsel = 10U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp11ToTimer0Captsel = 11U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp12ToTimer0Captsel = 12U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp13ToTimer0Captsel = 13U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp14ToTimer0Captsel = 14U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp15ToTimer0Captsel = 15U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp16ToTimer0Captsel = 16U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp17ToTimer0Captsel = 17U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp18ToTimer0Captsel = 18U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp19ToTimer0Captsel = 19U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Usb0FrameToggleToTimer0Captsel = 20U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Usb1FrameToggleToTimer0Captsel = 21U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CompOutToTimer0Captsel = 22U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_I2sSharedWs0ToTimer0Captsel = 23U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_I2sSharedWs1ToTimer0Captsel = 24U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + + /*!< TIMER1 CAPTSEL. */ + kINPUTMUX_CtimerInp0ToTimer1Captsel = 0U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp1ToTimer1Captsel = 1U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp2ToTimer1Captsel = 2U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp3ToTimer1Captsel = 3U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp4ToTimer1Captsel = 4U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp5ToTimer1Captsel = 5U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp6ToTimer1Captsel = 6U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp7ToTimer1Captsel = 7U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp8ToTimer1Captsel = 8U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp9ToTimer1Captsel = 9U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp10ToTimer1Captsel = 10U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp11ToTimer1Captsel = 11U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp12ToTimer1Captsel = 12U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp13ToTimer1Captsel = 13U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp14ToTimer1Captsel = 14U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp15ToTimer1Captsel = 15U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp16ToTimer1Captsel = 16U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp17ToTimer1Captsel = 17U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp18ToTimer1Captsel = 18U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp19ToTimer1Captsel = 19U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Usb0FrameToggleToTimer1Captsel = 20U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Usb1FrameToggleToTimer1Captsel = 21U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CompOutToTimer1Captsel = 22U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_I2sSharedWs0ToTimer1Captsel = 23U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_I2sSharedWs1ToTimer1Captsel = 24U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + + /*!< TIMER2 CAPTSEL. */ + kINPUTMUX_CtimerInp0ToTimer2Captsel = 0U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp1ToTimer2Captsel = 1U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp2ToTimer2Captsel = 2U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp3ToTimer2Captsel = 3U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp4ToTimer2Captsel = 4U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp5ToTimer2Captsel = 5U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp6ToTimer2Captsel = 6U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp7ToTimer2Captsel = 7U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp8ToTimer2Captsel = 8U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp9ToTimer2Captsel = 9U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp10ToTimer2Captsel = 10U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp11ToTimer2Captsel = 11U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp12ToTimer2Captsel = 12U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp13ToTimer2Captsel = 13U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp14ToTimer2Captsel = 14U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp15ToTimer2Captsel = 15U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp16ToTimer2Captsel = 16U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp17ToTimer2Captsel = 17U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp18ToTimer2Captsel = 18U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp19ToTimer2Captsel = 19U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Usb0FrameToggleToTimer2Captsel = 20U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Usb1FrameToggleToTimer2Captsel = 21U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CompOutToTimer2Captsel = 22U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_I2sSharedWs0ToTimer2Captsel = 23U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_I2sSharedWs1ToTimer2Captsel = 24U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + + /*!< Pin interrupt select. */ + kINPUTMUX_GpioPort0Pin0ToPintsel = 0U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin1ToPintsel = 1U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin2ToPintsel = 2U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin3ToPintsel = 3U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin4ToPintsel = 4U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin5ToPintsel = 5U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin6ToPintsel = 6U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin7ToPintsel = 7U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin8ToPintsel = 8U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin9ToPintsel = 9U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin10ToPintsel = 10U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin11ToPintsel = 11U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin12ToPintsel = 12U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin13ToPintsel = 13U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin14ToPintsel = 14U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin15ToPintsel = 15U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin16ToPintsel = 16U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin17ToPintsel = 17U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin18ToPintsel = 18U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin19ToPintsel = 19U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin20ToPintsel = 20U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin21ToPintsel = 21U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin22ToPintsel = 22U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin23ToPintsel = 23U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin24ToPintsel = 24U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin25ToPintsel = 25U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin26ToPintsel = 26U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin27ToPintsel = 27U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin28ToPintsel = 28U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin29ToPintsel = 29U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin30ToPintsel = 30U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin31ToPintsel = 31U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin0ToPintsel = 32U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin1ToPintsel = 33U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin2ToPintsel = 34U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin3ToPintsel = 35U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin4ToPintsel = 36U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin5ToPintsel = 37U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin6ToPintsel = 38U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin7ToPintsel = 39U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin8ToPintsel = 40U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin9ToPintsel = 41U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin10ToPintsel = 42U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin11ToPintsel = 43U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin12ToPintsel = 44U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin13ToPintsel = 45U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin14ToPintsel = 46U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin15ToPintsel = 47U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin16ToPintsel = 48U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin17ToPintsel = 49U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin18ToPintsel = 50U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin19ToPintsel = 51U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin20ToPintsel = 52U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin21ToPintsel = 53U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin22ToPintsel = 54U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin23ToPintsel = 55U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin24ToPintsel = 56U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin25ToPintsel = 57U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin26ToPintsel = 58U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin27ToPintsel = 59U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin28ToPintsel = 60U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin29ToPintsel = 61U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin30ToPintsel = 62U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin31ToPintsel = 63U + (PINTSEL0 << PMUX_SHIFT), + + /*!< DMA0 Input trigger. */ + kINPUTMUX_PinInt0ToDma0 = 0U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_PinInt1ToDma0 = 1U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_PinInt2ToDma0 = 2U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_PinInt3ToDma0 = 3U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer0M0ToDma0 = 4U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToDma0 = 5U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToDma0 = 6U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToDma0 = 7U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToDma0 = 8U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToDma0 = 9U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToDma0 = 10U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer3M1ToDma0 = 11U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToDma0 = 12U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToDma0 = 13U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_CompOutToDma0 = 14U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Otrig0ToDma0 = 15U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Otrig1ToDma0 = 16U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Otrig2ToDma0 = 17U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Otrig3ToDma0 = 18U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Sct0DmaReq0ToDma0 = 19U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Sct0DmaReq1ToDma0 = 20U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_HashDmaRxToDma0 = 21U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + + /*!< DMA0 output trigger. */ + kINPUTMUX_Dma0Hash0TxTrigoutToTriginChannels = 0U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0HsLspiRxTrigoutToTriginChannels = 2U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0HsLspiTxTrigoutToTriginChannels = 3U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0Flexcomm0RxTrigoutToTriginChannels = 4U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0Flexcomm0TxTrigoutToTriginChannels = 5U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0Flexcomm1RxTrigoutToTriginChannels = 6U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0Flexcomm1TxTrigoutToTriginChannels = 7U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0Flexcomm3RxTrigoutToTriginChannels = 8U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0Flexcomm3TxTrigoutToTriginChannels = 9U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0Flexcomm2RxTrigoutToTriginChannels = 10U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0Flexcomm2TxTrigoutToTriginChannels = 11U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0Flexcomm4RxTrigoutToTriginChannels = 12U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0Flexcomm4TxTrigoutToTriginChannels = 13U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0Flexcomm5RxTrigoutToTriginChannels = 14U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0Flexcomm5TxTrigoutToTriginChannels = 15U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0Flexcomm6RxTrigoutToTriginChannels = 16U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0Flexcomm6TxTrigoutToTriginChannels = 17U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0Flexcomm7RxTrigoutToTriginChannels = 18U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0Flexcomm7TxTrigoutToTriginChannels = 19U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0Adc0Ch0TrigoutToTriginChannels = 21U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0Adc0Ch1TrigoutToTriginChannels = 22U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + + /*!< Selection for frequency measurement reference clock. */ + kINPUTMUX_ExternOscToFreqmeasRef = 0U + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_Fro12MhzToFreqmeasRef = 1u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_Fro96MhzToFreqmeasRef = 2u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_WdtOscToFreqmeasRef = 3u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_32KhzOscToFreqmeasRef= 4u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_MainClkToFreqmeasRef = 5u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_FreqmeGpioClk_aRef = 6u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_FreqmeGpioClk_bRef = 7u + (FREQMEAS_REF_REG << PMUX_SHIFT), + + /*!< Selection for frequency measurement target clock. */ + kINPUTMUX_ExternOscToFreqmeasTarget = 0U + (FREQMEAS_TARGET_REG << PMUX_SHIFT), + kINPUTMUX_Fro12MhzToFreqmeasTarget = 1u + (FREQMEAS_TARGET_REG << PMUX_SHIFT), + kINPUTMUX_Fro96MhzToFreqmeasTarget = 2u + (FREQMEAS_TARGET_REG << PMUX_SHIFT), + kINPUTMUX_WdtOscToFreqmeasTarget = 3u + (FREQMEAS_TARGET_REG << PMUX_SHIFT), + kINPUTMUX_32KhzOscToFreqmeasTarget= 4u + (FREQMEAS_TARGET_REG << PMUX_SHIFT), + kINPUTMUX_MainClkToFreqmeasTarget = 5u + (FREQMEAS_TARGET_REG << PMUX_SHIFT), + kINPUTMUX_FreqmeGpioClk_aTarget = 6u + (FREQMEAS_TARGET_REG << PMUX_SHIFT), + kINPUTMUX_FreqmeGpioClk_bTarget = 7u + (FREQMEAS_TARGET_REG << PMUX_SHIFT), + + /*!< TIMER3 CAPTSEL. */ + kINPUTMUX_CtimerInp0ToTimer3Captsel = 0U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp1ToTimer3Captsel = 1U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp2ToTimer3Captsel = 2U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp3ToTimer3Captsel = 3U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp4ToTimer3Captsel = 4U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp5ToTimer3Captsel = 5U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp6ToTimer3Captsel = 6U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp7ToTimer3Captsel = 7U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp8ToTimer3Captsel = 8U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp9ToTimer3Captsel = 9U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp10ToTimer3Captsel = 10U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp11ToTimer3Captsel = 11U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp12ToTimer3Captsel = 12U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp13ToTimer3Captsel = 13U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp14ToTimer3Captsel = 14U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp15ToTimer3Captsel = 15U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp16ToTimer3Captsel = 16U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp17ToTimer3Captsel = 17U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp18ToTimer3Captsel = 18U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp19ToTimer3Captsel = 19U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Usb0FrameToggleToTimer3Captsel = 20U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Usb1FrameToggleToTimer3Captsel = 21U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CompOutToTimer3Captsel = 22U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_I2sSharedWs0ToTimer3Captsel = 23U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_I2sSharedWs1ToTimer3Captsel = 24U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + + /*!< Timer4 CAPTSEL. */ + kINPUTMUX_CtimerInp0ToTimer4Captsel = 0U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp1ToTimer4Captsel = 1U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp2ToTimer4Captsel = 2U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp3ToTimer4Captsel = 3U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp4ToTimer4Captsel = 4U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp5ToTimer4Captsel = 5U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp6ToTimer4Captsel = 6U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp7ToTimer4Captsel = 7U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp8ToTimer4Captsel = 8U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp9ToTimer4Captsel = 9U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp10ToTimer4Captsel = 10U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp11ToTimer4Captsel = 11U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp12ToTimer4Captsel = 12U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp13ToTimer4Captsel = 13U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp14ToTimer4Captsel = 14U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp15ToTimer4Captsel = 15U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp16ToTimer4Captsel = 16U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp17ToTimer4Captsel = 17U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp18ToTimer4Captsel = 18U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp19ToTimer4Captsel = 19U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Usb0FrameToggleToTimer4Captsel = 20U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Usb1FrameToggleToTimer4Captsel = 21U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CompOutToTimer4Captsel = 22U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_I2sSharedWs0ToTimer4Captsel = 23U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_I2sSharedWs1ToTimer4Captsel = 24U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + + /*Pin interrupt secure select */ + kINPUTMUX_GpioPort0Pin0ToPintSecsel = 0U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin1ToPintSecsel = 1U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin2ToPintSecsel = 2U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin3ToPintSecsel = 3U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin4ToPintSecsel = 4U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin5ToPintSecsel = 5U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin6ToPintSecsel = 6U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin7ToPintSecsel = 7U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin8ToPintSecsel = 8U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin9ToPintSecsel = 9U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin10ToPintSecsel = 10U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin11ToPintSecsel = 11U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin12ToPintSecsel = 12U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin13ToPintSecsel = 13U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin14ToPintSecsel = 14U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin15ToPintSecsel = 15U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin16ToPintSecsel = 16U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin17ToPintSecsel = 17U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin18ToPintSecsel = 18U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin19ToPintSecsel = 19U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin20ToPintSecsel = 20U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin21ToPintSecsel = 21U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin22ToPintSecsel = 22U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin23ToPintSecsel = 23U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin24ToPintSecsel = 24U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin25ToPintSecsel = 25U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin26ToPintSecsel = 26U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin27ToPintSecsel = 27U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin28ToPintSecsel = 28U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin29ToPintSecsel = 29U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin30ToPintSecsel = 30U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin31ToPintSecsel = 31U + (PINTSECSEL0 << PMUX_SHIFT), + + /*!< DMA1 Input trigger. */ + kINPUTMUX_PinInt0ToDma1 = 0U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_PinInt1ToDma1 = 1U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_PinInt2ToDma1 = 2U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_PinInt3ToDma1 = 3U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer0M0ToDma1 = 4U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToDma1 = 5U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToDma1 = 6U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToDma1 = 7U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Otrig0ToDma1 = 8U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Otrig1ToDma1 = 9U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Otrig2ToDma1 = 10U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Otrig3ToDma1 = 11U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Sct0DmaReq0ToDma1 = 12U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Sct0DmaReq1ToDma1 = 13U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_HashDmaRxToDma1 = 14U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), + + /*!< DMA1 output trigger. */ + kINPUTMUX_Dma1Hash0TxTrigoutToTriginChannels = 0U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma1HsLspiRxTrigoutToTriginChannels = 2U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma1HsLspiTxTrigoutToTriginChannels = 3U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma1Flexcomm0RxTrigoutToTriginChannels = 4U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma1Flexcomm0TxTrigoutToTriginChannels = 5U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma1Flexcomm1RxTrigoutToTriginChannels = 6U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma1Flexcomm1TxTrigoutToTriginChannels = 7U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma1Flexcomm2RxTrigoutToTriginChannels = 8U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma1Flexcomm2TxTrigoutToTriginChannels = 9U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), +} inputmux_connection_t; + +/*@}*/ + +#endif /* _FSL_INPUTMUX_CONNECTIONS_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_iocon.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_iocon.h new file mode 100644 index 000000000..25cd4e9b2 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_iocon.h @@ -0,0 +1,288 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_IOCON_H_ +#define _FSL_IOCON_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup lpc_iocon + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpc_iocon" +#endif + +/*! @name Driver version */ +/*@{*/ +/*! @brief IOCON driver version 2.1.1. */ +#define FSL_IOCON_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) +/*@}*/ + +/** + * @brief Array of IOCON pin definitions passed to IOCON_SetPinMuxing() must be in this format + */ +typedef struct _iocon_group +{ + uint32_t port : 8; /* Pin port */ + uint32_t pin : 8; /* Pin number */ + uint32_t ionumber : 8; /* IO number */ + uint32_t modefunc : 16; /* Function and mode */ +} iocon_group_t; + +/** + * @brief IOCON function and mode selection definitions + * @note See the User Manual for specific modes and functions supported by the various pins. + */ +#if defined(FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH) && (FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH == 4) +#define IOCON_FUNC0 0x0 /*!< Selects pin function 0 */ +#define IOCON_FUNC1 0x1 /*!< Selects pin function 1 */ +#define IOCON_FUNC2 0x2 /*!< Selects pin function 2 */ +#define IOCON_FUNC3 0x3 /*!< Selects pin function 3 */ +#define IOCON_FUNC4 0x4 /*!< Selects pin function 4 */ +#define IOCON_FUNC5 0x5 /*!< Selects pin function 5 */ +#define IOCON_FUNC6 0x6 /*!< Selects pin function 6 */ +#define IOCON_FUNC7 0x7 /*!< Selects pin function 7 */ +#define IOCON_FUNC8 0x8 /*!< Selects pin function 8 */ +#define IOCON_FUNC9 0x9 /*!< Selects pin function 9 */ +#define IOCON_FUNC10 0xA /*!< Selects pin function 10 */ +#define IOCON_FUNC11 0xB /*!< Selects pin function 11 */ +#define IOCON_FUNC12 0xC /*!< Selects pin function 12 */ +#define IOCON_FUNC13 0xD /*!< Selects pin function 13 */ +#define IOCON_FUNC14 0xE /*!< Selects pin function 14 */ +#define IOCON_FUNC15 0xF /*!< Selects pin function 15 */ +#if defined(IOCON_PIO_MODE_SHIFT) +#define IOCON_MODE_INACT (0x0 << IOCON_PIO_MODE_SHIFT) /*!< No addition pin function */ +#define IOCON_MODE_PULLDOWN (0x1 << IOCON_PIO_MODE_SHIFT) /*!< Selects pull-down function */ +#define IOCON_MODE_PULLUP (0x2 << IOCON_PIO_MODE_SHIFT) /*!< Selects pull-up function */ +#define IOCON_MODE_REPEATER (0x3 << IOCON_PIO_MODE_SHIFT) /*!< Selects pin repeater function */ +#endif + +#if defined(IOCON_PIO_I2CSLEW_SHIFT) +#define IOCON_GPIO_MODE (0x1 << IOCON_PIO_I2CSLEW_SHIFT) /*!< GPIO Mode */ +#define IOCON_I2C_SLEW (0x0 << IOCON_PIO_I2CSLEW_SHIFT) /*!< I2C Slew Rate Control */ +#endif + +#if defined(IOCON_PIO_EGP_SHIFT) +#define IOCON_GPIO_MODE (0x1 << IOCON_PIO_EGP_SHIFT) /*!< GPIO Mode */ +#define IOCON_I2C_SLEW (0x0 << IOCON_PIO_EGP_SHIFT) /*!< I2C Slew Rate Control */ +#endif + +#if defined(IOCON_PIO_SLEW_SHIFT) +#define IOCON_SLEW_STANDARD (0x0 << IOCON_PIO_SLEW_SHIFT) /*!< Driver Slew Rate Control */ +#define IOCON_SLEW_FAST (0x1 << IOCON_PIO_SLEW_SHIFT) /*!< Driver Slew Rate Control */ +#endif + +#if defined(IOCON_PIO_INVERT_SHIFT) +#define IOCON_INV_EN (0x1 << IOCON_PIO_INVERT_SHIFT) /*!< Enables invert function on input */ +#endif + +#if defined(IOCON_PIO_DIGIMODE_SHIFT) +#define IOCON_ANALOG_EN (0x0 << IOCON_PIO_DIGIMODE_SHIFT) /*!< Enables analog function by setting 0 to bit 7 */ +#define IOCON_DIGITAL_EN \ + (0x1 << IOCON_PIO_DIGIMODE_SHIFT) /*!< Enables digital function by setting 1 to bit 7(default) */ +#endif + +#if defined(IOCON_PIO_FILTEROFF_SHIFT) +#define IOCON_INPFILT_OFF (0x1 << IOCON_PIO_FILTEROFF_SHIFT) /*!< Input filter Off for GPIO pins */ +#define IOCON_INPFILT_ON (0x0 << IOCON_PIO_FILTEROFF_SHIFT) /*!< Input filter On for GPIO pins */ +#endif + +#if defined(IOCON_PIO_I2CDRIVE_SHIFT) +#define IOCON_I2C_LOWDRIVER (0x0 << IOCON_PIO_I2CDRIVE_SHIFT) /*!< Low drive, Output drive sink is 4 mA */ +#define IOCON_I2C_HIGHDRIVER (0x1 << IOCON_PIO_I2CDRIVE_SHIFT) /*!< High drive, Output drive sink is 20 mA */ +#endif + +#if defined(IOCON_PIO_OD_SHIFT) +#define IOCON_OPENDRAIN_EN (0x1 << IOCON_PIO_OD_SHIFT) /*!< Enables open-drain function */ +#endif + +#if defined(IOCON_PIO_I2CFILTER_SHIFT) +#define IOCON_I2CFILTER_OFF (0x1 << IOCON_PIO_I2CFILTER_SHIFT) /*!< I2C 50 ns glitch filter enabled */ +#define IOCON_I2CFILTER_ON (0x0 << IOCON_PIO_I2CFILTER_SHIFT) /*!< I2C 50 ns glitch filter not enabled, */ +#endif + +#if defined(IOCON_PIO_ASW_SHIFT) +#define IOCON_AWS_EN (0x1 << IOCON_PIO_ASW_SHIFT) /*!< Enables analog switch function */ +#endif + +#if defined(IOCON_PIO_SSEL_SHIFT) +#define IOCON_SSEL_3V3 (0x0 << IOCON_PIO_SSEL_SHIFT) /*!< 3V3 signaling in I2C mode */ +#define IOCON_SSEL_1V8 (0x1 << IOCON_PIO_SSEL_SHIFT) /*!< 1V8 signaling in I2C mode */ +#endif + +#if defined(IOCON_PIO_ECS_SHIFT) +#define IOCON_ECS_OFF (0x0 << IOCON_PIO_ECS_SHIFT) /*!< IO is an open drain cell */ +#define IOCON_ECS_ON (0x1 << IOCON_PIO_ECS_SHIFT) /*!< Pull-up resistor is connected */ +#endif + +#if defined(IOCON_PIO_S_MODE_SHIFT) +#define IOCON_S_MODE_0CLK (0x0 << IOCON_PIO_S_MODE_SHIFT) /*!< Bypass input filter */ +#define IOCON_S_MODE_1CLK \ + (0x1 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 1 filter clock are rejected \ \ \ \ \ + */ +#define IOCON_S_MODE_2CLK \ + (0x2 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 2 filter clock2 are rejected \ \ \ \ \ + */ +#define IOCON_S_MODE_3CLK \ + (0x3 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 3 filter clock2 are rejected \ \ \ \ \ + */ +#define IOCON_S_MODE(clks) ((clks) << IOCON_PIO_S_MODE_SHIFT) /*!< Select clocks for digital input filter mode */ +#endif + +#if defined(IOCON_PIO_CLK_DIV_SHIFT) +#define IOCON_CLKDIV(div) \ + ((div) \ + << IOCON_PIO_CLK_DIV_SHIFT) /*!< Select peripheral clock divider for input filter sampling clock, 2^n, n=0-6 */ +#endif + +#else +#define IOCON_FUNC0 0x0 /*!< Selects pin function 0 */ +#define IOCON_FUNC1 0x1 /*!< Selects pin function 1 */ +#define IOCON_FUNC2 0x2 /*!< Selects pin function 2 */ +#define IOCON_FUNC3 0x3 /*!< Selects pin function 3 */ +#define IOCON_FUNC4 0x4 /*!< Selects pin function 4 */ +#define IOCON_FUNC5 0x5 /*!< Selects pin function 5 */ +#define IOCON_FUNC6 0x6 /*!< Selects pin function 6 */ +#define IOCON_FUNC7 0x7 /*!< Selects pin function 7 */ + +#if defined(IOCON_PIO_MODE_SHIFT) +#define IOCON_MODE_INACT (0x0 << IOCON_PIO_MODE_SHIFT) /*!< No addition pin function */ +#define IOCON_MODE_PULLDOWN (0x1 << IOCON_PIO_MODE_SHIFT) /*!< Selects pull-down function */ +#define IOCON_MODE_PULLUP (0x2 << IOCON_PIO_MODE_SHIFT) /*!< Selects pull-up function */ +#define IOCON_MODE_REPEATER (0x3 << IOCON_PIO_MODE_SHIFT) /*!< Selects pin repeater function */ +#endif + +#if defined(IOCON_PIO_I2CSLEW_SHIFT) +#define IOCON_GPIO_MODE (0x1 << IOCON_PIO_I2CSLEW_SHIFT) /*!< GPIO Mode */ +#define IOCON_I2C_SLEW (0x0 << IOCON_PIO_I2CSLEW_SHIFT) /*!< I2C Slew Rate Control */ +#endif + +#if defined(IOCON_PIO_EGP_SHIFT) +#define IOCON_GPIO_MODE (0x1 << IOCON_PIO_EGP_SHIFT) /*!< GPIO Mode */ +#define IOCON_I2C_SLEW (0x0 << IOCON_PIO_EGP_SHIFT) /*!< I2C Slew Rate Control */ +#endif + +#if defined(IOCON_PIO_INVERT_SHIFT) +#define IOCON_INV_EN (0x1 << IOCON_PIO_INVERT_SHIFT) /*!< Enables invert function on input */ +#endif + +#if defined(IOCON_PIO_DIGIMODE_SHIFT) +#define IOCON_ANALOG_EN (0x0 << IOCON_PIO_DIGIMODE_SHIFT) /*!< Enables analog function by setting 0 to bit 7 */ +#define IOCON_DIGITAL_EN \ + (0x1 << IOCON_PIO_DIGIMODE_SHIFT) /*!< Enables digital function by setting 1 to bit 7(default) */ +#endif + +#if defined(IOCON_PIO_FILTEROFF_SHIFT) +#define IOCON_INPFILT_OFF (0x1 << IOCON_PIO_FILTEROFF_SHIFT) /*!< Input filter Off for GPIO pins */ +#define IOCON_INPFILT_ON (0x0 << IOCON_PIO_FILTEROFF_SHIFT) /*!< Input filter On for GPIO pins */ +#endif + +#if defined(IOCON_PIO_I2CDRIVE_SHIFT) +#define IOCON_I2C_LOWDRIVER (0x0 << IOCON_PIO_I2CDRIVE_SHIFT) /*!< Low drive, Output drive sink is 4 mA */ +#define IOCON_I2C_HIGHDRIVER (0x1 << IOCON_PIO_I2CDRIVE_SHIFT) /*!< High drive, Output drive sink is 20 mA */ +#endif + +#if defined(IOCON_PIO_OD_SHIFT) +#define IOCON_OPENDRAIN_EN (0x1 << IOCON_PIO_OD_SHIFT) /*!< Enables open-drain function */ +#endif + +#if defined(IOCON_PIO_I2CFILTER_SHIFT) +#define IOCON_I2CFILTER_OFF (0x1 << IOCON_PIO_I2CFILTER_SHIFT) /*!< I2C 50 ns glitch filter enabled */ +#define IOCON_I2CFILTER_ON (0x0 << IOCON_PIO_I2CFILTER_SHIFT) /*!< I2C 50 ns glitch filter not enabled */ +#endif + +#if defined(IOCON_PIO_S_MODE_SHIFT) +#define IOCON_S_MODE_0CLK (0x0 << IOCON_PIO_S_MODE_SHIFT) /*!< Bypass input filter */ +#define IOCON_S_MODE_1CLK \ + (0x1 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 1 filter clock are rejected \ \ \ \ \ + */ +#define IOCON_S_MODE_2CLK \ + (0x2 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 2 filter clock2 are rejected \ \ \ \ \ + */ +#define IOCON_S_MODE_3CLK \ + (0x3 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 3 filter clock2 are rejected \ \ \ \ \ + */ +#define IOCON_S_MODE(clks) ((clks) << IOCON_PIO_S_MODE_SHIFT) /*!< Select clocks for digital input filter mode */ +#endif + +#if defined(IOCON_PIO_CLK_DIV_SHIFT) +#define IOCON_CLKDIV(div) \ + ((div) \ + << IOCON_PIO_CLK_DIV_SHIFT) /*!< Select peripheral clock divider for input filter sampling clock, 2^n, n=0-6 */ +#endif + +#endif +#if defined(__cplusplus) +extern "C" { +#endif + +#if (defined(FSL_FEATURE_IOCON_ONE_DIMENSION) && (FSL_FEATURE_IOCON_ONE_DIMENSION == 1)) +/** + * @brief Sets I/O Control pin mux + * @param base : The base of IOCON peripheral on the chip + * @param ionumber : GPIO number to mux + * @param modefunc : OR'ed values of type IOCON_* + * @return Nothing + */ +__STATIC_INLINE void IOCON_PinMuxSet(IOCON_Type *base, uint8_t ionumber, uint32_t modefunc) +{ + base->PIO[ionumber] = modefunc; +} +#else +/** + * @brief Sets I/O Control pin mux + * @param base : The base of IOCON peripheral on the chip + * @param port : GPIO port to mux + * @param pin : GPIO pin to mux + * @param modefunc : OR'ed values of type IOCON_* + * @return Nothing + */ +__STATIC_INLINE void IOCON_PinMuxSet(IOCON_Type *base, uint8_t port, uint8_t pin, uint32_t modefunc) +{ + base->PIO[port][pin] = modefunc; +} +#endif + +/** + * @brief Set all I/O Control pin muxing + * @param base : The base of IOCON peripheral on the chip + * @param pinArray : Pointer to array of pin mux selections + * @param arrayLength : Number of entries in pinArray + * @return Nothing + */ +__STATIC_INLINE void IOCON_SetPinMuxing(IOCON_Type *base, const iocon_group_t *pinArray, uint32_t arrayLength) +{ + uint32_t i; + + for (i = 0; i < arrayLength; i++) + { +#if (defined(FSL_FEATURE_IOCON_ONE_DIMENSION) && (FSL_FEATURE_IOCON_ONE_DIMENSION == 1)) + IOCON_PinMuxSet(base, pinArray[i].ionumber, pinArray[i].modefunc); +#else + IOCON_PinMuxSet(base, pinArray[i].port, pinArray[i].pin, pinArray[i].modefunc); +#endif /* FSL_FEATURE_IOCON_ONE_DIMENSION */ + } +} + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +#endif /* _FSL_IOCON_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_lpadc.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_lpadc.c new file mode 100644 index 000000000..8bfe10565 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_lpadc.c @@ -0,0 +1,609 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_lpadc.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpadc" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Get instance number for LPADC module. + * + * @param base LPADC peripheral base address + */ +static uint32_t LPADC_GetInstance(ADC_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to LPADC bases for each instance. */ +static ADC_Type *const s_lpadcBases[] = ADC_BASE_PTRS; +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to LPADC clocks for each instance. */ +static const clock_ip_name_t s_lpadcClocks[] = LPADC_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t LPADC_GetInstance(ADC_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_lpadcBases); instance++) + { + if (s_lpadcBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_lpadcBases)); + + return instance; +} + +/*! + * brief Initializes the LPADC module. + * + * param base LPADC peripheral base address. + * param config Pointer to configuration structure. See "lpadc_config_t". + */ +void LPADC_Init(ADC_Type *base, const lpadc_config_t *config) +{ + /* Check if the pointer is available. */ + assert(config != NULL); + + uint32_t tmp32 = 0U; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock for LPADC instance. */ + CLOCK_EnableClock(s_lpadcClocks[LPADC_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Reset the module. */ + LPADC_DoResetConfig(base); +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) + LPADC_DoResetFIFO0(base); + LPADC_DoResetFIFO1(base); +#else + LPADC_DoResetFIFO(base); +#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ + + /* Disable the module before setting configuration. */ + LPADC_Enable(base, false); + + /* Configure the module generally. */ + if (config->enableInDozeMode) + { + base->CTRL &= ~ADC_CTRL_DOZEN_MASK; + } + else + { + base->CTRL |= ADC_CTRL_DOZEN_MASK; + } + +#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS + /* Set calibration average mode. */ + base->CTRL |= ADC_CTRL_CAL_AVGS(config->conversionAverageMode); +#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS */ + +/* ADCx_CFG. */ +#if defined(FSL_FEATURE_LPADC_HAS_CFG_ADCKEN) && FSL_FEATURE_LPADC_HAS_CFG_ADCKEN + if (config->enableInternalClock) + { + tmp32 |= ADC_CFG_ADCKEN_MASK; + } +#endif /* FSL_FEATURE_LPADC_HAS_CFG_ADCKEN */ +#if defined(FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG) && FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG + if (config->enableVref1LowVoltage) + { + tmp32 |= ADC_CFG_VREF1RNG_MASK; + } +#endif /* FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG */ + if (config->enableAnalogPreliminary) + { + tmp32 |= ADC_CFG_PWREN_MASK; + } + tmp32 |= ADC_CFG_PUDLY(config->powerUpDelay) /* Power up delay. */ + | ADC_CFG_REFSEL(config->referenceVoltageSource) /* Reference voltage. */ + | ADC_CFG_PWRSEL(config->powerLevelMode) /* Power configuration. */ + | ADC_CFG_TPRICTRL(config->triggerPrioirtyPolicy); /* Trigger priority policy. */ + base->CFG = tmp32; + + /* ADCx_PAUSE. */ + if (config->enableConvPause) + { + base->PAUSE = ADC_PAUSE_PAUSEEN_MASK | ADC_PAUSE_PAUSEDLY(config->convPauseDelay); + } + else + { + base->PAUSE = 0U; + } + +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) + /* ADCx_FCTRL0. */ + base->FCTRL[0] = ADC_FCTRL_FWMARK(config->FIFO0Watermark); + /* ADCx_FCTRL1. */ + base->FCTRL[1] = ADC_FCTRL_FWMARK(config->FIFO1Watermark); +#else + /* ADCx_FCTRL. */ + base->FCTRL = ADC_FCTRL_FWMARK(config->FIFOWatermark); +#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ + + /* Enable the module after setting configuration. */ + LPADC_Enable(base, true); +} + +/*! + * brief Gets an available pre-defined settings for initial configuration. + * + * This function initializes the converter configuration structure with an available settings. The default values are: + * code + * config->enableInDozeMode = true; + * config->conversionAverageMode = kLPADC_ConversionAverage1; + * config->enableAnalogPreliminary = false; + * config->powerUpDelay = 0x80; + * config->referenceVoltageSource = kLPADC_ReferenceVoltageAlt1; + * config->powerLevelMode = kLPADC_PowerLevelAlt1; + * config->triggerPrioirtyPolicy = kLPADC_TriggerPriorityPreemptImmediately; + * config->enableConvPause = false; + * config->convPauseDelay = 0U; + * config->FIFO0Watermark = 0U; + * config->FIFO1Watermark = 0U; + * config->FIFOWatermark = 0U; + * endcode + * param config Pointer to configuration structure. + */ +void LPADC_GetDefaultConfig(lpadc_config_t *config) +{ + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + +#if defined(FSL_FEATURE_LPADC_HAS_CFG_ADCKEN) && FSL_FEATURE_LPADC_HAS_CFG_ADCKEN + config->enableInternalClock = false; +#endif /* FSL_FEATURE_LPADC_HAS_CFG_ADCKEN */ +#if defined(FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG) && FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG + config->enableVref1LowVoltage = false; +#endif /* FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG */ + config->enableInDozeMode = true; +#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS + /* Set calibration average mode. */ + config->conversionAverageMode = kLPADC_ConversionAverage1; +#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS */ + config->enableAnalogPreliminary = false; + config->powerUpDelay = 0x80; + config->referenceVoltageSource = kLPADC_ReferenceVoltageAlt1; + config->powerLevelMode = kLPADC_PowerLevelAlt1; + config->triggerPrioirtyPolicy = kLPADC_TriggerPriorityPreemptImmediately; + config->enableConvPause = false; + config->convPauseDelay = 0U; +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) + config->FIFO0Watermark = 0U; + config->FIFO1Watermark = 0U; +#else + config->FIFOWatermark = 0U; +#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ +} + +/*! + * brief De-initializes the LPADC module. + * + * param base LPADC peripheral base address. + */ +void LPADC_Deinit(ADC_Type *base) +{ + /* Disable the module. */ + LPADC_Enable(base, false); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Gate the clock. */ + CLOCK_DisableClock(s_lpadcClocks[LPADC_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) +/*! + * brief Get the result in conversion FIFOn. + * + * param base LPADC peripheral base address. + * param result Pointer to structure variable that keeps the conversion result in conversion FIFOn. + * param index Result FIFO index. + * + * return Status whether FIFOn entry is valid. + */ +bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result, uint8_t index) +{ + assert(result != NULL); /* Check if the input pointer is available. */ + + uint32_t tmp32; + + tmp32 = base->RESFIFO[index]; + + if (0U == (ADC_RESFIFO_VALID_MASK & tmp32)) + { + return false; /* FIFO is empty. Discard any read from RESFIFO. */ + } + + result->commandIdSource = (tmp32 & ADC_RESFIFO_CMDSRC_MASK) >> ADC_RESFIFO_CMDSRC_SHIFT; + result->loopCountIndex = (tmp32 & ADC_RESFIFO_LOOPCNT_MASK) >> ADC_RESFIFO_LOOPCNT_SHIFT; + result->triggerIdSource = (tmp32 & ADC_RESFIFO_TSRC_MASK) >> ADC_RESFIFO_TSRC_SHIFT; + result->convValue = (uint16_t)(tmp32 & ADC_RESFIFO_D_MASK); + + return true; +} +#else +/*! + * brief Get the result in conversion FIFO. + * + * param base LPADC peripheral base address. + * param result Pointer to structure variable that keeps the conversion result in conversion FIFO. + * + * return Status whether FIFO entry is valid. + */ +bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result) +{ + assert(result != NULL); /* Check if the input pointer is available. */ + + uint32_t tmp32; + + tmp32 = base->RESFIFO; + + if (0U == (ADC_RESFIFO_VALID_MASK & tmp32)) + { + return false; /* FIFO is empty. Discard any read from RESFIFO. */ + } + + result->commandIdSource = (tmp32 & ADC_RESFIFO_CMDSRC_MASK) >> ADC_RESFIFO_CMDSRC_SHIFT; + result->loopCountIndex = (tmp32 & ADC_RESFIFO_LOOPCNT_MASK) >> ADC_RESFIFO_LOOPCNT_SHIFT; + result->triggerIdSource = (tmp32 & ADC_RESFIFO_TSRC_MASK) >> ADC_RESFIFO_TSRC_SHIFT; + result->convValue = (uint16_t)(tmp32 & ADC_RESFIFO_D_MASK); + + return true; +} +#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ + +/*! + * brief Configure the conversion trigger source. + * + * Each programmable trigger can launch the conversion command in command buffer. + * + * param base LPADC peripheral base address. + * param triggerId ID for each trigger. Typically, the available value range is from 0. + * param config Pointer to configuration structure. See to #lpadc_conv_trigger_config_t. + */ +void LPADC_SetConvTriggerConfig(ADC_Type *base, uint32_t triggerId, const lpadc_conv_trigger_config_t *config) +{ + assert(triggerId < ADC_TCTRL_COUNT); /* Check if the triggerId is available in this device. */ + assert(config != NULL); /* Check if the input pointer is available. */ + + uint32_t tmp32; + + tmp32 = ADC_TCTRL_TCMD(config->targetCommandId) /* Trigger command select. */ + | ADC_TCTRL_TDLY(config->delayPower) /* Trigger delay select. */ + | ADC_TCTRL_TPRI(config->priority) /* Trigger priority setting. */ +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) + | ADC_TCTRL_FIFO_SEL_A(config->channelAFIFOSelect) | ADC_TCTRL_FIFO_SEL_B(config->channelBFIFOSelect) +#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ + ; + if (config->enableHardwareTrigger) + { + tmp32 |= ADC_TCTRL_HTEN_MASK; + } + + base->TCTRL[triggerId] = tmp32; +} + +/*! + * brief Gets an available pre-defined settings for trigger's configuration. + * + * This function initializes the trigger's configuration structure with an available settings. The default values are: + * code + * config->commandIdSource = 0U; + * config->loopCountIndex = 0U; + * config->triggerIdSource = 0U; + * config->enableHardwareTrigger = false; + * config->channelAFIFOSelect = 0U; + * config->channelBFIFOSelect = 0U; + * endcode + * param config Pointer to configuration structure. + */ +void LPADC_GetDefaultConvTriggerConfig(lpadc_conv_trigger_config_t *config) +{ + assert(config != NULL); /* Check if the input pointer is available. */ + + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + + config->targetCommandId = 0U; + config->delayPower = 0U; + config->priority = 0U; +#if defined(FSL_FEATURE_LPADC_FIFO_COUNT) && FSL_FEATURE_LPADC_FIFO_COUNT + config->channelAFIFOSelect = 0U; + config->channelBFIFOSelect = 0U; +#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ + config->enableHardwareTrigger = false; +} + +/*! + * brief Configure conversion command. + * + * param base LPADC peripheral base address. + * param commandId ID for command in command buffer. Typically, the available value range is 1 - 15. + * param config Pointer to configuration structure. See to #lpadc_conv_command_config_t. + */ +void LPADC_SetConvCommandConfig(ADC_Type *base, uint32_t commandId, const lpadc_conv_command_config_t *config) +{ + assert(commandId < (ADC_CMDL_COUNT + 1U)); /* Check if the commandId is available on this device. */ + assert(config != NULL); /* Check if the input pointer is available. */ + + uint32_t tmp32 = 0; + + commandId--; /* The available command number are 1-15, while the index of register group are 0-14. */ + + /* ADCx_CMDL. */ + tmp32 = ADC_CMDL_ADCH(config->channelNumber); /* Channel number. */ +#if defined(FSL_FEATURE_LPADC_HAS_CMDL_CSCALE) && FSL_FEATURE_LPADC_HAS_CMDL_CSCALE + tmp32 |= ADC_CMDL_CSCALE(config->sampleScaleMode); /* Full/Part scale input voltage. */ +#endif /* FSL_FEATURE_LPADC_HAS_CMDL_CSCALE */ +#if defined(FSL_FEATURE_LPADC_HAS_CMDL_CTYPE) && FSL_FEATURE_LPADC_HAS_CMDL_CTYPE + tmp32 |= ADC_CMDL_CTYPE(config->sampleChannelMode); +#else + switch (config->sampleChannelMode) /* Sample input. */ + { + case kLPADC_SampleChannelSingleEndSideB: + tmp32 |= ADC_CMDL_ABSEL_MASK; + break; +#if defined(FSL_FEATURE_LPADC_HAS_CMDL_DIFF) && FSL_FEATURE_LPADC_HAS_CMDL_DIFF + case kLPADC_SampleChannelDiffBothSideAB: + tmp32 |= ADC_CMDL_DIFF_MASK; + break; + case kLPADC_SampleChannelDiffBothSideBA: + tmp32 |= ADC_CMDL_ABSEL_MASK | ADC_CMDL_DIFF_MASK; + break; +#endif /* FSL_FEATURE_LPADC_HAS_CMDL_DIFF */ + default: /* kLPADC_SampleChannelSingleEndSideA. */ + break; + } +#endif /* FSL_FEATURE_LPADC_HAS_CMDL_CTYPE */ +#if defined(FSL_FEATURE_LPADC_HAS_CMDL_MODE) && FSL_FEATURE_LPADC_HAS_CMDL_MODE + tmp32 |= ADC_CMDL_MODE(config->conversionResoultuionMode); +#endif /* FSL_FEATURE_LPADC_HAS_CMDL_MODE */ + base->CMD[commandId].CMDL = tmp32; + + /* ADCx_CMDH. */ + tmp32 = ADC_CMDH_NEXT(config->chainedNextCommandNumber) /* Next Command Select. */ + | ADC_CMDH_LOOP(config->loopCount) /* Loop Count Select. */ + | ADC_CMDH_AVGS(config->hardwareAverageMode) /* Hardware Average Select. */ + | ADC_CMDH_STS(config->sampleTimeMode) /* Sample Time Select. */ + | ADC_CMDH_CMPEN(config->hardwareCompareMode); /* Hardware compare enable. */ +#if (defined(FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG) && FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG) + if (config->enableWaitTrigger) + { + tmp32 |= ADC_CMDH_WAIT_TRIG_MASK; /* Wait trigger enable. */ + } +#endif /* FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG */ + + if (config->enableAutoChannelIncrement) + { + tmp32 |= ADC_CMDH_LWI_MASK; + } + base->CMD[commandId].CMDH = tmp32; + + /* Hardware compare settings. + * Not all Command Buffers have an associated Compare Value register. The compare function is only available on + * Command Buffers that have a corresponding Compare Value register. + */ + if (kLPADC_HardwareCompareDisabled != config->hardwareCompareMode) + { + /* Check if the hardware compare feature is available for indicated command buffer. */ + assert(commandId < ADC_CV_COUNT); + + /* Set CV register. */ + base->CV[commandId] = ADC_CV_CVH(config->hardwareCompareValueHigh) /* Compare value high. */ + | ADC_CV_CVL(config->hardwareCompareValueLow); /* Compare value low. */ + } +} + +/*! + * brief Gets an available pre-defined settings for conversion command's configuration. + * + * This function initializes the conversion command's configuration structure with an available settings. The default + * values are: + * code + * config->sampleScaleMode = kLPADC_SampleFullScale; + * config->channelSampleMode = kLPADC_SampleChannelSingleEndSideA; + * config->channelNumber = 0U; + * config->chainedNextCmdNumber = 0U; + * config->enableAutoChannelIncrement = false; + * config->loopCount = 0U; + * config->hardwareAverageMode = kLPADC_HardwareAverageCount1; + * config->sampleTimeMode = kLPADC_SampleTimeADCK3; + * config->hardwareCompareMode = kLPADC_HardwareCompareDisabled; + * config->hardwareCompareValueHigh = 0U; + * config->hardwareCompareValueLow = 0U; + * config->conversionResoultuionMode = kLPADC_ConversionResolutionStandard; + * config->enableWaitTrigger = false; + * endcode + * param config Pointer to configuration structure. + */ +void LPADC_GetDefaultConvCommandConfig(lpadc_conv_command_config_t *config) +{ + assert(config != NULL); /* Check if the input pointer is available. */ + + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + +#if defined(FSL_FEATURE_LPADC_HAS_CMDL_CSCALE) && FSL_FEATURE_LPADC_HAS_CMDL_CSCALE + config->sampleScaleMode = kLPADC_SampleFullScale; +#endif /* FSL_FEATURE_LPADC_HAS_CMDL_CSCALE */ + config->sampleChannelMode = kLPADC_SampleChannelSingleEndSideA; + config->channelNumber = 0U; + config->chainedNextCommandNumber = 0U; /* No next command defined. */ + config->enableAutoChannelIncrement = false; + config->loopCount = 0U; + config->hardwareAverageMode = kLPADC_HardwareAverageCount1; + config->sampleTimeMode = kLPADC_SampleTimeADCK3; + config->hardwareCompareMode = kLPADC_HardwareCompareDisabled; + config->hardwareCompareValueHigh = 0U; /* No used. */ + config->hardwareCompareValueLow = 0U; /* No used. */ +#if defined(FSL_FEATURE_LPADC_HAS_CMDL_MODE) && FSL_FEATURE_LPADC_HAS_CMDL_MODE + config->conversionResoultuionMode = kLPADC_ConversionResolutionStandard; +#endif /* FSL_FEATURE_LPADC_HAS_CMDL_MODE */ +#if defined(FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG) && FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG + config->enableWaitTrigger = false; +#endif /* FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG */ +} + +#if defined(FSL_FEATURE_LPADC_HAS_CFG_CALOFS) && FSL_FEATURE_LPADC_HAS_CFG_CALOFS +/*! + * brief Enable the calibration function. + * + * When CALOFS is set, the ADC is configured to perform a calibration function anytime the ADC executes + * a conversion. Any channel selected is ignored and the value returned in the RESFIFO is a signed value + * between -31 and 31. -32 is not a valid and is never a returned value. Software should copy the lower 6- + * bits of the conversion result stored in the RESFIFO after a completed calibration conversion to the + * OFSTRIM field. The OFSTRIM field is used in normal operation for offset correction. + * + * param base LPADC peripheral base address. + * bool enable switcher to the calibration function. + */ +void LPADC_EnableCalibration(ADC_Type *base, bool enable) +{ + LPADC_Enable(base, false); + if (enable) + { + base->CFG |= ADC_CFG_CALOFS_MASK; + } + else + { + base->CFG &= ~ADC_CFG_CALOFS_MASK; + } + LPADC_Enable(base, true); +} + +#if defined(FSL_FEATURE_LPADC_HAS_OFSTRIM) && FSL_FEATURE_LPADC_HAS_OFSTRIM +/*! + * brief Do auto calibration. + * + * Calibration function should be executed before using converter in application. It used the software trigger and a + * dummy conversion, get the offset and write them into the OFSTRIM register. It called some of functional API + * including: -LPADC_EnableCalibration(...) -LPADC_LPADC_SetOffsetValue(...) -LPADC_SetConvCommandConfig(...) + * -LPADC_SetConvTriggerConfig(...) + * + * param base LPADC peripheral base address. + */ +void LPADC_DoAutoCalibration(ADC_Type *base) +{ + assert(0u == LPADC_GetConvResultCount(base)); + + uint32_t mLpadcCMDL; + uint32_t mLpadcCMDH; + uint32_t mLpadcTrigger; + lpadc_conv_trigger_config_t mLpadcTriggerConfigStruct; + lpadc_conv_command_config_t mLpadcCommandConfigStruct; + lpadc_conv_result_t mLpadcResultConfigStruct; + + /* Enable the calibration function. */ + LPADC_EnableCalibration(base, true); + + /* Keep the CMD and TRG state here and restore it later if the calibration completes.*/ + mLpadcCMDL = base->CMD[0].CMDL; /* CMD1L. */ + mLpadcCMDH = base->CMD[0].CMDH; /* CMD1H. */ + mLpadcTrigger = base->TCTRL[0]; /* Trigger0. */ + + /* Set trigger0 configuration - for software trigger. */ + LPADC_GetDefaultConvTriggerConfig(&mLpadcTriggerConfigStruct); + mLpadcTriggerConfigStruct.targetCommandId = 1U; /* CMD1 is executed. */ + LPADC_SetConvTriggerConfig(base, 0U, &mLpadcTriggerConfigStruct); /* Configurate the trigger0. */ + + /* Set conversion CMD configuration. */ + LPADC_GetDefaultConvCommandConfig(&mLpadcCommandConfigStruct); + mLpadcCommandConfigStruct.hardwareAverageMode = kLPADC_HardwareAverageCount128; + LPADC_SetConvCommandConfig(base, 1U, &mLpadcCommandConfigStruct); /* Set CMD1 configuration. */ + + /* Do calibration. */ + LPADC_DoSoftwareTrigger(base, 1U); /* 1U is trigger0 mask. */ + while (!LPADC_GetConvResult(base, &mLpadcResultConfigStruct)) + { + } + /* The valid bits of data are bits 14:3 in the RESFIFO register. */ + LPADC_SetOffsetValue(base, (mLpadcResultConfigStruct.convValue) >> 3U); + /* Disable the calibration function. */ + LPADC_EnableCalibration(base, false); + + /* restore CMD and TRG registers. */ + base->CMD[0].CMDL = mLpadcCMDL; /* CMD1L. */ + base->CMD[0].CMDH = mLpadcCMDH; /* CMD1H. */ + base->TCTRL[0] = mLpadcTrigger; /* Trigger0. */ +} +#endif /* FSL_FEATURE_LPADC_HAS_OFSTRIM */ +#endif /* FSL_FEATURE_LPADC_HAS_CFG_CALOFS */ + +#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CALOFS) && FSL_FEATURE_LPADC_HAS_CTRL_CALOFS +/*! + * brief Do offset calibration. + * + * param base LPADC peripheral base address. + */ +void LPADC_DoOffsetCalibration(ADC_Type *base) +{ + LPADC_EnableOffsetCalibration(base, true); + while (ADC_STAT_CAL_RDY_MASK != (base->STAT & ADC_STAT_CAL_RDY_MASK)) + { + } +} + +#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ +/*! + * brief Do auto calibration. + * + * param base LPADC peripheral base address. + */ +void LPADC_DoAutoCalibration(ADC_Type *base) +{ + assert((0u == LPADC_GetConvResultCount(base, 0)) && (0u == LPADC_GetConvResultCount(base, 1))); + + uint32_t GCCa; + uint32_t GCCb; + uint32_t GCRa; + uint32_t GCRb; + + /* Request gain calibration. */ + base->CTRL |= ADC_CTRL_CAL_REQ_MASK; + while ((ADC_GCC_RDY_MASK != (base->GCC[0] & ADC_GCC_RDY_MASK)) || + (ADC_GCC_RDY_MASK != (base->GCC[1] & ADC_GCC_RDY_MASK))) + { + } + + /* Calculate gain offset. */ + GCCa = (base->GCC[0] & ADC_GCC_GAIN_CAL_MASK); + GCCb = (base->GCC[1] & ADC_GCC_GAIN_CAL_MASK); + GCRa = (uint16_t)((GCCa << 16U) / + (0x1FFFFU - GCCa)); /* Gain_CalA = (131072 / (131072-(ADC_GCC_GAIN_CAL(ADC0->GCC[0])) - 1. */ + GCRb = (uint16_t)((GCCb << 16U) / + (0x1FFFFU - GCCb)); /* Gain_CalB = (131072 / (131072-(ADC_GCC_GAIN_CAL(ADC0->GCC[1])) - 1. */ + base->GCR[0] = ADC_GCR_GCALR(GCRa); + base->GCR[1] = ADC_GCR_GCALR(GCRb); + + /* Indicate the values are valid. */ + base->GCR[0] |= ADC_GCR_RDY_MASK; + base->GCR[1] |= ADC_GCR_RDY_MASK; + + while (ADC_STAT_CAL_RDY_MASK != (base->STAT & ADC_STAT_CAL_RDY_MASK)) + { + } +} +#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ */ +#endif /* FSL_FEATURE_LPADC_HAS_CFG_CALOFS */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_lpadc.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_lpadc.h new file mode 100644 index 000000000..4a862f7bb --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_lpadc.h @@ -0,0 +1,841 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_LPADC_H_ +#define _FSL_LPADC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup lpadc + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief LPADC driver version 2.1.1. */ +#define FSL_LPADC_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) +/*@}*/ + +/*! + * @brief Define the MACRO function to get command status from status value. + * + * The statusVal is the return value from LPADC_GetStatusFlags(). + */ +#define LPADC_GET_ACTIVE_COMMAND_STATUS(statusVal) ((statusVal & ADC_STAT_CMDACT_MASK) >> ADC_STAT_CMDACT_SHIFT) + +/*! + * @brief Define the MACRO function to get trigger status from status value. + * + * The statusVal is the return value from LPADC_GetStatusFlags(). + */ +#define LPADC_GET_ACTIVE_TRIGGER_STATUE(statusVal) ((statusVal & ADC_STAT_TRGACT_MASK) >> ADC_STAT_TRGACT_SHIFT) + +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) +/*! + * @brief Define hardware flags of the module. + */ +enum _lpadc_status_flags +{ + kLPADC_ResultFIFO0OverflowFlag = ADC_STAT_FOF0_MASK, /*!< Indicates that more data has been written to the Result + FIFO 0 than it can hold. */ + kLPADC_ResultFIFO0ReadyFlag = ADC_STAT_RDY0_MASK, /*!< Indicates when the number of valid datawords in the result + FIFO 0 is greater than the setting watermark level. */ + kLPADC_ResultFIFO1OverflowFlag = ADC_STAT_FOF1_MASK, /*!< Indicates that more data has been written to the Result + FIFO 1 than it can hold. */ + kLPADC_ResultFIFO1ReadyFlag = ADC_STAT_RDY1_MASK, /*!< Indicates when the number of valid datawords in the result + FIFO 1 is greater than the setting watermark level. */ +}; + +/*! + * @brief Define interrupt switchers of the module. + */ +enum _lpadc_interrupt_enable +{ + kLPADC_ResultFIFO0OverflowInterruptEnable = ADC_IE_FOFIE0_MASK, /*!< Configures ADC to generate overflow interrupt + requests when FOF0 flag is asserted. */ + kLPADC_FIFO0WatermarkInterruptEnable = ADC_IE_FWMIE0_MASK, /*!< Configures ADC to generate watermark interrupt + requests when RDY0 flag is asserted. */ + kLPADC_ResultFIFO1OverflowInterruptEnable = ADC_IE_FOFIE1_MASK, /*!< Configures ADC to generate overflow interrupt + requests when FOF1 flag is asserted. */ + kLPADC_FIFO1WatermarkInterruptEnable = ADC_IE_FWMIE1_MASK, /*!< Configures ADC to generate watermark interrupt + requests when RDY1 flag is asserted. */ +}; +#else +/*! + * @brief Define hardware flags of the module. + */ +enum _lpadc_status_flags +{ + kLPADC_ResultFIFOOverflowFlag = ADC_STAT_FOF_MASK, /*!< Indicates that more data has been written to the Result FIFO + than it can hold. */ + kLPADC_ResultFIFOReadyFlag = ADC_STAT_RDY_MASK, /*!< Indicates when the number of valid datawords in the result FIFO + is greater than the setting watermark level. */ +}; + +/*! + * @brief Define interrupt switchers of the module. + */ +enum _lpadc_interrupt_enable +{ + kLPADC_ResultFIFOOverflowInterruptEnable = ADC_IE_FOFIE_MASK, /*!< Configures ADC to generate overflow interrupt + requests when FOF flag is asserted. */ + kLPADC_FIFOWatermarkInterruptEnable = ADC_IE_FWMIE_MASK, /*!< Configures ADC to generate watermark interrupt + requests when RDY flag is asserted. */ +}; +#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ + +/*! + * @brief Define enumeration of sample scale mode. + * + * The sample scale mode is used to reduce the selected ADC analog channel input voltage level by a factor. The maximum + * possible voltage on the ADC channel input should be considered when selecting a scale mode to ensure that the + * reducing factor always results voltage level at or below the VREFH reference. This reducing capability allows + * conversion of analog inputs higher than VREFH. A-side and B-side channel inputs are both scaled using the scale mode. + */ +typedef enum _lpadc_sample_scale_mode +{ + kLPADC_SamplePartScale = 0U, /*!< Use divided input voltage signal. (Factor of 30/64). */ + kLPADC_SampleFullScale = 1U, /*!< Full scale (Factor of 1). */ +} lpadc_sample_scale_mode_t; + +/*! + * @brief Define enumeration of channel sample mode. + * + * The channel sample mode configures the channel with single-end/differential/dual-single-end, side A/B. + */ +typedef enum _lpadc_sample_channel_mode +{ + kLPADC_SampleChannelSingleEndSideA = 0U, /*!< Single end mode, using side A. */ + kLPADC_SampleChannelSingleEndSideB = 1U, /*!< Single end mode, using side B. */ +#if defined(FSL_FEATURE_LPADC_HAS_CMDL_DIFF) && FSL_FEATURE_LPADC_HAS_CMDL_DIFF + kLPADC_SampleChannelDiffBothSideAB = 2U, /*!< Differential mode, using A as plus side and B as minue side. */ + kLPADC_SampleChannelDiffBothSideBA = 3U, /*!< Differential mode, using B as plus side and A as minue side. */ +#elif defined(FSL_FEATURE_LPADC_HAS_CMDL_CTYPE) && FSL_FEATURE_LPADC_HAS_CMDL_CTYPE + kLPADC_SampleChannelDiffBothSide = 2U, /*!< Differential mode, using A and B. */ + kLPADC_SampleChannelDualSingleEndBothSide = + 3U, /*!< Dual-Single-Ended Mode. Both A side and B side channels are converted independently. */ +#endif +} lpadc_sample_channel_mode_t; + +/*! + * @brief Define enumeration of hardware average selection. + * + * It Selects how many ADC conversions are averaged to create the ADC result. An internal storage buffer is used to + * capture temporary results while the averaging iterations are executed. + */ +typedef enum _lpadc_hardware_average_mode +{ + kLPADC_HardwareAverageCount1 = 0U, /*!< Single conversion. */ + kLPADC_HardwareAverageCount2 = 1U, /*!< 2 conversions averaged. */ + kLPADC_HardwareAverageCount4 = 2U, /*!< 4 conversions averaged. */ + kLPADC_HardwareAverageCount8 = 3U, /*!< 8 conversions averaged. */ + kLPADC_HardwareAverageCount16 = 4U, /*!< 16 conversions averaged. */ + kLPADC_HardwareAverageCount32 = 5U, /*!< 32 conversions averaged. */ + kLPADC_HardwareAverageCount64 = 6U, /*!< 64 conversions averaged. */ + kLPADC_HardwareAverageCount128 = 7U, /*!< 128 conversions averaged. */ +} lpadc_hardware_average_mode_t; + +/*! + * @brief Define enumeration of sample time selection. + * + * The shortest sample time maximizes conversion speed for lower impedance inputs. Extending sample time allows higher + * impedance inputs to be accurately sampled. Longer sample times can also be used to lower overall power consumption + * when command looping and sequencing is configured and high conversion rates are not required. + */ +typedef enum _lpadc_sample_time_mode +{ + kLPADC_SampleTimeADCK3 = 0U, /*!< 3 ADCK cycles total sample time. */ + kLPADC_SampleTimeADCK5 = 1U, /*!< 5 ADCK cycles total sample time. */ + kLPADC_SampleTimeADCK7 = 2U, /*!< 7 ADCK cycles total sample time. */ + kLPADC_SampleTimeADCK11 = 3U, /*!< 11 ADCK cycles total sample time. */ + kLPADC_SampleTimeADCK19 = 4U, /*!< 19 ADCK cycles total sample time. */ + kLPADC_SampleTimeADCK35 = 5U, /*!< 35 ADCK cycles total sample time. */ + kLPADC_SampleTimeADCK67 = 6U, /*!< 69 ADCK cycles total sample time. */ + kLPADC_SampleTimeADCK131 = 7U, /*!< 131 ADCK cycles total sample time. */ +} lpadc_sample_time_mode_t; + +/*! + * @brief Define enumeration of hardware compare mode. + * + * After an ADC channel input is sampled and converted and any averaging iterations are performed, this mode setting + * guides operation of the automatic compare function to optionally only store when the compare operation is true. + * When compare is enabled, the conversion result is compared to the compare values. + */ +typedef enum _lpadc_hardware_compare_mode +{ + kLPADC_HardwareCompareDisabled = 0U, /*!< Compare disabled. */ + kLPADC_HardwareCompareStoreOnTrue = 2U, /*!< Compare enabled. Store on true. */ + kLPADC_HardwareCompareRepeatUntilTrue = 3U, /*!< Compare enabled. Repeat channel acquisition until true. */ +} lpadc_hardware_compare_mode_t; + +/*! + * @brief Define enumeration of conversion resolution mode. + * + * Configure the resolution bit in specific conversion type. For detailed resolution accuracy, see to + * #_lpadc_sample_channel_mode + */ +typedef enum _lpadc_conversion_resolution_mode +{ + kLPADC_ConversionResolutionStandard = 0U, /*!< Standard resolution. Single-ended 12-bit conversion, Differential + 13-bit conversion with 2’s complement output. */ + kLPADC_ConversionResolutionHigh = 1U, /*!< High resolution. Single-ended 16-bit conversion; Differential 16-bit + conversion with 2’s complement output. */ +} lpadc_conversion_resolution_mode_t; + +#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS +/*! + * @brief Define enumeration of conversion averages mode. + * + * Configure the converion average number for auto-calibration. + */ +typedef enum _lpadc_conversion_average_mode +{ + kLPADC_ConversionAverage1 = 0U, /*!< Single conversion. */ + kLPADC_ConversionAverage2 = 1U, /*!< 2 conversions averaged. */ + kLPADC_ConversionAverage4 = 2U, /*!< 4 conversions averaged. */ + kLPADC_ConversionAverage8 = 3U, /*!< 8 conversions averaged. */ + kLPADC_ConversionAverage16 = 4U, /*!< 16 conversions averaged. */ + kLPADC_ConversionAverage32 = 5U, /*!< 32 conversions averaged. */ + kLPADC_ConversionAverage64 = 6U, /*!< 64 conversions averaged. */ + kLPADC_ConversionAverage128 = 7U, /*!< 128 conversions averaged. */ +} lpadc_conversion_average_mode_t; +#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS */ + +/*! + * @brief Define enumeration of reference voltage source. + * + * For detail information, need to check the SoC's specification. + */ +typedef enum _lpadc_reference_voltage_mode +{ + kLPADC_ReferenceVoltageAlt1 = 0U, /*!< Option 1 setting. */ + kLPADC_ReferenceVoltageAlt2 = 1U, /*!< Option 2 setting. */ + kLPADC_ReferenceVoltageAlt3 = 2U, /*!< Option 3 setting. */ +} lpadc_reference_voltage_source_t; + +/*! + * @brief Define enumeration of power configuration. + * + * Configures the ADC for power and performance. In the highest power setting the highest conversion rates will be + * possible. Refer to the device data sheet for power and performance capabilities for each setting. + */ +typedef enum _lpadc_power_level_mode +{ + kLPADC_PowerLevelAlt1 = 0U, /*!< Lowest power setting. */ + kLPADC_PowerLevelAlt2 = 1U, /*!< Next lowest power setting. */ + kLPADC_PowerLevelAlt3 = 2U, /*!< ... */ + kLPADC_PowerLevelAlt4 = 3U, /*!< Highest power setting. */ +} lpadc_power_level_mode_t; + +/*! + * @brief Define enumeration of trigger priority policy. + * + * This selection controls how higher priority triggers are handled. + */ +typedef enum _lpadc_trigger_priority_policy +{ + kLPADC_TriggerPriorityPreemptImmediately = 0U, /*!< If a higher priority trigger is detected during command + processing, the current conversion is aborted and the new + command specified by the trigger is started. */ + kLPADC_TriggerPriorityPreemptSoftly = 1U, /*!< If a higher priority trigger is received during command processing, + the current conversion is completed (including averaging iterations + and compare function if enabled) and stored to the result FIFO + before the higher priority trigger/command is initiated. */ +#if defined(FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY) && FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY + kLPADC_TriggerPriorityPreemptSubsequently = 2U, /*!< If a higher priority trigger is received during command + processing, the current command will be completed (averaging, + looping, compare) before servicing the higher priority trigger. */ +#endif /* FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY */ +} lpadc_trigger_priority_policy_t; + +/*! + * @beief LPADC global configuration. + * + * This structure would used to keep the settings for initialization. + */ +typedef struct +{ +#if defined(FSL_FEATURE_LPADC_HAS_CFG_ADCKEN) && FSL_FEATURE_LPADC_HAS_CFG_ADCKEN + bool enableInternalClock; /*!< Enables the internally generated clock source. The clock source is used in clock + selection logic at the chip level and is optionally used for the ADC clock source. */ +#endif /* FSL_FEATURE_LPADC_HAS_CFG_ADCKEN */ +#if defined(FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG) && FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG + bool enableVref1LowVoltage; /*!< If voltage reference option1 input is below 1.8V, it should be "true". + If voltage reference option1 input is above 1.8V, it should be "false". */ +#endif /* FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG */ + bool enableInDozeMode; /*!< Control system transition to Stop and Wait power modes while ADC is converting. When + enabled in Doze mode, immediate entries to Wait or Stop are allowed. When disabled, the + ADC will wait for the current averaging iteration/FIFO storage to complete before + acknowledging stop or wait mode entry. */ +#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS + lpadc_conversion_average_mode_t conversionAverageMode; /*!< Auto-Calibration Averages. */ +#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS */ + bool enableAnalogPreliminary; /*!< ADC analog circuits are pre-enabled and ready to execute conversions without + startup delays(at the cost of higher DC current consumption). */ + uint32_t powerUpDelay; /*!< When the analog circuits are not pre-enabled, the ADC analog circuits are only powered + while the ADC is active and there is a counted delay defined by this field after an + initial trigger transitions the ADC from its Idle state to allow time for the analog + circuits to stabilize. The startup delay count of (powerUpDelay * 4) ADCK cycles must + result in a longer delay than the analog startup time. */ + lpadc_reference_voltage_source_t referenceVoltageSource; /*!< Selects the voltage reference high used for + conversions.*/ + lpadc_power_level_mode_t powerLevelMode; /*!< Power Configuration Selection. */ + lpadc_trigger_priority_policy_t triggerPrioirtyPolicy; /*!< Control how higher priority triggers are handled, see to + #lpadc_trigger_priority_policy_mode_t. */ + bool enableConvPause; /*!< Enables the ADC pausing function. When enabled, a programmable delay is inserted during + command execution sequencing between LOOP iterations, between commands in a sequence, and + between conversions when command is executing in "Compare Until True" configuration. */ + uint32_t convPauseDelay; /*!< Controls the duration of pausing during command execution sequencing. The pause delay + is a count of (convPauseDelay*4) ADCK cycles. Only available when ADC pausing + function is enabled. The available value range is in 9-bit. */ +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) + /* for FIFO0. */ + uint32_t FIFO0Watermark; /*!< FIFO0Watermark is a programmable threshold setting. When the number of datawords + stored in the ADC Result FIFO0 is greater than the value in this field, the ready flag + would be asserted to indicate stored data has reached the programmable threshold. */ + /* for FIFO1. */ + uint32_t FIFO1Watermark; /*!< FIFO1Watermark is a programmable threshold setting. When the number of datawords + stored in the ADC Result FIFO1 is greater than the value in this field, the ready flag + would be asserted to indicate stored data has reached the programmable threshold. */ +#else + /* for FIFO. */ + uint32_t FIFOWatermark; /*!< FIFOWatermark is a programmable threshold setting. When the number of datawords stored + in the ADC Result FIFO is greater than the value in this field, the ready flag would be + asserted to indicate stored data has reached the programmable threshold. */ +#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ +} lpadc_config_t; + +/*! + * @brief Define structure to keep the configuration for conversion command. + */ +typedef struct +{ +#if defined(FSL_FEATURE_LPADC_HAS_CMDL_CSCALE) && FSL_FEATURE_LPADC_HAS_CMDL_CSCALE + lpadc_sample_scale_mode_t sampleScaleMode; /*!< Sample scale mode. */ +#endif /* FSL_FEATURE_LPADC_HAS_CMDL_CSCALE */ + lpadc_sample_channel_mode_t sampleChannelMode; /*!< Channel sample mode. */ + uint32_t channelNumber; /*!< Channel number, select the channel or channel pair. */ + uint32_t chainedNextCommandNumber; /*!< Selects the next command to be executed after this command completes. + 1-15 is available, 0 is to terminate the chain after this command. */ + bool enableAutoChannelIncrement; /*!< Loop with increment: when disabled, the "loopCount" field selects the number + of times the selected channel is converted consecutively; when enabled, the + "loopCount" field defines how many consecutive channels are converted as part + of the command execution. */ + uint32_t loopCount; /*!< Selects how many times this command executes before finish and transition to the next + command or Idle state. Command executes LOOP+1 times. 0-15 is available. */ + lpadc_hardware_average_mode_t hardwareAverageMode; /*!< Hardware average selection. */ + lpadc_sample_time_mode_t sampleTimeMode; /*!< Sample time selection. */ + + lpadc_hardware_compare_mode_t hardwareCompareMode; /*!< Hardware compare selection. */ + uint32_t hardwareCompareValueHigh; /*!< Compare Value High. The available value range is in 16-bit. */ + uint32_t hardwareCompareValueLow; /*!< Compare Value Low. The available value range is in 16-bit. */ +#if defined(FSL_FEATURE_LPADC_HAS_CMDL_MODE) && FSL_FEATURE_LPADC_HAS_CMDL_MODE + lpadc_conversion_resolution_mode_t conversionResoultuionMode; /*!< Conversion resolution mode. */ +#endif /* FSL_FEATURE_LPADC_HAS_CMDL_MODE */ +#if defined(FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG) && FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG + bool enableWaitTrigger; /*!< Wait for trigger assertion before execution: when disabled, this command will be + automatically executed; when enabled, the active trigger must be asserted again before + executing this command. */ +#endif /* FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG */ +} lpadc_conv_command_config_t; + +/*! + * @brief Define structure to keep the configuration for conversion trigger. + */ +typedef struct +{ + uint32_t targetCommandId; /*!< Select the command from command buffer to execute upon detect of the associated + trigger event. */ + uint32_t delayPower; /*!< Select the trigger delay duration to wait at the start of servicing a trigger event. + When this field is clear, then no delay is incurred. When this field is set to a non-zero + value, the duration for the delay is 2^delayPower ADCK cycles. The available value range + is 4-bit. */ + uint32_t priority; /*!< Sets the priority of the associated trigger source. If two or more triggers have the same + priority level setting, the lower order trigger event has the higher priority. The lower + value for this field is for the higher priority, the available value range is 1-bit. */ +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) + uint8_t channelAFIFOSelect; /* SAR Result Destination For Channel A. */ + uint8_t channelBFIFOSelect; /* SAR Result Destination For Channel B. */ +#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ + bool enableHardwareTrigger; /*!< Enable hardware trigger source to initiate conversion on the rising edge of the + input trigger source or not. THe software trigger is always available. */ +} lpadc_conv_trigger_config_t; + +/*! + * @brief Define the structure to keep the conversion result. + */ +typedef struct +{ + uint32_t commandIdSource; /*!< Indicate the command buffer being executed that generated this result. */ + uint32_t loopCountIndex; /*!< Indicate the loop count value during command execution that generated this result. */ + uint32_t triggerIdSource; /*!< Indicate the trigger source that initiated a conversion and generated this result. */ + uint16_t convValue; /*!< Data result. */ +} lpadc_conv_result_t; + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* + * API + ******************************************************************************/ +/*! + * @name Initialization & de-initialization. + * @{ + */ + +/*! + * @brief Initializes the LPADC module. + * + * @param base LPADC peripheral base address. + * @param config Pointer to configuration structure. See "lpadc_config_t". + */ +void LPADC_Init(ADC_Type *base, const lpadc_config_t *config); + +/*! + * @brief Gets an available pre-defined settings for initial configuration. + * + * This function initializes the converter configuration structure with an available settings. The default values are: + * @code + * config->enableInDozeMode = true; + * config->enableAnalogPreliminary = false; + * config->powerUpDelay = 0x80; + * config->referenceVoltageSource = kLPADC_ReferenceVoltageAlt1; + * config->powerLevelMode = kLPADC_PowerLevelAlt1; + * config->triggerPrioirtyPolicy = kLPADC_TriggerPriorityPreemptImmediately; + * config->enableConvPause = false; + * config->convPauseDelay = 0U; + * config->FIFOWatermark = 0U; + * @endcode + * @param config Pointer to configuration structure. + */ +void LPADC_GetDefaultConfig(lpadc_config_t *config); + +/*! + * @brief De-initializes the LPADC module. + * + * @param base LPADC peripheral base address. + */ +void LPADC_Deinit(ADC_Type *base); + +/*! + * @brief Switch on/off the LPADC module. + * + * @param base LPADC peripheral base address. + * @param enable switcher to the module. + */ +static inline void LPADC_Enable(ADC_Type *base, bool enable) +{ + if (enable) + { + base->CTRL |= ADC_CTRL_ADCEN_MASK; + } + else + { + base->CTRL &= ~ADC_CTRL_ADCEN_MASK; + } +} + +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) +/*! + * @brief Do reset the conversion FIFO0. + * + * @param base LPADC peripheral base address. + */ +static inline void LPADC_DoResetFIFO0(ADC_Type *base) +{ + base->CTRL |= ADC_CTRL_RSTFIFO0_MASK; +} + +/*! + * @brief Do reset the conversion FIFO1. + * + * @param base LPADC peripheral base address. + */ +static inline void LPADC_DoResetFIFO1(ADC_Type *base) +{ + base->CTRL |= ADC_CTRL_RSTFIFO1_MASK; +} +#else +/*! + * @brief Do reset the conversion FIFO. + * + * @param base LPADC peripheral base address. + */ +static inline void LPADC_DoResetFIFO(ADC_Type *base) +{ + base->CTRL |= ADC_CTRL_RSTFIFO_MASK; +} +#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ + +/*! + * @brief Do reset the module's configuration. + * + * Reset all ADC internal logic and registers, except the Control Register (ADCx_CTRL). + * + * @param base LPADC peripheral base address. + */ +static inline void LPADC_DoResetConfig(ADC_Type *base) +{ + base->CTRL |= ADC_CTRL_RST_MASK; + base->CTRL &= ~ADC_CTRL_RST_MASK; +} + +/* @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Get status flags. + * + * @param base LPADC peripheral base address. + * @return status flags' mask. See to #_lpadc_status_flags. + */ +static inline uint32_t LPADC_GetStatusFlags(ADC_Type *base) +{ + return base->STAT; +} + +/*! + * @brief Clear status flags. + * + * Only the flags can be cleared by writing ADCx_STATUS register would be cleared by this API. + * + * @param base LPADC peripheral base address. + * @param mask Mask value for flags to be cleared. See to #_lpadc_status_flags. + */ +static inline void LPADC_ClearStatusFlags(ADC_Type *base, uint32_t mask) +{ + base->STAT = mask; +} + +/* @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enable interrupts. + * + * @param base LPADC peripheral base address. + * @mask Mask value for interrupt events. See to #_lpadc_interrupt_enable. + */ +static inline void LPADC_EnableInterrupts(ADC_Type *base, uint32_t mask) +{ + base->IE |= mask; +} + +/*! + * @brief Disable interrupts. + * + * @param base LPADC peripheral base address. + * @param mask Mask value for interrupt events. See to #_lpadc_interrupt_enable. + */ +static inline void LPADC_DisableInterrupts(ADC_Type *base, uint32_t mask) +{ + base->IE &= ~mask; +} + +/*! + * @name DMA Control + * @{ + */ + +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) +/*! + * @brief Switch on/off the DMA trigger for FIFO0 watermark event. + * + * @param base LPADC peripheral base address. + * @param enable Switcher to the event. + */ +static inline void LPADC_EnableFIFO0WatermarkDMA(ADC_Type *base, bool enable) +{ + if (enable) + { + base->DE |= ADC_DE_FWMDE0_MASK; + } + else + { + base->DE &= ~ADC_DE_FWMDE0_MASK; + } +} + +/*! + * @brief Switch on/off the DMA trigger for FIFO1 watermark event. + * + * @param base LPADC peripheral base address. + * @param enable Switcher to the event. + */ +static inline void LPADC_EnableFIFO1WatermarkDMA(ADC_Type *base, bool enable) +{ + if (enable) + { + base->DE |= ADC_DE_FWMDE1_MASK; + } + else + { + base->DE &= ~ADC_DE_FWMDE1_MASK; + } +} +#else +/*! + * @brief Switch on/off the DMA trigger for FIFO watermark event. + * + * @param base LPADC peripheral base address. + * @param enable Switcher to the event. + */ +static inline void LPADC_EnableFIFOWatermarkDMA(ADC_Type *base, bool enable) +{ + if (enable) + { + base->DE |= ADC_DE_FWMDE_MASK; + } + else + { + base->DE &= ~ADC_DE_FWMDE_MASK; + } +} +#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ + /* @} */ + +/*! + * @name Trigger and conversion with FIFO. + * @{ + */ + +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) +/*! + * @brief Get the count of result kept in conversion FIFOn. + * + * @param base LPADC peripheral base address. + * @param index Result FIFO index. + * @return The count of result kept in conversion FIFOn. + */ +static inline uint32_t LPADC_GetConvResultCount(ADC_Type *base, uint8_t index) +{ + return (ADC_FCTRL_FCOUNT_MASK & base->FCTRL[index]) >> ADC_FCTRL_FCOUNT_SHIFT; +} + +/*! + * brief Get the result in conversion FIFOn. + * + * param base LPADC peripheral base address. + * param result Pointer to structure variable that keeps the conversion result in conversion FIFOn. + * param index Result FIFO index. + * + * return Status whether FIFOn entry is valid. + */ +bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result, uint8_t index); +#else +/*! + * @brief Get the count of result kept in conversion FIFO. + * + * @param base LPADC peripheral base address. + * @return The count of result kept in conversion FIFO. + */ +static inline uint32_t LPADC_GetConvResultCount(ADC_Type *base) +{ + return (ADC_FCTRL_FCOUNT_MASK & base->FCTRL) >> ADC_FCTRL_FCOUNT_SHIFT; +} + +/*! + * @brief Get the result in conversion FIFO. + * + * @param base LPADC peripheral base address. + * @param result Pointer to structure variable that keeps the conversion result in conversion FIFO. + * + * @return Status whether FIFO entry is valid. + */ +bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result); +#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ + +/*! + * @brief Configure the conversion trigger source. + * + * Each programmable trigger can launch the conversion command in command buffer. + * + * @param base LPADC peripheral base address. + * @param triggerId ID for each trigger. Typically, the available value range is from 0. + * @param config Pointer to configuration structure. See to #lpadc_conv_trigger_config_t. + */ +void LPADC_SetConvTriggerConfig(ADC_Type *base, uint32_t triggerId, const lpadc_conv_trigger_config_t *config); + +/*! + * @brief Gets an available pre-defined settings for trigger's configuration. + * + * This function initializes the trigger's configuration structure with an available settings. The default values are: + * @code + * config->commandIdSource = 0U; + * config->loopCountIndex = 0U; + * config->triggerIdSource = 0U; + * config->enableHardwareTrigger = false; + * @endcode + * @param config Pointer to configuration structure. + */ +void LPADC_GetDefaultConvTriggerConfig(lpadc_conv_trigger_config_t *config); + +/*! + * @brief Do software trigger to conversion command. + * + * @param base LPADC peripheral base address. + * @param triggerIdMask Mask value for software trigger indexes, which count from zero. + */ +static inline void LPADC_DoSoftwareTrigger(ADC_Type *base, uint32_t triggerIdMask) +{ + /* Writes to ADCx_SWTRIG register are ignored while ADCx_CTRL[ADCEN] is clear. */ + base->SWTRIG = triggerIdMask; +} + +/*! + * @brief Configure conversion command. + * + * @param base LPADC peripheral base address. + * @param commandId ID for command in command buffer. Typically, the available value range is 1 - 15. + * @param config Pointer to configuration structure. See to #lpadc_conv_command_config_t. + */ +void LPADC_SetConvCommandConfig(ADC_Type *base, uint32_t commandId, const lpadc_conv_command_config_t *config); + +/*! + * @brief Gets an available pre-defined settings for conversion command's configuration. + * + * This function initializes the conversion command's configuration structure with an available settings. The default + * values are: + * @code + * config->sampleScaleMode = kLPADC_SampleFullScale; + * config->channelSampleMode = kLPADC_SampleChannelSingleEndSideA; + * config->channelNumber = 0U; + * config->chainedNextCmdNumber = 0U; + * config->enableAutoChannelIncrement = false; + * config->loopCount = 0U; + * config->hardwareAverageMode = kLPADC_HardwareAverageCount1; + * config->sampleTimeMode = kLPADC_SampleTimeADCK3; + * config->hardwareCompareMode = kLPADC_HardwareCompareDisabled; + * config->hardwareCompareValueHigh = 0U; + * config->hardwareCompareValueLow = 0U; + * config->conversionResoultuionMode = kLPADC_ConversionResolutionStandard; + * config->enableWaitTrigger = false; + * @endcode + * @param config Pointer to configuration structure. + */ +void LPADC_GetDefaultConvCommandConfig(lpadc_conv_command_config_t *config); + +#if defined(FSL_FEATURE_LPADC_HAS_CFG_CALOFS) && FSL_FEATURE_LPADC_HAS_CFG_CALOFS +/*! + * @brief Enable the calibration function. + * + * When CALOFS is set, the ADC is configured to perform a calibration function anytime the ADC executes + * a conversion. Any channel selected is ignored and the value returned in the RESFIFO is a signed value + * between -31 and 31. -32 is not a valid and is never a returned value. Software should copy the lower 6- + * bits of the conversion result stored in the RESFIFO after a completed calibration conversion to the + * OFSTRIM field. The OFSTRIM field is used in normal operation for offset correction. + * + * @param base LPADC peripheral base address. + * @bool enable switcher to the calibration function. + */ +void LPADC_EnableCalibration(ADC_Type *base, bool enable); +#if defined(FSL_FEATURE_LPADC_HAS_OFSTRIM) && FSL_FEATURE_LPADC_HAS_OFSTRIM +/*! + * @brief Set proper offset value to trim ADC. + * + * To minimize the offset during normal operation, software should read the conversion result from + * the RESFIFO calibration operation and write the lower 6 bits to the OFSTRIM register. + * + * @param base LPADC peripheral base address. + * @param value Setting offset value. + */ +static inline void LPADC_SetOffsetValue(ADC_Type *base, uint32_t value) +{ + base->OFSTRIM = (value & ADC_OFSTRIM_OFSTRIM_MASK) >> ADC_OFSTRIM_OFSTRIM_SHIFT; +} + +/*! + * @brief Do auto calibration. + * + * Calibration function should be executed before using converter in application. It used the software trigger and a + * dummy conversion, get the offset and write them into the OFSTRIM register. It called some of functional API + * including: -LPADC_EnableCalibration(...) -LPADC_LPADC_SetOffsetValue(...) -LPADC_SetConvCommandConfig(...) + * -LPADC_SetConvTriggerConfig(...) + * + * @param base LPADC peripheral base address. + */ +void LPADC_DoAutoCalibration(ADC_Type *base); +#endif /* FSL_FEATURE_LPADC_HAS_OFSTRIM */ +#endif /* FSL_FEATURE_LPADC_HAS_CFG_CALOFS */ + +#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CALOFS) && FSL_FEATURE_LPADC_HAS_CTRL_CALOFS +#if defined(FSL_FEATURE_LPADC_HAS_OFSTRIM) && FSL_FEATURE_LPADC_HAS_OFSTRIM +/*! + * @brief Set proper offset value to trim ADC. + * + * Set the offset trim value for offset calibration manually. + * + * @param base LPADC peripheral base address. + * @param valueA Setting offset value A. + * @param valueB Setting offset value B. + * @note In normal adc sequence, the values are automatically calculated by LPADC_EnableOffsetCalibration. + */ +static inline void LPADC_SetOffsetValue(ADC_Type *base, uint32_t valueA, uint32_t valueB) +{ + base->OFSTRIM = ADC_OFSTRIM_OFSTRIM_A(valueA) | ADC_OFSTRIM_OFSTRIM_B(valueB); +} +#endif /* FSL_FEATURE_LPADC_HAS_OFSTRIM */ + +/*! + * @brief Enable the offset calibration function. + * + * @param base LPADC peripheral base address. + * @bool enable switcher to the calibration function. + */ +static inline void LPADC_EnableOffsetCalibration(ADC_Type *base, bool enable) +{ + if (enable) + { + base->CTRL |= ADC_CTRL_CALOFS_MASK; + } + else + { + base->CTRL &= ~ADC_CTRL_CALOFS_MASK; + } +} + +/*! + * @brief Do offset calibration. + * + * @param base LPADC peripheral base address. + */ +void LPADC_DoOffsetCalibration(ADC_Type *base); + +#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ +/*! + * brief Do auto calibration. + * + * param base LPADC peripheral base address. + */ +void LPADC_DoAutoCalibration(ADC_Type *base); +#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ */ +#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CALOFS */ +/* @} */ + +#if defined(__cplusplus) +} +#endif +/*! + * @} + */ +#endif /* _FSL_LPADC_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_mailbox.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_mailbox.h new file mode 100644 index 000000000..a73554252 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_mailbox.h @@ -0,0 +1,214 @@ +/* + * Copyright 2014, NXP + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_MAILBOX_H_ +#define _FSL_MAILBOX_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup mailbox + * @{ + */ + +/*! @file */ + +/****************************************************************************** + * Definitions + *****************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.mailbox" +#endif + +/*! @name Driver version */ +/*@{*/ +/*! @brief MAILBOX driver version 2.1.0. */ +#define FSL_MAILBOX_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) +/*@}*/ + +/*! + * @brief CPU ID. + */ +#if (defined(LPC55S69_cm33_core0_SERIES) || defined(LPC55S69_cm33_core1_SERIES)) +typedef enum _mailbox_cpu_id +{ + kMAILBOX_CM33_Core1 = 0, + kMAILBOX_CM33_Core0 +} mailbox_cpu_id_t; +#else +typedef enum _mailbox_cpu_id +{ + kMAILBOX_CM0Plus = 0, + kMAILBOX_CM4 +} mailbox_cpu_id_t; +#endif +/******************************************************************************* + * API + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * @name MAILBOX initialization + * @{ + */ + +/*! + * @brief Initializes the MAILBOX module. + * + * This function enables the MAILBOX clock only. + * + * @param base MAILBOX peripheral base address. + */ +static inline void MAILBOX_Init(MAILBOX_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + CLOCK_EnableClock(kCLOCK_Mailbox); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#if !(defined(FSL_FEATURE_MAILBOX_HAS_NO_RESET) && FSL_FEATURE_MAILBOX_HAS_NO_RESET) + /* Reset the MAILBOX module */ + RESET_PeripheralReset(kMAILBOX_RST_SHIFT_RSTn); +#endif +} + +/*! + * @brief De-initializes the MAILBOX module. + * + * This function disables the MAILBOX clock only. + * + * @param base MAILBOX peripheral base address. + */ +static inline void MAILBOX_Deinit(MAILBOX_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + CLOCK_DisableClock(kCLOCK_Mailbox); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/* @} */ + +/*! + * @brief Set data value in the mailbox based on the CPU ID. + * + * @param base MAILBOX peripheral base address. + * @param cpu_id CPU id, kMAILBOX_CM0Plus or kMAILBOX_CM4 for LPC5410x and LPC5411x devices, + * kMAILBOX_CM33_Core0 or kMAILBOX_CM33_Core1 for LPC55S69 devices. + * @param mboxData Data to send in the mailbox. + * + * @note Sets a data value to send via the MAILBOX to the other core. + */ +static inline void MAILBOX_SetValue(MAILBOX_Type *base, mailbox_cpu_id_t cpu_id, uint32_t mboxData) +{ +#if (defined(LPC55S69_cm33_core0_SERIES) || defined(LPC55S69_cm33_core1_SERIES)) + assert((cpu_id == kMAILBOX_CM33_Core0) || (cpu_id == kMAILBOX_CM33_Core1)); +#else + assert((cpu_id == kMAILBOX_CM0Plus) || (cpu_id == kMAILBOX_CM4)); +#endif + base->MBOXIRQ[cpu_id].IRQ = mboxData; +} + +/*! + * @brief Get data in the mailbox based on the CPU ID. + * + * @param base MAILBOX peripheral base address. + * @param cpu_id CPU id, kMAILBOX_CM0Plus or kMAILBOX_CM4 for LPC5410x and LPC5411x devices, + * kMAILBOX_CM33_Core0 or kMAILBOX_CM33_Core1 for LPC55S69 devices. + * + * @return Current mailbox data. + */ +static inline uint32_t MAILBOX_GetValue(MAILBOX_Type *base, mailbox_cpu_id_t cpu_id) +{ +#if (defined(LPC55S69_cm33_core0_SERIES) || defined(LPC55S69_cm33_core1_SERIES)) + assert((cpu_id == kMAILBOX_CM33_Core0) || (cpu_id == kMAILBOX_CM33_Core1)); +#else + assert((cpu_id == kMAILBOX_CM0Plus) || (cpu_id == kMAILBOX_CM4)); +#endif + return base->MBOXIRQ[cpu_id].IRQ; +} + +/*! + * @brief Set data bits in the mailbox based on the CPU ID. + * + * @param base MAILBOX peripheral base address. + * @param cpu_id CPU id, kMAILBOX_CM0Plus or kMAILBOX_CM4 for LPC5410x and LPC5411x devices, + * kMAILBOX_CM33_Core0 or kMAILBOX_CM33_Core1 for LPC55S69 devices. + * @param mboxSetBits Data bits to set in the mailbox. + * + * @note Sets data bits to send via the MAILBOX to the other core. A value of 0 will + * do nothing. Only sets bits selected with a 1 in it's bit position. + */ +static inline void MAILBOX_SetValueBits(MAILBOX_Type *base, mailbox_cpu_id_t cpu_id, uint32_t mboxSetBits) +{ +#if (defined(LPC55S69_cm33_core0_SERIES) || defined(LPC55S69_cm33_core1_SERIES)) + assert((cpu_id == kMAILBOX_CM33_Core0) || (cpu_id == kMAILBOX_CM33_Core1)); +#else + assert((cpu_id == kMAILBOX_CM0Plus) || (cpu_id == kMAILBOX_CM4)); +#endif + base->MBOXIRQ[cpu_id].IRQSET = mboxSetBits; +} + +/*! + * @brief Clear data bits in the mailbox based on the CPU ID. + * + * @param base MAILBOX peripheral base address. + * @param cpu_id CPU id, kMAILBOX_CM0Plus or kMAILBOX_CM4 for LPC5410x and LPC5411x devices, + * kMAILBOX_CM33_Core0 or kMAILBOX_CM33_Core1 for LPC55S69 devices. + * @param mboxClrBits Data bits to clear in the mailbox. + * + * @note Clear data bits to send via the MAILBOX to the other core. A value of 0 will + * do nothing. Only clears bits selected with a 1 in it's bit position. + */ +static inline void MAILBOX_ClearValueBits(MAILBOX_Type *base, mailbox_cpu_id_t cpu_id, uint32_t mboxClrBits) +{ +#if (defined(LPC55S69_cm33_core0_SERIES) || defined(LPC55S69_cm33_core1_SERIES)) + assert((cpu_id == kMAILBOX_CM33_Core0) || (cpu_id == kMAILBOX_CM33_Core1)); +#else + assert((cpu_id == kMAILBOX_CM0Plus) || (cpu_id == kMAILBOX_CM4)); +#endif + base->MBOXIRQ[cpu_id].IRQCLR = mboxClrBits; +} + +/*! + * @brief Get MUTEX state and lock mutex + * + * @param base MAILBOX peripheral base address. + * + * @return See note + * + * @note Returns '1' if the mutex was taken or '0' if another resources has the + * mutex locked. Once a mutex is taken, it can be returned with the MAILBOX_SetMutex() + * function. + */ +static inline uint32_t MAILBOX_GetMutex(MAILBOX_Type *base) +{ + return (base->MUTEX & MAILBOX_MUTEX_EX_MASK); +} + +/*! + * @brief Set MUTEX state + * + * @param base MAILBOX peripheral base address. + * + * @note Sets mutex state to '1' and allows other resources to get the mutex. + */ +static inline void MAILBOX_SetMutex(MAILBOX_Type *base) +{ + base->MUTEX = MAILBOX_MUTEX_EX_MASK; +} + +#if defined(__cplusplus) +} +#endif /*_cplusplus*/ +/*@}*/ + +#endif /* _FSL_MAILBOX_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_mrt.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_mrt.c new file mode 100644 index 000000000..8306b33e7 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_mrt.c @@ -0,0 +1,150 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_mrt.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.mrt" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Gets the instance from the base address + * + * @param base Multi-Rate timer peripheral base address + * + * @return The MRT instance + */ +static uint32_t MRT_GetInstance(MRT_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to MRT bases for each instance. */ +static MRT_Type *const s_mrtBases[] = MRT_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to MRT clocks for each instance. */ +static const clock_ip_name_t s_mrtClocks[] = MRT_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) +#if defined(FSL_FEATURE_MRT_WRITE_ZERO_ASSERT_RESET) && FSL_FEATURE_MRT_WRITE_ZERO_ASSERT_RESET +/*! @brief Pointers to MRT resets for each instance, writing a zero asserts the reset */ +static const reset_ip_name_t s_mrtResets[] = MRT_RSTS_N; +#else +/*! @brief Pointers to MRT resets for each instance, writing a one asserts the reset */ +static const reset_ip_name_t s_mrtResets[] = MRT_RSTS; +#endif +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t MRT_GetInstance(MRT_Type *base) +{ + uint32_t instance; + uint32_t mrtArrayCount = (sizeof(s_mrtBases) / sizeof(s_mrtBases[0])); + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < mrtArrayCount; instance++) + { + if (s_mrtBases[instance] == base) + { + break; + } + } + + assert(instance < mrtArrayCount); + + return instance; +} + +/*! + * brief Ungates the MRT clock and configures the peripheral for basic operation. + * + * note This API should be called at the beginning of the application using the MRT driver. + * + * param base Multi-Rate timer peripheral base address + * param config Pointer to user's MRT config structure. If MRT has MULTITASK bit field in + * MODCFG reigster, param config is useless. + */ +void MRT_Init(MRT_Type *base, const mrt_config_t *config) +{ + assert(config); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate the MRT clock */ + CLOCK_EnableClock(s_mrtClocks[MRT_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) + /* Reset the module. */ + RESET_PeripheralReset(s_mrtResets[MRT_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + +#if !(defined(FSL_FEATURE_MRT_HAS_NO_MODCFG_MULTITASK) && FSL_FEATURE_MRT_HAS_NO_MODCFG_MULTITASK) + /* Set timer operating mode */ + base->MODCFG = MRT_MODCFG_MULTITASK(config->enableMultiTask); +#endif +} + +/*! + * brief Gate the MRT clock + * + * param base Multi-Rate timer peripheral base address + */ +void MRT_Deinit(MRT_Type *base) +{ + /* Stop all the timers */ + MRT_StopTimer(base, kMRT_Channel_0); + MRT_StopTimer(base, kMRT_Channel_1); +#if (FSL_FEATURE_MRT_NUMBER_OF_CHANNELS > 2U) + MRT_StopTimer(base, kMRT_Channel_2); +#endif +#if (FSL_FEATURE_MRT_NUMBER_OF_CHANNELS > 3U) + MRT_StopTimer(base, kMRT_Channel_3); +#endif + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Gate the MRT clock*/ + CLOCK_DisableClock(s_mrtClocks[MRT_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Used to update the timer period in units of count. + * + * The new value will be immediately loaded or will be loaded at the end of the current time + * interval. For one-shot interrupt mode the new value will be immediately loaded. + * + * note User can call the utility macros provided in fsl_common.h to convert to ticks + * + * param base Multi-Rate timer peripheral base address + * param channel Timer channel number + * param count Timer period in units of ticks + * param immediateLoad true: Load the new value immediately into the TIMER register; + * false: Load the new value at the end of current timer interval + */ +void MRT_UpdateTimerPeriod(MRT_Type *base, mrt_chnl_t channel, uint32_t count, bool immediateLoad) +{ + assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); + + uint32_t newValue = count; + if (((base->CHANNEL[channel].CTRL & MRT_CHANNEL_CTRL_MODE_MASK) == kMRT_OneShotMode) || (immediateLoad)) + { + /* For one-shot interrupt mode, load the new value immediately even if user forgot to enable */ + newValue |= MRT_CHANNEL_INTVAL_LOAD_MASK; + } + + /* Update the timer interval value */ + base->CHANNEL[channel].INTVAL = newValue; +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_mrt.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_mrt.h new file mode 100644 index 000000000..2e90d01d5 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_mrt.h @@ -0,0 +1,366 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_MRT_H_ +#define _FSL_MRT_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup mrt + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_MRT_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*!< Version 2.0.1 */ +/*@}*/ + +/*! @brief List of MRT channels */ +typedef enum _mrt_chnl +{ + kMRT_Channel_0 = 0U, /*!< MRT channel number 0*/ + kMRT_Channel_1, /*!< MRT channel number 1 */ + kMRT_Channel_2, /*!< MRT channel number 2 */ + kMRT_Channel_3 /*!< MRT channel number 3 */ +} mrt_chnl_t; + +/*! @brief List of MRT timer modes */ +typedef enum _mrt_timer_mode +{ + kMRT_RepeatMode = (0 << MRT_CHANNEL_CTRL_MODE_SHIFT), /*!< Repeat Interrupt mode */ + kMRT_OneShotMode = (1 << MRT_CHANNEL_CTRL_MODE_SHIFT), /*!< One-shot Interrupt mode */ + kMRT_OneShotStallMode = (2 << MRT_CHANNEL_CTRL_MODE_SHIFT) /*!< One-shot stall mode */ +} mrt_timer_mode_t; + +/*! @brief List of MRT interrupts */ +typedef enum _mrt_interrupt_enable +{ + kMRT_TimerInterruptEnable = MRT_CHANNEL_CTRL_INTEN_MASK /*!< Timer interrupt enable*/ +} mrt_interrupt_enable_t; + +/*! @brief List of MRT status flags */ +typedef enum _mrt_status_flags +{ + kMRT_TimerInterruptFlag = MRT_CHANNEL_STAT_INTFLAG_MASK, /*!< Timer interrupt flag */ + kMRT_TimerRunFlag = MRT_CHANNEL_STAT_RUN_MASK, /*!< Indicates state of the timer */ +} mrt_status_flags_t; + +/*! + * @brief MRT configuration structure + * + * This structure holds the configuration settings for the MRT peripheral. To initialize this + * structure to reasonable defaults, call the MRT_GetDefaultConfig() function and pass a + * pointer to your config structure instance. + * + * The config struct can be made const so it resides in flash + */ +typedef struct _mrt_config +{ + bool enableMultiTask; /*!< true: Timers run in multi-task mode; false: Timers run in hardware status mode */ +} mrt_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Ungates the MRT clock and configures the peripheral for basic operation. + * + * @note This API should be called at the beginning of the application using the MRT driver. + * + * @param base Multi-Rate timer peripheral base address + * @param config Pointer to user's MRT config structure. If MRT has MULTITASK bit field in + * MODCFG reigster, param config is useless. + */ +void MRT_Init(MRT_Type *base, const mrt_config_t *config); + +/*! + * @brief Gate the MRT clock + * + * @param base Multi-Rate timer peripheral base address + */ +void MRT_Deinit(MRT_Type *base); + +/*! + * @brief Fill in the MRT config struct with the default settings + * + * The default values are: + * @code + * config->enableMultiTask = false; + * @endcode + * @param config Pointer to user's MRT config structure. + */ +static inline void MRT_GetDefaultConfig(mrt_config_t *config) +{ + assert(config); +#if !(defined(FSL_FEATURE_MRT_HAS_NO_MODCFG_MULTITASK) && FSL_FEATURE_MRT_HAS_NO_MODCFG_MULTITASK) + /* Use hardware status operating mode */ + config->enableMultiTask = false; +#endif +} + +/*! + * @brief Sets up an MRT channel mode. + * + * @param base Multi-Rate timer peripheral base address + * @param channel Channel that is being configured. + * @param mode Timer mode to use for the channel. + */ +static inline void MRT_SetupChannelMode(MRT_Type *base, mrt_chnl_t channel, const mrt_timer_mode_t mode) +{ + assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); + + uint32_t reg = base->CHANNEL[channel].CTRL; + + /* Clear old value */ + reg &= ~MRT_CHANNEL_CTRL_MODE_MASK; + /* Add the new mode */ + reg |= mode; + + base->CHANNEL[channel].CTRL = reg; +} + +/*! @}*/ + +/*! + * @name Interrupt Interface + * @{ + */ + +/*! + * @brief Enables the MRT interrupt. + * + * @param base Multi-Rate timer peripheral base address + * @param channel Timer channel number + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::mrt_interrupt_enable_t + */ +static inline void MRT_EnableInterrupts(MRT_Type *base, mrt_chnl_t channel, uint32_t mask) +{ + assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); + base->CHANNEL[channel].CTRL |= mask; +} + +/*! + * @brief Disables the selected MRT interrupt. + * + * @param base Multi-Rate timer peripheral base address + * @param channel Timer channel number + * @param mask The interrupts to disable. This is a logical OR of members of the + * enumeration ::mrt_interrupt_enable_t + */ +static inline void MRT_DisableInterrupts(MRT_Type *base, mrt_chnl_t channel, uint32_t mask) +{ + assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); + base->CHANNEL[channel].CTRL &= ~mask; +} + +/*! + * @brief Gets the enabled MRT interrupts. + * + * @param base Multi-Rate timer peripheral base address + * @param channel Timer channel number + * + * @return The enabled interrupts. This is the logical OR of members of the + * enumeration ::mrt_interrupt_enable_t + */ +static inline uint32_t MRT_GetEnabledInterrupts(MRT_Type *base, mrt_chnl_t channel) +{ + assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); + return (base->CHANNEL[channel].CTRL & MRT_CHANNEL_CTRL_INTEN_MASK); +} + +/*! @}*/ + +/*! + * @name Status Interface + * @{ + */ + +/*! + * @brief Gets the MRT status flags + * + * @param base Multi-Rate timer peripheral base address + * @param channel Timer channel number + * + * @return The status flags. This is the logical OR of members of the + * enumeration ::mrt_status_flags_t + */ +static inline uint32_t MRT_GetStatusFlags(MRT_Type *base, mrt_chnl_t channel) +{ + assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); + return (base->CHANNEL[channel].STAT & (MRT_CHANNEL_STAT_INTFLAG_MASK | MRT_CHANNEL_STAT_RUN_MASK)); +} + +/*! + * @brief Clears the MRT status flags. + * + * @param base Multi-Rate timer peripheral base address + * @param channel Timer channel number + * @param mask The status flags to clear. This is a logical OR of members of the + * enumeration ::mrt_status_flags_t + */ +static inline void MRT_ClearStatusFlags(MRT_Type *base, mrt_chnl_t channel, uint32_t mask) +{ + assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); + base->CHANNEL[channel].STAT = (mask & MRT_CHANNEL_STAT_INTFLAG_MASK); +} + +/*! @}*/ + +/*! + * @name Read and Write the timer period + * @{ + */ + +/*! + * @brief Used to update the timer period in units of count. + * + * The new value will be immediately loaded or will be loaded at the end of the current time + * interval. For one-shot interrupt mode the new value will be immediately loaded. + * + * @note User can call the utility macros provided in fsl_common.h to convert to ticks + * + * @param base Multi-Rate timer peripheral base address + * @param channel Timer channel number + * @param count Timer period in units of ticks + * @param immediateLoad true: Load the new value immediately into the TIMER register; + * false: Load the new value at the end of current timer interval + */ +void MRT_UpdateTimerPeriod(MRT_Type *base, mrt_chnl_t channel, uint32_t count, bool immediateLoad); + +/*! + * @brief Reads the current timer counting value. + * + * This function returns the real-time timer counting value, in a range from 0 to a + * timer period. + * + * @note User can call the utility macros provided in fsl_common.h to convert ticks to usec or msec + * + * @param base Multi-Rate timer peripheral base address + * @param channel Timer channel number + * + * @return Current timer counting value in ticks + */ +static inline uint32_t MRT_GetCurrentTimerCount(MRT_Type *base, mrt_chnl_t channel) +{ + assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); + return base->CHANNEL[channel].TIMER; +} + +/*! @}*/ + +/*! + * @name Timer Start and Stop + * @{ + */ + +/*! + * @brief Starts the timer counting. + * + * After calling this function, timers load period value, counts down to 0 and + * depending on the timer mode it will either load the respective start value again or stop. + * + * @note User can call the utility macros provided in fsl_common.h to convert to ticks + * + * @param base Multi-Rate timer peripheral base address + * @param channel Timer channel number. + * @param count Timer period in units of ticks + */ +static inline void MRT_StartTimer(MRT_Type *base, mrt_chnl_t channel, uint32_t count) +{ + assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); + assert(count < MRT_CHANNEL_INTVAL_IVALUE_MASK); + /* Write the timer interval value */ + base->CHANNEL[channel].INTVAL = count; +} + +/*! + * @brief Stops the timer counting. + * + * This function stops the timer from counting. + * + * @param base Multi-Rate timer peripheral base address + * @param channel Timer channel number. + */ +static inline void MRT_StopTimer(MRT_Type *base, mrt_chnl_t channel) +{ + assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); + /* Stop the timer immediately */ + base->CHANNEL[channel].INTVAL = MRT_CHANNEL_INTVAL_LOAD_MASK; +} + +/*! @}*/ + +/*! + * @name Get & release channel + * @{ + */ + +/*! + * @brief Find the available channel. + * + * This function returns the lowest available channel number. + * + * @param base Multi-Rate timer peripheral base address + */ +static inline uint32_t MRT_GetIdleChannel(MRT_Type *base) +{ + return base->IDLE_CH; +} + +#if !(defined(FSL_FEATURE_MRT_HAS_NO_CHANNEL_STAT_INUSE) && FSL_FEATURE_MRT_HAS_NO_CHANNEL_STAT_INUSE) +/*! + * @brief Release the channel when the timer is using the multi-task mode. + * + * In multi-task mode, the INUSE flags allow more control over when MRT channels are released for + * further use. The user can hold on to a channel acquired by calling MRT_GetIdleChannel() for as + * long as it is needed and release it by calling this function. This removes the need to ask for + * an available channel for every use. + * + * @param base Multi-Rate timer peripheral base address + * @param channel Timer channel number. + */ +static inline void MRT_ReleaseChannel(MRT_Type *base, mrt_chnl_t channel) +{ + assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); + + uint32_t reg = base->CHANNEL[channel].STAT; + + /* Clear flag bits to prevent accidentally clearing anything when writing back */ + reg = ~MRT_CHANNEL_STAT_INTFLAG_MASK; + reg |= MRT_CHANNEL_STAT_INUSE_MASK; + + base->CHANNEL[channel].STAT = reg; +} +#endif + +/*! @}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_MRT_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_ostimer.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_ostimer.c new file mode 100644 index 000000000..27c86c005 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_ostimer.c @@ -0,0 +1,266 @@ +/* + * Copyright 2018-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_ostimer.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.ostimer" +#endif + +/* Typedef for interrupt handler. */ +typedef void (*ostimer_isr_t)(OSTIMER_Type *base, ostimer_callback_t cb); + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Gets the instance from the base address + * + * @param base OSTIMER peripheral base address + * + * @return The OSTIMER instance + */ +static uint32_t OSTIMER_GetInstance(OSTIMER_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* Array of OSTIMER handle. */ +static ostimer_callback_t s_ostimerHandle[FSL_FEATURE_SOC_OSTIMER_COUNT]; +/* Array of OSTIMER peripheral base address. */ +static OSTIMER_Type *const s_ostimerBases[] = OSTIMER_BASE_PTRS; +/* Array of OSTIMER IRQ number. */ +static const IRQn_Type s_ostimerIRQ[] = OSTIMER_IRQS; +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/* Array of OSTIMER clock name. */ +static const clock_ip_name_t s_ostimerClock[] = OSTIMER_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/* OSTIMER ISR for transactional APIs. */ +static ostimer_isr_t s_ostimerIsr; + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* @brief Function for getting the instance number of OS timer. */ +static uint32_t OSTIMER_GetInstance(OSTIMER_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_ostimerBases); instance++) + { + if (s_ostimerBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_ostimerBases)); + + return instance; +} + +/* @brief Translate the value from gray-code to decimal. */ +static uint64_t OSTIMER_GrayToDecimal(uint64_t gray) +{ + uint64_t temp = gray; + while (temp) + { + temp >>= 1U; + gray ^= temp; + } + + return gray; +} + +/* @brief Translate the value from decimal to gray-code. */ +static uint64_t OSTIMER_DecimalToGray(uint64_t dec) +{ + return (dec ^ (dec >> 1U)); +} + +/*! + * @brief Initializes an OSTIMER by turning it's clock on. + * + */ +void OSTIMER_Init(OSTIMER_Type *base) +{ + assert(base); + + uint32_t instance = OSTIMER_GetInstance(base); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +#if !(defined(FSL_FEATURE_PMC_HAS_NO_OSTIMER_REG) && FSL_FEATURE_PMC_HAS_NO_OSTIMER_REG) + /* Enable the OSTIMER 32k clock in PMC module. */ + PMC->OSTIMERr |= PMC_OSTIMER_CLOCKENABLE_MASK; + PMC->OSTIMERr &= ~PMC_OSTIMER_OSC32KPD_MASK; +#endif + /* Enable clock for OSTIMER. */ + CLOCK_EnableClock(s_ostimerClock[instance]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * @brief Deinitializes a OSTIMER instance. + * + * This function shuts down OSTIMER clock + * + * @param base OSTIMER peripheral base address. + */ +void OSTIMER_Deinit(OSTIMER_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable clock for OSTIMER. */ + CLOCK_DisableClock(s_ostimerClock[OSTIMER_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * @brief Get OSTIMER status Flags. + * + * This returns the status flag. + * Currently, only match interrupt flag can be got. + * + * @param base OSTIMER peripheral base address. + * @return status register value + */ +uint32_t OSTIMER_GetStatusFlags(OSTIMER_Type *base) +{ + return base->OSEVENT_CTRL & OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK; +} + +/*! + * @brief Clear Status Interrupt Flags. + * + * This clears intr status flag. + * Currently, only match interrupt flag can be cleared. + * + * @param base OSTIMER peripheral base address. + * @return none + */ +void OSTIMER_ClearStatusFlags(OSTIMER_Type *base, uint32_t mask) +{ + base->OSEVENT_CTRL |= mask; +} + +/*! + * @brief Set the match raw value for OSTIMER. + * + * This function will set a match value for OSTIMER with an optional callback. And this callback + * will be called while the data in dedicated pair match register is equals to the value of central EVTIMER. + * Please note that, the data format is gray-code, if decimal data was desired, please using OSTIMER_SetMatchValue(). + * + * @param base OSTIMER peripheral base address. + * @param count OSTIMER timer match value.(Value is gray-code format) + * + * @param cb OSTIMER callback (can be left as NULL if none, otherwise should be a void func(void)). + * @return none + */ +void OSTIMER_SetMatchRawValue(OSTIMER_Type *base, uint64_t count, ostimer_callback_t cb) +{ + uint64_t tmp = count; + uint32_t instance = OSTIMER_GetInstance(base); + s_ostimerIsr = OSTIMER_HandleIRQ; + s_ostimerHandle[instance] = cb; + + /* Set the match value. */ + base->MATCHN_L = tmp; + base->MATCHN_H = tmp >> 32U; + + /* Enable IRQ for generating call back function. */ + base->OSEVENT_CTRL |= OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK; +#if !(defined(FSL_FEATURE_PMC_HAS_NO_OSTIMER_REG) && FSL_FEATURE_PMC_HAS_NO_OSTIMER_REG) + PMC->OSTIMERr |= PMC_OSTIMER_DPDWAKEUPENABLE_MASK; +#endif + + EnableIRQ(s_ostimerIRQ[instance]); +} + +/*! + * @brief Set the match value for OSTIMER. + * + * This function will set a match value for OSTIMER with an optional callback. And this callback + * will be called while the data in dedicated pair match register is equals to the value of central EVTIMER. + * + * @param base OSTIMER peripheral base address. + * @param count OSTIMER timer match value.(Value is decimal format, and this value will be translate to Gray code in + * API. ) + * @param cb OSTIMER callback (can be left as NULL if none, otherwise should be a void func(void)). + * @return none + */ +void OSTIMER_SetMatchValue(OSTIMER_Type *base, uint64_t count, ostimer_callback_t cb) +{ + uint64_t tmp = OSTIMER_DecimalToGray(count); + + OSTIMER_SetMatchRawValue(base, tmp, cb); +} + +/*! + * @brief Get current timer count value from OSTIMER. + * + * This function will get a decimal timer count value. + * The RAW value of timer count is gray code format, will be translated to decimal data internally. + * + * @param base OSTIMER peripheral base address. + * @return Value of OSTIMER which will formated to decimal value. + */ +uint64_t OSTIMER_GetCurrentTimerValue(OSTIMER_Type *base) +{ + uint64_t tmp = 0U; + + tmp = OSTIMER_GetCurrentTimerRawValue(base); + + return OSTIMER_GrayToDecimal(tmp); +} + +/*! + * @brief Get the capture value from OSTIMER. + * + * This function will get a capture decimal-value from OSTIMER. + * The RAW value of timer capture is gray code format, will be translated to decimal data internally. + * + * @param base OSTIMER peripheral base address. + * @return Value of capture register, data format is decimal. + */ +uint64_t OSTIMER_GetCaptureValue(OSTIMER_Type *base) +{ + uint64_t tmp = 0U; + + tmp = OSTIMER_GetCaptureRawValue(base); + + return OSTIMER_GrayToDecimal(tmp); +} + +void OSTIMER_HandleIRQ(OSTIMER_Type *base, ostimer_callback_t cb) +{ + /* Clear the match interrupt flag. */ + OSTIMER_ClearStatusFlags(base, kOSTIMER_MatchInterruptFlag); + + if (cb) + { + cb(); + } +} + +#if defined(OSTIMER) +void OS_EVENT_DriverIRQHandler(void) +{ + s_ostimerIsr(OSTIMER, s_ostimerHandle[0]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_ostimer.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_ostimer.h new file mode 100644 index 000000000..b7191c1c2 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_ostimer.h @@ -0,0 +1,217 @@ +/* + * Copyright 2018-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_OSTIMER_H_ +#define _FSL_OSTIMER_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup ostimer + * @{ + */ + +/*! @file*/ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief OSTIMER driver version 2.0.1. */ +#define FSL_OSTIMER_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/*! + * @brief OSTIMER status flags. + */ +enum _ostimer_flags +{ + kOSTIMER_MatchInterruptFlag = (OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK), /*!< Match interrupt flag bit, sets if + the match value was reached. */ +}; + +/*! @brief ostimer callback function. */ +typedef void (*ostimer_callback_t)(void); + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* _cplusplus */ + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initializes an OSTIMER by turning its bus clock on + * + */ +void OSTIMER_Init(OSTIMER_Type *base); + +/*! + * @brief Deinitializes a OSTIMER instance. + * + * This function shuts down OSTIMER bus clock + * + * @param base OSTIMER peripheral base address. + */ +void OSTIMER_Deinit(OSTIMER_Type *base); + +/*! + * @brief OSTIMER software reset. + * + * This function will use software to trigger an OSTIMER reset. + * Please note that, the OS timer reset bit was in PMC->OSTIMERr register. + * + * @param base OSTIMER peripheral base address. + */ +static inline void OSTIMER_SoftwareReset(OSTIMER_Type *base) +{ +#if !(defined(FSL_FEATURE_PMC_HAS_NO_OSTIMER_REG) && FSL_FEATURE_PMC_HAS_NO_OSTIMER_REG) + PMC->OSTIMERr |= PMC_OSTIMER_SOFTRESET_MASK; + PMC->OSTIMERr &= ~PMC_OSTIMER_SOFTRESET_MASK; +#endif +} + +/*! + * @brief Get OSTIMER status Flags. + * + * This returns the status flag. + * Currently, only match interrupt flag can be got. + * + * @param base OSTIMER peripheral base address. + * @return status register value + */ +uint32_t OSTIMER_GetStatusFlags(OSTIMER_Type *base); + +/*! + * @brief Clear Status Interrupt Flags. + * + * This clears intrrupt status flag. + * Currently, only match interrupt flag can be cleared. + * + * @param base OSTIMER peripheral base address. + * @return none + */ +void OSTIMER_ClearStatusFlags(OSTIMER_Type *base, uint32_t mask); + +/*! + * @brief Set the match raw value for OSTIMER. + * + * This function will set a match value for OSTIMER with an optional callback. And this callback + * will be called while the data in dedicated pair match register is equals to the value of central EVTIMER. + * Please note that, the data format is gray-code, if decimal data was desired, please using OSTIMER_SetMatchValue(). + * + * @param base OSTIMER peripheral base address. + * @param count OSTIMER timer match value.(Value is gray-code format) + * + * @param cb OSTIMER callback (can be left as NULL if none, otherwise should be a void func(void)). + * @return none + */ +void OSTIMER_SetMatchRawValue(OSTIMER_Type *base, uint64_t count, ostimer_callback_t cb); + +/*! + * @brief Set the match value for OSTIMER. + * + * This function will set a match value for OSTIMER with an optional callback. And this callback + * will be called while the data in dedicated pair match register is equals to the value of central OS TIMER. + * + * @param base OSTIMER peripheral base address. + * @param count OSTIMER timer match value.(Value is decimal format, and this value will be translate to Gray code + * internally.) + * + * @param cb OSTIMER callback (can be left as NULL if none, otherwise should be a void func(void)). + * @return none + */ +void OSTIMER_SetMatchValue(OSTIMER_Type *base, uint64_t count, ostimer_callback_t cb); + +/*! + * @brief Get current timer raw count value from OSTIMER. + * + * This function will get a gray code type timer count value from OS timer register. + * The raw value of timer count is gray code format. + * + * @param base OSTIMER peripheral base address. + * @return Raw value of OSTIMER, gray code format. + */ +static inline uint64_t OSTIMER_GetCurrentTimerRawValue(OSTIMER_Type *base) +{ + uint64_t tmp = 0U; + + tmp = base->EVTIMERL; + tmp |= (uint64_t)(base->EVTIMERH) << 32U; + + return tmp; +} + +/*! + * @brief Get current timer count value from OSTIMER. + * + * This function will get a decimal timer count value. + * The RAW value of timer count is gray code format, will be translated to decimal data internally. + * + * @param base OSTIMER peripheral base address. + * @return Value of OSTIMER which will be formated to decimal value. + */ +uint64_t OSTIMER_GetCurrentTimerValue(OSTIMER_Type *base); + +/*! + * @brief Get the capture value from OSTIMER. + * + * This function will get a captured gray-code value from OSTIMER. + * The Raw value of timer capture is gray code format. + * + * @param base OSTIMER peripheral base address. + * @return Raw value of capture register, data format is gray code. + */ +static inline uint64_t OSTIMER_GetCaptureRawValue(OSTIMER_Type *base) +{ + uint64_t tmp = 0U; + + tmp = base->CAPTUREN_L; + tmp |= (uint64_t)(base->CAPTUREN_H) << 32U; + + return tmp; +} + +/*! + * @brief Get the capture value from OSTIMER. + * + * This function will get a capture decimal-value from OSTIMER. + * The RAW value of timer capture is gray code format, will be translated to decimal data internally. + * + * @param base OSTIMER peripheral base address. + * @return Value of capture register, data format is decimal. + */ +uint64_t OSTIMER_GetCaptureValue(OSTIMER_Type *base); + +/*! + * @brief OS timer interrupt Service Handler. + * + * This function handles the interrupt and refers to the callback array in the driver to callback user (as per request + * in OSTIMER_SetMatchValue()). + * if no user callback is scheduled, the interrupt will simply be cleared. + * + * @param base OS timer peripheral base address. + * @param cb callback scheduled for this instance of OS timer + * @return none + */ +void OSTIMER_HandleIRQ(OSTIMER_Type *base, ostimer_callback_t cb); +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_OSTIMER_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_pint.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_pint.c new file mode 100644 index 000000000..e651702a9 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_pint.c @@ -0,0 +1,855 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_pint.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.pint" +#endif + +/******************************************************************************* + * Variables + ******************************************************************************/ + +#if defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) +/*! @brief Irq number array */ +static const IRQn_Type s_pintIRQ[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS + + FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS] = PINT_IRQS; + +/*! @brief Callback function array for PINT(s). */ +static pint_cb_t + s_pintCallback[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS + FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS]; +#else +/*! @brief Irq number array */ +static const IRQn_Type s_pintIRQ[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS] = PINT_IRQS; + +/*! @brief Callback function array for PINT(s). */ +static pint_cb_t s_pintCallback[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS]; +#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * brief Initialize PINT peripheral. + + * This function initializes the PINT peripheral and enables the clock. + * + * param base Base address of the PINT peripheral. + * + * retval None. + */ +void PINT_Init(PINT_Type *base) +{ + uint32_t i; + uint32_t pmcfg; + uint8_t pintcount; + assert(base); + pmcfg = 0; + +#if defined(SECPINT) + pintcount = SEC_PINT_PIN_INT_COUNT; +#else + pintcount = PINT_PIN_INT_COUNT; +#endif /* SECPINT */ + + for (i = 0; i < FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) + { + s_pintCallback[i] = NULL; + } + + /* Disable all bit slices for pint*/ + for (i = 0; i < pintcount; i++) + { + pmcfg = pmcfg | (kPINT_PatternMatchNever << (PININT_BITSLICE_CFG_START + (i * 3U))); + } + +#if defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 1) +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock. */ + CLOCK_EnableClock(kCLOCK_GpioInt); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) + /* Reset the module. */ + RESET_PeripheralReset(kGPIOINT_RST_N_SHIFT_RSTn); +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + +#elif defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 0) +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock. */ + CLOCK_EnableClock(kCLOCK_Gpio0); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) + /* Reset the module. */ + RESET_PeripheralReset(kGPIO0_RST_N_SHIFT_RSTn); +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + +#if defined(SECPINT) +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock. */ + CLOCK_EnableClock(kCLOCK_Gpio_Sec); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) + /* Reset the module. */ + RESET_PeripheralReset(kGPIOSEC_RST_SHIFT_RSTn); +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ +#endif /* SECPINT */ +#else + /* if need config SECURE PINT device,then enable secure pint interrupt clock */ + if (base == PINT) + { +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock. */ + CLOCK_EnableClock(kCLOCK_Pint); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) + /* Reset the module. */ + RESET_PeripheralReset(kPINT_RST_SHIFT_RSTn); +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + } +#if defined(SECPINT) + else if (base == SECPINT) + { +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock. */ + CLOCK_EnableClock(kCLOCK_Gpio_sec_Int); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) + /* Reset the module. */ + RESET_PeripheralReset(kGPIOSECINT_RST_SHIFT_RSTn); +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + } +#endif /* SECPINT */ +#endif /* FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE */ + + /* Disable all pattern match bit slices */ + base->PMCFG = pmcfg; +} + +/*! + * brief Configure PINT peripheral pin interrupt. + + * This function configures a given pin interrupt. + * + * param base Base address of the PINT peripheral. + * param intr Pin interrupt. + * param enable Selects detection logic. + * param callback Callback. + * + * retval None. + */ +void PINT_PinInterruptConfig(PINT_Type *base, pint_pin_int_t intr, pint_pin_enable_t enable, pint_cb_t callback) +{ + assert(base); + + /* Clear Rise and Fall flags first */ + PINT_PinInterruptClrRiseFlag(base, intr); + PINT_PinInterruptClrFallFlag(base, intr); + + /* select level or edge sensitive */ + base->ISEL = + (base->ISEL & ~(1UL << (uint32_t)intr)) | ((enable & PINT_PIN_INT_LEVEL) ? (1UL << (uint32_t)intr) : 0U); + + /* enable rising or level interrupt */ + if (enable & (PINT_PIN_INT_LEVEL | PINT_PIN_INT_RISE)) + { + base->SIENR = 1UL << (uint32_t)intr; + } + else + { + base->CIENR = 1UL << (uint32_t)intr; + } + + /* Enable falling or select high level */ + if (enable & PINT_PIN_INT_FALL_OR_HIGH_LEVEL) + { + base->SIENF = 1UL << (uint32_t)intr; + } + else + { + base->CIENF = 1UL << (uint32_t)intr; + } + + s_pintCallback[intr] = callback; +} + +/*! + * brief Get PINT peripheral pin interrupt configuration. + + * This function returns the configuration of a given pin interrupt. + * + * param base Base address of the PINT peripheral. + * param pintr Pin interrupt. + * param enable Pointer to store the detection logic. + * param callback Callback. + * + * retval None. + */ +void PINT_PinInterruptGetConfig(PINT_Type *base, pint_pin_int_t pintr, pint_pin_enable_t *enable, pint_cb_t *callback) +{ + uint32_t mask; + bool level; + + assert(base); + + *enable = kPINT_PinIntEnableNone; + level = false; + + mask = 1UL << (uint32_t)pintr; + if ((base->ISEL & mask) != 0U) + { + /* Pin interrupt is level sensitive */ + level = true; + } + + if ((base->IENR & mask) != 0U) + { + if (level) + { + /* Level interrupt is enabled */ + *enable = kPINT_PinIntEnableLowLevel; + } + else + { + /* Rising edge interrupt */ + *enable = kPINT_PinIntEnableRiseEdge; + } + } + + if ((base->IENF & mask) != 0U) + { + if (level) + { + /* Level interrupt is active high */ + *enable = kPINT_PinIntEnableHighLevel; + } + else + { + /* Either falling or both edge */ + if (*enable == kPINT_PinIntEnableRiseEdge) + { + /* Rising and faling edge */ + *enable = kPINT_PinIntEnableBothEdges; + } + else + { + /* Falling edge */ + *enable = kPINT_PinIntEnableFallEdge; + } + } + } + + *callback = s_pintCallback[pintr]; +} + +/*! + * brief Configure PINT pattern match. + + * This function configures a given pattern match bit slice. + * + * param base Base address of the PINT peripheral. + * param bslice Pattern match bit slice number. + * param cfg Pointer to bit slice configuration. + * + * retval None. + */ +void PINT_PatternMatchConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg) +{ + uint32_t src_shift; + uint32_t cfg_shift; + uint32_t pmcfg; + uint32_t tmp_src_shift = PININT_BITSLICE_SRC_MASK; + uint32_t tmp_cfg_shift = PININT_BITSLICE_CFG_MASK; + + assert(base); + + src_shift = PININT_BITSLICE_SRC_START + ((uint32_t)bslice * 3UL); + cfg_shift = PININT_BITSLICE_CFG_START + ((uint32_t)bslice * 3UL); + + /* Input source selection for selected bit slice */ + base->PMSRC = (base->PMSRC & ~(tmp_src_shift << src_shift)) | (cfg->bs_src << src_shift); + + /* Bit slice configuration */ + pmcfg = base->PMCFG; + pmcfg = (pmcfg & ~(tmp_cfg_shift << cfg_shift)) | (cfg->bs_cfg << cfg_shift); + + /* If end point is true, enable the bits */ + if ((uint32_t)bslice != 7UL) + { + if (cfg->end_point) + { + pmcfg |= (1UL << (uint32_t)bslice); + } + else + { + pmcfg &= ~(1UL << (uint32_t)bslice); + } + } + + base->PMCFG = pmcfg; + + /* Save callback pointer */ + s_pintCallback[bslice] = cfg->callback; +} + +/*! + * brief Get PINT pattern match configuration. + + * This function returns the configuration of a given pattern match bit slice. + * + * param base Base address of the PINT peripheral. + * param bslice Pattern match bit slice number. + * param cfg Pointer to bit slice configuration. + * + * retval None. + */ +void PINT_PatternMatchGetConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg) +{ + uint32_t src_shift; + uint32_t cfg_shift; + uint32_t tmp_src_shift = PININT_BITSLICE_SRC_MASK; + uint32_t tmp_cfg_shift = PININT_BITSLICE_CFG_MASK; + + assert(base); + + src_shift = PININT_BITSLICE_SRC_START + ((uint32_t)bslice * 3UL); + cfg_shift = PININT_BITSLICE_CFG_START + ((uint32_t)bslice * 3UL); + + cfg->bs_src = (pint_pmatch_input_src_t)((base->PMSRC & (tmp_src_shift << src_shift)) >> src_shift); + cfg->bs_cfg = (pint_pmatch_bslice_cfg_t)((base->PMCFG & (tmp_cfg_shift << cfg_shift)) >> cfg_shift); + + if ((uint32_t)bslice == 7U) + { + cfg->end_point = true; + } + else + { + cfg->end_point = ((base->PMCFG & (1UL << (uint32_t)bslice)) >> (uint32_t)bslice); + } + cfg->callback = s_pintCallback[bslice]; +} + +/*! + * brief Reset pattern match detection logic. + + * This function resets the pattern match detection logic if any of the product term is matching. + * + * param base Base address of the PINT peripheral. + * + * retval pmstatus Each bit position indicates the match status of corresponding bit slice. + * = 0 Match was detected. = 1 Match was not detected. + */ +uint32_t PINT_PatternMatchResetDetectLogic(PINT_Type *base) +{ + uint32_t pmctrl; + uint32_t pmstatus; + uint32_t pmsrc; + + pmctrl = base->PMCTRL; + pmstatus = pmctrl >> PINT_PMCTRL_PMAT_SHIFT; + if (pmstatus != 0UL) + { + /* Reset Pattern match engine detection logic */ + pmsrc = base->PMSRC; + base->PMSRC = pmsrc; + } + return (pmstatus); +} + +/*! + * @brief Clear Selected pin interrupt status only when the pin was triggered by edge-sensitive. + + * This function clears the selected pin interrupt status. + * + * @param base Base address of the PINT peripheral. + * @param pintr Pin interrupt. + * + * @retval None. + */ +void PINT_PinInterruptClrStatus(PINT_Type *base, pint_pin_int_t pintr) +{ + uint32_t pinIntMode = base->ISEL & (1UL << (uint32_t)pintr); + uint32_t pinIntStatus = base->IST & (1UL << (uint32_t)pintr); + + /* Edge sensitive and pin interrupt that is currently requesting an interrupt. */ + if ((pinIntMode == 0x0UL) && (pinIntStatus != 0x0UL)) + { + base->IST = (1UL << (uint32_t)pintr); + } +} + +/*! + * @brief Clear all pin interrupts status only when pins were triggered by edge-sensitive. + + * This function clears the status of all pin interrupts. + * + * @param base Base address of the PINT peripheral. + * + * @retval None. + */ +void PINT_PinInterruptClrStatusAll(PINT_Type *base) +{ + uint32_t pinIntMode = 0; + uint32_t pinIntStatus = 0; + uint32_t mask = 0; + uint32_t i; + + for (i = 0; i < FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) + { + pinIntMode = base->ISEL & (1UL << i); + pinIntStatus = base->IST & (1UL << i); + + /* Edge sensitive and pin interrupt that is currently requesting an interrupt. */ + if ((pinIntMode == 0x0UL) && (pinIntStatus != 0x0UL)) + { + mask |= 1UL << i; + } + } + + base->IST = mask; +} + +/*! + * brief Enable callback. + + * This function enables the interrupt for the selected PINT peripheral. Although the pin(s) are monitored + * as soon as they are enabled, the callback function is not enabled until this function is called. + * + * param base Base address of the PINT peripheral. + * + * retval None. + */ +void PINT_EnableCallback(PINT_Type *base) +{ + uint32_t i; + + assert(base); + + for (i = 0; i < FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) + { + NVIC_ClearPendingIRQ(s_pintIRQ[i]); + PINT_PinInterruptClrStatus(base, (pint_pin_int_t)i); + (void)EnableIRQ(s_pintIRQ[i]); + } +} + +/*! + * brief enable callback by pin index. + + * This function enables callback by pin index instead of enabling all pins. + * + * param base Base address of the peripheral. + * param pinIdx pin index. + * + * retval None. + */ +void PINT_EnableCallbackByIndex(PINT_Type *base, pint_pin_int_t pintIdx) +{ + assert(base); + + NVIC_ClearPendingIRQ(s_pintIRQ[pintIdx]); + PINT_PinInterruptClrStatus(base, (pint_pin_int_t)pintIdx); + (void)EnableIRQ(s_pintIRQ[pintIdx]); +} + +/*! + * brief Disable callback. + + * This function disables the interrupt for the selected PINT peripheral. Although the pins are still + * being monitored but the callback function is not called. + * + * param base Base address of the peripheral. + * + * retval None. + */ +void PINT_DisableCallback(PINT_Type *base) +{ + uint32_t i; + + assert(base); + + for (i = 0; i < FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) + { + (void)DisableIRQ(s_pintIRQ[i]); + PINT_PinInterruptClrStatus(base, (pint_pin_int_t)i); + NVIC_ClearPendingIRQ(s_pintIRQ[i]); + } +} + +/*! + * brief disable callback by pin index. + + * This function disables callback by pin index instead of disabling all pins. + * + * param base Base address of the peripheral. + * param pinIdx pin index. + * + * retval None. + */ +void PINT_DisableCallbackByIndex(PINT_Type *base, pint_pin_int_t pintIdx) +{ + assert(base); + + (void)DisableIRQ(s_pintIRQ[pintIdx]); + PINT_PinInterruptClrStatus(base, (pint_pin_int_t)pintIdx); + NVIC_ClearPendingIRQ(s_pintIRQ[pintIdx]); +} + +/*! + * brief Deinitialize PINT peripheral. + + * This function disables the PINT clock. + * + * param base Base address of the PINT peripheral. + * + * retval None. + */ +void PINT_Deinit(PINT_Type *base) +{ + uint32_t i; + + assert(base); + + /* Cleanup */ + PINT_DisableCallback(base); + for (i = 0; i < FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) + { + s_pintCallback[i] = NULL; + } + +#if defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 1) +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) + /* Reset the module. */ + RESET_PeripheralReset(kGPIOINT_RST_N_SHIFT_RSTn); +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable the clock. */ + CLOCK_DisableClock(kCLOCK_GpioInt); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#elif defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 0) +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) + /* Reset the module. */ + RESET_PeripheralReset(kGPIO0_RST_N_SHIFT_RSTn); +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable the clock. */ + CLOCK_DisableClock(kCLOCK_Gpio0); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(SECPINT) +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) + /* Reset the module. */ + RESET_PeripheralReset(kGPIOSEC_RST_SHIFT_RSTn); +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock. */ + CLOCK_DisableClock(kCLOCK_Gpio_Sec); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#endif /* SECPINT */ +#else + if (base == PINT) + { +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) + /* Reset the module. */ + RESET_PeripheralReset(kPINT_RST_SHIFT_RSTn); +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable the clock. */ + CLOCK_DisableClock(kCLOCK_Pint); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + } +#if defined(SECPINT) + else if (base == SECPINT) + { +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) + /* Reset the module. */ + RESET_PeripheralReset(kGPIOSECINT_RST_SHIFT_RSTn); +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable the clock. */ + CLOCK_DisableClock(kCLOCK_Gpio_sec_Int); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + } +#endif /* SECPINT */ +#endif /* FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE */ +} +#if defined(SECPINT) +/* IRQ handler functions overloading weak symbols in the startup */ +void SEC_GPIO_INT0_IRQ0_DriverIRQHandler(void) +{ + uint32_t pmstatus = 0; + + /* Reset pattern match detection */ + pmstatus = PINT_PatternMatchResetDetectLogic(SECPINT); + /* Call user function */ + if (s_pintCallback[kPINT_SecPinInt0] != NULL) + { + s_pintCallback[kPINT_SecPinInt0](kPINT_SecPinInt0, pmstatus); + } + if ((SECPINT->ISEL & 0x1U) == 0x0U) + { + /* Edge sensitive: clear Pin interrupt after callback */ + PINT_PinInterruptClrStatus(SECPINT, kPINT_PinInt0); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +#if (FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) +/* IRQ handler functions overloading weak symbols in the startup */ +void SEC_GPIO_INT0_IRQ1_DriverIRQHandler(void) +{ + uint32_t pmstatus; + + /* Reset pattern match detection */ + pmstatus = PINT_PatternMatchResetDetectLogic(SECPINT); + /* Call user function */ + if (s_pintCallback[kPINT_SecPinInt1] != NULL) + { + s_pintCallback[kPINT_SecPinInt1](kPINT_SecPinInt1, pmstatus); + } + if ((SECPINT->ISEL & 0x1U) == 0x0U) + { + /* Edge sensitive: clear Pin interrupt after callback */ + PINT_PinInterruptClrStatus(SECPINT, kPINT_PinInt1); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ +#endif /* SECPINT */ + +/* IRQ handler functions overloading weak symbols in the startup */ +void PIN_INT0_DriverIRQHandler(void) +{ + uint32_t pmstatus; + + /* Reset pattern match detection */ + pmstatus = PINT_PatternMatchResetDetectLogic(PINT); + /* Call user function */ + if (s_pintCallback[kPINT_PinInt0] != NULL) + { + s_pintCallback[kPINT_PinInt0](kPINT_PinInt0, pmstatus); + } + if ((PINT->ISEL & 0x1U) == 0x0U) + { + /* Edge sensitive: clear Pin interrupt after callback */ + PINT_PinInterruptClrStatus(PINT, kPINT_PinInt0); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) +void PIN_INT1_DriverIRQHandler(void) +{ + uint32_t pmstatus; + + /* Reset pattern match detection */ + pmstatus = PINT_PatternMatchResetDetectLogic(PINT); + /* Call user function */ + if (s_pintCallback[kPINT_PinInt1] != NULL) + { + s_pintCallback[kPINT_PinInt1](kPINT_PinInt1, pmstatus); + } + if ((PINT->ISEL & 0x2U) == 0x0U) + { + /* Edge sensitive: clear Pin interrupt after callback */ + PINT_PinInterruptClrStatus(PINT, kPINT_PinInt1); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 2U) +void PIN_INT2_DriverIRQHandler(void) +{ + uint32_t pmstatus; + + /* Reset pattern match detection */ + pmstatus = PINT_PatternMatchResetDetectLogic(PINT); + /* Call user function */ + if (s_pintCallback[kPINT_PinInt2] != NULL) + { + s_pintCallback[kPINT_PinInt2](kPINT_PinInt2, pmstatus); + } + if ((PINT->ISEL & 0x4U) == 0x0U) + { + /* Edge sensitive: clear Pin interrupt after callback */ + PINT_PinInterruptClrStatus(PINT, kPINT_PinInt2); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 3U) +void PIN_INT3_DriverIRQHandler(void) +{ + uint32_t pmstatus; + + /* Reset pattern match detection */ + pmstatus = PINT_PatternMatchResetDetectLogic(PINT); + /* Call user function */ + if (s_pintCallback[kPINT_PinInt3] != NULL) + { + s_pintCallback[kPINT_PinInt3](kPINT_PinInt3, pmstatus); + } + if ((PINT->ISEL & 0x8U) == 0x0U) + { + /* Edge sensitive: clear Pin interrupt after callback */ + PINT_PinInterruptClrStatus(PINT, kPINT_PinInt3); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 4U) +void PIN_INT4_DriverIRQHandler(void) +{ + uint32_t pmstatus; + + /* Reset pattern match detection */ + pmstatus = PINT_PatternMatchResetDetectLogic(PINT); + /* Call user function */ + if (s_pintCallback[kPINT_PinInt4] != NULL) + { + s_pintCallback[kPINT_PinInt4](kPINT_PinInt4, pmstatus); + } + if ((PINT->ISEL & 0x10U) == 0x0U) + { + /* Edge sensitive: clear Pin interrupt after callback */ + PINT_PinInterruptClrStatus(PINT, kPINT_PinInt4); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 5U) +#if defined(FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER) && FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER +void PIN_INT5_DAC1_IRQHandler(void) +#else +void PIN_INT5_DriverIRQHandler(void) +#endif /* FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER */ +{ + uint32_t pmstatus; + + /* Reset pattern match detection */ + pmstatus = PINT_PatternMatchResetDetectLogic(PINT); + /* Call user function */ + if (s_pintCallback[kPINT_PinInt5] != NULL) + { + s_pintCallback[kPINT_PinInt5](kPINT_PinInt5, pmstatus); + } + if ((PINT->ISEL & 0x20U) == 0x0U) + { + /* Edge sensitive: clear Pin interrupt after callback */ + PINT_PinInterruptClrStatus(PINT, kPINT_PinInt5); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 6U) +#if defined(FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER) && FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER +void PIN_INT6_USART3_IRQHandler(void) +#else +void PIN_INT6_DriverIRQHandler(void) +#endif /* FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER */ +{ + uint32_t pmstatus; + + /* Reset pattern match detection */ + pmstatus = PINT_PatternMatchResetDetectLogic(PINT); + /* Call user function */ + if (s_pintCallback[kPINT_PinInt6] != NULL) + { + s_pintCallback[kPINT_PinInt6](kPINT_PinInt6, pmstatus); + } + if ((PINT->ISEL & 0x40U) == 0x0U) + { + /* Edge sensitive: clear Pin interrupt after callback */ + PINT_PinInterruptClrStatus(PINT, kPINT_PinInt6); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 7U) +#if defined(FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER) && FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER +void PIN_INT7_USART4_IRQHandler(void) +#else +void PIN_INT7_DriverIRQHandler(void) +#endif /* FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER */ +{ + uint32_t pmstatus; + + /* Reset pattern match detection */ + pmstatus = PINT_PatternMatchResetDetectLogic(PINT); + /* Call user function */ + if (s_pintCallback[kPINT_PinInt7] != NULL) + { + s_pintCallback[kPINT_PinInt7](kPINT_PinInt7, pmstatus); + } + if ((PINT->ISEL & 0x80U) == 0x0U) + { + /* Edge sensitive: clear Pin interrupt after callback */ + PINT_PinInterruptClrStatus(PINT, kPINT_PinInt7); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_pint.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_pint.h new file mode 100644 index 000000000..074bf23fe --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_pint.h @@ -0,0 +1,579 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_PINT_H_ +#define _FSL_PINT_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup pint_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_PINT_DRIVER_VERSION (MAKE_VERSION(2, 1, 3)) /*!< Version 2.1.3 */ +/*@}*/ + +/* Number of interrupt line supported by PINT */ +#define PINT_PIN_INT_COUNT 8U + +/* Number of interrupt line supported by SECURE PINT */ +#define SEC_PINT_PIN_INT_COUNT 2U + +/* Number of input sources supported by PINT */ +#define PINT_INPUT_COUNT 8U + +/* PININT Bit slice source register bits */ +#define PININT_BITSLICE_SRC_START 8U +#define PININT_BITSLICE_SRC_MASK 7U + +/* PININT Bit slice configuration register bits */ +#define PININT_BITSLICE_CFG_START 8U +#define PININT_BITSLICE_CFG_MASK 7U +#define PININT_BITSLICE_ENDP_MASK 7U + +#define PINT_PIN_INT_LEVEL 0x10U +#define PINT_PIN_INT_EDGE 0x00U +#define PINT_PIN_INT_FALL_OR_HIGH_LEVEL 0x02U +#define PINT_PIN_INT_RISE 0x01U +#define PINT_PIN_RISE_EDGE (PINT_PIN_INT_EDGE | PINT_PIN_INT_RISE) +#define PINT_PIN_FALL_EDGE (PINT_PIN_INT_EDGE | PINT_PIN_INT_FALL_OR_HIGH_LEVEL) +#define PINT_PIN_BOTH_EDGE (PINT_PIN_INT_EDGE | PINT_PIN_INT_RISE | PINT_PIN_INT_FALL_OR_HIGH_LEVEL) +#define PINT_PIN_LOW_LEVEL (PINT_PIN_INT_LEVEL) +#define PINT_PIN_HIGH_LEVEL (PINT_PIN_INT_LEVEL | PINT_PIN_INT_FALL_OR_HIGH_LEVEL) + +/*! @brief PINT Pin Interrupt enable type */ +typedef enum _pint_pin_enable +{ + kPINT_PinIntEnableNone = 0U, /*!< Do not generate Pin Interrupt */ + kPINT_PinIntEnableRiseEdge = PINT_PIN_RISE_EDGE, /*!< Generate Pin Interrupt on rising edge */ + kPINT_PinIntEnableFallEdge = PINT_PIN_FALL_EDGE, /*!< Generate Pin Interrupt on falling edge */ + kPINT_PinIntEnableBothEdges = PINT_PIN_BOTH_EDGE, /*!< Generate Pin Interrupt on both edges */ + kPINT_PinIntEnableLowLevel = PINT_PIN_LOW_LEVEL, /*!< Generate Pin Interrupt on low level */ + kPINT_PinIntEnableHighLevel = PINT_PIN_HIGH_LEVEL /*!< Generate Pin Interrupt on high level */ +} pint_pin_enable_t; + +/*! @brief PINT Pin Interrupt type */ +typedef enum _pint_int +{ + kPINT_PinInt0 = 0U, /*!< Pin Interrupt 0 */ +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) + kPINT_PinInt1 = 1U, /*!< Pin Interrupt 1 */ +#endif +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 2U) + kPINT_PinInt2 = 2U, /*!< Pin Interrupt 2 */ +#endif +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 3U) + kPINT_PinInt3 = 3U, /*!< Pin Interrupt 3 */ +#endif +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 4U) + kPINT_PinInt4 = 4U, /*!< Pin Interrupt 4 */ +#endif +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 5U) + kPINT_PinInt5 = 5U, /*!< Pin Interrupt 5 */ +#endif +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 6U) + kPINT_PinInt6 = 6U, /*!< Pin Interrupt 6 */ +#endif +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 7U) + kPINT_PinInt7 = 7U, /*!< Pin Interrupt 7 */ +#endif +#if (FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS > 0U) + kPINT_SecPinInt0 = 8U, /*!< Secure Pin Interrupt 0 */ +#endif +#if (FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) + kPINT_SecPinInt1 = 9U, /*!< Secure Pin Interrupt 1 */ +#endif +} pint_pin_int_t; + +/*! @brief PINT Pattern Match bit slice input source type */ +typedef enum _pint_pmatch_input_src +{ + kPINT_PatternMatchInp0Src = 0U, /*!< Input source 0 */ + kPINT_PatternMatchInp1Src = 1U, /*!< Input source 1 */ + kPINT_PatternMatchInp2Src = 2U, /*!< Input source 2 */ + kPINT_PatternMatchInp3Src = 3U, /*!< Input source 3 */ + kPINT_PatternMatchInp4Src = 4U, /*!< Input source 4 */ + kPINT_PatternMatchInp5Src = 5U, /*!< Input source 5 */ + kPINT_PatternMatchInp6Src = 6U, /*!< Input source 6 */ + kPINT_PatternMatchInp7Src = 7U, /*!< Input source 7 */ +} pint_pmatch_input_src_t; + +/*! @brief PINT Pattern Match bit slice type */ +typedef enum _pint_pmatch_bslice +{ + kPINT_PatternMatchBSlice0 = 0U, /*!< Bit slice 0 */ +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) + kPINT_PatternMatchBSlice1 = 1U, /*!< Bit slice 1 */ +#endif +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 2U) + kPINT_PatternMatchBSlice2 = 2U, /*!< Bit slice 2 */ +#endif +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 3U) + kPINT_PatternMatchBSlice3 = 3U, /*!< Bit slice 3 */ +#endif +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 4U) + kPINT_PatternMatchBSlice4 = 4U, /*!< Bit slice 4 */ +#endif +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 5U) + kPINT_PatternMatchBSlice5 = 5U, /*!< Bit slice 5 */ +#endif +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 6U) + kPINT_PatternMatchBSlice6 = 6U, /*!< Bit slice 6 */ +#endif +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 7U) + kPINT_PatternMatchBSlice7 = 7U, /*!< Bit slice 7 */ +#endif +#if (FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS > 0U) + kSECPINT_PatternMatchBSlice0 = 8U, /*!< Bit slice 0 */ +#endif +#if (FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) + kSECPINT_PatternMatchBSlice1 = 9U, /*!< Bit slice 1 */ +#endif +} pint_pmatch_bslice_t; + +/*! @brief PINT Pattern Match configuration type */ +typedef enum _pint_pmatch_bslice_cfg +{ + kPINT_PatternMatchAlways = 0U, /*!< Always Contributes to product term match */ + kPINT_PatternMatchStickyRise = 1U, /*!< Sticky Rising edge */ + kPINT_PatternMatchStickyFall = 2U, /*!< Sticky Falling edge */ + kPINT_PatternMatchStickyBothEdges = 3U, /*!< Sticky Rising or Falling edge */ + kPINT_PatternMatchHigh = 4U, /*!< High level */ + kPINT_PatternMatchLow = 5U, /*!< Low level */ + kPINT_PatternMatchNever = 6U, /*!< Never contributes to product term match */ + kPINT_PatternMatchBothEdges = 7U, /*!< Either rising or falling edge */ +} pint_pmatch_bslice_cfg_t; + +/*! @brief PINT Callback function. */ +typedef void (*pint_cb_t)(pint_pin_int_t pintr, uint32_t pmatch_status); + +typedef struct _pint_pmatch_cfg +{ + pint_pmatch_input_src_t bs_src; + pint_pmatch_bslice_cfg_t bs_cfg; + bool end_point; + pint_cb_t callback; +} pint_pmatch_cfg_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Initialize PINT peripheral. + + * This function initializes the PINT peripheral and enables the clock. + * + * @param base Base address of the PINT peripheral. + * + * @retval None. + */ +void PINT_Init(PINT_Type *base); + +/*! + * @brief Configure PINT peripheral pin interrupt. + + * This function configures a given pin interrupt. + * + * @param base Base address of the PINT peripheral. + * @param intr Pin interrupt. + * @param enable Selects detection logic. + * @param callback Callback. + * + * @retval None. + */ +void PINT_PinInterruptConfig(PINT_Type *base, pint_pin_int_t intr, pint_pin_enable_t enable, pint_cb_t callback); + +/*! + * @brief Get PINT peripheral pin interrupt configuration. + + * This function returns the configuration of a given pin interrupt. + * + * @param base Base address of the PINT peripheral. + * @param pintr Pin interrupt. + * @param enable Pointer to store the detection logic. + * @param callback Callback. + * + * @retval None. + */ +void PINT_PinInterruptGetConfig(PINT_Type *base, pint_pin_int_t pintr, pint_pin_enable_t *enable, pint_cb_t *callback); + +/*! + * @brief Clear Selected pin interrupt status only when the pin was triggered by edge-sensitive. + + * This function clears the selected pin interrupt status. + * + * @param base Base address of the PINT peripheral. + * @param pintr Pin interrupt. + * + * @retval None. + */ +void PINT_PinInterruptClrStatus(PINT_Type *base, pint_pin_int_t pintr); + +/*! + * @brief Get Selected pin interrupt status. + + * This function returns the selected pin interrupt status. + * + * @param base Base address of the PINT peripheral. + * @param pintr Pin interrupt. + * + * @retval status = 0 No pin interrupt request. = 1 Selected Pin interrupt request active. + */ +static inline uint32_t PINT_PinInterruptGetStatus(PINT_Type *base, pint_pin_int_t pintr) +{ + return ((base->IST & (1UL << (uint32_t)pintr)) != 0U ? 1U : 0U); +} + +/*! + * @brief Clear all pin interrupts status only when pins were triggered by edge-sensitive. + + * This function clears the status of all pin interrupts. + * + * @param base Base address of the PINT peripheral. + * + * @retval None. + */ +void PINT_PinInterruptClrStatusAll(PINT_Type *base); + +/*! + * @brief Get all pin interrupts status. + + * This function returns the status of all pin interrupts. + * + * @param base Base address of the PINT peripheral. + * + * @retval status Each bit position indicates the status of corresponding pin interrupt. + * = 0 No pin interrupt request. = 1 Pin interrupt request active. + */ +static inline uint32_t PINT_PinInterruptGetStatusAll(PINT_Type *base) +{ + return (base->IST); +} + +/*! + * @brief Clear Selected pin interrupt fall flag. + + * This function clears the selected pin interrupt fall flag. + * + * @param base Base address of the PINT peripheral. + * @param pintr Pin interrupt. + * + * @retval None. + */ +static inline void PINT_PinInterruptClrFallFlag(PINT_Type *base, pint_pin_int_t pintr) +{ + base->FALL = (1UL << (uint32_t)pintr); +} + +/*! + * @brief Get selected pin interrupt fall flag. + + * This function returns the selected pin interrupt fall flag. + * + * @param base Base address of the PINT peripheral. + * @param pintr Pin interrupt. + * + * @retval flag = 0 Falling edge has not been detected. = 1 Falling edge has been detected. + */ +static inline uint32_t PINT_PinInterruptGetFallFlag(PINT_Type *base, pint_pin_int_t pintr) +{ + return ((base->FALL & (1UL << (uint32_t)pintr)) != 0U ? 1U : 0U); +} + +/*! + * @brief Clear all pin interrupt fall flags. + + * This function clears the fall flag for all pin interrupts. + * + * @param base Base address of the PINT peripheral. + * + * @retval None. + */ +static inline void PINT_PinInterruptClrFallFlagAll(PINT_Type *base) +{ + base->FALL = PINT_FALL_FDET_MASK; +} + +/*! + * @brief Get all pin interrupt fall flags. + + * This function returns the fall flag of all pin interrupts. + * + * @param base Base address of the PINT peripheral. + * + * @retval flags Each bit position indicates the falling edge detection of the corresponding pin interrupt. + * 0 Falling edge has not been detected. = 1 Falling edge has been detected. + */ +static inline uint32_t PINT_PinInterruptGetFallFlagAll(PINT_Type *base) +{ + return (base->FALL); +} + +/*! + * @brief Clear Selected pin interrupt rise flag. + + * This function clears the selected pin interrupt rise flag. + * + * @param base Base address of the PINT peripheral. + * @param pintr Pin interrupt. + * + * @retval None. + */ +static inline void PINT_PinInterruptClrRiseFlag(PINT_Type *base, pint_pin_int_t pintr) +{ + base->RISE = (1UL << (uint32_t)pintr); +} + +/*! + * @brief Get selected pin interrupt rise flag. + + * This function returns the selected pin interrupt rise flag. + * + * @param base Base address of the PINT peripheral. + * @param pintr Pin interrupt. + * + * @retval flag = 0 Rising edge has not been detected. = 1 Rising edge has been detected. + */ +static inline uint32_t PINT_PinInterruptGetRiseFlag(PINT_Type *base, pint_pin_int_t pintr) +{ + return ((base->RISE & (1UL << (uint32_t)pintr)) != 0U ? 1U : 0U); +} + +/*! + * @brief Clear all pin interrupt rise flags. + + * This function clears the rise flag for all pin interrupts. + * + * @param base Base address of the PINT peripheral. + * + * @retval None. + */ +static inline void PINT_PinInterruptClrRiseFlagAll(PINT_Type *base) +{ + base->RISE = PINT_RISE_RDET_MASK; +} + +/*! + * @brief Get all pin interrupt rise flags. + + * This function returns the rise flag of all pin interrupts. + * + * @param base Base address of the PINT peripheral. + * + * @retval flags Each bit position indicates the rising edge detection of the corresponding pin interrupt. + * 0 Rising edge has not been detected. = 1 Rising edge has been detected. + */ +static inline uint32_t PINT_PinInterruptGetRiseFlagAll(PINT_Type *base) +{ + return (base->RISE); +} + +/*! + * @brief Configure PINT pattern match. + + * This function configures a given pattern match bit slice. + * + * @param base Base address of the PINT peripheral. + * @param bslice Pattern match bit slice number. + * @param cfg Pointer to bit slice configuration. + * + * @retval None. + */ +void PINT_PatternMatchConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg); + +/*! + * @brief Get PINT pattern match configuration. + + * This function returns the configuration of a given pattern match bit slice. + * + * @param base Base address of the PINT peripheral. + * @param bslice Pattern match bit slice number. + * @param cfg Pointer to bit slice configuration. + * + * @retval None. + */ +void PINT_PatternMatchGetConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg); + +/*! + * @brief Get pattern match bit slice status. + + * This function returns the status of selected bit slice. + * + * @param base Base address of the PINT peripheral. + * @param bslice Pattern match bit slice number. + * + * @retval status = 0 Match has not been detected. = 1 Match has been detected. + */ +static inline uint32_t PINT_PatternMatchGetStatus(PINT_Type *base, pint_pmatch_bslice_t bslice) +{ + return ((base->PMCTRL >> PINT_PMCTRL_PMAT_SHIFT) & (1UL << (uint32_t)bslice)) >> (uint32_t)bslice; +} + +/*! + * @brief Get status of all pattern match bit slices. + + * This function returns the status of all bit slices. + * + * @param base Base address of the PINT peripheral. + * + * @retval status Each bit position indicates the match status of corresponding bit slice. + * = 0 Match has not been detected. = 1 Match has been detected. + */ +static inline uint32_t PINT_PatternMatchGetStatusAll(PINT_Type *base) +{ + return base->PMCTRL >> PINT_PMCTRL_PMAT_SHIFT; +} + +/*! + * @brief Reset pattern match detection logic. + + * This function resets the pattern match detection logic if any of the product term is matching. + * + * @param base Base address of the PINT peripheral. + * + * @retval pmstatus Each bit position indicates the match status of corresponding bit slice. + * = 0 Match was detected. = 1 Match was not detected. + */ +uint32_t PINT_PatternMatchResetDetectLogic(PINT_Type *base); + +/*! + * @brief Enable pattern match function. + + * This function enables the pattern match function. + * + * @param base Base address of the PINT peripheral. + * + * @retval None. + */ +static inline void PINT_PatternMatchEnable(PINT_Type *base) +{ + base->PMCTRL = (base->PMCTRL & PINT_PMCTRL_ENA_RXEV_MASK) | PINT_PMCTRL_SEL_PMATCH_MASK; +} + +/*! + * @brief Disable pattern match function. + + * This function disables the pattern match function. + * + * @param base Base address of the PINT peripheral. + * + * @retval None. + */ +static inline void PINT_PatternMatchDisable(PINT_Type *base) +{ + base->PMCTRL = (base->PMCTRL & PINT_PMCTRL_ENA_RXEV_MASK) & ~PINT_PMCTRL_SEL_PMATCH_MASK; +} + +/*! + * @brief Enable RXEV output. + + * This function enables the pattern match RXEV output. + * + * @param base Base address of the PINT peripheral. + * + * @retval None. + */ +static inline void PINT_PatternMatchEnableRXEV(PINT_Type *base) +{ + base->PMCTRL = (base->PMCTRL & PINT_PMCTRL_SEL_PMATCH_MASK) | PINT_PMCTRL_ENA_RXEV_MASK; +} + +/*! + * @brief Disable RXEV output. + + * This function disables the pattern match RXEV output. + * + * @param base Base address of the PINT peripheral. + * + * @retval None. + */ +static inline void PINT_PatternMatchDisableRXEV(PINT_Type *base) +{ + base->PMCTRL = (base->PMCTRL & PINT_PMCTRL_SEL_PMATCH_MASK) & ~PINT_PMCTRL_ENA_RXEV_MASK; +} + +/*! + * @brief Enable callback. + + * This function enables the interrupt for the selected PINT peripheral. Although the pin(s) are monitored + * as soon as they are enabled, the callback function is not enabled until this function is called. + * + * @param base Base address of the PINT peripheral. + * + * @retval None. + */ +void PINT_EnableCallback(PINT_Type *base); + +/*! + * @brief Disable callback. + + * This function disables the interrupt for the selected PINT peripheral. Although the pins are still + * being monitored but the callback function is not called. + * + * @param base Base address of the peripheral. + * + * @retval None. + */ +void PINT_DisableCallback(PINT_Type *base); + +/*! + * @brief Deinitialize PINT peripheral. + + * This function disables the PINT clock. + * + * @param base Base address of the PINT peripheral. + * + * @retval None. + */ +void PINT_Deinit(PINT_Type *base); + +/*! + * @brief enable callback by pin index. + + * This function enables callback by pin index instead of enabling all pins. + * + * @param base Base address of the peripheral. + * @param pinIdx pin index. + * + * @retval None. + */ +void PINT_EnableCallbackByIndex(PINT_Type *base, pint_pin_int_t pintIdx); + +/*! + * @brief disable callback by pin index. + + * This function disables callback by pin index instead of disabling all pins. + * + * @param base Base address of the peripheral. + * @param pinIdx pin index. + * + * @retval None. + */ +void PINT_DisableCallbackByIndex(PINT_Type *base, pint_pin_int_t pintIdx); + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _FSL_PINT_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_plu.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_plu.c new file mode 100644 index 000000000..082ed0571 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_plu.c @@ -0,0 +1,97 @@ +/* + * Copyright 2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_plu.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.plu" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Gets the instance from the base address + * + * @param base PLU peripheral base address + * + * @return The PLU instance + */ +static uint32_t PLU_GetInstance(PLU_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to PLU bases for each instance. */ +static PLU_Type *const s_pluBases[] = PLU_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to PLU clocks for each instance. */ +static const clock_ip_name_t s_pluClocks[] = PLU_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) +/*! @brief Pointers to PLU resets for each instance. */ +static const reset_ip_name_t s_lpuResets[] = PLU_RSTS_N; +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t PLU_GetInstance(PLU_Type *base) +{ + uint32_t instance; + uint32_t pluArrayCount = (sizeof(s_pluBases) / sizeof(s_pluBases[0])); + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < pluArrayCount; instance++) + { + if (s_pluBases[instance] == base) + { + break; + } + } + + assert(instance < pluArrayCount); + + return instance; +} + +/*! + * brief Ungates the PLU clock and reset the module. + * + * note This API should be called at the beginning of the application using the PLU driver. + * + * param base PLU peripheral base address + */ +void PLU_Init(PLU_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the PLU peripheral clock */ + CLOCK_EnableClock(s_pluClocks[PLU_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) + /* Reset the module. */ + RESET_PeripheralReset(s_lpuResets[PLU_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ +} + +/*! + * brief Gate the PLU clock + * + * param base PLU peripheral base address + */ +void PLU_Deinit(PLU_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Gate the module clock */ + CLOCK_DisableClock((s_pluClocks[PLU_GetInstance(base)])); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_plu.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_plu.h new file mode 100644 index 000000000..e7da779c8 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_plu.h @@ -0,0 +1,266 @@ +/* + * Copyright 2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_PLU_H_ +#define _FSL_PLU_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup plu + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_PLU_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*!< Version 2.0.1 */ + /*@}*/ + +/*! @brief Index of LUT */ +typedef enum _plu_lut_index +{ + kPLU_LUT_0 = 0U, /*!< 5-input Look-up Table 0 */ + kPLU_LUT_1 = 1U, /*!< 5-input Look-up Table 1 */ + kPLU_LUT_2 = 2U, /*!< 5-input Look-up Table 2 */ + kPLU_LUT_3 = 3U, /*!< 5-input Look-up Table 3 */ + kPLU_LUT_4 = 4U, /*!< 5-input Look-up Table 4 */ + kPLU_LUT_5 = 5U, /*!< 5-input Look-up Table 5 */ + kPLU_LUT_6 = 6U, /*!< 5-input Look-up Table 6 */ + kPLU_LUT_7 = 7U, /*!< 5-input Look-up Table 7 */ + kPLU_LUT_8 = 8U, /*!< 5-input Look-up Table 8 */ + kPLU_LUT_9 = 9U, /*!< 5-input Look-up Table 9 */ + kPLU_LUT_10 = 10U, /*!< 5-input Look-up Table 10 */ + kPLU_LUT_11 = 11U, /*!< 5-input Look-up Table 11 */ + kPLU_LUT_12 = 12U, /*!< 5-input Look-up Table 12 */ + kPLU_LUT_13 = 13U, /*!< 5-input Look-up Table 13 */ + kPLU_LUT_14 = 14U, /*!< 5-input Look-up Table 14 */ + kPLU_LUT_15 = 15U, /*!< 5-input Look-up Table 15 */ + kPLU_LUT_16 = 16U, /*!< 5-input Look-up Table 16 */ + kPLU_LUT_17 = 17U, /*!< 5-input Look-up Table 17 */ + kPLU_LUT_18 = 18U, /*!< 5-input Look-up Table 18 */ + kPLU_LUT_19 = 19U, /*!< 5-input Look-up Table 19 */ + kPLU_LUT_20 = 20U, /*!< 5-input Look-up Table 20 */ + kPLU_LUT_21 = 21U, /*!< 5-input Look-up Table 21 */ + kPLU_LUT_22 = 22U, /*!< 5-input Look-up Table 22 */ + kPLU_LUT_23 = 23U, /*!< 5-input Look-up Table 23 */ + kPLU_LUT_24 = 24U, /*!< 5-input Look-up Table 24 */ + kPLU_LUT_25 = 25U /*!< 5-input Look-up Table 25 */ +} plu_lut_index_t; + +/*! @brief Inputs of LUT. 5 input present for each LUT. */ +typedef enum _plu_lut_in_index +{ + kPLU_LUT_IN_0 = 0U, /*!< LUT input 0 */ + kPLU_LUT_IN_1 = 1U, /*!< LUT input 1 */ + kPLU_LUT_IN_2 = 2U, /*!< LUT input 2 */ + kPLU_LUT_IN_3 = 3U, /*!< LUT input 3 */ + kPLU_LUT_IN_4 = 4U /*!< LUT input 4 */ +} plu_lut_in_index_t; + +/*! @brief Available sources of LUT input */ +typedef enum _plu_lut_input_source +{ + kPLU_LUT_IN_SRC_PLU_IN_0 = 0U, /*!< Select PLU input 0 to be connected to LUTn Input x */ + kPLU_LUT_IN_SRC_PLU_IN_1 = 1U, /*!< Select PLU input 1 to be connected to LUTn Input x */ + kPLU_LUT_IN_SRC_PLU_IN_2 = 2U, /*!< Select PLU input 2 to be connected to LUTn Input x */ + kPLU_LUT_IN_SRC_PLU_IN_3 = 3U, /*!< Select PLU input 3 to be connected to LUTn Input x */ + kPLU_LUT_IN_SRC_PLU_IN_4 = 4U, /*!< Select PLU input 4 to be connected to LUTn Input x */ + kPLU_LUT_IN_SRC_PLU_IN_5 = 5U, /*!< Select PLU input 5 to be connected to LUTn Input x */ + kPLU_LUT_IN_SRC_LUT_OUT_0 = 6U, /*!< Select LUT output 0 to be connected to LUTn Input x */ + kPLU_LUT_IN_SRC_LUT_OUT_1 = 7U, /*!< Select LUT output 1 to be connected to LUTn Input x */ + kPLU_LUT_IN_SRC_LUT_OUT_2 = 8U, /*!< Select LUT output 2 to be connected to LUTn Input x */ + kPLU_LUT_IN_SRC_LUT_OUT_3 = 9U, /*!< Select LUT output 3 to be connected to LUTn Input x */ + kPLU_LUT_IN_SRC_LUT_OUT_4 = 10U, /*!< Select LUT output 4 to be connected to LUTn Input x */ + kPLU_LUT_IN_SRC_LUT_OUT_5 = 11U, /*!< Select LUT output 5 to be connected to LUTn Input x */ + kPLU_LUT_IN_SRC_LUT_OUT_6 = 12U, /*!< Select LUT output 6 to be connected to LUTn Input x */ + kPLU_LUT_IN_SRC_LUT_OUT_7 = 13U, /*!< Select LUT output 7 to be connected to LUTn Input x */ + kPLU_LUT_IN_SRC_LUT_OUT_8 = 14U, /*!< Select LUT output 8 to be connected to LUTn Input x */ + kPLU_LUT_IN_SRC_LUT_OUT_9 = 15U, /*!< Select LUT output 9 to be connected to LUTn Input x */ + kPLU_LUT_IN_SRC_LUT_OUT_10 = 16U, /*!< Select LUT output 10 to be connected to LUTn Input x */ + kPLU_LUT_IN_SRC_LUT_OUT_11 = 17U, /*!< Select LUT output 11 to be connected to LUTn Input x */ + kPLU_LUT_IN_SRC_LUT_OUT_12 = 18U, /*!< Select LUT output 12 to be connected to LUTn Input x */ + kPLU_LUT_IN_SRC_LUT_OUT_13 = 19U, /*!< Select LUT output 13 to be connected to LUTn Input x */ + kPLU_LUT_IN_SRC_LUT_OUT_14 = 20U, /*!< Select LUT output 14 to be connected to LUTn Input x */ + kPLU_LUT_IN_SRC_LUT_OUT_15 = 21U, /*!< Select LUT output 15 to be connected to LUTn Input x */ + kPLU_LUT_IN_SRC_LUT_OUT_16 = 22U, /*!< Select LUT output 16 to be connected to LUTn Input x */ + kPLU_LUT_IN_SRC_LUT_OUT_17 = 23U, /*!< Select LUT output 17 to be connected to LUTn Input x */ + kPLU_LUT_IN_SRC_LUT_OUT_18 = 24U, /*!< Select LUT output 18 to be connected to LUTn Input x */ + kPLU_LUT_IN_SRC_LUT_OUT_19 = 25U, /*!< Select LUT output 19 to be connected to LUTn Input x */ + kPLU_LUT_IN_SRC_LUT_OUT_20 = 26U, /*!< Select LUT output 20 to be connected to LUTn Input x */ + kPLU_LUT_IN_SRC_LUT_OUT_21 = 27U, /*!< Select LUT output 21 to be connected to LUTn Input x */ + kPLU_LUT_IN_SRC_LUT_OUT_22 = 28U, /*!< Select LUT output 22 to be connected to LUTn Input x */ + kPLU_LUT_IN_SRC_LUT_OUT_23 = 29U, /*!< Select LUT output 23 to be connected to LUTn Input x */ + kPLU_LUT_IN_SRC_LUT_OUT_24 = 30U, /*!< Select LUT output 24 to be connected to LUTn Input x */ + kPLU_LUT_IN_SRC_LUT_OUT_25 = 31U, /*!< Select LUT output 25 to be connected to LUTn Input x */ + kPLU_LUT_IN_SRC_FLIPFLOP_0 = 32U, /*!< Select Flip-Flops state 0 to be connected to LUTn Input x */ + kPLU_LUT_IN_SRC_FLIPFLOP_1 = 33U, /*!< Select Flip-Flops state 1 to be connected to LUTn Input x */ + kPLU_LUT_IN_SRC_FLIPFLOP_2 = 34U, /*!< Select Flip-Flops state 2 to be connected to LUTn Input x */ + kPLU_LUT_IN_SRC_FLIPFLOP_3 = 35U /*!< Select Flip-Flops state 3 to be connected to LUTn Input x */ +} plu_lut_input_source_t; + +/*! @brief PLU output multiplexer registers */ +typedef enum _plu_output_index +{ + kPLU_OUTPUT_0 = 0U, /*!< PLU OUTPUT 0 */ + kPLU_OUTPUT_1 = 1U, /*!< PLU OUTPUT 1 */ + kPLU_OUTPUT_2 = 2U, /*!< PLU OUTPUT 2 */ + kPLU_OUTPUT_3 = 3U, /*!< PLU OUTPUT 3 */ + kPLU_OUTPUT_4 = 4U, /*!< PLU OUTPUT 4 */ + kPLU_OUTPUT_5 = 5U, /*!< PLU OUTPUT 5 */ + kPLU_OUTPUT_6 = 6U, /*!< PLU OUTPUT 6 */ + kPLU_OUTPUT_7 = 7U /*!< PLU OUTPUT 7 */ +} plu_output_index_t; + +/*! @brief Available sources of PLU output */ +typedef enum _plu_output_source +{ + kPLU_OUT_SRC_LUT_0 = 0U, /*!< Select LUT0 output to be connected to PLU output */ + kPLU_OUT_SRC_LUT_1 = 1U, /*!< Select LUT1 output to be connected to PLU output */ + kPLU_OUT_SRC_LUT_2 = 2U, /*!< Select LUT2 output to be connected to PLU output */ + kPLU_OUT_SRC_LUT_3 = 3U, /*!< Select LUT3 output to be connected to PLU output */ + kPLU_OUT_SRC_LUT_4 = 4U, /*!< Select LUT4 output to be connected to PLU output */ + kPLU_OUT_SRC_LUT_5 = 5U, /*!< Select LUT5 output to be connected to PLU output */ + kPLU_OUT_SRC_LUT_6 = 6U, /*!< Select LUT6 output to be connected to PLU output */ + kPLU_OUT_SRC_LUT_7 = 7U, /*!< Select LUT7 output to be connected to PLU output */ + kPLU_OUT_SRC_LUT_8 = 8U, /*!< Select LUT8 output to be connected to PLU output */ + kPLU_OUT_SRC_LUT_9 = 9U, /*!< Select LUT9 output to be connected to PLU output */ + kPLU_OUT_SRC_LUT_10 = 10U, /*!< Select LUT10 output to be connected to PLU output */ + kPLU_OUT_SRC_LUT_11 = 11U, /*!< Select LUT11 output to be connected to PLU output */ + kPLU_OUT_SRC_LUT_12 = 12U, /*!< Select LUT12 output to be connected to PLU output */ + kPLU_OUT_SRC_LUT_13 = 13U, /*!< Select LUT13 output to be connected to PLU output */ + kPLU_OUT_SRC_LUT_14 = 14U, /*!< Select LUT14 output to be connected to PLU output */ + kPLU_OUT_SRC_LUT_15 = 15U, /*!< Select LUT15 output to be connected to PLU output */ + kPLU_OUT_SRC_LUT_16 = 16U, /*!< Select LUT16 output to be connected to PLU output */ + kPLU_OUT_SRC_LUT_17 = 17U, /*!< Select LUT17 output to be connected to PLU output */ + kPLU_OUT_SRC_LUT_18 = 18U, /*!< Select LUT18 output to be connected to PLU output */ + kPLU_OUT_SRC_LUT_19 = 19U, /*!< Select LUT19 output to be connected to PLU output */ + kPLU_OUT_SRC_LUT_20 = 20U, /*!< Select LUT20 output to be connected to PLU output */ + kPLU_OUT_SRC_LUT_21 = 21U, /*!< Select LUT21 output to be connected to PLU output */ + kPLU_OUT_SRC_LUT_22 = 22U, /*!< Select LUT22 output to be connected to PLU output */ + kPLU_OUT_SRC_LUT_23 = 23U, /*!< Select LUT23 output to be connected to PLU output */ + kPLU_OUT_SRC_LUT_24 = 24U, /*!< Select LUT24 output to be connected to PLU output */ + kPLU_OUT_SRC_LUT_25 = 25U, /*!< Select LUT25 output to be connected to PLU output */ + kPLU_OUT_SRC_FLIPFLOP_0 = 26U, /*!< Select Flip-Flops state(0) to be connected to PLU output */ + kPLU_OUT_SRC_FLIPFLOP_1 = 27U, /*!< Select Flip-Flops state(1) to be connected to PLU output */ + kPLU_OUT_SRC_FLIPFLOP_2 = 28U, /*!< Select Flip-Flops state(2) to be connected to PLU output */ + kPLU_OUT_SRC_FLIPFLOP_3 = 29U /*!< Select Flip-Flops state(3) to be connected to PLU output */ +} plu_output_source_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Ungates the PLU clock and reset the module. + * + * @note This API should be called at the beginning of the application using the PLU driver. + * + * @param base PLU peripheral base address + */ +void PLU_Init(PLU_Type *base); + +/*! + * @brief Gate the PLU clock + * + * @param base PLU peripheral base address + */ +void PLU_Deinit(PLU_Type *base); + +/*! @}*/ + +/*! + * @name Set input/output source and Truth Table + * @{ + */ + +/*! + * @brief Set Input source of LUT. + * + * Note: An external clock must be applied to the PLU_CLKIN input when using FFs. + * For each LUT, the slot associated with the output from LUTn itself is tied low. + * + * @param base PLU peripheral base address. + * @param lutIndex LUT index (see @ref plu_lut_index_t typedef enumeration). + * @param lutInIndex LUT input index (see @ref plu_lut_in_index_t typedef enumeration). + * @param inputSrc LUT input source (see @ref plu_lut_input_source_t typedef enumeration). + */ +static inline void PLU_SetLutInputSource(PLU_Type *base, + plu_lut_index_t lutIndex, + plu_lut_in_index_t lutInIndex, + plu_lut_input_source_t inputSrc) +{ + PLU->LUT[lutIndex].INP[lutInIndex] = inputSrc; +} + +/*! + * @brief Set Output source of PLU. + * + * Note: An external clock must be applied to the PLU_CLKIN input when using FFs. + * + * @param base PLU peripheral base address. + * @param outputIndex PLU output index (see @ref plu_output_index_t typedef enumeration). + * @param outputSrc PLU output source (see @ref plu_output_source_t typedef enumeration). + */ +static inline void PLU_SetOutputSource(PLU_Type *base, plu_output_index_t outputIndex, plu_output_source_t outputSrc) +{ + base->OUTPUT_MUX[outputIndex] = outputSrc; +} + +/*! + * @brief Set Truth Table of LUT. + * + * @param base PLU peripheral base address. + * @param lutIndex LUT index (see @ref plu_lut_index_t typedef enumeration). + * @param truthTable Truth Table value. + */ +static inline void PLU_SetLutTruthTable(PLU_Type *base, plu_lut_index_t lutIndex, uint32_t truthTable) +{ + base->LUT_TRUTH[lutIndex] = truthTable; +} + +/*! @}*/ + +/*! + * @name Read current Output State + * @{ + */ + +/*! + * @brief Read the current state of the 8 designated PLU Outputs. + * + * Note: The PLU bus clock must be re-enabled prior to reading the Outpus Register if PLU bus clock is + * shut-off. + * + * @param base PLU peripheral base address. + * @return Current PLU output state value. + */ +static inline uint32_t PLU_ReadOutputState(PLU_Type *base) +{ + return (base->OUTPUTS & PLU_OUTPUTS_OUTPUT_STATE_MASK); +} + +/*! @}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_PLU_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_power.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_power.c new file mode 100644 index 000000000..a0b833175 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_power.c @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016, NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include "fsl_common.h" +#include "fsl_power.h" +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.power" +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* Empty file since implementation is in header file and power library */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_power.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_power.h new file mode 100644 index 000000000..e945037f1 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_power.h @@ -0,0 +1,737 @@ +/* + * Copyright 2017, NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_POWER_H_ +#define _FSL_POWER_H_ + +#include "fsl_common.h" +#include "fsl_device_registers.h" +#include + +/*! + * @addtogroup power + * @{ + */ +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief power driver version 1.0.0. */ +#define FSL_POWER_DRIVER_VERSION (MAKE_VERSION(1, 0, 0)) +/*@}*/ + + +/** @brief Low Power main structure */ +typedef enum +{ + VD_AON = 0x0, /*!< Digital Always On power domain */ + VD_MEM = 0x1, /*!< Memories (SRAM) power domain */ + VD_DCDC = 0x2, /*!< Core logic power domain */ + VD_DEEPSLEEP = 0x3 /*!< Core logic power domain */ +} LPC_POWER_DOMAIN_T; + +/** @brief Low Power main structure */ +typedef struct +{ /* */ + __IO uint32_t CFG; /*!< Low Power Mode Configuration, and miscallenous options */ + __IO uint32_t PDCTRL0; /*!< Power Down control : controls power of various modules + in the different Low power modes, including ROM */ + __IO uint32_t SRAMRETCTRL; /*!< Power Down control : controls power SRAM instances + in the different Low power modes */ + __IO uint32_t CPURETCTRL; /*!< CPU0 retention control : controls CPU retention parameters in POWER DOWN modes */ + __IO uint64_t VOLTAGE; /*!< Voltage control in Low Power Modes */ + __IO uint64_t WAKEUPSRC; /*!< Wake up sources control for sleepcon */ + __IO uint64_t WAKEUPINT; /*!< Wake up sources control for ARM */ + __IO uint32_t HWWAKE; /*!< Interrupt that can postpone power down modes + in case an interrupt is pending when the processor request deepsleep */ + __IO uint32_t WAKEUPIOSRC; /*!< Wake up I/O sources in DEEP POWER DOWN mode */ + __IO uint32_t TIMERCFG; /*!< Wake up timers configuration */ + __IO uint32_t TIMERCOUNT; /*!< Wake up Timer count*/ + __IO uint32_t POWERCYCLE; /*!< Cancels entry in Low Power mode if set with 0xDEADABBA (might be used by some + interrupt handlers)*/ +} LPC_LOWPOWER_T; + +/* */ +#define LOWPOWER_POWERCYCLE_CANCELLED 0xDEADABBA /*!< */ + +/* Low Power modes */ +#define LOWPOWER_CFG_LPMODE_INDEX 0 +#define LOWPOWER_CFG_LPMODE_MASK (0x3UL << LOWPOWER_CFG_LPMODE_INDEX) +#define LOWPOWER_CFG_SELCLOCK_INDEX 2 +#define LOWPOWER_CFG_SELCLOCK_MASK (0x1UL << LOWPOWER_CFG_SELCLOCK_INDEX) +#define LOWPOWER_CFG_SELMEMSUPPLY_INDEX 3 +#define LOWPOWER_CFG_SELMEMSUPPLY_MASK (0x1UL << LOWPOWER_CFG_SELMEMSUPPLY_INDEX) +#define LOWPOWER_CFG_MEMLOWPOWERMODE_INDEX 4 +#define LOWPOWER_CFG_MEMLOWPOWERMODE_MASK (0x1UL << LOWPOWER_CFG_MEMLOWPOWERMODE_INDEX) +#define LOWPOWER_CFG_LDODEEPSLEEPREF_INDEX 5 +#define LOWPOWER_CFG_LDODEEPSLEEPREF_MASK (0x1UL << LOWPOWER_CFG_LDODEEPSLEEPREF_INDEX) + +#define LOWPOWER_CFG_LPMODE_ACTIVE 0 /*!< ACTIVE mode */ +#define LOWPOWER_CFG_LPMODE_DEEPSLEEP 1 /*!< DEEP SLEEP mode */ +#define LOWPOWER_CFG_LPMODE_POWERDOWN 2 /*!< POWER DOWN mode */ +#define LOWPOWER_CFG_LPMODE_DEEPPOWERDOWN 3 /*!< DEEP POWER DOWN mode */ +#define LOWPOWER_CFG_LPMODE_SLEEP 4 /*!< SLEEP mode */ + +#define LOWPOWER_CFG_SELCLOCK_1MHZ 0 /*!< The 1 MHz clock is used during the configuration of the PMC */ +#define LOWPOWER_CFG_SELCLOCK_12MHZ 1 /*!< The 12 MHz clock is used during the configuration of the PMC (to speed up PMC configuration process)*/ + +#define LOWPOWER_CFG_SELMEMSUPPLY_LDOMEM 0 /*!< In DEEP SLEEP power mode, the Memories are supplied by the LDO_MEM */ +#define LOWPOWER_CFG_SELMEMSUPPLY_LDODEEPSLEEP 1 /*!< In DEEP SLEEP power mode, the Memories are supplied by the LDO_DEEP_SLEEP (or DCDC) */ + +#define LOWPOWER_CFG_MEMLOWPOWERMODE_SOURCEBIASING 0 /*!< All SRAM instances use "Source Biasing" as low power mode technic (it is recommended to set LDO_MEM as high as possible -- 1.1V typical -- during low power mode) */ +#define LOWPOWER_CFG_MEMLOWPOWERMODE_VOLTAGESCALING 1 /*!< All SRAM instances use "Voltage Scaling" as low power mode technic (it is recommended to set LDO_MEM as low as possible -- down to 0.7V -- during low power mode) */ + +#define LOWPOWER_CFG_LDODEEPSLEEPREF_FLASHBUFFER 0 /*!< LDO DEEP SLEEP uses Flash Buffer as reference */ +#define LOWPOWER_CFG_LDODEEPSLEEPREF_BANDGAG0P8V 1 /*!< LDO DEEP SLEEP uses Band Gap 0.8V as reference */ + +/* CPU Retention Control*/ +#define LOWPOWER_CPURETCTRL_ENA_INDEX 0 +#define LOWPOWER_CPURETCTRL_ENA_MASK (0x1UL << LOWPOWER_CPURETCTRL_ENA_INDEX) +#define LOWPOWER_CPURETCTRL_MEMBASE_INDEX 1 +#define LOWPOWER_CPURETCTRL_MEMBASE_MASK (0x1FFF << LOWPOWER_CPURETCTRL_MEMBASE_INDEX) +#define LOWPOWER_CPURETCTRL_RETDATALENGTH_INDEX 14 +#define LOWPOWER_CPURETCTRL_RETDATALENGTH_MASK (0x3FFUL << LOWPOWER_CPURETCTRL_RETDATALENGTH_INDEX) + +#define LOWPOWER_CPURETCTRL_ENA_DISABLE 0 /*!< In POWER DOWN mode, CPU Retention is disabled */ +#define LOWPOWER_CPURETCTRL_ENA_ENABLE 1 /*!< In POWER DOWN mode, CPU Retention is enabled */ + +/** + * @brief Analog components power modes control during low power modes + */ +typedef enum pd_bits +{ + kPDRUNCFG_PD_DCDC = (1UL << 0), + kPDRUNCFG_PD_BIAS = (1UL << 1), + kPDRUNCFG_PD_BODCORE = (1UL << 2), + kPDRUNCFG_PD_BODVBAT = (1UL << 3), + kPDRUNCFG_PD_FRO1M = (1UL << 4), + kPDRUNCFG_PD_FRO192M = (1UL << 5), + kPDRUNCFG_PD_FRO32K = (1UL << 6), + kPDRUNCFG_PD_XTAL32K = (1UL << 7), + kPDRUNCFG_PD_XTAL32M = (1UL << 8), + kPDRUNCFG_PD_PLL0 = (1UL << 9), + kPDRUNCFG_PD_PLL1 = (1UL << 10), + kPDRUNCFG_PD_USB0_PHY = (1UL << 11), + kPDRUNCFG_PD_USB1_PHY = (1UL << 12), + kPDRUNCFG_PD_COMP = (1UL << 13), + kPDRUNCFG_PD_TEMPSENS = (1UL << 14), + kPDRUNCFG_PD_GPADC = (1UL << 15), + kPDRUNCFG_PD_LDOMEM = (1UL << 16), + kPDRUNCFG_PD_LDODEEPSLEEP = (1UL << 17), + kPDRUNCFG_PD_LDOUSBHS = (1UL << 18), + kPDRUNCFG_PD_LDOGPADC = (1UL << 19), + kPDRUNCFG_PD_LDOXO32M = (1UL << 20), + kPDRUNCFG_PD_LDOFLASHNV = (1UL << 21), + kPDRUNCFG_PD_RNG = (1UL << 22), + kPDRUNCFG_PD_PLL0_SSCG = (1UL << 23), + kPDRUNCFG_PD_ROM = (1UL << 24), + + /* + This enum member has no practical meaning,it is used to avoid MISRA issue, + user should not trying to use it. + */ + kPDRUNCFG_ForceUnsigned = 0x80000000U, +} pd_bit_t; + +/** + * @brief SRAM instances retention control during low power modes + */ +#define LOWPOWER_SRAMRETCTRL_RETEN_RAMX0 (1UL << 0) /*!< Enable SRAMX_0 retention when entering in Low power modes */ +#define LOWPOWER_SRAMRETCTRL_RETEN_RAMX1 (1UL << 1) /*!< Enable SRAMX_1 retention when entering in Low power modes */ +#define LOWPOWER_SRAMRETCTRL_RETEN_RAMX2 (1UL << 2) /*!< Enable SRAMX_2 retention when entering in Low power modes */ +#define LOWPOWER_SRAMRETCTRL_RETEN_RAMX3 (1UL << 3) /*!< Enable SRAMX_3 retention when entering in Low power modes */ +#define LOWPOWER_SRAMRETCTRL_RETEN_RAM00 (1UL << 4) /*!< Enable SRAM0_0 retention when entering in Low power modes */ +#define LOWPOWER_SRAMRETCTRL_RETEN_RAM01 (1UL << 5) /*!< Enable SRAM0_1 retention when entering in Low power modes */ +#define LOWPOWER_SRAMRETCTRL_RETEN_RAM10 (1UL << 6) /*!< Enable SRAM1_0 retention when entering in Low power modes */ +#define LOWPOWER_SRAMRETCTRL_RETEN_RAM20 (1UL << 7) /*!< Enable SRAM2_0 retention when entering in Low power modes */ +#define LOWPOWER_SRAMRETCTRL_RETEN_RAM30 (1UL << 8) /*!< Enable SRAM3_0 retention when entering in Low power modes */ +#define LOWPOWER_SRAMRETCTRL_RETEN_RAM31 (1UL << 9) /*!< Enable SRAM3_1 retention when entering in Low power modes */ +#define LOWPOWER_SRAMRETCTRL_RETEN_RAM40 (1UL << 10) /*!< Enable SRAM4_0 retention when entering in Low power modes */ +#define LOWPOWER_SRAMRETCTRL_RETEN_RAM41 (1UL << 11) /*!< Enable SRAM4_1 retention when entering in Low power modes */ +#define LOWPOWER_SRAMRETCTRL_RETEN_RAM42 (1UL << 12) /*!< Enable SRAM4_2 retention when entering in Low power modes */ +#define LOWPOWER_SRAMRETCTRL_RETEN_RAM43 (1UL << 13) /*!< Enable SRAM4_3 retention when entering in Low power modes */ +#define LOWPOWER_SRAMRETCTRL_RETEN_RAM_USB_HS (1UL << 14) /*!< Enable SRAM USB HS retention when entering in Low power modes */ +#define LOWPOWER_SRAMRETCTRL_RETEN_RAM_PUF (1UL << 15) /*!< Enable SRAM PUFF retention when entering in Low power modes */ + +/** + * @brief SRAM Low Power Modes + */ + +#define LOWPOWER_SRAM_LPMODE_MASK (0xFUL) +#define LOWPOWER_SRAM_LPMODE_ACTIVE (0x6UL) /*!< SRAM functional mode */ +#define LOWPOWER_SRAM_LPMODE_SLEEP (0xFUL) /*!< SRAM Sleep mode (Data retention, fast wake up) */ +#define LOWPOWER_SRAM_LPMODE_DEEPSLEEP (0x8UL) /*!< SRAM Deep Sleep mode (Data retention, slow wake up) */ +#define LOWPOWER_SRAM_LPMODE_SHUTDOWN (0x9UL) /*!< SRAM Shut Down mode (no data retention) */ +#define LOWPOWER_SRAM_LPMODE_POWERUP (0xAUL) /*!< SRAM is powering up */ + +/*@brief BOD VBAT level */ +typedef enum _power_bod_vbat_level +{ + kPOWER_BodVbatLevel1000mv = 0, /*!< Brown out detector VBAT level 1V */ + kPOWER_BodVbatLevel1100mv = 1, /*!< Brown out detector VBAT level 1.1V */ + kPOWER_BodVbatLevel1200mv = 2, /*!< Brown out detector VBAT level 1.2V */ + kPOWER_BodVbatLevel1300mv = 3, /*!< Brown out detector VBAT level 1.3V */ + kPOWER_BodVbatLevel1400mv = 4, /*!< Brown out detector VBAT level 1.4V */ + kPOWER_BodVbatLevel1500mv = 5, /*!< Brown out detector VBAT level 1.5V */ + kPOWER_BodVbatLevel1600mv = 6, /*!< Brown out detector VBAT level 1.6V */ + kPOWER_BodVbatLevel1650mv = 7, /*!< Brown out detector VBAT level 1.65V */ + kPOWER_BodVbatLevel1700mv = 8, /*!< Brown out detector VBAT level 1.7V */ + kPOWER_BodVbatLevel1750mv = 9, /*!< Brown out detector VBAT level 1.75V */ + kPOWER_BodVbatLevel1800mv = 10, /*!< Brown out detector VBAT level 1.8V */ + kPOWER_BodVbatLevel1900mv = 11, /*!< Brown out detector VBAT level 1.9V */ + kPOWER_BodVbatLevel2000mv = 12, /*!< Brown out detector VBAT level 2V */ + kPOWER_BodVbatLevel2100mv = 13, /*!< Brown out detector VBAT level 2.1V */ + kPOWER_BodVbatLevel2200mv = 14, /*!< Brown out detector VBAT level 2.2V */ + kPOWER_BodVbatLevel2300mv = 15, /*!< Brown out detector VBAT level 2.3V */ + kPOWER_BodVbatLevel2400mv = 16, /*!< Brown out detector VBAT level 2.4V */ + kPOWER_BodVbatLevel2500mv = 17, /*!< Brown out detector VBAT level 2.5V */ + kPOWER_BodVbatLevel2600mv = 18, /*!< Brown out detector VBAT level 2.6V */ + kPOWER_BodVbatLevel2700mv = 19, /*!< Brown out detector VBAT level 2.7V */ + kPOWER_BodVbatLevel2806mv = 20, /*!< Brown out detector VBAT level 2.806V */ + kPOWER_BodVbatLevel2900mv = 21, /*!< Brown out detector VBAT level 2.9V */ + kPOWER_BodVbatLevel3000mv = 22, /*!< Brown out detector VBAT level 3.0V */ + kPOWER_BodVbatLevel3100mv = 23, /*!< Brown out detector VBAT level 3.1V */ + kPOWER_BodVbatLevel3200mv = 24, /*!< Brown out detector VBAT level 3.2V */ + kPOWER_BodVbatLevel3300mv = 25, /*!< Brown out detector VBAT level 3.3V */ +} power_bod_vbat_level_t; + +/*@brief BOD core level */ +typedef enum _power_bod_core_level +{ + kPOWER_BodCoreLevel600mv = 0, /*!< Brown out detector core level 600mV */ + kPOWER_BodCoreLevel650mv = 1, /*!< Brown out detector core level 650mV */ + kPOWER_BodCoreLevel700mv = 2, /*!< Brown out detector core level 700mV */ + kPOWER_BodCoreLevel750mv = 3, /*!< Brown out detector core level 750mV */ + kPOWER_BodCoreLevel800mv = 4, /*!< Brown out detector core level 800mV */ + kPOWER_BodCoreLevel850mv = 5, /*!< Brown out detector core level 850mV */ + kPOWER_BodCoreLevel900mv = 6, /*!< Brown out detector core level 900mV */ + kPOWER_BodCoreLevel950mv = 7, /*!< Brown out detector core level 950mV */ +} power_bod_core_level_t; + +/*@brief BOD Hysteresis control */ +typedef enum _power_bod_hyst +{ + kPOWER_BodHystLevel25mv = 0U, /*!< BOD Hysteresis control level 25mv */ + kPOWER_BodHystLevel50mv = 1U, /*!< BOD Hysteresis control level 50mv */ + kPOWER_BodHystLevel75mv = 2U, /*!< BOD Hysteresis control level 75mv */ + kPOWER_BodHystLevel100mv = 3U, /*!< BOD Hysteresis control level 100mv */ +} power_bod_hyst_t; + +/** + * @brief LDO Voltage control in Low Power Modes + */ +#define LOWPOWER_VOLTAGE_LDO_PMU_INDEX 0 +#define LOWPOWER_VOLTAGE_LDO_PMU_MASK (0x1FULL << LOWPOWER_VOLTAGE_LDO_PMU_INDEX) +#define LOWPOWER_VOLTAGE_LDO_MEM_INDEX 5 +#define LOWPOWER_VOLTAGE_LDO_MEM_MASK (0x1FULL << LOWPOWER_VOLTAGE_LDO_MEM_INDEX) +#define LOWPOWER_VOLTAGE_LDO_DEEP_SLEEP_INDEX 10 +#define LOWPOWER_VOLTAGE_LDO_DEEP_SLEEP_MASK (0x7ULL << LOWPOWER_VOLTAGE_LDO_DEEP_SLEEP_INDEX) +#define LOWPOWER_VOLTAGE_LDO_PMU_BOOST_INDEX 19 +#define LOWPOWER_VOLTAGE_LDO_PMU_BOOST_MASK (0x1FULL << LOWPOWER_VOLTAGE_LDO_PMU_BOOST_INDEX) +#define LOWPOWER_VOLTAGE_LDO_MEM_BOOST_INDEX 24 +#define LOWPOWER_VOLTAGE_LDO_MEM_BOOST_MASK (0x1FULL << LOWPOWER_VOLTAGE_LDO_MEM_BOOST_INDEX) +#define LOWPOWER_VOLTAGE_DCDC_INDEX 29 +#define LOWPOWER_VOLTAGE_DCDC_MASK (0xFULL << LOWPOWER_VOLTAGE_DCDC_INDEX) + +/** + * @brief Always On and Memories LDO voltage settings + */ + +typedef enum _v_ao +{ + // V_AO_1P220 1.22 = 0, /*!< 1.22 V */ + V_AO_0P700 = 1, /*!< 0.7 V */ + V_AO_0P725 = 2, /*!< 0.725 V */ + V_AO_0P750 = 3, /*!< 0.75 V */ + V_AO_0P775 = 4, /*!< 0.775 V */ + V_AO_0P800 = 5, /*!< 0.8 V */ + V_AO_0P825 = 6, /*!< 0.825 V */ + V_AO_0P850 = 7, /*!< 0.85 V */ + V_AO_0P875 = 8, /*!< 0.875 V */ + V_AO_0P900 = 9, /*!< 0.9 V */ + V_AO_0P960 = 10, /*!< 0.96 V */ + V_AO_0P970 = 11, /*!< 0.97 V */ + V_AO_0P980 = 12, /*!< 0.98 V */ + V_AO_0P990 = 13, /*!< 0.99 V */ + V_AO_1P000 = 14, /*!< 1 V */ + V_AO_1P010 = 15, /*!< 1.01 V */ + V_AO_1P020 = 16, /*!< 1.02 V */ + V_AO_1P030 = 17, /*!< 1.03 V */ + V_AO_1P040 = 18, /*!< 1.04 V */ + V_AO_1P050 = 19, /*!< 1.05 V */ + V_AO_1P060 = 20, /*!< 1.06 V */ + V_AO_1P070 = 21, /*!< 1.07 V */ + V_AO_1P080 = 22, /*!< 1.08 V */ + V_AO_1P090 = 23, /*!< 1.09 V */ + V_AO_1P100 = 24, /*!< 1.1 V */ + V_AO_1P110 = 25, /*!< 1.11 V */ + V_AO_1P120 = 26, /*!< 1.12 V */ + V_AO_1P130 = 27, /*!< 1.13 V */ + V_AO_1P140 = 28, /*!< 1.14 V */ + V_AO_1P150 = 29, /*!< 1.15 V */ + V_AO_1P160 = 30, /*!< 1.16 V */ + V_AO_1P220 = 31 /*!< 1.22 V */ +} v_ao_t; + +/** + * @brief Deep Sleep LDO voltage settings + */ +typedef enum _v_deepsleep +{ + V_DEEPSLEEP_0P900 = 0, /*!< 0.9 V */ + V_DEEPSLEEP_0P925 = 1, /*!< 0.925 V */ + V_DEEPSLEEP_0P950 = 2, /*!< 0.95 V */ + V_DEEPSLEEP_0P975 = 3, /*!< 0.975 V */ + V_DEEPSLEEP_1P000 = 4, /*!< 1.000 V */ + V_DEEPSLEEP_1P025 = 5, /*!< 1.025 V */ + V_DEEPSLEEP_1P050 = 6, /*!< 1.050 V */ + V_DEEPSLEEP_1P075 = 7 /*!< 1.075 V */ +} v_deepsleep_t; + +/** + * @brief DCDC voltage settings + */ +typedef enum _v_dcdc +{ + V_DCDC_0P950 = 0, /*!< 0.95 V */ + V_DCDC_0P975 = 1, /*!< 0.975 V */ + V_DCDC_1P000 = 2, /*!< 1 V */ + V_DCDC_1P025 = 3, /*!< 1.025 V */ + V_DCDC_1P050 = 4, /*!< 1.050 V */ + V_DCDC_1P075 = 5, /*!< 1.075 V */ + V_DCDC_1P100 = 6, /*!< 1.1 V */ + V_DCDC_1P125 = 7, /*!< 1.125 V */ + V_DCDC_1P150 = 8, /*!< 1.150 V */ + V_DCDC_1P175 = 9, /*!< 1.175 V */ + V_DCDC_1P200 = 10 /*!< 1.2 V */ +} v_dcdc_t; +/** + * @brief LDO_FLASH_NV & LDO_USB voltage settings + */ +typedef enum _v_flashnv +{ + V_LDOFLASHNV_1P650 = 0, /*!< 0.95 V */ + V_LDOFLASHNV_1P700 = 1, /*!< 0.975 V */ + V_LDOFLASHNV_1P750 = 2, /*!< 1 V */ + V_LDOFLASHNV_0P800 = 3, /*!< 1.025 V */ + V_LDOFLASHNV_1P850 = 4, /*!< 1.050 V */ + V_LDOFLASHNV_1P900 = 5, /*!< 1.075 V */ + V_LDOFLASHNV_1P950 = 6, /*!< 1.1 V */ + V_LDOFLASHNV_2P000 = 7 /*!< 1.125 V */ +} v_flashnv_t; + +/** + * @brief Low Power Modes Wake up sources + */ + +#define WAKEUP_SYS (1ULL << 0) /*!< [SLEEP, DEEP SLEEP ] */ /* WWDT0_IRQ and BOD_IRQ*/ +#define WAKEUP_SDMA0 (1ULL << 1) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_GPIO_GLOBALINT0 (1ULL << 2) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */ +#define WAKEUP_GPIO_GLOBALINT1 (1ULL << 3) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */ +#define WAKEUP_GPIO_INT0_0 (1ULL << 4) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_GPIO_INT0_1 (1ULL << 5) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_GPIO_INT0_2 (1ULL << 6) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_GPIO_INT0_3 (1ULL << 7) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_UTICK (1ULL << 8) /*!< [SLEEP, ] */ +#define WAKEUP_MRT (1ULL << 9) /*!< [SLEEP, ] */ +#define WAKEUP_CTIMER0 (1ULL << 10) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_CTIMER1 (1ULL << 11) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_SCT (1ULL << 12) /*!< [SLEEP, ] */ +#define WAKEUP_CTIMER3 (1ULL << 13) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_FLEXCOMM0 (1ULL << 14) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_FLEXCOMM1 (1ULL << 15) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_FLEXCOMM2 (1ULL << 16) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_FLEXCOMM3 (1ULL << 17) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */ +#define WAKEUP_FLEXCOMM4 (1ULL << 18) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_FLEXCOMM5 (1ULL << 19) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_FLEXCOMM6 (1ULL << 20) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_FLEXCOMM7 (1ULL << 21) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_ADC (1ULL << 22) /*!< [SLEEP, ] */ +// reserved (1ULL << 23) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_ACMP_CAPT (1ULL << 24) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */ +// reserved (1ULL << 25) +// reserved (1ULL << 26) +#define WAKEUP_USB0_NEEDCLK (1ULL << 27) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_USB0 (1ULL << 28) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_RTC_LITE_ALARM_WAKEUP (1ULL << 29) /*!< [SLEEP, DEEP SLEEP, POWER DOWN, DEEP POWER DOWN] */ +#define WAKEUP_EZH_ARCH_B (1ULL << 30) /*!< [SLEEP, ] */ +#define WAKEUP_WAKEUP_MAILBOX (1ULL << 31) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */ +#define WAKEUP_GPIO_INT0_4 (1ULL << 32) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_GPIO_INT0_5 (1ULL << 33) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_GPIO_INT0_6 (1ULL << 34) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_GPIO_INT0_7 (1ULL << 35) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_CTIMER2 (1ULL << 36) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_CTIMER4 (1ULL << 37) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_OS_EVENT_TIMER (1ULL << 38) /*!< [SLEEP, DEEP SLEEP, POWER DOWN, DEEP POWER DOWN] */ +// reserved (1ULL << 39) +// reserved (1ULL << 40) +// reserved (1ULL << 41) +#define WAKEUP_SDIO (1ULL << 42) /*!< [SLEEP, ] */ +// reserved (1ULL << 43) +// reserved (1ULL << 44) +// reserved (1ULL << 45) +// reserved (1ULL << 46) +#define WAKEUP_USB1 (1ULL << 47) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_USB1_NEEDCLK (1ULL << 48) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_SEC_HYPERVISOR_CALL (1ULL << 49) /*!< [SLEEP, ] */ +#define WAKEUP_SEC_GPIO_INT0_0 (1ULL << 50) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_SEC_GPIO_INT0_1 (1ULL << 51) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_PLU (1ULL << 52) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_SEC_VIO (1ULL << 53) +#define WAKEUP_SHA (1ULL << 54) /*!< [SLEEP, ] */ +#define WAKEUP_CASPER (1ULL << 55) /*!< [SLEEP, ] */ +#define WAKEUP_PUFF (1ULL << 56) /*!< [SLEEP, ] */ +#define WAKEUP_PQ (1ULL << 57) /*!< [SLEEP, ] */ +#define WAKEUP_SDMA1 (1ULL << 58) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_LSPI_HS (1ULL << 59) /*!< [SLEEP, DEEP SLEEP ] */ +// reserved WAKEUP_PVTVF0_AMBER (1ULL << 60) +// reserved WAKEUP_PVTVF0_RED (1ULL << 61) +// reserved WAKEUP_PVTVF1_AMBER (1ULL << 62) +#define WAKEUP_ALLWAKEUPIOS (1ULL << 63) /*!< [ , DEEP POWER DOWN] */ + + +/** + * @brief Sleep Postpone + */ +#define LOWPOWER_HWWAKE_FORCED (1UL << 0) /*!< Force peripheral clocking to stay on during deep-sleep mode. */ +#define LOWPOWER_HWWAKE_PERIPHERALS (1UL << 1) /*!< Wake for Flexcomms. Any Flexcomm FIFO reaching the level specified by its own TXLVL will cause peripheral clocking to wake up temporarily while the related status is asserted */ +#define LOWPOWER_HWWAKE_SDMA0 (1UL << 3) /*!< Wake for DMA0. DMA0 being busy will cause peripheral clocking to remain running until DMA completes. Used in conjonction with LOWPOWER_HWWAKE_PERIPHERALS */ +#define LOWPOWER_HWWAKE_SDMA1 (1UL << 5) /*!< Wake for DMA1. DMA0 being busy will cause peripheral clocking to remain running until DMA completes. Used in conjonction with LOWPOWER_HWWAKE_PERIPHERALS */ +#define LOWPOWER_HWWAKE_ENABLE_FRO192M (1UL << 31) /*!< Need to be set if FRO192M is disable - via PDCTRL0 - in Deep Sleep mode and any of LOWPOWER_HWWAKE_PERIPHERALS, LOWPOWER_HWWAKE_SDMA0 or LOWPOWER_HWWAKE_SDMA1 is set */ + +/** + * @brief Wake up I/O sources + */ +#define LOWPOWER_WAKEUPIOSRC_PIO0_INDEX 0 /*!< Pin P1( 1) */ +#define LOWPOWER_WAKEUPIOSRC_PIO1_INDEX 2 /*!< Pin P0(28) */ +#define LOWPOWER_WAKEUPIOSRC_PIO2_INDEX 4 /*!< Pin P1(18) */ +#define LOWPOWER_WAKEUPIOSRC_PIO3_INDEX 6 /*!< Pin P1(30) */ + +#define LOWPOWER_WAKEUPIOSRC_DISABLE 0 /*!< Wake up is disable */ +#define LOWPOWER_WAKEUPIOSRC_RISING 1 /*!< Wake up on rising edge */ +#define LOWPOWER_WAKEUPIOSRC_FALLING 2 /*!< Wake up on falling edge */ +#define LOWPOWER_WAKEUPIOSRC_RISING_FALLING 3 /*!< Wake up on both rising or falling edges */ + +#define LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_INDEX 8 /*!< Wake-up I/O 0 pull-up/down configuration index */ +#define LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_INDEX 9 /*!< Wake-up I/O 1 pull-up/down configuration index */ +#define LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_INDEX 10 /*!< Wake-up I/O 2 pull-up/down configuration index */ +#define LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_INDEX 11 /*!< Wake-up I/O 3 pull-up/down configuration index */ + +#define LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_MASK (1UL << LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_INDEX) /*!< Wake-up I/O 0 pull-up/down mask */ +#define LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_MASK (1UL << LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_INDEX) /*!< Wake-up I/O 1 pull-up/down mask */ +#define LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_MASK (1UL << LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_INDEX) /*!< Wake-up I/O 2 pull-up/down mask */ +#define LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_MASK (1UL << LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_INDEX) /*!< Wake-up I/O 3 pull-up/down mask */ + +#define LOWPOWER_WAKEUPIO_PULLDOWN 0 /*!< Select pull-down */ +#define LOWPOWER_WAKEUPIO_PULLUP 1 /*!< Select pull-up */ + +/** + * @brief Wake up timers configuration in Low Power Modes + */ +#define LOWPOWER_TIMERCFG_CTRL_INDEX 0 +#define LOWPOWER_TIMERCFG_CTRL_MASK (0x1UL << LOWPOWER_TIMERCFG_CTRL_INDEX) +#define LOWPOWER_TIMERCFG_TIMER_INDEX 1 +#define LOWPOWER_TIMERCFG_TIMER_MASK (0x7UL << LOWPOWER_TIMERCFG_TIMER_INDEX) +#define LOWPOWER_TIMERCFG_OSC32K_INDEX 4 +#define LOWPOWER_TIMERCFG_OSC32K_MASK (0x1UL << LOWPOWER_TIMERCFG_OSC32K_INDEX) + +#define LOWPOWER_TIMERCFG_CTRL_DISABLE 0 /*!< Wake Timer Disable */ +#define LOWPOWER_TIMERCFG_CTRL_ENABLE 1 /*!< Wake Timer Enable */ + +/** + * @brief Primary Wake up timers configuration in Low Power Modes + */ +#define LOWPOWER_TIMERCFG_TIMER_RTC1KHZ 0 /*!< 1 KHz Real Time Counter (RTC) used as wake up source */ +#define LOWPOWER_TIMERCFG_TIMER_RTC1HZ 1 /*!< 1 Hz Real Time Counter (RTC) used as wake up source */ +#define LOWPOWER_TIMERCFG_TIMER_OSTIMER 2 /*!< OS Event Timer used as wake up source */ + +#define LOWPOWER_TIMERCFG_OSC32K_FRO32KHZ 0 /*!< Wake up Timers uses FRO 32 KHz as clock source */ +#define LOWPOWER_TIMERCFG_OSC32K_XTAL32KHZ 1 /*!< Wake up Timers uses Chrystal 32 KHz as clock source */ + +//! @brief Interface for lowpower functions +typedef struct LowpowerDriverInterface +{ + void (*power_cycle_cpu_and_flash)(void); + void (*set_lowpower_mode)(LPC_LOWPOWER_T *p_lowpower_cfg); +} lowpower_driver_interface_t; + +/* Power mode configuration API parameter */ +typedef enum _power_mode_config +{ + kPmu_Sleep = 0U, + kPmu_Deep_Sleep = 1U, + kPmu_PowerDown = 2U, + kPmu_Deep_PowerDown = 3U, +} power_mode_cfg_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * @brief API to enable PDRUNCFG bit in the Syscon. Note that enabling the bit powers down the peripheral + * + * @param en peripheral for which to enable the PDRUNCFG bit + * @return none + */ +static inline void POWER_EnablePD(pd_bit_t en) +{ + /* PDRUNCFGSET */ + PMC->PDRUNCFGSET0 = en; +} + +/*! + * @brief API to disable PDRUNCFG bit in the Syscon. Note that disabling the bit powers up the peripheral + * + * @param en peripheral for which to disable the PDRUNCFG bit + * @return none + */ +static inline void POWER_DisablePD(pd_bit_t en) +{ + /* PDRUNCFGCLR */ + PMC->PDRUNCFGCLR0 = en; +} + +/*! + * @brief set BOD VBAT level. + * + * @param level BOD detect level + * @param hyst BoD Hysteresis control + * @param enBodVbatReset VBAT brown out detect reset + */ +static inline void POWER_SetBodVbatLevel(power_bod_vbat_level_t level, power_bod_hyst_t hyst, bool enBodVbatReset) +{ + PMC->BODVBAT = (PMC->BODVBAT & (~(PMC_BODVBAT_TRIGLVL_MASK | PMC_BODVBAT_HYST_MASK))) | PMC_BODVBAT_TRIGLVL(level) | + PMC_BODVBAT_HYST(hyst); + PMC->RESETCTRL = + (PMC->RESETCTRL & (~PMC_RESETCTRL_BODVBATRESETENABLE_MASK)) | PMC_RESETCTRL_BODVBATRESETENABLE(enBodVbatReset); +} + +/*! + * @brief set BOD core level. + * + * @param level BOD detect level + * @param hyst BoD Hysteresis control + * @param enBodCoreReset core brown out detect reset + */ +static inline void POWER_SetBodCoreLevel(power_bod_core_level_t level, power_bod_hyst_t hyst, bool enBodCoreReset) +{ + PMC->BODCORE = (PMC->BODCORE & (~(PMC_BODCORE_TRIGLVL_MASK | PMC_BODCORE_HYST_MASK))) | PMC_BODCORE_TRIGLVL(level) | + PMC_BODCORE_HYST(hyst); + PMC->RESETCTRL = + (PMC->RESETCTRL & (~PMC_RESETCTRL_BODCORERESETENABLE_MASK)) | PMC_RESETCTRL_BODCORERESETENABLE(enBodCoreReset); +} + +/*! + * @brief API to enable deep sleep bit in the ARM Core. + * + * @param none + * @return none + */ +static inline void POWER_EnableDeepSleep(void) +{ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; +} + +/*! + * @brief API to disable deep sleep bit in the ARM Core. + * + * @param none + * @return none + */ +static inline void POWER_DisableDeepSleep(void) +{ + SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; +} + +/*! + * @brief API to power down flash controller. + * + * @param none + * @return none + */ +static inline void POWER_PowerDownFlash(void) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* TURN OFF clock ip_2113 (only needed for FLASH programming, will be turned on by ROM API) */ + CLOCK_DisableClock(kCLOCK_Flash); + + /* TURN OFF clock ip_2113 (only needed for FLASH programming, will be turned on by ROM API) */ + CLOCK_DisableClock(kCLOCK_Fmc); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * @brief API to power up flash controller. + * + * @param none + * @return none + */ +static inline void POWER_PowerUpFlash(void) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* TURN OFF clock ip_2113 (only needed for FLASH programming, will be turned on by ROM API) */ + CLOCK_EnableClock(kCLOCK_Fmc); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/** + * @brief Configures and enters in low power mode + * @param p_lowpower_cfg: pointer to a structure that contains all low power mode parameters + * @return Nothing + * + * !!! IMPORTANT NOTES : + * 1 - CPU Interrupt Enable registers are updated with p_lowpower_cfg->WAKEUPINT. They are NOT restored by the + * API. + * 2 - The Non Maskable Interrupt (NMI) should be disable before calling this API (otherwise, there is a risk + * of Dead Lock). + * 3 - The HARD FAULT handler should execute from SRAM. (The Hard fault handler should initiate a full chip + * reset) + */ +void POWER_EnterLowPower(LPC_LOWPOWER_T *p_lowpower_cfg); + +/** + * @brief Shut off the Flash and execute the _WFI(), then power up the Flash after wake-up event + * This MUST BE EXECUTED outside the Flash: + * either from ROM or from SRAM. The rest could stay in Flash. But, for consistency, it is + * preferable to have all functions defined in this file implemented in ROM. + * @param None + * @return Nothing + */ +void POWER_CycleCpuAndFlash(void); + +/** + * @brief Configures and enters in DEEP-SLEEP low power mode + * @param exclude_from_pd: + * @param sram_retention_ctrl: + * @param wakeup_interrupts: + * @param hardware_wake_ctrl: + + * @return Nothing + * + * !!! IMPORTANT NOTES : + 0 - CPU0 & System CLock frequency is switched to FRO12MHz and is NOT restored back by the API. + * 1 - CPU0 Interrupt Enable registers (NVIC->ISER) are modified by this function. They are restored back in case of CPU retention or if POWERDOWN is not taken (for instance because an interrupt is pending). + * 2 - The Non Maskable Interrupt (NMI) is disabled and its configuration before calling this function will be restored back if POWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending). + * 3 - The HARD FAULT handler should execute from SRAM. (The Hard fault handler should initiate a full chip reset) + reset) + */ +void POWER_EnterDeepSleep(uint32_t exclude_from_pd, uint32_t sram_retention_ctrl, uint64_t wakeup_interrupts,uint32_t hardware_wake_ctrl); + +/** + * @brief Configures and enters in POWERDOWN low power mode + * @param exclude_from_pd: + * @param sram_retention_ctrl: + * @param wakeup_interrupts: + * @param cpu_retention_ctrl: 0 = CPU retention is disable / 1 = CPU retention is enabled, all other values are + RESERVED. + + * @return Nothing + * + * !!! IMPORTANT NOTES : + 0 - CPU0 & System CLock frequency is switched to FRO12MHz and is NOT restored back by the API. + * 1 - CPU0 Interrupt Enable registers (NVIC->ISER) are modified by this function. They are restored back in case of CPU retention or if POWERDOWN is not taken (for instance because an interrupt is pending). + * 2 - The Non Maskable Interrupt (NMI) is disabled and its configuration before calling this function will be restored back if POWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending). + * 3 - In case of CPU retention, it is the responsability of the user to make sure that SRAM instance containing the stack used to call this function WILL BE preserved during low power (via parameter "sram_retention_ctrl") + * 4 - The HARD FAULT handler should execute from SRAM. (The Hard fault handler should initiate a full chip reset) + reset) + */ +void POWER_EnterPowerDown(uint32_t exclude_from_pd, uint32_t sram_retention_ctrl, uint64_t wakeup_interrupts, uint32_t cpu_retention_ctrl); + +/** + * @brief Configures and enters in DEEPPOWERDOWN low power mode + * @param exclude_from_pd: + * @param sram_retention_ctrl: + * @param wakeup_interrupts: + * @param wakeup_io_ctrl: + + * @return Nothing + * + * !!! IMPORTANT NOTES : + 0 - CPU0 & System CLock frequency is switched to FRO12MHz and is NOT restored back by the API. + * 1 - CPU0 Interrupt Enable registers (NVIC->ISER) are modified by this function. They are restored back if DEEPPOWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending). + * 2 - The Non Maskable Interrupt (NMI) is disabled and its configuration before calling this function will be restored back if DEEPPOWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending). + * 3 - The HARD FAULT handler should execute from SRAM. (The Hard fault handler should initiate a full chip reset) + */ +void POWER_EnterDeepPowerDown(uint32_t exclude_from_pd, uint32_t sram_retention_ctrl, uint64_t wakeup_interrupts, uint32_t wakeup_io_ctrl); + +/** + * @brief Configures and enters in SLEEP low power mode + * @param : + * @return Nothing + */ +void POWER_EnterSleep(void); + +/*! + * @brief Power Library API to choose normal regulation and set the voltage for the desired operating frequency. + * + * @param system_freq_hz - The desired frequency (in Hertz) at which the part would like to operate, + * note that the voltage and flash wait states should be set before changing frequency + * @return none + */ +void POWER_SetVoltageForFreq(uint32_t system_freq_hz); + +/*! + * @brief Power Library API to return the library version. + * + * @param none + * @return version number of the power library + */ +uint32_t POWER_GetLibVersion(void); + +/** + * @brief Sets board-specific trim values for 16MHz XTAL + * @param pi32_32MfXtalIecLoadpF_x100 Load capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120 + * @param pi32_32MfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120 + * @param pi32_32MfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120 + * @return none + * @note Following default Values can be used: + * pi32_32MfXtalIecLoadpF_x100 Load capacitance, pF x 100 : 600 + * pi32_32MfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100 : 20 + * pi32_32MfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100 : 40 + */ +extern void POWER_Xtal16mhzCapabankTrim(int32_t pi32_16MfXtalIecLoadpF_x100, int32_t pi32_16MfXtalPPcbParCappF_x100, int32_t pi32_16MfXtalNPcbParCappF_x100); +/** + * @brief Sets board-specific trim values for 32kHz XTAL + * @param pi32_32kfXtalIecLoadpF_x100 Load capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120 + * @param pi32_32kfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120 + * @param pi32_32kfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120 + + * @return none + * @note Following default Values can be used: + * pi32_32kfXtalIecLoadpF_x100 Load capacitance, pF x 100 : 600 + * pi32_32kfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100 : 40 + * pi32_32kfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100 : 40 + */ +extern void POWER_Xtal32khzCapabankTrim(int32_t pi32_32kfXtalIecLoadpF_x100, int32_t pi32_32kfXtalPPcbParCappF_x100, int32_t pi32_32kfXtalNPcbParCappF_x100); +/** + * @brief Enables and sets LDO for 16MHz XTAL + * @param none + * @return none + */ +extern void POWER_SetXtal16mhzLdo(void); +/** + * @brief Set up 16-MHz XTAL Trimmings + * @param amp Amplitude + * @param gm Transconductance + * @return none + */ +extern void POWER_SetXtal16mhzTrim(uint32_t amp, uint32_t gm); +#ifdef __cplusplus + } +#endif + +/** + * @} + */ + +#endif /* _FSL_POWER_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_powerquad.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_powerquad.h new file mode 100644 index 000000000..573b6f371 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_powerquad.h @@ -0,0 +1,2706 @@ +/* + * Copyright 2018-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_POWERQUAD_H_ +#define _FSL_POWERQUAD_H_ + +#if defined(__CC_ARM) + +#elif defined(__ICCARM__) +#include +#elif defined(__GNUC__) +#include +#endif /* defined(__CC_ARM) */ + +#include "fsl_common.h" +#include "fsl_powerquad_data.h" + +/*! + * @addtogroup powerquad + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_POWERQUAD_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*!< Version 2.0.1. */ +/*@}*/ + +#define PQ_FLOAT32 0U +#define PQ_FIXEDPT 1U + +#define CP_PQ 0U +#define CP_MTX 1U +#define CP_FFT 2U +#define CP_FIR 3U +#define CP_CORDIC 5U + +#define PQ_TRANS 0U +#define PQ_TRIG 1U +#define PQ_BIQUAD 2U + +#define PQ_TRANS_FIXED 4U +#define PQ_TRIG_FIXED 5U +#define PQ_BIQUAD_FIXED 6U + +#define PQ_INV 0U +#define PQ_LN 1U +#define PQ_SQRT 2U +#define PQ_INVSQRT 3U +#define PQ_ETOX 4U +#define PQ_ETONX 5U +#define PQ_DIV 6U + +#define PQ_SIN 0U +#define PQ_COS 1U + +#define PQ_BIQ0_CALC 1U +#define PQ_BIQ1_CALC 1U + +#define PQ_COMP0_ONLY (0U << 1) +#define PQ_COMP1_ONLY (1U << 1) + +#define CORDIC_ITER(x) (x << 2) +#define CORDIC_MIU(x) (x << 1) +#define CORDIC_T(x) (x << 0) +#define CORDIC_ARCTAN CORDIC_T(1) | CORDIC_MIU(0) +#define CORDIC_ARCTANH CORDIC_T(1) | CORDIC_MIU(1) + +#define INST_BUSY 0x80000000U + +#define PQ_ERRSTAT_OVERFLOW 0U +#define PQ_ERRSTAT_NAN 1U +#define PQ_ERRSTAT_FIXEDOVERFLOW 2U +#define PQ_ERRSTAT_UNDERFLOW 3U + +#define PQ_TRANS_CFFT 0U +#define PQ_TRANS_IFFT 1U +#define PQ_TRANS_CDCT 2U +#define PQ_TRANS_IDCT 3U +#define PQ_TRANS_RFFT 4U +#define PQ_TRANS_RDCT 6U + +#define PQ_MTX_SCALE 1U +#define PQ_MTX_MULT 2U +#define PQ_MTX_ADD 3U +#define PQ_MTX_INV 4U +#define PQ_MTX_PROD 5U +#define PQ_MTX_SUB 7U +#define PQ_VEC_DOTP 9U +#define PQ_MTX_TRAN 10U + +/* FIR engine operation type */ +#define PQ_FIR_FIR 0U +#define PQ_FIR_CONVOLUTION 1U +#define PQ_FIR_CORRELATION 2U +#define PQ_FIR_INCREMENTAL 4U + +#define _pq_ln0(x) __arm_mcr(CP_PQ, PQ_LN, x, PQ_FLOAT32 | PQ_COMP0_ONLY, 0, PQ_TRANS) +#define _pq_inv0(x) __arm_mcr(CP_PQ, PQ_INV, x, PQ_FLOAT32 | PQ_COMP0_ONLY, 0, PQ_TRANS) +#define _pq_sqrt0(x) __arm_mcr(CP_PQ, PQ_SQRT, x, PQ_FLOAT32 | PQ_COMP0_ONLY, 0, PQ_TRANS) +#define _pq_invsqrt0(x) __arm_mcr(CP_PQ, PQ_INVSQRT, x, PQ_FLOAT32 | PQ_COMP0_ONLY, 0, PQ_TRANS) +#define _pq_etox0(x) __arm_mcr(CP_PQ, PQ_ETOX, x, PQ_FLOAT32 | PQ_COMP0_ONLY, 0, PQ_TRANS) +#define _pq_etonx0(x) __arm_mcr(CP_PQ, PQ_ETONX, x, PQ_FLOAT32 | PQ_COMP0_ONLY, 0, PQ_TRANS) +#define _pq_sin0(x) __arm_mcr(CP_PQ, PQ_SIN, x, PQ_FLOAT32 | PQ_COMP0_ONLY, 0, PQ_TRIG) +#define _pq_cos0(x) __arm_mcr(CP_PQ, PQ_COS, x, PQ_FLOAT32 | PQ_COMP0_ONLY, 0, PQ_TRIG) +#define _pq_biquad0(x) __arm_mcr(CP_PQ, PQ_BIQ0_CALC, x, PQ_FLOAT32 | PQ_COMP0_ONLY, 0, PQ_BIQUAD) + +#define _pq_ln_fx0(x) __arm_mcr(CP_PQ, PQ_LN, x, PQ_FIXEDPT | PQ_COMP0_ONLY, 0, PQ_TRANS_FIXED) +#define _pq_inv_fx0(x) __arm_mcr(CP_PQ, PQ_INV, x, PQ_FIXEDPT | PQ_COMP0_ONLY, 0, PQ_TRANS_FIXED) +#define _pq_sqrt_fx0(x) __arm_mcr(CP_PQ, PQ_SQRT, x, PQ_FIXEDPT | PQ_COMP0_ONLY, 0, PQ_TRANS_FIXED) +#define _pq_invsqrt_fx0(x) __arm_mcr(CP_PQ, PQ_INVSQRT, x, PQ_FIXEDPT | PQ_COMP0_ONLY, 0, PQ_TRANS_FIXED) +#define _pq_etox_fx0(x) __arm_mcr(CP_PQ, PQ_ETOX, x, PQ_FIXEDPT | PQ_COMP0_ONLY, 0, PQ_TRANS_FIXED) +#define _pq_etonx_fx0(x) __arm_mcr(CP_PQ, PQ_ETONX, x, PQ_FIXEDPT | PQ_COMP0_ONLY, 0, PQ_TRANS_FIXED) +#define _pq_sin_fx0(x) __arm_mcr(CP_PQ, PQ_SIN, x, PQ_FIXEDPT | PQ_COMP0_ONLY, 0, PQ_TRIG_FIXED) +#define _pq_cos_fx0(x) __arm_mcr(CP_PQ, PQ_COS, x, PQ_FIXEDPT | PQ_COMP0_ONLY, 0, PQ_TRIG_FIXED) +#define _pq_biquad0_fx(x) __arm_mcr(CP_PQ, PQ_BIQ0_CALC, x, PQ_FIXEDPT | PQ_COMP0_ONLY, 0, PQ_BIQUAD_FIXED) + +#define _pq_div0(x) __arm_mcrr(CP_PQ, PQ_FLOAT32 | PQ_COMP0_ONLY, x, PQ_DIV) +#define _pq_div1(x) __arm_mcrr(CP_PQ, PQ_FLOAT32 | PQ_COMP1_ONLY, x, PQ_DIV) + +#define _pq_ln1(x) __arm_mcr(CP_PQ, PQ_LN, x, PQ_FLOAT32 | PQ_COMP1_ONLY, 0, PQ_TRANS) +#define _pq_inv1(x) __arm_mcr(CP_PQ, PQ_INV, x, PQ_FLOAT32 | PQ_COMP1_ONLY, 0, PQ_TRANS) +#define _pq_sqrt1(x) __arm_mcr(CP_PQ, PQ_SQRT, x, PQ_FLOAT32 | PQ_COMP1_ONLY, 0, PQ_TRANS) +#define _pq_invsqrt1(x) __arm_mcr(CP_PQ, PQ_INVSQRT, x, PQ_FLOAT32 | PQ_COMP1_ONLY, 0, PQ_TRANS) +#define _pq_etox1(x) __arm_mcr(CP_PQ, PQ_ETOX, x, PQ_FLOAT32 | PQ_COMP1_ONLY, 0, PQ_TRANS) +#define _pq_etonx1(x) __arm_mcr(CP_PQ, PQ_ETONX, x, PQ_FLOAT32 | PQ_COMP1_ONLY, 0, PQ_TRANS) +#define _pq_sin1(x) __arm_mcr(CP_PQ, PQ_SIN, x, PQ_FLOAT32 | PQ_COMP1_ONLY, 0, PQ_TRIG) +#define _pq_cos1(x) __arm_mcr(CP_PQ, PQ_COS, x, PQ_FLOAT32 | PQ_COMP1_ONLY, 0, PQ_TRIG) +#define _pq_biquad1(x) __arm_mcr(CP_PQ, PQ_BIQ1_CALC, x, PQ_FLOAT32 | PQ_COMP1_ONLY, 0, PQ_BIQUAD) + +#define _pq_ln_fx1(x) __arm_mcr(CP_PQ, PQ_LN, x, PQ_FIXEDPT | PQ_COMP1_ONLY, 0, PQ_TRANS_FIXED) +#define _pq_inv_fx1(x) __arm_mcr(CP_PQ, PQ_INV, x, PQ_FIXEDPT | PQ_COMP1_ONLY, 0, PQ_TRANS_FIXED) +#define _pq_sqrt_fx1(x) __arm_mcr(CP_PQ, PQ_SQRT, x, PQ_FIXEDPT | PQ_COMP1_ONLY, 0, PQ_TRANS_FIXED) +#define _pq_invsqrt_fx1(x) __arm_mcr(CP_PQ, PQ_INVSQRT, x, PQ_FIXEDPT | PQ_COMP1_ONLY, 0, PQ_TRANS_FIXED) +#define _pq_etox_fx1(x) __arm_mcr(CP_PQ, PQ_ETOX, x, PQ_FIXEDPT | PQ_COMP1_ONLY, 0, PQ_TRANS_FIXED) +#define _pq_etonx_fx1(x) __arm_mcr(CP_PQ, PQ_ETONX, x, PQ_FIXEDPT | PQ_COMP1_ONLY, 0, PQ_TRANS_FIXED) +#define _pq_sin_fx1(x) __arm_mcr(CP_PQ, PQ_SIN, x, PQ_FIXEDPT | PQ_COMP1_ONLY, 0, PQ_TRIG_FIXED) +#define _pq_cos_fx1(x) __arm_mcr(CP_PQ, PQ_COS, x, PQ_FIXEDPT | PQ_COMP1_ONLY, 0, PQ_TRIG_FIXED) +#define _pq_biquad1_fx(x) __arm_mcr(CP_PQ, PQ_BIQ1_CALC, x, PQ_FIXEDPT | PQ_COMP1_ONLY, 0, PQ_BIQUAD_FIXED) + +#define _pq_readMult0() __arm_mrc(CP_PQ, 0, PQ_FLOAT32 | PQ_COMP0_ONLY, 0, 0) +#define _pq_readAdd0() __arm_mrc(CP_PQ, 1, PQ_FLOAT32 | PQ_COMP0_ONLY, 0, 0) +#define _pq_readMult1() __arm_mrc(CP_PQ, 0, PQ_FLOAT32 | PQ_COMP1_ONLY, 0, 0) +#define _pq_readAdd1() __arm_mrc(CP_PQ, 1, PQ_FLOAT32 | PQ_COMP1_ONLY, 0, 0) +#define _pq_readMult0_fx() __arm_mrc(CP_PQ, 0, PQ_FIXEDPT | PQ_COMP0_ONLY, 0, 0) +#define _pq_readAdd0_fx() __arm_mrc(CP_PQ, 1, PQ_FIXEDPT | PQ_COMP0_ONLY, 0, 0) +#define _pq_readMult1_fx() __arm_mrc(CP_PQ, 0, PQ_FIXEDPT | PQ_COMP1_ONLY, 0, 0) +#define _pq_readAdd1_fx() __arm_mrc(CP_PQ, 1, PQ_FIXEDPT | PQ_COMP1_ONLY, 0, 0) + +/*! Parameter used for vector ln(x) */ +#define PQ_LN_INF PQ_LN, 1, PQ_TRANS +/*! Parameter used for vector 1/x */ +#define PQ_INV_INF PQ_INV, 0, PQ_TRANS +/*! Parameter used for vector sqrt(x) */ +#define PQ_SQRT_INF PQ_SQRT, 0, PQ_TRANS +/*! Parameter used for vector 1/sqrt(x) */ +#define PQ_ISQRT_INF PQ_INVSQRT, 0, PQ_TRANS +/*! Parameter used for vector e^x */ +#define PQ_ETOX_INF PQ_ETOX, 0, PQ_TRANS +/*! Parameter used for vector e^(-x) */ +#define PQ_ETONX_INF PQ_ETONX, 0, PQ_TRANS +/*! Parameter used for vector sin(x) */ +#define PQ_SIN_INF PQ_SIN, 1, PQ_TRIG +/*! Parameter used for vector cos(x) */ +#define PQ_COS_INF PQ_COS, 1, PQ_TRIG + +/* + * Register assignment for the vector calculation assembly. + * r0: pSrc, r1: pDest, r2-r7: Data + */ + +#define PQ_RUN_OPCODE_R3_R2(BATCH_OPCODE, BATCH_MACHINE) \ + __asm volatile( \ + " MCR p0,%[opcode],r3,c2,c0,%[machine] \n" \ + " MCR p0,%[opcode],r2,c0,c0,%[machine] \n" ::[opcode] "i"(BATCH_OPCODE), \ + [machine] "i"(BATCH_MACHINE)) + +#define PQ_RUN_OPCODE_R5_R4(BATCH_OPCODE, BATCH_MACHINE) \ + __asm volatile( \ + " MCR p0,%[opcode],r5,c2,c0,%[machine] \n" \ + " MCR p0,%[opcode],r4,c0,c0,%[machine] \n" ::[opcode] "i"(BATCH_OPCODE), \ + [machine] "i"(BATCH_MACHINE)) + +#define PQ_RUN_OPCODE_R7_R6(BATCH_OPCODE, BATCH_MACHINE) \ + __asm volatile( \ + " MCR p0,%[opcode],r7,c2,c0,%[machine] \n" \ + " MCR p0,%[opcode],r6,c0,c0,%[machine] \n" ::[opcode] "i"(BATCH_OPCODE), \ + [machine] "i"(BATCH_MACHINE)) + +#define PQ_Vector8_FP(middle, last, BATCH_OPCODE, DOUBLE_READ_ADDERS, BATCH_MACHINE) \ + PQ_RUN_OPCODE_R3_R2(BATCH_OPCODE, BATCH_MACHINE); \ + if (middle) \ + { \ + __asm volatile("STRD r4,r5,[r1],#8"); /* store fourth two results */ \ + } \ + __asm volatile("LDMIA r0!,{r4-r5}"); /* load next 2 datas */ \ + if (DOUBLE_READ_ADDERS) \ + { \ + __asm volatile("MRRC p0,#0,r2,r3,c1"); \ + } \ + else \ + { \ + __asm volatile("MRRC p0,#0,r2,r3,c0"); \ + } \ + PQ_RUN_OPCODE_R5_R4(BATCH_OPCODE, BATCH_MACHINE); \ + __asm volatile("STRD r2,r3,[r1],#8"); /* store first two results */ \ + __asm volatile("LDMIA r0!,{r6-r7}"); /* load next 2 datas */ \ + if (DOUBLE_READ_ADDERS) \ + { \ + __asm volatile("MRRC p0,#0,r4,r5,c1"); \ + } \ + else \ + { \ + __asm volatile("MRRC p0,#0,r4,r5,c0"); \ + } \ + PQ_RUN_OPCODE_R7_R6(BATCH_OPCODE, BATCH_MACHINE); \ + __asm volatile("STRD r4,r5,[r1],#8"); /* store second two results */ \ + __asm volatile("LDRD r4,r5,[r0],#8"); /* load last 2 of the 8 */ \ + if (DOUBLE_READ_ADDERS) \ + { \ + __asm volatile("MRRC p0,#0,r6,r7,c1"); \ + } \ + else \ + { \ + __asm volatile("MRRC p0,#0,r6,r7,c0"); \ + } \ + PQ_RUN_OPCODE_R5_R4(BATCH_OPCODE, BATCH_MACHINE); \ + __asm volatile("STRD r6,r7,[r1],#8"); /* store third two results */ \ + if (!last) \ + { \ + __asm volatile("LDRD r2,r3,[r0],#8"); /* load first two of next 8 */ \ + } \ + else \ + { \ + __asm volatile("NOP"); \ + } \ + if (DOUBLE_READ_ADDERS) \ + { \ + __asm volatile("MRRC p0,#0,r4,r5,c1"); \ + } \ + else \ + { \ + __asm volatile("MRRC p0,#0,r4,r5,c0"); \ + } \ + if (last) \ + { \ + __asm volatile("STRD r4,r5,[r1],#8"); /* store fourth two results */ \ + } + +#define PQ_RUN_OPCODE_R2_R3(BATCH_OPCODE, BATCH_MACHINE) \ + __asm volatile( \ + " MCR p0,%[opcode],r2,c1,c0,%[machine] \n" \ + " MCR p0,%[opcode],r3,c3,c0,%[machine] \n" ::[opcode] "i"(BATCH_OPCODE), \ + [machine] "i"(BATCH_MACHINE)) + +#define PQ_RUN_OPCODE_R4_R5(BATCH_OPCODE, BATCH_MACHINE) \ + __asm volatile( \ + " MCR p0,%[opcode],r4,c1,c0,%[machine] \n" \ + " MCR p0,%[opcode],r5,c3,c0,%[machine] \n" ::[opcode] "i"(BATCH_OPCODE), \ + [machine] "i"(BATCH_MACHINE)) + +#define PQ_RUN_OPCODE_R6_R7(BATCH_OPCODE, BATCH_MACHINE) \ + __asm volatile( \ + " MCR p0,%[opcode],r6,c1,c0,%[machine] \n" \ + " MCR p0,%[opcode],r7,c3,c0,%[machine] \n" ::[opcode] "i"(BATCH_OPCODE), \ + [machine] "i"(BATCH_MACHINE)) + +#define PQ_Vector8_FX(middle, last, BATCH_OPCODE, DOUBLE_READ_ADDERS, BATCH_MACHINE) \ + PQ_RUN_OPCODE_R2_R3(BATCH_OPCODE, BATCH_MACHINE); \ + if (middle) \ + { \ + __asm volatile("STRD r4,r5,[r1],#8"); /* store fourth two results */ \ + } \ + __asm volatile("LDMIA r0!,{r4-r7}"); /* load next 4 datas */ \ + if (DOUBLE_READ_ADDERS) \ + { \ + __asm volatile("MRC p0,#0x1,r2,c1,c0,#0"); \ + __asm volatile("MRC p0,#0x1,r3,c3,c0,#0"); \ + } \ + else \ + { \ + __asm volatile("MRC p0,#0,r2,c1,c0,#0"); \ + __asm volatile("MRC p0,#0,r3,c3,c0,#0"); \ + } \ + PQ_RUN_OPCODE_R4_R5(BATCH_OPCODE, BATCH_MACHINE); \ + __asm volatile("STRD r2,r3,[r1],#8"); /* store first two results */ \ + if (DOUBLE_READ_ADDERS) \ + { \ + __asm volatile("MRC p0,#0x1,r4,c1,c0,#0"); \ + __asm volatile("MRC p0,#0x1,r5,c3,c0,#0"); \ + } \ + else \ + { \ + __asm volatile("MRC p0,#0,r4,c1,c0,#0"); \ + __asm volatile("MRC p0,#0,r5,c3,c0,#0"); \ + } \ + PQ_RUN_OPCODE_R6_R7(BATCH_OPCODE, BATCH_MACHINE); \ + __asm volatile("STRD r4,r5,[r1],#8"); /* store second two results */ \ + __asm volatile("LDRD r4,r5,[r0],#8"); /* load last 2 of the 8 */ \ + if (DOUBLE_READ_ADDERS) \ + { \ + __asm volatile("MRC p0,#0x1,r6,c1,c0,#0"); \ + __asm volatile("MRC p0,#0x1,r7,c3,c0,#0"); \ + } \ + else \ + { \ + __asm volatile("MRC p0,#0,r6,c1,c0,#0"); \ + __asm volatile("MRC p0,#0,r7,c3,c0,#0"); \ + } \ + PQ_RUN_OPCODE_R4_R5(BATCH_OPCODE, BATCH_MACHINE); \ + __asm volatile("STRD r6,r7,[r1],#8"); /* store third two results */ \ + if (!last) \ + __asm volatile("LDRD r2,r3,[r0],#8"); /* load first two of next 8 */ \ + if (DOUBLE_READ_ADDERS) \ + { \ + __asm volatile("MRC p0,#0x1,r4,c1,c0,#0"); \ + __asm volatile("MRC p0,#0x1,r5,c3,c0,#0"); \ + } \ + else \ + { \ + __asm volatile("MRC p0,#0,r4,c1,c0,#0"); \ + __asm volatile("MRC p0,#0,r5,c3,c0,#0"); \ + } \ + if (last) \ + { \ + __asm volatile("STRD r4,r5,[r1],#8"); /* store fourth two results */ \ + } + +/*! + * @brief Start 32-bit data vector calculation. + * + * Start the vector calculation, the input data could be float, int32_t or Q31. + * + * @param PSRC Pointer to the source data. + * @param PDST Pointer to the destination data. + */ +#define PQ_Initiate_Vector_Func(pSrc, pDst) \ + __asm volatile( \ + "MOV r0, %[psrc] \n" \ + "MOV r1, %[pdst] \n" \ + "PUSH {r2-r7} \n" \ + "LDRD r2,r3,[r0],#8 \n" ::[psrc] "r"(pSrc), \ + [pdst] "r"(pDst) \ + : "r0", "r1") + +/*! + * @brief End vector calculation. + * + * This function should be called after vector calculation. + */ +#define PQ_End_Vector_Func() __asm volatile("POP {r2-r7}") + +/* + * Register assignment for the vector calculation assembly. + * r0: pSrc, r1: pDest, r2: length, r3: middle, r4-r9: Data, r10:dra + */ + +/*! + * @brief Start 32-bit data vector calculation. + * + * Start the vector calculation, the input data could be float, int32_t or Q31. + * + * @param PSRC Pointer to the source data. + * @param PDST Pointer to the destination data. + * @param LENGTH Number of the data, must be multiple of 8. + */ +#define PQ_StartVector(PSRC, PDST, LENGTH) \ + __asm volatile( \ + "MOV r0, %[psrc] \n" \ + "MOV r1, %[pdst] \n" \ + "MOV r2, %[length] \n" \ + "PUSH {r3-r10} \n" \ + "MOV r3, #0 \n" \ + "MOV r10, #0 \n" \ + "LDRD r4,r5,[r0],#8 \n" ::[psrc] "r"(PSRC), \ + [pdst] "r"(PDST), [length] "r"(LENGTH) \ + : "r0", "r1", "r2") + +/*! + * @brief Start 16-bit data vector calculation. + * + * Start the vector calculation, the input data could be int16_t. This function + * should be use with @ref PQ_Vector8Fixed16. + * + * @param PSRC Pointer to the source data. + * @param PDST Pointer to the destination data. + * @param LENGTH Number of the data, must be multiple of 8. + */ +#define PQ_StartVectorFixed16(PSRC, PDST, LENGTH) \ + __asm volatile( \ + "MOV r0, %[psrc] \n" \ + "MOV r1, %[pdst] \n" \ + "MOV r2, %[length] \n" \ + "PUSH {r3-r10} \n" \ + "MOV r3, #0 \n" \ + "LDRSH r4,[r0],#2 \n" \ + "LDRSH r5,[r0],#2 \n" ::[psrc] "r"(PSRC), \ + [pdst] "r"(PDST), [length] "r"(LENGTH) \ + : "r0", "r1", "r2") + +/*! + * @brief Start Q15-bit data vector calculation. + * + * Start the vector calculation, the input data could be Q15. This function + * should be use with @ref PQ_Vector8Q15. This function is dedicate for + * SinQ15/CosQ15 vector calculation. Because PowerQuad only supports Q31 Sin/Cos + * fixed function, so the input Q15 data is left shift 16 bits first, after + * Q31 calculation, the output data is right shift 16 bits. + * + * @param PSRC Pointer to the source data. + * @param PDST Pointer to the destination data. + * @param LENGTH Number of the data, must be multiple of 8. + */ +#define PQ_StartVectorQ15(PSRC, PDST, LENGTH) \ + __asm volatile( \ + "MOV r0, %[psrc] \n" \ + "MOV r1, %[pdst] \n" \ + "MOV r2, %[length] \n" \ + "PUSH {r3-r10} \n" \ + "MOV r3, #0 \n" \ + "LDR r5,[r0],#4 \n" \ + "LSL r4,r5,#16 \n" \ + "BFC r5,#0,#16 \n" ::[psrc] "r"(PSRC), \ + [pdst] "r"(PDST), [length] "r"(LENGTH) \ + : "r0", "r1", "r2") + +/*! + * @brief End vector calculation. + * + * This function should be called after vector calculation. + */ +#define PQ_EndVector() __asm volatile("POP {r3-r10} \n") + +/*! + * @brief Float data vector calculation. + * + * Float data vector calculation, the input data should be float. The parameter + * could be PQ_LN_INF, PQ_INV_INF, PQ_SQRT_INF, PQ_ISQRT_INF, PQ_ETOX_INF, PQ_ETONX_INF. + * For example, to calculate sqrt of a vector, use like this: + * @code + #define VECTOR_LEN 8 + float input[VECTOR_LEN] = {1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0}; + float output[VECTOR_LEN]; + + PQ_StartVector(input, output, VECTOR_LEN); + PQ_Vector8F32(PQ_SQRT_INF); + PQ_EndVector(); + @endcode + * + */ +#define PQ_Vector8F32(BATCH_OPCODE, DOUBLE_READ_ADDERS, BATCH_MACHINE) \ + __asm volatile( \ + "1: \n" \ + " MCR p0,%[opcode],r5,c2,c0,%[machine] \n" \ + " MCR p0,%[opcode],r4,c0,c0,%[machine] \n" \ + " CMP r3, #0 \n" \ + " ITE NE \n" \ + " STRDNE r6,r7,[r1],#8 \n" /* store fourth two results */ \ + " MOVEQ r3, #1 \n" /* middle = 1 */ \ + " LDMIA r0!,{r6-r9} \n" /* load next 4 datas */ \ + " MOV r10,%[dra] \n" \ + " CMP r10, #0 \n" \ + " ITE NE \n" \ + " MRRCNE p0,#0,r4,r5,c1 \n" \ + " MRRCEQ p0,#0,r4,r5,c0 \n" \ + " MCR p0,%[opcode],r7,c2,c0,%[machine] \n" \ + " MCR p0,%[opcode],r6,c0,c0,%[machine] \n" \ + " STRD r4,r5,[r1],#8 \n" /* store first two results */ \ + " MOV r10,%[dra] \n" \ + " CMP r10, #0 \n" \ + " ITE NE \n" \ + " MRRCNE p0,#0,r6,r7,c1 \n" \ + " MRRCEQ p0,#0,r6,r7,c0 \n" \ + " MCR p0,%[opcode],r9,c2,c0,%[machine] \n" \ + " MCR p0,%[opcode],r8,c0,c0,%[machine] \n" \ + " STRD r6,r7,[r1],#8 \n" /* store second two results */ \ + " LDRD r6,r7,[r0],#8 \n" /* load last 2 of the 8 */ \ + " CMP r10, #0 \n" \ + " ITE NE \n" \ + " MRRCNE p0,#0,r8,r9,c1 \n" \ + " MRRCEQ p0,#0,r8,r9,c0 \n" \ + " MCR p0,%[opcode],r7,c2,c0,%[machine] \n" \ + " MCR p0,%[opcode],r6,c0,c0,%[machine] \n" \ + " STRD r8,r9,[r1],#8 \n" /* store third two results */ \ + " SUBS r2, r2, #8 \n" /* length -= 8; if (length != 0) */ \ + " IT NE \n" \ + " LDRDNE r4,r5,[r0],#8 \n" /* load first two of next 8 */ \ + " CMP r10, #0 \n" \ + " ITE NE \n" \ + " MRRCNE p0,#0,r6,r7,c1 \n" \ + " MRRCEQ p0,#0,r6,r7,c0 \n" \ + " CMP r2, #0 \n" /* if (length == 0) */ \ + " BNE 1b \n" \ + " STRD r6,r7,[r1],#8 \n" /* store fourth two results */ \ + ::[opcode] "i"(BATCH_OPCODE), \ + [dra] "i"(DOUBLE_READ_ADDERS), [machine] "i"(BATCH_MACHINE)) + +/*! + * @brief Fixed 32bits data vector calculation. + * + * Float data vector calculation, the input data should be 32-bit integer. The parameter + * could be PQ_LN_INF, PQ_INV_INF, PQ_SQRT_INF, PQ_ISQRT_INF, PQ_ETOX_INF, PQ_ETONX_INF. + * PQ_SIN_INF, PQ_COS_INF. When this function is used for sin/cos calculation, the input + * data should be in the format Q1.31. + * For example, to calculate sqrt of a vector, use like this: + * @code + #define VECTOR_LEN 8 + int32_t input[VECTOR_LEN] = {1, 4, 9, 16, 25, 36, 49, 64}; + int32_t output[VECTOR_LEN]; + + PQ_StartVector(input, output, VECTOR_LEN); + PQ_Vector8F32(PQ_SQRT_INF); + PQ_EndVector(); + @endcode + * + */ +#define PQ_Vector8Fixed32(BATCH_OPCODE, DOUBLE_READ_ADDERS, BATCH_MACHINE) \ + __asm volatile( \ + "1: \n" \ + " MCR p0,%[opcode],r4,c1,c0,%[machine] \n" \ + " ISB \n" \ + " MCR p0,%[opcode],r5,c3,c0,%[machine] \n" \ + " CMP r3, #0 \n" \ + " ITE NE \n" \ + " STRDNE r6,r7,[r1],#8 \n" /* store fourth two results */ \ + " MOVEQ r3, #1 \n" /* middle = 1 */ \ + " LDMIA r0!,{r6-r9} \n" /* load next 4 datas */ \ + " MRC p0,%[dra],r4,c1,c0,#0 \n" \ + " MRC p0,%[dra],r5,c3,c0,#0 \n" \ + " MCR p0,%[opcode],r6,c1,c0,%[machine] \n" \ + " ISB \n" \ + " MCR p0,%[opcode],r7,c3,c0,%[machine] \n" \ + " STRD r4,r5,[r1],#8 \n" /* store first two results */ \ + " MRC p0,%[dra],r6,c1,c0,#0 \n" \ + " MRC p0,%[dra],r7,c3,c0,#0 \n" \ + " MCR p0,%[opcode],r8,c1,c0,%[machine] \n" \ + " ISB \n" \ + " MCR p0,%[opcode],r9,c3,c0,%[machine] \n" \ + " STRD r6,r7,[r1],#8 \n" /* store second two results */ \ + " LDRD r6,r7,[r0],#8 \n" /* load last 2 of the 8 */ \ + " MRC p0,%[dra],r8,c1,c0,#0 \n" \ + " MRC p0,%[dra],r9,c3,c0,#0 \n" \ + " MCR p0,%[opcode],r6,c1,c0,%[machine] \n" \ + " ISB \n" \ + " MCR p0,%[opcode],r7,c3,c0,%[machine] \n" \ + " STRD r8,r9,[r1],#8 \n" /* store third two results */ \ + " SUBS r2, r2, #8 \n" /* length -= 8; if (length != 0) */ \ + " IT NE \n" \ + " LDRDNE r4,r5,[r0],#8 \n" /* load first two of next 8 */ \ + " MRC p0,%[dra],r6,c1,c0,#0 \n" \ + " MRC p0,%[dra],r7,c3,c0,#0 \n" \ + " CMP r2, #0 \n" /* if (length == 0) */ \ + " BNE 1b \n" \ + " STRD r6,r7,[r1],#8 \n" /* store fourth two results */ \ + ::[opcode] "i"(BATCH_OPCODE), \ + [dra] "i"(DOUBLE_READ_ADDERS), [machine] "i"(BATCH_MACHINE)) + +/*! + * @brief Fixed 32bits data vector calculation. + * + * Float data vector calculation, the input data should be 16-bit integer. The parameter + * could be PQ_LN_INF, PQ_INV_INF, PQ_SQRT_INF, PQ_ISQRT_INF, PQ_ETOX_INF, PQ_ETONX_INF. + * For example, to calculate sqrt of a vector, use like this: + * @code + #define VECTOR_LEN 8 + int16_t input[VECTOR_LEN] = {1, 4, 9, 16, 25, 36, 49, 64}; + int16_t output[VECTOR_LEN]; + + PQ_StartVector(input, output, VECTOR_LEN); + PQ_Vector8F32(PQ_SQRT_INF); + PQ_EndVector(); + @endcode + * + */ +#define PQ_Vector8Fixed16(BATCH_OPCODE, DOUBLE_READ_ADDERS, BATCH_MACHINE) \ + __asm volatile( \ + "1: \n" \ + " MCR p0,%[opcode],r4,c1,c0,%[machine] \n" \ + " MCR p0,%[opcode],r5,c3,c0,%[machine] \n" \ + " CMP r3, #0 \n" \ + " ITTE NE \n" \ + " STRHNE r6,[r1],#2 \n" /* store fourth two results */ \ + " STRHNE r7,[r1],#2 \n" /* store fourth two results */ \ + " MOVEQ r3, #1 \n" /* middle = 1 */ \ + " LDRSH r6,[r0],#2 \n" /* load next 2 of the 8 */ \ + " LDRSH r7,[r0],#2 \n" /* load next 2 of the 8 */ \ + " MRC p0,%[dra],r4,c1,c0,#0 \n" \ + " MRC p0,%[dra],r5,c3,c0,#0 \n" \ + " MCR p0,%[opcode],r6,c1,c0,%[machine] \n" \ + " MCR p0,%[opcode],r7,c3,c0,%[machine] \n" \ + " STRH r4,[r1],#2 \n" /* store first two results */ \ + " STRH r5,[r1],#2 \n" /* store first two results */ \ + " LDRSH r8,[r0],#2 \n" /* load next 2 of the 8 */ \ + " LDRSH r9,[r0],#2 \n" /* load next 2 of the 8 */ \ + " MRC p0,%[dra],r6,c1,c0,#0 \n" \ + " MRC p0,%[dra],r7,c3,c0,#0 \n" \ + " MCR p0,%[opcode],r8,c1,c0,%[machine] \n" \ + " MCR p0,%[opcode],r9,c3,c0,%[machine] \n" \ + " STRH r6,[r1],#2 \n" /* store second two results */ \ + " STRH r7,[r1],#2 \n" /* store second two results */ \ + " LDRSH r6,[r0],#2 \n" /* load last 2 of the 8 */ \ + " LDRSH r7,[r0],#2 \n" /* load last 2 of the 8 */ \ + " MRC p0,%[dra],r8,c1,c0,#0 \n" \ + " MRC p0,%[dra],r9,c3,c0,#0 \n" \ + " MCR p0,%[opcode],r6,c1,c0,%[machine] \n" \ + " MCR p0,%[opcode],r7,c3,c0,%[machine] \n" \ + " STRH r8,[r1],#2 \n" /* store third two results */ \ + " STRH r9,[r1],#2 \n" /* store third two results */ \ + " SUBS r2, r2, #8 \n" /* length -= 8; if (length != 0) */ \ + " ITT NE \n" \ + " LDRSHNE r4,[r0],#2 \n" /* load first two of next 8 */ \ + " LDRSHNE r5,[r0],#2 \n" /* load first two of next 8 */ \ + " MRC p0,%[dra],r6,c1,c0,#0 \n" \ + " MRC p0,%[dra],r7,c3,c0,#0 \n" \ + " CMP r2, #0 \n" /* if (length == 0) */ \ + " BNE 1b \n" \ + " STRH r6,[r1],#2 \n" /* store fourth two results */ \ + " STRH r7,[r1],#2 \n" /* store fourth two results */ \ + ::[opcode] "i"(BATCH_OPCODE), \ + [dra] "i"(DOUBLE_READ_ADDERS), [machine] "i"(BATCH_MACHINE)) + +/*! + * @brief Q15 data vector calculation. + * + * Q15 data vector calculation, this function should only be used for sin/cos Q15 calculation, + * and the coprocessor output prescaler must be set to 31 before this function. This function + * loads Q15 data and left shift 16 bits, calculate and right shift 16 bits, then stores to + * the output array. The input range -1 to 1 means -pi to pi. + * For example, to calculate sin of a vector, use like this: + * @code + #define VECTOR_LEN 8 + int16_t input[VECTOR_LEN] = {...} + int16_t output[VECTOR_LEN]; + const pq_prescale_t prescale = + { + .inputPrescale = 0, + .outputPrescale = 31, + .outputSaturate = 0 + }; + + PQ_SetCoprocessorScaler(POWERQUAD, const pq_prescale_t *prescale); + + PQ_StartVectorQ15(pSrc, pDst, length); + PQ_Vector8Q15(PQ_SQRT_INF); + PQ_EndVector(); + @endcode + * + */ +#define PQ_Vector8Q15(BATCH_OPCODE, DOUBLE_READ_ADDERS, BATCH_MACHINE) \ + __asm volatile( \ + "1: \n" \ + " MCR p0,%[opcode],r4,c1,c0,%[machine] \n" \ + " ISB \n" \ + " MCR p0,%[opcode],r5,c3,c0,%[machine] \n" \ + " CMP r3, #0 \n" \ + " ITTTE NE \n" \ + " LSRNE r6,r6,#16 \n" /* store fourth two results */ \ + " BFINE r7,r6,#0,#16 \n" /* store fourth two results */ \ + " STRNE r7,[r1],#4 \n" /* store fourth two results */ \ + " MOVEQ r3, #1 \n" /* middle = 1 */ \ + " LDR r7,[r0],#4 \n" /* load next 2 of the 8 */ \ + " LSL r6,r7,#16 \n" /* load next 2 of the 8 */ \ + " BFC r7,#0,#16 \n" /* load next 2 of the 8 */ \ + " MRC p0,%[dra],r4,c1,c0,#0 \n" \ + " MRC p0,%[dra],r5,c3,c0,#0 \n" \ + " MCR p0,%[opcode],r6,c1,c0,%[machine] \n" \ + " ISB \n" \ + " MCR p0,%[opcode],r7,c3,c0,%[machine] \n" \ + " LSR r4,r4,#16 \n" /* store first two results */ \ + " BFI r5,r4,#0,#16 \n" /* store first two results */ \ + " STR r5,[r1],#4 \n" /* store first two results */ \ + " LDR r9,[r0],#4 \n" /* load next 2 of the 8 */ \ + " LSL r8,r9,#16 \n" /* load next 2 of the 8 */ \ + " BFC r9,#0,#16 \n" /* load next 2 of the 8 */ \ + " MRC p0,%[dra],r6,c1,c0,#0 \n" \ + " MRC p0,%[dra],r7,c3,c0,#0 \n" \ + " MCR p0,%[opcode],r8,c1,c0,%[machine] \n" \ + " ISB \n" \ + " MCR p0,%[opcode],r9,c3,c0,%[machine] \n" \ + " LSR r6,r6,#16 \n" /* store second two results */ \ + " BFI r7,r6,#0,#16 \n" /* store second two results */ \ + " STR r7,[r1],#4 \n" /* store second two results */ \ + " LDR r7,[r0],#4 \n" /* load next 2 of the 8 */ \ + " LSL r6,r7,#16 \n" /* load next 2 of the 8 */ \ + " BFC r7,#0,#16 \n" /* load next 2 of the 8 */ \ + " MRC p0,%[dra],r8,c1,c0,#0 \n" \ + " MRC p0,%[dra],r9,c3,c0,#0 \n" \ + " MCR p0,%[opcode],r6,c1,c0,%[machine] \n" \ + " ISB \n" \ + " MCR p0,%[opcode],r7,c3,c0,%[machine] \n" \ + " LSR r8,r8,#16 \n" /* store third two results */ \ + " BFI r9,r8,#0,#16 \n" /* store third two results */ \ + " STR r9,[r1],#4 \n" /* store third two results */ \ + " SUBS r2, r2, #8 \n" /* length -= 8; if (length != 0) */ \ + " ITTT NE \n" \ + " LDRNE r5,[r0],#4 \n" /* load next 2 of the 8 */ \ + " LSLNE r4,r5,#16 \n" /* load next 2 of the 8 */ \ + " BFCNE r5,#0,#16 \n" /* load next 2 of the 8 */ \ + " MRC p0,%[dra],r6,c1,c0,#0 \n" \ + " MRC p0,%[dra],r7,c3,c0,#0 \n" \ + " CMP r2, #0 \n" /* if (length == 0) */ \ + " BNE 1b \n" \ + " LSR r6,r6,#16 \n" /* store fourth two results */ \ + " BFI r7,r6,#0,#16 \n" /* store fourth two results */ \ + " STR r7,[r1],#4 \n" /* store fourth two results */ \ + ::[opcode] "i"(BATCH_OPCODE), \ + [dra] "i"(DOUBLE_READ_ADDERS), [machine] "i"(BATCH_MACHINE)) + +/*! + * @brief Float data vector biquad direct form II calculation. + * + * Biquad filter, the input and output data are float data. Biquad side 0 is used. Example: + * @code + #define VECTOR_LEN 16 + float input[VECTOR_LEN] = {1024.0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; + float output[VECTOR_LEN]; + pq_biquad_state_t state = + { + .param = + { + .a_1 = xxx, + .a_2 = xxx, + .b_0 = xxx, + .b_1 = xxx, + .b_2 = xxx, + }, + }; + + PQ_BiquadRestoreInternalState(POWERQUAD, 0, &state); + + PQ_Initiate_Vector_Func(pSrc,pDst); + PQ_DF2_Vector8_FP(false,false); + PQ_DF2_Vector8_FP(true,true); + PQ_End_Vector_Func(); + @endcode + * + */ +#define PQ_DF2_Vector8_FP(middle, last) \ + __asm volatile("MCR p0,#0x1,r2,c0,c0,#6"); /* write biquad0*/ \ + if (middle) \ + { \ + __asm volatile("STR r5,[r1],#4"); /* store last result*/ \ + } \ + __asm volatile("LDRD r4,r5,[r0],#8"); /* load next 2 datas */ \ + __asm volatile("MRC p0,#0x1,r2,c0,c0,#0"); /* read biquad0*/ \ + __asm volatile("MCR p0,#0x1,r3,c0,c0,#6"); /* write biquad0 */ \ + __asm volatile("MRC p0,#0x1,r3,c0,c0,#0"); /* read biquad0*/ \ + __asm volatile("MCR p0,#0x1,r4,c0,c0,#6"); /* write biquad0 */ \ + __asm volatile("STRD r2,r3,[r1],#8"); /* store first 2 results */ \ + __asm volatile("MRC p0,#0x1,r4,c0,c0,#0"); \ + __asm volatile("MCR p0,#0x1,r5,c0,c0,#6"); \ + __asm volatile("LDRD r6,r7,[r0],#8"); /* load next 2 datas */ \ + __asm volatile("MRC p0,#0x1,r5,c0,c0,#0"); \ + __asm volatile("MCR p0,#0x1,r6,c0,c0,#6"); \ + __asm volatile("STRD r4,r5,[r1],#8"); /* store next 2 results */ \ + __asm volatile("MRC p0,#0x1,r6,c0,c0,#0"); \ + __asm volatile("MCR p0,#0x1,r7,c0,c0,#6"); \ + __asm volatile("LDRD r4,r5,[r0],#8"); /* load next 2 datas */ \ + __asm volatile("MRC p0,#0x1,r7,c0,c0,#0"); \ + __asm volatile("MCR p0,#0x1,r4,c0,c0,#6"); \ + __asm volatile("STRD r6,r7,[r1],#8"); /* store next 2 results */ \ + __asm volatile("MRC p0,#0x1,r4,c0,c0,#0"); \ + __asm volatile("MCR p0,#0x1,r5,c0,c0,#6"); \ + if (!last) \ + { \ + __asm volatile("LDRD r2,r3,[r0],#8"); /* load first two of next 8 */ \ + } \ + __asm volatile("STR r4,[r1],#4"); \ + __asm volatile("MRC p0,#0x1,r5,c0,c0,#0"); \ + if (last) \ + { \ + __asm volatile("STR r5,[r1],#4"); /* store last result */ \ + } + +/*! + * @brief Fixed data vector biquad direct form II calculation. + * + * Biquad filter, the input and output data are fixed data. Biquad side 0 is used. Example: + * @code + #define VECTOR_LEN 16 + int32_t input[VECTOR_LEN] = {1024, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; + int32_t output[VECTOR_LEN]; + pq_biquad_state_t state = + { + .param = + { + .a_1 = xxx, + .a_2 = xxx, + .b_0 = xxx, + .b_1 = xxx, + .b_2 = xxx, + }, + }; + + PQ_BiquadRestoreInternalState(POWERQUAD, 0, &state); + + PQ_Initiate_Vector_Func(pSrc,pDst); + PQ_DF2_Vector8_FX(false,false); + PQ_DF2_Vector8_FX(true,true); + PQ_End_Vector_Func(); + @endcode + * + */ +#define PQ_DF2_Vector8_FX(middle, last) \ + __asm volatile("MCR p0,#0x1,r2,c1,c0,#6"); /* write biquad0*/ \ + if (middle) \ + { \ + __asm volatile("STR r5,[r1],#4"); /* store last result*/ \ + } \ + __asm volatile("LDRD r4,r5,[r0],#8"); /* load next 2 datas */ \ + __asm volatile("MRC p0,#0x1,r2,c1,c0,#0"); /* read biquad0*/ \ + __asm volatile("MCR p0,#0x1,r3,c1,c0,#6"); /* write biquad0 */ \ + __asm volatile("MRC p0,#0x1,r3,c1,c0,#0"); \ + __asm volatile("MCR p0,#0x1,r4,c1,c0,#6"); \ + __asm volatile("STRD r2,r3,[r1],#8"); /* store first 2 results */ \ + __asm volatile("MRC p0,#0x1,r4,c1,c0,#0"); \ + __asm volatile("MCR p0,#0x1,r5,c1,c0,#6"); \ + __asm volatile("LDRD r6,r7,[r0],#8"); \ + __asm volatile("MRC p0,#0x1,r5,c1,c0,#0"); \ + __asm volatile("MCR p0,#0x1,r6,c1,c0,#6"); \ + __asm volatile("STRD r4,r5,[r1],#8"); /* store next 2 results */ \ + __asm volatile("MRC p0,#0x1,r6,c1,c0,#0"); \ + __asm volatile("MCR p0,#0x1,r7,c1,c0,#6"); \ + __asm volatile("LDRD r4,r5,[r0],#8"); \ + __asm volatile("MRC p0,#0x1,r7,c1,c0,#0"); \ + __asm volatile("MCR p0,#0x1,r4,c1,c0,#6"); \ + __asm volatile("STRD r6,r7,[r1],#8"); /* store next 2 results */ \ + __asm volatile("MRC p0,#0x1,r4,c1,c0,#0"); \ + __asm volatile("MCR p0,#0x1,r5,c1,c0,#6"); \ + if (!last) \ + { \ + __asm volatile("LDRD r2,r3,[r0],#8"); /* load two of next 8 */ \ + } \ + __asm volatile("STR r4,[r1],#4"); /* store 7th results */ \ + __asm volatile("MRC p0,#0x1,r5,c1,c0,#0"); \ + if (last) \ + { \ + __asm volatile("STR r5,[r1],#4"); /* store last result */ \ + } + +/*! + * @brief Float data vector biquad direct form II calculation. + * + * Biquad filter, the input and output data are float data. Biquad side 0 is used. Example: + * @code + #define VECTOR_LEN 8 + float input[VECTOR_LEN] = {1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0}; + float output[VECTOR_LEN]; + pq_biquad_state_t state = + { + .param = + { + .a_1 = xxx, + .a_2 = xxx, + .b_0 = xxx, + .b_1 = xxx, + .b_2 = xxx, + }, + }; + + PQ_BiquadRestoreInternalState(POWERQUAD, 0, &state); + + PQ_StartVector(input, output, VECTOR_LEN); + PQ_Vector8BiquadDf2F32(); + PQ_EndVector(); + @endcode + * + */ +#define PQ_Vector8BiquadDf2F32() \ + __asm volatile( \ + "1: \n" \ + " MCR p0,#0x1,r4,c0,c0,#6 \n" /* write biquad0*/ \ + " CMP r3, #0 \n" \ + " ITE NE \n" \ + " STRNE r7,[r1],#4 \n" /* store last result*/ \ + " MOVEQ r3, #1 \n" /* middle = 1 */ \ + " LDMIA r0!,{r6-r9} \n" /* load next 4 datas */ \ + " MRC p0,#0x1,r4,c0,c0,#0 \n" /* read biquad0*/ \ + " MCR p0,#0x1,r5,c0,c0,#6 \n" /* write biquad0 */ \ + " MRC p0,#0x1,r5,c0,c0,#0 \n" /* read biquad0*/ \ + " MCR p0,#0x1,r6,c0,c0,#6 \n" /* write biquad0 */ \ + " MRC p0,#0x1,r6,c0,c0,#0 \n" /* read biquad0 */ \ + " MCR p0,#0x1,r7,c0,c0,#6 \n" /* write biquad0 */ \ + " MRC p0,#0x1,r7,c0,c0,#0 \n" /* read biquad0 */ \ + " MCR p0,#0x1,r8,c0,c0,#6 \n" /* write biquad0*/ \ + " STMIA r1!,{r4-r7} \n" /* store first four results */ \ + " MRC p0,#0x1,r8,c0,c0,#0 \n" /* read biquad0*/ \ + " MCR p0,#0x1,r9,c0,c0,#6 \n" /* write biquad0*/ \ + " LDRD r6,r7,[r0],#8 \n" /* load next 2 items*/ \ + " MRC p0,#0x1,r9,c0,c0,#0 \n" /* read biquad0*/ \ + " MCR p0,#0x1,r6,c0,c0,#6 \n" /* write biquad0*/ \ + " STRD r8,r9,[r1],#8 \n" /* store third two results */ \ + " MRC p0,#0x1,r6,c0,c0,#0 \n" /* read biquad0*/ \ + " MCR p0,#0x1,r7,c0,c0,#6 \n" /* write biquad0*/ \ + " SUBS r2, r2, #8 \n" /* length -= 8; if (length != 0) */ \ + " IT NE \n" \ + " LDRDNE r4,r5,[r0],#8 \n" /* load first two of next 8 */ \ + " STR r6,[r1],#4 \n" /* store 7th results */ \ + " MRC p0,#0x1,r7,c0,c0,#0 \n" /* read biquad0*/ \ + " CMP r2, #0 \n" /* if (length == 0) */ \ + " BNE 1b \n" \ + " STR r7,[r1],#4 \n" /* store last result */ \ + ) + +/*! + * @brief Fixed 32-bit data vector biquad direct form II calculation. + * + * Biquad filter, the input and output data are Q31 or 32-bit integer. Biquad side 0 is used. Example: + * @code + #define VECTOR_LEN 8 + int32_t input[VECTOR_LEN] = {1, 2, 3, 4, 5, 6, 7, 8}; + int32_t output[VECTOR_LEN]; + pq_biquad_state_t state = + { + .param = + { + .a_1 = xxx, + .a_2 = xxx, + .b_0 = xxx, + .b_1 = xxx, + .b_2 = xxx, + }, + }; + + PQ_BiquadRestoreInternalState(POWERQUAD, 0, &state); + + PQ_StartVector(input, output, VECTOR_LEN); + PQ_Vector8BiquadDf2Fixed32(); + PQ_EndVector(); + @endcode + * + */ +#define PQ_Vector8BiquadDf2Fixed32() \ + __asm volatile( \ + "1: \n" \ + " MCR p0,#0x1,r4,c1,c0,#6 \n" /* write biquad0*/ \ + " CMP r3, #0 \n" \ + " ITE NE \n" \ + " STRNE r7,[r1],#4 \n" /* store last result*/ \ + " MOVEQ r3, #1 \n" /* middle = 1 */ \ + " LDMIA r0!,{r6-r9} \n" /* load next 4 datas */ \ + " MRC p0,#0x1,r4,c1,c0,#0 \n" /* read biquad0*/ \ + " MCR p0,#0x1,r5,c1,c0,#6 \n" /* write biquad0 */ \ + " MRC p0,#0x1,r5,c1,c0,#0 \n" /* read biquad0*/ \ + " MCR p0,#0x1,r6,c1,c0,#6 \n" /* write biquad0 */ \ + " MRC p0,#0x1,r6,c1,c0,#0 \n" /* read biquad0 */ \ + " MCR p0,#0x1,r7,c1,c0,#6 \n" /* write biquad0 */ \ + " MRC p0,#0x1,r7,c1,c0,#0 \n" /* read biquad0 */ \ + " MCR p0,#0x1,r8,c1,c0,#6 \n" /* write biquad0*/ \ + " STMIA r1!,{r4-r7} \n" /* store first four results */ \ + " MRC p0,#0x1,r8,c1,c0,#0 \n" /* read biquad0*/ \ + " MCR p0,#0x1,r9,c1,c0,#6 \n" /* write biquad0*/ \ + " LDRD r6,r7,[r0],#8 \n" /* load next 2 items*/ \ + " MRC p0,#0x1,r9,c1,c0,#0 \n" /* read biquad0*/ \ + " MCR p0,#0x1,r6,c1,c0,#6 \n" /* write biquad0*/ \ + " STRD r8,r9,[r1],#8 \n" /* store third two results */ \ + " MRC p0,#0x1,r6,c1,c0,#0 \n" /* read biquad0*/ \ + " MCR p0,#0x1,r7,c1,c0,#6 \n" /* write biquad0*/ \ + " SUBS r2, r2, #8 \n" /* length -= 8; if (length != 0) */ \ + " IT NE \n" \ + " LDRDNE r4,r5,[r0],#8 \n" /* load first two of next 8 */ \ + " STR r6,[r1],#4 \n" /* store 7th results */ \ + " MRC p0,#0x1,r7,c1,c0,#0 \n" /* read biquad0*/ \ + " CMP r2, #0 \n" /* if (length == 0) */ \ + " BNE 1b \n" \ + " STR r7,[r1],#4 \n" /* store last result */ \ + ) + +/*! + * @brief Fixed 16-bit data vector biquad direct form II calculation. + * + * Biquad filter, the input and output data are Q15 or 16-bit integer. Biquad side 0 is used. Example: + * @code + #define VECTOR_LEN 8 + int16_t input[VECTOR_LEN] = {1, 2, 3, 4, 5, 6, 7, 8}; + int16_t output[VECTOR_LEN]; + pq_biquad_state_t state = + { + .param = + { + .a_1 = xxx, + .a_2 = xxx, + .b_0 = xxx, + .b_1 = xxx, + .b_2 = xxx, + }, + }; + + PQ_BiquadRestoreInternalState(POWERQUAD, 0, &state); + + PQ_StartVector(input, output, VECTOR_LEN); + PQ_Vector8BiquadDf2Fixed16(); + PQ_EndVector(); + @endcode + * + */ +#define PQ_Vector8BiquadDf2Fixed16() \ + __asm volatile( \ + "1: \n" \ + " MCR p0,#0x1,r4,c1,c0,#6 \n" /* write biquad0*/ \ + " CMP r3, #0 \n" \ + " ITE NE \n" \ + " STRHNE r7,[r1],#2 \n" /* store last result*/ \ + " MOVEQ r3, #1 \n" /* middle = 1 */ \ + " LDRSH r6,[r0],#2 \n" /* load next 2 of the 8*/ \ + " LDRSH r7,[r0],#2 \n" /* load next 2 of the 8*/ \ + " MRC p0,#0x1,r4,c1,c0,#0 \n" /* read biquad0*/ \ + " MCR p0,#0x1,r5,c1,c0,#6 \n" /* write biquad0 */ \ + " MRC p0,#0x1,r5,c1,c0,#0 \n" /* read biquad0*/ \ + " LDRSH r8,[r0],#2 \n" /* load next 2 of the 8*/ \ + " LDRSH r9,[r0],#2 \n" /* load next 2 of the 8*/ \ + " MCR p0,#0x1,r6,c1,c0,#6 \n" /* write biquad0 */ \ + " MRC p0,#0x1,r6,c1,c0,#0 \n" /* read biquad0 */ \ + " MCR p0,#0x1,r7,c1,c0,#6 \n" /* write biquad0 */ \ + " MRC p0,#0x1,r7,c1,c0,#0 \n" /* read biquad0 */ \ + " STRH r4,[r1],#2 \n" /* store first 4 results */ \ + " STRH r5,[r1],#2 \n" /* store first 4 results */ \ + " MCR p0,#0x1,r8,c1,c0,#6 \n" /* write biquad0*/ \ + " STRH r6,[r1],#2 \n" /* store first 4 results */ \ + " STRH r7,[r1],#2 \n" /* store first 4 results */ \ + " MRC p0,#0x1,r8,c1,c0,#0 \n" /* read biquad0*/ \ + " MCR p0,#0x1,r9,c1,c0,#6 \n" /* write biquad0*/ \ + " LDRSH r6,[r0],#2 \n" /* load next 1 of the 8*/ \ + " LDRSH r7,[r0],#2 \n" /* load next 1 of the 8*/ \ + " MRC p0,#0x1,r9,c1,c0,#0 \n" /* read biquad0*/ \ + " MCR p0,#0x1,r6,c1,c0,#6 \n" /* write biquad0*/ \ + " STRH r8,[r1],#2 \n" /* store next two results */ \ + " STRH r9,[r1],#2 \n" /* store next two results */ \ + " MRC p0,#0x1,r6,c1,c0,#0 \n" /* read biquad0*/ \ + " MCR p0,#0x1,r7,c1,c0,#6 \n" /* write biquad0*/ \ + " SUBS r2, r2, #8 \n" /* length -= 8; if (length != 0) */ \ + " ITT NE \n" \ + " LDRSHNE r4,[r0],#2 \n" /* load first two of next 8*/ \ + " LDRSHNE r5,[r0],#2 \n" /* load first two of next 8*/ \ + " STRH r6,[r1],#2 \n" /* store 7th results */ \ + " MRC p0,#0x1,r7,c1,c0,#0 \n" /* read biquad0*/ \ + " CMP r2, #0 \n" /* if (length == 0) */ \ + " BNE 1b \n" \ + " STRH r7,[r1],#2 \n" /* store last result */ \ + ) + +/*! + * @brief Float data vector direct form II biquad cascade filter. + * + * The input and output data are float data. The data flow is + * input -> biquad side 1 -> biquad side 0 -> output. + * + * @code + #define VECTOR_LEN 16 + float input[VECTOR_LEN] = {1024.0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; + float output[VECTOR_LEN]; + pq_biquad_state_t state0 = + { + .param = + { + .a_1 = xxx, + .a_2 = xxx, + .b_0 = xxx, + .b_1 = xxx, + .b_2 = xxx, + }, + }; + + pq_biquad_state_t state1 = + { + .param = + { + .a_1 = xxx, + .a_2 = xxx, + .b_0 = xxx, + .b_1 = xxx, + .b_2 = xxx, + }, + }; + + PQ_BiquadRestoreInternalState(POWERQUAD, 0, &state0); + PQ_BiquadRestoreInternalState(POWERQUAD, 1, &state1); + + PQ_Initiate_Vector_Func(pSrc, pDst); + PQ_DF2_Cascade_Vector8_FP(false, false); + PQ_DF2_Cascade_Vector8_FP(true, true); + PQ_End_Vector_Func(); + @endcode + * + */ +#define PQ_DF2_Cascade_Vector8_FP(middle, last) \ + __asm volatile("MCR p0,#0x1,r2,c2,c0,#6"); /* write biquad1*/ \ + if (middle) \ + { \ + __asm volatile("MCR p0,#0x1,r5,c0,c0,#6"); /* write biquad0*/ \ + __asm volatile("MRRC p0,#0,r5,r2,c1"); /* read both biquad*/ \ + } \ + else \ + { \ + __asm volatile("MRC p0,#0x1,r2,c2,c0,#0"); /* read biquad1*/ \ + } \ + __asm volatile("MCR p0,#0x1,r3,c2,c0,#6"); /* write biquad1*/ \ + __asm volatile("MCR p0,#0x1,r2,c0,c0,#6"); /* write biquad0*/ \ + if (middle) \ + { \ + __asm volatile("STRD r4,r5,[r1],#8"); /* store last two results*/ \ + } \ + __asm volatile("LDRD r4,r5,[r0],#8"); /* load next 2 datas */ \ + __asm volatile("MRRC p0,#0,r2,r3,c1"); /* read both biquad*/ \ + __asm volatile("MCR p0,#0x1,r4,c2,c0,#6"); /* write biquad1*/ \ + __asm volatile("MCR p0,#0x1,r3,c0,c0,#6"); /* write biquad0*/ \ + __asm volatile("LDRD r6,r7,[r0],#8"); \ + __asm volatile("MRRC p0,#0,r3,r4,c1"); \ + __asm volatile("MCR p0,#0x1,r5,c2,c0,#6"); \ + __asm volatile("MCR p0,#0x1,r4,c0,c0,#6"); \ + __asm volatile("STRD r2,r3,[r1],#8"); /* store first two results */ \ + __asm volatile("MRRC p0,#0,r4,r5,c1"); \ + __asm volatile("MCR p0,#0x1,r6,c2,c0,#6"); \ + __asm volatile("MCR p0,#0x1,r5,c0,c0,#6"); \ + __asm volatile("STR r4,[r1],#4"); \ + __asm volatile("MRRC p0,#0,r5,r6,c1"); \ + __asm volatile("MCR p0,#0x1,r7,c2,c0,#6"); \ + __asm volatile("MCR p0,#0x1,r6,c0,c0,#6"); \ + __asm volatile("STR r5,[r1],#4"); \ + __asm volatile("LDRD r4,r5,[r0],#8"); \ + __asm volatile("MRRC p0,#0,r6,r7,c1"); \ + __asm volatile("MCR p0,#0x1,r4,c2,c0,#6"); \ + __asm volatile("MCR p0,#0x1,r7,c0,c0,#6"); \ + if (!last) \ + { \ + __asm volatile("LDRD r2,r3,[r0],#8"); /* load first two of next 8 */ \ + } \ + __asm volatile("MRRC p0,#0,r7,r4,c1"); \ + __asm volatile("MCR p0,#0x1,r5,c2,c0,#6"); \ + __asm volatile("MCR p0,#0x1,r4,c0,c0,#6"); \ + __asm volatile("STRD r6,r7,[r1],#8"); /* store third two results */ \ + __asm volatile("MRRC p0,#0,r4,r5,c1"); \ + if (last) \ + { \ + __asm volatile("MCR p0,#0x1,r5,c0,c0,#6"); /* write biquad0*/ \ + __asm volatile("MRC p0,#0x1,r5,c0,c0,#0"); /* read biquad0*/ \ + __asm volatile("STRD r4,r5,[r1],#8"); /* store fourth two results */ \ + } + +/*! + * @brief Fixed data vector direct form II biquad cascade filter. + * + * The input and output data are fixed data. The data flow is + * input -> biquad side 1 -> biquad side 0 -> output. + * + * @code + #define VECTOR_LEN 16 + int32_t input[VECTOR_LEN] = {1024.0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; + int32_t output[VECTOR_LEN]; + pq_biquad_state_t state0 = + { + .param = + { + .a_1 = xxx, + .a_2 = xxx, + .b_0 = xxx, + .b_1 = xxx, + .b_2 = xxx, + }, + }; + + pq_biquad_state_t state1 = + { + .param = + { + .a_1 = xxx, + .a_2 = xxx, + .b_0 = xxx, + .b_1 = xxx, + .b_2 = xxx, + }, + }; + + PQ_BiquadRestoreInternalState(POWERQUAD, 0, &state0); + PQ_BiquadRestoreInternalState(POWERQUAD, 1, &state1); + + PQ_Initiate_Vector_Func(pSrc, pDst); + PQ_DF2_Cascade_Vector8_FX(false, false); + PQ_DF2_Cascade_Vector8_FX(true, true); + PQ_End_Vector_Func(); + @endcode + * + */ +#define PQ_DF2_Cascade_Vector8_FX(middle, last) \ + __asm volatile("MCR p0,#0x1,r2,c3,c0,#6"); /* write biquad1*/ \ + if (middle) \ + { \ + __asm volatile("MCR p0,#0x1,r5,c1,c0,#6"); /* write biquad0*/ \ + __asm volatile("MRC p0,#0x1,r5,c1,c0,#0"); /* read biquad0*/ \ + __asm volatile("MRC p0,#0x1,r2,c3,c0,#0"); /* read biquad1*/ \ + } \ + else \ + { \ + __asm volatile("MRC p0,#0x1,r2,c3,c0,#0"); /* read biquad1*/ \ + } \ + __asm volatile("MCR p0,#0x1,r3,c3,c0,#6"); /* write biquad1*/ \ + __asm volatile("MCR p0,#0x1,r2,c1,c0,#6"); /* write biquad0*/ \ + if (middle) \ + { \ + __asm volatile("STRD r4,r5,[r1],#8"); /* store last two results*/ \ + } \ + __asm volatile("LDRD r4,r5,[r0],#8"); /* load next 2 datas */ \ + __asm volatile("MRC p0,#0x1,r2,c1,c0,#0"); /* read biquad0*/ \ + __asm volatile("MRC p0,#0x1,r3,c3,c0,#0"); /* read biquad1*/ \ + __asm volatile("MCR p0,#0x1,r4,c3,c0,#6"); /* write biquad1*/ \ + __asm volatile("MCR p0,#0x1,r3,c1,c0,#6"); /* write biquad0*/ \ + __asm volatile("LDRD r6,r7,[r0],#8"); \ + __asm volatile("MRC p0,#0x1,r3,c1,c0,#0"); \ + __asm volatile("MRC p0,#0x1,r4,c3,c0,#0"); \ + __asm volatile("MCR p0,#0x1,r5,c3,c0,#6"); \ + __asm volatile("MCR p0,#0x1,r4,c1,c0,#6"); \ + __asm volatile("STRD r2,r3,[r1],#8"); \ + __asm volatile("MRC p0,#0x1,r4,c1,c0,#0"); \ + __asm volatile("MRC p0,#0x1,r5,c3,c0,#0"); \ + __asm volatile("MCR p0,#0x1,r6,c3,c0,#6"); \ + __asm volatile("MCR p0,#0x1,r5,c1,c0,#6"); \ + __asm volatile("STR r4,[r1],#4"); \ + __asm volatile("MRC p0,#0x1,r5,c1,c0,#0"); \ + __asm volatile("MRC p0,#0x1,r6,c3,c0,#0"); \ + __asm volatile("MCR p0,#0x1,r7,c3,c0,#6"); \ + __asm volatile("MCR p0,#0x1,r6,c1,c0,#6"); \ + __asm volatile("STR r5,[r1],#4"); \ + __asm volatile("LDRD r4,r5,[r0],#8"); \ + __asm volatile("MRC p0,#0x1,r6,c1,c0,#0"); \ + __asm volatile("MRC p0,#0x1,r7,c3,c0,#0"); \ + __asm volatile("MCR p0,#0x1,r4,c3,c0,#6"); \ + __asm volatile("MCR p0,#0x1,r7,c1,c0,#6"); \ + if (!last) \ + { \ + __asm volatile("LDRD r2,r3,[r0],#8"); /* load first two of next 8 */ \ + } \ + __asm volatile("MRC p0,#0x1,r7,c1,c0,#0"); \ + __asm volatile("MRC p0,#0x1,r4,c3,c0,#0"); \ + __asm volatile("MCR p0,#0x1,r5,c3,c0,#6"); \ + __asm volatile("MCR p0,#0x1,r4,c1,c0,#6"); \ + __asm volatile("STRD r6,r7,[r1],#8"); /* store third two results */ \ + __asm volatile("MRC p0,#0x1,r4,c1,c0,#0"); /* read biquad0*/ \ + __asm volatile("MRC p0,#0x1,r5,c3,c0,#0"); /* read biquad1*/ \ + if (last) \ + { \ + __asm volatile("MCR p0,#0x1,r5,c1,c0,#6"); /* write biquad0*/ \ + __asm volatile("MRC p0,#0x1,r5,c1,c0,#0"); /* read biquad0*/ \ + __asm volatile("STRD r4,r5,[r1],#8"); /* store fourth two results */ \ + } + +/*! + * @brief Float data vector direct form II biquad cascade filter. + * + * The input and output data are float data. The data flow is + * input -> biquad side 1 -> biquad side 0 -> output. + * + * @code + #define VECTOR_LEN 8 + float input[VECTOR_LEN] = {1, 2, 3, 4, 5, 6, 7, 8}; + float output[VECTOR_LEN]; + pq_biquad_state_t state0 = + { + .param = + { + .a_1 = xxx, + .a_2 = xxx, + .b_0 = xxx, + .b_1 = xxx, + .b_2 = xxx, + }, + }; + + pq_biquad_state_t state1 = + { + .param = + { + .a_1 = xxx, + .a_2 = xxx, + .b_0 = xxx, + .b_1 = xxx, + .b_2 = xxx, + }, + }; + + PQ_BiquadRestoreInternalState(POWERQUAD, 0, &state0); + PQ_BiquadRestoreInternalState(POWERQUAD, 1, &state1); + + PQ_StartVector(input, output, VECTOR_LEN); + PQ_Vector8BiqaudDf2CascadeF32(); + PQ_EndVector(); + @endcode + * + */ +#define PQ_Vector8BiqaudDf2CascadeF32() \ + __asm volatile( \ + "1: \n" \ + " MCR p0,#0x1,r4,c2,c0,#2 \n" /* write biquad1*/ \ + " CMP r3, #0 \n" \ + " ITTE NE \n" \ + " MCRNE p0,#0x1,r7,c0,c0,#2 \n" /* write biquad0*/ \ + " MRRCNE p0,#0,r7,r4,c1 \n" /* read both biquad*/ \ + " MRCEQ p0,#0x1,r4,c2,c0,#0 \n" /* read biquad1*/ \ + " MCR p0,#0x1,r5,c2,c0,#2 \n" /* write biquad1*/ \ + " MCR p0,#0x1,r4,c0,c0,#2 \n" /* write biquad0*/ \ + " CMP r3, #0 \n" \ + " ITE NE \n" \ + " STRDNE r6,r7,[r1],#8 \n" /* store last two results*/ \ + " MOVEQ r3, #1 \n" /* middle = 1 */ \ + " LDMIA r0!,{r6-r9} \n" /* load next 4 datas */ \ + " MRRC p0,#0,r4,r5,c1 \n" /* read both biquad*/ \ + " MCR p0,#0x1,r6,c2,c0,#2 \n" /* write biquad1*/ \ + " MCR p0,#0x1,r5,c0,c0,#2 \n" /* write biquad0*/ \ + " MRRC p0,#0,r5,r6,c1 \n" /* read both biquad*/ \ + " MCR p0,#0x1,r7,c2,c0,#2 \n" /* write biquad1*/ \ + " MCR p0,#0x1,r6,c0,c0,#2 \n" /* write biquad0*/ \ + " MRRC p0,#0,r6,r7,c1 \n" /* read both biquad*/ \ + " MCR p0,#0x1,r8,c2,c0,#2 \n" /* write biquad1*/ \ + " MCR p0,#0x1,r7,c0,c0,#2 \n" /* write biquad0*/ \ + " MRRC p0,#0,r7,r8,c1 \n" /* read both biquad*/ \ + " MCR p0,#0x1,r9,c2,c0,#2 \n" /* write biquad1*/ \ + " MCR p0,#0x1,r8,c0,c0,#2 \n" /* write biquad0*/ \ + " STMIA r1!,{R4-R7} \n" /* store first and second two results */ \ + " LDRD r6,r7,[r0],#8 \n" /* load last 2 of the 8 */ \ + " MRRC p0,#0,r8,r9,c1 \n" /* read both biquad*/ \ + " MCR p0,#0x1,r6,c2,c0,#2 \n" /* write biquad1*/ \ + " MCR p0,#0x1,r9,c0,c0,#2 \n" /* write biquad0*/ \ + " SUBS r2, r2, #8 \n" /* length -= 8; if (length != 0) */ \ + " IT NE \n" \ + " LDRDNE r4,r5,[r0],#8 \n" /* load first two of next 8 */ \ + " MRRC p0,#0,r9,r6,c1 \n" /* read both biquad*/ \ + " MCR p0,#0x1,r7,c2,c0,#2 \n" /* write biquad1*/ \ + " MCR p0,#0x1,r6,c0,c0,#2 \n" /* write biquad0*/ \ + " STRD r8,r9,[r1],#8 \n" /* store third two results */ \ + " MRRC p0,#0,r6,r7,c1 \n" /* read both biquad*/ \ + " CMP r2, #0 \n" /* if (length == 0) */ \ + " BNE 1b \n" \ + " MCR p0,#0x1,r7,c0,c0,#2 \n" /* write biquad0*/ \ + " MRC p0,#0x1,r7,c0,c0,#0 \n" /* read biquad0*/ \ + " STRD r6,r7,[r1],#8 \n" /* store fourth two results */ \ + ) + +/*! + * @brief Fixed 32-bit data vector direct form II biquad cascade filter. + * + * The input and output data are fixed 32-bit data. The data flow is + * input -> biquad side 1 -> biquad side 0 -> output. + * + * @code + #define VECTOR_LEN 8 + int32_t input[VECTOR_LEN] = {1, 2, 3, 4, 5, 6, 7, 8}; + int32_t output[VECTOR_LEN]; + pq_biquad_state_t state0 = + { + .param = + { + .a_1 = xxx, + .a_2 = xxx, + .b_0 = xxx, + .b_1 = xxx, + .b_2 = xxx, + }, + }; + + pq_biquad_state_t state1 = + { + .param = + { + .a_1 = xxx, + .a_2 = xxx, + .b_0 = xxx, + .b_1 = xxx, + .b_2 = xxx, + }, + }; + + PQ_BiquadRestoreInternalState(POWERQUAD, 0, &state0); + PQ_BiquadRestoreInternalState(POWERQUAD, 1, &state1); + + PQ_StartVector(input, output, VECTOR_LEN); + PQ_Vector8BiqaudDf2CascadeFixed32(); + PQ_EndVector(); + @endcode + * + */ +#define PQ_Vector8BiqaudDf2CascadeFixed32() \ + __asm volatile( \ + "1: \n" \ + " MCR p0,#0x1,r4,c3,c0,#6 \n" /* write biquad1*/ \ + " CMP r3, #0 \n" \ + " ITTTE NE \n" \ + " MCRNE p0,#0x1,r7,c1,c0,#6 \n" /* write biquad0*/ \ + " MRCNE p0,#0x1,r7,c1,c0,#0 \n" /* read biquad0*/ \ + " MRCNE p0,#0x1,r4,c3,c0,#0 \n" /* read biquad1*/ \ + " MRCEQ p0,#0x1,r4,c3,c0,#0 \n" /* read biquad1*/ \ + " MCR p0,#0x1,r5,c3,c0,#6 \n" /* write biquad1*/ \ + " MCR p0,#0x1,r4,c1,c0,#6 \n" /* write biquad0*/ \ + " CMP r3, #0 \n" \ + " ITE NE \n" \ + " STRDNE r6,r7,[r1],#8 \n" /* store last two results*/ \ + " MOVEQ r3, #1 \n" /* middle = 1 */ \ + " LDMIA r0!,{r6-r9} \n" /* load next 4 datas */ \ + " MRC p0,#0x1,r4,c1,c0,#0 \n" /* read biquad0*/ \ + " MRC p0,#0x1,r5,c3,c0,#0 \n" /* read biquad1*/ \ + " MCR p0,#0x1,r6,c3,c0,#6 \n" /* write biquad1*/ \ + " MCR p0,#0x1,r5,c1,c0,#6 \n" /* write biquad0*/ \ + " MRC p0,#0x1,r5,c1,c0,#0 \n" /* read biquad0*/ \ + " MRC p0,#0x1,r6,c3,c0,#0 \n" /* read biquad1*/ \ + " MCR p0,#0x1,r7,c3,c0,#6 \n" /* write biquad1*/ \ + " MCR p0,#0x1,r6,c1,c0,#6 \n" /* write biquad0*/ \ + " MRC p0,#0x1,r6,c1,c0,#0 \n" /* read biquad0*/ \ + " MRC p0,#0x1,r7,c3,c0,#0 \n" /* read biquad1*/ \ + " MCR p0,#0x1,r8,c3,c0,#6 \n" /* write biquad1*/ \ + " MCR p0,#0x1,r7,c1,c0,#6 \n" /* write biquad0*/ \ + " MRC p0,#0x1,r7,c1,c0,#0 \n" /* read biquad0*/ \ + " MRC p0,#0x1,r8,c3,c0,#0 \n" /* read biquad1*/ \ + " MCR p0,#0x1,r9,c3,c0,#6 \n" /* write biquad1*/ \ + " MCR p0,#0x1,r8,c1,c0,#6 \n" /* write biquad0*/ \ + " STMIA r1!,{R4-R7} \n" /* store first and second two results */ \ + " LDRD r6,r7,[r0],#8 \n" /* load last 2 of the 8 */ \ + " MRC p0,#0x1,r8,c1,c0,#0 \n" /* read biquad0*/ \ + " MRC p0,#0x1,r9,c3,c0,#0 \n" /* read biquad1*/ \ + " MCR p0,#0x1,r6,c3,c0,#6 \n" /* write biquad1*/ \ + " MCR p0,#0x1,r9,c1,c0,#6 \n" /* write biquad0*/ \ + " SUBS r2, r2, #8 \n" /* length -= 8; if (length != 0) */ \ + " IT NE \n" \ + " LDRDNE r4,r5,[r0],#8 \n" /* load first two of next 8 */ \ + " MRC p0,#0x1,r9,c1,c0,#0 \n" /* read biquad0*/ \ + " MRC p0,#0x1,r6,c3,c0,#0 \n" /* read biquad1*/ \ + " MCR p0,#0x1,r7,c3,c0,#6 \n" /* write biquad1*/ \ + " MCR p0,#0x1,r6,c1,c0,#6 \n" /* write biquad0*/ \ + " STRD r8,r9,[r1],#8 \n" /* store third two results */ \ + " MRC p0,#0x1,r6,c1,c0,#0 \n" /* read biquad0*/ \ + " MRC p0,#0x1,r7,c3,c0,#0 \n" /* read biquad1*/ \ + " CMP r2, #0 \n" /* if (length == 0) */ \ + " BNE 1b \n" \ + " MCR p0,#0x1,r7,c1,c0,#6 \n" /* write biquad0*/ \ + " MRC p0,#0x1,r7,c1,c0,#0 \n" /* read biquad0*/ \ + " STRD r6,r7,[r1],#8 \n" /* store fourth two results */ \ + ) + +/*! + * @brief Fixed 16-bit data vector direct form II biquad cascade filter. + * + * The input and output data are fixed 16-bit data. The data flow is + * input -> biquad side 1 -> biquad side 0 -> output. + * + * @code + #define VECTOR_LEN 8 + int32_t input[VECTOR_LEN] = {1, 2, 3, 4, 5, 6, 7, 8}; + int32_t output[VECTOR_LEN]; + pq_biquad_state_t state0 = + { + .param = + { + .a_1 = xxx, + .a_2 = xxx, + .b_0 = xxx, + .b_1 = xxx, + .b_2 = xxx, + }, + }; + + pq_biquad_state_t state1 = + { + .param = + { + .a_1 = xxx, + .a_2 = xxx, + .b_0 = xxx, + .b_1 = xxx, + .b_2 = xxx, + }, + }; + + PQ_BiquadRestoreInternalState(POWERQUAD, 0, &state0); + PQ_BiquadRestoreInternalState(POWERQUAD, 1, &state1); + + PQ_StartVector(input, output, VECTOR_LEN); + PQ_Vector8BiqaudDf2CascadeFixed16(); + PQ_EndVector(); + @endcode + * + */ +#define PQ_Vector8BiqaudDf2CascadeFixed16() \ + __asm volatile( \ + "1: \n" \ + " MCR p0,#0x1,r4,c3,c0,#6 \n" /* write biquad1*/ \ + " CMP r3, #0 \n" \ + " ITTTE NE \n" \ + " MCRNE p0,#0x1,r7,c1,c0,#6 \n" /* write biquad0*/ \ + " MRCNE p0,#0x1,r7,c1,c0,#0 \n" /* read biquad0*/ \ + " MRCNE p0,#0x1,r4,c3,c0,#0 \n" /* read biquad1*/ \ + " MRCEQ p0,#0x1,r4,c3,c0,#0 \n" /* read biquad1*/ \ + " MCR p0,#0x1,r5,c3,c0,#6 \n" /* write biquad1*/ \ + " MCR p0,#0x1,r4,c1,c0,#6 \n" /* write biquad0*/ \ + " CMP r3, #0 \n" \ + " ITTE NE \n" \ + " STRHNE r6,[r1],#2 \n" /* store last two results*/ \ + " STRHNE r7,[r1],#2 \n" /* store last two results*/ \ + " MOVEQ r3, #1 \n" /* middle = 1 */ \ + " LDRSH r6,[r0],#2 \n" /* load next 2 of the 8*/ \ + " LDRSH r7,[r0],#2 \n" /* load next 2 of the 8*/ \ + " MRC p0,#0x1,r4,c1,c0,#0 \n" /* read biquad0*/ \ + " MRC p0,#0x1,r5,c3,c0,#0 \n" /* read biquad1*/ \ + " MCR p0,#0x1,r6,c3,c0,#6 \n" /* write biquad1*/ \ + " MCR p0,#0x1,r5,c1,c0,#6 \n" /* write biquad0*/ \ + " MRC p0,#0x1,r5,c1,c0,#0 \n" /* read biquad0*/ \ + " MRC p0,#0x1,r6,c3,c0,#0 \n" /* read biquad1*/ \ + " LDRSH r8,[r0],#2 \n" /* load next 2 of the 8*/ \ + " LDRSH r9,[r0],#2 \n" /* load next 2 of the 8*/ \ + " MCR p0,#0x1,r7,c3,c0,#6 \n" /* write biquad1*/ \ + " MCR p0,#0x1,r6,c1,c0,#6 \n" /* write biquad0*/ \ + " MRC p0,#0x1,r6,c1,c0,#0 \n" /* read biquad0*/ \ + " MRC p0,#0x1,r7,c3,c0,#0 \n" /* read biquad1*/ \ + " STRH r4,[r1],#2 \n" /* store first 4 results */ \ + " STRH r5,[r1],#2 \n" /* store first 4 results */ \ + " MCR p0,#0x1,r8,c3,c0,#6 \n" /* write biquad1*/ \ + " MCR p0,#0x1,r7,c1,c0,#6 \n" /* write biquad0*/ \ + " MRC p0,#0x1,r7,c1,c0,#0 \n" /* read biquad0*/ \ + " MRC p0,#0x1,r8,c3,c0,#0 \n" /* read biquad1*/ \ + " MCR p0,#0x1,r9,c3,c0,#6 \n" /* write biquad1*/ \ + " MCR p0,#0x1,r8,c1,c0,#6 \n" /* write biquad0*/ \ + " STRH r6,[r1],#2 \n" /* store first 4 results */ \ + " STRH r7,[r1],#2 \n" /* store first 4 results */ \ + " LDRSH r6,[r0],#2 \n" /* load last 2 of the 8*/ \ + " LDRSH r7,[r0],#2 \n" /* load last 2 of the 8*/ \ + " MRC p0,#0x1,r8,c1,c0,#0 \n" /* read biquad0*/ \ + " MRC p0,#0x1,r9,c3,c0,#0 \n" /* read biquad1*/ \ + " MCR p0,#0x1,r6,c3,c0,#6 \n" /* write biquad1*/ \ + " MCR p0,#0x1,r9,c1,c0,#6 \n" /* write biquad0*/ \ + " SUBS r2, r2, #8 \n" /* length -= 8; if (length != 0) */ \ + " ITT NE \n" \ + " LDRSHNE r4,[r0],#2 \n" /* load first two of next 8*/ \ + " LDRSHNE r5,[r0],#2 \n" /* load first two of next 8*/ \ + " MRC p0,#0x1,r9,c1,c0,#0 \n" /* read biquad0*/ \ + " MRC p0,#0x1,r6,c3,c0,#0 \n" /* read biquad1*/ \ + " MCR p0,#0x1,r7,c3,c0,#6 \n" /* write biquad1*/ \ + " MCR p0,#0x1,r6,c1,c0,#6 \n" /* write biquad0*/ \ + " STRH r8,[r1],#2 \n" /* store third two results */ \ + " STRH r9,[r1],#2 \n" /* store third two results */ \ + " MRC p0,#0x1,r6,c1,c0,#0 \n" /* read biquad0*/ \ + " MRC p0,#0x1,r7,c3,c0,#0 \n" /* read biquad1*/ \ + " CMP r2, #0 \n" /* if (length == 0) */ \ + " BNE 1b \n" \ + " MCR p0,#0x1,r7,c1,c0,#6 \n" /* write biquad0*/ \ + " MRC p0,#0x1,r7,c1,c0,#0 \n" /* read biquad0*/ \ + " STRH r6,[r1],#2 \n" /* store fourth two results */ \ + " STRH r7,[r1],#2 \n" /* store fourth two results */ \ + ) + +/*! @brief Make the length used for matrix functions. */ +#define POWERQUAD_MAKE_MATRIX_LEN(mat1Row, mat1Col, mat2Col) \ + (((uint32_t)(mat1Row) << 0U) | ((uint32_t)(mat1Col) << 8U) | ((uint32_t)(mat2Col) << 16U)) + +/*! @brief Convert Q31 to float. */ +#define PQ_Q31_2_FLOAT(x) (((float)(x)) / 2147483648.0f) + +/*! @brief Convert Q15 to float. */ +#define PQ_Q15_2_FLOAT(x) (((float)(x)) / 32768.0f) + +/*! @brief powerquad computation engine */ +typedef enum +{ + kPQ_CP_PQ = 0, /*!< Math engine.*/ + kPQ_CP_MTX = 1, /*!< Matrix engine.*/ + kPQ_CP_FFT = 2, /*!< FFT engine.*/ + kPQ_CP_FIR = 3, /*!< FIR engine.*/ + kPQ_CP_CORDIC = 5 /*!< CORDIC engine.*/ +} pq_computationengine_t; + +/*! @brief powerquad data structure format type */ +typedef enum +{ + kPQ_16Bit = 0, /*!< Int16 Fixed point.*/ + kPQ_32Bit = 1, /*!< Int32 Fixed point.*/ + kPQ_Float = 2 /*!< Float point.*/ +} pq_format_t; + +/*! @brief Coprocessor prescale */ +typedef struct +{ + int8_t inputPrescale; /*!< Input prescale.*/ + int8_t outputPrescale; /*!< Output prescale.*/ + int8_t outputSaturate; /*!< Output saturate at n bits, for example 0x11 is 8 bit space, + the value will be truncated at +127 or -128.*/ +} pq_prescale_t; + +/*! @brief powerquad data structure format */ +typedef struct +{ + pq_format_t inputAFormat; /*!< Input A format.*/ + int8_t inputAPrescale; /*!< Input A prescale, for example 1.5 can be 1.5*2^n if you scale by 'shifting' + ('scaling' by a factor of n).*/ + pq_format_t inputBFormat; /*!< Input B format.*/ + int8_t inputBPrescale; /*!< Input B prescale.*/ + pq_format_t outputFormat; /*!< Out format.*/ + int8_t outputPrescale; /*!< Out prescale.*/ + pq_format_t tmpFormat; /*!< Temp format.*/ + int8_t tmpPrescale; /*!< Temp prescale.*/ + pq_format_t machineFormat; /*!< Machine format.*/ + uint32_t *tmpBase; /*!< Tmp base address.*/ +} pq_config_t; + +/*! @brief Struct to save biquad parameters. */ +typedef struct _pq_biquad_param +{ + float v_n_1; /*!< v[n-1], set to 0 when initialization. */ + float v_n; /*!< v[n], set to 0 when initialization. */ + float a_1; /*!< a[1] */ + float a_2; /*!< a[2] */ + float b_0; /*!< b[0] */ + float b_1; /*!< b[1] */ + float b_2; /*!< b[2] */ +} pq_biquad_param_t; + +/*! @brief Struct to save biquad state. */ +typedef struct _pq_biquad_state +{ + pq_biquad_param_t param; /*!< Filter parameter. */ + uint32_t compreg; /*!< Internal register, set to 0 when initialization. */ +} pq_biquad_state_t; + +/*! @brief Instance structure for the direct form II Biquad cascade filter */ +typedef struct +{ + uint8_t numStages; /**< Number of 2nd order stages in the filter.*/ + pq_biquad_state_t *pState; /**< Points to the array of state coefficients.*/ +} pq_biquad_cascade_df2_instance; + +/*! @brief CORDIC iteration */ +typedef enum +{ + kPQ_Iteration_8 = 0, /*!< Iterate 8 times.*/ + kPQ_Iteration_16, /*!< Iterate 16 times.*/ + kPQ_Iteration_24 /*!< Iterate 24 times.*/ +} pq_cordic_iter_t; + +/*! @brief Conversion between integer and float type */ +typedef union _pq_float +{ + float floatX; /*!< Float type.*/ + uint32_t integerX; /*!< Iterger type.*/ +} pq_float_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @name POWERQUAD functional Operation + * @{ + */ + +/*! + * @brief Get default configuration. + * + * This function initializes the POWERQUAD configuration structure to a default value. + * FORMAT register field definitions + * Bits[15:8] scaler (for scaled 'q31' formats) + * Bits[5:4] external format. 00b=q15, 01b=q31, 10b=float + * Bits[1:0] internal format. 00b=q15, 01b=q31, 10b=float + * POWERQUAD->INAFORMAT = (config->inputAPrescale << 8) | (config->inputAFormat << 4) | config->machineFormat + * + * For all Powerquad operations internal format must be float (with the only exception being + * the FFT related functions, ie FFT/IFFT/DCT/IDCT which must be set to q31). + * The default values are: + * config->inputAFormat = kPQ_Float; + * config->inputAPrescale = 0; + * config->inputBFormat = kPQ_Float; + * config->inputBPrescale = 0; + * config->outputFormat = kPQ_Float; + * config->outputPrescale = 0; + * config->tmpFormat = kPQ_Float; + * config->tmpPrescale = 0; + * config->machineFormat = kPQ_Float; + * config->tmpBase = 0xE0000000; + * + * @param config Pointer to "pq_config_t" structure. + */ +void PQ_GetDefaultConfig(pq_config_t *config); + +/*! + * @brief Set configuration with format/prescale. + * + * @param base POWERQUAD peripheral base address + * @param config Pointer to "pq_config_t" structure. + */ +void PQ_SetConfig(POWERQUAD_Type *base, const pq_config_t *config); + +/*! + * @brief set coprocessor scaler for coprocessor instructions, this function is used to + * set output saturation and scaleing for input/output. + * + * @param base POWERQUAD peripheral base address + * @param prescale Pointer to "pq_prescale_t" structure. + */ +static inline void PQ_SetCoprocessorScaler(POWERQUAD_Type *base, const pq_prescale_t *prescale) +{ + assert(prescale); + + base->CPPRE = POWERQUAD_CPPRE_CPPRE_IN(prescale->inputPrescale) | + POWERQUAD_CPPRE_CPPRE_OUT(prescale->outputPrescale) | + ((uint32_t)prescale->outputSaturate << POWERQUAD_CPPRE_CPPRE_SAT_SHIFT); +} + +/*! + * @brief Initializes the POWERQUAD module. + * + * @param base POWERQUAD peripheral base address. + */ +void PQ_Init(POWERQUAD_Type *base); + +/*! + * @brief De-initializes the POWERQUAD module. + * + * @param base POWERQUAD peripheral base address. + */ +void PQ_Deinit(POWERQUAD_Type *base); + +/*! + * @brief Set format for non-coprecessor instructions. + * + * @param base POWERQUAD peripheral base address + * @param engine Computation engine + * @param format Data format + */ +void PQ_SetFormat(POWERQUAD_Type *base, pq_computationengine_t engine, pq_format_t format); + +/*! + * @brief Wait for the completion. + * + * @param base POWERQUAD peripheral base address + */ +static inline void PQ_WaitDone(POWERQUAD_Type *base) +{ + /* wait for the completion */ + while ((base->CONTROL & INST_BUSY) == INST_BUSY) + { + __WFE(); + } +} + +/*! + * @brief Processing function for the floating-point natural log. + * + * @param *pSrc points to the block of input data. The range of the input value is (0 +INFINITY). + * @param *pDst points to the block of output data + */ +static inline void PQ_LnF32(float *pSrc, float *pDst) +{ + _pq_ln0(*(int32_t *)pSrc); + *(int32_t *)pDst = _pq_readAdd0(); +} + +/*! + * @brief Processing function for the floating-point reciprocal. + * + * @param *pSrc points to the block of input data. The range of the input value is non-zero. + * @param *pDst points to the block of output data + */ +static inline void PQ_InvF32(float *pSrc, float *pDst) +{ + _pq_inv0(*(int32_t *)pSrc); + *(int32_t *)pDst = _pq_readMult0(); +} + +/*! + * @brief Processing function for the floating-point square-root. + * + * @param *pSrc points to the block of input data. The range of the input value is [0 +INFINITY). + * @param *pDst points to the block of output data + */ +static inline void PQ_SqrtF32(float *pSrc, float *pDst) +{ + _pq_sqrt0(*(int32_t *)pSrc); + *(int32_t *)pDst = _pq_readMult0(); +} + +/*! + * @brief Processing function for the floating-point inverse square-root. + * + * @param *pSrc points to the block of input data. The range of the input value is (0 +INFINITY). + * @param *pDst points to the block of output data + */ +static inline void PQ_InvSqrtF32(float *pSrc, float *pDst) +{ + _pq_invsqrt0(*(int32_t *)pSrc); + *(int32_t *)pDst = _pq_readMult0(); +} + +/*! + * @brief Processing function for the floating-point natural exponent. + * + * @param *pSrc points to the block of input data. The range of the input value is (-INFINITY +INFINITY). + * @param *pDst points to the block of output data + */ +static inline void PQ_EtoxF32(float *pSrc, float *pDst) +{ + _pq_etox0(*(int32_t *)pSrc); + *(int32_t *)pDst = _pq_readMult0(); +} + +/*! + * @brief Processing function for the floating-point natural exponent with negative parameter. + * + * @param *pSrc points to the block of input data. The range of the input value is (-INFINITY +INFINITY). + * @param *pDst points to the block of output data + */ +static inline void PQ_EtonxF32(float *pSrc, float *pDst) +{ + _pq_etonx0(*(int32_t *)pSrc); + *(int32_t *)pDst = _pq_readMult0(); +} + +/*! + * @brief Processing function for the floating-point sine. + * + * @param *pSrc points to the block of input data. The input value is in radians, the range is (-INFINITY + * +INFINITY). + * @param *pDst points to the block of output data + */ +static inline void PQ_SinF32(float *pSrc, float *pDst) +{ + _pq_sin0(*(int32_t *)pSrc); + *(int32_t *)pDst = _pq_readAdd0(); +} + +/*! + * @brief Processing function for the floating-point cosine. + * + * @param *pSrc points to the block of input data. The input value is in radians, the range is (-INFINITY + * +INFINITY). + * @param *pDst points to the block of output data + */ +static inline void PQ_CosF32(float *pSrc, float *pDst) +{ + _pq_cos0(*(int32_t *)pSrc); + *(int32_t *)pDst = _pq_readAdd0(); +} + +/*! + * @brief Processing function for the floating-point biquad. + * + * @param *pSrc points to the block of input data + * @param *pDst points to the block of output data + */ +static inline void PQ_BiquadF32(float *pSrc, float *pDst) +{ + _pq_biquad0(*(int32_t *)pSrc); + *(int32_t *)pDst = _pq_readAdd0(); +} + +/*! + * @brief Processing function for the floating-point division. + * + * Get x1 / x2. + * + * @param x1 x1 + * @param x2 x2 + * @param *pDst points to the block of output data + */ +static inline void PQ_DivF32(float *x1, float *x2, float *pDst) +{ + uint32_t X1 = *(uint32_t *)x1; + uint32_t X2 = *(uint32_t *)x2; + uint64_t input = (uint64_t)(X2) | ((uint64_t)(X1) << 32U); + + _pq_div0(input); + *(int32_t *)pDst = _pq_readMult0(); +} + +/*! + * @brief Processing function for the floating-point biquad. + * + * @param *pSrc points to the block of input data + * @param *pDst points to the block of output data + */ +static inline void PQ_Biquad1F32(float *pSrc, float *pDst) +{ + _pq_biquad1(*(int32_t *)pSrc); + *(int32_t *)pDst = _pq_readAdd1(); +} + +/*! + * @brief Processing function for the fixed natural log. + * + * @param val value to be calculated. The range of the input value is (0 +INFINITY). + * @return returns ln(val). + */ +static inline int32_t PQ_LnFixed(int32_t val) +{ + _pq_ln_fx0(val); + return _pq_readAdd0_fx(); +} + +/*! + * @brief Processing function for the fixed reciprocal. + * + * @param val value to be calculated. The range of the input value is non-zero. + * @return returns inv(val). + */ +static inline int32_t PQ_InvFixed(int32_t val) +{ + _pq_inv_fx0(val); + return _pq_readMult0_fx(); +} + +/*! + * @brief Processing function for the fixed square-root. + * + * @param val value to be calculated. The range of the input value is [0 +INFINITY). + * @return returns sqrt(val). + */ +static inline uint32_t PQ_SqrtFixed(uint32_t val) +{ + _pq_sqrt_fx0(val); + return _pq_readMult0_fx(); +} + +/*! + * @brief Processing function for the fixed inverse square-root. + * + * @param val value to be calculated. The range of the input value is (0 +INFINITY). + * @return returns 1/sqrt(val). + */ +static inline int32_t PQ_InvSqrtFixed(int32_t val) +{ + _pq_invsqrt_fx0(val); + return _pq_readMult0_fx(); +} + +/*! + * @brief Processing function for the Fixed natural exponent. + * + * @param val value to be calculated. The range of the input value is (-INFINITY +INFINITY). + * @return returns etox^(val). + */ +static inline int32_t PQ_EtoxFixed(int32_t val) +{ + _pq_etox_fx0(val); + return _pq_readMult0_fx(); +} + +/*! + * @brief Processing function for the fixed natural exponent with negative parameter. + * + * @param val value to be calculated. The range of the input value is (-INFINITY +INFINITY). + * @return returns etonx^(val). + */ +static inline int32_t PQ_EtonxFixed(int32_t val) +{ + _pq_etonx_fx0(val); + return _pq_readMult0_fx(); +} + +/*! + * @brief Processing function for the fixed sine. + * + * @param val value to be calculated. The input value is [-1, 1] in Q31 format, which means [-pi, pi]. + * @return returns sin(val). + */ +static inline int32_t PQ_SinQ31(int32_t val) +{ + int32_t ret; + uint32_t cppre; +#if defined(FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA) && FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA + pq_float_t magic; + pq_float_t valFloat; + + magic.integerX = 0x30c90fdb; + valFloat.floatX = magic.floatX * (float)val; +#endif + + cppre = POWERQUAD->CPPRE; + POWERQUAD->CPPRE = POWERQUAD_CPPRE_CPPRE_OUT(31); + +#if defined(FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA) && FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA + _pq_sin0(valFloat.integerX); + + ret = _pq_readAdd0(); + ret = _pq_readAdd0_fx(); +#else + _pq_sin_fx0(val); + ret = _pq_readAdd0_fx(); +#endif + + POWERQUAD->CPPRE = cppre; + + return ret; +} + +/*! + * @brief Processing function for the fixed sine. + * + * @param val value to be calculated. The input value is [-1, 1] in Q15 format, which means [-pi, pi]. + * @return returns sin(val). + */ +static inline int16_t PQ_SinQ15(int16_t val) +{ + int32_t ret; + uint32_t cppre; +#if defined(FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA) && FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA + pq_float_t magic; + pq_float_t valFloat; + + magic.integerX = 0x30c90fdb; + valFloat.floatX = magic.floatX * (float)(val << 16); +#endif + + cppre = POWERQUAD->CPPRE; + /* Don't use 15 here, it is wrong then val is 0x4000 */ + POWERQUAD->CPPRE = POWERQUAD_CPPRE_CPPRE_OUT(31); + +#if defined(FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA) && FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA + _pq_sin0(valFloat.integerX); + + ret = _pq_readAdd0(); + ret = _pq_readAdd0_fx(); + ret >>= 16; +#else + _pq_sin_fx0((uint32_t)val << 16); + ret = (_pq_readAdd0_fx()) >> 16; +#endif + + POWERQUAD->CPPRE = cppre; + + return (int16_t)ret; +} + +/*! + * @brief Processing function for the fixed cosine. + * + * @param val value to be calculated. The input value is [-1, 1] in Q31 format, which means [-pi, pi]. + * @return returns cos(val). + */ +static inline int32_t PQ_CosQ31(int32_t val) +{ + int32_t ret; + uint32_t cppre; +#if defined(FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA) && FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA + pq_float_t magic; + pq_float_t valFloat; + + magic.integerX = 0x30c90fdb; + valFloat.floatX = magic.floatX * (float)val; +#endif + + cppre = POWERQUAD->CPPRE; + POWERQUAD->CPPRE = POWERQUAD_CPPRE_CPPRE_OUT(31); + +#if defined(FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA) && FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA + _pq_cos0(valFloat.integerX); + + ret = _pq_readAdd0(); + ret = _pq_readAdd0_fx(); +#else + _pq_cos_fx0(val); + ret = _pq_readAdd0_fx(); +#endif + + POWERQUAD->CPPRE = cppre; + + return ret; +} + +/*! + * @brief Processing function for the fixed sine. + * + * @param val value to be calculated. The input value is [-1, 1] in Q15 format, which means [-pi, pi]. + * @return returns sin(val). + */ +static inline int16_t PQ_CosQ15(int16_t val) +{ + int32_t ret; + uint32_t cppre; +#if defined(FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA) && FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA + pq_float_t magic; + pq_float_t valFloat; + + magic.integerX = 0x30c90fdb; + valFloat.floatX = magic.floatX * (float)(val << 16); +#endif + + cppre = POWERQUAD->CPPRE; + POWERQUAD->CPPRE = POWERQUAD_CPPRE_CPPRE_OUT(31); + +#if defined(FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA) && FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA + _pq_cos0(valFloat.integerX); + + ret = _pq_readAdd0(); + ret = _pq_readAdd0_fx(); + ret >>= 16; +#else + _pq_cos_fx0((uint32_t)val << 16); + ret = (_pq_readAdd0_fx()) >> 16; +#endif + + POWERQUAD->CPPRE = cppre; + + return (int16_t)ret; +} + +/*! + * @brief Processing function for the fixed biquad. + * + * @param val value to be calculated + * @return returns biquad(val). + */ +static inline int32_t PQ_BiquadFixed(int32_t val) +{ + _pq_biquad0_fx(val); + return _pq_readAdd0_fx(); +} + +/*! + * @brief Processing function for the floating-point vectorised natural log. + * + * @param *pSrc points to the block of input data + * @param *pDst points to the block of output data + * @param length the block of input data. + */ +void PQ_VectorLnF32(float *pSrc, float *pDst, int32_t length); + +/*! + * @brief Processing function for the floating-point vectorised reciprocal. + * + * @param *pSrc points to the block of input data + * @param *pDst points to the block of output data + * @param length the block of input data. + */ +void PQ_VectorInvF32(float *pSrc, float *pDst, int32_t length); + +/*! + * @brief Processing function for the floating-point vectorised square-root. + * + * @param *pSrc points to the block of input data + * @param *pDst points to the block of output data + * @param length the block of input data. + */ +void PQ_VectorSqrtF32(float *pSrc, float *pDst, int32_t length); + +/*! + * @brief Processing function for the floating-point vectorised inverse square-root. + * + * @param *pSrc points to the block of input data + * @param *pDst points to the block of output data + * @param length the block of input data. + */ +void PQ_VectorInvSqrtF32(float *pSrc, float *pDst, int32_t length); + +/*! + * @brief Processing function for the floating-point vectorised natural exponent. + * + * @param *pSrc points to the block of input data + * @param *pDst points to the block of output data + * @param length the block of input data. + */ +void PQ_VectorEtoxF32(float *pSrc, float *pDst, int32_t length); + +/*! + * @brief Processing function for the floating-point vectorised natural exponent with negative parameter. + * + * @param *pSrc points to the block of input data + * @param *pDst points to the block of output data + * @param length the block of input data. + */ +void PQ_VectorEtonxF32(float *pSrc, float *pDst, int32_t length); + +/*! + * @brief Processing function for the floating-point vectorised sine + * + * @param *pSrc points to the block of input data + * @param *pDst points to the block of output data + * @param length the block of input data. + */ +void PQ_VectorSinF32(float *pSrc, float *pDst, int32_t length); + +/*! + * @brief Processing function for the floating-point vectorised cosine. + * + * @param *pSrc points to the block of input data + * @param *pDst points to the block of output data + * @param length the block of input data. + */ +void PQ_VectorCosF32(float *pSrc, float *pDst, int32_t length); + +/*! + * @brief Processing function for the Q31 vectorised natural log. + * + * @param *pSrc points to the block of input data + * @param *pDst points to the block of output data + * @param length the block of input data. + */ +void PQ_VectorLnFixed32(int32_t *pSrc, int32_t *pDst, int32_t length); + +/*! + * @brief Processing function for the Q31 vectorised reciprocal. + * + * @param *pSrc points to the block of input data + * @param *pDst points to the block of output data + * @param length the block of input data. + */ +void PQ_VectorInvFixed32(int32_t *pSrc, int32_t *pDst, int32_t length); + +/*! + * @brief Processing function for the 32-bit integer vectorised square-root. + * + * @param *pSrc points to the block of input data + * @param *pDst points to the block of output data + * @param length the block of input data. + */ +void PQ_VectorSqrtFixed32(int32_t *pSrc, int32_t *pDst, int32_t length); + +/*! + * @brief Processing function for the 32-bit integer vectorised inverse square-root. + * + * @param *pSrc points to the block of input data + * @param *pDst points to the block of output data + * @param length the block of input data. + */ +void PQ_VectorInvSqrtFixed32(int32_t *pSrc, int32_t *pDst, int32_t length); + +/*! + * @brief Processing function for the 32-bit integer vectorised natural exponent. + * + * @param *pSrc points to the block of input data + * @param *pDst points to the block of output data + * @param length the block of input data. + */ +void PQ_VectorEtoxFixed32(int32_t *pSrc, int32_t *pDst, int32_t length); + +/*! + * @brief Processing function for the 32-bit integer vectorised natural exponent with negative parameter. + * + * @param *pSrc points to the block of input data + * @param *pDst points to the block of output data + * @param length the block of input data. + */ +void PQ_VectorEtonxFixed32(int32_t *pSrc, int32_t *pDst, int32_t length); + +/*! + * @brief Processing function for the Q15 vectorised sine + * + * @param *pSrc points to the block of input data + * @param *pDst points to the block of output data + * @param length the block of input data. + */ +void PQ_VectorSinQ15(int16_t *pSrc, int16_t *pDst, int32_t length); + +/*! + * @brief Processing function for the Q15 vectorised cosine. + * + * @param *pSrc points to the block of input data + * @param *pDst points to the block of output data + * @param length the block of input data. + */ +void PQ_VectorCosQ15(int16_t *pSrc, int16_t *pDst, int32_t length); + +/*! + * @brief Processing function for the Q31 vectorised sine + * + * @param *pSrc points to the block of input data + * @param *pDst points to the block of output data + * @param length the block of input data. + */ +void PQ_VectorSinQ31(int32_t *pSrc, int32_t *pDst, int32_t length); + +/*! + * @brief Processing function for the Q31 vectorised cosine. + * + * @param *pSrc points to the block of input data + * @param *pDst points to the block of output data + * @param length the block of input data. + */ +void PQ_VectorCosQ31(int32_t *pSrc, int32_t *pDst, int32_t length); + +/*! + * @brief Processing function for the 16-bit integer vectorised natural log. + * + * @param *pSrc points to the block of input data + * @param *pDst points to the block of output data + * @param length the block of input data. + */ +void PQ_VectorLnFixed16(int16_t *pSrc, int16_t *pDst, int32_t length); + +/*! + * @brief Processing function for the 16-bit integer vectorised reciprocal. + * + * @param *pSrc points to the block of input data + * @param *pDst points to the block of output data + * @param length the block of input data. + */ +void PQ_VectorInvFixed16(int16_t *pSrc, int16_t *pDst, int32_t length); + +/*! + * @brief Processing function for the 16-bit integer vectorised square-root. + * + * @param *pSrc points to the block of input data + * @param *pDst points to the block of output data + * @param length the block of input data. + */ +void PQ_VectorSqrtFixed16(int16_t *pSrc, int16_t *pDst, int32_t length); + +/*! + * @brief Processing function for the 16-bit integer vectorised inverse square-root. + * + * @param *pSrc points to the block of input data + * @param *pDst points to the block of output data + * @param length the block of input data. + */ +void PQ_VectorInvSqrtFixed16(int16_t *pSrc, int16_t *pDst, int32_t length); + +/*! + * @brief Processing function for the 16-bit integer vectorised natural exponent. + * + * @param *pSrc points to the block of input data + * @param *pDst points to the block of output data + * @param length the block of input data. + */ +void PQ_VectorEtoxFixed16(int16_t *pSrc, int16_t *pDst, int32_t length); + +/*! + * @brief Processing function for the 16-bit integer vectorised natural exponent with negative parameter. + * + * @param *pSrc points to the block of input data + * @param *pDst points to the block of output data + * @param length the block of input data. + */ +void PQ_VectorEtonxFixed16(int16_t *pSrc, int16_t *pDst, int32_t length); + +/*! + * @brief Processing function for the floating-point vectorised biquad direct form II. + * + * @param *pSrc points to the block of input data + * @param *pDst points to the block of output data + * @param length the block size of input data. + */ +void PQ_VectorBiqaudDf2F32(float *pSrc, float *pDst, int32_t length); + +/*! + * @brief Processing function for the 32-bit integer vectorised biquad direct form II. + * + * @param *pSrc points to the block of input data + * @param *pDst points to the block of output data + * @param blocksSize the block size of input data + */ +void PQ_VectorBiqaudDf2Fixed32(int32_t *pSrc, int32_t *pDst, int32_t length); + +/*! + * @brief Processing function for the 16-bit integer vectorised biquad direct form II. + * + * @param *pSrc points to the block of input data + * @param *pDst points to the block of output data + * @param blocksSize the block size of input data + */ +void PQ_VectorBiqaudDf2Fixed16(int16_t *pSrc, int16_t *pDst, int32_t length); + +/*! + * @brief Processing function for the floating-point vectorised biquad direct form II. + * + * @param *pSrc points to the block of input data + * @param *pDst points to the block of output data + * @param blocksSize the block size of input data + */ +void PQ_VectorBiqaudCascadeDf2F32(float *pSrc, float *pDst, int32_t length); + +/*! + * @brief Processing function for the 32-bit integer vectorised biquad direct form II. + * + * @param *pSrc points to the block of input data + * @param *pDst points to the block of output data + * @param blocksSize the block size of input data + */ +void PQ_VectorBiqaudCascadeDf2Fixed32(int32_t *pSrc, int32_t *pDst, int32_t length); + +/*! + * @brief Processing function for the 16-bit integer vectorised biquad direct form II. + * + * @param *pSrc points to the block of input data + * @param *pDst points to the block of output data + * @param blocksSize the block size of input data + */ +void PQ_VectorBiqaudCascadeDf2Fixed16(int16_t *pSrc, int16_t *pDst, int32_t length); + +/*! + * @brief Processing function for the fixed inverse trigonometric. + * + * @param base POWERQUAD peripheral base address + * @param x value of opposite + * @param y value of adjacent + * @param iteration iteration times + * @return The return value is in the range of -2^27 to 2^27, which means -pi to pi. + * @note The sum of x and y should not exceed the range of int32_t. + * @note Larger input number gets higher output accuracy, for example the arctan(0.5), + * the result of PQ_ArctanFixed(POWERQUAD, 100000, 200000, kPQ_Iteration_24) is more + * accurate than PQ_ArctanFixed(POWERQUAD, 1, 2, kPQ_Iteration_24). + */ +int32_t PQ_ArctanFixed(POWERQUAD_Type *base, int32_t x, int32_t y, pq_cordic_iter_t iteration); + +/*! + * @brief Processing function for the fixed inverse trigonometric. + * + * @param base POWERQUAD peripheral base address + * @param x value of opposite + * @param y value of adjacent + * @param iteration iteration times + * @return The return value is in the range of -2^27 to 2^27, which means -1 to 1. + * @note The sum of x and y should not exceed the range of int32_t. + * @note Larger input number gets higher output accuracy, for example the arctanh(0.5), + * the result of PQ_ArctanhFixed(POWERQUAD, 100000, 200000, kPQ_Iteration_24) is more + * accurate than PQ_ArctanhFixed(POWERQUAD, 1, 2, kPQ_Iteration_24). + */ +int32_t PQ_ArctanhFixed(POWERQUAD_Type *base, int32_t x, int32_t y, pq_cordic_iter_t iteration); + +/*! + * @brief Processing function for the fixed biquad. + * + * @param val value to be calculated + * @return returns biquad(val). + */ +static inline int32_t PQ_Biquad1Fixed(int32_t val) +{ + _pq_biquad1_fx(val); + return _pq_readAdd1_fx(); +} + +/*! + * @brief Processing function for the complex FFT. + * + * @param base POWERQUAD peripheral base address + * @param length number of input samples + * @param pData input data + * @param pResult output data. + */ +void PQ_TransformCFFT(POWERQUAD_Type *base, uint32_t length, void *pData, void *pResult); + +/*! + * @brief Processing function for the real FFT. + * + * @param base POWERQUAD peripheral base address + * @param length number of input samples + * @param pData input data + * @param pResult output data. + */ +void PQ_TransformRFFT(POWERQUAD_Type *base, uint32_t length, void *pData, void *pResult); + +/*! + * @brief Processing function for the inverse complex FFT. + * + * @param base POWERQUAD peripheral base address + * @param length number of input samples + * @param pData input data + * @param pResult output data. + */ +void PQ_TransformIFFT(POWERQUAD_Type *base, uint32_t length, void *pData, void *pResult); + +/*! + * @brief Processing function for the complex DCT. + * + * @param base POWERQUAD peripheral base address + * @param length number of input samples + * @param pData input data + * @param pResult output data. + */ +void PQ_TransformCDCT(POWERQUAD_Type *base, uint32_t length, void *pData, void *pResult); + +/*! + * @brief Processing function for the real DCT. + * + * @param base POWERQUAD peripheral base address + * @param length number of input samples + * @param pData input data + * @param pResult output data. + */ +void PQ_TransformRDCT(POWERQUAD_Type *base, uint32_t length, void *pData, void *pResult); + +/*! + * @brief Processing function for the inverse complex DCT. + * + * @param base POWERQUAD peripheral base address + * @param length number of input samples + * @param pData input data + * @param pResult output data. + */ +void PQ_TransformIDCT(POWERQUAD_Type *base, uint32_t length, void *pData, void *pResult); + +/*! + * @brief Processing function for backup biquad context. + * + * @param base POWERQUAD peripheral base address + * @param biquad_num biquad side + * @param state point to states. + */ +void PQ_BiquadBackUpInternalState(POWERQUAD_Type *base, int32_t biquad_num, pq_biquad_state_t *state); + +/*! + * @brief Processing function for restore biquad context. + * + * @param base POWERQUAD peripheral base address + * @param biquad_num biquad side + * @param state point to states. + */ +void PQ_BiquadRestoreInternalState(POWERQUAD_Type *base, int32_t biquad_num, pq_biquad_state_t *state); + +/*! + * @brief Initialization function for the direct form II Biquad cascade filter. + * + * @param[in,out] *S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pState points to the state buffer. + */ +void PQ_BiquadCascadeDf2Init(pq_biquad_cascade_df2_instance *S, uint8_t numStages, pq_biquad_state_t *pState); + +/*! + * @brief Processing function for the floating-point direct form II Biquad cascade filter. + * + * @param[in] *S points to an instance of the filter data structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ +void PQ_BiquadCascadeDf2F32(const pq_biquad_cascade_df2_instance *S, float *pSrc, float *pDst, uint32_t blockSize); + +/*! + * @brief Processing function for the Q31 direct form II Biquad cascade filter. + * + * @param[in] *S points to an instance of the filter data structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ +void PQ_BiquadCascadeDf2Fixed32(const pq_biquad_cascade_df2_instance *S, + int32_t *pSrc, + int32_t *pDst, + uint32_t blockSize); + +/*! + * @brief Processing function for the Q15 direct form II Biquad cascade filter. + * + * @param[in] *S points to an instance of the filter data structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ +void PQ_BiquadCascadeDf2Fixed16(const pq_biquad_cascade_df2_instance *S, + int16_t *pSrc, + int16_t *pDst, + uint32_t blockSize); + +/*! + * @brief Processing function for the FIR. + * + * @param base POWERQUAD peripheral base address + * @param pAData the first input sequence + * @param ALength number of the first input sequence + * @param pBData the second input sequence + * @param BLength number of the second input sequence + * @param pResult array for the output data + * @param opType operation type, could be PQ_FIR_FIR, PQ_FIR_CONVOLUTION, PQ_FIR_CORRELATION. + */ +void PQ_FIR( + POWERQUAD_Type *base, void *pAData, int32_t ALength, void *pBData, int32_t BLength, void *pResult, uint32_t opType); + +/*! + * @brief Processing function for the incremental FIR. + * This function can be used after pq_fir() for incremental FIR + * operation when new x data are available + * + * @param base POWERQUAD peripheral base address + * @param ALength number of input samples + * @param BLength number of taps + * @param xoffset offset for number of input samples + */ +void PQ_FIRIncrement(POWERQUAD_Type *base, int32_t ALength, int32_t BLength, int32_t xOffset); + +/*! + * @brief Processing function for the matrix addition. + * + * @param base POWERQUAD peripheral base address + * @param length rows and cols for matrix. LENGTH register configuration: + * LENGTH[23:16] = M2 cols + * LENGTH[15:8] = M1 cols + * LENGTH[7:0] = M1 rows + * This could be constructed using macro @ref POWERQUAD_MAKE_MATRIX_LEN. + * @param pAData input matrix A + * @param pBData input matrix B + * @param pResult array for the output data. + */ +void PQ_MatrixAddition(POWERQUAD_Type *base, uint32_t length, void *pAData, void *pBData, void *pResult); + +/*! + * @brief Processing function for the matrix subtraction. + * + * @param base POWERQUAD peripheral base address + * @param length rows and cols for matrix. LENGTH register configuration: + * LENGTH[23:16] = M2 cols + * LENGTH[15:8] = M1 cols + * LENGTH[7:0] = M1 rows + * This could be constructed using macro @ref POWERQUAD_MAKE_MATRIX_LEN. + * @param pAData input matrix A + * @param pBData input matrix B + * @param pResult array for the output data. + */ +void PQ_MatrixSubtraction(POWERQUAD_Type *base, uint32_t length, void *pAData, void *pBData, void *pResult); + +/*! + * @brief Processing function for the matrix multiplication. + * + * @param base POWERQUAD peripheral base address + * @param length rows and cols for matrix. LENGTH register configuration: + * LENGTH[23:16] = M2 cols + * LENGTH[15:8] = M1 cols + * LENGTH[7:0] = M1 rows + * This could be constructed using macro @ref POWERQUAD_MAKE_MATRIX_LEN. + * @param pAData input matrix A + * @param pBData input matrix B + * @param pResult array for the output data. + */ +void PQ_MatrixMultiplication(POWERQUAD_Type *base, uint32_t length, void *pAData, void *pBData, void *pResult); + +/*! + * @brief Processing function for the matrix product. + * + * @param base POWERQUAD peripheral base address + * @param length rows and cols for matrix. LENGTH register configuration: + * LENGTH[23:16] = M2 cols + * LENGTH[15:8] = M1 cols + * LENGTH[7:0] = M1 rows + * This could be constructed using macro @ref POWERQUAD_MAKE_MATRIX_LEN. + * @param pAData input matrix A + * @param pBData input matrix B + * @param pResult array for the output data. + */ +void PQ_MatrixProduct(POWERQUAD_Type *base, uint32_t length, void *pAData, void *pBData, void *pResult); + +/*! + * @brief Processing function for the vector dot product. + * + * @param base POWERQUAD peripheral base address + * @param length length of vector + * @param pAData input vector A + * @param pBData input vector B + * @param pResult array for the output data. + */ +void PQ_VectorDotProduct(POWERQUAD_Type *base, uint32_t length, void *pAData, void *pBData, void *pResult); + +/*! + * @brief Processing function for the matrix inverse. + * + * @param base POWERQUAD peripheral base address + * @param length rows and cols for matrix. LENGTH register configuration: + * LENGTH[23:16] = M2 cols + * LENGTH[15:8] = M1 cols + * LENGTH[7:0] = M1 rows + * This could be constructed using macro @ref POWERQUAD_MAKE_MATRIX_LEN. + * @param pData input matrix + * @param pTmpData input temporary matrix, pTmpData length not less than pData lenght and 1024 words is sufficient for + * the largest supported matrix. + * @param pResult array for the output data, round down for fixed point. + */ +void PQ_MatrixInversion(POWERQUAD_Type *base, uint32_t length, void *pData, void *pTmpData, void *pResult); + +/*! + * @brief Processing function for the matrix transpose. + * + * @param base POWERQUAD peripheral base address + * @param length rows and cols for matrix. LENGTH register configuration: + * LENGTH[23:16] = M2 cols + * LENGTH[15:8] = M1 cols + * LENGTH[7:0] = M1 rows + * This could be constructed using macro @ref POWERQUAD_MAKE_MATRIX_LEN. + * @param pData input matrix + * @param pResult array for the output data. + */ +void PQ_MatrixTranspose(POWERQUAD_Type *base, uint32_t length, void *pData, void *pResult); + +/*! + * @brief Processing function for the matrix scale. + * + * @param base POWERQUAD peripheral base address + * @param length rows and cols for matrix. LENGTH register configuration: + * LENGTH[23:16] = M2 cols + * LENGTH[15:8] = M1 cols + * LENGTH[7:0] = M1 rows + * This could be constructed using macro @ref POWERQUAD_MAKE_MATRIX_LEN. + * @param misc scaling parameters + * @param pData input matrix + * @param pResult array for the output data. + */ +void PQ_MatrixScale(POWERQUAD_Type *base, uint32_t length, float misc, void *pData, void *pResult); + +/* @} */ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @}*/ + +#endif /* _FSL_POWERQUAD_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_powerquad_basic.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_powerquad_basic.c new file mode 100644 index 000000000..a389b7bd0 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_powerquad_basic.c @@ -0,0 +1,126 @@ +/* + * Copyright 2018-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_powerquad.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.powerquad_basic" +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ +void PQ_GetDefaultConfig(pq_config_t *config) +{ + config->inputAFormat = kPQ_Float; + config->inputAPrescale = 0; + config->inputBFormat = kPQ_Float; + config->inputBPrescale = 0; + config->outputFormat = kPQ_Float; + config->outputPrescale = 0; + config->tmpFormat = kPQ_Float; + config->tmpPrescale = 0; + config->machineFormat = kPQ_Float; + config->tmpBase = (uint32_t *)0xE0000000; +} + +void PQ_SetConfig(POWERQUAD_Type *base, const pq_config_t *config) +{ + assert(config); + + base->TMPBASE = (uint32_t)config->tmpBase; + base->INAFORMAT = + ((uint32_t)config->inputAPrescale << 8U) | ((uint32_t)config->inputAFormat << 4U) | config->machineFormat; + base->INBFORMAT = + ((uint32_t)config->inputBPrescale << 8U) | ((uint32_t)config->inputBFormat << 4U) | config->machineFormat; + base->TMPFORMAT = + ((uint32_t)config->tmpPrescale << 8U) | ((uint32_t)config->tmpFormat << 4U) | config->machineFormat; + base->OUTFORMAT = + ((uint32_t)config->outputPrescale << 8U) | ((uint32_t)config->outputFormat << 4U) | config->machineFormat; +} + +void PQ_Init(POWERQUAD_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + CLOCK_EnableClock(kCLOCK_PowerQuad); +#endif +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) + RESET_PeripheralReset(kPOWERQUAD_RST_SHIFT_RSTn); +#endif + + /* Enable event used for WFE. */ + base->EVENTEN = POWERQUAD_EVENTEN_EVENT_OFLOW_MASK | POWERQUAD_EVENTEN_EVENT_NAN_MASK | + POWERQUAD_EVENTEN_EVENT_FIXED_MASK | POWERQUAD_EVENTEN_EVENT_UFLOW_MASK | + POWERQUAD_EVENTEN_EVENT_BERR_MASK | POWERQUAD_EVENTEN_EVENT_COMP_MASK; +} + +void PQ_Deinit(POWERQUAD_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + CLOCK_DisableClock(kCLOCK_PowerQuad); +#endif +} + +void PQ_SetFormat(POWERQUAD_Type *base, pq_computationengine_t engine, pq_format_t format) +{ + pq_config_t config; + + PQ_GetDefaultConfig(&config); + + /* 32-bit Float point */ + if (kPQ_Float == format) + { + config.inputAFormat = kPQ_Float; + config.inputAPrescale = 0; + config.inputBFormat = kPQ_Float; + config.inputBPrescale = 0; + config.outputFormat = kPQ_Float; + config.outputPrescale = 0; + config.tmpFormat = kPQ_Float; + config.tmpPrescale = 0; + } + /* 32-bit Fixed point */ + if (kPQ_32Bit == format) + { + config.inputAFormat = kPQ_32Bit; + config.inputAPrescale = 0; + config.inputBFormat = kPQ_32Bit; + config.inputBPrescale = 0; + config.outputFormat = kPQ_32Bit; + config.outputPrescale = 0; + config.tmpFormat = kPQ_Float; + config.tmpPrescale = 0; + } + /* 16-bit Fixed point */ + if (kPQ_16Bit == format) + { + config.inputAFormat = kPQ_16Bit; + config.inputAPrescale = 0; + config.inputBFormat = kPQ_16Bit; + config.inputBPrescale = 0; + config.outputFormat = kPQ_16Bit; + config.outputPrescale = 0; + config.tmpFormat = kPQ_Float; + config.tmpPrescale = 0; + } + + if (CP_FFT == engine) + { + config.machineFormat = kPQ_32Bit; + } + else + { + config.machineFormat = kPQ_Float; + } + + PQ_SetConfig(base, &config); +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_powerquad_cmsis.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_powerquad_cmsis.c new file mode 100644 index 000000000..6353347e0 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_powerquad_cmsis.c @@ -0,0 +1,1657 @@ +/* + * Copyright 2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_powerquad.h" +#include "fsl_powerquad_data.h" +#include "arm_math.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.powerquad_cmsis" +#endif + +#define PQ_SET_FIX32_CONFIG \ + POWERQUAD->OUTFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_32Bit << 4U) | kPQ_Float; \ + POWERQUAD->INAFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_32Bit << 4U) | kPQ_Float; \ + POWERQUAD->INBFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_32Bit << 4U) | kPQ_Float; \ + POWERQUAD->TMPFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_Float << 4U) | kPQ_Float; \ + POWERQUAD->TMPBASE = 0xE0000000 + +#define PQ_SET_FIX16_CONFIG \ + POWERQUAD->OUTFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_16Bit << 4U) | kPQ_Float; \ + POWERQUAD->INAFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_16Bit << 4U) | kPQ_Float; \ + POWERQUAD->INBFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_16Bit << 4U) | kPQ_Float; \ + POWERQUAD->TMPFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_Float << 4U) | kPQ_Float; \ + POWERQUAD->TMPBASE = 0xE0000000 + +#define PQ_SET_Q31_CONFIG \ + POWERQUAD->OUTFORMAT = ((uint32_t)(-31) << 8U) | ((uint32_t)kPQ_32Bit << 4U) | kPQ_Float; \ + POWERQUAD->INAFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_32Bit << 4U) | kPQ_Float; \ + POWERQUAD->INBFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_32Bit << 4U) | kPQ_Float; \ + POWERQUAD->TMPFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_Float << 4U) | kPQ_Float; \ + POWERQUAD->TMPBASE = 0xE0000000 + +#define PQ_SET_Q15_CONFIG \ + POWERQUAD->OUTFORMAT = ((uint32_t)(-15) << 8U) | ((uint32_t)kPQ_16Bit << 4U) | kPQ_Float; \ + POWERQUAD->INAFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_16Bit << 4U) | kPQ_Float; \ + POWERQUAD->INBFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_16Bit << 4U) | kPQ_Float; \ + POWERQUAD->TMPFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_Float << 4U) | kPQ_Float; \ + POWERQUAD->TMPBASE = 0xE0000000 + +#define PQ_SET_F32_CONFIG \ + POWERQUAD->OUTFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_Float << 4U) | kPQ_Float; \ + POWERQUAD->INAFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_Float << 4U) | kPQ_Float; \ + POWERQUAD->INBFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_Float << 4U) | kPQ_Float; \ + POWERQUAD->TMPFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_Float << 4U) | kPQ_Float; \ + POWERQUAD->TMPBASE = 0xE0000000 + +#define PQ_SET_FFT_Q31_CONFIG \ + POWERQUAD->OUTFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_32Bit << 4U) | kPQ_32Bit; \ + POWERQUAD->INAFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_32Bit << 4U) | kPQ_32Bit; \ + POWERQUAD->INBFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_32Bit << 4U) | kPQ_32Bit; \ + POWERQUAD->TMPFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_32Bit << 4U) | kPQ_32Bit; \ + POWERQUAD->TMPBASE = 0xE0000000 + +#define PQ_SET_FFT_Q15_CONFIG \ + POWERQUAD->OUTFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_16Bit << 4U) | kPQ_32Bit; \ + POWERQUAD->INAFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_16Bit << 4U) | kPQ_32Bit; \ + POWERQUAD->INBFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_16Bit << 4U) | kPQ_32Bit; \ + POWERQUAD->TMPFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_32Bit << 4U) | kPQ_32Bit; \ + POWERQUAD->TMPBASE = 0xE0000000 + +#define PQ_SET_MAT_FIX32_WORKAROUND_SCALE_CONFIG \ + POWERQUAD->OUTFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_Float << 4U) | kPQ_Float; \ + POWERQUAD->INAFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_32Bit << 4U) | kPQ_Float; \ + POWERQUAD->INBFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_32Bit << 4U) | kPQ_Float; \ + POWERQUAD->TMPFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_Float << 4U) | kPQ_Float; \ + POWERQUAD->TMPBASE = 0xE0000000 + +#define PQ_SET_MAT_FIX32_WORKAROUND_MULT_CONFIG \ + POWERQUAD->OUTFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_32Bit << 4U) | kPQ_Float; \ + POWERQUAD->INBFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_Float << 4U) | kPQ_Float; \ + POWERQUAD->TMPBASE = 0xE0000000 + +#define PQ_SET_MAT_FIX16_WORKAROUND_SCALE_CONFIG \ + POWERQUAD->OUTFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_Float << 4U) | kPQ_Float; \ + POWERQUAD->INAFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_16Bit << 4U) | kPQ_Float; \ + POWERQUAD->INBFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_16Bit << 4U) | kPQ_Float; \ + POWERQUAD->TMPFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_Float << 4U) | kPQ_Float; \ + POWERQUAD->TMPBASE = 0xE0000000 + +#define PQ_SET_MAT_FIX16_WORKAROUND_MULT_CONFIG \ + POWERQUAD->OUTFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_16Bit << 4U) | kPQ_Float; \ + POWERQUAD->INBFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_Float << 4U) | kPQ_Float; \ + POWERQUAD->TMPBASE = 0xE0000000 + +/******************************************************************************* + * Code + ******************************************************************************/ +static void _arm_fir_increment(void *pSrc, uint16_t srcLen, void *pTap, uint16_t tapLen, void *pDst, uint32_t offset) +{ + POWERQUAD->INABASE = (uint32_t)pSrc; + POWERQUAD->INBBASE = (uint32_t)pTap; + POWERQUAD->LENGTH = ((uint32_t)tapLen << 16U) + srcLen; + POWERQUAD->OUTBASE = (uint32_t)pDst; + POWERQUAD->MISC = offset; + POWERQUAD->CONTROL = (CP_FIR << 4) | PQ_FIR_INCREMENTAL; +} + +float32_t arm_cos_f32(float32_t x) +{ + float tmp; + + PQ_CosF32(&x, &tmp); + return tmp; +} + +q31_t arm_cos_q31(q31_t x) +{ + /* For PQ: input -1 to 1 means -pi to pi + * For CMSIS DSP: input 0 to 1 means pi to 2*pi */ + x *= 2; + return PQ_CosQ31(x); +} + +q15_t arm_cos_q15(q15_t x) +{ + /* For PQ: input -1 to 1 means -pi to pi + * For CMSIS DSP: input 0 to 1 means pi to 2*pi */ + x *= 2; + return PQ_CosQ15(x); +} + +float32_t arm_sin_f32(float32_t x) +{ + float tmp; + + PQ_SinF32(&x, &tmp); + return tmp; +} + +q31_t arm_sin_q31(q31_t x) +{ + /* For PQ: input -1 to 1 means -pi to pi + * For CMSIS DSP: input 0 to 1 means pi to 2*pi */ + x *= 2; + return PQ_SinQ31(x); +} + +q15_t arm_sin_q15(q15_t x) +{ + /* For PQ: input -1 to 1 means -pi to pi + * For CMSIS DSP: input 0 to 1 means pi to 2*pi */ + x *= 2; + return PQ_SinQ15(x); +} + +arm_status arm_sqrt_q31(q31_t in, q31_t *pOut) +{ + uint32_t cppre; + + /* If the input is a positive number then compute the signBits. */ + if (in > 0) + { + cppre = POWERQUAD->CPPRE; + POWERQUAD->CPPRE = POWERQUAD_CPPRE_CPPRE_IN(-31) | POWERQUAD_CPPRE_CPPRE_OUT(31); + *pOut = PQ_SqrtFixed(in); + POWERQUAD->CPPRE = cppre; + + return (ARM_MATH_SUCCESS); + } + /* If the number is a negative number then store zero as its square root value */ + else + { + *pOut = 0; + + return (ARM_MATH_ARGUMENT_ERROR); + } +} + +arm_status arm_sqrt_q15(q15_t in, q15_t *pOut) +{ + uint32_t cppre; + + /* If the input is a positive number then compute the signBits. */ + if (in > 0) + { + cppre = POWERQUAD->CPPRE; + POWERQUAD->CPPRE = POWERQUAD_CPPRE_CPPRE_IN(-15) | POWERQUAD_CPPRE_CPPRE_OUT(15); + *pOut = PQ_SqrtFixed(in); + POWERQUAD->CPPRE = cppre; + + return (ARM_MATH_SUCCESS); + } + /* If the number is a negative number then store zero as its square root value */ + else + { + *pOut = 0; + + return (ARM_MATH_ARGUMENT_ERROR); + } +} + +void arm_cfft_q31(const arm_cfft_instance_q31 *S, q31_t *p1, uint8_t ifftFlag, uint8_t bitReverseFlag) +{ + assert(bitReverseFlag == 1); + + q31_t *pIn = p1; + q31_t *pOut = p1; + uint32_t length = S->fftLen; + + PQ_SET_FFT_Q31_CONFIG; + + if (ifftFlag == 1U) + { + PQ_TransformIFFT(POWERQUAD, length, pIn, pOut); + } + else + { + PQ_TransformCFFT(POWERQUAD, length, pIn, pOut); + } + + PQ_WaitDone(POWERQUAD); +} + +void arm_cfft_q15(const arm_cfft_instance_q15 *S, q15_t *p1, uint8_t ifftFlag, uint8_t bitReverseFlag) +{ + assert(bitReverseFlag == 1); + + q15_t *pIn = p1; + q15_t *pOut = p1; + uint32_t length = S->fftLen; + + PQ_SET_FFT_Q15_CONFIG; + + if (ifftFlag == 1U) + { + PQ_TransformIFFT(POWERQUAD, length, pIn, pOut); + } + else + { + PQ_TransformCFFT(POWERQUAD, length, pIn, pOut); + } + + PQ_WaitDone(POWERQUAD); +} + +arm_status arm_rfft_init_q31(arm_rfft_instance_q31 *S, uint32_t fftLenReal, uint32_t ifftFlagR, uint32_t bitReverseFlag) +{ + /* Only supprt such mode. */ + assert(ifftFlagR == 0); + assert(bitReverseFlag == 1); + + /* Initialise the default arm status */ + arm_status status = ARM_MATH_SUCCESS; + + /* Initialize the Real FFT length */ + S->fftLenReal = (uint16_t)fftLenReal; + + /* Initialize the Flag for selection of RFFT or RIFFT */ + S->ifftFlagR = (uint8_t)ifftFlagR; + + /* Initialize the Flag for calculation Bit reversal or not */ + S->bitReverseFlagR = (uint8_t)bitReverseFlag; + + /* return the status of RFFT Init function */ + return (status); +} + +void arm_rfft_q31(const arm_rfft_instance_q31 *S, q31_t *pSrc, q31_t *pDst) +{ + uint32_t length = S->fftLenReal; + PQ_SET_FFT_Q31_CONFIG; + + /* Calculation of RFFT of input */ + PQ_TransformRFFT(POWERQUAD, length, pSrc, pDst); + + PQ_WaitDone(POWERQUAD); +} + +arm_status arm_rfft_init_q15(arm_rfft_instance_q15 *S, uint32_t fftLenReal, uint32_t ifftFlagR, uint32_t bitReverseFlag) +{ + /* Only supprt such mode. */ + assert(ifftFlagR == 0); + assert(bitReverseFlag == 1); + + /* Initialise the default arm status */ + arm_status status = ARM_MATH_SUCCESS; + + /* Initialize the Real FFT length */ + S->fftLenReal = (uint16_t)fftLenReal; + + /* Initialize the Flag for selection of RFFT or RIFFT */ + S->ifftFlagR = (uint8_t)ifftFlagR; + + /* Initialize the Flag for calculation Bit reversal or not */ + S->bitReverseFlagR = (uint8_t)bitReverseFlag; + + /* return the status of RFFT Init function */ + return (status); +} + +void arm_rfft_q15(const arm_rfft_instance_q15 *S, q15_t *pSrc, q15_t *pDst) +{ + uint32_t length = S->fftLenReal; + PQ_SET_FFT_Q15_CONFIG; + + /* Calculation of RFFT of input */ + PQ_TransformRFFT(POWERQUAD, length, pSrc, pDst); + + PQ_WaitDone(POWERQUAD); +} + +arm_status arm_dct4_init_q31(arm_dct4_instance_q31 *S, + arm_rfft_instance_q31 *S_RFFT, + arm_cfft_radix4_instance_q31 *S_CFFT, + uint16_t N, + uint16_t Nby2, + q31_t normalize) +{ + /* Initialize the DCT4 length */ + S->N = N; + + /* Initialize Real FFT Instance */ + S->pRfft = S_RFFT; + + switch (N) + { + /* Initialize the table modifier values */ + case 512U: + S->pTwiddle = dct512_twiddle; + S->pCosFactor = dct512_cosFactor; + break; + + case 256U: + S->pTwiddle = dct256_twiddle; + S->pCosFactor = dct256_cosFactor; + break; + + case 128U: + S->pTwiddle = dct128_twiddle; + S->pCosFactor = dct128_cosFactor; + break; + + case 64U: + S->pTwiddle = dct64_twiddle; + S->pCosFactor = dct64_cosFactor; + break; + + case 32U: + S->pTwiddle = dct32_twiddle; + S->pCosFactor = dct32_cosFactor; + break; + + case 16U: + S->pTwiddle = dct16_twiddle; + S->pCosFactor = dct16_cosFactor; + break; + + default: + return ARM_MATH_ARGUMENT_ERROR; + } + + /* Initialize the RFFT/RIFFT Function */ + arm_rfft_init_q31(S->pRfft, S->N, 0, 1); + + return ARM_MATH_SUCCESS; +} + +void arm_dct4_q31(const arm_dct4_instance_q31 *S, q31_t *pState, q31_t *pInlineBuffer) +{ + /* Calculate DCT-II for N-point input */ + uint16_t i; /* Loop counter */ + q31_t *weights; /* Pointer to the Weights table */ + q31_t *pOut; /* Temporary pointers for output buffer */ + q31_t *pS1, *pbuff; /* Temporary pointers for input buffer and pState buffer */ + q31_t in; /* Temporary variable */ + q31_t *cosFact; + uint32_t length; + uint8_t matRow; + uint8_t matCol; + uint8_t matLoop; + uint16_t lenPerMatLoop; + + /* + * Pre-processing involves multiplying input with cos factor, + * r(n) = 2 * u(n) * cos(pi*(2*n+1)/(4*N)) + * where, + * r(n) -- output of preprocessing + * u(n) -- input to preprocessing(actual Source buffer) + */ + + /* + * Use matrix production function for preprocessing. Matrix production + * supports 16x16 at the most, so the matrix row is set to 16. + */ + matRow = 16; + lenPerMatLoop = S->N >= 256 ? 256 : S->N; + matCol = lenPerMatLoop / 16; + matLoop = ((S->N - 1) >> 8) + 1; + cosFact = S->pCosFactor; + pbuff = pInlineBuffer; + + length = POWERQUAD_MAKE_MATRIX_LEN(matRow, matCol, matCol); + + while (matLoop--) + { + PQ_SET_MAT_FIX32_WORKAROUND_SCALE_CONFIG; + + /* cos factor is Q31, convert to float */ + PQ_MatrixScale(POWERQUAD, length, 2.0f / 2147483648.0f, cosFact, (void *)0xE0000000); + cosFact += lenPerMatLoop; + + PQ_WaitDone(POWERQUAD); + + /* Product. */ + PQ_SET_MAT_FIX32_WORKAROUND_MULT_CONFIG; + + PQ_MatrixProduct(POWERQUAD, length, pbuff, (void *)0xE0000000, pbuff); + + pbuff += lenPerMatLoop; + + PQ_WaitDone(POWERQUAD); + } + + PQ_SET_FFT_Q31_CONFIG; + + PQ_TransformRDCT(POWERQUAD, S->N, pInlineBuffer, pState); + + /* ARM calculation while PQ is running. */ + /* + * Use matrix production function for twiddle multiplication. + * Matrix production supports 16x16 at the most. The total elements are 2*N; + */ + lenPerMatLoop = S->N >= 128 ? 128 : S->N; + matCol = lenPerMatLoop / 8; + matLoop = ((S->N - 1) >> 7) + 1; + weights = S->pTwiddle; + pOut = pState; + + length = POWERQUAD_MAKE_MATRIX_LEN(matRow, matCol, matCol); + + PQ_WaitDone(POWERQUAD); + + while (matLoop--) + { + PQ_SET_MAT_FIX32_WORKAROUND_SCALE_CONFIG; + + /* Downscale by 1024 * 1024 * 16, because the twiddle are multiplied by 1024 * 1024 * 16. */ + PQ_MatrixScale(POWERQUAD, length, 1.0f / 16777216.0f, weights, (void *)0xE0000000); + weights += lenPerMatLoop * 2; + + PQ_WaitDone(POWERQUAD); + + /* Product. */ + PQ_SET_MAT_FIX32_WORKAROUND_MULT_CONFIG; + + PQ_MatrixProduct(POWERQUAD, length, pOut, (void *)0xE0000000, pOut); + + PQ_WaitDone(POWERQUAD); + + for (i = 0; i < lenPerMatLoop / 4; i++) + { + *pOut -= *(pOut + 1); + pOut += 2; + *pOut -= *(pOut + 1); + pOut += 2; + *pOut -= *(pOut + 1); + pOut += 2; + *pOut -= *(pOut + 1); + pOut += 2; + } + } + + /* ----------- Post-processing ---------- */ + /* DCT-IV can be obtained from DCT-II by the equation, + * Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0) + * Hence, Y4(0) = Y2(0)/2 */ + /* Getting only real part from the output and Converting to DCT-IV */ + + /* pbuff initialized to input buffer. */ + pbuff = pInlineBuffer; + + /* pS1 initialized to pState */ + pS1 = pState; + + /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2. Considering the DCT II normalize, here divided by sqrt(2).*/ + in = (q31_t)((float)*pS1 / 1.41421356237f); + *pbuff++ = in; + pS1 += 2; + + in = *pS1 - in; + *pbuff++ = in; + pS1 += 2; + + in = *pS1 - in; + *pbuff++ = in; + pS1 += 2; + + in = *pS1 - in; + *pbuff++ = in; + pS1 += 2; + + i = S->N / 4 - 1; + + while (i > 0U) + { + in = *pS1 - in; + *pbuff++ = in; + pS1 += 2; + + in = *pS1 - in; + *pbuff++ = in; + pS1 += 2; + + in = *pS1 - in; + *pbuff++ = in; + pS1 += 2; + + in = *pS1 - in; + *pbuff++ = in; + pS1 += 2; + + i--; + } +} + +arm_status arm_dct4_init_q15(arm_dct4_instance_q15 *S, + arm_rfft_instance_q15 *S_RFFT, + arm_cfft_radix4_instance_q15 *S_CFFT, + uint16_t N, + uint16_t Nby2, + q15_t normalize) +{ + /* Initialize the DCT4 length */ + S->N = N; + + /* Initialize Real FFT Instance */ + S->pRfft = S_RFFT; + + switch (N) + { + /* Initialize the table modifier values */ + case 512U: + S->pTwiddle = (q15_t *)dct512_twiddle; + S->pCosFactor = (q15_t *)dct512_cosFactor; + break; + + case 256U: + S->pTwiddle = (q15_t *)dct256_twiddle; + S->pCosFactor = (q15_t *)dct256_cosFactor; + break; + + case 128U: + S->pTwiddle = (q15_t *)dct128_twiddle; + S->pCosFactor = (q15_t *)dct128_cosFactor; + break; + + case 64U: + S->pTwiddle = (q15_t *)dct64_twiddle; + S->pCosFactor = (q15_t *)dct64_cosFactor; + break; + + case 32U: + S->pTwiddle = (q15_t *)dct32_twiddle; + S->pCosFactor = (q15_t *)dct32_cosFactor; + break; + + case 16U: + S->pTwiddle = (q15_t *)dct16_twiddle; + S->pCosFactor = (q15_t *)dct16_cosFactor; + break; + + default: + return ARM_MATH_ARGUMENT_ERROR; + } + + /* Initialize the RFFT/RIFFT Function */ + arm_rfft_init_q15(S->pRfft, S->N, 0, 1); + + /* return the status of DCT4 Init function */ + return ARM_MATH_SUCCESS; +} + +void arm_dct4_q15(const arm_dct4_instance_q15 *S, q15_t *pState, q15_t *pInlineBuffer) +{ + /* Calculate DCT-II for N-point input */ + uint16_t i; /* Loop counter */ + q15_t *weights; /* Pointer to the Weights table */ + q15_t *pOut; /* Temporary pointers for output buffer */ + q15_t *pS1, *pbuff; /* Temporary pointers for input buffer and pState buffer */ + q15_t in; /* Temporary variable */ + q15_t *cosFact; + uint32_t length; + uint8_t matRow; + uint8_t matCol; + uint8_t matLoop; + uint16_t lenPerMatLoop; + + /* + * Pre-processing involves multiplying input with cos factor, + * r(n) = 2 * u(n) * cos(pi*(2*n+1)/(4*N)) + * where, + * r(n) -- output of preprocessing + * u(n) -- input to preprocessing(actual Source buffer) + */ + + /* + * Use matrix production function for preprocessing. Matrix production + * supports 16x16 at the most, so the matrix row is set to 16. + */ + matRow = 16; + lenPerMatLoop = S->N >= 256 ? 256 : S->N; + matCol = lenPerMatLoop / 16; + matLoop = ((S->N - 1) >> 8) + 1; + cosFact = S->pCosFactor; + pbuff = pInlineBuffer; + + length = POWERQUAD_MAKE_MATRIX_LEN(matRow, matCol, 0); + + while (matLoop--) + { + PQ_SET_MAT_FIX32_WORKAROUND_SCALE_CONFIG; + + /* cos factor is Q31, convert to float */ + PQ_MatrixScale(POWERQUAD, length, 2.0f / 2147483648.0f, cosFact, (void *)0xE0000000); + cosFact += 2 * lenPerMatLoop; + + PQ_WaitDone(POWERQUAD); + + /* Product. */ + POWERQUAD->OUTFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_16Bit << 4U) | kPQ_Float; + POWERQUAD->INAFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_16Bit << 4U) | kPQ_Float; + POWERQUAD->INBFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_Float << 4U) | kPQ_Float; + POWERQUAD->TMPFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_Float << 4U) | kPQ_Float; + POWERQUAD->TMPBASE = 0xE0000000; + + PQ_MatrixProduct(POWERQUAD, length, pbuff, (void *)0xE0000000, pbuff); + + PQ_WaitDone(POWERQUAD); + + pbuff += lenPerMatLoop; + } + + PQ_SET_FFT_Q15_CONFIG; + + PQ_TransformRDCT(POWERQUAD, S->N, pInlineBuffer, pState); + + /* ARM calculation while PQ is running. */ + /* + * Use matrix production function for twiddle multiplication. + * Matrix production supports 16x16 at the most. The total elements are 2*N; + */ + lenPerMatLoop = S->N >= 128 ? 128 : S->N; + matCol = lenPerMatLoop / 8; + matLoop = ((S->N - 1) >> 7) + 1; + weights = S->pTwiddle; + pOut = pState; + + length = POWERQUAD_MAKE_MATRIX_LEN(matRow, matCol, matCol); + + PQ_WaitDone(POWERQUAD); + + while (matLoop--) + { + PQ_SET_MAT_FIX32_WORKAROUND_SCALE_CONFIG; + + /* Downscale by 1024 * 1024 * 16, because the twiddle are multiplied by 1024 * 1024 * 16. */ + PQ_MatrixScale(POWERQUAD, length, 1.0f / 16777216.0f, weights, (void *)0xE0000000); + weights += lenPerMatLoop * 2; + + PQ_WaitDone(POWERQUAD); + + /* Product. */ + POWERQUAD->OUTFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_16Bit << 4U) | kPQ_Float; + POWERQUAD->INAFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_16Bit << 4U) | kPQ_Float; + POWERQUAD->INBFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_Float << 4U) | kPQ_Float; + POWERQUAD->TMPFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_Float << 4U) | kPQ_Float; + POWERQUAD->TMPBASE = 0xE0000000; + + PQ_MatrixProduct(POWERQUAD, length, pOut, (void *)0xE0000000, pOut); + + PQ_WaitDone(POWERQUAD); + + for (i = 0; i < lenPerMatLoop / 4; i++) + { + *pOut -= *(pOut + 1); + pOut += 2; + *pOut -= *(pOut + 1); + pOut += 2; + *pOut -= *(pOut + 1); + pOut += 2; + *pOut -= *(pOut + 1); + pOut += 2; + } + } + + /* ----------- Post-processing ---------- */ + /* DCT-IV can be obtained from DCT-II by the equation, + * Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0) + * Hence, Y4(0) = Y2(0)/2 */ + /* Getting only real part from the output and Converting to DCT-IV */ + + /* pbuff initialized to input buffer. */ + pbuff = pInlineBuffer; + + /* pS1 initialized to pState */ + pS1 = pState; + + /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2. Considering the DCT II normalize, here divided by sqrt(2).*/ + in = (q15_t)((float)*pS1 / 1.41421356237f); + *pbuff++ = in; + pS1 += 2; + + in = *pS1 - in; + *pbuff++ = in; + pS1 += 2; + + in = *pS1 - in; + *pbuff++ = in; + pS1 += 2; + + in = *pS1 - in; + *pbuff++ = in; + pS1 += 2; + + i = S->N / 4 - 1; + + while (i > 0U) + { + in = *pS1 - in; + *pbuff++ = in; + pS1 += 2; + + in = *pS1 - in; + *pbuff++ = in; + pS1 += 2; + + in = *pS1 - in; + *pbuff++ = in; + pS1 += 2; + + in = *pS1 - in; + *pbuff++ = in; + pS1 += 2; + + i--; + } +} + +void arm_fir_init_f32( + arm_fir_instance_f32 *S, uint16_t numTaps, float32_t *pCoeffs, float32_t *pState, uint32_t blockSize) +{ + uint32_t i; + + /* + * CMSIS DSP API filter coefficients stored in time reversed order, but PQ + * uses the positive order. PQ does not use pState, so pState pState[1:numTaps] + * is used here to save the coefficients in positive order. At the same time, + * pState[0] is used to save the offset used for incremetal calculation. + * Because the length of pState is (numTaps + blockSize -1), to ensure enough space, + * the blockSize should be larger than 1. + */ + assert(blockSize > 1); + + S->numTaps = numTaps; + S->pCoeffs = pCoeffs; + S->pState = pState; + + for (i = 0; i < numTaps; i++) + { + pState[numTaps - i] = pCoeffs[i]; + } + + *(uint32_t *)pState = 0; +} + +void arm_fir_init_q31(arm_fir_instance_q31 *S, uint16_t numTaps, q31_t *pCoeffs, q31_t *pState, uint32_t blockSize) +{ + uint32_t i; + + /* + * CMSIS DSP API filter coefficients stored in time reversed order, but PQ + * uses the positive order. PQ does not use pState, so pState pState[1:numTaps] + * is used here to save the coefficients in positive order. At the same time, + * pState[0] is used to save the offset used for incremetal calculation. + * Because the length of pState is (numTaps + blockSize -1), to ensure enough space, + * the blockSize should be larger than 1. + */ + assert(blockSize > 1); + + S->numTaps = numTaps; + S->pCoeffs = pCoeffs; + S->pState = pState; + + for (i = 0; i < numTaps; i++) + { + pState[numTaps - i] = pCoeffs[i]; + } + + pState[0] = 0; +} + +arm_status arm_fir_init_q15( + arm_fir_instance_q15 *S, uint16_t numTaps, q15_t *pCoeffs, q15_t *pState, uint32_t blockSize) +{ + uint32_t i; + + /* + * CMSIS DSP API filter coefficients stored in time reversed order, but PQ + * uses the positive order. PQ does not use pState, so pState pState[2:numTaps] + * is used here to save the coefficients in positive order. At the same time, + * pState[0:1] is used to save the offset used for incremetal calculation. + * Because the length of pState is (numTaps + blockSize -1), to ensure enough space, + * the blockSize should be larger than 2. + */ + assert(blockSize > 2); + + S->numTaps = numTaps; + S->pCoeffs = pCoeffs; + S->pState = pState; + + for (i = 0; i < numTaps; i++) + { + pState[numTaps + 1 - i] = pCoeffs[i]; + } + + *(uint32_t *)pState = 0; + + return ARM_MATH_SUCCESS; +} + +void arm_fir_f32(const arm_fir_instance_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize) +{ + assert(S); + assert(pSrc); + assert(pDst); + + uint32_t curOffset; + PQ_SET_F32_CONFIG; + + curOffset = *(uint32_t *)(S->pState); + + if (curOffset == 0) + { + PQ_FIR(POWERQUAD, pSrc, blockSize, &(S->pState[1]), S->numTaps, pDst, PQ_FIR_FIR); + } + else + { + _arm_fir_increment(pSrc - curOffset, blockSize, &S->pState[1], S->numTaps, pDst - curOffset, curOffset); + } + + *(uint32_t *)(S->pState) = curOffset + blockSize; + + PQ_WaitDone(POWERQUAD); +} + +void arm_fir_q31(const arm_fir_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize) +{ + assert(S); + assert(pSrc); + assert(pDst); + + uint32_t curOffset; + PQ_SET_Q31_CONFIG; + + curOffset = *(uint32_t *)(S->pState); + + if (curOffset == 0) + { + PQ_FIR(POWERQUAD, pSrc, blockSize, &(S->pState[1]), S->numTaps, pDst, PQ_FIR_FIR); + } + else + { + _arm_fir_increment(pSrc - curOffset, blockSize, &S->pState[1], S->numTaps, pDst - curOffset, curOffset); + } + + *(uint32_t *)(S->pState) = curOffset + blockSize; + + PQ_WaitDone(POWERQUAD); +} + +void arm_fir_q15(const arm_fir_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize) +{ + assert(S); + assert(pSrc); + assert(pDst); + + uint32_t curOffset; + + PQ_SET_Q15_CONFIG; + + curOffset = *(uint32_t *)(S->pState); + + if (curOffset == 0) + { + PQ_FIR(POWERQUAD, pSrc, blockSize, &(S->pState[2]), S->numTaps, pDst, PQ_FIR_FIR); + } + else + { + _arm_fir_increment(pSrc - curOffset, blockSize, &S->pState[2], S->numTaps, pDst - curOffset, curOffset); + } + + *(uint32_t *)(S->pState) = curOffset + blockSize; + + PQ_WaitDone(POWERQUAD); +} + +void arm_conv_f32(float32_t *pSrcA, uint32_t srcALen, float32_t *pSrcB, uint32_t srcBLen, float32_t *pDst) +{ + assert(pSrcA); + assert(pSrcB); + assert(pDst); + + PQ_SET_F32_CONFIG; + + PQ_FIR(POWERQUAD, pSrcA, srcALen, pSrcB, srcBLen, pDst, PQ_FIR_CONVOLUTION); + PQ_WaitDone(POWERQUAD); +} + +void arm_conv_q31(q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst) +{ + assert(pSrcA); + assert(pSrcB); + assert(pDst); + + PQ_SET_Q31_CONFIG; + + PQ_FIR(POWERQUAD, pSrcA, srcALen, pSrcB, srcBLen, pDst, PQ_FIR_CONVOLUTION); + PQ_WaitDone(POWERQUAD); +} + +void arm_conv_q15(q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst) +{ + assert(pSrcA); + assert(pSrcB); + assert(pDst); + + PQ_SET_Q15_CONFIG; + + PQ_FIR(POWERQUAD, pSrcA, srcALen, pSrcB, srcBLen, pDst, PQ_FIR_CONVOLUTION); + PQ_WaitDone(POWERQUAD); +} + +void arm_correlate_f32(float32_t *pSrcA, uint32_t srcALen, float32_t *pSrcB, uint32_t srcBLen, float32_t *pDst) +{ + assert(pSrcA); + assert(pSrcB); + assert(pDst); + + PQ_SET_F32_CONFIG; + + PQ_FIR(POWERQUAD, pSrcA, srcALen, pSrcB, srcBLen, pDst, PQ_FIR_CORRELATION); + PQ_WaitDone(POWERQUAD); +} + +void arm_correlate_q31(q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst) +{ + assert(pSrcA); + assert(pSrcB); + assert(pDst); + + PQ_SET_Q31_CONFIG; + + PQ_FIR(POWERQUAD, pSrcA, srcALen, pSrcB, srcBLen, pDst, PQ_FIR_CORRELATION); + PQ_WaitDone(POWERQUAD); +} + +void arm_correlate_q15(q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst) +{ + assert(pSrcA); + assert(pSrcB); + assert(pDst); + + PQ_SET_Q15_CONFIG; + + PQ_FIR(POWERQUAD, pSrcA, srcALen, pSrcB, srcBLen, pDst, PQ_FIR_CORRELATION); + PQ_WaitDone(POWERQUAD); +} + +void arm_mat_init_f32(arm_matrix_instance_f32 *S, uint16_t nRows, uint16_t nColumns, float32_t *pData) +{ + /* Assign Number of Rows */ + S->numRows = nRows; + + /* Assign Number of Columns */ + S->numCols = nColumns; + + /* Assign Data pointer */ + S->pData = pData; +} + +void arm_mat_init_q31(arm_matrix_instance_q31 *S, uint16_t nRows, uint16_t nColumns, q31_t *pData) +{ + /* Assign Number of Rows */ + S->numRows = nRows; + + /* Assign Number of Columns */ + S->numCols = nColumns; + + /* Assign Data pointer */ + S->pData = pData; +} + +void arm_mat_init_q15(arm_matrix_instance_q15 *S, uint16_t nRows, uint16_t nColumns, q15_t *pData) +{ + /* Assign Number of Rows */ + S->numRows = nRows; + + /* Assign Number of Columns */ + S->numCols = nColumns; + + /* Assign Data pointer */ + S->pData = pData; +} + +arm_status arm_mat_add_f32(const arm_matrix_instance_f32 *pSrcA, + const arm_matrix_instance_f32 *pSrcB, + arm_matrix_instance_f32 *pDst) +{ + assert(pSrcA); + assert(pSrcB); + assert(pDst); + + arm_status status; + q31_t length; + +#ifdef ARM_MATH_MATRIX_CHECK + /* Check for matrix mismatch condition */ + if ((pSrcA->numRows != pSrcB->numRows) || (pSrcA->numCols != pSrcB->numCols) || (pSrcA->numRows != pDst->numRows) || + (pSrcA->numCols != pDst->numCols)) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif + { + PQ_SET_F32_CONFIG; + + length = (pSrcB->numCols << 16) | (pSrcA->numCols << 8) | (pSrcA->numRows << 0); + + PQ_MatrixAddition(POWERQUAD, length, pSrcA->pData, pSrcB->pData, pDst->pData); + + /* Wait for the completion */ + PQ_WaitDone(POWERQUAD); + + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return status; +} + +arm_status arm_mat_add_q31(const arm_matrix_instance_q31 *pSrcA, + const arm_matrix_instance_q31 *pSrcB, + arm_matrix_instance_q31 *pDst) +{ + assert(pSrcA); + assert(pSrcB); + assert(pDst); + + arm_status status; + q31_t length; + +#ifdef ARM_MATH_MATRIX_CHECK + /* Check for matrix mismatch condition */ + if ((pSrcA->numRows != pSrcB->numRows) || (pSrcA->numCols != pSrcB->numCols) || (pSrcA->numRows != pDst->numRows) || + (pSrcA->numCols != pDst->numCols)) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif + { + PQ_SET_FIX32_CONFIG; + + length = (pSrcB->numCols << 16) | (pSrcA->numCols << 8) | (pSrcA->numRows << 0); + + PQ_MatrixAddition(POWERQUAD, length, pSrcA->pData, pSrcB->pData, pDst->pData); + + /* Wait for the completion */ + PQ_WaitDone(POWERQUAD); + + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return status; +} + +arm_status arm_mat_add_q15(const arm_matrix_instance_q15 *pSrcA, + const arm_matrix_instance_q15 *pSrcB, + arm_matrix_instance_q15 *pDst) +{ + assert(pSrcA); + assert(pSrcB); + assert(pDst); + + arm_status status; + q31_t length; + +#ifdef ARM_MATH_MATRIX_CHECK + /* Check for matrix mismatch condition */ + if ((pSrcA->numRows != pSrcB->numRows) || (pSrcA->numCols != pSrcB->numCols) || (pSrcA->numRows != pDst->numRows) || + (pSrcA->numCols != pDst->numCols)) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif + { + PQ_SET_FIX16_CONFIG; + + length = (pSrcB->numCols << 16) | (pSrcA->numCols << 8) | (pSrcA->numRows << 0); + + PQ_MatrixAddition(POWERQUAD, length, pSrcA->pData, pSrcB->pData, pDst->pData); + + /* Wait for the completion */ + PQ_WaitDone(POWERQUAD); + + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return status; +} + +arm_status arm_mat_sub_f32(const arm_matrix_instance_f32 *pSrcA, + const arm_matrix_instance_f32 *pSrcB, + arm_matrix_instance_f32 *pDst) +{ + assert(pSrcA); + assert(pSrcB); + assert(pDst); + + arm_status status; + q31_t length; + +#ifdef ARM_MATH_MATRIX_CHECK + /* Check for matrix mismatch condition */ + if ((pSrcA->numRows != pSrcB->numRows) || (pSrcA->numCols != pSrcB->numCols) || (pSrcA->numRows != pDst->numRows) || + (pSrcA->numCols != pDst->numCols)) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif + { + PQ_SET_F32_CONFIG; + + length = (pSrcB->numCols << 16) | (pSrcA->numCols << 8) | (pSrcA->numRows << 0); + + PQ_MatrixSubtraction(POWERQUAD, length, pSrcA->pData, pSrcB->pData, pDst->pData); + + /* Wait for the completion */ + PQ_WaitDone(POWERQUAD); + + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return status; +} + +arm_status arm_mat_sub_q31(const arm_matrix_instance_q31 *pSrcA, + const arm_matrix_instance_q31 *pSrcB, + arm_matrix_instance_q31 *pDst) +{ + assert(pSrcA); + assert(pSrcB); + assert(pDst); + + arm_status status; + q31_t length; + +#ifdef ARM_MATH_MATRIX_CHECK + /* Check for matrix mismatch condition */ + if ((pSrcA->numRows != pSrcB->numRows) || (pSrcA->numCols != pSrcB->numCols) || (pSrcA->numRows != pDst->numRows) || + (pSrcA->numCols != pDst->numCols)) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif + { + PQ_SET_FIX32_CONFIG; + + length = (pSrcB->numCols << 16) | (pSrcA->numCols << 8) | (pSrcA->numRows << 0); + + PQ_MatrixSubtraction(POWERQUAD, length, pSrcA->pData, pSrcB->pData, pDst->pData); + + /* Wait for the completion */ + PQ_WaitDone(POWERQUAD); + + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return status; +} + +arm_status arm_mat_sub_q15(const arm_matrix_instance_q15 *pSrcA, + const arm_matrix_instance_q15 *pSrcB, + arm_matrix_instance_q15 *pDst) +{ + assert(pSrcA); + assert(pSrcB); + assert(pDst); + + arm_status status; + q31_t length; + +#ifdef ARM_MATH_MATRIX_CHECK + /* Check for matrix mismatch condition */ + if ((pSrcA->numRows != pSrcB->numRows) || (pSrcA->numCols != pSrcB->numCols) || (pSrcA->numRows != pDst->numRows) || + (pSrcA->numCols != pDst->numCols)) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif + { + PQ_SET_FIX16_CONFIG; + + length = (pSrcB->numCols << 16) | (pSrcA->numCols << 8) | (pSrcA->numRows << 0); + + PQ_MatrixSubtraction(POWERQUAD, length, pSrcA->pData, pSrcB->pData, pDst->pData); + + /* Wait for the completion */ + PQ_WaitDone(POWERQUAD); + + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return status; +} + +arm_status arm_mat_mult_f32(const arm_matrix_instance_f32 *pSrcA, + const arm_matrix_instance_f32 *pSrcB, + arm_matrix_instance_f32 *pDst) +{ + assert(pSrcA); + assert(pSrcB); + assert(pDst); + + arm_status status; + q31_t length; + +#ifdef ARM_MATH_MATRIX_CHECK + /* Check for matrix mismatch condition */ + if ((pSrcA->numRows != pSrcB->numRows) || (pSrcA->numCols != pSrcB->numCols) || (pSrcA->numRows != pDst->numRows) || + (pSrcA->numCols != pDst->numCols)) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif + { + PQ_SET_F32_CONFIG; + + length = (pSrcB->numCols << 16) | (pSrcA->numCols << 8) | (pSrcA->numRows << 0); + + PQ_MatrixMultiplication(POWERQUAD, length, pSrcA->pData, pSrcB->pData, pDst->pData); + + /* Wait for the completion */ + PQ_WaitDone(POWERQUAD); + + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return status; +} + +arm_status arm_mat_mult_q31(const arm_matrix_instance_q31 *pSrcA, + const arm_matrix_instance_q31 *pSrcB, + arm_matrix_instance_q31 *pDst) +{ + assert(pSrcA); + assert(pSrcB); + assert(pDst); + + arm_status status; + q31_t length; + + /* + * The output prescale does not supprt negative value due to hardware issue, + * workaround: + * 1. Downscale the matrix B and save the float output value to private memory. + * 2. Multiply the float matrix B in private memory with matrix A, output as Q31. + * Note: Put matrix B in private memory is faster. + */ + +#ifdef ARM_MATH_MATRIX_CHECK + /* Check for matrix mismatch condition */ + if ((pSrcA->numRows != pSrcB->numRows) || (pSrcA->numCols != pSrcB->numCols) || (pSrcA->numRows != pDst->numRows) || + (pSrcA->numCols != pDst->numCols)) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif + { + length = (pSrcB->numCols << 8) | (pSrcB->numRows << 0); + + PQ_SET_MAT_FIX32_WORKAROUND_SCALE_CONFIG; + + /* Downscale. */ + PQ_MatrixScale(POWERQUAD, length, 1.0f / 2147483648.0f, pSrcB->pData, (void *)0xE0000000); + + length = (pSrcB->numCols << 16) | (pSrcA->numCols << 8) | (pSrcA->numRows << 0); + + PQ_WaitDone(POWERQUAD); + + PQ_SET_MAT_FIX32_WORKAROUND_MULT_CONFIG; + + PQ_MatrixMultiplication(POWERQUAD, length, pSrcA->pData, (void *)0xE0000000, pDst->pData); + + /* Wait for the completion */ + PQ_WaitDone(POWERQUAD); + + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return status; +} + +arm_status arm_mat_mult_q15(const arm_matrix_instance_q15 *pSrcA, + const arm_matrix_instance_q15 *pSrcB, + arm_matrix_instance_q15 *pDst, + q15_t *pState) +{ + assert(pSrcA); + assert(pSrcB); + assert(pDst); + + arm_status status; + q31_t length; + +#ifdef ARM_MATH_MATRIX_CHECK + /* Check for matrix mismatch condition */ + if ((pSrcA->numRows != pSrcB->numRows) || (pSrcA->numCols != pSrcB->numCols) || (pSrcA->numRows != pDst->numRows) || + (pSrcA->numCols != pDst->numCols)) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif + { + length = (pSrcB->numCols << 8) | (pSrcB->numRows << 0); + + PQ_SET_MAT_FIX16_WORKAROUND_SCALE_CONFIG; + + /* Downscale. */ + PQ_MatrixScale(POWERQUAD, length, 1.0f / 32768.0f, pSrcB->pData, (void *)0xE0000000); + + length = (pSrcB->numCols << 16) | (pSrcA->numCols << 8) | (pSrcA->numRows << 0); + + PQ_WaitDone(POWERQUAD); + + PQ_SET_MAT_FIX16_WORKAROUND_MULT_CONFIG; + + PQ_MatrixMultiplication(POWERQUAD, length, pSrcA->pData, (void *)0xE0000000, pDst->pData); + + /* Wait for the completion */ + PQ_WaitDone(POWERQUAD); + + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return status; +} + +arm_status arm_mat_inverse_f32(const arm_matrix_instance_f32 *pSrc, arm_matrix_instance_f32 *pDst) +{ + assert(pSrc); + assert(pDst); + + arm_status status; + q31_t length; + float tmp[1024]; + +#ifdef ARM_MATH_MATRIX_CHECK + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pSrc->numCols) || (pDst->numRows != pDst->numCols) || (pSrc->numRows != pDst->numRows)) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif + { + PQ_SET_F32_CONFIG; + + length = (pSrc->numRows << 16) | (pSrc->numRows << 8) | (pSrc->numRows << 0); + + PQ_MatrixInversion(POWERQUAD, length, pSrc->pData, tmp, pDst->pData); + + /* Wait for the completion */ + PQ_WaitDone(POWERQUAD); + + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return status; +} + +arm_status arm_mat_trans_f32(const arm_matrix_instance_f32 *pSrc, arm_matrix_instance_f32 *pDst) +{ + assert(pSrc); + assert(pDst); + + arm_status status; + q31_t length; + +#ifdef ARM_MATH_MATRIX_CHECK + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pSrc->numCols) || (pDst->numRows != pDst->numCols) || (pSrc->numRows != pDst->numRows)) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif + { + length = (pSrc->numCols << 8) | (pSrc->numRows << 0); + + PQ_SetFormat(POWERQUAD, kPQ_CP_MTX, kPQ_Float); + + PQ_MatrixTranspose(POWERQUAD, length, pSrc->pData, pDst->pData); + + /* Wait for the completion */ + PQ_WaitDone(POWERQUAD); + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return status; +} + +arm_status arm_mat_trans_q31(const arm_matrix_instance_q31 *pSrc, arm_matrix_instance_q31 *pDst) +{ + assert(pSrc); + assert(pDst); + + arm_status status; + q31_t length; + +#ifdef ARM_MATH_MATRIX_CHECK + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pSrc->numCols) || (pDst->numRows != pDst->numCols) || (pSrc->numRows != pDst->numRows)) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif + { + PQ_SET_FIX32_CONFIG; + + length = (pSrc->numCols << 8) | (pSrc->numRows << 0); + + PQ_MatrixTranspose(POWERQUAD, length, pSrc->pData, pDst->pData); + + /* Wait for the completion */ + PQ_WaitDone(POWERQUAD); + + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return status; +} + +arm_status arm_mat_trans_q15(const arm_matrix_instance_q15 *pSrc, arm_matrix_instance_q15 *pDst) +{ + assert(pSrc); + assert(pDst); + + arm_status status; + q31_t length; + +#ifdef ARM_MATH_MATRIX_CHECK + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pSrc->numCols) || (pDst->numRows != pDst->numCols) || (pSrc->numRows != pDst->numRows)) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif + { + PQ_SET_FIX16_CONFIG; + + length = (pSrc->numCols << 8) | (pSrc->numRows << 0); + + PQ_MatrixTranspose(POWERQUAD, length, pSrc->pData, pDst->pData); + + /* Wait for the completion */ + PQ_WaitDone(POWERQUAD); + + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return status; +} + +arm_status arm_mat_scale_f32(const arm_matrix_instance_f32 *pSrc, float32_t scale, arm_matrix_instance_f32 *pDst) +{ + assert(pSrc); + assert(pDst); + + arm_status status; + q31_t length; + +#ifdef ARM_MATH_MATRIX_CHECK + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pSrc->numCols) || (pDst->numRows != pDst->numCols) || (pSrc->numRows != pDst->numRows)) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif + { + PQ_SET_F32_CONFIG; + + length = (pSrc->numCols << 8) | (pSrc->numRows << 0); + + PQ_MatrixScale(POWERQUAD, length, scale, pSrc->pData, pDst->pData); + + /* Wait for the completion */ + PQ_WaitDone(POWERQUAD); + + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return status; +} + +arm_status arm_mat_scale_q31(const arm_matrix_instance_q31 *pSrc, + q31_t scale, + int32_t shift, + arm_matrix_instance_q31 *pDst) +{ + assert(pSrc); + assert(pDst); + + arm_status status; + q31_t length; + float scaleFloat; + + pq_config_t config = { + kPQ_32Bit, /* inputAFormat */ + 0, /* inputAPrescale */ + kPQ_32Bit, /* inputBFormat */ + 0, /* inputBPrescale */ + kPQ_32Bit, /* outputFormat */ + (int8_t)shift, /* outputPrescale */ + kPQ_Float, /* tmpFormat */ + 0, /* tmpPrescale */ + kPQ_Float, /* machineFormat */ + (uint32_t *)0xe0000000, /* tmpBase */ + }; + +#ifdef ARM_MATH_MATRIX_CHECK + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pSrc->numCols) || (pDst->numRows != pDst->numCols) || (pSrc->numRows != pDst->numRows)) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif + { + length = (pSrc->numCols << 8) | (pSrc->numRows << 0); + + scaleFloat = PQ_Q31_2_FLOAT(scale); + + PQ_SetConfig(POWERQUAD, &config); + + PQ_MatrixScale(POWERQUAD, length, scaleFloat, pSrc->pData, pDst->pData); + + /* Wait for the completion */ + PQ_WaitDone(POWERQUAD); + + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return status; +} + +arm_status arm_mat_scale_q15(const arm_matrix_instance_q15 *pSrc, + q15_t scale, + int32_t shift, + arm_matrix_instance_q15 *pDst) +{ + assert(pSrc); + assert(pDst); + + arm_status status; + q31_t length; + float scaleFloat; + + pq_config_t config = { + kPQ_16Bit, /* inputAFormat */ + 0, /* inputAPrescale */ + kPQ_16Bit, /* inputBFormat */ + 0, /* inputBPrescale */ + kPQ_16Bit, /* outputFormat */ + (int8_t)shift, /* outputPrescale */ + kPQ_Float, /* tmpFormat */ + 0, /* tmpPrescale */ + kPQ_Float, /* machineFormat */ + (uint32_t *)0xe0000000, /* tmpBase */ + }; + +#ifdef ARM_MATH_MATRIX_CHECK + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pSrc->numCols) || (pDst->numRows != pDst->numCols) || (pSrc->numRows != pDst->numRows)) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif + { + length = (pSrc->numCols << 8) | (pSrc->numRows << 0); + + scaleFloat = PQ_Q15_2_FLOAT(scale); + + PQ_SetConfig(POWERQUAD, &config); + + PQ_MatrixScale(POWERQUAD, length, scaleFloat, pSrc->pData, pDst->pData); + + /* Wait for the completion */ + PQ_WaitDone(POWERQUAD); + + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return status; +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_powerquad_data.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_powerquad_data.c new file mode 100644 index 000000000..9cee85b24 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_powerquad_data.c @@ -0,0 +1,584 @@ +/* + * Copyright 2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.powerquad" +#endif + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +/*! + * @brief MATLAB script for calculating twiddle factor table for DCT is below,this gives phasor for FFTs twiddle at end + * of DCT, + * note that y is raw, scaled y is for fixed point multiplication. + * + * N=32; + * n=0; + * while(n + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +extern int32_t dct16_twiddle[32]; +extern int32_t dct32_twiddle[64]; +extern int32_t dct64_twiddle[128]; +extern int32_t dct128_twiddle[256]; +extern int32_t dct256_twiddle[512]; +extern int32_t dct512_twiddle[1024]; +extern int32_t idct16_twiddle[32]; +extern int32_t idct32_twiddle[64]; +extern int32_t idct64_twiddle[128]; +extern int32_t idct128_twiddle[256]; +extern int32_t idct256_twiddle[512]; +extern int32_t idct512_twiddle[1024]; +extern int32_t dct16_cosFactor[32]; +extern int32_t dct32_cosFactor[64]; +extern int32_t dct64_cosFactor[128]; +extern int32_t dct128_cosFactor[256]; +extern int32_t dct256_cosFactor[512]; +extern int32_t dct512_cosFactor[1024]; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +#endif /* _FSL_POWERQUAD_DATA_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_powerquad_filter.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_powerquad_filter.c new file mode 100644 index 000000000..fe5688d0f --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_powerquad_filter.c @@ -0,0 +1,413 @@ +/* + * Copyright 2018-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_powerquad.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.powerquad_filter" +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ +void PQ_VectorBiqaudDf2F32(float *pSrc, float *pDst, int32_t length) +{ + int32_t remainderBy8 = length % 8; + + if (remainderBy8) + { + length -= remainderBy8; + while (remainderBy8--) + { + _pq_biquad0(*(int32_t *)pSrc++); + *(int32_t *)pDst++ = _pq_readAdd0(); + } + } + + if (length) + { + PQ_StartVector(pSrc, pDst, length); + PQ_Vector8BiquadDf2F32(); + PQ_EndVector(); + } +} + +void PQ_VectorBiqaudDf2Fixed32(int32_t *pSrc, int32_t *pDst, int32_t length) +{ + int32_t remainderBy8 = length % 8; + + if (remainderBy8) + { + length -= remainderBy8; + while (remainderBy8--) + { + _pq_biquad0_fx(*pSrc++); + *pDst++ = _pq_readAdd0_fx(); + } + } + + if (length) + { + PQ_StartVector(pSrc, pDst, length); + PQ_Vector8BiquadDf2Fixed32(); + PQ_EndVector(); + } +} + +void PQ_VectorBiqaudDf2Fixed16(int16_t *pSrc, int16_t *pDst, int32_t length) +{ + int32_t remainderBy8 = length % 8; + + if (remainderBy8) + { + length -= remainderBy8; + while (remainderBy8--) + { + _pq_biquad0_fx(*pSrc++); + *pDst++ = _pq_readAdd0_fx(); + } + } + + if (length) + { + PQ_StartVectorFixed16(pSrc, pDst, length); + PQ_Vector8BiquadDf2Fixed16(); + PQ_EndVector(); + } +} + +void PQ_VectorBiqaudCascadeDf2F32(float *pSrc, float *pDst, int32_t length) +{ + int32_t remainderBy8 = length % 8; + + if (remainderBy8) + { + length -= remainderBy8; + + PQ_Biquad1F32(&pSrc[0], &pDst[0]); + + for (int i = 1; i < remainderBy8; i++) + { + _pq_biquad0(*(int32_t *)&pSrc[i - 1]); + _pq_biquad1(*(int32_t *)&pSrc[i]); + *(int32_t *)&pDst[i - 1] = _pq_readAdd0(); + *(int32_t *)&pDst[i] = _pq_readAdd1(); + } + + PQ_BiquadF32(&pSrc[remainderBy8 - 1], &pDst[remainderBy8 - 1]); + } + + if (length) + { + PQ_StartVector(&pSrc[remainderBy8], &pDst[remainderBy8], length); + PQ_Vector8BiqaudDf2CascadeF32(); + PQ_EndVector(); + } +} + +void PQ_VectorBiqaudCascadeDf2Fixed32(int32_t *pSrc, int32_t *pDst, int32_t length) +{ + int32_t remainderBy8 = length % 8; + + if (remainderBy8) + { + length -= remainderBy8; + + _pq_biquad1_fx(pSrc[0]); + pDst[0] = _pq_readAdd1_fx(); + + for (int i = 1; i < remainderBy8; i++) + { + _pq_biquad0_fx(pSrc[i - 1]); + _pq_biquad1_fx(pSrc[i]); + pDst[i - 1] = _pq_readAdd0_fx(); + pDst[i] = _pq_readAdd1_fx(); + } + + _pq_biquad0_fx(pSrc[remainderBy8 - 1]); + pDst[remainderBy8 - 1] = _pq_readAdd0_fx(); + } + + if (length) + { + PQ_StartVector(&pSrc[remainderBy8], &pDst[remainderBy8], length); + PQ_Vector8BiqaudDf2CascadeFixed32(); + PQ_EndVector(); + } +} + +void PQ_VectorBiqaudCascadeDf2Fixed16(int16_t *pSrc, int16_t *pDst, int32_t length) +{ + int32_t remainderBy8 = length % 8; + + if (remainderBy8) + { + length -= remainderBy8; + + _pq_biquad1_fx(pSrc[0]); + pDst[0] = _pq_readAdd1_fx(); + + for (int i = 1; i < remainderBy8; i++) + { + _pq_biquad0_fx(pSrc[i - 1]); + _pq_biquad1_fx(pSrc[i]); + pDst[i - 1] = _pq_readAdd0_fx(); + pDst[i] = _pq_readAdd1_fx(); + } + + _pq_biquad0_fx(pSrc[remainderBy8 - 1]); + pDst[remainderBy8 - 1] = _pq_readAdd0_fx(); + } + + if (length) + { + PQ_StartVectorFixed16(&pSrc[remainderBy8], &pDst[remainderBy8], length); + PQ_Vector8BiqaudDf2CascadeFixed16(); + PQ_EndVector(); + } +} + +void PQ_BiquadBackUpInternalState(POWERQUAD_Type *base, int32_t biquad_num, pq_biquad_state_t *state) +{ + pq_float_t v_n_1; + pq_float_t v_n; + +#if defined(__GNUC__) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wstrict-aliasing" +#endif + if (0 == biquad_num) + { + v_n_1.integerX = base->GPREG[0]; + v_n.integerX = base->GPREG[1]; + + state->param.v_n_1 = v_n_1.floatX; + state->param.v_n = v_n.floatX; + state->compreg = base->COMPREG[1]; + } + else + { + v_n_1.integerX = base->GPREG[8]; + v_n.integerX = base->GPREG[9]; + + state->param.v_n_1 = v_n_1.floatX; + state->param.v_n = v_n.floatX; + state->compreg = base->COMPREG[3]; + } +#if defined(__GNUC__) +#pragma GCC diagnostic pop +#endif +} + +void PQ_BiquadRestoreInternalState(POWERQUAD_Type *base, int32_t biquad_num, pq_biquad_state_t *state) +{ + pq_float_t v_n_1; + pq_float_t v_n; + pq_float_t a_1; + pq_float_t a_2; + pq_float_t b_0; + pq_float_t b_1; + pq_float_t b_2; + + if (0 == biquad_num) + { + v_n_1.floatX = state->param.v_n_1; + v_n.floatX = state->param.v_n; + a_1.floatX = state->param.a_1; + a_2.floatX = state->param.a_2; + b_0.floatX = state->param.b_0; + b_1.floatX = state->param.b_1; + b_2.floatX = state->param.b_2; + + base->GPREG[0] = v_n_1.integerX; + base->GPREG[1] = v_n.integerX; + base->GPREG[2] = a_1.integerX; + base->GPREG[3] = a_2.integerX; + base->GPREG[4] = b_0.integerX; + base->GPREG[5] = b_1.integerX; + base->GPREG[6] = b_2.integerX; + base->COMPREG[1] = state->compreg; + } + else + { + v_n_1.floatX = state->param.v_n_1; + v_n.floatX = state->param.v_n; + a_1.floatX = state->param.a_1; + a_2.floatX = state->param.a_2; + b_0.floatX = state->param.b_0; + b_1.floatX = state->param.b_1; + b_2.floatX = state->param.b_2; + + base->GPREG[8] = v_n_1.integerX; + base->GPREG[9] = v_n.integerX; + base->GPREG[10] = a_1.integerX; + base->GPREG[11] = a_2.integerX; + base->GPREG[12] = b_0.integerX; + base->GPREG[13] = b_1.integerX; + base->GPREG[14] = b_2.integerX; + base->COMPREG[3] = state->compreg; + } +} + +void PQ_FIR( + POWERQUAD_Type *base, void *pAData, int32_t ALength, void *pBData, int32_t BLength, void *pResult, uint32_t opType) +{ + assert(pAData); + assert(pBData); + assert(pResult); + + base->INABASE = (uint32_t)pAData; + base->INBBASE = (uint32_t)pBData; + base->LENGTH = ((uint32_t)BLength << 16U) + (uint32_t)ALength; + base->OUTBASE = (uint32_t)pResult; + base->CONTROL = (CP_FIR << 4U) | opType; +} + +void PQ_FIRIncrement(POWERQUAD_Type *base, int32_t ALength, int32_t BLength, int32_t xOffset) +{ + base->MISC = xOffset; + base->LENGTH = ((uint32_t)BLength << 16) + (uint32_t)ALength; + base->CONTROL = (CP_FIR << 4) | PQ_FIR_INCREMENTAL; +} + +void PQ_BiquadCascadeDf2Init(pq_biquad_cascade_df2_instance *S, uint8_t numStages, pq_biquad_state_t *pState) +{ + S->numStages = numStages; + S->pState = pState; +} + +void PQ_BiquadCascadeDf2F32(const pq_biquad_cascade_df2_instance *S, float *pSrc, float *pDst, uint32_t blockSize) +{ + uint32_t stage = S->numStages; + pq_biquad_state_t *states = S->pState; + + if (pDst != pSrc) + { + memcpy(pDst, pSrc, 4 * blockSize); + } + + if (stage % 2 != 0) + { + PQ_BiquadRestoreInternalState(POWERQUAD, 0, states); + + PQ_VectorBiqaudDf2F32(pSrc, pDst, blockSize); + + PQ_BiquadBackUpInternalState(POWERQUAD, 0, states); + + states++; + stage--; + } + + do + { + PQ_BiquadRestoreInternalState(POWERQUAD, 1, states); + states++; + PQ_BiquadRestoreInternalState(POWERQUAD, 0, states); + + PQ_VectorBiqaudCascadeDf2F32(pDst, pDst, blockSize); + + states--; + PQ_BiquadBackUpInternalState(POWERQUAD, 1, states); + states++; + PQ_BiquadBackUpInternalState(POWERQUAD, 0, states); + + states++; + stage -= 2U; + + } while (stage > 0U); +} + +void PQ_BiquadCascadeDf2Fixed32(const pq_biquad_cascade_df2_instance *S, + int32_t *pSrc, + int32_t *pDst, + uint32_t blockSize) +{ + uint32_t stage = S->numStages; + pq_biquad_state_t *states = S->pState; + + if (pDst != pSrc) + { + memcpy(pDst, pSrc, 4 * blockSize); + } + + if (stage % 2 != 0) + { + PQ_BiquadRestoreInternalState(POWERQUAD, 0, states); + + PQ_VectorBiqaudDf2Fixed32(pSrc, pDst, blockSize); + + PQ_BiquadBackUpInternalState(POWERQUAD, 0, states); + + states++; + stage--; + } + + do + { + PQ_BiquadRestoreInternalState(POWERQUAD, 0, states); + states++; + PQ_BiquadRestoreInternalState(POWERQUAD, 1, states); + + PQ_VectorBiqaudCascadeDf2Fixed32(pDst, pDst, blockSize); + + states--; + PQ_BiquadBackUpInternalState(POWERQUAD, 0, states); + states++; + PQ_BiquadBackUpInternalState(POWERQUAD, 1, states); + + states++; + stage -= 2U; + } while (stage > 0U); +} + +void PQ_BiquadCascadeDf2Fixed16(const pq_biquad_cascade_df2_instance *S, + int16_t *pSrc, + int16_t *pDst, + uint32_t blockSize) +{ + uint32_t stage = S->numStages; + pq_biquad_state_t *states = S->pState; + + if (pDst != pSrc) + { + memcpy(pDst, pSrc, 2 * blockSize); + } + + if (stage % 2 != 0) + { + PQ_BiquadRestoreInternalState(POWERQUAD, 0, states); + + PQ_VectorBiqaudDf2Fixed16(pSrc, pDst, blockSize); + + PQ_BiquadBackUpInternalState(POWERQUAD, 0, states); + + states++; + stage--; + } + + do + { + PQ_BiquadRestoreInternalState(POWERQUAD, 0, states); + states++; + PQ_BiquadRestoreInternalState(POWERQUAD, 1, states); + + PQ_VectorBiqaudCascadeDf2Fixed16(pDst, pDst, blockSize); + + states--; + PQ_BiquadBackUpInternalState(POWERQUAD, 0, states); + states++; + PQ_BiquadBackUpInternalState(POWERQUAD, 1, states); + + states++; + stage -= 2U; + } while (stage > 0U); +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_powerquad_math.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_powerquad_math.c new file mode 100644 index 000000000..78c4a836a --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_powerquad_math.c @@ -0,0 +1,864 @@ +/* + * Copyright 2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_powerquad.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.powerquad_math" +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ +void PQ_VectorLnF32(float *pSrc, float *pDst, int32_t length) +{ + int32_t remainderBy8 = length % 8; + + if (remainderBy8) + { + length -= remainderBy8; + while (remainderBy8--) + { + _pq_ln0(*(int32_t *)pSrc++); + *(int32_t *)pDst++ = _pq_readAdd0(); + } + } + + if (length) + { + PQ_StartVector(pSrc, pDst, length); + PQ_Vector8F32(PQ_LN, 1, PQ_TRANS); + PQ_EndVector(); + } +} + +void PQ_VectorInvF32(float *pSrc, float *pDst, int32_t length) +{ + int32_t remainderBy8 = length % 8; + + if (remainderBy8) + { + length -= remainderBy8; + while (remainderBy8--) + { + _pq_inv0(*(int32_t *)pSrc++); + *(int32_t *)pDst++ = _pq_readMult0(); + } + } + + if (length) + { + PQ_StartVector(pSrc, pDst, length); + PQ_Vector8F32(PQ_INV, 0, PQ_TRANS); + PQ_EndVector(); + } +} + +void PQ_VectorSqrtF32(float *pSrc, float *pDst, int32_t length) +{ + int32_t remainderBy8 = length % 8; + + if (remainderBy8) + { + length -= remainderBy8; + while (remainderBy8--) + { + _pq_sqrt0(*(int32_t *)pSrc++); + *(int32_t *)pDst++ = _pq_readMult0(); + } + } + + if (length) + { + PQ_StartVector(pSrc, pDst, length); + PQ_Vector8F32(PQ_SQRT, 0, PQ_TRANS); + PQ_EndVector(); + } +} + +void PQ_VectorInvSqrtF32(float *pSrc, float *pDst, int32_t length) +{ + int32_t remainderBy8 = length % 8; + + if (remainderBy8) + { + length -= remainderBy8; + while (remainderBy8--) + { + _pq_invsqrt0(*(int32_t *)pSrc++); + *(int32_t *)pDst++ = _pq_readMult0(); + } + } + + if (length) + { + PQ_StartVector(pSrc, pDst, length); + PQ_Vector8F32(PQ_INVSQRT, 0, PQ_TRANS); + PQ_EndVector(); + } +} + +void PQ_VectorEtoxF32(float *pSrc, float *pDst, int32_t length) +{ + int32_t remainderBy8 = length % 8; + + if (remainderBy8) + { + length -= remainderBy8; + while (remainderBy8--) + { + _pq_etox0(*(int32_t *)pSrc++); + *(int32_t *)pDst++ = _pq_readMult0(); + } + } + + if (length) + { + PQ_StartVector(pSrc, pDst, length); + PQ_Vector8F32(PQ_ETOX, 0, PQ_TRANS); + PQ_EndVector(); + } +} + +void PQ_VectorEtonxF32(float *pSrc, float *pDst, int32_t length) +{ + int32_t remainderBy8 = length % 8; + + if (remainderBy8) + { + length -= remainderBy8; + while (remainderBy8--) + { + _pq_etonx0(*(int32_t *)pSrc++); + *(int32_t *)pDst++ = _pq_readMult0(); + } + } + + if (length) + { + PQ_StartVector(pSrc, pDst, length); + PQ_Vector8F32(PQ_ETONX, 0, PQ_TRANS); + PQ_EndVector(); + } +} + +void PQ_VectorSinF32(float *pSrc, float *pDst, int32_t length) +{ + int32_t remainderBy8 = length % 8; + + if (remainderBy8) + { + length -= remainderBy8; + while (remainderBy8--) + { + _pq_sin0(*(int32_t *)pSrc++); + *(int32_t *)pDst++ = _pq_readAdd0(); + } + } + + if (length) + { + PQ_StartVector(pSrc, pDst, length); + PQ_Vector8F32(PQ_SIN, 1, PQ_TRIG); + PQ_EndVector(); + } +} + +void PQ_VectorCosF32(float *pSrc, float *pDst, int32_t length) +{ + int32_t remainderBy8 = length % 8; + + if (remainderBy8) + { + length -= remainderBy8; + while (remainderBy8--) + { + _pq_cos0(*(int32_t *)pSrc++); + *(int32_t *)pDst++ = _pq_readAdd0(); + } + } + + if (length) + { + PQ_StartVector(pSrc, pDst, length); + PQ_Vector8F32(PQ_COS, 1, PQ_TRIG); + PQ_EndVector(); + } +} + +void PQ_VectorLnFixed32(int32_t *pSrc, int32_t *pDst, int32_t length) +{ + int32_t remainderBy8 = length % 8; + + if (remainderBy8) + { + length -= remainderBy8; + while (remainderBy8--) + { + _pq_ln_fx0(*pSrc++); + *pDst++ = _pq_readAdd0_fx(); + } + } + + if (length) + { + PQ_StartVector(pSrc, pDst, length); + PQ_Vector8Fixed32(PQ_LN, 1, PQ_TRANS_FIXED); + PQ_EndVector(); + } +} + +void PQ_VectorInvFixed32(int32_t *pSrc, int32_t *pDst, int32_t length) +{ + int32_t remainderBy8 = length % 8; + + if (remainderBy8) + { + length -= remainderBy8; + while (remainderBy8--) + { + _pq_inv_fx0(*pSrc++); + *pDst++ = _pq_readMult0_fx(); + } + } + + if (length) + { + PQ_StartVector(pSrc, pDst, length); + PQ_Vector8Fixed32(PQ_INV, 0, PQ_TRANS_FIXED); + PQ_EndVector(); + } +} + +void PQ_VectorSqrtFixed32(int32_t *pSrc, int32_t *pDst, int32_t length) +{ + int32_t remainderBy8 = length % 8; + + if (remainderBy8) + { + length -= remainderBy8; + while (remainderBy8--) + { + _pq_sqrt_fx0(*pSrc++); + *pDst++ = _pq_readMult0_fx(); + } + } + + if (length) + { + PQ_StartVector(pSrc, pDst, length); + PQ_Vector8Fixed32(PQ_SQRT, 0, PQ_TRANS_FIXED); + PQ_EndVector(); + } +} + +void PQ_VectorInvSqrtFixed32(int32_t *pSrc, int32_t *pDst, int32_t length) +{ + int32_t remainderBy8 = length % 8; + + if (remainderBy8) + { + length -= remainderBy8; + while (remainderBy8--) + { + _pq_invsqrt_fx0(*pSrc++); + *pDst++ = _pq_readMult0_fx(); + } + } + + if (length) + { + PQ_StartVector(pSrc, pDst, length); + PQ_Vector8Fixed32(PQ_INVSQRT, 0, PQ_TRANS_FIXED); + PQ_EndVector(); + } +} + +void PQ_VectorEtoxFixed32(int32_t *pSrc, int32_t *pDst, int32_t length) +{ + int32_t remainderBy8 = length % 8; + + if (remainderBy8) + { + length -= remainderBy8; + while (remainderBy8--) + { + _pq_etox_fx0(*pSrc++); + *pDst++ = _pq_readMult0_fx(); + } + } + + if (length) + { + PQ_StartVector(pSrc, pDst, length); + PQ_Vector8Fixed32(PQ_ETOX, 0, PQ_TRANS_FIXED); + PQ_EndVector(); + } +} + +void PQ_VectorEtonxFixed32(int32_t *pSrc, int32_t *pDst, int32_t length) +{ + int32_t remainderBy8 = length % 8; + + if (remainderBy8) + { + length -= remainderBy8; + while (remainderBy8--) + { + _pq_etonx_fx0(*pSrc++); + *pDst++ = _pq_readMult0_fx(); + } + } + + if (length) + { + PQ_StartVector(pSrc, pDst, length); + PQ_Vector8Fixed32(PQ_ETONX, 0, PQ_TRANS_FIXED); + PQ_EndVector(); + } +} + +void PQ_VectorSinQ31(int32_t *pSrc, int32_t *pDst, int32_t length) +{ + int32_t remainderBy8 = length % 8; + + uint32_t cppre; +#if defined(FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA) && FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA + pq_float_t magic; + pq_float_t valFloat; + + magic.integerX = 0x30c90fdb; +#endif + + cppre = POWERQUAD->CPPRE; + POWERQUAD->CPPRE = POWERQUAD_CPPRE_CPPRE_OUT(31); + +#if defined(FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA) && FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA + if (remainderBy8) + { + length -= remainderBy8; + while (remainderBy8--) + { + valFloat.floatX = magic.floatX * (float)(*pSrc++); + _pq_sin0(valFloat.integerX); + _pq_readAdd0(); + *pDst++ = (_pq_readAdd0_fx()); + } + } + + while (length > 0) + { + valFloat.floatX = magic.floatX * (float)(*pSrc++); + _pq_sin0(valFloat.integerX); + _pq_readAdd0(); + *pDst++ = (_pq_readAdd0_fx()); + + valFloat.floatX = magic.floatX * (float)(*pSrc++); + _pq_sin0(valFloat.integerX); + _pq_readAdd0(); + *pDst++ = (_pq_readAdd0_fx()); + + valFloat.floatX = magic.floatX * (float)(*pSrc++); + _pq_sin0(valFloat.integerX); + _pq_readAdd0(); + *pDst++ = (_pq_readAdd0_fx()); + + valFloat.floatX = magic.floatX * (float)(*pSrc++); + _pq_sin0(valFloat.integerX); + _pq_readAdd0(); + *pDst++ = (_pq_readAdd0_fx()); + + valFloat.floatX = magic.floatX * (float)(*pSrc++); + _pq_sin0(valFloat.integerX); + _pq_readAdd0(); + *pDst++ = (_pq_readAdd0_fx()); + + valFloat.floatX = magic.floatX * (float)(*pSrc++); + _pq_sin0(valFloat.integerX); + _pq_readAdd0(); + *pDst++ = (_pq_readAdd0_fx()); + + valFloat.floatX = magic.floatX * (float)(*pSrc++); + _pq_sin0(valFloat.integerX); + _pq_readAdd0(); + *pDst++ = (_pq_readAdd0_fx()); + + valFloat.floatX = magic.floatX * (float)(*pSrc++); + _pq_sin0(valFloat.integerX); + _pq_readAdd0(); + *pDst++ = (_pq_readAdd0_fx()); + + length -= 8; + } + +#else + if (remainderBy8) + { + length -= remainderBy8; + while (remainderBy8--) + { + _pq_sin_fx0(*pSrc++); + *pDst++ = _pq_readAdd0_fx(); + } + } + + if (length) + { + PQ_StartVector(pSrc, pDst, length); + PQ_Vector8Fixed32(PQ_SIN, 1, PQ_TRIG_FIXED); + PQ_EndVector(); + } +#endif + + POWERQUAD->CPPRE = cppre; +} + +void PQ_VectorCosQ31(int32_t *pSrc, int32_t *pDst, int32_t length) +{ + int32_t remainderBy8 = length % 8; + + uint32_t cppre; +#if defined(FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA) && FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA + pq_float_t magic; + pq_float_t valFloat; + + magic.integerX = 0x30c90fdb; +#endif + + cppre = POWERQUAD->CPPRE; + POWERQUAD->CPPRE = POWERQUAD_CPPRE_CPPRE_OUT(31); + +#if defined(FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA) && FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA + if (remainderBy8) + { + length -= remainderBy8; + while (remainderBy8--) + { + valFloat.floatX = magic.floatX * (float)(*pSrc++); + _pq_cos0(valFloat.integerX); + _pq_readAdd0(); + *pDst++ = (_pq_readAdd0_fx()); + } + } + + while (length > 0) + { + valFloat.floatX = magic.floatX * (float)(*pSrc++); + _pq_cos0(valFloat.integerX); + _pq_readAdd0(); + *pDst++ = (_pq_readAdd0_fx()); + + valFloat.floatX = magic.floatX * (float)(*pSrc++); + _pq_cos0(valFloat.integerX); + _pq_readAdd0(); + *pDst++ = (_pq_readAdd0_fx()); + + valFloat.floatX = magic.floatX * (float)(*pSrc++); + _pq_cos0(valFloat.integerX); + _pq_readAdd0(); + *pDst++ = (_pq_readAdd0_fx()); + + valFloat.floatX = magic.floatX * (float)(*pSrc++); + _pq_cos0(valFloat.integerX); + _pq_readAdd0(); + *pDst++ = (_pq_readAdd0_fx()); + + valFloat.floatX = magic.floatX * (float)(*pSrc++); + _pq_cos0(valFloat.integerX); + _pq_readAdd0(); + *pDst++ = (_pq_readAdd0_fx()); + + valFloat.floatX = magic.floatX * (float)(*pSrc++); + _pq_cos0(valFloat.integerX); + _pq_readAdd0(); + *pDst++ = (_pq_readAdd0_fx()); + + valFloat.floatX = magic.floatX * (float)(*pSrc++); + _pq_cos0(valFloat.integerX); + _pq_readAdd0(); + *pDst++ = (_pq_readAdd0_fx()); + + valFloat.floatX = magic.floatX * (float)(*pSrc++); + _pq_cos0(valFloat.integerX); + _pq_readAdd0(); + *pDst++ = (_pq_readAdd0_fx()); + + length -= 8; + } + +#else + if (remainderBy8) + { + length -= remainderBy8; + while (remainderBy8--) + { + _pq_cos_fx0(*pSrc++); + *pDst++ = _pq_readAdd0_fx(); + } + } + + if (length) + { + PQ_StartVector(pSrc, pDst, length); + PQ_Vector8Fixed32(PQ_COS, 1, PQ_TRIG_FIXED); + PQ_EndVector(); + } +#endif + + POWERQUAD->CPPRE = cppre; +} + +void PQ_VectorLnFixed16(int16_t *pSrc, int16_t *pDst, int32_t length) +{ + int32_t remainderBy8 = length % 8; + + if (remainderBy8) + { + length -= remainderBy8; + while (remainderBy8--) + { + _pq_ln_fx0(*pSrc++); + *pDst++ = _pq_readAdd0_fx(); + } + } + + if (length) + { + PQ_StartVectorFixed16(pSrc, pDst, length); + PQ_Vector8Fixed16(PQ_LN, 1, PQ_TRANS_FIXED); + PQ_EndVector(); + } +} + +void PQ_VectorInvFixed16(int16_t *pSrc, int16_t *pDst, int32_t length) +{ + int32_t remainderBy8 = length % 8; + + if (remainderBy8) + { + length -= remainderBy8; + while (remainderBy8--) + { + _pq_inv_fx0(*pSrc++); + *pDst++ = _pq_readMult0_fx(); + } + } + + if (length) + { + PQ_StartVectorFixed16(pSrc, pDst, length); + PQ_Vector8Fixed16(PQ_INV, 0, PQ_TRANS_FIXED); + PQ_EndVector(); + } +} + +void PQ_VectorSqrtFixed16(int16_t *pSrc, int16_t *pDst, int32_t length) +{ + int32_t remainderBy8 = length % 8; + + if (remainderBy8) + { + length -= remainderBy8; + while (remainderBy8--) + { + _pq_sqrt_fx0(*pSrc++); + *pDst++ = _pq_readMult0_fx(); + } + } + + if (length) + { + PQ_StartVectorFixed16(pSrc, pDst, length); + PQ_Vector8Fixed16(PQ_SQRT, 0, PQ_TRANS_FIXED); + PQ_EndVector(); + } +} + +void PQ_VectorInvSqrtFixed16(int16_t *pSrc, int16_t *pDst, int32_t length) +{ + int32_t remainderBy8 = length % 8; + + if (remainderBy8) + { + length -= remainderBy8; + while (remainderBy8--) + { + _pq_invsqrt_fx0(*pSrc++); + *pDst++ = _pq_readMult0_fx(); + } + } + + if (length) + { + PQ_StartVectorFixed16(pSrc, pDst, length); + PQ_Vector8Fixed16(PQ_INVSQRT, 0, PQ_TRANS_FIXED); + PQ_EndVector(); + } +} + +void PQ_VectorEtoxFixed16(int16_t *pSrc, int16_t *pDst, int32_t length) +{ + int32_t remainderBy8 = length % 8; + + if (remainderBy8) + { + length -= remainderBy8; + while (remainderBy8--) + { + _pq_etox_fx0(*pSrc++); + *pDst++ = _pq_readMult0_fx(); + } + } + + if (length) + { + PQ_StartVectorFixed16(pSrc, pDst, length); + PQ_Vector8Fixed16(PQ_ETOX, 0, PQ_TRANS_FIXED); + PQ_EndVector(); + } +} + +void PQ_VectorEtonxFixed16(int16_t *pSrc, int16_t *pDst, int32_t length) +{ + int32_t remainderBy8 = length % 8; + + if (remainderBy8) + { + length -= remainderBy8; + while (remainderBy8--) + { + _pq_etonx_fx0(*pSrc++); + *pDst++ = _pq_readMult0_fx(); + } + } + + if (length) + { + PQ_StartVectorFixed16(pSrc, pDst, length); + PQ_Vector8Fixed16(PQ_ETONX, 0, PQ_TRANS_FIXED); + PQ_EndVector(); + } +} + +void PQ_VectorSinQ15(int16_t *pSrc, int16_t *pDst, int32_t length) +{ + uint32_t cppre; +#if defined(FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA) && FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA + pq_float_t magic; + pq_float_t valFloat; + + magic.integerX = 0x30c90fdb; +#endif + + cppre = POWERQUAD->CPPRE; + POWERQUAD->CPPRE = POWERQUAD_CPPRE_CPPRE_OUT(31); + + int32_t remainderBy8 = length % 8; + +#if defined(FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA) && FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA + if (remainderBy8) + { + length -= remainderBy8; + while (remainderBy8--) + { + valFloat.floatX = magic.floatX * (float)((uint32_t)(*pSrc++) << 16); + _pq_sin0(*(int32_t *)(&valFloat)); + _pq_readAdd0(); + *pDst++ = (_pq_readAdd0_fx()) >> 16; + } + } + + while (length > 0) + { + valFloat.floatX = magic.floatX * (float)((uint32_t)(*pSrc++) << 16); + _pq_sin0(valFloat.integerX); + _pq_readAdd0(); + *pDst++ = (_pq_readAdd0_fx()) >> 16; + + valFloat.floatX = magic.floatX * (float)((uint32_t)(*pSrc++) << 16); + _pq_sin0(valFloat.integerX); + _pq_readAdd0(); + *pDst++ = (_pq_readAdd0_fx()) >> 16; + + valFloat.floatX = magic.floatX * (float)((uint32_t)(*pSrc++) << 16); + _pq_sin0(valFloat.integerX); + _pq_readAdd0(); + *pDst++ = (_pq_readAdd0_fx()) >> 16; + + valFloat.floatX = magic.floatX * (float)((uint32_t)(*pSrc++) << 16); + _pq_sin0(valFloat.integerX); + _pq_readAdd0(); + *pDst++ = (_pq_readAdd0_fx()) >> 16; + + valFloat.floatX = magic.floatX * (float)((uint32_t)(*pSrc++) << 16); + _pq_sin0(valFloat.integerX); + _pq_readAdd0(); + *pDst++ = (_pq_readAdd0_fx()) >> 16; + + valFloat.floatX = magic.floatX * (float)((uint32_t)(*pSrc++) << 16); + _pq_sin0(valFloat.integerX); + _pq_readAdd0(); + *pDst++ = (_pq_readAdd0_fx()) >> 16; + + valFloat.floatX = magic.floatX * (float)((uint32_t)(*pSrc++) << 16); + _pq_sin0(valFloat.integerX); + _pq_readAdd0(); + *pDst++ = (_pq_readAdd0_fx()) >> 16; + + valFloat.floatX = magic.floatX * (float)((uint32_t)(*pSrc++) << 16); + _pq_sin0(valFloat.integerX); + _pq_readAdd0(); + *pDst++ = (_pq_readAdd0_fx()) >> 16; + + length -= 8; + } + +#else + + if (remainderBy8) + { + length -= remainderBy8; + while (remainderBy8--) + { + _pq_sin_fx0((uint32_t)(*pSrc++) << 16); + *pDst++ = (_pq_readAdd0_fx()) >> 16; + } + } + + if (length) + { + PQ_StartVectorQ15(pSrc, pDst, length); + PQ_Vector8Q15(PQ_SIN, 1, PQ_TRIG_FIXED); + PQ_EndVector(); + } +#endif + + POWERQUAD->CPPRE = cppre; +} + +void PQ_VectorCosQ15(int16_t *pSrc, int16_t *pDst, int32_t length) +{ + uint32_t cppre; +#if defined(FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA) && FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA + pq_float_t magic; + pq_float_t valFloat; + + magic.integerX = 0x30c90fdb; +#endif + + cppre = POWERQUAD->CPPRE; + POWERQUAD->CPPRE = POWERQUAD_CPPRE_CPPRE_OUT(31); + + int32_t remainderBy8 = length % 8; + +#if defined(FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA) && FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA + if (remainderBy8) + { + length -= remainderBy8; + while (remainderBy8--) + { + valFloat.floatX = magic.floatX * (float)((*pSrc++) << 16); + _pq_cos0(valFloat.integerX); + _pq_readAdd0(); + *pDst++ = (_pq_readAdd0_fx()) >> 16; + } + } + + while (length > 0) + { + valFloat.floatX = magic.floatX * (float)((*pSrc++) << 16); + _pq_cos0(valFloat.integerX); + _pq_readAdd0(); + *pDst++ = (_pq_readAdd0_fx()) >> 16; + + valFloat.floatX = magic.floatX * (float)((*pSrc++) << 16); + _pq_cos0(valFloat.integerX); + _pq_readAdd0(); + *pDst++ = (_pq_readAdd0_fx()) >> 16; + + valFloat.floatX = magic.floatX * (float)((*pSrc++) << 16); + _pq_cos0(valFloat.integerX); + _pq_readAdd0(); + *pDst++ = (_pq_readAdd0_fx()) >> 16; + + valFloat.floatX = magic.floatX * (float)((*pSrc++) << 16); + _pq_cos0(valFloat.integerX); + _pq_readAdd0(); + *pDst++ = (_pq_readAdd0_fx()) >> 16; + + valFloat.floatX = magic.floatX * (float)((*pSrc++) << 16); + _pq_cos0(valFloat.integerX); + _pq_readAdd0(); + *pDst++ = (_pq_readAdd0_fx()) >> 16; + + valFloat.floatX = magic.floatX * (float)((*pSrc++) << 16); + _pq_cos0(valFloat.integerX); + _pq_readAdd0(); + *pDst++ = (_pq_readAdd0_fx()) >> 16; + + valFloat.floatX = magic.floatX * (float)((*pSrc++) << 16); + _pq_cos0(valFloat.integerX); + _pq_readAdd0(); + *pDst++ = (_pq_readAdd0_fx()) >> 16; + + valFloat.floatX = magic.floatX * (float)((*pSrc++) << 16); + _pq_cos0(valFloat.integerX); + _pq_readAdd0(); + *pDst++ = (_pq_readAdd0_fx()) >> 16; + + length -= 8; + } + +#else + + if (remainderBy8) + { + length -= remainderBy8; + while (remainderBy8--) + { + _pq_cos_fx0((uint32_t)(*pSrc++) << 16); + *pDst++ = (_pq_readAdd0_fx()) >> 16; + } + } + + if (length) + { + PQ_StartVectorQ15(pSrc, pDst, length); + PQ_Vector8Q15(PQ_COS, 1, PQ_TRIG_FIXED); + PQ_EndVector(); + } +#endif + + POWERQUAD->CPPRE = cppre; +} + +int32_t PQ_ArctanFixed(POWERQUAD_Type *base, int32_t x, int32_t y, pq_cordic_iter_t iteration) +{ + base->CORDIC_X = x; + base->CORDIC_Y = y; + base->CORDIC_Z = 0; + base->CONTROL = (CP_CORDIC << 4) | CORDIC_ARCTAN | CORDIC_ITER(iteration); + + PQ_WaitDone(base); + return base->CORDIC_Z; +} + +int32_t PQ_ArctanhFixed(POWERQUAD_Type *base, int32_t x, int32_t y, pq_cordic_iter_t iteration) +{ + base->CORDIC_X = x; + base->CORDIC_Y = y; + base->CORDIC_Z = 0; + base->CONTROL = (CP_CORDIC << 4) | CORDIC_ARCTANH | CORDIC_ITER(iteration); + + PQ_WaitDone(base); + return base->CORDIC_Z; +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_powerquad_matrix.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_powerquad_matrix.c new file mode 100644 index 000000000..6d14e1633 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_powerquad_matrix.c @@ -0,0 +1,134 @@ +/* + * Copyright 2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_powerquad.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.powerquad_matrix" +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ +void PQ_MatrixAddition(POWERQUAD_Type *base, uint32_t length, void *pAData, void *pBData, void *pResult) +{ + assert(pAData); + assert(pBData); + assert(pResult); + + base->OUTBASE = (int32_t)pResult; + base->INABASE = (int32_t)pAData; + base->INBBASE = (int32_t)pBData; + base->LENGTH = length; + base->CONTROL = (CP_MTX << 4) | PQ_MTX_ADD; +} + +void PQ_MatrixSubtraction(POWERQUAD_Type *base, uint32_t length, void *pAData, void *pBData, void *pResult) +{ + assert(pAData); + assert(pBData); + assert(pResult); + + base->OUTBASE = (int32_t)pResult; + base->INABASE = (int32_t)pAData; + base->INBBASE = (int32_t)pBData; + base->LENGTH = length; + base->CONTROL = (CP_MTX << 4) | PQ_MTX_SUB; +} + +void PQ_MatrixMultiplication(POWERQUAD_Type *base, uint32_t length, void *pAData, void *pBData, void *pResult) +{ + assert(pAData); + assert(pBData); + assert(pResult); + + base->OUTBASE = (int32_t)pResult; + base->INABASE = (int32_t)pAData; + base->INBBASE = (int32_t)pBData; + base->LENGTH = length; + base->CONTROL = (CP_MTX << 4) | PQ_MTX_MULT; +} + +void PQ_MatrixProduct(POWERQUAD_Type *base, uint32_t length, void *pAData, void *pBData, void *pResult) +{ + assert(pAData); + assert(pBData); + assert(pResult); + + base->OUTBASE = (int32_t)pResult; + base->INABASE = (int32_t)pAData; + base->INBBASE = (int32_t)pBData; + base->LENGTH = length; + base->CONTROL = (CP_MTX << 4) | PQ_MTX_PROD; +} + +void PQ_VectorDotProduct(POWERQUAD_Type *base, uint32_t length, void *pAData, void *pBData, void *pResult) +{ + assert(pAData); + assert(pBData); + assert(pResult); + + base->OUTBASE = (int32_t)pResult; + base->INABASE = (int32_t)pAData; + base->INBBASE = (int32_t)pBData; + base->LENGTH = length; + base->CONTROL = (CP_MTX << 4) | PQ_VEC_DOTP; +} + +void PQ_MatrixInversion(POWERQUAD_Type *base, uint32_t length, void *pData, void *pTmpData, void *pResult) +{ + assert(pData); + assert(pTmpData); + assert(pResult); + + /* Workaround: + * + * Matrix inv depends on the coproc 1/x function, this puts coproc to right state. + */ + _pq_inv0(1.0); + + base->INABASE = (uint32_t)pData; + base->TMPBASE = (uint32_t)pTmpData; + base->OUTBASE = (uint32_t)pResult; + base->LENGTH = length; + base->CONTROL = (CP_MTX << 4) | PQ_MTX_INV; +} + +void PQ_MatrixTranspose(POWERQUAD_Type *base, uint32_t length, void *pData, void *pResult) +{ + assert(pData); + assert(pResult); + + base->OUTBASE = (int32_t)pResult; + base->INABASE = (int32_t)pData; + base->LENGTH = length; + base->CONTROL = (CP_MTX << 4) | PQ_MTX_TRAN; +} + +void PQ_MatrixScale(POWERQUAD_Type *base, uint32_t length, float misc, void *pData, void *pResult) +{ + assert(pData); + assert(pResult); + + base->OUTBASE = (int32_t)pResult; + base->INABASE = (int32_t)pData; + base->LENGTH = length; +#if defined(__GNUC__) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wstrict-aliasing" +#endif + base->MISC = *(uint32_t *)&misc; +#if defined(__GNUC__) +#pragma GCC diagnostic pop +#endif + base->CONTROL = (CP_MTX << 4) | PQ_MTX_SCALE; +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_powerquad_transform.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_powerquad_transform.c new file mode 100644 index 000000000..43c828503 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_powerquad_transform.c @@ -0,0 +1,103 @@ +/* + * Copyright 2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_powerquad.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.powerquad_transform" +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ +void PQ_TransformCFFT(POWERQUAD_Type *base, uint32_t length, void *pData, void *pResult) +{ + assert(pData); + assert(pResult); + + base->OUTBASE = (int32_t)pResult; + base->INABASE = (int32_t)pData; + base->LENGTH = length; + base->CONTROL = (CP_FFT << 4) | PQ_TRANS_CFFT; +} + +void PQ_TransformRFFT(POWERQUAD_Type *base, uint32_t length, void *pData, void *pResult) +{ + assert(pData); + assert(pResult); + + /* Set 0's for imaginary inputs as not be reading them in by the machine */ + base->GPREG[1] = 0; + base->GPREG[3] = 0; + base->GPREG[5] = 0; + base->GPREG[7] = 0; + base->GPREG[9] = 0; + base->GPREG[11] = 0; + base->GPREG[13] = 0; + base->GPREG[15] = 0; + base->OUTBASE = (int32_t)pResult; + base->INABASE = (int32_t)pData; + base->LENGTH = length; + base->CONTROL = (CP_FFT << 4) | PQ_TRANS_RFFT; +} + +void PQ_TransformIFFT(POWERQUAD_Type *base, uint32_t length, void *pData, void *pResult) +{ + assert(pData); + assert(pResult); + + base->OUTBASE = (int32_t)pResult; + base->INABASE = (int32_t)pData; + base->LENGTH = length; + base->CONTROL = (CP_FFT << 4) | PQ_TRANS_IFFT; +} + +void PQ_TransformCDCT(POWERQUAD_Type *base, uint32_t length, void *pData, void *pResult) +{ + assert(pData); + assert(pResult); + + base->OUTBASE = (int32_t)pResult; + base->INABASE = (int32_t)pData; + base->LENGTH = length; + base->CONTROL = (CP_FFT << 4) | PQ_TRANS_CDCT; +} + +void PQ_TransformRDCT(POWERQUAD_Type *base, uint32_t length, void *pData, void *pResult) +{ + assert(pData); + assert(pResult); + + base->GPREG[1] = 0; + base->GPREG[3] = 0; + base->GPREG[5] = 0; + base->GPREG[7] = 0; + base->GPREG[9] = 0; + base->GPREG[11] = 0; + base->GPREG[13] = 0; + base->GPREG[15] = 0; + base->OUTBASE = (int32_t)pResult; + base->INABASE = (int32_t)pData; + base->LENGTH = length; + base->CONTROL = (CP_FFT << 4) | PQ_TRANS_RDCT; +} + +void PQ_TransformIDCT(POWERQUAD_Type *base, uint32_t length, void *pData, void *pResult) +{ + assert(pData); + assert(pResult); + + base->OUTBASE = (int32_t)pResult; + base->INABASE = (int32_t)pData; + base->LENGTH = length; + base->CONTROL = (CP_FFT << 4) | PQ_TRANS_IDCT; +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_prince.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_prince.c new file mode 100644 index 000000000..e31228235 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_prince.c @@ -0,0 +1,454 @@ +/* + * Copyright 2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_prince.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ + +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.prince" +#endif + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +/*! + * brief Generate new IV code. + * + * This function generates new IV code and stores it into the persistent memory. + * Ensure about 800 bytes free space on the stack when calling this routine with the store parameter set to true! + * + * param region PRINCE region index. + * param iv_code IV code pointer used for storing the newly generated 52 bytes long IV code. + * param store flag to allow storing the newly generated IV code into the persistent memory (FFR). + * param flash_context pointer to the flash driver context structure. + * + * return kStatus_Success upon success + * return kStatus_Fail otherwise, kStatus_Fail is also returned if the key code for the particular + * PRINCE region is not present in the keystore (though new IV code has been provided) + */ +status_t PRINCE_GenNewIV(prince_region_t region, uint8_t *iv_code, bool store, flash_config_t *flash_context) +{ + status_t retVal = kStatus_Fail; + uint8_t prince_iv_code[FLASH_FFR_IV_CODE_SIZE] = {0}; + uint8_t tempBuffer[FLASH_FFR_MAX_PAGE_SIZE] = {0}; + + if (((SYSCON->PERIPHENCFG & SYSCON_PERIPHENCFG_PRINCEEN_MASK) ? true : false) == false) + { + return retVal; /* PRINCE peripheral not enabled, return kStatus_Fail. */ + } + + /* Make sure PUF is started to allow key and IV code decryption and generation */ + if (true != PUF_IsGetKeyAllowed(PUF)) + { + return retVal; + } + + /* Generate new IV code for the PRINCE region */ + retVal = PUF_SetIntrinsicKey(PUF, (puf_key_index_register_t)(kPUF_KeyIndex_02 + (puf_key_index_register_t)region), + 8, &prince_iv_code[0], FLASH_FFR_IV_CODE_SIZE); + if ((kStatus_Success == retVal) && (true == store)) + { + /* Store the new IV code for the PRINCE region into the respective FFRs. */ + /* Create a new version of "Customer Field Programmable" (CFP) page. */ + if (kStatus_FLASH_Success == + FFR_GetCustomerInfieldData(flash_context, (uint8_t *)tempBuffer, 0, FLASH_FFR_MAX_PAGE_SIZE)) + { + /* Set the IV code in the page */ + memcpy(&tempBuffer[offsetof(cfpa_cfg_info_t, ivCodePrinceRegion) + ((region * sizeof(cfpa_cfg_iv_code_t))) + + 4], + &prince_iv_code[0], FLASH_FFR_IV_CODE_SIZE); + + uint32_t *p32 = (uint32_t *)tempBuffer; + uint32_t version = p32[1]; + if (version == 0xFFFFFFFFu) + { + return kStatus_Fail; + } + version++; + p32[1] = version; + + /* Program the page and enable firewall for "Customer field area" */ + if (kStatus_FLASH_Success == + FFR_InfieldPageWrite(flash_context, (uint8_t *)tempBuffer, FLASH_FFR_MAX_PAGE_SIZE)) + { + retVal = kStatus_Success; + } + else + { + retVal = kStatus_Fail; + } + } + } + if (retVal == kStatus_Success) + { + /* Pass the new IV code */ + memcpy(iv_code, &prince_iv_code[0], FLASH_FFR_IV_CODE_SIZE); + } + return retVal; +} + +/*! + * brief Load IV code. + * + * This function enables IV code loading into the PRINCE bus encryption engine. + * + * param region PRINCE region index. + * param iv_code IV code pointer used for passing the IV code. + * + * return kStatus_Success upon success + * return kStatus_Fail otherwise + */ +status_t PRINCE_LoadIV(prince_region_t region, uint8_t *iv_code) +{ + status_t retVal = kStatus_Fail; + uint32_t keyIndex = 0x0Fu & iv_code[1]; + uint8_t prince_iv[8] = {0}; + + if (((SYSCON->PERIPHENCFG & SYSCON_PERIPHENCFG_PRINCEEN_MASK) ? true : false) == false) + { + return retVal; /* PRINCE peripheral not enabled, return kStatus_Fail. */ + } + + /* Make sure PUF is started to allow key and IV code decryption and generation */ + if (true != PUF_IsGetKeyAllowed(PUF)) + { + return retVal; + } + + /* Check if region number matches the PUF index value */ + if ((kPUF_KeyIndex_02 + (puf_key_index_register_t)region) == (puf_key_index_register_t)keyIndex) + { + /* Decrypt the IV */ + if (kStatus_Success == PUF_GetKey(PUF, iv_code, FLASH_FFR_IV_CODE_SIZE, &prince_iv[0], 8)) + { + /* Store the new IV for the PRINCE region into PRINCE registers. */ + PRINCE_SetRegionIV(PRINCE, (prince_region_t)region, prince_iv); + retVal = kStatus_Success; + } + } + return retVal; +} + +/*! + * brief Allow encryption/decryption for specified address range. + * + * This function sets the encryption/decryption for specified address range. + * Ensure about 800 bytes free space on the stack when calling this routine! + * + * param region PRINCE region index. + * param start_address start address of the area to be encrypted/decrypted. + * param length length of the area to be encrypted/decrypted. + * param flash_context pointer to the flash driver context structure. + * + * return kStatus_Success upon success + * return kStatus_Fail otherwise + */ +status_t PRINCE_SetEncryptForAddressRange(prince_region_t region, + uint32_t start_address, + uint32_t length, + flash_config_t *flash_context) +{ + status_t retVal = kStatus_Fail; + uint32_t srEnableRegister = 0; + uint32_t alignedStartAddress; + uint32_t end_address = start_address + length; + uint32_t prince_region_base_address = 0; + uint8_t my_prince_iv_code[52] = {0}; + uint8_t tempBuffer[512] = {0}; + uint32_t prince_base_addr_ffr_word = 0; + + /* Check the address range, regions overlaping. */ + if ((start_address > 0xA0000) || ((start_address < 0x40000) && (end_address > 0x40000)) || + ((start_address < 0x80000) && (end_address > 0x80000)) || + ((start_address < 0xA0000) && (end_address > 0xA0000))) + { + return kStatus_Fail; + } + + /* Generate new IV code for the PRINCE region and store the new IV into the respective FFRs */ + retVal = PRINCE_GenNewIV((prince_region_t)region, &my_prince_iv_code[0], true, flash_context); + if (kStatus_Success != retVal) + { + return kStatus_Fail; + } + + /* Store the new IV for the PRINCE region into PRINCE registers. */ + retVal = PRINCE_LoadIV((prince_region_t)region, &my_prince_iv_code[0]); + if (kStatus_Success != retVal) + { + return kStatus_Fail; + } + + alignedStartAddress = ALIGN_DOWN(start_address, FSL_PRINCE_DRIVER_SUBREGION_SIZE_IN_KB * 1024); + + uint32_t subregion = alignedStartAddress / (FSL_PRINCE_DRIVER_SUBREGION_SIZE_IN_KB * 1024); + if (subregion < (32)) + { + /* PRINCE_Region0 */ + prince_region_base_address = 0; + } + else if (subregion < (64)) + { + /* PRINCE_Region1 */ + subregion = subregion - 32; + prince_region_base_address = 0x40000; + } + else + { + /* PRINCE_Region2 */ + subregion = subregion - 64; + prince_region_base_address = 0x80000; + } + + srEnableRegister = (1 << subregion); + alignedStartAddress += (FSL_PRINCE_DRIVER_SUBREGION_SIZE_IN_KB * 1024); + + while (alignedStartAddress < (start_address + length)) + { + subregion++; + srEnableRegister |= (1 << subregion); + alignedStartAddress += (FSL_PRINCE_DRIVER_SUBREGION_SIZE_IN_KB * 1024); + } + + /* Store BASE_ADDR into PRINCE register before storing the SR to avoid en/decryption triggering + from addresses being defined by current BASE_ADDR register content (could be 0 and the decryption + of actually executed code can be started causing the hardfault then). */ + retVal = PRINCE_SetRegionBaseAddress(PRINCE, (prince_region_t)region, prince_region_base_address); + if (kStatus_Success != retVal) + { + return retVal; + } + + /* Store SR into PRINCE register */ + retVal = PRINCE_SetRegionSREnable(PRINCE, (prince_region_t)region, srEnableRegister); + if (kStatus_Success != retVal) + { + return retVal; + } + + /* Store SR and BASE_ADDR into CMPA FFR */ + if (kStatus_Success == FFR_GetCustomerData(flash_context, (uint8_t *)&tempBuffer, 0, FLASH_FFR_MAX_PAGE_SIZE)) + { + /* Set the PRINCE_SR_X in the page */ + memcpy(&tempBuffer[offsetof(cmpa_cfg_info_t, princeSr) + (region * sizeof(uint32_t))], &srEnableRegister, + sizeof(uint32_t)); + + /* Set the ADDRX_PRG in the page */ + memcpy(&prince_base_addr_ffr_word, &tempBuffer[offsetof(cmpa_cfg_info_t, princeBaseAddr)], sizeof(uint32_t)); + prince_base_addr_ffr_word &= ~((FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_MASK) << (region * 4)); + prince_base_addr_ffr_word |= + (((prince_region_base_address >> 18) & FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_MASK) << (region * 4)); + memcpy(&tempBuffer[offsetof(cmpa_cfg_info_t, princeBaseAddr)], &prince_base_addr_ffr_word, sizeof(uint32_t)); + + /* Program the CMPA page, set seal_part parameter to false (used during development to avoid sealing the part) + */ + retVal = FFR_CustFactoryPageWrite(flash_context, (uint8_t *)tempBuffer, false); + } + + return retVal; +} + +/*! + * brief Gets the PRINCE Sub-Region Enable register. + * + * This function gets PRINCE SR_ENABLE register. + * + * param base PRINCE peripheral address. + * param region PRINCE region index. + * param sr_enable Sub-Region Enable register pointer. + * + * return kStatus_Success upon success + * return kStatus_InvalidArgument + */ +status_t PRINCE_GetRegionSREnable(PRINCE_Type *base, prince_region_t region, uint32_t *sr_enable) +{ + status_t status = kStatus_Success; + + switch (region) + { + case kPRINCE_Region0: + *sr_enable = base->SR_ENABLE0; + break; + + case kPRINCE_Region1: + *sr_enable = base->SR_ENABLE1; + break; + + case kPRINCE_Region2: + *sr_enable = base->SR_ENABLE2; + break; + + default: + status = kStatus_InvalidArgument; + break; + } + + return status; +} + +/*! + * brief Gets the PRINCE region base address register. + * + * This function gets PRINCE BASE_ADDR register. + * + * param base PRINCE peripheral address. + * param region PRINCE region index. + * param region_base_addr Region base address pointer. + * + * return kStatus_Success upon success + * return kStatus_InvalidArgument + */ +status_t PRINCE_GetRegionBaseAddress(PRINCE_Type *base, prince_region_t region, uint32_t *region_base_addr) +{ + status_t status = kStatus_Success; + + switch (region) + { + case kPRINCE_Region0: + *region_base_addr = base->BASE_ADDR0; + break; + + case kPRINCE_Region1: + *region_base_addr = base->BASE_ADDR1; + break; + + case kPRINCE_Region2: + *region_base_addr = base->BASE_ADDR2; + break; + + default: + status = kStatus_InvalidArgument; + break; + } + + return status; +} + +/*! + * @brief Sets the PRINCE region IV. + * + * This function sets specified AES IV for the given region. + * + * @param base PRINCE peripheral address. + * @param region Selection of the PRINCE region to be configured. + * @param iv 64-bit AES IV in little-endian byte order. + */ +status_t PRINCE_SetRegionIV(PRINCE_Type *base, prince_region_t region, const uint8_t iv[8]) +{ + status_t status = kStatus_Fail; + volatile uint32_t *IVMsb_reg = NULL; + volatile uint32_t *IVLsb_reg = NULL; + + switch (region) + { + case kPRINCE_Region0: + IVLsb_reg = &base->IV_LSB0; + IVMsb_reg = &base->IV_MSB0; + break; + + case kPRINCE_Region1: + IVLsb_reg = &base->IV_LSB1; + IVMsb_reg = &base->IV_MSB1; + break; + + case kPRINCE_Region2: + IVLsb_reg = &base->IV_LSB2; + IVMsb_reg = &base->IV_MSB2; + break; + + default: + status = kStatus_InvalidArgument; + break; + } + + if (status != kStatus_InvalidArgument) + { + *IVLsb_reg = ((uint32_t *)(uintptr_t)iv)[0]; + *IVMsb_reg = ((uint32_t *)(uintptr_t)iv)[1]; + status = kStatus_Success; + } + + return status; +} + +/*! + * @brief Sets the PRINCE region base address. + * + * This function configures PRINCE region base address. + * + * @param base PRINCE peripheral address. + * @param region Selection of the PRINCE region to be configured. + * @param region_base_addr Base Address for region. + */ +status_t PRINCE_SetRegionBaseAddress(PRINCE_Type *base, prince_region_t region, uint32_t region_base_addr) +{ + status_t status = kStatus_Success; + + switch (region) + { + case kPRINCE_Region0: + base->BASE_ADDR0 = region_base_addr; + break; + + case kPRINCE_Region1: + base->BASE_ADDR1 = region_base_addr; + break; + + case kPRINCE_Region2: + base->BASE_ADDR2 = region_base_addr; + break; + + default: + status = kStatus_InvalidArgument; + break; + } + + return status; +} + +/*! + * @brief Sets the PRINCE Sub-Region Enable register. + * + * This function configures PRINCE SR_ENABLE register. + * + * @param base PRINCE peripheral address. + * @param region Selection of the PRINCE region to be configured. + * @param sr_enable Sub-Region Enable register value. + */ +status_t PRINCE_SetRegionSREnable(PRINCE_Type *base, prince_region_t region, uint32_t sr_enable) +{ + status_t status = kStatus_Success; + + switch (region) + { + case kPRINCE_Region0: + base->SR_ENABLE0 = sr_enable; + break; + + case kPRINCE_Region1: + base->SR_ENABLE1 = sr_enable; + break; + + case kPRINCE_Region2: + base->SR_ENABLE2 = sr_enable; + break; + + default: + status = kStatus_InvalidArgument; + break; + } + + return status; +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_prince.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_prince.h new file mode 100644 index 000000000..04e37a48a --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_prince.h @@ -0,0 +1,238 @@ +/* + * Copyright 2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_PRINCE_H_ +#define _FSL_PRINCE_H_ + +#include "fsl_common.h" +#include "fsl_iap_ffr.h" +#include "fsl_puf.h" + +/*! + * @addtogroup prince + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief PRINCE driver version 2.0.0. + * + * Current version: 2.0.0 + * + * Change log: + * - Version 2.0.0 + * - Initial version. + */ +#define FSL_PRINCE_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +#define FSL_PRINCE_DRIVER_SUBREGION_SIZE_IN_KB (8) + +#if !defined(ALIGN_DOWN) +#define ALIGN_DOWN(x, a) ((x) & (uint32_t)(-((int32_t)(a)))) +#endif + +typedef enum _prince_region +{ + kPRINCE_Region0 = 0U, /*!< PRINCE region 0 */ + kPRINCE_Region1 = 1U, /*!< PRINCE region 1 */ + kPRINCE_Region2 = 2U, /*!< PRINCE region 2 */ +} prince_region_t; + +typedef enum _prince_lock +{ + kPRINCE_Region0Lock = 1U, /*!< PRINCE region 0 lock */ + kPRINCE_Region1Lock = 2U, /*!< PRINCE region 1 lock */ + kPRINCE_Region2Lock = 4U, /*!< PRINCE region 2 lock */ + kPRINCE_MaskLock = 256U, /*!< PRINCE mask register lock */ +} prince_lock_t; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Enable data encryption. + * + * This function enables PRINCE on-the-fly data encryption. + * + * @param base PRINCE peripheral address. + */ +static inline void PRINCE_EncryptEnable(PRINCE_Type *base) +{ + base->ENC_ENABLE = 1; +} + +/*! + * @brief Disable data encryption. + * + * This function disables PRINCE on-the-fly data encryption. + * + * @param base PRINCE peripheral address. + */ +static inline void PRINCE_EncryptDisable(PRINCE_Type *base) +{ + base->ENC_ENABLE = 0; +} + +/*! + * @brief Sets PRINCE data mask. + * + * This function sets the PRINCE mask that is used to mask decrypted data. + * + * @param base PRINCE peripheral address. + * @param mask 64-bit data mask value. + */ +static inline void PRINCE_SetMask(PRINCE_Type *base, uint64_t mask) +{ + base->MASK_LSB = mask & 0xffffffffu; + base->MASK_MSB = mask >> 32u; +} + +/*! + * @brief Locks access for specified region registers or data mask register. + * + * This function sets lock on specified region registers or mask register. + * + * @param base PRINCE peripheral address. + * @param lock registers to lock. This is a logical OR of members of the + * enumeration ::prince_lock_t + */ +static inline void PRINCE_SetLock(PRINCE_Type *base, uint32_t lock) +{ + base->LOCK = lock & 0x1ffu; +} + +/*! + * @brief Generate new IV code. + * + * This function generates new IV code and stores it into the persistent memory. + * This function is implemented as a wrapper of the exported ROM bootloader API. + * Ensure about 800 bytes free space on the stack when calling this routine with the store parameter set to true! + * + * @param region PRINCE region index. + * @param iv_code IV code pointer used for storing the newly generated 52 bytes long IV code. + * @param store flag to allow storing the newly generated IV code into the persistent memory (FFR). + * param flash_context pointer to the flash driver context structure. + * + * @return kStatus_Success upon success + * @return kStatus_Fail otherwise, kStatus_Fail is also returned if the key code for the particular + * PRINCE region is not present in the keystore (though new IV code has been provided) + */ +status_t PRINCE_GenNewIV(prince_region_t region, uint8_t *iv_code, bool store, flash_config_t *flash_context); + +/*! + * @brief Load IV code. + * + * This function enables IV code loading into the PRINCE bus encryption engine. + * This function is implemented as a wrapper of the exported ROM bootloader API. + * + * @param region PRINCE region index. + * @param iv_code IV code pointer used for passing the IV code. + * + * @return kStatus_Success upon success + * @return kStatus_Fail otherwise + */ +status_t PRINCE_LoadIV(prince_region_t region, uint8_t *iv_code); + +/*! + * @brief Allow encryption/decryption for specified address range. + * + * This function sets the encryption/decryption for specified address range. + * This function is implemented as a wrapper of the exported ROM bootloader API. + * Ensure about 800 bytes free space on the stack when calling this routine! + * + * @param region PRINCE region index. + * @param start_address start address of the area to be encrypted/decrypted. + * @param length length of the area to be encrypted/decrypted. + * param flash_context pointer to the flash driver context structure. + * + * @return kStatus_Success upon success + * @return kStatus_Fail otherwise + */ +status_t PRINCE_SetEncryptForAddressRange(prince_region_t region, + uint32_t start_address, + uint32_t length, + flash_config_t *flash_context); + +/*! + * @brief Gets the PRINCE Sub-Region Enable register. + * + * This function gets PRINCE SR_ENABLE register. + * + * @param base PRINCE peripheral address. + * @param region PRINCE region index. + * @param sr_enable Sub-Region Enable register pointer. + * + * @return kStatus_Success upon success + * @return kStatus_InvalidArgument + */ +status_t PRINCE_GetRegionSREnable(PRINCE_Type *base, prince_region_t region, uint32_t *sr_enable); + +/*! + * @brief Gets the PRINCE region base address register. + * + * This function gets PRINCE BASE_ADDR register. + * + * @param base PRINCE peripheral address. + * @param region PRINCE region index. + * @param region_base_addr Region base address pointer. + * + * @return kStatus_Success upon success + * @return kStatus_InvalidArgument + */ +status_t PRINCE_GetRegionBaseAddress(PRINCE_Type *base, prince_region_t region, uint32_t *region_base_addr); + +/*! + * @brief Sets the PRINCE region IV. + * + * This function sets specified AES IV for the given region. + * + * @param base PRINCE peripheral address. + * @param region Selection of the PRINCE region to be configured. + * @param iv 64-bit AES IV in little-endian byte order. + */ +status_t PRINCE_SetRegionIV(PRINCE_Type *base, prince_region_t region, const uint8_t iv[8]); + +/*! + * @brief Sets the PRINCE region base address. + * + * This function configures PRINCE region base address. + * + * @param base PRINCE peripheral address. + * @param region Selection of the PRINCE region to be configured. + * @param region_base_addr Base Address for region. + */ +status_t PRINCE_SetRegionBaseAddress(PRINCE_Type *base, prince_region_t region, uint32_t region_base_addr); + +/*! + * @brief Sets the PRINCE Sub-Region Enable register. + * + * This function configures PRINCE SR_ENABLE register. + * + * @param base PRINCE peripheral address. + * @param region Selection of the PRINCE region to be configured. + * @param sr_enable Sub-Region Enable register value. + */ +status_t PRINCE_SetRegionSREnable(PRINCE_Type *base, prince_region_t region, uint32_t sr_enable); + +#if defined(__cplusplus) +} +#endif + +/*! + *@} + */ + +#endif /* _FSL_PRINCE_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_puf.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_puf.c new file mode 100644 index 000000000..805c98d45 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_puf.c @@ -0,0 +1,817 @@ +/* + * Copyright 2018 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_puf.h" +#include "fsl_clock.h" +#include "fsl_reset.h" +#include "fsl_common.h" +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.puf" +#endif + +static void puf_wait_usec(volatile uint32_t usec, uint32_t coreClockFrequencyMHz) +{ + while (usec > 0) + { + usec--; + + /* number of MHz is directly number of core clocks to wait 1 usec. */ + /* the while loop below is actually 4 clocks so divide by 4 for ~1 usec */ + register uint32_t ticksCount = coreClockFrequencyMHz / 4u + 1u; + while (ticksCount--) + { + } + } +} + +static status_t puf_waitForInit(PUF_Type *base) +{ + status_t status = kStatus_Fail; + + /* wait until status register reads non-zero. All zero is not valid. It should be BUSY or OK or ERROR */ + while (0 == base->STAT) + { + } + + /* wait if busy */ + while ((base->STAT & PUF_STAT_BUSY_MASK) != 0) + { + } + + /* return status */ + if (base->STAT & (PUF_STAT_SUCCESS_MASK | PUF_STAT_ERROR_MASK)) + { + status = kStatus_Success; + } + + return status; +} + +static void puf_powerOn(PUF_Type *base) +{ +#if defined(FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL) && (FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL > 0) + /* RT6xxs */ + base->PWRCTRL = 0x5u; + base->PWRCTRL = 0xDu; + base->PWRCTRL = 0x9u; +#else /* !FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL */ + /* Niobe4 & Aruba FL */ + base->PWRCTRL = PUF_PWRCTRL_RAMON_MASK; + while (0 == (PUF_PWRCTRL_RAMSTAT_MASK & base->PWRCTRL)) + { + } +#endif /* FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL */ +} + +static status_t puf_powerCycle(PUF_Type *base, uint32_t dischargeTimeMsec, uint32_t coreClockFrequencyHz) +{ +#if defined(FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL) && (FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL > 0) + /* RT6xxs */ + uint32_t coreClockFrequencyMHz = coreClockFrequencyHz / 1000000u; + + base->PWRCTRL = 0xDu; /* disable RAM CK */ + + /* enter ASPS mode */ + base->PWRCTRL = 0xCu; /* SLEEP = 1 */ + base->PWRCTRL = 0x8u; /* enable RAM CK */ + base->PWRCTRL = 0xF8u; /* SLEEP=1, PSW*=1 */ + + /* Wait enough time to discharge fully */ + puf_wait_usec(dischargeTimeMsec * 1000u, coreClockFrequencyHz / 1000000u); + + /* write PWRCTRL=0x38. wait time > 1 us */ + base->PWRCTRL = 0x38u; /* SLEEP=1. PSWSMALL*=0. PSWLARGE*=1. */ + puf_wait_usec(1, coreClockFrequencyMHz); + + /* write PWRCTRL=0x8. wait time > 1 us */ + base->PWRCTRL = 0x08u; /* SLEEP=1. PSWSMALL*=0. PSWLARGE*=0 */ + puf_wait_usec(1, coreClockFrequencyMHz); + + base->PWRCTRL = 0xCu; + base->PWRCTRL = 0xDu; + base->PWRCTRL = 0x9u; + + /* Generate INITN low pulse */ + base->PWRCTRL = 0xDu; + base->PWRCTRL = 0x5u; + base->PWRCTRL = 0x1u; +#else + /* Niobe4 & Aruba FL */ + base->PWRCTRL = 0x0u; + while (PUF_PWRCTRL_RAMSTAT_MASK & base->PWRCTRL) + { + } + + /* Wait enough time to discharge fully */ + puf_wait_usec(dischargeTimeMsec * 1000u, coreClockFrequencyHz / 1000000u); +#endif + + /* Reset PUF and reenable power to PUF SRAM */ + RESET_PeripheralReset(kPUF_RST_SHIFT_RSTn); + puf_powerOn(base); + + return kStatus_Success; +} + +/*! + * brief Initialize PUF + * + * This function enables power to PUF block and waits until the block initializes. + * + * param base PUF peripheral base address + * param dischargeTimeMsec time in ms to wait for PUF SRAM to fully discharge + * param coreClockFrequencyHz core clock frequency in Hz + * return Status of the init operation + */ +status_t PUF_Init(PUF_Type *base, uint32_t dischargeTimeMsec, uint32_t coreClockFrequencyHz) +{ + status_t status = kStatus_Fail; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + CLOCK_EnableClock(kCLOCK_Puf); +#endif + /* Reset PUF */ + RESET_PeripheralReset(kPUF_RST_SHIFT_RSTn); + + /* Enable power to PUF SRAM */ + puf_powerOn(base); + + /* Wait for peripheral to become ready */ + status = puf_waitForInit(base); + + /* In case of error or enroll & start not allowed, do power-cycle */ + if ((status != kStatus_Success) || ((PUF_ALLOW_ALLOWENROLL_MASK | PUF_ALLOW_ALLOWSTART_MASK) != + (base->ALLOW & (PUF_ALLOW_ALLOWENROLL_MASK | PUF_ALLOW_ALLOWSTART_MASK)))) + { + puf_powerCycle(base, dischargeTimeMsec, coreClockFrequencyHz); + status = puf_waitForInit(base); + } + + return status; +} + +/*! + * brief Denitialize PUF + * + * This function disables power to PUF SRAM and peripheral clock. + * + * param base PUF peripheral base address + */ +void PUF_Deinit(PUF_Type *base, uint32_t dischargeTimeMsec, uint32_t coreClockFrequencyHz) +{ +#if defined(FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL) && (FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL > 0) + /* RT6xxs */ + base->PWRCTRL = 0xDu; /* disable RAM CK */ + + /* enter ASPS mode */ + base->PWRCTRL = 0xCu; /* SLEEP = 1 */ + base->PWRCTRL = 0x8u; /* enable RAM CK */ + base->PWRCTRL = 0xF8u; /* SLEEP=1, PSW*=1 */ +#else /* !FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL */ + /* Niobe4 & Aruba FL */ + base->PWRCTRL = 0x00u; +#endif + + /* Wait enough time to discharge fully */ + puf_wait_usec(dischargeTimeMsec * 1000u, coreClockFrequencyHz / 1000000u); + + RESET_SetPeripheralReset(kPUF_RST_SHIFT_RSTn); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + CLOCK_DisableClock(kCLOCK_Puf); +#endif +} + +/*! + * brief Enroll PUF + * + * This function derives a digital fingerprint, generates the corresponding Activation Code (AC) + * and returns it to be stored in an NVM or a file. This step needs to be + * performed only once for each device. This function may be permanently disallowed by a fuse. + * + * param base PUF peripheral base address + * param[out] activationCode Word aligned address of the resulting activation code. + * param activationCodeSize Size of the activationCode buffer in bytes. Shall be 1192 bytes. + * return Status of enroll operation. + */ +status_t PUF_Enroll(PUF_Type *base, uint8_t *activationCode, size_t activationCodeSize) +{ + status_t status = kStatus_Fail; + uint32_t *activationCodeAligned = NULL; + register uint32_t temp32 = 0; + + /* check that activation code buffer size is at least 1192 bytes */ + if (activationCodeSize < PUF_ACTIVATION_CODE_SIZE) + { + return kStatus_InvalidArgument; + } + + /* only work with aligned activationCode */ + if (0x3u & (uintptr_t)activationCode) + { + return kStatus_InvalidArgument; + } + + activationCodeAligned = (uint32_t *)(uintptr_t)activationCode; + + /* check if ENROLL is allowed */ + if (0x0u == (base->ALLOW & PUF_ALLOW_ALLOWENROLL_MASK)) + { + return kStatus_Fail; + } + + /* begin */ + base->CTRL = PUF_CTRL_ENROLL_MASK; + + /* check status */ + while (0 == (base->STAT & (PUF_STAT_BUSY_MASK | PUF_STAT_ERROR_MASK))) + { + } + + /* read out AC */ + while (0 != (base->STAT & PUF_STAT_BUSY_MASK)) + { + if (0 != (PUF_STAT_CODEOUTAVAIL_MASK & base->STAT)) + { + temp32 = base->CODEOUTPUT; + if (activationCodeSize >= sizeof(uint32_t)) + { + *activationCodeAligned = temp32; + activationCodeAligned++; + activationCodeSize -= sizeof(uint32_t); + } + } + } + + if ((base->STAT & PUF_STAT_SUCCESS_MASK) && (activationCodeSize == 0)) + { + status = kStatus_Success; + } + + return status; +} + +/*! + * brief Start PUF + * + * The Activation Code generated during the Enroll operation is used to + * reconstruct the digital fingerprint. This needs to be done after every power-up + * and reset. + * + * param base PUF peripheral base address + * param activationCode Word aligned address of the input activation code. + * param activationCodeSize Size of the activationCode buffer in bytes. Shall be 1192 bytes. + * return Status of start operation. + */ +status_t PUF_Start(PUF_Type *base, const uint8_t *activationCode, size_t activationCodeSize) +{ + status_t status = kStatus_Fail; + const uint32_t *activationCodeAligned = NULL; + register uint32_t temp32 = 0; + + /* check that activation code size is at least 1192 bytes */ + if (activationCodeSize < 1192) + { + return kStatus_InvalidArgument; + } + + /* only work with aligned activationCode */ + if (0x3u & (uintptr_t)activationCode) + { + return kStatus_InvalidArgument; + } + + activationCodeAligned = (const uint32_t *)(uintptr_t)activationCode; + + /* check if START is allowed */ + if (0x0u == (base->ALLOW & PUF_ALLOW_ALLOWSTART_MASK)) + { + return kStatus_Fail; + } + + /* begin */ + base->CTRL = PUF_CTRL_START_MASK; + + /* check status */ + while (0 == (base->STAT & (PUF_STAT_BUSY_MASK | PUF_STAT_ERROR_MASK))) + { + } + + /* while busy send AC */ + while (0 != (base->STAT & PUF_STAT_BUSY_MASK)) + { + if (0 != (PUF_STAT_CODEINREQ_MASK & base->STAT)) + { + if (activationCodeSize >= sizeof(uint32_t)) + { + temp32 = *activationCodeAligned; + activationCodeAligned++; + activationCodeSize -= sizeof(uint32_t); + } + base->CODEINPUT = temp32; + } + } + + /* get status */ + if (0 != (base->STAT & PUF_STAT_SUCCESS_MASK)) + { + status = kStatus_Success; + } + + return status; +} + +/*! + * brief Set intrinsic key + * + * The digital fingerprint generated during the Enroll/Start + * operations is used to generate a Key Code (KC) that defines a unique intrinsic + * key. This KC is returned to be stored in an NVM or a file. This operation + * needs to be done only once for each intrinsic key. + * Each time a Set Intrinsic Key operation is executed a new unique key is + * generated. + * + * param base PUF peripheral base address + * param keyIndex PUF key index register + * param keySize Size of the intrinsic key to generate in bytes. + * param[out] keyCode Word aligned address of the resulting key code. + * param keyCodeSize Size of the keyCode buffer in bytes. Shall be PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(keySize). + * return Status of set intrinsic key operation. + */ +status_t PUF_SetIntrinsicKey( + PUF_Type *base, puf_key_index_register_t keyIndex, size_t keySize, uint8_t *keyCode, size_t keyCodeSize) +{ + status_t status = kStatus_Fail; + uint32_t *keyCodeAligned = NULL; + register uint32_t temp32 = 0; + + /* check if SET KEY is allowed */ + if (0x0u == (base->ALLOW & PUF_ALLOW_ALLOWSETKEY_MASK)) + { + return kStatus_Fail; + } + + /* only work with aligned keyCode */ + if (0x3u & (uintptr_t)keyCode) + { + return kStatus_InvalidArgument; + } + + /* Check that keySize is in the correct range and that it is multiple of 8 */ + if ((keySize < kPUF_KeySizeMin) || (keySize > kPUF_KeySizeMax) || (keySize & 0x7)) + { + return kStatus_InvalidArgument; + } + + /* check that keyCodeSize is correct for given keySize */ + if (keyCodeSize < PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(keySize)) + { + return kStatus_InvalidArgument; + } + + if ((uint32_t)keyIndex > kPUF_KeyIndexMax) + { + return kStatus_InvalidArgument; + } + + keyCodeAligned = (uint32_t *)(uintptr_t)keyCode; + + /* program the key size and index */ + base->KEYSIZE = keySize >> 3; + base->KEYINDEX = (uint32_t)keyIndex; + + /* begin */ + base->CTRL = PUF_CTRL_GENERATEKEY_MASK; + + /* wait till command is accepted */ + while (0 == (base->STAT & (PUF_STAT_BUSY_MASK | PUF_STAT_ERROR_MASK))) + { + } + + /* while busy read KC */ + while (0 != (base->STAT & PUF_STAT_BUSY_MASK)) + { + if (0 != (PUF_STAT_CODEOUTAVAIL_MASK & base->STAT)) + { + temp32 = base->CODEOUTPUT; + if (keyCodeSize >= sizeof(uint32_t)) + { + *keyCodeAligned = temp32; + keyCodeAligned++; + keyCodeSize -= sizeof(uint32_t); + } + } + } + + /* get status */ + if (0 != (base->STAT & PUF_STAT_SUCCESS_MASK)) + { + status = kStatus_Success; + } + + return status; +} + +/*! + * brief Set user key + * + * The digital fingerprint generated during the Enroll/Start + * operations and a user key (UK) provided as input are used to + * generate a Key Code (KC). This KC is sent returned to be stored + * in an NVM or a file. This operation needs to be done only once for each user key. + * + * param base PUF peripheral base address + * param keyIndex PUF key index register + * param userKey Word aligned address of input user key. + * param userKeySize Size of the input user key in bytes. + * param[out] keyCode Word aligned address of the resulting key code. + * param keyCodeSize Size of the keyCode buffer in bytes. Shall be PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(userKeySize). + * return Status of set user key operation. + */ +status_t PUF_SetUserKey(PUF_Type *base, + puf_key_index_register_t keyIndex, + const uint8_t *userKey, + size_t userKeySize, + uint8_t *keyCode, + size_t keyCodeSize) +{ + status_t status = kStatus_Fail; + uint32_t *keyCodeAligned = NULL; + const uint32_t *userKeyAligned = NULL; + register uint32_t temp32 = 0; + + /* check if SET KEY is allowed */ + if (0x0u == (base->ALLOW & PUF_ALLOW_ALLOWSETKEY_MASK)) + { + return kStatus_Fail; + } + + /* only work with aligned keyCode */ + if (0x3u & (uintptr_t)keyCode) + { + return kStatus_InvalidArgument; + } + + /* Check that userKeySize is in the correct range and that it is multiple of 8 */ + if ((userKeySize < kPUF_KeySizeMin) || (userKeySize > kPUF_KeySizeMax) || (userKeySize & 0x7)) + { + return kStatus_InvalidArgument; + } + + /* check that keyCodeSize is correct for given userKeySize */ + if (keyCodeSize < PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(userKeySize)) + { + return kStatus_InvalidArgument; + } + + if ((uint32_t)keyIndex > kPUF_KeyIndexMax) + { + return kStatus_InvalidArgument; + } + + keyCodeAligned = (uint32_t *)(uintptr_t)keyCode; + userKeyAligned = (const uint32_t *)(uintptr_t)userKey; + + /* program the key size and index */ + base->KEYSIZE = userKeySize >> 3; /* convert to 64-bit blocks */ + base->KEYINDEX = (uint32_t)keyIndex; + + /* begin */ + base->CTRL = PUF_CTRL_SETKEY_MASK; + + /* wait till command is accepted */ + while (0 == (base->STAT & (PUF_STAT_BUSY_MASK | PUF_STAT_ERROR_MASK))) + { + } + + /* while busy write UK and read KC */ + while (0 != (base->STAT & PUF_STAT_BUSY_MASK)) + { + if (0 != (PUF_STAT_KEYINREQ_MASK & base->STAT)) + { + if (userKeySize >= sizeof(uint32_t)) + { + temp32 = *userKeyAligned; + userKeyAligned++; + userKeySize -= sizeof(uint32_t); + } + base->KEYINPUT = temp32; + } + + if (0 != (PUF_STAT_CODEOUTAVAIL_MASK & base->STAT)) + { + temp32 = base->CODEOUTPUT; + if (keyCodeSize >= sizeof(uint32_t)) + { + *keyCodeAligned = temp32; + keyCodeAligned++; + keyCodeSize -= sizeof(uint32_t); + } + } + } + + /* get status */ + if (0 != (base->STAT & PUF_STAT_SUCCESS_MASK)) + { + status = kStatus_Success; + } + + return status; +} + +static status_t puf_getHwKey(PUF_Type *base, const uint8_t *keyCode, size_t keyCodeSize) +{ + status_t status = kStatus_Fail; + uint32_t *keyCodeAligned = NULL; + register uint32_t temp32 = 0; + + keyCodeAligned = (uint32_t *)(uintptr_t)keyCode; + + /* begin */ + base->CTRL = PUF_CTRL_GETKEY_MASK; + + /* wait till command is accepted */ + while (0 == (base->STAT & (PUF_STAT_BUSY_MASK | PUF_STAT_ERROR_MASK))) + { + } + + /* while busy send KC, key is reconstructed to HW bus */ + while (0 != (base->STAT & PUF_STAT_BUSY_MASK)) + { + if (0 != (PUF_STAT_CODEINREQ_MASK & base->STAT)) + { + if (keyCodeSize >= sizeof(uint32_t)) + { + temp32 = *keyCodeAligned; + keyCodeAligned++; + keyCodeSize -= sizeof(uint32_t); + } + base->CODEINPUT = temp32; + } + } + + /* get status */ + if (0 != (base->STAT & PUF_STAT_SUCCESS_MASK)) + { + status = kStatus_Success; + } + + return status; +} + +/*! + * brief Reconstruct hw bus key from a key code + * + * The digital fingerprint generated during the Start operation and the KC + * generated during a Set Key operation (Set intrinsic key or Set user key) are used to retrieve a stored key. This + * operation needs to be done every time a key is needed. + * This function accepts only Key Codes created for PUF index register kPUF_KeyIndex_00. + * Such a key is output directly to a dedicated hardware bus. The reconstructed key is not exposed to system memory. + * + * param base PUF peripheral base address + * param keyCode Word aligned address of the input key code. + * param keyCodeSize Size of the keyCode buffer in bytes. Shall be PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(keySize). + * param keySlot key slot to output on hw bus. Parameter is ignored on devices with less than two key slots. + * param keyMask key masking value. Shall be random for each POR/reset. Value does not have to be cryptographicaly + * secure. + * return Status of get key operation. + */ +status_t PUF_GetHwKey( + PUF_Type *base, const uint8_t *keyCode, size_t keyCodeSize, puf_key_slot_t keySlot, uint32_t keyMask) +{ + status_t status = kStatus_Fail; + uint32_t keyIndex; + + /* check if GET KEY is allowed */ + if (0x0u == (base->ALLOW & PUF_ALLOW_ALLOWGETKEY_MASK)) + { + return kStatus_Fail; + } + + /* only work with aligned keyCode */ + if (0x3u & (uintptr_t)keyCode) + { + return kStatus_Fail; + } + + /* check that keyCodeSize is at least PUF_MIN_KEY_CODE_SIZE */ + if (keyCodeSize < PUF_MIN_KEY_CODE_SIZE) + { + return kStatus_InvalidArgument; + } + + keyIndex = 0x0Fu & keyCode[1]; + + /* check the Key Code header byte 1. index must be zero for the hw key. */ + if (kPUF_KeyIndex_00 != (puf_key_index_register_t)keyIndex) + { + return kStatus_Fail; + } + +#if defined(FSL_FEATURE_PUF_HAS_KEYSLOTS) && (FSL_FEATURE_PUF_HAS_KEYSLOTS > 0) + volatile uint32_t *keyMask_reg = NULL; + uint32_t regVal = (2 << (2 * keySlot)); + + switch (keySlot) + { + case kPUF_KeySlot0: + keyMask_reg = &base->KEYMASK[0]; + break; + + case kPUF_KeySlot1: + keyMask_reg = &base->KEYMASK[1]; + break; +#if (FSL_FEATURE_PUF_HAS_KEYSLOTS > 2) + case kPUF_KeySlot2: + keyMask_reg = &base->KEYMASK[2]; + break; + + case kPUF_KeySlot3: + keyMask_reg = &base->KEYMASK[3]; + break; +#endif /* FSL_FEATURE_PUF_HAS_KEYSLOTS > 2 */ + default: + status = kStatus_InvalidArgument; + break; + } +#endif /* FSL_FEATURE_PUF_HAS_KEYSLOTS */ + + if (status != kStatus_InvalidArgument) + { +#if defined(FSL_FEATURE_PUF_HAS_KEYSLOTS) && (FSL_FEATURE_PUF_HAS_KEYSLOTS > 0) + base->KEYRESET = regVal; + base->KEYENABLE = regVal; + *keyMask_reg = keyMask; +#endif /* FSL_FEATURE_PUF_HAS_KEYSLOTS */ + + status = puf_getHwKey(base, keyCode, keyCodeSize); + +#if defined(FSL_FEATURE_PUF_HAS_SHIFT_STATUS) && (FSL_FEATURE_PUF_HAS_SHIFT_STATUS > 0) + size_t keyWords = 0; + + if (status == kStatus_Success) + { + /* if the corresponding shift count does not match, return fail anyway */ + keyWords = ((((size_t)keyCode[3]) * 2) - 1u) << (keySlot << 2); + if (keyWords != ((0x0Fu << (keySlot << 2)) & base->SHIFT_STATUS)) + { + status = kStatus_Fail; + } + } +#endif /* FSL_FEATURE_PUF_HAS_SHIFT_STATUS */ + } + + return status; +} + +/*! + * brief Checks if Get Key operation is allowed. + * + * This function returns true if get key operation is allowed. + * + * param base PUF peripheral base address + * return true if get key operation is allowed + */ +bool PUF_IsGetKeyAllowed(PUF_Type *base) +{ + /* check if GET KEY is allowed */ + if (0x0u == (base->ALLOW & PUF_ALLOW_ALLOWGETKEY_MASK)) + { + return false; + } + + return true; +} + +/*! + * brief Reconstruct key from a key code + * + * The digital fingerprint generated during the Start operation and the KC + * generated during a Set Key operation (Set intrinsic key or Set user key) are used to retrieve a stored key. This + * operation needs to be done every time a key is needed. + * This function accepts only Key Codes created for PUF index registers kPUF_KeyIndex_01 to kPUF_KeyIndex_15. + * + * param base PUF peripheral base address + * param keyCode Word aligned address of the input key code. + * param keyCodeSize Size of the keyCode buffer in bytes. Shall be PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(keySize). + * param[out] key Word aligned address of output key. + * param keySize Size of the output key in bytes. + * return Status of get key operation. + */ +status_t PUF_GetKey(PUF_Type *base, const uint8_t *keyCode, size_t keyCodeSize, uint8_t *key, size_t keySize) +{ + status_t status = kStatus_Fail; + uint32_t *keyCodeAligned = NULL; + uint32_t *keyAligned = NULL; + uint32_t keyIndex; + register uint32_t temp32 = 0; + + /* check if GET KEY is allowed */ + if (0x0u == (base->ALLOW & PUF_ALLOW_ALLOWGETKEY_MASK)) + { + return kStatus_Fail; + } + + /* only work with aligned keyCode */ + if (0x3u & (uintptr_t)keyCode) + { + return kStatus_Fail; + } + + /* only work with aligned key */ + if (0x3u & (uintptr_t)key) + { + return kStatus_Fail; + } + + /* check that keyCodeSize is correct for given keySize */ + if (keyCodeSize < PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(keySize)) + { + return kStatus_InvalidArgument; + } + + keyIndex = 0x0Fu & keyCode[1]; + + /* check the Key Code header byte 1. index must be non-zero for the register key. */ + if (kPUF_KeyIndex_00 == (puf_key_index_register_t)keyIndex) + { + return kStatus_Fail; + } + + keyCodeAligned = (uint32_t *)(uintptr_t)keyCode; + keyAligned = (uint32_t *)(uintptr_t)key; + + /* begin */ + base->CTRL = PUF_CTRL_GETKEY_MASK; + + /* wait till command is accepted */ + while (0 == (base->STAT & (PUF_STAT_BUSY_MASK | PUF_STAT_ERROR_MASK))) + { + } + + /* while busy send KC, read key */ + while (0 != (base->STAT & PUF_STAT_BUSY_MASK)) + { + if (0 != (PUF_STAT_CODEINREQ_MASK & base->STAT)) + { + temp32 = 0; + if (keyCodeSize >= sizeof(uint32_t)) + { + temp32 = *keyCodeAligned; + keyCodeAligned++; + keyCodeSize -= sizeof(uint32_t); + } + base->CODEINPUT = temp32; + } + + if (0 != (PUF_STAT_KEYOUTAVAIL_MASK & base->STAT)) + { + keyIndex = base->KEYOUTINDEX; + temp32 = base->KEYOUTPUT; + if (keySize >= sizeof(uint32_t)) + { + *keyAligned = temp32; + keyAligned++; + keySize -= sizeof(uint32_t); + } + } + } + + /* get status */ + if ((keyIndex) && (0 != (base->STAT & PUF_STAT_SUCCESS_MASK))) + { + status = kStatus_Success; + } + + return status; +} + +/*! + * brief Zeroize PUF + * + * This function clears all PUF internal logic and puts the PUF to error state. + * + * param base PUF peripheral base address + * return Status of the zeroize operation. + */ +status_t PUF_Zeroize(PUF_Type *base) +{ + status_t status = kStatus_Fail; + + /* zeroize command is always allowed */ + base->CTRL = PUF_CTRL_ZEROIZE_MASK; + + /* check that command is accepted */ + if ((0 != (base->STAT & PUF_STAT_ERROR_MASK)) && (0 == base->ALLOW)) + { + status = kStatus_Success; + } + + return status; +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_puf.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_puf.h new file mode 100644 index 000000000..abc00ffaf --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_puf.h @@ -0,0 +1,231 @@ +/* + * Copyright 2018 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PUF_H_ +#define _PUF_H_ + +#include +#include + +#include "fsl_common.h" + +typedef enum _puf_key_index_register +{ + kPUF_KeyIndex_00 = 0x00U, + kPUF_KeyIndex_01 = 0x01U, + kPUF_KeyIndex_02 = 0x02U, + kPUF_KeyIndex_03 = 0x03U, + kPUF_KeyIndex_04 = 0x04U, + kPUF_KeyIndex_05 = 0x05U, + kPUF_KeyIndex_06 = 0x06U, + kPUF_KeyIndex_07 = 0x07U, + kPUF_KeyIndex_08 = 0x08U, + kPUF_KeyIndex_09 = 0x09U, + kPUF_KeyIndex_10 = 0x0AU, + kPUF_KeyIndex_11 = 0x0BU, + kPUF_KeyIndex_12 = 0x0CU, + kPUF_KeyIndex_13 = 0x0DU, + kPUF_KeyIndex_14 = 0x0EU, + kPUF_KeyIndex_15 = 0x0FU, +} puf_key_index_register_t; + +typedef enum _puf_min_max +{ + kPUF_KeySizeMin = 8u, + kPUF_KeySizeMax = 512u, + kPUF_KeyIndexMax = kPUF_KeyIndex_15, +} puf_min_max_t; + +typedef enum _puf_key_slot +{ + kPUF_KeySlot0 = 0U, /*!< PUF key slot 0 */ + kPUF_KeySlot1 = 1U, /*!< PUF key slot 1 */ +#if defined(FSL_FEATURE_PUF_HAS_KEYSLOTS) && (FSL_FEATURE_PUF_HAS_KEYSLOTS > 2) + kPUF_KeySlot2 = 2U, /*!< PUF key slot 2 */ + kPUF_KeySlot3 = 3U, /*!< PUF key slot 3 */ +#endif +} puf_key_slot_t; + +/*! @brief Get Key Code size in bytes from key size in bytes at compile time. */ +#define PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(x) ((160u + ((((x << 3) + 255u) >> 8) << 8)) >> 3) +#define PUF_MIN_KEY_CODE_SIZE PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(8) +#define PUF_ACTIVATION_CODE_SIZE 1192 +/******************************************************************************* + * API + *******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @brief Initialize PUF + * + * This function enables power to PUF block and waits until the block initializes. + * + * @param base PUF peripheral base address + * @param dischargeTimeMsec time in ms to wait for PUF SRAM to fully discharge + * @param coreClockFrequencyHz core clock frequency in Hz + * @return Status of the init operation + */ +status_t PUF_Init(PUF_Type *base, uint32_t dischargeTimeMsec, uint32_t coreClockFrequencyHz); + +/*! + * @brief Denitialize PUF + * + * This function disables power to PUF SRAM and peripheral clock. + * + * @param base PUF peripheral base address + * @param dischargeTimeMsec time in ms to wait for PUF SRAM to fully discharge + * @param coreClockFrequencyHz core clock frequency in Hz + */ +void PUF_Deinit(PUF_Type *base, uint32_t dischargeTimeMsec, uint32_t coreClockFrequencyHz); + +/*! + * @brief Enroll PUF + * + * This function derives a digital fingerprint, generates the corresponding Activation Code (AC) + * and returns it to be stored in an NVM or a file. This step needs to be + * performed only once for each device. This function may be permanently disallowed by a fuse. + * + * @param base PUF peripheral base address + * @param[out] activationCode Word aligned address of the resulting activation code. + * @param activationCodeSize Size of the activationCode buffer in bytes. Shall be 1192 bytes. + * @return Status of enroll operation. + */ +status_t PUF_Enroll(PUF_Type *base, uint8_t *activationCode, size_t activationCodeSize); + +/*! + * @brief Start PUF + * + * The Activation Code generated during the Enroll operation is used to + * reconstruct the digital fingerprint. This needs to be done after every power-up + * and reset. + * + * @param base PUF peripheral base address + * @param activationCode Word aligned address of the input activation code. + * @param activationCodeSize Size of the activationCode buffer in bytes. Shall be 1192 bytes. + * @return Status of start operation. + */ +status_t PUF_Start(PUF_Type *base, const uint8_t *activationCode, size_t activationCodeSize); + +/*! + * @brief Set intrinsic key + * + * The digital fingerprint generated during the Enroll/Start + * operations is used to generate a Key Code (KC) that defines a unique intrinsic + * key. This KC is returned to be stored in an NVM or a file. This operation + * needs to be done only once for each intrinsic key. + * Each time a Set Intrinsic Key operation is executed a new unique key is + * generated. + * + * @param base PUF peripheral base address + * @param keyIndex PUF key index register + * @param keySize Size of the intrinsic key to generate in bytes. + * @param[out] keyCode Word aligned address of the resulting key code. + * @param keyCodeSize Size of the keyCode buffer in bytes. Shall be PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(keySize). + * @return Status of set intrinsic key operation. + */ +status_t PUF_SetIntrinsicKey( + PUF_Type *base, puf_key_index_register_t keyIndex, size_t keySize, uint8_t *keyCode, size_t keyCodeSize); + +/*! + * @brief Set user key + * + * The digital fingerprint generated during the Enroll/Start + * operations and a user key (UK) provided as input are used to + * generate a Key Code (KC). This KC is sent returned to be stored + * in an NVM or a file. This operation needs to be done only once for each user key. + * + * @param base PUF peripheral base address + * @param keyIndex PUF key index register + * @param userKey Word aligned address of input user key. + * @param userKeySize Size of the input user key in bytes. + * @param[out] keyCode Word aligned address of the resulting key code. + * @param keyCodeSize Size of the keyCode buffer in bytes. Shall be PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(userKeySize). + * @return Status of set user key operation. + */ +status_t PUF_SetUserKey(PUF_Type *base, + puf_key_index_register_t keyIndex, + const uint8_t *userKey, + size_t userKeySize, + uint8_t *keyCode, + size_t keyCodeSize); + +/*! + * @brief Reconstruct key from a key code + * + * The digital fingerprint generated during the Start operation and the KC + * generated during a Set Key operation (Set intrinsic key or Set user key) are used to retrieve a stored key. This + * operation needs to be done every time a key is needed. + * This function accepts only Key Codes created for PUF index registers kPUF_KeyIndex_01 to kPUF_KeyIndex_15. + * + * @param base PUF peripheral base address + * @param keyCode Word aligned address of the input key code. + * @param keyCodeSize Size of the keyCode buffer in bytes. Shall be PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(keySize). + * @param[out] key Word aligned address of output key. + * @param keySize Size of the output key in bytes. + * @return Status of get key operation. + */ +status_t PUF_GetKey(PUF_Type *base, const uint8_t *keyCode, size_t keyCodeSize, uint8_t *key, size_t keySize); + +/*! + * @brief Reconstruct hw bus key from a key code + * + * The digital fingerprint generated during the Start operation and the KC + * generated during a Set Key operation (Set intrinsic key or Set user key) are used to retrieve a stored key. This + * operation needs to be done every time a key is needed. + * This function accepts only Key Codes created for PUF index register kPUF_KeyIndex_00. + * Such a key is output directly to a dedicated hardware bus. The reconstructed key is not exposed to system memory. + * + * @param base PUF peripheral base address + * @param keyCode Word aligned address of the input key code. + * @param keyCodeSize Size of the keyCode buffer in bytes. Shall be PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(keySize). + * @param keySlot key slot to output on hw bus. Parameter is ignored on devices with less than two key slots. + * @param keyMask key masking value. Shall be random for each POR/reset. Value does not have to be cryptographicaly + * secure. + * @return Status of get key operation. + */ +status_t PUF_GetHwKey( + PUF_Type *base, const uint8_t *keyCode, size_t keyCodeSize, puf_key_slot_t keySlot, uint32_t keyMask); + +/*! + * @brief Zeroize PUF + * + * This function clears all PUF internal logic and puts the PUF to error state. + * + * @param base PUF peripheral base address + * @return Status of the zeroize operation. + */ +status_t PUF_Zeroize(PUF_Type *base); + +/*! + * @brief Checks if Get Key operation is allowed. + * + * This function returns true if get key operation is allowed. + * + * @param base PUF peripheral base address + * @return true if get key operation is allowed + */ +bool PUF_IsGetKeyAllowed(PUF_Type *base); + +static inline void PUF_BlockSetKey(PUF_Type *base) +{ + base->CFG |= PUF_CFG_BLOCKKEYOUTPUT_MASK; /* block set key */ +} + +static inline void PUF_BlockEnroll(PUF_Type *base) +{ + base->CFG |= PUF_CFG_BLOCKENROLL_SETKEY_MASK; /* block enroll */ +} + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +#endif /* _PUF_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_reset.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_reset.c new file mode 100644 index 000000000..84857298f --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_reset.c @@ -0,0 +1,99 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016, NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" +#include "fsl_reset.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.reset" +#endif + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) + +/*! + * brief Assert reset to peripheral. + * + * Asserts reset signal to specified peripheral module. + * + * param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register + * and reset bit position in the reset register. + */ +void RESET_SetPeripheralReset(reset_ip_name_t peripheral) +{ + const uint32_t regIndex = ((uint32_t)peripheral & 0xFFFF0000u) >> 16; + const uint32_t bitPos = ((uint32_t)peripheral & 0x0000FFFFu); + const uint32_t bitMask = 1u << bitPos; + + assert(bitPos < 32u); + + /* reset register is in SYSCON */ + /* set bit */ + SYSCON->PRESETCTRLSET[regIndex] = bitMask; + /* wait until it reads 0b1 */ + while (0u == (SYSCON->PRESETCTRLX[regIndex] & bitMask)) + { + } +} + +/*! + * brief Clear reset to peripheral. + * + * Clears reset signal to specified peripheral module, allows it to operate. + * + * param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register + * and reset bit position in the reset register. + */ +void RESET_ClearPeripheralReset(reset_ip_name_t peripheral) +{ + const uint32_t regIndex = ((uint32_t)peripheral & 0xFFFF0000u) >> 16; + const uint32_t bitPos = ((uint32_t)peripheral & 0x0000FFFFu); + const uint32_t bitMask = 1u << bitPos; + + assert(bitPos < 32u); + + /* reset register is in SYSCON */ + + /* clear bit */ + SYSCON->PRESETCTRLCLR[regIndex] = bitMask; + /* wait until it reads 0b0 */ + while (bitMask == (SYSCON->PRESETCTRLX[regIndex] & bitMask)) + { + } +} + +/*! + * brief Reset peripheral module. + * + * Reset peripheral module. + * + * param peripheral Peripheral to reset. The enum argument contains encoding of reset register + * and reset bit position in the reset register. + */ +void RESET_PeripheralReset(reset_ip_name_t peripheral) +{ + RESET_SetPeripheralReset(peripheral); + RESET_ClearPeripheralReset(peripheral); +} + +#endif /* FSL_FEATURE_SOC_SYSCON_COUNT || FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_reset.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_reset.h new file mode 100644 index 000000000..1e92823ff --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_reset.h @@ -0,0 +1,281 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016, NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_RESET_H_ +#define _FSL_RESET_H_ + +#include +#include +#include +#include +#include "fsl_device_registers.h" + +/*! + * @addtogroup ksdk_common + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief reset driver version 2.0.0. */ +#define FSL_RESET_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/*! + * @brief Enumeration for peripheral reset control bits + * + * Defines the enumeration for peripheral reset control bits in PRESETCTRL/ASYNCPRESETCTRL registers + */ +typedef enum _SYSCON_RSTn +{ + kROM_RST_SHIFT_RSTn = 0 | 1U, /**< ROM reset control */ + kSRAM1_RST_SHIFT_RSTn = 0 | 3U, /**< SRAM1 reset control */ + kSRAM2_RST_SHIFT_RSTn = 0 | 4U, /**< SRAM2 reset control */ + kSRAM3_RST_SHIFT_RSTn = 0 | 5U, /**< SRAM3 reset control */ + kSRAM4_RST_SHIFT_RSTn = 0 | 6U, /**< SRAM4 reset control */ + kFLASH_RST_SHIFT_RSTn = 0 | 7U, /**< Flash controller reset control */ + kFMC_RST_SHIFT_RSTn = 0 | 8U, /**< Flash accelerator reset control */ + kSPIFI_RST_SHIFT_RSTn = 0 | 10U, /**< SPIFI reset control */ + kMUX0_RST_SHIFT_RSTn = 0 | 11U, /**< Input mux0 reset control */ + kIOCON_RST_SHIFT_RSTn = 0 | 13U, /**< IOCON reset control */ + kGPIO0_RST_SHIFT_RSTn = 0 | 14U, /**< GPIO0 reset control */ + kGPIO1_RST_SHIFT_RSTn = 0 | 15U, /**< GPIO1 reset control */ + kGPIO2_RST_SHIFT_RSTn = 0 | 16U, /**< GPIO2 reset control */ + kGPIO3_RST_SHIFT_RSTn = 0 | 17U, /**< GPIO3 reset control */ + kPINT_RST_SHIFT_RSTn = 0 | 18U, /**< Pin interrupt (PINT) reset control */ + kGINT_RST_SHIFT_RSTn = 0 | 19U, /**< Grouped interrupt (PINT) reset control. */ + kDMA0_RST_SHIFT_RSTn = 0 | 20U, /**< DMA reset control */ + kCRC_RST_SHIFT_RSTn = 0 | 21U, /**< CRC reset control */ + kWWDT_RST_SHIFT_RSTn = 0 | 22U, /**< Watchdog timer reset control */ + kRTC_RST_SHIFT_RSTn = 0 | 23U, /**< RTC reset control */ + kMAILBOX_RST_SHIFT_RSTn = 0 | 26U, /**< Mailbox reset control */ + kADC0_RST_SHIFT_RSTn = 0 | 27U, /**< ADC0 reset control */ + + kMRT_RST_SHIFT_RSTn = 65536 | 0U, /**< Multi-rate timer (MRT) reset control */ + kOSTIMER0_RST_SHIFT_RSTn = 65536 | 1U, /**< OSTimer0 reset control */ + kSCT0_RST_SHIFT_RSTn = 65536 | 2U, /**< SCTimer/PWM 0 (SCT0) reset control */ + kSCTIPU_RST_SHIFT_RSTn = 65536 | 6U, /**< SCTIPU reset control */ + kUTICK_RST_SHIFT_RSTn = 65536 | 10U, /**< Micro-tick timer reset control */ + kFC0_RST_SHIFT_RSTn = 65536 | 11U, /**< Flexcomm Interface 0 reset control */ + kFC1_RST_SHIFT_RSTn = 65536 | 12U, /**< Flexcomm Interface 1 reset control */ + kFC2_RST_SHIFT_RSTn = 65536 | 13U, /**< Flexcomm Interface 2 reset control */ + kFC3_RST_SHIFT_RSTn = 65536 | 14U, /**< Flexcomm Interface 3 reset control */ + kFC4_RST_SHIFT_RSTn = 65536 | 15U, /**< Flexcomm Interface 4 reset control */ + kFC5_RST_SHIFT_RSTn = 65536 | 16U, /**< Flexcomm Interface 5 reset control */ + kFC6_RST_SHIFT_RSTn = 65536 | 17U, /**< Flexcomm Interface 6 reset control */ + kFC7_RST_SHIFT_RSTn = 65536 | 18U, /**< Flexcomm Interface 7 reset control */ + kCTIMER2_RST_SHIFT_RSTn = 65536 | 22U, /**< CTimer 2 reset control */ + kUSB0D_RST_SHIFT_RSTn = 65536 | 25U, /**< USB0 Device reset control */ + kCTIMER0_RST_SHIFT_RSTn = 65536 | 26U, /**< CTimer 0 reset control */ + kCTIMER1_RST_SHIFT_RSTn = 65536 | 27U, /**< CTimer 1 reset control */ + kPVT_RST_SHIFT_RSTn = 65536 | 28U, /**< PVT reset control */ + kEZHA_RST_SHIFT_RSTn = 65536 | 30U, /**< EZHA reset control */ + kEZHB_RST_SHIFT_RSTn = 65536 | 31U, /**< EZHB reset control */ + + kDMA1_RST_SHIFT_RSTn = 131072 | 1U, /**< DMA1 reset control */ + kCMP_RST_SHIFT_RSTn = 131072 | 2U, /**< CMP reset control */ + kSDIO_RST_SHIFT_RSTn = 131072 | 3U, /**< SDIO reset control */ + kUSB1H_RST_SHIFT_RSTn = 131072 | 4U, /**< USBHS Host reset control */ + kUSB1D_RST_SHIFT_RSTn = 131072 | 5U, /**< USBHS Device reset control */ + kUSB1RAM_RST_SHIFT_RSTn = 131072 | 6U, /**< USB RAM reset control */ + kUSB1_RST_SHIFT_RSTn = 131072 | 7U, /**< USBHS reset control */ + kFREQME_RST_SHIFT_RSTn = 131072 | 8U, /**< FREQME reset control */ + kGPIO4_RST_SHIFT_RSTn = 131072 | 9U, /**< GPIO4 reset control */ + kGPIO5_RST_SHIFT_RSTn = 131072 | 10U, /**< GPIO5 reset control */ + kAES_RST_SHIFT_RSTn = 131072 | 11U, /**< AES reset control */ + kOTP_RST_SHIFT_RSTn = 131072 | 12U, /**< OTP reset control */ + kRNG_RST_SHIFT_RSTn = 131072 | 13U, /**< RNG reset control */ + kMUX1_RST_SHIFT_RSTn = 131072 | 14U, /**< Input mux1 reset control */ + kUSB0HMR_RST_SHIFT_RSTn = 131072 | 16U, /**< USB0HMR reset control */ + kUSB0HSL_RST_SHIFT_RSTn = 131072 | 17U, /**< USB0HSL reset control */ + kHASHCRYPT_RST_SHIFT_RSTn = 131072 | 18U, /**< HASHCRYPT reset control */ + kPOWERQUAD_RST_SHIFT_RSTn = 131072 | 19U, /**< PowerQuad reset control */ + kPLULUT_RST_SHIFT_RSTn = 131072 | 20U, /**< PLU LUT reset control */ + kCTIMER3_RST_SHIFT_RSTn = 131072 | 21U, /**< CTimer 3 reset control */ + kCTIMER4_RST_SHIFT_RSTn = 131072 | 22U, /**< CTimer 4 reset control */ + kPUF_RST_SHIFT_RSTn = 131072 | 23U, /**< PUF reset control */ + kCASPER_RST_SHIFT_RSTn = 131072 | 24U, /**< CASPER reset control */ + kCAP0_RST_SHIFT_RSTn = 131072 | 25U, /**< CASPER reset control */ + kOSTIMER1_RST_SHIFT_RSTn = 131072 | 26U, /**< OSTIMER1 reset control */ + kANALOGCTL_RST_SHIFT_RSTn = 131072 | 27U, /**< ANALOG_CTL reset control */ + kHSLSPI_RST_SHIFT_RSTn = 131072 | 28U, /**< HS LSPI reset control */ + kGPIOSEC_RST_SHIFT_RSTn = 131072 | 29U, /**< GPIO Secure reset control */ + kGPIOSECINT_RST_SHIFT_RSTn = 131072 | 30U, /**< GPIO Secure int reset control */ +} SYSCON_RSTn_t; + +/** Array initializers with peripheral reset bits **/ +#define ADC_RSTS \ + { \ + kADC0_RST_SHIFT_RSTn \ + } /* Reset bits for ADC peripheral */ +#define AES_RSTS \ + { \ + kAES_RST_SHIFT_RSTn \ + } /* Reset bits for AES peripheral */ +#define CRC_RSTS \ + { \ + kCRC_RST_SHIFT_RSTn \ + } /* Reset bits for CRC peripheral */ +#define CTIMER_RSTS \ + { \ + kCTIMER0_RST_SHIFT_RSTn, kCTIMER1_RST_SHIFT_RSTn, kCTIMER2_RST_SHIFT_RSTn, kCTIMER3_RST_SHIFT_RSTn, \ + kCTIMER4_RST_SHIFT_RSTn \ + } /* Reset bits for CTIMER peripheral */ +#define DMA_RSTS_N \ + { \ + kDMA0_RST_SHIFT_RSTn, kDMA1_RST_SHIFT_RSTn \ + } /* Reset bits for DMA peripheral */ + +#define FLEXCOMM_RSTS \ + { \ + kFC0_RST_SHIFT_RSTn, kFC1_RST_SHIFT_RSTn, kFC2_RST_SHIFT_RSTn, kFC3_RST_SHIFT_RSTn, kFC4_RST_SHIFT_RSTn, \ + kFC5_RST_SHIFT_RSTn, kFC6_RST_SHIFT_RSTn, kFC7_RST_SHIFT_RSTn, kHSLSPI_RST_SHIFT_RSTn \ + } /* Reset bits for FLEXCOMM peripheral */ +#define GINT_RSTS \ + { \ + kGINT_RST_SHIFT_RSTn, kGINT_RST_SHIFT_RSTn \ + } /* Reset bits for GINT peripheral. GINT0 & GINT1 share same slot */ +#define GPIO_RSTS_N \ + { \ + kGPIO0_RST_SHIFT_RSTn, kGPIO1_RST_SHIFT_RSTn, kGPIO2_RST_SHIFT_RSTn, kGPIO3_RST_SHIFT_RSTn, \ + kGPIO4_RST_SHIFT_RSTn, kGPIO5_RST_SHIFT_RSTn \ + } /* Reset bits for GPIO peripheral */ +#define INPUTMUX_RSTS \ + { \ + kMUX0_RST_SHIFT_RSTn, kMUX1_RST_SHIFT_RSTn \ + } /* Reset bits for INPUTMUX peripheral */ +#define IOCON_RSTS \ + { \ + kIOCON_RST_SHIFT_RSTn \ + } /* Reset bits for IOCON peripheral */ +#define FLASH_RSTS \ + { \ + kFLASH_RST_SHIFT_RSTn, kFMC_RST_SHIFT_RSTn \ + } /* Reset bits for Flash peripheral */ +#define MRT_RSTS \ + { \ + kMRT_RST_SHIFT_RSTn \ + } /* Reset bits for MRT peripheral */ +#define OTP_RSTS \ + { \ + kOTP_RST_SHIFT_RSTn \ + } /* Reset bits for OTP peripheral */ +#define PINT_RSTS \ + { \ + kPINT_RST_SHIFT_RSTn \ + } /* Reset bits for PINT peripheral */ +#define RNG_RSTS \ + { \ + kRNG_RST_SHIFT_RSTn \ + } /* Reset bits for RNG peripheral */ +#define SDIO_RST \ + { \ + kSDIO_RST_SHIFT_RSTn \ + } /* Reset bits for SDIO peripheral */ +#define SCT_RSTS \ + { \ + kSCT0_RST_SHIFT_RSTn \ + } /* Reset bits for SCT peripheral */ +#define SPIFI_RSTS \ + { \ + kSPIFI_RST_SHIFT_RSTn \ + } /* Reset bits for SPIFI peripheral */ +#define USB0D_RST \ + { \ + kUSB0D_RST_SHIFT_RSTn \ + } /* Reset bits for USB0D peripheral */ +#define USB0HMR_RST \ + { \ + kUSB0HMR_RST_SHIFT_RSTn \ + } /* Reset bits for USB0HMR peripheral */ +#define USB0HSL_RST \ + { \ + kUSB0HSL_RST_SHIFT_RSTn \ + } /* Reset bits for USB0HSL peripheral */ +#define USB1H_RST \ + { \ + kUSB1H_RST_SHIFT_RSTn \ + } /* Reset bits for USB1H peripheral */ +#define USB1D_RST \ + { \ + kUSB1D_RST_SHIFT_RSTn \ + } /* Reset bits for USB1D peripheral */ +#define USB1RAM_RST \ + { \ + kUSB1RAM_RST_SHIFT_RSTn \ + } /* Reset bits for USB1RAM peripheral */ +#define UTICK_RSTS \ + { \ + kUTICK_RST_SHIFT_RSTn \ + } /* Reset bits for UTICK peripheral */ +#define WWDT_RSTS \ + { \ + kWWDT_RST_SHIFT_RSTn \ + } /* Reset bits for WWDT peripheral */ +#define CAPT_RSTS_N \ + { \ + kCAP0_RST_SHIFT_RSTn \ + } /* Reset bits for CAPT peripheral */ +#define PLU_RSTS_N \ + { \ + kPLULUT_RST_SHIFT_RSTn \ + } /* Reset bits for PLU peripheral */ +#define OSTIMER_RSTS \ + { \ + kOSTIMER0_RST_SHIFT_RSTn \ + } /* Reset bits for OSTIMER peripheral */ +typedef SYSCON_RSTn_t reset_ip_name_t; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Assert reset to peripheral. + * + * Asserts reset signal to specified peripheral module. + * + * @param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register + * and reset bit position in the reset register. + */ +void RESET_SetPeripheralReset(reset_ip_name_t peripheral); + +/*! + * @brief Clear reset to peripheral. + * + * Clears reset signal to specified peripheral module, allows it to operate. + * + * @param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register + * and reset bit position in the reset register. + */ +void RESET_ClearPeripheralReset(reset_ip_name_t peripheral); + +/*! + * @brief Reset peripheral module. + * + * Reset peripheral module. + * + * @param peripheral Peripheral to reset. The enum argument contains encoding of reset register + * and reset bit position in the reset register. + */ +void RESET_PeripheralReset(reset_ip_name_t peripheral); + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /* _FSL_RESET_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_rng.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_rng.c new file mode 100644 index 000000000..5da5be410 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_rng.c @@ -0,0 +1,96 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_rng.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.rng_1" +#endif + +/******************************************************************************* + * Definitions + *******************************************************************************/ + +/******************************************************************************* + * Prototypes + *******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +void RNG_Init(RNG_Type *base) +{ + /* Clear ring oscilator disable bit*/ + PMC->PDRUNCFGCLR0 = PMC_PDRUNCFG0_PDEN_RNG_MASK; +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + CLOCK_EnableClock(kCLOCK_Rng); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + /* Clear POWERDOWN bit to enable RNG */ + base->POWERDOWN &= ~RNG_POWERDOWN_POWERDOWN_MASK; +} + +void RNG_Deinit(RNG_Type *base) +{ + /* Set ring oscilator disable bit*/ + PMC->PDRUNCFGSET0 = PMC_PDRUNCFG0_PDEN_RNG_MASK; + /* Set POWERDOWN bit to disable RNG */ + base->POWERDOWN |= RNG_POWERDOWN_POWERDOWN_MASK; +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + CLOCK_DisableClock(kCLOCK_Rng); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +status_t RNG_GetRandomData(RNG_Type *base, void *data, size_t dataSize) +{ + status_t result = kStatus_Fail; + uint32_t random32; + uint32_t randomSize; + uint8_t *pRandom; + uint8_t *pData = (uint8_t *)data; + uint32_t i; + + /* Check input parameters.*/ + if (!(base && data && dataSize)) + { + result = kStatus_InvalidArgument; + } + else + { + /* Check that ring oscilator is enabled */ + if (!(PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_RNG_MASK)) + { + do + { + /* Read Entropy.*/ + random32 = base->RANDOM_NUMBER; + pRandom = (uint8_t *)&random32; + + if (dataSize < sizeof(random32)) + { + randomSize = dataSize; + } + else + { + randomSize = sizeof(random32); + } + + for (i = 0; i < randomSize; i++) + { + *pData++ = *pRandom++; + } + + dataSize -= randomSize; + } while (dataSize > 0); + + result = kStatus_Success; + } + } + + return result; +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_rng.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_rng.h new file mode 100644 index 000000000..e5a7e90c4 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_rng.h @@ -0,0 +1,95 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_RNG_DRIVER_H_ +#define _FSL_RNG_DRIVER_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup rng + * @{ + */ + +/******************************************************************************* + * Definitions + *******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief RNG driver version. Version 2.0.0. + * + * Current version: 2.0.0 + * + * Change log: + * - Version 2.0.0 + * - Initial version + */ +#define FSL_RNG_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/******************************************************************************* + * API + *******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Initializes the RNG. + * + * This function initializes the RNG. + * When called, the RNG module and ring oscillator is enabled. + * + * @param base RNG base address + * @param userConfig Pointer to the initialization configuration structure. + * @return If successful, returns the kStatus_RNG_Success. Otherwise, it returns an error. + */ +void RNG_Init(RNG_Type *base); + +/*! + * @brief Shuts down the RNG. + * + * This function shuts down the RNG. + * + * @param base RNG base address. + */ +void RNG_Deinit(RNG_Type *base); + +/*! + * @brief Gets random data. + * + * This function gets random data from the RNG. + * + * @param base RNG base address. + * @param data Pointer address used to store random data. + * @param dataSize Size of the buffer pointed by the data parameter. + * @return random data + */ +status_t RNG_GetRandomData(RNG_Type *base, void *data, size_t data_size); + +/*! + * @brief Returns random 32-bit number. + * + * This function gets random number from the RNG. + * + * @param base RNG base address. + * @return random number + */ +static inline uint32_t RNG_GetRandomWord(RNG_Type *base) +{ + return base->RANDOM_NUMBER; +} + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /*_FSL_RNG_H_*/ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_rtc.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_rtc.c new file mode 100644 index 000000000..49915aec4 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_rtc.c @@ -0,0 +1,321 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_rtc.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpc_rtc" +#endif + +#define SECONDS_IN_A_DAY (86400U) +#define SECONDS_IN_A_HOUR (3600U) +#define SECONDS_IN_A_MINUTE (60U) +#define DAYS_IN_A_YEAR (365U) +#define YEAR_RANGE_START (1970U) +#define YEAR_RANGE_END (2099U) + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Checks whether the date and time passed in is valid + * + * @param datetime Pointer to structure where the date and time details are stored + * + * @return Returns false if the date & time details are out of range; true if in range + */ +static bool RTC_CheckDatetimeFormat(const rtc_datetime_t *datetime); + +/*! + * @brief Converts time data from datetime to seconds + * + * @param datetime Pointer to datetime structure where the date and time details are stored + * + * @return The result of the conversion in seconds + */ +static uint32_t RTC_ConvertDatetimeToSeconds(const rtc_datetime_t *datetime); + +/*! + * @brief Converts time data from seconds to a datetime structure + * + * @param seconds Seconds value that needs to be converted to datetime format + * @param datetime Pointer to the datetime structure where the result of the conversion is stored + */ +static void RTC_ConvertSecondsToDatetime(uint32_t seconds, rtc_datetime_t *datetime); + +/******************************************************************************* + * Code + ******************************************************************************/ +static bool RTC_CheckDatetimeFormat(const rtc_datetime_t *datetime) +{ + assert(datetime); + + /* Table of days in a month for a non leap year. First entry in the table is not used, + * valid months start from 1 + */ + uint8_t daysPerMonth[] = {0U, 31U, 28U, 31U, 30U, 31U, 30U, 31U, 31U, 30U, 31U, 30U, 31U}; + + /* Check year, month, hour, minute, seconds */ + if ((datetime->year < YEAR_RANGE_START) || (datetime->year > YEAR_RANGE_END) || (datetime->month > 12U) || + (datetime->month < 1U) || (datetime->hour >= 24U) || (datetime->minute >= 60U) || (datetime->second >= 60U)) + { + /* If not correct then error*/ + return false; + } + + /* Adjust the days in February for a leap year */ + if ((((datetime->year & 3U) == 0) && (datetime->year % 100 != 0)) || (datetime->year % 400 == 0)) + { + daysPerMonth[2] = 29U; + } + + /* Check the validity of the day */ + if ((datetime->day > daysPerMonth[datetime->month]) || (datetime->day < 1U)) + { + return false; + } + + return true; +} + +static uint32_t RTC_ConvertDatetimeToSeconds(const rtc_datetime_t *datetime) +{ + assert(datetime); + + /* Number of days from begin of the non Leap-year*/ + /* Number of days from begin of the non Leap-year*/ + uint16_t monthDays[] = {0U, 0U, 31U, 59U, 90U, 120U, 151U, 181U, 212U, 243U, 273U, 304U, 334U}; + uint32_t seconds; + + /* Compute number of days from 1970 till given year*/ + seconds = (datetime->year - 1970U) * DAYS_IN_A_YEAR; + /* Add leap year days */ + seconds += ((datetime->year / 4) - (1970U / 4)); + /* Add number of days till given month*/ + seconds += monthDays[datetime->month]; + /* Add days in given month. We subtract the current day as it is + * represented in the hours, minutes and seconds field*/ + seconds += (datetime->day - 1); + /* For leap year if month less than or equal to Febraury, decrement day counter*/ + if ((!(datetime->year & 3U)) && (datetime->month <= 2U)) + { + seconds--; + } + + seconds = (seconds * SECONDS_IN_A_DAY) + (datetime->hour * SECONDS_IN_A_HOUR) + + (datetime->minute * SECONDS_IN_A_MINUTE) + datetime->second; + + return seconds; +} + +static void RTC_ConvertSecondsToDatetime(uint32_t seconds, rtc_datetime_t *datetime) +{ + assert(datetime); + + uint32_t x; + uint32_t secondsRemaining, days; + uint16_t daysInYear; + /* Table of days in a month for a non leap year. First entry in the table is not used, + * valid months start from 1 + */ + uint8_t daysPerMonth[] = {0U, 31U, 28U, 31U, 30U, 31U, 30U, 31U, 31U, 30U, 31U, 30U, 31U}; + + /* Start with the seconds value that is passed in to be converted to date time format */ + secondsRemaining = seconds; + + /* Calcuate the number of days, we add 1 for the current day which is represented in the + * hours and seconds field + */ + days = secondsRemaining / SECONDS_IN_A_DAY + 1; + + /* Update seconds left*/ + secondsRemaining = secondsRemaining % SECONDS_IN_A_DAY; + + /* Calculate the datetime hour, minute and second fields */ + datetime->hour = secondsRemaining / SECONDS_IN_A_HOUR; + secondsRemaining = secondsRemaining % SECONDS_IN_A_HOUR; + datetime->minute = secondsRemaining / 60U; + datetime->second = secondsRemaining % SECONDS_IN_A_MINUTE; + + /* Calculate year */ + daysInYear = DAYS_IN_A_YEAR; + datetime->year = YEAR_RANGE_START; + while (days > daysInYear) + { + /* Decrease day count by a year and increment year by 1 */ + days -= daysInYear; + datetime->year++; + + /* Adjust the number of days for a leap year */ + if (datetime->year & 3U) + { + daysInYear = DAYS_IN_A_YEAR; + } + else + { + daysInYear = DAYS_IN_A_YEAR + 1; + } + } + + /* Adjust the days in February for a leap year */ + if (!(datetime->year & 3U)) + { + daysPerMonth[2] = 29U; + } + + for (x = 1U; x <= 12U; x++) + { + if (days <= daysPerMonth[x]) + { + datetime->month = x; + break; + } + else + { + days -= daysPerMonth[x]; + } + } + + datetime->day = days; +} + +/*! + * brief Ungates the RTC clock and enables the RTC oscillator. + * + * note This API should be called at the beginning of the application using the RTC driver. + * + * param base RTC peripheral base address + */ +void RTC_Init(RTC_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the RTC peripheral clock */ + CLOCK_EnableClock(kCLOCK_Rtc); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_FEATURE_RTC_HAS_NO_RESET) && FSL_FEATURE_RTC_HAS_NO_RESET) + RESET_PeripheralReset(kRTC_RST_SHIFT_RSTn); +#endif + /* Make sure the reset bit is cleared */ + base->CTRL &= ~RTC_CTRL_SWRESET_MASK; + +#if !(defined(FSL_FEATURE_RTC_HAS_NO_OSC_PD) && FSL_FEATURE_RTC_HAS_NO_OSC_PD) + /* Make sure the RTC OSC is powered up */ + base->CTRL &= ~RTC_CTRL_RTC_OSC_PD_MASK; +#endif +} + +/*! + * brief Sets the RTC date and time according to the given time structure. + * + * The RTC counter must be stopped prior to calling this function as writes to the RTC + * seconds register will fail if the RTC counter is running. + * + * param base RTC peripheral base address + * param datetime Pointer to structure where the date and time details to set are stored + * + * return kStatus_Success: Success in setting the time and starting the RTC + * kStatus_InvalidArgument: Error because the datetime format is incorrect + */ +status_t RTC_SetDatetime(RTC_Type *base, const rtc_datetime_t *datetime) +{ + assert(datetime); + + /* Return error if the time provided is not valid */ + if (!(RTC_CheckDatetimeFormat(datetime))) + { + return kStatus_InvalidArgument; + } + + /* Set time in seconds */ + base->COUNT = RTC_ConvertDatetimeToSeconds(datetime); + + return kStatus_Success; +} + +/*! + * brief Gets the RTC time and stores it in the given time structure. + * + * param base RTC peripheral base address + * param datetime Pointer to structure where the date and time details are stored. + */ +void RTC_GetDatetime(RTC_Type *base, rtc_datetime_t *datetime) +{ + assert(datetime); + + uint32_t seconds = 0; + + seconds = base->COUNT; + RTC_ConvertSecondsToDatetime(seconds, datetime); +} + +/*! + * brief Sets the RTC alarm time + * + * The function checks whether the specified alarm time is greater than the present + * time. If not, the function does not set the alarm and returns an error. + * + * param base RTC peripheral base address + * param alarmTime Pointer to structure where the alarm time is stored. + * + * return kStatus_Success: success in setting the RTC alarm + * kStatus_InvalidArgument: Error because the alarm datetime format is incorrect + * kStatus_Fail: Error because the alarm time has already passed + */ +status_t RTC_SetAlarm(RTC_Type *base, const rtc_datetime_t *alarmTime) +{ + assert(alarmTime); + + uint32_t alarmSeconds = 0; + uint32_t currSeconds = 0; + + /* Return error if the alarm time provided is not valid */ + if (!(RTC_CheckDatetimeFormat(alarmTime))) + { + return kStatus_InvalidArgument; + } + + alarmSeconds = RTC_ConvertDatetimeToSeconds(alarmTime); + + /* Get the current time */ + currSeconds = base->COUNT; + + /* Return error if the alarm time has passed */ + if (alarmSeconds < currSeconds) + { + return kStatus_Fail; + } + + /* Set alarm in seconds*/ + base->MATCH = alarmSeconds; + + return kStatus_Success; +} + +/*! + * brief Returns the RTC alarm time. + * + * param base RTC peripheral base address + * param datetime Pointer to structure where the alarm date and time details are stored. + */ +void RTC_GetAlarm(RTC_Type *base, rtc_datetime_t *datetime) +{ + assert(datetime); + + uint32_t alarmSeconds = 0; + + /* Get alarm in seconds */ + alarmSeconds = base->MATCH; + + RTC_ConvertSecondsToDatetime(alarmSeconds, datetime); +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_rtc.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_rtc.h new file mode 100644 index 000000000..ebffd9c52 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_rtc.h @@ -0,0 +1,318 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_RTC_H_ +#define _FSL_RTC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup rtc + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_RTC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */ +/*@}*/ + +/*! @brief List of RTC interrupts */ +typedef enum _rtc_interrupt_enable +{ + kRTC_AlarmInterruptEnable = RTC_CTRL_ALARMDPD_EN_MASK, /*!< Alarm interrupt.*/ + kRTC_WakeupInterruptEnable = RTC_CTRL_WAKEDPD_EN_MASK /*!< Wake-up interrupt.*/ +} rtc_interrupt_enable_t; + +/*! @brief List of RTC flags */ +typedef enum _rtc_status_flags +{ + kRTC_AlarmFlag = RTC_CTRL_ALARM1HZ_MASK, /*!< Alarm flag*/ + kRTC_WakeupFlag = RTC_CTRL_WAKE1KHZ_MASK /*!< 1kHz wake-up timer flag*/ +} rtc_status_flags_t; + +/*! @brief Structure is used to hold the date and time */ +typedef struct _rtc_datetime +{ + uint16_t year; /*!< Range from 1970 to 2099.*/ + uint8_t month; /*!< Range from 1 to 12.*/ + uint8_t day; /*!< Range from 1 to 31 (depending on month).*/ + uint8_t hour; /*!< Range from 0 to 23.*/ + uint8_t minute; /*!< Range from 0 to 59.*/ + uint8_t second; /*!< Range from 0 to 59.*/ +} rtc_datetime_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Ungates the RTC clock and enables the RTC oscillator. + * + * @note This API should be called at the beginning of the application using the RTC driver. + * + * @param base RTC peripheral base address + */ +void RTC_Init(RTC_Type *base); + +/*! + * @brief Stop the timer and gate the RTC clock + * + * @param base RTC peripheral base address + */ +static inline void RTC_Deinit(RTC_Type *base) +{ + /* Stop the RTC timer */ + base->CTRL &= ~RTC_CTRL_RTC_EN_MASK; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Gate the module clock */ + CLOCK_DisableClock(kCLOCK_Rtc); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! @}*/ + +/*! + * @name Current Time & Alarm + * @{ + */ + +/*! + * @brief Sets the RTC date and time according to the given time structure. + * + * The RTC counter must be stopped prior to calling this function as writes to the RTC + * seconds register will fail if the RTC counter is running. + * + * @param base RTC peripheral base address + * @param datetime Pointer to structure where the date and time details to set are stored + * + * @return kStatus_Success: Success in setting the time and starting the RTC + * kStatus_InvalidArgument: Error because the datetime format is incorrect + */ +status_t RTC_SetDatetime(RTC_Type *base, const rtc_datetime_t *datetime); + +/*! + * @brief Gets the RTC time and stores it in the given time structure. + * + * @param base RTC peripheral base address + * @param datetime Pointer to structure where the date and time details are stored. + */ +void RTC_GetDatetime(RTC_Type *base, rtc_datetime_t *datetime); + +/*! + * @brief Sets the RTC alarm time + * + * The function checks whether the specified alarm time is greater than the present + * time. If not, the function does not set the alarm and returns an error. + * + * @param base RTC peripheral base address + * @param alarmTime Pointer to structure where the alarm time is stored. + * + * @return kStatus_Success: success in setting the RTC alarm + * kStatus_InvalidArgument: Error because the alarm datetime format is incorrect + * kStatus_Fail: Error because the alarm time has already passed + */ +status_t RTC_SetAlarm(RTC_Type *base, const rtc_datetime_t *alarmTime); + +/*! + * @brief Returns the RTC alarm time. + * + * @param base RTC peripheral base address + * @param datetime Pointer to structure where the alarm date and time details are stored. + */ +void RTC_GetAlarm(RTC_Type *base, rtc_datetime_t *datetime); + +/*! @}*/ + +/*! + * @brief Enable the RTC high resolution timer and set the wake-up time. + * + * @param base RTC peripheral base address + * @param wakeupValue The value to be loaded into the RTC WAKE register + */ +static inline void RTC_SetWakeupCount(RTC_Type *base, uint16_t wakeupValue) +{ + /* Enable the 1kHz RTC timer */ + base->CTRL |= RTC_CTRL_RTC1KHZ_EN_MASK; + + /* Set the start count value into the wake-up timer */ + base->WAKE = wakeupValue; +} + +/*! + * @brief Read actual RTC counter value. + * + * @param base RTC peripheral base address + */ +static inline uint16_t RTC_GetWakeupCount(RTC_Type *base) +{ + /* Read wake-up counter */ + return RTC_WAKE_VAL(base->WAKE); +} + +/*! + * @name Interrupt Interface + * @{ + */ + +/*! + * @brief Enables the selected RTC interrupts. + * + * @param base RTC peripheral base address + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::rtc_interrupt_enable_t + */ +static inline void RTC_EnableInterrupts(RTC_Type *base, uint32_t mask) +{ + uint32_t reg = base->CTRL; + + /* Clear flag bits to prevent accidentally clearing anything when writing back */ + reg &= ~(RTC_CTRL_ALARM1HZ_MASK | RTC_CTRL_WAKE1KHZ_MASK); + reg |= mask; + + base->CTRL = reg; +} + +/*! + * @brief Disables the selected RTC interrupts. + * + * @param base RTC peripheral base address + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::rtc_interrupt_enable_t + */ +static inline void RTC_DisableInterrupts(RTC_Type *base, uint32_t mask) +{ + uint32_t reg = base->CTRL; + + /* Clear flag bits to prevent accidentally clearing anything when writing back */ + reg &= ~(RTC_CTRL_ALARM1HZ_MASK | RTC_CTRL_WAKE1KHZ_MASK | mask); + + base->CTRL = reg; +} + +/*! + * @brief Gets the enabled RTC interrupts. + * + * @param base RTC peripheral base address + * + * @return The enabled interrupts. This is the logical OR of members of the + * enumeration ::rtc_interrupt_enable_t + */ +static inline uint32_t RTC_GetEnabledInterrupts(RTC_Type *base) +{ + return (base->CTRL & (RTC_CTRL_ALARMDPD_EN_MASK | RTC_CTRL_WAKEDPD_EN_MASK)); +} + +/*! @}*/ + +/*! + * @name Status Interface + * @{ + */ + +/*! + * @brief Gets the RTC status flags + * + * @param base RTC peripheral base address + * + * @return The status flags. This is the logical OR of members of the + * enumeration ::rtc_status_flags_t + */ +static inline uint32_t RTC_GetStatusFlags(RTC_Type *base) +{ + return (base->CTRL & (RTC_CTRL_ALARM1HZ_MASK | RTC_CTRL_WAKE1KHZ_MASK)); +} + +/*! + * @brief Clears the RTC status flags. + * + * @param base RTC peripheral base address + * @param mask The status flags to clear. This is a logical OR of members of the + * enumeration ::rtc_status_flags_t + */ +static inline void RTC_ClearStatusFlags(RTC_Type *base, uint32_t mask) +{ + uint32_t reg = base->CTRL; + + /* Clear flag bits to prevent accidentally clearing anything when writing back */ + reg &= ~(RTC_CTRL_ALARM1HZ_MASK | RTC_CTRL_WAKE1KHZ_MASK); + + /* Write 1 to the flags we wish to clear */ + reg |= mask; + + base->CTRL = reg; +} + +/*! @}*/ + +/*! + * @name Timer Start and Stop + * @{ + */ + +/*! + * @brief Starts the RTC time counter. + * + * After calling this function, the timer counter increments once a second provided SR[TOF] or + * SR[TIF] are not set. + * + * @param base RTC peripheral base address + */ +static inline void RTC_StartTimer(RTC_Type *base) +{ + base->CTRL |= RTC_CTRL_RTC_EN_MASK; +} + +/*! + * @brief Stops the RTC time counter. + * + * RTC's seconds register can be written to only when the timer is stopped. + * + * @param base RTC peripheral base address + */ +static inline void RTC_StopTimer(RTC_Type *base) +{ + base->CTRL &= ~RTC_CTRL_RTC_EN_MASK; +} + +/*! @}*/ + +/*! + * @brief Performs a software reset on the RTC module. + * + * This resets all RTC registers to their reset value. The bit is cleared by software explicitly clearing it. + * + * @param base RTC peripheral base address + */ +static inline void RTC_Reset(RTC_Type *base) +{ + base->CTRL |= RTC_CTRL_SWRESET_MASK; + base->CTRL &= ~RTC_CTRL_SWRESET_MASK; +} + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_RTC_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_sctimer.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_sctimer.c new file mode 100644 index 000000000..ab89d3ff4 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_sctimer.c @@ -0,0 +1,715 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_sctimer.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.sctimer" +#endif + +/*! @brief Typedef for interrupt handler. */ +typedef void (*sctimer_isr_t)(SCT_Type *base); + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Gets the instance from the base address + * + * @param base SCTimer peripheral base address + * + * @return The SCTimer instance + */ +static uint32_t SCTIMER_GetInstance(SCT_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to SCT bases for each instance. */ +static SCT_Type *const s_sctBases[] = SCT_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to SCT clocks for each instance. */ +static const clock_ip_name_t s_sctClocks[] = SCT_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) +#if defined(FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET) && FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET +/*! @brief Pointers to SCT resets for each instance, writing a zero asserts the reset */ +static const reset_ip_name_t s_sctResets[] = SCT_RSTS_N; +#else +/*! @brief Pointers to SCT resets for each instance, writing a one asserts the reset */ +static const reset_ip_name_t s_sctResets[] = SCT_RSTS; +#endif +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + +/*!< @brief SCTimer event Callback function. */ +static sctimer_event_callback_t s_eventCallback[FSL_FEATURE_SCT_NUMBER_OF_EVENTS]; + +/*!< @brief Keep track of SCTimer event number */ +static uint32_t s_currentEvent; + +/*!< @brief Keep track of SCTimer state number */ +static uint32_t s_currentState; + +/*!< @brief Keep track of SCTimer match/capture register number */ +static uint32_t s_currentMatch; + +/*! @brief Pointer to SCTimer IRQ handler */ +static sctimer_isr_t s_sctimerIsr; + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t SCTIMER_GetInstance(SCT_Type *base) +{ + uint32_t instance; + uint32_t sctArrayCount = (sizeof(s_sctBases) / sizeof(s_sctBases[0])); + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < sctArrayCount; instance++) + { + if (s_sctBases[instance] == base) + { + break; + } + } + + assert(instance < sctArrayCount); + + return instance; +} + +/*! + * brief Ungates the SCTimer clock and configures the peripheral for basic operation. + * + * note This API should be called at the beginning of the application using the SCTimer driver. + * + * param base SCTimer peripheral base address + * param config Pointer to the user configuration structure. + * + * return kStatus_Success indicates success; Else indicates failure. + */ +status_t SCTIMER_Init(SCT_Type *base, const sctimer_config_t *config) +{ + assert(config); + uint32_t i; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the SCTimer clock*/ + CLOCK_EnableClock(s_sctClocks[SCTIMER_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) + /* Reset the module. */ + RESET_PeripheralReset(s_sctResets[SCTIMER_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + + /* Setup the counter operation. For Current Driver interface SCTIMER_Init don't know detail + * frequency of input clock, but User know it. So the INSYNC have to set by user level. */ + base->CONFIG = SCT_CONFIG_CKSEL(config->clockSelect) | SCT_CONFIG_CLKMODE(config->clockMode) | + SCT_CONFIG_UNIFY(config->enableCounterUnify) | SCT_CONFIG_INSYNC(config->inputsync); + + /* Write to the control register, clear the counter and keep the counters halted */ + base->CTRL = SCT_CTRL_BIDIR_L(config->enableBidirection_l) | SCT_CTRL_PRE_L(config->prescale_l) | + SCT_CTRL_CLRCTR_L_MASK | SCT_CTRL_HALT_L_MASK; + + if (!(config->enableCounterUnify)) + { + base->CTRL |= SCT_CTRL_BIDIR_H(config->enableBidirection_h) | SCT_CTRL_PRE_H(config->prescale_h) | + SCT_CTRL_CLRCTR_H_MASK | SCT_CTRL_HALT_H_MASK; + } + + /* Initial state of channel output */ + base->OUTPUT = config->outInitState; + + /* Clear the global variables */ + s_currentEvent = 0; + s_currentState = 0; + s_currentMatch = 0; + + /* Clear the callback array */ + for (i = 0; i < FSL_FEATURE_SCT_NUMBER_OF_EVENTS; i++) + { + s_eventCallback[i] = NULL; + } + + /* Save interrupt handler */ + s_sctimerIsr = SCTIMER_EventHandleIRQ; + + return kStatus_Success; +} + +/*! + * brief Gates the SCTimer clock. + * + * param base SCTimer peripheral base address + */ +void SCTIMER_Deinit(SCT_Type *base) +{ + /* Halt the counters */ + base->CTRL |= (SCT_CTRL_HALT_L_MASK | SCT_CTRL_HALT_H_MASK); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable the SCTimer clock*/ + CLOCK_DisableClock(s_sctClocks[SCTIMER_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Fills in the SCTimer configuration structure with the default settings. + * + * The default values are: + * code + * config->enableCounterUnify = true; + * config->clockMode = kSCTIMER_System_ClockMode; + * config->clockSelect = kSCTIMER_Clock_On_Rise_Input_0; + * config->enableBidirection_l = false; + * config->enableBidirection_h = false; + * config->prescale_l = 0U; + * config->prescale_h = 0U; + * config->outInitState = 0U; + * config->inputsync = 0xFU; + * endcode + * param config Pointer to the user configuration structure. + */ +void SCTIMER_GetDefaultConfig(sctimer_config_t *config) +{ + assert(config); + + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + + /* SCT operates as a unified 32-bit counter */ + config->enableCounterUnify = true; + /* System clock clocks the entire SCT module */ + config->clockMode = kSCTIMER_System_ClockMode; + /* This is used only by certain clock modes */ + config->clockSelect = kSCTIMER_Clock_On_Rise_Input_0; + /* Up count mode only for the unified counter */ + config->enableBidirection_l = false; + /* Up count mode only for Counte_H */ + config->enableBidirection_h = false; + /* Prescale factor of 1 */ + config->prescale_l = 0U; + /* Prescale factor of 1 for Counter_H*/ + config->prescale_h = 0U; + /* Clear outputs */ + config->outInitState = 0U; + /* Default value is 0xFU, it can be clear as 0 when speical conditions met. + * Condition can be clear as 0: (for all Clock Modes): + * (1) The corresponding input is already synchronous to the SCTimer/PWM clock. + * (2) The SCTimer/PWM clock frequency does not exceed 100 MHz. + * Note: The SCTimer/PWM clock is the bus/system clock for CKMODE 0-2 or asynchronous input + * clock for CKMODE3. + * Another condition can be clear as 0: (for CKMODE2 only) + * (1) The corresponding input is synchronous to the designated CKMODE2 input clock. + * (2) The CKMODE2 input clock frequency is less than one-third the frequency of the bus/system clock. + * Default value set as 0U, input0~input3 are set as bypasses. */ + config->inputsync = 0xFU; +} + +/*! + * brief Configures the PWM signal parameters. + * + * Call this function to configure the PWM signal period, mode, duty cycle, and edge. This + * function will create 2 events; one of the events will trigger on match with the pulse value + * and the other will trigger when the counter matches the PWM period. The PWM period event is + * also used as a limit event to reset the counter or change direction. Both events are enabled + * for the same state. The state number can be retrieved by calling the function + * SCTIMER_GetCurrentStateNumber(). + * The counter is set to operate as one 32-bit counter (unify bit is set to 1). + * The counter operates in bi-directional mode when generating a center-aligned PWM. + * + * note When setting PWM output from multiple output pins, they all should use the same PWM mode + * i.e all PWM's should be either edge-aligned or center-aligned. + * When using this API, the PWM signal frequency of all the initialized channels must be the same. + * Otherwise all the initialized channels' PWM signal frequency is equal to the last call to the + * API's pwmFreq_Hz. + * + * param base SCTimer peripheral base address + * param pwmParams PWM parameters to configure the output + * param mode PWM operation mode, options available in enumeration ::sctimer_pwm_mode_t + * param pwmFreq_Hz PWM signal frequency in Hz + * param srcClock_Hz SCTimer counter clock in Hz + * param event Pointer to a variable where the PWM period event number is stored + * + * return kStatus_Success on success + * kStatus_Fail If we have hit the limit in terms of number of events created or if + * an incorrect PWM dutycylce is passed in. + */ +status_t SCTIMER_SetupPwm(SCT_Type *base, + const sctimer_pwm_signal_param_t *pwmParams, + sctimer_pwm_mode_t mode, + uint32_t pwmFreq_Hz, + uint32_t srcClock_Hz, + uint32_t *event) +{ + assert(pwmParams); + assert(srcClock_Hz); + assert(pwmFreq_Hz); + assert(pwmParams->output < FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS); + + uint32_t period, pulsePeriod = 0; + uint32_t sctClock = srcClock_Hz / (((base->CTRL & SCT_CTRL_PRE_L_MASK) >> SCT_CTRL_PRE_L_SHIFT) + 1); + uint32_t periodEvent = 0, pulseEvent = 0; + uint32_t reg; + + /* This function will create 2 events, return an error if we do not have enough events available */ + if ((s_currentEvent + 2) > FSL_FEATURE_SCT_NUMBER_OF_EVENTS) + { + return kStatus_Fail; + } + + if (pwmParams->dutyCyclePercent == 0) + { + return kStatus_Fail; + } + + /* Set unify bit to operate in 32-bit counter mode */ + base->CONFIG |= SCT_CONFIG_UNIFY_MASK; + + /* Use bi-directional mode for center-aligned PWM */ + if (mode == kSCTIMER_CenterAlignedPwm) + { + base->CTRL |= SCT_CTRL_BIDIR_L_MASK; + } + + /* Calculate PWM period match value */ + if (mode == kSCTIMER_EdgeAlignedPwm) + { + period = (sctClock / pwmFreq_Hz) - 1; + } + else + { + period = sctClock / (pwmFreq_Hz * 2); + } + + /* Calculate pulse width match value */ + pulsePeriod = (period * pwmParams->dutyCyclePercent) / 100; + + /* For 100% dutycyle, make pulse period greater than period so the event will never occur */ + if (pwmParams->dutyCyclePercent >= 100) + { + pulsePeriod = period + 2; + } + + /* Schedule an event when we reach the PWM period */ + SCTIMER_CreateAndScheduleEvent(base, kSCTIMER_MatchEventOnly, period, 0, kSCTIMER_Counter_L, &periodEvent); + + /* Schedule an event when we reach the pulse width */ + SCTIMER_CreateAndScheduleEvent(base, kSCTIMER_MatchEventOnly, pulsePeriod, 0, kSCTIMER_Counter_L, &pulseEvent); + + /* Reset the counter when we reach the PWM period */ + SCTIMER_SetupCounterLimitAction(base, kSCTIMER_Counter_L, periodEvent); + + /* Return the period event to the user */ + *event = periodEvent; + + /* For high-true level */ + if (pwmParams->level == kSCTIMER_HighTrue) + { + /* Set the initial output level to low which is the inactive state */ + base->OUTPUT &= ~(1U << pwmParams->output); + + if (mode == kSCTIMER_EdgeAlignedPwm) + { + /* Set the output when we reach the PWM period */ + SCTIMER_SetupOutputSetAction(base, pwmParams->output, periodEvent); + /* Clear the output when we reach the PWM pulse value */ + SCTIMER_SetupOutputClearAction(base, pwmParams->output, pulseEvent); + } + else + { + /* Clear the output when we reach the PWM pulse event */ + SCTIMER_SetupOutputClearAction(base, pwmParams->output, pulseEvent); + /* Reverse output when down counting */ + reg = base->OUTPUTDIRCTRL; + reg &= ~(SCT_OUTPUTDIRCTRL_SETCLR0_MASK << (2 * pwmParams->output)); + reg |= (1U << (2 * pwmParams->output)); + base->OUTPUTDIRCTRL = reg; + } + } + /* For low-true level */ + else + { + /* Set the initial output level to high which is the inactive state */ + base->OUTPUT |= (1U << pwmParams->output); + + if (mode == kSCTIMER_EdgeAlignedPwm) + { + /* Clear the output when we reach the PWM period */ + SCTIMER_SetupOutputClearAction(base, pwmParams->output, periodEvent); + /* Set the output when we reach the PWM pulse value */ + SCTIMER_SetupOutputSetAction(base, pwmParams->output, pulseEvent); + } + else + { + /* Set the output when we reach the PWM pulse event */ + SCTIMER_SetupOutputSetAction(base, pwmParams->output, pulseEvent); + /* Reverse output when down counting */ + reg = base->OUTPUTDIRCTRL; + reg &= ~(SCT_OUTPUTDIRCTRL_SETCLR0_MASK << (2 * pwmParams->output)); + reg |= (1U << (2 * pwmParams->output)); + base->OUTPUTDIRCTRL = reg; + } + } + + return kStatus_Success; +} + +/*! + * brief Updates the duty cycle of an active PWM signal. + * + * param base SCTimer peripheral base address + * param output The output to configure + * param dutyCyclePercent New PWM pulse width; the value should be between 1 to 100 + * param event Event number associated with this PWM signal. This was returned to the user by the + * function SCTIMER_SetupPwm(). + */ +void SCTIMER_UpdatePwmDutycycle(SCT_Type *base, sctimer_out_t output, uint8_t dutyCyclePercent, uint32_t event) + +{ + assert(dutyCyclePercent > 0); + assert(output < FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS); + + uint32_t periodMatchReg, pulseMatchReg; + uint32_t pulsePeriod = 0, period; + + /* Retrieve the match register number for the PWM period */ + periodMatchReg = base->EVENT[event].CTRL & SCT_EVENT_CTRL_MATCHSEL_MASK; + + /* Retrieve the match register number for the PWM pulse period */ + pulseMatchReg = base->EVENT[event + 1].CTRL & SCT_EVENT_CTRL_MATCHSEL_MASK; + + period = base->SCTMATCH[periodMatchReg]; + + /* Calculate pulse width match value */ + pulsePeriod = (period * dutyCyclePercent) / 100; + + /* For 100% dutycyle, make pulse period greater than period so the event will never occur */ + if (dutyCyclePercent >= 100) + { + pulsePeriod = period + 2; + } + + /* Stop the counter before updating match register */ + SCTIMER_StopTimer(base, kSCTIMER_Counter_L); + + /* Update dutycycle */ + base->SCTMATCH[pulseMatchReg] = SCT_SCTMATCH_MATCHn_L(pulsePeriod); + base->SCTMATCHREL[pulseMatchReg] = SCT_SCTMATCHREL_RELOADn_L(pulsePeriod); + + /* Restart the counter */ + SCTIMER_StartTimer(base, kSCTIMER_Counter_L); +} + +/*! + * brief Create an event that is triggered on a match or IO and schedule in current state. + * + * This function will configure an event using the options provided by the user. If the event type uses + * the counter match, then the function will set the user provided match value into a match register + * and put this match register number into the event control register. + * The event is enabled for the current state and the event number is increased by one at the end. + * The function returns the event number; this event number can be used to configure actions to be + * done when this event is triggered. + * + * param base SCTimer peripheral base address + * param howToMonitor Event type; options are available in the enumeration ::sctimer_interrupt_enable_t + * param matchValue The match value that will be programmed to a match register + * param whichIO The input or output that will be involved in event triggering. This field + * is ignored if the event type is "match only" + * param whichCounter SCTimer counter to use when operating in 16-bit mode. In 32-bit mode, this + * field has no meaning as we have only 1 unified counter; hence ignored. + * param event Pointer to a variable where the new event number is stored + * + * return kStatus_Success on success + * kStatus_Error if we have hit the limit in terms of number of events created or + if we have reached the limit in terms of number of match registers + */ +status_t SCTIMER_CreateAndScheduleEvent(SCT_Type *base, + sctimer_event_t howToMonitor, + uint32_t matchValue, + uint32_t whichIO, + sctimer_counter_t whichCounter, + uint32_t *event) +{ + uint32_t combMode = (((uint32_t)howToMonitor & SCT_EVENT_CTRL_COMBMODE_MASK) >> SCT_EVENT_CTRL_COMBMODE_SHIFT); + uint32_t currentCtrlVal = howToMonitor; + + /* Return an error if we have hit the limit in terms of number of events created */ + if (s_currentEvent >= FSL_FEATURE_SCT_NUMBER_OF_EVENTS) + { + return kStatus_Fail; + } + + /* IO only mode */ + if (combMode == 0x2U) + { + base->EVENT[s_currentEvent].CTRL = currentCtrlVal | SCT_EVENT_CTRL_IOSEL(whichIO); + } + /* Match mode only */ + else if (combMode == 0x1U) + { + /* Return an error if we have hit the limit in terms of number of number of match registers */ + if (s_currentMatch >= FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE) + { + return kStatus_Fail; + } + + currentCtrlVal |= SCT_EVENT_CTRL_MATCHSEL(s_currentMatch); + /* Use Counter_L bits if counter is operating in 32-bit mode or user wants to setup the L counter */ + if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (whichCounter == kSCTIMER_Counter_L)) + { + base->SCTMATCH[s_currentMatch] = SCT_SCTMATCH_MATCHn_L(matchValue); + base->SCTMATCHREL[s_currentMatch] = SCT_SCTMATCHREL_RELOADn_L(matchValue); + } + else + { + /* Select the counter, no need for this if operating in 32-bit mode */ + currentCtrlVal |= SCT_EVENT_CTRL_HEVENT(whichCounter); + base->SCTMATCH[s_currentMatch] = SCT_SCTMATCH_MATCHn_H(matchValue); + base->SCTMATCHREL[s_currentMatch] = SCT_SCTMATCHREL_RELOADn_H(matchValue); + } + base->EVENT[s_currentEvent].CTRL = currentCtrlVal; + /* Increment the match register number */ + s_currentMatch++; + } + /* Use both Match & IO */ + else + { + /* Return an error if we have hit the limit in terms of number of number of match registers */ + if (s_currentMatch >= FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE) + { + return kStatus_Fail; + } + + currentCtrlVal |= SCT_EVENT_CTRL_MATCHSEL(s_currentMatch) | SCT_EVENT_CTRL_IOSEL(whichIO); + /* Use Counter_L bits if counter is operating in 32-bit mode or user wants to setup the L counter */ + if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (whichCounter == kSCTIMER_Counter_L)) + { + base->SCTMATCH[s_currentMatch] = SCT_SCTMATCH_MATCHn_L(matchValue); + base->SCTMATCHREL[s_currentMatch] = SCT_SCTMATCHREL_RELOADn_L(matchValue); + } + else + { + /* Select the counter, no need for this if operating in 32-bit mode */ + currentCtrlVal |= SCT_EVENT_CTRL_HEVENT(whichCounter); + base->SCTMATCH[s_currentMatch] = SCT_SCTMATCH_MATCHn_H(matchValue); + base->SCTMATCHREL[s_currentMatch] = SCT_SCTMATCHREL_RELOADn_H(matchValue); + } + base->EVENT[s_currentEvent].CTRL = currentCtrlVal; + /* Increment the match register number */ + s_currentMatch++; + } + + /* Enable the event in the current state */ + base->EVENT[s_currentEvent].STATE = (1U << s_currentState); + + /* Return the event number */ + *event = s_currentEvent; + + /* Increment the event number */ + s_currentEvent++; + + return kStatus_Success; +} + +/*! + * brief Enable an event in the current state. + * + * This function will allow the event passed in to trigger in the current state. The event must + * be created earlier by either calling the function SCTIMER_SetupPwm() or function + * SCTIMER_CreateAndScheduleEvent() . + * + * param base SCTimer peripheral base address + * param event Event number to enable in the current state + * + */ +void SCTIMER_ScheduleEvent(SCT_Type *base, uint32_t event) +{ + /* Enable event in the current state */ + base->EVENT[event].STATE |= (1U << s_currentState); +} + +/*! + * brief Increase the state by 1 + * + * All future events created by calling the function SCTIMER_ScheduleEvent() will be enabled in this new + * state. + * + * param base SCTimer peripheral base address + * + * return kStatus_Success on success + * kStatus_Error if we have hit the limit in terms of states used + + */ +status_t SCTIMER_IncreaseState(SCT_Type *base) +{ + /* Return an error if we have hit the limit in terms of states used */ + if (s_currentState >= FSL_FEATURE_SCT_NUMBER_OF_STATES) + { + return kStatus_Fail; + } + + s_currentState++; + + return kStatus_Success; +} + +/*! + * brief Provides the current state + * + * User can use this to set the next state by calling the function SCTIMER_SetupNextStateAction(). + * + * param base SCTimer peripheral base address + * + * return The current state + */ +uint32_t SCTIMER_GetCurrentState(SCT_Type *base) +{ + return s_currentState; +} + +/*! + * brief Toggle the output level. + * + * This change in the output level is triggered by the event number that is passed in by the user. + * + * param base SCTimer peripheral base address + * param whichIO The output to toggle + * param event Event number that will trigger the output change + */ +void SCTIMER_SetupOutputToggleAction(SCT_Type *base, uint32_t whichIO, uint32_t event) +{ + assert(whichIO < FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS); + + uint32_t reg; + + /* Set the same event to set and clear the output */ + base->OUT[whichIO].CLR |= (1U << event); + base->OUT[whichIO].SET |= (1U << event); + + /* Set the conflict resolution to toggle output */ + reg = base->RES; + reg &= ~(SCT_RES_O0RES_MASK << (2 * whichIO)); + reg |= (uint32_t)(kSCTIMER_ResolveToggle << (2 * whichIO)); + base->RES = reg; +} + +/*! + * brief Setup capture of the counter value on trigger of a selected event + * + * param base SCTimer peripheral base address + * param whichCounter SCTimer counter to use when operating in 16-bit mode. In 32-bit mode, this + * field has no meaning as only the Counter_L bits are used. + * param captureRegister Pointer to a variable where the capture register number will be returned. User + * can read the captured value from this register when the specified event is triggered. + * param event Event number that will trigger the capture + * + * return kStatus_Success on success + * kStatus_Error if we have hit the limit in terms of number of match/capture registers available + */ +status_t SCTIMER_SetupCaptureAction(SCT_Type *base, + sctimer_counter_t whichCounter, + uint32_t *captureRegister, + uint32_t event) +{ + /* Return an error if we have hit the limit in terms of number of capture/match registers used */ + if (s_currentMatch >= FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE) + { + return kStatus_Fail; + } + + /* Use Counter_L bits if counter is operating in 32-bit mode or user wants to setup the L counter */ + if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (whichCounter == kSCTIMER_Counter_L)) + { + /* Set the bit to enable event */ + base->SCTCAPCTRL[s_currentMatch] |= SCT_SCTCAPCTRL_CAPCONn_L(1 << event); + + /* Set this resource to be a capture rather than match */ + base->REGMODE |= SCT_REGMODE_REGMOD_L(1 << s_currentMatch); + } + else + { + /* Set bit to enable event */ + base->SCTCAPCTRL[s_currentMatch] |= SCT_SCTCAPCTRL_CAPCONn_H(1 << event); + + /* Set this resource to be a capture rather than match */ + base->REGMODE |= SCT_REGMODE_REGMOD_H(1 << s_currentMatch); + } + + /* Return the match register number */ + *captureRegister = s_currentMatch; + + /* Increase the match register number */ + s_currentMatch++; + + return kStatus_Success; +} + +/*! + * brief Receive noticification when the event trigger an interrupt. + * + * If the interrupt for the event is enabled by the user, then a callback can be registered + * which will be invoked when the event is triggered + * + * param base SCTimer peripheral base address + * param event Event number that will trigger the interrupt + * param callback Function to invoke when the event is triggered + */ + +void SCTIMER_SetCallback(SCT_Type *base, sctimer_event_callback_t callback, uint32_t event) +{ + s_eventCallback[event] = callback; +} + +/*! + * brief SCTimer interrupt handler. + * + * param base SCTimer peripheral base address. + */ +void SCTIMER_EventHandleIRQ(SCT_Type *base) +{ + uint32_t eventFlag = SCT0->EVFLAG; + /* Only clear the flags whose interrupt field is enabled */ + uint32_t clearFlag = (eventFlag & SCT0->EVEN); + uint32_t mask = eventFlag; + int i = 0; + + /* Invoke the callback for certain events */ + for (i = 0; (i < FSL_FEATURE_SCT_NUMBER_OF_EVENTS) && (mask != 0); i++) + { + if (mask & 0x1) + { + if (s_eventCallback[i] != NULL) + { + s_eventCallback[i](); + } + } + mask >>= 1; + } + + /* Clear event interrupt flag */ + SCT0->EVFLAG = clearFlag; +} + +void SCT0_DriverIRQHandler(void) +{ + s_sctimerIsr(SCT0); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_sctimer.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_sctimer.h new file mode 100644 index 000000000..db9865f07 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_sctimer.h @@ -0,0 +1,825 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_SCTIMER_H_ +#define _FSL_SCTIMER_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup sctimer + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_SCTIMER_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) /*!< Version 2.1.0 */ +/*@}*/ + +/*! @brief SCTimer PWM operation modes */ +typedef enum _sctimer_pwm_mode +{ + kSCTIMER_EdgeAlignedPwm = 0U, /*!< Edge-aligned PWM */ + kSCTIMER_CenterAlignedPwm /*!< Center-aligned PWM */ +} sctimer_pwm_mode_t; + +/*! @brief SCTimer counters when working as two independent 16-bit counters */ +typedef enum _sctimer_counter +{ + kSCTIMER_Counter_L = 0U, /*!< Counter L */ + kSCTIMER_Counter_H /*!< Counter H */ +} sctimer_counter_t; + +/*! @brief List of SCTimer input pins */ +typedef enum _sctimer_input +{ + kSCTIMER_Input_0 = 0U, /*!< SCTIMER input 0 */ + kSCTIMER_Input_1, /*!< SCTIMER input 1 */ + kSCTIMER_Input_2, /*!< SCTIMER input 2 */ + kSCTIMER_Input_3, /*!< SCTIMER input 3 */ + kSCTIMER_Input_4, /*!< SCTIMER input 4 */ + kSCTIMER_Input_5, /*!< SCTIMER input 5 */ + kSCTIMER_Input_6, /*!< SCTIMER input 6 */ + kSCTIMER_Input_7 /*!< SCTIMER input 7 */ +} sctimer_input_t; + +/*! @brief List of SCTimer output pins */ +typedef enum _sctimer_out +{ + kSCTIMER_Out_0 = 0U, /*!< SCTIMER output 0*/ + kSCTIMER_Out_1, /*!< SCTIMER output 1 */ + kSCTIMER_Out_2, /*!< SCTIMER output 2 */ + kSCTIMER_Out_3, /*!< SCTIMER output 3 */ + kSCTIMER_Out_4, /*!< SCTIMER output 4 */ + kSCTIMER_Out_5, /*!< SCTIMER output 5 */ + kSCTIMER_Out_6, /*!< SCTIMER output 6 */ + kSCTIMER_Out_7, /*!< SCTIMER output 7 */ + kSCTIMER_Out_8, /*!< SCTIMER output 8 */ + kSCTIMER_Out_9 /*!< SCTIMER output 9 */ +} sctimer_out_t; + +/*! @brief SCTimer PWM output pulse mode: high-true, low-true or no output */ +typedef enum _sctimer_pwm_level_select +{ + kSCTIMER_LowTrue = 0U, /*!< Low true pulses */ + kSCTIMER_HighTrue /*!< High true pulses */ +} sctimer_pwm_level_select_t; + +/*! @brief Options to configure a SCTimer PWM signal */ +typedef struct _sctimer_pwm_signal_param +{ + sctimer_out_t output; /*!< The output pin to use to generate the PWM signal */ + sctimer_pwm_level_select_t level; /*!< PWM output active level select. */ + uint8_t dutyCyclePercent; /*!< PWM pulse width, value should be between 1 to 100 + 100 = always active signal (100% duty cycle).*/ +} sctimer_pwm_signal_param_t; + +/*! @brief SCTimer clock mode options */ +typedef enum _sctimer_clock_mode +{ + kSCTIMER_System_ClockMode = 0U, /*!< System Clock Mode */ + kSCTIMER_Sampled_ClockMode, /*!< Sampled System Clock Mode */ + kSCTIMER_Input_ClockMode, /*!< SCT Input Clock Mode */ + kSCTIMER_Asynchronous_ClockMode /*!< Asynchronous Mode */ +} sctimer_clock_mode_t; + +/*! @brief SCTimer clock select options */ +typedef enum _sctimer_clock_select +{ + kSCTIMER_Clock_On_Rise_Input_0 = 0U, /*!< Rising edges on input 0 */ + kSCTIMER_Clock_On_Fall_Input_0, /*!< Falling edges on input 0 */ + kSCTIMER_Clock_On_Rise_Input_1, /*!< Rising edges on input 1 */ + kSCTIMER_Clock_On_Fall_Input_1, /*!< Falling edges on input 1 */ + kSCTIMER_Clock_On_Rise_Input_2, /*!< Rising edges on input 2 */ + kSCTIMER_Clock_On_Fall_Input_2, /*!< Falling edges on input 2 */ + kSCTIMER_Clock_On_Rise_Input_3, /*!< Rising edges on input 3 */ + kSCTIMER_Clock_On_Fall_Input_3, /*!< Falling edges on input 3 */ + kSCTIMER_Clock_On_Rise_Input_4, /*!< Rising edges on input 4 */ + kSCTIMER_Clock_On_Fall_Input_4, /*!< Falling edges on input 4 */ + kSCTIMER_Clock_On_Rise_Input_5, /*!< Rising edges on input 5 */ + kSCTIMER_Clock_On_Fall_Input_5, /*!< Falling edges on input 5 */ + kSCTIMER_Clock_On_Rise_Input_6, /*!< Rising edges on input 6 */ + kSCTIMER_Clock_On_Fall_Input_6, /*!< Falling edges on input 6 */ + kSCTIMER_Clock_On_Rise_Input_7, /*!< Rising edges on input 7 */ + kSCTIMER_Clock_On_Fall_Input_7 /*!< Falling edges on input 7 */ +} sctimer_clock_select_t; + +/*! + * @brief SCTimer output conflict resolution options. + * + * Specifies what action should be taken if multiple events dictate that a given output should be + * both set and cleared at the same time + */ +typedef enum _sctimer_conflict_resolution +{ + kSCTIMER_ResolveNone = 0U, /*!< No change */ + kSCTIMER_ResolveSet, /*!< Set output */ + kSCTIMER_ResolveClear, /*!< Clear output */ + kSCTIMER_ResolveToggle /*!< Toggle output */ +} sctimer_conflict_resolution_t; + +/*! @brief List of SCTimer event types */ +typedef enum _sctimer_event +{ + kSCTIMER_InputLowOrMatchEvent = + (0 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (0 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT), + kSCTIMER_InputRiseOrMatchEvent = + (0 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (1 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT), + kSCTIMER_InputFallOrMatchEvent = + (0 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (2 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT), + kSCTIMER_InputHighOrMatchEvent = + (0 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (3 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT), + + kSCTIMER_MatchEventOnly = + (1 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (0 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT), + + kSCTIMER_InputLowEvent = + (2 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (0 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT), + kSCTIMER_InputRiseEvent = + (2 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (1 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT), + kSCTIMER_InputFallEvent = + (2 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (2 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT), + kSCTIMER_InputHighEvent = + (2 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (3 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT), + + kSCTIMER_InputLowAndMatchEvent = + (3 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (0 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT), + kSCTIMER_InputRiseAndMatchEvent = + (3 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (1 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT), + kSCTIMER_InputFallAndMatchEvent = + (3 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (2 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT), + kSCTIMER_InputHighAndMatchEvent = + (3 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (3 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT), + + kSCTIMER_OutputLowOrMatchEvent = + (0 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (0 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT), + kSCTIMER_OutputRiseOrMatchEvent = + (0 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (1 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT), + kSCTIMER_OutputFallOrMatchEvent = + (0 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (2 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT), + kSCTIMER_OutputHighOrMatchEvent = + (0 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (3 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT), + + kSCTIMER_OutputLowEvent = + (2 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (0 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT), + kSCTIMER_OutputRiseEvent = + (2 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (1 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT), + kSCTIMER_OutputFallEvent = + (2 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (2 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT), + kSCTIMER_OutputHighEvent = + (2 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (3 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT), + + kSCTIMER_OutputLowAndMatchEvent = + (3 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (0 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT), + kSCTIMER_OutputRiseAndMatchEvent = + (3 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (1 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT), + kSCTIMER_OutputFallAndMatchEvent = + (3 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (2 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT), + kSCTIMER_OutputHighAndMatchEvent = + (3 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (3 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT) +} sctimer_event_t; + +/*! @brief SCTimer callback typedef. */ +typedef void (*sctimer_event_callback_t)(void); + +/*! @brief List of SCTimer interrupts */ +typedef enum _sctimer_interrupt_enable +{ + kSCTIMER_Event0InterruptEnable = (1U << 0), /*!< Event 0 interrupt */ + kSCTIMER_Event1InterruptEnable = (1U << 1), /*!< Event 1 interrupt */ + kSCTIMER_Event2InterruptEnable = (1U << 2), /*!< Event 2 interrupt */ + kSCTIMER_Event3InterruptEnable = (1U << 3), /*!< Event 3 interrupt */ + kSCTIMER_Event4InterruptEnable = (1U << 4), /*!< Event 4 interrupt */ + kSCTIMER_Event5InterruptEnable = (1U << 5), /*!< Event 5 interrupt */ + kSCTIMER_Event6InterruptEnable = (1U << 6), /*!< Event 6 interrupt */ + kSCTIMER_Event7InterruptEnable = (1U << 7), /*!< Event 7 interrupt */ + kSCTIMER_Event8InterruptEnable = (1U << 8), /*!< Event 8 interrupt */ + kSCTIMER_Event9InterruptEnable = (1U << 9), /*!< Event 9 interrupt */ + kSCTIMER_Event10InterruptEnable = (1U << 10), /*!< Event 10 interrupt */ + kSCTIMER_Event11InterruptEnable = (1U << 11), /*!< Event 11 interrupt */ + kSCTIMER_Event12InterruptEnable = (1U << 12), /*!< Event 12 interrupt */ +} sctimer_interrupt_enable_t; + +/*! @brief List of SCTimer flags */ +typedef enum _sctimer_status_flags +{ + kSCTIMER_Event0Flag = (1U << 0), /*!< Event 0 Flag */ + kSCTIMER_Event1Flag = (1U << 1), /*!< Event 1 Flag */ + kSCTIMER_Event2Flag = (1U << 2), /*!< Event 2 Flag */ + kSCTIMER_Event3Flag = (1U << 3), /*!< Event 3 Flag */ + kSCTIMER_Event4Flag = (1U << 4), /*!< Event 4 Flag */ + kSCTIMER_Event5Flag = (1U << 5), /*!< Event 5 Flag */ + kSCTIMER_Event6Flag = (1U << 6), /*!< Event 6 Flag */ + kSCTIMER_Event7Flag = (1U << 7), /*!< Event 7 Flag */ + kSCTIMER_Event8Flag = (1U << 8), /*!< Event 8 Flag */ + kSCTIMER_Event9Flag = (1U << 9), /*!< Event 9 Flag */ + kSCTIMER_Event10Flag = (1U << 10), /*!< Event 10 Flag */ + kSCTIMER_Event11Flag = (1U << 11), /*!< Event 11 Flag */ + kSCTIMER_Event12Flag = (1U << 12), /*!< Event 12 Flag */ + kSCTIMER_BusErrorLFlag = + (1U << SCT_CONFLAG_BUSERRL_SHIFT), /*!< Bus error due to write when L counter was not halted */ + kSCTIMER_BusErrorHFlag = + (int)(1U << SCT_CONFLAG_BUSERRH_SHIFT) /*!< Bus error due to write when H counter was not halted */ +} sctimer_status_flags_t; + +/*! + * @brief SCTimer configuration structure + * + * This structure holds the configuration settings for the SCTimer peripheral. To initialize this + * structure to reasonable defaults, call the SCTMR_GetDefaultConfig() function and pass a + * pointer to the configuration structure instance. + * + * The configuration structure can be made constant so as to reside in flash. + */ +typedef struct _sctimer_config +{ + bool enableCounterUnify; /*!< true: SCT operates as a unified 32-bit counter; + false: SCT operates as two 16-bit counters */ + sctimer_clock_mode_t clockMode; /*!< SCT clock mode value */ + sctimer_clock_select_t clockSelect; /*!< SCT clock select value */ + bool enableBidirection_l; /*!< true: Up-down count mode for the L or unified counter + false: Up count mode only for the L or unified counter */ + bool enableBidirection_h; /*!< true: Up-down count mode for the H or unified counter + false: Up count mode only for the H or unified counter. + This field is used only if the enableCounterUnify is set + to false */ + uint8_t prescale_l; /*!< Prescale value to produce the L or unified counter clock */ + uint8_t prescale_h; /*!< Prescale value to produce the H counter clock. + This field is used only if the enableCounterUnify is set + to false */ + uint8_t outInitState; /*!< Defines the initial output value */ + uint8_t inputsync; /*!< SCT INSYNC value, INSYNC field in the CONFIG register, from bit9 to bit 16. + it is used to define synchronization for input N: + bit 9 = input 0 + bit 10 = input 1 + bit 11 = input 2 + bit 12 = input 3 + All other bits are reserved (bit13 ~bit 16). + How User to set the the value for the member inputsync. + IE: delay for input0, and input 1, bypasses for input 2 and input 3 + MACRO definition in user level. + #define INPUTSYNC0 (0U) + #define INPUTSYNC1 (1U) + #define INPUTSYNC2 (2U) + #define INPUTSYNC3 (3U) + User Code. + sctimerInfo.inputsync = (1 << INPUTSYNC2) | (1 << INPUTSYNC3); */ +} sctimer_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Ungates the SCTimer clock and configures the peripheral for basic operation. + * + * @note This API should be called at the beginning of the application using the SCTimer driver. + * + * @param base SCTimer peripheral base address + * @param config Pointer to the user configuration structure. + * + * @return kStatus_Success indicates success; Else indicates failure. + */ +status_t SCTIMER_Init(SCT_Type *base, const sctimer_config_t *config); + +/*! + * @brief Gates the SCTimer clock. + * + * @param base SCTimer peripheral base address + */ +void SCTIMER_Deinit(SCT_Type *base); + +/*! + * @brief Fills in the SCTimer configuration structure with the default settings. + * + * The default values are: + * @code + * config->enableCounterUnify = true; + * config->clockMode = kSCTIMER_System_ClockMode; + * config->clockSelect = kSCTIMER_Clock_On_Rise_Input_0; + * config->enableBidirection_l = false; + * config->enableBidirection_h = false; + * config->prescale_l = 0U; + * config->prescale_h = 0U; + * config->outInitState = 0U; + * config->inputsync = 0xFU; + * @endcode + * @param config Pointer to the user configuration structure. + */ +void SCTIMER_GetDefaultConfig(sctimer_config_t *config); + +/*! @}*/ + +/*! + * @name PWM setup operations + * @{ + */ + +/*! + * @brief Configures the PWM signal parameters. + * + * Call this function to configure the PWM signal period, mode, duty cycle, and edge. This + * function will create 2 events; one of the events will trigger on match with the pulse value + * and the other will trigger when the counter matches the PWM period. The PWM period event is + * also used as a limit event to reset the counter or change direction. Both events are enabled + * for the same state. The state number can be retrieved by calling the function + * SCTIMER_GetCurrentStateNumber(). + * The counter is set to operate as one 32-bit counter (unify bit is set to 1). + * The counter operates in bi-directional mode when generating a center-aligned PWM. + * + * @note When setting PWM output from multiple output pins, they all should use the same PWM mode + * i.e all PWM's should be either edge-aligned or center-aligned. + * When using this API, the PWM signal frequency of all the initialized channels must be the same. + * Otherwise all the initialized channels' PWM signal frequency is equal to the last call to the + * API's pwmFreq_Hz. + * + * @param base SCTimer peripheral base address + * @param pwmParams PWM parameters to configure the output + * @param mode PWM operation mode, options available in enumeration ::sctimer_pwm_mode_t + * @param pwmFreq_Hz PWM signal frequency in Hz + * @param srcClock_Hz SCTimer counter clock in Hz + * @param event Pointer to a variable where the PWM period event number is stored + * + * @return kStatus_Success on success + * kStatus_Fail If we have hit the limit in terms of number of events created or if + * an incorrect PWM dutycylce is passed in. + */ +status_t SCTIMER_SetupPwm(SCT_Type *base, + const sctimer_pwm_signal_param_t *pwmParams, + sctimer_pwm_mode_t mode, + uint32_t pwmFreq_Hz, + uint32_t srcClock_Hz, + uint32_t *event); + +/*! + * @brief Updates the duty cycle of an active PWM signal. + * + * @param base SCTimer peripheral base address + * @param output The output to configure + * @param dutyCyclePercent New PWM pulse width; the value should be between 1 to 100 + * @param event Event number associated with this PWM signal. This was returned to the user by the + * function SCTIMER_SetupPwm(). + */ +void SCTIMER_UpdatePwmDutycycle(SCT_Type *base, sctimer_out_t output, uint8_t dutyCyclePercent, uint32_t event); + +/*! + * @name Interrupt Interface + * @{ + */ + +/*! + * @brief Enables the selected SCTimer interrupts. + * + * @param base SCTimer peripheral base address + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::sctimer_interrupt_enable_t + */ +static inline void SCTIMER_EnableInterrupts(SCT_Type *base, uint32_t mask) +{ + base->EVEN |= mask; +} + +/*! + * @brief Disables the selected SCTimer interrupts. + * + * @param base SCTimer peripheral base address + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::sctimer_interrupt_enable_t + */ +static inline void SCTIMER_DisableInterrupts(SCT_Type *base, uint32_t mask) +{ + base->EVEN &= ~mask; +} + +/*! + * @brief Gets the enabled SCTimer interrupts. + * + * @param base SCTimer peripheral base address + * + * @return The enabled interrupts. This is the logical OR of members of the + * enumeration ::sctimer_interrupt_enable_t + */ +static inline uint32_t SCTIMER_GetEnabledInterrupts(SCT_Type *base) +{ + return (base->EVEN & 0xFFFFU); +} + +/*! @}*/ + +/*! + * @name Status Interface + * @{ + */ + +/*! + * @brief Gets the SCTimer status flags. + * + * @param base SCTimer peripheral base address + * + * @return The status flags. This is the logical OR of members of the + * enumeration ::sctimer_status_flags_t + */ +static inline uint32_t SCTIMER_GetStatusFlags(SCT_Type *base) +{ + uint32_t statusFlags = 0; + + /* Add the recorded events */ + statusFlags = (base->EVFLAG & 0xFFFFU); + + /* Add bus error flags */ + statusFlags |= (base->CONFLAG & (SCT_CONFLAG_BUSERRL_MASK | SCT_CONFLAG_BUSERRH_MASK)); + + return statusFlags; +} + +/*! + * @brief Clears the SCTimer status flags. + * + * @param base SCTimer peripheral base address + * @param mask The status flags to clear. This is a logical OR of members of the + * enumeration ::sctimer_status_flags_t + */ +static inline void SCTIMER_ClearStatusFlags(SCT_Type *base, uint32_t mask) +{ + /* Write to the flag registers */ + base->EVFLAG = (mask & 0xFFFFU); + base->CONFLAG = (mask & (SCT_CONFLAG_BUSERRL_MASK | SCT_CONFLAG_BUSERRH_MASK)); +} + +/*! @}*/ + +/*! + * @name Counter Start and Stop + * @{ + */ + +/*! + * @brief Starts the SCTimer counter. + * + * @param base SCTimer peripheral base address + * @param countertoStart SCTimer counter to start; if unify mode is set then function always + * writes to HALT_L bit + */ +static inline void SCTIMER_StartTimer(SCT_Type *base, sctimer_counter_t countertoStart) +{ + /* Clear HALT_L bit if counter is operating in 32-bit mode or user wants to start L counter */ + if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (countertoStart == kSCTIMER_Counter_L)) + { + base->CTRL &= ~(SCT_CTRL_HALT_L_MASK); + } + else + { + /* Start H counter */ + base->CTRL &= ~(SCT_CTRL_HALT_H_MASK); + } +} + +/*! + * @brief Halts the SCTimer counter. + * + * @param base SCTimer peripheral base address + * @param countertoStop SCTimer counter to stop; if unify mode is set then function always + * writes to HALT_L bit + */ +static inline void SCTIMER_StopTimer(SCT_Type *base, sctimer_counter_t countertoStop) +{ + /* Set HALT_L bit if counter is operating in 32-bit mode or user wants to stop L counter */ + if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (countertoStop == kSCTIMER_Counter_L)) + { + base->CTRL |= (SCT_CTRL_HALT_L_MASK); + } + else + { + /* Stop H counter */ + base->CTRL |= (SCT_CTRL_HALT_H_MASK); + } +} + +/*! @}*/ + +/*! + * @name Functions to create a new event and manage the state logic + * @{ + */ + +/*! + * @brief Create an event that is triggered on a match or IO and schedule in current state. + * + * This function will configure an event using the options provided by the user. If the event type uses + * the counter match, then the function will set the user provided match value into a match register + * and put this match register number into the event control register. + * The event is enabled for the current state and the event number is increased by one at the end. + * The function returns the event number; this event number can be used to configure actions to be + * done when this event is triggered. + * + * @param base SCTimer peripheral base address + * @param howToMonitor Event type; options are available in the enumeration ::sctimer_interrupt_enable_t + * @param matchValue The match value that will be programmed to a match register + * @param whichIO The input or output that will be involved in event triggering. This field + * is ignored if the event type is "match only" + * @param whichCounter SCTimer counter to use when operating in 16-bit mode. In 32-bit mode, this + * field has no meaning as we have only 1 unified counter; hence ignored. + * @param event Pointer to a variable where the new event number is stored + * + * @return kStatus_Success on success + * kStatus_Error if we have hit the limit in terms of number of events created or + if we have reached the limit in terms of number of match registers + */ +status_t SCTIMER_CreateAndScheduleEvent(SCT_Type *base, + sctimer_event_t howToMonitor, + uint32_t matchValue, + uint32_t whichIO, + sctimer_counter_t whichCounter, + uint32_t *event); + +/*! + * @brief Enable an event in the current state. + * + * This function will allow the event passed in to trigger in the current state. The event must + * be created earlier by either calling the function SCTIMER_SetupPwm() or function + * SCTIMER_CreateAndScheduleEvent() . + * + * @param base SCTimer peripheral base address + * @param event Event number to enable in the current state + * + */ +void SCTIMER_ScheduleEvent(SCT_Type *base, uint32_t event); + +/*! + * @brief Increase the state by 1 + * + * All future events created by calling the function SCTIMER_ScheduleEvent() will be enabled in this new + * state. + * + * @param base SCTimer peripheral base address + * + * @return kStatus_Success on success + * kStatus_Error if we have hit the limit in terms of states used + + */ +status_t SCTIMER_IncreaseState(SCT_Type *base); + +/*! + * @brief Provides the current state + * + * User can use this to set the next state by calling the function SCTIMER_SetupNextStateAction(). + * + * @param base SCTimer peripheral base address + * + * @return The current state + */ +uint32_t SCTIMER_GetCurrentState(SCT_Type *base); + +/*! @}*/ + +/*! + * @name Actions to take in response to an event + * @{ + */ + +/*! + * @brief Setup capture of the counter value on trigger of a selected event + * + * @param base SCTimer peripheral base address + * @param whichCounter SCTimer counter to use when operating in 16-bit mode. In 32-bit mode, this + * field has no meaning as only the Counter_L bits are used. + * @param captureRegister Pointer to a variable where the capture register number will be returned. User + * can read the captured value from this register when the specified event is triggered. + * @param event Event number that will trigger the capture + * + * @return kStatus_Success on success + * kStatus_Error if we have hit the limit in terms of number of match/capture registers available + */ +status_t SCTIMER_SetupCaptureAction(SCT_Type *base, + sctimer_counter_t whichCounter, + uint32_t *captureRegister, + uint32_t event); + +/*! + * @brief Receive noticification when the event trigger an interrupt. + * + * If the interrupt for the event is enabled by the user, then a callback can be registered + * which will be invoked when the event is triggered + * + * @param base SCTimer peripheral base address + * @param event Event number that will trigger the interrupt + * @param callback Function to invoke when the event is triggered + */ + +void SCTIMER_SetCallback(SCT_Type *base, sctimer_event_callback_t callback, uint32_t event); + +/*! + * @brief Transition to the specified state. + * + * This transition will be triggered by the event number that is passed in by the user. + * + * @param base SCTimer peripheral base address + * @param nextState The next state SCTimer will transition to + * @param event Event number that will trigger the state transition + */ +static inline void SCTIMER_SetupNextStateAction(SCT_Type *base, uint32_t nextState, uint32_t event) +{ + uint32_t reg = base->EVENT[event].CTRL; + + reg &= ~(SCT_EVENT_CTRL_STATEV_MASK); + /* Load the STATEV value when the event occurs to be the next state */ + reg |= SCT_EVENT_CTRL_STATEV(nextState) | SCT_EVENT_CTRL_STATELD_MASK; + + base->EVENT[event].CTRL = reg; +} + +/*! + * @brief Set the Output. + * + * This output will be set when the event number that is passed in by the user is triggered. + * + * @param base SCTimer peripheral base address + * @param whichIO The output to set + * @param event Event number that will trigger the output change + */ +static inline void SCTIMER_SetupOutputSetAction(SCT_Type *base, uint32_t whichIO, uint32_t event) +{ + assert(whichIO < FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS); + + base->OUT[whichIO].SET |= (1U << event); +} + +/*! + * @brief Clear the Output. + * + * This output will be cleared when the event number that is passed in by the user is triggered. + * + * @param base SCTimer peripheral base address + * @param whichIO The output to clear + * @param event Event number that will trigger the output change + */ +static inline void SCTIMER_SetupOutputClearAction(SCT_Type *base, uint32_t whichIO, uint32_t event) +{ + assert(whichIO < FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS); + + base->OUT[whichIO].CLR |= (1U << event); +} + +/*! + * @brief Toggle the output level. + * + * This change in the output level is triggered by the event number that is passed in by the user. + * + * @param base SCTimer peripheral base address + * @param whichIO The output to toggle + * @param event Event number that will trigger the output change + */ +void SCTIMER_SetupOutputToggleAction(SCT_Type *base, uint32_t whichIO, uint32_t event); + +/*! + * @brief Limit the running counter. + * + * The counter is limited when the event number that is passed in by the user is triggered. + * + * @param base SCTimer peripheral base address + * @param whichCounter SCTimer counter to use when operating in 16-bit mode. In 32-bit mode, this + * field has no meaning as only the Counter_L bits are used. + * @param event Event number that will trigger the counter to be limited + */ +static inline void SCTIMER_SetupCounterLimitAction(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t event) +{ + /* Use Counter_L bits if counter is operating in 32-bit mode or user wants to setup the L counter */ + if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (whichCounter == kSCTIMER_Counter_L)) + { + base->LIMIT |= SCT_LIMIT_LIMMSK_L(1U << event); + } + else + { + base->LIMIT |= SCT_LIMIT_LIMMSK_H(1U << event); + } +} + +/*! + * @brief Stop the running counter. + * + * The counter is stopped when the event number that is passed in by the user is triggered. + * + * @param base SCTimer peripheral base address + * @param whichCounter SCTimer counter to use when operating in 16-bit mode. In 32-bit mode, this + * field has no meaning as only the Counter_L bits are used. + * @param event Event number that will trigger the counter to be stopped + */ +static inline void SCTIMER_SetupCounterStopAction(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t event) +{ + /* Use Counter_L bits if counter is operating in 32-bit mode or user wants to setup the L counter */ + if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (whichCounter == kSCTIMER_Counter_L)) + { + base->STOP |= SCT_STOP_STOPMSK_L(1U << event); + } + else + { + base->STOP |= SCT_STOP_STOPMSK_H(1U << event); + } +} + +/*! + * @brief Re-start the stopped counter. + * + * The counter will re-start when the event number that is passed in by the user is triggered. + * + * @param base SCTimer peripheral base address + * @param whichCounter SCTimer counter to use when operating in 16-bit mode. In 32-bit mode, this + * field has no meaning as only the Counter_L bits are used. + * @param event Event number that will trigger the counter to re-start + */ +static inline void SCTIMER_SetupCounterStartAction(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t event) +{ + /* Use Counter_L bits if counter is operating in 32-bit mode or user wants to setup the L counter */ + if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (whichCounter == kSCTIMER_Counter_L)) + { + base->START |= SCT_START_STARTMSK_L(1U << event); + } + else + { + base->START |= SCT_START_STARTMSK_H(1U << event); + } +} + +/*! + * @brief Halt the running counter. + * + * The counter is disabled (halted) when the event number that is passed in by the user is + * triggered. When the counter is halted, all further events are disabled. The HALT condition + * can only be removed by calling the SCTIMER_StartTimer() function. + * + * @param base SCTimer peripheral base address + * @param whichCounter SCTimer counter to use when operating in 16-bit mode. In 32-bit mode, this + * field has no meaning as only the Counter_L bits are used. + * @param event Event number that will trigger the counter to be halted + */ +static inline void SCTIMER_SetupCounterHaltAction(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t event) +{ + /* Use Counter_L bits if counter is operating in 32-bit mode or user wants to setup the L counter */ + if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (whichCounter == kSCTIMER_Counter_L)) + { + base->HALT |= SCT_HALT_HALTMSK_L(1U << event); + } + else + { + base->HALT |= SCT_HALT_HALTMSK_H(1U << event); + } +} + +#if !(defined(FSL_FEATURE_SCT_HAS_NO_DMA_REQUEST) && FSL_FEATURE_SCT_HAS_NO_DMA_REQUEST) +/*! + * @brief Generate a DMA request. + * + * DMA request will be triggered by the event number that is passed in by the user. + * + * @param base SCTimer peripheral base address + * @param dmaNumber The DMA request to generate + * @param event Event number that will trigger the DMA request + */ +static inline void SCTIMER_SetupDmaTriggerAction(SCT_Type *base, uint32_t dmaNumber, uint32_t event) +{ + if (dmaNumber == 0) + { + base->DMA0REQUEST |= (1U << event); + } + else + { + base->DMA1REQUEST |= (1U << event); + } +} +#endif /* FSL_FEATURE_SCT_HAS_NO_DMA_REQUEST */ + +/*! + * @brief SCTimer interrupt handler. + * + * @param base SCTimer peripheral base address. + */ +void SCTIMER_EventHandleIRQ(SCT_Type *base); + +/*! @}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_SCTIMER_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_sdif.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_sdif.c new file mode 100644 index 000000000..f00f74fc1 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_sdif.c @@ -0,0 +1,1573 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_sdif.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.sdif" +#endif + +/* Typedef for interrupt handler. */ +typedef void (*sdif_isr_t)(SDIF_Type *base, sdif_handle_t *handle); + +/*! @brief convert the name here, due to RM use SDIO */ +#define SDIF_DriverIRQHandler SDIO_DriverIRQHandler +/*! @brief define the controller support sd/sdio card version 2.0 */ +#define SDIF_SUPPORT_SD_VERSION (0x20) +/*! @brief define the controller support mmc card version 4.4 */ +#define SDIF_SUPPORT_MMC_VERSION (0x44) + +#ifndef SDIF_TIMEOUT_VALUE +/*! @brief define the timeout counter, used to polling the start bit auto-cleared when sending clock sync command */ +#define SDIF_TIMEOUT_VALUE (~0U) +#endif + +#ifndef SDIF_RESET_TIMEOUT_VALUE +/*! @brief define the reset timeout counter, two AHB clock cycle, the reset should auto-cleared. */ +#define SDIF_RESET_TIMEOUT_VALUE (100U) +#endif + +/*! @brief this value can be any value */ +#define SDIF_POLL_DEMAND_VALUE (0xFFU) +/*! @brief DMA descriptor buffer1 size */ +#define SDIF_DMA_DESCRIPTOR_BUFFER1_SIZE(x) ((x)&0x1FFFU) +/*! @brief DMA descriptor buffer2 size */ +#define SDIF_DMA_DESCRIPTOR_BUFFER2_SIZE(x) (((x)&0x1FFFU) << 13U) +/*! @brief RX water mark value */ +#define SDIF_RX_WATERMARK (15U) +/*! @brief TX water mark value */ +#define SDIF_TX_WATERMARK (16U) + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Get the instance. + * + * @param base SDIF peripheral base address. + * @return Instance number. + */ +static uint32_t SDIF_GetInstance(SDIF_Type *base); + +/* + * @brief config the SDIF interface before transfer between the card and host + * @param SDIF base address + * @param transfer config structure + * @param enDMA DMA enable flag + */ +static status_t SDIF_TransferConfig(SDIF_Type *base, sdif_transfer_t *transfer, bool enDMA); + +/* + * @brief wait the command done function and check error status + * @param SDIF base address + * @param command config structure + */ +static status_t SDIF_WaitCommandDone(SDIF_Type *base, sdif_command_t *command); + +/* + * @brief transfer data in a blocking way + * @param SDIF base address + * @param data config structure + * @param indicate current transfer mode:DMA or polling + */ +static status_t SDIF_TransferDataBlocking(SDIF_Type *base, sdif_data_t *data, bool isDMA); + +/* + * @brief read the command response + * @param SDIF base address + * @param sdif command pointer + */ +static status_t SDIF_ReadCommandResponse(SDIF_Type *base, sdif_command_t *command); + +/* + * @brief handle transfer command interrupt + * @param SDIF base address + * @param sdif handle + * @param interrupt mask flags + */ +static void SDIF_TransferHandleCommand(SDIF_Type *base, sdif_handle_t *handle, uint32_t interruptFlags); + +/* + * @brief handle transfer data interrupt + * @param SDIF base address + * @param sdif handle + * @param interrupt mask flags + */ +static void SDIF_TransferHandleData(SDIF_Type *base, sdif_handle_t *handle, uint32_t interruptFlags); + +/* + * @brief handle DMA transfer + * @param SDIF base address + * @param sdif handle + * @param interrupt mask flag + */ +static void SDIF_TransferHandleDMA(SDIF_Type *base, sdif_handle_t *handle, uint32_t interruptFlags); + +/* + * @brief driver IRQ handler + * @param SDIF base address + * @param sdif handle + */ +static void SDIF_TransferHandleIRQ(SDIF_Type *base, sdif_handle_t *handle); + +/* + * @brief read data port + * @param SDIF base address + * @param sdif data + * @param the number of data been transferred + */ +static uint32_t SDIF_ReadDataPort(SDIF_Type *base, sdif_data_t *data, uint32_t transferredWords); + +/* + * @brief write data port + * @param SDIF base address + * @param sdif data + * @param the number of data been transferred + */ +static uint32_t SDIF_WriteDataPort(SDIF_Type *base, sdif_data_t *data, uint32_t transferredWords); + +/* + * @brief read data by blocking way + * @param SDIF base address + * @param sdif data + */ +static status_t SDIF_ReadDataPortBlocking(SDIF_Type *base, sdif_data_t *data); + +/* + * @brief write data by blocking way + * @param SDIF base address + * @param sdif data + */ +static status_t SDIF_WriteDataPortBlocking(SDIF_Type *base, sdif_data_t *data); + +/* + * @brief handle sdio interrupt + * This function will call the SDIO interrupt callback + * @param SDIF base address + * @param SDIF handle + */ +static void SDIF_TransferHandleSDIOInterrupt(SDIF_Type *base, sdif_handle_t *handle); + +/* + * @brief handle card detect + * This function will call the cardInserted callback + * @param SDIF base addres + * @param SDIF handle + */ +static void SDIF_TransferHandleCardDetect(SDIF_Type *base, sdif_handle_t *handle); + +/* + * @brief set command register + * This api include polling the status of the bit START_COMMAND, if 0 used as timeout value, then this function + * will return directly without polling the START_CMD status. + * + * @param base SDIF base addres + * @param cmdIndex command index + * @param argument command argument + * @param timeout timeout value + * + * @return kStatus_Success, kStatus_SDIF_SyncCmdTimeout + */ +static status_t SDIF_SetCommandRegister(SDIF_Type *base, uint32_t cmdIndex, uint32_t argument, uint32_t timeout); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief SDIF internal handle pointer array */ +static sdif_handle_t *s_sdifHandle[FSL_FEATURE_SOC_SDIF_COUNT]; + +/*! @brief SDIF base pointer array */ +static SDIF_Type *const s_sdifBase[] = SDIF_BASE_PTRS; + +/*! @brief SDIF IRQ name array */ +static const IRQn_Type s_sdifIRQ[] = SDIF_IRQS; + +/* SDIF ISR for transactional APIs. */ +static sdif_isr_t s_sdifIsr; + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t SDIF_GetInstance(SDIF_Type *base) +{ + uint8_t instance = 0U; + + while ((instance < ARRAY_SIZE(s_sdifBase)) && (s_sdifBase[instance] != base)) + { + instance++; + } + + assert(instance < ARRAY_SIZE(s_sdifBase)); + + return instance; +} + +static status_t SDIF_TransferConfig(SDIF_Type *base, sdif_transfer_t *transfer, bool enDMA) +{ + sdif_command_t *command = transfer->command; + sdif_data_t *data = transfer->data; + + if ((command == NULL) || (data && (data->blockSize > SDIF_BLKSIZ_BLOCK_SIZE_MASK))) + { + return kStatus_SDIF_InvalidArgument; + } + + if (data != NULL) + { + /* config the block size register ,the block size maybe smaller than FIFO + depth, will test on the board */ + base->BLKSIZ = SDIF_BLKSIZ_BLOCK_SIZE(data->blockSize); + /* config the byte count register */ + base->BYTCNT = SDIF_BYTCNT_BYTE_COUNT(data->blockSize * data->blockCount); + + command->flags |= kSDIF_DataExpect; /* need transfer data flag */ + + if (data->txData != NULL) + { + command->flags |= kSDIF_DataWriteToCard; /* data transfer direction */ + } + else + { + /* config the card read threshold,enable the card read threshold */ + if (data->blockSize <= (SDIF_FIFO_COUNT * sizeof(uint32_t))) + { + base->CARDTHRCTL = SDIF_CARDTHRCTL_CARDRDTHREN_MASK | SDIF_CARDTHRCTL_CARDTHRESHOLD(data->blockSize); + } + else + { + base->CARDTHRCTL &= ~SDIF_CARDTHRCTL_CARDRDTHREN_MASK; + } + } + + if (data->streamTransfer) + { + command->flags |= kSDIF_DataStreamTransfer; /* indicate if use stream transfer or block transfer */ + } + + if ((data->enableAutoCommand12) && + (data->blockCount > 1U)) /* indicate if auto stop will send after the data transfer done */ + { + command->flags |= kSDIF_DataTransferAutoStop; + } + + if (enDMA) + { + base->INTMASK &= ~(kSDIF_DataTransferOver | kSDIF_WriteFIFORequest | kSDIF_ReadFIFORequest); + } + else + { + base->INTMASK |= (kSDIF_DataTransferOver | kSDIF_WriteFIFORequest | kSDIF_ReadFIFORequest); + } + } + /* R2 response length long */ + if (command->responseType == kCARD_ResponseTypeR2) + { + command->flags |= (kSDIF_CmdCheckResponseCRC | kSDIF_CmdResponseLengthLong | kSDIF_CmdResponseExpect); + } + else if ((command->responseType == kCARD_ResponseTypeR3) || (command->responseType == kCARD_ResponseTypeR4)) + { + command->flags |= kSDIF_CmdResponseExpect; /* response R3 do not check Response CRC */ + } + else + { + if (command->responseType != kCARD_ResponseTypeNone) + { + command->flags |= (kSDIF_CmdCheckResponseCRC | kSDIF_CmdResponseExpect); + } + } + + if (command->type == kCARD_CommandTypeAbort) + { + command->flags |= kSDIF_TransferStopAbort; + } + + /* wait pre-transfer complete */ + command->flags |= kSDIF_WaitPreTransferComplete | kSDIF_CmdDataUseHoldReg; + + return kStatus_Success; +} + +static status_t SDIF_ReadCommandResponse(SDIF_Type *base, sdif_command_t *command) +{ + /* check if command exist,if not, do not read the response */ + if (NULL != command) + { + /* read response */ + command->response[0U] = base->RESP[0U]; + if (command->responseType == kCARD_ResponseTypeR2) + { + command->response[1U] = base->RESP[1U]; + command->response[2U] = base->RESP[2U]; + command->response[3U] = base->RESP[3U]; + } + + if ((command->responseErrorFlags != 0U) && + ((command->responseType == kCARD_ResponseTypeR1) || (command->responseType == kCARD_ResponseTypeR1b) || + (command->responseType == kCARD_ResponseTypeR6) || (command->responseType == kCARD_ResponseTypeR5))) + { + if (((command->responseErrorFlags) & (command->response[0U])) != 0U) + { + return kStatus_SDIF_ResponseError; + } + } + } + + return kStatus_Success; +} + +static status_t SDIF_WaitCommandDone(SDIF_Type *base, sdif_command_t *command) +{ + uint32_t status = 0U; + + do + { + status = SDIF_GetInterruptStatus(base); + } while ((status & kSDIF_CommandDone) != kSDIF_CommandDone); + /* clear interrupt status flag first */ + SDIF_ClearInterruptStatus(base, status & kSDIF_CommandTransferStatus); + if ((status & (kSDIF_ResponseError | kSDIF_ResponseCRCError | kSDIF_ResponseTimeout | kSDIF_HardwareLockError)) != + 0u) + { + return kStatus_SDIF_SendCmdFail; + } + else + { + return SDIF_ReadCommandResponse(base, command); + } +} + +static status_t SDIF_SetCommandRegister(SDIF_Type *base, uint32_t cmdIndex, uint32_t argument, uint32_t timeout) +{ + uint32_t syncTimeout = timeout; + + base->CMDARG = argument; + base->CMD = cmdIndex | SDIF_CMD_START_CMD_MASK; + + while (((base->CMD & SDIF_CMD_START_CMD_MASK) == SDIF_CMD_START_CMD_MASK) && syncTimeout) + { + --syncTimeout; + + if (!syncTimeout) + { + return kStatus_SDIF_SyncCmdTimeout; + } + } + + return kStatus_Success; +} + +/*! + * brief SDIF release the DMA descriptor to DMA engine + * this function should be called when DMA descriptor unavailable status occurs + * param base SDIF peripheral base address. + * param sdif DMA config pointer + */ +status_t SDIF_ReleaseDMADescriptor(SDIF_Type *base, sdif_dma_config_t *dmaConfig) +{ + assert(NULL != dmaConfig); + assert(NULL != dmaConfig->dmaDesBufferStartAddr); + + sdif_dma_descriptor_t *dmaDesAddr; + uint32_t *tempDMADesBuffer = dmaConfig->dmaDesBufferStartAddr; + uint32_t dmaDesBufferSize = 0U; + + dmaDesAddr = (sdif_dma_descriptor_t *)tempDMADesBuffer; + + /* chain descriptor mode */ + if (dmaConfig->mode == kSDIF_ChainDMAMode) + { + while (((dmaDesAddr->dmaDesAttribute & SDIF_DMA_DESCRIPTOR_DATA_BUFFER_END_FLAG) != + SDIF_DMA_DESCRIPTOR_DATA_BUFFER_END_FLAG) && + (dmaDesBufferSize < dmaConfig->dmaDesBufferLen * sizeof(uint32_t))) + { + /* set the OWN bit */ + dmaDesAddr->dmaDesAttribute |= SDIF_DMA_DESCRIPTOR_OWN_BY_DMA_FLAG; + dmaDesAddr++; + dmaDesBufferSize += sizeof(sdif_dma_descriptor_t); + } + /* if access dma des address overflow, return fail */ + if (dmaDesBufferSize > dmaConfig->dmaDesBufferLen * sizeof(uint32_t)) + { + return kStatus_Fail; + } + dmaDesAddr->dmaDesAttribute |= SDIF_DMA_DESCRIPTOR_OWN_BY_DMA_FLAG; + } + /* dual descriptor mode */ + else + { + while (((dmaDesAddr->dmaDesAttribute & SDIF_DMA_DESCRIPTOR_DESCRIPTOR_END_FLAG) != + SDIF_DMA_DESCRIPTOR_DESCRIPTOR_END_FLAG) && + (dmaDesBufferSize < dmaConfig->dmaDesBufferLen * sizeof(uint32_t))) + { + dmaDesAddr = (sdif_dma_descriptor_t *)tempDMADesBuffer; + dmaDesAddr->dmaDesAttribute |= SDIF_DMA_DESCRIPTOR_OWN_BY_DMA_FLAG; + tempDMADesBuffer += dmaConfig->dmaDesSkipLen; + } + /* if access dma des address overflow, return fail */ + if (dmaDesBufferSize > dmaConfig->dmaDesBufferLen * sizeof(uint32_t)) + { + return kStatus_Fail; + } + dmaDesAddr->dmaDesAttribute |= SDIF_DMA_DESCRIPTOR_OWN_BY_DMA_FLAG; + } + /* reload DMA descriptor */ + base->PLDMND = SDIF_POLL_DEMAND_VALUE; + + return kStatus_Success; +} + +static uint32_t SDIF_ReadDataPort(SDIF_Type *base, sdif_data_t *data, uint32_t transferredWords) +{ + uint32_t i; + uint32_t totalWords; + uint32_t wordsCanBeRead; /* The words can be read at this time. */ + uint32_t readWatermark = ((base->FIFOTH & SDIF_FIFOTH_RX_WMARK_MASK) >> SDIF_FIFOTH_RX_WMARK_SHIFT); + + if ((base->CTRL & SDIF_CTRL_USE_INTERNAL_DMAC_MASK) == 0U) + { + if (data->blockSize % sizeof(uint32_t) != 0U) + { + data->blockSize += + sizeof(uint32_t) - (data->blockSize % sizeof(uint32_t)); /* make the block size as word-aligned */ + } + + totalWords = ((data->blockCount * data->blockSize) / sizeof(uint32_t)); + + /* If watermark level is equal or bigger than totalWords, transfers totalWords data. */ + if (readWatermark >= totalWords) + { + wordsCanBeRead = totalWords; + } + /* If watermark level is less than totalWords and left words to be sent is equal or bigger than readWatermark, + transfers watermark level words. */ + else if ((readWatermark < totalWords) && ((totalWords - transferredWords) >= readWatermark)) + { + wordsCanBeRead = readWatermark; + } + /* If watermark level is less than totalWords and left words to be sent is less than readWatermark, transfers + left + words. */ + else + { + wordsCanBeRead = (totalWords - transferredWords); + } + + i = 0U; + while (i < wordsCanBeRead) + { + data->rxData[transferredWords++] = base->FIFO[i]; + i++; + } + } + + return transferredWords; +} + +static uint32_t SDIF_WriteDataPort(SDIF_Type *base, sdif_data_t *data, uint32_t transferredWords) +{ + uint32_t i; + uint32_t totalWords; + uint32_t wordsCanBeWrite; /* The words can be read at this time. */ + uint32_t writeWatermark = ((base->FIFOTH & SDIF_FIFOTH_TX_WMARK_MASK) >> SDIF_FIFOTH_TX_WMARK_SHIFT); + + if ((base->CTRL & SDIF_CTRL_USE_INTERNAL_DMAC_MASK) == 0U) + { + if (data->blockSize % sizeof(uint32_t) != 0U) + { + data->blockSize += + sizeof(uint32_t) - (data->blockSize % sizeof(uint32_t)); /* make the block size as word-aligned */ + } + + totalWords = ((data->blockCount * data->blockSize) / sizeof(uint32_t)); + + /* If watermark level is equal or bigger than totalWords, transfers totalWords data. */ + if (writeWatermark >= totalWords) + { + wordsCanBeWrite = totalWords; + } + /* If watermark level is less than totalWords and left words to be sent is equal or bigger than writeWatermark, + transfers watermark level words. */ + else if ((writeWatermark < totalWords) && ((totalWords - transferredWords) >= writeWatermark)) + { + wordsCanBeWrite = writeWatermark; + } + /* If watermark level is less than totalWords and left words to be sent is less than writeWatermark, transfers + left + words. */ + else + { + wordsCanBeWrite = (totalWords - transferredWords); + } + + i = 0U; + while (i < wordsCanBeWrite) + { + base->FIFO[i] = data->txData[transferredWords++]; + i++; + } + } + + return transferredWords; +} + +static status_t SDIF_ReadDataPortBlocking(SDIF_Type *base, sdif_data_t *data) +{ + uint32_t totalWords; + uint32_t transferredWords = 0U; + status_t error = kStatus_Success; + uint32_t status; + bool transferOver = false; + + if (data->blockSize % sizeof(uint32_t) != 0U) + { + data->blockSize += + sizeof(uint32_t) - (data->blockSize % sizeof(uint32_t)); /* make the block size as word-aligned */ + } + + totalWords = ((data->blockCount * data->blockSize) / sizeof(uint32_t)); + + while ((transferredWords < totalWords) && (error == kStatus_Success)) + { + /* wait data transfer complete or reach RX watermark */ + do + { + status = SDIF_GetInterruptStatus(base); + if (status & kSDIF_DataTransferError) + { + if (!(data->enableIgnoreError)) + { + error = kStatus_Fail; + break; + } + } + } while (((status & (kSDIF_DataTransferOver | kSDIF_ReadFIFORequest)) == 0U) && (!transferOver)); + + if ((status & kSDIF_DataTransferOver) == kSDIF_DataTransferOver) + { + transferOver = true; + } + + if (error == kStatus_Success) + { + transferredWords = SDIF_ReadDataPort(base, data, transferredWords); + } + + /* clear interrupt status */ + SDIF_ClearInterruptStatus(base, status); + } + + return error; +} + +static status_t SDIF_WriteDataPortBlocking(SDIF_Type *base, sdif_data_t *data) +{ + uint32_t totalWords; + uint32_t transferredWords = 0U; + status_t error = kStatus_Success; + uint32_t status; + + if (data->blockSize % sizeof(uint32_t) != 0U) + { + data->blockSize += + sizeof(uint32_t) - (data->blockSize % sizeof(uint32_t)); /* make the block size as word-aligned */ + } + + totalWords = ((data->blockCount * data->blockSize) / sizeof(uint32_t)); + + while ((transferredWords < totalWords) && (error == kStatus_Success)) + { + /* wait data transfer complete or reach RX watermark */ + do + { + status = SDIF_GetInterruptStatus(base); + if (status & kSDIF_DataTransferError) + { + if (!(data->enableIgnoreError)) + { + error = kStatus_Fail; + } + } + } while ((status & kSDIF_WriteFIFORequest) == 0U); + + if (error == kStatus_Success) + { + transferredWords = SDIF_WriteDataPort(base, data, transferredWords); + } + + /* clear interrupt status */ + SDIF_ClearInterruptStatus(base, status); + } + + while ((SDIF_GetInterruptStatus(base) & kSDIF_DataTransferOver) != kSDIF_DataTransferOver) + { + } + + if (SDIF_GetInterruptStatus(base) & kSDIF_DataTransferError) + { + if (!(data->enableIgnoreError)) + { + error = kStatus_Fail; + } + } + SDIF_ClearInterruptStatus(base, (kSDIF_DataTransferOver | kSDIF_DataTransferError)); + + return error; +} + +/*! + * brief reset the different block of the interface. + * param base SDIF peripheral base address. + * param mask indicate which block to reset. + * param timeout value,set to wait the bit self clear + * return reset result. + */ +bool SDIF_Reset(SDIF_Type *base, uint32_t mask, uint32_t timeout) +{ + /* reset through CTRL */ + base->CTRL |= mask; + /* DMA software reset */ + if (mask & kSDIF_ResetDMAInterface) + { + /* disable DMA first then do DMA software reset */ + base->BMOD = (base->BMOD & (~SDIF_BMOD_DE_MASK)) | SDIF_BMOD_SWR_MASK; + } + + /* check software DMA reset here for DMA reset also need to check this bit */ + while ((base->CTRL & mask) != 0U) + { + if (!timeout) + { + break; + } + timeout--; + } + + return timeout ? true : false; +} + +static status_t SDIF_TransferDataBlocking(SDIF_Type *base, sdif_data_t *data, bool isDMA) +{ + assert(NULL != data); + + uint32_t dmaStatus = 0U; + status_t error = kStatus_Success; + + /* in DMA mode, only need to wait the complete flag and check error */ + if (isDMA) + { + do + { + dmaStatus = SDIF_GetInternalDMAStatus(base); + if ((dmaStatus & kSDIF_DMAFatalBusError) == kSDIF_DMAFatalBusError) + { + SDIF_ClearInternalDMAStatus(base, kSDIF_DMAFatalBusError | kSDIF_AbnormalInterruptSummary); + error = kStatus_SDIF_DMATransferFailWithFBE; /* in this condition,need reset */ + } + /* Card error summary, include EBE,SBE,Data CRC,RTO,DRTO,Response error */ + if ((dmaStatus & kSDIF_DMACardErrorSummary) == kSDIF_DMACardErrorSummary) + { + SDIF_ClearInternalDMAStatus(base, kSDIF_DMACardErrorSummary | kSDIF_AbnormalInterruptSummary); + if (!(data->enableIgnoreError)) + { + error = kStatus_SDIF_DataTransferFail; + } + + /* if error occur, then return */ + break; + } + } while ((dmaStatus & (kSDIF_DMATransFinishOneDescriptor | kSDIF_DMARecvFinishOneDescriptor)) == 0U); + + /* clear the corresponding status bit */ + SDIF_ClearInternalDMAStatus(base, (kSDIF_DMATransFinishOneDescriptor | kSDIF_DMARecvFinishOneDescriptor | + kSDIF_NormalInterruptSummary)); + + SDIF_ClearInterruptStatus(base, SDIF_GetInterruptStatus(base)); + } + else + { + if (data->rxData != NULL) + { + error = SDIF_ReadDataPortBlocking(base, data); + } + else + { + error = SDIF_WriteDataPortBlocking(base, data); + } + } + + return error; +} + +/*! + * brief send command to the card + * + * This api include polling the status of the bit START_COMMAND, if 0 used as timeout value, then this function + * will return directly without polling the START_CMD status. + * param base SDIF peripheral base address. + * param command configuration collection + * param timeout not used in this function + * return command excute status + */ +status_t SDIF_SendCommand(SDIF_Type *base, sdif_command_t *cmd, uint32_t timeout) +{ + assert(NULL != cmd); + + base->CMDARG = cmd->argument; + base->CMD = SDIF_CMD_CMD_INDEX(cmd->index) | SDIF_CMD_START_CMD_MASK | (cmd->flags & (~SDIF_CMD_CMD_INDEX_MASK)); + + /* wait start_cmd bit auto clear within timeout */ + while ((base->CMD & SDIF_CMD_START_CMD_MASK) == SDIF_CMD_START_CMD_MASK) + { + } + + return kStatus_Success; +} + +/*! + * brief SDIF send initialize 80 clocks for SD card after initial + * param base SDIF peripheral base address. + * param timeout value + */ +bool SDIF_SendCardActive(SDIF_Type *base, uint32_t timeout) +{ + bool enINT = false; + + /* add for conflict with interrupt mode,close the interrupt temporary */ + if ((base->CTRL & SDIF_CTRL_INT_ENABLE_MASK) == SDIF_CTRL_INT_ENABLE_MASK) + { + enINT = true; + base->CTRL &= ~SDIF_CTRL_INT_ENABLE_MASK; + } + + /* send initialization command */ + if (SDIF_SetCommandRegister(base, SDIF_CMD_SEND_INITIALIZATION_MASK, 0U, timeout) != kStatus_Success) + { + return false; + } + + /* wait command done */ + while ((SDIF_GetInterruptStatus(base) & kSDIF_CommandDone) != kSDIF_CommandDone) + { + } + + /* clear status */ + SDIF_ClearInterruptStatus(base, kSDIF_CommandDone); + + /* add for conflict with interrupt mode */ + if (enINT) + { + base->CTRL |= SDIF_CTRL_INT_ENABLE_MASK; + } + + return true; +} + +/*! + * brief SDIF config the clock delay + * This function is used to config the cclk_in delay to + * sample and driver the data ,should meet the min setup + * time and hold time, and user need to config this parameter + * according to your board setting + * param target freq work mode + * param divider not used in this function anymore, use DELAY value instead of phase directly. + */ +void SDIF_ConfigClockDelay(uint32_t target_HZ, uint32_t divider) +{ + uint32_t sdioClkCtrl = SYSCON->SDIOCLKCTRL; + + if (target_HZ >= SDIF_CLOCK_RANGE_NEED_DELAY) + { +#ifdef SDIF_HIGHSPEED_SAMPLE_DELAY + sdioClkCtrl |= SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK | + SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY(SDIF_HIGHSPEED_SAMPLE_DELAY); +#endif +#ifdef SDIF_HIGHSPEED_DRV_DELAY + sdioClkCtrl |= + SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK | SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY(SDIF_HIGHSPEED_DRV_DELAY); +#endif + } + else + { +#if defined(SDIF_DEFAULT_MODE_SAMPLE_DELAY) + sdioClkCtrl |= SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK | + SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY(SDIF_DEFAULT_MODE_SAMPLE_DELAY); +#endif +#if defined(SDIF_DEFAULT_MODE_DRV_DELAY) + sdioClkCtrl |= SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK | + SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY(SDIF_DEFAULT_MODE_DRV_DELAY); +#endif + } + + SYSCON->SDIOCLKCTRL = sdioClkCtrl; +} + +/*! + * brief Sets the card bus clock frequency. + * + * param base SDIF peripheral base address. + * param srcClock_Hz SDIF source clock frequency united in Hz. + * param target_HZ card bus clock frequency united in Hz. + * return The nearest frequency of busClock_Hz configured to SD bus. + */ +uint32_t SDIF_SetCardClock(SDIF_Type *base, uint32_t srcClock_Hz, uint32_t target_HZ) +{ + uint32_t divider = 0U, targetFreq = target_HZ; + uint32_t syncTimeout = SDIF_TIMEOUT_VALUE; + + /* if target freq bigger than the source clk, set the target_HZ to + src clk, this interface can run up to 52MHZ with card */ + if (srcClock_Hz < targetFreq) + { + targetFreq = srcClock_Hz; + } + + /* disable the clock first,need sync to CIU*/ + SDIF_EnableCardClock(base, false); + /* update the clock register and wait the pre-transfer complete */ + if (SDIF_SetCommandRegister(base, kSDIF_CmdUpdateClockRegisterOnly | kSDIF_WaitPreTransferComplete, 0U, + syncTimeout) != kStatus_Success) + { + return 0U; + } + + /*calculate the divider*/ + if (targetFreq != srcClock_Hz) + { + divider = (srcClock_Hz / targetFreq + 1U) / 2U; + } + /* load the clock divider */ + base->CLKDIV = SDIF_CLKDIV_CLK_DIVIDER0(divider); + /* update the divider to CIU */ + if (SDIF_SetCommandRegister(base, kSDIF_CmdUpdateClockRegisterOnly | kSDIF_WaitPreTransferComplete, 0U, + syncTimeout) != kStatus_Success) + { + return 0U; + } + + /* enable the card clock and sync to CIU */ + SDIF_EnableCardClock(base, true); + if (SDIF_SetCommandRegister(base, kSDIF_CmdUpdateClockRegisterOnly | kSDIF_WaitPreTransferComplete, 0U, + syncTimeout) != kStatus_Success) + { + return 0U; + } + + /* config the clock delay to meet the hold time and setup time */ + SDIF_ConfigClockDelay(target_HZ, divider); + + /* return the actual card clock freq */ + return (divider != 0U) ? (srcClock_Hz / (divider * 2U)) : srcClock_Hz; +} + +/*! + * brief SDIF abort the read data when SDIF card is in suspend state + * Once assert this bit,data state machine will be reset which is waiting for the + * next blocking data,used in SDIO card suspend sequence,should call after suspend + * cmd send + * param base SDIF peripheral base address. + * param timeout value to wait this bit self clear which indicate the data machine + * reset to idle + */ +bool SDIF_AbortReadData(SDIF_Type *base, uint32_t timeout) +{ + /* assert this bit to reset the data machine to abort the read data */ + base->CTRL |= SDIF_CTRL_ABORT_READ_DATA_MASK; + /* polling the bit self clear */ + while ((base->CTRL & SDIF_CTRL_ABORT_READ_DATA_MASK) == SDIF_CTRL_ABORT_READ_DATA_MASK) + { + if (!timeout) + { + break; + } + timeout--; + } + + return base->CTRL & SDIF_CTRL_ABORT_READ_DATA_MASK ? false : true; +} + +/*! + * brief SDIF internal DMA config function + * param base SDIF peripheral base address. + * param internal DMA configuration collection + * param data buffer pointer + * param data buffer size + */ +status_t SDIF_InternalDMAConfig(SDIF_Type *base, sdif_dma_config_t *config, const uint32_t *data, uint32_t dataSize) +{ + assert(NULL != config); + assert(NULL != data); + + uint32_t dmaEntry = 0U, i, dmaBufferSize = 0U, dmaBuffer1Size = 0U; + uint32_t *tempDMADesBuffer = config->dmaDesBufferStartAddr; + const uint32_t *dataBuffer = data; + sdif_dma_descriptor_t *descriptorPoniter = NULL; + uint32_t maxDMABuffer = FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE * (config->mode); + + if ((((uint32_t)data % SDIF_INTERNAL_DMA_ADDR_ALIGN) != 0U) || + (((uint32_t)tempDMADesBuffer % SDIF_INTERNAL_DMA_ADDR_ALIGN) != 0U)) + { + return kStatus_SDIF_DMAAddrNotAlign; + } + + /* check the read/write data size,must be a multiple of 4 */ + if (dataSize % sizeof(uint32_t) != 0U) + { + dataSize += sizeof(uint32_t) - (dataSize % sizeof(uint32_t)); + } + + /*config the bus mode*/ + if (config->enableFixBurstLen) + { + base->BMOD |= SDIF_BMOD_FB_MASK; + } + + /* calculate the dma descriptor entry due to DMA buffer size limit */ + /* if data size smaller than one descriptor buffer size */ + if (dataSize > maxDMABuffer) + { + dmaEntry = dataSize / maxDMABuffer + (dataSize % maxDMABuffer ? 1U : 0U); + } + else /* need one dma descriptor */ + { + dmaEntry = 1U; + } + + /* check the DMA descriptor buffer len one more time,it is user's responsibility to make sure the DMA descriptor + table + size is bigger enough to hold the transfer descriptor */ + if (config->dmaDesBufferLen * sizeof(uint32_t) < (dmaEntry * sizeof(sdif_dma_descriptor_t) + config->dmaDesSkipLen)) + { + return kStatus_SDIF_DescriptorBufferLenError; + } + + switch (config->mode) + { + case kSDIF_DualDMAMode: + base->BMOD |= SDIF_BMOD_DSL(config->dmaDesSkipLen); /* config the distance between the DMA descriptor */ + for (i = 0U; i < dmaEntry; i++) + { + if (dataSize > FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE) + { + dmaBufferSize = FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE; + dataSize -= dmaBufferSize; + dmaBuffer1Size = dataSize > FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE ? + FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE : + dataSize; + dataSize -= dmaBuffer1Size; + } + else + { + dmaBufferSize = dataSize; + dmaBuffer1Size = 0U; + } + + descriptorPoniter = (sdif_dma_descriptor_t *)tempDMADesBuffer; + if (i == 0U) + { + descriptorPoniter->dmaDesAttribute = SDIF_DMA_DESCRIPTOR_DATA_BUFFER_START_FLAG; + } + descriptorPoniter->dmaDesAttribute |= + SDIF_DMA_DESCRIPTOR_OWN_BY_DMA_FLAG | SDIF_DMA_DESCRIPTOR_DISABLE_COMPLETE_INT_FLAG; + descriptorPoniter->dmaDataBufferSize = + SDIF_DMA_DESCRIPTOR_BUFFER1_SIZE(dmaBufferSize) | SDIF_DMA_DESCRIPTOR_BUFFER2_SIZE(dmaBuffer1Size); + + descriptorPoniter->dmaDataBufferAddr0 = dataBuffer; + descriptorPoniter->dmaDataBufferAddr1 = dataBuffer + dmaBufferSize / sizeof(uint32_t); + dataBuffer += (dmaBufferSize + dmaBuffer1Size) / sizeof(uint32_t); + + /* descriptor skip length */ + tempDMADesBuffer += config->dmaDesSkipLen + sizeof(sdif_dma_descriptor_t) / sizeof(uint32_t); + } + /* enable the completion interrupt when reach the last descriptor */ + descriptorPoniter->dmaDesAttribute &= ~SDIF_DMA_DESCRIPTOR_DISABLE_COMPLETE_INT_FLAG; + descriptorPoniter->dmaDesAttribute |= + SDIF_DMA_DESCRIPTOR_DATA_BUFFER_END_FLAG | SDIF_DMA_DESCRIPTOR_DESCRIPTOR_END_FLAG; + break; + + case kSDIF_ChainDMAMode: + for (i = 0U; i < dmaEntry; i++) + { + if (dataSize > FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE) + { + dmaBufferSize = FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE; + dataSize -= FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE; + } + else + { + dmaBufferSize = dataSize; + } + + descriptorPoniter = (sdif_dma_descriptor_t *)tempDMADesBuffer; + if (i == 0U) + { + descriptorPoniter->dmaDesAttribute = SDIF_DMA_DESCRIPTOR_DATA_BUFFER_START_FLAG; + } + descriptorPoniter->dmaDesAttribute |= SDIF_DMA_DESCRIPTOR_OWN_BY_DMA_FLAG | + SDIF_DMA_DESCRIPTOR_SECOND_ADDR_CHAIN_FLAG | + SDIF_DMA_DESCRIPTOR_DISABLE_COMPLETE_INT_FLAG; + descriptorPoniter->dmaDataBufferSize = + SDIF_DMA_DESCRIPTOR_BUFFER1_SIZE(dmaBufferSize); /* use only buffer 1 for data buffer*/ + descriptorPoniter->dmaDataBufferAddr0 = dataBuffer; + dataBuffer += dmaBufferSize / sizeof(uint32_t); + tempDMADesBuffer += + sizeof(sdif_dma_descriptor_t) / sizeof(uint32_t); /* calculate the next descriptor address */ + /* this descriptor buffer2 pointer to the next descriptor address */ + descriptorPoniter->dmaDataBufferAddr1 = tempDMADesBuffer; + } + /* enable the completion interrupt when reach the last descriptor */ + descriptorPoniter->dmaDesAttribute &= ~SDIF_DMA_DESCRIPTOR_DISABLE_COMPLETE_INT_FLAG; + descriptorPoniter->dmaDesAttribute |= SDIF_DMA_DESCRIPTOR_DATA_BUFFER_END_FLAG; + break; + + default: + break; + } + + /* use internal DMA interface */ + base->CTRL |= SDIF_CTRL_USE_INTERNAL_DMAC_MASK; + /* enable the internal SD/MMC DMA */ + base->BMOD |= SDIF_BMOD_DE_MASK; + /* enable DMA status check */ + base->IDINTEN |= kSDIF_DMAAllStatus; + /* load DMA descriptor buffer address */ + base->DBADDR = (uint32_t)config->dmaDesBufferStartAddr; + + return kStatus_Success; +} + +#if defined(FSL_FEATURE_SDIF_ONE_INSTANCE_SUPPORT_TWO_CARD) && FSL_FEATURE_SDIF_ONE_INSTANCE_SUPPORT_TWO_CARD +/*! + * brief set card data bus width + * param base SDIF peripheral base address. + * param data bus width type + */ +void SDIF_SetCardBusWidth(SDIF_Type *base, sdif_bus_width_t type) +{ + switch (type) + { + case kSDIF_Bus1BitWidth: + base->CTYPE &= ~(SDIF_CTYPE_CARD0_WIDTH0_MASK | SDIF_CTYPE_CARD0_WIDTH1_MASK); + break; + case kSDIF_Bus4BitWidth: + base->CTYPE = (base->CTYPE & (~SDIF_CTYPE_CARD0_WIDTH1_MASK)) | SDIF_CTYPE_CARD0_WIDTH0_MASK; + break; + case kSDIF_Bus8BitWidth: + base->CTYPE |= SDIF_CTYPE_CARD0_WIDTH1_MASK; + break; + default: + break; + } +} + +/*! + * brief set card1 data bus width + * param base SDIF peripheral base address. + * param data bus width type + */ +void SDIF_SetCard1BusWidth(SDIF_Type *base, sdif_bus_width_t type) +{ + switch (type) + { + case kSDIF_Bus1BitWidth: + base->CTYPE &= ~(SDIF_CTYPE_CARD1_WIDTH0_MASK | SDIF_CTYPE_CARD1_WIDTH1_MASK); + break; + case kSDIF_Bus4BitWidth: + base->CTYPE = (base->CTYPE & (~SDIF_CTYPE_CARD1_WIDTH1_MASK)) | SDIF_CTYPE_CARD1_WIDTH0_MASK; + break; + case kSDIF_Bus8BitWidth: + base->CTYPE |= SDIF_CTYPE_CARD1_WIDTH1_MASK; + break; + default: + break; + } +} +#else +/*! + * brief set card data bus width + * param base SDIF peripheral base address. + * param data bus width type + */ +void SDIF_SetCardBusWidth(SDIF_Type *base, sdif_bus_width_t type) +{ + switch (type) + { + case kSDIF_Bus1BitWidth: + base->CTYPE &= ~(SDIF_CTYPE_CARD_WIDTH0_MASK | SDIF_CTYPE_CARD_WIDTH1_MASK); + break; + case kSDIF_Bus4BitWidth: + base->CTYPE = (base->CTYPE & (~SDIF_CTYPE_CARD_WIDTH1_MASK)) | SDIF_CTYPE_CARD_WIDTH0_MASK; + break; + case kSDIF_Bus8BitWidth: + base->CTYPE |= SDIF_CTYPE_CARD_WIDTH1_MASK; + break; + default: + break; + } +} +#endif + +/*! + * brief SDIF module initialization function. + * + * Configures the SDIF according to the user configuration. + * param base SDIF peripheral base address. + * param config SDIF configuration information. + */ +void SDIF_Init(SDIF_Type *base, sdif_config_t *config) +{ + assert(NULL != config); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock. */ + CLOCK_EnableClock(kCLOCK_Sdio); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) + /* Reset the module. */ + RESET_PeripheralReset(kSDIO_RST_SHIFT_RSTn); +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + + /*config timeout register */ + base->TMOUT = ((base->TMOUT) & ~(SDIF_TMOUT_RESPONSE_TIMEOUT_MASK | SDIF_TMOUT_DATA_TIMEOUT_MASK)) | + SDIF_TMOUT_RESPONSE_TIMEOUT(config->responseTimeout) | SDIF_TMOUT_DATA_TIMEOUT(config->dataTimeout); + + /* config the card detect debounce clock count */ + base->DEBNCE = SDIF_DEBNCE_DEBOUNCE_COUNT(config->cardDetDebounce_Clock); + + /*config the watermark/burst transfer value */ + base->FIFOTH = + SDIF_FIFOTH_TX_WMARK(SDIF_TX_WATERMARK) | SDIF_FIFOTH_RX_WMARK(SDIF_RX_WATERMARK) | SDIF_FIFOTH_DMA_MTS(1U); + + /* enable the interrupt status */ + SDIF_EnableInterrupt(base, kSDIF_AllInterruptStatus); + + /* clear all interrupt/DMA status */ + SDIF_ClearInterruptStatus(base, kSDIF_AllInterruptStatus); + SDIF_ClearInternalDMAStatus(base, kSDIF_DMAAllStatus); +} + +/*! + * brief SDIF transfer function data/cmd in a blocking way + * param base SDIF peripheral base address. + * param DMA config structure + * 1. NULL + * In this condition, polling transfer mode is selected + * 2. avaliable DMA config + * In this condition, DMA transfer mode is selected + * param sdif transfer configuration collection + */ +status_t SDIF_TransferBlocking(SDIF_Type *base, sdif_dma_config_t *dmaConfig, sdif_transfer_t *transfer) +{ + assert(NULL != transfer); + + bool enDMA = true; + sdif_data_t *data = transfer->data; + status_t error = kStatus_Fail; + + /* if need transfer data in dma mode, config the DMA descriptor first */ + if ((data != NULL) && (dmaConfig != NULL)) + { + if ((error = SDIF_InternalDMAConfig(base, dmaConfig, data->rxData ? data->rxData : data->txData, + data->blockSize * data->blockCount)) == + kStatus_SDIF_DescriptorBufferLenError) + { + return kStatus_SDIF_DescriptorBufferLenError; + } + /* if DMA descriptor address or data buffer address not align with SDIF_INTERNAL_DMA_ADDR_ALIGN, switch to + polling transfer mode, disable the internal DMA */ + if (error == kStatus_SDIF_DMAAddrNotAlign) + { + enDMA = false; + } + } + else + { + enDMA = false; + } + + if (!enDMA) + { + SDIF_EnableInternalDMA(base, false); + /* reset FIFO and clear RAW status for host transfer */ + SDIF_Reset(base, kSDIF_ResetFIFO, SDIF_RESET_TIMEOUT_VALUE); + SDIF_ClearInterruptStatus(base, kSDIF_AllInterruptStatus); + } + + /* config the transfer parameter */ + if (SDIF_TransferConfig(base, transfer, enDMA) != kStatus_Success) + { + return kStatus_SDIF_InvalidArgument; + } + + /* send command first, do not wait start bit auto cleared, command done bit should wait while sending normal command + */ + SDIF_SendCommand(base, transfer->command, 0U); + + /* wait the command transfer done and check if error occurs */ + if (SDIF_WaitCommandDone(base, transfer->command) != kStatus_Success) + { + return kStatus_SDIF_SendCmdFail; + } + + /* if use DMA transfer mode ,check the corresponding status bit */ + if (data != NULL) + { + /* handle data transfer */ + if (SDIF_TransferDataBlocking(base, data, enDMA) != kStatus_Success) + { + return kStatus_SDIF_DataTransferFail; + } + } + + return kStatus_Success; +} + +/*! + * brief SDIF transfer function data/cmd in a non-blocking way + * this API should be use in interrupt mode, when use this API user + * must call SDIF_TransferCreateHandle first, all status check through + * interrupt + * param base SDIF peripheral base address. + * param sdif handle + * param DMA config structure + * This parameter can be config as: + * 1. NULL + In this condition, polling transfer mode is selected + 2. avaliable DMA config + In this condition, DMA transfer mode is selected + * param sdif transfer configuration collection + */ +status_t SDIF_TransferNonBlocking(SDIF_Type *base, + sdif_handle_t *handle, + sdif_dma_config_t *dmaConfig, + sdif_transfer_t *transfer) +{ + assert(NULL != transfer); + + sdif_data_t *data = transfer->data; + status_t error = kStatus_Fail; + bool enDMA = true; + + /* save the data and command before transfer */ + handle->data = transfer->data; + handle->command = transfer->command; + handle->transferredWords = 0U; + + if ((data != NULL) && (dmaConfig != NULL)) + { + /* use internal DMA mode to transfer between the card and host*/ + if ((error = SDIF_InternalDMAConfig(base, dmaConfig, data->rxData ? data->rxData : data->txData, + data->blockSize * data->blockCount)) == + kStatus_SDIF_DescriptorBufferLenError) + { + return kStatus_SDIF_DescriptorBufferLenError; + } + /* if DMA descriptor address or data buffer address not align with SDIF_INTERNAL_DMA_ADDR_ALIGN, switch to + polling transfer mode, disable the internal DMA */ + if (error == kStatus_SDIF_DMAAddrNotAlign) + { + enDMA = false; + } + } + else + { + enDMA = false; + } + + if (!enDMA) + { + SDIF_EnableInternalDMA(base, false); + /* reset FIFO and clear RAW status for host transfer */ + SDIF_Reset(base, kSDIF_ResetFIFO, SDIF_RESET_TIMEOUT_VALUE); + SDIF_ClearInterruptStatus(base, kSDIF_AllInterruptStatus); + } + + /* config the transfer parameter */ + if (SDIF_TransferConfig(base, transfer, enDMA) != kStatus_Success) + { + return kStatus_SDIF_InvalidArgument; + } + + /* send command first, do not wait start bit auto cleared, command done bit should wait while sending normal command + */ + SDIF_SendCommand(base, transfer->command, 0U); + + return kStatus_Success; +} + +/*! + * brief Creates the SDIF handle. + * register call back function for interrupt and enable the interrupt + * param base SDIF peripheral base address. + * param handle SDIF handle pointer. + * param callback Structure pointer to contain all callback functions. + * param userData Callback function parameter. + */ +void SDIF_TransferCreateHandle(SDIF_Type *base, + sdif_handle_t *handle, + sdif_transfer_callback_t *callback, + void *userData) +{ + assert(handle); + assert(callback); + + /* reset the handle. */ + memset(handle, 0U, sizeof(*handle)); + + /* Set the callback. */ + handle->callback.SDIOInterrupt = callback->SDIOInterrupt; + handle->callback.DMADesUnavailable = callback->DMADesUnavailable; + handle->callback.CommandReload = callback->CommandReload; + handle->callback.TransferComplete = callback->TransferComplete; + handle->callback.cardInserted = callback->cardInserted; + handle->userData = userData; + + /* Save the handle in global variables to support the double weak mechanism. */ + s_sdifHandle[SDIF_GetInstance(base)] = handle; + + /* save IRQ handler */ + s_sdifIsr = SDIF_TransferHandleIRQ; + + /* enable the global interrupt */ + SDIF_EnableGlobalInterrupt(base, true); + + EnableIRQ(s_sdifIRQ[SDIF_GetInstance(base)]); +} + +/*! + * brief SDIF return the controller capability + * param base SDIF peripheral base address. + * param sdif capability pointer + */ +void SDIF_GetCapability(SDIF_Type *base, sdif_capability_t *capability) +{ + assert(NULL != capability); + + /* Initializes the configure structure to zero. */ + memset(capability, 0, sizeof(*capability)); + + capability->sdVersion = SDIF_SUPPORT_SD_VERSION; + capability->mmcVersion = SDIF_SUPPORT_MMC_VERSION; + capability->maxBlockLength = SDIF_BLKSIZ_BLOCK_SIZE_MASK; + /* set the max block count = max byte count / max block size */ + capability->maxBlockCount = SDIF_BYTCNT_BYTE_COUNT_MASK / SDIF_BLKSIZ_BLOCK_SIZE_MASK; + capability->flags = kSDIF_SupportHighSpeedFlag | kSDIF_SupportDmaFlag | kSDIF_SupportSuspendResumeFlag | + kSDIF_SupportV330Flag | kSDIF_Support4BitFlag | kSDIF_Support8BitFlag; +} + +static void SDIF_TransferHandleCommand(SDIF_Type *base, sdif_handle_t *handle, uint32_t interruptFlags) +{ + assert(handle->command); + + /* cmd buffer full, in this condition user need re-send the command */ + if (interruptFlags & kSDIF_HardwareLockError) + { + if (handle->callback.CommandReload) + { + handle->callback.CommandReload(base, handle->userData); + } + } + /* transfer command done */ + else + { + if ((kSDIF_CommandDone & interruptFlags) != 0U) + { + /* transfer error */ + if (interruptFlags & (kSDIF_ResponseError | kSDIF_ResponseCRCError | kSDIF_ResponseTimeout)) + { + handle->callback.TransferComplete(base, handle, kStatus_SDIF_SendCmdFail, handle->userData); + } + else + { + SDIF_ReadCommandResponse(base, handle->command); + if (((handle->data) == NULL) && (handle->callback.TransferComplete)) + { + handle->callback.TransferComplete(base, handle, kStatus_Success, handle->userData); + } + } + } + } +} + +static void SDIF_TransferHandleData(SDIF_Type *base, sdif_handle_t *handle, uint32_t interruptFlags) +{ + assert(handle->data); + + /* data starvation by host time out, software should read/write FIFO*/ + if (interruptFlags & kSDIF_DataStarvationByHostTimeout) + { + if (handle->data->rxData != NULL) + { + handle->transferredWords = SDIF_ReadDataPort(base, handle->data, handle->transferredWords); + } + else if (handle->data->txData != NULL) + { + handle->transferredWords = SDIF_WriteDataPort(base, handle->data, handle->transferredWords); + } + else + { + handle->callback.TransferComplete(base, handle, kStatus_SDIF_DataTransferFail, handle->userData); + } + } + /* data transfer fail */ + else if (interruptFlags & kSDIF_DataTransferError) + { + if (!handle->data->enableIgnoreError) + { + handle->callback.TransferComplete(base, handle, kStatus_SDIF_DataTransferFail, handle->userData); + } + } + /* need fill data to FIFO */ + else if (interruptFlags & kSDIF_WriteFIFORequest) + { + handle->transferredWords = SDIF_WriteDataPort(base, handle->data, handle->transferredWords); + } + /* need read data from FIFO */ + else if (interruptFlags & kSDIF_ReadFIFORequest) + { + handle->transferredWords = SDIF_ReadDataPort(base, handle->data, handle->transferredWords); + } + else + { + } + + /* data transfer over */ + if (interruptFlags & kSDIF_DataTransferOver) + { + while ((handle->data->rxData != NULL) && ((base->STATUS & SDIF_STATUS_FIFO_COUNT_MASK) != 0U)) + { + handle->transferredWords = SDIF_ReadDataPort(base, handle->data, handle->transferredWords); + } + handle->callback.TransferComplete(base, handle, kStatus_Success, handle->userData); + } +} + +static void SDIF_TransferHandleDMA(SDIF_Type *base, sdif_handle_t *handle, uint32_t interruptFlags) +{ + if (interruptFlags & kSDIF_DMAFatalBusError) + { + handle->callback.TransferComplete(base, handle, kStatus_SDIF_DMATransferFailWithFBE, handle->userData); + } + else if (interruptFlags & kSDIF_DMADescriptorUnavailable) + { + if (handle->callback.DMADesUnavailable) + { + handle->callback.DMADesUnavailable(base, handle->userData); + } + } + else if ((interruptFlags & (kSDIF_AbnormalInterruptSummary | kSDIF_DMACardErrorSummary)) && + (!handle->data->enableIgnoreError)) + { + handle->callback.TransferComplete(base, handle, kStatus_SDIF_DataTransferFail, handle->userData); + } + /* card normal summary */ + else + { + handle->callback.TransferComplete(base, handle, kStatus_Success, handle->userData); + } +} + +static void SDIF_TransferHandleSDIOInterrupt(SDIF_Type *base, sdif_handle_t *handle) +{ + if (handle->callback.SDIOInterrupt != NULL) + { + handle->callback.SDIOInterrupt(base, handle->userData); + } +} + +static void SDIF_TransferHandleCardDetect(SDIF_Type *base, sdif_handle_t *handle) +{ + if (SDIF_DetectCardInsert(base, false)) + { + if ((handle->callback.cardInserted) != NULL) + { + handle->callback.cardInserted(base, handle->userData); + } + } + else + { + if ((handle->callback.cardRemoved) != NULL) + { + handle->callback.cardRemoved(base, handle->userData); + } + } +} + +static void SDIF_TransferHandleIRQ(SDIF_Type *base, sdif_handle_t *handle) +{ + assert(handle); + + uint32_t interruptFlags, dmaInterruptFlags; + + interruptFlags = SDIF_GetEnabledInterruptStatus(base); + dmaInterruptFlags = SDIF_GetEnabledDMAInterruptStatus(base); + + if ((interruptFlags & kSDIF_CommandTransferStatus) != 0U) + { + SDIF_TransferHandleCommand(base, handle, (interruptFlags & kSDIF_CommandTransferStatus)); + } + if ((interruptFlags & kSDIF_DataTransferStatus) != 0U) + { + SDIF_TransferHandleData(base, handle, (interruptFlags & kSDIF_DataTransferStatus)); + } + if (interruptFlags & kSDIF_SDIOInterrupt) + { + SDIF_TransferHandleSDIOInterrupt(base, handle); + } + if (dmaInterruptFlags & kSDIF_DMAAllStatus) + { + SDIF_TransferHandleDMA(base, handle, dmaInterruptFlags); + } + if (interruptFlags & kSDIF_CardDetect) + { + SDIF_TransferHandleCardDetect(base, handle); + } + + SDIF_ClearInterruptStatus(base, interruptFlags); + SDIF_ClearInternalDMAStatus(base, dmaInterruptFlags); +} + +/*! + * brief SDIF module deinit function. + * user should call this function follow with IP reset + * param base SDIF peripheral base address. + */ +void SDIF_Deinit(SDIF_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable the clock. */ + CLOCK_DisableClock(kCLOCK_Sdio); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + /* disable the SDIOCLKCTRL */ + SYSCON->SDIOCLKCTRL &= ~(SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK | + SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK | SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) + /* Reset the module. */ + RESET_PeripheralReset(kSDIO_RST_SHIFT_RSTn); +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ +} + +#if defined(SDIF) +void SDIF_DriverIRQHandler(void) +{ + assert(s_sdifHandle[0]); + + s_sdifIsr(SDIF, s_sdifHandle[0]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_sdif.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_sdif.h new file mode 100644 index 000000000..e8149629c --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_sdif.h @@ -0,0 +1,1033 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_SDIF_H_ +#define _FSL_SDIF_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup sdif + * @{ + */ + +/********************************** + * Definitions. + *****************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief Driver version 2.0.11. */ +#define FSL_SDIF_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 11U)) +/*@}*/ + +/*! @brief SDIOCLKCTRL setting + * Below clock delay setting should depend on specific platform, so + * it can be redefined when timing mismatch issue occur. + * Such as: response error/CRC error and so on + */ +/*! @brief clock range value which need to add delay to avoid timing issue */ +#ifndef SDIF_CLOCK_RANGE_NEED_DELAY +#define SDIF_CLOCK_RANGE_NEED_DELAY (50000000U) +#endif + +/* + * Fixed delay configuration + * min hold time:2ns + * min setup time: 6ns + * delay = (x+1)*250ps + */ +/*! @brief High speed mode clk_sample fixed delay*/ +#ifndef SDIF_HIGHSPEED_SAMPLE_DELAY +#define SDIF_HIGHSPEED_SAMPLE_DELAY (12U) /*!< 12 * 250ps = 3ns */ +#endif +/*! @brief High speed mode clk_drv fixed delay */ +#ifndef SDIF_HIGHSPEED_DRV_DELAY +#define SDIF_HIGHSPEED_DRV_DELAY (0x1FU) /*!< 31 * 250ps = 7.75ns */ +#endif + +/* + * Phase shift delay configuration + * 0 degree: no delay + * 90 degree: 0.25/source clk value + * 180 degree: 0.50/source clk value + * 270 degree: 0.75/source clk value + */ +/*! @brief High speed mode clk_sample phase shift */ +#ifndef SDIF_HIGHSPEED_SAMPLE_PHASE_SHIFT +#define SDIF_HIGHSPEED_SAMPLE_PHASE_SHIFT (0U) +#endif +/*! @brief High speed mode clk_drv phase shift */ +#ifndef SDIF_HIGHSPEED_DRV_PHASE_SHIFT +#define SDIF_HIGHSPEED_DRV_PHASE_SHIFT (1U) /* 90 degrees clk_drv phase delay */ +#endif +/*! @brief default mode sample fixed delay */ +#ifndef SDIF_DEFAULT_MODE_SAMPLE_DELAY +#define SDIF_DEFAULT_MODE_SAMPLE_DELAY (31U) /*!< 31 * 250ps = 7.75ns */ +#endif + +#ifndef SDIF_DEFAULT_MODE_DRV_DELAY +#define SDIF_DEFAULT_MODE_DRV_DELAY (31U) /*!< 31 * 250ps = 7.75ns */ +#endif + +/*! @brief SDIF internal DMA descriptor address and the data buffer address align */ +#define SDIF_INTERNAL_DMA_ADDR_ALIGN (4U) +/*! @brief SDIF DMA descriptor flag */ +#define SDIF_DMA_DESCRIPTOR_DISABLE_COMPLETE_INT_FLAG (1U << 1U) +#define SDIF_DMA_DESCRIPTOR_DATA_BUFFER_END_FLAG (1U << 2U) +#define SDIF_DMA_DESCRIPTOR_DATA_BUFFER_START_FLAG (1U << 3U) +#define SDIF_DMA_DESCRIPTOR_SECOND_ADDR_CHAIN_FLAG (1U << 4U) +#define SDIF_DMA_DESCRIPTOR_DESCRIPTOR_END_FLAG (1U << 5U) +#define SDIF_DMA_DESCRIPTOR_OWN_BY_DMA_FLAG (1U << 31U) + +/*! @brief SDIF status */ +enum _sdif_status +{ + kStatus_SDIF_DescriptorBufferLenError = MAKE_STATUS(kStatusGroup_SDIF, 0U), /*!< Set DMA descriptor failed */ + kStatus_SDIF_InvalidArgument = MAKE_STATUS(kStatusGroup_SDIF, 1U), /*!< invalid argument status */ + kStatus_SDIF_SyncCmdTimeout = MAKE_STATUS(kStatusGroup_SDIF, 2U), /*!< sync command to CIU timeout status */ + kStatus_SDIF_SendCmdFail = MAKE_STATUS(kStatusGroup_SDIF, 3U), /*!< send command to card fail */ + kStatus_SDIF_SendCmdErrorBufferFull = + MAKE_STATUS(kStatusGroup_SDIF, 4U), /*!< send command to card fail, due to command buffer full + user need to resend this command */ + kStatus_SDIF_DMATransferFailWithFBE = + MAKE_STATUS(kStatusGroup_SDIF, 5U), /*!< DMA transfer data fail with fatal bus error , + to do with this error :issue a hard reset/controller reset*/ + kStatus_SDIF_DMATransferDescriptorUnavailable = + MAKE_STATUS(kStatusGroup_SDIF, 6U), /*!< DMA descriptor unavailable */ + kStatus_SDIF_DataTransferFail = MAKE_STATUS(kStatusGroup_SDIF, 6U), /*!< transfer data fail */ + kStatus_SDIF_ResponseError = MAKE_STATUS(kStatusGroup_SDIF, 7U), /*!< response error */ + kStatus_SDIF_DMAAddrNotAlign = MAKE_STATUS(kStatusGroup_SDIF, 8U), /*!< DMA address not align */ +}; + +/*! @brief Host controller capabilities flag mask */ +enum _sdif_capability_flag +{ + kSDIF_SupportHighSpeedFlag = 0x1U, /*!< Support high-speed */ + kSDIF_SupportDmaFlag = 0x2U, /*!< Support DMA */ + kSDIF_SupportSuspendResumeFlag = 0x4U, /*!< Support suspend/resume */ + kSDIF_SupportV330Flag = 0x8U, /*!< Support voltage 3.3V */ + kSDIF_Support4BitFlag = 0x10U, /*!< Support 4 bit mode */ + kSDIF_Support8BitFlag = 0x20U, /*!< Support 8 bit mode */ +}; + +/*! @brief define the reset type */ +enum _sdif_reset_type +{ + kSDIF_ResetController = SDIF_CTRL_CONTROLLER_RESET_MASK, /*!< reset controller,will reset: BIU/CIU interface + CIU and state machine,ABORT_READ_DATA,SEND_IRQ_RESPONSE + and READ_WAIT bits of control register,START_CMD bit of + the command register*/ + kSDIF_ResetFIFO = SDIF_CTRL_FIFO_RESET_MASK, /*!< reset data FIFO*/ + kSDIF_ResetDMAInterface = SDIF_CTRL_DMA_RESET_MASK, /*!< reset DMA interface */ + + kSDIF_ResetAll = kSDIF_ResetController | kSDIF_ResetFIFO | /*!< reset all*/ + kSDIF_ResetDMAInterface, +}; + +/*! @brief define the card bus width type */ +typedef enum _sdif_bus_width +{ + kSDIF_Bus1BitWidth = 0U, /*!< 1bit bus width, 1bit mode and 4bit mode + share one register bit */ + kSDIF_Bus4BitWidth = 1U, /*!< 4bit mode mask */ + kSDIF_Bus8BitWidth = 2U, /*!< support 8 bit mode */ +} sdif_bus_width_t; + +/*! @brief define the command flags */ +enum _sdif_command_flags +{ + kSDIF_CmdResponseExpect = SDIF_CMD_RESPONSE_EXPECT_MASK, /*!< command request response*/ + kSDIF_CmdResponseLengthLong = SDIF_CMD_RESPONSE_LENGTH_MASK, /*!< command response length long */ + kSDIF_CmdCheckResponseCRC = SDIF_CMD_CHECK_RESPONSE_CRC_MASK, /*!< request check command response CRC*/ + kSDIF_DataExpect = SDIF_CMD_DATA_EXPECTED_MASK, /*!< request data transfer,either read/write*/ + kSDIF_DataWriteToCard = SDIF_CMD_READ_WRITE_MASK, /*!< data transfer direction */ + kSDIF_DataStreamTransfer = SDIF_CMD_TRANSFER_MODE_MASK, /*!< data transfer mode :stream/block transfer command */ + kSDIF_DataTransferAutoStop = SDIF_CMD_SEND_AUTO_STOP_MASK, /*!< data transfer with auto stop at the end of */ + kSDIF_WaitPreTransferComplete = + SDIF_CMD_WAIT_PRVDATA_COMPLETE_MASK, /*!< wait pre transfer complete before sending this cmd */ + kSDIF_TransferStopAbort = SDIF_CMD_STOP_ABORT_CMD_MASK, /*!< when host issue stop or abort cmd to stop data transfer + ,this bit should set so that cmd/data state-machines of CIU + can return to idle correctly*/ + kSDIF_SendInitialization = + SDIF_CMD_SEND_INITIALIZATION_MASK, /*!< send initialization 80 clocks for SD card after power on */ + kSDIF_CmdUpdateClockRegisterOnly = + SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_MASK, /*!< send cmd update the CIU clock register only */ + kSDIF_CmdtoReadCEATADevice = SDIF_CMD_READ_CEATA_DEVICE_MASK, /*!< host is perform read access to CE-ATA device */ + kSDIF_CmdExpectCCS = SDIF_CMD_CCS_EXPECTED_MASK, /*!< command expect command completion signal signal */ + kSDIF_BootModeEnable = SDIF_CMD_ENABLE_BOOT_MASK, /*!< this bit should only be set for mandatory boot mode */ + kSDIF_BootModeExpectAck = SDIF_CMD_EXPECT_BOOT_ACK_MASK, /*!< boot mode expect ack */ + kSDIF_BootModeDisable = SDIF_CMD_DISABLE_BOOT_MASK, /*!< when software set this bit along with START_CMD, CIU + terminates the boot operation*/ + kSDIF_BootModeAlternate = SDIF_CMD_BOOT_MODE_MASK, /*!< select boot mode ,alternate or mandatory*/ + kSDIF_CmdVoltageSwitch = SDIF_CMD_VOLT_SWITCH_MASK, /*!< this bit set for CMD11 only */ + kSDIF_CmdDataUseHoldReg = SDIF_CMD_USE_HOLD_REG_MASK, /*!< cmd and data send to card through the HOLD register*/ +}; + +/*! @brief The command type */ +enum _sdif_command_type +{ + kCARD_CommandTypeNormal = 0U, /*!< Normal command */ + kCARD_CommandTypeSuspend = 1U, /*!< Suspend command */ + kCARD_CommandTypeResume = 2U, /*!< Resume command */ + kCARD_CommandTypeAbort = 3U, /*!< Abort command */ +}; + +/*! + * @brief The command response type. + * + * Define the command response type from card to host controller. + */ +enum _sdif_response_type +{ + kCARD_ResponseTypeNone = 0U, /*!< Response type: none */ + kCARD_ResponseTypeR1 = 1U, /*!< Response type: R1 */ + kCARD_ResponseTypeR1b = 2U, /*!< Response type: R1b */ + kCARD_ResponseTypeR2 = 3U, /*!< Response type: R2 */ + kCARD_ResponseTypeR3 = 4U, /*!< Response type: R3 */ + kCARD_ResponseTypeR4 = 5U, /*!< Response type: R4 */ + kCARD_ResponseTypeR5 = 6U, /*!< Response type: R5 */ + kCARD_ResponseTypeR5b = 7U, /*!< Response type: R5b */ + kCARD_ResponseTypeR6 = 8U, /*!< Response type: R6 */ + kCARD_ResponseTypeR7 = 9U, /*!< Response type: R7 */ +}; + +/*! @brief define the interrupt mask flags */ +enum _sdif_interrupt_mask +{ + kSDIF_CardDetect = SDIF_INTMASK_CDET_MASK, /*!< mask for card detect */ + kSDIF_ResponseError = SDIF_INTMASK_RE_MASK, /*!< command response error */ + kSDIF_CommandDone = SDIF_INTMASK_CDONE_MASK, /*!< command transfer over*/ + kSDIF_DataTransferOver = SDIF_INTMASK_DTO_MASK, /*!< data transfer over flag*/ + kSDIF_WriteFIFORequest = SDIF_INTMASK_TXDR_MASK, /*!< write FIFO request */ + kSDIF_ReadFIFORequest = SDIF_INTMASK_RXDR_MASK, /*!< read FIFO request */ + kSDIF_ResponseCRCError = SDIF_INTMASK_RCRC_MASK, /*!< response CRC error */ + kSDIF_DataCRCError = SDIF_INTMASK_DCRC_MASK, /*!< data CRC error */ + kSDIF_ResponseTimeout = SDIF_INTMASK_RTO_MASK, /*!< response timeout */ + kSDIF_DataReadTimeout = SDIF_INTMASK_DRTO_MASK, /*!< read data timeout */ + kSDIF_DataStarvationByHostTimeout = SDIF_INTMASK_HTO_MASK, /*!< data starvation by host time out */ + kSDIF_FIFOError = SDIF_INTMASK_FRUN_MASK, /*!< indicate the FIFO under run or overrun error */ + kSDIF_HardwareLockError = SDIF_INTMASK_HLE_MASK, /*!< hardware lock write error */ + kSDIF_DataStartBitError = SDIF_INTMASK_SBE_MASK, /*!< start bit error */ + kSDIF_AutoCmdDone = SDIF_INTMASK_ACD_MASK, /*!< indicate the auto command done */ + kSDIF_DataEndBitError = SDIF_INTMASK_EBE_MASK, /*!< end bit error */ + kSDIF_SDIOInterrupt = SDIF_INTMASK_SDIO_INT_MASK_MASK, /*!< interrupt from the SDIO card */ + + kSDIF_CommandTransferStatus = kSDIF_ResponseError | kSDIF_CommandDone | kSDIF_ResponseCRCError | + kSDIF_ResponseTimeout | + kSDIF_HardwareLockError, /*!< command transfer status collection*/ + kSDIF_DataTransferStatus = kSDIF_DataTransferOver | kSDIF_WriteFIFORequest | kSDIF_ReadFIFORequest | + kSDIF_DataCRCError | kSDIF_DataReadTimeout | kSDIF_DataStarvationByHostTimeout | + kSDIF_FIFOError | kSDIF_DataStartBitError | kSDIF_DataEndBitError | + kSDIF_AutoCmdDone, /*!< data transfer status collection */ + kSDIF_DataTransferError = + kSDIF_DataCRCError | kSDIF_FIFOError | kSDIF_DataStartBitError | kSDIF_DataEndBitError | kSDIF_DataReadTimeout, + kSDIF_AllInterruptStatus = 0x1FFFFU, /*!< all interrupt mask */ + +}; + +/*! @brief define the internal DMA status flags */ +enum _sdif_dma_status +{ + kSDIF_DMATransFinishOneDescriptor = SDIF_IDSTS_TI_MASK, /*!< DMA transfer finished for one DMA descriptor */ + kSDIF_DMARecvFinishOneDescriptor = SDIF_IDSTS_RI_MASK, /*!< DMA receive finished for one DMA descriptor */ + kSDIF_DMAFatalBusError = SDIF_IDSTS_FBE_MASK, /*!< DMA fatal bus error */ + kSDIF_DMADescriptorUnavailable = SDIF_IDSTS_DU_MASK, /*!< DMA descriptor unavailable */ + kSDIF_DMACardErrorSummary = SDIF_IDSTS_CES_MASK, /*!< card error summary */ + kSDIF_NormalInterruptSummary = SDIF_IDSTS_NIS_MASK, /*!< normal interrupt summary */ + kSDIF_AbnormalInterruptSummary = SDIF_IDSTS_AIS_MASK, /*!< abnormal interrupt summary*/ + + kSDIF_DMAAllStatus = kSDIF_DMATransFinishOneDescriptor | kSDIF_DMARecvFinishOneDescriptor | kSDIF_DMAFatalBusError | + kSDIF_DMADescriptorUnavailable | kSDIF_DMACardErrorSummary | kSDIF_NormalInterruptSummary | + kSDIF_AbnormalInterruptSummary, + +}; + +/*! @brief define the internal DMA descriptor flag + * @deprecated Do not use this enum anymore, please use SDIF_DMA_DESCRIPTOR_XXX_FLAG instead. + */ +enum _sdif_dma_descriptor_flag +{ + kSDIF_DisableCompleteInterrupt = 0x2U, /*!< disable the complete interrupt flag for the ends + in the buffer pointed to by this descriptor*/ + kSDIF_DMADescriptorDataBufferEnd = 0x4U, /*!< indicate this descriptor contain the last data buffer of data */ + kSDIF_DMADescriptorDataBufferStart = 0x8U, /*!< indicate this descriptor contain the first data buffer + of data,if first buffer size is 0,next descriptor contain + the begin of the data*/ + + kSDIF_DMASecondAddrChained = 0x10U, /*!< indicate that the second addr in the descriptor is the + next descriptor addr not the data buffer */ + kSDIF_DMADescriptorEnd = 0x20U, /*!< indicate that the descriptor list reached its final descriptor*/ + kSDIF_DMADescriptorOwnByDMA = (int)0x80000000, /*!< indicate the descriptor is own by SD/MMC DMA */ +}; + +/*! @brief define the internal DMA mode */ +typedef enum _sdif_dma_mode +{ + kSDIF_ChainDMAMode = 0x01U, /* one descriptor with one buffer,but one descriptor point to another */ + kSDIF_DualDMAMode = 0x02U, /* dual mode is one descriptor with two buffer */ +} sdif_dma_mode_t; + +/*! @brief define the internal DMA descriptor */ +typedef struct _sdif_dma_descriptor +{ + uint32_t dmaDesAttribute; /*!< internal DMA attribute control and status */ + uint32_t dmaDataBufferSize; /*!< internal DMA transfer buffer size control */ + const uint32_t *dmaDataBufferAddr0; /*!< internal DMA buffer 0 addr ,the buffer size must be 32bit aligned */ + const uint32_t *dmaDataBufferAddr1; /*!< internal DMA buffer 1 addr ,the buffer size must be 32bit aligned */ + +} sdif_dma_descriptor_t; + +/*! @brief Defines the internal DMA configure structure. */ +typedef struct _sdif_dma_config +{ + bool enableFixBurstLen; /*!< fix burst len enable/disable flag,When set, the AHB will + use only SINGLE, INCR4, INCR8 or INCR16 during start of + normal burst transfers. When reset, the AHB will use SINGLE + and INCR burst transfer operations */ + + sdif_dma_mode_t mode; /*!< define the DMA mode */ + + uint8_t dmaDesSkipLen; /*!< define the descriptor skip length ,the length between two descriptor + this field is special for dual DMA mode */ + + uint32_t *dmaDesBufferStartAddr; /*!< internal DMA descriptor start address*/ + uint32_t dmaDesBufferLen; /*!< internal DMA buffer descriptor buffer len ,user need to pay attention to the + dma descriptor buffer length if it is bigger enough for your transfer */ + +} sdif_dma_config_t; + +/*! + * @brief Card data descriptor + */ +typedef struct _sdif_data +{ + bool streamTransfer; /*!< indicate this is a stream data transfer command */ + bool enableAutoCommand12; /*!< indicate if auto stop will send when data transfer over */ + bool enableIgnoreError; /*!< indicate if enable ignore error when transfer data */ + + size_t blockSize; /*!< Block size, take care when configure this parameter */ + uint32_t blockCount; /*!< Block count */ + uint32_t *rxData; /*!< data buffer to receive */ + const uint32_t *txData; /*!< data buffer to transfer */ +} sdif_data_t; + +/*! + * @brief Card command descriptor + * + * Define card command-related attribute. + */ +typedef struct _sdif_command +{ + uint32_t index; /*!< Command index */ + uint32_t argument; /*!< Command argument */ + uint32_t response[4U]; /*!< Response for this command */ + uint32_t type; /*!< define the command type */ + uint32_t responseType; /*!< Command response type */ + uint32_t flags; /*!< Cmd flags */ + uint32_t responseErrorFlags; /*!< response error flags, need to check the flags when + receive the cmd response */ +} sdif_command_t; + +/*! @brief Transfer state */ +typedef struct _sdif_transfer +{ + sdif_data_t *data; /*!< Data to transfer */ + sdif_command_t *command; /*!< Command to send */ +} sdif_transfer_t; + +/*! @brief Data structure to initialize the sdif */ +typedef struct _sdif_config +{ + uint8_t responseTimeout; /*!< command response timeout value */ + uint32_t cardDetDebounce_Clock; /*!< define the debounce clock count which will used in + card detect logic,typical value is 5-25ms */ + uint32_t endianMode; /*!< define endian mode ,this field is not used in this + module actually, keep for compatible with middleware*/ + uint32_t dataTimeout; /*!< data timeout value */ +} sdif_config_t; + +/*! + * @brief SDIF capability information. + * Defines a structure to get the capability information of SDIF. + */ +typedef struct _sdif_capability +{ + uint32_t sdVersion; /*!< support SD card/sdio version */ + uint32_t mmcVersion; /*!< support emmc card version */ + uint32_t maxBlockLength; /*!< Maximum block length united as byte */ + uint32_t maxBlockCount; /*!< Maximum byte count can be transfered */ + uint32_t flags; /*!< Capability flags to indicate the support information */ +} sdif_capability_t; + +/*! @brief sdif callback functions. */ +typedef struct _sdif_transfer_callback +{ + void (*cardInserted)(SDIF_Type *base, void *userData); /*!< card insert call back */ + void (*cardRemoved)(SDIF_Type *base, void *userData); /*!< card remove call back */ + void (*SDIOInterrupt)(SDIF_Type *base, void *userData); /*!< SDIO card interrupt occurs */ + void (*DMADesUnavailable)(SDIF_Type *base, void *userData); /*!< DMA descriptor unavailable */ + void (*CommandReload)(SDIF_Type *base, void *userData); /*!< command buffer full,need re-load */ + void (*TransferComplete)(SDIF_Type *base, + void *handle, + status_t status, + void *userData); /*!< Transfer complete callback */ +} sdif_transfer_callback_t; + +/*! + * @brief sdif handle + * + * Defines the structure to save the sdif state information and callback function. The detail interrupt status when + * send command or transfer data can be obtained from interruptFlags field by using mask defined in + * sdif_interrupt_flag_t; + * @note All the fields except interruptFlags and transferredWords must be allocated by the user. + */ +typedef struct _sdif_handle +{ + /* Transfer parameter */ + sdif_data_t *volatile data; /*!< Data to transfer */ + sdif_command_t *volatile command; /*!< Command to send */ + + /* Transfer status */ + volatile uint32_t transferredWords; /*!< Words transferred by polling way */ + + /* Callback functions */ + sdif_transfer_callback_t callback; /*!< Callback function */ + void *userData; /*!< Parameter for transfer complete callback */ +} sdif_handle_t; + +/*! @brief sdif transfer function. */ +typedef status_t (*sdif_transfer_function_t)(SDIF_Type *base, sdif_transfer_t *content); + +/*! @brief sdif host descriptor */ +typedef struct _sdif_host +{ + SDIF_Type *base; /*!< sdif peripheral base address */ + uint32_t sourceClock_Hz; /*!< sdif source clock frequency united in Hz */ + sdif_config_t config; /*!< sdif configuration */ + sdif_transfer_function_t transfer; /*!< sdif transfer function */ + sdif_capability_t capability; /*!< sdif capability information */ +} sdif_host_t; + +/************************************************************************************************* + * API + ************************************************************************************************/ +#if defined(__cplusplus) +extern "C" +{ +#endif + +/*! + * @brief SDIF module initialization function. + * + * Configures the SDIF according to the user configuration. + * @param base SDIF peripheral base address. + * @param config SDIF configuration information. + */ +void SDIF_Init(SDIF_Type *base, sdif_config_t *config); + +/*! + * @brief SDIF module deinit function. + * user should call this function follow with IP reset + * @param base SDIF peripheral base address. + */ +void SDIF_Deinit(SDIF_Type *base); + +/*! + * @brief SDIF send initialize 80 clocks for SD card after initial + * @param base SDIF peripheral base address. + * @param timeout value + */ +bool SDIF_SendCardActive(SDIF_Type *base, uint32_t timeout); + +#if defined(FSL_FEATURE_SDIF_ONE_INSTANCE_SUPPORT_TWO_CARD) && FSL_FEATURE_SDIF_ONE_INSTANCE_SUPPORT_TWO_CARD +/*! + * @brief SDIF module enable/disable card0 clock. + * @param base SDIF peripheral base address. + * @param enable/disable flag + */ +static inline void SDIF_EnableCardClock(SDIF_Type *base, bool enable) +{ + if (enable) + { + base->CLKENA |= SDIF_CLKENA_CCLK0_ENABLE_MASK; + } + else + { + base->CLKENA &= SDIF_CLKENA_CCLK0_ENABLE_MASK; + } +} + +/*! + * @brief SDIF module enable/disable card1 clock. + * @param base SDIF peripheral base address. + * @param enable/disable flag + */ +static inline void SDIF_EnableCard1Clock(SDIF_Type *base, bool enable) +{ + if (enable) + { + base->CLKENA |= SDIF_CLKENA_CCLK1_ENABLE_MASK; + } + else + { + base->CLKENA &= ~SDIF_CLKENA_CCLK1_ENABLE_MASK; + } +} + +/*! + * @brief SDIF module enable/disable module disable the card clock + * to enter low power mode when card is idle,for SDIF cards, if + * interrupts must be detected, clock should not be stopped + * @param base SDIF peripheral base address. + * @param enable/disable flag + */ +static inline void SDIF_EnableLowPowerMode(SDIF_Type *base, bool enable) +{ + if (enable) + { + base->CLKENA |= SDIF_CLKENA_CCLK0_LOW_POWER_MASK; + } + else + { + base->CLKENA &= ~SDIF_CLKENA_CCLK0_LOW_POWER_MASK; + } +} + +/*! + * @brief SDIF module enable/disable module disable the card clock + * to enter low power mode when card is idle,for SDIF cards, if + * interrupts must be detected, clock should not be stopped + * @param base SDIF peripheral base address. + * @param enable/disable flag + */ +static inline void SDIF_EnableCard1LowPowerMode(SDIF_Type *base, bool enable) +{ + if (enable) + { + base->CLKENA |= SDIF_CLKENA_CCLK1_LOW_POWER_MASK; + } + else + { + base->CLKENA &= ~SDIF_CLKENA_CCLK1_LOW_POWER_MASK; + } +} + +/*! + * @brief enable/disable the card0 power. + * once turn power on, software should wait for regulator/switch + * ramp-up time before trying to initialize card. + * @param base SDIF peripheral base address. + * @param enable/disable flag. + */ +static inline void SDIF_EnableCardPower(SDIF_Type *base, bool enable) +{ + if (enable) + { + base->PWREN |= SDIF_PWREN_POWER_ENABLE0_MASK; + } + else + { + base->PWREN &= ~SDIF_PWREN_POWER_ENABLE0_MASK; + } +} + +/*! + * @brief enable/disable the card1 power. + * once turn power on, software should wait for regulator/switch + * ramp-up time before trying to initialize card. + * @param base SDIF peripheral base address. + * @param enable/disable flag. + */ +static inline void SDIF_EnableCard1Power(SDIF_Type *base, bool enable) +{ + if (enable) + { + base->PWREN |= SDIF_PWREN_POWER_ENABLE1_MASK; + } + else + { + base->PWREN &= ~SDIF_PWREN_POWER_ENABLE1_MASK; + } +} + +/*! + * @brief set card0 data bus width + * @param base SDIF peripheral base address. + * @param data bus width type + */ +void SDIF_SetCardBusWidth(SDIF_Type *base, sdif_bus_width_t type); + +/*! + * @brief set card1 data bus width + * @param base SDIF peripheral base address. + * @param data bus width type + */ +void SDIF_SetCard1BusWidth(SDIF_Type *base, sdif_bus_width_t type); + +/*! + * @brief SDIF module detect card0 insert status function. + * @param base SDIF peripheral base address. + * @param data3 indicate use data3 as card insert detect pin + * @retval 1 card is inserted + * 0 card is removed + */ +static inline uint32_t SDIF_DetectCardInsert(SDIF_Type *base, bool data3) +{ + if (data3) + { + return (base->STATUS & SDIF_STATUS_DATA_3_STATUS_MASK) == SDIF_STATUS_DATA_3_STATUS_MASK ? 1U : 0U; + } + else + { + return (base->CDETECT & SDIF_CDETECT_CARD0_DETECT_MASK) == 0U ? 1U : 0U; + } +} + +/*! + * @brief SDIF module detect card1 insert status function. + * @param base SDIF peripheral base address. + * @param data3 indicate use data3 as card insert detect pin + * @retval 1 card is inserted + * 0 card is removed + */ +static inline uint32_t SDIF_DetectCard1Insert(SDIF_Type *base, bool data3) +{ + if (data3) + { + return (base->STATUS & SDIF_STATUS_DATA_3_STATUS_MASK) == SDIF_STATUS_DATA_3_STATUS_MASK ? 1U : 0U; + } + else + { + return (base->CDETECT & SDIF_CDETECT_CARD1_DETECT_MASK) == 0U ? 1U : 0U; + } +} +#else +/*! + * @brief SDIF module enable/disable card clock. + * @param base SDIF peripheral base address. + * @param enable/disable flag + */ +static inline void SDIF_EnableCardClock(SDIF_Type *base, bool enable) +{ + if (enable) + { + base->CLKENA |= SDIF_CLKENA_CCLK_ENABLE_MASK; + } + else + { + base->CLKENA &= ~SDIF_CLKENA_CCLK_ENABLE_MASK; + } +} + +/*! + * @brief SDIF module enable/disable module disable the card clock + * to enter low power mode when card is idle,for SDIF cards, if + * interrupts must be detected, clock should not be stopped + * @param base SDIF peripheral base address. + * @param enable/disable flag + */ +static inline void SDIF_EnableLowPowerMode(SDIF_Type *base, bool enable) +{ + if (enable) + { + base->CLKENA |= SDIF_CLKENA_CCLK_LOW_POWER_MASK; + } + else + { + base->CLKENA &= ~SDIF_CLKENA_CCLK_LOW_POWER_MASK; + } +} + +/*! + * @brief enable/disable the card power. + * once turn power on, software should wait for regulator/switch + * ramp-up time before trying to initialize card. + * @param base SDIF peripheral base address. + * @param enable/disable flag. + */ +static inline void SDIF_EnableCardPower(SDIF_Type *base, bool enable) +{ + if (enable) + { + base->PWREN |= SDIF_PWREN_POWER_ENABLE_MASK; + } + else + { + base->PWREN &= ~SDIF_PWREN_POWER_ENABLE_MASK; + } +} + +/*! + * @brief set card data bus width + * @param base SDIF peripheral base address. + * @param data bus width type + */ +void SDIF_SetCardBusWidth(SDIF_Type *base, sdif_bus_width_t type); + +/*! + * @brief SDIF module detect card insert status function. + * @param base SDIF peripheral base address. + * @param data3 indicate use data3 as card insert detect pin + * @retval 1 card is inserted + * 0 card is removed + */ +static inline uint32_t SDIF_DetectCardInsert(SDIF_Type *base, bool data3) +{ + if (data3) + { + return (base->STATUS & SDIF_STATUS_DATA_3_STATUS_MASK) == SDIF_STATUS_DATA_3_STATUS_MASK ? 1U : 0U; + } + else + { + return (base->CDETECT & SDIF_CDETECT_CARD_DETECT_MASK) == 0U ? 1U : 0U; + } +} +#endif + +/*! + * @brief Sets the card bus clock frequency. + * + * @param base SDIF peripheral base address. + * @param srcClock_Hz SDIF source clock frequency united in Hz. + * @param target_HZ card bus clock frequency united in Hz. + * @return The nearest frequency of busClock_Hz configured to SD bus. + */ +uint32_t SDIF_SetCardClock(SDIF_Type *base, uint32_t srcClock_Hz, uint32_t target_HZ); + +/*! + * @brief reset the different block of the interface. + * @param base SDIF peripheral base address. + * @param mask indicate which block to reset. + * @param timeout value,set to wait the bit self clear + * @return reset result. + */ +bool SDIF_Reset(SDIF_Type *base, uint32_t mask, uint32_t timeout); + +/*! + * @brief get the card write protect status + * @param base SDIF peripheral base address. + */ +static inline uint32_t SDIF_GetCardWriteProtect(SDIF_Type *base) +{ + return base->WRTPRT & SDIF_WRTPRT_WRITE_PROTECT_MASK; +} + +/*! + * @brief toggle state on hardware reset PIN + * This is used which card has a reset PIN typically. + * @param base SDIF peripheral base address. + */ +static inline void SDIF_AssertHardwareReset(SDIF_Type *base) +{ + base->RST_N &= ~SDIF_RST_N_CARD_RESET_MASK; +} + +/*! + * @brief send command to the card + * + * This api include polling the status of the bit START_COMMAND, if 0 used as timeout value, then this function + * will return directly without polling the START_CMD status. + * @param base SDIF peripheral base address. + * @param command configuration collection + * @param timeout not used in this function + * @return command excute status + */ +status_t SDIF_SendCommand(SDIF_Type *base, sdif_command_t *cmd, uint32_t timeout); + +/*! + * @brief SDIF enable/disable global interrupt + * @param base SDIF peripheral base address. + * @param enable/disable flag + */ +static inline void SDIF_EnableGlobalInterrupt(SDIF_Type *base, bool enable) +{ + if (enable) + { + base->CTRL |= SDIF_CTRL_INT_ENABLE_MASK; + } + else + { + base->CTRL &= ~SDIF_CTRL_INT_ENABLE_MASK; + } +} + +/*! + * @brief SDIF enable interrupt + * @param base SDIF peripheral base address. + * @param interrupt mask + */ +static inline void SDIF_EnableInterrupt(SDIF_Type *base, uint32_t mask) +{ + base->INTMASK |= mask; +} + +/*! + * @brief SDIF disable interrupt + * @param base SDIF peripheral base address. + * @param interrupt mask + */ +static inline void SDIF_DisableInterrupt(SDIF_Type *base, uint32_t mask) +{ + base->INTMASK &= ~mask; +} + +/*! + * @brief SDIF get interrupt status + * @param base SDIF peripheral base address. + */ +static inline uint32_t SDIF_GetInterruptStatus(SDIF_Type *base) +{ + return base->MINTSTS; +} + +/*! + * @brief SDIF get enabled interrupt status + * @param base SDIF peripheral base address. + */ +static inline uint32_t SDIF_GetEnabledInterruptStatus(SDIF_Type *base) +{ + return (base->MINTSTS) & (base->INTMASK); +} + +/*! + * @brief SDIF clear interrupt status + * @param base SDIF peripheral base address. + * @param status mask to clear + */ +static inline void SDIF_ClearInterruptStatus(SDIF_Type *base, uint32_t mask) +{ + base->RINTSTS &= mask; +} + +/*! + * @brief Creates the SDIF handle. + * register call back function for interrupt and enable the interrupt + * @param base SDIF peripheral base address. + * @param handle SDIF handle pointer. + * @param callback Structure pointer to contain all callback functions. + * @param userData Callback function parameter. + */ +void SDIF_TransferCreateHandle(SDIF_Type *base, + sdif_handle_t *handle, + sdif_transfer_callback_t *callback, + void *userData); + +/*! + * @brief SDIF enable DMA interrupt + * @param base SDIF peripheral base address. + * @param interrupt mask to set + */ +static inline void SDIF_EnableDmaInterrupt(SDIF_Type *base, uint32_t mask) +{ + base->IDINTEN |= mask; +} + +/*! + * @brief SDIF disable DMA interrupt + * @param base SDIF peripheral base address. + * @param interrupt mask to clear + */ +static inline void SDIF_DisableDmaInterrupt(SDIF_Type *base, uint32_t mask) +{ + base->IDINTEN &= ~mask; +} + +/*! + * @brief SDIF get internal DMA status + * @param base SDIF peripheral base address. + * @return the internal DMA status register + */ +static inline uint32_t SDIF_GetInternalDMAStatus(SDIF_Type *base) +{ + return base->IDSTS; +} + +/*! + * @brief SDIF get enabled internal DMA interrupt status + * @param base SDIF peripheral base address. + * @return the internal DMA status register + */ +static inline uint32_t SDIF_GetEnabledDMAInterruptStatus(SDIF_Type *base) +{ + return (base->IDSTS) & (base->IDINTEN); +} +/*! + * @brief SDIF clear internal DMA status + * @param base SDIF peripheral base address. + * @param status mask to clear + */ +static inline void SDIF_ClearInternalDMAStatus(SDIF_Type *base, uint32_t mask) +{ + base->IDSTS &= mask; +} + +/*! + * @brief SDIF internal DMA config function + * @param base SDIF peripheral base address. + * @param internal DMA configuration collection + * @param data buffer pointer + * @param data buffer size + */ +status_t SDIF_InternalDMAConfig(SDIF_Type *base, + sdif_dma_config_t *config, + const uint32_t *data, + uint32_t dataSize); + +/*! + * @brief SDIF internal DMA enable + * @param base SDIF peripheral base address. + * @param enable internal DMA enable or disable flag. + */ +static inline void SDIF_EnableInternalDMA(SDIF_Type *base, bool enable) +{ + if (enable) + { + /* use internal DMA interface */ + base->CTRL |= SDIF_CTRL_USE_INTERNAL_DMAC_MASK; + /* enable the internal SD/MMC DMA */ + base->BMOD |= SDIF_BMOD_DE_MASK; + } + else + { + /* use internal DMA interface */ + base->CTRL &= ~SDIF_CTRL_USE_INTERNAL_DMAC_MASK; + /* enable the internal SD/MMC DMA */ + base->BMOD &= ~SDIF_BMOD_DE_MASK; + } +} + +/*! + * @brief SDIF send read wait to SDIF card function + * @param base SDIF peripheral base address. + */ +static inline void SDIF_SendReadWait(SDIF_Type *base) +{ + base->CTRL |= SDIF_CTRL_READ_WAIT_MASK; +} + +/*! + * @brief SDIF abort the read data when SDIF card is in suspend state + * Once assert this bit,data state machine will be reset which is waiting for the + * next blocking data,used in SDIO card suspend sequence,should call after suspend + * cmd send + * @param base SDIF peripheral base address. + * @param timeout value to wait this bit self clear which indicate the data machine + * reset to idle + */ +bool SDIF_AbortReadData(SDIF_Type *base, uint32_t timeout); + +/*! + * @brief SDIF enable/disable CE-ATA card interrupt + * this bit should set together with the card register + * @param base SDIF peripheral base address. + * @param enable/disable flag + */ +static inline void SDIF_EnableCEATAInterrupt(SDIF_Type *base, bool enable) +{ + if (enable) + { + base->CTRL |= SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_MASK; + } + else + { + base->CTRL &= ~SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_MASK; + } +} + +/*! + * @brief SDIF transfer function data/cmd in a non-blocking way + * this API should be use in interrupt mode, when use this API user + * must call SDIF_TransferCreateHandle first, all status check through + * interrupt + * @param base SDIF peripheral base address. + * @param sdif handle + * @param DMA config structure + * This parameter can be config as: + * 1. NULL + In this condition, polling transfer mode is selected + 2. avaliable DMA config + In this condition, DMA transfer mode is selected + * @param sdif transfer configuration collection + */ +status_t SDIF_TransferNonBlocking(SDIF_Type *base, + sdif_handle_t *handle, + sdif_dma_config_t *dmaConfig, + sdif_transfer_t *transfer); + +/*! + * @brief SDIF transfer function data/cmd in a blocking way + * @param base SDIF peripheral base address. + * @param DMA config structure + * 1. NULL + * In this condition, polling transfer mode is selected + * 2. avaliable DMA config + * In this condition, DMA transfer mode is selected + * @param sdif transfer configuration collection + */ +status_t SDIF_TransferBlocking(SDIF_Type *base, sdif_dma_config_t *dmaConfig, sdif_transfer_t *transfer); + +/*! + * @brief SDIF release the DMA descriptor to DMA engine + * this function should be called when DMA descriptor unavailable status occurs + * @param base SDIF peripheral base address. + * @param sdif DMA config pointer + */ +status_t SDIF_ReleaseDMADescriptor(SDIF_Type *base, sdif_dma_config_t *dmaConfig); + +/*! + * @brief SDIF return the controller capability + * @param base SDIF peripheral base address. + * @param sdif capability pointer + */ +void SDIF_GetCapability(SDIF_Type *base, sdif_capability_t *capability); + +/*! + * @brief SDIF return the controller status + * @param base SDIF peripheral base address. + */ +static inline uint32_t SDIF_GetControllerStatus(SDIF_Type *base) +{ + return base->STATUS; +} + +/*! + * @brief SDIF send command complete signal disable to CE-ATA card + * @param base SDIF peripheral base address. + * @param send auto stop flag + */ +static inline void SDIF_SendCCSD(SDIF_Type *base, bool withAutoStop) +{ + if (withAutoStop) + { + base->CTRL |= SDIF_CTRL_SEND_CCSD_MASK | SDIF_CTRL_SEND_AUTO_STOP_CCSD_MASK; + } + else + { + base->CTRL |= SDIF_CTRL_SEND_CCSD_MASK; + } +} + +/*! + * @brief SDIF config the clock delay + * This function is used to config the cclk_in delay to + * sample and driver the data ,should meet the min setup + * time and hold time, and user need to config this parameter + * according to your board setting + * @param target freq work mode + * @param divider not used in this function anymore, use DELAY value instead of phase directly. + */ +void SDIF_ConfigClockDelay(uint32_t target_HZ, uint32_t divider); + +/* @} */ + +#if defined(__cplusplus) +} +#endif +/*! @} */ + +#endif /* _FSL_sdif_H_*/ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_spi.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_spi.c new file mode 100644 index 000000000..30d433097 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_spi.c @@ -0,0 +1,1040 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_spi.h" +#include "fsl_flexcomm.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexcomm_spi" +#endif + +/* Note: FIFOCFG[SIZE] has always value 1 = 8 items depth */ + +#if defined(FSL_FEATURE_SPI_FIFOSIZE_CFG) && (FSL_FEATURE_SPI_FIFOSIZE_CFG) +#define SPI_FIFO_DEPTH(base) 4 +#else +#define SPI_FIFO_DEPTH(base) ((((base)->FIFOCFG & SPI_FIFOCFG_SIZE_MASK) >> SPI_FIFOCFG_SIZE_SHIFT) << 3) +#endif /*FSL_FEATURE_SPI_FIFOSIZE_CFG*/ + +/* Convert transfer count to transfer bytes. dataWidth is a + * range <0,15>. Range <8,15> represents 2B transfer */ +#define SPI_COUNT_TO_BYTES(dataWidth, count) ((count) << ((dataWidth) >> 3U)) +#define SPI_BYTES_TO_COUNT(dataWidth, bytes) ((bytes) >> ((dataWidth) >> 3U)) +#define SPI_SSELPOL_MASK ((SPI_CFG_SPOL0_MASK) | (SPI_CFG_SPOL1_MASK) | (SPI_CFG_SPOL2_MASK) | (SPI_CFG_SPOL3_MASK)) + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief internal SPI config array */ +static spi_config_t g_configs[FSL_FEATURE_SOC_SPI_COUNT] = {(spi_data_width_t)0}; + +/*! @brief Array to map SPI instance number to base address. */ +static const uint32_t s_spiBaseAddrs[FSL_FEATURE_SOC_SPI_COUNT] = SPI_BASE_ADDRS; + +/*! @brief IRQ name array */ +static const IRQn_Type s_spiIRQ[] = SPI_IRQS; + +/* @brief Dummy data for each instance. This data is used when user's tx buffer is NULL*/ +volatile uint8_t s_dummyData[FSL_FEATURE_SOC_SPI_COUNT] = {0}; +/******************************************************************************* + * Code + ******************************************************************************/ + +/* Get the index corresponding to the FLEXCOMM */ +/*! brief Returns instance number for SPI peripheral base address. */ +uint32_t SPI_GetInstance(SPI_Type *base) +{ + int i; + + for (i = 0; i < FSL_FEATURE_SOC_SPI_COUNT; i++) + { + if ((uint32_t)base == s_spiBaseAddrs[i]) + { + return i; + } + } + + assert(false); + return 0; +} + +/*! + * brief Set up the dummy data. + * + * param base SPI peripheral address. + * param dummyData Data to be transferred when tx buffer is NULL. + */ +void SPI_SetDummyData(SPI_Type *base, uint8_t dummyData) +{ + uint32_t instance = SPI_GetInstance(base); + s_dummyData[instance] = dummyData; +} + +/*! + * brief Returns the configurations. + * + * param base SPI peripheral address. + * return return configurations which contain datawidth and SSEL numbers. + * return data type is a pointer of spi_config_t. + */ +void *SPI_GetConfig(SPI_Type *base) +{ + int32_t instance; + instance = SPI_GetInstance(base); + if (instance < 0) + { + return NULL; + } + return &g_configs[instance]; +} + +/*! + * brief Sets the SPI master configuration structure to default values. + * + * The purpose of this API is to get the configuration structure initialized for use in SPI_MasterInit(). + * User may use the initialized structure unchanged in SPI_MasterInit(), or modify + * some fields of the structure before calling SPI_MasterInit(). After calling this API, + * the master is ready to transfer. + * Example: + code + spi_master_config_t config; + SPI_MasterGetDefaultConfig(&config); + endcode + * + * param config pointer to master config structure + */ +void SPI_MasterGetDefaultConfig(spi_master_config_t *config) +{ + assert(NULL != config); + + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + + config->enableLoopback = false; + config->enableMaster = true; + config->polarity = kSPI_ClockPolarityActiveHigh; + config->phase = kSPI_ClockPhaseFirstEdge; + config->direction = kSPI_MsbFirst; + config->baudRate_Bps = 500000U; + config->dataWidth = kSPI_Data8Bits; + config->sselNum = kSPI_Ssel0; + config->txWatermark = kSPI_TxFifo0; + config->rxWatermark = kSPI_RxFifo1; + config->sselPol = kSPI_SpolActiveAllLow; + config->delayConfig.preDelay = 0U; + config->delayConfig.postDelay = 0U; + config->delayConfig.frameDelay = 0U; + config->delayConfig.transferDelay = 0U; +} + +/*! + * brief Initializes the SPI with master configuration. + * + * The configuration structure can be filled by user from scratch, or be set with default + * values by SPI_MasterGetDefaultConfig(). After calling this API, the slave is ready to transfer. + * Example + code + spi_master_config_t config = { + .baudRate_Bps = 400000, + ... + }; + SPI_MasterInit(SPI0, &config); + endcode + * + * param base SPI base pointer + * param config pointer to master configuration structure + * param srcClock_Hz Source clock frequency. + */ +status_t SPI_MasterInit(SPI_Type *base, const spi_master_config_t *config, uint32_t srcClock_Hz) +{ + int32_t result = 0, instance = 0; + uint32_t tmp; + + /* assert params */ + assert(!((NULL == base) || (NULL == config) || (0 == srcClock_Hz))); + if ((NULL == base) || (NULL == config) || (0 == srcClock_Hz)) + { + return kStatus_InvalidArgument; + } + + /* initialize flexcomm to SPI mode */ + result = FLEXCOMM_Init(base, FLEXCOMM_PERIPH_SPI); + assert(kStatus_Success == result); + if (kStatus_Success != result) + { + return result; + } + + /* set divider */ + result = SPI_MasterSetBaud(base, config->baudRate_Bps, srcClock_Hz); + if (kStatus_Success != result) + { + return result; + } + /* get instance number */ + instance = SPI_GetInstance(base); + assert(instance >= 0); + + /* configure SPI mode */ + tmp = base->CFG; + tmp &= ~(SPI_CFG_MASTER_MASK | SPI_CFG_LSBF_MASK | SPI_CFG_CPHA_MASK | SPI_CFG_CPOL_MASK | SPI_CFG_LOOP_MASK | + SPI_CFG_ENABLE_MASK | SPI_SSELPOL_MASK); + /* phase */ + tmp |= SPI_CFG_CPHA(config->phase); + /* polarity */ + tmp |= SPI_CFG_CPOL(config->polarity); + /* direction */ + tmp |= SPI_CFG_LSBF(config->direction); + /* master mode */ + tmp |= SPI_CFG_MASTER(1); + /* loopback */ + tmp |= SPI_CFG_LOOP(config->enableLoopback); + /* configure active level for all CS */ + tmp |= ((uint32_t)config->sselPol & (SPI_SSELPOL_MASK)); + base->CFG = tmp; + + /* store configuration */ + g_configs[instance].dataWidth = config->dataWidth; + g_configs[instance].sselNum = config->sselNum; + /* enable FIFOs */ + base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK; + base->FIFOCFG |= SPI_FIFOCFG_ENABLETX_MASK | SPI_FIFOCFG_ENABLERX_MASK; + /* trigger level - empty txFIFO, one item in rxFIFO */ + tmp = base->FIFOTRIG & (~(SPI_FIFOTRIG_RXLVL_MASK | SPI_FIFOTRIG_TXLVL_MASK)); + tmp |= SPI_FIFOTRIG_TXLVL(config->txWatermark) | SPI_FIFOTRIG_RXLVL(config->rxWatermark); + /* enable generating interrupts for FIFOTRIG levels */ + tmp |= SPI_FIFOTRIG_TXLVLENA_MASK | SPI_FIFOTRIG_RXLVLENA_MASK; + /* set FIFOTRIG */ + base->FIFOTRIG = tmp; + + /* Set the delay configuration. */ + SPI_SetTransferDelay(base, &config->delayConfig); + /* Set the dummy data. */ + SPI_SetDummyData(base, (uint8_t)SPI_DUMMYDATA); + + SPI_Enable(base, config->enableMaster); + return kStatus_Success; +} + +/*! + * brief Sets the SPI slave configuration structure to default values. + * + * The purpose of this API is to get the configuration structure initialized for use in SPI_SlaveInit(). + * Modify some fields of the structure before calling SPI_SlaveInit(). + * Example: + code + spi_slave_config_t config; + SPI_SlaveGetDefaultConfig(&config); + endcode + * + * param config pointer to slave configuration structure + */ +void SPI_SlaveGetDefaultConfig(spi_slave_config_t *config) +{ + assert(NULL != config); + + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + + config->enableSlave = true; + config->polarity = kSPI_ClockPolarityActiveHigh; + config->phase = kSPI_ClockPhaseFirstEdge; + config->direction = kSPI_MsbFirst; + config->dataWidth = kSPI_Data8Bits; + config->txWatermark = kSPI_TxFifo0; + config->rxWatermark = kSPI_RxFifo1; + config->sselPol = kSPI_SpolActiveAllLow; +} + +/*! + * brief Initializes the SPI with slave configuration. + * + * The configuration structure can be filled by user from scratch or be set with + * default values by SPI_SlaveGetDefaultConfig(). + * After calling this API, the slave is ready to transfer. + * Example + code + spi_slave_config_t config = { + .polarity = flexSPIClockPolarity_ActiveHigh; + .phase = flexSPIClockPhase_FirstEdge; + .direction = flexSPIMsbFirst; + ... + }; + SPI_SlaveInit(SPI0, &config); + endcode + * + * param base SPI base pointer + * param config pointer to slave configuration structure + */ +status_t SPI_SlaveInit(SPI_Type *base, const spi_slave_config_t *config) +{ + int32_t result = 0, instance; + uint32_t tmp; + + /* assert params */ + assert(!((NULL == base) || (NULL == config))); + if ((NULL == base) || (NULL == config)) + { + return kStatus_InvalidArgument; + } + /* configure flexcomm to SPI, enable clock gate */ + result = FLEXCOMM_Init(base, FLEXCOMM_PERIPH_SPI); + assert(kStatus_Success == result); + if (kStatus_Success != result) + { + return result; + } + + instance = SPI_GetInstance(base); + + /* configure SPI mode */ + tmp = base->CFG; + tmp &= ~(SPI_CFG_MASTER_MASK | SPI_CFG_LSBF_MASK | SPI_CFG_CPHA_MASK | SPI_CFG_CPOL_MASK | SPI_CFG_ENABLE_MASK | + SPI_SSELPOL_MASK); + /* phase */ + tmp |= SPI_CFG_CPHA(config->phase); + /* polarity */ + tmp |= SPI_CFG_CPOL(config->polarity); + /* direction */ + tmp |= SPI_CFG_LSBF(config->direction); + /* configure active level for all CS */ + tmp |= ((uint32_t)config->sselPol & (SPI_SSELPOL_MASK)); + base->CFG = tmp; + + /* store configuration */ + g_configs[instance].dataWidth = config->dataWidth; + /* empty and enable FIFOs */ + base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK; + base->FIFOCFG |= SPI_FIFOCFG_ENABLETX_MASK | SPI_FIFOCFG_ENABLERX_MASK; + /* trigger level - empty txFIFO, one item in rxFIFO */ + tmp = base->FIFOTRIG & (~(SPI_FIFOTRIG_RXLVL_MASK | SPI_FIFOTRIG_TXLVL_MASK)); + tmp |= SPI_FIFOTRIG_TXLVL(config->txWatermark) | SPI_FIFOTRIG_RXLVL(config->rxWatermark); + /* enable generating interrupts for FIFOTRIG levels */ + tmp |= SPI_FIFOTRIG_TXLVLENA_MASK | SPI_FIFOTRIG_RXLVLENA_MASK; + /* set FIFOTRIG */ + base->FIFOTRIG = tmp; + + SPI_SetDummyData(base, (uint8_t)SPI_DUMMYDATA); + + SPI_Enable(base, config->enableSlave); + return kStatus_Success; +} + +/*! + * brief De-initializes the SPI. + * + * Calling this API resets the SPI module, gates the SPI clock. + * The SPI module can't work unless calling the SPI_MasterInit/SPI_SlaveInit to initialize module. + * + * param base SPI base pointer + */ +void SPI_Deinit(SPI_Type *base) +{ + /* Assert arguments */ + assert(NULL != base); + /* Disable interrupts, disable dma requests, disable peripheral */ + base->FIFOINTENCLR = SPI_FIFOINTENCLR_TXERR_MASK | SPI_FIFOINTENCLR_RXERR_MASK | SPI_FIFOINTENCLR_TXLVL_MASK | + SPI_FIFOINTENCLR_RXLVL_MASK; + base->FIFOCFG &= ~(SPI_FIFOCFG_DMATX_MASK | SPI_FIFOCFG_DMARX_MASK); + base->CFG &= ~(SPI_CFG_ENABLE_MASK); +} + +/*! + * brief Enables the DMA request from SPI txFIFO. + * + * param base SPI base pointer + * param enable True means enable DMA, false means disable DMA + */ +void SPI_EnableTxDMA(SPI_Type *base, bool enable) +{ + if (enable) + { + base->FIFOCFG |= SPI_FIFOCFG_DMATX_MASK; + } + else + { + base->FIFOCFG &= ~SPI_FIFOCFG_DMATX_MASK; + } +} + +/*! + * brief Enables the DMA request from SPI rxFIFO. + * + * param base SPI base pointer + * param enable True means enable DMA, false means disable DMA + */ +void SPI_EnableRxDMA(SPI_Type *base, bool enable) +{ + if (enable) + { + base->FIFOCFG |= SPI_FIFOCFG_DMARX_MASK; + } + else + { + base->FIFOCFG &= ~SPI_FIFOCFG_DMARX_MASK; + } +} + +/*! + * brief Sets the baud rate for SPI transfer. This is only used in master. + * + * param base SPI base pointer + * param baudrate_Bps baud rate needed in Hz. + * param srcClock_Hz SPI source clock frequency in Hz. + */ +status_t SPI_MasterSetBaud(SPI_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz) +{ + uint32_t tmp; + + /* assert params */ + assert(!((NULL == base) || (0 == baudrate_Bps) || (0 == srcClock_Hz))); + if ((NULL == base) || (0 == baudrate_Bps) || (0 == srcClock_Hz)) + { + return kStatus_InvalidArgument; + } + + /* calculate baudrate */ + tmp = (srcClock_Hz / baudrate_Bps) - 1; + if (tmp > 0xFFFF) + { + return kStatus_SPI_BaudrateNotSupport; + } + base->DIV &= ~SPI_DIV_DIVVAL_MASK; + base->DIV |= SPI_DIV_DIVVAL(tmp); + return kStatus_Success; +} + +/*! + * brief Writes a data into the SPI data register. + * + * param base SPI base pointer + * param data needs to be write. + * param configFlags transfer configuration options ref spi_xfer_option_t + */ +void SPI_WriteData(SPI_Type *base, uint16_t data, uint32_t configFlags) +{ + uint32_t control = 0; + int32_t instance; + + /* check params */ + assert(NULL != base); + /* get and check instance */ + instance = SPI_GetInstance(base); + assert(!(instance < 0)); + if (instance < 0) + { + return; + } + + /* set data width */ + control |= SPI_FIFOWR_LEN(g_configs[instance].dataWidth); + /* set sssel */ + control |= (SPI_DEASSERT_ALL & (~SPI_DEASSERTNUM_SSEL(g_configs[instance].sselNum))); + /* mask configFlags */ + control |= (configFlags & SPI_FIFOWR_FLAGS_MASK); + /* control should not affect lower 16 bits */ + assert(!(control & 0xFFFF)); + base->FIFOWR = data | control; +} + +/*! + * brief Initializes the SPI master handle. + * + * This function initializes the SPI master handle which can be used for other SPI master transactional APIs. Usually, + * for a specified SPI instance, call this API once to get the initialized handle. + * + * param base SPI peripheral base address. + * param handle SPI handle pointer. + * param callback Callback function. + * param userData User data. + */ +status_t SPI_MasterTransferCreateHandle(SPI_Type *base, + spi_master_handle_t *handle, + spi_master_callback_t callback, + void *userData) +{ + int32_t instance = 0; + + /* check 'base' */ + assert(!(NULL == base)); + if (NULL == base) + { + return kStatus_InvalidArgument; + } + /* check 'handle' */ + assert(!(NULL == handle)); + if (NULL == handle) + { + return kStatus_InvalidArgument; + } + /* get flexcomm instance by 'base' param */ + instance = SPI_GetInstance(base); + assert(!(instance < 0)); + if (instance < 0) + { + return kStatus_InvalidArgument; + } + + memset(handle, 0, sizeof(*handle)); + /* Initialize the handle */ + if (base->CFG & SPI_CFG_MASTER_MASK) + { + FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)SPI_MasterTransferHandleIRQ, handle); + } + else + { + FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)SPI_SlaveTransferHandleIRQ, handle); + } + + handle->dataWidth = g_configs[instance].dataWidth; + /* in slave mode, the sselNum is not important */ + handle->sselNum = g_configs[instance].sselNum; + handle->txWatermark = (spi_txfifo_watermark_t)SPI_FIFOTRIG_TXLVL_GET(base); + handle->rxWatermark = (spi_rxfifo_watermark_t)SPI_FIFOTRIG_RXLVL_GET(base); + handle->callback = callback; + handle->userData = userData; + + /* Enable SPI NVIC */ + EnableIRQ(s_spiIRQ[instance]); + + return kStatus_Success; +} + +/*! + * brief Transfers a block of data using a polling method. + * + * param base SPI base pointer + * param xfer pointer to spi_xfer_config_t structure + * retval kStatus_Success Successfully start a transfer. + * retval kStatus_InvalidArgument Input argument is invalid. + */ +status_t SPI_MasterTransferBlocking(SPI_Type *base, spi_transfer_t *xfer) +{ + int32_t instance; + uint32_t tx_ctrl = 0, last_ctrl = 0; + uint32_t tmp32, rxRemainingBytes, txRemainingBytes, dataWidth; + uint32_t toReceiveCount = 0; + uint8_t *txData, *rxData; + uint32_t fifoDepth; + + /* check params */ + assert(!((NULL == base) || (NULL == xfer) || ((NULL == xfer->txData) && (NULL == xfer->rxData)))); + if ((NULL == base) || (NULL == xfer) || ((NULL == xfer->txData) && (NULL == xfer->rxData))) + { + return kStatus_InvalidArgument; + } + + fifoDepth = SPI_FIFO_DEPTH(base); + txData = xfer->txData; + rxData = xfer->rxData; + txRemainingBytes = txData ? xfer->dataSize : 0; + rxRemainingBytes = rxData ? xfer->dataSize : 0; + + instance = SPI_GetInstance(base); + assert(instance >= 0); + dataWidth = g_configs[instance].dataWidth; + + /* dataSize (in bytes) is not aligned to 16bit (2B) transfer */ + assert(!((dataWidth > kSPI_Data8Bits) && (xfer->dataSize & 0x1))); + if ((dataWidth > kSPI_Data8Bits) && (xfer->dataSize & 0x1)) + { + return kStatus_InvalidArgument; + } + + /* clear tx/rx errors and empty FIFOs */ + base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK; + base->FIFOSTAT |= SPI_FIFOSTAT_TXERR_MASK | SPI_FIFOSTAT_RXERR_MASK; + /* select slave to talk with */ + tx_ctrl |= (SPI_DEASSERT_ALL & (~SPI_DEASSERTNUM_SSEL(g_configs[instance].sselNum))); + /* set width of data - range asserted at entry */ + tx_ctrl |= SPI_FIFOWR_LEN(dataWidth); + /* delay for frames */ + tx_ctrl |= (xfer->configFlags & (uint32_t)kSPI_FrameDelay) ? (uint32_t)kSPI_FrameDelay : 0; + /* end of transfer */ + last_ctrl |= (xfer->configFlags & (uint32_t)kSPI_FrameAssert) ? (uint32_t)kSPI_FrameAssert : 0; + /* last index of loop */ + while (txRemainingBytes || rxRemainingBytes || toReceiveCount) + { + /* if rxFIFO is not empty */ + if (base->FIFOSTAT & SPI_FIFOSTAT_RXNOTEMPTY_MASK) + { + tmp32 = base->FIFORD; + /* rxBuffer is not empty */ + if (rxRemainingBytes) + { + *(rxData++) = tmp32; + rxRemainingBytes--; + /* read 16 bits at once */ + if (dataWidth > 8) + { + *(rxData++) = tmp32 >> 8; + rxRemainingBytes--; + } + } + /* decrease number of data expected to receive */ + toReceiveCount -= 1; + } + /* transmit if txFIFO is not full and data to receive does not exceed FIFO depth */ + if ((base->FIFOSTAT & SPI_FIFOSTAT_TXNOTFULL_MASK) && (toReceiveCount < fifoDepth) && + ((txRemainingBytes) || (rxRemainingBytes >= SPI_COUNT_TO_BYTES(dataWidth, toReceiveCount + 1)))) + { + /* txBuffer is not empty */ + if (txRemainingBytes) + { + tmp32 = *(txData++); + txRemainingBytes--; + /* write 16 bit at once */ + if (dataWidth > 8) + { + tmp32 |= ((uint32_t)(*(txData++))) << 8U; + txRemainingBytes--; + } + if (!txRemainingBytes) + { + tx_ctrl |= last_ctrl; + } + } + else + { + tmp32 = ((uint32_t)s_dummyData[instance] << 8U | (s_dummyData[instance])); + /* last transfer */ + if (rxRemainingBytes == SPI_COUNT_TO_BYTES(dataWidth, toReceiveCount + 1)) + { + tx_ctrl |= last_ctrl; + } + } + /* send data */ + tmp32 = tx_ctrl | tmp32; + base->FIFOWR = tmp32; + toReceiveCount += 1; + } + } + /* wait if TX FIFO of previous transfer is not empty */ + while (!(base->FIFOSTAT & SPI_FIFOSTAT_TXEMPTY_MASK)) + { + } + return kStatus_Success; +} + +/*! + * brief Performs a non-blocking SPI interrupt transfer. + * + * param base SPI peripheral base address. + * param handle pointer to spi_master_handle_t structure which stores the transfer state + * param xfer pointer to spi_xfer_config_t structure + * retval kStatus_Success Successfully start a transfer. + * retval kStatus_InvalidArgument Input argument is invalid. + * retval kStatus_SPI_Busy SPI is not idle, is running another transfer. + */ +status_t SPI_MasterTransferNonBlocking(SPI_Type *base, spi_master_handle_t *handle, spi_transfer_t *xfer) +{ + /* check params */ + assert( + !((NULL == base) || (NULL == handle) || (NULL == xfer) || ((NULL == xfer->txData) && (NULL == xfer->rxData)))); + if ((NULL == base) || (NULL == handle) || (NULL == xfer) || ((NULL == xfer->txData) && (NULL == xfer->rxData))) + { + return kStatus_InvalidArgument; + } + + /* dataSize (in bytes) is not aligned to 16bit (2B) transfer */ + assert(!((handle->dataWidth > kSPI_Data8Bits) && (xfer->dataSize & 0x1))); + if ((handle->dataWidth > kSPI_Data8Bits) && (xfer->dataSize & 0x1)) + { + return kStatus_InvalidArgument; + } + + /* Check if SPI is busy */ + if (handle->state == kStatus_SPI_Busy) + { + return kStatus_SPI_Busy; + } + + /* Set the handle information */ + handle->txData = xfer->txData; + handle->rxData = xfer->rxData; + /* set count */ + handle->txRemainingBytes = xfer->txData ? xfer->dataSize : 0; + handle->rxRemainingBytes = xfer->rxData ? xfer->dataSize : 0; + handle->totalByteCount = xfer->dataSize; + /* other options */ + handle->toReceiveCount = 0; + handle->configFlags = xfer->configFlags; + /* Set the SPI state to busy */ + handle->state = kStatus_SPI_Busy; + /* clear FIFOs when transfer starts */ + base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK; + base->FIFOSTAT |= SPI_FIFOSTAT_TXERR_MASK | SPI_FIFOSTAT_RXERR_MASK; + /* enable generating txIRQ and rxIRQ, first transfer is fired by empty txFIFO */ + base->FIFOINTENSET |= SPI_FIFOINTENSET_TXLVL_MASK | SPI_FIFOINTENSET_RXLVL_MASK; + return kStatus_Success; +} + +/*! + * brief Transfers a block of data using a polling method. + * + * This function will do a half-duplex transfer for SPI master, This is a blocking function, + * which does not retuen until all transfer have been completed. And data transfer mechanism is half-duplex, + * users can set transmit first or receive first. + * + * param base SPI base pointer + * param xfer pointer to spi_half_duplex_transfer_t structure + * return status of status_t. + */ +status_t SPI_MasterHalfDuplexTransferBlocking(SPI_Type *base, spi_half_duplex_transfer_t *xfer) +{ + assert(xfer); + + spi_transfer_t tempXfer = {0}; + status_t status; + + if (xfer->isTransmitFirst) + { + tempXfer.txData = xfer->txData; + tempXfer.rxData = NULL; + tempXfer.dataSize = xfer->txDataSize; + } + else + { + tempXfer.txData = NULL; + tempXfer.rxData = xfer->rxData; + tempXfer.dataSize = xfer->rxDataSize; + } + /* If the pcs pin keep assert between transmit and receive. */ + if (xfer->isPcsAssertInTransfer) + { + tempXfer.configFlags = (xfer->configFlags) & (uint32_t)(~kSPI_FrameAssert); + } + else + { + tempXfer.configFlags = (xfer->configFlags) | kSPI_FrameAssert; + } + + status = SPI_MasterTransferBlocking(base, &tempXfer); + + if (status != kStatus_Success) + { + return status; + } + + if (xfer->isTransmitFirst) + { + tempXfer.txData = NULL; + tempXfer.rxData = xfer->rxData; + tempXfer.dataSize = xfer->rxDataSize; + } + else + { + tempXfer.txData = xfer->txData; + tempXfer.rxData = NULL; + tempXfer.dataSize = xfer->txDataSize; + } + tempXfer.configFlags = xfer->configFlags; + + /* SPI transfer blocking. */ + status = SPI_MasterTransferBlocking(base, &tempXfer); + + return status; +} + +/*! + * brief Performs a non-blocking SPI interrupt transfer. + * + * This function using polling way to do the first half transimission and using interrupts to + * do the second half transimission, the transfer mechanism is half-duplex. + * When do the second half transimission, code will return right away. When all data is transferred, + * the callback function is called. + * + * param base SPI peripheral base address. + * param handle pointer to spi_master_handle_t structure which stores the transfer state + * param xfer pointer to spi_half_duplex_transfer_t structure + * return status of status_t. + */ +status_t SPI_MasterHalfDuplexTransferNonBlocking(SPI_Type *base, + spi_master_handle_t *handle, + spi_half_duplex_transfer_t *xfer) +{ + assert(xfer); + assert(handle); + spi_transfer_t tempXfer = {0}; + status_t status; + + if (xfer->isTransmitFirst) + { + tempXfer.txData = xfer->txData; + tempXfer.rxData = NULL; + tempXfer.dataSize = xfer->txDataSize; + } + else + { + tempXfer.txData = NULL; + tempXfer.rxData = xfer->rxData; + tempXfer.dataSize = xfer->rxDataSize; + } + /* If the PCS pin keep assert between transmit and receive. */ + if (xfer->isPcsAssertInTransfer) + { + tempXfer.configFlags = (xfer->configFlags) & (uint32_t)(~kSPI_FrameAssert); + } + else + { + tempXfer.configFlags = (xfer->configFlags) | kSPI_FrameAssert; + } + + status = SPI_MasterTransferBlocking(base, &tempXfer); + if (status != kStatus_Success) + { + return status; + } + + if (xfer->isTransmitFirst) + { + tempXfer.txData = NULL; + tempXfer.rxData = xfer->rxData; + tempXfer.dataSize = xfer->rxDataSize; + } + else + { + tempXfer.txData = xfer->txData; + tempXfer.rxData = NULL; + tempXfer.dataSize = xfer->txDataSize; + } + tempXfer.configFlags = xfer->configFlags; + + status = SPI_MasterTransferNonBlocking(base, handle, &tempXfer); + + return status; +} + +/*! + * brief Gets the master transfer count. + * + * This function gets the master transfer count. + * + * param base SPI peripheral base address. + * param handle Pointer to the spi_master_handle_t structure which stores the transfer state. + * param count The number of bytes transferred by using the non-blocking transaction. + * return status of status_t. + */ +status_t SPI_MasterTransferGetCount(SPI_Type *base, spi_master_handle_t *handle, size_t *count) +{ + assert(NULL != handle); + + if (!count) + { + return kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + if (handle->state != kStatus_SPI_Busy) + { + *count = 0; + return kStatus_NoTransferInProgress; + } + + *count = handle->totalByteCount - handle->rxRemainingBytes; + return kStatus_Success; +} + +/*! + * brief SPI master aborts a transfer using an interrupt. + * + * This function aborts a transfer using an interrupt. + * + * param base SPI peripheral base address. + * param handle Pointer to the spi_master_handle_t structure which stores the transfer state. + */ +void SPI_MasterTransferAbort(SPI_Type *base, spi_master_handle_t *handle) +{ + assert(NULL != handle); + + /* Disable interrupt requests*/ + base->FIFOINTENSET &= ~(SPI_FIFOINTENSET_TXLVL_MASK | SPI_FIFOINTENSET_RXLVL_MASK); + /* Empty FIFOs */ + base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK; + + handle->state = kStatus_SPI_Idle; + handle->txRemainingBytes = 0; + handle->rxRemainingBytes = 0; +} + +static void SPI_TransferHandleIRQInternal(SPI_Type *base, spi_master_handle_t *handle) +{ + uint32_t tx_ctrl = 0, last_ctrl = 0, tmp32; + bool loopContinue; + uint32_t fifoDepth; + /* Get flexcomm instance by 'base' param */ + uint32_t instance = SPI_GetInstance(base); + + /* check params */ + assert((NULL != base) && (NULL != handle) && ((NULL != handle->txData) || (NULL != handle->rxData))); + + fifoDepth = SPI_FIFO_DEPTH(base); + /* select slave to talk with */ + tx_ctrl |= (SPI_DEASSERT_ALL & SPI_ASSERTNUM_SSEL(handle->sselNum)); + /* set width of data */ + tx_ctrl |= SPI_FIFOWR_LEN(handle->dataWidth); + /* delay for frames */ + tx_ctrl |= (handle->configFlags & (uint32_t)kSPI_FrameDelay) ? (uint32_t)kSPI_FrameDelay : 0; + /* end of transfer */ + last_ctrl |= (handle->configFlags & (uint32_t)kSPI_FrameAssert) ? (uint32_t)kSPI_FrameAssert : 0; + do + { + loopContinue = false; + + /* rxFIFO is not empty */ + if (base->FIFOSTAT & SPI_FIFOSTAT_RXNOTEMPTY_MASK) + { + tmp32 = base->FIFORD; + /* rxBuffer is not empty */ + if (handle->rxRemainingBytes) + { + /* low byte must go first */ + *(handle->rxData++) = tmp32; + handle->rxRemainingBytes--; + /* read 16 bits at once */ + if (handle->dataWidth > kSPI_Data8Bits) + { + *(handle->rxData++) = tmp32 >> 8; + handle->rxRemainingBytes--; + } + } + /* decrease number of data expected to receive */ + handle->toReceiveCount -= 1; + loopContinue = true; + } + + /* - txFIFO is not full + * - we cannot cause rxFIFO overflow by sending more data than is the depth of FIFO + * - txBuffer is not empty or the next 'toReceiveCount' data can fit into rxBuffer + */ + if ((base->FIFOSTAT & SPI_FIFOSTAT_TXNOTFULL_MASK) && (handle->toReceiveCount < fifoDepth) && + ((handle->txRemainingBytes) || + (handle->rxRemainingBytes >= SPI_COUNT_TO_BYTES(handle->dataWidth, handle->toReceiveCount + 1)))) + { + /* txBuffer is not empty */ + if (handle->txRemainingBytes) + { + /* low byte must go first */ + tmp32 = *(handle->txData++); + handle->txRemainingBytes--; + /* write 16 bit at once */ + if (handle->dataWidth > kSPI_Data8Bits) + { + tmp32 |= ((uint32_t)(*(handle->txData++))) << 8U; + handle->txRemainingBytes--; + } + /* last transfer */ + if (!handle->txRemainingBytes) + { + tx_ctrl |= last_ctrl; + } + } + else + { + tmp32 = ((uint32_t)s_dummyData[instance] << 8U | (s_dummyData[instance])); + /* last transfer */ + if (handle->rxRemainingBytes == SPI_COUNT_TO_BYTES(handle->dataWidth, handle->toReceiveCount + 1)) + { + tx_ctrl |= last_ctrl; + } + } + /* send data */ + tmp32 = tx_ctrl | tmp32; + base->FIFOWR = tmp32; + /* increase number of expected data to receive */ + handle->toReceiveCount += 1; + loopContinue = true; + } + } while (loopContinue); +} + +/*! + * brief Interrupts the handler for the SPI. + * + * param base SPI peripheral base address. + * param handle pointer to spi_master_handle_t structure which stores the transfer state. + */ +void SPI_MasterTransferHandleIRQ(SPI_Type *base, spi_master_handle_t *handle) +{ + assert((NULL != base) && (NULL != handle)); + + /* IRQ behaviour: + * - first interrupt is triggered by empty txFIFO. The transfer function + * then tries empty rxFIFO and fill txFIFO interleaved that results to + * strategy to process as many items as possible. + * - the next IRQs can be: + * rxIRQ from nonempty rxFIFO which requires to empty rxFIFO. + * txIRQ from empty txFIFO which requires to refill txFIFO. + * - last interrupt is triggered by empty txFIFO. The last state is + * known by empty rxBuffer and txBuffer. If there is nothing to receive + * or send - both operations have been finished and interrupts can be + * disabled. + */ + + /* Data to send or read or expected to receive */ + if ((handle->txRemainingBytes) || (handle->rxRemainingBytes) || (handle->toReceiveCount)) + { + /* Transmit or receive data */ + SPI_TransferHandleIRQInternal(base, handle); + /* No data to send or read or receive. Transfer ends. Set txTrigger to 0 level and + * enable txIRQ to confirm when txFIFO becomes empty */ + if ((!handle->txRemainingBytes) && (!handle->rxRemainingBytes) && (!handle->toReceiveCount)) + { + base->FIFOTRIG = base->FIFOTRIG & (~SPI_FIFOTRIG_TXLVL_MASK); + base->FIFOINTENSET |= SPI_FIFOINTENSET_TXLVL_MASK; + } + else + { + uint32_t rxRemainingCount = SPI_BYTES_TO_COUNT(handle->dataWidth, handle->rxRemainingBytes); + /* If, there are no data to send or rxFIFO is already filled with necessary number of dummy data, + * disable txIRQ. From this point only rxIRQ is used to receive data without any transmission */ + if ((!handle->txRemainingBytes) && (rxRemainingCount <= handle->toReceiveCount)) + { + base->FIFOINTENCLR = SPI_FIFOINTENCLR_TXLVL_MASK; + } + /* Nothing to receive or transmit, but we still have pending data which are bellow rxLevel. + * Cannot clear rxFIFO, txFIFO might be still active */ + if (rxRemainingCount == 0) + { + if ((handle->txRemainingBytes == 0) && (handle->toReceiveCount != 0) && + (handle->toReceiveCount < SPI_FIFOTRIG_RXLVL_GET(base) + 1)) + { + base->FIFOTRIG = + (base->FIFOTRIG & (~SPI_FIFOTRIG_RXLVL_MASK)) | SPI_FIFOTRIG_RXLVL(handle->toReceiveCount - 1); + } + } + /* Expected to receive less data than rxLevel value, we have to update rxLevel */ + else + { + if (rxRemainingCount < (SPI_FIFOTRIG_RXLVL_GET(base) + 1)) + { + base->FIFOTRIG = + (base->FIFOTRIG & (~SPI_FIFOTRIG_RXLVL_MASK)) | SPI_FIFOTRIG_RXLVL(rxRemainingCount - 1); + } + } + } + } + else + { + /* Empty txFIFO is confirmed. Disable IRQs and restore triggers values */ + base->FIFOINTENCLR = SPI_FIFOINTENCLR_RXLVL_MASK | SPI_FIFOINTENCLR_TXLVL_MASK; + base->FIFOTRIG = (base->FIFOTRIG & (~(SPI_FIFOTRIG_RXLVL_MASK | SPI_FIFOTRIG_RXLVL_MASK))) | + SPI_FIFOTRIG_RXLVL(handle->rxWatermark) | SPI_FIFOTRIG_TXLVL(handle->txWatermark); + /* set idle state and call user callback */ + handle->state = kStatus_SPI_Idle; + if (handle->callback) + { + (handle->callback)(base, handle, handle->state, handle->userData); + } + } +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_spi.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_spi.h new file mode 100644 index 000000000..6da8f899e --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_spi.h @@ -0,0 +1,725 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_SPI_H_ +#define _FSL_SPI_H_ + +#include "fsl_common.h" +#include "fsl_flexcomm.h" + +/*! + * @addtogroup spi_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief SPI driver version 2.0.3. */ +#define FSL_SPI_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) +/*@}*/ + +/*! @brief Global variable for dummy data value setting. */ +extern volatile uint8_t s_dummyData[]; + +#ifndef SPI_DUMMYDATA +/*! @brief SPI dummy transfer data, the data is sent while txBuff is NULL. */ +#define SPI_DUMMYDATA (0xFFU) +#endif + +#define SPI_DATA(n) (((uint32_t)(n)) & 0xFFFF) +#define SPI_CTRLMASK (0xFFFF0000) + +#define SPI_ASSERTNUM_SSEL(n) ((~(1U << ((n) + 16))) & 0xF0000) +#define SPI_DEASSERTNUM_SSEL(n) (1U << ((n) + 16)) +#define SPI_DEASSERT_ALL (0xF0000) + +#define SPI_FIFOWR_FLAGS_MASK (~(SPI_DEASSERT_ALL | SPI_FIFOWR_TXDATA_MASK | SPI_FIFOWR_LEN_MASK)) + +#define SPI_FIFOTRIG_TXLVL_GET(base) (((base)->FIFOTRIG & SPI_FIFOTRIG_TXLVL_MASK) >> SPI_FIFOTRIG_TXLVL_SHIFT) +#define SPI_FIFOTRIG_RXLVL_GET(base) (((base)->FIFOTRIG & SPI_FIFOTRIG_RXLVL_MASK) >> SPI_FIFOTRIG_RXLVL_SHIFT) + +/*! @brief SPI transfer option.*/ +typedef enum _spi_xfer_option +{ + kSPI_FrameDelay = (SPI_FIFOWR_EOF_MASK), /*!< A delay may be inserted, defined in the DLY register.*/ + kSPI_FrameAssert = (SPI_FIFOWR_EOT_MASK), /*!< SSEL will be deasserted at the end of a transfer */ +} spi_xfer_option_t; + +/*! @brief SPI data shifter direction options.*/ +typedef enum _spi_shift_direction +{ + kSPI_MsbFirst = 0U, /*!< Data transfers start with most significant bit. */ + kSPI_LsbFirst = 1U /*!< Data transfers start with least significant bit. */ +} spi_shift_direction_t; + +/*! @brief SPI clock polarity configuration.*/ +typedef enum _spi_clock_polarity +{ + kSPI_ClockPolarityActiveHigh = 0x0U, /*!< Active-high SPI clock (idles low). */ + kSPI_ClockPolarityActiveLow /*!< Active-low SPI clock (idles high). */ +} spi_clock_polarity_t; + +/*! @brief SPI clock phase configuration.*/ +typedef enum _spi_clock_phase +{ + kSPI_ClockPhaseFirstEdge = 0x0U, /*!< First edge on SCK occurs at the middle of the first + * cycle of a data transfer. */ + kSPI_ClockPhaseSecondEdge /*!< First edge on SCK occurs at the start of the + * first cycle of a data transfer. */ +} spi_clock_phase_t; + +/*! @brief txFIFO watermark values */ +typedef enum _spi_txfifo_watermark +{ + kSPI_TxFifo0 = 0, /*!< SPI tx watermark is empty */ + kSPI_TxFifo1 = 1, /*!< SPI tx watermark at 1 item */ + kSPI_TxFifo2 = 2, /*!< SPI tx watermark at 2 items */ + kSPI_TxFifo3 = 3, /*!< SPI tx watermark at 3 items */ + kSPI_TxFifo4 = 4, /*!< SPI tx watermark at 4 items */ + kSPI_TxFifo5 = 5, /*!< SPI tx watermark at 5 items */ + kSPI_TxFifo6 = 6, /*!< SPI tx watermark at 6 items */ + kSPI_TxFifo7 = 7, /*!< SPI tx watermark at 7 items */ +} spi_txfifo_watermark_t; + +/*! @brief rxFIFO watermark values */ +typedef enum _spi_rxfifo_watermark +{ + kSPI_RxFifo1 = 0, /*!< SPI rx watermark at 1 item */ + kSPI_RxFifo2 = 1, /*!< SPI rx watermark at 2 items */ + kSPI_RxFifo3 = 2, /*!< SPI rx watermark at 3 items */ + kSPI_RxFifo4 = 3, /*!< SPI rx watermark at 4 items */ + kSPI_RxFifo5 = 4, /*!< SPI rx watermark at 5 items */ + kSPI_RxFifo6 = 5, /*!< SPI rx watermark at 6 items */ + kSPI_RxFifo7 = 6, /*!< SPI rx watermark at 7 items */ + kSPI_RxFifo8 = 7, /*!< SPI rx watermark at 8 items */ +} spi_rxfifo_watermark_t; + +/*! @brief Transfer data width */ +typedef enum _spi_data_width +{ + kSPI_Data4Bits = 3, /*!< 4 bits data width */ + kSPI_Data5Bits = 4, /*!< 5 bits data width */ + kSPI_Data6Bits = 5, /*!< 6 bits data width */ + kSPI_Data7Bits = 6, /*!< 7 bits data width */ + kSPI_Data8Bits = 7, /*!< 8 bits data width */ + kSPI_Data9Bits = 8, /*!< 9 bits data width */ + kSPI_Data10Bits = 9, /*!< 10 bits data width */ + kSPI_Data11Bits = 10, /*!< 11 bits data width */ + kSPI_Data12Bits = 11, /*!< 12 bits data width */ + kSPI_Data13Bits = 12, /*!< 13 bits data width */ + kSPI_Data14Bits = 13, /*!< 14 bits data width */ + kSPI_Data15Bits = 14, /*!< 15 bits data width */ + kSPI_Data16Bits = 15, /*!< 16 bits data width */ +} spi_data_width_t; + +/*! @brief Slave select */ +typedef enum _spi_ssel +{ + kSPI_Ssel0 = 0, /*!< Slave select 0 */ + kSPI_Ssel1 = 1, /*!< Slave select 1 */ + kSPI_Ssel2 = 2, /*!< Slave select 2 */ + kSPI_Ssel3 = 3, /*!< Slave select 3 */ +} spi_ssel_t; + +/*! @brief ssel polarity */ +typedef enum _spi_spol +{ + kSPI_Spol0ActiveHigh = SPI_CFG_SPOL0(1), + kSPI_Spol1ActiveHigh = SPI_CFG_SPOL1(1), + kSPI_Spol2ActiveHigh = SPI_CFG_SPOL2(1), + kSPI_Spol3ActiveHigh = SPI_CFG_SPOL3(1), + kSPI_SpolActiveAllHigh = + (kSPI_Spol0ActiveHigh | kSPI_Spol1ActiveHigh | kSPI_Spol2ActiveHigh | kSPI_Spol3ActiveHigh), + kSPI_SpolActiveAllLow = 0, +} spi_spol_t; + +/*! + * @brief SPI delay time configure structure. + * Note: + * The DLY register controls several programmable delays related to SPI signalling, + * it stands for how many SPI clock time will be inserted. + * The maxinun value of these delay time is 15. + */ +typedef struct _spi_delay_config +{ + uint8_t preDelay; /*!< Delay between SSEL assertion and the beginning of transfer. */ + uint8_t postDelay; /*!< Delay between the end of transfer and SSEL deassertion. */ + uint8_t frameDelay; /*!< Delay between frame to frame. */ + uint8_t transferDelay; /*!< Delay between transfer to transfer. */ +} spi_delay_config_t; + +/*! @brief SPI master user configure structure.*/ +typedef struct _spi_master_config +{ + bool enableLoopback; /*!< Enable loopback for test purpose */ + bool enableMaster; /*!< Enable SPI at initialization time */ + spi_clock_polarity_t polarity; /*!< Clock polarity */ + spi_clock_phase_t phase; /*!< Clock phase */ + spi_shift_direction_t direction; /*!< MSB or LSB */ + uint32_t baudRate_Bps; /*!< Baud Rate for SPI in Hz */ + spi_data_width_t dataWidth; /*!< Width of the data */ + spi_ssel_t sselNum; /*!< Slave select number */ + spi_spol_t sselPol; /*!< Configure active CS polarity */ + spi_txfifo_watermark_t txWatermark; /*!< txFIFO watermark */ + spi_rxfifo_watermark_t rxWatermark; /*!< rxFIFO watermark */ + spi_delay_config_t delayConfig; /*!< Delay configuration. */ +} spi_master_config_t; + +/*! @brief SPI slave user configure structure.*/ +typedef struct _spi_slave_config +{ + bool enableSlave; /*!< Enable SPI at initialization time */ + spi_clock_polarity_t polarity; /*!< Clock polarity */ + spi_clock_phase_t phase; /*!< Clock phase */ + spi_shift_direction_t direction; /*!< MSB or LSB */ + spi_data_width_t dataWidth; /*!< Width of the data */ + spi_spol_t sselPol; /*!< Configure active CS polarity */ + spi_txfifo_watermark_t txWatermark; /*!< txFIFO watermark */ + spi_rxfifo_watermark_t rxWatermark; /*!< rxFIFO watermark */ +} spi_slave_config_t; + +/*! @brief SPI transfer status.*/ +enum _spi_status +{ + kStatus_SPI_Busy = MAKE_STATUS(kStatusGroup_LPC_SPI, 0), /*!< SPI bus is busy */ + kStatus_SPI_Idle = MAKE_STATUS(kStatusGroup_LPC_SPI, 1), /*!< SPI is idle */ + kStatus_SPI_Error = MAKE_STATUS(kStatusGroup_LPC_SPI, 2), /*!< SPI error */ + kStatus_SPI_BaudrateNotSupport = + MAKE_STATUS(kStatusGroup_LPC_SPI, 3) /*!< Baudrate is not support in current clock source */ +}; + +/*! @brief SPI interrupt sources.*/ +enum _spi_interrupt_enable +{ + kSPI_RxLvlIrq = SPI_FIFOINTENSET_RXLVL_MASK, /*!< Rx level interrupt */ + kSPI_TxLvlIrq = SPI_FIFOINTENSET_TXLVL_MASK, /*!< Tx level interrupt */ +}; + +/*! @brief SPI status flags.*/ +enum _spi_statusflags +{ + kSPI_TxEmptyFlag = SPI_FIFOSTAT_TXEMPTY_MASK, /*!< txFifo is empty */ + kSPI_TxNotFullFlag = SPI_FIFOSTAT_TXNOTFULL_MASK, /*!< txFifo is not full */ + kSPI_RxNotEmptyFlag = SPI_FIFOSTAT_RXNOTEMPTY_MASK, /*!< rxFIFO is not empty */ + kSPI_RxFullFlag = SPI_FIFOSTAT_RXFULL_MASK, /*!< rxFIFO is full */ +}; + +/*! @brief SPI transfer structure */ +typedef struct _spi_transfer +{ + uint8_t *txData; /*!< Send buffer */ + uint8_t *rxData; /*!< Receive buffer */ + uint32_t configFlags; /*!< Additional option to control transfer, @ref spi_xfer_option_t. */ + size_t dataSize; /*!< Transfer bytes */ +} spi_transfer_t; + +/*! @brief SPI half-duplex(master only) transfer structure */ +typedef struct _spi_half_duplex_transfer +{ + uint8_t *txData; /*!< Send buffer */ + uint8_t *rxData; /*!< Receive buffer */ + size_t txDataSize; /*!< Transfer bytes for transmit */ + size_t rxDataSize; /*!< Transfer bytes */ + uint32_t configFlags; /*!< Transfer configuration flags, @ref spi_xfer_option_t. */ + bool isPcsAssertInTransfer; /*!< If PCS pin keep assert between transmit and receive. true for assert and false for + deassert. */ + bool isTransmitFirst; /*!< True for transmit first and false for receive first. */ +} spi_half_duplex_transfer_t; + +/*! @brief Internal configuration structure used in 'spi' and 'spi_dma' driver */ +typedef struct _spi_config +{ + spi_data_width_t dataWidth; + spi_ssel_t sselNum; +} spi_config_t; + +/*! @brief Master handle type */ +typedef struct _spi_master_handle spi_master_handle_t; + +/*! @brief Slave handle type */ +typedef spi_master_handle_t spi_slave_handle_t; + +/*! @brief SPI master callback for finished transmit */ +typedef void (*spi_master_callback_t)(SPI_Type *base, spi_master_handle_t *handle, status_t status, void *userData); + +/*! @brief SPI slave callback for finished transmit */ +typedef void (*spi_slave_callback_t)(SPI_Type *base, spi_slave_handle_t *handle, status_t status, void *userData); + +/*! @brief SPI transfer handle structure */ +struct _spi_master_handle +{ + uint8_t *volatile txData; /*!< Transfer buffer */ + uint8_t *volatile rxData; /*!< Receive buffer */ + volatile size_t txRemainingBytes; /*!< Number of data to be transmitted [in bytes] */ + volatile size_t rxRemainingBytes; /*!< Number of data to be received [in bytes] */ + volatile size_t toReceiveCount; /*!< Receive data remaining in bytes */ + size_t totalByteCount; /*!< A number of transfer bytes */ + volatile uint32_t state; /*!< SPI internal state */ + spi_master_callback_t callback; /*!< SPI callback */ + void *userData; /*!< Callback parameter */ + uint8_t dataWidth; /*!< Width of the data [Valid values: 1 to 16] */ + uint8_t sselNum; /*!< Slave select number to be asserted when transferring data [Valid values: 0 to 3] */ + uint32_t configFlags; /*!< Additional option to control transfer */ + spi_txfifo_watermark_t txWatermark; /*!< txFIFO watermark */ + spi_rxfifo_watermark_t rxWatermark; /*!< rxFIFO watermark */ +}; + +#if defined(__cplusplus) +extern "C" { +#endif +/******************************************************************************* + * API + ******************************************************************************/ + +/*! @brief Returns instance number for SPI peripheral base address. */ +uint32_t SPI_GetInstance(SPI_Type *base); + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Sets the SPI master configuration structure to default values. + * + * The purpose of this API is to get the configuration structure initialized for use in SPI_MasterInit(). + * User may use the initialized structure unchanged in SPI_MasterInit(), or modify + * some fields of the structure before calling SPI_MasterInit(). After calling this API, + * the master is ready to transfer. + * Example: + @code + spi_master_config_t config; + SPI_MasterGetDefaultConfig(&config); + @endcode + * + * @param config pointer to master config structure + */ +void SPI_MasterGetDefaultConfig(spi_master_config_t *config); + +/*! + * @brief Initializes the SPI with master configuration. + * + * The configuration structure can be filled by user from scratch, or be set with default + * values by SPI_MasterGetDefaultConfig(). After calling this API, the slave is ready to transfer. + * Example + @code + spi_master_config_t config = { + .baudRate_Bps = 400000, + ... + }; + SPI_MasterInit(SPI0, &config); + @endcode + * + * @param base SPI base pointer + * @param config pointer to master configuration structure + * @param srcClock_Hz Source clock frequency. + */ +status_t SPI_MasterInit(SPI_Type *base, const spi_master_config_t *config, uint32_t srcClock_Hz); + +/*! + * @brief Sets the SPI slave configuration structure to default values. + * + * The purpose of this API is to get the configuration structure initialized for use in SPI_SlaveInit(). + * Modify some fields of the structure before calling SPI_SlaveInit(). + * Example: + @code + spi_slave_config_t config; + SPI_SlaveGetDefaultConfig(&config); + @endcode + * + * @param config pointer to slave configuration structure + */ +void SPI_SlaveGetDefaultConfig(spi_slave_config_t *config); + +/*! + * @brief Initializes the SPI with slave configuration. + * + * The configuration structure can be filled by user from scratch or be set with + * default values by SPI_SlaveGetDefaultConfig(). + * After calling this API, the slave is ready to transfer. + * Example + @code + spi_slave_config_t config = { + .polarity = flexSPIClockPolarity_ActiveHigh; + .phase = flexSPIClockPhase_FirstEdge; + .direction = flexSPIMsbFirst; + ... + }; + SPI_SlaveInit(SPI0, &config); + @endcode + * + * @param base SPI base pointer + * @param config pointer to slave configuration structure + */ +status_t SPI_SlaveInit(SPI_Type *base, const spi_slave_config_t *config); + +/*! + * @brief De-initializes the SPI. + * + * Calling this API resets the SPI module, gates the SPI clock. + * The SPI module can't work unless calling the SPI_MasterInit/SPI_SlaveInit to initialize module. + * + * @param base SPI base pointer + */ +void SPI_Deinit(SPI_Type *base); + +/*! + * @brief Enable or disable the SPI Master or Slave + * @param base SPI base pointer + * @param enable or disable ( true = enable, false = disable) + */ +static inline void SPI_Enable(SPI_Type *base, bool enable) +{ + if (enable) + { + base->CFG |= SPI_CFG_ENABLE_MASK; + } + else + { + base->CFG &= ~SPI_CFG_ENABLE_MASK; + } +} + +/*! @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets the status flag. + * + * @param base SPI base pointer + * @return SPI Status, use status flag to AND @ref _spi_statusflags could get the related status. + */ +static inline uint32_t SPI_GetStatusFlags(SPI_Type *base) +{ + assert(NULL != base); + return base->FIFOSTAT; +} + +/*! @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables the interrupt for the SPI. + * + * @param base SPI base pointer + * @param irqs SPI interrupt source. The parameter can be any combination of the following values: + * @arg kSPI_RxLvlIrq + * @arg kSPI_TxLvlIrq + */ +static inline void SPI_EnableInterrupts(SPI_Type *base, uint32_t irqs) +{ + assert(NULL != base); + base->FIFOINTENSET = irqs; +} + +/*! + * @brief Disables the interrupt for the SPI. + * + * @param base SPI base pointer + * @param irqs SPI interrupt source. The parameter can be any combination of the following values: + * @arg kSPI_RxLvlIrq + * @arg kSPI_TxLvlIrq + */ +static inline void SPI_DisableInterrupts(SPI_Type *base, uint32_t irqs) +{ + assert(NULL != base); + base->FIFOINTENCLR = irqs; +} + +/*! @} */ + +/*! + * @name DMA Control + * @{ + */ + +/*! + * @brief Enables the DMA request from SPI txFIFO. + * + * @param base SPI base pointer + * @param enable True means enable DMA, false means disable DMA + */ +void SPI_EnableTxDMA(SPI_Type *base, bool enable); + +/*! + * @brief Enables the DMA request from SPI rxFIFO. + * + * @param base SPI base pointer + * @param enable True means enable DMA, false means disable DMA + */ +void SPI_EnableRxDMA(SPI_Type *base, bool enable); + +/*! @} */ + +/*! + * @name Bus Operations + * @{ + */ +/*! + * @brief Returns the configurations. + * + * @param base SPI peripheral address. + * @return return configurations which contain datawidth and SSEL numbers. + * return data type is a pointer of spi_config_t. + */ +void *SPI_GetConfig(SPI_Type *base); + +/*! + * @brief Sets the baud rate for SPI transfer. This is only used in master. + * + * @param base SPI base pointer + * @param baudrate_Bps baud rate needed in Hz. + * @param srcClock_Hz SPI source clock frequency in Hz. + */ +status_t SPI_MasterSetBaud(SPI_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz); + +/*! + * @brief Writes a data into the SPI data register. + * + * @param base SPI base pointer + * @param data needs to be write. + * @param configFlags transfer configuration options @ref spi_xfer_option_t + */ +void SPI_WriteData(SPI_Type *base, uint16_t data, uint32_t configFlags); + +/*! + * @brief Gets a data from the SPI data register. + * + * @param base SPI base pointer + * @return Data in the register. + */ +static inline uint32_t SPI_ReadData(SPI_Type *base) +{ + assert(NULL != base); + return base->FIFORD; +} + +/*! + * @brief Set delay time for transfer. + * the delay uint is SPI clock time, maximum value is 0xF. + * @param base SPI base pointer + * @param config configuration for delay option @ref spi_delay_config_t. + */ +static inline void SPI_SetTransferDelay(SPI_Type *base, const spi_delay_config_t *config) +{ + assert(NULL != base); + assert(NULL != config); + base->DLY = (SPI_DLY_PRE_DELAY(config->preDelay) | SPI_DLY_POST_DELAY(config->postDelay) | + SPI_DLY_FRAME_DELAY(config->frameDelay) | SPI_DLY_TRANSFER_DELAY(config->transferDelay)); +} + +/*! + * @brief Set up the dummy data. + * + * @param base SPI peripheral address. + * @param dummyData Data to be transferred when tx buffer is NULL. + */ +void SPI_SetDummyData(SPI_Type *base, uint8_t dummyData); + +/*! @} */ + +/*! + * @name Transactional + * @{ + */ + +/*! + * @brief Initializes the SPI master handle. + * + * This function initializes the SPI master handle which can be used for other SPI master transactional APIs. Usually, + * for a specified SPI instance, call this API once to get the initialized handle. + * + * @param base SPI peripheral base address. + * @param handle SPI handle pointer. + * @param callback Callback function. + * @param userData User data. + */ +status_t SPI_MasterTransferCreateHandle(SPI_Type *base, + spi_master_handle_t *handle, + spi_master_callback_t callback, + void *userData); + +/*! + * @brief Transfers a block of data using a polling method. + * + * @param base SPI base pointer + * @param xfer pointer to spi_xfer_config_t structure + * @retval kStatus_Success Successfully start a transfer. + * @retval kStatus_InvalidArgument Input argument is invalid. + */ +status_t SPI_MasterTransferBlocking(SPI_Type *base, spi_transfer_t *xfer); + +/*! + * @brief Performs a non-blocking SPI interrupt transfer. + * + * @param base SPI peripheral base address. + * @param handle pointer to spi_master_handle_t structure which stores the transfer state + * @param xfer pointer to spi_xfer_config_t structure + * @retval kStatus_Success Successfully start a transfer. + * @retval kStatus_InvalidArgument Input argument is invalid. + * @retval kStatus_SPI_Busy SPI is not idle, is running another transfer. + */ +status_t SPI_MasterTransferNonBlocking(SPI_Type *base, spi_master_handle_t *handle, spi_transfer_t *xfer); + +/*! + * @brief Transfers a block of data using a polling method. + * + * This function will do a half-duplex transfer for SPI master, This is a blocking function, + * which does not retuen until all transfer have been completed. And data transfer mechanism is half-duplex, + * users can set transmit first or receive first. + * + * @param base SPI base pointer + * @param xfer pointer to spi_half_duplex_transfer_t structure + * @return status of status_t. + */ +status_t SPI_MasterHalfDuplexTransferBlocking(SPI_Type *base, spi_half_duplex_transfer_t *xfer); + +/*! + * @brief Performs a non-blocking SPI interrupt transfer. + * + * This function using polling way to do the first half transimission and using interrupts to + * do the second half transimission, the transfer mechanism is half-duplex. + * When do the second half transimission, code will return right away. When all data is transferred, + * the callback function is called. + * + * @param base SPI peripheral base address. + * @param handle pointer to spi_master_handle_t structure which stores the transfer state + * @param xfer pointer to spi_half_duplex_transfer_t structure + * @return status of status_t. + */ +status_t SPI_MasterHalfDuplexTransferNonBlocking(SPI_Type *base, + spi_master_handle_t *handle, + spi_half_duplex_transfer_t *xfer); + +/*! + * @brief Gets the master transfer count. + * + * This function gets the master transfer count. + * + * @param base SPI peripheral base address. + * @param handle Pointer to the spi_master_handle_t structure which stores the transfer state. + * @param count The number of bytes transferred by using the non-blocking transaction. + * @return status of status_t. + */ +status_t SPI_MasterTransferGetCount(SPI_Type *base, spi_master_handle_t *handle, size_t *count); + +/*! + * @brief SPI master aborts a transfer using an interrupt. + * + * This function aborts a transfer using an interrupt. + * + * @param base SPI peripheral base address. + * @param handle Pointer to the spi_master_handle_t structure which stores the transfer state. + */ +void SPI_MasterTransferAbort(SPI_Type *base, spi_master_handle_t *handle); + +/*! + * @brief Interrupts the handler for the SPI. + * + * @param base SPI peripheral base address. + * @param handle pointer to spi_master_handle_t structure which stores the transfer state. + */ +void SPI_MasterTransferHandleIRQ(SPI_Type *base, spi_master_handle_t *handle); + +/*! + * @brief Initializes the SPI slave handle. + * + * This function initializes the SPI slave handle which can be used for other SPI slave transactional APIs. Usually, + * for a specified SPI instance, call this API once to get the initialized handle. + * + * @param base SPI peripheral base address. + * @param handle SPI handle pointer. + * @param callback Callback function. + * @param userData User data. + */ +static inline status_t SPI_SlaveTransferCreateHandle(SPI_Type *base, + spi_slave_handle_t *handle, + spi_slave_callback_t callback, + void *userData) +{ + return SPI_MasterTransferCreateHandle(base, handle, callback, userData); +} + +/*! + * @brief Performs a non-blocking SPI slave interrupt transfer. + * + * @note The API returns immediately after the transfer initialization is finished. + * + * @param base SPI peripheral base address. + * @param handle pointer to spi_master_handle_t structure which stores the transfer state + * @param xfer pointer to spi_xfer_config_t structure + * @retval kStatus_Success Successfully start a transfer. + * @retval kStatus_InvalidArgument Input argument is invalid. + * @retval kStatus_SPI_Busy SPI is not idle, is running another transfer. + */ +static inline status_t SPI_SlaveTransferNonBlocking(SPI_Type *base, spi_slave_handle_t *handle, spi_transfer_t *xfer) +{ + return SPI_MasterTransferNonBlocking(base, handle, xfer); +} + +/*! + * @brief Gets the slave transfer count. + * + * This function gets the slave transfer count. + * + * @param base SPI peripheral base address. + * @param handle Pointer to the spi_master_handle_t structure which stores the transfer state. + * @param count The number of bytes transferred by using the non-blocking transaction. + * @return status of status_t. + */ +static inline status_t SPI_SlaveTransferGetCount(SPI_Type *base, spi_slave_handle_t *handle, size_t *count) +{ + return SPI_MasterTransferGetCount(base, (spi_master_handle_t *)handle, count); +} + +/*! + * @brief SPI slave aborts a transfer using an interrupt. + * + * This function aborts a transfer using an interrupt. + * + * @param base SPI peripheral base address. + * @param handle Pointer to the spi_slave_handle_t structure which stores the transfer state. + */ +static inline void SPI_SlaveTransferAbort(SPI_Type *base, spi_slave_handle_t *handle) +{ + SPI_MasterTransferAbort(base, (spi_master_handle_t *)handle); +} + +/*! + * @brief Interrupts a handler for the SPI slave. + * + * @param base SPI peripheral base address. + * @param handle pointer to spi_slave_handle_t structure which stores the transfer state + */ +static inline void SPI_SlaveTransferHandleIRQ(SPI_Type *base, spi_slave_handle_t *handle) +{ + SPI_MasterTransferHandleIRQ(base, handle); +} + +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /* _FSL_SPI_H_*/ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_spi_dma.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_spi_dma.c new file mode 100644 index 000000000..3e725909c --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_spi_dma.c @@ -0,0 +1,554 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_spi_dma.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexcomm_spi_dma" +#endif + +/*configFlags & (uint32_t)kSPI_FrameDelay ? (uint32_t)kSPI_FrameDelay : 0; + *fifowr |= xfer->configFlags & (uint32_t)kSPI_FrameAssert ? (uint32_t)kSPI_FrameAssert : 0; +} + +static void SpiConfigToFifoWR(spi_config_t *config, uint32_t *fifowr) +{ + *fifowr |= (SPI_DEASSERT_ALL & (~SPI_DEASSERTNUM_SSEL(config->sselNum))); + /* set width of data - range asserted at entry */ + *fifowr |= SPI_FIFOWR_LEN(config->dataWidth); +} + +static void PrepareTxLastWord(spi_transfer_t *xfer, uint32_t *txLastWord, spi_config_t *config) +{ + if (config->dataWidth > kSPI_Data8Bits) + { + *txLastWord = (((uint32_t)xfer->txData[xfer->dataSize - 1] << 8U) | (xfer->txData[xfer->dataSize - 2])); + } + else + { + *txLastWord = xfer->txData[xfer->dataSize - 1]; + } + XferToFifoWR(xfer, txLastWord); + SpiConfigToFifoWR(config, txLastWord); +} + +static void SPI_SetupDummy(SPI_Type *base, spi_dma_txdummy_t *dummy, spi_transfer_t *xfer, spi_config_t *spi_config_p) +{ + uint32_t instance = SPI_GetInstance(base); + dummy->word = ((uint32_t)s_dummyData[instance] << 8U | s_dummyData[instance]); + dummy->lastWord = ((uint32_t)s_dummyData[instance] << 8U | s_dummyData[instance]); + XferToFifoWR(xfer, &dummy->word); + XferToFifoWR(xfer, &dummy->lastWord); + SpiConfigToFifoWR(spi_config_p, &dummy->word); + SpiConfigToFifoWR(spi_config_p, &dummy->lastWord); + /* Clear the end of transfer bit for continue word transfer. */ + dummy->word &= (uint32_t)(~kSPI_FrameAssert); +} + +/*! + * brief Initialize the SPI master DMA handle. + * + * This function initializes the SPI master DMA handle which can be used for other SPI master transactional APIs. + * Usually, for a specified SPI instance, user need only call this API once to get the initialized handle. + * + * param base SPI peripheral base address. + * param handle SPI handle pointer. + * param callback User callback function called at the end of a transfer. + * param userData User data for callback. + * param txHandle DMA handle pointer for SPI Tx, the handle shall be static allocated by users. + * param rxHandle DMA handle pointer for SPI Rx, the handle shall be static allocated by users. + */ +status_t SPI_MasterTransferCreateHandleDMA(SPI_Type *base, + spi_dma_handle_t *handle, + spi_dma_callback_t callback, + void *userData, + dma_handle_t *txHandle, + dma_handle_t *rxHandle) +{ + int32_t instance = 0; + + /* check 'base' */ + assert(!(NULL == base)); + if (NULL == base) + { + return kStatus_InvalidArgument; + } + /* check 'handle' */ + assert(!(NULL == handle)); + if (NULL == handle) + { + return kStatus_InvalidArgument; + } + + instance = SPI_GetInstance(base); + + memset(handle, 0, sizeof(*handle)); + /* Set spi base to handle */ + handle->txHandle = txHandle; + handle->rxHandle = rxHandle; + handle->callback = callback; + handle->userData = userData; + + /* Set SPI state to idle */ + handle->state = kSPI_Idle; + + /* Set handle to global state */ + s_dmaPrivateHandle[instance].base = base; + s_dmaPrivateHandle[instance].handle = handle; + + /* Install callback for Tx dma channel */ + DMA_SetCallback(handle->txHandle, SPI_TxDMACallback, &s_dmaPrivateHandle[instance]); + DMA_SetCallback(handle->rxHandle, SPI_RxDMACallback, &s_dmaPrivateHandle[instance]); + + return kStatus_Success; +} + +/*! + * brief Perform a non-blocking SPI transfer using DMA. + * + * note This interface returned immediately after transfer initiates, users should call + * SPI_GetTransferStatus to poll the transfer status to check whether SPI transfer finished. + * + * param base SPI peripheral base address. + * param handle SPI DMA handle pointer. + * param xfer Pointer to dma transfer structure. + * retval kStatus_Success Successfully start a transfer. + * retval kStatus_InvalidArgument Input argument is invalid. + * retval kStatus_SPI_Busy SPI is not idle, is running another transfer. + */ +status_t SPI_MasterTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_transfer_t *xfer) +{ + int32_t instance; + status_t result = kStatus_Success; + spi_config_t *spi_config_p; + + assert(!((NULL == handle) || (NULL == xfer))); + if ((NULL == handle) || (NULL == xfer)) + { + return kStatus_InvalidArgument; + } + + /* Byte size is zero. */ + assert(!(xfer->dataSize == 0)); + if (xfer->dataSize == 0) + { + return kStatus_InvalidArgument; + } + /* cannot get instance from base address */ + instance = SPI_GetInstance(base); + assert(!(instance < 0)); + if (instance < 0) + { + return kStatus_InvalidArgument; + } + + /* Check if the device is busy */ + if (handle->state == kSPI_Busy) + { + return kStatus_SPI_Busy; + } + else + { + uint32_t tmp; + dma_transfer_config_t xferConfig = {0}; + spi_config_p = (spi_config_t *)SPI_GetConfig(base); + + handle->state = kStatus_SPI_Busy; + handle->transferSize = xfer->dataSize; + + /* receive */ + SPI_EnableRxDMA(base, true); + if (xfer->rxData) + { + DMA_PrepareTransfer(&xferConfig, ((void *)((uint32_t)&base->FIFORD)), xfer->rxData, + ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))), + xfer->dataSize, kDMA_PeripheralToMemory, NULL); + } + else + { + DMA_PrepareTransfer(&xferConfig, ((void *)((uint32_t)&base->FIFORD)), &s_rxDummy, + ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))), + xfer->dataSize, kDMA_StaticToStatic, NULL); + } + DMA_SubmitTransfer(handle->rxHandle, &xferConfig); + handle->rxInProgress = true; + DMA_StartTransfer(handle->rxHandle); + + /* transmit */ + SPI_EnableTxDMA(base, true); + + if (xfer->txData) + { + if (xfer->configFlags & kSPI_FrameAssert) + { + PrepareTxLastWord(xfer, &s_txLastWord[instance], spi_config_p); + } + /* If end of tranfer function is enabled and data transfer frame is bigger then 1, use dma + * descriptor to send the last data. + */ + if ((xfer->configFlags & kSPI_FrameAssert) && + ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (xfer->dataSize > 2) : (xfer->dataSize > 1))) + { + dma_xfercfg_t tmp_xfercfg = {0}; + tmp_xfercfg.valid = true; + tmp_xfercfg.swtrig = true; + tmp_xfercfg.intA = true; + tmp_xfercfg.byteWidth = sizeof(uint32_t); + tmp_xfercfg.srcInc = 0; + tmp_xfercfg.dstInc = 0; + tmp_xfercfg.transferCount = 1; + /* Create chained descriptor to transmit last word */ + DMA_CreateDescriptor(&s_spi_descriptor_table[instance], &tmp_xfercfg, &s_txLastWord[instance], + ((void *)((uint32_t)&base->FIFOWR)), NULL); + + DMA_PrepareTransfer( + &xferConfig, xfer->txData, ((void *)((uint32_t)&base->FIFOWR)), + ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))), + ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (xfer->dataSize - 2) : (xfer->dataSize - 1)), + kDMA_MemoryToPeripheral, &s_spi_descriptor_table[instance]); + /* Disable interrupts for first descriptor to avoid calling callback twice. */ + xferConfig.xfercfg.intA = false; + xferConfig.xfercfg.intB = false; + result = DMA_SubmitTransfer(handle->txHandle, &xferConfig); + if (result != kStatus_Success) + { + return result; + } + } + else + { + DMA_PrepareTransfer( + &xferConfig, xfer->txData, ((void *)((uint32_t)&base->FIFOWR)), + ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))), + xfer->dataSize, kDMA_MemoryToPeripheral, NULL); + DMA_SubmitTransfer(handle->txHandle, &xferConfig); + } + } + else + { + /* Setup tx dummy data. */ + SPI_SetupDummy(base, &s_txDummy[instance], xfer, spi_config_p); + if ((xfer->configFlags & kSPI_FrameAssert) && + ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (xfer->dataSize > 2) : (xfer->dataSize > 1))) + { + dma_xfercfg_t tmp_xfercfg = {0}; + tmp_xfercfg.valid = true; + tmp_xfercfg.swtrig = true; + tmp_xfercfg.intA = true; + tmp_xfercfg.byteWidth = sizeof(uint32_t); + tmp_xfercfg.srcInc = 0; + tmp_xfercfg.dstInc = 0; + tmp_xfercfg.transferCount = 1; + /* Create chained descriptor to transmit last word */ + DMA_CreateDescriptor(&s_spi_descriptor_table[instance], &tmp_xfercfg, &s_txDummy[instance].lastWord, + (void *)((uint32_t)&base->FIFOWR), NULL); + /* Use common API to setup first descriptor */ + DMA_PrepareTransfer( + &xferConfig, &s_txDummy[instance].word, ((void *)((uint32_t)&base->FIFOWR)), + ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))), + ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (xfer->dataSize - 2) : (xfer->dataSize - 1)), + kDMA_StaticToStatic, &s_spi_descriptor_table[instance]); + /* Disable interrupts for first descriptor to avoid calling callback twice */ + xferConfig.xfercfg.intA = false; + xferConfig.xfercfg.intB = false; + result = DMA_SubmitTransfer(handle->txHandle, &xferConfig); + if (result != kStatus_Success) + { + return result; + } + } + else + { + DMA_PrepareTransfer( + &xferConfig, &s_txDummy[instance].word, ((void *)((uint32_t)&base->FIFOWR)), + ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))), + xfer->dataSize, kDMA_StaticToStatic, NULL); + result = DMA_SubmitTransfer(handle->txHandle, &xferConfig); + if (result != kStatus_Success) + { + return result; + } + } + } + + handle->txInProgress = true; + tmp = 0; + XferToFifoWR(xfer, &tmp); + SpiConfigToFifoWR(spi_config_p, &tmp); + + /* Setup the control info. + * Halfword writes to just the control bits (offset 0xE22) doesn't push anything into the FIFO. + * And the data access type of control bits must be uint16_t, byte writes or halfword writes to FIFOWR + * will push the data and the current control bits into the FIFO. + */ + if ((xfer->configFlags & kSPI_FrameAssert) && + ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (xfer->dataSize == 2U) : (xfer->dataSize == 1U))) + { + *(((uint16_t *)((uint32_t) & (base->FIFOWR))) + 1) = (uint16_t)(tmp >> 16U); + } + else + { + /* Clear the SPI_FIFOWR_EOT_MASK bit when data is not the last. */ + tmp &= (uint32_t)(~kSPI_FrameAssert); + *(((uint16_t *)((uint32_t) & (base->FIFOWR))) + 1) = (uint16_t)(tmp >> 16U); + } + + DMA_StartTransfer(handle->txHandle); + } + + return result; +} + +/*! + * brief Transfers a block of data using a DMA method. + * + * This function using polling way to do the first half transimission and using DMA way to + * do the srcond half transimission, the transfer mechanism is half-duplex. + * When do the second half transimission, code will return right away. When all data is transferred, + * the callback function is called. + * + * param base SPI base pointer + * param handle A pointer to the spi_master_dma_handle_t structure which stores the transfer state. + * param transfer A pointer to the spi_half_duplex_transfer_t structure. + * return status of status_t. + */ +status_t SPI_MasterHalfDuplexTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_half_duplex_transfer_t *xfer) +{ + assert(xfer); + assert(handle); + spi_transfer_t tempXfer = {0}; + status_t status; + + if (xfer->isTransmitFirst) + { + tempXfer.txData = xfer->txData; + tempXfer.rxData = NULL; + tempXfer.dataSize = xfer->txDataSize; + } + else + { + tempXfer.txData = NULL; + tempXfer.rxData = xfer->rxData; + tempXfer.dataSize = xfer->rxDataSize; + } + /* If the pcs pin keep assert between transmit and receive. */ + if (xfer->isPcsAssertInTransfer) + { + tempXfer.configFlags = (xfer->configFlags) & (uint32_t)(~kSPI_FrameAssert); + } + else + { + tempXfer.configFlags = (xfer->configFlags) | kSPI_FrameAssert; + } + + status = SPI_MasterTransferBlocking(base, &tempXfer); + if (status != kStatus_Success) + { + return status; + } + + if (xfer->isTransmitFirst) + { + tempXfer.txData = NULL; + tempXfer.rxData = xfer->rxData; + tempXfer.dataSize = xfer->rxDataSize; + } + else + { + tempXfer.txData = xfer->txData; + tempXfer.rxData = NULL; + tempXfer.dataSize = xfer->txDataSize; + } + tempXfer.configFlags = xfer->configFlags; + + status = SPI_MasterTransferDMA(base, handle, &tempXfer); + + return status; +} + +static void SPI_RxDMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t intmode) +{ + spi_dma_private_handle_t *privHandle = (spi_dma_private_handle_t *)userData; + spi_dma_handle_t *spiHandle = privHandle->handle; + SPI_Type *base = privHandle->base; + + /* change the state */ + spiHandle->rxInProgress = false; + + /* All finished, call the callback */ + if ((spiHandle->txInProgress == false) && (spiHandle->rxInProgress == false)) + { + spiHandle->state = kSPI_Idle; + if (spiHandle->callback) + { + (spiHandle->callback)(base, spiHandle, kStatus_Success, spiHandle->userData); + } + } +} + +static void SPI_TxDMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t intmode) +{ + spi_dma_private_handle_t *privHandle = (spi_dma_private_handle_t *)userData; + spi_dma_handle_t *spiHandle = privHandle->handle; + SPI_Type *base = privHandle->base; + + /* change the state */ + spiHandle->txInProgress = false; + + /* All finished, call the callback */ + if ((spiHandle->txInProgress == false) && (spiHandle->rxInProgress == false)) + { + spiHandle->state = kSPI_Idle; + if (spiHandle->callback) + { + (spiHandle->callback)(base, spiHandle, kStatus_Success, spiHandle->userData); + } + } +} + +/*! + * brief Abort a SPI transfer using DMA. + * + * param base SPI peripheral base address. + * param handle SPI DMA handle pointer. + */ +void SPI_MasterTransferAbortDMA(SPI_Type *base, spi_dma_handle_t *handle) +{ + assert(NULL != handle); + + /* Stop tx transfer first */ + DMA_AbortTransfer(handle->txHandle); + /* Then rx transfer */ + DMA_AbortTransfer(handle->rxHandle); + + /* Set the handle state */ + handle->txInProgress = false; + handle->rxInProgress = false; + handle->state = kSPI_Idle; +} + +/*! + * brief Gets the master DMA transfer remaining bytes. + * + * This function gets the master DMA transfer remaining bytes. + * + * param base SPI peripheral base address. + * param handle A pointer to the spi_dma_handle_t structure which stores the transfer state. + * param count A number of bytes transferred by the non-blocking transaction. + * return status of status_t. + */ +status_t SPI_MasterTransferGetCountDMA(SPI_Type *base, spi_dma_handle_t *handle, size_t *count) +{ + assert(handle); + + if (!count) + { + return kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + if (handle->state != kSPI_Busy) + { + *count = 0; + return kStatus_NoTransferInProgress; + } + + size_t bytes; + + bytes = DMA_GetRemainingBytes(handle->rxHandle->base, handle->rxHandle->channel); + + *count = handle->transferSize - bytes; + + return kStatus_Success; +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_spi_dma.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_spi_dma.h new file mode 100644 index 000000000..9fd388a7a --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_spi_dma.h @@ -0,0 +1,208 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_SPI_DMA_H_ +#define _FSL_SPI_DMA_H_ + +#include "fsl_dma.h" +#include "fsl_spi.h" + +/*! + * @addtogroup spi_dma_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief SPI DMA driver version 2.0.3. */ +#define FSL_SPI_DMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) +/*@}*/ + +typedef struct _spi_dma_handle spi_dma_handle_t; + +/*! @brief SPI DMA callback called at the end of transfer. */ +typedef void (*spi_dma_callback_t)(SPI_Type *base, spi_dma_handle_t *handle, status_t status, void *userData); + +/*! @brief SPI DMA transfer handle, users should not touch the content of the handle.*/ +struct _spi_dma_handle +{ + volatile bool txInProgress; /*!< Send transfer finished */ + volatile bool rxInProgress; /*!< Receive transfer finished */ + dma_handle_t *txHandle; /*!< DMA handler for SPI send */ + dma_handle_t *rxHandle; /*!< DMA handler for SPI receive */ + uint8_t bytesPerFrame; /*!< Bytes in a frame for SPI transfer */ + spi_dma_callback_t callback; /*!< Callback for SPI DMA transfer */ + void *userData; /*!< User Data for SPI DMA callback */ + uint32_t state; /*!< Internal state of SPI DMA transfer */ + size_t transferSize; /*!< Bytes need to be transfer */ +}; + +/******************************************************************************* + * APIs + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name DMA Transactional + * @{ + */ + +/*! + * @brief Initialize the SPI master DMA handle. + * + * This function initializes the SPI master DMA handle which can be used for other SPI master transactional APIs. + * Usually, for a specified SPI instance, user need only call this API once to get the initialized handle. + * + * @param base SPI peripheral base address. + * @param handle SPI handle pointer. + * @param callback User callback function called at the end of a transfer. + * @param userData User data for callback. + * @param txHandle DMA handle pointer for SPI Tx, the handle shall be static allocated by users. + * @param rxHandle DMA handle pointer for SPI Rx, the handle shall be static allocated by users. + */ +status_t SPI_MasterTransferCreateHandleDMA(SPI_Type *base, + spi_dma_handle_t *handle, + spi_dma_callback_t callback, + void *userData, + dma_handle_t *txHandle, + dma_handle_t *rxHandle); + +/*! + * @brief Perform a non-blocking SPI transfer using DMA. + * + * @note This interface returned immediately after transfer initiates, users should call + * SPI_GetTransferStatus to poll the transfer status to check whether SPI transfer finished. + * + * @param base SPI peripheral base address. + * @param handle SPI DMA handle pointer. + * @param xfer Pointer to dma transfer structure. + * @retval kStatus_Success Successfully start a transfer. + * @retval kStatus_InvalidArgument Input argument is invalid. + * @retval kStatus_SPI_Busy SPI is not idle, is running another transfer. + */ +status_t SPI_MasterTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_transfer_t *xfer); + +/*! + * @brief Transfers a block of data using a DMA method. + * + * This function using polling way to do the first half transimission and using DMA way to + * do the srcond half transimission, the transfer mechanism is half-duplex. + * When do the second half transimission, code will return right away. When all data is transferred, + * the callback function is called. + * + * @param base SPI base pointer + * @param handle A pointer to the spi_master_dma_handle_t structure which stores the transfer state. + * @param transfer A pointer to the spi_half_duplex_transfer_t structure. + * @return status of status_t. + */ +status_t SPI_MasterHalfDuplexTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_half_duplex_transfer_t *xfer); + +/*! + * @brief Initialize the SPI slave DMA handle. + * + * This function initializes the SPI slave DMA handle which can be used for other SPI master transactional APIs. + * Usually, for a specified SPI instance, user need only call this API once to get the initialized handle. + * + * @param base SPI peripheral base address. + * @param handle SPI handle pointer. + * @param callback User callback function called at the end of a transfer. + * @param userData User data for callback. + * @param txHandle DMA handle pointer for SPI Tx, the handle shall be static allocated by users. + * @param rxHandle DMA handle pointer for SPI Rx, the handle shall be static allocated by users. + */ +static inline status_t SPI_SlaveTransferCreateHandleDMA(SPI_Type *base, + spi_dma_handle_t *handle, + spi_dma_callback_t callback, + void *userData, + dma_handle_t *txHandle, + dma_handle_t *rxHandle) +{ + return SPI_MasterTransferCreateHandleDMA(base, handle, callback, userData, txHandle, rxHandle); +} + +/*! + * @brief Perform a non-blocking SPI transfer using DMA. + * + * @note This interface returned immediately after transfer initiates, users should call + * SPI_GetTransferStatus to poll the transfer status to check whether SPI transfer finished. + * + * @param base SPI peripheral base address. + * @param handle SPI DMA handle pointer. + * @param xfer Pointer to dma transfer structure. + * @retval kStatus_Success Successfully start a transfer. + * @retval kStatus_InvalidArgument Input argument is invalid. + * @retval kStatus_SPI_Busy SPI is not idle, is running another transfer. + */ +static inline status_t SPI_SlaveTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_transfer_t *xfer) +{ + return SPI_MasterTransferDMA(base, handle, xfer); +} + +/*! + * @brief Abort a SPI transfer using DMA. + * + * @param base SPI peripheral base address. + * @param handle SPI DMA handle pointer. + */ +void SPI_MasterTransferAbortDMA(SPI_Type *base, spi_dma_handle_t *handle); + +/*! + * @brief Gets the master DMA transfer remaining bytes. + * + * This function gets the master DMA transfer remaining bytes. + * + * @param base SPI peripheral base address. + * @param handle A pointer to the spi_dma_handle_t structure which stores the transfer state. + * @param count A number of bytes transferred by the non-blocking transaction. + * @return status of status_t. + */ +status_t SPI_MasterTransferGetCountDMA(SPI_Type *base, spi_dma_handle_t *handle, size_t *count); + +/*! + * @brief Abort a SPI transfer using DMA. + * + * @param base SPI peripheral base address. + * @param handle SPI DMA handle pointer. + */ +static inline void SPI_SlaveTransferAbortDMA(SPI_Type *base, spi_dma_handle_t *handle) +{ + SPI_MasterTransferAbortDMA(base, handle); +} + +/*! + * @brief Gets the slave DMA transfer remaining bytes. + * + * This function gets the slave DMA transfer remaining bytes. + * + * @param base SPI peripheral base address. + * @param handle A pointer to the spi_dma_handle_t structure which stores the transfer state. + * @param count A number of bytes transferred by the non-blocking transaction. + * @return status of status_t. + */ +static inline status_t SPI_SlaveTransferGetCountDMA(SPI_Type *base, spi_dma_handle_t *handle, size_t *count) +{ + return SPI_MasterTransferGetCountDMA(base, handle, count); +} + +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /* _FSL_SPI_DMA_H_*/ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_sysctl.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_sysctl.c new file mode 100644 index 000000000..c62f96dac --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_sysctl.c @@ -0,0 +1,206 @@ +/* + * Copyright 2018 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_sysctl.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.sysctl" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Get the instance. + * + * @param base SYSCTL peripheral base address. + * @return Instance number. + */ +static uint32_t SYSCTL_GetInstance(SYSCTL_Type *base); + +/*! + * @brief Enable SYSCTL write protect + * + * @param base SYSCTL peripheral base address. + * @param regAddr register address + * @param value value to write. + */ +static void SYSCTL_UpdateRegister(SYSCTL_Type *base, volatile uint32_t *regAddr, uint32_t value); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief SYSCTL base address array name */ +static SYSCTL_Type *const s_sysctlBase[] = SYSCTL_BASE_PTRS; +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief SYSCTL clock array name */ +static const clock_ip_name_t s_sysctlClock[] = SYSCTL_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Code + ******************************************************************************/ +static void SYSCTL_UpdateRegister(SYSCTL_Type *base, volatile uint32_t *regAddr, uint32_t value) +{ + base->UPDATELCKOUT &= ~SYSCTL_UPDATELCKOUT_UPDATELCKOUT_MASK; + *regAddr = value; + base->UPDATELCKOUT |= SYSCTL_UPDATELCKOUT_UPDATELCKOUT_MASK; +} + +static uint32_t SYSCTL_GetInstance(SYSCTL_Type *base) +{ + uint8_t instance = 0; + + while ((instance < ARRAY_SIZE(s_sysctlBase)) && (s_sysctlBase[instance] != base)) + { + instance++; + } + + assert(instance < ARRAY_SIZE(s_sysctlBase)); + + return instance; +} + +/*! + * @brief SYSCTL initial + * + * @param base Base address of the SYSCTL peripheral. + */ +void SYSCTL_Init(SYSCTL_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable SYSCTL clock. */ + CLOCK_EnableClock(s_sysctlClock[SYSCTL_GetInstance(base)]); +#endif +} + +/*! + * @brief SYSCTL deinit + * + * @param base Base address of the SYSCTL peripheral. + */ +void SYSCTL_Deinit(SYSCTL_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable SYSCTL clock. */ + CLOCK_DisableClock(s_sysctlClock[SYSCTL_GetInstance(base)]); +#endif +} + +/*! + * @brief SYSCTL share set configure for separate signal + * + * @param base Base address of the SYSCTL peripheral + * @param flexCommIndex index of flexcomm,reference _sysctl_share_src + * @param setIndex share set for sck, reference _sysctl_share_set_index + * + */ +void SYSCTL_SetShareSet(SYSCTL_Type *base, uint32_t flexCommIndex, sysctl_fcctrlsel_signal_t signal, uint32_t set) +{ + uint32_t tempReg = base->FCCTRLSEL[flexCommIndex]; + + tempReg &= ~(SYSCTL_FCCTRLSEL_SCKINSEL_MASK << signal); + tempReg |= (set + 1U) << signal; + + SYSCTL_UpdateRegister(base, &base->FCCTRLSEL[flexCommIndex], tempReg); +} + +/*! + * @brief SYSCTL share set configure for flexcomm + * + * @param base Base address of the SYSCTL peripheral. + * @param flexCommIndex index of flexcomm, reference _sysctl_share_src + * @param sckSet share set for sck,reference _sysctl_share_set_index + * @param wsSet share set for ws, reference _sysctl_share_set_index + * @param dataInSet share set for data in, reference _sysctl_share_set_index + * @param dataOutSet share set for data out, reference _sysctl_share_set_index + * + */ +void SYSCTL_SetFlexcommShareSet( + SYSCTL_Type *base, uint32_t flexCommIndex, uint32_t sckSet, uint32_t wsSet, uint32_t dataInSet, uint32_t dataOutSet) +{ + uint32_t tempReg = base->FCCTRLSEL[flexCommIndex]; + + tempReg &= ~(SYSCTL_FCCTRLSEL_SCKINSEL_MASK | SYSCTL_FCCTRLSEL_WSINSEL_MASK | SYSCTL_FCCTRLSEL_DATAINSEL_MASK | + SYSCTL_FCCTRLSEL_DATAOUTSEL_MASK); + tempReg |= SYSCTL_FCCTRLSEL_SCKINSEL(sckSet + 1U) | SYSCTL_FCCTRLSEL_WSINSEL(wsSet + 1U) | + SYSCTL_FCCTRLSEL_DATAINSEL(dataInSet + 1U) | SYSCTL_FCCTRLSEL_DATAOUTSEL(dataOutSet + 1U); + + SYSCTL_UpdateRegister(base, &base->FCCTRLSEL[flexCommIndex], tempReg); +} + +/*! + * @brief SYSCTL share set source configure + * + * @param base Base address of the SYSCTL peripheral + * @param setIndex index of share set, reference _sysctl_share_set_index + * @param sckShareSrc sck source for this share set,reference _sysctl_share_src + * @param wsShareSrc ws source for this share set,reference _sysctl_share_src + * @param dataInShareSrc data in source for this share set,reference _sysctl_share_src + * @param dataOutShareSrc data out source for this share set,reference _sysctl_dataout_mask + * + */ +void SYSCTL_SetShareSetSrc(SYSCTL_Type *base, + uint32_t setIndex, + uint32_t sckShareSrc, + uint32_t wsShareSrc, + uint32_t dataInShareSrc, + uint32_t dataOutMask) +{ + uint32_t tempReg = base->SHAREDCTRLSET[setIndex]; + + /* WS,SCK,DATA IN */ + tempReg &= + ~(SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDSCKSEL_MASK | SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDWSSEL_MASK | + SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDDATASEL_MASK); + tempReg |= SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDSCKSEL(sckShareSrc) | + SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDWSSEL(wsShareSrc) | + SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDDATASEL(dataInShareSrc); + + /* data out */ + tempReg &= + ~(SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC0DATAOUTEN_MASK | SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC1DATAOUTEN_MASK | + SYSCTL_SHARECTRLSET_SHAREDCTRLSET_F20DATAOUTEN_MASK | SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC6DATAOUTEN_MASK | + SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC7DATAOUTEN_MASK); + tempReg |= dataOutMask; + + SYSCTL_UpdateRegister(base, &base->SHAREDCTRLSET[setIndex], tempReg); +} + +/*! + * @brief SYSCTL sck source configure + * + * @param base Base address of the SYSCTL peripheral + * @param setIndex index of share set, reference _sysctl_share_set_index + * @param sckShareSrc sck source fro this share set,reference _sysctl_share_src + * + */ +void SYSCTL_SetShareSignalSrc(SYSCTL_Type *base, + uint32_t setIndex, + sysctl_sharedctrlset_signal_t signal, + uint32_t shareSrc) +{ + uint32_t tempReg = base->SHAREDCTRLSET[setIndex]; + + if (signal == kSYSCTL_SharedCtrlSignalDataOut) + { + tempReg |= 1 << (signal + shareSrc); + } + else + { + tempReg &= ~(SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDSCKSEL_MASK << signal); + tempReg |= shareSrc << signal; + } + + SYSCTL_UpdateRegister(base, &base->SHAREDCTRLSET[setIndex], tempReg); +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_sysctl.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_sysctl.h new file mode 100644 index 000000000..edeb0ecd2 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_sysctl.h @@ -0,0 +1,185 @@ +/* + * Copyright 2018 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_SYSCTL_H_ +#define _FSL_SYSCTL_H_ + +#include "fsl_common.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @addtogroup sysctl + * @{ + */ + +/*! @file */ +/*! @file fsl_sysctl.h */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief Group sysctl driver version for SDK */ +#define FSL_SYSCTL_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) /*!< Version 2.0.2. */ +/*@}*/ + +/*! @brief SYSCTL share set*/ +enum _sysctl_share_set_index +{ + kSYSCTL_ShareSet0 = 0, /*!< share set 0 */ + kSYSCTL_ShareSet1 = 1, /*!< share set 1 */ +}; + +/*! @brief SYSCTL flexcomm signal */ +typedef enum _sysctl_fcctrlsel_signal +{ + kSYSCTL_FlexcommSignalSCK = SYSCTL_FCCTRLSEL_SCKINSEL_SHIFT, /*!< SCK signal */ + kSYSCTL_FlexcommSignalWS = SYSCTL_FCCTRLSEL_WSINSEL_SHIFT, /*!< WS signal */ + kSYSCTL_FlexcommSignalDataIn = SYSCTL_FCCTRLSEL_DATAINSEL_SHIFT, /*!< Data in signal */ + kSYSCTL_FlexcommSignalDataOut = SYSCTL_FCCTRLSEL_DATAOUTSEL_SHIFT, /*!< Data out signal */ +} sysctl_fcctrlsel_signal_t; + +/*! @brief SYSCTL flexcomm index*/ +enum _sysctl_share_src +{ + kSYSCTL_Flexcomm0 = 0, /*!< share set 0 */ + kSYSCTL_Flexcomm1 = 1, /*!< share set 1 */ + kSYSCTL_Flexcomm2 = 2, /*!< share set 2 */ + kSYSCTL_Flexcomm4 = 4, /*!< share set 4 */ + kSYSCTL_Flexcomm5 = 5, /*!< share set 5 */ + kSYSCTL_Flexcomm6 = 6, /*!< share set 6 */ + kSYSCTL_Flexcomm7 = 7, /*!< share set 7 */ +}; + +/*! @brief SYSCTL shared data out mask */ +enum _sysctl_dataout_mask +{ + kSYSCTL_Flexcomm0DataOut = SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC0DATAOUTEN_MASK, /*!< share set 0 */ + kSYSCTL_Flexcomm1DataOut = SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC1DATAOUTEN_MASK, /*!< share set 1 */ + kSYSCTL_Flexcomm2DataOut = SYSCTL_SHARECTRLSET_SHAREDCTRLSET_F20DATAOUTEN_MASK, /*!< share set 2 */ + kSYSCTL_Flexcomm4DataOut = SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC4DATAOUTEN_MASK, /*!< share set 4 */ + kSYSCTL_Flexcomm5DataOut = SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC5DATAOUTEN_MASK, /*!< share set 5 */ + kSYSCTL_Flexcomm6DataOut = SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC6DATAOUTEN_MASK, /*!< share set 6 */ + kSYSCTL_Flexcomm7DataOut = SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC7DATAOUTEN_MASK, /*!< share set 7 */ +}; + +/*! @brief SYSCTL flexcomm signal */ +typedef enum _sysctl_sharedctrlset_signal +{ + kSYSCTL_SharedCtrlSignalSCK = SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDSCKSEL_SHIFT, /*!< SCK signal */ + kSYSCTL_SharedCtrlSignalWS = SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDWSSEL_SHIFT, /*!< WS signal */ + kSYSCTL_SharedCtrlSignalDataIn = SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDDATASEL_SHIFT, /*!< Data in signal */ + kSYSCTL_SharedCtrlSignalDataOut = SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC0DATAOUTEN_SHIFT, /*!< Data out signal */ +} sysctl_sharedctrlset_signal_t; +/******************************************************************************* + * API + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief SYSCTL initial + * + * @param base Base address of the SYSCTL peripheral. + */ +void SYSCTL_Init(SYSCTL_Type *base); + +/*! + * @brief SYSCTL deinit + * + * @param base Base address of the SYSCTL peripheral. + */ +void SYSCTL_Deinit(SYSCTL_Type *base); + +/* @} */ + +/*! + * @name SYSCTL share signal configure + * @{ + */ + +/*! + * @brief SYSCTL share set configure for flexcomm + * + * @param base Base address of the SYSCTL peripheral. + * @param flexCommIndex index of flexcomm, reference _sysctl_share_src + * @param sckSet share set for sck,reference _sysctl_share_set_index + * @param wsSet share set for ws, reference _sysctl_share_set_index + * @param dataInSet share set for data in, reference _sysctl_share_set_index + * @param dataOutSet share set for data out, reference _sysctl_dataout_mask + * + */ +void SYSCTL_SetFlexcommShareSet(SYSCTL_Type *base, + uint32_t flexCommIndex, + uint32_t sckSet, + uint32_t wsSet, + uint32_t dataInSet, + uint32_t dataOutSet); + +/*! + * @brief SYSCTL share set configure for separate signal + * + * @param base Base address of the SYSCTL peripheral + * @param flexCommIndex index of flexcomm,reference _sysctl_share_src + * @param signal FCCTRLSEL signal shift + * @param setIndex share set for sck, reference _sysctl_share_set_index + * + */ +void SYSCTL_SetShareSet(SYSCTL_Type *base, uint32_t flexCommIndex, sysctl_fcctrlsel_signal_t signal, uint32_t set); + +/*! + * @brief SYSCTL share set source configure + * + * @param base Base address of the SYSCTL peripheral + * @param setIndex index of share set, reference _sysctl_share_set_index + * @param sckShareSrc sck source for this share set,reference _sysctl_share_src + * @param wsShareSrc ws source for this share set,reference _sysctl_share_src + * @param dataInShareSrc data in source for this share set,reference _sysctl_share_src + * @param dataOutShareSrc data out source for this share set,reference _sysctl_dataout_mask + * + */ +void SYSCTL_SetShareSetSrc(SYSCTL_Type *base, + uint32_t setIndex, + uint32_t sckShareSrc, + uint32_t wsShareSrc, + uint32_t dataInShareSrc, + uint32_t dataOutShareSrc); + +/*! + * @brief SYSCTL sck source configure + * + * @param base Base address of the SYSCTL peripheral + * @param setIndex index of share set, reference _sysctl_share_set_index + * @param sckShareSrc sck source fro this share set,reference _sysctl_share_src + * + */ +void SYSCTL_SetShareSignalSrc(SYSCTL_Type *base, + uint32_t setIndex, + sysctl_sharedctrlset_signal_t signal, + uint32_t shareSrc); + +/* @} */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _FSL_SYSCTL_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_usart.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_usart.c new file mode 100644 index 000000000..5df14ed83 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_usart.c @@ -0,0 +1,939 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_usart.h" +#include "fsl_device_registers.h" +#include "fsl_flexcomm.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexcomm_usart" +#endif + +enum _usart_transfer_states +{ + kUSART_TxIdle, /* TX idle. */ + kUSART_TxBusy, /* TX busy. */ + kUSART_RxIdle, /* RX idle. */ + kUSART_RxBusy /* RX busy. */ +}; + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief IRQ name array */ +static const IRQn_Type s_usartIRQ[] = USART_IRQS; + +/*! @brief Array to map USART instance number to base address. */ +static const uint32_t s_usartBaseAddrs[FSL_FEATURE_SOC_USART_COUNT] = USART_BASE_ADDRS; + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* Get the index corresponding to the USART */ +/*! brief Returns instance number for USART peripheral base address. */ +uint32_t USART_GetInstance(USART_Type *base) +{ + int i; + + for (i = 0; i < FSL_FEATURE_SOC_USART_COUNT; i++) + { + if ((uint32_t)base == s_usartBaseAddrs[i]) + { + return i; + } + } + + assert(false); + return 0; +} + +/*! + * brief Get the length of received data in RX ring buffer. + * + * param handle USART handle pointer. + * return Length of received data in RX ring buffer. + */ +size_t USART_TransferGetRxRingBufferLength(usart_handle_t *handle) +{ + size_t size; + + /* Check arguments */ + assert(NULL != handle); + + if (handle->rxRingBufferTail > handle->rxRingBufferHead) + { + size = (size_t)(handle->rxRingBufferHead + handle->rxRingBufferSize - handle->rxRingBufferTail); + } + else + { + size = (size_t)(handle->rxRingBufferHead - handle->rxRingBufferTail); + } + return size; +} + +static bool USART_TransferIsRxRingBufferFull(usart_handle_t *handle) +{ + bool full; + + /* Check arguments */ + assert(NULL != handle); + + if (USART_TransferGetRxRingBufferLength(handle) == (handle->rxRingBufferSize - 1U)) + { + full = true; + } + else + { + full = false; + } + return full; +} + +/*! + * brief Sets up the RX ring buffer. + * + * This function sets up the RX ring buffer to a specific USART handle. + * + * When the RX ring buffer is used, data received are stored into the ring buffer even when the + * user doesn't call the USART_TransferReceiveNonBlocking() API. If there is already data received + * in the ring buffer, the user can get the received data from the ring buffer directly. + * + * note When using the RX ring buffer, one byte is reserved for internal use. In other + * words, if p ringBufferSize is 32, then only 31 bytes are used for saving data. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + * param ringBuffer Start address of the ring buffer for background receiving. Pass NULL to disable the ring buffer. + * param ringBufferSize size of the ring buffer. + */ +void USART_TransferStartRingBuffer(USART_Type *base, usart_handle_t *handle, uint8_t *ringBuffer, size_t ringBufferSize) +{ + /* Check arguments */ + assert(NULL != base); + assert(NULL != handle); + assert(NULL != ringBuffer); + + /* Setup the ringbuffer address */ + handle->rxRingBuffer = ringBuffer; + handle->rxRingBufferSize = ringBufferSize; + handle->rxRingBufferHead = 0U; + handle->rxRingBufferTail = 0U; + /* ring buffer is ready we can start receiving data */ + base->FIFOINTENSET |= USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; +} + +/*! + * brief Aborts the background transfer and uninstalls the ring buffer. + * + * This function aborts the background transfer and uninstalls the ring buffer. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + */ +void USART_TransferStopRingBuffer(USART_Type *base, usart_handle_t *handle) +{ + /* Check arguments */ + assert(NULL != base); + assert(NULL != handle); + + if (handle->rxState == kUSART_RxIdle) + { + base->FIFOINTENCLR = USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENCLR_RXERR_MASK; + } + handle->rxRingBuffer = NULL; + handle->rxRingBufferSize = 0U; + handle->rxRingBufferHead = 0U; + handle->rxRingBufferTail = 0U; +} + +/*! + * brief Initializes a USART instance with user configuration structure and peripheral clock. + * + * This function configures the USART module with the user-defined settings. The user can configure the configuration + * structure and also get the default configuration by using the USART_GetDefaultConfig() function. + * Example below shows how to use this API to configure USART. + * code + * usart_config_t usartConfig; + * usartConfig.baudRate_Bps = 115200U; + * usartConfig.parityMode = kUSART_ParityDisabled; + * usartConfig.stopBitCount = kUSART_OneStopBit; + * USART_Init(USART1, &usartConfig, 20000000U); + * endcode + * + * param base USART peripheral base address. + * param config Pointer to user-defined configuration structure. + * param srcClock_Hz USART clock source frequency in HZ. + * retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. + * retval kStatus_InvalidArgument USART base address is not valid + * retval kStatus_Success Status USART initialize succeed + */ +status_t USART_Init(USART_Type *base, const usart_config_t *config, uint32_t srcClock_Hz) +{ + int result; + + /* check arguments */ + assert(!((NULL == base) || (NULL == config) || (0 == srcClock_Hz))); + if ((NULL == base) || (NULL == config) || (0 == srcClock_Hz)) + { + return kStatus_InvalidArgument; + } + + /* initialize flexcomm to USART mode */ + result = FLEXCOMM_Init(base, FLEXCOMM_PERIPH_USART); + if (kStatus_Success != result) + { + return result; + } + + if (config->enableTx) + { + /* empty and enable txFIFO */ + base->FIFOCFG |= USART_FIFOCFG_EMPTYTX_MASK | USART_FIFOCFG_ENABLETX_MASK; + /* setup trigger level */ + base->FIFOTRIG &= ~(USART_FIFOTRIG_TXLVL_MASK); + base->FIFOTRIG |= USART_FIFOTRIG_TXLVL(config->txWatermark); + /* enable trigger interrupt */ + base->FIFOTRIG |= USART_FIFOTRIG_TXLVLENA_MASK; + } + + /* empty and enable rxFIFO */ + if (config->enableRx) + { + base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK | USART_FIFOCFG_ENABLERX_MASK; + /* setup trigger level */ + base->FIFOTRIG &= ~(USART_FIFOTRIG_RXLVL_MASK); + base->FIFOTRIG |= USART_FIFOTRIG_RXLVL(config->rxWatermark); + /* enable trigger interrupt */ + base->FIFOTRIG |= USART_FIFOTRIG_RXLVLENA_MASK; + } + /* setup configuration and enable USART */ + base->CFG = USART_CFG_PARITYSEL(config->parityMode) | USART_CFG_STOPLEN(config->stopBitCount) | + USART_CFG_DATALEN(config->bitCountPerChar) | USART_CFG_LOOP(config->loopback) | + USART_CFG_SYNCEN(config->syncMode >> 1) | USART_CFG_SYNCMST(config->syncMode) | + USART_CFG_CLKPOL(config->clockPolarity) | USART_CFG_ENABLE_MASK; + + /* Setup baudrate */ + result = USART_SetBaudRate(base, config->baudRate_Bps, srcClock_Hz); + if (kStatus_Success != result) + { + return result; + } + /* Setting continuous Clock configuration. used for synchronous mode. */ + USART_EnableContinuousSCLK(base, config->enableContinuousSCLK); + + return kStatus_Success; +} + +/*! + * brief Deinitializes a USART instance. + * + * This function waits for TX complete, disables TX and RX, and disables the USART clock. + * + * param base USART peripheral base address. + */ +void USART_Deinit(USART_Type *base) +{ + /* Check arguments */ + assert(NULL != base); + while (!(base->STAT & USART_STAT_TXIDLE_MASK)) + { + } + /* Disable interrupts, disable dma requests, disable peripheral */ + base->FIFOINTENCLR = USART_FIFOINTENCLR_TXERR_MASK | USART_FIFOINTENCLR_RXERR_MASK | USART_FIFOINTENCLR_TXLVL_MASK | + USART_FIFOINTENCLR_RXLVL_MASK; + base->FIFOCFG &= ~(USART_FIFOCFG_DMATX_MASK | USART_FIFOCFG_DMARX_MASK); + base->CFG &= ~(USART_CFG_ENABLE_MASK); +} + +/*! + * brief Gets the default configuration structure. + * + * This function initializes the USART configuration structure to a default value. The default + * values are: + * usartConfig->baudRate_Bps = 115200U; + * usartConfig->parityMode = kUSART_ParityDisabled; + * usartConfig->stopBitCount = kUSART_OneStopBit; + * usartConfig->bitCountPerChar = kUSART_8BitsPerChar; + * usartConfig->loopback = false; + * usartConfig->enableTx = false; + * usartConfig->enableRx = false; + * + * param config Pointer to configuration structure. + */ +void USART_GetDefaultConfig(usart_config_t *config) +{ + /* Check arguments */ + assert(NULL != config); + + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + + /* Set always all members ! */ + config->baudRate_Bps = 115200U; + config->parityMode = kUSART_ParityDisabled; + config->stopBitCount = kUSART_OneStopBit; + config->bitCountPerChar = kUSART_8BitsPerChar; + config->loopback = false; + config->enableRx = false; + config->enableTx = false; + config->txWatermark = kUSART_TxFifo0; + config->rxWatermark = kUSART_RxFifo1; + config->syncMode = kUSART_SyncModeDisabled; + config->enableContinuousSCLK = false; + config->clockPolarity = kUSART_RxSampleOnFallingEdge; +} + +/*! + * brief Sets the USART instance baud rate. + * + * This function configures the USART module baud rate. This function is used to update + * the USART module baud rate after the USART module is initialized by the USART_Init. + * code + * USART_SetBaudRate(USART1, 115200U, 20000000U); + * endcode + * + * param base USART peripheral base address. + * param baudrate_Bps USART baudrate to be set. + * param srcClock_Hz USART clock source frequency in HZ. + * retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. + * retval kStatus_Success Set baudrate succeed. + * retval kStatus_InvalidArgument One or more arguments are invalid. + */ +status_t USART_SetBaudRate(USART_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz) +{ + uint32_t best_diff = (uint32_t)-1, best_osrval = 0xf, best_brgval = (uint32_t)-1; + uint32_t osrval, brgval, diff, baudrate; + + /* check arguments */ + assert(!((NULL == base) || (0 == baudrate_Bps) || (0 == srcClock_Hz))); + if ((NULL == base) || (0 == baudrate_Bps) || (0 == srcClock_Hz)) + { + return kStatus_InvalidArgument; + } + + /* If synchronous master mode is enabled, only configure the BRG value. */ + if (base->CFG & USART_CFG_SYNCEN_MASK) + { + if (base->CFG & USART_CFG_SYNCMST_MASK) + { + brgval = srcClock_Hz / baudrate_Bps; + base->BRG = brgval - 1; + } + } + else + { + /* + * Smaller values of OSR can make the sampling position within a data bit less accurate and may + * potentially cause more noise errors or incorrect data. + */ + for (osrval = best_osrval; osrval >= 8; osrval--) + { + brgval = (srcClock_Hz / ((osrval + 1) * baudrate_Bps)) - 1; + if (brgval > 0xFFFF) + { + continue; + } + baudrate = srcClock_Hz / ((osrval + 1) * (brgval + 1)); + diff = baudrate_Bps < baudrate ? baudrate - baudrate_Bps : baudrate_Bps - baudrate; + if (diff < best_diff) + { + best_diff = diff; + best_osrval = osrval; + best_brgval = brgval; + } + } + + /* value over range */ + if (best_brgval > 0xFFFF) + { + return kStatus_USART_BaudrateNotSupport; + } + + base->OSR = best_osrval; + base->BRG = best_brgval; + } + + return kStatus_Success; +} + +/*! + * brief Writes to the TX register using a blocking method. + * + * This function polls the TX register, waits for the TX register to be empty or for the TX FIFO + * to have room and writes data to the TX buffer. + * + * param base USART peripheral base address. + * param data Start address of the data to write. + * param length Size of the data to write. + */ +void USART_WriteBlocking(USART_Type *base, const uint8_t *data, size_t length) +{ + /* Check arguments */ + assert(!((NULL == base) || (NULL == data))); + if ((NULL == base) || (NULL == data)) + { + return; + } + /* Check whether txFIFO is enabled */ + if (!(base->FIFOCFG & USART_FIFOCFG_ENABLETX_MASK)) + { + return; + } + for (; length > 0; length--) + { + /* Loop until txFIFO get some space for new data */ + while (!(base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK)) + { + } + base->FIFOWR = *data; + data++; + } + /* Wait to finish transfer */ + while (!(base->STAT & USART_STAT_TXIDLE_MASK)) + { + } +} + +/*! + * brief Read RX data register using a blocking method. + * + * This function polls the RX register, waits for the RX register to be full or for RX FIFO to + * have data and read data from the TX register. + * + * param base USART peripheral base address. + * param data Start address of the buffer to store the received data. + * param length Size of the buffer. + * retval kStatus_USART_FramingError Receiver overrun happened while receiving data. + * retval kStatus_USART_ParityError Noise error happened while receiving data. + * retval kStatus_USART_NoiseError Framing error happened while receiving data. + * retval kStatus_USART_RxError Overflow or underflow rxFIFO happened. + * retval kStatus_Success Successfully received all data. + */ +status_t USART_ReadBlocking(USART_Type *base, uint8_t *data, size_t length) +{ + uint32_t status; + + /* check arguments */ + assert(!((NULL == base) || (NULL == data))); + if ((NULL == base) || (NULL == data)) + { + return kStatus_InvalidArgument; + } + + /* Check whether rxFIFO is enabled */ + if (!(base->FIFOCFG & USART_FIFOCFG_ENABLERX_MASK)) + { + return kStatus_Fail; + } + for (; length > 0; length--) + { + /* loop until rxFIFO have some data to read */ + while (!(base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK)) + { + } + /* check receive status */ + status = base->STAT; + if (status & USART_STAT_FRAMERRINT_MASK) + { + base->STAT |= USART_STAT_FRAMERRINT_MASK; + return kStatus_USART_FramingError; + } + if (status & USART_STAT_PARITYERRINT_MASK) + { + base->STAT |= USART_STAT_PARITYERRINT_MASK; + return kStatus_USART_ParityError; + } + if (status & USART_STAT_RXNOISEINT_MASK) + { + base->STAT |= USART_STAT_RXNOISEINT_MASK; + return kStatus_USART_NoiseError; + } + /* check rxFIFO status */ + if (base->FIFOSTAT & USART_FIFOSTAT_RXERR_MASK) + { + base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK; + base->FIFOSTAT |= USART_FIFOSTAT_RXERR_MASK; + return kStatus_USART_RxError; + } + + *data = base->FIFORD; + data++; + } + return kStatus_Success; +} + +/*! + * brief Initializes the USART handle. + * + * This function initializes the USART handle which can be used for other USART + * transactional APIs. Usually, for a specified USART instance, + * call this API once to get the initialized handle. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + * param callback The callback function. + * param userData The parameter of the callback function. + */ +status_t USART_TransferCreateHandle(USART_Type *base, + usart_handle_t *handle, + usart_transfer_callback_t callback, + void *userData) +{ + int32_t instance = 0; + + /* Check 'base' */ + assert(!((NULL == base) || (NULL == handle))); + if ((NULL == base) || (NULL == handle)) + { + return kStatus_InvalidArgument; + } + + instance = USART_GetInstance(base); + + memset(handle, 0, sizeof(*handle)); + /* Set the TX/RX state. */ + handle->rxState = kUSART_RxIdle; + handle->txState = kUSART_TxIdle; + /* Set the callback and user data. */ + handle->callback = callback; + handle->userData = userData; + handle->rxWatermark = (usart_rxfifo_watermark_t)USART_FIFOTRIG_RXLVL_GET(base); + handle->txWatermark = (usart_txfifo_watermark_t)USART_FIFOTRIG_TXLVL_GET(base); + + FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)USART_TransferHandleIRQ, handle); + + /* Enable interrupt in NVIC. */ + EnableIRQ(s_usartIRQ[instance]); + + return kStatus_Success; +} + +/*! + * brief Transmits a buffer of data using the interrupt method. + * + * This function sends data using an interrupt method. This is a non-blocking function, which + * returns directly without waiting for all data to be written to the TX register. When + * all data is written to the TX register in the IRQ handler, the USART driver calls the callback + * function and passes the ref kStatus_USART_TxIdle as status parameter. + * + * note The kStatus_USART_TxIdle is passed to the upper layer when all data is written + * to the TX register. However it does not ensure that all data are sent out. Before disabling the TX, + * check the kUSART_TransmissionCompleteFlag to ensure that the TX is finished. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + * param xfer USART transfer structure. See #usart_transfer_t. + * retval kStatus_Success Successfully start the data transmission. + * retval kStatus_USART_TxBusy Previous transmission still not finished, data not all written to TX register yet. + * retval kStatus_InvalidArgument Invalid argument. + */ +status_t USART_TransferSendNonBlocking(USART_Type *base, usart_handle_t *handle, usart_transfer_t *xfer) +{ + /* Check arguments */ + assert(!((NULL == base) || (NULL == handle) || (NULL == xfer))); + if ((NULL == base) || (NULL == handle) || (NULL == xfer)) + { + return kStatus_InvalidArgument; + } + /* Check xfer members */ + assert(!((0 == xfer->dataSize) || (NULL == xfer->data))); + if ((0 == xfer->dataSize) || (NULL == xfer->data)) + { + return kStatus_InvalidArgument; + } + + /* Return error if current TX busy. */ + if (kUSART_TxBusy == handle->txState) + { + return kStatus_USART_TxBusy; + } + else + { + handle->txData = xfer->data; + handle->txDataSize = xfer->dataSize; + handle->txDataSizeAll = xfer->dataSize; + handle->txState = kUSART_TxBusy; + /* Enable transmiter interrupt. */ + base->FIFOINTENSET |= USART_FIFOINTENSET_TXLVL_MASK; + } + return kStatus_Success; +} + +/*! + * brief Aborts the interrupt-driven data transmit. + * + * This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out + * how many bytes are still not sent out. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + */ +void USART_TransferAbortSend(USART_Type *base, usart_handle_t *handle) +{ + assert(NULL != handle); + + /* Disable interrupts */ + USART_DisableInterrupts(base, kUSART_TxLevelInterruptEnable); + /* Empty txFIFO */ + base->FIFOCFG |= USART_FIFOCFG_EMPTYTX_MASK; + + handle->txDataSize = 0; + handle->txState = kUSART_TxIdle; +} + +/*! + * brief Get the number of bytes that have been written to USART TX register. + * + * This function gets the number of bytes that have been written to USART TX + * register by interrupt method. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + * param count Send bytes count. + * retval kStatus_NoTransferInProgress No send in progress. + * retval kStatus_InvalidArgument Parameter is invalid. + * retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t USART_TransferGetSendCount(USART_Type *base, usart_handle_t *handle, uint32_t *count) +{ + assert(NULL != handle); + assert(NULL != count); + + if (kUSART_TxIdle == handle->txState) + { + return kStatus_NoTransferInProgress; + } + + *count = handle->txDataSizeAll - handle->txDataSize; + + return kStatus_Success; +} + +/*! + * brief Receives a buffer of data using an interrupt method. + * + * This function receives data using an interrupt method. This is a non-blocking function, which + * returns without waiting for all data to be received. + * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and + * the parameter p receivedBytes shows how many bytes are copied from the ring buffer. + * After copying, if the data in the ring buffer is not enough to read, the receive + * request is saved by the USART driver. When the new data arrives, the receive request + * is serviced first. When all data is received, the USART driver notifies the upper layer + * through a callback function and passes the status parameter ref kStatus_USART_RxIdle. + * For example, the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer. + * The 5 bytes are copied to the xfer->data and this function returns with the + * parameter p receivedBytes set to 5. For the left 5 bytes, newly arrived data is + * saved from the xfer->data[5]. When 5 bytes are received, the USART driver notifies the upper layer. + * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt + * to receive data to the xfer->data. When all data is received, the upper layer is notified. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + * param xfer USART transfer structure, see #usart_transfer_t. + * param receivedBytes Bytes received from the ring buffer directly. + * retval kStatus_Success Successfully queue the transfer into transmit queue. + * retval kStatus_USART_RxBusy Previous receive request is not finished. + * retval kStatus_InvalidArgument Invalid argument. + */ +status_t USART_TransferReceiveNonBlocking(USART_Type *base, + usart_handle_t *handle, + usart_transfer_t *xfer, + size_t *receivedBytes) +{ + uint32_t i; + /* How many bytes to copy from ring buffer to user memory. */ + size_t bytesToCopy = 0U; + /* How many bytes to receive. */ + size_t bytesToReceive; + /* How many bytes currently have received. */ + size_t bytesCurrentReceived; + uint32_t regPrimask = 0U; + + /* Check arguments */ + assert(!((NULL == base) || (NULL == handle) || (NULL == xfer))); + if ((NULL == base) || (NULL == handle) || (NULL == xfer)) + { + return kStatus_InvalidArgument; + } + /* Check xfer members */ + assert(!((0 == xfer->dataSize) || (NULL == xfer->data))); + if ((0 == xfer->dataSize) || (NULL == xfer->data)) + { + return kStatus_InvalidArgument; + } + + /* How to get data: + 1. If RX ring buffer is not enabled, then save xfer->data and xfer->dataSize + to uart handle, enable interrupt to store received data to xfer->data. When + all data received, trigger callback. + 2. If RX ring buffer is enabled and not empty, get data from ring buffer first. + If there are enough data in ring buffer, copy them to xfer->data and return. + If there are not enough data in ring buffer, copy all of them to xfer->data, + save the xfer->data remained empty space to uart handle, receive data + to this empty space and trigger callback when finished. */ + if (kUSART_RxBusy == handle->rxState) + { + return kStatus_USART_RxBusy; + } + else + { + bytesToReceive = xfer->dataSize; + bytesCurrentReceived = 0U; + /* If RX ring buffer is used. */ + if (handle->rxRingBuffer) + { + /* Disable IRQ, protect ring buffer. */ + regPrimask = DisableGlobalIRQ(); + /* How many bytes in RX ring buffer currently. */ + bytesToCopy = USART_TransferGetRxRingBufferLength(handle); + if (bytesToCopy) + { + bytesToCopy = MIN(bytesToReceive, bytesToCopy); + bytesToReceive -= bytesToCopy; + /* Copy data from ring buffer to user memory. */ + for (i = 0U; i < bytesToCopy; i++) + { + xfer->data[bytesCurrentReceived++] = handle->rxRingBuffer[handle->rxRingBufferTail]; + /* Wrap to 0. Not use modulo (%) because it might be large and slow. */ + if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize) + { + handle->rxRingBufferTail = 0U; + } + else + { + handle->rxRingBufferTail++; + } + } + } + /* If ring buffer does not have enough data, still need to read more data. */ + if (bytesToReceive) + { + /* No data in ring buffer, save the request to UART handle. */ + handle->rxData = xfer->data + bytesCurrentReceived; + handle->rxDataSize = bytesToReceive; + handle->rxDataSizeAll = bytesToReceive; + handle->rxState = kUSART_RxBusy; + } + /* Enable IRQ if previously enabled. */ + EnableGlobalIRQ(regPrimask); + /* Call user callback since all data are received. */ + if (0 == bytesToReceive) + { + if (handle->callback) + { + handle->callback(base, handle, kStatus_USART_RxIdle, handle->userData); + } + } + } + /* Ring buffer not used. */ + else + { + handle->rxData = xfer->data + bytesCurrentReceived; + handle->rxDataSize = bytesToReceive; + handle->rxDataSizeAll = bytesToReceive; + handle->rxState = kUSART_RxBusy; + + /* Enable RX interrupt. */ + base->FIFOINTENSET |= USART_FIFOINTENSET_RXLVL_MASK; + } + /* Return the how many bytes have read. */ + if (receivedBytes) + { + *receivedBytes = bytesCurrentReceived; + } + } + return kStatus_Success; +} + +/*! + * brief Aborts the interrupt-driven data receiving. + * + * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out + * how many bytes not received yet. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + */ +void USART_TransferAbortReceive(USART_Type *base, usart_handle_t *handle) +{ + assert(NULL != handle); + + /* Only abort the receive to handle->rxData, the RX ring buffer is still working. */ + if (!handle->rxRingBuffer) + { + /* Disable interrupts */ + USART_DisableInterrupts(base, kUSART_RxLevelInterruptEnable); + /* Empty rxFIFO */ + base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK; + } + + handle->rxDataSize = 0U; + handle->rxState = kUSART_RxIdle; +} + +/*! + * brief Get the number of bytes that have been received. + * + * This function gets the number of bytes that have been received. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + * param count Receive bytes count. + * retval kStatus_NoTransferInProgress No receive in progress. + * retval kStatus_InvalidArgument Parameter is invalid. + * retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t USART_TransferGetReceiveCount(USART_Type *base, usart_handle_t *handle, uint32_t *count) +{ + assert(NULL != handle); + assert(NULL != count); + + if (kUSART_RxIdle == handle->rxState) + { + return kStatus_NoTransferInProgress; + } + + *count = handle->rxDataSizeAll - handle->rxDataSize; + + return kStatus_Success; +} + +/*! + * brief USART IRQ handle function. + * + * This function handles the USART transmit and receive IRQ request. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + */ +void USART_TransferHandleIRQ(USART_Type *base, usart_handle_t *handle) +{ + /* Check arguments */ + assert((NULL != base) && (NULL != handle)); + + bool receiveEnabled = (handle->rxDataSize) || (handle->rxRingBuffer); + bool sendEnabled = handle->txDataSize; + + /* If RX overrun. */ + if (base->FIFOSTAT & USART_FIFOSTAT_RXERR_MASK) + { + /* Clear rx error state. */ + base->FIFOSTAT |= USART_FIFOSTAT_RXERR_MASK; + /* clear rxFIFO */ + base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK; + /* Trigger callback. */ + if (handle->callback) + { + handle->callback(base, handle, kStatus_USART_RxError, handle->userData); + } + } + while ((receiveEnabled && (base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK)) || + (sendEnabled && (base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK))) + { + /* Receive data */ + if (receiveEnabled && (base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK)) + { + /* Receive to app bufffer if app buffer is present */ + if (handle->rxDataSize) + { + *handle->rxData = base->FIFORD; + handle->rxDataSize--; + handle->rxData++; + receiveEnabled = ((handle->rxDataSize != 0) || (handle->rxRingBuffer)); + if (!handle->rxDataSize) + { + if (!handle->rxRingBuffer) + { + base->FIFOINTENCLR = USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; + } + handle->rxState = kUSART_RxIdle; + if (handle->callback) + { + handle->callback(base, handle, kStatus_USART_RxIdle, handle->userData); + } + } + } + /* Otherwise receive to ring buffer if ring buffer is present */ + else + { + if (handle->rxRingBuffer) + { + /* If RX ring buffer is full, trigger callback to notify over run. */ + if (USART_TransferIsRxRingBufferFull(handle)) + { + if (handle->callback) + { + handle->callback(base, handle, kStatus_USART_RxRingBufferOverrun, handle->userData); + } + } + /* If ring buffer is still full after callback function, the oldest data is overridden. */ + if (USART_TransferIsRxRingBufferFull(handle)) + { + /* Increase handle->rxRingBufferTail to make room for new data. */ + if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize) + { + handle->rxRingBufferTail = 0U; + } + else + { + handle->rxRingBufferTail++; + } + } + /* Read data. */ + handle->rxRingBuffer[handle->rxRingBufferHead] = base->FIFORD; + /* Increase handle->rxRingBufferHead. */ + if (handle->rxRingBufferHead + 1U == handle->rxRingBufferSize) + { + handle->rxRingBufferHead = 0U; + } + else + { + handle->rxRingBufferHead++; + } + } + } + } + /* Send data */ + if (sendEnabled && (base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK)) + { + base->FIFOWR = *handle->txData; + handle->txDataSize--; + handle->txData++; + sendEnabled = handle->txDataSize != 0; + if (!sendEnabled) + { + base->FIFOINTENCLR = USART_FIFOINTENCLR_TXLVL_MASK; + handle->txState = kUSART_TxIdle; + if (handle->callback) + { + handle->callback(base, handle, kStatus_USART_TxIdle, handle->userData); + } + } + } + } + + /* ring buffer is not used */ + if (NULL == handle->rxRingBuffer) + { + /* restore if rx transfer ends and rxLevel is different from default value */ + if ((handle->rxDataSize == 0) && (USART_FIFOTRIG_RXLVL_GET(base) != handle->rxWatermark)) + { + base->FIFOTRIG = + (base->FIFOTRIG & (~USART_FIFOTRIG_RXLVL_MASK)) | USART_FIFOTRIG_RXLVL(handle->rxWatermark); + } + /* decrease level if rx transfer is bellow */ + if ((handle->rxDataSize != 0) && (handle->rxDataSize < (USART_FIFOTRIG_RXLVL_GET(base) + 1))) + { + base->FIFOTRIG = + (base->FIFOTRIG & (~USART_FIFOTRIG_RXLVL_MASK)) | (USART_FIFOTRIG_RXLVL(handle->rxDataSize - 1)); + } + } +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_usart.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_usart.h new file mode 100644 index 000000000..8a6c5d4c1 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_usart.h @@ -0,0 +1,718 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_USART_H_ +#define _FSL_USART_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup usart_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief USART driver version 2.1.0. */ +#define FSL_USART_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) +/*@}*/ + +#define USART_FIFOTRIG_TXLVL_GET(base) (((base)->FIFOTRIG & USART_FIFOTRIG_TXLVL_MASK) >> USART_FIFOTRIG_TXLVL_SHIFT) +#define USART_FIFOTRIG_RXLVL_GET(base) (((base)->FIFOTRIG & USART_FIFOTRIG_RXLVL_MASK) >> USART_FIFOTRIG_RXLVL_SHIFT) + +/*! @brief Error codes for the USART driver. */ +enum _usart_status +{ + kStatus_USART_TxBusy = MAKE_STATUS(kStatusGroup_LPC_USART, 0), /*!< Transmitter is busy. */ + kStatus_USART_RxBusy = MAKE_STATUS(kStatusGroup_LPC_USART, 1), /*!< Receiver is busy. */ + kStatus_USART_TxIdle = MAKE_STATUS(kStatusGroup_LPC_USART, 2), /*!< USART transmitter is idle. */ + kStatus_USART_RxIdle = MAKE_STATUS(kStatusGroup_LPC_USART, 3), /*!< USART receiver is idle. */ + kStatus_USART_TxError = MAKE_STATUS(kStatusGroup_LPC_USART, 7), /*!< Error happens on txFIFO. */ + kStatus_USART_RxError = MAKE_STATUS(kStatusGroup_LPC_USART, 9), /*!< Error happens on rxFIFO. */ + kStatus_USART_RxRingBufferOverrun = MAKE_STATUS(kStatusGroup_LPC_USART, 8), /*!< Error happens on rx ring buffer */ + kStatus_USART_NoiseError = MAKE_STATUS(kStatusGroup_LPC_USART, 10), /*!< USART noise error. */ + kStatus_USART_FramingError = MAKE_STATUS(kStatusGroup_LPC_USART, 11), /*!< USART framing error. */ + kStatus_USART_ParityError = MAKE_STATUS(kStatusGroup_LPC_USART, 12), /*!< USART parity error. */ + kStatus_USART_BaudrateNotSupport = + MAKE_STATUS(kStatusGroup_LPC_USART, 13), /*!< Baudrate is not support in current clock source */ +}; + +/*! @brief USART synchronous mode. */ +typedef enum _usart_sync_mode +{ + kUSART_SyncModeDisabled = 0x0U, /*!< Asynchronous mode. */ + kUSART_SyncModeSlave = 0x2U, /*!< Synchronous slave mode. */ + kUSART_SyncModeMaster = 0x3U, /*!< Synchronous master mode. */ +} usart_sync_mode_t; + +/*! @brief USART parity mode. */ +typedef enum _usart_parity_mode +{ + kUSART_ParityDisabled = 0x0U, /*!< Parity disabled */ + kUSART_ParityEven = 0x2U, /*!< Parity enabled, type even, bit setting: PE|PT = 10 */ + kUSART_ParityOdd = 0x3U, /*!< Parity enabled, type odd, bit setting: PE|PT = 11 */ +} usart_parity_mode_t; + +/*! @brief USART stop bit count. */ +typedef enum _usart_stop_bit_count +{ + kUSART_OneStopBit = 0U, /*!< One stop bit */ + kUSART_TwoStopBit = 1U, /*!< Two stop bits */ +} usart_stop_bit_count_t; + +/*! @brief USART data size. */ +typedef enum _usart_data_len +{ + kUSART_7BitsPerChar = 0U, /*!< Seven bit mode */ + kUSART_8BitsPerChar = 1U, /*!< Eight bit mode */ +} usart_data_len_t; + +/*! @brief USART clock polarity configuration, used in sync mode.*/ +typedef enum _usart_clock_polarity +{ + kUSART_RxSampleOnFallingEdge = 0x0U, /*!< Un_RXD is sampled on the falling edge of SCLK. */ + kUSART_RxSampleOnRisingEdge = 0x1U, /*!< Un_RXD is sampled on the rising edge of SCLK. */ +} usart_clock_polarity_t; + +/*! @brief txFIFO watermark values */ +typedef enum _usart_txfifo_watermark +{ + kUSART_TxFifo0 = 0, /*!< USART tx watermark is empty */ + kUSART_TxFifo1 = 1, /*!< USART tx watermark at 1 item */ + kUSART_TxFifo2 = 2, /*!< USART tx watermark at 2 items */ + kUSART_TxFifo3 = 3, /*!< USART tx watermark at 3 items */ + kUSART_TxFifo4 = 4, /*!< USART tx watermark at 4 items */ + kUSART_TxFifo5 = 5, /*!< USART tx watermark at 5 items */ + kUSART_TxFifo6 = 6, /*!< USART tx watermark at 6 items */ + kUSART_TxFifo7 = 7, /*!< USART tx watermark at 7 items */ +} usart_txfifo_watermark_t; + +/*! @brief rxFIFO watermark values */ +typedef enum _usart_rxfifo_watermark +{ + kUSART_RxFifo1 = 0, /*!< USART rx watermark at 1 item */ + kUSART_RxFifo2 = 1, /*!< USART rx watermark at 2 items */ + kUSART_RxFifo3 = 2, /*!< USART rx watermark at 3 items */ + kUSART_RxFifo4 = 3, /*!< USART rx watermark at 4 items */ + kUSART_RxFifo5 = 4, /*!< USART rx watermark at 5 items */ + kUSART_RxFifo6 = 5, /*!< USART rx watermark at 6 items */ + kUSART_RxFifo7 = 6, /*!< USART rx watermark at 7 items */ + kUSART_RxFifo8 = 7, /*!< USART rx watermark at 8 items */ +} usart_rxfifo_watermark_t; + +/*! + * @brief USART interrupt configuration structure, default settings all disabled. + */ +enum _usart_interrupt_enable +{ + kUSART_TxErrorInterruptEnable = (USART_FIFOINTENSET_TXERR_MASK), + kUSART_RxErrorInterruptEnable = (USART_FIFOINTENSET_RXERR_MASK), + kUSART_TxLevelInterruptEnable = (USART_FIFOINTENSET_TXLVL_MASK), + kUSART_RxLevelInterruptEnable = (USART_FIFOINTENSET_RXLVL_MASK), +}; + +/*! + * @brief USART status flags. + * + * This provides constants for the USART status flags for use in the USART functions. + */ +enum _usart_flags +{ + kUSART_TxError = (USART_FIFOSTAT_TXERR_MASK), /*!< TEERR bit, sets if TX buffer is error */ + kUSART_RxError = (USART_FIFOSTAT_RXERR_MASK), /*!< RXERR bit, sets if RX buffer is error */ + kUSART_TxFifoEmptyFlag = (USART_FIFOSTAT_TXEMPTY_MASK), /*!< TXEMPTY bit, sets if TX buffer is empty */ + kUSART_TxFifoNotFullFlag = (USART_FIFOSTAT_TXNOTFULL_MASK), /*!< TXNOTFULL bit, sets if TX buffer is not full */ + kUSART_RxFifoNotEmptyFlag = (USART_FIFOSTAT_RXNOTEMPTY_MASK), /*!< RXNOEMPTY bit, sets if RX buffer is not empty */ + kUSART_RxFifoFullFlag = (USART_FIFOSTAT_RXFULL_MASK), /*!< RXFULL bit, sets if RX buffer is full */ +}; + +/*! @brief USART configuration structure. */ +typedef struct _usart_config +{ + uint32_t baudRate_Bps; /*!< USART baud rate */ + usart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */ + usart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits */ + usart_data_len_t bitCountPerChar; /*!< Data length - 7 bit, 8 bit */ + bool loopback; /*!< Enable peripheral loopback */ + bool enableRx; /*!< Enable RX */ + bool enableTx; /*!< Enable TX */ + bool enableContinuousSCLK; /*!< USART continuous Clock generation enable in synchronous master mode. */ + usart_txfifo_watermark_t txWatermark; /*!< txFIFO watermark */ + usart_rxfifo_watermark_t rxWatermark; /*!< rxFIFO watermark */ + usart_sync_mode_t syncMode; /*!< Transfer mode select - asynchronous, synchronous master, synchronous slave. */ + usart_clock_polarity_t clockPolarity; /*!< Selects the clock polarity and sampling edge in synchronous mode. */ +} usart_config_t; + +/*! @brief USART transfer structure. */ +typedef struct _usart_transfer +{ + uint8_t *data; /*!< The buffer of data to be transfer.*/ + size_t dataSize; /*!< The byte count to be transfer. */ +} usart_transfer_t; + +/* Forward declaration of the handle typedef. */ +typedef struct _usart_handle usart_handle_t; + +/*! @brief USART transfer callback function. */ +typedef void (*usart_transfer_callback_t)(USART_Type *base, usart_handle_t *handle, status_t status, void *userData); + +/*! @brief USART handle structure. */ +struct _usart_handle +{ + uint8_t *volatile txData; /*!< Address of remaining data to send. */ + volatile size_t txDataSize; /*!< Size of the remaining data to send. */ + size_t txDataSizeAll; /*!< Size of the data to send out. */ + uint8_t *volatile rxData; /*!< Address of remaining data to receive. */ + volatile size_t rxDataSize; /*!< Size of the remaining data to receive. */ + size_t rxDataSizeAll; /*!< Size of the data to receive. */ + + uint8_t *rxRingBuffer; /*!< Start address of the receiver ring buffer. */ + size_t rxRingBufferSize; /*!< Size of the ring buffer. */ + volatile uint16_t rxRingBufferHead; /*!< Index for the driver to store received data into ring buffer. */ + volatile uint16_t rxRingBufferTail; /*!< Index for the user to get data from the ring buffer. */ + + usart_transfer_callback_t callback; /*!< Callback function. */ + void *userData; /*!< USART callback function parameter.*/ + + volatile uint8_t txState; /*!< TX transfer state. */ + volatile uint8_t rxState; /*!< RX transfer state */ + + usart_txfifo_watermark_t txWatermark; /*!< txFIFO watermark */ + usart_rxfifo_watermark_t rxWatermark; /*!< rxFIFO watermark */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* _cplusplus */ + +/*! @brief Returns instance number for USART peripheral base address. */ +uint32_t USART_GetInstance(USART_Type *base); + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initializes a USART instance with user configuration structure and peripheral clock. + * + * This function configures the USART module with the user-defined settings. The user can configure the configuration + * structure and also get the default configuration by using the USART_GetDefaultConfig() function. + * Example below shows how to use this API to configure USART. + * @code + * usart_config_t usartConfig; + * usartConfig.baudRate_Bps = 115200U; + * usartConfig.parityMode = kUSART_ParityDisabled; + * usartConfig.stopBitCount = kUSART_OneStopBit; + * USART_Init(USART1, &usartConfig, 20000000U); + * @endcode + * + * @param base USART peripheral base address. + * @param config Pointer to user-defined configuration structure. + * @param srcClock_Hz USART clock source frequency in HZ. + * @retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. + * @retval kStatus_InvalidArgument USART base address is not valid + * @retval kStatus_Success Status USART initialize succeed + */ +status_t USART_Init(USART_Type *base, const usart_config_t *config, uint32_t srcClock_Hz); + +/*! + * @brief Deinitializes a USART instance. + * + * This function waits for TX complete, disables TX and RX, and disables the USART clock. + * + * @param base USART peripheral base address. + */ +void USART_Deinit(USART_Type *base); + +/*! + * @brief Gets the default configuration structure. + * + * This function initializes the USART configuration structure to a default value. The default + * values are: + * usartConfig->baudRate_Bps = 115200U; + * usartConfig->parityMode = kUSART_ParityDisabled; + * usartConfig->stopBitCount = kUSART_OneStopBit; + * usartConfig->bitCountPerChar = kUSART_8BitsPerChar; + * usartConfig->loopback = false; + * usartConfig->enableTx = false; + * usartConfig->enableRx = false; + * + * @param config Pointer to configuration structure. + */ +void USART_GetDefaultConfig(usart_config_t *config); + +/*! + * @brief Sets the USART instance baud rate. + * + * This function configures the USART module baud rate. This function is used to update + * the USART module baud rate after the USART module is initialized by the USART_Init. + * @code + * USART_SetBaudRate(USART1, 115200U, 20000000U); + * @endcode + * + * @param base USART peripheral base address. + * @param baudrate_Bps USART baudrate to be set. + * @param srcClock_Hz USART clock source frequency in HZ. + * @retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. + * @retval kStatus_Success Set baudrate succeed. + * @retval kStatus_InvalidArgument One or more arguments are invalid. + */ +status_t USART_SetBaudRate(USART_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz); + +/* @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Get USART status flags. + * + * This function get all USART status flags, the flags are returned as the logical + * OR value of the enumerators @ref _usart_flags. To check a specific status, + * compare the return value with enumerators in @ref _usart_flags. + * For example, to check whether the TX is empty: + * @code + * if (kUSART_TxFifoNotFullFlag & USART_GetStatusFlags(USART1)) + * { + * ... + * } + * @endcode + * + * @param base USART peripheral base address. + * @return USART status flags which are ORed by the enumerators in the _usart_flags. + */ +static inline uint32_t USART_GetStatusFlags(USART_Type *base) +{ + return base->FIFOSTAT; +} + +/*! + * @brief Clear USART status flags. + * + * This function clear supported USART status flags + * Flags that can be cleared or set are: + * kUSART_TxError + * kUSART_RxError + * For example: + * @code + * USART_ClearStatusFlags(USART1, kUSART_TxError | kUSART_RxError) + * @endcode + * + * @param base USART peripheral base address. + * @param mask status flags to be cleared. + */ +static inline void USART_ClearStatusFlags(USART_Type *base, uint32_t mask) +{ + /* Only TXERR, RXERR fields support write. Remaining fields should be set to zero */ + base->FIFOSTAT = mask & (USART_FIFOSTAT_TXERR_MASK | USART_FIFOSTAT_RXERR_MASK); +} + +/* @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables USART interrupts according to the provided mask. + * + * This function enables the USART interrupts according to the provided mask. The mask + * is a logical OR of enumeration members. See @ref _usart_interrupt_enable. + * For example, to enable TX empty interrupt and RX full interrupt: + * @code + * USART_EnableInterrupts(USART1, kUSART_TxLevelInterruptEnable | kUSART_RxLevelInterruptEnable); + * @endcode + * + * @param base USART peripheral base address. + * @param mask The interrupts to enable. Logical OR of @ref _usart_interrupt_enable. + */ +static inline void USART_EnableInterrupts(USART_Type *base, uint32_t mask) +{ + base->FIFOINTENSET = mask & 0xF; +} + +/*! + * @brief Disables USART interrupts according to a provided mask. + * + * This function disables the USART interrupts according to a provided mask. The mask + * is a logical OR of enumeration members. See @ref _usart_interrupt_enable. + * This example shows how to disable the TX empty interrupt and RX full interrupt: + * @code + * USART_DisableInterrupts(USART1, kUSART_TxLevelInterruptEnable | kUSART_RxLevelInterruptEnable); + * @endcode + * + * @param base USART peripheral base address. + * @param mask The interrupts to disable. Logical OR of @ref _usart_interrupt_enable. + */ +static inline void USART_DisableInterrupts(USART_Type *base, uint32_t mask) +{ + base->FIFOINTENCLR = mask & 0xF; +} + +/*! + * @brief Returns enabled USART interrupts. + * + * This function returns the enabled USART interrupts. + * + * @param base USART peripheral base address. + */ +static inline uint32_t USART_GetEnabledInterrupts(USART_Type *base) +{ + return base->FIFOINTENSET; +} + +/*! + * @brief Enable DMA for Tx + */ +static inline void USART_EnableTxDMA(USART_Type *base, bool enable) +{ + if (enable) + { + base->FIFOCFG |= USART_FIFOCFG_DMATX_MASK; + } + else + { + base->FIFOCFG &= ~(USART_FIFOCFG_DMATX_MASK); + } +} + +/*! + * @brief Enable DMA for Rx + */ +static inline void USART_EnableRxDMA(USART_Type *base, bool enable) +{ + if (enable) + { + base->FIFOCFG |= USART_FIFOCFG_DMARX_MASK; + } + else + { + base->FIFOCFG &= ~(USART_FIFOCFG_DMARX_MASK); + } +} + +/*! + * @brief Enable CTS. + * This function will determine whether CTS is used for flow control. + * + * @param base USART peripheral base address. + * @param enable Enable CTS or not, true for enable and false for disable. + */ +static inline void USART_EnableCTS(USART_Type *base, bool enable) +{ + if (enable) + { + base->CFG |= USART_CFG_CTSEN_MASK; + } + else + { + base->CFG &= ~USART_CFG_CTSEN_MASK; + } +} + +/*! + * @brief Continuous Clock generation. + * By default, SCLK is only output while data is being transmitted in synchronous mode. + * Enable this funciton, SCLK will run continuously in synchronous mode, allowing + * characters to be received on Un_RxD independently from transmission on Un_TXD). + * + * @param base USART peripheral base address. + * @param enable Enable Continuous Clock generation mode or not, true for enable and false for disable. + */ +static inline void USART_EnableContinuousSCLK(USART_Type *base, bool enable) +{ + if (enable) + { + base->CTL |= USART_CTL_CC_MASK; + } + else + { + base->CTL &= ~USART_CTL_CC_MASK; + } +} + +/*! + * @brief Enable Continuous Clock generation bit auto clear. + * While enable this cuntion, the Continuous Clock bit is automatically cleared when a complete + * character has been received. This bit is cleared at the same time. + * + * @param base USART peripheral base address. + * @param enable Enable auto clear or not, true for enable and false for disable. + */ +static inline void USART_EnableAutoClearSCLK(USART_Type *base, bool enable) +{ + if (enable) + { + base->CTL |= USART_CTL_CLRCCONRX_MASK; + } + else + { + base->CTL &= ~USART_CTL_CLRCCONRX_MASK; + } +} +/* @} */ + +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Writes to the FIFOWR register. + * + * This function writes data to the txFIFO directly. The upper layer must ensure + * that txFIFO has space for data to write before calling this function. + * + * @param base USART peripheral base address. + * @param data The byte to write. + */ +static inline void USART_WriteByte(USART_Type *base, uint8_t data) +{ + base->FIFOWR = data; +} + +/*! + * @brief Reads the FIFORD register directly. + * + * This function reads data from the rxFIFO directly. The upper layer must + * ensure that the rxFIFO is not empty before calling this function. + * + * @param base USART peripheral base address. + * @return The byte read from USART data register. + */ +static inline uint8_t USART_ReadByte(USART_Type *base) +{ + return base->FIFORD; +} + +/*! + * @brief Writes to the TX register using a blocking method. + * + * This function polls the TX register, waits for the TX register to be empty or for the TX FIFO + * to have room and writes data to the TX buffer. + * + * @param base USART peripheral base address. + * @param data Start address of the data to write. + * @param length Size of the data to write. + */ +void USART_WriteBlocking(USART_Type *base, const uint8_t *data, size_t length); + +/*! + * @brief Read RX data register using a blocking method. + * + * This function polls the RX register, waits for the RX register to be full or for RX FIFO to + * have data and read data from the TX register. + * + * @param base USART peripheral base address. + * @param data Start address of the buffer to store the received data. + * @param length Size of the buffer. + * @retval kStatus_USART_FramingError Receiver overrun happened while receiving data. + * @retval kStatus_USART_ParityError Noise error happened while receiving data. + * @retval kStatus_USART_NoiseError Framing error happened while receiving data. + * @retval kStatus_USART_RxError Overflow or underflow rxFIFO happened. + * @retval kStatus_Success Successfully received all data. + */ +status_t USART_ReadBlocking(USART_Type *base, uint8_t *data, size_t length); + +/* @} */ + +/*! + * @name Transactional + * @{ + */ + +/*! + * @brief Initializes the USART handle. + * + * This function initializes the USART handle which can be used for other USART + * transactional APIs. Usually, for a specified USART instance, + * call this API once to get the initialized handle. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + * @param callback The callback function. + * @param userData The parameter of the callback function. + */ +status_t USART_TransferCreateHandle(USART_Type *base, + usart_handle_t *handle, + usart_transfer_callback_t callback, + void *userData); + +/*! + * @brief Transmits a buffer of data using the interrupt method. + * + * This function sends data using an interrupt method. This is a non-blocking function, which + * returns directly without waiting for all data to be written to the TX register. When + * all data is written to the TX register in the IRQ handler, the USART driver calls the callback + * function and passes the @ref kStatus_USART_TxIdle as status parameter. + * + * @note The kStatus_USART_TxIdle is passed to the upper layer when all data is written + * to the TX register. However it does not ensure that all data are sent out. Before disabling the TX, + * check the kUSART_TransmissionCompleteFlag to ensure that the TX is finished. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + * @param xfer USART transfer structure. See #usart_transfer_t. + * @retval kStatus_Success Successfully start the data transmission. + * @retval kStatus_USART_TxBusy Previous transmission still not finished, data not all written to TX register yet. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t USART_TransferSendNonBlocking(USART_Type *base, usart_handle_t *handle, usart_transfer_t *xfer); + +/*! + * @brief Sets up the RX ring buffer. + * + * This function sets up the RX ring buffer to a specific USART handle. + * + * When the RX ring buffer is used, data received are stored into the ring buffer even when the + * user doesn't call the USART_TransferReceiveNonBlocking() API. If there is already data received + * in the ring buffer, the user can get the received data from the ring buffer directly. + * + * @note When using the RX ring buffer, one byte is reserved for internal use. In other + * words, if @p ringBufferSize is 32, then only 31 bytes are used for saving data. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + * @param ringBuffer Start address of the ring buffer for background receiving. Pass NULL to disable the ring buffer. + * @param ringBufferSize size of the ring buffer. + */ +void USART_TransferStartRingBuffer(USART_Type *base, + usart_handle_t *handle, + uint8_t *ringBuffer, + size_t ringBufferSize); + +/*! + * @brief Aborts the background transfer and uninstalls the ring buffer. + * + * This function aborts the background transfer and uninstalls the ring buffer. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + */ +void USART_TransferStopRingBuffer(USART_Type *base, usart_handle_t *handle); + +/*! + * @brief Get the length of received data in RX ring buffer. + * + * @param handle USART handle pointer. + * @return Length of received data in RX ring buffer. + */ +size_t USART_TransferGetRxRingBufferLength(usart_handle_t *handle); + +/*! + * @brief Aborts the interrupt-driven data transmit. + * + * This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out + * how many bytes are still not sent out. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + */ +void USART_TransferAbortSend(USART_Type *base, usart_handle_t *handle); + +/*! + * @brief Get the number of bytes that have been written to USART TX register. + * + * This function gets the number of bytes that have been written to USART TX + * register by interrupt method. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + * @param count Send bytes count. + * @retval kStatus_NoTransferInProgress No send in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t USART_TransferGetSendCount(USART_Type *base, usart_handle_t *handle, uint32_t *count); + +/*! + * @brief Receives a buffer of data using an interrupt method. + * + * This function receives data using an interrupt method. This is a non-blocking function, which + * returns without waiting for all data to be received. + * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and + * the parameter @p receivedBytes shows how many bytes are copied from the ring buffer. + * After copying, if the data in the ring buffer is not enough to read, the receive + * request is saved by the USART driver. When the new data arrives, the receive request + * is serviced first. When all data is received, the USART driver notifies the upper layer + * through a callback function and passes the status parameter @ref kStatus_USART_RxIdle. + * For example, the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer. + * The 5 bytes are copied to the xfer->data and this function returns with the + * parameter @p receivedBytes set to 5. For the left 5 bytes, newly arrived data is + * saved from the xfer->data[5]. When 5 bytes are received, the USART driver notifies the upper layer. + * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt + * to receive data to the xfer->data. When all data is received, the upper layer is notified. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + * @param xfer USART transfer structure, see #usart_transfer_t. + * @param receivedBytes Bytes received from the ring buffer directly. + * @retval kStatus_Success Successfully queue the transfer into transmit queue. + * @retval kStatus_USART_RxBusy Previous receive request is not finished. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t USART_TransferReceiveNonBlocking(USART_Type *base, + usart_handle_t *handle, + usart_transfer_t *xfer, + size_t *receivedBytes); + +/*! + * @brief Aborts the interrupt-driven data receiving. + * + * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out + * how many bytes not received yet. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + */ +void USART_TransferAbortReceive(USART_Type *base, usart_handle_t *handle); + +/*! + * @brief Get the number of bytes that have been received. + * + * This function gets the number of bytes that have been received. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + * @param count Receive bytes count. + * @retval kStatus_NoTransferInProgress No receive in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t USART_TransferGetReceiveCount(USART_Type *base, usart_handle_t *handle, uint32_t *count); + +/*! + * @brief USART IRQ handle function. + * + * This function handles the USART transmit and receive IRQ request. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + */ +void USART_TransferHandleIRQ(USART_Type *base, usart_handle_t *handle); + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_USART_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_usart_dma.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_usart_dma.c new file mode 100644 index 000000000..82c969f81 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_usart_dma.c @@ -0,0 +1,307 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_usart.h" +#include "fsl_device_registers.h" +#include "fsl_dma.h" +#include "fsl_flexcomm.h" +#include "fsl_usart_dma.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexcomm_usart_dma" +#endif + +/*base, false); + + usartPrivateHandle->handle->txState = kUSART_TxIdle; + + if (usartPrivateHandle->handle->callback) + { + usartPrivateHandle->handle->callback(usartPrivateHandle->base, usartPrivateHandle->handle, kStatus_USART_TxIdle, + usartPrivateHandle->handle->userData); + } +} + +static void USART_TransferReceiveDMACallback(dma_handle_t *handle, void *param, bool transferDone, uint32_t intmode) +{ + assert(handle); + assert(param); + + usart_dma_private_handle_t *usartPrivateHandle = (usart_dma_private_handle_t *)param; + + /* Disable UART RX DMA. */ + USART_EnableRxDMA(usartPrivateHandle->base, false); + + usartPrivateHandle->handle->rxState = kUSART_RxIdle; + + if (usartPrivateHandle->handle->callback) + { + usartPrivateHandle->handle->callback(usartPrivateHandle->base, usartPrivateHandle->handle, kStatus_USART_RxIdle, + usartPrivateHandle->handle->userData); + } +} + +/*! + * brief Initializes the USART handle which is used in transactional functions. + * param base USART peripheral base address. + * param handle Pointer to usart_dma_handle_t structure. + * param callback Callback function. + * param userData User data. + * param txDmaHandle User-requested DMA handle for TX DMA transfer. + * param rxDmaHandle User-requested DMA handle for RX DMA transfer. + */ +status_t USART_TransferCreateHandleDMA(USART_Type *base, + usart_dma_handle_t *handle, + usart_dma_transfer_callback_t callback, + void *userData, + dma_handle_t *txDmaHandle, + dma_handle_t *rxDmaHandle) +{ + int32_t instance = 0; + + /* check 'base' */ + assert(!(NULL == base)); + if (NULL == base) + { + return kStatus_InvalidArgument; + } + /* check 'handle' */ + assert(!(NULL == handle)); + if (NULL == handle) + { + return kStatus_InvalidArgument; + } + + instance = USART_GetInstance(base); + + memset(handle, 0, sizeof(*handle)); + /* assign 'base' and 'handle' */ + s_dmaPrivateHandle[instance].base = base; + s_dmaPrivateHandle[instance].handle = handle; + + /* set tx/rx 'idle' state */ + handle->rxState = kUSART_RxIdle; + handle->txState = kUSART_TxIdle; + + handle->callback = callback; + handle->userData = userData; + + handle->rxDmaHandle = rxDmaHandle; + handle->txDmaHandle = txDmaHandle; + + /* Configure TX. */ + if (txDmaHandle) + { + DMA_SetCallback(txDmaHandle, USART_TransferSendDMACallback, &s_dmaPrivateHandle[instance]); + } + + /* Configure RX. */ + if (rxDmaHandle) + { + DMA_SetCallback(rxDmaHandle, USART_TransferReceiveDMACallback, &s_dmaPrivateHandle[instance]); + } + + return kStatus_Success; +} + +/*! + * brief Sends data using DMA. + * + * This function sends data using DMA. This is a non-blocking function, which returns + * right away. When all data is sent, the send callback function is called. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + * param xfer USART DMA transfer structure. See #usart_transfer_t. + * retval kStatus_Success if succeed, others failed. + * retval kStatus_USART_TxBusy Previous transfer on going. + * retval kStatus_InvalidArgument Invalid argument. + */ +status_t USART_TransferSendDMA(USART_Type *base, usart_dma_handle_t *handle, usart_transfer_t *xfer) +{ + assert(handle); + assert(handle->txDmaHandle); + assert(xfer); + assert(xfer->data); + assert(xfer->dataSize); + + dma_transfer_config_t xferConfig; + status_t status; + + /* If previous TX not finished. */ + if (kUSART_TxBusy == handle->txState) + { + status = kStatus_USART_TxBusy; + } + else + { + handle->txState = kUSART_TxBusy; + handle->txDataSizeAll = xfer->dataSize; + + /* Enable DMA request from txFIFO */ + USART_EnableTxDMA(base, true); + + /* Prepare transfer. */ + DMA_PrepareTransfer(&xferConfig, xfer->data, ((void *)((uint32_t)&base->FIFOWR)), sizeof(uint8_t), + xfer->dataSize, kDMA_MemoryToPeripheral, NULL); + + /* Submit transfer. */ + DMA_SubmitTransfer(handle->txDmaHandle, &xferConfig); + DMA_StartTransfer(handle->txDmaHandle); + + status = kStatus_Success; + } + + return status; +} + +/*! + * brief Receives data using DMA. + * + * This function receives data using DMA. This is a non-blocking function, which returns + * right away. When all data is received, the receive callback function is called. + * + * param base USART peripheral base address. + * param handle Pointer to usart_dma_handle_t structure. + * param xfer USART DMA transfer structure. See #usart_transfer_t. + * retval kStatus_Success if succeed, others failed. + * retval kStatus_USART_RxBusy Previous transfer on going. + * retval kStatus_InvalidArgument Invalid argument. + */ +status_t USART_TransferReceiveDMA(USART_Type *base, usart_dma_handle_t *handle, usart_transfer_t *xfer) +{ + assert(handle); + assert(handle->rxDmaHandle); + assert(xfer); + assert(xfer->data); + assert(xfer->dataSize); + + dma_transfer_config_t xferConfig; + status_t status; + + /* If previous RX not finished. */ + if (kUSART_RxBusy == handle->rxState) + { + status = kStatus_USART_RxBusy; + } + else + { + handle->rxState = kUSART_RxBusy; + handle->rxDataSizeAll = xfer->dataSize; + + /* Enable DMA request from rxFIFO */ + USART_EnableRxDMA(base, true); + + /* Prepare transfer. */ + DMA_PrepareTransfer(&xferConfig, ((void *)((uint32_t)&base->FIFORD)), xfer->data, sizeof(uint8_t), + xfer->dataSize, kDMA_PeripheralToMemory, NULL); + + /* Submit transfer. */ + DMA_SubmitTransfer(handle->rxDmaHandle, &xferConfig); + DMA_StartTransfer(handle->rxDmaHandle); + + status = kStatus_Success; + } + + return status; +} + +/*! + * brief Aborts the sent data using DMA. + * + * This function aborts send data using DMA. + * + * param base USART peripheral base address + * param handle Pointer to usart_dma_handle_t structure + */ +void USART_TransferAbortSendDMA(USART_Type *base, usart_dma_handle_t *handle) +{ + assert(NULL != handle); + assert(NULL != handle->txDmaHandle); + + /* Stop transfer. */ + DMA_AbortTransfer(handle->txDmaHandle); + handle->txState = kUSART_TxIdle; +} + +/*! + * brief Aborts the received data using DMA. + * + * This function aborts the received data using DMA. + * + * param base USART peripheral base address + * param handle Pointer to usart_dma_handle_t structure + */ +void USART_TransferAbortReceiveDMA(USART_Type *base, usart_dma_handle_t *handle) +{ + assert(NULL != handle); + assert(NULL != handle->rxDmaHandle); + + /* Stop transfer. */ + DMA_AbortTransfer(handle->rxDmaHandle); + handle->rxState = kUSART_RxIdle; +} + +/*! + * brief Get the number of bytes that have been received. + * + * This function gets the number of bytes that have been received. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + * param count Receive bytes count. + * retval kStatus_NoTransferInProgress No receive in progress. + * retval kStatus_InvalidArgument Parameter is invalid. + * retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t USART_TransferGetReceiveCountDMA(USART_Type *base, usart_dma_handle_t *handle, uint32_t *count) +{ + assert(handle); + assert(handle->rxDmaHandle); + assert(count); + + if (kUSART_RxIdle == handle->rxState) + { + return kStatus_NoTransferInProgress; + } + + *count = handle->rxDataSizeAll - DMA_GetRemainingBytes(handle->rxDmaHandle->base, handle->rxDmaHandle->channel); + + return kStatus_Success; +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_usart_dma.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_usart_dma.h new file mode 100644 index 000000000..e2ee65798 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_usart_dma.h @@ -0,0 +1,161 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_USART_DMA_H_ +#define _FSL_USART_DMA_H_ + +#include "fsl_common.h" +#include "fsl_dma.h" +#include "fsl_usart.h" + +/*! + * @addtogroup usart_dma_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief USART dma driver version 2.0.1. */ +#define FSL_USART_DMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/* Forward declaration of the handle typedef. */ +typedef struct _usart_dma_handle usart_dma_handle_t; + +/*! @brief UART transfer callback function. */ +typedef void (*usart_dma_transfer_callback_t)(USART_Type *base, + usart_dma_handle_t *handle, + status_t status, + void *userData); + +/*! + * @brief UART DMA handle + */ +struct _usart_dma_handle +{ + USART_Type *base; /*!< UART peripheral base address. */ + + usart_dma_transfer_callback_t callback; /*!< Callback function. */ + void *userData; /*!< UART callback function parameter.*/ + size_t rxDataSizeAll; /*!< Size of the data to receive. */ + size_t txDataSizeAll; /*!< Size of the data to send out. */ + + dma_handle_t *txDmaHandle; /*!< The DMA TX channel used. */ + dma_handle_t *rxDmaHandle; /*!< The DMA RX channel used. */ + + volatile uint8_t txState; /*!< TX transfer state. */ + volatile uint8_t rxState; /*!< RX transfer state */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* _cplusplus */ + +/*! + * @name DMA transactional + * @{ + */ + +/*! + * @brief Initializes the USART handle which is used in transactional functions. + * @param base USART peripheral base address. + * @param handle Pointer to usart_dma_handle_t structure. + * @param callback Callback function. + * @param userData User data. + * @param txDmaHandle User-requested DMA handle for TX DMA transfer. + * @param rxDmaHandle User-requested DMA handle for RX DMA transfer. + */ +status_t USART_TransferCreateHandleDMA(USART_Type *base, + usart_dma_handle_t *handle, + usart_dma_transfer_callback_t callback, + void *userData, + dma_handle_t *txDmaHandle, + dma_handle_t *rxDmaHandle); + +/*! + * @brief Sends data using DMA. + * + * This function sends data using DMA. This is a non-blocking function, which returns + * right away. When all data is sent, the send callback function is called. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + * @param xfer USART DMA transfer structure. See #usart_transfer_t. + * @retval kStatus_Success if succeed, others failed. + * @retval kStatus_USART_TxBusy Previous transfer on going. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t USART_TransferSendDMA(USART_Type *base, usart_dma_handle_t *handle, usart_transfer_t *xfer); + +/*! + * @brief Receives data using DMA. + * + * This function receives data using DMA. This is a non-blocking function, which returns + * right away. When all data is received, the receive callback function is called. + * + * @param base USART peripheral base address. + * @param handle Pointer to usart_dma_handle_t structure. + * @param xfer USART DMA transfer structure. See #usart_transfer_t. + * @retval kStatus_Success if succeed, others failed. + * @retval kStatus_USART_RxBusy Previous transfer on going. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t USART_TransferReceiveDMA(USART_Type *base, usart_dma_handle_t *handle, usart_transfer_t *xfer); + +/*! + * @brief Aborts the sent data using DMA. + * + * This function aborts send data using DMA. + * + * @param base USART peripheral base address + * @param handle Pointer to usart_dma_handle_t structure + */ +void USART_TransferAbortSendDMA(USART_Type *base, usart_dma_handle_t *handle); + +/*! + * @brief Aborts the received data using DMA. + * + * This function aborts the received data using DMA. + * + * @param base USART peripheral base address + * @param handle Pointer to usart_dma_handle_t structure + */ +void USART_TransferAbortReceiveDMA(USART_Type *base, usart_dma_handle_t *handle); + +/*! + * @brief Get the number of bytes that have been received. + * + * This function gets the number of bytes that have been received. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + * @param count Receive bytes count. + * @retval kStatus_NoTransferInProgress No receive in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t USART_TransferGetReceiveCountDMA(USART_Type *base, usart_dma_handle_t *handle, uint32_t *count); + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_USART_DMA_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_utick.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_utick.c new file mode 100644 index 000000000..8014834d8 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_utick.c @@ -0,0 +1,220 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_utick.h" +#include "fsl_power.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.utick" +#endif + +/* Typedef for interrupt handler. */ +typedef void (*utick_isr_t)(UTICK_Type *base, utick_callback_t cb); + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Gets the instance from the base address + * + * @param base UTICK peripheral base address + * + * @return The UTICK instance + */ +static uint32_t UTICK_GetInstance(UTICK_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* Array of UTICK handle. */ +static utick_callback_t s_utickHandle[FSL_FEATURE_SOC_UTICK_COUNT]; +/* Array of UTICK peripheral base address. */ +static UTICK_Type *const s_utickBases[] = UTICK_BASE_PTRS; +/* Array of UTICK IRQ number. */ +static const IRQn_Type s_utickIRQ[] = UTICK_IRQS; +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/* Array of UTICK clock name. */ +static const clock_ip_name_t s_utickClock[] = UTICK_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_FEATURE_UTICK_HAS_NO_RESET) && FSL_FEATURE_UTICK_HAS_NO_RESET) +/*! @brief Pointers to UTICK resets for each instance. */ +static const reset_ip_name_t s_utickResets[] = UTICK_RSTS; +#endif + +/* UTICK ISR for transactional APIs. */ +static utick_isr_t s_utickIsr; + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t UTICK_GetInstance(UTICK_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_utickBases); instance++) + { + if (s_utickBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_utickBases)); + + return instance; +} + +/*! + * brief Starts UTICK. + * + * This function starts a repeat/onetime countdown with an optional callback + * + * param base UTICK peripheral base address. + * param mode UTICK timer mode (ie kUTICK_onetime or kUTICK_repeat) + * param count UTICK timer mode (ie kUTICK_onetime or kUTICK_repeat) + * param cb UTICK callback (can be left as NULL if none, otherwise should be a void func(void)) + * return none + */ +void UTICK_SetTick(UTICK_Type *base, utick_mode_t mode, uint32_t count, utick_callback_t cb) +{ + uint32_t instance; + + /* Get instance from peripheral base address. */ + instance = UTICK_GetInstance(base); + + /* Save the handle in global variables to support the double weak mechanism. */ + s_utickHandle[instance] = cb; + EnableDeepSleepIRQ(s_utickIRQ[instance]); + base->CTRL = count | UTICK_CTRL_REPEAT(mode); +} + +/*! + * brief Initializes an UTICK by turning its bus clock on + * + */ +void UTICK_Init(UTICK_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable utick clock */ + CLOCK_EnableClock(s_utickClock[UTICK_GetInstance(base)]); +#endif + +#if !(defined(FSL_FEATURE_UTICK_HAS_NO_RESET) && FSL_FEATURE_UTICK_HAS_NO_RESET) + RESET_PeripheralReset(s_utickResets[UTICK_GetInstance(base)]); +#endif + +#if !(defined(FSL_FEATURE_UTICK_HAS_NO_PDCFG) && FSL_FEATURE_UTICK_HAS_NO_PDCFG) + /* Power up Watchdog oscillator*/ + POWER_DisablePD(kPDRUNCFG_PD_WDT_OSC); +#endif + + s_utickIsr = UTICK_HandleIRQ; +} + +/*! + * brief Deinitializes a UTICK instance. + * + * This function shuts down Utick bus clock + * + * param base UTICK peripheral base address. + */ +void UTICK_Deinit(UTICK_Type *base) +{ + /* Turn off utick */ + base->CTRL = 0; +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable utick clock */ + CLOCK_DisableClock(s_utickClock[UTICK_GetInstance(base)]); +#endif +} + +/*! + * brief Get Status Flags. + * + * This returns the status flag + * + * param base UTICK peripheral base address. + * return status register value + */ +uint32_t UTICK_GetStatusFlags(UTICK_Type *base) +{ + return (base->STAT); +} + +/*! + * brief Clear Status Interrupt Flags. + * + * This clears intr status flag + * + * param base UTICK peripheral base address. + * return none + */ +void UTICK_ClearStatusFlags(UTICK_Type *base) +{ + base->STAT = UTICK_STAT_INTR_MASK; +} + +/*! + * brief UTICK Interrupt Service Handler. + * + * This function handles the interrupt and refers to the callback array in the driver to callback user (as per request + * in UTICK_SetTick()). + * if no user callback is scheduled, the interrupt will simply be cleared. + * + * param base UTICK peripheral base address. + * param cb callback scheduled for this instance of UTICK + * return none + */ +void UTICK_HandleIRQ(UTICK_Type *base, utick_callback_t cb) +{ + UTICK_ClearStatusFlags(base); + if (cb) + { + cb(); + } +} + +#if defined(UTICK0) +void UTICK0_DriverIRQHandler(void) +{ + s_utickIsr(UTICK0, s_utickHandle[0]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif +#if defined(UTICK1) +void UTICK1_DriverIRQHandler(void) +{ + s_utickIsr(UTICK1, s_utickHandle[1]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif +#if defined(UTICK2) +void UTICK2_DriverIRQHandler(void) +{ + s_utickIsr(UTICK2, s_utickHandle[2]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_utick.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_utick.h new file mode 100644 index 000000000..7db3ca415 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_utick.h @@ -0,0 +1,118 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_UTICK_H_ +#define _FSL_UTICK_H_ + +#include "fsl_common.h" +/*! + * @addtogroup utick + * @{ + */ + +/*! @file*/ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief UTICK driver version 2.0.2. */ +#define FSL_UTICK_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) +/*@}*/ + +/*! @brief UTICK timer operational mode. */ +typedef enum _utick_mode +{ + kUTICK_Onetime = 0x0U, /*!< Trigger once*/ + kUTICK_Repeat = 0x1U, /*!< Trigger repeatedly */ +} utick_mode_t; + +/*! @brief UTICK callback function. */ +typedef void (*utick_callback_t)(void); + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* _cplusplus */ + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initializes an UTICK by turning its bus clock on + * + */ +void UTICK_Init(UTICK_Type *base); + +/*! + * @brief Deinitializes a UTICK instance. + * + * This function shuts down Utick bus clock + * + * @param base UTICK peripheral base address. + */ +void UTICK_Deinit(UTICK_Type *base); +/*! + * @brief Get Status Flags. + * + * This returns the status flag + * + * @param base UTICK peripheral base address. + * @return status register value + */ +uint32_t UTICK_GetStatusFlags(UTICK_Type *base); +/*! + * @brief Clear Status Interrupt Flags. + * + * This clears intr status flag + * + * @param base UTICK peripheral base address. + * @return none + */ +void UTICK_ClearStatusFlags(UTICK_Type *base); + +/*! + * @brief Starts UTICK. + * + * This function starts a repeat/onetime countdown with an optional callback + * + * @param base UTICK peripheral base address. + * @param mode UTICK timer mode (ie kUTICK_onetime or kUTICK_repeat) + * @param count UTICK timer mode (ie kUTICK_onetime or kUTICK_repeat) + * @param cb UTICK callback (can be left as NULL if none, otherwise should be a void func(void)) + * @return none + */ +void UTICK_SetTick(UTICK_Type *base, utick_mode_t mode, uint32_t count, utick_callback_t cb); +/*! + * @brief UTICK Interrupt Service Handler. + * + * This function handles the interrupt and refers to the callback array in the driver to callback user (as per request + * in UTICK_SetTick()). + * if no user callback is scheduled, the interrupt will simply be cleared. + * + * @param base UTICK peripheral base address. + * @param cb callback scheduled for this instance of UTICK + * @return none + */ +void UTICK_HandleIRQ(UTICK_Type *base, utick_callback_t cb); + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_UTICK_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_wwdt.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_wwdt.c new file mode 100644 index 000000000..6b510371a --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_wwdt.c @@ -0,0 +1,250 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_wwdt.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.wwdt" +#endif + +#define FREQUENCY_3MHZ (3000000U) +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Gets the instance from the base address + * + * @param base WWDT peripheral base address + * + * @return The WWDT instance + */ +static uint32_t WWDT_GetInstance(WWDT_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to WWDT bases for each instance. */ +static WWDT_Type *const s_wwdtBases[] = WWDT_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to WWDT clocks for each instance. */ +static const clock_ip_name_t s_wwdtClocks[] = WWDT_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) +#if !(defined(FSL_FEATURE_WWDT_HAS_NO_RESET) && FSL_FEATURE_WWDT_HAS_NO_RESET) +/*! @brief Pointers to WWDT resets for each instance. */ +static const reset_ip_name_t s_wwdtResets[] = WWDT_RSTS; +#endif +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t WWDT_GetInstance(WWDT_Type *base) +{ + uint32_t instance; + uint32_t wwdtArrayCount = (sizeof(s_wwdtBases) / sizeof(s_wwdtBases[0])); + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < wwdtArrayCount; instance++) + { + if (s_wwdtBases[instance] == base) + { + break; + } + } + + assert(instance < wwdtArrayCount); + + return instance; +} + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * brief Initializes WWDT configure structure. + * + * This function initializes the WWDT configure structure to default value. The default + * value are: + * code + * config->enableWwdt = true; + * config->enableWatchdogReset = false; + * config->enableWatchdogProtect = false; + * config->enableLockOscillator = false; + * config->windowValue = 0xFFFFFFU; + * config->timeoutValue = 0xFFFFFFU; + * config->warningValue = 0; + * endcode + * + * param config Pointer to WWDT config structure. + * see wwdt_config_t + */ +void WWDT_GetDefaultConfig(wwdt_config_t *config) +{ + assert(config); + + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + + /* Enable the watch dog */ + config->enableWwdt = true; + /* Disable the watchdog timeout reset */ + config->enableWatchdogReset = false; + /* Disable the watchdog protection for updating the timeout value */ + config->enableWatchdogProtect = false; +#if !(defined(FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK) && FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK) + /* Do not lock the watchdog oscillator */ + config->enableLockOscillator = false; +#endif + /* Windowing is not in effect */ + config->windowValue = 0xFFFFFFU; + /* Set the timeout value to the max */ + config->timeoutValue = 0xFFFFFFU; + /* No warning is provided */ + config->warningValue = 0; + /* Set clock frequency. */ + config->clockFreq_Hz = 0U; +} + +/*! + * brief Initializes the WWDT. + * + * This function initializes the WWDT. When called, the WWDT runs according to the configuration. + * + * Example: + * code + * wwdt_config_t config; + * WWDT_GetDefaultConfig(&config); + * config.timeoutValue = 0x7ffU; + * WWDT_Init(wwdt_base,&config); + * endcode + * + * param base WWDT peripheral base address + * param config The configuration of WWDT + */ +void WWDT_Init(WWDT_Type *base, const wwdt_config_t *config) +{ + assert(config); + /* The config->clockFreq_Hz must be set in order to config the delay time. */ + assert(config->clockFreq_Hz); + + uint32_t value = 0U; + uint32_t DelayUs = 0U; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the WWDT clock */ + CLOCK_EnableClock(s_wwdtClocks[WWDT_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) +#if !(defined(FSL_FEATURE_WWDT_HAS_NO_RESET) && FSL_FEATURE_WWDT_HAS_NO_RESET) + /* Reset the module. */ + RESET_PeripheralReset(s_wwdtResets[WWDT_GetInstance(base)]); +#endif +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + +#if !(defined(FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK) && FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK) + value = WWDT_MOD_WDEN(config->enableWwdt) | WWDT_MOD_WDRESET(config->enableWatchdogReset) | + WWDT_MOD_LOCK(config->enableLockOscillator); +#else + value = WWDT_MOD_WDEN(config->enableWwdt) | WWDT_MOD_WDRESET(config->enableWatchdogReset); +#endif + /* Set configuration */ + base->TC = WWDT_TC_COUNT(config->timeoutValue); + base->MOD |= value; + base->WINDOW = WWDT_WINDOW_WINDOW(config->windowValue); + base->WARNINT = WWDT_WARNINT_WARNINT(config->warningValue); + WWDT_Refresh(base); + /* This WDPROTECT bit can be set once by software and is only cleared by a reset */ + if ((base->MOD & WWDT_MOD_WDPROTECT_MASK) == 0U) + { + /* Set the WDPROTECT bit after the Feed Sequence (0xAA, 0x55) with 3 WDCLK delay */ + DelayUs = FREQUENCY_3MHZ / config->clockFreq_Hz + 1U; + SDK_DelayAtLeastUs(DelayUs); + + base->MOD |= WWDT_MOD_WDPROTECT(config->enableWatchdogProtect); + } +} + +/*! + * brief Shuts down the WWDT. + * + * This function shuts down the WWDT. + * + * param base WWDT peripheral base address + */ +void WWDT_Deinit(WWDT_Type *base) +{ + WWDT_Disable(base); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable the WWDT clock */ + CLOCK_DisableClock(s_wwdtClocks[WWDT_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Refreshes the WWDT timer. + * + * This function feeds the WWDT. + * This function should be called before WWDT timer is in timeout. Otherwise, a reset is asserted. + * + * param base WWDT peripheral base address + */ +void WWDT_Refresh(WWDT_Type *base) +{ + uint32_t primaskValue = 0U; + + /* Disable the global interrupt to protect refresh sequence */ + primaskValue = DisableGlobalIRQ(); + base->FEED = WWDT_FIRST_WORD_OF_REFRESH; + base->FEED = WWDT_SECOND_WORD_OF_REFRESH; + EnableGlobalIRQ(primaskValue); +} + +/*! + * brief Clear WWDT flag. + * + * This function clears WWDT status flag. + * + * Example for clearing warning flag: + * code + * WWDT_ClearStatusFlags(wwdt_base, kWWDT_WarningFlag); + * endcode + * param base WWDT peripheral base address + * param mask The status flags to clear. This is a logical OR of members of the + * enumeration ::_wwdt_status_flags_t + */ +void WWDT_ClearStatusFlags(WWDT_Type *base, uint32_t mask) +{ + /* Clear the WDINT bit so that we don't accidentally clear it */ + uint32_t reg = (base->MOD & (~WWDT_MOD_WDINT_MASK)); + + /* Clear timeout by writing a zero */ + if (mask & kWWDT_TimeoutFlag) + { + reg &= ~WWDT_MOD_WDTOF_MASK; +#if defined(FSL_FEATURE_WWDT_WDTRESET_FROM_PMC) && (FSL_FEATURE_WWDT_WDTRESET_FROM_PMC) + /* PMC RESETCAUSE: set bit to clear it */ + PMC->RESETCAUSE |= PMC_RESETCAUSE_WDTRESET_MASK; +#endif /*FSL_FEATURE_WWDT_WDTRESET_FROM_PMC*/ + } + + /* Clear warning interrupt flag by writing a one */ + if (mask & kWWDT_WarningFlag) + { + reg |= WWDT_MOD_WDINT_MASK; + } + + base->MOD = reg; +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_wwdt.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_wwdt.h new file mode 100644 index 000000000..7cccdf41d --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_wwdt.h @@ -0,0 +1,274 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_WWDT_H_ +#define _FSL_WWDT_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup wwdt + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + *******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief Defines WWDT driver version 2.1.2. */ +#define FSL_WWDT_DRIVER_VERSION (MAKE_VERSION(2, 1, 2)) +/*@}*/ + +/*! @name Refresh sequence */ +/*@{*/ +#define WWDT_FIRST_WORD_OF_REFRESH (0xAAU) /*!< First word of refresh sequence */ +#define WWDT_SECOND_WORD_OF_REFRESH (0x55U) /*!< Second word of refresh sequence */ +/*@}*/ + +/*! @brief Describes WWDT configuration structure. */ +typedef struct _wwdt_config +{ + bool enableWwdt; /*!< Enables or disables WWDT */ + bool enableWatchdogReset; /*!< true: Watchdog timeout will cause a chip reset + false: Watchdog timeout will not cause a chip reset */ + bool enableWatchdogProtect; /*!< true: Enable watchdog protect i.e timeout value can only be + changed after counter is below warning & window values + false: Disable watchdog protect; timeout value can be changed + at any time */ +#if !(defined(FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK) && FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK) + bool enableLockOscillator; /*!< true: Disabling or powering down the watchdog oscillator is prevented + Once set, this bit can only be cleared by a reset + false: Do not lock oscillator */ +#endif + uint32_t windowValue; /*!< Window value, set this to 0xFFFFFF if windowing is not in effect */ + uint32_t timeoutValue; /*!< Timeout value */ + uint32_t warningValue; /*!< Watchdog time counter value that will generate a + warning interrupt. Set this to 0 for no warning */ + uint32_t clockFreq_Hz; /*!< Watchdog clock source frequency. */ +} wwdt_config_t; + +/*! + * @brief WWDT status flags. + * + * This structure contains the WWDT status flags for use in the WWDT functions. + */ +enum _wwdt_status_flags_t +{ + kWWDT_TimeoutFlag = WWDT_MOD_WDTOF_MASK, /*!< Time-out flag, set when the timer times out */ + kWWDT_WarningFlag = WWDT_MOD_WDINT_MASK /*!< Warning interrupt flag, set when timer is below the value WDWARNINT */ +}; + +/******************************************************************************* + * API + *******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @name WWDT Initialization and De-initialization + * @{ + */ + +/*! + * @brief Initializes WWDT configure structure. + * + * This function initializes the WWDT configure structure to default value. The default + * value are: + * @code + * config->enableWwdt = true; + * config->enableWatchdogReset = false; + * config->enableWatchdogProtect = false; + * config->enableLockOscillator = false; + * config->windowValue = 0xFFFFFFU; + * config->timeoutValue = 0xFFFFFFU; + * config->warningValue = 0; + * @endcode + * + * @param config Pointer to WWDT config structure. + * @see wwdt_config_t + */ +void WWDT_GetDefaultConfig(wwdt_config_t *config); + +/*! + * @brief Initializes the WWDT. + * + * This function initializes the WWDT. When called, the WWDT runs according to the configuration. + * + * Example: + * @code + * wwdt_config_t config; + * WWDT_GetDefaultConfig(&config); + * config.timeoutValue = 0x7ffU; + * WWDT_Init(wwdt_base,&config); + * @endcode + * + * @param base WWDT peripheral base address + * @param config The configuration of WWDT + */ +void WWDT_Init(WWDT_Type *base, const wwdt_config_t *config); + +/*! + * @brief Shuts down the WWDT. + * + * This function shuts down the WWDT. + * + * @param base WWDT peripheral base address + */ +void WWDT_Deinit(WWDT_Type *base); + +/* @} */ + +/*! + * @name WWDT Functional Operation + * @{ + */ + +/*! + * @brief Enables the WWDT module. + * + * This function write value into WWDT_MOD register to enable the WWDT, it is a write-once bit; + * once this bit is set to one and a watchdog feed is performed, the watchdog timer will run + * permanently. + * + * @param base WWDT peripheral base address + */ +static inline void WWDT_Enable(WWDT_Type *base) +{ + base->MOD |= WWDT_MOD_WDEN_MASK; +} + +/*! + * @brief Disables the WWDT module. + * + * This function write value into WWDT_MOD register to disable the WWDT. + * + * @param base WWDT peripheral base address + */ +static inline void WWDT_Disable(WWDT_Type *base) +{ + base->MOD &= ~WWDT_MOD_WDEN_MASK; +} + +/*! + * @brief Gets all WWDT status flags. + * + * This function gets all status flags. + * + * Example for getting Timeout Flag: + * @code + * uint32_t status; + * status = WWDT_GetStatusFlags(wwdt_base) & kWWDT_TimeoutFlag; + * @endcode + * @param base WWDT peripheral base address + * @return The status flags. This is the logical OR of members of the + * enumeration ::_wwdt_status_flags_t + */ +static inline uint32_t WWDT_GetStatusFlags(WWDT_Type *base) +{ +#if defined(FSL_FEATURE_WWDT_WDTRESET_FROM_PMC) && (FSL_FEATURE_WWDT_WDTRESET_FROM_PMC) + uint32_t status; + /* WDTOF is not set in case of WD reset - get info from PMC instead */ + status = (base->MOD & (WWDT_MOD_WDTOF_MASK | WWDT_MOD_WDINT_MASK)); + if (PMC->RESETCAUSE & PMC_RESETCAUSE_WDTRESET_MASK) + { + status |= kWWDT_TimeoutFlag; + } + return status; +#else + return (base->MOD & (WWDT_MOD_WDTOF_MASK | WWDT_MOD_WDINT_MASK)); +#endif /*FSL_FEATURE_WWDT_WDTRESET_FROM_PMC*/ +} + +/*! + * @brief Clear WWDT flag. + * + * This function clears WWDT status flag. + * + * Example for clearing warning flag: + * @code + * WWDT_ClearStatusFlags(wwdt_base, kWWDT_WarningFlag); + * @endcode + * @param base WWDT peripheral base address + * @param mask The status flags to clear. This is a logical OR of members of the + * enumeration ::_wwdt_status_flags_t + */ +void WWDT_ClearStatusFlags(WWDT_Type *base, uint32_t mask); + +/*! + * @brief Set the WWDT warning value. + * + * The WDWARNINT register determines the watchdog timer counter value that will generate a watchdog + * interrupt. When the watchdog timer counter is no longer greater than the value defined by + * WARNINT, an interrupt will be generated after the subsequent WDCLK. + * + * @param base WWDT peripheral base address + * @param warningValue WWDT warning value. + */ +static inline void WWDT_SetWarningValue(WWDT_Type *base, uint32_t warningValue) +{ + base->WARNINT = WWDT_WARNINT_WARNINT(warningValue); +} + +/*! + * @brief Set the WWDT timeout value. + * + * This function sets the timeout value. Every time a feed sequence occurs the value in the TC + * register is loaded into the Watchdog timer. Writing a value below 0xFF will cause 0xFF to be + * loaded into the TC register. Thus the minimum time-out interval is TWDCLK*256*4. + * If enableWatchdogProtect flag is true in wwdt_config_t config structure, any attempt to change + * the timeout value before the watchdog counter is below the warning and window values + * will cause a watchdog reset and set the WDTOF flag. + * + * @param base WWDT peripheral base address + * @param timeoutCount WWDT timeout value, count of WWDT clock tick. + */ +static inline void WWDT_SetTimeoutValue(WWDT_Type *base, uint32_t timeoutCount) +{ + base->TC = WWDT_TC_COUNT(timeoutCount); +} + +/*! + * @brief Sets the WWDT window value. + * + * The WINDOW register determines the highest TV value allowed when a watchdog feed is performed. + * If a feed sequence occurs when timer value is greater than the value in WINDOW, a watchdog + * event will occur. To disable windowing, set windowValue to 0xFFFFFF (maximum possible timer + * value) so windowing is not in effect. + * + * @param base WWDT peripheral base address + * @param windowValue WWDT window value. + */ +static inline void WWDT_SetWindowValue(WWDT_Type *base, uint32_t windowValue) +{ + base->WINDOW = WWDT_WINDOW_WINDOW(windowValue); +} + +/*! + * @brief Refreshes the WWDT timer. + * + * This function feeds the WWDT. + * This function should be called before WWDT timer is in timeout. Otherwise, a reset is asserted. + * + * @param base WWDT peripheral base address + */ +void WWDT_Refresh(WWDT_Type *base); + +/*@}*/ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @}*/ + +#endif /* _FSL_WWDT_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/fsl_device_registers.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/fsl_device_registers.h new file mode 100644 index 000000000..1455785a8 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/fsl_device_registers.h @@ -0,0 +1,44 @@ +/* + * Copyright 2014-2016 Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef __FSL_DEVICE_REGISTERS_H__ +#define __FSL_DEVICE_REGISTERS_H__ + +/* + * Include the cpu specific register header files. + * + * The CPU macro should be declared in the project or makefile. + */ +#if (defined(CPU_LPC55S69JBD100_cm33_core0) || defined(CPU_LPC55S69JET98_cm33_core0)) + +#define LPC55S69_cm33_core0_SERIES + +/* CMSIS-style register definitions */ +#include "LPC55S69_cm33_core0.h" +/* CPU specific feature definitions */ +#include "LPC55S69_cm33_core0_features.h" + +#elif (defined(CPU_LPC55S69JBD100_cm33_core1) || defined(CPU_LPC55S69JET98_cm33_core1)) + +#define LPC55S69_cm33_core1_SERIES + +/* CMSIS-style register definitions */ +#include "LPC55S69_cm33_core1.h" +/* CPU specific feature definitions */ +#include "LPC55S69_cm33_core1_features.h" + +#else + #error "No valid CPU defined!" +#endif + +#endif /* __FSL_DEVICE_REGISTERS_H__ */ + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/gcc/LPC55S69_cm33_core0_flash.ld b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/gcc/LPC55S69_cm33_core0_flash.ld new file mode 100644 index 000000000..90f8ee7db --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/gcc/LPC55S69_cm33_core0_flash.ld @@ -0,0 +1,231 @@ +/* +** ################################################################### +** Processors: LPC55S69JBD100_cm33_core0 +** LPC55S69JET98_cm33_core0 +** +** Compiler: GNU C Compiler +** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.2 15 Aug 2018 +** Version: rev. 1.0, 2018-08-22 +** Build: b180921 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + + + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0800; +RPMSG_SHMEM_SIZE = DEFINED(__use_shmem__) ? 0x1800 : 0; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x00000000, LENGTH = 0x00000140 + m_text (RX) : ORIGIN = 0x00000140, LENGTH = 0x00071EC0 + m_core1_image (RX) : ORIGIN = 0x00072000, LENGTH = 0x00026000 + m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00033000 - RPMSG_SHMEM_SIZE + rpmsg_sh_mem (RW) : ORIGIN = 0x20033000 - RPMSG_SHMEM_SIZE, LENGTH = RPMSG_SHMEM_SIZE + m_usb_sram (RW) : ORIGIN = 0x40100000, LENGTH = 0x00004000 +} + +/* Define output sections */ +SECTIONS +{ + /* section for storing the secondary core image */ + .m0code : + { + . = ALIGN(4) ; + KEEP (*(.m0code)) + *(.m0code*) + . = ALIGN(4) ; + } > m_core1_image + + /* NOINIT section for rpmsg_sh_mem */ + .noinit_rpmsg_sh_mem (NOLOAD) : ALIGN(4) + { + *(.noinit.$rpmsg_sh_mem*) + . = ALIGN(4) ; + } > rpmsg_sh_mem + + /* The startup code goes first into internal flash */ + .interrupts : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + /* The program code and other data goes into internal flash */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.ramfunc*) /* for functions in ram */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + m_usb_bdt (NOLOAD) : + { + . = ALIGN(512); + *(m_usb_bdt) + } > m_usb_sram + + m_usb_global (NOLOAD) : + { + *(m_usb_global) + } > m_usb_sram + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/gcc/LPC55S69_cm33_core0_flash_ns.ld b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/gcc/LPC55S69_cm33_core0_flash_ns.ld new file mode 100644 index 000000000..cbf9e3779 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/gcc/LPC55S69_cm33_core0_flash_ns.ld @@ -0,0 +1,231 @@ +/* +** ################################################################### +** Processors: LPC55S69JBD100_cm33_core0 +** LPC55S69JET98_cm33_core0 +** +** Compiler: GNU C Compiler +** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.2 15 Aug 2018 +** Version: rev. 1.0, 2018-08-22 +** Build: b180921 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + + + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0800; +RPMSG_SHMEM_SIZE = DEFINED(__use_shmem__) ? 0x1800 : 0; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x00010000, LENGTH = 0x00000140 + m_text (RX) : ORIGIN = 0x00010140, LENGTH = 0x00061EC0 + m_core1_image (RX) : ORIGIN = 0x00072000, LENGTH = 0x00026000 + m_data (RW) : ORIGIN = 0x20008000, LENGTH = 0x00028000 + rpmsg_sh_mem (RW) : ORIGIN = 0x20033000 - RPMSG_SHMEM_SIZE, LENGTH = RPMSG_SHMEM_SIZE + m_usb_sram (RW) : ORIGIN = 0x40100000, LENGTH = 0x00004000 +} + +/* Define output sections */ +SECTIONS +{ + /* section for storing the secondary core image */ + .m0code : + { + . = ALIGN(4) ; + KEEP (*(.m0code)) + *(.m0code*) + . = ALIGN(4) ; + } > m_core1_image + + /* NOINIT section for rpmsg_sh_mem */ + .noinit_rpmsg_sh_mem (NOLOAD) : ALIGN(4) + { + *(.noinit.$rpmsg_sh_mem*) + . = ALIGN(4) ; + } > rpmsg_sh_mem + + /* The startup code goes first into internal flash */ + .interrupts : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + /* The program code and other data goes into internal flash */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.ramfunc*) /* for functions in ram */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + m_usb_bdt (NOLOAD) : + { + . = ALIGN(512); + *(m_usb_bdt) + } > m_usb_sram + + m_usb_global (NOLOAD) : + { + *(m_usb_global) + } > m_usb_sram + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/gcc/LPC55S69_cm33_core0_flash_s.ld b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/gcc/LPC55S69_cm33_core0_flash_s.ld new file mode 100644 index 000000000..bfd82ab05 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/gcc/LPC55S69_cm33_core0_flash_s.ld @@ -0,0 +1,242 @@ +/* +** ################################################################### +** Processors: LPC55S69JBD100_cm33_core0 +** LPC55S69JET98_cm33_core0 +** +** Compiler: GNU C Compiler +** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.2 15 Aug 2018 +** Version: rev. 1.0, 2018-08-22 +** Build: b180921 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + + + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0800; +RPMSG_SHMEM_SIZE = DEFINED(__use_shmem__) ? 0x1800 : 0; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x10000000, LENGTH = 0x00000140 + m_text (RX) : ORIGIN = 0x10000140, LENGTH = 0x0000FCC0 + m_veneer_table (RX) : ORIGIN = 0x1000FE00, LENGTH = 0x00000200 + m_core1_image (RX) : ORIGIN = 0x10072000, LENGTH = 0x00026000 + m_data (RW) : ORIGIN = 0x30000000, LENGTH = 0x00008000 + rpmsg_sh_mem (RW) : ORIGIN = 0x30033000 - RPMSG_SHMEM_SIZE, LENGTH = RPMSG_SHMEM_SIZE + m_usb_sram (RW) : ORIGIN = 0x50100000, LENGTH = 0x00004000 +} + +/* Define output sections */ +SECTIONS +{ + /* section for storing the secondary core image */ + .m0code : + { + . = ALIGN(4) ; + KEEP (*(.m0code)) + *(.m0code*) + . = ALIGN(4) ; + } > m_core1_image + + /* NOINIT section for rpmsg_sh_mem */ + .noinit_rpmsg_sh_mem (NOLOAD) : ALIGN(4) + { + *(.noinit.$rpmsg_sh_mem*) + . = ALIGN(4) ; + } > rpmsg_sh_mem + + /* The startup code goes first into internal flash */ + .interrupts : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + /* The program code and other data goes into internal flash */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + /* section for veneer table */ + .gnu.sgstubs : + { + . = ALIGN(32); + _start_sg = .; + *(.gnu.sgstubs*) + . = ALIGN(32); + _end_sg = .; + } > m_veneer_table + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.ramfunc*) /* for functions in ram */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + m_usb_bdt (NOLOAD) : + { + . = ALIGN(512); + *(m_usb_bdt) + } > m_usb_sram + + m_usb_global (NOLOAD) : + { + *(m_usb_global) + } > m_usb_sram + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/gcc/LPC55S69_cm33_core0_ram.ld b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/gcc/LPC55S69_cm33_core0_ram.ld new file mode 100644 index 000000000..3fbe35bf3 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/gcc/LPC55S69_cm33_core0_ram.ld @@ -0,0 +1,231 @@ +/* +** ################################################################### +** Processors: LPC55S69JBD100_cm33_core0 +** LPC55S69JET98_cm33_core0 +** +** Compiler: GNU C Compiler +** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.2 15 Aug 2018 +** Version: rev. 1.0, 2018-08-22 +** Build: b180921 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + + + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0800; +RPMSG_SHMEM_SIZE = DEFINED(__use_shmem__) ? 0x1800 : 0; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x04000000, LENGTH = 0x00000140 + m_text (RX) : ORIGIN = 0x04000140, LENGTH = 0x00007EC0 + m_core1_image (RX) : ORIGIN = 0x20033000, LENGTH = 0x00008800 + m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00033000 - RPMSG_SHMEM_SIZE + rpmsg_sh_mem (RW) : ORIGIN = 0x20033000 - RPMSG_SHMEM_SIZE, LENGTH = RPMSG_SHMEM_SIZE + m_usb_sram (RW) : ORIGIN = 0x40100000, LENGTH = 0x00004000 +} + +/* Define output sections */ +SECTIONS +{ + /* section for storing the secondary core image */ + .m0code : + { + . = ALIGN(4) ; + KEEP (*(.m0code)) + *(.m0code*) + . = ALIGN(4) ; + } > m_core1_image + + /* NOINIT section for rpmsg_sh_mem */ + .noinit_rpmsg_sh_mem (NOLOAD) : ALIGN(4) + { + *(.noinit.$rpmsg_sh_mem*) + . = ALIGN(4) ; + } > rpmsg_sh_mem + + /* The startup code goes first into internal flash */ + .interrupts : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + /* The program code and other data goes into internal flash */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.ramfunc*) /* for functions in ram */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + m_usb_bdt (NOLOAD) : + { + . = ALIGN(512); + *(m_usb_bdt) + } > m_usb_sram + + m_usb_global (NOLOAD) : + { + *(m_usb_global) + } > m_usb_sram + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/gcc/LPC55S69_cm33_core1_flash.ld b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/gcc/LPC55S69_cm33_core1_flash.ld new file mode 100644 index 000000000..ffbca1ee1 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/gcc/LPC55S69_cm33_core1_flash.ld @@ -0,0 +1,221 @@ +/* +** ################################################################### +** Processors: LPC55S69JBD100_cm33_core1 +** LPC55S69JET98_cm33_core1 +** +** Compiler: GNU C Compiler +** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.2 15 Aug 2018 +** Version: rev. 1.0, 2018-08-22 +** Build: b180921 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + + + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0800; +RPMSG_SHMEM_SIZE = DEFINED(__use_shmem__) ? 0x1800 : 0; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x00072000, LENGTH = 0x00000140 + m_text (RX) : ORIGIN = 0x00072140, LENGTH = 0x00025EC0 + m_data (RW) : ORIGIN = 0x20033000, LENGTH = 0x00010800 + rpmsg_sh_mem (RW) : ORIGIN = 0x20033000 - RPMSG_SHMEM_SIZE, LENGTH = RPMSG_SHMEM_SIZE + m_usb_sram (RW) : ORIGIN = 0x40100000, LENGTH = 0x00004000 +} + +/* Define output sections */ +SECTIONS +{ + /* NOINIT section for rpmsg_sh_mem */ + .noinit_rpmsg_sh_mem (NOLOAD) : ALIGN(4) + { + *(.noinit.$rpmsg_sh_mem*) + . = ALIGN(4) ; + } > rpmsg_sh_mem + + /* The startup code goes first into internal flash */ + .interrupts : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + /* The program code and other data goes into internal flash */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.ramfunc*) /* for functions in ram */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + m_usb_bdt (NOLOAD) : + { + . = ALIGN(512); + *(m_usb_bdt) + } > m_usb_sram + + m_usb_global (NOLOAD) : + { + *(m_usb_global) + } > m_usb_sram + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/gcc/LPC55S69_cm33_core1_ram.ld b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/gcc/LPC55S69_cm33_core1_ram.ld new file mode 100644 index 000000000..71c2ba04e --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/gcc/LPC55S69_cm33_core1_ram.ld @@ -0,0 +1,221 @@ +/* +** ################################################################### +** Processors: LPC55S69JBD100_cm33_core1 +** LPC55S69JET98_cm33_core1 +** +** Compiler: GNU C Compiler +** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.2 15 Aug 2018 +** Version: rev. 1.0, 2018-08-22 +** Build: b180921 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + + + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0800; +RPMSG_SHMEM_SIZE = DEFINED(__use_shmem__) ? 0x1800 : 0; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x20033000, LENGTH = 0x00000140 + m_text (RX) : ORIGIN = 0x20033140, LENGTH = 0x0000B6C0 + m_data (RW) : ORIGIN = 0x2003E800, LENGTH = 0x00005800 + rpmsg_sh_mem (RW) : ORIGIN = 0x20033000 - RPMSG_SHMEM_SIZE, LENGTH = RPMSG_SHMEM_SIZE + m_usb_sram (RW) : ORIGIN = 0x40100000, LENGTH = 0x00004000 +} + +/* Define output sections */ +SECTIONS +{ + /* NOINIT section for rpmsg_sh_mem */ + .noinit_rpmsg_sh_mem (NOLOAD) : ALIGN(4) + { + *(.noinit.$rpmsg_sh_mem*) + . = ALIGN(4) ; + } > rpmsg_sh_mem + + /* The startup code goes first into internal flash */ + .interrupts : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + /* The program code and other data goes into internal flash */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.ramfunc*) /* for functions in ram */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + m_usb_bdt (NOLOAD) : + { + . = ALIGN(512); + *(m_usb_bdt) + } > m_usb_sram + + m_usb_global (NOLOAD) : + { + *(m_usb_global) + } > m_usb_sram + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/gcc/LPC55S69_cm33_core1_ram_s.ld b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/gcc/LPC55S69_cm33_core1_ram_s.ld new file mode 100644 index 000000000..fe9b7a27f --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/gcc/LPC55S69_cm33_core1_ram_s.ld @@ -0,0 +1,221 @@ +/* +** ################################################################### +** Processors: LPC55S69JBD100_cm33_core1 +** LPC55S69JET98_cm33_core1 +** +** Compiler: GNU C Compiler +** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.2 15 Aug 2018 +** Version: rev. 1.0, 2018-08-22 +** Build: b180921 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + + + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0800; +RPMSG_SHMEM_SIZE = DEFINED(__use_shmem__) ? 0x1800 : 0; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x30033000, LENGTH = 0x00000140 + m_text (RX) : ORIGIN = 0x30033140, LENGTH = 0x0000B6C0 + m_data (RW) : ORIGIN = 0x3003E800, LENGTH = 0x00005800 + rpmsg_sh_mem (RW) : ORIGIN = 0x30033000 - RPMSG_SHMEM_SIZE, LENGTH = RPMSG_SHMEM_SIZE + m_usb_sram (RW) : ORIGIN = 0x50100000, LENGTH = 0x00004000 +} + +/* Define output sections */ +SECTIONS +{ + /* NOINIT section for rpmsg_sh_mem */ + .noinit_rpmsg_sh_mem (NOLOAD) : ALIGN(4) + { + *(.noinit.$rpmsg_sh_mem*) + . = ALIGN(4) ; + } > rpmsg_sh_mem + + /* The startup code goes first into internal flash */ + .interrupts : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + /* The program code and other data goes into internal flash */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.ramfunc*) /* for functions in ram */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + m_usb_bdt (NOLOAD) : + { + . = ALIGN(512); + *(m_usb_bdt) + } > m_usb_sram + + m_usb_global (NOLOAD) : + { + *(m_usb_global) + } > m_usb_sram + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/gcc/libpower_hardabi.a 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Core Device Startup File */ +/* LPC55S69_cm33_core0 */ +/* @version: 1.1 */ +/* @date: 2019-5-16 */ +/* --------------------------------------------------------------------------*/ +/* */ +/* Copyright 1997-2016 Freescale Semiconductor, Inc. */ +/* Copyright 2016-2019 NXP */ +/* All rights reserved. */ +/* */ +/* SPDX-License-Identifier: BSD-3-Clause */ +/*****************************************************************************/ +/* Version: GCC for ARM Embedded Processors */ +/*****************************************************************************/ + + + .syntax unified + .arch armv8-m.main + + .section .isr_vector, "a" + .align 2 + .globl __Vectors +__Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler*/ + .long HardFault_Handler /* Hard Fault Handler*/ + .long MemManage_Handler /* MPU Fault Handler*/ + .long BusFault_Handler /* Bus Fault Handler*/ + .long UsageFault_Handler /* Usage Fault Handler*/ + .long SecureFault_Handler /* Secure Fault Handler*/ + .long 0 /* Reserved*/ + .long 0 /* Reserved*/ + .long 0 /* Reserved*/ + .long SVC_Handler /* SVCall Handler*/ + .long DebugMon_Handler /* Debug Monitor Handler*/ + .long 0 /* Reserved*/ + .long PendSV_Handler /* PendSV Handler*/ + .long SysTick_Handler /* SysTick Handler*/ + + /* External Interrupts */ + .long WDT_BOD_IRQHandler /* Windowed watchdog timer, Brownout detect, Flash interrupt */ + .long DMA0_IRQHandler /* DMA0 controller */ + .long GINT0_IRQHandler /* GPIO group 0 */ + .long GINT1_IRQHandler /* GPIO group 1 */ + .long PIN_INT0_IRQHandler /* Pin interrupt 0 or pattern match engine slice 0 */ + .long PIN_INT1_IRQHandler /* Pin interrupt 1or pattern match engine slice 1 */ + .long PIN_INT2_IRQHandler /* Pin interrupt 2 or pattern match engine slice 2 */ + .long PIN_INT3_IRQHandler /* Pin interrupt 3 or pattern match engine slice 3 */ + .long UTICK0_IRQHandler /* Micro-tick Timer */ + .long MRT0_IRQHandler /* Multi-rate timer */ + .long CTIMER0_IRQHandler /* Standard counter/timer CTIMER0 */ + .long CTIMER1_IRQHandler /* Standard counter/timer CTIMER1 */ + .long SCT0_IRQHandler /* SCTimer/PWM */ + .long CTIMER3_IRQHandler /* Standard counter/timer CTIMER3 */ + .long FLEXCOMM0_IRQHandler /* Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) */ + .long FLEXCOMM1_IRQHandler /* Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) */ + .long FLEXCOMM2_IRQHandler /* Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) */ + .long FLEXCOMM3_IRQHandler /* Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) */ + .long FLEXCOMM4_IRQHandler /* Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) */ + .long FLEXCOMM5_IRQHandler /* Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) */ + .long FLEXCOMM6_IRQHandler /* Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) */ + .long FLEXCOMM7_IRQHandler /* Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) */ + .long ADC0_IRQHandler /* ADC0 */ + .long Reserved39_IRQHandler /* Reserved interrupt */ + .long ACMP_IRQHandler /* ACMP interrupts */ + .long Reserved41_IRQHandler /* Reserved interrupt */ + .long Reserved42_IRQHandler /* Reserved interrupt */ + .long USB0_NEEDCLK_IRQHandler /* USB Activity Wake-up Interrupt */ + .long USB0_IRQHandler /* USB device */ + .long RTC_IRQHandler /* RTC alarm and wake-up interrupts */ + .long Reserved46_IRQHandler /* Reserved interrupt */ + .long MAILBOX_IRQHandler /* WAKEUP,Mailbox interrupt (present on selected devices) */ + .long PIN_INT4_IRQHandler /* Pin interrupt 4 or pattern match engine slice 4 int */ + .long PIN_INT5_IRQHandler /* Pin interrupt 5 or pattern match engine slice 5 int */ + .long PIN_INT6_IRQHandler /* Pin interrupt 6 or pattern match engine slice 6 int */ + .long PIN_INT7_IRQHandler /* Pin interrupt 7 or pattern match engine slice 7 int */ + .long CTIMER2_IRQHandler /* Standard counter/timer CTIMER2 */ + .long CTIMER4_IRQHandler /* Standard counter/timer CTIMER4 */ + .long OS_EVENT_IRQHandler /* OSEVTIMER0 and OSEVTIMER0_WAKEUP interrupts */ + .long Reserved55_IRQHandler /* Reserved interrupt */ + .long Reserved56_IRQHandler /* Reserved interrupt */ + .long Reserved57_IRQHandler /* Reserved interrupt */ + .long SDIO_IRQHandler /* SD/MMC */ + .long Reserved59_IRQHandler /* Reserved interrupt */ + .long Reserved60_IRQHandler /* Reserved interrupt */ + .long Reserved61_IRQHandler /* Reserved interrupt */ + .long USB1_UTMI_IRQHandler /* USB1_UTMI */ + .long USB1_IRQHandler /* USB1 interrupt */ + .long USB1_NEEDCLK_IRQHandler /* USB1 activity */ + .long SEC_HYPERVISOR_CALL_IRQHandler /* SEC_HYPERVISOR_CALL interrupt */ + .long SEC_GPIO_INT0_IRQ0_IRQHandler /* SEC_GPIO_INT0_IRQ0 interrupt */ + .long SEC_GPIO_INT0_IRQ1_IRQHandler /* SEC_GPIO_INT0_IRQ1 interrupt */ + .long PLU_IRQHandler /* PLU interrupt */ + .long SEC_VIO_IRQHandler /* SEC_VIO interrupt */ + .long HASHCRYPT_IRQHandler /* HASHCRYPT interrupt */ + .long CASER_IRQHandler /* CASPER interrupt */ + .long PUF_IRQHandler /* PUF interrupt */ + .long PQ_IRQHandler /* PQ interrupt */ + .long DMA1_IRQHandler /* DMA1 interrupt */ + .long FLEXCOMM8_IRQHandler /* Flexcomm Interface 8 (SPI, , FLEXCOMM) */ + + .size __Vectors, . - __Vectors + + .text + .thumb + +/* Reset Handler */ + .thumb_func + .align 2 + .globl Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: +#ifndef __NO_SYSTEM_INIT + ldr r0,=SystemInit + blx r0 +#endif +/* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * __etext: End of code section, i.e., begin of data sections to copy from. + * __data_start__/__data_end__: RAM address range that data should be + * copied to. Both must be aligned to 4 bytes boundary. */ + + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +#if 1 +/* Here are two copies of loop implemenations. First one favors code size + * and the second one favors performance. Default uses the first one. + * Change to "#if 0" to use the second one */ +.LC0: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .LC0 +#else + subs r3, r2 + ble .LC1 +.LC0: + subs r3, #4 + ldr r0, [r1, r3] + str r0, [r2, r3] + bgt .LC0 +.LC1: +#endif + +#ifdef __STARTUP_CLEAR_BSS +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * Loop to zero out BSS section, which uses following symbols + * in linker script: + * __bss_start__: start of BSS section. Must align to 4 + * __bss_end__: end of BSS section. Must align to 4 + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 +.LC2: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .LC2 +#endif /* __STARTUP_CLEAR_BSS */ + +/* Add stack / heap initializaiton */ + movs r0, 0 + ldr r1, =__HeapBase + ldr r2, =__HeapLimit +.LC3: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .LC3 + + ldr r1, =__StackLimit + ldr r2, =__StackTop +.LC4: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .LC4 +/*End of stack / heap initializaiton */ + cpsie i /* Unmask interrupts */ + +#ifndef __START +#define __START _start +#endif +#ifndef __ATOLLIC__ + ldr r0,=__START + blx r0 +#else + ldr r0,=__libc_init_array + blx r0 + ldr r0,=main + bx r0 +#endif + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak DefaultISR + .type DefaultISR, %function +DefaultISR: + b DefaultISR + .size DefaultISR, . - DefaultISR + + .align 1 + .thumb_func + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + ldr r0,=NMI_Handler + bx r0 + .size NMI_Handler, . - NMI_Handler + + .align 1 + .thumb_func + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + ldr r0,=HardFault_Handler + bx r0 + .size HardFault_Handler, . - HardFault_Handler + + .align 1 + .thumb_func + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + ldr r0,=SVC_Handler + bx r0 + .size SVC_Handler, . - SVC_Handler + + .align 1 + .thumb_func + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + ldr r0,=PendSV_Handler + bx r0 + .size PendSV_Handler, . - PendSV_Handler + + .align 1 + .thumb_func + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + ldr r0,=SysTick_Handler + bx r0 + .size SysTick_Handler, . - SysTick_Handler + + .align 1 + .thumb_func + .weak WDT_BOD_IRQHandler + .type WDT_BOD_IRQHandler, %function +WDT_BOD_IRQHandler: + ldr r0,=WDT_BOD_DriverIRQHandler + bx r0 + .size WDT_BOD_IRQHandler, . - WDT_BOD_IRQHandler + + .align 1 + .thumb_func + .weak DMA0_IRQHandler + .type DMA0_IRQHandler, %function +DMA0_IRQHandler: + ldr r0,=DMA0_DriverIRQHandler + bx r0 + .size DMA0_IRQHandler, . - DMA0_IRQHandler + + .align 1 + .thumb_func + .weak GINT0_IRQHandler + .type GINT0_IRQHandler, %function +GINT0_IRQHandler: + ldr r0,=GINT0_DriverIRQHandler + bx r0 + .size GINT0_IRQHandler, . - GINT0_IRQHandler + + .align 1 + .thumb_func + .weak GINT1_IRQHandler + .type GINT1_IRQHandler, %function +GINT1_IRQHandler: + ldr r0,=GINT1_DriverIRQHandler + bx r0 + .size GINT1_IRQHandler, . - GINT1_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT0_IRQHandler + .type PIN_INT0_IRQHandler, %function +PIN_INT0_IRQHandler: + ldr r0,=PIN_INT0_DriverIRQHandler + bx r0 + .size PIN_INT0_IRQHandler, . - PIN_INT0_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT1_IRQHandler + .type PIN_INT1_IRQHandler, %function +PIN_INT1_IRQHandler: + ldr r0,=PIN_INT1_DriverIRQHandler + bx r0 + .size PIN_INT1_IRQHandler, . - PIN_INT1_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT2_IRQHandler + .type PIN_INT2_IRQHandler, %function +PIN_INT2_IRQHandler: + ldr r0,=PIN_INT2_DriverIRQHandler + bx r0 + .size PIN_INT2_IRQHandler, . - PIN_INT2_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT3_IRQHandler + .type PIN_INT3_IRQHandler, %function +PIN_INT3_IRQHandler: + ldr r0,=PIN_INT3_DriverIRQHandler + bx r0 + .size PIN_INT3_IRQHandler, . - PIN_INT3_IRQHandler + + .align 1 + .thumb_func + .weak UTICK0_IRQHandler + .type UTICK0_IRQHandler, %function +UTICK0_IRQHandler: + ldr r0,=UTICK0_DriverIRQHandler + bx r0 + .size UTICK0_IRQHandler, . - UTICK0_IRQHandler + + .align 1 + .thumb_func + .weak MRT0_IRQHandler + .type MRT0_IRQHandler, %function +MRT0_IRQHandler: + ldr r0,=MRT0_DriverIRQHandler + bx r0 + .size MRT0_IRQHandler, . - MRT0_IRQHandler + + .align 1 + .thumb_func + .weak CTIMER0_IRQHandler + .type CTIMER0_IRQHandler, %function +CTIMER0_IRQHandler: + ldr r0,=CTIMER0_DriverIRQHandler + bx r0 + .size CTIMER0_IRQHandler, . - CTIMER0_IRQHandler + + .align 1 + .thumb_func + .weak CTIMER1_IRQHandler + .type CTIMER1_IRQHandler, %function +CTIMER1_IRQHandler: + ldr r0,=CTIMER1_DriverIRQHandler + bx r0 + .size CTIMER1_IRQHandler, . - CTIMER1_IRQHandler + + .align 1 + .thumb_func + .weak SCT0_IRQHandler + .type SCT0_IRQHandler, %function +SCT0_IRQHandler: + ldr r0,=SCT0_DriverIRQHandler + bx r0 + .size SCT0_IRQHandler, . - SCT0_IRQHandler + + .align 1 + .thumb_func + .weak CTIMER3_IRQHandler + .type CTIMER3_IRQHandler, %function +CTIMER3_IRQHandler: + ldr r0,=CTIMER3_DriverIRQHandler + bx r0 + .size CTIMER3_IRQHandler, . - CTIMER3_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM0_IRQHandler + .type FLEXCOMM0_IRQHandler, %function +FLEXCOMM0_IRQHandler: + ldr r0,=FLEXCOMM0_DriverIRQHandler + bx r0 + .size FLEXCOMM0_IRQHandler, . - FLEXCOMM0_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM1_IRQHandler + .type FLEXCOMM1_IRQHandler, %function +FLEXCOMM1_IRQHandler: + ldr r0,=FLEXCOMM1_DriverIRQHandler + bx r0 + .size FLEXCOMM1_IRQHandler, . - FLEXCOMM1_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM2_IRQHandler + .type FLEXCOMM2_IRQHandler, %function +FLEXCOMM2_IRQHandler: + ldr r0,=FLEXCOMM2_DriverIRQHandler + bx r0 + .size FLEXCOMM2_IRQHandler, . - FLEXCOMM2_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM3_IRQHandler + .type FLEXCOMM3_IRQHandler, %function +FLEXCOMM3_IRQHandler: + ldr r0,=FLEXCOMM3_DriverIRQHandler + bx r0 + .size FLEXCOMM3_IRQHandler, . - FLEXCOMM3_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM4_IRQHandler + .type FLEXCOMM4_IRQHandler, %function +FLEXCOMM4_IRQHandler: + ldr r0,=FLEXCOMM4_DriverIRQHandler + bx r0 + .size FLEXCOMM4_IRQHandler, . - FLEXCOMM4_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM5_IRQHandler + .type FLEXCOMM5_IRQHandler, %function +FLEXCOMM5_IRQHandler: + ldr r0,=FLEXCOMM5_DriverIRQHandler + bx r0 + .size FLEXCOMM5_IRQHandler, . - FLEXCOMM5_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM6_IRQHandler + .type FLEXCOMM6_IRQHandler, %function +FLEXCOMM6_IRQHandler: + ldr r0,=FLEXCOMM6_DriverIRQHandler + bx r0 + .size FLEXCOMM6_IRQHandler, . - FLEXCOMM6_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM7_IRQHandler + .type FLEXCOMM7_IRQHandler, %function +FLEXCOMM7_IRQHandler: + ldr r0,=FLEXCOMM7_DriverIRQHandler + bx r0 + .size FLEXCOMM7_IRQHandler, . - FLEXCOMM7_IRQHandler + + .align 1 + .thumb_func + .weak ADC0_IRQHandler + .type ADC0_IRQHandler, %function +ADC0_IRQHandler: + ldr r0,=ADC0_DriverIRQHandler + bx r0 + .size ADC0_IRQHandler, . - ADC0_IRQHandler + + .align 1 + .thumb_func + .weak Reserved39_IRQHandler + .type Reserved39_IRQHandler, %function +Reserved39_IRQHandler: + ldr r0,=Reserved39_DriverIRQHandler + bx r0 + .size Reserved39_IRQHandler, . - Reserved39_IRQHandler + + .align 1 + .thumb_func + .weak ACMP_IRQHandler + .type ACMP_IRQHandler, %function +ACMP_IRQHandler: + ldr r0,=ACMP_DriverIRQHandler + bx r0 + .size ACMP_IRQHandler, . - ACMP_IRQHandler + + .align 1 + .thumb_func + .weak Reserved41_IRQHandler + .type Reserved41_IRQHandler, %function +Reserved41_IRQHandler: + ldr r0,=Reserved41_DriverIRQHandler + bx r0 + .size Reserved41_IRQHandler, . - Reserved41_IRQHandler + + .align 1 + .thumb_func + .weak Reserved42_IRQHandler + .type Reserved42_IRQHandler, %function +Reserved42_IRQHandler: + ldr r0,=Reserved42_DriverIRQHandler + bx r0 + .size Reserved42_IRQHandler, . - Reserved42_IRQHandler + + .align 1 + .thumb_func + .weak USB0_NEEDCLK_IRQHandler + .type USB0_NEEDCLK_IRQHandler, %function +USB0_NEEDCLK_IRQHandler: + ldr r0,=USB0_NEEDCLK_DriverIRQHandler + bx r0 + .size USB0_NEEDCLK_IRQHandler, . - USB0_NEEDCLK_IRQHandler + + .align 1 + .thumb_func + .weak USB0_IRQHandler + .type USB0_IRQHandler, %function +USB0_IRQHandler: + ldr r0,=USB0_DriverIRQHandler + bx r0 + .size USB0_IRQHandler, . - USB0_IRQHandler + + .align 1 + .thumb_func + .weak RTC_IRQHandler + .type RTC_IRQHandler, %function +RTC_IRQHandler: + ldr r0,=RTC_DriverIRQHandler + bx r0 + .size RTC_IRQHandler, . - RTC_IRQHandler + + .align 1 + .thumb_func + .weak Reserved46_IRQHandler + .type Reserved46_IRQHandler, %function +Reserved46_IRQHandler: + ldr r0,=Reserved46_DriverIRQHandler + bx r0 + .size Reserved46_IRQHandler, . - Reserved46_IRQHandler + + .align 1 + .thumb_func + .weak MAILBOX_IRQHandler + .type MAILBOX_IRQHandler, %function +MAILBOX_IRQHandler: + ldr r0,=MAILBOX_DriverIRQHandler + bx r0 + .size MAILBOX_IRQHandler, . - MAILBOX_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT4_IRQHandler + .type PIN_INT4_IRQHandler, %function +PIN_INT4_IRQHandler: + ldr r0,=PIN_INT4_DriverIRQHandler + bx r0 + .size PIN_INT4_IRQHandler, . - PIN_INT4_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT5_IRQHandler + .type PIN_INT5_IRQHandler, %function +PIN_INT5_IRQHandler: + ldr r0,=PIN_INT5_DriverIRQHandler + bx r0 + .size PIN_INT5_IRQHandler, . - PIN_INT5_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT6_IRQHandler + .type PIN_INT6_IRQHandler, %function +PIN_INT6_IRQHandler: + ldr r0,=PIN_INT6_DriverIRQHandler + bx r0 + .size PIN_INT6_IRQHandler, . - PIN_INT6_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT7_IRQHandler + .type PIN_INT7_IRQHandler, %function +PIN_INT7_IRQHandler: + ldr r0,=PIN_INT7_DriverIRQHandler + bx r0 + .size PIN_INT7_IRQHandler, . - PIN_INT7_IRQHandler + + .align 1 + .thumb_func + .weak CTIMER2_IRQHandler + .type CTIMER2_IRQHandler, %function +CTIMER2_IRQHandler: + ldr r0,=CTIMER2_DriverIRQHandler + bx r0 + .size CTIMER2_IRQHandler, . - CTIMER2_IRQHandler + + .align 1 + .thumb_func + .weak CTIMER4_IRQHandler + .type CTIMER4_IRQHandler, %function +CTIMER4_IRQHandler: + ldr r0,=CTIMER4_DriverIRQHandler + bx r0 + .size CTIMER4_IRQHandler, . - CTIMER4_IRQHandler + + .align 1 + .thumb_func + .weak OS_EVENT_IRQHandler + .type OS_EVENT_IRQHandler, %function +OS_EVENT_IRQHandler: + ldr r0,=OS_EVENT_DriverIRQHandler + bx r0 + .size OS_EVENT_IRQHandler, . - OS_EVENT_IRQHandler + + .align 1 + .thumb_func + .weak Reserved55_IRQHandler + .type Reserved55_IRQHandler, %function +Reserved55_IRQHandler: + ldr r0,=Reserved55_DriverIRQHandler + bx r0 + .size Reserved55_IRQHandler, . - Reserved55_IRQHandler + + .align 1 + .thumb_func + .weak Reserved56_IRQHandler + .type Reserved56_IRQHandler, %function +Reserved56_IRQHandler: + ldr r0,=Reserved56_DriverIRQHandler + bx r0 + .size Reserved56_IRQHandler, . - Reserved56_IRQHandler + + .align 1 + .thumb_func + .weak Reserved57_IRQHandler + .type Reserved57_IRQHandler, %function +Reserved57_IRQHandler: + ldr r0,=Reserved57_DriverIRQHandler + bx r0 + .size Reserved57_IRQHandler, . - Reserved57_IRQHandler + + .align 1 + .thumb_func + .weak SDIO_IRQHandler + .type SDIO_IRQHandler, %function +SDIO_IRQHandler: + ldr r0,=SDIO_DriverIRQHandler + bx r0 + .size SDIO_IRQHandler, . - SDIO_IRQHandler + + .align 1 + .thumb_func + .weak Reserved59_IRQHandler + .type Reserved59_IRQHandler, %function +Reserved59_IRQHandler: + ldr r0,=Reserved59_DriverIRQHandler + bx r0 + .size Reserved59_IRQHandler, . - Reserved59_IRQHandler + + .align 1 + .thumb_func + .weak Reserved60_IRQHandler + .type Reserved60_IRQHandler, %function +Reserved60_IRQHandler: + ldr r0,=Reserved60_DriverIRQHandler + bx r0 + .size Reserved60_IRQHandler, . - Reserved60_IRQHandler + + .align 1 + .thumb_func + .weak Reserved61_IRQHandler + .type Reserved61_IRQHandler, %function +Reserved61_IRQHandler: + ldr r0,=Reserved61_DriverIRQHandler + bx r0 + .size Reserved61_IRQHandler, . - Reserved61_IRQHandler + + .align 1 + .thumb_func + .weak USB1_UTMI_IRQHandler + .type USB1_UTMI_IRQHandler, %function +USB1_UTMI_IRQHandler: + ldr r0,=USB1_UTMI_DriverIRQHandler + bx r0 + .size USB1_UTMI_IRQHandler, . - USB1_UTMI_IRQHandler + + .align 1 + .thumb_func + .weak USB1_IRQHandler + .type USB1_IRQHandler, %function +USB1_IRQHandler: + ldr r0,=USB1_DriverIRQHandler + bx r0 + .size USB1_IRQHandler, . - USB1_IRQHandler + + .align 1 + .thumb_func + .weak USB1_NEEDCLK_IRQHandler + .type USB1_NEEDCLK_IRQHandler, %function +USB1_NEEDCLK_IRQHandler: + ldr r0,=USB1_NEEDCLK_DriverIRQHandler + bx r0 + .size USB1_NEEDCLK_IRQHandler, . - USB1_NEEDCLK_IRQHandler + + .align 1 + .thumb_func + .weak SEC_HYPERVISOR_CALL_IRQHandler + .type SEC_HYPERVISOR_CALL_IRQHandler, %function +SEC_HYPERVISOR_CALL_IRQHandler: + ldr r0,=SEC_HYPERVISOR_CALL_DriverIRQHandler + bx r0 + .size SEC_HYPERVISOR_CALL_IRQHandler, . - SEC_HYPERVISOR_CALL_IRQHandler + + .align 1 + .thumb_func + .weak SEC_GPIO_INT0_IRQ0_IRQHandler + .type SEC_GPIO_INT0_IRQ0_IRQHandler, %function +SEC_GPIO_INT0_IRQ0_IRQHandler: + ldr r0,=SEC_GPIO_INT0_IRQ0_DriverIRQHandler + bx r0 + .size SEC_GPIO_INT0_IRQ0_IRQHandler, . - SEC_GPIO_INT0_IRQ0_IRQHandler + + .align 1 + .thumb_func + .weak SEC_GPIO_INT0_IRQ1_IRQHandler + .type SEC_GPIO_INT0_IRQ1_IRQHandler, %function +SEC_GPIO_INT0_IRQ1_IRQHandler: + ldr r0,=SEC_GPIO_INT0_IRQ1_DriverIRQHandler + bx r0 + .size SEC_GPIO_INT0_IRQ1_IRQHandler, . - SEC_GPIO_INT0_IRQ1_IRQHandler + + .align 1 + .thumb_func + .weak PLU_IRQHandler + .type PLU_IRQHandler, %function +PLU_IRQHandler: + ldr r0,=PLU_DriverIRQHandler + bx r0 + .size PLU_IRQHandler, . - PLU_IRQHandler + + .align 1 + .thumb_func + .weak SEC_VIO_IRQHandler + .type SEC_VIO_IRQHandler, %function +SEC_VIO_IRQHandler: + ldr r0,=SEC_VIO_DriverIRQHandler + bx r0 + .size SEC_VIO_IRQHandler, . - SEC_VIO_IRQHandler + + .align 1 + .thumb_func + .weak HASHCRYPT_IRQHandler + .type HASHCRYPT_IRQHandler, %function +HASHCRYPT_IRQHandler: + ldr r0,=HASHCRYPT_DriverIRQHandler + bx r0 + .size HASHCRYPT_IRQHandler, . - HASHCRYPT_IRQHandler + + .align 1 + .thumb_func + .weak CASER_IRQHandler + .type CASER_IRQHandler, %function +CASER_IRQHandler: + ldr r0,=CASER_DriverIRQHandler + bx r0 + .size CASER_IRQHandler, . - CASER_IRQHandler + + .align 1 + .thumb_func + .weak PUF_IRQHandler + .type PUF_IRQHandler, %function +PUF_IRQHandler: + ldr r0,=PUF_DriverIRQHandler + bx r0 + .size PUF_IRQHandler, . - PUF_IRQHandler + + .align 1 + .thumb_func + .weak PQ_IRQHandler + .type PQ_IRQHandler, %function +PQ_IRQHandler: + ldr r0,=PQ_DriverIRQHandler + bx r0 + .size PQ_IRQHandler, . - PQ_IRQHandler + + .align 1 + .thumb_func + .weak DMA1_IRQHandler + .type DMA1_IRQHandler, %function +DMA1_IRQHandler: + ldr r0,=DMA1_DriverIRQHandler + bx r0 + .size DMA1_IRQHandler, . - DMA1_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM8_IRQHandler + .type FLEXCOMM8_IRQHandler, %function +FLEXCOMM8_IRQHandler: + ldr r0,=FLEXCOMM8_DriverIRQHandler + bx r0 + .size FLEXCOMM8_IRQHandler, . - FLEXCOMM8_IRQHandler + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, DefaultISR + .endm +/* Exception Handlers */ + def_irq_handler MemManage_Handler + def_irq_handler BusFault_Handler + def_irq_handler UsageFault_Handler + def_irq_handler SecureFault_Handler + def_irq_handler DebugMon_Handler + def_irq_handler WDT_BOD_DriverIRQHandler + def_irq_handler DMA0_DriverIRQHandler + def_irq_handler GINT0_DriverIRQHandler + def_irq_handler GINT1_DriverIRQHandler + def_irq_handler PIN_INT0_DriverIRQHandler + def_irq_handler PIN_INT1_DriverIRQHandler + def_irq_handler PIN_INT2_DriverIRQHandler + def_irq_handler PIN_INT3_DriverIRQHandler + def_irq_handler UTICK0_DriverIRQHandler + def_irq_handler MRT0_DriverIRQHandler + def_irq_handler CTIMER0_DriverIRQHandler + def_irq_handler CTIMER1_DriverIRQHandler + def_irq_handler SCT0_DriverIRQHandler + def_irq_handler CTIMER3_DriverIRQHandler + def_irq_handler FLEXCOMM0_DriverIRQHandler + def_irq_handler FLEXCOMM1_DriverIRQHandler + def_irq_handler FLEXCOMM2_DriverIRQHandler + def_irq_handler FLEXCOMM3_DriverIRQHandler + def_irq_handler FLEXCOMM4_DriverIRQHandler + def_irq_handler FLEXCOMM5_DriverIRQHandler + def_irq_handler FLEXCOMM6_DriverIRQHandler + def_irq_handler FLEXCOMM7_DriverIRQHandler + def_irq_handler ADC0_DriverIRQHandler + def_irq_handler Reserved39_DriverIRQHandler + def_irq_handler ACMP_DriverIRQHandler + def_irq_handler Reserved41_DriverIRQHandler + def_irq_handler Reserved42_DriverIRQHandler + def_irq_handler USB0_NEEDCLK_DriverIRQHandler + def_irq_handler USB0_DriverIRQHandler + def_irq_handler RTC_DriverIRQHandler + def_irq_handler Reserved46_DriverIRQHandler + def_irq_handler MAILBOX_DriverIRQHandler + def_irq_handler PIN_INT4_DriverIRQHandler + def_irq_handler PIN_INT5_DriverIRQHandler + def_irq_handler PIN_INT6_DriverIRQHandler + def_irq_handler PIN_INT7_DriverIRQHandler + def_irq_handler CTIMER2_DriverIRQHandler + def_irq_handler CTIMER4_DriverIRQHandler + def_irq_handler OS_EVENT_DriverIRQHandler + def_irq_handler Reserved55_DriverIRQHandler + def_irq_handler Reserved56_DriverIRQHandler + def_irq_handler Reserved57_DriverIRQHandler + def_irq_handler SDIO_DriverIRQHandler + def_irq_handler Reserved59_DriverIRQHandler + def_irq_handler Reserved60_DriverIRQHandler + def_irq_handler Reserved61_DriverIRQHandler + def_irq_handler USB1_UTMI_DriverIRQHandler + def_irq_handler USB1_DriverIRQHandler + def_irq_handler USB1_NEEDCLK_DriverIRQHandler + def_irq_handler SEC_HYPERVISOR_CALL_DriverIRQHandler + def_irq_handler SEC_GPIO_INT0_IRQ0_DriverIRQHandler + def_irq_handler SEC_GPIO_INT0_IRQ1_DriverIRQHandler + def_irq_handler PLU_DriverIRQHandler + def_irq_handler SEC_VIO_DriverIRQHandler + def_irq_handler HASHCRYPT_DriverIRQHandler + def_irq_handler CASER_DriverIRQHandler + def_irq_handler PUF_DriverIRQHandler + def_irq_handler PQ_DriverIRQHandler + def_irq_handler DMA1_DriverIRQHandler + def_irq_handler FLEXCOMM8_DriverIRQHandler + + .end diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/gcc/startup_LPC55S69_cm33_core1.S b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/gcc/startup_LPC55S69_cm33_core1.S new file mode 100644 index 000000000..fff53798f --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/gcc/startup_LPC55S69_cm33_core1.S @@ -0,0 +1,875 @@ +/* --------------------------------------------------------------------------*/ +/* @file: startup_LPC55S69_cm33_core1.s */ +/* @purpose: CMSIS Cortex-M33 Core Device Startup File */ +/* LPC55S69_cm33_core1 */ +/* @version: 1.1 */ +/* @date: 2019-5-16 */ +/* --------------------------------------------------------------------------*/ +/* */ +/* Copyright 1997-2016 Freescale Semiconductor, Inc. */ +/* Copyright 2016-2019 NXP */ +/* All rights reserved. */ +/* */ +/* SPDX-License-Identifier: BSD-3-Clause */ +/*****************************************************************************/ +/* Version: GCC for ARM Embedded Processors */ +/*****************************************************************************/ + + + .syntax unified + .arch armv8-m.main + + .section .isr_vector, "a" + .align 2 + .globl __Vectors +__Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler*/ + .long HardFault_Handler /* Hard Fault Handler*/ + .long MemManage_Handler /* MPU Fault Handler*/ + .long BusFault_Handler /* Bus Fault Handler*/ + .long UsageFault_Handler /* Usage Fault Handler*/ + .long SecureFault_Handler /* Secure Fault Handler*/ + .long 0 /* Reserved*/ + .long 0 /* Reserved*/ + .long 0 /* Reserved*/ + .long SVC_Handler /* SVCall Handler*/ + .long DebugMon_Handler /* Debug Monitor Handler*/ + .long 0 /* Reserved*/ + .long PendSV_Handler /* PendSV Handler*/ + .long SysTick_Handler /* SysTick Handler*/ + + /* External Interrupts */ + .long WDT_BOD_IRQHandler /* Windowed watchdog timer, Brownout detect, Flash interrupt */ + .long DMA0_IRQHandler /* DMA0 controller */ + .long GINT0_IRQHandler /* GPIO group 0 */ + .long GINT1_IRQHandler /* GPIO group 1 */ + .long PIN_INT0_IRQHandler /* Pin interrupt 0 or pattern match engine slice 0 */ + .long PIN_INT1_IRQHandler /* Pin interrupt 1or pattern match engine slice 1 */ + .long PIN_INT2_IRQHandler /* Pin interrupt 2 or pattern match engine slice 2 */ + .long PIN_INT3_IRQHandler /* Pin interrupt 3 or pattern match engine slice 3 */ + .long UTICK0_IRQHandler /* Micro-tick Timer */ + .long MRT0_IRQHandler /* Multi-rate timer */ + .long CTIMER0_IRQHandler /* Standard counter/timer CTIMER0 */ + .long CTIMER1_IRQHandler /* Standard counter/timer CTIMER1 */ + .long SCT0_IRQHandler /* SCTimer/PWM */ + .long CTIMER3_IRQHandler /* Standard counter/timer CTIMER3 */ + .long FLEXCOMM0_IRQHandler /* Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) */ + .long FLEXCOMM1_IRQHandler /* Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) */ + .long FLEXCOMM2_IRQHandler /* Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) */ + .long FLEXCOMM3_IRQHandler /* Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) */ + .long FLEXCOMM4_IRQHandler /* Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) */ + .long FLEXCOMM5_IRQHandler /* Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) */ + .long FLEXCOMM6_IRQHandler /* Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) */ + .long FLEXCOMM7_IRQHandler /* Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) */ + .long ADC0_IRQHandler /* ADC0 */ + .long Reserved39_IRQHandler /* Reserved interrupt */ + .long ACMP_IRQHandler /* ACMP interrupts */ + .long Reserved41_IRQHandler /* Reserved interrupt */ + .long Reserved42_IRQHandler /* Reserved interrupt */ + .long USB0_NEEDCLK_IRQHandler /* USB Activity Wake-up Interrupt */ + .long USB0_IRQHandler /* USB device */ + .long RTC_IRQHandler /* RTC alarm and wake-up interrupts */ + .long Reserved46_IRQHandler /* Reserved interrupt */ + .long MAILBOX_IRQHandler /* WAKEUP,Mailbox interrupt (present on selected devices) */ + .long PIN_INT4_IRQHandler /* Pin interrupt 4 or pattern match engine slice 4 int */ + .long PIN_INT5_IRQHandler /* Pin interrupt 5 or pattern match engine slice 5 int */ + .long PIN_INT6_IRQHandler /* Pin interrupt 6 or pattern match engine slice 6 int */ + .long PIN_INT7_IRQHandler /* Pin interrupt 7 or pattern match engine slice 7 int */ + .long CTIMER2_IRQHandler /* Standard counter/timer CTIMER2 */ + .long CTIMER4_IRQHandler /* Standard counter/timer CTIMER4 */ + .long OS_EVENT_IRQHandler /* OSEVTIMER0 and OSEVTIMER0_WAKEUP interrupts */ + .long Reserved55_IRQHandler /* Reserved interrupt */ + .long Reserved56_IRQHandler /* Reserved interrupt */ + .long Reserved57_IRQHandler /* Reserved interrupt */ + .long SDIO_IRQHandler /* SD/MMC */ + .long Reserved59_IRQHandler /* Reserved interrupt */ + .long Reserved60_IRQHandler /* Reserved interrupt */ + .long Reserved61_IRQHandler /* Reserved interrupt */ + .long USB1_UTMI_IRQHandler /* USB1_UTMI */ + .long USB1_IRQHandler /* USB1 interrupt */ + .long USB1_NEEDCLK_IRQHandler /* USB1 activity */ + .long SEC_HYPERVISOR_CALL_IRQHandler /* SEC_HYPERVISOR_CALL interrupt */ + .long SEC_GPIO_INT0_IRQ0_IRQHandler /* SEC_GPIO_INT0_IRQ0 interrupt */ + .long SEC_GPIO_INT0_IRQ1_IRQHandler /* SEC_GPIO_INT0_IRQ1 interrupt */ + .long PLU_IRQHandler /* PLU interrupt */ + .long SEC_VIO_IRQHandler /* SEC_VIO interrupt */ + .long HASHCRYPT_IRQHandler /* HASHCRYPT interrupt */ + .long CASER_IRQHandler /* CASPER interrupt */ + .long PUF_IRQHandler /* PUF interrupt */ + .long PQ_IRQHandler /* PQ interrupt */ + .long DMA1_IRQHandler /* DMA1 interrupt */ + .long FLEXCOMM8_IRQHandler /* Flexcomm Interface 8 (SPI, , FLEXCOMM) */ + + .size __Vectors, . - __Vectors + + .text + .thumb + +/* Reset Handler */ + .thumb_func + .align 2 + .globl Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: +#ifndef __NO_SYSTEM_INIT + ldr r0,=SystemInit + blx r0 +#endif +/* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * __etext: End of code section, i.e., begin of data sections to copy from. + * __data_start__/__data_end__: RAM address range that data should be + * copied to. Both must be aligned to 4 bytes boundary. */ + + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +#if 1 +/* Here are two copies of loop implemenations. First one favors code size + * and the second one favors performance. Default uses the first one. + * Change to "#if 0" to use the second one */ +.LC0: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .LC0 +#else + subs r3, r2 + ble .LC1 +.LC0: + subs r3, #4 + ldr r0, [r1, r3] + str r0, [r2, r3] + bgt .LC0 +.LC1: +#endif + +#ifdef __STARTUP_CLEAR_BSS +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * Loop to zero out BSS section, which uses following symbols + * in linker script: + * __bss_start__: start of BSS section. Must align to 4 + * __bss_end__: end of BSS section. Must align to 4 + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 +.LC2: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .LC2 +#endif /* __STARTUP_CLEAR_BSS */ + +/* Add stack / heap initializaiton */ + movs r0, 0 + ldr r1, =__HeapBase + ldr r2, =__HeapLimit +.LC3: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .LC3 + + ldr r1, =__StackLimit + ldr r2, =__StackTop +.LC4: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .LC4 +/*End of stack / heap initializaiton */ + cpsie i /* Unmask interrupts */ + +#ifndef __START +#define __START _start +#endif +#ifndef __ATOLLIC__ + ldr r0,=__START + blx r0 +#else + ldr r0,=__libc_init_array + blx r0 + ldr r0,=main + bx r0 +#endif + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak DefaultISR + .type DefaultISR, %function +DefaultISR: + b DefaultISR + .size DefaultISR, . - DefaultISR + + .align 1 + .thumb_func + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + ldr r0,=NMI_Handler + bx r0 + .size NMI_Handler, . - NMI_Handler + + .align 1 + .thumb_func + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + ldr r0,=HardFault_Handler + bx r0 + .size HardFault_Handler, . - HardFault_Handler + + .align 1 + .thumb_func + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + ldr r0,=SVC_Handler + bx r0 + .size SVC_Handler, . - SVC_Handler + + .align 1 + .thumb_func + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + ldr r0,=PendSV_Handler + bx r0 + .size PendSV_Handler, . - PendSV_Handler + + .align 1 + .thumb_func + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + ldr r0,=SysTick_Handler + bx r0 + .size SysTick_Handler, . - SysTick_Handler + + .align 1 + .thumb_func + .weak WDT_BOD_IRQHandler + .type WDT_BOD_IRQHandler, %function +WDT_BOD_IRQHandler: + ldr r0,=WDT_BOD_DriverIRQHandler + bx r0 + .size WDT_BOD_IRQHandler, . - WDT_BOD_IRQHandler + + .align 1 + .thumb_func + .weak DMA0_IRQHandler + .type DMA0_IRQHandler, %function +DMA0_IRQHandler: + ldr r0,=DMA0_DriverIRQHandler + bx r0 + .size DMA0_IRQHandler, . - DMA0_IRQHandler + + .align 1 + .thumb_func + .weak GINT0_IRQHandler + .type GINT0_IRQHandler, %function +GINT0_IRQHandler: + ldr r0,=GINT0_DriverIRQHandler + bx r0 + .size GINT0_IRQHandler, . - GINT0_IRQHandler + + .align 1 + .thumb_func + .weak GINT1_IRQHandler + .type GINT1_IRQHandler, %function +GINT1_IRQHandler: + ldr r0,=GINT1_DriverIRQHandler + bx r0 + .size GINT1_IRQHandler, . - GINT1_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT0_IRQHandler + .type PIN_INT0_IRQHandler, %function +PIN_INT0_IRQHandler: + ldr r0,=PIN_INT0_DriverIRQHandler + bx r0 + .size PIN_INT0_IRQHandler, . - PIN_INT0_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT1_IRQHandler + .type PIN_INT1_IRQHandler, %function +PIN_INT1_IRQHandler: + ldr r0,=PIN_INT1_DriverIRQHandler + bx r0 + .size PIN_INT1_IRQHandler, . - PIN_INT1_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT2_IRQHandler + .type PIN_INT2_IRQHandler, %function +PIN_INT2_IRQHandler: + ldr r0,=PIN_INT2_DriverIRQHandler + bx r0 + .size PIN_INT2_IRQHandler, . - PIN_INT2_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT3_IRQHandler + .type PIN_INT3_IRQHandler, %function +PIN_INT3_IRQHandler: + ldr r0,=PIN_INT3_DriverIRQHandler + bx r0 + .size PIN_INT3_IRQHandler, . - PIN_INT3_IRQHandler + + .align 1 + .thumb_func + .weak UTICK0_IRQHandler + .type UTICK0_IRQHandler, %function +UTICK0_IRQHandler: + ldr r0,=UTICK0_DriverIRQHandler + bx r0 + .size UTICK0_IRQHandler, . - UTICK0_IRQHandler + + .align 1 + .thumb_func + .weak MRT0_IRQHandler + .type MRT0_IRQHandler, %function +MRT0_IRQHandler: + ldr r0,=MRT0_DriverIRQHandler + bx r0 + .size MRT0_IRQHandler, . - MRT0_IRQHandler + + .align 1 + .thumb_func + .weak CTIMER0_IRQHandler + .type CTIMER0_IRQHandler, %function +CTIMER0_IRQHandler: + ldr r0,=CTIMER0_DriverIRQHandler + bx r0 + .size CTIMER0_IRQHandler, . - CTIMER0_IRQHandler + + .align 1 + .thumb_func + .weak CTIMER1_IRQHandler + .type CTIMER1_IRQHandler, %function +CTIMER1_IRQHandler: + ldr r0,=CTIMER1_DriverIRQHandler + bx r0 + .size CTIMER1_IRQHandler, . - CTIMER1_IRQHandler + + .align 1 + .thumb_func + .weak SCT0_IRQHandler + .type SCT0_IRQHandler, %function +SCT0_IRQHandler: + ldr r0,=SCT0_DriverIRQHandler + bx r0 + .size SCT0_IRQHandler, . - SCT0_IRQHandler + + .align 1 + .thumb_func + .weak CTIMER3_IRQHandler + .type CTIMER3_IRQHandler, %function +CTIMER3_IRQHandler: + ldr r0,=CTIMER3_DriverIRQHandler + bx r0 + .size CTIMER3_IRQHandler, . - CTIMER3_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM0_IRQHandler + .type FLEXCOMM0_IRQHandler, %function +FLEXCOMM0_IRQHandler: + ldr r0,=FLEXCOMM0_DriverIRQHandler + bx r0 + .size FLEXCOMM0_IRQHandler, . - FLEXCOMM0_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM1_IRQHandler + .type FLEXCOMM1_IRQHandler, %function +FLEXCOMM1_IRQHandler: + ldr r0,=FLEXCOMM1_DriverIRQHandler + bx r0 + .size FLEXCOMM1_IRQHandler, . - FLEXCOMM1_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM2_IRQHandler + .type FLEXCOMM2_IRQHandler, %function +FLEXCOMM2_IRQHandler: + ldr r0,=FLEXCOMM2_DriverIRQHandler + bx r0 + .size FLEXCOMM2_IRQHandler, . - FLEXCOMM2_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM3_IRQHandler + .type FLEXCOMM3_IRQHandler, %function +FLEXCOMM3_IRQHandler: + ldr r0,=FLEXCOMM3_DriverIRQHandler + bx r0 + .size FLEXCOMM3_IRQHandler, . - FLEXCOMM3_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM4_IRQHandler + .type FLEXCOMM4_IRQHandler, %function +FLEXCOMM4_IRQHandler: + ldr r0,=FLEXCOMM4_DriverIRQHandler + bx r0 + .size FLEXCOMM4_IRQHandler, . - FLEXCOMM4_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM5_IRQHandler + .type FLEXCOMM5_IRQHandler, %function +FLEXCOMM5_IRQHandler: + ldr r0,=FLEXCOMM5_DriverIRQHandler + bx r0 + .size FLEXCOMM5_IRQHandler, . - FLEXCOMM5_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM6_IRQHandler + .type FLEXCOMM6_IRQHandler, %function +FLEXCOMM6_IRQHandler: + ldr r0,=FLEXCOMM6_DriverIRQHandler + bx r0 + .size FLEXCOMM6_IRQHandler, . - FLEXCOMM6_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM7_IRQHandler + .type FLEXCOMM7_IRQHandler, %function +FLEXCOMM7_IRQHandler: + ldr r0,=FLEXCOMM7_DriverIRQHandler + bx r0 + .size FLEXCOMM7_IRQHandler, . - FLEXCOMM7_IRQHandler + + .align 1 + .thumb_func + .weak ADC0_IRQHandler + .type ADC0_IRQHandler, %function +ADC0_IRQHandler: + ldr r0,=ADC0_DriverIRQHandler + bx r0 + .size ADC0_IRQHandler, . - ADC0_IRQHandler + + .align 1 + .thumb_func + .weak Reserved39_IRQHandler + .type Reserved39_IRQHandler, %function +Reserved39_IRQHandler: + ldr r0,=Reserved39_DriverIRQHandler + bx r0 + .size Reserved39_IRQHandler, . - Reserved39_IRQHandler + + .align 1 + .thumb_func + .weak ACMP_IRQHandler + .type ACMP_IRQHandler, %function +ACMP_IRQHandler: + ldr r0,=ACMP_DriverIRQHandler + bx r0 + .size ACMP_IRQHandler, . - ACMP_IRQHandler + + .align 1 + .thumb_func + .weak Reserved41_IRQHandler + .type Reserved41_IRQHandler, %function +Reserved41_IRQHandler: + ldr r0,=Reserved41_DriverIRQHandler + bx r0 + .size Reserved41_IRQHandler, . - Reserved41_IRQHandler + + .align 1 + .thumb_func + .weak Reserved42_IRQHandler + .type Reserved42_IRQHandler, %function +Reserved42_IRQHandler: + ldr r0,=Reserved42_DriverIRQHandler + bx r0 + .size Reserved42_IRQHandler, . - Reserved42_IRQHandler + + .align 1 + .thumb_func + .weak USB0_NEEDCLK_IRQHandler + .type USB0_NEEDCLK_IRQHandler, %function +USB0_NEEDCLK_IRQHandler: + ldr r0,=USB0_NEEDCLK_DriverIRQHandler + bx r0 + .size USB0_NEEDCLK_IRQHandler, . - USB0_NEEDCLK_IRQHandler + + .align 1 + .thumb_func + .weak USB0_IRQHandler + .type USB0_IRQHandler, %function +USB0_IRQHandler: + ldr r0,=USB0_DriverIRQHandler + bx r0 + .size USB0_IRQHandler, . - USB0_IRQHandler + + .align 1 + .thumb_func + .weak RTC_IRQHandler + .type RTC_IRQHandler, %function +RTC_IRQHandler: + ldr r0,=RTC_DriverIRQHandler + bx r0 + .size RTC_IRQHandler, . - RTC_IRQHandler + + .align 1 + .thumb_func + .weak Reserved46_IRQHandler + .type Reserved46_IRQHandler, %function +Reserved46_IRQHandler: + ldr r0,=Reserved46_DriverIRQHandler + bx r0 + .size Reserved46_IRQHandler, . - Reserved46_IRQHandler + + .align 1 + .thumb_func + .weak MAILBOX_IRQHandler + .type MAILBOX_IRQHandler, %function +MAILBOX_IRQHandler: + ldr r0,=MAILBOX_DriverIRQHandler + bx r0 + .size MAILBOX_IRQHandler, . - MAILBOX_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT4_IRQHandler + .type PIN_INT4_IRQHandler, %function +PIN_INT4_IRQHandler: + ldr r0,=PIN_INT4_DriverIRQHandler + bx r0 + .size PIN_INT4_IRQHandler, . - PIN_INT4_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT5_IRQHandler + .type PIN_INT5_IRQHandler, %function +PIN_INT5_IRQHandler: + ldr r0,=PIN_INT5_DriverIRQHandler + bx r0 + .size PIN_INT5_IRQHandler, . - PIN_INT5_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT6_IRQHandler + .type PIN_INT6_IRQHandler, %function +PIN_INT6_IRQHandler: + ldr r0,=PIN_INT6_DriverIRQHandler + bx r0 + .size PIN_INT6_IRQHandler, . - PIN_INT6_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT7_IRQHandler + .type PIN_INT7_IRQHandler, %function +PIN_INT7_IRQHandler: + ldr r0,=PIN_INT7_DriverIRQHandler + bx r0 + .size PIN_INT7_IRQHandler, . - PIN_INT7_IRQHandler + + .align 1 + .thumb_func + .weak CTIMER2_IRQHandler + .type CTIMER2_IRQHandler, %function +CTIMER2_IRQHandler: + ldr r0,=CTIMER2_DriverIRQHandler + bx r0 + .size CTIMER2_IRQHandler, . - CTIMER2_IRQHandler + + .align 1 + .thumb_func + .weak CTIMER4_IRQHandler + .type CTIMER4_IRQHandler, %function +CTIMER4_IRQHandler: + ldr r0,=CTIMER4_DriverIRQHandler + bx r0 + .size CTIMER4_IRQHandler, . - CTIMER4_IRQHandler + + .align 1 + .thumb_func + .weak OS_EVENT_IRQHandler + .type OS_EVENT_IRQHandler, %function +OS_EVENT_IRQHandler: + ldr r0,=OS_EVENT_DriverIRQHandler + bx r0 + .size OS_EVENT_IRQHandler, . - OS_EVENT_IRQHandler + + .align 1 + .thumb_func + .weak Reserved55_IRQHandler + .type Reserved55_IRQHandler, %function +Reserved55_IRQHandler: + ldr r0,=Reserved55_DriverIRQHandler + bx r0 + .size Reserved55_IRQHandler, . - Reserved55_IRQHandler + + .align 1 + .thumb_func + .weak Reserved56_IRQHandler + .type Reserved56_IRQHandler, %function +Reserved56_IRQHandler: + ldr r0,=Reserved56_DriverIRQHandler + bx r0 + .size Reserved56_IRQHandler, . - Reserved56_IRQHandler + + .align 1 + .thumb_func + .weak Reserved57_IRQHandler + .type Reserved57_IRQHandler, %function +Reserved57_IRQHandler: + ldr r0,=Reserved57_DriverIRQHandler + bx r0 + .size Reserved57_IRQHandler, . - Reserved57_IRQHandler + + .align 1 + .thumb_func + .weak SDIO_IRQHandler + .type SDIO_IRQHandler, %function +SDIO_IRQHandler: + ldr r0,=SDIO_DriverIRQHandler + bx r0 + .size SDIO_IRQHandler, . - SDIO_IRQHandler + + .align 1 + .thumb_func + .weak Reserved59_IRQHandler + .type Reserved59_IRQHandler, %function +Reserved59_IRQHandler: + ldr r0,=Reserved59_DriverIRQHandler + bx r0 + .size Reserved59_IRQHandler, . - Reserved59_IRQHandler + + .align 1 + .thumb_func + .weak Reserved60_IRQHandler + .type Reserved60_IRQHandler, %function +Reserved60_IRQHandler: + ldr r0,=Reserved60_DriverIRQHandler + bx r0 + .size Reserved60_IRQHandler, . - Reserved60_IRQHandler + + .align 1 + .thumb_func + .weak Reserved61_IRQHandler + .type Reserved61_IRQHandler, %function +Reserved61_IRQHandler: + ldr r0,=Reserved61_DriverIRQHandler + bx r0 + .size Reserved61_IRQHandler, . - Reserved61_IRQHandler + + .align 1 + .thumb_func + .weak USB1_UTMI_IRQHandler + .type USB1_UTMI_IRQHandler, %function +USB1_UTMI_IRQHandler: + ldr r0,=USB1_UTMI_DriverIRQHandler + bx r0 + .size USB1_UTMI_IRQHandler, . - USB1_UTMI_IRQHandler + + .align 1 + .thumb_func + .weak USB1_IRQHandler + .type USB1_IRQHandler, %function +USB1_IRQHandler: + ldr r0,=USB1_DriverIRQHandler + bx r0 + .size USB1_IRQHandler, . - USB1_IRQHandler + + .align 1 + .thumb_func + .weak USB1_NEEDCLK_IRQHandler + .type USB1_NEEDCLK_IRQHandler, %function +USB1_NEEDCLK_IRQHandler: + ldr r0,=USB1_NEEDCLK_DriverIRQHandler + bx r0 + .size USB1_NEEDCLK_IRQHandler, . - USB1_NEEDCLK_IRQHandler + + .align 1 + .thumb_func + .weak SEC_HYPERVISOR_CALL_IRQHandler + .type SEC_HYPERVISOR_CALL_IRQHandler, %function +SEC_HYPERVISOR_CALL_IRQHandler: + ldr r0,=SEC_HYPERVISOR_CALL_DriverIRQHandler + bx r0 + .size SEC_HYPERVISOR_CALL_IRQHandler, . - SEC_HYPERVISOR_CALL_IRQHandler + + .align 1 + .thumb_func + .weak SEC_GPIO_INT0_IRQ0_IRQHandler + .type SEC_GPIO_INT0_IRQ0_IRQHandler, %function +SEC_GPIO_INT0_IRQ0_IRQHandler: + ldr r0,=SEC_GPIO_INT0_IRQ0_DriverIRQHandler + bx r0 + .size SEC_GPIO_INT0_IRQ0_IRQHandler, . - SEC_GPIO_INT0_IRQ0_IRQHandler + + .align 1 + .thumb_func + .weak SEC_GPIO_INT0_IRQ1_IRQHandler + .type SEC_GPIO_INT0_IRQ1_IRQHandler, %function +SEC_GPIO_INT0_IRQ1_IRQHandler: + ldr r0,=SEC_GPIO_INT0_IRQ1_DriverIRQHandler + bx r0 + .size SEC_GPIO_INT0_IRQ1_IRQHandler, . - SEC_GPIO_INT0_IRQ1_IRQHandler + + .align 1 + .thumb_func + .weak PLU_IRQHandler + .type PLU_IRQHandler, %function +PLU_IRQHandler: + ldr r0,=PLU_DriverIRQHandler + bx r0 + .size PLU_IRQHandler, . - PLU_IRQHandler + + .align 1 + .thumb_func + .weak SEC_VIO_IRQHandler + .type SEC_VIO_IRQHandler, %function +SEC_VIO_IRQHandler: + ldr r0,=SEC_VIO_DriverIRQHandler + bx r0 + .size SEC_VIO_IRQHandler, . - SEC_VIO_IRQHandler + + .align 1 + .thumb_func + .weak HASHCRYPT_IRQHandler + .type HASHCRYPT_IRQHandler, %function +HASHCRYPT_IRQHandler: + ldr r0,=HASHCRYPT_DriverIRQHandler + bx r0 + .size HASHCRYPT_IRQHandler, . - HASHCRYPT_IRQHandler + + .align 1 + .thumb_func + .weak CASER_IRQHandler + .type CASER_IRQHandler, %function +CASER_IRQHandler: + ldr r0,=CASER_DriverIRQHandler + bx r0 + .size CASER_IRQHandler, . - CASER_IRQHandler + + .align 1 + .thumb_func + .weak PUF_IRQHandler + .type PUF_IRQHandler, %function +PUF_IRQHandler: + ldr r0,=PUF_DriverIRQHandler + bx r0 + .size PUF_IRQHandler, . - PUF_IRQHandler + + .align 1 + .thumb_func + .weak PQ_IRQHandler + .type PQ_IRQHandler, %function +PQ_IRQHandler: + ldr r0,=PQ_DriverIRQHandler + bx r0 + .size PQ_IRQHandler, . - PQ_IRQHandler + + .align 1 + .thumb_func + .weak DMA1_IRQHandler + .type DMA1_IRQHandler, %function +DMA1_IRQHandler: + ldr r0,=DMA1_DriverIRQHandler + bx r0 + .size DMA1_IRQHandler, . - DMA1_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM8_IRQHandler + .type FLEXCOMM8_IRQHandler, %function +FLEXCOMM8_IRQHandler: + ldr r0,=FLEXCOMM8_DriverIRQHandler + bx r0 + .size FLEXCOMM8_IRQHandler, . - FLEXCOMM8_IRQHandler + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, DefaultISR + .endm +/* Exception Handlers */ + def_irq_handler MemManage_Handler + def_irq_handler BusFault_Handler + def_irq_handler UsageFault_Handler + def_irq_handler SecureFault_Handler + def_irq_handler DebugMon_Handler + def_irq_handler WDT_BOD_DriverIRQHandler + def_irq_handler DMA0_DriverIRQHandler + def_irq_handler GINT0_DriverIRQHandler + def_irq_handler GINT1_DriverIRQHandler + def_irq_handler PIN_INT0_DriverIRQHandler + def_irq_handler PIN_INT1_DriverIRQHandler + def_irq_handler PIN_INT2_DriverIRQHandler + def_irq_handler PIN_INT3_DriverIRQHandler + def_irq_handler UTICK0_DriverIRQHandler + def_irq_handler MRT0_DriverIRQHandler + def_irq_handler CTIMER0_DriverIRQHandler + def_irq_handler CTIMER1_DriverIRQHandler + def_irq_handler SCT0_DriverIRQHandler + def_irq_handler CTIMER3_DriverIRQHandler + def_irq_handler FLEXCOMM0_DriverIRQHandler + def_irq_handler FLEXCOMM1_DriverIRQHandler + def_irq_handler FLEXCOMM2_DriverIRQHandler + def_irq_handler FLEXCOMM3_DriverIRQHandler + def_irq_handler FLEXCOMM4_DriverIRQHandler + def_irq_handler FLEXCOMM5_DriverIRQHandler + def_irq_handler FLEXCOMM6_DriverIRQHandler + def_irq_handler FLEXCOMM7_DriverIRQHandler + def_irq_handler ADC0_DriverIRQHandler + def_irq_handler Reserved39_DriverIRQHandler + def_irq_handler ACMP_DriverIRQHandler + def_irq_handler Reserved41_DriverIRQHandler + def_irq_handler Reserved42_DriverIRQHandler + def_irq_handler USB0_NEEDCLK_DriverIRQHandler + def_irq_handler USB0_DriverIRQHandler + def_irq_handler RTC_DriverIRQHandler + def_irq_handler Reserved46_DriverIRQHandler + def_irq_handler MAILBOX_DriverIRQHandler + def_irq_handler PIN_INT4_DriverIRQHandler + def_irq_handler PIN_INT5_DriverIRQHandler + def_irq_handler PIN_INT6_DriverIRQHandler + def_irq_handler PIN_INT7_DriverIRQHandler + def_irq_handler CTIMER2_DriverIRQHandler + def_irq_handler CTIMER4_DriverIRQHandler + def_irq_handler OS_EVENT_DriverIRQHandler + def_irq_handler Reserved55_DriverIRQHandler + def_irq_handler Reserved56_DriverIRQHandler + def_irq_handler Reserved57_DriverIRQHandler + def_irq_handler SDIO_DriverIRQHandler + def_irq_handler Reserved59_DriverIRQHandler + def_irq_handler Reserved60_DriverIRQHandler + def_irq_handler Reserved61_DriverIRQHandler + def_irq_handler USB1_UTMI_DriverIRQHandler + def_irq_handler USB1_DriverIRQHandler + def_irq_handler USB1_NEEDCLK_DriverIRQHandler + def_irq_handler SEC_HYPERVISOR_CALL_DriverIRQHandler + def_irq_handler SEC_GPIO_INT0_IRQ0_DriverIRQHandler + def_irq_handler SEC_GPIO_INT0_IRQ1_DriverIRQHandler + def_irq_handler PLU_DriverIRQHandler + def_irq_handler SEC_VIO_DriverIRQHandler + def_irq_handler HASHCRYPT_DriverIRQHandler + def_irq_handler CASER_DriverIRQHandler + def_irq_handler PUF_DriverIRQHandler + def_irq_handler PQ_DriverIRQHandler + def_irq_handler DMA1_DriverIRQHandler + def_irq_handler FLEXCOMM8_DriverIRQHandler + + .end diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/iar/LPC55S69_cm33_core0_flash.icf b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/iar/LPC55S69_cm33_core0_flash.icf new file mode 100644 index 000000000..4d5f2e6ee --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/iar/LPC55S69_cm33_core0_flash.icf @@ -0,0 +1,111 @@ +/* +** ################################################################### +** Processors: LPC55S69JBD100_cm33_core0 +** LPC55S69JET98_cm33_core0 +** +** Compiler: IAR ANSI C/C++ Compiler for ARM +** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.2 15 Aug 2018 +** Version: rev. 1.0, 2018-08-22 +** Build: b180921 +** +** Abstract: +** Linker file for the IAR ANSI C/C++ Compiler for ARM +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + + +/* USB BDT size */ +define symbol usb_bdt_size = 0x0; +/* Stack and Heap Sizes */ +if (isdefinedsymbol(__stack_size__)) { + define symbol __size_cstack__ = __stack_size__; +} else { + define symbol __size_cstack__ = 0x0400; +} + +if (isdefinedsymbol(__heap_size__)) { + define symbol __size_heap__ = __heap_size__; +} else { + define symbol __size_heap__ = 0x0400; +} + +define symbol m_interrupts_start = 0x00000000; +define symbol m_interrupts_end = 0x0000013F; + +define symbol m_text_start = 0x00000140; +define symbol m_text_end = 0x00071FFF; + +define exported symbol core1_image_start = 0x00072000; +define exported symbol core1_image_end = 0x00097FFF; + +if (isdefinedsymbol(__use_shmem__)) { + define symbol m_data_start = 0x20000000; + define symbol m_data_end = 0x200317FF; + define exported symbol rpmsg_sh_mem_start = 0x20031800; + define exported symbol rpmsg_sh_mem_end = 0x20032FFF; +} else { + define symbol m_data_start = 0x20000000; + define symbol m_data_end = 0x20032FFF; +} + +define symbol m_usb_sram_start = 0x40100000; +define symbol m_usb_sram_end = 0x40103FFF; + +define memory mem with size = 4G; + +define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] + | mem:[from m_text_start to m_text_end]; +define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; +define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; +if (isdefinedsymbol(__use_shmem__)) { + define region rpmsg_sh_mem_region = mem:[from rpmsg_sh_mem_start to rpmsg_sh_mem_end]; +} + +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block RW { readwrite }; +define block ZI { zi }; + +define region core1_region = mem:[from core1_image_start to core1_image_end]; +define block SEC_CORE_IMAGE_BLOCK { section __sec_core }; + +/* regions for USB */ +define region USB_BDT_region = mem:[from m_usb_sram_start to m_usb_sram_start + usb_bdt_size - 1]; +define region USB_SRAM_region = mem:[from m_usb_sram_start + usb_bdt_size to m_usb_sram_end]; +place in USB_BDT_region { section m_usb_bdt }; +place in USB_SRAM_region { section m_usb_global }; + +initialize by copy { readwrite, section .textrw }; + +if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) +{ + /* Required in a multi-threaded application */ + initialize by copy with packing = none { section __DLIB_PERTHREAD }; +} + +do not initialize { section .noinit, section m_usb_bdt, section m_usb_global }; +if (isdefinedsymbol(__use_shmem__)) { + do not initialize { section rpmsg_sh_mem_section }; +} + +place at address mem: m_interrupts_start { readonly section .intvec }; +place in TEXT_region { readonly }; +place in DATA_region { block RW }; +place in DATA_region { block ZI }; +place in DATA_region { last block HEAP }; +place in CSTACK_region { block CSTACK }; +if (isdefinedsymbol(__use_shmem__)) { + place in rpmsg_sh_mem_region { section rpmsg_sh_mem_section }; +} +place in core1_region { block SEC_CORE_IMAGE_BLOCK }; + diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/iar/LPC55S69_cm33_core0_flash_ns.icf b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/iar/LPC55S69_cm33_core0_flash_ns.icf new file mode 100644 index 000000000..6f890542c --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/iar/LPC55S69_cm33_core0_flash_ns.icf @@ -0,0 +1,111 @@ +/* +** ################################################################### +** Processors: LPC55S69JBD100_cm33_core0 +** LPC55S69JET98_cm33_core0 +** +** Compiler: IAR ANSI C/C++ Compiler for ARM +** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.2 15 Aug 2018 +** Version: rev. 1.0, 2018-08-22 +** Build: b180921 +** +** Abstract: +** Linker file for the IAR ANSI C/C++ Compiler for ARM +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + + +/* USB BDT size */ +define symbol usb_bdt_size = 0x0; +/* Stack and Heap Sizes */ +if (isdefinedsymbol(__stack_size__)) { + define symbol __size_cstack__ = __stack_size__; +} else { + define symbol __size_cstack__ = 0x0400; +} + +if (isdefinedsymbol(__heap_size__)) { + define symbol __size_heap__ = __heap_size__; +} else { + define symbol __size_heap__ = 0x0400; +} + +define symbol m_interrupts_start = 0x00010000; +define symbol m_interrupts_end = 0x0001013F; + +define symbol m_text_start = 0x00010140; +define symbol m_text_end = 0x00071FFF; + +define exported symbol core1_image_start = 0x00072000; +define exported symbol core1_image_end = 0x00097FFF; + +if (isdefinedsymbol(__use_shmem__)) { + define symbol m_data_start = 0x20008000; + define symbol m_data_end = 0x2002FFFF; + define exported symbol rpmsg_sh_mem_start = 0x20031800; + define exported symbol rpmsg_sh_mem_end = 0x20032FFF; +} else { + define symbol m_data_start = 0x20008000; + define symbol m_data_end = 0x20032FFF; +} + +define symbol m_usb_sram_start = 0x40100000; +define symbol m_usb_sram_end = 0x40103FFF; + +define memory mem with size = 4G; + +define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] + | mem:[from m_text_start to m_text_end]; +define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; +define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; +if (isdefinedsymbol(__use_shmem__)) { + define region rpmsg_sh_mem_region = mem:[from rpmsg_sh_mem_start to rpmsg_sh_mem_end]; +} + +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block RW { readwrite }; +define block ZI { zi }; + +define region core1_region = mem:[from core1_image_start to core1_image_end]; +define block SEC_CORE_IMAGE_BLOCK { section __sec_core }; + +/* regions for USB */ +define region USB_BDT_region = mem:[from m_usb_sram_start to m_usb_sram_start + usb_bdt_size - 1]; +define region USB_SRAM_region = mem:[from m_usb_sram_start + usb_bdt_size to m_usb_sram_end]; +place in USB_BDT_region { section m_usb_bdt }; +place in USB_SRAM_region { section m_usb_global }; + +initialize by copy { readwrite, section .textrw }; + +if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) +{ + /* Required in a multi-threaded application */ + initialize by copy with packing = none { section __DLIB_PERTHREAD }; +} + +do not initialize { section .noinit, section m_usb_bdt, section m_usb_global }; +if (isdefinedsymbol(__use_shmem__)) { + do not initialize { section rpmsg_sh_mem_section }; +} + +place at address mem: m_interrupts_start { readonly section .intvec }; +place in TEXT_region { readonly }; +place in DATA_region { block RW }; +place in DATA_region { block ZI }; +place in DATA_region { last block HEAP }; +place in CSTACK_region { block CSTACK }; +if (isdefinedsymbol(__use_shmem__)) { + place in rpmsg_sh_mem_region { section rpmsg_sh_mem_section }; +} +place in core1_region { block SEC_CORE_IMAGE_BLOCK }; + diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/iar/LPC55S69_cm33_core0_flash_s.icf b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/iar/LPC55S69_cm33_core0_flash_s.icf new file mode 100644 index 000000000..2090bb801 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/iar/LPC55S69_cm33_core0_flash_s.icf @@ -0,0 +1,121 @@ +/* +** ################################################################### +** Processors: LPC55S69JBD100_cm33_core0 +** LPC55S69JET98_cm33_core0 +** +** Compiler: IAR ANSI C/C++ Compiler for ARM +** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.2 15 Aug 2018 +** Version: rev. 1.0, 2018-08-22 +** Build: b180921 +** +** Abstract: +** Linker file for the IAR ANSI C/C++ Compiler for ARM +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + + +/* USB BDT size */ +define symbol usb_bdt_size = 0x0; +/* Stack and Heap Sizes */ +if (isdefinedsymbol(__stack_size__)) { + define symbol __size_cstack__ = __stack_size__; +} else { + define symbol __size_cstack__ = 0x0400; +} + +if (isdefinedsymbol(__heap_size__)) { + define symbol __size_heap__ = __heap_size__; +} else { + define symbol __size_heap__ = 0x0400; +} + +/* Only the first 64kB of flash is used as secure memory. */ +define symbol m_interrupts_start = 0x10000000; +define symbol m_interrupts_end = 0x1000013F; + +define symbol m_text_start = 0x10000140; +define symbol m_text_end = 0x1000FDFF; + +define exported symbol core1_image_start = 0x00072000; +define exported symbol core1_image_end = 0x00097FFF; + +/* Only first 32kB of data RAM is used as secure memory. */ +if (isdefinedsymbol(__use_shmem__)) { + define symbol m_data_start = 0x30000000; + define symbol m_data_end = 0x30007FFF; + define exported symbol rpmsg_sh_mem_start = 0x30031800; + define exported symbol rpmsg_sh_mem_end = 0x30032FFF; +} else { + define symbol m_data_start = 0x30000000; + define symbol m_data_end = 0x30007FFF; +} + +/* 512B - memory for veneer table (NSC - secure, non-secure callable memory) */ +define symbol m_veneer_table_start = 0x1000FE00; +define symbol m_veneer_table_size = 0x200; + +define symbol m_usb_sram_start = 0x50100000; +define symbol m_usb_sram_end = 0x50103FFF; + +define memory mem with size = 4G; + +define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] + | mem:[from m_text_start to m_text_end]; +define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; +define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; +if (isdefinedsymbol(__use_shmem__)) { + define region rpmsg_sh_mem_region = mem:[from rpmsg_sh_mem_start to rpmsg_sh_mem_end]; +} + +define region VENEER_TABLE_region = mem:[from m_veneer_table_start to m_veneer_table_start + m_veneer_table_size - 1]; + +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block RW { readwrite }; +define block ZI { zi }; + +define region core1_region = mem:[from core1_image_start to core1_image_end]; +define block SEC_CORE_IMAGE_BLOCK { section __sec_core }; + +/* regions for USB */ +define region USB_BDT_region = mem:[from m_usb_sram_start to m_usb_sram_start + usb_bdt_size - 1]; +define region USB_SRAM_region = mem:[from m_usb_sram_start + usb_bdt_size to m_usb_sram_end]; +place in USB_BDT_region { section m_usb_bdt }; +place in USB_SRAM_region { section m_usb_global }; + +initialize by copy { readwrite, section .textrw }; + +if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) +{ + /* Required in a multi-threaded application */ + initialize by copy with packing = none { section __DLIB_PERTHREAD }; +} + +do not initialize { section .noinit, section m_usb_bdt, section m_usb_global }; +if (isdefinedsymbol(__use_shmem__)) { + do not initialize { section rpmsg_sh_mem_section }; +} + +place at address mem: m_interrupts_start { readonly section .intvec }; +place in TEXT_region { readonly }; +place in DATA_region { block RW }; +place in DATA_region { block ZI }; +place in DATA_region { last block HEAP }; +place in CSTACK_region { block CSTACK }; +place in VENEER_TABLE_region { section Veneer$$CMSE }; + +if (isdefinedsymbol(__use_shmem__)) { + place in rpmsg_sh_mem_region { section rpmsg_sh_mem_section }; +} +place in core1_region { block SEC_CORE_IMAGE_BLOCK }; + diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/iar/LPC55S69_cm33_core0_ram.icf b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/iar/LPC55S69_cm33_core0_ram.icf new file mode 100644 index 000000000..d76623985 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/iar/LPC55S69_cm33_core0_ram.icf @@ -0,0 +1,111 @@ +/* +** ################################################################### +** Processors: LPC55S69JBD100_cm33_core0 +** LPC55S69JET98_cm33_core0 +** +** Compiler: IAR ANSI C/C++ Compiler for ARM +** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.2 15 Aug 2018 +** Version: rev. 1.0, 2018-08-22 +** Build: b180921 +** +** Abstract: +** Linker file for the IAR ANSI C/C++ Compiler for ARM +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + + +/* USB BDT size */ +define symbol usb_bdt_size = 0x0; +/* Stack and Heap Sizes */ +if (isdefinedsymbol(__stack_size__)) { + define symbol __size_cstack__ = __stack_size__; +} else { + define symbol __size_cstack__ = 0x0400; +} + +if (isdefinedsymbol(__heap_size__)) { + define symbol __size_heap__ = __heap_size__; +} else { + define symbol __size_heap__ = 0x0400; +} + +define symbol m_interrupts_start = 0x04000000; +define symbol m_interrupts_end = 0x0400013F; + +define symbol m_text_start = 0x04000140; +define symbol m_text_end = 0x04007FFF; + +define exported symbol core1_image_start = 0x20033000; +define exported symbol core1_image_end = 0x2003B7FF; + +if (isdefinedsymbol(__use_shmem__)) { + define symbol m_data_start = 0x20000000; + define symbol m_data_end = 0x200317FF; + define exported symbol rpmsg_sh_mem_start = 0x20031800; + define exported symbol rpmsg_sh_mem_end = 0x20032FFF; +} else { + define symbol m_data_start = 0x20000000; + define symbol m_data_end = 0x20032FFF; +} + +define symbol m_usb_sram_start = 0x40100000; +define symbol m_usb_sram_end = 0x40103FFF; + +define memory mem with size = 4G; + +define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] + | mem:[from m_text_start to m_text_end]; +define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; +define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; +if (isdefinedsymbol(__use_shmem__)) { + define region rpmsg_sh_mem_region = mem:[from rpmsg_sh_mem_start to rpmsg_sh_mem_end]; +} + +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block RW { readwrite }; +define block ZI { zi }; + +define region core1_region = mem:[from core1_image_start to core1_image_end]; +define block SEC_CORE_IMAGE_BLOCK { section __sec_core }; + +/* regions for USB */ +define region USB_BDT_region = mem:[from m_usb_sram_start to m_usb_sram_start + usb_bdt_size - 1]; +define region USB_SRAM_region = mem:[from m_usb_sram_start + usb_bdt_size to m_usb_sram_end]; +place in USB_BDT_region { section m_usb_bdt }; +place in USB_SRAM_region { section m_usb_global }; + +initialize by copy { readwrite, section .textrw }; + +if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) +{ + /* Required in a multi-threaded application */ + initialize by copy with packing = none { section __DLIB_PERTHREAD }; +} + +do not initialize { section .noinit, section m_usb_bdt, section m_usb_global }; +if (isdefinedsymbol(__use_shmem__)) { + do not initialize { section rpmsg_sh_mem_section }; +} + +place at address mem: m_interrupts_start { readonly section .intvec }; +place in TEXT_region { readonly }; +place in DATA_region { block RW }; +place in DATA_region { block ZI }; +place in DATA_region { last block HEAP }; +place in CSTACK_region { block CSTACK }; +if (isdefinedsymbol(__use_shmem__)) { + place in rpmsg_sh_mem_region { section rpmsg_sh_mem_section }; +} +place in core1_region { block SEC_CORE_IMAGE_BLOCK }; + diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/iar/LPC55S69_cm33_core1_flash.icf b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/iar/LPC55S69_cm33_core1_flash.icf new file mode 100644 index 000000000..bbd8748a6 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/iar/LPC55S69_cm33_core1_flash.icf @@ -0,0 +1,104 @@ +/* +** ################################################################### +** Processors: LPC55S69JBD100_cm33_core1 +** LPC55S69JET98_cm33_core1 +** +** Compiler: IAR ANSI C/C++ Compiler for ARM +** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.2 15 Aug 2018 +** Version: rev. 1.0, 2018-08-22 +** Build: b180921 +** +** Abstract: +** Linker file for the IAR ANSI C/C++ Compiler for ARM +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + + +/* USB BDT size */ +define symbol usb_bdt_size = 0x0; +/* Stack and Heap Sizes */ +if (isdefinedsymbol(__stack_size__)) { + define symbol __size_cstack__ = __stack_size__; +} else { + define symbol __size_cstack__ = 0x0400; +} + +if (isdefinedsymbol(__heap_size__)) { + define symbol __size_heap__ = __heap_size__; +} else { + define symbol __size_heap__ = 0x0400; +} + +define symbol m_interrupts_start = 0x00072000; +define symbol m_interrupts_end = 0x0007213F; + +define symbol m_text_start = 0x00072140; +define symbol m_text_end = 0x00097FFF; + + +define symbol m_data_start = 0x20033000; +define symbol m_data_end = 0x20043FFF; + +if (isdefinedsymbol(__use_shmem__)) { + define exported symbol rpmsg_sh_mem_start = 0x20031800; + define exported symbol rpmsg_sh_mem_end = 0x20032FFF; +} + +define symbol m_usb_sram_start = 0x40100000; +define symbol m_usb_sram_end = 0x40103FFF; + +define memory mem with size = 4G; + +define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] + | mem:[from m_text_start to m_text_end]; +define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; +define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; +if (isdefinedsymbol(__use_shmem__)) { + define region rpmsg_sh_mem_region = mem:[from rpmsg_sh_mem_start to rpmsg_sh_mem_end]; +} + +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block RW { readwrite }; +define block ZI { zi }; + + +/* regions for USB */ +define region USB_BDT_region = mem:[from m_usb_sram_start to m_usb_sram_start + usb_bdt_size - 1]; +define region USB_SRAM_region = mem:[from m_usb_sram_start + usb_bdt_size to m_usb_sram_end]; +place in USB_BDT_region { section m_usb_bdt }; +place in USB_SRAM_region { section m_usb_global }; + +initialize by copy { readwrite, section .textrw }; + +if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) +{ + /* Required in a multi-threaded application */ + initialize by copy with packing = none { section __DLIB_PERTHREAD }; +} + +do not initialize { section .noinit, section m_usb_bdt, section m_usb_global }; +if (isdefinedsymbol(__use_shmem__)) { + do not initialize { section rpmsg_sh_mem_section }; +} + +place at address mem: m_interrupts_start { readonly section .intvec }; +place in TEXT_region { readonly }; +place in DATA_region { block RW }; +place in DATA_region { block ZI }; +place in DATA_region { last block HEAP }; +place in CSTACK_region { block CSTACK }; +if (isdefinedsymbol(__use_shmem__)) { + place in rpmsg_sh_mem_region { section rpmsg_sh_mem_section }; +} + diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/iar/LPC55S69_cm33_core1_ram.icf b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/iar/LPC55S69_cm33_core1_ram.icf new file mode 100644 index 000000000..661476cab --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/iar/LPC55S69_cm33_core1_ram.icf @@ -0,0 +1,104 @@ +/* +** ################################################################### +** Processors: LPC55S69JBD100_cm33_core1 +** LPC55S69JET98_cm33_core1 +** +** Compiler: IAR ANSI C/C++ Compiler for ARM +** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.2 15 Aug 2018 +** Version: rev. 1.0, 2018-08-22 +** Build: b180921 +** +** Abstract: +** Linker file for the IAR ANSI C/C++ Compiler for ARM +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + + +/* USB BDT size */ +define symbol usb_bdt_size = 0x0; +/* Stack and Heap Sizes */ +if (isdefinedsymbol(__stack_size__)) { + define symbol __size_cstack__ = __stack_size__; +} else { + define symbol __size_cstack__ = 0x0400; +} + +if (isdefinedsymbol(__heap_size__)) { + define symbol __size_heap__ = __heap_size__; +} else { + define symbol __size_heap__ = 0x0400; +} + +define symbol m_interrupts_start = 0x20033000; +define symbol m_interrupts_end = 0x2003313F; + +define symbol m_text_start = 0x20033140; +define symbol m_text_end = 0x2003E7FF; + + +define symbol m_data_start = 0x2003E800; +define symbol m_data_end = 0x20043FFF; + +if (isdefinedsymbol(__use_shmem__)) { + define exported symbol rpmsg_sh_mem_start = 0x20031800; + define exported symbol rpmsg_sh_mem_end = 0x20032FFF; +} + +define symbol m_usb_sram_start = 0x40100000; +define symbol m_usb_sram_end = 0x40103FFF; + +define memory mem with size = 4G; + +define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] + | mem:[from m_text_start to m_text_end]; +define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; +define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; +if (isdefinedsymbol(__use_shmem__)) { + define region rpmsg_sh_mem_region = mem:[from rpmsg_sh_mem_start to rpmsg_sh_mem_end]; +} + +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block RW { readwrite }; +define block ZI { zi }; + + +/* regions for USB */ +define region USB_BDT_region = mem:[from m_usb_sram_start to m_usb_sram_start + usb_bdt_size - 1]; +define region USB_SRAM_region = mem:[from m_usb_sram_start + usb_bdt_size to m_usb_sram_end]; +place in USB_BDT_region { section m_usb_bdt }; +place in USB_SRAM_region { section m_usb_global }; + +initialize by copy { readwrite, section .textrw }; + +if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) +{ + /* Required in a multi-threaded application */ + initialize by copy with packing = none { section __DLIB_PERTHREAD }; +} + +do not initialize { section .noinit, section m_usb_bdt, section m_usb_global }; +if (isdefinedsymbol(__use_shmem__)) { + do not initialize { section rpmsg_sh_mem_section }; +} + +place at address mem: m_interrupts_start { readonly section .intvec }; +place in TEXT_region { readonly }; +place in DATA_region { block RW }; +place in DATA_region { block ZI }; +place in DATA_region { last block HEAP }; +place in CSTACK_region { block CSTACK }; +if (isdefinedsymbol(__use_shmem__)) { + place in rpmsg_sh_mem_region { section rpmsg_sh_mem_section }; +} + diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/iar/LPC55S69_cm33_core1_ram_s.icf b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/iar/LPC55S69_cm33_core1_ram_s.icf new file mode 100644 index 000000000..3591babb5 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/iar/LPC55S69_cm33_core1_ram_s.icf @@ -0,0 +1,104 @@ +/* +** ################################################################### +** Processors: LPC55S69JBD100_cm33_core1 +** LPC55S69JET98_cm33_core1 +** +** Compiler: IAR ANSI C/C++ Compiler for ARM +** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.2 15 Aug 2018 +** Version: rev. 1.0, 2018-08-22 +** Build: b180921 +** +** Abstract: +** Linker file for the IAR ANSI C/C++ Compiler for ARM +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + + +/* USB BDT size */ +define symbol usb_bdt_size = 0x0; +/* Stack and Heap Sizes */ +if (isdefinedsymbol(__stack_size__)) { + define symbol __size_cstack__ = __stack_size__; +} else { + define symbol __size_cstack__ = 0x0400; +} + +if (isdefinedsymbol(__heap_size__)) { + define symbol __size_heap__ = __heap_size__; +} else { + define symbol __size_heap__ = 0x0400; +} + +define symbol m_interrupts_start = 0x30033000; +define symbol m_interrupts_end = 0x3003313F; + +define symbol m_text_start = 0x30033140; +define symbol m_text_end = 0x3003E7FF; + + +define symbol m_data_start = 0x3003E800; +define symbol m_data_end = 0x30043FFF; + +if (isdefinedsymbol(__use_shmem__)) { + define exported symbol rpmsg_sh_mem_start = 0x30031800; + define exported symbol rpmsg_sh_mem_end = 0x30032FFF; +} + +define symbol m_usb_sram_start = 0x50100000; +define symbol m_usb_sram_end = 0x50103FFF; + +define memory mem with size = 4G; + +define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] + | mem:[from m_text_start to m_text_end]; +define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; +define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; +if (isdefinedsymbol(__use_shmem__)) { + define region rpmsg_sh_mem_region = mem:[from rpmsg_sh_mem_start to rpmsg_sh_mem_end]; +} + +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block RW { readwrite }; +define block ZI { zi }; + + +/* regions for USB */ +define region USB_BDT_region = mem:[from m_usb_sram_start to m_usb_sram_start + usb_bdt_size - 1]; +define region USB_SRAM_region = mem:[from m_usb_sram_start + usb_bdt_size to m_usb_sram_end]; +place in USB_BDT_region { section m_usb_bdt }; +place in USB_SRAM_region { section m_usb_global }; + +initialize by copy { readwrite, section .textrw }; + +if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) +{ + /* Required in a multi-threaded application */ + initialize by copy with packing = none { section __DLIB_PERTHREAD }; +} + +do not initialize { section .noinit, section m_usb_bdt, section m_usb_global }; +if (isdefinedsymbol(__use_shmem__)) { + do not initialize { section rpmsg_sh_mem_section }; +} + +place at address mem: m_interrupts_start { readonly section .intvec }; +place in TEXT_region { readonly }; +place in DATA_region { block RW }; +place in DATA_region { block ZI }; +place in DATA_region { last block HEAP }; +place in CSTACK_region { block CSTACK }; +if (isdefinedsymbol(__use_shmem__)) { + place in rpmsg_sh_mem_region { section rpmsg_sh_mem_section }; +} + diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/iar/iar_lib_power_cm33_core0.a b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/iar/iar_lib_power_cm33_core0.a new file mode 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zKF3}O^jh_N8K%c`5PC-YmFS8y)%Q;5&1SqElkBbf9D6TAZ#ModK_w0U#2N{kGx>K7 z^k!o(EZJN0IsOeo56kao()9K_DcQp|L!_DfI}5$p^slXWs=noty>H{*q#t>)Sc9I2 zZ>FX1gJ(;!A?PL4 + +//#define SYSCON_BASE ((uint32_t) 0x40000000) +#define SYSCON_BASE ((uint32_t) 0x50000000) + +#define CPBOOT (((volatile uint32_t *) (SYSCON_BASE + 0x804))) +#define CPUCTRL (((volatile uint32_t *) (SYSCON_BASE + 0x800))) +#define CPUCFG (((volatile uint32_t *) (SYSCON_BASE + 0xFD4))) + +#define CPUCTRL_KEY ((uint32_t)(0x0000C0C4 << 16)) +#define CORE1_CLK_ENA (1<<3) +#define CORE1_RESET_ENA (1<<5) +#define CORE1_ENABLE (1 <<2) + + +extern uint8_t __core_m33slave_START__; + +void boot_multicore_slave(void) { + + volatile uint32_t *u32REG, u32Val; + + unsigned int *slavevectortable_ptr = + (uint32_t *) &__core_m33slave_START__; + + // Enable CPU1 in SYSCON->CPUCFG + *CPUCFG |= CORE1_ENABLE; + + // Set CPU1 boot address in SYSCON->CPBoot + *CPBOOT = (uint32_t) slavevectortable_ptr; + + // Read SYSCON->CPUCTRL and set key value in bits 31:16 + u32REG = (uint32_t *) CPUCTRL; + u32Val = *u32REG | CPUCTRL_KEY; + + // Enable slave clock and reset in SYSCON->CPUCTRL + *u32REG = u32Val | CORE1_CLK_ENA | CORE1_RESET_ENA; + + // Clear slave reset in SYSCON->CPUCTRL + *u32REG = (u32Val | CORE1_CLK_ENA) & (~CORE1_RESET_ENA); + +} +#endif //defined (__MULTICORE_MASTER) diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/mcuxpresso/boot_multicore_slave.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/mcuxpresso/boot_multicore_slave.h new file mode 100644 index 000000000..2e1f9761a --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/mcuxpresso/boot_multicore_slave.h @@ -0,0 +1,46 @@ +//***************************************************************************** +// boot_multicore_slave.h +// +// Header for functions used for booting of slave core in multicore system +//***************************************************************************** +// +// Copyright 2014, NXP +// All rights reserved. +// +// Software that is described herein is for illustrative purposes only +// which provides customers with programming information regarding the +// LPC products. This software is supplied "AS IS" without any warranties of +// any kind, and NXP Semiconductors and its licensor disclaim any and +// all warranties, express or implied, including all implied warranties of +// merchantability, fitness for a particular purpose and non-infringement of +// intellectual property rights. NXP Semiconductors assumes no responsibility +// or liability for the use of the software, conveys no license or rights under any +// patent, copyright, mask work right, or any other intellectual property rights in +// or to any products. NXP Semiconductors reserves the right to make changes +// in the software without notification. NXP Semiconductors also makes no +// representation or warranty that such application will be suitable for the +// specified use without further testing or modification. +// +// Permission to use, copy, modify, and distribute this software and its +// documentation is hereby granted, under NXP Semiconductors' and its +// licensor's relevant copyrights in the software, without fee, provided that it +// is used in conjunction with NXP Semiconductors microcontrollers. This +// copyright, permission, and disclaimer notice must appear in all copies of +// this code. +//***************************************************************************** + +#ifndef BOOT_MULTICORE_SLAVE_H_ +#define BOOT_MULTICORE_SLAVE_H_ + +#ifdef __cplusplus +extern "C" +{ +#endif + +void boot_multicore_slave(void); + +#ifdef __cplusplus +} +#endif + +#endif /* BOOT_MULTICORE_SLAVE_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/mcuxpresso/startup_lpc55s69_cm33_core0.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/mcuxpresso/startup_lpc55s69_cm33_core0.c new file mode 100644 index 000000000..6227ec529 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/mcuxpresso/startup_lpc55s69_cm33_core0.c @@ -0,0 +1,744 @@ +//***************************************************************************** +// LPC55S69_cm33_core0 startup code for use with MCUXpresso IDE +// +// Version : 240619 +//***************************************************************************** +// +// Copyright 2016-2019 NXP +// All rights reserved. +// +// SPDX-License-Identifier: BSD-3-Clause +//***************************************************************************** + +#if defined (DEBUG) +#pragma GCC push_options +#pragma GCC optimize ("Og") +#endif // (DEBUG) + +#if defined (__cplusplus) +#ifdef __REDLIB__ +#error Redlib does not support C++ +#else +//***************************************************************************** +// +// The entry point for the C++ library startup +// +//***************************************************************************** +extern "C" { + extern void __libc_init_array(void); +} +#endif +#endif + +#define WEAK __attribute__ ((weak)) +#define WEAK_AV __attribute__ ((weak, section(".after_vectors"))) +#define ALIAS(f) __attribute__ ((weak, alias (#f))) + +//***************************************************************************** +#if defined (__cplusplus) +extern "C" { +#endif + +//***************************************************************************** +// Variable to store CRP value in. Will be placed automatically +// by the linker when "Enable Code Read Protect" selected. +// See crp.h header for more information +//***************************************************************************** +//***************************************************************************** +// Declaration of external SystemInit function +//***************************************************************************** +#if defined (__USE_CMSIS) +extern void SystemInit(void); +#endif // (__USE_CMSIS) + +//***************************************************************************** +// Forward declaration of the core exception handlers. +// When the application defines a handler (with the same name), this will +// automatically take precedence over these weak definitions. +// If your application is a C++ one, then any interrupt handlers defined +// in C++ files within in your main application will need to have C linkage +// rather than C++ linkage. To do this, make sure that you are using extern "C" +// { .... } around the interrupt handler within your main application code. +//***************************************************************************** + void ResetISR(void); +WEAK void NMI_Handler(void); +WEAK void HardFault_Handler(void); +WEAK void MemManage_Handler(void); +WEAK void BusFault_Handler(void); +WEAK void UsageFault_Handler(void); +WEAK void SecureFault_Handler(void); +WEAK void SVC_Handler(void); +WEAK void DebugMon_Handler(void); +WEAK void PendSV_Handler(void); +WEAK void SysTick_Handler(void); +WEAK void IntDefaultHandler(void); + +//***************************************************************************** +// Forward declaration of the application IRQ handlers. When the application +// defines a handler (with the same name), this will automatically take +// precedence over weak definitions below +//***************************************************************************** +WEAK void WDT_BOD_IRQHandler(void); +WEAK void DMA0_IRQHandler(void); +WEAK void GINT0_IRQHandler(void); +WEAK void GINT1_IRQHandler(void); +WEAK void PIN_INT0_IRQHandler(void); +WEAK void PIN_INT1_IRQHandler(void); +WEAK void PIN_INT2_IRQHandler(void); +WEAK void PIN_INT3_IRQHandler(void); +WEAK void UTICK0_IRQHandler(void); +WEAK void MRT0_IRQHandler(void); +WEAK void CTIMER0_IRQHandler(void); +WEAK void CTIMER1_IRQHandler(void); +WEAK void SCT0_IRQHandler(void); +WEAK void CTIMER3_IRQHandler(void); +WEAK void FLEXCOMM0_IRQHandler(void); +WEAK void FLEXCOMM1_IRQHandler(void); +WEAK void FLEXCOMM2_IRQHandler(void); +WEAK void FLEXCOMM3_IRQHandler(void); +WEAK void FLEXCOMM4_IRQHandler(void); +WEAK void FLEXCOMM5_IRQHandler(void); +WEAK void FLEXCOMM6_IRQHandler(void); +WEAK void FLEXCOMM7_IRQHandler(void); +WEAK void ADC0_IRQHandler(void); +WEAK void Reserved39_IRQHandler(void); +WEAK void ACMP_IRQHandler(void); +WEAK void Reserved41_IRQHandler(void); +WEAK void Reserved42_IRQHandler(void); +WEAK void USB0_NEEDCLK_IRQHandler(void); +WEAK void USB0_IRQHandler(void); +WEAK void RTC_IRQHandler(void); +WEAK void Reserved46_IRQHandler(void); +WEAK void MAILBOX_IRQHandler(void); +WEAK void PIN_INT4_IRQHandler(void); +WEAK void PIN_INT5_IRQHandler(void); +WEAK void PIN_INT6_IRQHandler(void); +WEAK void PIN_INT7_IRQHandler(void); +WEAK void CTIMER2_IRQHandler(void); +WEAK void CTIMER4_IRQHandler(void); +WEAK void OS_EVENT_IRQHandler(void); +WEAK void Reserved55_IRQHandler(void); +WEAK void Reserved56_IRQHandler(void); +WEAK void Reserved57_IRQHandler(void); +WEAK void SDIO_IRQHandler(void); +WEAK void Reserved59_IRQHandler(void); +WEAK void Reserved60_IRQHandler(void); +WEAK void Reserved61_IRQHandler(void); +WEAK void USB1_UTMI_IRQHandler(void); +WEAK void USB1_IRQHandler(void); +WEAK void USB1_NEEDCLK_IRQHandler(void); +WEAK void SEC_HYPERVISOR_CALL_IRQHandler(void); +WEAK void SEC_GPIO_INT0_IRQ0_IRQHandler(void); +WEAK void SEC_GPIO_INT0_IRQ1_IRQHandler(void); +WEAK void PLU_IRQHandler(void); +WEAK void SEC_VIO_IRQHandler(void); +WEAK void HASHCRYPT_IRQHandler(void); +WEAK void CASER_IRQHandler(void); +WEAK void PUF_IRQHandler(void); +WEAK void PQ_IRQHandler(void); +WEAK void DMA1_IRQHandler(void); +WEAK void FLEXCOMM8_IRQHandler(void); + +//***************************************************************************** +// Forward declaration of the driver IRQ handlers. These are aliased +// to the IntDefaultHandler, which is a 'forever' loop. When the driver +// defines a handler (with the same name), this will automatically take +// precedence over these weak definitions +//***************************************************************************** +void WDT_BOD_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void DMA0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GINT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GINT1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PIN_INT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PIN_INT1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PIN_INT2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PIN_INT3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void UTICK0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void MRT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CTIMER0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CTIMER1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SCT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CTIMER3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXCOMM0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXCOMM1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXCOMM2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXCOMM3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXCOMM4_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXCOMM5_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXCOMM6_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXCOMM7_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ADC0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved39_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ACMP_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved41_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved42_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void USB0_NEEDCLK_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void USB0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void RTC_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved46_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void MAILBOX_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PIN_INT4_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PIN_INT5_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PIN_INT6_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PIN_INT7_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CTIMER2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CTIMER4_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void OS_EVENT_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved55_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved56_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved57_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SDIO_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved59_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved60_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved61_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void USB1_UTMI_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void USB1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void USB1_NEEDCLK_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SEC_HYPERVISOR_CALL_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SEC_GPIO_INT0_IRQ0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SEC_GPIO_INT0_IRQ1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PLU_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SEC_VIO_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void HASHCRYPT_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CASER_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PUF_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PQ_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void DMA1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXCOMM8_DriverIRQHandler(void) ALIAS(IntDefaultHandler); + +//***************************************************************************** +// The entry point for the application. +// __main() is the entry point for Redlib based applications +// main() is the entry point for Newlib based applications +//***************************************************************************** +#if defined (__REDLIB__) +extern void __main(void); +#endif +extern int main(void); + +//***************************************************************************** +// External declaration for the pointer to the stack top from the Linker Script +//***************************************************************************** +extern void _vStackTop(void); +//***************************************************************************** +// External declaration for LPC MCU vector table checksum from Linker Script +//***************************************************************************** +WEAK extern void __valid_user_code_checksum(); + +//***************************************************************************** +//***************************************************************************** +#if defined (__cplusplus) +} // extern "C" +#endif +//***************************************************************************** +// The vector table. +// This relies on the linker script to place at correct location in memory. +//***************************************************************************** +extern void (* const g_pfnVectors[])(void); +extern void * __Vectors __attribute__ ((alias ("g_pfnVectors"))); + +__attribute__ ((used, section(".isr_vector"))) +void (* const g_pfnVectors[])(void) = { + // Core Level - CM33 + &_vStackTop, // The initial stack pointer + ResetISR, // The reset handler + NMI_Handler, // The NMI handler + HardFault_Handler, // The hard fault handler + MemManage_Handler, // The MPU fault handler + BusFault_Handler, // The bus fault handler + UsageFault_Handler, // The usage fault handler + SecureFault_Handler, // The secure fault handler + 0, // ECRP + 0, // Reserved + 0, // Reserved + SVC_Handler, // SVCall handler + DebugMon_Handler, // Debug monitor handler + 0, // Reserved + PendSV_Handler, // The PendSV handler + SysTick_Handler, // The SysTick handler + + // Chip Level - LPC55S69_cm33_core0 + WDT_BOD_IRQHandler, // 16: Windowed watchdog timer, Brownout detect, Flash interrupt + DMA0_IRQHandler, // 17: DMA0 controller + GINT0_IRQHandler, // 18: GPIO group 0 + GINT1_IRQHandler, // 19: GPIO group 1 + PIN_INT0_IRQHandler, // 20: Pin interrupt 0 or pattern match engine slice 0 + PIN_INT1_IRQHandler, // 21: Pin interrupt 1or pattern match engine slice 1 + PIN_INT2_IRQHandler, // 22: Pin interrupt 2 or pattern match engine slice 2 + PIN_INT3_IRQHandler, // 23: Pin interrupt 3 or pattern match engine slice 3 + UTICK0_IRQHandler, // 24: Micro-tick Timer + MRT0_IRQHandler, // 25: Multi-rate timer + CTIMER0_IRQHandler, // 26: Standard counter/timer CTIMER0 + CTIMER1_IRQHandler, // 27: Standard counter/timer CTIMER1 + SCT0_IRQHandler, // 28: SCTimer/PWM + CTIMER3_IRQHandler, // 29: Standard counter/timer CTIMER3 + FLEXCOMM0_IRQHandler, // 30: Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) + FLEXCOMM1_IRQHandler, // 31: Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) + FLEXCOMM2_IRQHandler, // 32: Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) + FLEXCOMM3_IRQHandler, // 33: Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) + FLEXCOMM4_IRQHandler, // 34: Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) + FLEXCOMM5_IRQHandler, // 35: Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) + FLEXCOMM6_IRQHandler, // 36: Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) + FLEXCOMM7_IRQHandler, // 37: Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) + ADC0_IRQHandler, // 38: ADC0 + Reserved39_IRQHandler, // 39: Reserved interrupt + ACMP_IRQHandler, // 40: ACMP interrupts + Reserved41_IRQHandler, // 41: Reserved interrupt + Reserved42_IRQHandler, // 42: Reserved interrupt + USB0_NEEDCLK_IRQHandler, // 43: USB Activity Wake-up Interrupt + USB0_IRQHandler, // 44: USB device + RTC_IRQHandler, // 45: RTC alarm and wake-up interrupts + Reserved46_IRQHandler, // 46: Reserved interrupt + MAILBOX_IRQHandler, // 47: WAKEUP,Mailbox interrupt (present on selected devices) + PIN_INT4_IRQHandler, // 48: Pin interrupt 4 or pattern match engine slice 4 int + PIN_INT5_IRQHandler, // 49: Pin interrupt 5 or pattern match engine slice 5 int + PIN_INT6_IRQHandler, // 50: Pin interrupt 6 or pattern match engine slice 6 int + PIN_INT7_IRQHandler, // 51: Pin interrupt 7 or pattern match engine slice 7 int + CTIMER2_IRQHandler, // 52: Standard counter/timer CTIMER2 + CTIMER4_IRQHandler, // 53: Standard counter/timer CTIMER4 + OS_EVENT_IRQHandler, // 54: OSEVTIMER0 and OSEVTIMER0_WAKEUP interrupts + Reserved55_IRQHandler, // 55: Reserved interrupt + Reserved56_IRQHandler, // 56: Reserved interrupt + Reserved57_IRQHandler, // 57: Reserved interrupt + SDIO_IRQHandler, // 58: SD/MMC + Reserved59_IRQHandler, // 59: Reserved interrupt + Reserved60_IRQHandler, // 60: Reserved interrupt + Reserved61_IRQHandler, // 61: Reserved interrupt + USB1_UTMI_IRQHandler, // 62: USB1_UTMI + USB1_IRQHandler, // 63: USB1 interrupt + USB1_NEEDCLK_IRQHandler, // 64: USB1 activity + SEC_HYPERVISOR_CALL_IRQHandler, // 65: SEC_HYPERVISOR_CALL interrupt + SEC_GPIO_INT0_IRQ0_IRQHandler, // 66: SEC_GPIO_INT0_IRQ0 interrupt + SEC_GPIO_INT0_IRQ1_IRQHandler, // 67: SEC_GPIO_INT0_IRQ1 interrupt + PLU_IRQHandler, // 68: PLU interrupt + SEC_VIO_IRQHandler, // 69: SEC_VIO interrupt + HASHCRYPT_IRQHandler, // 70: HASHCRYPT interrupt + CASER_IRQHandler, // 71: CASPER interrupt + PUF_IRQHandler, // 72: PUF interrupt + PQ_IRQHandler, // 73: PQ interrupt + DMA1_IRQHandler, // 74: DMA1 interrupt + FLEXCOMM8_IRQHandler, // 75: Flexcomm Interface 8 (SPI, , FLEXCOMM) + +}; /* End of g_pfnVectors */ + +//***************************************************************************** +// Functions to carry out the initialization of RW and BSS data sections. These +// are written as separate functions rather than being inlined within the +// ResetISR() function in order to cope with MCUs with multiple banks of +// memory. +//***************************************************************************** +__attribute__ ((section(".after_vectors.init_data"))) +void data_init(unsigned int romstart, unsigned int start, unsigned int len) { + unsigned int *pulDest = (unsigned int*) start; + unsigned int *pulSrc = (unsigned int*) romstart; + unsigned int loop; + for (loop = 0; loop < len; loop = loop + 4) + *pulDest++ = *pulSrc++; +} + +__attribute__ ((section(".after_vectors.init_bss"))) +void bss_init(unsigned int start, unsigned int len) { + unsigned int *pulDest = (unsigned int*) start; + unsigned int loop; + for (loop = 0; loop < len; loop = loop + 4) + *pulDest++ = 0; +} + +//***************************************************************************** +// The following symbols are constructs generated by the linker, indicating +// the location of various points in the "Global Section Table". This table is +// created by the linker via the Code Red managed linker script mechanism. It +// contains the load address, execution address and length of each RW data +// section and the execution and length of each BSS (zero initialized) section. +//***************************************************************************** +extern unsigned int __data_section_table; +extern unsigned int __data_section_table_end; +extern unsigned int __bss_section_table; +extern unsigned int __bss_section_table_end; + +//***************************************************************************** +// Reset entry point for your code. +// Sets up a simple runtime environment and initializes the C/C++ +// library. +//***************************************************************************** +__attribute__ ((section(".after_vectors.reset"))) +void ResetISR(void) { + + // Disable interrupts + __asm volatile ("cpsid i"); + + + +#if defined (__USE_CMSIS) +// If __USE_CMSIS defined, then call CMSIS SystemInit code + SystemInit(); + +#endif // (__USE_CMSIS) + + // + // Copy the data sections from flash to SRAM. + // + unsigned int LoadAddr, ExeAddr, SectionLen; + unsigned int *SectionTableAddr; + + // Load base address of Global Section Table + SectionTableAddr = &__data_section_table; + + // Copy the data sections from flash to SRAM. + while (SectionTableAddr < &__data_section_table_end) { + LoadAddr = *SectionTableAddr++; + ExeAddr = *SectionTableAddr++; + SectionLen = *SectionTableAddr++; + data_init(LoadAddr, ExeAddr, SectionLen); + } + + // At this point, SectionTableAddr = &__bss_section_table; + // Zero fill the bss segment + while (SectionTableAddr < &__bss_section_table_end) { + ExeAddr = *SectionTableAddr++; + SectionLen = *SectionTableAddr++; + bss_init(ExeAddr, SectionLen); + } + + +#if !defined (__USE_CMSIS) +// Assume that if __USE_CMSIS defined, then CMSIS SystemInit code +// will setup the VTOR register + + // Check to see if we are running the code from a non-zero + // address (eg RAM, external flash), in which case we need + // to modify the VTOR register to tell the CPU that the + // vector table is located at a non-0x0 address. + unsigned int * pSCB_VTOR = (unsigned int *) 0xE000ED08; + if ((unsigned int *)g_pfnVectors!=(unsigned int *) 0x00000000) { + *pSCB_VTOR = (unsigned int)g_pfnVectors; + } +#endif // (__USE_CMSIS) +#if defined (__cplusplus) + // + // Call C++ library initialisation + // + __libc_init_array(); +#endif + + // Reenable interrupts + __asm volatile ("cpsie i"); + +#if defined (__REDLIB__) + // Call the Redlib library, which in turn calls main() + __main(); +#else + main(); +#endif + + // + // main() shouldn't return, but if it does, we'll just enter an infinite loop + // + while (1) { + ; + } +} + +//***************************************************************************** +// Default core exception handlers. Override the ones here by defining your own +// handler routines in your application code. +//***************************************************************************** +WEAK_AV void NMI_Handler(void) +{ while(1) {} +} + +WEAK_AV void HardFault_Handler(void) +{ while(1) {} +} + +WEAK_AV void MemManage_Handler(void) +{ while(1) {} +} + +WEAK_AV void BusFault_Handler(void) +{ while(1) {} +} + +WEAK_AV void UsageFault_Handler(void) +{ while(1) {} +} + +WEAK_AV void SecureFault_Handler(void) +{ while(1) {} +} + +WEAK_AV void SVC_Handler(void) +{ while(1) {} +} + +WEAK_AV void DebugMon_Handler(void) +{ while(1) {} +} + +WEAK_AV void PendSV_Handler(void) +{ while(1) {} +} + +WEAK_AV void SysTick_Handler(void) +{ while(1) {} +} + +//***************************************************************************** +// Processor ends up here if an unexpected interrupt occurs or a specific +// handler is not present in the application code. +//***************************************************************************** +WEAK_AV void IntDefaultHandler(void) +{ while(1) {} +} + +//***************************************************************************** +// Default application exception handlers. Override the ones here by defining +// your own handler routines in your application code. These routines call +// driver exception handlers or IntDefaultHandler() if no driver exception +// handler is included. +//***************************************************************************** +WEAK void WDT_BOD_IRQHandler(void) +{ WDT_BOD_DriverIRQHandler(); +} + +WEAK void DMA0_IRQHandler(void) +{ DMA0_DriverIRQHandler(); +} + +WEAK void GINT0_IRQHandler(void) +{ GINT0_DriverIRQHandler(); +} + +WEAK void GINT1_IRQHandler(void) +{ GINT1_DriverIRQHandler(); +} + +WEAK void PIN_INT0_IRQHandler(void) +{ PIN_INT0_DriverIRQHandler(); +} + +WEAK void PIN_INT1_IRQHandler(void) +{ PIN_INT1_DriverIRQHandler(); +} + +WEAK void PIN_INT2_IRQHandler(void) +{ PIN_INT2_DriverIRQHandler(); +} + +WEAK void PIN_INT3_IRQHandler(void) +{ PIN_INT3_DriverIRQHandler(); +} + +WEAK void UTICK0_IRQHandler(void) +{ UTICK0_DriverIRQHandler(); +} + +WEAK void MRT0_IRQHandler(void) +{ MRT0_DriverIRQHandler(); +} + +WEAK void CTIMER0_IRQHandler(void) +{ CTIMER0_DriverIRQHandler(); +} + +WEAK void CTIMER1_IRQHandler(void) +{ CTIMER1_DriverIRQHandler(); +} + +WEAK void SCT0_IRQHandler(void) +{ SCT0_DriverIRQHandler(); +} + +WEAK void CTIMER3_IRQHandler(void) +{ CTIMER3_DriverIRQHandler(); +} + +WEAK void FLEXCOMM0_IRQHandler(void) +{ FLEXCOMM0_DriverIRQHandler(); +} + +WEAK void FLEXCOMM1_IRQHandler(void) +{ FLEXCOMM1_DriverIRQHandler(); +} + +WEAK void FLEXCOMM2_IRQHandler(void) +{ FLEXCOMM2_DriverIRQHandler(); +} + +WEAK void FLEXCOMM3_IRQHandler(void) +{ FLEXCOMM3_DriverIRQHandler(); +} + +WEAK void FLEXCOMM4_IRQHandler(void) +{ FLEXCOMM4_DriverIRQHandler(); +} + +WEAK void FLEXCOMM5_IRQHandler(void) +{ FLEXCOMM5_DriverIRQHandler(); +} + +WEAK void FLEXCOMM6_IRQHandler(void) +{ FLEXCOMM6_DriverIRQHandler(); +} + +WEAK void FLEXCOMM7_IRQHandler(void) +{ FLEXCOMM7_DriverIRQHandler(); +} + +WEAK void ADC0_IRQHandler(void) +{ ADC0_DriverIRQHandler(); +} + +WEAK void Reserved39_IRQHandler(void) +{ Reserved39_DriverIRQHandler(); +} + +WEAK void ACMP_IRQHandler(void) +{ ACMP_DriverIRQHandler(); +} + +WEAK void Reserved41_IRQHandler(void) +{ Reserved41_DriverIRQHandler(); +} + +WEAK void Reserved42_IRQHandler(void) +{ Reserved42_DriverIRQHandler(); +} + +WEAK void USB0_NEEDCLK_IRQHandler(void) +{ USB0_NEEDCLK_DriverIRQHandler(); +} + +WEAK void USB0_IRQHandler(void) +{ USB0_DriverIRQHandler(); +} + +WEAK void RTC_IRQHandler(void) +{ RTC_DriverIRQHandler(); +} + +WEAK void Reserved46_IRQHandler(void) +{ Reserved46_DriverIRQHandler(); +} + +WEAK void MAILBOX_IRQHandler(void) +{ MAILBOX_DriverIRQHandler(); +} + +WEAK void PIN_INT4_IRQHandler(void) +{ PIN_INT4_DriverIRQHandler(); +} + +WEAK void PIN_INT5_IRQHandler(void) +{ PIN_INT5_DriverIRQHandler(); +} + +WEAK void PIN_INT6_IRQHandler(void) +{ PIN_INT6_DriverIRQHandler(); +} + +WEAK void PIN_INT7_IRQHandler(void) +{ PIN_INT7_DriverIRQHandler(); +} + +WEAK void CTIMER2_IRQHandler(void) +{ CTIMER2_DriverIRQHandler(); +} + +WEAK void CTIMER4_IRQHandler(void) +{ CTIMER4_DriverIRQHandler(); +} + +WEAK void OS_EVENT_IRQHandler(void) +{ OS_EVENT_DriverIRQHandler(); +} + +WEAK void Reserved55_IRQHandler(void) +{ Reserved55_DriverIRQHandler(); +} + +WEAK void Reserved56_IRQHandler(void) +{ Reserved56_DriverIRQHandler(); +} + +WEAK void Reserved57_IRQHandler(void) +{ Reserved57_DriverIRQHandler(); +} + +WEAK void SDIO_IRQHandler(void) +{ SDIO_DriverIRQHandler(); +} + +WEAK void Reserved59_IRQHandler(void) +{ Reserved59_DriverIRQHandler(); +} + +WEAK void Reserved60_IRQHandler(void) +{ Reserved60_DriverIRQHandler(); +} + +WEAK void Reserved61_IRQHandler(void) +{ Reserved61_DriverIRQHandler(); +} + +WEAK void USB1_UTMI_IRQHandler(void) +{ USB1_UTMI_DriverIRQHandler(); +} + +WEAK void USB1_IRQHandler(void) +{ USB1_DriverIRQHandler(); +} + +WEAK void USB1_NEEDCLK_IRQHandler(void) +{ USB1_NEEDCLK_DriverIRQHandler(); +} + +WEAK void SEC_HYPERVISOR_CALL_IRQHandler(void) +{ SEC_HYPERVISOR_CALL_DriverIRQHandler(); +} + +WEAK void SEC_GPIO_INT0_IRQ0_IRQHandler(void) +{ SEC_GPIO_INT0_IRQ0_DriverIRQHandler(); +} + +WEAK void SEC_GPIO_INT0_IRQ1_IRQHandler(void) +{ SEC_GPIO_INT0_IRQ1_DriverIRQHandler(); +} + +WEAK void PLU_IRQHandler(void) +{ PLU_DriverIRQHandler(); +} + +WEAK void SEC_VIO_IRQHandler(void) +{ SEC_VIO_DriverIRQHandler(); +} + +WEAK void HASHCRYPT_IRQHandler(void) +{ HASHCRYPT_DriverIRQHandler(); +} + +WEAK void CASER_IRQHandler(void) +{ CASER_DriverIRQHandler(); +} + +WEAK void PUF_IRQHandler(void) +{ PUF_DriverIRQHandler(); +} + +WEAK void PQ_IRQHandler(void) +{ PQ_DriverIRQHandler(); +} + +WEAK void DMA1_IRQHandler(void) +{ DMA1_DriverIRQHandler(); +} + +WEAK void FLEXCOMM8_IRQHandler(void) +{ FLEXCOMM8_DriverIRQHandler(); +} + +//***************************************************************************** + +#if defined (DEBUG) +#pragma GCC pop_options +#endif // (DEBUG) diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/mcuxpresso/startup_lpc55s69_cm33_core0.cpp b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/mcuxpresso/startup_lpc55s69_cm33_core0.cpp new file mode 100644 index 000000000..6227ec529 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/mcuxpresso/startup_lpc55s69_cm33_core0.cpp @@ -0,0 +1,744 @@ +//***************************************************************************** +// LPC55S69_cm33_core0 startup code for use with MCUXpresso IDE +// +// Version : 240619 +//***************************************************************************** +// +// Copyright 2016-2019 NXP +// All rights reserved. +// +// SPDX-License-Identifier: BSD-3-Clause +//***************************************************************************** + +#if defined (DEBUG) +#pragma GCC push_options +#pragma GCC optimize ("Og") +#endif // (DEBUG) + +#if defined (__cplusplus) +#ifdef __REDLIB__ +#error Redlib does not support C++ +#else +//***************************************************************************** +// +// The entry point for the C++ library startup +// +//***************************************************************************** +extern "C" { + extern void __libc_init_array(void); +} +#endif +#endif + +#define WEAK __attribute__ ((weak)) +#define WEAK_AV __attribute__ ((weak, section(".after_vectors"))) +#define ALIAS(f) __attribute__ ((weak, alias (#f))) + +//***************************************************************************** +#if defined (__cplusplus) +extern "C" { +#endif + +//***************************************************************************** +// Variable to store CRP value in. Will be placed automatically +// by the linker when "Enable Code Read Protect" selected. +// See crp.h header for more information +//***************************************************************************** +//***************************************************************************** +// Declaration of external SystemInit function +//***************************************************************************** +#if defined (__USE_CMSIS) +extern void SystemInit(void); +#endif // (__USE_CMSIS) + +//***************************************************************************** +// Forward declaration of the core exception handlers. +// When the application defines a handler (with the same name), this will +// automatically take precedence over these weak definitions. +// If your application is a C++ one, then any interrupt handlers defined +// in C++ files within in your main application will need to have C linkage +// rather than C++ linkage. To do this, make sure that you are using extern "C" +// { .... } around the interrupt handler within your main application code. +//***************************************************************************** + void ResetISR(void); +WEAK void NMI_Handler(void); +WEAK void HardFault_Handler(void); +WEAK void MemManage_Handler(void); +WEAK void BusFault_Handler(void); +WEAK void UsageFault_Handler(void); +WEAK void SecureFault_Handler(void); +WEAK void SVC_Handler(void); +WEAK void DebugMon_Handler(void); +WEAK void PendSV_Handler(void); +WEAK void SysTick_Handler(void); +WEAK void IntDefaultHandler(void); + +//***************************************************************************** +// Forward declaration of the application IRQ handlers. When the application +// defines a handler (with the same name), this will automatically take +// precedence over weak definitions below +//***************************************************************************** +WEAK void WDT_BOD_IRQHandler(void); +WEAK void DMA0_IRQHandler(void); +WEAK void GINT0_IRQHandler(void); +WEAK void GINT1_IRQHandler(void); +WEAK void PIN_INT0_IRQHandler(void); +WEAK void PIN_INT1_IRQHandler(void); +WEAK void PIN_INT2_IRQHandler(void); +WEAK void PIN_INT3_IRQHandler(void); +WEAK void UTICK0_IRQHandler(void); +WEAK void MRT0_IRQHandler(void); +WEAK void CTIMER0_IRQHandler(void); +WEAK void CTIMER1_IRQHandler(void); +WEAK void SCT0_IRQHandler(void); +WEAK void CTIMER3_IRQHandler(void); +WEAK void FLEXCOMM0_IRQHandler(void); +WEAK void FLEXCOMM1_IRQHandler(void); +WEAK void FLEXCOMM2_IRQHandler(void); +WEAK void FLEXCOMM3_IRQHandler(void); +WEAK void FLEXCOMM4_IRQHandler(void); +WEAK void FLEXCOMM5_IRQHandler(void); +WEAK void FLEXCOMM6_IRQHandler(void); +WEAK void FLEXCOMM7_IRQHandler(void); +WEAK void ADC0_IRQHandler(void); +WEAK void Reserved39_IRQHandler(void); +WEAK void ACMP_IRQHandler(void); +WEAK void Reserved41_IRQHandler(void); +WEAK void Reserved42_IRQHandler(void); +WEAK void USB0_NEEDCLK_IRQHandler(void); +WEAK void USB0_IRQHandler(void); +WEAK void RTC_IRQHandler(void); +WEAK void Reserved46_IRQHandler(void); +WEAK void MAILBOX_IRQHandler(void); +WEAK void PIN_INT4_IRQHandler(void); +WEAK void PIN_INT5_IRQHandler(void); +WEAK void PIN_INT6_IRQHandler(void); +WEAK void PIN_INT7_IRQHandler(void); +WEAK void CTIMER2_IRQHandler(void); +WEAK void CTIMER4_IRQHandler(void); +WEAK void OS_EVENT_IRQHandler(void); +WEAK void Reserved55_IRQHandler(void); +WEAK void Reserved56_IRQHandler(void); +WEAK void Reserved57_IRQHandler(void); +WEAK void SDIO_IRQHandler(void); +WEAK void Reserved59_IRQHandler(void); +WEAK void Reserved60_IRQHandler(void); +WEAK void Reserved61_IRQHandler(void); +WEAK void USB1_UTMI_IRQHandler(void); +WEAK void USB1_IRQHandler(void); +WEAK void USB1_NEEDCLK_IRQHandler(void); +WEAK void SEC_HYPERVISOR_CALL_IRQHandler(void); +WEAK void SEC_GPIO_INT0_IRQ0_IRQHandler(void); +WEAK void SEC_GPIO_INT0_IRQ1_IRQHandler(void); +WEAK void PLU_IRQHandler(void); +WEAK void SEC_VIO_IRQHandler(void); +WEAK void HASHCRYPT_IRQHandler(void); +WEAK void CASER_IRQHandler(void); +WEAK void PUF_IRQHandler(void); +WEAK void PQ_IRQHandler(void); +WEAK void DMA1_IRQHandler(void); +WEAK void FLEXCOMM8_IRQHandler(void); + +//***************************************************************************** +// Forward declaration of the driver IRQ handlers. These are aliased +// to the IntDefaultHandler, which is a 'forever' loop. When the driver +// defines a handler (with the same name), this will automatically take +// precedence over these weak definitions +//***************************************************************************** +void WDT_BOD_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void DMA0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GINT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GINT1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PIN_INT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PIN_INT1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PIN_INT2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PIN_INT3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void UTICK0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void MRT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CTIMER0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CTIMER1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SCT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CTIMER3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXCOMM0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXCOMM1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXCOMM2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXCOMM3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXCOMM4_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXCOMM5_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXCOMM6_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXCOMM7_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ADC0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved39_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ACMP_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved41_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved42_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void USB0_NEEDCLK_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void USB0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void RTC_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved46_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void MAILBOX_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PIN_INT4_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PIN_INT5_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PIN_INT6_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PIN_INT7_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CTIMER2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CTIMER4_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void OS_EVENT_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved55_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved56_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved57_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SDIO_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved59_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved60_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved61_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void USB1_UTMI_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void USB1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void USB1_NEEDCLK_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SEC_HYPERVISOR_CALL_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SEC_GPIO_INT0_IRQ0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SEC_GPIO_INT0_IRQ1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PLU_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SEC_VIO_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void HASHCRYPT_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CASER_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PUF_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PQ_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void DMA1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXCOMM8_DriverIRQHandler(void) ALIAS(IntDefaultHandler); + +//***************************************************************************** +// The entry point for the application. +// __main() is the entry point for Redlib based applications +// main() is the entry point for Newlib based applications +//***************************************************************************** +#if defined (__REDLIB__) +extern void __main(void); +#endif +extern int main(void); + +//***************************************************************************** +// External declaration for the pointer to the stack top from the Linker Script +//***************************************************************************** +extern void _vStackTop(void); +//***************************************************************************** +// External declaration for LPC MCU vector table checksum from Linker Script +//***************************************************************************** +WEAK extern void __valid_user_code_checksum(); + +//***************************************************************************** +//***************************************************************************** +#if defined (__cplusplus) +} // extern "C" +#endif +//***************************************************************************** +// The vector table. +// This relies on the linker script to place at correct location in memory. +//***************************************************************************** +extern void (* const g_pfnVectors[])(void); +extern void * __Vectors __attribute__ ((alias ("g_pfnVectors"))); + +__attribute__ ((used, section(".isr_vector"))) +void (* const g_pfnVectors[])(void) = { + // Core Level - CM33 + &_vStackTop, // The initial stack pointer + ResetISR, // The reset handler + NMI_Handler, // The NMI handler + HardFault_Handler, // The hard fault handler + MemManage_Handler, // The MPU fault handler + BusFault_Handler, // The bus fault handler + UsageFault_Handler, // The usage fault handler + SecureFault_Handler, // The secure fault handler + 0, // ECRP + 0, // Reserved + 0, // Reserved + SVC_Handler, // SVCall handler + DebugMon_Handler, // Debug monitor handler + 0, // Reserved + PendSV_Handler, // The PendSV handler + SysTick_Handler, // The SysTick handler + + // Chip Level - LPC55S69_cm33_core0 + WDT_BOD_IRQHandler, // 16: Windowed watchdog timer, Brownout detect, Flash interrupt + DMA0_IRQHandler, // 17: DMA0 controller + GINT0_IRQHandler, // 18: GPIO group 0 + GINT1_IRQHandler, // 19: GPIO group 1 + PIN_INT0_IRQHandler, // 20: Pin interrupt 0 or pattern match engine slice 0 + PIN_INT1_IRQHandler, // 21: Pin interrupt 1or pattern match engine slice 1 + PIN_INT2_IRQHandler, // 22: Pin interrupt 2 or pattern match engine slice 2 + PIN_INT3_IRQHandler, // 23: Pin interrupt 3 or pattern match engine slice 3 + UTICK0_IRQHandler, // 24: Micro-tick Timer + MRT0_IRQHandler, // 25: Multi-rate timer + CTIMER0_IRQHandler, // 26: Standard counter/timer CTIMER0 + CTIMER1_IRQHandler, // 27: Standard counter/timer CTIMER1 + SCT0_IRQHandler, // 28: SCTimer/PWM + CTIMER3_IRQHandler, // 29: Standard counter/timer CTIMER3 + FLEXCOMM0_IRQHandler, // 30: Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) + FLEXCOMM1_IRQHandler, // 31: Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) + FLEXCOMM2_IRQHandler, // 32: Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) + FLEXCOMM3_IRQHandler, // 33: Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) + FLEXCOMM4_IRQHandler, // 34: Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) + FLEXCOMM5_IRQHandler, // 35: Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) + FLEXCOMM6_IRQHandler, // 36: Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) + FLEXCOMM7_IRQHandler, // 37: Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) + ADC0_IRQHandler, // 38: ADC0 + Reserved39_IRQHandler, // 39: Reserved interrupt + ACMP_IRQHandler, // 40: ACMP interrupts + Reserved41_IRQHandler, // 41: Reserved interrupt + Reserved42_IRQHandler, // 42: Reserved interrupt + USB0_NEEDCLK_IRQHandler, // 43: USB Activity Wake-up Interrupt + USB0_IRQHandler, // 44: USB device + RTC_IRQHandler, // 45: RTC alarm and wake-up interrupts + Reserved46_IRQHandler, // 46: Reserved interrupt + MAILBOX_IRQHandler, // 47: WAKEUP,Mailbox interrupt (present on selected devices) + PIN_INT4_IRQHandler, // 48: Pin interrupt 4 or pattern match engine slice 4 int + PIN_INT5_IRQHandler, // 49: Pin interrupt 5 or pattern match engine slice 5 int + PIN_INT6_IRQHandler, // 50: Pin interrupt 6 or pattern match engine slice 6 int + PIN_INT7_IRQHandler, // 51: Pin interrupt 7 or pattern match engine slice 7 int + CTIMER2_IRQHandler, // 52: Standard counter/timer CTIMER2 + CTIMER4_IRQHandler, // 53: Standard counter/timer CTIMER4 + OS_EVENT_IRQHandler, // 54: OSEVTIMER0 and OSEVTIMER0_WAKEUP interrupts + Reserved55_IRQHandler, // 55: Reserved interrupt + Reserved56_IRQHandler, // 56: Reserved interrupt + Reserved57_IRQHandler, // 57: Reserved interrupt + SDIO_IRQHandler, // 58: SD/MMC + Reserved59_IRQHandler, // 59: Reserved interrupt + Reserved60_IRQHandler, // 60: Reserved interrupt + Reserved61_IRQHandler, // 61: Reserved interrupt + USB1_UTMI_IRQHandler, // 62: USB1_UTMI + USB1_IRQHandler, // 63: USB1 interrupt + USB1_NEEDCLK_IRQHandler, // 64: USB1 activity + SEC_HYPERVISOR_CALL_IRQHandler, // 65: SEC_HYPERVISOR_CALL interrupt + SEC_GPIO_INT0_IRQ0_IRQHandler, // 66: SEC_GPIO_INT0_IRQ0 interrupt + SEC_GPIO_INT0_IRQ1_IRQHandler, // 67: SEC_GPIO_INT0_IRQ1 interrupt + PLU_IRQHandler, // 68: PLU interrupt + SEC_VIO_IRQHandler, // 69: SEC_VIO interrupt + HASHCRYPT_IRQHandler, // 70: HASHCRYPT interrupt + CASER_IRQHandler, // 71: CASPER interrupt + PUF_IRQHandler, // 72: PUF interrupt + PQ_IRQHandler, // 73: PQ interrupt + DMA1_IRQHandler, // 74: DMA1 interrupt + FLEXCOMM8_IRQHandler, // 75: Flexcomm Interface 8 (SPI, , FLEXCOMM) + +}; /* End of g_pfnVectors */ + +//***************************************************************************** +// Functions to carry out the initialization of RW and BSS data sections. These +// are written as separate functions rather than being inlined within the +// ResetISR() function in order to cope with MCUs with multiple banks of +// memory. +//***************************************************************************** +__attribute__ ((section(".after_vectors.init_data"))) +void data_init(unsigned int romstart, unsigned int start, unsigned int len) { + unsigned int *pulDest = (unsigned int*) start; + unsigned int *pulSrc = (unsigned int*) romstart; + unsigned int loop; + for (loop = 0; loop < len; loop = loop + 4) + *pulDest++ = *pulSrc++; +} + +__attribute__ ((section(".after_vectors.init_bss"))) +void bss_init(unsigned int start, unsigned int len) { + unsigned int *pulDest = (unsigned int*) start; + unsigned int loop; + for (loop = 0; loop < len; loop = loop + 4) + *pulDest++ = 0; +} + +//***************************************************************************** +// The following symbols are constructs generated by the linker, indicating +// the location of various points in the "Global Section Table". This table is +// created by the linker via the Code Red managed linker script mechanism. It +// contains the load address, execution address and length of each RW data +// section and the execution and length of each BSS (zero initialized) section. +//***************************************************************************** +extern unsigned int __data_section_table; +extern unsigned int __data_section_table_end; +extern unsigned int __bss_section_table; +extern unsigned int __bss_section_table_end; + +//***************************************************************************** +// Reset entry point for your code. +// Sets up a simple runtime environment and initializes the C/C++ +// library. +//***************************************************************************** +__attribute__ ((section(".after_vectors.reset"))) +void ResetISR(void) { + + // Disable interrupts + __asm volatile ("cpsid i"); + + + +#if defined (__USE_CMSIS) +// If __USE_CMSIS defined, then call CMSIS SystemInit code + SystemInit(); + +#endif // (__USE_CMSIS) + + // + // Copy the data sections from flash to SRAM. + // + unsigned int LoadAddr, ExeAddr, SectionLen; + unsigned int *SectionTableAddr; + + // Load base address of Global Section Table + SectionTableAddr = &__data_section_table; + + // Copy the data sections from flash to SRAM. + while (SectionTableAddr < &__data_section_table_end) { + LoadAddr = *SectionTableAddr++; + ExeAddr = *SectionTableAddr++; + SectionLen = *SectionTableAddr++; + data_init(LoadAddr, ExeAddr, SectionLen); + } + + // At this point, SectionTableAddr = &__bss_section_table; + // Zero fill the bss segment + while (SectionTableAddr < &__bss_section_table_end) { + ExeAddr = *SectionTableAddr++; + SectionLen = *SectionTableAddr++; + bss_init(ExeAddr, SectionLen); + } + + +#if !defined (__USE_CMSIS) +// Assume that if __USE_CMSIS defined, then CMSIS SystemInit code +// will setup the VTOR register + + // Check to see if we are running the code from a non-zero + // address (eg RAM, external flash), in which case we need + // to modify the VTOR register to tell the CPU that the + // vector table is located at a non-0x0 address. + unsigned int * pSCB_VTOR = (unsigned int *) 0xE000ED08; + if ((unsigned int *)g_pfnVectors!=(unsigned int *) 0x00000000) { + *pSCB_VTOR = (unsigned int)g_pfnVectors; + } +#endif // (__USE_CMSIS) +#if defined (__cplusplus) + // + // Call C++ library initialisation + // + __libc_init_array(); +#endif + + // Reenable interrupts + __asm volatile ("cpsie i"); + +#if defined (__REDLIB__) + // Call the Redlib library, which in turn calls main() + __main(); +#else + main(); +#endif + + // + // main() shouldn't return, but if it does, we'll just enter an infinite loop + // + while (1) { + ; + } +} + +//***************************************************************************** +// Default core exception handlers. Override the ones here by defining your own +// handler routines in your application code. +//***************************************************************************** +WEAK_AV void NMI_Handler(void) +{ while(1) {} +} + +WEAK_AV void HardFault_Handler(void) +{ while(1) {} +} + +WEAK_AV void MemManage_Handler(void) +{ while(1) {} +} + +WEAK_AV void BusFault_Handler(void) +{ while(1) {} +} + +WEAK_AV void UsageFault_Handler(void) +{ while(1) {} +} + +WEAK_AV void SecureFault_Handler(void) +{ while(1) {} +} + +WEAK_AV void SVC_Handler(void) +{ while(1) {} +} + +WEAK_AV void DebugMon_Handler(void) +{ while(1) {} +} + +WEAK_AV void PendSV_Handler(void) +{ while(1) {} +} + +WEAK_AV void SysTick_Handler(void) +{ while(1) {} +} + +//***************************************************************************** +// Processor ends up here if an unexpected interrupt occurs or a specific +// handler is not present in the application code. +//***************************************************************************** +WEAK_AV void IntDefaultHandler(void) +{ while(1) {} +} + +//***************************************************************************** +// Default application exception handlers. Override the ones here by defining +// your own handler routines in your application code. These routines call +// driver exception handlers or IntDefaultHandler() if no driver exception +// handler is included. +//***************************************************************************** +WEAK void WDT_BOD_IRQHandler(void) +{ WDT_BOD_DriverIRQHandler(); +} + +WEAK void DMA0_IRQHandler(void) +{ DMA0_DriverIRQHandler(); +} + +WEAK void GINT0_IRQHandler(void) +{ GINT0_DriverIRQHandler(); +} + +WEAK void GINT1_IRQHandler(void) +{ GINT1_DriverIRQHandler(); +} + +WEAK void PIN_INT0_IRQHandler(void) +{ PIN_INT0_DriverIRQHandler(); +} + +WEAK void PIN_INT1_IRQHandler(void) +{ PIN_INT1_DriverIRQHandler(); +} + +WEAK void PIN_INT2_IRQHandler(void) +{ PIN_INT2_DriverIRQHandler(); +} + +WEAK void PIN_INT3_IRQHandler(void) +{ PIN_INT3_DriverIRQHandler(); +} + +WEAK void UTICK0_IRQHandler(void) +{ UTICK0_DriverIRQHandler(); +} + +WEAK void MRT0_IRQHandler(void) +{ MRT0_DriverIRQHandler(); +} + +WEAK void CTIMER0_IRQHandler(void) +{ CTIMER0_DriverIRQHandler(); +} + +WEAK void CTIMER1_IRQHandler(void) +{ CTIMER1_DriverIRQHandler(); +} + +WEAK void SCT0_IRQHandler(void) +{ SCT0_DriverIRQHandler(); +} + +WEAK void CTIMER3_IRQHandler(void) +{ CTIMER3_DriverIRQHandler(); +} + +WEAK void FLEXCOMM0_IRQHandler(void) +{ FLEXCOMM0_DriverIRQHandler(); +} + +WEAK void FLEXCOMM1_IRQHandler(void) +{ FLEXCOMM1_DriverIRQHandler(); +} + +WEAK void FLEXCOMM2_IRQHandler(void) +{ FLEXCOMM2_DriverIRQHandler(); +} + +WEAK void FLEXCOMM3_IRQHandler(void) +{ FLEXCOMM3_DriverIRQHandler(); +} + +WEAK void FLEXCOMM4_IRQHandler(void) +{ FLEXCOMM4_DriverIRQHandler(); +} + +WEAK void FLEXCOMM5_IRQHandler(void) +{ FLEXCOMM5_DriverIRQHandler(); +} + +WEAK void FLEXCOMM6_IRQHandler(void) +{ FLEXCOMM6_DriverIRQHandler(); +} + +WEAK void FLEXCOMM7_IRQHandler(void) +{ FLEXCOMM7_DriverIRQHandler(); +} + +WEAK void ADC0_IRQHandler(void) +{ ADC0_DriverIRQHandler(); +} + +WEAK void Reserved39_IRQHandler(void) +{ Reserved39_DriverIRQHandler(); +} + +WEAK void ACMP_IRQHandler(void) +{ ACMP_DriverIRQHandler(); +} + +WEAK void Reserved41_IRQHandler(void) +{ Reserved41_DriverIRQHandler(); +} + +WEAK void Reserved42_IRQHandler(void) +{ Reserved42_DriverIRQHandler(); +} + +WEAK void USB0_NEEDCLK_IRQHandler(void) +{ USB0_NEEDCLK_DriverIRQHandler(); +} + +WEAK void USB0_IRQHandler(void) +{ USB0_DriverIRQHandler(); +} + +WEAK void RTC_IRQHandler(void) +{ RTC_DriverIRQHandler(); +} + +WEAK void Reserved46_IRQHandler(void) +{ Reserved46_DriverIRQHandler(); +} + +WEAK void MAILBOX_IRQHandler(void) +{ MAILBOX_DriverIRQHandler(); +} + +WEAK void PIN_INT4_IRQHandler(void) +{ PIN_INT4_DriverIRQHandler(); +} + +WEAK void PIN_INT5_IRQHandler(void) +{ PIN_INT5_DriverIRQHandler(); +} + +WEAK void PIN_INT6_IRQHandler(void) +{ PIN_INT6_DriverIRQHandler(); +} + +WEAK void PIN_INT7_IRQHandler(void) +{ PIN_INT7_DriverIRQHandler(); +} + +WEAK void CTIMER2_IRQHandler(void) +{ CTIMER2_DriverIRQHandler(); +} + +WEAK void CTIMER4_IRQHandler(void) +{ CTIMER4_DriverIRQHandler(); +} + +WEAK void OS_EVENT_IRQHandler(void) +{ OS_EVENT_DriverIRQHandler(); +} + +WEAK void Reserved55_IRQHandler(void) +{ Reserved55_DriverIRQHandler(); +} + +WEAK void Reserved56_IRQHandler(void) +{ Reserved56_DriverIRQHandler(); +} + +WEAK void Reserved57_IRQHandler(void) +{ Reserved57_DriverIRQHandler(); +} + +WEAK void SDIO_IRQHandler(void) +{ SDIO_DriverIRQHandler(); +} + +WEAK void Reserved59_IRQHandler(void) +{ Reserved59_DriverIRQHandler(); +} + +WEAK void Reserved60_IRQHandler(void) +{ Reserved60_DriverIRQHandler(); +} + +WEAK void Reserved61_IRQHandler(void) +{ Reserved61_DriverIRQHandler(); +} + +WEAK void USB1_UTMI_IRQHandler(void) +{ USB1_UTMI_DriverIRQHandler(); +} + +WEAK void USB1_IRQHandler(void) +{ USB1_DriverIRQHandler(); +} + +WEAK void USB1_NEEDCLK_IRQHandler(void) +{ USB1_NEEDCLK_DriverIRQHandler(); +} + +WEAK void SEC_HYPERVISOR_CALL_IRQHandler(void) +{ SEC_HYPERVISOR_CALL_DriverIRQHandler(); +} + +WEAK void SEC_GPIO_INT0_IRQ0_IRQHandler(void) +{ SEC_GPIO_INT0_IRQ0_DriverIRQHandler(); +} + +WEAK void SEC_GPIO_INT0_IRQ1_IRQHandler(void) +{ SEC_GPIO_INT0_IRQ1_DriverIRQHandler(); +} + +WEAK void PLU_IRQHandler(void) +{ PLU_DriverIRQHandler(); +} + +WEAK void SEC_VIO_IRQHandler(void) +{ SEC_VIO_DriverIRQHandler(); +} + +WEAK void HASHCRYPT_IRQHandler(void) +{ HASHCRYPT_DriverIRQHandler(); +} + +WEAK void CASER_IRQHandler(void) +{ CASER_DriverIRQHandler(); +} + +WEAK void PUF_IRQHandler(void) +{ PUF_DriverIRQHandler(); +} + +WEAK void PQ_IRQHandler(void) +{ PQ_DriverIRQHandler(); +} + +WEAK void DMA1_IRQHandler(void) +{ DMA1_DriverIRQHandler(); +} + +WEAK void FLEXCOMM8_IRQHandler(void) +{ FLEXCOMM8_DriverIRQHandler(); +} + +//***************************************************************************** + +#if defined (DEBUG) +#pragma GCC pop_options +#endif // (DEBUG) diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/mcuxpresso/startup_lpc55s69_cm33_core1.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/mcuxpresso/startup_lpc55s69_cm33_core1.c new file mode 100644 index 000000000..ed5a43606 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/mcuxpresso/startup_lpc55s69_cm33_core1.c @@ -0,0 +1,744 @@ +//***************************************************************************** +// LPC55S69_cm33_core1 startup code for use with MCUXpresso IDE +// +// Version : 240619 +//***************************************************************************** +// +// Copyright 2016-2019 NXP +// All rights reserved. +// +// SPDX-License-Identifier: BSD-3-Clause +//***************************************************************************** + +#if defined (DEBUG) +#pragma GCC push_options +#pragma GCC optimize ("Og") +#endif // (DEBUG) + +#if defined (__cplusplus) +#ifdef __REDLIB__ +#error Redlib does not support C++ +#else +//***************************************************************************** +// +// The entry point for the C++ library startup +// +//***************************************************************************** +extern "C" { + extern void __libc_init_array(void); +} +#endif +#endif + +#define WEAK __attribute__ ((weak)) +#define WEAK_AV __attribute__ ((weak, section(".after_vectors"))) +#define ALIAS(f) __attribute__ ((weak, alias (#f))) + +//***************************************************************************** +#if defined (__cplusplus) +extern "C" { +#endif + +//***************************************************************************** +// Variable to store CRP value in. Will be placed automatically +// by the linker when "Enable Code Read Protect" selected. +// See crp.h header for more information +//***************************************************************************** +//***************************************************************************** +// Declaration of external SystemInit function +//***************************************************************************** +#if defined (__USE_CMSIS) +extern void SystemInit(void); +#endif // (__USE_CMSIS) + +//***************************************************************************** +// Forward declaration of the core exception handlers. +// When the application defines a handler (with the same name), this will +// automatically take precedence over these weak definitions. +// If your application is a C++ one, then any interrupt handlers defined +// in C++ files within in your main application will need to have C linkage +// rather than C++ linkage. To do this, make sure that you are using extern "C" +// { .... } around the interrupt handler within your main application code. +//***************************************************************************** + void ResetISR(void); +WEAK void NMI_Handler(void); +WEAK void HardFault_Handler(void); +WEAK void MemManage_Handler(void); +WEAK void BusFault_Handler(void); +WEAK void UsageFault_Handler(void); +WEAK void SecureFault_Handler(void); +WEAK void SVC_Handler(void); +WEAK void DebugMon_Handler(void); +WEAK void PendSV_Handler(void); +WEAK void SysTick_Handler(void); +WEAK void IntDefaultHandler(void); + +//***************************************************************************** +// Forward declaration of the application IRQ handlers. When the application +// defines a handler (with the same name), this will automatically take +// precedence over weak definitions below +//***************************************************************************** +WEAK void WDT_BOD_IRQHandler(void); +WEAK void DMA0_IRQHandler(void); +WEAK void GINT0_IRQHandler(void); +WEAK void GINT1_IRQHandler(void); +WEAK void PIN_INT0_IRQHandler(void); +WEAK void PIN_INT1_IRQHandler(void); +WEAK void PIN_INT2_IRQHandler(void); +WEAK void PIN_INT3_IRQHandler(void); +WEAK void UTICK0_IRQHandler(void); +WEAK void MRT0_IRQHandler(void); +WEAK void CTIMER0_IRQHandler(void); +WEAK void CTIMER1_IRQHandler(void); +WEAK void SCT0_IRQHandler(void); +WEAK void CTIMER3_IRQHandler(void); +WEAK void FLEXCOMM0_IRQHandler(void); +WEAK void FLEXCOMM1_IRQHandler(void); +WEAK void FLEXCOMM2_IRQHandler(void); +WEAK void FLEXCOMM3_IRQHandler(void); +WEAK void FLEXCOMM4_IRQHandler(void); +WEAK void FLEXCOMM5_IRQHandler(void); +WEAK void FLEXCOMM6_IRQHandler(void); +WEAK void FLEXCOMM7_IRQHandler(void); +WEAK void ADC0_IRQHandler(void); +WEAK void Reserved39_IRQHandler(void); +WEAK void ACMP_IRQHandler(void); +WEAK void Reserved41_IRQHandler(void); +WEAK void Reserved42_IRQHandler(void); +WEAK void USB0_NEEDCLK_IRQHandler(void); +WEAK void USB0_IRQHandler(void); +WEAK void RTC_IRQHandler(void); +WEAK void Reserved46_IRQHandler(void); +WEAK void MAILBOX_IRQHandler(void); +WEAK void PIN_INT4_IRQHandler(void); +WEAK void PIN_INT5_IRQHandler(void); +WEAK void PIN_INT6_IRQHandler(void); +WEAK void PIN_INT7_IRQHandler(void); +WEAK void CTIMER2_IRQHandler(void); +WEAK void CTIMER4_IRQHandler(void); +WEAK void OS_EVENT_IRQHandler(void); +WEAK void Reserved55_IRQHandler(void); +WEAK void Reserved56_IRQHandler(void); +WEAK void Reserved57_IRQHandler(void); +WEAK void SDIO_IRQHandler(void); +WEAK void Reserved59_IRQHandler(void); +WEAK void Reserved60_IRQHandler(void); +WEAK void Reserved61_IRQHandler(void); +WEAK void USB1_UTMI_IRQHandler(void); +WEAK void USB1_IRQHandler(void); +WEAK void USB1_NEEDCLK_IRQHandler(void); +WEAK void SEC_HYPERVISOR_CALL_IRQHandler(void); +WEAK void SEC_GPIO_INT0_IRQ0_IRQHandler(void); +WEAK void SEC_GPIO_INT0_IRQ1_IRQHandler(void); +WEAK void PLU_IRQHandler(void); +WEAK void SEC_VIO_IRQHandler(void); +WEAK void HASHCRYPT_IRQHandler(void); +WEAK void CASER_IRQHandler(void); +WEAK void PUF_IRQHandler(void); +WEAK void PQ_IRQHandler(void); +WEAK void DMA1_IRQHandler(void); +WEAK void FLEXCOMM8_IRQHandler(void); + +//***************************************************************************** +// Forward declaration of the driver IRQ handlers. These are aliased +// to the IntDefaultHandler, which is a 'forever' loop. When the driver +// defines a handler (with the same name), this will automatically take +// precedence over these weak definitions +//***************************************************************************** +void WDT_BOD_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void DMA0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GINT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GINT1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PIN_INT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PIN_INT1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PIN_INT2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PIN_INT3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void UTICK0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void MRT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CTIMER0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CTIMER1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SCT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CTIMER3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXCOMM0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXCOMM1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXCOMM2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXCOMM3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXCOMM4_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXCOMM5_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXCOMM6_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXCOMM7_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ADC0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved39_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ACMP_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved41_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved42_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void USB0_NEEDCLK_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void USB0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void RTC_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved46_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void MAILBOX_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PIN_INT4_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PIN_INT5_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PIN_INT6_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PIN_INT7_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CTIMER2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CTIMER4_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void OS_EVENT_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved55_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved56_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved57_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SDIO_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved59_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved60_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved61_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void USB1_UTMI_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void USB1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void USB1_NEEDCLK_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SEC_HYPERVISOR_CALL_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SEC_GPIO_INT0_IRQ0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SEC_GPIO_INT0_IRQ1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PLU_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SEC_VIO_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void HASHCRYPT_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CASER_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PUF_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PQ_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void DMA1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXCOMM8_DriverIRQHandler(void) ALIAS(IntDefaultHandler); + +//***************************************************************************** +// The entry point for the application. +// __main() is the entry point for Redlib based applications +// main() is the entry point for Newlib based applications +//***************************************************************************** +#if defined (__REDLIB__) +extern void __main(void); +#endif +extern int main(void); + +//***************************************************************************** +// External declaration for the pointer to the stack top from the Linker Script +//***************************************************************************** +extern void _vStackTop(void); +//***************************************************************************** +// External declaration for LPC MCU vector table checksum from Linker Script +//***************************************************************************** +WEAK extern void __valid_user_code_checksum(); + +//***************************************************************************** +//***************************************************************************** +#if defined (__cplusplus) +} // extern "C" +#endif +//***************************************************************************** +// The vector table. +// This relies on the linker script to place at correct location in memory. +//***************************************************************************** +extern void (* const g_pfnVectors[])(void); +extern void * __Vectors __attribute__ ((alias ("g_pfnVectors"))); + +__attribute__ ((used, section(".isr_vector"))) +void (* const g_pfnVectors[])(void) = { + // Core Level - CM33 + &_vStackTop, // The initial stack pointer + ResetISR, // The reset handler + NMI_Handler, // The NMI handler + HardFault_Handler, // The hard fault handler + MemManage_Handler, // The MPU fault handler + BusFault_Handler, // The bus fault handler + UsageFault_Handler, // The usage fault handler + SecureFault_Handler, // The secure fault handler + 0, // ECRP + 0, // Reserved + 0, // Reserved + SVC_Handler, // SVCall handler + DebugMon_Handler, // Debug monitor handler + 0, // Reserved + PendSV_Handler, // The PendSV handler + SysTick_Handler, // The SysTick handler + + // Chip Level - LPC55S69_cm33_core1 + WDT_BOD_IRQHandler, // 16: Windowed watchdog timer, Brownout detect, Flash interrupt + DMA0_IRQHandler, // 17: DMA0 controller + GINT0_IRQHandler, // 18: GPIO group 0 + GINT1_IRQHandler, // 19: GPIO group 1 + PIN_INT0_IRQHandler, // 20: Pin interrupt 0 or pattern match engine slice 0 + PIN_INT1_IRQHandler, // 21: Pin interrupt 1or pattern match engine slice 1 + PIN_INT2_IRQHandler, // 22: Pin interrupt 2 or pattern match engine slice 2 + PIN_INT3_IRQHandler, // 23: Pin interrupt 3 or pattern match engine slice 3 + UTICK0_IRQHandler, // 24: Micro-tick Timer + MRT0_IRQHandler, // 25: Multi-rate timer + CTIMER0_IRQHandler, // 26: Standard counter/timer CTIMER0 + CTIMER1_IRQHandler, // 27: Standard counter/timer CTIMER1 + SCT0_IRQHandler, // 28: SCTimer/PWM + CTIMER3_IRQHandler, // 29: Standard counter/timer CTIMER3 + FLEXCOMM0_IRQHandler, // 30: Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) + FLEXCOMM1_IRQHandler, // 31: Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) + FLEXCOMM2_IRQHandler, // 32: Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) + FLEXCOMM3_IRQHandler, // 33: Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) + FLEXCOMM4_IRQHandler, // 34: Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) + FLEXCOMM5_IRQHandler, // 35: Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) + FLEXCOMM6_IRQHandler, // 36: Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) + FLEXCOMM7_IRQHandler, // 37: Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) + ADC0_IRQHandler, // 38: ADC0 + Reserved39_IRQHandler, // 39: Reserved interrupt + ACMP_IRQHandler, // 40: ACMP interrupts + Reserved41_IRQHandler, // 41: Reserved interrupt + Reserved42_IRQHandler, // 42: Reserved interrupt + USB0_NEEDCLK_IRQHandler, // 43: USB Activity Wake-up Interrupt + USB0_IRQHandler, // 44: USB device + RTC_IRQHandler, // 45: RTC alarm and wake-up interrupts + Reserved46_IRQHandler, // 46: Reserved interrupt + MAILBOX_IRQHandler, // 47: WAKEUP,Mailbox interrupt (present on selected devices) + PIN_INT4_IRQHandler, // 48: Pin interrupt 4 or pattern match engine slice 4 int + PIN_INT5_IRQHandler, // 49: Pin interrupt 5 or pattern match engine slice 5 int + PIN_INT6_IRQHandler, // 50: Pin interrupt 6 or pattern match engine slice 6 int + PIN_INT7_IRQHandler, // 51: Pin interrupt 7 or pattern match engine slice 7 int + CTIMER2_IRQHandler, // 52: Standard counter/timer CTIMER2 + CTIMER4_IRQHandler, // 53: Standard counter/timer CTIMER4 + OS_EVENT_IRQHandler, // 54: OSEVTIMER0 and OSEVTIMER0_WAKEUP interrupts + Reserved55_IRQHandler, // 55: Reserved interrupt + Reserved56_IRQHandler, // 56: Reserved interrupt + Reserved57_IRQHandler, // 57: Reserved interrupt + SDIO_IRQHandler, // 58: SD/MMC + Reserved59_IRQHandler, // 59: Reserved interrupt + Reserved60_IRQHandler, // 60: Reserved interrupt + Reserved61_IRQHandler, // 61: Reserved interrupt + USB1_UTMI_IRQHandler, // 62: USB1_UTMI + USB1_IRQHandler, // 63: USB1 interrupt + USB1_NEEDCLK_IRQHandler, // 64: USB1 activity + SEC_HYPERVISOR_CALL_IRQHandler, // 65: SEC_HYPERVISOR_CALL interrupt + SEC_GPIO_INT0_IRQ0_IRQHandler, // 66: SEC_GPIO_INT0_IRQ0 interrupt + SEC_GPIO_INT0_IRQ1_IRQHandler, // 67: SEC_GPIO_INT0_IRQ1 interrupt + PLU_IRQHandler, // 68: PLU interrupt + SEC_VIO_IRQHandler, // 69: SEC_VIO interrupt + HASHCRYPT_IRQHandler, // 70: HASHCRYPT interrupt + CASER_IRQHandler, // 71: CASPER interrupt + PUF_IRQHandler, // 72: PUF interrupt + PQ_IRQHandler, // 73: PQ interrupt + DMA1_IRQHandler, // 74: DMA1 interrupt + FLEXCOMM8_IRQHandler, // 75: Flexcomm Interface 8 (SPI, , FLEXCOMM) + +}; /* End of g_pfnVectors */ + +//***************************************************************************** +// Functions to carry out the initialization of RW and BSS data sections. These +// are written as separate functions rather than being inlined within the +// ResetISR() function in order to cope with MCUs with multiple banks of +// memory. +//***************************************************************************** +__attribute__ ((section(".after_vectors.init_data"))) +void data_init(unsigned int romstart, unsigned int start, unsigned int len) { + unsigned int *pulDest = (unsigned int*) start; + unsigned int *pulSrc = (unsigned int*) romstart; + unsigned int loop; + for (loop = 0; loop < len; loop = loop + 4) + *pulDest++ = *pulSrc++; +} + +__attribute__ ((section(".after_vectors.init_bss"))) +void bss_init(unsigned int start, unsigned int len) { + unsigned int *pulDest = (unsigned int*) start; + unsigned int loop; + for (loop = 0; loop < len; loop = loop + 4) + *pulDest++ = 0; +} + +//***************************************************************************** +// The following symbols are constructs generated by the linker, indicating +// the location of various points in the "Global Section Table". This table is +// created by the linker via the Code Red managed linker script mechanism. It +// contains the load address, execution address and length of each RW data +// section and the execution and length of each BSS (zero initialized) section. +//***************************************************************************** +extern unsigned int __data_section_table; +extern unsigned int __data_section_table_end; +extern unsigned int __bss_section_table; +extern unsigned int __bss_section_table_end; + +//***************************************************************************** +// Reset entry point for your code. +// Sets up a simple runtime environment and initializes the C/C++ +// library. +//***************************************************************************** +__attribute__ ((section(".after_vectors.reset"))) +void ResetISR(void) { + + // Disable interrupts + __asm volatile ("cpsid i"); + + + +#if defined (__USE_CMSIS) +// If __USE_CMSIS defined, then call CMSIS SystemInit code + SystemInit(); + +#endif // (__USE_CMSIS) + + // + // Copy the data sections from flash to SRAM. + // + unsigned int LoadAddr, ExeAddr, SectionLen; + unsigned int *SectionTableAddr; + + // Load base address of Global Section Table + SectionTableAddr = &__data_section_table; + + // Copy the data sections from flash to SRAM. + while (SectionTableAddr < &__data_section_table_end) { + LoadAddr = *SectionTableAddr++; + ExeAddr = *SectionTableAddr++; + SectionLen = *SectionTableAddr++; + data_init(LoadAddr, ExeAddr, SectionLen); + } + + // At this point, SectionTableAddr = &__bss_section_table; + // Zero fill the bss segment + while (SectionTableAddr < &__bss_section_table_end) { + ExeAddr = *SectionTableAddr++; + SectionLen = *SectionTableAddr++; + bss_init(ExeAddr, SectionLen); + } + + +#if !defined (__USE_CMSIS) +// Assume that if __USE_CMSIS defined, then CMSIS SystemInit code +// will setup the VTOR register + + // Check to see if we are running the code from a non-zero + // address (eg RAM, external flash), in which case we need + // to modify the VTOR register to tell the CPU that the + // vector table is located at a non-0x0 address. + unsigned int * pSCB_VTOR = (unsigned int *) 0xE000ED08; + if ((unsigned int *)g_pfnVectors!=(unsigned int *) 0x00000000) { + *pSCB_VTOR = (unsigned int)g_pfnVectors; + } +#endif // (__USE_CMSIS) +#if defined (__cplusplus) + // + // Call C++ library initialisation + // + __libc_init_array(); +#endif + + // Reenable interrupts + __asm volatile ("cpsie i"); + +#if defined (__REDLIB__) + // Call the Redlib library, which in turn calls main() + __main(); +#else + main(); +#endif + + // + // main() shouldn't return, but if it does, we'll just enter an infinite loop + // + while (1) { + ; + } +} + +//***************************************************************************** +// Default core exception handlers. Override the ones here by defining your own +// handler routines in your application code. +//***************************************************************************** +WEAK_AV void NMI_Handler(void) +{ while(1) {} +} + +WEAK_AV void HardFault_Handler(void) +{ while(1) {} +} + +WEAK_AV void MemManage_Handler(void) +{ while(1) {} +} + +WEAK_AV void BusFault_Handler(void) +{ while(1) {} +} + +WEAK_AV void UsageFault_Handler(void) +{ while(1) {} +} + +WEAK_AV void SecureFault_Handler(void) +{ while(1) {} +} + +WEAK_AV void SVC_Handler(void) +{ while(1) {} +} + +WEAK_AV void DebugMon_Handler(void) +{ while(1) {} +} + +WEAK_AV void PendSV_Handler(void) +{ while(1) {} +} + +WEAK_AV void SysTick_Handler(void) +{ while(1) {} +} + +//***************************************************************************** +// Processor ends up here if an unexpected interrupt occurs or a specific +// handler is not present in the application code. +//***************************************************************************** +WEAK_AV void IntDefaultHandler(void) +{ while(1) {} +} + +//***************************************************************************** +// Default application exception handlers. Override the ones here by defining +// your own handler routines in your application code. These routines call +// driver exception handlers or IntDefaultHandler() if no driver exception +// handler is included. +//***************************************************************************** +WEAK void WDT_BOD_IRQHandler(void) +{ WDT_BOD_DriverIRQHandler(); +} + +WEAK void DMA0_IRQHandler(void) +{ DMA0_DriverIRQHandler(); +} + +WEAK void GINT0_IRQHandler(void) +{ GINT0_DriverIRQHandler(); +} + +WEAK void GINT1_IRQHandler(void) +{ GINT1_DriverIRQHandler(); +} + +WEAK void PIN_INT0_IRQHandler(void) +{ PIN_INT0_DriverIRQHandler(); +} + +WEAK void PIN_INT1_IRQHandler(void) +{ PIN_INT1_DriverIRQHandler(); +} + +WEAK void PIN_INT2_IRQHandler(void) +{ PIN_INT2_DriverIRQHandler(); +} + +WEAK void PIN_INT3_IRQHandler(void) +{ PIN_INT3_DriverIRQHandler(); +} + +WEAK void UTICK0_IRQHandler(void) +{ UTICK0_DriverIRQHandler(); +} + +WEAK void MRT0_IRQHandler(void) +{ MRT0_DriverIRQHandler(); +} + +WEAK void CTIMER0_IRQHandler(void) +{ CTIMER0_DriverIRQHandler(); +} + +WEAK void CTIMER1_IRQHandler(void) +{ CTIMER1_DriverIRQHandler(); +} + +WEAK void SCT0_IRQHandler(void) +{ SCT0_DriverIRQHandler(); +} + +WEAK void CTIMER3_IRQHandler(void) +{ CTIMER3_DriverIRQHandler(); +} + +WEAK void FLEXCOMM0_IRQHandler(void) +{ FLEXCOMM0_DriverIRQHandler(); +} + +WEAK void FLEXCOMM1_IRQHandler(void) +{ FLEXCOMM1_DriverIRQHandler(); +} + +WEAK void FLEXCOMM2_IRQHandler(void) +{ FLEXCOMM2_DriverIRQHandler(); +} + +WEAK void FLEXCOMM3_IRQHandler(void) +{ FLEXCOMM3_DriverIRQHandler(); +} + +WEAK void FLEXCOMM4_IRQHandler(void) +{ FLEXCOMM4_DriverIRQHandler(); +} + +WEAK void FLEXCOMM5_IRQHandler(void) +{ FLEXCOMM5_DriverIRQHandler(); +} + +WEAK void FLEXCOMM6_IRQHandler(void) +{ FLEXCOMM6_DriverIRQHandler(); +} + +WEAK void FLEXCOMM7_IRQHandler(void) +{ FLEXCOMM7_DriverIRQHandler(); +} + +WEAK void ADC0_IRQHandler(void) +{ ADC0_DriverIRQHandler(); +} + +WEAK void Reserved39_IRQHandler(void) +{ Reserved39_DriverIRQHandler(); +} + +WEAK void ACMP_IRQHandler(void) +{ ACMP_DriverIRQHandler(); +} + +WEAK void Reserved41_IRQHandler(void) +{ Reserved41_DriverIRQHandler(); +} + +WEAK void Reserved42_IRQHandler(void) +{ Reserved42_DriverIRQHandler(); +} + +WEAK void USB0_NEEDCLK_IRQHandler(void) +{ USB0_NEEDCLK_DriverIRQHandler(); +} + +WEAK void USB0_IRQHandler(void) +{ USB0_DriverIRQHandler(); +} + +WEAK void RTC_IRQHandler(void) +{ RTC_DriverIRQHandler(); +} + +WEAK void Reserved46_IRQHandler(void) +{ Reserved46_DriverIRQHandler(); +} + +WEAK void MAILBOX_IRQHandler(void) +{ MAILBOX_DriverIRQHandler(); +} + +WEAK void PIN_INT4_IRQHandler(void) +{ PIN_INT4_DriverIRQHandler(); +} + +WEAK void PIN_INT5_IRQHandler(void) +{ PIN_INT5_DriverIRQHandler(); +} + +WEAK void PIN_INT6_IRQHandler(void) +{ PIN_INT6_DriverIRQHandler(); +} + +WEAK void PIN_INT7_IRQHandler(void) +{ PIN_INT7_DriverIRQHandler(); +} + +WEAK void CTIMER2_IRQHandler(void) +{ CTIMER2_DriverIRQHandler(); +} + +WEAK void CTIMER4_IRQHandler(void) +{ CTIMER4_DriverIRQHandler(); +} + +WEAK void OS_EVENT_IRQHandler(void) +{ OS_EVENT_DriverIRQHandler(); +} + +WEAK void Reserved55_IRQHandler(void) +{ Reserved55_DriverIRQHandler(); +} + +WEAK void Reserved56_IRQHandler(void) +{ Reserved56_DriverIRQHandler(); +} + +WEAK void Reserved57_IRQHandler(void) +{ Reserved57_DriverIRQHandler(); +} + +WEAK void SDIO_IRQHandler(void) +{ SDIO_DriverIRQHandler(); +} + +WEAK void Reserved59_IRQHandler(void) +{ Reserved59_DriverIRQHandler(); +} + +WEAK void Reserved60_IRQHandler(void) +{ Reserved60_DriverIRQHandler(); +} + +WEAK void Reserved61_IRQHandler(void) +{ Reserved61_DriverIRQHandler(); +} + +WEAK void USB1_UTMI_IRQHandler(void) +{ USB1_UTMI_DriverIRQHandler(); +} + +WEAK void USB1_IRQHandler(void) +{ USB1_DriverIRQHandler(); +} + +WEAK void USB1_NEEDCLK_IRQHandler(void) +{ USB1_NEEDCLK_DriverIRQHandler(); +} + +WEAK void SEC_HYPERVISOR_CALL_IRQHandler(void) +{ SEC_HYPERVISOR_CALL_DriverIRQHandler(); +} + +WEAK void SEC_GPIO_INT0_IRQ0_IRQHandler(void) +{ SEC_GPIO_INT0_IRQ0_DriverIRQHandler(); +} + +WEAK void SEC_GPIO_INT0_IRQ1_IRQHandler(void) +{ SEC_GPIO_INT0_IRQ1_DriverIRQHandler(); +} + +WEAK void PLU_IRQHandler(void) +{ PLU_DriverIRQHandler(); +} + +WEAK void SEC_VIO_IRQHandler(void) +{ SEC_VIO_DriverIRQHandler(); +} + +WEAK void HASHCRYPT_IRQHandler(void) +{ HASHCRYPT_DriverIRQHandler(); +} + +WEAK void CASER_IRQHandler(void) +{ CASER_DriverIRQHandler(); +} + +WEAK void PUF_IRQHandler(void) +{ PUF_DriverIRQHandler(); +} + +WEAK void PQ_IRQHandler(void) +{ PQ_DriverIRQHandler(); +} + +WEAK void DMA1_IRQHandler(void) +{ DMA1_DriverIRQHandler(); +} + +WEAK void FLEXCOMM8_IRQHandler(void) +{ FLEXCOMM8_DriverIRQHandler(); +} + +//***************************************************************************** + +#if defined (DEBUG) +#pragma GCC pop_options +#endif // (DEBUG) diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/mcuxpresso/startup_lpc55s69_cm33_core1.cpp b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/mcuxpresso/startup_lpc55s69_cm33_core1.cpp new file mode 100644 index 000000000..ed5a43606 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/mcuxpresso/startup_lpc55s69_cm33_core1.cpp @@ -0,0 +1,744 @@ +//***************************************************************************** +// LPC55S69_cm33_core1 startup code for use with MCUXpresso IDE +// +// Version : 240619 +//***************************************************************************** +// +// Copyright 2016-2019 NXP +// All rights reserved. +// +// SPDX-License-Identifier: BSD-3-Clause +//***************************************************************************** + +#if defined (DEBUG) +#pragma GCC push_options +#pragma GCC optimize ("Og") +#endif // (DEBUG) + +#if defined (__cplusplus) +#ifdef __REDLIB__ +#error Redlib does not support C++ +#else +//***************************************************************************** +// +// The entry point for the C++ library startup +// +//***************************************************************************** +extern "C" { + extern void __libc_init_array(void); +} +#endif +#endif + +#define WEAK __attribute__ ((weak)) +#define WEAK_AV __attribute__ ((weak, section(".after_vectors"))) +#define ALIAS(f) __attribute__ ((weak, alias (#f))) + +//***************************************************************************** +#if defined (__cplusplus) +extern "C" { +#endif + +//***************************************************************************** +// Variable to store CRP value in. Will be placed automatically +// by the linker when "Enable Code Read Protect" selected. +// See crp.h header for more information +//***************************************************************************** +//***************************************************************************** +// Declaration of external SystemInit function +//***************************************************************************** +#if defined (__USE_CMSIS) +extern void SystemInit(void); +#endif // (__USE_CMSIS) + +//***************************************************************************** +// Forward declaration of the core exception handlers. +// When the application defines a handler (with the same name), this will +// automatically take precedence over these weak definitions. +// If your application is a C++ one, then any interrupt handlers defined +// in C++ files within in your main application will need to have C linkage +// rather than C++ linkage. To do this, make sure that you are using extern "C" +// { .... } around the interrupt handler within your main application code. +//***************************************************************************** + void ResetISR(void); +WEAK void NMI_Handler(void); +WEAK void HardFault_Handler(void); +WEAK void MemManage_Handler(void); +WEAK void BusFault_Handler(void); +WEAK void UsageFault_Handler(void); +WEAK void SecureFault_Handler(void); +WEAK void SVC_Handler(void); +WEAK void DebugMon_Handler(void); +WEAK void PendSV_Handler(void); +WEAK void SysTick_Handler(void); +WEAK void IntDefaultHandler(void); + +//***************************************************************************** +// Forward declaration of the application IRQ handlers. When the application +// defines a handler (with the same name), this will automatically take +// precedence over weak definitions below +//***************************************************************************** +WEAK void WDT_BOD_IRQHandler(void); +WEAK void DMA0_IRQHandler(void); +WEAK void GINT0_IRQHandler(void); +WEAK void GINT1_IRQHandler(void); +WEAK void PIN_INT0_IRQHandler(void); +WEAK void PIN_INT1_IRQHandler(void); +WEAK void PIN_INT2_IRQHandler(void); +WEAK void PIN_INT3_IRQHandler(void); +WEAK void UTICK0_IRQHandler(void); +WEAK void MRT0_IRQHandler(void); +WEAK void CTIMER0_IRQHandler(void); +WEAK void CTIMER1_IRQHandler(void); +WEAK void SCT0_IRQHandler(void); +WEAK void CTIMER3_IRQHandler(void); +WEAK void FLEXCOMM0_IRQHandler(void); +WEAK void FLEXCOMM1_IRQHandler(void); +WEAK void FLEXCOMM2_IRQHandler(void); +WEAK void FLEXCOMM3_IRQHandler(void); +WEAK void FLEXCOMM4_IRQHandler(void); +WEAK void FLEXCOMM5_IRQHandler(void); +WEAK void FLEXCOMM6_IRQHandler(void); +WEAK void FLEXCOMM7_IRQHandler(void); +WEAK void ADC0_IRQHandler(void); +WEAK void Reserved39_IRQHandler(void); +WEAK void ACMP_IRQHandler(void); +WEAK void Reserved41_IRQHandler(void); +WEAK void Reserved42_IRQHandler(void); +WEAK void USB0_NEEDCLK_IRQHandler(void); +WEAK void USB0_IRQHandler(void); +WEAK void RTC_IRQHandler(void); +WEAK void Reserved46_IRQHandler(void); +WEAK void MAILBOX_IRQHandler(void); +WEAK void PIN_INT4_IRQHandler(void); +WEAK void PIN_INT5_IRQHandler(void); +WEAK void PIN_INT6_IRQHandler(void); +WEAK void PIN_INT7_IRQHandler(void); +WEAK void CTIMER2_IRQHandler(void); +WEAK void CTIMER4_IRQHandler(void); +WEAK void OS_EVENT_IRQHandler(void); +WEAK void Reserved55_IRQHandler(void); +WEAK void Reserved56_IRQHandler(void); +WEAK void Reserved57_IRQHandler(void); +WEAK void SDIO_IRQHandler(void); +WEAK void Reserved59_IRQHandler(void); +WEAK void Reserved60_IRQHandler(void); +WEAK void Reserved61_IRQHandler(void); +WEAK void USB1_UTMI_IRQHandler(void); +WEAK void USB1_IRQHandler(void); +WEAK void USB1_NEEDCLK_IRQHandler(void); +WEAK void SEC_HYPERVISOR_CALL_IRQHandler(void); +WEAK void SEC_GPIO_INT0_IRQ0_IRQHandler(void); +WEAK void SEC_GPIO_INT0_IRQ1_IRQHandler(void); +WEAK void PLU_IRQHandler(void); +WEAK void SEC_VIO_IRQHandler(void); +WEAK void HASHCRYPT_IRQHandler(void); +WEAK void CASER_IRQHandler(void); +WEAK void PUF_IRQHandler(void); +WEAK void PQ_IRQHandler(void); +WEAK void DMA1_IRQHandler(void); +WEAK void FLEXCOMM8_IRQHandler(void); + +//***************************************************************************** +// Forward declaration of the driver IRQ handlers. These are aliased +// to the IntDefaultHandler, which is a 'forever' loop. When the driver +// defines a handler (with the same name), this will automatically take +// precedence over these weak definitions +//***************************************************************************** +void WDT_BOD_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void DMA0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GINT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GINT1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PIN_INT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PIN_INT1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PIN_INT2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PIN_INT3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void UTICK0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void MRT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CTIMER0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CTIMER1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SCT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CTIMER3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXCOMM0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXCOMM1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXCOMM2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXCOMM3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXCOMM4_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXCOMM5_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXCOMM6_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXCOMM7_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ADC0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved39_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ACMP_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved41_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved42_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void USB0_NEEDCLK_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void USB0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void RTC_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved46_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void MAILBOX_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PIN_INT4_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PIN_INT5_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PIN_INT6_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PIN_INT7_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CTIMER2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CTIMER4_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void OS_EVENT_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved55_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved56_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved57_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SDIO_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved59_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved60_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved61_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void USB1_UTMI_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void USB1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void USB1_NEEDCLK_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SEC_HYPERVISOR_CALL_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SEC_GPIO_INT0_IRQ0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SEC_GPIO_INT0_IRQ1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PLU_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SEC_VIO_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void HASHCRYPT_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CASER_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PUF_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PQ_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void DMA1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXCOMM8_DriverIRQHandler(void) ALIAS(IntDefaultHandler); + +//***************************************************************************** +// The entry point for the application. +// __main() is the entry point for Redlib based applications +// main() is the entry point for Newlib based applications +//***************************************************************************** +#if defined (__REDLIB__) +extern void __main(void); +#endif +extern int main(void); + +//***************************************************************************** +// External declaration for the pointer to the stack top from the Linker Script +//***************************************************************************** +extern void _vStackTop(void); +//***************************************************************************** +// External declaration for LPC MCU vector table checksum from Linker Script +//***************************************************************************** +WEAK extern void __valid_user_code_checksum(); + +//***************************************************************************** +//***************************************************************************** +#if defined (__cplusplus) +} // extern "C" +#endif +//***************************************************************************** +// The vector table. +// This relies on the linker script to place at correct location in memory. +//***************************************************************************** +extern void (* const g_pfnVectors[])(void); +extern void * __Vectors __attribute__ ((alias ("g_pfnVectors"))); + +__attribute__ ((used, section(".isr_vector"))) +void (* const g_pfnVectors[])(void) = { + // Core Level - CM33 + &_vStackTop, // The initial stack pointer + ResetISR, // The reset handler + NMI_Handler, // The NMI handler + HardFault_Handler, // The hard fault handler + MemManage_Handler, // The MPU fault handler + BusFault_Handler, // The bus fault handler + UsageFault_Handler, // The usage fault handler + SecureFault_Handler, // The secure fault handler + 0, // ECRP + 0, // Reserved + 0, // Reserved + SVC_Handler, // SVCall handler + DebugMon_Handler, // Debug monitor handler + 0, // Reserved + PendSV_Handler, // The PendSV handler + SysTick_Handler, // The SysTick handler + + // Chip Level - LPC55S69_cm33_core1 + WDT_BOD_IRQHandler, // 16: Windowed watchdog timer, Brownout detect, Flash interrupt + DMA0_IRQHandler, // 17: DMA0 controller + GINT0_IRQHandler, // 18: GPIO group 0 + GINT1_IRQHandler, // 19: GPIO group 1 + PIN_INT0_IRQHandler, // 20: Pin interrupt 0 or pattern match engine slice 0 + PIN_INT1_IRQHandler, // 21: Pin interrupt 1or pattern match engine slice 1 + PIN_INT2_IRQHandler, // 22: Pin interrupt 2 or pattern match engine slice 2 + PIN_INT3_IRQHandler, // 23: Pin interrupt 3 or pattern match engine slice 3 + UTICK0_IRQHandler, // 24: Micro-tick Timer + MRT0_IRQHandler, // 25: Multi-rate timer + CTIMER0_IRQHandler, // 26: Standard counter/timer CTIMER0 + CTIMER1_IRQHandler, // 27: Standard counter/timer CTIMER1 + SCT0_IRQHandler, // 28: SCTimer/PWM + CTIMER3_IRQHandler, // 29: Standard counter/timer CTIMER3 + FLEXCOMM0_IRQHandler, // 30: Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) + FLEXCOMM1_IRQHandler, // 31: Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) + FLEXCOMM2_IRQHandler, // 32: Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) + FLEXCOMM3_IRQHandler, // 33: Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) + FLEXCOMM4_IRQHandler, // 34: Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) + FLEXCOMM5_IRQHandler, // 35: Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) + FLEXCOMM6_IRQHandler, // 36: Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) + FLEXCOMM7_IRQHandler, // 37: Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) + ADC0_IRQHandler, // 38: ADC0 + Reserved39_IRQHandler, // 39: Reserved interrupt + ACMP_IRQHandler, // 40: ACMP interrupts + Reserved41_IRQHandler, // 41: Reserved interrupt + Reserved42_IRQHandler, // 42: Reserved interrupt + USB0_NEEDCLK_IRQHandler, // 43: USB Activity Wake-up Interrupt + USB0_IRQHandler, // 44: USB device + RTC_IRQHandler, // 45: RTC alarm and wake-up interrupts + Reserved46_IRQHandler, // 46: Reserved interrupt + MAILBOX_IRQHandler, // 47: WAKEUP,Mailbox interrupt (present on selected devices) + PIN_INT4_IRQHandler, // 48: Pin interrupt 4 or pattern match engine slice 4 int + PIN_INT5_IRQHandler, // 49: Pin interrupt 5 or pattern match engine slice 5 int + PIN_INT6_IRQHandler, // 50: Pin interrupt 6 or pattern match engine slice 6 int + PIN_INT7_IRQHandler, // 51: Pin interrupt 7 or pattern match engine slice 7 int + CTIMER2_IRQHandler, // 52: Standard counter/timer CTIMER2 + CTIMER4_IRQHandler, // 53: Standard counter/timer CTIMER4 + OS_EVENT_IRQHandler, // 54: OSEVTIMER0 and OSEVTIMER0_WAKEUP interrupts + Reserved55_IRQHandler, // 55: Reserved interrupt + Reserved56_IRQHandler, // 56: Reserved interrupt + Reserved57_IRQHandler, // 57: Reserved interrupt + SDIO_IRQHandler, // 58: SD/MMC + Reserved59_IRQHandler, // 59: Reserved interrupt + Reserved60_IRQHandler, // 60: Reserved interrupt + Reserved61_IRQHandler, // 61: Reserved interrupt + USB1_UTMI_IRQHandler, // 62: USB1_UTMI + USB1_IRQHandler, // 63: USB1 interrupt + USB1_NEEDCLK_IRQHandler, // 64: USB1 activity + SEC_HYPERVISOR_CALL_IRQHandler, // 65: SEC_HYPERVISOR_CALL interrupt + SEC_GPIO_INT0_IRQ0_IRQHandler, // 66: SEC_GPIO_INT0_IRQ0 interrupt + SEC_GPIO_INT0_IRQ1_IRQHandler, // 67: SEC_GPIO_INT0_IRQ1 interrupt + PLU_IRQHandler, // 68: PLU interrupt + SEC_VIO_IRQHandler, // 69: SEC_VIO interrupt + HASHCRYPT_IRQHandler, // 70: HASHCRYPT interrupt + CASER_IRQHandler, // 71: CASPER interrupt + PUF_IRQHandler, // 72: PUF interrupt + PQ_IRQHandler, // 73: PQ interrupt + DMA1_IRQHandler, // 74: DMA1 interrupt + FLEXCOMM8_IRQHandler, // 75: Flexcomm Interface 8 (SPI, , FLEXCOMM) + +}; /* End of g_pfnVectors */ + +//***************************************************************************** +// Functions to carry out the initialization of RW and BSS data sections. These +// are written as separate functions rather than being inlined within the +// ResetISR() function in order to cope with MCUs with multiple banks of +// memory. +//***************************************************************************** +__attribute__ ((section(".after_vectors.init_data"))) +void data_init(unsigned int romstart, unsigned int start, unsigned int len) { + unsigned int *pulDest = (unsigned int*) start; + unsigned int *pulSrc = (unsigned int*) romstart; + unsigned int loop; + for (loop = 0; loop < len; loop = loop + 4) + *pulDest++ = *pulSrc++; +} + +__attribute__ ((section(".after_vectors.init_bss"))) +void bss_init(unsigned int start, unsigned int len) { + unsigned int *pulDest = (unsigned int*) start; + unsigned int loop; + for (loop = 0; loop < len; loop = loop + 4) + *pulDest++ = 0; +} + +//***************************************************************************** +// The following symbols are constructs generated by the linker, indicating +// the location of various points in the "Global Section Table". This table is +// created by the linker via the Code Red managed linker script mechanism. It +// contains the load address, execution address and length of each RW data +// section and the execution and length of each BSS (zero initialized) section. +//***************************************************************************** +extern unsigned int __data_section_table; +extern unsigned int __data_section_table_end; +extern unsigned int __bss_section_table; +extern unsigned int __bss_section_table_end; + +//***************************************************************************** +// Reset entry point for your code. +// Sets up a simple runtime environment and initializes the C/C++ +// library. +//***************************************************************************** +__attribute__ ((section(".after_vectors.reset"))) +void ResetISR(void) { + + // Disable interrupts + __asm volatile ("cpsid i"); + + + +#if defined (__USE_CMSIS) +// If __USE_CMSIS defined, then call CMSIS SystemInit code + SystemInit(); + +#endif // (__USE_CMSIS) + + // + // Copy the data sections from flash to SRAM. + // + unsigned int LoadAddr, ExeAddr, SectionLen; + unsigned int *SectionTableAddr; + + // Load base address of Global Section Table + SectionTableAddr = &__data_section_table; + + // Copy the data sections from flash to SRAM. + while (SectionTableAddr < &__data_section_table_end) { + LoadAddr = *SectionTableAddr++; + ExeAddr = *SectionTableAddr++; + SectionLen = *SectionTableAddr++; + data_init(LoadAddr, ExeAddr, SectionLen); + } + + // At this point, SectionTableAddr = &__bss_section_table; + // Zero fill the bss segment + while (SectionTableAddr < &__bss_section_table_end) { + ExeAddr = *SectionTableAddr++; + SectionLen = *SectionTableAddr++; + bss_init(ExeAddr, SectionLen); + } + + +#if !defined (__USE_CMSIS) +// Assume that if __USE_CMSIS defined, then CMSIS SystemInit code +// will setup the VTOR register + + // Check to see if we are running the code from a non-zero + // address (eg RAM, external flash), in which case we need + // to modify the VTOR register to tell the CPU that the + // vector table is located at a non-0x0 address. + unsigned int * pSCB_VTOR = (unsigned int *) 0xE000ED08; + if ((unsigned int *)g_pfnVectors!=(unsigned int *) 0x00000000) { + *pSCB_VTOR = (unsigned int)g_pfnVectors; + } +#endif // (__USE_CMSIS) +#if defined (__cplusplus) + // + // Call C++ library initialisation + // + __libc_init_array(); +#endif + + // Reenable interrupts + __asm volatile ("cpsie i"); + +#if defined (__REDLIB__) + // Call the Redlib library, which in turn calls main() + __main(); +#else + main(); +#endif + + // + // main() shouldn't return, but if it does, we'll just enter an infinite loop + // + while (1) { + ; + } +} + +//***************************************************************************** +// Default core exception handlers. Override the ones here by defining your own +// handler routines in your application code. +//***************************************************************************** +WEAK_AV void NMI_Handler(void) +{ while(1) {} +} + +WEAK_AV void HardFault_Handler(void) +{ while(1) {} +} + +WEAK_AV void MemManage_Handler(void) +{ while(1) {} +} + +WEAK_AV void BusFault_Handler(void) +{ while(1) {} +} + +WEAK_AV void UsageFault_Handler(void) +{ while(1) {} +} + +WEAK_AV void SecureFault_Handler(void) +{ while(1) {} +} + +WEAK_AV void SVC_Handler(void) +{ while(1) {} +} + +WEAK_AV void DebugMon_Handler(void) +{ while(1) {} +} + +WEAK_AV void PendSV_Handler(void) +{ while(1) {} +} + +WEAK_AV void SysTick_Handler(void) +{ while(1) {} +} + +//***************************************************************************** +// Processor ends up here if an unexpected interrupt occurs or a specific +// handler is not present in the application code. +//***************************************************************************** +WEAK_AV void IntDefaultHandler(void) +{ while(1) {} +} + +//***************************************************************************** +// Default application exception handlers. Override the ones here by defining +// your own handler routines in your application code. These routines call +// driver exception handlers or IntDefaultHandler() if no driver exception +// handler is included. +//***************************************************************************** +WEAK void WDT_BOD_IRQHandler(void) +{ WDT_BOD_DriverIRQHandler(); +} + +WEAK void DMA0_IRQHandler(void) +{ DMA0_DriverIRQHandler(); +} + +WEAK void GINT0_IRQHandler(void) +{ GINT0_DriverIRQHandler(); +} + +WEAK void GINT1_IRQHandler(void) +{ GINT1_DriverIRQHandler(); +} + +WEAK void PIN_INT0_IRQHandler(void) +{ PIN_INT0_DriverIRQHandler(); +} + +WEAK void PIN_INT1_IRQHandler(void) +{ PIN_INT1_DriverIRQHandler(); +} + +WEAK void PIN_INT2_IRQHandler(void) +{ PIN_INT2_DriverIRQHandler(); +} + +WEAK void PIN_INT3_IRQHandler(void) +{ PIN_INT3_DriverIRQHandler(); +} + +WEAK void UTICK0_IRQHandler(void) +{ UTICK0_DriverIRQHandler(); +} + +WEAK void MRT0_IRQHandler(void) +{ MRT0_DriverIRQHandler(); +} + +WEAK void CTIMER0_IRQHandler(void) +{ CTIMER0_DriverIRQHandler(); +} + +WEAK void CTIMER1_IRQHandler(void) +{ CTIMER1_DriverIRQHandler(); +} + +WEAK void SCT0_IRQHandler(void) +{ SCT0_DriverIRQHandler(); +} + +WEAK void CTIMER3_IRQHandler(void) +{ CTIMER3_DriverIRQHandler(); +} + +WEAK void FLEXCOMM0_IRQHandler(void) +{ FLEXCOMM0_DriverIRQHandler(); +} + +WEAK void FLEXCOMM1_IRQHandler(void) +{ FLEXCOMM1_DriverIRQHandler(); +} + +WEAK void FLEXCOMM2_IRQHandler(void) +{ FLEXCOMM2_DriverIRQHandler(); +} + +WEAK void FLEXCOMM3_IRQHandler(void) +{ FLEXCOMM3_DriverIRQHandler(); +} + +WEAK void FLEXCOMM4_IRQHandler(void) +{ FLEXCOMM4_DriverIRQHandler(); +} + +WEAK void FLEXCOMM5_IRQHandler(void) +{ FLEXCOMM5_DriverIRQHandler(); +} + +WEAK void FLEXCOMM6_IRQHandler(void) +{ FLEXCOMM6_DriverIRQHandler(); +} + +WEAK void FLEXCOMM7_IRQHandler(void) +{ FLEXCOMM7_DriverIRQHandler(); +} + +WEAK void ADC0_IRQHandler(void) +{ ADC0_DriverIRQHandler(); +} + +WEAK void Reserved39_IRQHandler(void) +{ Reserved39_DriverIRQHandler(); +} + +WEAK void ACMP_IRQHandler(void) +{ ACMP_DriverIRQHandler(); +} + +WEAK void Reserved41_IRQHandler(void) +{ Reserved41_DriverIRQHandler(); +} + +WEAK void Reserved42_IRQHandler(void) +{ Reserved42_DriverIRQHandler(); +} + +WEAK void USB0_NEEDCLK_IRQHandler(void) +{ USB0_NEEDCLK_DriverIRQHandler(); +} + +WEAK void USB0_IRQHandler(void) +{ USB0_DriverIRQHandler(); +} + +WEAK void RTC_IRQHandler(void) +{ RTC_DriverIRQHandler(); +} + +WEAK void Reserved46_IRQHandler(void) +{ Reserved46_DriverIRQHandler(); +} + +WEAK void MAILBOX_IRQHandler(void) +{ MAILBOX_DriverIRQHandler(); +} + +WEAK void PIN_INT4_IRQHandler(void) +{ PIN_INT4_DriverIRQHandler(); +} + +WEAK void PIN_INT5_IRQHandler(void) +{ PIN_INT5_DriverIRQHandler(); +} + +WEAK void PIN_INT6_IRQHandler(void) +{ PIN_INT6_DriverIRQHandler(); +} + +WEAK void PIN_INT7_IRQHandler(void) +{ PIN_INT7_DriverIRQHandler(); +} + +WEAK void CTIMER2_IRQHandler(void) +{ CTIMER2_DriverIRQHandler(); +} + +WEAK void CTIMER4_IRQHandler(void) +{ CTIMER4_DriverIRQHandler(); +} + +WEAK void OS_EVENT_IRQHandler(void) +{ OS_EVENT_DriverIRQHandler(); +} + +WEAK void Reserved55_IRQHandler(void) +{ Reserved55_DriverIRQHandler(); +} + +WEAK void Reserved56_IRQHandler(void) +{ Reserved56_DriverIRQHandler(); +} + +WEAK void Reserved57_IRQHandler(void) +{ Reserved57_DriverIRQHandler(); +} + +WEAK void SDIO_IRQHandler(void) +{ SDIO_DriverIRQHandler(); +} + +WEAK void Reserved59_IRQHandler(void) +{ Reserved59_DriverIRQHandler(); +} + +WEAK void Reserved60_IRQHandler(void) +{ Reserved60_DriverIRQHandler(); +} + +WEAK void Reserved61_IRQHandler(void) +{ Reserved61_DriverIRQHandler(); +} + +WEAK void USB1_UTMI_IRQHandler(void) +{ USB1_UTMI_DriverIRQHandler(); +} + +WEAK void USB1_IRQHandler(void) +{ USB1_DriverIRQHandler(); +} + +WEAK void USB1_NEEDCLK_IRQHandler(void) +{ USB1_NEEDCLK_DriverIRQHandler(); +} + +WEAK void SEC_HYPERVISOR_CALL_IRQHandler(void) +{ SEC_HYPERVISOR_CALL_DriverIRQHandler(); +} + +WEAK void SEC_GPIO_INT0_IRQ0_IRQHandler(void) +{ SEC_GPIO_INT0_IRQ0_DriverIRQHandler(); +} + +WEAK void SEC_GPIO_INT0_IRQ1_IRQHandler(void) +{ SEC_GPIO_INT0_IRQ1_DriverIRQHandler(); +} + +WEAK void PLU_IRQHandler(void) +{ PLU_DriverIRQHandler(); +} + +WEAK void SEC_VIO_IRQHandler(void) +{ SEC_VIO_DriverIRQHandler(); +} + +WEAK void HASHCRYPT_IRQHandler(void) +{ HASHCRYPT_DriverIRQHandler(); +} + +WEAK void CASER_IRQHandler(void) +{ CASER_DriverIRQHandler(); +} + +WEAK void PUF_IRQHandler(void) +{ PUF_DriverIRQHandler(); +} + +WEAK void PQ_IRQHandler(void) +{ PQ_DriverIRQHandler(); +} + +WEAK void DMA1_IRQHandler(void) +{ DMA1_DriverIRQHandler(); +} + +WEAK void FLEXCOMM8_IRQHandler(void) +{ FLEXCOMM8_DriverIRQHandler(); +} + +//***************************************************************************** + +#if defined (DEBUG) +#pragma GCC pop_options +#endif // (DEBUG) diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/system_LPC55S69_cm33_core0.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/system_LPC55S69_cm33_core0.c new file mode 100644 index 000000000..aedd4504f --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/system_LPC55S69_cm33_core0.c @@ -0,0 +1,363 @@ +/* +** ################################################################### +** Processors: LPC55S69JBD100_cm33_core0 +** LPC55S69JET98_cm33_core0 +** +** Compilers: GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.4 25 Sep 2018 +** Version: rev. 1.0, 2018-08-22 +** Build: b181219 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2018-08-22) +** Initial version based on v0.2UM +** +** ################################################################### +*/ + +/*! + * @file LPC55S69_cm33_core0 + * @version 1.0 + * @date 2018-08-22 + * @brief Device specific configuration file for LPC55S69_cm33_core0 + * (implementation file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#include +#include "fsl_device_registers.h" + +/* PLL0 SSCG control1 */ +#define PLL_SSCG_MD_FRACT_P 0U +#define PLL_SSCG_MD_INT_P 25U +#define PLL_SSCG_MD_FRACT_M (0x1FFFFFFUL << PLL_SSCG_MD_FRACT_P) +#define PLL_SSCG_MD_INT_M ((uint64_t)0xFFUL << PLL_SSCG_MD_INT_P) + +/* Get predivider (N) from PLL0 NDEC setting */ +static uint32_t findPll0PreDiv(void) +{ + uint32_t preDiv = 1; + + /* Direct input is not used? */ + if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPREDIV_MASK) == 0) + { + preDiv = SYSCON->PLL0NDEC & SYSCON_PLL0NDEC_NDIV_MASK; + if (preDiv == 0) + { + preDiv = 1; + } + } + return preDiv; +} + +/* Get postdivider (P) from PLL0 PDEC setting */ +static uint32_t findPll0PostDiv(void) +{ + uint32_t postDiv = 1; + + if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK) == 0) + { + if (SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK) + { + postDiv = SYSCON->PLL0PDEC & SYSCON_PLL0PDEC_PDIV_MASK; + } + else + { + postDiv = 2 * (SYSCON->PLL0PDEC & SYSCON_PLL0PDEC_PDIV_MASK); + } + if (postDiv == 0) + { + postDiv = 2; + } + } + return postDiv; +} + +/* Get multiplier (M) from PLL0 SSCG and SEL_EXT settings */ +static float findPll0MMult(void) +{ + float mMult = 1; + float mMult_fract; + uint32_t mMult_int; + + if (SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_SEL_EXT_MASK) + { + mMult = (SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) >> SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT; + } + else + { + mMult_int = ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MD_MBS_MASK) << 7U) | ((SYSCON->PLL0SSCG0) >> PLL_SSCG_MD_INT_P); + mMult_fract = ((float)((SYSCON->PLL0SSCG0) & PLL_SSCG_MD_FRACT_M)/(1 << PLL_SSCG_MD_INT_P)); + mMult = (float)mMult_int + mMult_fract; + } + if (mMult == 0) + { + mMult = 1; + } + return mMult; +} + +/* Get predivider (N) from PLL1 NDEC setting */ +static uint32_t findPll1PreDiv(void) +{ + uint32_t preDiv = 1; + + /* Direct input is not used? */ + if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPREDIV_MASK) == 0) + { + preDiv = SYSCON->PLL1NDEC & SYSCON_PLL1NDEC_NDIV_MASK; + if (preDiv == 0) + { + preDiv = 1; + } + } + return preDiv; +} + +/* Get postdivider (P) from PLL1 PDEC setting */ +static uint32_t findPll1PostDiv(void) +{ + uint32_t postDiv = 1; + + if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPOSTDIV_MASK) == 0) + { + if (SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPOSTDIV2_MASK) + { + postDiv = SYSCON->PLL1PDEC & SYSCON_PLL1PDEC_PDIV_MASK; + } + else + { + postDiv = 2 * (SYSCON->PLL1PDEC & SYSCON_PLL1PDEC_PDIV_MASK); + } + if (postDiv == 0) + { + postDiv = 2; + } + } + return postDiv; +} + +/* Get multiplier (M) from PLL1 MDEC settings */ +static uint32_t findPll1MMult(void) +{ + uint32_t mMult = 1; + + mMult = SYSCON->PLL1MDEC & SYSCON_PLL1MDEC_MDIV_MASK; + + if (mMult == 0) + { + mMult = 1; + } + return mMult; +} + +/* Get FRO 12M Clk */ +/*! brief Return Frequency of FRO 12MHz + * return Frequency of FRO 12MHz + */ +static uint32_t CLOCK_GetFro12MFreq(void) +{ + return (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_FRO192M_MASK) ? + 0 : + (ANACTRL->FRO192M_CTRL & ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK) ? 12000000U : 0U; +} + +/* Get FRO 1M Clk */ +/*! brief Return Frequency of FRO 1MHz + * return Frequency of FRO 1MHz + */ +static uint32_t CLOCK_GetFro1MFreq(void) +{ + return (SYSCON->CLOCK_CTRL & SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK) ? 1000000U : 0U; +} + +/* Get EXT OSC Clk */ +/*! brief Return Frequency of External Clock + * return Frequency of External Clock. If no external clock is used returns 0. + */ +static uint32_t CLOCK_GetExtClkFreq(void) +{ + return (ANACTRL->XO32M_CTRL & ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK) ? CLK_CLK_IN : 0U; +} + +/* Get HF FRO Clk */ +/*! brief Return Frequency of High-Freq output of FRO + * return Frequency of High-Freq output of FRO + */ +static uint32_t CLOCK_GetFroHfFreq(void) +{ + return (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_FRO192M_MASK) ? + 0 : + (ANACTRL->FRO192M_CTRL & ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK) ? 96000000U : 0U; +} + +/* Get RTC OSC Clk */ +/*! brief Return Frequency of 32kHz osc + * return Frequency of 32kHz osc + */ +static uint32_t CLOCK_GetOsc32KFreq(void) +{ + return ((!(PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_FRO32K_MASK)) && (!(PMC->RTCOSC32K & PMC_RTCOSC32K_SEL_MASK))) ? + CLK_RTC_32K_CLK : + ((!(PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_XTAL32K_MASK)) && (PMC->RTCOSC32K & PMC_RTCOSC32K_SEL_MASK)) ? + CLK_RTC_32K_CLK : + 0U; +} + + + +/* ---------------------------------------------------------------------------- + -- Core clock + ---------------------------------------------------------------------------- */ + +uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; + +/* ---------------------------------------------------------------------------- + -- SystemInit() + ---------------------------------------------------------------------------- */ + +__attribute__ ((weak)) void SystemInit (void) { +#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) + SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */ +#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ + + SCB->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access (enable PowerQuad) */ + + SCB->NSACR |= ((3UL << 0) | (3UL << 10)); /* enable CP0, CP1, CP10, CP11 Non-secure Access */ + +#if defined(__MCUXPRESSO) + extern void(*const g_pfnVectors[]) (void); + SCB->VTOR = (uint32_t) &g_pfnVectors; +#else + extern void *__Vectors; + SCB->VTOR = (uint32_t) &__Vectors; +#endif + SystemInitHook(); +} + +/* ---------------------------------------------------------------------------- + -- SystemCoreClockUpdate() + ---------------------------------------------------------------------------- */ + +void SystemCoreClockUpdate (void) { + uint32_t clkRate = 0; + uint32_t prediv, postdiv; + float workRate; + uint64_t workRate1; + + switch (SYSCON->MAINCLKSELB & SYSCON_MAINCLKSELB_SEL_MASK) + { + case 0x00: /* MAINCLKSELA clock (main_clk_a)*/ + switch (SYSCON->MAINCLKSELA & SYSCON_MAINCLKSELA_SEL_MASK) + { + case 0x00: /* FRO 12 MHz (fro_12m) */ + clkRate = CLOCK_GetFro12MFreq(); + break; + case 0x01: /* CLKIN (clk_in) */ + clkRate = CLOCK_GetExtClkFreq(); + break; + case 0x02: /* Fro 1MHz (fro_1m) */ + clkRate = CLOCK_GetFro1MFreq(); + break; + default: /* = 0x03 = FRO 96 MHz (fro_hf) */ + clkRate = CLOCK_GetFroHfFreq(); + break; + } + break; + case 0x01: /* PLL0 clock (pll0_clk)*/ + switch (SYSCON->PLL0CLKSEL & SYSCON_PLL0CLKSEL_SEL_MASK) + { + case 0x00: /* FRO 12 MHz (fro_12m) */ + clkRate = CLOCK_GetFro12MFreq(); + break; + case 0x01: /* CLKIN (clk_in) */ + clkRate = CLOCK_GetExtClkFreq(); + break; + case 0x02: /* Fro 1MHz (fro_1m) */ + clkRate = CLOCK_GetFro1MFreq(); + break; + case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */ + clkRate = CLOCK_GetOsc32KFreq(); + break; + default: + break; + } + if (((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPLL_MASK) == 0) && (SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_CLKEN_MASK) && ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_MASK) == 0) && ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK) == 0)) + { + prediv = findPll0PreDiv(); + postdiv = findPll0PostDiv(); + /* Adjust input clock */ + clkRate = clkRate / prediv; + /* MDEC used for rate */ + workRate = (float)clkRate * (float)findPll0MMult(); + clkRate = (uint32_t)(workRate / ((float)postdiv)); + } + break; + case 0x02: /* PLL1 clock (pll1_clk)*/ + switch (SYSCON->PLL1CLKSEL & SYSCON_PLL1CLKSEL_SEL_MASK) + { + case 0x00: /* FRO 12 MHz (fro_12m) */ + clkRate = CLOCK_GetFro12MFreq(); + break; + case 0x01: /* CLKIN (clk_in) */ + clkRate = CLOCK_GetExtClkFreq(); + break; + case 0x02: /* Fro 1MHz (fro_1m) */ + clkRate = CLOCK_GetFro1MFreq(); + break; + case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */ + clkRate = CLOCK_GetOsc32KFreq(); + break; + default: + break; + } + if (((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPLL_MASK) == 0) && (SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_CLKEN_MASK) && ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL1_MASK) == 0)) + { + /* PLL is not in bypass mode, get pre-divider, post-divider, and M divider */ + prediv = findPll1PreDiv(); + postdiv = findPll1PostDiv(); + /* Adjust input clock */ + clkRate = clkRate / prediv; + + /* MDEC used for rate */ + workRate1 = (uint64_t)clkRate * (uint64_t)findPll1MMult(); + clkRate = workRate1 / ((uint64_t)postdiv); + } + break; + case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */ + clkRate = CLOCK_GetOsc32KFreq(); + break; + default: + break; + } + SystemCoreClock = clkRate / ((SYSCON->AHBCLKDIV & 0xFF) + 1); +} + +/* ---------------------------------------------------------------------------- + -- SystemInitHook() + ---------------------------------------------------------------------------- */ + +__attribute__ ((weak)) void SystemInitHook (void) { + /* Void implementation of the weak function. */ +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/system_LPC55S69_cm33_core0.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/system_LPC55S69_cm33_core0.h new file mode 100644 index 000000000..705e6508a --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/system_LPC55S69_cm33_core0.h @@ -0,0 +1,110 @@ +/* +** ################################################################### +** Processors: LPC55S69JBD100_cm33_core0 +** LPC55S69JET98_cm33_core0 +** +** Compilers: GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.4 25 Sep 2018 +** Version: rev. 1.0, 2018-08-22 +** Build: b181219 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2018-08-22) +** Initial version based on v0.2UM +** +** ################################################################### +*/ + +/*! + * @file LPC55S69_cm33_core0 + * @version 1.0 + * @date 2018-08-22 + * @brief Device specific configuration file for LPC55S69_cm33_core0 (header + * file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#ifndef _SYSTEM_LPC55S69_cm33_core0_H_ +#define _SYSTEM_LPC55S69_cm33_core0_H_ /**< Symbol preventing repeated inclusion */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#define DEFAULT_SYSTEM_CLOCK 12000000u /* Default System clock value */ +#define CLK_RTC_32K_CLK 32768u /* RTC oscillator 32 kHz output (32k_clk */ +#define CLK_FRO_12MHZ 12000000u /* FRO 12 MHz (fro_12m) */ +#define CLK_FRO_48MHZ 48000000u /* FRO 48 MHz (fro_48m) */ +#define CLK_FRO_96MHZ 96000000u /* FRO 96 MHz (fro_96m) */ +#define CLK_CLK_IN 16000000u /* Default CLK_IN pin clock */ + + +/** + * @brief System clock frequency (core clock) + * + * The system clock frequency supplied to the SysTick timer and the processor + * core clock. This variable can be used by the user application to setup the + * SysTick timer or configure other parameters. It may also be used by debugger to + * query the frequency of the debug timer or configure the trace clock speed + * SystemCoreClock is initialized with a correct predefined value. + */ +extern uint32_t SystemCoreClock; + +/** + * @brief Setup the microcontroller system. + * + * Typically this function configures the oscillator (PLL) that is part of the + * microcontroller device. For systems with variable clock speed it also updates + * the variable SystemCoreClock. SystemInit is called from startup_device file. + */ +void SystemInit (void); + +/** + * @brief Updates the SystemCoreClock variable. + * + * It must be called whenever the core clock is changed during program + * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates + * the current core clock. + */ +void SystemCoreClockUpdate (void); + +/** + * @brief SystemInit function hook. + * + * This weak function allows to call specific initialization code during the + * SystemInit() execution.This can be used when an application specific code needs + * to be called as close to the reset entry as possible (for example the Multicore + * Manager MCMGR_EarlyInit() function call). + * NOTE: No global r/w variables can be used in this hook function because the + * initialization of these variables happens after this function. + */ +void SystemInitHook (void); + +#ifdef __cplusplus +} +#endif + +#endif /* _SYSTEM_LPC55S69_cm33_core0_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/system_LPC55S69_cm33_core1.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/system_LPC55S69_cm33_core1.c new file mode 100644 index 000000000..0b684c517 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/system_LPC55S69_cm33_core1.c @@ -0,0 +1,366 @@ +/* +** ################################################################### +** Processors: LPC55S69JBD100_cm33_core1 +** LPC55S69JET98_cm33_core1 +** +** Compilers: GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.4 25 Sep 2018 +** Version: rev. 1.0, 2018-08-22 +** Build: b181219 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2018-08-22) +** Initial version based on v0.2UM +** +** ################################################################### +*/ + +/*! + * @file LPC55S69_cm33_core1 + * @version 1.0 + * @date 2018-08-22 + * @brief Device specific configuration file for LPC55S69_cm33_core1 + * (implementation file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#include +#include "fsl_device_registers.h" + +/* PLL0 SSCG control1 */ +#define PLL_SSCG_MD_FRACT_P 0U +#define PLL_SSCG_MD_INT_P 25U +#define PLL_SSCG_MD_FRACT_M (0x1FFFFFFUL << PLL_SSCG_MD_FRACT_P) +#define PLL_SSCG_MD_INT_M ((uint64_t)0xFFUL << PLL_SSCG_MD_INT_P) + +/* Get predivider (N) from PLL0 NDEC setting */ +static uint32_t findPll0PreDiv(void) +{ + uint32_t preDiv = 1; + + /* Direct input is not used? */ + if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPREDIV_MASK) == 0) + { + preDiv = SYSCON->PLL0NDEC & SYSCON_PLL0NDEC_NDIV_MASK; + if (preDiv == 0) + { + preDiv = 1; + } + } + return preDiv; +} + +/* Get postdivider (P) from PLL0 PDEC setting */ +static uint32_t findPll0PostDiv(void) +{ + uint32_t postDiv = 1; + + if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK) == 0) + { + if (SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK) + { + postDiv = SYSCON->PLL0PDEC & SYSCON_PLL0PDEC_PDIV_MASK; + } + else + { + postDiv = 2 * (SYSCON->PLL0PDEC & SYSCON_PLL0PDEC_PDIV_MASK); + } + if (postDiv == 0) + { + postDiv = 2; + } + } + return postDiv; +} + +/* Get multiplier (M) from PLL0 SSCG and SEL_EXT settings */ +static float findPll0MMult(void) +{ + float mMult = 1; + float mMult_fract; + uint32_t mMult_int; + + if (SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_SEL_EXT_MASK) + { + mMult = (SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) >> SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT; + } + else + { + mMult_int = ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MD_MBS_MASK) << 7U) | ((SYSCON->PLL0SSCG0) >> PLL_SSCG_MD_INT_P); + mMult_fract = ((float)((SYSCON->PLL0SSCG0) & PLL_SSCG_MD_FRACT_M)/(1 << PLL_SSCG_MD_INT_P)); + mMult = (float)mMult_int + mMult_fract; + } + if (mMult == 0) + { + mMult = 1; + } + return mMult; +} + +/* Get predivider (N) from PLL1 NDEC setting */ +static uint32_t findPll1PreDiv(void) +{ + uint32_t preDiv = 1; + + /* Direct input is not used? */ + if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPREDIV_MASK) == 0) + { + preDiv = SYSCON->PLL1NDEC & SYSCON_PLL1NDEC_NDIV_MASK; + if (preDiv == 0) + { + preDiv = 1; + } + } + return preDiv; +} + +/* Get postdivider (P) from PLL1 PDEC setting */ +static uint32_t findPll1PostDiv(void) +{ + uint32_t postDiv = 1; + + if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPOSTDIV_MASK) == 0) + { + if (SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPOSTDIV2_MASK) + { + postDiv = SYSCON->PLL1PDEC & SYSCON_PLL1PDEC_PDIV_MASK; + } + else + { + postDiv = 2 * (SYSCON->PLL1PDEC & SYSCON_PLL1PDEC_PDIV_MASK); + } + if (postDiv == 0) + { + postDiv = 2; + } + } + return postDiv; +} + +/* Get multiplier (M) from PLL1 MDEC settings */ +static uint32_t findPll1MMult(void) +{ + uint32_t mMult = 1; + + mMult = SYSCON->PLL1MDEC & SYSCON_PLL1MDEC_MDIV_MASK; + + if (mMult == 0) + { + mMult = 1; + } + return mMult; +} + +/* Get FRO 12M Clk */ +/*! brief Return Frequency of FRO 12MHz + * return Frequency of FRO 12MHz + */ +static uint32_t CLOCK_GetFro12MFreq(void) +{ + return (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_FRO192M_MASK) ? + 0 : + (ANACTRL->FRO192M_CTRL & ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK) ? 12000000U : 0U; +} + +/* Get FRO 1M Clk */ +/*! brief Return Frequency of FRO 1MHz + * return Frequency of FRO 1MHz + */ +static uint32_t CLOCK_GetFro1MFreq(void) +{ + return (SYSCON->CLOCK_CTRL & SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK) ? 1000000U : 0U; +} + +/* Get EXT OSC Clk */ +/*! brief Return Frequency of External Clock + * return Frequency of External Clock. If no external clock is used returns 0. + */ +static uint32_t CLOCK_GetExtClkFreq(void) +{ + return (ANACTRL->XO32M_CTRL & ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK) ? CLK_CLK_IN : 0U; +} + +/* Get HF FRO Clk */ +/*! brief Return Frequency of High-Freq output of FRO + * return Frequency of High-Freq output of FRO + */ +static uint32_t CLOCK_GetFroHfFreq(void) +{ + return (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_FRO192M_MASK) ? + 0 : + (ANACTRL->FRO192M_CTRL & ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK) ? 96000000U : 0U; +} + +/* Get RTC OSC Clk */ +/*! brief Return Frequency of 32kHz osc + * return Frequency of 32kHz osc + */ +static uint32_t CLOCK_GetOsc32KFreq(void) +{ + return ((!(PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_FRO32K_MASK)) && (!(PMC->RTCOSC32K & PMC_RTCOSC32K_SEL_MASK))) ? + CLK_RTC_32K_CLK : + ((!(PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_XTAL32K_MASK)) && (PMC->RTCOSC32K & PMC_RTCOSC32K_SEL_MASK)) ? + CLK_RTC_32K_CLK : + 0U; +} + + + +/* ---------------------------------------------------------------------------- + -- Core clock + ---------------------------------------------------------------------------- */ + +uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; + +/* ---------------------------------------------------------------------------- + -- SystemInit() + ---------------------------------------------------------------------------- */ + +void SystemInit (void) { + + SCB->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access (enable PowerQuad) */ + + SCB->NSACR |= ((3UL << 0) | (3UL << 10)); /* enable CP0, CP1, CP10, CP11 Non-secure Access */ + +#if defined(__MCUXPRESSO) + extern void(*const g_pfnVectors[]) (void); + SCB->VTOR = (uint32_t) &g_pfnVectors; +#else + extern void *__Vectors; + SCB->VTOR = (uint32_t) &__Vectors; +#endif + SYSCON->TRACECLKDIV = 0; +/* Optionally enable RAM banks that may be off by default at reset */ +#if !defined(DONT_ENABLE_DISABLED_RAMBANKS) + SYSCON->AHBCLKCTRLSET[0] = SYSCON_AHBCLKCTRL0_SRAM_CTRL1_MASK | SYSCON_AHBCLKCTRL0_SRAM_CTRL2_MASK + | SYSCON_AHBCLKCTRL0_SRAM_CTRL3_MASK | SYSCON_AHBCLKCTRL0_SRAM_CTRL4_MASK; +#endif + SystemInitHook(); +} + +/* ---------------------------------------------------------------------------- + -- SystemCoreClockUpdate() + ---------------------------------------------------------------------------- */ + +void SystemCoreClockUpdate (void) { + uint32_t clkRate = 0; + uint32_t prediv, postdiv; + float workRate; + uint64_t workRate1; + + switch (SYSCON->MAINCLKSELB & SYSCON_MAINCLKSELB_SEL_MASK) + { + case 0x00: /* MAINCLKSELA clock (main_clk_a)*/ + switch (SYSCON->MAINCLKSELA & SYSCON_MAINCLKSELA_SEL_MASK) + { + case 0x00: /* FRO 12 MHz (fro_12m) */ + clkRate = CLOCK_GetFro12MFreq(); + break; + case 0x01: /* CLKIN (clk_in) */ + clkRate = CLOCK_GetExtClkFreq(); + break; + case 0x02: /* Fro 1MHz (fro_1m) */ + clkRate = CLOCK_GetFro1MFreq(); + break; + default: /* = 0x03 = FRO 96 MHz (fro_hf) */ + clkRate = CLOCK_GetFroHfFreq(); + break; + } + break; + case 0x01: /* PLL0 clock (pll0_clk)*/ + switch (SYSCON->PLL0CLKSEL & SYSCON_PLL0CLKSEL_SEL_MASK) + { + case 0x00: /* FRO 12 MHz (fro_12m) */ + clkRate = CLOCK_GetFro12MFreq(); + break; + case 0x01: /* CLKIN (clk_in) */ + clkRate = CLOCK_GetExtClkFreq(); + break; + case 0x02: /* Fro 1MHz (fro_1m) */ + clkRate = CLOCK_GetFro1MFreq(); + break; + case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */ + clkRate = CLOCK_GetOsc32KFreq(); + break; + default: + break; + } + if (((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPLL_MASK) == 0) && (SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_CLKEN_MASK) && ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_MASK) == 0) && ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK) == 0)) + { + prediv = findPll0PreDiv(); + postdiv = findPll0PostDiv(); + /* Adjust input clock */ + clkRate = clkRate / prediv; + /* MDEC used for rate */ + workRate = (float)clkRate * (float)findPll0MMult(); + clkRate = (uint32_t)(workRate / ((float)postdiv)); + } + break; + case 0x02: /* PLL1 clock (pll1_clk)*/ + switch (SYSCON->PLL1CLKSEL & SYSCON_PLL1CLKSEL_SEL_MASK) + { + case 0x00: /* FRO 12 MHz (fro_12m) */ + clkRate = CLOCK_GetFro12MFreq(); + break; + case 0x01: /* CLKIN (clk_in) */ + clkRate = CLOCK_GetExtClkFreq(); + break; + case 0x02: /* Fro 1MHz (fro_1m) */ + clkRate = CLOCK_GetFro1MFreq(); + break; + case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */ + clkRate = CLOCK_GetOsc32KFreq(); + break; + default: + break; + } + if (((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPLL_MASK) == 0) && (SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_CLKEN_MASK) && ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL1_MASK) == 0)) + { + /* PLL is not in bypass mode, get pre-divider, post-divider, and M divider */ + prediv = findPll1PreDiv(); + postdiv = findPll1PostDiv(); + /* Adjust input clock */ + clkRate = clkRate / prediv; + + /* MDEC used for rate */ + workRate1 = (uint64_t)clkRate * (uint64_t)findPll1MMult(); + clkRate = workRate1 / ((uint64_t)postdiv); + } + break; + case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */ + clkRate = CLOCK_GetOsc32KFreq(); + break; + default: + break; + } + SystemCoreClock = clkRate / ((SYSCON->AHBCLKDIV & 0xFF) + 1); +} + +/* ---------------------------------------------------------------------------- + -- SystemInitHook() + ---------------------------------------------------------------------------- */ + +__attribute__ ((weak)) void SystemInitHook (void) { + /* Void implementation of the weak function. */ +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/system_LPC55S69_cm33_core1.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/system_LPC55S69_cm33_core1.h new file mode 100644 index 000000000..8da7ec5bd --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/system_LPC55S69_cm33_core1.h @@ -0,0 +1,110 @@ +/* +** ################################################################### +** Processors: LPC55S69JBD100_cm33_core1 +** LPC55S69JET98_cm33_core1 +** +** Compilers: GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.4 25 Sep 2018 +** Version: rev. 1.0, 2018-08-22 +** Build: b181219 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2018-08-22) +** Initial version based on v0.2UM +** +** ################################################################### +*/ + +/*! + * @file LPC55S69_cm33_core1 + * @version 1.0 + * @date 2018-08-22 + * @brief Device specific configuration file for LPC55S69_cm33_core1 (header + * file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#ifndef _SYSTEM_LPC55S69_cm33_core1_H_ +#define _SYSTEM_LPC55S69_cm33_core1_H_ /**< Symbol preventing repeated inclusion */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#define DEFAULT_SYSTEM_CLOCK 12000000u /* Default System clock value */ +#define CLK_RTC_32K_CLK 32768u /* RTC oscillator 32 kHz output (32k_clk */ +#define CLK_FRO_12MHZ 12000000u /* FRO 12 MHz (fro_12m) */ +#define CLK_FRO_48MHZ 48000000u /* FRO 48 MHz (fro_48m) */ +#define CLK_FRO_96MHZ 96000000u /* FRO 96 MHz (fro_96m) */ +#define CLK_CLK_IN 16000000u /* Default CLK_IN pin clock */ + + +/** + * @brief System clock frequency (core clock) + * + * The system clock frequency supplied to the SysTick timer and the processor + * core clock. This variable can be used by the user application to setup the + * SysTick timer or configure other parameters. It may also be used by debugger to + * query the frequency of the debug timer or configure the trace clock speed + * SystemCoreClock is initialized with a correct predefined value. + */ +extern uint32_t SystemCoreClock; + +/** + * @brief Setup the microcontroller system. + * + * Typically this function configures the oscillator (PLL) that is part of the + * microcontroller device. For systems with variable clock speed it also updates + * the variable SystemCoreClock. SystemInit is called from startup_device file. + */ +void SystemInit (void); + +/** + * @brief Updates the SystemCoreClock variable. + * + * It must be called whenever the core clock is changed during program + * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates + * the current core clock. + */ +void SystemCoreClockUpdate (void); + +/** + * @brief SystemInit function hook. + * + * This weak function allows to call specific initialization code during the + * SystemInit() execution.This can be used when an application specific code needs + * to be called as close to the reset entry as possible (for example the Multicore + * Manager MCMGR_EarlyInit() function call). + * NOTE: No global r/w variables can be used in this hook function because the + * initialization of these variables happens after this function. + */ +void SystemInitHook (void); + +#ifdef __cplusplus +} +#endif + +#endif /* _SYSTEM_LPC55S69_cm33_core1_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/SConscript b/bsp/lpc55sxx/Libraries/LPC55S6X/SConscript new file mode 100644 index 000000000..73a71bccc --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/SConscript @@ -0,0 +1,70 @@ +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() +path = [cwd + '/CMSIS/Include',cwd + '/components/codec', cwd + '/LPC55S6X', cwd + '/LPC55S6X/drivers', cwd + '/middleware/sdmmc/inc', cwd + '/middleware/sdmmc/port'] +src = Split(''' + LPC55S6X/system_LPC55S69_cm33_core0.c + ''') + +if rtconfig.CROSS_TOOL == 'gcc': + src += ['LPC55S6X/gcc/startup_LPC55S69_cm33_core0.S'] +elif rtconfig.CROSS_TOOL == 'keil': + src += ['LPC55S6X/arm/startup_LPC55S69_cm33_core0.s'] +elif rtconfig.CROSS_TOOL == 'iar': + src += ['LPC55S6X/iar/startup_LPC55S69_cm33_core0.s'] + +src += ['LPC55S6X/drivers/fsl_anactrl.c'] +src += ['LPC55S6X/drivers/fsl_casper.c'] +src += ['LPC55S6X/drivers/fsl_clock.c'] +src += ['LPC55S6X/drivers/fsl_cmp.c'] +src += ['LPC55S6X/drivers/fsl_common.c'] +src += ['LPC55S6X/drivers/fsl_crc.c'] +src += ['LPC55S6X/drivers/fsl_ctimer.c'] +src += ['LPC55S6X/drivers/fsl_flexcomm.c'] +src += ['LPC55S6X/drivers/fsl_dma.c'] +src += ['LPC55S6X/drivers/fsl_gint.c'] +src += ['LPC55S6X/drivers/fsl_gpio.c'] +src += ['LPC55S6X/drivers/fsl_hashcrypt.c'] +src += ['LPC55S6X/drivers/fsl_i2c.c'] +src += ['LPC55S6X/drivers/fsl_i2c_dma.c'] +src += ['LPC55S6X/drivers/fsl_i2s.c'] +src += ['LPC55S6X/drivers/fsl_i2s_dma.c'] +src += ['LPC55S6X/drivers/fsl_iap.c'] +src += ['LPC55S6X/drivers/fsl_inputmux.c'] +src += ['LPC55S6X/drivers/fsl_lpadc.c'] +src += ['LPC55S6X/drivers/fsl_mrt.c'] +src += ['LPC55S6X/drivers/fsl_ostimer.c'] +src += ['LPC55S6X/drivers/fsl_pint.c'] +src += ['LPC55S6X/drivers/fsl_plu.c'] +src += ['LPC55S6X/drivers/fsl_power.c'] +src += ['LPC55S6X/drivers/fsl_powerquad_basic.c'] +src += ['LPC55S6X/drivers/fsl_prince.c'] +src += ['LPC55S6X/drivers/fsl_puf.c'] +src += ['LPC55S6X/drivers/fsl_reset.c'] +src += ['LPC55S6X/drivers/fsl_rng.c'] +src += ['LPC55S6X/drivers/fsl_rtc.c'] +src += ['LPC55S6X/drivers/fsl_sctimer.c'] +src += ['LPC55S6X/drivers/fsl_sdif.c'] +src += ['LPC55S6X/drivers/fsl_spi.c'] +src += ['LPC55S6X/drivers/fsl_spi_dma.c'] +src += ['LPC55S6X/drivers/fsl_sysctl.c'] +src += ['LPC55S6X/drivers/fsl_usart.c'] +src += ['LPC55S6X/drivers/fsl_usart_dma.c'] +src += ['LPC55S6X/drivers/fsl_utick.c'] +src += ['LPC55S6X/drivers/fsl_wwdt.c'] +src += ['middleware/sdmmc/src/fsl_sd.c'] +src += ['middleware/sdmmc/src/fsl_sdmmc_common.c'] +src += ['middleware/sdmmc/port/sdif/rt_thread/fsl_sdmmc_event.c'] +src += ['middleware/sdmmc/port/sdif/rt_thread/fsl_sdmmc_host.c'] + +if rtconfig.CROSS_TOOL == 'gcc': + src += ['LPC55S6X/gcc/libpower_hardabi.a'] +elif rtconfig.CROSS_TOOL == 'keil': + src += ['LPC55S6X/arm/keil_lib_power_cm33_core0.lib'] +elif rtconfig.CROSS_TOOL == 'iar': + src += ['LPC55S6X/iar/iar_lib_power_cm33_core0.a'] + +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path) + +Return('group') diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/components/codec/fsl_codec_common.c b/bsp/lpc55sxx/Libraries/LPC55S6X/components/codec/fsl_codec_common.c new file mode 100644 index 000000000..95ae10a41 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/components/codec/fsl_codec_common.c @@ -0,0 +1,238 @@ +/* + * Copyright 2017-2019 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_codec_common.h" +#include "fsl_codec_adapter.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief codec play and record capability */ +#define GET_PLAY_CHANNEL_CAPABILITY(capability) (capability & 0xFFU) +#define GET_PLAY_SOURCE_CAPABILITY(capability) (capability >> 8U) +#define GET_RECORD_SOURCE_CAPABILITY(capability) (capability & 0x3FU) +#define GET_RECORD_CHANNEL_CAPABILITY(capability) (capability >> 6U) +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +/*! + * brief Codec initilization. + * + * param handle codec handle. + * param config codec configuration. + * return kStatus_Success is success, else initial failed. + */ +status_t CODEC_Init(codec_handle_t *handle, codec_config_t *config) +{ + assert((config != NULL) && (handle != NULL)); + + /* Set the handle information */ + handle->codecConfig = config; + + return HAL_CODEC_Init(handle, config); +} + +/*! + * brief Codec de-initilization. + * + * param handle codec handle. + * return kStatus_Success is success, else de-initial failed. + */ +status_t CODEC_Deinit(codec_handle_t *handle) +{ + assert((handle != NULL) && (handle->codecConfig != NULL)); + + return HAL_CODEC_Deinit(handle); +} + +/*! + * brief set audio data format. + * + * param handle codec handle. + * param mclk master clock frequency in HZ. + * param sampleRate sample rate in HZ. + * param bitWidth bit width. + * return kStatus_Success is success, else configure failed. + */ +status_t CODEC_SetFormat(codec_handle_t *handle, uint32_t mclk, uint32_t sampleRate, uint32_t bitWidth) +{ + assert((handle != NULL) && (handle->codecConfig != NULL)); + + return HAL_CODEC_SetFormat(handle, mclk, sampleRate, bitWidth); +} + +/*! + * brief codec module control. + * + * This function is used for codec module control, support switch digital interface cmd, can be expand to support codec + * module specific feature + * + * param handle codec handle. + * param cmd module control cmd, reference _codec_module_ctrl_cmd. + * param data value to write, when cmd is kCODEC_ModuleRecordSourceChannel, the data should be a value combine + * of channel and source, please reference macro CODEC_MODULE_RECORD_SOURCE_CHANNEL(source, LP, LN, RP, RN), reference + * codec specific driver for detail configurations. + * return kStatus_Success is success, else configure failed. + */ +status_t CODEC_ModuleControl(codec_handle_t *handle, codec_module_ctrl_cmd_t cmd, uint32_t data) +{ + assert((handle != NULL) && (handle->codecConfig != NULL)); + + switch (cmd) + { + case kCODEC_ModuleSwitchI2SInInterface: + if ((handle->codecCapability.codecModuleCapability & kCODEC_SupportModuleI2SInSwitchInterface) == 0U) + { + return kStatus_CODEC_NotSupport; + } + break; + + default: + return kStatus_CODEC_NotSupport; + } + + return HAL_CODEC_ModuleControl(handle, cmd, data); +} + +/*! + * brief set audio codec module volume. + * + * param handle codec handle. + * param channel audio codec play channel, can be a value or combine value of _codec_play_channel. + * param volume volume value, support 0 ~ 100, 0 is mute, 100 is the maximum volume value. + * return kStatus_Success is success, else configure failed. + */ +status_t CODEC_SetVolume(codec_handle_t *handle, uint32_t playChannel, uint32_t volume) +{ + assert((handle != NULL) && (handle->codecConfig != NULL)); + assert(volume <= CODEC_VOLUME_MAX_VALUE); + + /* check capability of set volume */ + if ((GET_PLAY_CHANNEL_CAPABILITY(handle->codecCapability.codecPlayCapability) & playChannel) == 0U) + { + return kStatus_CODEC_NotSupport; + } + + return HAL_CODEC_SetVolume(handle, playChannel, volume); +} + +/*! + * brief set audio codec module mute. + * + * param handle codec handle. + * param channel audio codec play channel, can be a value or combine value of _codec_play_channel. + * param mute true is mute, false is unmute. + * return kStatus_Success is success, else configure failed. + */ +status_t CODEC_SetMute(codec_handle_t *handle, uint32_t playChannel, bool mute) +{ + assert((handle != NULL) && (handle->codecConfig != NULL)); + + /* check capability of mute */ + if ((GET_PLAY_CHANNEL_CAPABILITY(handle->codecCapability.codecPlayCapability) & playChannel) == 0U) + { + return kStatus_CODEC_NotSupport; + } + + return HAL_CODEC_SetMute(handle, playChannel, mute); +} + +/*! + * brief set audio codec module power. + * + * param handle codec handle. + * param module audio codec module. + * param powerOn true is power on, false is power down. + * return kStatus_Success is success, else configure failed. + */ +status_t CODEC_SetPower(codec_handle_t *handle, codec_module_t module, bool powerOn) +{ + assert((handle != NULL) && (handle->codecConfig != NULL)); + + /* check capability of power switch */ + if ((handle->codecCapability.codecModuleCapability & (1U << module)) == 0U) + { + return kStatus_CODEC_NotSupport; + } + + return HAL_CODEC_SetPower(handle, module, powerOn); +} + +/*! + * brief codec set record source. + * + * param handle codec handle. + * param source audio codec record source, can be a value or combine value of _codec_record_source. + * + * return kStatus_Success is success, else configure failed. + */ +status_t CODEC_SetRecord(codec_handle_t *handle, uint32_t recordSource) +{ + assert((handle != NULL) && (handle->codecConfig != NULL)); + + /* check capability of record capability */ + if ((GET_RECORD_SOURCE_CAPABILITY(handle->codecCapability.codecRecordCapability) & recordSource) == 0U) + { + return kStatus_CODEC_NotSupport; + } + + return HAL_CODEC_SetRecord(handle, recordSource); +} + +/*! + * brief codec set record channel. + * + * param handle codec handle. + * param leftRecordChannel audio codec record channel, reference _codec_record_channel, can be a value or combine value + of member in _codec_record_channel. + * param rightRecordChannel audio codec record channel, reference _codec_record_channel, can be a value combine of + member in _codec_record_channel. + + * return kStatus_Success is success, else configure failed. + */ +status_t CODEC_SetRecordChannel(codec_handle_t *handle, uint32_t leftRecordChannel, uint32_t rightRecordChannel) +{ + assert((handle != NULL) && (handle->codecConfig != NULL)); + + /* check capability of record capability */ + if ((GET_RECORD_CHANNEL_CAPABILITY(handle->codecCapability.codecRecordCapability) & leftRecordChannel) == 0U) + { + return kStatus_CODEC_NotSupport; + } + + if ((GET_RECORD_CHANNEL_CAPABILITY(handle->codecCapability.codecRecordCapability) & rightRecordChannel) == 0U) + { + return kStatus_CODEC_NotSupport; + } + + return HAL_CODEC_SetRecordChannel(handle, leftRecordChannel, rightRecordChannel); +} + +/*! + * brief codec set play source. + * + * param handle codec handle. + * param playSource audio codec play source, can be a value or combine value of _codec_play_source. + * + * return kStatus_Success is success, else configure failed. + */ +status_t CODEC_SetPlay(codec_handle_t *handle, uint32_t playSource) +{ + assert((handle != NULL) && (handle->codecConfig != NULL)); + + /* check capability of record capability */ + if ((GET_PLAY_SOURCE_CAPABILITY(handle->codecCapability.codecPlayCapability) & playSource) == 0U) + { + return kStatus_CODEC_NotSupport; + } + + return HAL_CODEC_SetPlay(handle, playSource); +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/components/codec/fsl_codec_common.h b/bsp/lpc55sxx/Libraries/LPC55S6X/components/codec/fsl_codec_common.h new file mode 100644 index 000000000..c285589e8 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/components/codec/fsl_codec_common.h @@ -0,0 +1,363 @@ +/* + * Copyright 2017- 2019 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_CODEC_COMMON_H_ +#define _FSL_CODEC_COMMON_H_ + +#include "fsl_common.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @name Driver version */ +/*@{*/ +/*! @brief CLOCK driver version 2.1.0. */ +#define FSL_CODEC_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) +/*@}*/ + +/*! @brief CODEC handle buffer size */ +#ifndef CODEC_HANDLE_SIZE +#define CODEC_HANDLE_SIZE (128U) +#endif + +/*! @brief codec maximum volume range */ +#define CODEC_VOLUME_MAX_VALUE (100U) + +/*! @brief CODEC status */ +enum _codec_status +{ + kStatus_CODEC_NotSupport = MAKE_STATUS(kStatusGroup_CODEC, 0U), /*!< CODEC not support status */ + kStatus_CODEC_DeviceNotRegistered = MAKE_STATUS(kStatusGroup_CODEC, 1U), /*!< CODEC device register failed status */ + kStatus_CODEC_I2CBusInitialFailed = + MAKE_STATUS(kStatusGroup_CODEC, 2U), /*!< CODEC i2c bus initialization failed status */ + kStatus_CODEC_I2CCommandTransferFailed = + MAKE_STATUS(kStatusGroup_CODEC, 3U), /*!< CODEC i2c bus command transfer failed status */ +}; + +/*! @brief AUDIO format definition. */ +typedef enum _codec_audio_protocol +{ + kCODEC_BusI2S = 0U, /*!< I2S type */ + kCODEC_BusLeftJustified = 1U, /*!< Left justified mode */ + kCODEC_BusRightJustified = 2U, /*!< Right justified mode */ + kCODEC_BusPCMA = 3U, /*!< DSP/PCM A mode */ + kCODEC_BusPCMB = 4U, /*!< DSP/PCM B mode */ + kCODEC_BusTDM = 5U, /*!< TDM mode */ +} codec_audio_protocol_t; + +/*! @brief audio sample rate definition */ +enum _codec_audio_sample_rate +{ + kCODEC_AudioSampleRate8KHz = 8000U, /*!< Sample rate 8000 Hz */ + kCODEC_AudioSampleRate11025Hz = 11025U, /*!< Sample rate 11025 Hz */ + kCODEC_AudioSampleRate12KHz = 12000U, /*!< Sample rate 12000 Hz */ + kCODEC_AudioSampleRate16KHz = 16000U, /*!< Sample rate 16000 Hz */ + kCODEC_AudioSampleRate22050Hz = 22050U, /*!< Sample rate 22050 Hz */ + kCODEC_AudioSampleRate24KHz = 24000U, /*!< Sample rate 24000 Hz */ + kCODEC_AudioSampleRate32KHz = 32000U, /*!< Sample rate 32000 Hz */ + kCODEC_AudioSampleRate44100Hz = 44100U, /*!< Sample rate 44100 Hz */ + kCODEC_AudioSampleRate48KHz = 48000U, /*!< Sample rate 48000 Hz */ + kCODEC_AudioSampleRate96KHz = 96000U, /*!< Sample rate 96000 Hz */ + kCODEC_AudioSampleRate192KHz = 192000U, /*!< Sample rate 192000 Hz */ + kCODEC_AudioSampleRate384KHz = 384000U, /*!< Sample rate 384000 Hz */ +}; + +/*! @brief audio bit width */ +enum _codec_audio_bit_width +{ + kCODEC_AudioBitWidth16bit = 16U, /*!< audio bit width 16 */ + kCODEC_AudioBitWidth20bit = 20U, /*!< audio bit width 20 */ + kCODEC_AudioBitWidth24bit = 24U, /*!< audio bit width 24 */ + kCODEC_AudioBitWidth32bit = 32U, /*!< audio bit width 32 */ +}; + +/*! @brief audio codec module*/ +typedef enum _codec_module +{ + kCODEC_ModuleADC = 0U, /*!< codec module ADC */ + kCODEC_ModuleDAC = 1U, /*!< codec module DAC */ + kCODEC_ModulePGA = 2U, /*!< codec module PGA */ + kCODEC_ModuleHeadphone = 3U, /*!< codec module headphone */ + kCODEC_ModuleSpeaker = 4U, /*!< codec module speaker */ + kCODEC_ModuleLinein = 5U, /*!< codec module linein */ + kCODEC_ModuleLineout = 6U, /*!< codec module lineout */ + kCODEC_ModuleVref = 7U, /*!< codec module VREF */ + kCODEC_ModuleMicbias = 8U, /*!< codec module MIC BIAS */ + kCODEC_ModuleMic = 9U, /*!< codec module MIC */ + kCODEC_ModuleI2SIn = 10U, /*!< codec module I2S in */ + kCODEC_ModuleI2SOut = 11U, /*!< codec module I2S out */ + kCODEC_ModuleMxier = 12U, /*!< codec module mixer */ +} codec_module_t; + +/*! @brief audio codec module control cmd */ +typedef enum _codec_module_ctrl_cmd +{ + kCODEC_ModuleSwitchI2SInInterface = 0U, /*!< module digital interface siwtch. */ +} codec_module_ctrl_cmd_t; + +/*! @brief audio codec module digital interface */ +enum _codec_module_ctrl_i2s_in_interface +{ + kCODEC_ModuleI2SInInterfacePCM = 0U, /*!< Pcm interface*/ + kCODEC_ModuleI2SInInterfaceDSD = 1U, /*!< DSD interface */ +}; + +/*! @brief audio codec module record source value */ +enum _codec_record_source +{ + kCODEC_RecordSourceDifferentialLine = 1U, /*!< record source from differential line */ + kCODEC_RecordSourceLineInput = 2U, /*!< record source from line input */ + kCODEC_RecordSourceDifferentialMic = 4U, /*!< record source from differential mic */ + kCODEC_RecordSourceDigitalMic = 8U, /*!< record source from digital microphone */ + kCODEC_RecordSourceSingleEndMic = 16U, /*!< record source from single microphone */ +}; + +/*! @brief audio codec record channel */ +enum _codec_reocrd_channel +{ + kCODEC_RecordChannelLeft1 = 1U, /*!< left record channel 1 */ + kCODEC_RecordChannelLeft2 = 2U, /*!< left record channel 2 */ + kCODEC_RecordChannelLeft3 = 4U, /*!< left record channel 3 */ + kCODEC_RecordChannelRight1 = 1U, /*!< right record channel 1 */ + kCODEC_RecordChannelRight2 = 2U, /*!< right record channel 2 */ + kCODEC_RecordChannelRight3 = 4U, /*!< right record channel 3 */ + kCODEC_RecordChannelDifferentialPositive1 = 1U, /*!< differential positive record channel 1 */ + kCODEC_RecordChannelDifferentialPositive2 = 2U, /*!< differential positive record channel 2 */ + kCODEC_RecordChannelDifferentialPositive3 = 4U, /*!< differential positive record channel 3 */ + kCODEC_RecordChannelDifferentialNegative1 = 8U, /*!< differential negative record channel 1 */ + kCODEC_RecordChannelDifferentialNegative2 = 16U, /*!< differential negative record channel 2 */ + kCODEC_RecordChannelDifferentialNegative3 = 32U, /*!< differential negative record channel 3 */ +}; + +/*! @brief audio codec module play source value */ +enum _codec_play_source +{ + kCODEC_PlaySourcePGA = 1U, /*!< play source PGA, bypass ADC */ + kCODEC_PlaySourceInput = 2U, /*!< play source Input3 */ + kCODEC_PlaySourceDAC = 4U, /*!< play source DAC */ + kCODEC_PlaySourceMixerIn = 1U, /*!< play source mixer in */ + kCODEC_PlaySourceMixerInLeft = 2U, /*!< play source mixer in left */ + kCODEC_PlaySourceMixerInRight = 4U, /*!< play source mixer in right */ + kCODEC_PlaySourceAux = 8U, /*!< play source mixer in AUx */ +}; + +/*! @brief codec play channel */ +enum _codec_play_channel +{ + kCODEC_PlayChannelHeadphoneLeft = 1U, /*!< play channel headphone left */ + kCODEC_PlayChannelHeadphoneRight = 2U, /*!< play channel headphone right */ + kCODEC_PlayChannelSpeakerLeft = 4U, /*!< play channel speaker left */ + kCODEC_PlayChannelSpeakerRight = 8U, /*!< play channel speaker right */ + kCODEC_PlayChannelLineOutLeft = 16U, /*!< play channel lineout left */ + kCODEC_PlayChannelLineOutRight = 32U, /*!< play channel lineout right */ + + kCODEC_PlayChannelLeft0 = 1U, /*!< play channel left0 */ + kCODEC_PlayChannelRight0 = 2U, /*!< play channel right0 */ + kCODEC_PlayChannelLeft1 = 4U, /*!< play channel left1 */ + kCODEC_PlayChannelRight1 = 8U, /*!< play channel right1 */ + kCODEC_PlayChannelLeft2 = 16U, /*!< play channel left2 */ + kCODEC_PlayChannelRight2 = 32U, /*!< play channel right2 */ + kCODEC_PlayChannelLeft3 = 64U, /*!< play channel left3 */ + kCODEC_PlayChannelRight3 = 128U, /*!< play channel right3 */ +}; + +/*! @brief audio codec capability */ +enum _codec_capability_flag +{ + kCODEC_SupportModuleADC = 1U << 0U, /*!< codec capability of module ADC */ + kCODEC_SupportModuleDAC = 1U << 1U, /*!< codec capability of module DAC */ + kCODEC_SupportModulePGA = 1U << 2U, /*!< codec capability of module PGA */ + kCODEC_SupportModuleHeadphone = 1U << 3U, /*!< codec capability of module headphone */ + kCODEC_SupportModuleSpeaker = 1U << 4U, /*!< codec capability of module speaker */ + kCODEC_SupportModuleLinein = 1U << 5U, /*!< codec capability of module linein */ + kCODEC_SupportModuleLineout = 1U << 6U, /*!< codec capability of module lineout */ + kCODEC_SupportModuleVref = 1U << 7U, /*!< codec capability of module vref */ + kCODEC_SupportModuleMicbias = 1U << 8U, /*!< codec capability of module mic bias */ + kCODEC_SupportModuleMic = 1U << 9U, /*!< codec capability of module mic bias */ + kCODEC_SupportModuleI2SIn = 1U << 10U, /*!< codec capability of module I2S in */ + kCODEC_SupportModuleI2SOut = 1U << 11U, /*!< codec capability of module I2S out */ + kCODEC_SupportModuleMixer = 1U << 12U, /*!< codec capability of module mixer */ + kCODEC_SupportModuleI2SInSwitchInterface = 1U << 13U, /*!< codec capability of module I2S in switch interface */ + + kCODEC_SupportPlayChannelLeft0 = 1U << 0U, /*!< codec capability of play channel left 0 */ + kCODEC_SupportPlayChannelRight0 = 1U << 1U, /*!< codec capability of play channel right 0 */ + kCODEC_SupportPlayChannelLeft1 = 1U << 2U, /*!< codec capability of play channel left 1 */ + kCODEC_SupportPlayChannelRight1 = 1U << 3U, /*!< codec capability of play channel right 1 */ + kCODEC_SupportPlayChannelLeft2 = 1U << 4U, /*!< codec capability of play channel left 2 */ + kCODEC_SupportPlayChannelRight2 = 1U << 5U, /*!< codec capability of play channel right 2 */ + kCODEC_SupportPlayChannelLeft3 = 1U << 6U, /*!< codec capability of play channel left 3 */ + kCODEC_SupportPlayChannelRight3 = 1U << 7U, /*!< codec capability of play channel right 3 */ + + kCODEC_SupportPlaySourcePGA = 1U << 8U, /*!< codec capability of set playback source PGA */ + kCODEC_SupportPlaySourceInput = 1U << 9U, /*!< codec capability of set playback source INPUT */ + kCODEC_SupportPlaySourceDAC = 1U << 10U, /*!< codec capability of set playback source DAC */ + kCODEC_SupportPlaySourceMixerIn = 1U << 11U, /*!< codec capability of set play source Mixer in */ + kCODEC_SupportPlaySourceMixerInLeft = 1U << 12U, /*!< codec capability of set play source Mixer in left */ + kCODEC_SupportPlaySourceMixerInRight = 1U << 13U, /*!< codec capability of set play source Mixer in right */ + kCODEC_SupportPlaySourceAux = 1U << 14U, /*!< codec capability of set play source aux */ + + kCODEC_SupportRecordSourceDifferentialLine = 1U << 0U, /*!< codec capability of record source differential line */ + kCODEC_SupportRecordSourceLineInput = 1U << 1U, /*!< codec capability of record source line input */ + kCODEC_SupportRecordSourceDifferentialMic = 1U << 2U, /*!< codec capability of record source differential mic */ + kCODEC_SupportRecordSourceDigitalMic = 1U << 3U, /*!< codec capability of record digital mic */ + kCODEC_SupportRecordSourceSingleEndMic = 1U << 4U, /*!< codec capability of single end mic */ + kCODEC_SupportRecordChannelLeft1 = 1U << 6U, /*!< left record channel 1 */ + kCODEC_SupportRecordChannelLeft2 = 1U << 7U, /*!< left record channel 2 */ + kCODEC_SupportRecordChannelLeft3 = 1U << 8U, /*!< left record channel 3 */ + kCODEC_SupportRecordChannelRight1 = 1U << 9U, /*!< right record channel 1 */ + kCODEC_SupportRecordChannelRight2 = 1U << 10U, /*!< right record channel 2 */ + kCODEC_SupportRecordChannelRight3 = 1U << 11U, /*!< right record channel 3 */ +}; + +/*!@brief codec handle declaration */ +typedef struct codec_handle codec_handle_t; + +/*! @brief Initialize structure of the codec */ +typedef struct _codec_config +{ + uint32_t codecDevType; /*!< codec type */ + void *codecDevConfig; /*!< Codec device specific configuration */ +} codec_config_t; + +/*! @brief codec capability */ +typedef struct _codec_capability +{ + uint32_t codecModuleCapability; /*!< codec module capability */ + uint32_t codecPlayCapability; /*!< codec play capability */ + uint32_t codecRecordCapability; /*!< codec record capability */ +} codec_capability_t; + +/*! @brief Codec handle definition. + * * Application should allocate a buffer with CODEC_HANDLE_SIZE for handle definition, such as + * uint8_t codecHandleBuffer[CODEC_HANDLE_SIZE]; + * codec_handle_t *codecHandle = codecHandleBuffer; + */ +struct codec_handle +{ + codec_config_t *codecConfig; /*!< codec configuration function pointer */ + codec_capability_t codecCapability; /*!< codec capability */ + void *codecDevHandle; /*!< codec device handle */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif +/*! + * @brief Codec initilization. + * + * @param handle codec handle. + * @param config codec configurations. + * @return kStatus_Success is success, else de-initial failed. + */ +status_t CODEC_Init(codec_handle_t *handle, codec_config_t *config); + +/*! + * @brief Codec de-initilization. + * + * @param handle codec handle. + * @return kStatus_Success is success, else de-initial failed. + */ +status_t CODEC_Deinit(codec_handle_t *handle); + +/*! + * @brief set audio data format. + * + * @param handle codec handle. + * @param mclk master clock frequency in HZ. + * @param sampleRate sample rate in HZ. + * @param bitWidth bit width. + * @return kStatus_Success is success, else configure failed. + */ +status_t CODEC_SetFormat(codec_handle_t *handle, uint32_t mclk, uint32_t sampleRate, uint32_t bitWidth); + +/*! + * @brief codec module control. + * + * This function is used for codec module control, support switch digital interface cmd, can be expand to support codec + * module specific feature. + * + * @param handle codec handle. + * @param cmd module control cmd, reference _codec_module_ctrl_cmd. + * @param data value to write, when cmd is kCODEC_ModuleRecordSourceChannel, the data should be a value combine + * of channel and source, please reference macro CODEC_MODULE_RECORD_SOURCE_CHANNEL(source, LP, LN, RP, RN), reference + * codec specific driver for detail configurations. + * @return kStatus_Success is success, else configure failed. + */ +status_t CODEC_ModuleControl(codec_handle_t *handle, codec_module_ctrl_cmd_t cmd, uint32_t data); + +/*! + * @brief set audio codec pl volume. + * + * @param handle codec handle. + * @param channel audio codec play channel, can be a value or combine value of _codec_play_channel. + * @param volume volume value, support 0 ~ 100, 0 is mute, 100 is the maximum volume value. + * @return kStatus_Success is success, else configure failed. + */ +status_t CODEC_SetVolume(codec_handle_t *handle, uint32_t channel, uint32_t volume); + +/*! + * @brief set audio codec module mute. + * + * @param handle codec handle. + * @param channel audio codec play channel, can be a value or combine value of _codec_play_channel. + * @param mute true is mute, false is unmute. + * @return kStatus_Success is success, else configure failed. + */ +status_t CODEC_SetMute(codec_handle_t *handle, uint32_t channel, bool mute); + +/*! + * @brief set audio codec power. + * + * @param handle codec handle. + * @param module audio codec module. + * @param powerOn true is power on, false is power down. + * @return kStatus_Success is success, else configure failed. + */ +status_t CODEC_SetPower(codec_handle_t *handle, codec_module_t module, bool powerOn); + +/*! + * @brief codec set record source. + * + * @param handle codec handle. + * @param source audio codec record source, can be a value or combine value of _codec_record_source. + * + * @return kStatus_Success is success, else configure failed. + */ +status_t CODEC_SetRecord(codec_handle_t *handle, uint32_t recordRource); + +/*! + * @brief codec set record channel. + * + * @param handle codec handle. + * @param leftRecordChannel audio codec record channel, reference _codec_record_channel, can be a value combine of + member in _codec_record_channel. + * @param rightRecordChannel audio codec record channel, reference _codec_record_channel, can be a value combine of + member in _codec_record_channel. + + * @return kStatus_Success is success, else configure failed. + */ +status_t CODEC_SetRecordChannel(codec_handle_t *handle, uint32_t leftRecordChannel, uint32_t rightRecordChannel); + +/*! + * @brief codec set play source. + * + * @param handle codec handle. + * @param playSource audio codec play source, can be a value or combine value of _codec_play_source. + * + * @return kStatus_Success is success, else configure failed. + */ +status_t CODEC_SetPlay(codec_handle_t *handle, uint32_t playSource); + +#if defined(__cplusplus) +} +#endif + +#endif /* _FSL_CODEC_COMMON_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/components/codec/i2c/fsl_codec_i2c.c b/bsp/lpc55sxx/Libraries/LPC55S6X/components/codec/i2c/fsl_codec_i2c.c new file mode 100644 index 000000000..dc89cd4cc --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/components/codec/i2c/fsl_codec_i2c.c @@ -0,0 +1,113 @@ +/* + * Copyright 2019 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_codec_i2c.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +/*! + * brief Codec i2c bus initilization. + * + * param handle i2c master handle. + * param i2CInstance instance number of the i2c bus, such as 0 is corresponding to I2C0. + * param i2cBaudrate i2c baudrate. + * param i2cSourceClockHz i2c source clock frequency. + * return kStatus_HAL_I2cSuccess is success, else initial failed. + */ +status_t CODEC_I2C_Init(void *handle, uint32_t i2cInstance, uint32_t i2cBaudrate, uint32_t i2cSourceClockHz) +{ + hal_i2c_master_config_t masterConfig; + + masterConfig.enableMaster = true; + masterConfig.baudRate_Bps = i2cBaudrate; + masterConfig.srcClock_Hz = i2cSourceClockHz; + masterConfig.instance = i2cInstance; + + return HAL_I2cMasterInit((hal_i2c_master_handle_t *)handle, &masterConfig); +} + +/*! + * brief Codec i2c de-initilization. + * + * param handle i2c master handle. + * return kStatus_HAL_I2cSuccess is success, else deinitial failed. + */ +status_t CODEC_I2C_Deinit(void *handle) +{ + return HAL_I2cMasterDeinit((hal_i2c_master_handle_t *)handle); +} + +/*! + * brief codec i2c send function. + * + * param handle i2c master handle. + * param deviceAddress codec device address. + * param subAddress register address. + * param subaddressSize register address width. + * param txBuff tx buffer pointer. + * param txBuffSize tx buffer size. + * return kStatus_HAL_I2cSuccess is success, else send failed. + */ +status_t CODEC_I2C_Send(void *handle, + uint8_t deviceAddress, + uint32_t subAddress, + uint8_t subaddressSize, + uint8_t *txBuff, + uint8_t txBuffSize) +{ + hal_i2c_master_transfer_t masterXfer; + + masterXfer.slaveAddress = deviceAddress; + masterXfer.direction = kHAL_I2cWrite; + masterXfer.subaddress = (uint32_t)subAddress; + masterXfer.subaddressSize = subaddressSize; + masterXfer.data = txBuff; + masterXfer.dataSize = txBuffSize; + masterXfer.flags = kHAL_I2cTransferDefaultFlag; + + return HAL_I2cMasterTransferBlocking((hal_i2c_master_handle_t *)handle, &masterXfer); +} + +/*! + * brief codec i2c receive function. + * + * param handle i2c master handle. + * param deviceAddress codec device address. + * param subAddress register address. + * param subaddressSize register address width. + * param rxBuff rx buffer pointer. + * param rxBuffSize rx buffer size. + * return kStatus_HAL_I2cSuccess is success, else receive failed. + */ +status_t CODEC_I2C_Receive(void *handle, + uint8_t deviceAddress, + uint32_t subAddress, + uint8_t subaddressSize, + uint8_t *rxBuff, + uint8_t rxBuffSize) +{ + hal_i2c_master_transfer_t masterXfer; + + masterXfer.slaveAddress = deviceAddress; + masterXfer.direction = kHAL_I2cRead; + masterXfer.subaddress = (uint32_t)subAddress; + masterXfer.subaddressSize = subaddressSize; + masterXfer.data = rxBuff; + masterXfer.dataSize = rxBuffSize; + masterXfer.flags = kHAL_I2cTransferDefaultFlag; + + return HAL_I2cMasterTransferBlocking((hal_i2c_master_handle_t *)handle, &masterXfer); +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/components/codec/i2c/fsl_codec_i2c.h b/bsp/lpc55sxx/Libraries/LPC55S6X/components/codec/i2c/fsl_codec_i2c.h new file mode 100644 index 000000000..7647a1cc8 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/components/codec/i2c/fsl_codec_i2c.h @@ -0,0 +1,107 @@ +/* + * Copyright 2019 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_CODEC_I2C_H_ +#define _FSL_CODEC_I2C_H_ + +#include "fsl_common.h" +#include "i2c.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief CODEC device register address type. */ +typedef enum _codec_reg_addr +{ + kCODEC_RegAddr8Bit = 1U, /*!< 8-bit register address. */ + kCODEC_RegAddr16Bit = 2U, /*!< 16-bit register address. */ +} codec_reg_addr_t; + +/*! @brief CODEC device register width. */ +typedef enum _codec_reg_width +{ + kCODEC_RegWidth8Bit = 1U, /*!< 8-bit register width. */ + kCODEC_RegWidth16Bit = 2U, /*!< 16-bit register width. */ + kCODEC_RegWidth32Bit = 4U, /*!< 32-bit register width. */ +} codec_reg_width_t; + +/*! @brief CODEC I2C configurations structure */ +typedef struct _codec_i2c_config +{ + uint32_t codecI2CInstance; /*!< i2c bus instance */ + uint32_t codecI2CSourceClock; /*!< i2c bus source clock frequency */ +} codec_i2c_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Codec i2c bus initilization. + * + * @param handle i2c master handle. + * @param i2CInstance instance number of the i2c bus, such as 0 is corresponding to I2C0. + * @param i2cBaudrate i2c baudrate. + * @param i2cSourceClockHz i2c source clock frequency. + * @return kStatus_HAL_I2cSuccess is success, else initial failed. + */ +status_t CODEC_I2C_Init(void *handle, uint32_t i2cInstance, uint32_t i2cBaudrate, uint32_t i2cSourceClockHz); + +/*! + * @brief Codec i2c de-initilization. + * + * @param handle i2c master handle. + * @return kStatus_HAL_I2cSuccess is success, else deinitial failed. + */ +status_t CODEC_I2C_Deinit(void *handle); + +/*! + * @brief codec i2c send function. + * + * @param handle i2c master handle. + * @param deviceAddress codec device address. + * @param subAddress register address. + * @param subaddressSize register address width. + * @param txBuff tx buffer pointer. + * @param txBuffSize tx buffer size. + * @return kStatus_HAL_I2cSuccess is success, else send failed. + */ +status_t CODEC_I2C_Send(void *handle, + uint8_t deviceAddress, + uint32_t subAddress, + uint8_t subaddressSize, + uint8_t *txBuff, + uint8_t txBuffSize); + +/*! + * @brief codec i2c receive function. + * + * @param handle i2c master handle. + * @param deviceAddress codec device address. + * @param subAddress register address. + * @param subaddressSize register address width. + * @param rxBuff rx buffer pointer. + * @param rxBuffSize rx buffer size. + * @return kStatus_HAL_I2cSuccess is success, else receive failed. + */ +status_t CODEC_I2C_Receive(void *handle, + uint8_t deviceAddress, + uint32_t subAddress, + uint8_t subaddressSize, + uint8_t *rxBuff, + uint8_t rxBuffSize); + +#if defined(__cplusplus) +} +#endif + +#endif /* _FSL_CODEC_I2C_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/components/codec/port/fsl_codec_adapter.h b/bsp/lpc55sxx/Libraries/LPC55S6X/components/codec/port/fsl_codec_adapter.h new file mode 100644 index 000000000..600675447 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/components/codec/port/fsl_codec_adapter.h @@ -0,0 +1,145 @@ +/* + * Copyright 2017- 2019 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_CODEC_ADAPTER_H_ +#define _FSL_CODEC_ADAPTER_H_ + +#include "fsl_codec_common.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief codec type */ +enum _codec_type +{ + kCODEC_WM8904, /*!< wm8904 */ + kCODEC_WM8960, /*!< wm8960 */ + kCODEC_WM8524, /*!< wm8524 */ + kCODEC_SGTL5000, /*!< sgtl5000 */ + kCODEC_DA7212, /*!< da7212 */ + kCODEC_CS42888, /*!< CS42888 */ + kCODEC_AK4497, /*!< AK4497 */ + kCODEC_AK4458, /*!< ak4458 */ +}; +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif +/*! + * @brief Codec initilization. + * + * @param handle codec handle. + * @param config codec configuration. + * @return kStatus_Success is success, else initial failed. + */ +status_t HAL_CODEC_Init(codec_handle_t *handle, void *config); + +/*! + * @brief Codec de-initilization. + * + * @param handle codec handle. + * @return kStatus_Success is success, else de-initial failed. + */ +status_t HAL_CODEC_Deinit(codec_handle_t *handle); + +/*! + * @brief set audio data format. + * + * @param handle codec handle. + * @param mclk master clock frequency in HZ. + * @param sampleRate sample rate in HZ. + * @param bitWidth bit width. + * @return kStatus_Success is success, else configure failed. + */ +status_t HAL_CODEC_SetFormat(codec_handle_t *handle, uint32_t mclk, uint32_t sampleRate, uint32_t bitWidth); + +/*! + * @brief set audio codec module volume. + * + * @param handle codec handle. + * @param channel audio codec play channel, can be a value or combine value of _codec_play_channel. + * @param volume volume value, support 0 ~ 100, 0 is mute, 100 is the maximum volume value. + * @return kStatus_Success is success, else configure failed. + */ +status_t HAL_CODEC_SetVolume(codec_handle_t *handle, uint32_t playChannel, uint32_t volume); + +/*! + * @brief set audio codec module mute. + * + * @param handle codec handle. + * @param channel audio codec play channel, can be a value or combine value of _codec_play_channel. + * @param isMute true is mute, false is unmute. + * @return kStatus_Success is success, else configure failed. + */ +status_t HAL_CODEC_SetMute(codec_handle_t *handle, uint32_t playChannel, bool isMute); + +/*! + * @brief set audio codec module power. + * + * @param handle codec handle. + * @param module audio codec module. + * @param powerOn true is power on, false is power down. + * @return kStatus_Success is success, else configure failed. + */ +status_t HAL_CODEC_SetPower(codec_handle_t *handle, codec_module_t module, bool powerOn); + +/*! + * @brief codec set record source. + * + * @param handle codec handle. + * @param source audio codec record source, can be a value or combine value of _codec_record_source. + * + * @return kStatus_Success is success, else configure failed. + */ +status_t HAL_CODEC_SetRecord(codec_handle_t *handle, uint32_t recordSource); + +/*! + * @brief codec set record channel. + * + * @param handle codec handle. + * @param leftRecordChannel audio codec record channel, reference _codec_record_channel, can be a value or combine value + of member in _codec_record_channel. + * @param rightRecordChannel audio codec record channel, reference _codec_record_channel, can be a value combine of + member in _codec_record_channel. + + * @return kStatus_Success is success, else configure failed. + */ +status_t HAL_CODEC_SetRecordChannel(codec_handle_t *handle, uint32_t leftRecordChannel, uint32_t rightRecordChannel); + +/*! + * @brief codec set play source. + * + * @param handle codec handle. + * @param playSource audio codec play source, can be a value or combine value of _codec_play_source. + * + * @return kStatus_Success is success, else configure failed. + */ +status_t HAL_CODEC_SetPlay(codec_handle_t *handle, uint32_t playSource); + +/*! + * @brief codec module control. + * + * This function is used for codec module control, support switch digital interface cmd, can be expand to support codec + * module specific feature + * + * @param handle codec handle. + * @param cmd module control cmd, reference _codec_module_ctrl_cmd. + * @param data value to write, when cmd is kCODEC_ModuleRecordSourceChannel, the data should be a value combine + * of channel and source, please reference macro CODEC_MODULE_RECORD_SOURCE_CHANNEL(source, LP, LN, RP, RN), reference + * codec specific driver for detail configurations. + * @return kStatus_Success is success, else configure failed. + */ +status_t HAL_CODEC_ModuleControl(codec_handle_t *handle, codec_module_ctrl_cmd_t cmd, uint32_t data); + +#if defined(__cplusplus) +} +#endif + +#endif /* _FSL_CODEC_ADAPTER_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/components/codec/port/wm8904/fsl_codec_adapter.c b/bsp/lpc55sxx/Libraries/LPC55S6X/components/codec/port/wm8904/fsl_codec_adapter.c new file mode 100644 index 000000000..874d3e754 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/components/codec/port/wm8904/fsl_codec_adapter.c @@ -0,0 +1,245 @@ +/* + * Copyright 2019 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_wm8904.h" +#include "fsl_codec_adapter.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief module capability definition */ +#define HAL_WM8904_MODULE_CAPABILITY \ + kCODEC_SupportModuleADC | kCODEC_SupportModuleDAC | kCODEC_SupportModulePGA | kCODEC_SupportModuleHeadphone | \ + kCODEC_SupportModuleLineout +#define HAL_WM8904_PLAY_CAPABILITY \ + kCODEC_SupportPlayChannelLeft0 | kCODEC_SupportPlayChannelRight0 | kCODEC_SupportPlayChannelLeft1 | \ + kCODEC_SupportPlayChannelRight1 | kCODEC_SupportPlaySourcePGA | kCODEC_SupportPlaySourceDAC +#define HAL_WM8904_RECORD_CAPABILITY \ + kCODEC_SupportRecordSourceDifferentialLine | kCODEC_SupportRecordSourceDifferentialMic | \ + kCODEC_SupportRecordSourceLineInput | kCODEC_SupportRecordSourceDigitalMic | \ + kCODEC_SupportRecordChannelLeft1 | kCODEC_SupportRecordChannelLeft2 | kCODEC_SupportRecordChannelLeft3 | \ + kCODEC_SupportRecordChannelRight1 | kCODEC_SupportRecordChannelRight2 | kCODEC_SupportRecordChannelRight3 + +/*! @brief wm8904 map protocol */ +#define HAL_WM8904_MAP_PROTOCOL(protocol) \ + (protocol == kCODEC_BusI2S ? \ + kWM8904_ProtocolI2S : \ + protocol == kCODEC_BusLeftJustified ? \ + kWM8904_ProtocolLeftJustified : \ + protocol == kCODEC_BusRightJustified ? \ + kWM8904_ProtocolRightJustified : \ + protocol == kCODEC_BusPCMA ? kWM8904_ProtocolPCMA : \ + protocol == kCODEC_BusPCMB ? kWM8904_ProtocolPCMB : kWM8904_ProtocolI2S) + +/*! @brief wm8904 map module */ +#define HAL_WM8904_MAP_MODULE(module) \ + (module == kCODEC_ModuleADC ? \ + kWM8904_ModuleADC : \ + module == kCODEC_ModuleDAC ? \ + kWM8904_ModuleDAC : \ + module == kCODEC_ModulePGA ? kWM8904_ModulePGA : \ + module == kCODEC_ModuleHeadphone ? \ + kWM8904_ModuleHeadphone : \ + module == kCODEC_ModuleLineout ? kWM8904_ModuleLineout : kWM8904_ModuleADC) + +/*! @brief wm8904 map protocol */ +#define HAL_WM8904_MAP_SAMPLERATE(sampleRATE) \ + (sampleRATE == kCODEC_AudioSampleRate8KHz ? \ + kWM8904_SampleRate8kHz : \ + sampleRATE == kCODEC_AudioSampleRate12KHz ? \ + kWM8904_SampleRate12kHz : \ + sampleRATE == kCODEC_AudioSampleRate16KHz ? \ + kWM8904_SampleRate16kHz : \ + sampleRATE == kCODEC_AudioSampleRate24KHz ? \ + kWM8904_SampleRate24kHz : \ + sampleRATE == kCODEC_AudioSampleRate32KHz ? kWM8904_SampleRate32kHz : kWM8904_SampleRate48kHz) + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +/*! + * brief Codec initilization. + * + * param handle codec handle. + * param config codec configuration. + * return kStatus_Success is success, else initial failed. + */ +status_t HAL_CODEC_Init(codec_handle_t *handle, void *config) +{ + assert((config != NULL) && (handle != NULL)); + assert(CODEC_HANDLE_SIZE >= (sizeof(codec_handle_t) + sizeof(wm8904_handle_t)) + HAL_I2C_MASTER_HANDLE_SIZE); + + codec_config_t *codecConfig = (codec_config_t *)config; + + wm8904_config_t *wm8904Config = (wm8904_config_t *)(codecConfig->codecDevConfig); + wm8904_handle_t *wm8904Handle = (wm8904_handle_t *)((uint32_t) & (handle->codecDevHandle)); + + /* load codec capability */ + handle->codecCapability.codecModuleCapability = HAL_WM8904_MODULE_CAPABILITY; + /* add nop to aovid alignment fault, since that the compiler may generate 'strd' instruction to store 64 bit + with one instruction, but the address may not word-aligned + Will remove the __NOP in next release and use a word align address. + */ + __NOP(); + handle->codecCapability.codecPlayCapability = HAL_WM8904_PLAY_CAPABILITY; + /* add nop to aovid alignment fault, since that the compiler may generate 'strd' instruction to store 64 bit + with one instruction, but the address may not word-aligned + Will remove the __NOP in next release and use a word align address. + */ + __NOP(); + handle->codecCapability.codecRecordCapability = HAL_WM8904_RECORD_CAPABILITY; + /* codec device initialization */ + return WM8904_Init(wm8904Handle, wm8904Config); +} + +/*! + * brief Codec de-initilization. + * + * param handle codec handle. + * return kStatus_Success is success, else de-initial failed. + */ +status_t HAL_CODEC_Deinit(codec_handle_t *handle) +{ + assert(handle != NULL); + + return WM8904_Deinit((wm8904_handle_t *)((uint32_t) & (handle->codecDevHandle))); +} + +/*! + * brief set audio data format. + * + * param handle codec handle. + * param mclk master clock frequency in HZ. + * param sampleRate sample rate in HZ. + * param bitWidth bit width. + * return kStatus_Success is success, else configure failed. + */ +status_t HAL_CODEC_SetFormat(codec_handle_t *handle, uint32_t mclk, uint32_t sampleRate, uint32_t bitWidth) +{ + assert(handle != NULL); + + return WM8904_SetAudioFormat((wm8904_handle_t *)((uint32_t) & (handle->codecDevHandle)), mclk, + HAL_WM8904_MAP_SAMPLERATE(sampleRate), bitWidth); +} + +/*! + * brief set audio codec module volume. + * + * param handle codec handle. + * param channel audio codec play channel, can be a value or combine value of _codec_play_channel. + * param volume volume value, support 0 ~ 100, 0 is mute, 100 is the maximum volume value. + * return kStatus_Success is success, else configure failed. + */ +status_t HAL_CODEC_SetVolume(codec_handle_t *handle, uint32_t playChannel, uint32_t volume) +{ + assert(handle != NULL); + + return WM8904_SetChannelVolume((wm8904_handle_t *)((uint32_t) & (handle->codecDevHandle)), playChannel, volume); +} + +/*! + * brief set audio codec module mute. + * + * param handle codec handle. + * param channel audio codec play channel, can be a value or combine value of _codec_play_channel. + * param isMute true is mute, false is unmute. + * return kStatus_Success is success, else configure failed. + */ +status_t HAL_CODEC_SetMute(codec_handle_t *handle, uint32_t playChannel, bool isMute) +{ + assert(handle != NULL); + + return WM8904_SetChannelMute((wm8904_handle_t *)((uint32_t) & (handle->codecDevHandle)), playChannel, isMute); +} + +/*! + * brief set audio codec module power. + * + * param handle codec handle. + * param module audio codec module. + * param powerOn true is power on, false is power down. + * return kStatus_Success is success, else configure failed. + */ +status_t HAL_CODEC_SetPower(codec_handle_t *handle, codec_module_t module, bool powerOn) +{ + assert(handle != NULL); + + return WM8904_SetModulePower((wm8904_handle_t *)((uint32_t) & (handle->codecDevHandle)), + HAL_WM8904_MAP_MODULE(module), powerOn); +} + +/*! + * brief codec set record source. + * + * param handle codec handle. + * param source audio codec record source, can be a value or combine value of _codec_record_source. + * + * return kStatus_Success is success, else configure failed. + */ +status_t HAL_CODEC_SetRecord(codec_handle_t *handle, uint32_t recordSource) +{ + assert(handle != NULL); + + return WM8904_SetRecord((wm8904_handle_t *)((uint32_t) & (handle->codecDevHandle)), recordSource); +} + +/*! + * brief codec set record channel. + * + * param handle codec handle. + * param leftRecordChannel audio codec record channel, reference _codec_record_channel, can be a value or combine value + of member in _codec_record_channel. + * param rightRecordChannel audio codec record channel, reference _codec_record_channel, can be a value combine of + member in _codec_record_channel. + + * return kStatus_Success is success, else configure failed. + */ +status_t HAL_CODEC_SetRecordChannel(codec_handle_t *handle, uint32_t leftRecordChannel, uint32_t rightRecordChannel) +{ + assert(handle != NULL); + + return WM8904_SetRecordChannel((wm8904_handle_t *)((uint32_t) & (handle->codecDevHandle)), leftRecordChannel, + rightRecordChannel); +} + +/*! + * brief codec set play source. + * + * param handle codec handle. + * param playSource audio codec play source, can be a value or combine value of _codec_play_source. + * + * return kStatus_Success is success, else configure failed. + */ +status_t HAL_CODEC_SetPlay(codec_handle_t *handle, uint32_t playSource) +{ + assert(handle != NULL); + + return WM8904_SetPlay((wm8904_handle_t *)((uint32_t) & (handle->codecDevHandle)), playSource); +} + +/*! + * brief codec module control. + * + * param handle codec handle. + * param cmd module control cmd, reference _codec_module_ctrl_cmd. + * param data value to write, when cmd is kCODEC_ModuleRecordSourceChannel, the data should be a value combine + * of channel and source, please reference macro CODEC_MODULE_RECORD_SOURCE_CHANNEL(source, LP, LN, RP, RN), reference + * codec specific driver for detail configurations. + * return kStatus_Success is success, else configure failed. + */ +status_t HAL_CODEC_ModuleControl(codec_handle_t *handle, codec_module_ctrl_cmd_t cmd, uint32_t data) +{ + return kStatus_CODEC_NotSupport; +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/components/codec/wm8904/fsl_wm8904.c b/bsp/lpc55sxx/Libraries/LPC55S6X/components/codec/wm8904/fsl_wm8904.c new file mode 100644 index 000000000..4581089a5 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/components/codec/wm8904/fsl_wm8904.c @@ -0,0 +1,1092 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_wm8904.h" +#if WM8904_DEBUG_REGISTER +#include "fsl_debug_console.h" +#endif +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief wm8904 volume mapping */ +#define WM8904_MAP_DAC_ADC_VOLUME(volume) (volume * (255 / 100U)) +#define WM8904_MAP_PGA_VOLUME(volume) (volume > 0x1FU ? 0x1FU : volume) +#define WM8904_MAP_HEADPHONE_LINEOUT_VOLUME(volume) (volume > 0x3FU ? 0x3FU : volume) +#define WM8904_SWAP_UINT16_BYTE_SEQUENCE(x) (__REV16(x)) +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief WM8904 update format. + * + * @param handle WM8904 handle structure. + * @param format format configurations. + * @return kStatus_Success, else failed. + */ +static status_t WM8904_UpdateFormat(wm8904_handle_t *handle, wm8904_audio_format_t *format); + +/*! + * @brief WM8904 wait on write sequencer. + * + * @param handle WM8904 handle structure. + * @return kStatus_Success, else failed. + */ +static status_t WM8904_WaitOnWriteSequencer(wm8904_handle_t *handle); +/******************************************************************************* + * Variables + ******************************************************************************/ +#if WM8904_DEBUG_REGISTER +/*! @brief register definition */ +static const uint8_t allRegisters[] = { + 0x00, 0x04, 0x05, 0x06, 0x07, 0x0A, 0x0C, 0x0E, 0x0F, 0x12, 0x14, 0x15, 0x16, 0x18, 0x19, 0x1A, 0x1B, + 0x1E, 0x1F, 0x20, 0x21, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, 0x2E, 0x2F, 0x39, + 0x3A, 0x3B, 0x3C, 0x3D, 0x43, 0x44, 0x45, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x5A, 0x5E, 0x62, + 0x68, 0x6C, 0x6D, 0x6E, 0x6F, 0x70, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x7B, 0x7C, 0x7E, 0x7F, + 0x80, 0x81, 0x82, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x8B, 0x8C, 0x8D, 0x8E, 0x8F, 0x90, 0x91, 0x92, 0x93, + 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0x9B, 0x9C, 0x9D, 0xC6, 0xF7, 0xF8}; +#endif +/******************************************************************************* + * Code + ******************************************************************************/ +static status_t WM8904_UpdateFormat(wm8904_handle_t *handle, wm8904_audio_format_t *format) +{ + status_t result; + + /* Disable SYSCLK */ + result = WM8904_WriteRegister(handle, WM8904_CLK_RATES_2, 0x00); + if (result != kStatus_WM8904_Success) + { + return result; + } + + /* Set Clock ratio and sample rate */ + result = WM8904_WriteRegister(handle, WM8904_CLK_RATES_1, (format->fsRatio << 10) | format->sampleRate); + if (result != kStatus_WM8904_Success) + { + return result; + } + + /* Set bit resolution */ + result = WM8904_ModifyRegister(handle, WM8904_AUDIO_IF_1, 0x000C, format->bitWidth); + if (result != kStatus_WM8904_Success) + { + return result; + } + + /* Enable SYSCLK */ + result = WM8904_WriteRegister(handle, WM8904_CLK_RATES_2, 0x1007); + if (result != kStatus_WM8904_Success) + { + return result; + } + + return kStatus_WM8904_Success; +} + +static status_t WM8904_WaitOnWriteSequencer(wm8904_handle_t *handle) +{ + status_t result; + uint16_t value; + + do + { + result = WM8904_ReadRegister(handle, WM8904_WRT_SEQUENCER_4, &value); + } while ((result == kStatus_WM8904_Success) && (value & 1)); + + return result; +} + +/*! + * brief WM8904 write register. + * + * param handle WM8904 handle structure. + * param reg register address. + * param value value to write. + * return kStatus_Success, else failed. + */ +status_t WM8904_WriteRegister(wm8904_handle_t *handle, uint8_t reg, uint16_t value) +{ + assert(handle->config != NULL); + assert(handle->config->slaveAddress != 0U); + + uint16_t writeValue = WM8904_SWAP_UINT16_BYTE_SEQUENCE(value); + + return CODEC_I2C_Send(&(handle->i2cHandle), handle->config->slaveAddress, reg, 1U, (uint8_t *)&writeValue, 2U); +} + +/*! + * brief WM8904 write register. + * + * param handle WM8904 handle structure. + * param reg register address. + * param value value to read. + * return kStatus_Success, else failed. + */ +status_t WM8904_ReadRegister(wm8904_handle_t *handle, uint8_t reg, uint16_t *value) +{ + assert(handle->config != NULL); + assert(handle->config->slaveAddress != 0U); + + uint8_t retval = 0; + uint16_t readValue = 0U; + + retval = CODEC_I2C_Receive(&(handle->i2cHandle), handle->config->slaveAddress, reg, 1U, (uint8_t *)&readValue, 2U); + + *value = WM8904_SWAP_UINT16_BYTE_SEQUENCE(readValue); + + return retval; +} + +/*! + * brief WM8904 modify register. + * + * param handle WM8904 handle structure. + * param reg register address. + * oaram mask register bits mask. + * param value value to write. + * return kStatus_Success, else failed. + */ +status_t WM8904_ModifyRegister(wm8904_handle_t *handle, uint8_t reg, uint16_t mask, uint16_t value) +{ + status_t result; + uint16_t regValue; + + result = WM8904_ReadRegister(handle, reg, ®Value); + if (result != kStatus_WM8904_Success) + { + return result; + } + + regValue &= (uint16_t)~mask; + regValue |= value; + + return WM8904_WriteRegister(handle, reg, regValue); +} + +/*! + * brief Initializes WM8904. + * + * param handle WM8904 handle structure. + * param codec_config WM8904 configuration structure. + */ +status_t WM8904_Init(wm8904_handle_t *handle, wm8904_config_t *wm8904Config) +{ + assert(handle != NULL); + assert(wm8904Config != NULL); + + status_t result; + wm8904_config_t *config = wm8904Config; + handle->config = config; + + /* i2c bus initialization */ + result = CODEC_I2C_Init(&(handle->i2cHandle), wm8904Config->i2cConfig.codecI2CInstance, WM8904_I2C_BITRATE, + wm8904Config->i2cConfig.codecI2CSourceClock); + if (result != kStatus_HAL_I2cSuccess) + { + return kStatus_WM8904_Fail; + } + + /* reset */ + result = WM8904_WriteRegister(handle, WM8904_RESET, 0x0000); + if (result != kStatus_WM8904_Success) + { + return result; + } + + /* MCLK_INV=0, SYSCLK_SRC=0, TOCLK_RATE=0, OPCLK_ENA=1, + * CLK_SYS_ENA=1, CLK_DSP_ENA=1, TOCLK_ENA=1 */ + result = WM8904_WriteRegister(handle, WM8904_CLK_RATES_2, 0x000F); + if (result != kStatus_WM8904_Success) + { + return result; + } + + /* WSEQ_ENA=1, WSEQ_WRITE_INDEX=0_0000 */ + result = WM8904_WriteRegister(handle, WM8904_WRT_SEQUENCER_0, 0x0100); + if (result != kStatus_WM8904_Success) + { + return result; + } + + /* WSEQ_ABORT=0, WSEQ_START=1, WSEQ_START_INDEX=00_0000 */ + result = WM8904_WriteRegister(handle, WM8904_WRT_SEQUENCER_3, 0x0100); + if (result != kStatus_WM8904_Success) + { + return result; + } + + result = WM8904_WaitOnWriteSequencer(handle); + if (result != kStatus_WM8904_Success) + { + return result; + } + + /* TOCLK_RATE_DIV16=0, TOCLK_RATE_x4=1, SR_MODE=0, MCLK_DIV=1 + * (Required for MMCs: SGY, KRT see erratum CE000546) */ + result = WM8904_WriteRegister(handle, WM8904_CLK_RATES_0, 0xA45F); + if (result != kStatus_WM8904_Success) + { + return result; + } + + /* INL_ENA=1, INR ENA=1 */ + result = WM8904_WriteRegister(handle, WM8904_POWER_MGMT_0, 0x0003); + if (result != kStatus_WM8904_Success) + { + return result; + } + + /* HPL_PGA_ENA=1, HPR_PGA_ENA=1 */ + result = WM8904_WriteRegister(handle, WM8904_POWER_MGMT_2, 0x0003); + if (result != kStatus_WM8904_Success) + { + return result; + } + + /* DACL_ENA=1, DACR_ENA=1, ADCL_ENA=1, ADCR_ENA=1 */ + result = WM8904_WriteRegister(handle, WM8904_POWER_MGMT_6, 0x000F); + if (result != kStatus_WM8904_Success) + { + return result; + } + + /* ADC_OSR128=1 */ + result = WM8904_WriteRegister(handle, WM8904_ANALOG_ADC_0, 0x0001); + if (result != kStatus_WM8904_Success) + { + return result; + } + + /* DACL_DATINV=0, DACR_DATINV=0, DAC_BOOST=00, LOOPBACK=0, AIFADCL_SRC=0, + * AIFADCR_SRC=1, AIFDACL_SRC=0, AIFDACR_SRC=1, ADC_COMP=0, ADC_COMPMODE=0, + * DAC_COMP=0, DAC_COMPMODE=0 */ + result = WM8904_WriteRegister(handle, WM8904_AUDIO_IF_0, 0x0050); + if (result != kStatus_WM8904_Success) + { + return result; + } + + /* DAC_MONO=0, DAC_SB_FILT-0, DAC_MUTERATE=0, DAC_UNMUTE RAMP=0, + * DAC_OSR128=1, DAC_MUTE=0, DEEMPH=0 (none) */ + result = WM8904_WriteRegister(handle, WM8904_DAC_DIG_1, 0x0040); + if (result != kStatus_WM8904_Success) + { + return result; + } + + /* LINMUTE=0, LIN_VOL=0_0101 */ + result = WM8904_WriteRegister(handle, WM8904_ANALOG_LEFT_IN_0, 0x0005); + if (result != kStatus_WM8904_Success) + { + return result; + } + + /* RINMUTE=0, RIN VOL=0_0101 LINEOUTL RMV SHORT-1, LINEOUTL ENA_OUTP=1, + * LINEOUTL_ENA_DLY=1, LINEOUTL_ENA=1, LINEOUTR_RMV_SHORT-1, + * LINEOUTR_ENA_OUTP=1 */ + result = WM8904_WriteRegister(handle, WM8904_ANALOG_RIGHT_IN_0, 0x0005); + if (result != kStatus_WM8904_Success) + { + return result; + } + + /* HPOUTL_MUTE=0, HPOUT_VU=0, HPOUTLZC=0, HPOUTL_VOL=11_1001 */ + result = WM8904_WriteRegister(handle, WM8904_ANALOG_OUT1_LEFT, 0x0039); + if (result != kStatus_WM8904_Success) + { + return result; + } + + /* HPOUTR_MUTE=0, HPOUT_VU=0, HPOUTRZC=0, HPOUTR_VOL=11_1001 */ + result = WM8904_WriteRegister(handle, WM8904_ANALOG_OUT1_RIGHT, 0x0039); + if (result != kStatus_WM8904_Success) + { + return result; + } + + /* Enable DC servos for headphone out */ + result = WM8904_WriteRegister(handle, WM8904_DC_SERVO_0, 0x0003); + if (result != kStatus_WM8904_Success) + { + return result; + } + + /* HPL_RMV_SHORT=1, HPL_ENA_OUTP=1, HPL_ENA_DLY=1, HPL_ENA=1, + * HPR_RMV_SHORT=1, HPR_ENA_OUTP=1, HPR_ENA_DLY=1, HPR_ENA=1 */ + result = WM8904_WriteRegister(handle, WM8904_ANALOG_HP_0, 0x00FF); + if (result != kStatus_WM8904_Success) + { + return result; + } + + /* CP_DYN_PWR=1 */ + result = WM8904_WriteRegister(handle, WM8904_CLS_W_0, 0x0001); + if (result != kStatus_WM8904_Success) + { + return result; + } + + /* CP_ENA=1 */ + result = WM8904_WriteRegister(handle, WM8904_CHRG_PUMP_0, 0x0001); + if (result != kStatus_WM8904_Success) + { + return result; + } + + /* set wm8904 as slave */ + result = WM8904_SetMasterSlave(handle, config->master); + if (result != kStatus_WM8904_Success) + { + return result; + } + + /* set audio format */ + result = WM8904_SetProtocol(handle, config->protocol); + if (result != kStatus_WM8904_Success) + { + return result; + } + + result = WM8904_CheckAudioFormat(handle, &config->format, config->mclk_HZ); + if (result != kStatus_WM8904_Success) + { + return result; + } + + /* set record source and channel */ + result = WM8904_SetRecord(handle, config->recordSource); + if (result != kStatus_WM8904_Success) + { + return result; + } + result = WM8904_SetRecordChannel(handle, config->recordChannelLeft, config->recordChannelRight); + if (result != kStatus_WM8904_Success) + { + return result; + } + /* set play source */ + result = WM8904_SetPlay(handle, config->playSource); + if (result != kStatus_WM8904_Success) + { + return result; + } + + return result; +} + +/*! + * brief Deinitializes the WM8904 codec. + * + * This function resets WM8904. + * + * param handle WM8904 handle structure. + * + * return kStatus_WM8904_Success if successful, different code otherwise. + */ +status_t WM8904_Deinit(wm8904_handle_t *handle) +{ + /* reset */ + if (WM8904_WriteRegister(handle, WM8904_RESET, 0x0000) == kStatus_WM8904_Success) + { + return CODEC_I2C_Deinit(&(handle->i2cHandle)); + } + + return kStatus_WM8904_Fail; +} + +/*! + * brief Fills the configuration structure with default values. + * + * The default values are: + * + * master = false; + * protocol = kWM8904_ProtocolI2S; + * format.fsRatio = kWM8904_FsRatio64X; + * format.sampleRate = kWM8904_SampleRate48kHz; + * format.bitWidth = kWM8904_BitWidth16; + * + * param handle WM8904 handle structure to be filled with default values. + */ +void WM8904_GetDefaultConfig(wm8904_config_t *config) +{ + memset(config, 0, sizeof(wm8904_config_t)); + + config->master = false; + config->protocol = kWM8904_ProtocolI2S; + config->format.sampleRate = kWM8904_SampleRate48kHz; + config->format.bitWidth = kWM8904_BitWidth16; +} + +/*! + * brief Sets WM8904 as master or slave. + * + * param handle WM8904 handle structure. + * param master true for master, false for slave. + * + * return kStatus_WM8904_Success if successful, different code otherwise. + */ +status_t WM8904_SetMasterSlave(wm8904_handle_t *handle, bool master) +{ + if (master) + { + /* only slave currently supported */ + return kStatus_WM8904_Fail; + } + + return kStatus_WM8904_Success; +} + +/*! + * brief Sets the audio data transfer protocol. + * + * param handle WM8904 handle structure. + * param protocol Audio transfer protocol. + * + * return kStatus_WM8904_Success if successful, different code otherwise. + */ +status_t WM8904_SetProtocol(wm8904_handle_t *handle, wm8904_protocol_t protocol) +{ + return WM8904_ModifyRegister(handle, WM8904_AUDIO_IF_1, (0x0003 | (1U << 4U)), (uint16_t)protocol); +} + +/*! + * brief Select LRC polarity. + * + * param handle WM8904 handle structure. + * param polarity LRC clock polarity. + * + * return kStatus_WM8904_Success if successful, different code otherwise. + */ +status_t WM8904_SelectLRCPolarity(wm8904_handle_t *handle, uint32_t polarity) +{ + return WM8904_ModifyRegister(handle, WM8904_AUDIO_IF_1, 0x0010, polarity); +} + +/*! + * brief Enable WM8904 DAC time slot. + * + * param handle WM8904 handle structure. + * param timeslot timeslot number. + * + * return kStatus_WM8904_Success if successful, different code otherwise. + */ +status_t WM8904_EnableDACTDMMode(wm8904_handle_t *handle, wm8904_timeslot_t timeSlot) +{ + return WM8904_ModifyRegister(handle, WM8904_AUDIO_IF_1, 3U << 12U, 1U << 13U | timeSlot << 12U); +} + +/*! + * brief Enable WM8904 ADC time slot. + * + * param handle WM8904 handle structure. + * param timeslot timeslot number. + * + * return kStatus_WM8904_Success if successful, different code otherwise. + */ +status_t WM8904_EnableADCTDMMode(wm8904_handle_t *handle, wm8904_timeslot_t timeSlot) +{ + return WM8904_ModifyRegister(handle, WM8904_AUDIO_IF_1, 3U << 10U, 1U << 11U | timeSlot << 10U); +} + +/*! + * brief check and update the audio data format. + * This api is used check the fsRatio setting based on the mclk and sample rate, if fsRatio setting + * is not correct, it will correct it according to mclk and sample rate. + * param handle WM8904 handle structure. + * param format audio data format + * param mclkFreq mclk frequency + * + * return kStatus_WM8904_Success if successful, different code otherwise. + */ +status_t WM8904_CheckAudioFormat(wm8904_handle_t *handle, wm8904_audio_format_t *format, uint32_t mclkFreq) +{ + assert(handle && format); + + status_t result; + uint16_t mclkDiv = 0U; + uint32_t sampleRate = 0U; + uint32_t fsRatio = 0U; + + result = WM8904_ReadRegister(handle, WM8904_CLK_RATES_0, &mclkDiv); + if (kStatus_WM8904_Success != result) + { + return result; + } + + switch (format->sampleRate) + { + case kWM8904_SampleRate8kHz: + sampleRate = 8000; + break; + case kWM8904_SampleRate12kHz: + sampleRate = 12000; + break; + case kWM8904_SampleRate16kHz: + sampleRate = 16000; + break; + case kWM8904_SampleRate24kHz: + sampleRate = 24000; + break; + case kWM8904_SampleRate32kHz: + sampleRate = 32000; + break; + case kWM8904_SampleRate48kHz: + sampleRate = 48000; + break; + default: + break; + } + + fsRatio = (mclkFreq >> (mclkDiv & 0x1U)) / sampleRate; + + switch (fsRatio) + { + case 64: + format->fsRatio = kWM8904_FsRatio64X; + break; + case 128: + format->fsRatio = kWM8904_FsRatio128X; + break; + case 192: + format->fsRatio = kWM8904_FsRatio192X; + break; + case 256: + format->fsRatio = kWM8904_FsRatio256X; + break; + case 384: + format->fsRatio = kWM8904_FsRatio384X; + break; + case 512: + format->fsRatio = kWM8904_FsRatio512X; + break; + case 768: + format->fsRatio = kWM8904_FsRatio768X; + break; + case 1024: + format->fsRatio = kWM8904_FsRatio1024X; + break; + case 1408: + format->fsRatio = kWM8904_FsRatio1408X; + break; + case 1536: + format->fsRatio = kWM8904_FsRatio1536X; + break; + default: + break; + } + + return WM8904_UpdateFormat(handle, format); +} + +/*! + * brief Sets the audio data format. + * + * param handle WM8904 handle structure. + * param sysclk System clock frequency for codec, user should pay attention to this parater, sysclk is caculate as + * SYSCLK = MCLK / MCLKDIV, MCLKDIV is bit0 of WM8904_CLK_RATES_0. + * param sampleRate Sample rate frequency in Hz. + * param bitWidth Audio data bit width. + * + * return kStatus_WM8904_Success if successful, different code otherwise. + */ +status_t WM8904_SetAudioFormat(wm8904_handle_t *handle, uint32_t sysclk, uint32_t sampleRate, uint32_t bitWidth) +{ + status_t result; + wm8904_audio_format_t format; + uint32_t ratio = 0; + + switch (sampleRate) + { + case 8000: + format.sampleRate = kWM8904_SampleRate8kHz; + break; + case 11025: + case 12000: + format.sampleRate = kWM8904_SampleRate12kHz; + break; + case 16000: + format.sampleRate = kWM8904_SampleRate16kHz; + break; + case 22050: + case 24000: + format.sampleRate = kWM8904_SampleRate24kHz; + break; + case 32000: + format.sampleRate = kWM8904_SampleRate32kHz; + break; + case 44100: + case 48000: + format.sampleRate = kWM8904_SampleRate48kHz; + break; + default: + return kStatus_WM8904_Fail; + } + + switch (bitWidth) + { + case 16: + format.bitWidth = kWM8904_BitWidth16; + break; + case 20: + format.bitWidth = kWM8904_BitWidth20; + break; + case 24: + format.bitWidth = kWM8904_BitWidth24; + break; + case 32: + format.bitWidth = kWM8904_BitWidth32; + break; + default: + break; + } + + ratio = sysclk / sampleRate; + switch (ratio) + { + case 64: + format.fsRatio = kWM8904_FsRatio64X; + break; + case 128: + format.fsRatio = kWM8904_FsRatio128X; + break; + case 192: + format.fsRatio = kWM8904_FsRatio192X; + break; + case 256: + format.fsRatio = kWM8904_FsRatio256X; + break; + case 384: + format.fsRatio = kWM8904_FsRatio384X; + break; + case 512: + format.fsRatio = kWM8904_FsRatio512X; + break; + case 768: + format.fsRatio = kWM8904_FsRatio768X; + break; + case 1024: + format.fsRatio = kWM8904_FsRatio1024X; + break; + case 1408: + format.fsRatio = kWM8904_FsRatio1408X; + break; + case 1536: + format.fsRatio = kWM8904_FsRatio1536X; + break; + default: + return kStatus_WM8904_Fail; + } + + result = WM8904_UpdateFormat(handle, &format); + + return result; +} + +/*! + * brief Sets the headphone output volume. + * + * The parameter should be from 0 to 63. + * The resulting volume will be (parameter - 57 dB). + * 0 for -57 dB, 57 for 0 dB, 63 for +6 dB etc. + * + * param handle WM8904 handle structure. + * param volumeLeft Volume of the left channel. + * param volumeRight Volume of the right channel. + * + * return kStatus_WM8904_Success if successful, different code otherwise. + */ +status_t WM8904_SetVolume(wm8904_handle_t *handle, uint16_t volumeLeft, uint16_t volumeRight) +{ + status_t result; + + result = WM8904_ModifyRegister(handle, WM8904_ANALOG_OUT1_LEFT, 0x3F, volumeLeft); + if (result != kStatus_WM8904_Success) + { + return result; + } + + result = WM8904_ModifyRegister(handle, WM8904_ANALOG_OUT1_RIGHT, 0xBF, volumeRight | 0x0080); + if (result != kStatus_WM8904_Success) + { + return result; + } + + return kStatus_WM8904_Success; +} + +/*! + * brief Sets the headphone output mute. + * + * param handle WM8904 handle structure. + * param muteLeft true to mute left channel, false to unmute. + * param muteRight true to mute right channel, false to unmute. + * + * return kStatus_WM8904_Success if successful, different code otherwise. + */ +status_t WM8904_SetMute(wm8904_handle_t *handle, bool muteLeft, bool muteRight) +{ + status_t result; + uint16_t left = muteLeft ? 0x0100 : 0x0000; + uint16_t right = muteRight ? 0x0100 : 0x0000; + + result = WM8904_ModifyRegister(handle, WM8904_ANALOG_OUT1_LEFT, 0x0100, left); + if (result != kStatus_WM8904_Success) + { + return result; + } + + result = WM8904_ModifyRegister(handle, WM8904_ANALOG_OUT1_RIGHT, 0x0180, right | 0x0080); + if (result != kStatus_WM8904_Success) + { + return result; + } + + return kStatus_WM8904_Success; +} + +#if WM8904_DEBUG_REGISTER +/*! + * brief Reads content of all WM8904 registers and prints it to debug console. + * + * param handle WM8904 handle structure. + * + * return kStatus_WM8904_Success if successful, different code otherwise. + */ +status_t WM8904_PrintRegisters(wm8904_handle_t *handle) +{ + status_t result; + uint16_t value; + uint32_t i; + + for (i = 0; i < sizeof(allRegisters); i++) + { + result = WM8904_ReadRegister(handle, allRegisters[i], &value); + if (result != kStatus_WM8904_Success) + { + PRINTF("\r\n"); + return result; + } + PRINTF("%s", ((i % 8) == 0) ? "\r\n" : "\t"); + PRINTF("%02X:%04X", allRegisters[i], value); + } + + PRINTF("\r\n"); + return result; +} +#endif + +/*! + * brief Sets the channel output volume. + * + * The parameter should be from 0 to 100. + * The resulting volume will be. + * 0 for mute, 100 for maximum volume value. + * + * param handle codec handle structure. + * param channel codec channel. + * param volume volume value. + * + * return kStatus_WM8904_Success if successful, different code otherwise. + */ +status_t WM8904_SetChannelVolume(wm8904_handle_t *handle, uint32_t channel, uint32_t volume) +{ + status_t ret = kStatus_Fail; + volume = WM8904_MAP_HEADPHONE_LINEOUT_VOLUME(volume); + + /* headphone left channel */ + if (channel & kWM8904_HeadphoneLeft) + { + ret = WM8904_ModifyRegister(handle, WM8904_ANALOG_OUT1_LEFT, volume == 0U ? 0x100U : 0x3FU, + volume == 0U ? 0x100U : (volume)); + } + /* headphone right channel */ + if (channel & kWM8904_HeadphoneRight) + { + ret = WM8904_ModifyRegister(handle, WM8904_ANALOG_OUT1_RIGHT, volume == 0U ? 0x100U : 0xBFU, + volume == 0U ? 0x100U : (volume | 0x80U)); + } + /* line out left channel */ + if (channel & kWM8904_LineoutLeft) + { + ret = WM8904_ModifyRegister(handle, WM8904_ANALOG_OUT2_LEFT, volume == 0U ? 0x100U : 0x3FU, + volume == 0U ? 0x100U : (volume)); + } + /* line out right channel */ + if (channel & kWM8904_LineoutRight) + { + ret = WM8904_ModifyRegister(handle, WM8904_ANALOG_OUT2_RIGHT, volume == 0U ? 0x100U : 0xBFU, + volume == 0U ? 0x100U : (volume | 0x80U)); + } + + return ret; +} + +/*! + * brief Sets the channel mute. + * + * param handle codec handle structure. + * param channel codec module name. + * param isMute true is mute, false unmute. + * + * return kStatus_WM8904_Success if successful, different code otherwise. + */ +status_t WM8904_SetChannelMute(wm8904_handle_t *handle, uint32_t channel, bool isMute) +{ + status_t ret = kStatus_Fail; + uint16_t regValue = 0U, regMask = 0U; + + regValue = isMute ? 0x180U : 0x80U; + regMask = 0x100U; + + /* headphone left channel */ + if (channel & kWM8904_HeadphoneLeft) + { + ret = WM8904_ModifyRegister(handle, WM8904_ANALOG_OUT1_LEFT, regMask, regValue); + } + + /* headphone right channel */ + if (channel & kWM8904_HeadphoneRight) + { + ret = WM8904_ModifyRegister(handle, WM8904_ANALOG_OUT1_RIGHT, regMask, regValue); + } + + /* line out left channel */ + if (channel & kWM8904_LineoutLeft) + { + ret = WM8904_ModifyRegister(handle, WM8904_ANALOG_OUT2_LEFT, regMask, regValue); + } + + /* line out right channel */ + if (channel & kWM8904_LineoutRight) + { + ret = WM8904_ModifyRegister(handle, WM8904_ANALOG_OUT2_RIGHT, regMask, regValue); + } + + return ret; +} + +/*! + * brief SET the module output power. + * + * param handle WM8904 handle structure. + * param module wm8904 module. + * param isEnabled, true is power on, false is power down. + * + * return kStatus_WM8904_Success if successful, different code otherwise.. + */ +status_t WM8904_SetModulePower(wm8904_handle_t *handle, wm8904_module_t module, bool isEnabled) +{ + uint8_t regAddr = 0, regBitMask = 0U, regValue = 0U; + + switch (module) + { + case kWM8904_ModuleADC: + regAddr = WM8904_POWER_MGMT_6; + regBitMask = 3U; + regValue = isEnabled ? 3U : 0U; + break; + case kWM8904_ModuleDAC: + regAddr = WM8904_POWER_MGMT_6; + regBitMask = 0xCU; + regValue = isEnabled ? 0xCU : 0U; + + break; + case kWM8904_ModulePGA: + regAddr = WM8904_POWER_MGMT_0; + regBitMask = 3U; + regValue = isEnabled ? 3U : 0U; + + break; + case kWM8904_ModuleHeadphone: + regAddr = WM8904_POWER_MGMT_2; + regBitMask = 3U; + regValue = isEnabled ? 3U : 0U; + break; + case kWM8904_ModuleLineout: + regAddr = WM8904_POWER_MGMT_3; + regBitMask = 3U; + regValue = isEnabled ? 3U : 0U; + break; + default: + return kStatus_InvalidArgument; + } + + return WM8904_ModifyRegister(handle, regAddr, regBitMask, regValue); +} + +/*! + * brief SET the WM8904 record source. + * + * param handle WM8904 handle structure. + * param recordSource record source , can be a value of kWM8904_ModuleRecordSourceDifferentialLine, + * kWM8904_ModuleRecordSourceDifferentialMic, kWM8904_ModuleRecordSourceSingleEndMic, + * kWM8904_ModuleRecordSourceDigitalMic. + * + * return kStatus_WM8904_Success if successful, different code otherwise. + */ +status_t WM8904_SetRecord(wm8904_handle_t *handle, uint32_t recordSource) +{ + uint8_t regLeftAddr = WM8904_ANALOG_LEFT_IN_1, regRightAddr = WM8904_ANALOG_RIGHT_IN_1; + uint16_t regLeftValue = 0U, regRightValue = 0U, regBitMask; + status_t ret = kStatus_Success; + + switch (recordSource) + { + case kWM8904_RecordSourceDifferentialLine: + regLeftValue = 1U; + regRightValue = 1U; + regBitMask = 0x3FU; + break; + case kWM8904_RecordSourceDifferentialMic: + regLeftValue = 2U; + regRightValue = 2U; + regBitMask = 0x3FU; + break; + case kWM8904_RecordSourceLineInput: + regLeftValue = 0U; + regRightValue = 0U; + regBitMask = 0x3FU; + break; + case kWM8904_RecordSourceDigitalMic: + regLeftValue = (1U << 12U); + regLeftAddr = WM8904_DAC_DIG_0; + regRightAddr = 0U; + regBitMask = 1U << 12U; + break; + + default: + return kStatus_InvalidArgument; + } + + ret = WM8904_ModifyRegister(handle, regLeftAddr, regBitMask, regLeftValue); + + if ((ret == kStatus_Success) && (regRightAddr)) + { + return WM8904_ModifyRegister(handle, regRightAddr, regBitMask, regRightValue); + } + + return kStatus_Success; +} + +/*! + * brief SET the WM8904 record source. + * + * param handle WM8904 handle structure. + * param leftRecordChannel channel number of left record channel when using differential source, channel number of + * single end left channel when using single end source, channel number of digital mic when using digital mic source. + * param rightRecordChannel channel number of right record channel when using differential source, channel number + * of single end right channel when using single end source. + * + * return kStatus_WM8904_Success if successful, different code otherwise.. + */ +status_t WM8904_SetRecordChannel(wm8904_handle_t *handle, uint32_t leftRecordChannel, uint32_t rightRecordChannel) +{ + uint8_t regLeftAddr = WM8904_ANALOG_LEFT_IN_1, regRightAddr = WM8904_ANALOG_RIGHT_IN_1; + uint16_t regLeftValue = 0U, regRightValue = 0U, regBitMask; + status_t ret = kStatus_Success; + uint8_t leftPositiveChannel = 0U, leftNegativeChannel = 0U, rightPositiveChannel = 0U, rightNegativeChannel = 0U; + + if (leftRecordChannel & kWM8904_RecordChannelDifferentialPositive1) + { + leftPositiveChannel = 0U; + } + else if (leftRecordChannel & kWM8904_RecordChannelDifferentialPositive2) + { + leftPositiveChannel = 1U; + } + else + { + leftPositiveChannel = 2U; + } + + if (leftRecordChannel & kWM8904_RecordChannelDifferentialNegative1) + { + leftNegativeChannel = 0U; + } + else if (leftRecordChannel & kWM8904_RecordChannelDifferentialNegative2) + { + leftNegativeChannel = 1U; + } + else if (leftRecordChannel & kWM8904_RecordChannelDifferentialNegative3) + { + leftNegativeChannel = 2U; + } + else + { + leftNegativeChannel = leftPositiveChannel; + } + + if (rightRecordChannel & kWM8904_RecordChannelDifferentialPositive1) + { + rightPositiveChannel = 0U; + } + else if (rightRecordChannel & kWM8904_RecordChannelDifferentialPositive2) + { + rightPositiveChannel = 1U; + } + else + { + rightPositiveChannel = 2U; + } + + if (rightRecordChannel & kWM8904_RecordChannelDifferentialNegative1) + { + rightNegativeChannel = 0U; + } + else if (rightRecordChannel & kWM8904_RecordChannelDifferentialNegative2) + { + rightNegativeChannel = 1U; + } + else if (rightRecordChannel & kWM8904_RecordChannelDifferentialNegative3) + { + rightNegativeChannel = 2U; + } + else + { + rightNegativeChannel = rightPositiveChannel; + } + + regLeftValue = ((leftNegativeChannel & 3U) << 4U) | ((leftPositiveChannel & 3U) << 2U); + regRightValue = ((rightNegativeChannel & 3U) << 4U) | ((rightPositiveChannel & 3U) << 2U); + regBitMask = 0x3CU; + + ret = WM8904_ModifyRegister(handle, regLeftAddr, regBitMask, regLeftValue); + + if ((ret == kStatus_Success) && (regRightAddr)) + { + return WM8904_ModifyRegister(handle, regRightAddr, regBitMask, regRightValue); + } + + return kStatus_Success; +} + +/*! + * brief SET the WM8904 play source. + * + * param handle WM8904 handle structure. + * param playSource play source , can be a value of kWM8904_PlaySourcePGA/kWM8904_PlaySourceDAC. + * + * return kStatus_WM8904_Success if successful, different code otherwise.. + */ +status_t WM8904_SetPlay(wm8904_handle_t *handle, uint32_t playSource) +{ + uint16_t regValue = 0U, regBitMask = 0xFU; + + /* source form PGA*/ + if (playSource == kWM8904_PlaySourcePGA) + { + regValue |= (3U << 2U) | 3U; + } + /* source from DAC*/ + if (playSource == kWM8904_PlaySourceDAC) + { + regValue &= ~((3U << 2U) | 3U); + } + + return WM8904_ModifyRegister(handle, WM8904_ANALOG_OUT12_ZC, regBitMask, regValue); +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/components/codec/wm8904/fsl_wm8904.h b/bsp/lpc55sxx/Libraries/LPC55S6X/components/codec/wm8904/fsl_wm8904.h new file mode 100644 index 000000000..dc94820db --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/components/codec/wm8904/fsl_wm8904.h @@ -0,0 +1,496 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_WM8904_H_ +#define _FSL_WM8904_H_ + +#include "fsl_common.h" +#include "fsl_codec_i2c.h" +/*! + * @addtogroup wm8904 + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @name Driver version */ +/*@{*/ +/*! @brief WM8904 driver version 2.1.0. */ +#define FSL_WM8904_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) +/*@}*/ + +/*! @brief wm8904 handle size */ +#ifndef WM8904_HANDLE_SIZE +#define WM8904_HANDLE_SIZE (100U) +#endif +/*! @brief wm8904 debug macro */ +#ifndef WM8904_DEBUG_REGISTER +#define WM8904_DEBUG_REGISTER 0 +#endif + +/*! @brief WM8904 register map*/ +#define WM8904_RESET (0x00) +#define WM8904_ANALOG_ADC_0 (0x0A) +#define WM8904_POWER_MGMT_0 (0x0C) +#define WM8904_POWER_MGMT_2 (0x0E) +#define WM8904_POWER_MGMT_3 (0x0F) +#define WM8904_POWER_MGMT_6 (0x12) +#define WM8904_CLK_RATES_0 (0x14) +#define WM8904_CLK_RATES_1 (0x15) +#define WM8904_CLK_RATES_2 (0x16) +#define WM8904_AUDIO_IF_0 (0x18) +#define WM8904_AUDIO_IF_1 (0x19) +#define WM8904_AUDIO_IF_2 (0x1A) +#define WM8904_AUDIO_IF_3 (0x1B) +#define WM8904_DAC_DIG_1 (0x21) +#define WM8904_DAC_DIG_0 (0x27) +#define WM8904_ANALOG_LEFT_IN_0 (0x2C) +#define WM8904_ANALOG_RIGHT_IN_0 (0x2D) +#define WM8904_ANALOG_LEFT_IN_1 (0x2E) +#define WM8904_ANALOG_RIGHT_IN_1 (0x2F) +#define WM8904_ANALOG_OUT1_LEFT (0x39) +#define WM8904_ANALOG_OUT1_RIGHT (0x3A) +#define WM8904_ANALOG_OUT12_ZC (0x3D) +#define WM8904_DC_SERVO_0 (0x43) +#define WM8904_ANALOG_HP_0 (0x5A) +#define WM8904_CHRG_PUMP_0 (0x62) +#define WM8904_CLS_W_0 (0x68) +#define WM8904_WRT_SEQUENCER_0 (0x6C) +#define WM8904_WRT_SEQUENCER_3 (0x6F) +#define WM8904_WRT_SEQUENCER_4 (0x70) +#define WM8904_DAC_DIGITAL_VOLUME_LEFT (0x1E) +#define WM8904_DAC_DIGITAL_VOLUME_RIGHT (0x1F) +#define WM8904_ADC_DIGITAL_VOLUME_LEFT (0x24) +#define WM8904_ADC_DIGITAL_VOLUME_RIGHT (0x25) +#define WM8904_ANALOG_OUT2_LEFT (0x3B) +#define WM8904_ANALOG_OUT2_RIGHT (0x3C) + +/*! @brief WM8904 I2C address. */ +#define WM8904_I2C_ADDRESS (0x1A) + +/*! @brief WM8904 I2C bit rate. */ +#define WM8904_I2C_BITRATE (400000U) + +/*! @brief WM8904 status return codes. */ +enum _wm8904_status +{ + kStatus_WM8904_Success = 0x0, /*!< Success */ + kStatus_WM8904_Fail = 0x1 /*!< Failure */ +}; + +/*! @brief WM8904 lrc polarity. */ +enum _wm8904_lrc_polarity +{ + kWM8904_LRCPolarityNormal = 0U, /*!< LRC polarity normal */ + kWM8904_LRCPolarityInverted = 1U << 4U, /*!< LRC polarity inverted */ +}; + +/*! @brief wm8904 module value*/ +typedef enum _wm8904_module +{ + kWM8904_ModuleADC = 0, /*!< moduel ADC */ + kWM8904_ModuleDAC = 1, /*!< module DAC */ + kWM8904_ModulePGA = 2, /*!< module PGA */ + kWM8904_ModuleHeadphone = 3, /*!< module headphone */ + kWM8904_ModuleLineout = 4, /*!< module line out */ +} wm8904_module_t; + +/*! @brief wm8904 play channel */ +enum _wm8904_play_channel +{ + kWM8904_HeadphoneLeft = 1U, + kWM8904_HeadphoneRight = 2U, + kWM8904_LineoutLeft = 4U, + kWM8904_LineoutRight = 8U, +}; + +/*! @brief WM8904 time slot. */ +typedef enum _wm8904_timeslot +{ + kWM8904_TimeSlot0 = 0U, /*!< time slot0 */ + kWM8904_TimeSlot1 = 1U, /*!< time slot1 */ +} wm8904_timeslot_t; + +/*! @brief The audio data transfer protocol. */ +typedef enum _wm8904_protocol +{ + kWM8904_ProtocolI2S = 0x2, /*!< I2S type */ + kWM8904_ProtocolLeftJustified = 0x1, /*!< Left justified mode */ + kWM8904_ProtocolRightJustified = 0x0, /*!< Right justified mode */ + kWM8904_ProtocolPCMA = 0x3, /*!< PCM A mode */ + kWM8904_ProtocolPCMB = 0x3 | (1 << 4), /*!< PCM B mode */ +} wm8904_protocol_t; + +/*! @brief The SYSCLK / fs ratio. */ +typedef enum _wm8904_fs_ratio +{ + kWM8904_FsRatio64X = 0x0, /*!< SYSCLK is 64 * sample rate * frame width */ + kWM8904_FsRatio128X = 0x1, /*!< SYSCLK is 128 * sample rate * frame width */ + kWM8904_FsRatio192X = 0x2, /*!< SYSCLK is 192 * sample rate * frame width */ + kWM8904_FsRatio256X = 0x3, /*!< SYSCLK is 256 * sample rate * frame width */ + kWM8904_FsRatio384X = 0x4, /*!< SYSCLK is 384 * sample rate * frame width */ + kWM8904_FsRatio512X = 0x5, /*!< SYSCLK is 512 * sample rate * frame width */ + kWM8904_FsRatio768X = 0x6, /*!< SYSCLK is 768 * sample rate * frame width */ + kWM8904_FsRatio1024X = 0x7, /*!< SYSCLK is 1024 * sample rate * frame width */ + kWM8904_FsRatio1408X = 0x8, /*!< SYSCLK is 1408 * sample rate * frame width */ + kWM8904_FsRatio1536X = 0x9 /*!< SYSCLK is 1536 * sample rate * frame width */ +} wm8904_fs_ratio_t; + +/*! @brief Sample rate. */ +typedef enum _wm8904_sample_rate +{ + kWM8904_SampleRate8kHz = 0x0, /*!< 8 kHz */ + kWM8904_SampleRate12kHz = 0x1, /*!< 11.025kHz, 12kHz */ + kWM8904_SampleRate16kHz = 0x2, /*!< 16kHz */ + kWM8904_SampleRate24kHz = 0x3, /*!< 22.05kHz, 24kHz */ + kWM8904_SampleRate32kHz = 0x4, /*!< 32kHz */ + kWM8904_SampleRate48kHz = 0x5 /*!< 44.1kHz, 48kHz */ +} wm8904_sample_rate_t; + +/*! @brief Bit width. */ +typedef enum _wm8904_bit_width +{ + kWM8904_BitWidth16 = 0x0, /*!< 16 bits */ + kWM8904_BitWidth20 = 0x1, /*!< 20 bits */ + kWM8904_BitWidth24 = 0x2, /*!< 24 bits */ + kWM8904_BitWidth32 = 0x3 /*!< 32 bits */ +} wm8904_bit_width_t; + +/*! @brief wm8904 record source */ +enum _wm8904_record_source +{ + kWM8904_RecordSourceDifferentialLine = 1U, /*!< record source from differential line */ + kWM8904_RecordSourceLineInput = 2U, /*!< record source from line input */ + kWM8904_RecordSourceDifferentialMic = 4U, /*!< record source from differential mic */ + kWM8904_RecordSourceDigitalMic = 8U, /*!< record source from digital microphone */ +}; + +/*! @brief wm8904 record channel*/ +enum _wm8904_record_channel +{ + kWM8904_RecordChannelLeft1 = 1U, /*!< left record channel 1 */ + kWM8904_RecordChannelLeft2 = 2U, /*!< left record channel 2 */ + kWM8904_RecordChannelLeft3 = 4U, /*!< left record channel 3 */ + kWM8904_RecordChannelRight1 = 1U, /*!< right record channel 1 */ + kWM8904_RecordChannelRight2 = 2U, /*!< right record channel 2 */ + kWM8904_RecordChannelRight3 = 4U, /*!< right record channel 3 */ + kWM8904_RecordChannelDifferentialPositive1 = 1U, /*!< differential positive record channel 1 */ + kWM8904_RecordChannelDifferentialPositive2 = 2U, /*!< differential positive record channel 2 */ + kWM8904_RecordChannelDifferentialPositive3 = 4U, /*!< differential positive record channel 3 */ + kWM8904_RecordChannelDifferentialNegative1 = 8U, /*!< differential negative record channel 1 */ + kWM8904_RecordChannelDifferentialNegative2 = 16U, /*!< differential negative record channel 2 */ + kWM8904_RecordChannelDifferentialNegative3 = 32U, /*!< differential negative record channel 3 */ +}; + +/*! @brief wm8904 play source*/ +enum _wm8904_play_source +{ + kWM8904_PlaySourcePGA = 1U, /*!< play source PGA, bypass ADC */ + kWM8904_PlaySourceDAC = 4U, /*!< play source Input3 */ +}; + +/*! @brief Audio format configuration. */ +typedef struct _wm8904_audio_format +{ + wm8904_fs_ratio_t fsRatio; /*!< SYSCLK / fs ratio */ + wm8904_sample_rate_t sampleRate; /*!< Sample rate */ + wm8904_bit_width_t bitWidth; /*!< Bit width */ +} wm8904_audio_format_t; + +/*! @brief Configuration structure of WM8904.*/ +typedef struct _wm8904_config +{ + bool master; /*!< Master or slave */ + wm8904_protocol_t protocol; /*!< Audio transfer protocol */ + wm8904_audio_format_t format; /*!< Audio format */ + uint32_t mclk_HZ; /*!< MCLK frequency value */ + + uint16_t recordSource; /*!< record source */ + uint16_t recordChannelLeft; /*!< record channel */ + uint16_t recordChannelRight; /*!< record channel */ + uint16_t playSource; /*!< play source */ + + uint8_t slaveAddress; /*!< code device slave address */ + codec_i2c_config_t i2cConfig; /*!< i2c bus configuration */ +} wm8904_config_t; + +/*! @brief wm8904 codec handler + * Applicationi should allocate a buffer with WM8904_HANDLE_SIZE for handle definition, such as + * uint8_t wm8904HandleBuffer[WM8904_HANDLE_SIZE]; + * wm8904_handle_t *wm8904Handle = wm8904HandleBuffer; + */ +typedef struct _wm8904_handle +{ + wm8904_config_t *config; /*!< wm8904 config pointer */ + void *i2cHandle; /*!< i2c handle */ +} wm8904_handle_t; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief WM8904 write register. + * + * @param handle WM8904 handle structure. + * @param reg register address. + * @param value value to write. + * @return kStatus_Success, else failed. + */ +status_t WM8904_WriteRegister(wm8904_handle_t *handle, uint8_t reg, uint16_t value); + +/*! + * @brief WM8904 write register. + * + * @param handle WM8904 handle structure. + * @param reg register address. + * @param value value to read. + * @return kStatus_Success, else failed. + */ +status_t WM8904_ReadRegister(wm8904_handle_t *handle, uint8_t reg, uint16_t *value); + +/*! + * @brief WM8904 modify register. + * + * @param handle WM8904 handle structure. + * @param reg register address. + * @oaram mask register bits mask. + * @param value value to write. + * @return kStatus_Success, else failed. + */ +status_t WM8904_ModifyRegister(wm8904_handle_t *handle, uint8_t reg, uint16_t mask, uint16_t value); + +/*! + * @brief Initializes WM8904. + * + * @param handle WM8904 handle structure. + * @param codec_config WM8904 configuration structure. + */ +status_t WM8904_Init(wm8904_handle_t *handle, wm8904_config_t *wm8904_config); + +/*! + * @brief Deinitializes the WM8904 codec. + * + * This function resets WM8904. + * + * @param handle WM8904 handle structure. + * + * @return kStatus_WM8904_Success if successful, different code otherwise. + */ +status_t WM8904_Deinit(wm8904_handle_t *handle); + +/*! + * @brief Fills the configuration structure with default values. + * + * The default values are: + * + * master = false; + * protocol = kWM8904_ProtocolI2S; + * format.fsRatio = kWM8904_FsRatio64X; + * format.sampleRate = kWM8904_SampleRate48kHz; + * format.bitWidth = kWM8904_BitWidth16; + * + * @param handle WM8904 handle structure to be filled with default values. + */ +void WM8904_GetDefaultConfig(wm8904_config_t *config); + +/*! + * @brief Sets WM8904 as master or slave. + * + * @param handle WM8904 handle structure. + * @param master true for master, false for slave. + * + * @return kStatus_WM8904_Success if successful, different code otherwise. + */ +status_t WM8904_SetMasterSlave(wm8904_handle_t *handle, bool master); + +/*! + * @brief Sets the audio data transfer protocol. + * + * @param handle WM8904 handle structure. + * @param protocol Audio transfer protocol. + * + * @return kStatus_WM8904_Success if successful, different code otherwise. + */ +status_t WM8904_SetProtocol(wm8904_handle_t *handle, wm8904_protocol_t protocol); + +/*! + * @brief Sets the audio data format. + * + * @param handle WM8904 handle structure. + * @param sysclk System clock frequency for codec, user should pay attention to this parater, sysclk is caculate as + * SYSCLK = MCLK / MCLKDIV, MCLKDIV is bit0 of WM8904_CLK_RATES_0. + * @param sampleRate Sample rate frequency in Hz. + * @param bitWidth Audio data bit width. + * + * @return kStatus_WM8904_Success if successful, different code otherwise. + */ +status_t WM8904_SetAudioFormat(wm8904_handle_t *handle, uint32_t sysclk, uint32_t sampleRate, uint32_t bitWidth); + +/*! + * @brief check and update the audio data format. + * This api is used check the fsRatio setting based on the mclk and sample rate, if fsRatio setting + * is not correct, it will correct it according to mclk and sample rate. + * @param handle WM8904 handle structure. + * @param format audio data format + * @param mclkFreq mclk frequency + * + * @return kStatus_WM8904_Success if successful, different code otherwise. + */ +status_t WM8904_CheckAudioFormat(wm8904_handle_t *handle, wm8904_audio_format_t *format, uint32_t mclkFreq); + +/*! + * @brief Sets the module output volume. + * + * The parameter should be from 0 to 100. + * The resulting volume will be. + * 0 for mute, 100 for maximum volume value. + * + * @param handle WM8904 handle structure. + * @param module wm8904 module name. + * @param volume volume value. + * + * @return kStatus_WM8904_Success if successful, different code otherwise. + */ +status_t WM8904_SetVolume(wm8904_handle_t *handle, uint16_t volumeLeft, uint16_t volumeRight); + +/*! + * @brief Sets the headphone output mute. + * + * @param handle WM8904 handle structure. + * @param muteLeft true to mute left channel, false to unmute. + * @param muteRight true to mute right channel, false to unmute. + * + * @return kStatus_WM8904_Success if successful, different code otherwise. + */ +status_t WM8904_SetMute(wm8904_handle_t *handle, bool muteLeft, bool muteRight); + +/*! + * @brief Select LRC polarity. + * + * @param handle WM8904 handle structure. + * @param polarity LRC clock polarity. + * + * @return kStatus_WM8904_Success if successful, different code otherwise. + */ +status_t WM8904_SelectLRCPolarity(wm8904_handle_t *handle, uint32_t polarity); + +/*! + * @brief Enable WM8904 DAC time slot. + * + * @param handle WM8904 handle structure. + * @param timeslot timeslot number. + * + * @return kStatus_WM8904_Success if successful, different code otherwise. + */ +status_t WM8904_EnableDACTDMMode(wm8904_handle_t *handle, wm8904_timeslot_t timeSlot); + +/*! + * @brief Enable WM8904 ADC time slot. + * + * @param handle WM8904 handle structure. + * @param timeslot timeslot number. + * + * @return kStatus_WM8904_Success if successful, different code otherwise. + */ +status_t WM8904_EnableADCTDMMode(wm8904_handle_t *handle, wm8904_timeslot_t timeSlot); + +#if WM8904_DEBUG_REGISTER +/*! + * @brief Reads content of all WM8904 registers and prints it to debug console. + * + * @param handle WM8904 handle structure. + * + * @return kStatus_WM8904_Success if successful, different code otherwise. + */ +status_t WM8904_PrintRegisters(wm8904_handle_t *handle); +#endif + +/*! + * brief SET the module output power. + * + * param handle WM8904 handle structure. + * param module wm8904 module. + * param isEnabled, true is power on, false is power down. + * + * return kStatus_WM8904_Success if successful, different code otherwise.. + */ +status_t WM8904_SetModulePower(wm8904_handle_t *handle, wm8904_module_t module, bool isEnabled); + +/*! + * @brief Sets the channel output volume. + * + * The parameter should be from 0 to 100. + * The resulting volume will be. + * 0 for mute, 100 for maximum volume value. + * + * param handle codec handle structure. + * @param channel codec channel. + * @param volume volume value. + * + * @return kStatus_WM8904_Success if successful, different code otherwise. + */ +status_t WM8904_SetChannelVolume(wm8904_handle_t *handle, uint32_t channel, uint32_t volume); + +/*! + * @brief SET the WM8904 record source. + * + * @param handle WM8904 handle structure. + * @param recordSource record source , can be a value of kCODEC_ModuleRecordSourceDifferentialLine, + * kCODEC_ModuleRecordSourceDifferentialMic, kCODEC_ModuleRecordSourceSingleEndMic, kCODEC_ModuleRecordSourceDigitalMic. + * + * @return kStatus_WM8904_Success if successful, different code otherwise. + */ +status_t WM8904_SetRecord(wm8904_handle_t *handle, uint32_t recordSource); + +/*! + * @brief SET the WM8904 record source. + * + * @param handle WM8904 handle structure. + * @param leftRecordChannel channel number of left record channel when using differential source, channel number of + * single end left channel when using single end source, channel number of digital mic when using digital mic source. + * @param rightRecordChannel channel number of right record channel when using differential source, channel number + * of single end right channel when using single end source. + * + * @return kStatus_WM8904_Success if successful, different code otherwise.. + */ +status_t WM8904_SetRecordChannel(wm8904_handle_t *handle, uint32_t leftRecordChannel, uint32_t rightRecordChannel); + +/*! + * @brief SET the WM8904 play source. + * + * @param handle WM8904 handle structure. + * @param playSource play source , can be a value of kCODEC_ModuleHeadphoneSourcePGA, + * kCODEC_ModuleHeadphoneSourceDAC, kCODEC_ModuleLineoutSourcePGA, kCODEC_ModuleLineoutSourceDAC. + * + * @return kStatus_WM8904_Success if successful, different code otherwise.. + */ +status_t WM8904_SetPlay(wm8904_handle_t *handle, uint32_t playSource); + +/*! + * @brief Sets the channel mute. + * + * @param handle codec handle structure. + * @param module codec module name. + * @param isMute true is mute, false unmute. + * + * @return kStatus_WM8904_Success if successful, different code otherwise. + */ +status_t WM8904_SetChannelMute(wm8904_handle_t *handle, uint32_t channel, bool isMute); + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /* _FSL_WM8904_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/inc/fsl_mmc.h b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/inc/fsl_mmc.h new file mode 100644 index 000000000..986db0d1e --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/inc/fsl_mmc.h @@ -0,0 +1,321 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_MMC_H_ +#define _FSL_MMC_H_ + +#include "fsl_sdmmc_common.h" + +/*! + * @addtogroup MMCCARD + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief MMC card flags */ +enum _mmc_card_flag +{ + kMMC_SupportHighSpeed26MHZFlag = (1U << 0U), /*!< Support high speed 26MHZ */ + kMMC_SupportHighSpeed52MHZFlag = (1U << 1U), /*!< Support high speed 52MHZ */ + kMMC_SupportHighSpeedDDR52MHZ180V300VFlag = (1 << 2U), /*!< ddr 52MHZ 1.8V or 3.0V */ + kMMC_SupportHighSpeedDDR52MHZ120VFlag = (1 << 3U), /*!< DDR 52MHZ 1.2V */ + kMMC_SupportHS200200MHZ180VFlag = (1 << 4U), /*!< HS200 ,200MHZ,1.8V */ + kMMC_SupportHS200200MHZ120VFlag = (1 << 5U), /*!< HS200, 200MHZ, 1.2V */ + kMMC_SupportHS400DDR200MHZ180VFlag = (1 << 6U), /*!< HS400, DDR, 200MHZ,1.8V */ + kMMC_SupportHS400DDR200MHZ120VFlag = (1 << 7U), /*!< HS400, DDR, 200MHZ,1.2V */ + kMMC_SupportHighCapacityFlag = (1U << 8U), /*!< Support high capacity */ + kMMC_SupportAlternateBootFlag = (1U << 9U), /*!< Support alternate boot */ + kMMC_SupportDDRBootFlag = (1U << 10U), /*!< support DDR boot flag*/ + kMMC_SupportHighSpeedBootFlag = (1U << 11U), /*!< support high speed boot flag*/ +}; + +/*! + * @brief mmc card state + * + * Define the card structure including the necessary fields to identify and describe the card. + */ +typedef struct _mmc_card +{ + SDMMCHOST_CONFIG host; /*!< Host information */ + mmccard_usr_param_t usrParam; /*!< user parameter */ + + bool isHostReady; /*!< Use this flag to indicate if need host re-init or not*/ + bool noInteralAlign; /*!< use this flag to disable sdmmc align. If disable, sdmmc will not make sure the + data buffer address is word align, otherwise all the transfer are align to low level driver */ + uint32_t busClock_Hz; /*!< MMC bus clock united in Hz */ + uint32_t relativeAddress; /*!< Relative address of the card */ + bool enablePreDefinedBlockCount; /*!< Enable PRE-DEFINED block count when read/write */ + uint32_t flags; /*!< Capability flag in _mmc_card_flag */ + uint32_t rawCid[4U]; /*!< Raw CID content */ + uint32_t rawCsd[4U]; /*!< Raw CSD content */ + uint32_t rawExtendedCsd[MMC_EXTENDED_CSD_BYTES / 4U]; /*!< Raw MMC Extended CSD content */ + uint32_t ocr; /*!< Raw OCR content */ + mmc_cid_t cid; /*!< CID */ + mmc_csd_t csd; /*!< CSD */ + mmc_extended_csd_t extendedCsd; /*!< Extended CSD */ + uint32_t blockSize; /*!< Card block size */ + uint32_t userPartitionBlocks; /*!< Card total block number in user partition */ + uint32_t bootPartitionBlocks; /*!< Boot partition size united as block size */ + uint32_t eraseGroupBlocks; /*!< Erase group size united as block size */ + mmc_access_partition_t currentPartition; /*!< Current access partition */ + mmc_voltage_window_t hostVoltageWindowVCCQ; /*!< Host IO voltage window */ + mmc_voltage_window_t hostVoltageWindowVCC; /*!< application must set this value according to board specific */ + mmc_high_speed_timing_t busTiming; /*!< indicate the current work timing mode*/ + mmc_data_bus_width_t busWidth; /*!< indicate the current work bus width */ +} mmc_card_t; + +/************************************************************************************************* + * API + ************************************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name MMCCARD Function + * @{ + */ + +/*! + * @brief Initializes the MMC card and host. + * + * @param card Card descriptor. + * + * @retval kStatus_SDMMC_HostNotReady host is not ready. + * @retval kStatus_SDMMC_GoIdleFailed Go idle failed. + * @retval kStatus_SDMMC_SendOperationConditionFailed Send operation condition failed. + * @retval kStatus_SDMMC_AllSendCidFailed Send CID failed. + * @retval kStatus_SDMMC_SetRelativeAddressFailed Set relative address failed. + * @retval kStatus_SDMMC_SendCsdFailed Send CSD failed. + * @retval kStatus_SDMMC_CardNotSupport Card not support. + * @retval kStatus_SDMMC_SelectCardFailed Send SELECT_CARD command failed. + * @retval kStatus_SDMMC_SendExtendedCsdFailed Send EXT_CSD failed. + * @retval kStatus_SDMMC_SetBusWidthFailed Set bus width failed. + * @retval kStatus_SDMMC_SwitchHighSpeedFailed Switch high speed failed. + * @retval kStatus_SDMMC_SetCardBlockSizeFailed Set card block size failed. + * @retval kStatus_Success Operate successfully. + */ +status_t MMC_Init(mmc_card_t *card); + +/*! + * @brief Deinitializes the card and host. + * + * @param card Card descriptor. + */ +void MMC_Deinit(mmc_card_t *card); + +/*! + * @brief intialize the card. + * + * @param card Card descriptor. + * + * @retval kStatus_SDMMC_HostNotReady host is not ready. + * @retval kStatus_SDMMC_GoIdleFailed Go idle failed. + * @retval kStatus_SDMMC_SendOperationConditionFailed Send operation condition failed. + * @retval kStatus_SDMMC_AllSendCidFailed Send CID failed. + * @retval kStatus_SDMMC_SetRelativeAddressFailed Set relative address failed. + * @retval kStatus_SDMMC_SendCsdFailed Send CSD failed. + * @retval kStatus_SDMMC_CardNotSupport Card not support. + * @retval kStatus_SDMMC_SelectCardFailed Send SELECT_CARD command failed. + * @retval kStatus_SDMMC_SendExtendedCsdFailed Send EXT_CSD failed. + * @retval kStatus_SDMMC_SetBusWidthFailed Set bus width failed. + * @retval kStatus_SDMMC_SwitchHighSpeedFailed Switch high speed failed. + * @retval kStatus_SDMMC_SetCardBlockSizeFailed Set card block size failed. + * @retval kStatus_Success Operate successfully. + */ +status_t MMC_CardInit(mmc_card_t *card); + +/*! + * @brief Deinitializes the card. + * + * @param card Card descriptor. + */ +void MMC_CardDeinit(mmc_card_t *card); + +/*! + * @brief initialize the host. + * + * This function deinitializes the specific host. + * + * @param card Card descriptor. + */ +status_t MMC_HostInit(mmc_card_t *card); + +/*! + * @brief Deinitializes the host. + * + * This function deinitializes the host. + * + * @param card Card descriptor. + */ +void MMC_HostDeinit(mmc_card_t *card); + +/*! + * @brief reset the host. + * + * This function reset the specific host. + * + * @param host host descriptor. + */ +void MMC_HostReset(SDMMCHOST_CONFIG *host); + +/*! + * @brief power on card. + * + * The power on operation depend on host or the user define power on function. + * @param base host base address. + * @param pwr user define power control configuration + */ +void MMC_PowerOnCard(SDMMCHOST_TYPE *base, const sdmmchost_pwr_card_t *pwr); + +/*! + * @brief power off card. + * + * The power off operation depend on host or the user define power on function. + * @param base host base address. + * @param pwr user define power control configuration + */ +void MMC_PowerOffCard(SDMMCHOST_TYPE *base, const sdmmchost_pwr_card_t *pwr); + +/*! + * @brief Checks if the card is read-only. + * + * @param card Card descriptor. + * @retval true Card is read only. + * @retval false Card isn't read only. + */ +bool MMC_CheckReadOnly(mmc_card_t *card); + +/*! + * @brief Reads data blocks from the card. + * + * @param card Card descriptor. + * @param buffer The buffer to save data. + * @param startBlock The start block index. + * @param blockCount The number of blocks to read. + * @retval kStatus_InvalidArgument Invalid argument. + * @retval kStatus_SDMMC_CardNotSupport Card not support. + * @retval kStatus_SDMMC_SetBlockCountFailed Set block count failed. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_SDMMC_StopTransmissionFailed Stop transmission failed. + * @retval kStatus_Success Operate successfully. + */ +status_t MMC_ReadBlocks(mmc_card_t *card, uint8_t *buffer, uint32_t startBlock, uint32_t blockCount); + +/*! + * @brief Writes data blocks to the card. + * + * @param card Card descriptor. + * @param buffer The buffer to save data blocks. + * @param startBlock Start block number to write. + * @param blockCount Block count. + * @retval kStatus_InvalidArgument Invalid argument. + * @retval kStatus_SDMMC_NotSupportYet Not support now. + * @retval kStatus_SDMMC_SetBlockCountFailed Set block count failed. + * @retval kStatus_SDMMC_WaitWriteCompleteFailed Send status failed. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_SDMMC_StopTransmissionFailed Stop transmission failed. + * @retval kStatus_Success Operate successfully. + */ +status_t MMC_WriteBlocks(mmc_card_t *card, const uint8_t *buffer, uint32_t startBlock, uint32_t blockCount); + +/*! + * @brief Erases groups of the card. + * + * Erase group is the smallest erase unit in MMC card. The erase range is [startGroup, endGroup]. + * + * @param card Card descriptor. + * @param startGroup Start group number. + * @param endGroup End group number. + * @retval kStatus_InvalidArgument Invalid argument. + * @retval kStatus_SDMMC_WaitWriteCompleteFailed Send status failed. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_Success Operate successfully. + */ +status_t MMC_EraseGroups(mmc_card_t *card, uint32_t startGroup, uint32_t endGroup); + +/*! + * @brief Selects the partition to access. + * + * @param card Card descriptor. + * @param partitionNumber The partition number. + * @retval kStatus_SDMMC_ConfigureExtendedCsdFailed Configure EXT_CSD failed. + * @retval kStatus_Success Operate successfully. + */ +status_t MMC_SelectPartition(mmc_card_t *card, mmc_access_partition_t partitionNumber); + +/*! + * @brief Configures the boot activity of the card. + * + * @param card Card descriptor. + * @param config Boot configuration structure. + * @retval kStatus_SDMMC_NotSupportYet Not support now. + * @retval kStatus_SDMMC_ConfigureExtendedCsdFailed Configure EXT_CSD failed. + * @retval kStatus_SDMMC_ConfigureBootFailed Configure boot failed. + * @retval kStatus_Success Operate successfully. + */ +status_t MMC_SetBootConfig(mmc_card_t *card, const mmc_boot_config_t *config); + +/*! + * @brief MMC card start boot. + * + * @param card Card descriptor. + * @param mmcConfig mmc Boot configuration structure. + * @param buffer address to recieve data. + * @param hostConfig host boot configurations. + * @retval kStatus_Fail fail. + * @retval kStatus_SDMMC_TransferFailed transfer fail. + * @retval kStatus_SDMMC_GoIdleFailed reset card fail. + * @retval kStatus_Success Operate successfully. + */ +status_t MMC_StartBoot(mmc_card_t *card, + const mmc_boot_config_t *mmcConfig, + uint8_t *buffer, + SDMMCHOST_BOOT_CONFIG *hostConfig); + +/*! + * @brief MMC card set boot configuration write protect. + * + * @param card Card descriptor. + * @param wp write protect value. + */ +status_t MMC_SetBootConfigWP(mmc_card_t *card, uint8_t wp); + +/*! + * @brief MMC card continous read boot data. + * + * @param card Card descriptor. + * @param buffer buffer address. + * @param hostConfig host boot configurations. + */ +status_t MMC_ReadBootData(mmc_card_t *card, uint8_t *buffer, SDMMCHOST_BOOT_CONFIG *hostConfig); + +/*! + * @brief MMC card stop boot mode. + * + * @param card Card descriptor. + * @param bootMode boot mode. + */ +status_t MMC_StopBoot(mmc_card_t *card, uint32_t bootMode); + +/*! + * @brief MMC card set boot partition write protect. + * + * @param card Card descriptor. + * @param bootPartitionWP boot partition write protect value. + */ +status_t MMC_SetBootPartitionWP(mmc_card_t *card, mmc_boot_partition_wp_t bootPartitionWP); + +/* @} */ +#if defined(__cplusplus) +} +#endif +/*! @} */ +#endif /* _FSL_MMC_H_*/ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/inc/fsl_sd.h b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/inc/fsl_sd.h new file mode 100644 index 000000000..16077d769 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/inc/fsl_sd.h @@ -0,0 +1,315 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_SD_H_ +#define _FSL_SD_H_ + +#include "fsl_sdmmc_common.h" +/*! + * @addtogroup SDCARD + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief SD card flags */ +enum _sd_card_flag +{ + kSD_SupportHighCapacityFlag = (1U << 1U), /*!< Support high capacity */ + kSD_Support4BitWidthFlag = (1U << 2U), /*!< Support 4-bit data width */ + kSD_SupportSdhcFlag = (1U << 3U), /*!< Card is SDHC */ + kSD_SupportSdxcFlag = (1U << 4U), /*!< Card is SDXC */ + kSD_SupportVoltage180v = (1U << 5U), /*!< card support 1.8v voltage*/ + kSD_SupportSetBlockCountCmd = (1U << 6U), /*!< card support cmd23 flag*/ + kSD_SupportSpeedClassControlCmd = (1U << 7U), /*!< card support speed class control flag */ +}; + +/*! + * @brief SD card state + * + * Define the card structure including the necessary fields to identify and describe the card. + */ +typedef struct _sd_card +{ + SDMMCHOST_CONFIG host; /*!< Host information */ + + sdcard_usr_param_t usrParam; /*!< user parameter */ + bool isHostReady; /*!< use this flag to indicate if need host re-init or not*/ + bool noInteralAlign; /*!< use this flag to disable sdmmc align. If disable, sdmmc will not make sure the + data buffer address is word align, otherwise all the transfer are align to low level driver */ + uint32_t busClock_Hz; /*!< SD bus clock frequency united in Hz */ + uint32_t relativeAddress; /*!< Relative address of the card */ + uint32_t version; /*!< Card version */ + uint32_t flags; /*!< Flags in _sd_card_flag */ + uint32_t rawCid[4U]; /*!< Raw CID content */ + uint32_t rawCsd[4U]; /*!< Raw CSD content */ + uint32_t rawScr[2U]; /*!< Raw CSD content */ + uint32_t ocr; /*!< Raw OCR content */ + sd_cid_t cid; /*!< CID */ + sd_csd_t csd; /*!< CSD */ + sd_scr_t scr; /*!< SCR */ + sd_status_t stat; /*!< sd 512 bit status */ + uint32_t blockCount; /*!< Card total block number */ + uint32_t blockSize; /*!< Card block size */ + sd_timing_mode_t currentTiming; /*!< current timing mode */ + sd_driver_strength_t driverStrength; /*!< driver strength */ + sd_max_current_t maxCurrent; /*!< card current limit */ + sdmmc_operation_voltage_t operationVoltage; /*!< card operation voltage */ +} sd_card_t; + +/************************************************************************************************* + * API + ************************************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name SDCARD Function + * @{ + */ + +/*! + * @brief Initializes the card on a specific host controller. + * @deprecated Do not use this function. It has been superceded by @ref SD_HostInit,SD_CardInit. + + * This function initializes the card on a specific host controller, it is consist of + * host init, card detect, card init function, however user can ignore this high level function, + * instead of use the low level function, such as SD_CardInit, SD_HostInit, SD_CardDetect. + * + * @param card Card descriptor. + * @retval kStatus_SDMMC_HostNotReady host is not ready. + * @retval kStatus_SDMMC_GoIdleFailed Go idle failed. + * @retval kStatus_SDMMC_NotSupportYet Card not support. + * @retval kStatus_SDMMC_SendOperationConditionFailed Send operation condition failed. + * @retval kStatus_SDMMC_AllSendCidFailed Send CID failed. + * @retval kStatus_SDMMC_SendRelativeAddressFailed Send relative address failed. + * @retval kStatus_SDMMC_SendCsdFailed Send CSD failed. + * @retval kStatus_SDMMC_SelectCardFailed Send SELECT_CARD command failed. + * @retval kStatus_SDMMC_SendScrFailed Send SCR failed. + * @retval kStatus_SDMMC_SetBusWidthFailed Set bus width failed. + * @retval kStatus_SDMMC_SwitchHighSpeedFailed Switch high speed failed. + * @retval kStatus_SDMMC_SetCardBlockSizeFailed Set card block size failed. + * @retval kStatus_Success Operate successfully. + */ +status_t SD_Init(sd_card_t *card); + +/*! + * @brief Deinitializes the card. + * @deprecated Do not use this function. It has been superceded by @ref SD_HostDeinit,SD_CardDeinit. + * This function deinitializes the specific card and host. + * + * @param card Card descriptor. + */ +void SD_Deinit(sd_card_t *card); + +/*! + * @brief Initializes the card. + * + * This function initializes the card only, make sure the host is ready when call this function, + * otherwise it will return kStatus_SDMMC_HostNotReady. + * + * @param card Card descriptor. + * @retval kStatus_SDMMC_HostNotReady host is not ready. + * @retval kStatus_SDMMC_GoIdleFailed Go idle failed. + * @retval kStatus_SDMMC_NotSupportYet Card not support. + * @retval kStatus_SDMMC_SendOperationConditionFailed Send operation condition failed. + * @retval kStatus_SDMMC_AllSendCidFailed Send CID failed. + * @retval kStatus_SDMMC_SendRelativeAddressFailed Send relative address failed. + * @retval kStatus_SDMMC_SendCsdFailed Send CSD failed. + * @retval kStatus_SDMMC_SelectCardFailed Send SELECT_CARD command failed. + * @retval kStatus_SDMMC_SendScrFailed Send SCR failed. + * @retval kStatus_SDMMC_SetBusWidthFailed Set bus width failed. + * @retval kStatus_SDMMC_SwitchHighSpeedFailed Switch high speed failed. + * @retval kStatus_SDMMC_SetCardBlockSizeFailed Set card block size failed. + * @retval kStatus_Success Operate successfully. + */ +status_t SD_CardInit(sd_card_t *card); + +/*! + * @brief Deinitializes the card. + * + * This function deinitializes the specific card. + * + * @param card Card descriptor. + */ +void SD_CardDeinit(sd_card_t *card); + +/*! + * @brief initialize the host. + * + * This function deinitializes the specific host. + * + * @param card Card descriptor. + */ +status_t SD_HostInit(sd_card_t *card); + +/*! + * @brief Deinitializes the host. + * + * This function deinitializes the host. + * + * @param card Card descriptor. + */ +void SD_HostDeinit(sd_card_t *card); + +/*! + * @brief reset the host. + * + * This function reset the specific host. + * + * @param host host descriptor. + */ +void SD_HostReset(SDMMCHOST_CONFIG *host); + +/*! + * @brief power on card. + * + * The power on operation depend on host or the user define power on function. + * @param base host base address. + * @param pwr user define power control configuration + */ +void SD_PowerOnCard(SDMMCHOST_TYPE *base, const sdmmchost_pwr_card_t *pwr); + +/*! + * @brief power off card. + * + * The power off operation depend on host or the user define power on function. + * @param base host base address. + * @param pwr user define power control configuration + */ +void SD_PowerOffCard(SDMMCHOST_TYPE *base, const sdmmchost_pwr_card_t *pwr); + +/*! + * @brief sd wait card detect function. + * + * Detect card through GPIO, CD, DATA3. + * + * @param card card descriptor. + * @param card detect configuration + * @param waitCardStatus wait card detect status + */ +status_t SD_WaitCardDetectStatus(SDMMCHOST_TYPE *hostBase, const sdmmchost_detect_card_t *cd, bool waitCardStatus); + +/*! + * @brief sd card present check function. + * + * @param card card descriptor. + */ +bool SD_IsCardPresent(sd_card_t *card); + +/*! + * @brief Checks whether the card is write-protected. + * + * This function checks if the card is write-protected via the CSD register. + * + * @param card The specific card. + * @retval true Card is read only. + * @retval false Card isn't read only. + */ +bool SD_CheckReadOnly(sd_card_t *card); + +/*! + * @brief Send SELECT_CARD command to set the card to be transfer state or not. + * + * @param card Card descriptor. + * @param isSelected True to set the card into transfer state, false to disselect. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_Success Operate successfully. + */ +status_t SD_SelectCard(sd_card_t *card, bool isSelected); + +/*! + * @brief Send ACMD13 to get the card current status. + * + * @param card Card descriptor. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_SDMMC_SendApplicationCommandFailed send application command failed. + * @retval kStatus_Success Operate successfully. + */ +status_t SD_ReadStatus(sd_card_t *card); + +/*! + * @brief Reads blocks from the specific card. + * + * This function reads blocks from the specific card with default block size defined by the + * SDHC_CARD_DEFAULT_BLOCK_SIZE. + * + * @param card Card descriptor. + * @param buffer The buffer to save the data read from card. + * @param startBlock The start block index. + * @param blockCount The number of blocks to read. + * @retval kStatus_InvalidArgument Invalid argument. + * @retval kStatus_SDMMC_CardNotSupport Card not support. + * @retval kStatus_SDMMC_NotSupportYet Not support now. + * @retval kStatus_SDMMC_WaitWriteCompleteFailed Send status failed. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_SDMMC_StopTransmissionFailed Stop transmission failed. + * @retval kStatus_Success Operate successfully. + */ +status_t SD_ReadBlocks(sd_card_t *card, uint8_t *buffer, uint32_t startBlock, uint32_t blockCount); + +/*! + * @brief Writes blocks of data to the specific card. + * + * This function writes blocks to the specific card with default block size 512 bytes. + * + * @param card Card descriptor. + * @param buffer The buffer holding the data to be written to the card. + * @param startBlock The start block index. + * @param blockCount The number of blocks to write. + * @retval kStatus_InvalidArgument Invalid argument. + * @retval kStatus_SDMMC_NotSupportYet Not support now. + * @retval kStatus_SDMMC_CardNotSupport Card not support. + * @retval kStatus_SDMMC_WaitWriteCompleteFailed Send status failed. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_SDMMC_StopTransmissionFailed Stop transmission failed. + * @retval kStatus_Success Operate successfully. + */ +status_t SD_WriteBlocks(sd_card_t *card, const uint8_t *buffer, uint32_t startBlock, uint32_t blockCount); + +/*! + * @brief Erases blocks of the specific card. + * + * This function erases blocks of the specific card with default block size 512 bytes. + * + * @param card Card descriptor. + * @param startBlock The start block index. + * @param blockCount The number of blocks to erase. + * @retval kStatus_InvalidArgument Invalid argument. + * @retval kStatus_SDMMC_WaitWriteCompleteFailed Send status failed. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_SDMMC_WaitWriteCompleteFailed Send status failed. + * @retval kStatus_Success Operate successfully. + */ +status_t SD_EraseBlocks(sd_card_t *card, uint32_t startBlock, uint32_t blockCount); + +/*! + * @brief select card driver strength + * select card driver strength + * @param card Card descriptor. + * @param driverStrength Driver strength + */ +status_t SD_SetDriverStrength(sd_card_t *card, sd_driver_strength_t driverStrength); + +/*! + * @brief select max current + * select max operation current + * @param card Card descriptor. + * @param maxCurrent Max current + */ +status_t SD_SetMaxCurrent(sd_card_t *card, sd_max_current_t maxCurrent); + +/* @} */ + +#if defined(__cplusplus) +} +#endif +/*! @} */ +#endif /* _FSL_SD_H_*/ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/inc/fsl_sdio.h b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/inc/fsl_sdio.h new file mode 100644 index 000000000..b740a3d7c --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/inc/fsl_sdio.h @@ -0,0 +1,507 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_SDIO_H_ +#define _FSL_SDIO_H_ + +#include "fsl_sdmmc_common.h" + +/*! + * @addtogroup SDIOCARD + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief Middleware version. */ +#define FSL_SDIO_DRIVER_VERSION (MAKE_VERSION(2U, 2U, 11U)) /*2.2.11*/ + +/*!@brief sdio device support maximum IO number */ +#ifndef FSL_SDIO_MAX_IO_NUMS +#define FSL_SDIO_MAX_IO_NUMS (7U) +#endif +/*!@brief sdio card descriptor */ +typedef struct _sdio_card sdio_card_t; +/*!@brief sdio io handler */ +typedef void (*sdio_io_irq_handler_t)(sdio_card_t *card, uint32_t func); +/*! @brief sdio io read/write direction */ +typedef enum _sdio_io_direction +{ + kSDIO_IORead = 0U, /*!< io read */ + kSDIO_IOWrite = 1U, /*!< io write */ +} sdio_io_direction_t; + +/*! + * @brief SDIO card state + * + * Define the card structure including the necessary fields to identify and describe the card. + */ +struct _sdio_card +{ + SDMMCHOST_CONFIG host; /*!< Host information */ + sdiocard_usr_param_t usrParam; /*!< user parameter */ + bool noInternalAlign; /*!< use this flag to disable sdmmc align. If disable, sdmmc will not make sure the + data buffer address is word align, otherwise all the transfer are align to low level driver */ + bool isHostReady; /*!< use this flag to indicate if need host re-init or not*/ + bool memPresentFlag; /*!< indicate if memory present */ + + uint32_t busClock_Hz; /*!< SD bus clock frequency united in Hz */ + uint32_t relativeAddress; /*!< Relative address of the card */ + uint8_t sdVersion; /*!< SD version */ + sd_timing_mode_t currentTiming; /*!< current timing mode */ + sd_driver_strength_t driverStrength; /*!< driver strength */ + sd_max_current_t maxCurrent; /*!< card current limit */ + sdmmc_operation_voltage_t operationVoltage; /*!< card operation voltage */ + + uint8_t sdioVersion; /*!< SDIO version */ + uint8_t cccrVersioin; /*!< CCCR version */ + uint8_t ioTotalNumber; /*!< total number of IO function */ + uint32_t cccrflags; /*!< Flags in _sd_card_flag */ + uint32_t io0blockSize; /*!< record the io0 block size*/ + uint32_t ocr; /*!< Raw OCR content, only 24bit avalible for SDIO card */ + uint32_t commonCISPointer; /*!< point to common CIS */ + sdio_common_cis_t commonCIS; /*!< CIS table */ + + /* io registers/IRQ handler */ + sdio_fbr_t ioFBR[FSL_SDIO_MAX_IO_NUMS]; /*!< FBR table */ + sdio_func_cis_t funcCIS[FSL_SDIO_MAX_IO_NUMS]; /*!< function CIS table*/ + sdio_io_irq_handler_t ioIRQHandler[FSL_SDIO_MAX_IO_NUMS]; /*!< io IRQ handler */ + uint8_t ioIntIndex; /*!< used to record current enabled io interrupt index */ + uint8_t ioIntNums; /*!< used to record total enabled io interrupt numbers */ +}; + +/************************************************************************************************* + * API + ************************************************************************************************/ +#if defined(__cplusplus) +extern "C" +{ +#endif +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief SDIO card init function + * + * @param card Card descriptor. + * @retval kStatus_SDMMC_GoIdleFailed + * @retval kStatus_SDMMC_HandShakeOperationConditionFailed + * @retval kStatus_SDMMC_SDIO_InvalidCard + * @retval kStatus_SDMMC_SDIO_InvalidVoltage + * @retval kStatus_SDMMC_SendRelativeAddressFailed + * @retval kStatus_SDMMC_SelectCardFailed + * @retval kStatus_SDMMC_SDIO_SwitchHighSpeedFail + * @retval kStatus_SDMMC_SDIO_ReadCISFail + * @retval kStatus_SDMMC_TransferFailed + * @retval kStatus_Success + */ +status_t SDIO_Init(sdio_card_t *card); + +/*! + * @brief SDIO card deinit, include card and host deinit. + * + * @param card Card descriptor. + */ +void SDIO_Deinit(sdio_card_t *card); + +/*! + * @brief Initializes the card. + * + * This function initializes the card only, make sure the host is ready when call this function, + * otherwise it will return kStatus_SDMMC_HostNotReady. + * + * @param card Card descriptor. + * @retval kStatus_SDMMC_HostNotReady host is not ready. + * @retval kStatus_SDMMC_GoIdleFailed Go idle failed. + * @retval kStatus_SDMMC_NotSupportYet Card not support. + * @retval kStatus_SDMMC_SendOperationConditionFailed Send operation condition failed. + * @retval kStatus_SDMMC_AllSendCidFailed Send CID failed. + * @retval kStatus_SDMMC_SendRelativeAddressFailed Send relative address failed. + * @retval kStatus_SDMMC_SendCsdFailed Send CSD failed. + * @retval kStatus_SDMMC_SelectCardFailed Send SELECT_CARD command failed. + * @retval kStatus_SDMMC_SendScrFailed Send SCR failed. + * @retval kStatus_SDMMC_SetBusWidthFailed Set bus width failed. + * @retval kStatus_SDMMC_SwitchHighSpeedFailed Switch high speed failed. + * @retval kStatus_SDMMC_SetCardBlockSizeFailed Set card block size failed. + * @retval kStatus_Success Operate successfully. + */ +status_t SDIO_CardInit(sdio_card_t *card); + +/*! + * @brief Deinitializes the card. + * + * This function deinitializes the specific card. + * + * @param card Card descriptor. + */ +void SDIO_CardDeinit(sdio_card_t *card); + +/*! + * @brief initialize the host. + * + * This function deinitializes the specific host. + * + * @param card Card descriptor. + */ +status_t SDIO_HostInit(sdio_card_t *card); + +/*! + * @brief Deinitializes the host. + * + * This function deinitializes the host. + * + * @param card Card descriptor. + */ +void SDIO_HostDeinit(sdio_card_t *card); + +/*! + * @brief reset the host. + * + * This function reset the specific host. + * + * @param host host descriptor. + */ +void SDIO_HostReset(SDMMCHOST_CONFIG *host); + +/*! + * @brief power on card. + * + * The power on operation depend on host or the user define power on function. + * @param base host base address. + * @param pwr user define power control configuration + */ +void SDIO_PowerOnCard(SDMMCHOST_TYPE *base, const sdmmchost_pwr_card_t *pwr); + +/*! + * @brief power on card. + * + * The power off operation depend on host or the user define power on function. + * @param base host base address. + * @param pwr user define power control configuration + */ +void SDIO_PowerOffCard(SDMMCHOST_TYPE *base, const sdmmchost_pwr_card_t *pwr); + +/*! + * @brief set SDIO card to inactive state + * + * @param card Card descriptor. + * @retval kStatus_SDMMC_TransferFailed + * @retval kStatus_Success + */ +status_t SDIO_CardInActive(sdio_card_t *card); + +/*! + * @brief get SDIO card capability + * + * @param card Card descriptor. + * @param function IO number + * @retval kStatus_SDMMC_TransferFailed + * @retval kStatus_Success + */ +status_t SDIO_GetCardCapability(sdio_card_t *card, sdio_func_num_t func); + +/*! + * @brief set SDIO card block size + * + * @param card Card descriptor. + * @param function io number + * @param block size + * @retval kStatus_SDMMC_SetCardBlockSizeFailed + * @retval kStatus_SDMMC_SDIO_InvalidArgument + * @retval kStatus_Success + */ +status_t SDIO_SetBlockSize(sdio_card_t *card, sdio_func_num_t func, uint32_t blockSize); + +/*! + * @brief set SDIO card reset + * + * @param card Card descriptor. + * @retval kStatus_SDMMC_TransferFailed + * @retval kStatus_Success + */ +status_t SDIO_CardReset(sdio_card_t *card); + +/*! + * @brief set SDIO card data bus width + * + * @param card Card descriptor. + * @param data bus width + * @retval kStatus_SDMMC_TransferFailed + * @retval kStatus_Success + */ +status_t SDIO_SetDataBusWidth(sdio_card_t *card, sdio_bus_width_t busWidth); + +/*! + * @brief switch the card to high speed + * + * @param card Card descriptor. + * @retval kStatus_SDMMC_TransferFailed + * @retval kStatus_SDMMC_SDIO_SwitchHighSpeedFail + * @retval kStatus_Success + */ +status_t SDIO_SwitchToHighSpeed(sdio_card_t *card); + +/*! + * @brief read SDIO card CIS for each function + * + * @param card Card descriptor. + * @param function io number + * @param tuple code list + * @param tuple code number + * @retval kStatus_SDMMC_SDIO_ReadCISFail + * @retval kStatus_SDMMC_TransferFailed + * @retval kStatus_Success + */ +status_t SDIO_ReadCIS(sdio_card_t *card, sdio_func_num_t func, const uint32_t *tupleList, uint32_t tupleNum); + +/*! + * @brief sdio wait card detect function. + * + * Detect card through GPIO, CD, DATA3. + * + * @param card card descriptor. + * @param card detect configuration + * @param waitCardStatus wait card detect status + */ +status_t SDIO_WaitCardDetectStatus(SDMMCHOST_TYPE *hostBase, + const sdmmchost_detect_card_t *cd, + bool waitCardStatus); + +/*! + * @brief sdio card present check function. + * + * @param card card descriptor. + */ +bool SDIO_IsCardPresent(sdio_card_t *card); + +/* @} */ + +/*! + * @name IO operations + * @{ + */ + +/*! + * @brief IO direct write transfer function + * + * @param card Card descriptor. + * @param function IO numner + * @param register address + * @param the data pinter to write + * @param raw flag, indicate read after write or write only + * @retval kStatus_SDMMC_TransferFailed + * @retval kStatus_Success + */ +status_t SDIO_IO_Write_Direct(sdio_card_t *card, sdio_func_num_t func, uint32_t regAddr, uint8_t *data, bool raw); + +/*! + * @brief IO direct read transfer function + * + * @param card Card descriptor. + * @param function IO number + * @param register address + * @param data pointer to read + * @retval kStatus_SDMMC_TransferFailed + * @retval kStatus_Success + */ +status_t SDIO_IO_Read_Direct(sdio_card_t *card, sdio_func_num_t func, uint32_t regAddr, uint8_t *data); + +/*! + * @brief IO direct read/write transfer function + * + * @param card Card descriptor. + * @param direction io access direction, please reference sdio_io_direction_t. + * @param function IO number + * @param register address + * @param dataIn data to write + * @param dataOut data pointer for readback data, support both for read and write, when application want readback + * the data after write command, dataOut should not be NULL. + * @retval kStatus_SDMMC_TransferFailed + * @retval kStatus_Success + */ + +status_t SDIO_IO_RW_Direct(sdio_card_t *card, + sdio_io_direction_t direction, + sdio_func_num_t func, + uint32_t regAddr, + uint8_t dataIn, + uint8_t *dataOut); + +/*! + * @brief IO extended write transfer function + * + * @param card Card descriptor. + * @param function IO number + * @param register address + * @param data buffer to write + * @param data count + * @param write flags + * @retval kStatus_SDMMC_TransferFailed + * @retval kStatus_SDMMC_SDIO_InvalidArgument + * @retval kStatus_Success + */ +status_t SDIO_IO_Write_Extended( + sdio_card_t *card, sdio_func_num_t func, uint32_t regAddr, uint8_t *buffer, uint32_t count, uint32_t flags); +/*! + * @brief IO extended read transfer function + * + * @param card Card descriptor. + * @param function IO number + * @param register address + * @param data buffer to read + * @param data count + * @param write flags + * @retval kStatus_SDMMC_TransferFailed + * @retval kStatus_SDMMC_SDIO_InvalidArgument + * @retval kStatus_Success + */ +status_t SDIO_IO_Read_Extended( + sdio_card_t *card, sdio_func_num_t func, uint32_t regAddr, uint8_t *buffer, uint32_t count, uint32_t flags); +/*! + * @brief enable IO interrupt + * + * @param card Card descriptor. + * @param function IO number + * @param enable/disable flag + * @retval kStatus_SDMMC_TransferFailed + * @retval kStatus_Success + */ +status_t SDIO_EnableIOInterrupt(sdio_card_t *card, sdio_func_num_t func, bool enable); + +/*! + * @brief enable IO and wait IO ready + * + * @param card Card descriptor. + * @param function IO number + * @param enable/disable flag + * @retval kStatus_SDMMC_TransferFailed + * @retval kStatus_Success + */ +status_t SDIO_EnableIO(sdio_card_t *card, sdio_func_num_t func, bool enable); + +/*! + * @brief select IO + * + * @param card Card descriptor. + * @param function IO number + * @retval kStatus_SDMMC_TransferFailed + * @retval kStatus_Success + */ +status_t SDIO_SelectIO(sdio_card_t *card, sdio_func_num_t func); + +/*! + * @brief Abort IO transfer + * + * @param card Card descriptor. + * @param function IO number + * @retval kStatus_SDMMC_TransferFailed + * @retval kStatus_Success + */ +status_t SDIO_AbortIO(sdio_card_t *card, sdio_func_num_t func); + +/*! + * @brief Set driver strength. + * + * @param card Card descriptor. + * @param driverStrength target driver strength. + * @retval kStatus_SDMMC_TransferFailed + * @retval kStatus_Success + */ +status_t SDIO_SetDriverStrength(sdio_card_t *card, sd_driver_strength_t driverStrength); + +/*! + * @brief Enable/Disable Async interrupt. + * + * @param card Card descriptor. + * @param func function io number. + * @param enable true is enable, false is disable. + * @retval kStatus_SDMMC_TransferFailed + * @retval kStatus_Success + */ +status_t SDIO_EnableAsyncInterrupt(sdio_card_t *card, bool enable); + +/*! + * @brief Get pending interrupt. + * + * @param card Card descriptor. + * @param pendingInt pointer store pending interrupt + * @retval kStatus_SDMMC_TransferFailed + * @retval kStatus_Success + */ +status_t SDIO_GetPendingInterrupt(sdio_card_t *card, uint8_t *pendingInt); + +/*! + * @brief sdio card io transfer function. + * This function can be used for trnansfer direct/extend command. + * Please pay attention to the non-align data buffer address transfer, + * if data buffer address can not meet host controller internal DMA requirement, sdio driver will try to use + internal align buffer if data size is not bigger than internal buffer size, + * Align address transfer always can get a better performance, so if application want sdio driver make sure buffer + address align, + * please redefine the SDMMC_GLOBAL_BUFFER_SIZE macro to a value which is big enough for your application. + * + * @param card card descriptor. + * @param cmd command to transfer + * @param argument argument to transfer + * @param blockSize used for block mode. + * @param txData tx buffer pointer or NULL + * @param rxData rx buffer pointer or NULL + * @param dataSize transfer data size + * @param response reponse pointer, if application want read response back, please set it to a NON-NULL pointer. + + */ +status_t SDIO_IO_Transfer(sdio_card_t *card, + sdio_command_t cmd, + uint32_t argument, + uint32_t blockSize, + uint8_t *txData, + uint8_t *rxData, + uint16_t dataSize, + uint32_t *response); + +/*! + * @brief sdio set io IRQ handler. + * + * @param card card descriptor. + * @param func function io number. + * @param handler, io IRQ handler. + */ +void SDIO_SetIOIRQHandler(sdio_card_t *card, sdio_func_num_t func, sdio_io_irq_handler_t handler); + +/*! + * @brief sdio card io pending interrupt handle function. + * This function is used to handle the pending io interrupt. + * To reigster a IO IRQ handler, + * @code + * //initialization + * SDIO_EnableIOInterrupt(card, 0, true); + * SDIO_SetIOIRQHandler(card, 0, func0_handler); + * //call it in interrupt callback + * SDIO_HandlePendingIOInterrupt(card); + * @code + * To releae a IO IRQ handler, + * @code + * SDIO_EnableIOInterrupt(card, 0, false); + * SDIO_SetIOIRQHandler(card, 0, NULL); + * @code + * @param card card descriptor. + * + * @retval kStatus_SDMMC_TransferFailed + * @retval kStatus_Success + */ +status_t SDIO_HandlePendingIOInterrupt(sdio_card_t *card); + +/* @} */ + +#if defined(__cplusplus) +} +#endif +/*! @} */ +#endif /* _FSL_SDIO_H_*/ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/inc/fsl_sdmmc_common.h b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/inc/fsl_sdmmc_common.h new file mode 100644 index 000000000..11e6e9ae9 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/inc/fsl_sdmmc_common.h @@ -0,0 +1,258 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_SDMMC_COMMON_H_ +#define _FSL_SDMMC_COMMON_H_ + +#include "fsl_common.h" +#include "fsl_sdmmc_host.h" +#include "fsl_sdmmc_spec.h" +#include "stdlib.h" + +/*! + * @addtogroup CARD + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief Middleware version. */ +#define FSL_SDMMC_DRIVER_VERSION (MAKE_VERSION(2U, 2U, 11U)) /*2.2.11*/ + +/*! @brief Reverse byte sequence in uint32_t */ +#define SWAP_WORD_BYTE_SEQUENCE(x) (__REV(x)) +/*! @brief Reverse byte sequence for each half word in uint32_t */ +#define SWAP_HALF_WROD_BYTE_SEQUENCE(x) (__REV16(x)) +/*! @brief Maximum loop count to check the card operation voltage range */ +#define FSL_SDMMC_MAX_VOLTAGE_RETRIES (1000U) +/*! @brief Maximum loop count to send the cmd */ +#define FSL_SDMMC_MAX_CMD_RETRIES (10U) +/*! @brief Default block size */ +#define FSL_SDMMC_DEFAULT_BLOCK_SIZE (512U) +#ifndef SDMMC_GLOBAL_BUFFER_SIZE +/*! @brief SDMMC global data buffer size, word unit*/ +#define SDMMC_GLOBAL_BUFFER_SIZE (128U) +#endif +/*! @brief SDMMC enable software tuning */ +#define SDMMC_ENABLE_SOFTWARE_TUNING (0U) +/* Common definition for cache line size align */ +#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL +#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#if defined(FSL_FEATURE_L2DCACHE_LINESIZE_BYTE) +#define SDMMC_DATA_BUFFER_ALIGN_CACHE MAX(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE, FSL_FEATURE_L2DCACHE_LINESIZE_BYTE) +#else +#define SDMMC_DATA_BUFFER_ALIGN_CACHE FSL_FEATURE_L1DCACHE_LINESIZE_BYTE +#endif +#else +#define SDMMC_DATA_BUFFER_ALIGN_CACHE 1 +#endif +#else +#define SDMMC_DATA_BUFFER_ALIGN_CACHE 1 +#endif + +/*! @brief SD/MMC error log. */ +#if defined SDMMC_ENABLE_LOG_PRINT +#include "fsl_debug_console.h" +#define SDMMC_LOG(...) PRINTF(__VA_ARGS__) +#else +#define SDMMC_LOG(format, ...) +#endif + +/*! @brief SD/MMC card API's running status. */ +enum _sdmmc_status +{ + kStatus_SDMMC_NotSupportYet = MAKE_STATUS(kStatusGroup_SDMMC, 0U), /*!< Haven't supported */ + kStatus_SDMMC_TransferFailed = MAKE_STATUS(kStatusGroup_SDMMC, 1U), /*!< Send command failed */ + kStatus_SDMMC_SetCardBlockSizeFailed = MAKE_STATUS(kStatusGroup_SDMMC, 2U), /*!< Set block size failed */ + kStatus_SDMMC_HostNotSupport = MAKE_STATUS(kStatusGroup_SDMMC, 3U), /*!< Host doesn't support */ + kStatus_SDMMC_CardNotSupport = MAKE_STATUS(kStatusGroup_SDMMC, 4U), /*!< Card doesn't support */ + kStatus_SDMMC_AllSendCidFailed = MAKE_STATUS(kStatusGroup_SDMMC, 5U), /*!< Send CID failed */ + kStatus_SDMMC_SendRelativeAddressFailed = MAKE_STATUS(kStatusGroup_SDMMC, 6U), /*!< Send relative address failed */ + kStatus_SDMMC_SendCsdFailed = MAKE_STATUS(kStatusGroup_SDMMC, 7U), /*!< Send CSD failed */ + kStatus_SDMMC_SelectCardFailed = MAKE_STATUS(kStatusGroup_SDMMC, 8U), /*!< Select card failed */ + kStatus_SDMMC_SendScrFailed = MAKE_STATUS(kStatusGroup_SDMMC, 9U), /*!< Send SCR failed */ + kStatus_SDMMC_SetDataBusWidthFailed = MAKE_STATUS(kStatusGroup_SDMMC, 10U), /*!< Set bus width failed */ + kStatus_SDMMC_GoIdleFailed = MAKE_STATUS(kStatusGroup_SDMMC, 11U), /*!< Go idle failed */ + kStatus_SDMMC_HandShakeOperationConditionFailed = + MAKE_STATUS(kStatusGroup_SDMMC, 12U), /*!< Send Operation Condition failed */ + kStatus_SDMMC_SendApplicationCommandFailed = + MAKE_STATUS(kStatusGroup_SDMMC, 13U), /*!< Send application command failed */ + kStatus_SDMMC_SwitchFailed = MAKE_STATUS(kStatusGroup_SDMMC, 14U), /*!< Switch command failed */ + kStatus_SDMMC_StopTransmissionFailed = MAKE_STATUS(kStatusGroup_SDMMC, 15U), /*!< Stop transmission failed */ + kStatus_SDMMC_WaitWriteCompleteFailed = MAKE_STATUS(kStatusGroup_SDMMC, 16U), /*!< Wait write complete failed */ + kStatus_SDMMC_SetBlockCountFailed = MAKE_STATUS(kStatusGroup_SDMMC, 17U), /*!< Set block count failed */ + kStatus_SDMMC_SetRelativeAddressFailed = MAKE_STATUS(kStatusGroup_SDMMC, 18U), /*!< Set relative address failed */ + kStatus_SDMMC_SwitchBusTimingFailed = MAKE_STATUS(kStatusGroup_SDMMC, 19U), /*!< Switch high speed failed */ + kStatus_SDMMC_SendExtendedCsdFailed = MAKE_STATUS(kStatusGroup_SDMMC, 20U), /*!< Send EXT_CSD failed */ + kStatus_SDMMC_ConfigureBootFailed = MAKE_STATUS(kStatusGroup_SDMMC, 21U), /*!< Configure boot failed */ + kStatus_SDMMC_ConfigureExtendedCsdFailed = MAKE_STATUS(kStatusGroup_SDMMC, 22U), /*!< Configure EXT_CSD failed */ + kStatus_SDMMC_EnableHighCapacityEraseFailed = + MAKE_STATUS(kStatusGroup_SDMMC, 23U), /*!< Enable high capacity erase failed */ + kStatus_SDMMC_SendTestPatternFailed = MAKE_STATUS(kStatusGroup_SDMMC, 24U), /*!< Send test pattern failed */ + kStatus_SDMMC_ReceiveTestPatternFailed = MAKE_STATUS(kStatusGroup_SDMMC, 25U), /*!< Receive test pattern failed */ + kStatus_SDMMC_SDIO_ResponseError = MAKE_STATUS(kStatusGroup_SDMMC, 26U), /*!< sdio response error */ + kStatus_SDMMC_SDIO_InvalidArgument = + MAKE_STATUS(kStatusGroup_SDMMC, 27U), /*!< sdio invalid argument response error */ + kStatus_SDMMC_SDIO_SendOperationConditionFail = + MAKE_STATUS(kStatusGroup_SDMMC, 28U), /*!< sdio send operation condition fail */ + kStatus_SDMMC_InvalidVoltage = MAKE_STATUS(kStatusGroup_SDMMC, 29U), /*!< invaild voltage */ + kStatus_SDMMC_SDIO_SwitchHighSpeedFail = MAKE_STATUS(kStatusGroup_SDMMC, 30U), /*!< switch to high speed fail */ + kStatus_SDMMC_SDIO_ReadCISFail = MAKE_STATUS(kStatusGroup_SDMMC, 31U), /*!< read CIS fail */ + kStatus_SDMMC_SDIO_InvalidCard = MAKE_STATUS(kStatusGroup_SDMMC, 32U), /*!< invaild SDIO card */ + kStatus_SDMMC_TuningFail = MAKE_STATUS(kStatusGroup_SDMMC, 33U), /*!< tuning fail */ + + kStatus_SDMMC_SwitchVoltageFail = MAKE_STATUS(kStatusGroup_SDMMC, 34U), /*!< switch voltage fail*/ + kStatus_SDMMC_SwitchVoltage18VFail33VSuccess = MAKE_STATUS(kStatusGroup_SDMMC, 35U), /*!< switch voltage fail*/ + + kStatus_SDMMC_ReTuningRequest = MAKE_STATUS(kStatusGroup_SDMMC, 36U), /*!< retuning request */ + kStatus_SDMMC_SetDriverStrengthFail = MAKE_STATUS(kStatusGroup_SDMMC, 37U), /*!< set driver strength fail */ + kStatus_SDMMC_SetPowerClassFail = MAKE_STATUS(kStatusGroup_SDMMC, 38U), /*!< set power class fail */ + kStatus_SDMMC_HostNotReady = MAKE_STATUS(kStatusGroup_SDMMC, 39U), /*!< host controller not ready */ + kStatus_SDMMC_CardDetectFailed = MAKE_STATUS(kStatusGroup_SDMMC, 40U), /*!< card detect failed */ + kStatus_SDMMC_AuSizeNotSetProperly = MAKE_STATUS(kStatusGroup_SDMMC, 41U), /*!< AU size not set properly */ + +}; + +/*! @brief card operation voltage */ +typedef enum _sdmmc_operation_voltage +{ + kCARD_OperationVoltageNone = 0U, /*!< indicate current voltage setting is not setting by suser*/ + kCARD_OperationVoltage330V = 1U, /*!< card operation voltage around 3.3v */ + kCARD_OperationVoltage300V = 2U, /*!< card operation voltage around 3.0v */ + kCARD_OperationVoltage180V = 3U, /*!< card operation voltage around 1.8v */ +} sdmmc_operation_voltage_t; + +/************************************************************************************************* + * API + ************************************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif +/*! + * @name common function + * @{ + */ + +/*! + * @brief Selects the card to put it into transfer state. + * + * @param base SDMMCHOST peripheral base address. + * @param transfer SDMMCHOST transfer function. + * @param relativeAddress Relative address. + * @param isSelected True to put card into transfer state. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_Success Operate successfully. + */ +status_t SDMMC_SelectCard(SDMMCHOST_TYPE *base, + SDMMCHOST_TRANSFER_FUNCTION transfer, + uint32_t relativeAddress, + bool isSelected); + +/*! + * @brief Sends an application command. + * + * @param base SDMMCHOST peripheral base address. + * @param transfer SDMMCHOST transfer function. + * @param relativeAddress Card relative address. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_SDMMC_CardNotSupport Card doesn't support. + * @retval kStatus_Success Operate successfully. + */ +status_t SDMMC_SendApplicationCommand(SDMMCHOST_TYPE *base, + SDMMCHOST_TRANSFER_FUNCTION transfer, + uint32_t relativeAddress); + +/*! + * @brief Sets the block count. + * + * @param base SDMMCHOST peripheral base address. + * @param transfer SDMMCHOST transfer function. + * @param blockCount Block count. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_Success Operate successfully. + */ +status_t SDMMC_SetBlockCount(SDMMCHOST_TYPE *base, SDMMCHOST_TRANSFER_FUNCTION transfer, uint32_t blockCount); + +/*! + * @brief Sets the card to be idle state. + * + * @param base SDMMCHOST peripheral base address. + * @param transfer SDMMCHOST transfer function. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_Success Operate successfully. + */ +status_t SDMMC_GoIdle(SDMMCHOST_TYPE *base, SDMMCHOST_TRANSFER_FUNCTION transfer); + +/*! + * @brief Sets data block size. + * + * @param base SDMMCHOST peripheral base address. + * @param transfer SDMMCHOST transfer function. + * @param blockSize Block size. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_Success Operate successfully. + */ +status_t SDMMC_SetBlockSize(SDMMCHOST_TYPE *base, SDMMCHOST_TRANSFER_FUNCTION transfer, uint32_t blockSize); + +/*! + * @brief Sets card to inactive status + * + * @param base SDMMCHOST peripheral base address. + * @param transfer SDMMCHOST transfer function. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_Success Operate successfully. + */ +status_t SDMMC_SetCardInactive(SDMMCHOST_TYPE *base, SDMMCHOST_TRANSFER_FUNCTION transfer); + +/*! + * @brief provide a simple delay function for sdmmc + * + * @param num Delay num*10000. + */ +void SDMMC_Delay(uint32_t num); + +/*! + * @brief provide a voltage switch function for SD/SDIO card + * @deprecated Do not use this function, it has been superceded by SDMMC_SwitchToVoltage. + * @param base SDMMCHOST peripheral base address. + * @param transfer SDMMCHOST transfer function. + */ +status_t SDMMC_SwitchVoltage(SDMMCHOST_TYPE *base, SDMMCHOST_TRANSFER_FUNCTION transfer); + +/*! + * @brief provide a voltage switch function for SD/SDIO card + * + * @param base SDMMCHOST peripheral base address. + * @param transfer SDMMCHOST transfer function. + * @param switchVoltageFunc voltage switch function. + * @return error code. + */ + +status_t SDMMC_SwitchToVoltage(SDMMCHOST_TYPE *base, + SDMMCHOST_TRANSFER_FUNCTION transfer, + sdmmchost_card_switch_voltage_t switchVoltageFunc); +/*! + * @brief excute tuning + * + * @param base SDMMCHOST peripheral base address. + * @param transfer Host transfer function + * @param tuningCmd Tuning cmd + * @param blockSize Tuning block size + */ +status_t SDMMC_ExecuteTuning(SDMMCHOST_TYPE *base, + SDMMCHOST_TRANSFER_FUNCTION transfer, + uint32_t tuningCmd, + uint32_t blockSize); +/* @} */ + +#if defined(__cplusplus) +} +#endif +/* @} */ +#endif /* _FSL_SDMMC_COMMON_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/inc/fsl_sdmmc_host.h b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/inc/fsl_sdmmc_host.h new file mode 100644 index 000000000..0c9075def --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/inc/fsl_sdmmc_host.h @@ -0,0 +1,780 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_SDMMC_HOST_H +#define _FSL_SDMMC_HOST_H + +#include "fsl_common.h" +#include "board.h" +#if defined(FSL_FEATURE_SOC_SDHC_COUNT) && FSL_FEATURE_SOC_SDHC_COUNT > 0U +#include "fsl_sdhc.h" +#elif defined(FSL_FEATURE_SOC_SDIF_COUNT) && FSL_FEATURE_SOC_SDIF_COUNT > 0U +#include "fsl_sdif.h" +#elif defined(FSL_FEATURE_SOC_USDHC_COUNT) && FSL_FEATURE_SOC_USDHC_COUNT > 0U +#include "fsl_usdhc.h" +#endif + +/*! + * @addtogroup SDMMCHOST + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Common definition for support and not support macro */ +#define SDMMCHOST_NOT_SUPPORT 0U /*!< use this define to indicate the host not support feature*/ +#define SDMMCHOST_SUPPORT 1U /*!< use this define to indicate the host support feature*/ + +/* Common definition for board support SDR104/HS200/HS400 frequency */ +/* SDR104 mode freq */ +#if defined BOARD_SD_HOST_SUPPORT_SDR104_FREQ +#define SDMMCHOST_SUPPORT_SDR104_FREQ BOARD_SD_HOST_SUPPORT_SDR104_FREQ +#else +#define SDMMCHOST_SUPPORT_SDR104_FREQ SD_CLOCK_208MHZ +#endif +/* HS200 mode freq */ +#if defined BOARD_SD_HOST_SUPPORT_HS200_FREQ +#define SDMMCHOST_SUPPORT_HS200_FREQ BOARD_SD_HOST_SUPPORT_HS200_FREQ +#else +#define SDMMCHOST_SUPPORT_HS200_FREQ MMC_CLOCK_HS200 +#endif +/* HS400 mode freq */ +#if defined BOARD_SD_HOST_SUPPORT_HS400_FREQ +#define SDMMCHOST_SUPPORT_HS400_FREQ BOARD_SD_HOST_SUPPORT_HS400_FREQ +#else +#define SDMMCHOST_SUPPORT_HS400_FREQ MMC_CLOCK_HS400 +#endif + +/* Common definition for SDMMCHOST transfer complete timeout */ +#define SDMMCHOST_TRANSFER_COMPLETE_TIMEOUT (500U) +/* Common definition for card detect timeout */ +#define SDMMCHOST_CARD_DETECT_TIMEOUT (~0U) + +/* Common definition for IRQ */ +#if defined(__CORTEX_M) +#define SDMMCHOST_SET_IRQ_PRIORITY(id, priority) (NVIC_SetPriority(id, priority)) +#else +#define SDMMCHOST_SET_IRQ_PRIORITY(id, priority) (GIC_SetPriority(id, priority)) +#endif + +#define SDMMCHOST_ENABLE_IRQ(id) (EnableIRQ(id)) + +/*********************************************************SDHC**********************************************************/ +#if (defined(FSL_FEATURE_SOC_SDHC_COUNT) && (FSL_FEATURE_SOC_SDHC_COUNT > 0U)) + +/*define host baseaddr ,clk freq, IRQ number*/ +#define MMC_HOST_BASEADDR BOARD_SDHC_BASEADDR +#define MMC_HOST_CLK_FREQ BOARD_SDHC_CLK_FREQ +#define MMC_HOST_IRQ BOARD_SDHC_IRQ +#define SD_HOST_BASEADDR BOARD_SDHC_BASEADDR +#define SD_HOST_CLK_FREQ BOARD_SDHC_CLK_FREQ +#define SD_HOST_IRQ BOARD_SDHC_IRQ + +/* define for card bus speed/strength cnofig */ +#define CARD_BUS_FREQ_50MHZ (0U) +#define CARD_BUS_FREQ_100MHZ0 (0U) +#define CARD_BUS_FREQ_100MHZ1 (0U) +#define CARD_BUS_FREQ_200MHZ (0U) + +#define CARD_BUS_STRENGTH_0 (0U) +#define CARD_BUS_STRENGTH_1 (0U) +#define CARD_BUS_STRENGTH_2 (0U) +#define CARD_BUS_STRENGTH_3 (0U) +#define CARD_BUS_STRENGTH_4 (0U) +#define CARD_BUS_STRENGTH_5 (0U) +#define CARD_BUS_STRENGTH_6 (0U) +#define CARD_BUS_STRENGTH_7 (0U) + +#define SDMMCHOST_TYPE SDHC_Type +#define SDMMCHOST_CONFIG sdhc_host_t +#define SDMMCHOST_TRANSFER sdhc_transfer_t +#define SDMMCHOST_COMMAND sdhc_command_t +#define SDMMCHOST_DATA sdhc_data_t +#define SDMMCHOST_BUS_WIDTH_TYPE sdhc_data_bus_width_t +#define SDMMCHOST_CAPABILITY sdhc_capability_t +#define SDMMCHOST_BOOT_CONFIG sdhc_boot_config_t + +#define CARD_DATA0_STATUS_MASK (kSDHC_Data0LineLevelFlag) +#define CARD_DATA0_NOT_BUSY (kSDHC_Data0LineLevelFlag) +#define CARD_DATA1_STATUS_MASK (kSDHC_Data1LineLevelFlag) +#define CARD_DATA2_STATUS_MASK (kSDHC_Data2LineLevelFlag) +#define CARD_DATA3_STATUS_MASK (kSDHC_Data3LineLevelFlag) + +#define kSDMMCHOST_DATABUSWIDTH1BIT kSDHC_DataBusWidth1Bit /*!< 1-bit mode */ +#define kSDMMCHOST_DATABUSWIDTH4BIT kSDHC_DataBusWidth4Bit /*!< 4-bit mode */ +#define kSDMMCHOST_DATABUSWIDTH8BIT kSDHC_DataBusWidth8Bit /*!< 8-bit mode */ + +#define SDMMCHOST_STANDARD_TUNING_START (0U) /*!< standard tuning start point */ +#define SDMMCHOST_TUINIG_STEP (1U) /*!< standard tuning step */ +#define SDMMCHOST_RETUNING_TIMER_COUNT (4U) /*!< Re-tuning timer */ +#define SDMMCHOST_TUNING_DELAY_MAX (0x7FU) +#define SDMMCHOST_RETUNING_REQUEST (1U) +#define SDMMCHOST_TUNING_ERROR (2U) + +/* function pointer define */ +#define SDMMCHOST_TRANSFER_FUNCTION sdhc_transfer_function_t +#define GET_SDMMCHOST_CAPABILITY(base, capability) (SDHC_GetCapability(base, capability)) +#define GET_SDMMCHOST_STATUS(base) (SDHC_GetPresentStatusFlags(base)) +#define SDMMCHOST_SET_CARD_CLOCK(base, sourceClock_HZ, busClock_HZ) (SDHC_SetSdClock(base, sourceClock_HZ, busClock_HZ)) +#define SDMMCHOST_SET_CARD_BUS_WIDTH(base, busWidth) (SDHC_SetDataBusWidth(base, busWidth)) +#define SDMMCHOST_SEND_CARD_ACTIVE(base, timeout) (SDHC_SetCardActive(base, timeout)) +#define SDMMCHOST_SWITCH_VOLTAGE180V(base, enable18v) +#define SDMMCHOST_SWITCH_VOLTAGE120V(base, enable12v) +#define SDMMCHOST_CONFIG_IO_STRENGTH(speed, strength) +#define SDMMCHOST_EXECUTE_STANDARD_TUNING_ENABLE(base, flag) +#define SDMMCHOST_EXECUTE_STANDARD_TUNING_STATUS(base) (0U) +#define SDMMCHOST_EXECUTE_STANDARD_TUNING_RESULT(base) (1U) +#define SDMMCHOST_CONFIG_SD_IO(speed, strength) +#define SDMMCHOST_CONFIG_MMC_IO(speed, strength) +#define SDMMCHOST_ENABLE_DDR_MODE(base, flag, nibblePos) +#define SDMMCHOST_FORCE_SDCLOCK_ON(base, enable) +#define SDMMCHOST_EXECUTE_MANUAL_TUNING_ENABLE(base, flag) +#define SDMMCHOST_ADJUST_MANUAL_TUNING_DELAY(base, delay) +#define SDMMCHOST_AUTO_MANUAL_TUNING_ENABLE(base, flag) +#define SDMMCHOST_ENABLE_CARD_CLOCK(base, enable) (SDHC_EnableSdClock(base, enable)) +#define SDMMCHOST_RESET_TUNING(base, timeout) +#define SDMMCHOST_CHECK_TUNING_ERROR(base) (0U) +#define SDMMCHOST_ADJUST_TUNING_DELAY(base, delay) +#define SDMMCHOST_AUTO_STANDARD_RETUNING_TIMER(base) +#define SDMMCHOST_TRANSFER_DATA_ERROR kStatus_SDHC_TransferDataFailed +#define SDMMCHOST_TRANSFER_CMD_ERROR kStatus_SDHC_SendCommandFailed +#define SDMMCHOST_ENABLE_HS400_MODE(base, flag) +#define SDMMCHOST_RESET_STROBE_DLL(base) +#define SDMMCHOST_ENABLE_STROBE_DLL(base, flag) +#define SDMMCHOST_CONFIG_STROBE_DLL(base, delay, updateInterval) +#define SDMMCHOST_GET_STROBE_DLL_STATUS(base) +/* sd card power */ +#define SDMMCHOST_INIT_SD_POWER() +#define SDMMCHOST_ENABLE_SD_POWER(enable) +#define SDMMCHOST_SWITCH_VCC_TO_180V() +#define SDMMCHOST_SWITCH_VCC_TO_330V() +/* mmc card power */ +#define SDMMCHOST_INIT_MMC_POWER() +#define SDMMCHOST_ENABLE_MMC_POWER(enable) +#define SDMMCHOST_ENABLE_TUNING_FLAG(data) +#define SDMMCHOST_ENABLE_BOOT_FLAG(data) +#define SDMMCHOST_ENABLE_BOOT_CONTINOUS_FLAG(data) +#define SDMMCHOST_GET_HOST_CONFIG_BLOCK_SIZE(config) (0U) +#define SDMMCHOST_GET_HOST_CONFIG_BLOCK_COUNT(config) (0U) +#define SDMMCHOST_GET_HOST_CONFIG_BOOT_MODE(config) (0U) +#define SDMMCHOST_EMPTY_CMD_FLAG(command) +#define SDMMCHOST_CARD_DETECT_GPIO_INTERRUPT_HANDLER BOARD_SDHC_CD_PORT_IRQ_HANDLER +#define SDMMCHOST_CARD_DETECT_IRQ BOARD_SDHC_CD_PORT_IRQ +/* sd card detect through host CD */ +#define SDMMCHOST_CARD_DETECT_INSERT_ENABLE(base) (SDHC_EnableInterruptStatus(base, kSDHC_CardInsertionFlag)) +#define SDMMCHOST_CARD_DETECT_REMOVE_ENABLE(base) (SDHC_EnableInterruptStatus(base, kSDHC_CardRemovalFlag)) +#define SDMMCHOST_CARD_DETECT_INSERT_STATUS(base) (SDHC_GetInterruptStatusFlags(base) & kSDHC_CardInsertionFlag) +#define SDMMCHOST_CARD_DETECT_REMOVE_STATUS(base) (SDHC_GetInterruptStatusFlags(base, kSDHC_CardRemovalFlag)) +#define SDMMCHOST_CARD_DETECT_INSERT_INTERRUPT_ENABLE(base) (SDHC_EnableInterruptSignal(base, kSDHC_CardInsertionFlag)) +#define SDMMCHOST_CARD_DETECT_INSERT_INTERRUPT_DISABLE(base) \ + (SDHC_DisableInterruptSignal(base, kSDHC_CardInsertionFlag)) +#define SDMMCHOST_CARD_DETECT_REMOVE_INTERRUPT_ENABLE(base) (SDHC_EnableInterruptSignal(base, kSDHC_CardRemovalFlag)) +#define SDMMCHOST_CARD_DETECT_DATA3_ENABLE(base, flag) (SDHC_CardDetectByData3(base, flag)) +#define SDMMCHOST_ENABLE_MMC_BOOT(base, flag) +#define SDMMCHOST_SETMMCBOOTCONFIG(base, config) (SDHC_SetMmcBootConfig(base, config)) +/* define card detect pin voltage level when card inserted */ +#if defined BOARD_SDHC_CARD_INSERT_CD_LEVEL +#define SDMMCHOST_CARD_INSERT_CD_LEVEL BOARD_SDHC_CARD_INSERT_CD_LEVEL +#else +#define SDMMCHOST_CARD_INSERT_CD_LEVEL (0U) +#endif +#define SDMMCHOST_AUTO_TUNING_ENABLE(base, flag) +#define SDMMCHOST_ENABLE_SDIO_INT(base) \ + SDHC_EnableInterruptStatus(base, kSDHC_CardInterruptFlag); \ + SDHC_EnableInterruptSignal(base, kSDHC_CardInterruptFlag) +#define SDMMCHOST_DISABLE_SDIO_INT(base) \ + SDHC_DisableInterruptStatus(base, kSDHC_CardInterruptFlag); \ + SDHC_DisableInterruptSignal(base, kSDHC_CardInterruptFlag) + +/*! @brief SDHC host capability*/ +enum _host_capability +{ + kSDMMCHOST_SupportAdma = kSDHC_SupportAdmaFlag, + kSDMMCHOST_SupportHighSpeed = kSDHC_SupportHighSpeedFlag, + kSDMMCHOST_SupportDma = kSDHC_SupportDmaFlag, + kSDMMCHOST_SupportSuspendResume = kSDHC_SupportSuspendResumeFlag, + kSDMMCHOST_SupportV330 = kSDHC_SupportV330Flag, + kSDMMCHOST_SupportV300 = SDMMCHOST_NOT_SUPPORT, + kSDMMCHOST_SupportV180 = SDMMCHOST_NOT_SUPPORT, + kSDMMCHOST_SupportV120 = SDMMCHOST_NOT_SUPPORT, + kSDMMCHOST_Support4BitBusWidth = kSDHC_Support4BitFlag, + kSDMMCHOST_Support8BitBusWidth = kSDHC_Support8BitFlag, + kSDMMCHOST_SupportDDR50 = SDMMCHOST_NOT_SUPPORT, + kSDMMCHOST_SupportSDR104 = SDMMCHOST_NOT_SUPPORT, + kSDMMCHOST_SupportSDR50 = SDMMCHOST_NOT_SUPPORT, + kSDMMCHOST_SupportHS200 = SDMMCHOST_NOT_SUPPORT, + kSDMMCHOST_SupportHS400 = SDMMCHOST_NOT_SUPPORT, +}; + +/* Endian mode. */ +#define SDHC_ENDIAN_MODE kSDHC_EndianModeLittle + +/* DMA mode */ +#define SDHC_DMA_MODE kSDHC_DmaModeAdma2 +/* address align */ +#define SDMMCHOST_DMA_BUFFER_ADDR_ALIGN (SDHC_ADMA2_ADDRESS_ALIGN) + +/* Read/write watermark level. The bigger value indicates DMA has higher read/write performance. */ +#define SDHC_READ_WATERMARK_LEVEL (0x80U) +#define SDHC_WRITE_WATERMARK_LEVEL (0x80U) + +/* ADMA table length united as word. + * + * SD card driver can't support ADMA1 transfer mode currently. + * One ADMA2 table item occupy two words which can transfer maximum 0xFFFFU bytes one time. + * The more data to be transferred in one time, the bigger value of SDHC_ADMA_TABLE_WORDS need to be set. + */ +#define SDHC_ADMA_TABLE_WORDS (8U) + +/*********************************************************SDIF**********************************************************/ +#elif (defined(FSL_FEATURE_SOC_SDIF_COUNT) && (FSL_FEATURE_SOC_SDIF_COUNT > 0U)) + +/*define host baseaddr ,clk freq, IRQ number*/ +#define MMC_HOST_BASEADDR BOARD_SDIF_BASEADDR +#define MMC_HOST_CLK_FREQ BOARD_SDIF_CLK_FREQ +#define MMC_HOST_IRQ BOARD_SDIF_IRQ +#define SD_HOST_BASEADDR BOARD_SDIF_BASEADDR +#define SD_HOST_CLK_FREQ BOARD_SDIF_CLK_FREQ +#define SD_HOST_IRQ BOARD_SDIF_IRQ + +/* define for card bus speed/strength cnofig */ +#define CARD_BUS_FREQ_50MHZ (0U) +#define CARD_BUS_FREQ_100MHZ0 (0U) +#define CARD_BUS_FREQ_100MHZ1 (0U) +#define CARD_BUS_FREQ_200MHZ (0U) + +#define CARD_BUS_STRENGTH_0 (0U) +#define CARD_BUS_STRENGTH_1 (0U) +#define CARD_BUS_STRENGTH_2 (0U) +#define CARD_BUS_STRENGTH_3 (0U) +#define CARD_BUS_STRENGTH_4 (0U) +#define CARD_BUS_STRENGTH_5 (0U) +#define CARD_BUS_STRENGTH_6 (0U) +#define CARD_BUS_STRENGTH_7 (0U) + +#define SDMMCHOST_TYPE SDIF_Type +#define SDMMCHOST_CONFIG sdif_host_t +#define SDMMCHOST_TRANSFER sdif_transfer_t +#define SDMMCHOST_COMMAND sdif_command_t +#define SDMMCHOST_DATA sdif_data_t +#define SDMMCHOST_BUS_WIDTH_TYPE sdif_bus_width_t +#define SDMMCHOST_CAPABILITY sdif_capability_t +#define SDMMCHOST_BOOT_CONFIG void + +#define CARD_DATA0_STATUS_MASK SDIF_STATUS_DATA_BUSY_MASK +#define CARD_DATA0_NOT_BUSY 0U + +#define CARD_DATA1_STATUS_MASK (0U) +#define CARD_DATA2_STATUS_MASK (0U) +#define CARD_DATA3_STATUS_MASK (0U) + +#define kSDMMCHOST_DATABUSWIDTH1BIT kSDIF_Bus1BitWidth /*!< 1-bit mode */ +#define kSDMMCHOST_DATABUSWIDTH4BIT kSDIF_Bus4BitWidth /*!< 4-bit mode */ +#define kSDMMCHOST_DATABUSWIDTH8BIT kSDIF_Bus8BitWidth /*!< 8-bit mode */ + +#define SDMMCHOST_STANDARD_TUNING_START (0U) /*!< standard tuning start point */ +#define SDMMCHOST_TUINIG_STEP (1U) /*!< standard tuning step */ +#define SDMMCHOST_RETUNING_TIMER_COUNT (4U) /*!< Re-tuning timer */ +#define SDMMCHOST_TUNING_DELAY_MAX (0x7FU) +#define SDMMCHOST_RETUNING_REQUEST (1U) +#define SDMMCHOST_TUNING_ERROR (2U) +/* function pointer define */ +#define SDMMCHOST_TRANSFER_FUNCTION sdif_transfer_function_t +#define GET_SDMMCHOST_CAPABILITY(base, capability) (SDIF_GetCapability(base, capability)) +#define GET_SDMMCHOST_STATUS(base) (SDIF_GetControllerStatus(base)) +#define SDMMCHOST_SET_CARD_CLOCK(base, sourceClock_HZ, busClock_HZ) \ + (SDIF_SetCardClock(base, sourceClock_HZ, busClock_HZ)) +#define SDMMCHOST_SET_CARD_BUS_WIDTH(base, busWidth) (SDIF_SetCardBusWidth(base, busWidth)) +#define SDMMCHOST_SEND_CARD_ACTIVE(base, timeout) (SDIF_SendCardActive(base, timeout)) +#define SDMMCHOST_SWITCH_VOLTAGE180V(base, enable18v) +#define SDMMCHOST_SWITCH_VOLTAGE120V(base, enable12v) +#define SDMMCHOST_CONFIG_IO_STRENGTH(speed, strength) +#define SDMMCHOST_EXECUTE_STANDARD_TUNING_ENABLE(base, flag) +#define SDMMCHOST_EXECUTE_STANDARD_TUNING_STATUS(base) (0U) +#define SDMMCHOST_EXECUTE_STANDARD_TUNING_RESULT(base) (1U) +#define SDMMCHOST_CONFIG_SD_IO(speed, strength) +#define SDMMCHOST_CONFIG_MMC_IO(speed, strength) +#define SDMMCHOST_ENABLE_DDR_MODE(base, flag, nibblePos) +#define SDMMCHOST_FORCE_SDCLOCK_ON(base, enable) +#define SDMMCHOST_EXECUTE_MANUAL_TUNING_ENABLE(base, flag) +#define SDMMCHOST_ADJUST_MANUAL_TUNING_DELAY(base, delay) +#define SDMMCHOST_AUTO_MANUAL_TUNING_ENABLE(base, flag) +#define SDMMCHOST_ENABLE_CARD_CLOCK(base, enable) (SDIF_EnableCardClock(base, enable)) +#define SDMMCHOST_RESET_TUNING(base, timeout) +#define SDMMCHOST_CHECK_TUNING_ERROR(base) (0U) +#define SDMMCHOST_ADJUST_TUNING_DELAY(base, delay) +#define SDMMCHOST_AUTO_STANDARD_RETUNING_TIMER(base) + +#define SDMMCHOST_ENABLE_HS400_MODE(base, flag) +#define SDMMCHOST_RESET_STROBE_DLL(base) +#define SDMMCHOST_ENABLE_STROBE_DLL(base, flag) +#define SDMMCHOST_CONFIG_STROBE_DLL(base, delay, updateInterval) +#define SDMMCHOST_GET_STROBE_DLL_STATUS(base) +/* sd card power */ +#define SDMMCHOST_INIT_SD_POWER() +#define SDMMCHOST_ENABLE_SD_POWER(enable) +#define SDMMCHOST_SWITCH_VCC_TO_180V() +#define SDMMCHOST_SWITCH_VCC_TO_330V() +/* mmc card power */ +#define SDMMCHOST_INIT_MMC_POWER() +#define SDMMCHOST_ENABLE_MMC_POWER(enable) +#define SDMMCHOST_ENABLE_TUNING_FLAG(data) +#define SDMMCHOST_ENABLE_MMC_BOOT(base, flag) +#define SDMMCHOST_SETMMCBOOTCONFIG(base, config) +#define SDMMCHOST_ENABLE_BOOT_FLAG(data) +#define SDMMCHOST_ENABLE_BOOT_CONTINOUS_FLAG(data) +#define SDMMCHOST_GET_HOST_CONFIG_BLOCK_SIZE(config) (0U) +#define SDMMCHOST_GET_HOST_CONFIG_BLOCK_COUNT(config) (0U) +#define SDMMCHOST_GET_HOST_CONFIG_BOOT_MODE(config) (0U) +#define SDMMCHOST_EMPTY_CMD_FLAG(command) +#define SDMMCHOST_CARD_DETECT_STATUS() BOARD_SDIF_CD_STATUS() +#define SDMMCHOST_CARD_DETECT_INIT() BOARD_SDIF_CD_GPIO_INIT() +#define SDMMCHOST_CARD_DETECT_INTERRUPT_STATUS() BOARD_SDIF_CD_INTERRUPT_STATUS() +#define SDMMCHOST_CARD_DETECT_INTERRUPT_CLEAR(flag) BOARD_SDIF_CD_CLEAR_INTERRUPT(flag) +#define SDMMCHOST_CARD_DETECT_GPIO_INTERRUPT_HANDLER BOARD_SDIF_CD_PORT_IRQ_HANDLER +#define SDMMCHOST_CARD_DETECT_IRQ BOARD_SDIF_CD_PORT_IRQ +#define SDMMCHOST_TRANSFER_DATA_ERROR kStatus_SDIF_DataTransferFail +#define SDMMCHOST_TRANSFER_CMD_ERROR kStatus_SDIF_SendCmdFail +/* define card detect pin voltage level when card inserted */ +#if defined BOARD_SDIF_CARD_INSERT_CD_LEVEL +#define SDMMCHOST_CARD_INSERT_CD_LEVEL BOARD_SDIF_CARD_INSERT_CD_LEVEL +#else +#define SDMMCHOST_CARD_INSERT_CD_LEVEL (0U) +#endif +#define SDMMCHOST_AUTO_TUNING_ENABLE(base, flag) +/* sd card detect through host CD */ +#define SDMMCHOST_CARD_DETECT_INSERT_ENABLE(base) (SDIF_EnableInterrupt(base, kSDIF_CardDetect)) +#define SDMMCHOST_CARD_DETECT_INSERT_STATUS(base, data3) (SDIF_DetectCardInsert(base, data3)) +#define SDMMCHOST_ENABLE_SDIO_INT(base) +#define SDMMCHOST_DISABLE_SDIO_INT(base) +/*! @brief SDIF host capability*/ +enum _host_capability +{ + kSDMMCHOST_SupportHighSpeed = kSDIF_SupportHighSpeedFlag, + kSDMMCHOST_SupportDma = kSDIF_SupportDmaFlag, + kSDMMCHOST_SupportSuspendResume = kSDIF_SupportSuspendResumeFlag, + kSDMMCHOST_SupportV330 = kSDIF_SupportV330Flag, + kSDMMCHOST_SupportV300 = SDMMCHOST_NOT_SUPPORT, + kSDMMCHOST_SupportV180 = SDMMCHOST_NOT_SUPPORT, + kSDMMCHOST_SupportV120 = SDMMCHOST_NOT_SUPPORT, + kSDMMCHOST_Support4BitBusWidth = kSDIF_Support4BitFlag, + kSDMMCHOST_Support8BitBusWidth = + SDMMCHOST_NOT_SUPPORT, /* mask the 8 bit here,user can change depend on your board */ + kSDMMCHOST_SupportDDR50 = SDMMCHOST_NOT_SUPPORT, + kSDMMCHOST_SupportSDR104 = SDMMCHOST_NOT_SUPPORT, + kSDMMCHOST_SupportSDR50 = SDMMCHOST_NOT_SUPPORT, + kSDMMCHOST_SupportHS200 = SDMMCHOST_NOT_SUPPORT, + kSDMMCHOST_SupportHS400 = SDMMCHOST_NOT_SUPPORT, + +}; + +/*! @brief DMA table length united as word + * One dma table item occupy four words which can transfer maximum 2*8188 bytes in dual DMA mode + * and 8188 bytes in chain mode + * The more data to be transferred in one time, the bigger value of SDHC_ADMA_TABLE_WORDS need to be set. + * user need check the DMA descriptor table lenght if bigger enough. + */ +#define SDIF_DMA_TABLE_WORDS (0x40U) +/* address align */ +#define SDMMCHOST_DMA_BUFFER_ADDR_ALIGN (4U) + +/*********************************************************USDHC**********************************************************/ +#elif (defined(FSL_FEATURE_SOC_USDHC_COUNT) && (FSL_FEATURE_SOC_USDHC_COUNT > 0U)) + +/*define host baseaddr ,clk freq, IRQ number*/ +#define MMC_HOST_BASEADDR BOARD_MMC_HOST_BASEADDR +#define MMC_HOST_CLK_FREQ BOARD_MMC_HOST_CLK_FREQ +#define MMC_HOST_IRQ BOARD_MMC_HOST_IRQ +#define SD_HOST_BASEADDR BOARD_SD_HOST_BASEADDR +#define SD_HOST_CLK_FREQ BOARD_SD_HOST_CLK_FREQ +#define SD_HOST_IRQ BOARD_SD_HOST_IRQ + +#define SDMMCHOST_TYPE USDHC_Type +#define SDMMCHOST_CONFIG usdhc_host_t +#define SDMMCHOST_TRANSFER usdhc_transfer_t +#define SDMMCHOST_COMMAND usdhc_command_t +#define SDMMCHOST_DATA usdhc_data_t +#define SDMMCHOST_BOOT_CONFIG usdhc_boot_config_t +#define CARD_DATA0_STATUS_MASK (kUSDHC_Data0LineLevelFlag) +#define CARD_DATA1_STATUS_MASK (kUSDHC_Data1LineLevelFlag) +#define CARD_DATA2_STATUS_MASK (kUSDHC_Data2LineLevelFlag) +#define CARD_DATA3_STATUS_MASK (kUSDHC_Data3LineLevelFlag) +#define CARD_DATA0_NOT_BUSY (kUSDHC_Data0LineLevelFlag) + +#define SDMMCHOST_BUS_WIDTH_TYPE usdhc_data_bus_width_t +#define SDMMCHOST_CAPABILITY usdhc_capability_t + +#define kSDMMCHOST_DATABUSWIDTH1BIT kUSDHC_DataBusWidth1Bit /*!< 1-bit mode */ +#define kSDMMCHOST_DATABUSWIDTH4BIT kUSDHC_DataBusWidth4Bit /*!< 4-bit mode */ +#define kSDMMCHOST_DATABUSWIDTH8BIT kUSDHC_DataBusWidth8Bit /*!< 8-bit mode */ + +#define SDMMCHOST_STANDARD_TUNING_START (10U) /*!< standard tuning start point */ +#define SDMMCHOST_TUINIG_STEP (2U) /*!< standard tuning step */ +#define SDMMCHOST_RETUNING_TIMER_COUNT (0U) /*!< Re-tuning timer */ +#define SDMMCHOST_TUNING_DELAY_MAX (0x7FU) +#define SDMMCHOST_RETUNING_REQUEST kStatus_USDHC_ReTuningRequest +#define SDMMCHOST_TUNING_ERROR kStatus_USDHC_TuningError +#define SDMMCHOST_TRANSFER_DATA_ERROR kStatus_USDHC_TransferDataFailed +#define SDMMCHOST_TRANSFER_CMD_ERROR kStatus_USDHC_SendCommandFailed +/* define for card bus speed/strength cnofig */ +#define CARD_BUS_FREQ_50MHZ (0U) +#define CARD_BUS_FREQ_100MHZ0 (1U) +#define CARD_BUS_FREQ_100MHZ1 (2U) +#define CARD_BUS_FREQ_200MHZ (3U) + +#define CARD_BUS_STRENGTH_0 (0U) +#define CARD_BUS_STRENGTH_1 (1U) +#define CARD_BUS_STRENGTH_2 (2U) +#define CARD_BUS_STRENGTH_3 (3U) +#define CARD_BUS_STRENGTH_4 (4U) +#define CARD_BUS_STRENGTH_5 (5U) +#define CARD_BUS_STRENGTH_6 (6U) +#define CARD_BUS_STRENGTH_7 (7U) + +#define SDMMCHOST_STROBE_DLL_DELAY_TARGET (7U) +#define SDMMCHOST_STROBE_DLL_DELAY_UPDATE_INTERVAL (4U) + +/* function pointer define */ +#define SDMMCHOST_TRANSFER_FUNCTION usdhc_transfer_function_t +#define GET_SDMMCHOST_CAPABILITY(base, capability) (USDHC_GetCapability(base, capability)) +#define GET_SDMMCHOST_STATUS(base) (USDHC_GetPresentStatusFlags(base)) +#define SDMMCHOST_SET_CARD_CLOCK(base, sourceClock_HZ, busClock_HZ) \ + (USDHC_SetSdClock(base, sourceClock_HZ, busClock_HZ)) +#define SDMMCHOST_ENABLE_CARD_CLOCK(base, enable) +#define SDMMCHOST_FORCE_SDCLOCK_ON(base, enable) (USDHC_ForceClockOn(base, enable)) +#define SDMMCHOST_SET_CARD_BUS_WIDTH(base, busWidth) (USDHC_SetDataBusWidth(base, busWidth)) +#define SDMMCHOST_SEND_CARD_ACTIVE(base, timeout) (USDHC_SetCardActive(base, timeout)) +#define SDMMCHOST_SWITCH_VOLTAGE180V(base, enable18v) (UDSHC_SelectVoltage(base, enable18v)) +#define SDMMCHOST_SWITCH_VOLTAGE120V(base, enable12v) +#define SDMMCHOST_CONFIG_SD_IO(speed, strength) BOARD_SD_Pin_Config(speed, strength) +#define SDMMCHOST_CONFIG_MMC_IO(speed, strength) BOARD_MMC_Pin_Config(speed, strength) +#define SDMMCHOST_SWITCH_VCC_TO_180V() +#define SDMMCHOST_SWITCH_VCC_TO_330V() + +#if defined(FSL_FEATURE_USDHC_HAS_SDR50_MODE) && (!FSL_FEATURE_USDHC_HAS_SDR50_MODE) +#define SDMMCHOST_EXECUTE_STANDARD_TUNING_STATUS(base) (0U) +#define SDMMCHOST_EXECUTE_STANDARD_TUNING_RESULT(base) (1U) +#define SDMMCHOST_AUTO_STANDARD_RETUNING_TIMER(base) +#define SDMMCHOST_EXECUTE_STANDARD_TUNING_ENABLE(base, flag) +#define SDMMCHOST_CHECK_TUNING_ERROR(base) (0U) +#define SDMMCHOST_ADJUST_TUNING_DELAY(base, delay) +#else +#define SDMMCHOST_EXECUTE_STANDARD_TUNING_ENABLE(base, flag) \ + (USDHC_EnableStandardTuning(base, SDMMCHOST_STANDARD_TUNING_START, SDMMCHOST_TUINIG_STEP, flag)) +#define SDMMCHOST_EXECUTE_STANDARD_TUNING_STATUS(base) (USDHC_GetExecuteStdTuningStatus(base)) +#define SDMMCHOST_EXECUTE_STANDARD_TUNING_RESULT(base) (USDHC_CheckStdTuningResult(base)) +#define SDMMCHOST_AUTO_STANDARD_RETUNING_TIMER(base) (USDHC_SetRetuningTimer(base, SDMMCHOST_RETUNING_TIMER_COUNT)) +#define SDMMCHOST_EXECUTE_MANUAL_TUNING_ENABLE(base, flag) (USDHC_EnableManualTuning(base, flag)) +#define SDMMCHOST_ADJUST_TUNING_DELAY(base, delay) (USDHC_AdjustDelayForManualTuning(base, delay)) +#define SDMMCHOST_AUTO_TUNING_ENABLE(base, flag) (USDHC_EnableAutoTuning(base, flag)) +#define SDMMCHOST_CHECK_TUNING_ERROR(base) (USDHC_CheckTuningError(base)) +#endif + +#define SDMMCHOST_AUTO_TUNING_CONFIG(base) (USDHC_EnableAutoTuningForCmdAndData(base)) +#define SDMMCHOST_RESET_TUNING(base, timeout) \ + { \ + (USDHC_Reset(base, kUSDHC_ResetTuning | kUSDHC_ResetData | kUSDHC_ResetCommand, timeout)); \ + } + +#define SDMMCHOST_ENABLE_DDR_MODE(base, flag, nibblePos) (USDHC_EnableDDRMode(base, flag, nibblePos)) + +#if FSL_FEATURE_USDHC_HAS_HS400_MODE +#define SDMMCHOST_ENABLE_HS400_MODE(base, flag) (USDHC_EnableHS400Mode(base, flag)) +#define SDMMCHOST_RESET_STROBE_DLL(base) (USDHC_ResetStrobeDLL(base)) +#define SDMMCHOST_ENABLE_STROBE_DLL(base, flag) (USDHC_EnableStrobeDLL(base, flag)) +#define SDMMCHOST_CONFIG_STROBE_DLL(base, delay, updateInterval) (USDHC_ConfigStrobeDLL(base, delay, updateInterval)) +#define SDMMCHOST_GET_STROBE_DLL_STATUS (base)(USDHC_GetStrobeDLLStatus(base)) +#else +#define SDMMCHOST_ENABLE_HS400_MODE(base, flag) +#define SDMMCHOST_RESET_STROBE_DLL(base) +#define SDMMCHOST_ENABLE_STROBE_DLL(base, flag) +#define SDMMCHOST_CONFIG_STROBE_DLL(base, delay, updateInterval) +#define SDMMCHOST_GET_STROBE_DLL_STATUS(base) +#endif + +#define SDMMCHOST_ENABLE_MMC_BOOT(base, flag) (USDHC_EnableMmcBoot(base, flag)) +#define SDMMCHOST_SETMMCBOOTCONFIG(base, config) (USDHC_SetMmcBootConfig(base, config)) +/* sd card power */ +#define SDMMCHOST_INIT_SD_POWER() BOARD_USDHC_SDCARD_POWER_CONTROL_INIT() +#define SDMMCHOST_ENABLE_SD_POWER(enable) BOARD_USDHC_SDCARD_POWER_CONTROL(enable) +/* mmc card power */ +#define SDMMCHOST_INIT_MMC_POWER() BOARD_USDHC_MMCCARD_POWER_CONTROL_INIT() +#define SDMMCHOST_ENABLE_MMC_POWER(enable) BOARD_USDHC_MMCCARD_POWER_CONTROL(enable) +/* sd card detect through gpio */ +#define SDMMCHOST_CARD_DETECT_GPIO_STATUS() BOARD_USDHC_CD_STATUS() +#define SDMMCHOST_CARD_DETECT_GPIO_INIT() BOARD_USDHC_CD_GPIO_INIT() +#define SDMMCHOST_CARD_DETECT_GPIO_INTERRUPT_STATUS() BOARD_USDHC_CD_INTERRUPT_STATUS() +#define SDMMCHOST_CARD_DETECT_GPIO_INTERRUPT_STATUS_CLEAR(flag) BOARD_USDHC_CD_CLEAR_INTERRUPT(flag) +#define SDMMCHOST_CARD_DETECT_GPIO_INTERRUPT_HANDLER BOARD_USDHC_CD_PORT_IRQ_HANDLER +#define SDMMCHOST_CARD_DETECT_GPIO_IRQ BOARD_USDHC_CD_PORT_IRQ +/* sd card detect through host CD */ +#define SDMMCHOST_CARD_DETECT_INSERT_ENABLE(base) (USDHC_EnableInterruptStatus(base, kUSDHC_CardInsertionFlag)) +#define SDMMCHOST_CARD_DETECT_REMOVE_ENABLE(base) (USDHC_EnableInterruptStatus(base, kUSDHC_CardRemovalFlag)) +#define SDMMCHOST_CARD_DETECT_INSERT_STATUS(base) (USDHC_DetectCardInsert(base)) +#define SDMMCHOST_CARD_DETECT_REMOVE_STATUS(base) (USDHC_GetInterruptStatusFlags(base, kUSDHC_CardRemovalFlag)) +#define SDMMCHOST_CARD_DETECT_INSERT_INTERRUPT_ENABLE(base) \ + (USDHC_EnableInterruptSignal(base, kUSDHC_CardInsertionFlag)) +#define SDMMCHOST_CARD_DETECT_REMOVE_INTERRUPT_ENABLE(base) (USDHC_EnableInterruptSignal(base, kUSDHC_CardRemovalFlag)) +#define SDMMCHOST_CARD_DETECT_DATA3_ENABLE(base, flag) (USDHC_CardDetectByData3(base, flag)) + +/* define card detect pin voltage level when card inserted */ +#if defined BOARD_USDHC_CARD_INSERT_CD_LEVEL +#define SDMMCHOST_CARD_INSERT_CD_LEVEL BOARD_USDHC_CARD_INSERT_CD_LEVEL +#else +#define SDMMCHOST_CARD_INSERT_CD_LEVEL (0U) +#endif +#define SDMMCHOST_ENABLE_TUNING_FLAG(data) (data.dataType = kUSDHC_TransferDataTuning) +#define SDMMCHOST_ENABLE_BOOT_FLAG(data) (data.dataType = kUSDHC_TransferDataBoot) +#define SDMMCHOST_ENABLE_BOOT_CONTINOUS_FLAG(data) (data.dataType = kUSDHC_TransferDataBootcontinous) +#define SDMMCHOST_GET_HOST_CONFIG_BLOCK_SIZE(config) (config->blockSize) +#define SDMMCHOST_GET_HOST_CONFIG_BLOCK_COUNT(config) (config->blockCount) +#define SDMMCHOST_GET_HOST_CONFIG_BOOT_MODE(config) (config->bootMode) +#define SDMMCHOST_EMPTY_CMD_FLAG(command) (command.type = kCARD_CommandTypeEmpty) +#define SDMMCHOST_ENABLE_SDIO_INT(base) \ + USDHC_EnableInterruptStatus(base, kUSDHC_CardInterruptFlag); \ + USDHC_EnableInterruptSignal(base, kUSDHC_CardInterruptFlag) +#define SDMMCHOST_DISABLE_SDIO_INT(base) \ + USDHC_DisableInterruptStatus(base, kUSDHC_CardInterruptFlag); \ + USDHC_DisableInterruptSignal(base, kUSDHC_CardInterruptFlag) +/*! @brief USDHC host capability*/ +enum _host_capability +{ + kSDMMCHOST_SupportAdma = kUSDHC_SupportAdmaFlag, + kSDMMCHOST_SupportHighSpeed = kUSDHC_SupportHighSpeedFlag, + kSDMMCHOST_SupportDma = kUSDHC_SupportDmaFlag, + kSDMMCHOST_SupportSuspendResume = kUSDHC_SupportSuspendResumeFlag, + kSDMMCHOST_SupportV330 = kUSDHC_SupportV330Flag, /* this define should depend on your board config */ + kSDMMCHOST_SupportV300 = kUSDHC_SupportV300Flag, /* this define should depend on your board config */ +#if defined(BOARD_SD_SUPPORT_180V) && !BOARD_SD_SUPPORT_180V + kSDMMCHOST_SupportV180 = SDMMCHOST_NOT_SUPPORT, /* this define should depend on you board config */ +#else + kSDMMCHOST_SupportV180 = kUSDHC_SupportV180Flag, /* this define should depend on you board config */ +#endif + kSDMMCHOST_SupportV120 = SDMMCHOST_NOT_SUPPORT, + kSDMMCHOST_Support4BitBusWidth = kUSDHC_Support4BitFlag, +#if defined(BOARD_MMC_SUPPORT_8BIT_BUS) +#if BOARD_MMC_SUPPORT_8BIT_BUS + kSDMMCHOST_Support8BitBusWidth = kUSDHC_Support8BitFlag, +#else + kSDMMCHOST_Support8BitBusWidth = SDMMCHOST_NOT_SUPPORT, +#endif +#else + kSDMMCHOST_Support8BitBusWidth = kUSDHC_Support8BitFlag, +#endif + kSDMMCHOST_SupportDDR50 = kUSDHC_SupportDDR50Flag, + kSDMMCHOST_SupportSDR104 = kUSDHC_SupportSDR104Flag, + kSDMMCHOST_SupportSDR50 = kUSDHC_SupportSDR50Flag, + kSDMMCHOST_SupportHS200 = kUSDHC_SupportSDR104Flag, +#if FSL_FEATURE_USDHC_HAS_HS400_MODE + kSDMMCHOST_SupportHS400 = SDMMCHOST_SUPPORT +#else + kSDMMCHOST_SupportHS400 = SDMMCHOST_NOT_SUPPORT, +#endif +}; + +/* Endian mode. */ +#define USDHC_ENDIAN_MODE kUSDHC_EndianModeLittle + +/* DMA mode */ +#define USDHC_DMA_MODE kUSDHC_DmaModeAdma2 +/* address align */ +#define SDMMCHOST_DMA_BUFFER_ADDR_ALIGN (USDHC_ADMA2_ADDRESS_ALIGN) + +/* Read/write watermark level. The bigger value indicates DMA has higher read/write performance. */ +#define USDHC_READ_WATERMARK_LEVEL (0x80U) +#define USDHC_WRITE_WATERMARK_LEVEL (0x80U) + +/* ADMA table length united as word. + * + * One ADMA2 table item occupy two words which can transfer maximum 0xFFFFU bytes one time. + * The more data to be transferred in one time, the bigger value of SDHC_ADMA_TABLE_WORDS need to be set. + */ +#define USDHC_ADMA_TABLE_WORDS (8U) /* define the ADMA descriptor table length */ +#define USDHC_ADMA2_ADDR_ALIGN (4U) /* define the ADMA2 descriptor table addr align size */ +#define USDHC_READ_BURST_LEN (8U) /*!< number of words USDHC read in a single burst */ +#define USDHC_WRITE_BURST_LEN (8U) /*!< number of words USDHC write in a single burst */ +#define USDHC_DATA_TIMEOUT (0xFU) /*!< data timeout counter value */ + +#endif /* (defined(FSL_FEATURE_SOC_SDHC_COUNT) && (FSL_FEATURE_SOC_SDHC_COUNT > 0U)) */ + +/*! @brief card detect callback definition */ +typedef void (*sdmmchost_cd_callback_t)(bool isInserted, void *userData); + +/*! @brief host Endian mode + * corresponding to driver define + */ +enum _sdmmchost_endian_mode +{ + kSDMMCHOST_EndianModeBig = 0U, /*!< Big endian mode */ + kSDMMCHOST_EndianModeHalfWordBig = 1U, /*!< Half word big endian mode */ + kSDMMCHOST_EndianModeLittle = 2U, /*!< Little endian mode */ +}; + +/*! @brief sd card detect type */ +typedef enum _sdmmchost_detect_card_type +{ + kSDMMCHOST_DetectCardByGpioCD, /*!< sd card detect by CD pin through GPIO */ + kSDMMCHOST_DetectCardByHostCD, /*!< sd card detect by CD pin through host */ + kSDMMCHOST_DetectCardByHostDATA3, /*!< sd card detect by DAT3 pin through host */ +} sdmmchost_detect_card_type_t; + +/*! @brief sd card detect */ +typedef struct _sdmmchost_detect_card +{ + sdmmchost_detect_card_type_t cdType; /*!< card detect type */ + uint32_t cdTimeOut_ms; /*!< card detect timeout which allow 0 - 0xFFFFFFF, value 0 will return immediately, value + 0xFFFFFFFF will block until card is insert */ + + sdmmchost_cd_callback_t cardInserted; /*!< card inserted callback which is meaningful for interrupt case */ + sdmmchost_cd_callback_t cardRemoved; /*!< card removed callback which is meaningful for interrupt case */ + + void *userData; /*!< user data */ +} sdmmchost_detect_card_t; + +/*! @brief card power control function pointer */ +typedef void (*sdmmchost_pwr_t)(void); + +/*! @brief card power control */ +typedef struct _sdmmchost_pwr_card +{ + sdmmchost_pwr_t powerOn; /*!< power on function pointer */ + uint32_t powerOnDelay_ms; /*!< power on delay */ + + sdmmchost_pwr_t powerOff; /*!< power off function pointer */ + uint32_t powerOffDelay_ms; /*!< power off delay */ +} sdmmchost_pwr_card_t; + +/*! @brief card interrupt function pointer */ +typedef void (*sdmmchost_card_int_callback_t)(void *userData); +/*! @brief card interrupt application callback */ +typedef struct _sdmmchost_card_int +{ + void *userData; /*!< user data */ + sdmmchost_card_int_callback_t cardInterrupt; /*!< card int call back */ +} sdmmchost_card_int_t; + +/*! @brief card switch voltage function pointer */ +typedef void (*sdmmchost_card_switch_voltage_t)(void); +/*! @brief card switch voltage function collection */ +typedef struct _sdmmchost_card_switch_voltage_func +{ + sdmmchost_card_switch_voltage_t cardSignalLine1V8; /*!< switch to 1.8v function pointer */ + sdmmchost_card_switch_voltage_t cardSignalLine3V3; /*! + +/*! + * @addtogroup CARD + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief SD/MMC card initialization clock frequency */ +#define SDMMC_CLOCK_400KHZ (400000U) +/*! @brief SD card bus frequency 1 in high-speed mode */ +#define SD_CLOCK_25MHZ (25000000U) +/*! @brief SD card bus frequency 2 in high-speed mode */ +#define SD_CLOCK_50MHZ (50000000U) +/*! @brief SD card bus frequency in SDR50 mode */ +#define SD_CLOCK_100MHZ (100000000U) +/*! @brief SD card bus frequency in SDR104 mode */ +#define SD_CLOCK_208MHZ (208000000U) +/*! @brief MMC card bus frequency 1 in high-speed mode */ +#define MMC_CLOCK_26MHZ (26000000U) +/*! @brief MMC card bus frequency 2 in high-speed mode */ +#define MMC_CLOCK_52MHZ (52000000U) +/*! @brief MMC card bus frequency in high-speed DDR52 mode */ +#define MMC_CLOCK_DDR52 (52000000U) +/*! @brief MMC card bus frequency in high-speed HS200 mode */ +#define MMC_CLOCK_HS200 (200000000U) +/*! @brief MMC card bus frequency in high-speed HS400 mode */ +#define MMC_CLOCK_HS400 (400000000U) + +/*!@brief mask convert */ +#define SDMMC_MASK(bit) (1U << (bit)) + +/*! @brief Card status bit in R1 */ +enum _sdmmc_r1_card_status_flag +{ + kSDMMC_R1OutOfRangeFlag = 31, /*!< Out of range status bit */ + kSDMMC_R1AddressErrorFlag = 30, /*!< Address error status bit */ + kSDMMC_R1BlockLengthErrorFlag = 29, /*!< Block length error status bit */ + kSDMMC_R1EraseSequenceErrorFlag = 28, /*!< Erase sequence error status bit */ + kSDMMC_R1EraseParameterErrorFlag = 27, /*!< Erase parameter error status bit */ + kSDMMC_R1WriteProtectViolationFlag = 26, /*!< Write protection violation status bit */ + kSDMMC_R1CardIsLockedFlag = 25, /*!< Card locked status bit */ + kSDMMC_R1LockUnlockFailedFlag = 24, /*!< lock/unlock error status bit */ + kSDMMC_R1CommandCrcErrorFlag = 23, /*!< CRC error status bit */ + kSDMMC_R1IllegalCommandFlag = 22, /*!< Illegal command status bit */ + kSDMMC_R1CardEccFailedFlag = 21, /*!< Card ecc error status bit */ + kSDMMC_R1CardControllerErrorFlag = 20, /*!< Internal card controller error status bit */ + kSDMMC_R1ErrorFlag = 19, /*!< A general or an unknown error status bit */ + kSDMMC_R1CidCsdOverwriteFlag = 16, /*!< Cid/csd overwrite status bit */ + kSDMMC_R1WriteProtectEraseSkipFlag = 15, /*!< Write protection erase skip status bit */ + kSDMMC_R1CardEccDisabledFlag = 14, /*!< Card ecc disabled status bit */ + kSDMMC_R1EraseResetFlag = 13, /*!< Erase reset status bit */ + kSDMMC_R1ReadyForDataFlag = 8, /*!< Ready for data status bit */ + kSDMMC_R1SwitchErrorFlag = 7, /*!< Switch error status bit */ + kSDMMC_R1ApplicationCommandFlag = 5, /*!< Application command enabled status bit */ + kSDMMC_R1AuthenticationSequenceErrorFlag = 3, /*!< error in the sequence of authentication process */ +}; + +/*! @brief R1 all the error flag */ +#define SDMMC_R1_ALL_ERROR_FLAG \ + (SDMMC_MASK(kSDMMC_R1OutOfRangeFlag) | SDMMC_MASK(kSDMMC_R1AddressErrorFlag) | \ + SDMMC_MASK(kSDMMC_R1BlockLengthErrorFlag) | SDMMC_MASK(kSDMMC_R1EraseSequenceErrorFlag) | \ + SDMMC_MASK(kSDMMC_R1EraseParameterErrorFlag) | SDMMC_MASK(kSDMMC_R1WriteProtectViolationFlag) | \ + SDMMC_MASK(kSDMMC_R1CardIsLockedFlag) | SDMMC_MASK(kSDMMC_R1LockUnlockFailedFlag) | \ + SDMMC_MASK(kSDMMC_R1CommandCrcErrorFlag) | SDMMC_MASK(kSDMMC_R1IllegalCommandFlag) | \ + SDMMC_MASK(kSDMMC_R1CardEccFailedFlag) | SDMMC_MASK(kSDMMC_R1CardControllerErrorFlag) | \ + SDMMC_MASK(kSDMMC_R1ErrorFlag) | SDMMC_MASK(kSDMMC_R1CidCsdOverwriteFlag) | \ + SDMMC_MASK(kSDMMC_R1AuthenticationSequenceErrorFlag)) + +/*! @brief R1: current state */ +#define SDMMC_R1_CURRENT_STATE(x) (((x)&0x00001E00U) >> 9U) + +/*! @brief CURRENT_STATE filed in R1 */ +typedef enum _sdmmc_r1_current_state +{ + kSDMMC_R1StateIdle = 0U, /*!< R1: current state: idle */ + kSDMMC_R1StateReady = 1U, /*!< R1: current state: ready */ + kSDMMC_R1StateIdentify = 2U, /*!< R1: current state: identification */ + kSDMMC_R1StateStandby = 3U, /*!< R1: current state: standby */ + kSDMMC_R1StateTransfer = 4U, /*!< R1: current state: transfer */ + kSDMMC_R1StateSendData = 5U, /*!< R1: current state: sending data */ + kSDMMC_R1StateReceiveData = 6U, /*!< R1: current state: receiving data */ + kSDMMC_R1StateProgram = 7U, /*!< R1: current state: programming */ + kSDMMC_R1StateDisconnect = 8U, /*!< R1: current state: disconnect */ +} sdmmc_r1_current_state_t; + +/*! @brief Error bit in SPI mode R1 */ +enum _sdspi_r1_error_status_flag +{ + kSDSPI_R1InIdleStateFlag = (1U << 0U), /*!< In idle state */ + kSDSPI_R1EraseResetFlag = (1U << 1U), /*!< Erase reset */ + kSDSPI_R1IllegalCommandFlag = (1U << 2U), /*!< Illegal command */ + kSDSPI_R1CommandCrcErrorFlag = (1U << 3U), /*!< Com crc error */ + kSDSPI_R1EraseSequenceErrorFlag = (1U << 4U), /*!< Erase sequence error */ + kSDSPI_R1AddressErrorFlag = (1U << 5U), /*!< Address error */ + kSDSPI_R1ParameterErrorFlag = (1U << 6U), /*!< Parameter error */ +}; + +/*! @brief Error bit in SPI mode R2 */ +enum _sdspi_r2_error_status_flag +{ + kSDSPI_R2CardLockedFlag = (1U << 0U), /*!< Card is locked */ + kSDSPI_R2WriteProtectEraseSkip = (1U << 1U), /*!< Write protect erase skip */ + kSDSPI_R2LockUnlockFailed = (1U << 1U), /*!< Lock/unlock command failed */ + kSDSPI_R2ErrorFlag = (1U << 2U), /*!< Unknown error */ + kSDSPI_R2CardControllerErrorFlag = (1U << 3U), /*!< Card controller error */ + kSDSPI_R2CardEccFailedFlag = (1U << 4U), /*!< Card ecc failed */ + kSDSPI_R2WriteProtectViolationFlag = (1U << 5U), /*!< Write protect violation */ + kSDSPI_R2EraseParameterErrorFlag = (1U << 6U), /*!< Erase parameter error */ + kSDSPI_R2OutOfRangeFlag = (1U << 7U), /*!< Out of range */ + kSDSPI_R2CsdOverwriteFlag = (1U << 7U), /*!< CSD overwrite */ +}; + +/*! @brief The bit mask for COMMAND VERSION field in R7 */ +#define SDSPI_R7_VERSION_SHIFT (28U) +/*! @brief The bit mask for COMMAND VERSION field in R7 */ +#define SDSPI_R7_VERSION_MASK (0xFU) +/*! @brief The bit shift for VOLTAGE ACCEPTED field in R7 */ +#define SDSPI_R7_VOLTAGE_SHIFT (8U) +/*! @brief The bit mask for VOLTAGE ACCEPTED field in R7 */ +#define SDSPI_R7_VOLTAGE_MASK (0xFU) +/*! @brief The bit mask for VOLTAGE 2.7V to 3.6V field in R7 */ +#define SDSPI_R7_VOLTAGE_27_36_MASK (0x1U << SDSPI_R7_VOLTAGE_SHIFT) +/*! @brief The bit shift for ECHO field in R7 */ +#define SDSPI_R7_ECHO_SHIFT (0U) +/*! @brief The bit mask for ECHO field in R7 */ +#define SDSPI_R7_ECHO_MASK (0xFFU) + +/*! @brief Data error token mask */ +#define SDSPI_DATA_ERROR_TOKEN_MASK (0xFU) +/*! @brief Data Error Token mask bit */ +enum _sdspi_data_error_token +{ + kSDSPI_DataErrorTokenError = (1U << 0U), /*!< Data error */ + kSDSPI_DataErrorTokenCardControllerError = (1U << 1U), /*!< Card controller error */ + kSDSPI_DataErrorTokenCardEccFailed = (1U << 2U), /*!< Card ecc error */ + kSDSPI_DataErrorTokenOutOfRange = (1U << 3U), /*!< Out of range */ +}; + +/*! @brief Data Token */ +typedef enum _sdspi_data_token +{ + kSDSPI_DataTokenBlockRead = 0xFEU, /*!< Single block read, multiple block read */ + kSDSPI_DataTokenSingleBlockWrite = 0xFEU, /*!< Single block write */ + kSDSPI_DataTokenMultipleBlockWrite = 0xFCU, /*!< Multiple block write */ + kSDSPI_DataTokenStopTransfer = 0xFDU, /*!< Stop transmission */ +} sdspi_data_token_t; + +/* Data Response Token mask */ +#define SDSPI_DATA_RESPONSE_TOKEN_MASK (0x1FU) /*!< Mask for data response bits */ +/*! @brief Data Response Token */ +typedef enum _sdspi_data_response_token +{ + kSDSPI_DataResponseTokenAccepted = 0x05U, /*!< Data accepted */ + kSDSPI_DataResponseTokenCrcError = 0x0BU, /*!< Data rejected due to CRC error */ + kSDSPI_DataResponseTokenWriteError = 0x0DU, /*!< Data rejected due to write error */ +} sdspi_data_response_token_t; + +/*! @brief SD card individual commands */ +typedef enum _sd_command +{ + kSD_SendRelativeAddress = 3U, /*!< Send Relative Address */ + kSD_Switch = 6U, /*!< Switch Function */ + kSD_SendInterfaceCondition = 8U, /*!< Send Interface Condition */ + kSD_VoltageSwitch = 11U, /*!< Voltage Switch */ + kSD_SpeedClassControl = 20U, /*!< Speed Class control */ + kSD_EraseWriteBlockStart = 32U, /*!< Write Block Start */ + kSD_EraseWriteBlockEnd = 33U, /*!< Write Block End */ + kSD_SendTuningBlock = 19U, /*!< Send Tuning Block */ +} sd_command_t; + +/*! @brief SDSPI individual commands */ +typedef enum _sdspi_command +{ + kSDSPI_CommandCrc = 59U, /*!< Command crc protection on/off */ +} sdspi_command_t; + +/*! @brief SD card individual application commands */ +typedef enum _sd_application_command +{ + kSD_ApplicationSetBusWdith = 6U, /*!< Set Bus Width */ + kSD_ApplicationStatus = 13U, /*!< Send SD status */ + kSD_ApplicationSendNumberWriteBlocks = 22U, /*!< Send Number Of Written Blocks */ + kSD_ApplicationSetWriteBlockEraseCount = 23U, /*!< Set Write Block Erase Count */ + kSD_ApplicationSendOperationCondition = 41U, /*!< Send Operation Condition */ + kSD_ApplicationSetClearCardDetect = 42U, /*!< Set Connnect/Disconnect pull up on detect pin */ + kSD_ApplicationSendScr = 51U, /*!< Send Scr */ +} sd_application_command_t; + +/*! @brief SD card command class */ +enum _sdmmc_command_class +{ + kSDMMC_CommandClassBasic = (1U << 0U), /*!< Card command class 0 */ + kSDMMC_CommandClassBlockRead = (1U << 2U), /*!< Card command class 2 */ + kSDMMC_CommandClassBlockWrite = (1U << 4U), /*!< Card command class 4 */ + kSDMMC_CommandClassErase = (1U << 5U), /*!< Card command class 5 */ + kSDMMC_CommandClassWriteProtect = (1U << 6U), /*!< Card command class 6 */ + kSDMMC_CommandClassLockCard = (1U << 7U), /*!< Card command class 7 */ + kSDMMC_CommandClassApplicationSpecific = (1U << 8U), /*!< Card command class 8 */ + kSDMMC_CommandClassInputOutputMode = (1U << 9U), /*!< Card command class 9 */ + kSDMMC_CommandClassSwitch = (1U << 10U), /*!< Card command class 10 */ +}; + +/*! @brief OCR register in SD card */ +enum _sd_ocr_flag +{ + kSD_OcrPowerUpBusyFlag = 31, /*!< Power up busy status */ + kSD_OcrHostCapacitySupportFlag = 30, /*!< Card capacity status */ + kSD_OcrCardCapacitySupportFlag = kSD_OcrHostCapacitySupportFlag, /*!< Card capacity status */ + kSD_OcrSwitch18RequestFlag = 24, /*!< Switch to 1.8V request */ + kSD_OcrSwitch18AcceptFlag = kSD_OcrSwitch18RequestFlag, /*!< Switch to 1.8V accepted */ + kSD_OcrVdd27_28Flag = 15, /*!< VDD 2.7-2.8 */ + kSD_OcrVdd28_29Flag = 16, /*!< VDD 2.8-2.9 */ + kSD_OcrVdd29_30Flag = 17, /*!< VDD 2.9-3.0 */ + kSD_OcrVdd30_31Flag = 18, /*!< VDD 2.9-3.0 */ + kSD_OcrVdd31_32Flag = 19, /*!< VDD 3.0-3.1 */ + kSD_OcrVdd32_33Flag = 20, /*!< VDD 3.1-3.2 */ + kSD_OcrVdd33_34Flag = 21, /*!< VDD 3.2-3.3 */ + kSD_OcrVdd34_35Flag = 22, /*!< VDD 3.3-3.4 */ + kSD_OcrVdd35_36Flag = 23, /*!< VDD 3.4-3.5 */ +}; + +/*! @brief SD card specification version number */ +enum _sd_specification_version +{ + kSD_SpecificationVersion1_0 = (1U << 0U), /*!< SD card version 1.0-1.01 */ + kSD_SpecificationVersion1_1 = (1U << 1U), /*!< SD card version 1.10 */ + kSD_SpecificationVersion2_0 = (1U << 2U), /*!< SD card version 2.00 */ + kSD_SpecificationVersion3_0 = (1U << 3U), /*!< SD card version 3.0 */ +}; + +/*! @brief SD card bus width */ +typedef enum _sd_data_bus_width +{ + kSD_DataBusWidth1Bit = 0U, /*!< SD data bus width 1-bit mode */ + kSD_DataBusWidth4Bit = 1U, /*!< SD data bus width 4-bit mode */ +} sd_data_bus_width_t; + +/*! @brief SD card switch mode */ +typedef enum _sd_switch_mode +{ + kSD_SwitchCheck = 0U, /*!< SD switch mode 0: check function */ + kSD_SwitchSet = 1U, /*!< SD switch mode 1: set function */ +} sd_switch_mode_t; + +/*! @brief SD card CSD register flags */ +enum _sd_csd_flag +{ + kSD_CsdReadBlockPartialFlag = (1U << 0U), /*!< Partial blocks for read allowed [79:79] */ + kSD_CsdWriteBlockMisalignFlag = (1U << 1U), /*!< Write block misalignment [78:78] */ + kSD_CsdReadBlockMisalignFlag = (1U << 2U), /*!< Read block misalignment [77:77] */ + kSD_CsdDsrImplementedFlag = (1U << 3U), /*!< DSR implemented [76:76] */ + kSD_CsdEraseBlockEnabledFlag = (1U << 4U), /*!< Erase single block enabled [46:46] */ + kSD_CsdWriteProtectGroupEnabledFlag = (1U << 5U), /*!< Write protect group enabled [31:31] */ + kSD_CsdWriteBlockPartialFlag = (1U << 6U), /*!< Partial blocks for write allowed [21:21] */ + kSD_CsdFileFormatGroupFlag = (1U << 7U), /*!< File format group [15:15] */ + kSD_CsdCopyFlag = (1U << 8U), /*!< Copy flag [14:14] */ + kSD_CsdPermanentWriteProtectFlag = (1U << 9U), /*!< Permanent write protection [13:13] */ + kSD_CsdTemporaryWriteProtectFlag = (1U << 10U), /*!< Temporary write protection [12:12] */ +}; + +/*! @brief SD card SCR register flags */ +enum _sd_scr_flag +{ + kSD_ScrDataStatusAfterErase = (1U << 0U), /*!< Data status after erases [55:55] */ + kSD_ScrSdSpecification3 = (1U << 1U), /*!< Specification version 3.00 or higher [47:47]*/ +}; + +/*! @brief SD timing function number */ +enum _sd_timing_function +{ + kSD_FunctionSDR12Deafult = 0U, /*!< SDR12 mode & default*/ + kSD_FunctionSDR25HighSpeed = 1U, /*!< SDR25 & high speed*/ + kSD_FunctionSDR50 = 2U, /*!< SDR50 mode*/ + kSD_FunctionSDR104 = 3U, /*!< SDR104 mode*/ + kSD_FunctionDDR50 = 4U, /*!< DDR50 mode*/ +}; + +/*! @brief SD group number */ +enum _sd_group_num +{ + kSD_GroupTimingMode = 0U, /*!< acess mode group*/ + kSD_GroupCommandSystem = 1U, /*!< command system group*/ + kSD_GroupDriverStrength = 2U, /*!< driver strength group*/ + kSD_GroupCurrentLimit = 3U, /*!< current limit group*/ +}; + +/*! @brief SD card timing mode flags */ +typedef enum _sd_timing_mode +{ + kSD_TimingSDR12DefaultMode = 0U, /*!< Identification mode & SDR12 */ + kSD_TimingSDR25HighSpeedMode = 1U, /*!< High speed mode & SDR25 */ + kSD_TimingSDR50Mode = 2U, /*!< SDR50 mode*/ + kSD_TimingSDR104Mode = 3U, /*!< SDR104 mode */ + kSD_TimingDDR50Mode = 4U, /*!< DDR50 mode */ +} sd_timing_mode_t; + +/*! @brief SD card driver strength */ +typedef enum _sd_driver_strength +{ + kSD_DriverStrengthTypeB = 0U, /*!< default driver strength*/ + kSD_DriverStrengthTypeA = 1U, /*!< driver strength TYPE A */ + kSD_DriverStrengthTypeC = 2U, /*!< driver strength TYPE C */ + kSD_DriverStrengthTypeD = 3U, /*!< driver strength TYPE D */ +} sd_driver_strength_t; + +/*! @brief SD card current limit */ +typedef enum _sd_max_current +{ + kSD_CurrentLimit200MA = 0U, /*!< default current limit */ + kSD_CurrentLimit400MA = 1U, /*!< current limit to 400MA */ + kSD_CurrentLimit600MA = 2U, /*!< current limit to 600MA */ + kSD_CurrentLimit800MA = 3U, /*!< current limit to 800MA */ +} sd_max_current_t; + +/*! @brief SD/MMC card common commands */ +typedef enum _sdmmc_command +{ + kSDMMC_GoIdleState = 0U, /*!< Go Idle State */ + kSDMMC_AllSendCid = 2U, /*!< All Send CID */ + kSDMMC_SetDsr = 4U, /*!< Set DSR */ + kSDMMC_SelectCard = 7U, /*!< Select Card */ + kSDMMC_SendCsd = 9U, /*!< Send CSD */ + kSDMMC_SendCid = 10U, /*!< Send CID */ + kSDMMC_StopTransmission = 12U, /*!< Stop Transmission */ + kSDMMC_SendStatus = 13U, /*!< Send Status */ + kSDMMC_GoInactiveState = 15U, /*!< Go Inactive State */ + kSDMMC_SetBlockLength = 16U, /*!< Set Block Length */ + kSDMMC_ReadSingleBlock = 17U, /*!< Read Single Block */ + kSDMMC_ReadMultipleBlock = 18U, /*!< Read Multiple Block */ + kSDMMC_SetBlockCount = 23U, /*!< Set Block Count */ + kSDMMC_WriteSingleBlock = 24U, /*!< Write Single Block */ + kSDMMC_WriteMultipleBlock = 25U, /*!< Write Multiple Block */ + kSDMMC_ProgramCsd = 27U, /*!< Program CSD */ + kSDMMC_SetWriteProtect = 28U, /*!< Set Write Protect */ + kSDMMC_ClearWriteProtect = 29U, /*!< Clear Write Protect */ + kSDMMC_SendWriteProtect = 30U, /*!< Send Write Protect */ + kSDMMC_Erase = 38U, /*!< Erase */ + kSDMMC_LockUnlock = 42U, /*!< Lock Unlock */ + kSDMMC_ApplicationCommand = 55U, /*!< Send Application Command */ + kSDMMC_GeneralCommand = 56U, /*!< General Purpose Command */ + kSDMMC_ReadOcr = 58U, /*!< Read OCR */ +} sdmmc_command_t; + +/*! @brief sdio card cccr register number */ +#define SDIO_CCCR_REG_NUMBER (0x16U) +/*! @brief sdio IO ready timeout steps */ +#ifndef SDIO_IO_READY_TIMEOUT_UNIT +#define SDIO_IO_READY_TIMEOUT_UNIT (10U) +#endif +/*! @brief sdio card cccr register addr */ +enum _sdio_cccr_reg +{ + kSDIO_RegCCCRSdioVer = 0x00U, /*!< CCCR & SDIO version*/ + kSDIO_RegSDVersion = 0x01U, /*!< SD version */ + kSDIO_RegIOEnable = 0x02U, /*!< io enable register */ + kSDIO_RegIOReady = 0x03U, /*!< io ready register */ + kSDIO_RegIOIntEnable = 0x04U, /*!< io interrupt enable register */ + kSDIO_RegIOIntPending = 0x05U, /*!< io interrupt pending register */ + kSDIO_RegIOAbort = 0x06U, /*!< io abort register */ + kSDIO_RegBusInterface = 0x07U, /*!< bus interface register */ + kSDIO_RegCardCapability = 0x08U, /*!< card capability register */ + kSDIO_RegCommonCISPointer = 0x09U, /*!< common CIS pointer register */ + kSDIO_RegBusSuspend = 0x0C, /*!< bus suspend register */ + kSDIO_RegFunctionSelect = 0x0DU, /*!< function select register */ + kSDIO_RegExecutionFlag = 0x0EU, /*!< execution flag register */ + kSDIO_RegReadyFlag = 0x0FU, /*!< ready flag register */ + kSDIO_RegFN0BlockSizeLow = 0x10U, /*!< FN0 block size register */ + kSDIO_RegFN0BlockSizeHigh = 0x11U, /*!< FN0 block size register */ + kSDIO_RegPowerControl = 0x12U, /*!< power control register */ + kSDIO_RegBusSpeed = 0x13U, /*!< bus speed register */ + kSDIO_RegUHSITimingSupport = 0x14U, /*!< UHS-I timing support register */ + kSDIO_RegDriverStrength = 0x15U, /*!< Driver strength register */ + kSDIO_RegInterruptExtension = 0x16U, /*!< Interrupt extension register */ +}; + +/*! @brief sdio card individual commands */ +typedef enum _sdio_command +{ + kSDIO_SendRelativeAddress = 3U, /*!< send relative address */ + kSDIO_SendOperationCondition = 5U, /*!< send operation condition */ + kSDIO_SendInterfaceCondition = 8U, /*!< send interface condition */ + kSDIO_RWIODirect = 52U, /*!< read/write IO direct command */ + kSDIO_RWIOExtended = 53U, /*!< read/write IO extended command */ +} sdio_command_t; + +/*! @brief sdio card individual commands */ +typedef enum _sdio_func_num +{ + kSDIO_FunctionNum0, /*!< sdio function0*/ + kSDIO_FunctionNum1, /*!< sdio function1*/ + kSDIO_FunctionNum2, /*!< sdio function2*/ + kSDIO_FunctionNum3, /*!< sdio function3*/ + kSDIO_FunctionNum4, /*!< sdio function4*/ + kSDIO_FunctionNum5, /*!< sdio function5*/ + kSDIO_FunctionNum6, /*!< sdio function6*/ + kSDIO_FunctionNum7, /*!< sdio function7*/ + kSDIO_FunctionMemory, /*!< for combo card*/ +} sdio_func_num_t; + +#define SDIO_CMD_ARGUMENT_RW_POS (31U) /*!< read/write flag position */ +#define SDIO_CMD_ARGUMENT_FUNC_NUM_POS (28U) /*!< function number position */ +#define SDIO_DIRECT_CMD_ARGUMENT_RAW_POS (27U) /*!< direct raw flag position */ +#define SDIO_CMD_ARGUMENT_REG_ADDR_POS (9U) /*!< direct reg addr position */ +#define SDIO_CMD_ARGUMENT_REG_ADDR_MASK (0x1FFFFU) /*!< direct reg addr mask */ +#define SDIO_DIRECT_CMD_DATA_MASK (0xFFU) /*!< data mask */ + +#define SDIO_EXTEND_CMD_ARGUMENT_BLOCK_MODE_POS (27U) /*!< extended command argument block mode bit position */ +#define SDIO_EXTEND_CMD_ARGUMENT_OP_CODE_POS (26U) /*!< extended command argument OP Code bit position */ +#define SDIO_EXTEND_CMD_BLOCK_MODE_MASK (0x08000000U) /*!< block mode mask */ +#define SDIO_EXTEND_CMD_OP_CODE_MASK (0x04000000U) /*!< op code mask */ +#define SDIO_EXTEND_CMD_COUNT_MASK (0x1FFU) /*!< byte/block count mask */ +#define SDIO_MAX_BLOCK_SIZE (2048U) /*!< max block size */ +#define SDIO_FBR_BASE(x) (x * 0x100U) /*!< function basic register */ +#define SDIO_TPL_CODE_END (0xFFU) /*!< tuple end */ +#define SDIO_TPL_CODE_MANIFID (0x20U) /*!< manufacturer ID */ +#define SDIO_TPL_CODE_FUNCID (0x21U) /*!< function ID */ +#define SDIO_TPL_CODE_FUNCE (0x22U) /*!< function extension tuple*/ +/*! @brief sdio command response flag */ +enum _sdio_status_flag +{ + kSDIO_StatusCmdCRCError = 0x8000U, /*!< the CRC check of the previous cmd fail*/ + kSDIO_StatusIllegalCmd = 0x4000U, /*!< cmd illegal for the card state */ + kSDIO_StatusR6Error = 0x2000U, /*!< special for R6 error status */ + kSDIO_StatusError = 0x0800U, /*!< A general or an unknown error occurred */ + kSDIO_StatusFunctionNumError = 0x0200U, /*!< invail function error */ + kSDIO_StatusOutofRange = 0x0100U, /*!< cmd argument was out of the allowed range*/ +}; + +/*! @brief sdio operation condition flag */ +enum _sdio_ocr_flag +{ + kSDIO_OcrPowerUpBusyFlag = 31, /*!< Power up busy status */ + kSDIO_OcrIONumber = 28, /*!< number of IO function */ + kSDIO_OcrMemPresent = 27, /*!< memory present flag */ + + kSDIO_OcrVdd20_21Flag = 8, /*!< VDD 2.0-2.1 */ + kSDIO_OcrVdd21_22Flag = 9, /*!< VDD 2.1-2.2 */ + kSDIO_OcrVdd22_23Flag = 10, /*!< VDD 2.2-2.3 */ + kSDIO_OcrVdd23_24Flag = 11, /*!< VDD 2.3-2.4 */ + kSDIO_OcrVdd24_25Flag = 12, /*!< VDD 2.4-2.5 */ + kSDIO_OcrVdd25_26Flag = 13, /*!< VDD 2.5-2.6 */ + kSDIO_OcrVdd26_27Flag = 14, /*!< VDD 2.6-2.7 */ + kSDIO_OcrVdd27_28Flag = 15, /*!< VDD 2.7-2.8 */ + kSDIO_OcrVdd28_29Flag = 16, /*!< VDD 2.8-2.9 */ + kSDIO_OcrVdd29_30Flag = 17, /*!< VDD 2.9-3.0 */ + kSDIO_OcrVdd30_31Flag = 18, /*!< VDD 2.9-3.0 */ + kSDIO_OcrVdd31_32Flag = 19, /*!< VDD 3.0-3.1 */ + kSDIO_OcrVdd32_33Flag = 20, /*!< VDD 3.1-3.2 */ + kSDIO_OcrVdd33_34Flag = 21, /*!< VDD 3.2-3.3 */ + kSDIO_OcrVdd34_35Flag = 22, /*!< VDD 3.3-3.4 */ + kSDIO_OcrVdd35_36Flag = 23, /*!< VDD 3.4-3.5 */ +}; +/*! @brief sdio ocr voltage window mask */ +#define SDIO_OCR_VOLTAGE_WINDOW_MASK (0xFFFFU << 8U) + +/*! @brief sdio ocr reigster IO NUMBER mask */ +#define SDIO_OCR_IO_NUM_MASK (7U << kSDIO_OcrIONumber) + +/*! @brief sdio capability flag */ +enum _sdio_capability_flag +{ + kSDIO_CCCRSupportDirectCmdDuringDataTrans = (1U << 0U), /*!< support direct cmd during data transfer */ + kSDIO_CCCRSupportMultiBlock = (1U << 1U), /*!< support multi block mode */ + kSDIO_CCCRSupportReadWait = (1U << 2U), /*!< support read wait */ + kSDIO_CCCRSupportSuspendResume = (1U << 3U), /*!< support suspend resume */ + kSDIO_CCCRSupportIntDuring4BitDataTrans = (1U << 4U), /*!< support interrupt during 4-bit data transfer */ + kSDIO_CCCRSupportLowSpeed1Bit = (1U << 6U), /*!< support low speed 1bit mode */ + kSDIO_CCCRSupportLowSpeed4Bit = (1U << 7U), /*!< support low speed 4bit mode */ + kSDIO_CCCRSupportMasterPowerControl = (1U << 8U), /*!< support master power control */ + kSDIO_CCCRSupportHighSpeed = (1U << 9U), /*!< support high speed */ + kSDIO_CCCRSupportContinuousSPIInt = (1U << 10U), /*!< support continuous SPI interrupt */ +}; +/*! @brief UHS timing mode flag */ +#define SDIO_CCCR_SUPPORT_HIGHSPEED (1u << 9U) +#define SDIO_CCCR_SUPPORT_SDR50 (1U << 11U) +#define SDIO_CCCR_SUPPORT_SDR104 (1U << 12U) +#define SDIO_CCCR_SUPPORT_DDR50 (1U << 13U) +#define SDIO_CCCR_SUPPORT_DRIVER_TYPE_A (1U << 14U) +#define SDIO_CCCR_SUPPORT_DRIVER_TYPE_C (1U << 15U) +#define SDIO_CCCR_SUPPORT_DRIVER_TYPE_D (1U << 16U) +#define SDIO_CCCR_SUPPORT_ASYNC_INT (1U << 17U) + +#define SDIO_CCCR_BUS_SPEED_MASK (7U << 1U) +#define SDIO_CCCR_ENABLE_HIGHSPEED_MODE (1U << 1U) +#define SDIO_CCCR_ENABLE_SDR50_MODE (2U << 1U) +#define SDIO_CCCR_ENABLE_SDR104_MODE (3U << 1U) +#define SDIO_CCCR_ENABLE_DDR50_MODE (4U << 1U) + +/*! @brief Driver type flag */ +#define SDIO_CCCR_DRIVER_TYPE_MASK (3U << 4U) +#define SDIO_CCCR_ENABLE_DRIVER_TYPE_B (0U << 4U) +#define SDIO_CCCR_ENABLE_DRIVER_TYPE_A (1U << 4U) +#define SDIO_CCCR_ENABLE_DRIVER_TYPE_C (2U << 4U) +#define SDIO_CCCR_ENABLE_DRIVER_TYPE_D (3U << 4U) + +/*! @brief aync interrupt flag*/ +#define SDIO_CCCR_ASYNC_INT_MASK (1U) +#define SDIO_CCCR_ENABLE_AYNC_INT (1U << 1U) + +/*! @brief 8 bit data bus flag*/ +#define SDIO_CCCR_SUPPORT_8BIT_BUS (1U << 18U) +#define SDIO_CCCR_SUPPORT_LOW_SPEED_4BIT_BUS (1U << 7U) +/*! @brief sdio fbr flag */ +enum _sdio_fbr_flag +{ + kSDIO_FBRSupportCSA = (1U << 0U), /*!< function support CSA */ + kSDIO_FBRSupportPowerSelection = (1U << 1U), /*!< function support power selection */ +}; + +/*! @brief sdio bus width */ +typedef enum _sdio_bus_width +{ + kSDIO_DataBus1Bit = 0x00U, /*!< 1 bit bus mode */ + kSDIO_DataBus4Bit = 0X02U, /*!< 4 bit bus mode*/ + kSDIO_DataBus8Bit = 0X03U, /*!< 8 bit bus mode*/ +} sdio_bus_width_t; + +/*! @brief MMC card individual commands */ +typedef enum _mmc_command +{ + kMMC_SendOperationCondition = 1U, /*!< Send Operation Condition */ + kMMC_SetRelativeAddress = 3U, /*!< Set Relative Address */ + kMMC_SleepAwake = 5U, /*!< Sleep Awake */ + kMMC_Switch = 6U, /*!< Switch */ + kMMC_SendExtendedCsd = 8U, /*!< Send EXT_CSD */ + kMMC_ReadDataUntilStop = 11U, /*!< Read Data Until Stop */ + kMMC_BusTestRead = 14U, /*!< Test Read */ + kMMC_SendingBusTest = 19U, /*!< test bus width cmd*/ + kMMC_WriteDataUntilStop = 20U, /*!< Write Data Until Stop */ + kMMC_SendTuningBlock = 21U, /*!< MMC sending tuning block */ + kMMC_ProgramCid = 26U, /*!< Program CID */ + kMMC_EraseGroupStart = 35U, /*!< Erase Group Start */ + kMMC_EraseGroupEnd = 36U, /*!< Erase Group End */ + kMMC_FastInputOutput = 39U, /*!< Fast IO */ + kMMC_GoInterruptState = 40U, /*!< Go interrupt State */ +} mmc_command_t; + +/*! @brief MMC card classified as voltage range */ +typedef enum _mmc_classified_voltage +{ + kMMC_ClassifiedVoltageHigh = 0U, /*!< High-voltage MMC card */ + kMMC_ClassifiedVoltageDual = 1U, /*!< Dual-voltage MMC card */ +} mmc_classified_voltage_t; + +/*! @brief MMC card classified as density level */ +typedef enum _mmc_classified_density +{ + kMMC_ClassifiedDensityWithin2GB = 0U, /*!< Density byte is less than or equal 2GB */ + kMMC_ClassifiedDensityHigher2GB = 1U, /* Density byte is higher than 2GB */ +} mmc_classified_density_t; + +/*! @brief The bit mask for VOLTAGE WINDOW 1.70V to 1.95V field in OCR */ +#define MMC_OCR_V170TO195_SHIFT (7U) +/*! @brief The bit mask for VOLTAGE WINDOW 1.70V to 1.95V field in OCR */ +#define MMC_OCR_V170TO195_MASK (0x00000080U) +/*! @brief The bit shift for VOLTAGE WINDOW 2.00V to 2.60V field in OCR */ +#define MMC_OCR_V200TO260_SHIFT (8U) +/*! @brief The bit mask for VOLTAGE WINDOW 2.00V to 2.60V field in OCR */ +#define MMC_OCR_V200TO260_MASK (0x00007F00U) +/*! @brief The bit shift for VOLTAGE WINDOW 2.70V to 3.60V field in OCR */ +#define MMC_OCR_V270TO360_SHIFT (15U) +/*! @brief The bit mask for VOLTAGE WINDOW 2.70V to 3.60V field in OCR */ +#define MMC_OCR_V270TO360_MASK (0x00FF8000U) +/*! @brief The bit shift for ACCESS MODE field in OCR */ +#define MMC_OCR_ACCESS_MODE_SHIFT (29U) +/*! @brief The bit mask for ACCESS MODE field in OCR */ +#define MMC_OCR_ACCESS_MODE_MASK (0x60000000U) +/*! @brief The bit shift for BUSY field in OCR */ +#define MMC_OCR_BUSY_SHIFT (31U) +/*! @brief The bit mask for BUSY field in OCR */ +#define MMC_OCR_BUSY_MASK (1U << MMC_OCR_BUSY_SHIFT) + +/*! @brief MMC card access mode(Access mode in OCR). */ +typedef enum _mmc_access_mode +{ + kMMC_AccessModeByte = 0U, /*!< The card should be accessed as byte */ + kMMC_AccessModeSector = 2U, /*!< The card should be accessed as sector */ +} mmc_access_mode_t; + +/*! @brief MMC card voltage window(VDD voltage window in OCR). */ +typedef enum _mmc_voltage_window +{ + kMMC_VoltageWindowNone = 0U, /*!< voltage window is not define by user*/ + kMMC_VoltageWindow120 = 0x01U, /*!< Voltage window is 1.20V */ + kMMC_VoltageWindow170to195 = 0x02U, /*!< Voltage window is 1.70V to 1.95V */ + kMMC_VoltageWindows270to360 = 0x1FFU, /*!< Voltage window is 2.70V to 3.60V */ +} mmc_voltage_window_t; + +/*! @brief CSD structure version(CSD_STRUCTURE in CSD). */ +typedef enum _mmc_csd_structure_version +{ + kMMC_CsdStrucureVersion10 = 0U, /*!< CSD version No. 1.0 */ + kMMC_CsdStrucureVersion11 = 1U, /*!< CSD version No. 1.1 */ + kMMC_CsdStrucureVersion12 = 2U, /*!< CSD version No. 1.2 */ + kMMC_CsdStrucureVersionInExtcsd = 3U, /*!< Version coded in Extended CSD */ +} mmc_csd_structure_version_t; + +/*! @brief MMC card specification version(SPEC_VERS in CSD). */ +typedef enum _mmc_specification_version +{ + kMMC_SpecificationVersion0 = 0U, /*!< Allocated by MMCA */ + kMMC_SpecificationVersion1 = 1U, /*!< Allocated by MMCA */ + kMMC_SpecificationVersion2 = 2U, /*!< Allocated by MMCA */ + kMMC_SpecificationVersion3 = 3U, /*!< Allocated by MMCA */ + kMMC_SpecificationVersion4 = 4U, /*!< Version 4.1/4.2/4.3/4.41-4.5-4.51-5.0 */ +} mmc_specification_version_t; + +/*! @brief The bit shift for FREQUENCY UNIT field in TRANSFER SPEED(TRAN-SPEED in Extended CSD) */ +#define MMC_TRANSFER_SPEED_FREQUENCY_UNIT_SHIFT (0U) +/*! @brief The bit mask for FRQEUENCY UNIT in TRANSFER SPEED */ +#define MMC_TRANSFER_SPEED_FREQUENCY_UNIT_MASK (0x07U) +/*! @brief The bit shift for MULTIPLIER field in TRANSFER SPEED */ +#define MMC_TRANSFER_SPEED_MULTIPLIER_SHIFT (3U) +/*! @brief The bit mask for MULTIPLIER field in TRANSFER SPEED */ +#define MMC_TRANSFER_SPEED_MULTIPLIER_MASK (0x78U) + +/*! @brief Read the value of FREQUENCY UNIT in TRANSFER SPEED. */ +#define READ_MMC_TRANSFER_SPEED_FREQUENCY_UNIT(CSD) \ + (((CSD.transferSpeed) & MMC_TRANSFER_SPEED_FREQUENCY_UNIT_MASK) >> MMC_TRANSFER_SPEED_FREQUENCY_UNIT_SHIFT) +/*! @brief Read the value of MULTIPLER filed in TRANSFER SPEED. */ +#define READ_MMC_TRANSFER_SPEED_MULTIPLIER(CSD) \ + (((CSD.transferSpeed) & MMC_TRANSFER_SPEED_MULTIPLIER_MASK) >> MMC_TRANSFER_SPEED_MULTIPLIER_SHIFT) + +/*! @brief MMC card Extended CSD fix version(EXT_CSD_REV in Extended CSD) */ +enum _mmc_extended_csd_revision +{ + kMMC_ExtendedCsdRevision10 = 0U, /*!< Revision 1.0 */ + kMMC_ExtendedCsdRevision11 = 1U, /*!< Revision 1.1 */ + kMMC_ExtendedCsdRevision12 = 2U, /*!< Revision 1.2 */ + kMMC_ExtendedCsdRevision13 = 3U, /*!< Revision 1.3 MMC4.3*/ + kMMC_ExtendedCsdRevision14 = 4U, /*!< Revision 1.4 obsolete*/ + kMMC_ExtendedCsdRevision15 = 5U, /*!< Revision 1.5 MMC4.41*/ + kMMC_ExtendedCsdRevision16 = 6U, /*!< Revision 1.6 MMC4.5*/ + kMMC_ExtendedCsdRevision17 = 7U, /*!< Revision 1.7 MMC5.0 */ +}; + +/*! @brief MMC card command set(COMMAND_SET in Extended CSD) */ +typedef enum _mmc_command_set +{ + kMMC_CommandSetStandard = 0U, /*!< Standard MMC */ + kMMC_CommandSet1 = 1U, /*!< Command set 1 */ + kMMC_CommandSet2 = 2U, /*!< Command set 2 */ + kMMC_CommandSet3 = 3U, /*!< Command set 3 */ + kMMC_CommandSet4 = 4U, /*!< Command set 4 */ +} mmc_command_set_t; + +/*! @brief boot support(BOOT_INFO in Extended CSD) */ +enum _mmc_support_boot_mode +{ + kMMC_SupportAlternateBoot = 1U, /*!< support alternative boot mode*/ + kMMC_SupportDDRBoot = 2U, /*!< support DDR boot mode*/ + kMMC_SupportHighSpeedBoot = 4U, /*!< support high speed boot mode*/ +}; +/*! @brief The power class value bit mask when bus in 4 bit mode */ +#define MMC_POWER_CLASS_4BIT_MASK (0x0FU) +/*! @brief The power class current value bit mask when bus in 8 bit mode */ +#define MMC_POWER_CLASS_8BIT_MASK (0xF0U) + +/*! @brief MMC card high-speed timing(HS_TIMING in Extended CSD) */ +typedef enum _mmc_high_speed_timing +{ + kMMC_HighSpeedTimingNone = 0U, /*!< MMC card using none high-speed timing */ + kMMC_HighSpeedTiming = 1U, /*!< MMC card using high-speed timing */ + kMMC_HighSpeed200Timing = 2U, /*!< MMC card high speed 200 timing*/ + kMMC_HighSpeed400Timing = 3U, /*!< MMC card high speed 400 timing*/ +} mmc_high_speed_timing_t; + +/*! @brief The number of data bus width type */ +#define MMC_DATA_BUS_WIDTH_TYPE_NUMBER (3U) +/*! @brief MMC card data bus width(BUS_WIDTH in Extended CSD) */ +typedef enum _mmc_data_bus_width +{ + kMMC_DataBusWidth1bit = 0U, /*!< MMC data bus width is 1 bit */ + kMMC_DataBusWidth4bit = 1U, /*!< MMC data bus width is 4 bits */ + kMMC_DataBusWidth8bit = 2U, /*!< MMC data bus width is 8 bits */ + kMMC_DataBusWidth4bitDDR = 5U, /*!< MMC data bus width is 4 bits ddr */ + kMMC_DataBusWidth8bitDDR = 6U, /*!< MMC data bus width is 8 bits ddr */ +} mmc_data_bus_width_t; + +/*! @brief MMC card boot partition enabled(BOOT_PARTITION_ENABLE in Extended CSD) */ +typedef enum _mmc_boot_partition_enable +{ + kMMC_BootPartitionEnableNot = 0U, /*!< Device not boot enabled (default) */ + kMMC_BootPartitionEnablePartition1 = 1U, /*!< Boot partition 1 enabled for boot */ + kMMC_BootPartitionEnablePartition2 = 2U, /*!< Boot partition 2 enabled for boot */ + kMMC_BootPartitionEnableUserAera = 7U, /*!< User area enabled for boot */ +} mmc_boot_partition_enable_t; + +/*! @brief boot mode configuration + * Note: HS200 & HS400 is not support during BOOT operation. + */ +typedef enum _mmc_boot_timing_mode +{ + kMMC_BootModeSDRWithDefaultTiming = 0U << 3U, /*!< boot mode single data rate with backward compatiable timings */ + kMMC_BootModeSDRWithHighSpeedTiming = 1U << 3U, /*!< boot mode single data rate with high speed timing */ + kMMC_BootModeDDRTiming = 2U << 3U, /*!< boot mode dual date rate */ +} mmc_boot_timing_mode_t; + +/*! @brief MMC card boot partition write protect configurations + * All the bits in BOOT_WP register, except the two R/W bits B_PERM_WP_DIS + * and B_PERM_WP_EN, shall only be written once per power cycle.The protection + * mdde intended for both boot areas will be set with a single write. + */ +typedef enum _mmc_boot_partition_wp +{ + kMMC_BootPartitionWPDisable = 0x50U, /*!< boot partition write protection disable */ + kMMC_BootPartitionPwrWPToBothPartition = + 0x01U, /*!< power on period write protection apply to both boot partitions */ + kMMC_BootPartitionPermWPToBothPartition = 0x04U, /*!< permanent write protection apply to both boot partitions */ + + kMMC_BootPartitionPwrWPToPartition1 = (1U << 7U) | 1U, /*!< power on period write protection apply to partition1 */ + kMMC_BootPartitionPwrWPToPartition2 = (1U << 7U) | 3U, /*!< power on period write protection apply to partition2 */ + + kMMC_BootPartitionPermWPToPartition1 = + (1U << 7U) | (1U << 2U), /*!< permanent write protection apply to partition1 */ + kMMC_BootPartitionPermWPToPartition2 = + (1U << 7U) | (3U << 2U), /*!< permanent write protection apply to partition2 */ + + kMMC_BootPartitionPermWPToPartition1PwrWPToPartition2 = + (1U << 7U) | (1U << 2U) | + 3U, /*!< permanent write protection apply to partition1, power on period write protection apply to partition2 */ + kMMC_BootPartitionPermWPToPartition2PwrWPToPartition1 = + (1U << 7U) | (3U << 2U) | + 1U, /*!< permanent write protection apply to partition2, power on period write protection apply to partition1 */ +} mmc_boot_partition_wp_t; + +/*! @brief MMC card boot partition write protect status */ +enum _mmc_boot_partition_wp_status +{ + kMMC_BootPartitionNotProtected = 0U, /*!< boot partition not protected */ + kMMC_BootPartitionPwrProtected = 1U, /*!< boot partition is power on period write protected */ + kMMC_BootPartitionPermProtected = 2U, /*!< boot partition is permanently protected */ +}; + +/*! @brief MMC card partition to be accessed(BOOT_PARTITION_ACCESS in Extended CSD) */ +typedef enum _mmc_access_partition +{ + kMMC_AccessPartitionUserAera = 0U, /*!< No access to boot partition (default), normal partition */ + kMMC_AccessPartitionBoot1 = 1U, /*!< Read/Write boot partition 1 */ + kMMC_AccessPartitionBoot2 = 2U, /*!< Read/Write boot partition 2*/ + kMMC_AccessRPMB = 3U, /*!< Replay protected mem block */ + kMMC_AccessGeneralPurposePartition1 = 4U, /*!< access to general purpose partition 1 */ + kMMC_AccessGeneralPurposePartition2 = 5U, /*!< access to general purpose partition 2 */ + kMMC_AccessGeneralPurposePartition3 = 6U, /*!< access to general purpose partition 3 */ + kMMC_AccessGeneralPurposePartition4 = 7U, /*!< access to general purpose partition 4 */ +} mmc_access_partition_t; + +/*! @brief The bit shift for PARTITION ACCESS filed in BOOT CONFIG (BOOT_CONFIG in Extend CSD) */ +#define MMC_PARTITION_CONFIG_PARTITION_ACCESS_SHIFT (0U) +/*! @brief The bit mask for PARTITION ACCESS field in BOOT CONFIG */ +#define MMC_PARTITION_CONFIG_PARTITION_ACCESS_MASK (0x00000007U) +/*! @brief The bit shift for PARTITION ENABLE field in BOOT CONFIG */ +#define MMC_PARTITION_CONFIG_PARTITION_ENABLE_SHIFT (3U) +/*! @brief The bit mask for PARTITION ENABLE field in BOOT CONFIG */ +#define MMC_PARTITION_CONFIG_PARTITION_ENABLE_MASK (0x00000038U) +/*! @brief The bit shift for ACK field in BOOT CONFIG */ +#define MMC_PARTITION_CONFIG_BOOT_ACK_SHIFT (6U) +/*! @brief The bit mask for ACK field in BOOT CONFIG */ +#define MMC_PARTITION_CONFIG_BOOT_ACK_MASK (0x00000040U) +/*! @brief The bit shift for BOOT BUS WIDTH field in BOOT CONFIG */ +#define MMC_BOOT_BUS_CONDITION_BUS_WIDTH_SHIFT (0U) +/*! @brief The bit mask for BOOT BUS WIDTH field in BOOT CONFIG */ +#define MMC_BOOT_BUS_CONDITION_BUS_WIDTH_MASK (3U) +/*! @brief The bit shift for BOOT BUS WIDTH RESET field in BOOT CONFIG */ +#define MMC_BOOT_BUS_CONDITION_RESET_BUS_CONDITION_SHIFT (2U) +/*! @brief The bit mask for BOOT BUS WIDTH RESET field in BOOT CONFIG */ +#define MMC_BOOT_BUS_CONDITION_RESET_BUS_CONDITION_MASK (4U) +/*! @brief The bit mask for BOOT BUS WIDTH RESET field in BOOT CONFIG */ +#define MMC_BOOT_BUS_CONDITION_BOOT_MODE_MASK (0x18U) + +/*! @brief MMC card CSD register flags */ +enum _mmc_csd_flag +{ + kMMC_CsdReadBlockPartialFlag = (1U << 0U), /*!< Partial blocks for read allowed */ + kMMC_CsdWriteBlockMisalignFlag = (1U << 1U), /*!< Write block misalignment */ + kMMC_CsdReadBlockMisalignFlag = (1U << 2U), /*!< Read block misalignment */ + kMMC_CsdDsrImplementedFlag = (1U << 3U), /*!< DSR implemented */ + kMMC_CsdWriteProtectGroupEnabledFlag = (1U << 4U), /*!< Write protect group enabled */ + kMMC_CsdWriteBlockPartialFlag = (1U << 5U), /*!< Partial blocks for write allowed */ + kMMC_ContentProtectApplicationFlag = (1U << 6U), /*!< Content protect application */ + kMMC_CsdFileFormatGroupFlag = (1U << 7U), /*!< File format group */ + kMMC_CsdCopyFlag = (1U << 8U), /*!< Copy flag */ + kMMC_CsdPermanentWriteProtectFlag = (1U << 9U), /*!< Permanent write protection */ + kMMC_CsdTemporaryWriteProtectFlag = (1U << 10U), /*!< Temporary write protection */ +}; + +/*! @brief Extended CSD register access mode(Access mode in CMD6). */ +typedef enum _mmc_extended_csd_access_mode +{ + kMMC_ExtendedCsdAccessModeCommandSet = 0U, /*!< Command set related setting */ + kMMC_ExtendedCsdAccessModeSetBits = 1U, /*!< Set bits in specific byte in Extended CSD */ + kMMC_ExtendedCsdAccessModeClearBits = 2U, /*!< Clear bits in specific byte in Extended CSD */ + kMMC_ExtendedCsdAccessModeWriteBits = 3U, /*!< Write a value to specific byte in Extended CSD */ +} mmc_extended_csd_access_mode_t; + +/*! @brief EXT CSD byte index */ +typedef enum _mmc_extended_csd_index +{ + kMMC_ExtendedCsdIndexBootPartitionWP = 173U, /*!< Boot partition write protect */ + kMMC_ExtendedCsdIndexEraseGroupDefinition = 175U, /*!< Erase Group Def */ + kMMC_ExtendedCsdIndexBootBusConditions = 177U, /*!< Boot Bus conditions */ + kMMC_ExtendedCsdIndexBootConfigWP = 178U, /*!< Boot config write protect */ + kMMC_ExtendedCsdIndexPartitionConfig = 179U, /*!< Partition Config, before BOOT_CONFIG */ + kMMC_ExtendedCsdIndexBusWidth = 183U, /*!< Bus Width */ + kMMC_ExtendedCsdIndexHighSpeedTiming = 185U, /*!< High-speed Timing */ + kMMC_ExtendedCsdIndexPowerClass = 187U, /*!< Power Class */ + kMMC_ExtendedCsdIndexCommandSet = 191U, /*!< Command Set */ +} mmc_extended_csd_index_t; + +/*! @brief mmc driver strength */ +enum _mmc_driver_strength +{ + kMMC_DriverStrength0 = 0U, /*!< Driver type0 ,nominal impedance 50ohm */ + kMMC_DriverStrength1 = 1U, /*!< Driver type1 ,nominal impedance 33ohm */ + kMMC_DriverStrength2 = 2U, /*!< Driver type2 ,nominal impedance 66ohm */ + kMMC_DriverStrength3 = 3U, /*!< Driver type3 ,nominal impedance 100ohm */ + kMMC_DriverStrength4 = 4U, /*!< Driver type4 ,nominal impedance 40ohm */ +}; + +/*! @brief mmc extended csd flags*/ +typedef enum _mmc_extended_csd_flags +{ + kMMC_ExtCsdExtPartitionSupport = (1 << 0U), /*!< partitioning support[160] */ + kMMC_ExtCsdEnhancePartitionSupport = (1 << 1U), /*!< partitioning support[160] */ + kMMC_ExtCsdPartitioningSupport = (1 << 2U), /*!< partitioning support[160] */ + kMMC_ExtCsdPrgCIDCSDInDDRModeSupport = (1 << 3U), /*!< CMD26 and CMD27 are support dual data rate [130]*/ + kMMC_ExtCsdBKOpsSupport = (1 << 4U), /*!< background operation feature support [502]*/ + kMMC_ExtCsdDataTagSupport = (1 << 5U), /*!< data tag support[499]*/ + kMMC_ExtCsdModeOperationCodeSupport = (1 << 6U), /*!< mode operation code support[493]*/ +} mmc_extended_csd_flags_t; + +/*! @brief MMC card boot mode */ +enum _mmc_boot_mode +{ + kMMC_BootModeNormal = 0U, /*!< Normal boot */ + kMMC_BootModeAlternative = 1U, /*!< Alternative boot */ +}; + +/*! @brief The length of Extended CSD register, unit as bytes. */ +#define MMC_EXTENDED_CSD_BYTES (512U) + +/*! @brief MMC card default relative address */ +#define MMC_DEFAULT_RELATIVE_ADDRESS (2U) + +/*! @brief SD card product name length united as bytes. */ +#define SD_PRODUCT_NAME_BYTES (5U) + +/*! @brief sdio card FBR register */ +typedef struct _sdio_fbr +{ + uint8_t flags; /*!< current io flags */ + uint8_t ioStdFunctionCode; /*!< current io standard function code */ + uint8_t ioExtFunctionCode; /*!< current io extended function code*/ + uint32_t ioPointerToCIS; /*!< current io pointer to CIS */ + uint32_t ioPointerToCSA; /*!< current io pointer to CSA*/ + uint16_t ioBlockSize; /*!< current io block size */ +} sdio_fbr_t; + +/*! @brief sdio card common CIS */ +typedef struct _sdio_common_cis +{ + /* manufacturer identification string tuple */ + uint16_t mID; /*!< manufacturer code */ + uint16_t mInfo; /*!< manufacturer information */ + + /*function identification tuple */ + uint8_t funcID; /*!< function ID */ + + /* function extension tuple */ + uint16_t fn0MaxBlkSize; /*!< function 0 max block size */ + uint8_t maxTransSpeed; /*!< max data transfer speed for all function */ + +} sdio_common_cis_t; + +/*! @brief sdio card function CIS */ +typedef struct _sdio_func_cis +{ + /*function identification tuple */ + uint8_t funcID; /*!< function ID */ + + /* function extension tuple */ + uint8_t funcInfo; /*!< function info */ + uint8_t ioVersion; /*!< level of application specification this io support */ + uint32_t cardPSN; /*!< product serial number */ + uint32_t ioCSASize; /*!< avaliable CSA size for io */ + uint8_t ioCSAProperty; /*!< CSA property */ + uint16_t ioMaxBlockSize; /*!< io max transfer data size */ + uint32_t ioOCR; /*!< io ioeration condition */ + uint8_t ioOPMinPwr; /*!< min current in operation mode */ + uint8_t ioOPAvgPwr; /*!< average current in operation mode */ + uint8_t ioOPMaxPwr; /*!< max current in operation mode */ + uint8_t ioSBMinPwr; /*!< min current in standby mode */ + uint8_t ioSBAvgPwr; /*!< average current in standby mode */ + uint8_t ioSBMaxPwr; /*!< max current in standby mode */ + + uint16_t ioMinBandWidth; /*!< io min transfer bandwidth */ + uint16_t ioOptimumBandWidth; /*!< io optimum transfer bandwidth */ + uint16_t ioReadyTimeout; /*!< timeout value from enalbe to ready */ + uint16_t ioHighCurrentAvgCurrent; /*!< the average peak current (mA) + when IO operating in high current mode */ + uint16_t ioHighCurrentMaxCurrent; /*!< the max peak current (mA) + when IO operating in high current mode */ + uint16_t ioLowCurrentAvgCurrent; /*!< the average peak current (mA) + when IO operating in lower current mode */ + uint16_t ioLowCurrentMaxCurrent; /*!< the max peak current (mA) + when IO operating in lower current mode */ +} sdio_func_cis_t; + +/*! @brief SD AU start value */ +#define SD_AU_START_VALUE (1U) +/*! @brief SD UHS AU start value */ +#define SD_UHS_AU_START_VALUE (7U) + +/*! @brief SD card status */ +typedef struct _sd_status +{ + uint8_t busWidth; /*!< current buswidth */ + uint8_t secureMode; /*!< secured mode */ + uint16_t cardType; /*!< sdcard type */ + uint32_t protectedSize; /*!< size of protected area */ + uint8_t speedClass; /*!< speed class of card */ + uint8_t performanceMove; /*!< Performance of move indicated by 1[MB/S]step */ + uint8_t auSize; /*!< size of AU */ + uint16_t eraseSize; /*!< number of AUs to be erased at a time */ + uint8_t eraseTimeout; /*!< timeout value for erasing areas specified by UNIT OF ERASE AU */ + uint8_t eraseOffset; /*!< fixed offset value added to erase time */ + uint8_t uhsSpeedGrade; /*!< speed grade for UHS mode */ + uint8_t uhsAuSize; /*!< size of AU for UHS mode */ +} sd_status_t; + +/*! @brief SD card CID register */ +typedef struct _sd_cid +{ + uint8_t manufacturerID; /*!< Manufacturer ID [127:120] */ + uint16_t applicationID; /*!< OEM/Application ID [119:104] */ + uint8_t productName[SD_PRODUCT_NAME_BYTES]; /*!< Product name [103:64] */ + uint8_t productVersion; /*!< Product revision [63:56] */ + uint32_t productSerialNumber; /*!< Product serial number [55:24] */ + uint16_t manufacturerData; /*!< Manufacturing date [19:8] */ +} sd_cid_t; + +/*! @brief SD card CSD register */ +typedef struct _sd_csd +{ + uint8_t csdStructure; /*!< CSD structure [127:126] */ + uint8_t dataReadAccessTime1; /*!< Data read access-time-1 [119:112] */ + uint8_t dataReadAccessTime2; /*!< Data read access-time-2 in clock cycles (NSAC*100) [111:104] */ + uint8_t transferSpeed; /*!< Maximum data transfer rate [103:96] */ + uint16_t cardCommandClass; /*!< Card command classes [95:84] */ + uint8_t readBlockLength; /*!< Maximum read data block length [83:80] */ + uint16_t flags; /*!< Flags in _sd_csd_flag */ + uint32_t deviceSize; /*!< Device size [73:62] */ + /* Following fields from 'readCurrentVddMin' to 'deviceSizeMultiplier' exist in CSD version 1 */ + uint8_t readCurrentVddMin; /*!< Maximum read current at VDD min [61:59] */ + uint8_t readCurrentVddMax; /*!< Maximum read current at VDD max [58:56] */ + uint8_t writeCurrentVddMin; /*!< Maximum write current at VDD min [55:53] */ + uint8_t writeCurrentVddMax; /*!< Maximum write current at VDD max [52:50] */ + uint8_t deviceSizeMultiplier; /*!< Device size multiplier [49:47] */ + + uint8_t eraseSectorSize; /*!< Erase sector size [45:39] */ + uint8_t writeProtectGroupSize; /*!< Write protect group size [38:32] */ + uint8_t writeSpeedFactor; /*!< Write speed factor [28:26] */ + uint8_t writeBlockLength; /*!< Maximum write data block length [25:22] */ + uint8_t fileFormat; /*!< File format [11:10] */ +} sd_csd_t; + +/*! @brief The bit shift for RATE UNIT field in TRANSFER SPEED */ +#define SD_TRANSFER_SPEED_RATE_UNIT_SHIFT (0U) +/*! @brief The bit mask for RATE UNIT field in TRANSFER SPEED */ +#define SD_TRANSFER_SPEED_RATE_UNIT_MASK (0x07U) +/*! @brief The bit shift for TIME VALUE field in TRANSFER SPEED */ +#define SD_TRANSFER_SPEED_TIME_VALUE_SHIFT (2U) +/*! @brief The bit mask for TIME VALUE field in TRANSFER SPEED */ +#define SD_TRANSFER_SPEED_TIME_VALUE_MASK (0x78U) +/*! @brief Read the value of FREQUENCY UNIT in TRANSFER SPEED field */ +#define SD_RD_TRANSFER_SPEED_RATE_UNIT(x) \ + (((x.transferSpeed) & SD_TRANSFER_SPEED_RATE_UNIT_MASK) >> SD_TRANSFER_SPEED_RATE_UNIT_SHIFT) +/*! @brief Read the value of TIME VALUE in TRANSFER SPEED field */ +#define SD_RD_TRANSFER_SPEED_TIME_VALUE(x) \ + (((x.transferSpeed) & SD_TRANSFER_SPEED_TIME_VALUE_MASK) >> SD_TRANSFER_SPEED_TIME_VALUE_SHIFT) + +/*! @brief SD card SCR register */ +typedef struct _sd_scr +{ + uint8_t scrStructure; /*!< SCR Structure [63:60] */ + uint8_t sdSpecification; /*!< SD memory card specification version [59:56] */ + uint16_t flags; /*!< SCR flags in _sd_scr_flag */ + uint8_t sdSecurity; /*!< Security specification supported [54:52] */ + uint8_t sdBusWidths; /*!< Data bus widths supported [51:48] */ + uint8_t extendedSecurity; /*!< Extended security support [46:43] */ + uint8_t commandSupport; /*!< Command support bits [33:32] 33-support CMD23, 32-support cmd20*/ + uint32_t reservedForManufacturer; /*!< reserved for manufacturer usage [31:0] */ +} sd_scr_t; + +/*! @brief MMC card product name length united as bytes. */ +#define MMC_PRODUCT_NAME_BYTES (6U) +/*! @brief MMC card CID register. */ +typedef struct _mmc_cid +{ + uint8_t manufacturerID; /*!< Manufacturer ID */ + uint16_t applicationID; /*!< OEM/Application ID */ + uint8_t productName[MMC_PRODUCT_NAME_BYTES]; /*!< Product name */ + uint8_t productVersion; /*!< Product revision */ + uint32_t productSerialNumber; /*!< Product serial number */ + uint8_t manufacturerData; /*!< Manufacturing date */ +} mmc_cid_t; + +/*! @brief MMC card CSD register. */ +typedef struct _mmc_csd +{ + uint8_t csdStructureVersion; /*!< CSD structure [127:126] */ + uint8_t systemSpecificationVersion; /*!< System specification version [125:122] */ + uint8_t dataReadAccessTime1; /*!< Data read access-time 1 [119:112] */ + uint8_t dataReadAccessTime2; /*!< Data read access-time 2 in CLOCK cycles (NSAC*100) [111:104] */ + uint8_t transferSpeed; /*!< Max. bus clock frequency [103:96] */ + uint16_t cardCommandClass; /*!< card command classes [95:84] */ + uint8_t readBlockLength; /*!< Max. read data block length [83:80] */ + uint16_t flags; /*!< Contain flags in _mmc_csd_flag */ + uint16_t deviceSize; /*!< Device size [73:62] */ + uint8_t readCurrentVddMin; /*!< Max. read current @ VDD min [61:59] */ + uint8_t readCurrentVddMax; /*!< Max. read current @ VDD max [58:56] */ + uint8_t writeCurrentVddMin; /*!< Max. write current @ VDD min [55:53] */ + uint8_t writeCurrentVddMax; /*!< Max. write current @ VDD max [52:50] */ + uint8_t deviceSizeMultiplier; /*!< Device size multiplier [49:47] */ + uint8_t eraseGroupSize; /*!< Erase group size [46:42] */ + uint8_t eraseGroupSizeMultiplier; /*!< Erase group size multiplier [41:37] */ + uint8_t writeProtectGroupSize; /*!< Write protect group size [36:32] */ + uint8_t defaultEcc; /*!< Manufacturer default ECC [30:29] */ + uint8_t writeSpeedFactor; /*!< Write speed factor [28:26] */ + uint8_t maxWriteBlockLength; /*!< Max. write data block length [25:22] */ + uint8_t fileFormat; /*!< File format [11:10] */ + uint8_t eccCode; /*!< ECC code [9:8] */ +} mmc_csd_t; + +/*! @brief MMC card Extended CSD register (unit: byte). */ +typedef struct _mmc_extended_csd +{ + /*uint8_t SecureRemoveType;*/ /*!< secure removal type[16]*/ + /*uint8_t enProductStateAware;*/ /*!< product state awareness enablement[17]*/ + /*uint32_t maxPreLoadDataSize;*/ /*!< max preload data size[21-18]*/ + /*uint32_t preLoadDataSize;*/ /*!< pre-load data size[25-22]*/ + /*uint8_t ffuStatus;*/ /*!< FFU status [26]*/ + /*uint8_t modeOperationCode;*/ /*!< mode operation code[29]*/ + /*uint8_t modeConfig;*/ /*!< mode config [30]*/ + /*uint8_t cacheCtrl;*/ /*!< control to turn on/off cache[33]*/ + /*uint8_t pwroffNotify;*/ /*!< power off notification[34]*/ + /*uint8_t packedCmdFailIndex;*/ /*!< packed cmd fail index [35]*/ + /*uint8_t packedCmdStatus;*/ /*!< packed cmd status[36]*/ + /*uint32_t contextConfig[4U];*/ /*!< context configuration[51-37]*/ + /*uint16_t extPartitionAttr;*/ /*!< extended partitions attribut[53-52]*/ + /*uint16_t exceptEventStatus;*/ /*!< exception events status[55-54]*/ + /*uint16_t exceptEventControl;*/ /*!< exception events control[57-56]*/ + /*uint8_t toReleaseAddressedGroup;*/ /*!< number of group to be released[58]*/ + /*uint8_t class6CmdCtrl;*/ /*!< class 6 command control[59]*/ + /*uint8_t intTimeoutEmu;*/ /*!< 1st initiallization after disabling sector size emu[60]*/ + /*uint8_t sectorSize;*/ /*!< sector size[61] */ + /*uint8_t sectorSizeEmu;*/ /*!< sector size emulation[62]*/ + /*uint8_t nativeSectorSize;*/ /*!< native sector size[63]*/ + /*uint8_t periodWakeup;*/ /*!< period wakeup [131]*/ + /*uint8_t tCASESupport;*/ /*!< package case temperature is controlled[132]*/ + /*uint8_t productionStateAware;*/ /*!< production state awareness[133]*/ + /*uint32_t enhanceUsrDataStartAddr;*/ /*!< enhanced user data start addr [139-136]*/ + /*uint32_t enhanceUsrDataSize;*/ /*!< enhanced user data area size[142-140]*/ + /*uint32_t generalPartitionSize[3];*/ /*!< general purpose partition size[154-143]*/ + uint8_t partitionAttribute; /*!< partition attribute [156]*/ + /*uint32_t maxEnhanceAreaSize;*/ /*!< max enhance area size [159-157]*/ + /*uint8_t hpiManagementEn;*/ /*!< HPI management [161]*/ + /*uint8_t writeReliabilityParameter;*/ /*!< write reliability parameter register[166] */ + /*uint8_t writeReliabilitySet;*/ /*!< write reliability setting register[167] */ + /*uint8_t rpmbSizeMult;*/ /*!< RPMB size multi [168]*/ + /*uint8_t fwConfig;*/ /*!< FW configuration[169]*/ + uint8_t userWP; /*!< user write protect register[171] */ + uint8_t bootPartitionWP; /*!< boot write protect register[173]*/ + uint8_t bootWPStatus; /*!< boot write protect status register[174]*/ + uint8_t highDensityEraseGroupDefinition; /*!< High-density erase group definition [175] */ + uint8_t bootDataBusConditions; /*!< Boot bus conditions [177] */ + uint8_t bootConfigProtect; /*!< Boot config protection [178]*/ + uint8_t partitionConfig; /*!< Boot configuration [179] */ + uint8_t eraseMemoryContent; /*!< Erased memory content [181] */ + uint8_t dataBusWidth; /*!< Data bus width mode [183] */ + uint8_t highSpeedTiming; /*!< High-speed interface timing [185] */ + uint8_t powerClass; /*!< Power class [187] */ + uint8_t commandSetRevision; /*!< Command set revision [189] */ + uint8_t commandSet; /*!< Command set [191] */ + uint8_t extendecCsdVersion; /*!< Extended CSD revision [192] */ + uint8_t csdStructureVersion; /*!< CSD structure version [194] */ + uint8_t cardType; /*!< Card Type [196] */ + uint8_t ioDriverStrength; /*!< IO driver strength [197] */ + /*uint8_t OutofInterruptBusyTiming;*/ /*!< out of interrupt busy timing [198] */ + /*uint8_t partitionSwitchTiming;*/ /*!< partition switch timing [199] */ + uint8_t powerClass52MHz195V; /*!< Power Class for 52MHz @ 1.95V [200] */ + uint8_t powerClass26MHz195V; /*!< Power Class for 26MHz @ 1.95V [201] */ + uint8_t powerClass52MHz360V; /*!< Power Class for 52MHz @ 3.6V [202] */ + uint8_t powerClass26MHz360V; /*!< Power Class for 26MHz @ 3.6V [203] */ + uint8_t minimumReadPerformance4Bit26MHz; /*!< Minimum Read Performance for 4bit at 26MHz [205] */ + uint8_t minimumWritePerformance4Bit26MHz; /*!< Minimum Write Performance for 4bit at 26MHz [206] */ + uint8_t minimumReadPerformance8Bit26MHz4Bit52MHz; + /*!< Minimum read Performance for 8bit at 26MHz/4bit @52MHz [207] */ + uint8_t minimumWritePerformance8Bit26MHz4Bit52MHz; + /*!< Minimum Write Performance for 8bit at 26MHz/4bit @52MHz [208] */ + uint8_t minimumReadPerformance8Bit52MHz; /*!< Minimum Read Performance for 8bit at 52MHz [209] */ + uint8_t minimumWritePerformance8Bit52MHz; /*!< Minimum Write Performance for 8bit at 52MHz [210] */ + uint32_t sectorCount; /*!< Sector Count [215:212] */ + /*uint8_t sleepNotificationTimeout;*/ /*!< sleep notification timeout [216]*/ + uint8_t sleepAwakeTimeout; /*!< Sleep/awake timeout [217] */ + /*uint8_t productionStateAwareTimeout;*/ /*!< Production state awareness timeout [218]*/ + uint8_t sleepCurrentVCCQ; /*!< Sleep current (VCCQ) [219] */ + uint8_t sleepCurrentVCC; /*!< Sleep current (VCC) [220] */ + uint8_t highCapacityWriteProtectGroupSize; /*!< High-capacity write protect group size [221] */ + uint8_t reliableWriteSectorCount; /*!< Reliable write sector count [222] */ + uint8_t highCapacityEraseTimeout; /*!< High-capacity erase timeout [223] */ + uint8_t highCapacityEraseUnitSize; /*!< High-capacity erase unit size [224] */ + uint8_t accessSize; /*!< Access size [225] */ + /*uint8_t secureTrimMultiplier;*/ /*!< secure trim multiplier[229]*/ + /*uint8_t secureEraseMultiplier;*/ /*!< secure erase multiplier[230]*/ + /*uint8_t secureFeatureSupport;*/ /*!< secure feature support[231]*/ + /*uint32_t trimMultiplier;*/ /*!< trim multiplier[232]*/ + uint8_t minReadPerformance8bitAt52MHZDDR; /*!< Minimum read performance for 8bit at DDR 52MHZ[234]*/ + uint8_t minWritePerformance8bitAt52MHZDDR; /*!< Minimum write performance for 8bit at DDR 52MHZ[235]*/ + uint8_t powerClass200MHZVCCQ130VVCC360V; /*!< power class for 200MHZ, at VCCQ= 1.3V,VCC=3.6V[236]*/ + uint8_t powerClass200MHZVCCQ195VVCC360V; /*!< power class for 200MHZ, at VCCQ= 1.95V,VCC=3.6V[237]*/ + uint8_t powerClass52MHZDDR195V; /*!< power class for 52MHZ,DDR at Vcc 1.95V[238]*/ + uint8_t powerClass52MHZDDR360V; /*!< power class for 52MHZ,DDR at Vcc 3.6V[239]*/ + /*uint8_t iniTimeoutAP;*/ /*!< 1st initialization time after partitioning[241]*/ + /*uint32_t correctPrgSectorNum;*/ /*!< correct prg sectors number[245-242]*/ + /*uint8_t bkOpsStatus;*/ /*!< background operations status[246]*/ + /*uint8_t powerOffNotifyTimeout;*/ /*!< power off notification timeout[247]*/ + /*uint8_t genericCMD6Timeout;*/ /*!< generic CMD6 timeout[248]*/ + uint32_t cacheSize; /*!< cache size[252-249]*/ + uint8_t powerClass200MHZDDR360V; /*!< power class for 200MHZ, DDR at VCC=2.6V[253]*/ + /*uint32_t fwVer[2U];*/ /*!< fw VERSION [261-254]*/ + /*uint16_t deviceVer;*/ /*!< device version[263-262]*/ + /*uint8_t optimalTrimSize;*/ /*!< optimal trim size[264]*/ + /*uint8_t optimalWriteSize;*/ /*!< optimal write size[265]*/ + /*uint8_t optimalReadSize;*/ /*!< optimal read size[266]*/ + /*uint8_t preEolInfo;*/ /*!< pre EOL information[267]*/ + /*uint8_t deviceLifeTimeEstimationA;*/ /*!< device life time estimation typeA[268]*/ + /*uint8_t deviceLifeTimeEstimationB;*/ /*!< device life time estimation typeB[269]*/ + /*uint32_t correctPrgFWSectorNum;*/ /*!< number of FW sectors correctly programmed[305-302]*/ + /*uint32_t ffuArg;*/ /*!< FFU argument[490-487]*/ + /*uint8_t operationCodeTimeout;*/ /*!< operation code timeout[491]*/ + /*uint8_t supportMode;*/ /*!< support mode [493]*/ + uint8_t extPartitionSupport; /*!< extended partition attribute support[494]*/ + /*uint8_t largeUnitSize;*/ /*!< large unit size[495]*/ + /*uint8_t contextManageCap;*/ /*!< context management capability[496]*/ + /*uint8_t tagResourceSize;*/ /*!< tag resource size[497]*/ + /*uint8_t tagUnitSize;*/ /*!< tag unit size[498]*/ + /*uint8_t maxPackedWriteCmd;*/ /*!< max packed write cmd[500]*/ + /*uint8_t maxPackedReadCmd;*/ /*!< max packed read cmd[501]*/ + /*uint8_t hpiFeature;*/ /*!< HPI feature[503]*/ + uint8_t supportedCommandSet; /*!< Supported Command Sets [504] */ + /*uint8_t extSecurityCmdError;*/ /*!< extended security commands error[505]*/ +} mmc_extended_csd_t; + +/*! @brief The bit shift for COMMAND SET field in SWITCH command. */ +#define MMC_SWITCH_COMMAND_SET_SHIFT (0U) +/*! @brief The bit mask for COMMAND set field in SWITCH command. */ +#define MMC_SWITCH_COMMAND_SET_MASK (0x00000007U) +/*! @brief The bit shift for VALUE field in SWITCH command */ +#define MMC_SWITCH_VALUE_SHIFT (8U) +/*! @brief The bit mask for VALUE field in SWITCH command */ +#define MMC_SWITCH_VALUE_MASK (0x0000FF00U) +/*! @brief The bit shift for BYTE INDEX field in SWITCH command */ +#define MMC_SWITCH_BYTE_INDEX_SHIFT (16U) +/*! @brief The bit mask for BYTE INDEX field in SWITCH command */ +#define MMC_SWITCH_BYTE_INDEX_MASK (0x00FF0000U) +/*! @brief The bit shift for ACCESS MODE field in SWITCH command */ +#define MMC_SWITCH_ACCESS_MODE_SHIFT (24U) +/*! @brief The bit mask for ACCESS MODE field in SWITCH command */ +#define MMC_SWTICH_ACCESS_MODE_MASK (0x03000000U) + +/*! @brief MMC Extended CSD configuration. */ +typedef struct _mmc_extended_csd_config +{ + mmc_command_set_t commandSet; /*!< Command set */ + uint8_t ByteValue; /*!< The value to set */ + uint8_t ByteIndex; /*!< The byte index in Extended CSD(mmc_extended_csd_index_t) */ + mmc_extended_csd_access_mode_t accessMode; /*!< Access mode */ +} mmc_extended_csd_config_t; + +/*! @brief MMC card boot configuration definition. */ +typedef struct _mmc_boot_config +{ + bool enableBootAck; /*!< Enable boot ACK */ + mmc_boot_partition_enable_t bootPartition; /*!< Boot partition */ + + mmc_boot_timing_mode_t bootTimingMode; /*!< boot mode */ + mmc_data_bus_width_t bootDataBusWidth; /*!< Boot data bus width */ + bool retainBootbusCondition; /*!< If retain boot bus width and boot mode conditions */ + + bool pwrBootConfigProtection; /*!< Disable the change of boot configuration register bits from at this point + until next power cycle or next H/W reset operation */ + bool premBootConfigProtection; /*!< Disable the change of boot configuration register bits permanently */ + + mmc_boot_partition_wp_t bootPartitionWP; /*!< boot partition write protect configurations */ + +} mmc_boot_config_t; + +/* @} */ + +#endif /* _FSL_SDMMC_SPEC_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/port/fsl_sdmmc_event.h b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/port/fsl_sdmmc_event.h new file mode 100644 index 000000000..de5a8f946 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/port/fsl_sdmmc_event.h @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_SDMMC_EVENT_H_ +#define _FSL_SDMMC_EVENT_H_ + +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief Event type */ +typedef enum _sdmmc_event +{ + kSDMMCEVENT_TransferComplete = 0U, /*!< Transfer complete event */ + kSDMMCEVENT_CardDetect = 1U, /*!< Card detect event */ +} sdmmc_event_t; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Event Function + * @{ + */ + +/*! + * @brief Initialize timer to implement wait event timeout. + */ +void SDMMCEVENT_InitTimer(void); + +/* Callback function for SDHC */ + +/*! + * @brief Create event. + * @param eventType The event type + * @retval true Create event successfully. + * @retval false Create event failed. + */ +bool SDMMCEVENT_Create(sdmmc_event_t eventType); + +/*! + * @brief Wait event. + * + * @param eventType The event type + * @param timeoutMilliseconds Timeout time in milliseconds. + * @retval true Wait event successfully. + * @retval false Wait event failed. + */ +bool SDMMCEVENT_Wait(sdmmc_event_t eventType, uint32_t timeoutMilliseconds); + +/*! + * @brief Notify event. + * @param eventType The event type + * @retval true Notify event successfully. + * @retval false Notify event failed. + */ +bool SDMMCEVENT_Notify(sdmmc_event_t eventType); + +/*! + * @brief Delete event. + * @param eventType The event type + */ +void SDMMCEVENT_Delete(sdmmc_event_t eventType); + +/*! + * @brief sdmmc delay. + * @param milliseconds time to delay + */ +void SDMMCEVENT_Delay(uint32_t milliseconds); + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +#endif /* _FSL_SDMMC_EVENT_H_*/ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/port/sdif/freertos/fsl_sdmmc_event.c b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/port/sdif/freertos/fsl_sdmmc_event.c new file mode 100644 index 000000000..4a01760e3 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/port/sdif/freertos/fsl_sdmmc_event.c @@ -0,0 +1,152 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include "FreeRTOS.h" +#include "event_groups.h" +#include "fsl_sdmmc_event.h" +#include "semphr.h" + +/******************************************************************************* + * Definitons + ******************************************************************************/ +/*! @brief Convert the milliseconds to ticks in FreeRTOS. */ +#define MSEC_TO_TICK(msec) \ + (((uint32_t)(msec) + 500uL / (uint32_t)configTICK_RATE_HZ) * (uint32_t)configTICK_RATE_HZ / 1000uL) + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Get event instance. + * @param eventType The event type + * @return The event instance's pointer. + */ +static SemaphoreHandle_t *SDMMCEVENT_GetInstance(sdmmc_event_t eventType); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Transfer complete event. */ +static SemaphoreHandle_t g_eventTransferComplete; +/*! @brief Card detect event. */ +static SemaphoreHandle_t g_eventCardDetect; + +/******************************************************************************* + * Code + ******************************************************************************/ +static SemaphoreHandle_t *SDMMCEVENT_GetInstance(sdmmc_event_t eventType) +{ + SemaphoreHandle_t *event; + + switch (eventType) + { + case kSDMMCEVENT_TransferComplete: + event = &g_eventTransferComplete; + break; + case kSDMMCEVENT_CardDetect: + event = &g_eventCardDetect; + break; + default: + event = NULL; + break; + } + + return event; +} + +bool SDMMCEVENT_Create(sdmmc_event_t eventType) +{ + SemaphoreHandle_t *event = SDMMCEVENT_GetInstance(eventType); + + if (event) + { + *event = xSemaphoreCreateBinary(); + if (*event == NULL) + { + return false; + } + + return true; + } + else + { + return false; + } +} + +bool SDMMCEVENT_Wait(sdmmc_event_t eventType, uint32_t timeoutMilliseconds) +{ + uint32_t timeoutTicks; + SemaphoreHandle_t *event = SDMMCEVENT_GetInstance(eventType); + + if (timeoutMilliseconds && event && (*event != 0U)) + { + if (timeoutMilliseconds == ~0U) + { + timeoutTicks = portMAX_DELAY; + } + else + { + timeoutTicks = MSEC_TO_TICK(timeoutMilliseconds); + } + if (xSemaphoreTake(*event, timeoutTicks) == pdFALSE) + { + return false; /* timeout */ + } + else + { + return true; /* event taken */ + } + } + else + { + return false; + } +} + +bool SDMMCEVENT_Notify(sdmmc_event_t eventType) +{ + SemaphoreHandle_t *event = SDMMCEVENT_GetInstance(eventType); + BaseType_t xHigherPriorityTaskWoken = pdFALSE; + BaseType_t xResult = pdFAIL; + + if (event && (*event != 0U)) + { + xResult = xSemaphoreGiveFromISR(*event, &xHigherPriorityTaskWoken); + if (xResult != pdFAIL) + { + portYIELD_FROM_ISR(xHigherPriorityTaskWoken); + return true; + } + else + { + return false; + } + } + else + { + return false; + } +} + +void SDMMCEVENT_Delete(sdmmc_event_t eventType) +{ + SemaphoreHandle_t *event = SDMMCEVENT_GetInstance(eventType); + + if (event && (*event != 0U)) + { + vSemaphoreDelete(*event); + } +} + +void SDMMCEVENT_Delay(uint32_t milliseconds) +{ + vTaskDelay(MSEC_TO_TICK(milliseconds)); +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/port/sdif/freertos/fsl_sdmmc_host.c b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/port/sdif/freertos/fsl_sdmmc_host.c new file mode 100644 index 000000000..c499b2c6d --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/port/sdif/freertos/fsl_sdmmc_host.c @@ -0,0 +1,296 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_sdmmc_host.h" +#include "fsl_sdmmc_event.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief SDMMCHOST detect card insert status by host controller. + * @param base host base address. + * @param userData user can register a application card insert callback through userData. + */ +static void SDMMCHOST_DetectCardInsertByHost(SDMMCHOST_TYPE *base, void *userData); + +/*! + * @brief SDMMCHOST detect card remove status by host controller. + * @param base host base address. + * @param userData user can register a application card insert callback through userData. + */ +static void SDMMCHOST_DetectCardRemoveByHost(SDMMCHOST_TYPE *base, void *userData); + +/*! + * @brief SDMMCHOST transfer function. + * @param base host base address. + * @param content transfer configurations. + */ +static status_t SDMMCHOST_TransferFunction(SDMMCHOST_TYPE *base, SDMMCHOST_TRANSFER *content); + +/*! + * @brief SDMMCHOST transfer complete callback. + * @param base host base address. + * @param handle host handle. + * @param status interrupt status. + * @param userData user data. + */ +static void SDMMCHOST_TransferCompleteCallback(SDMMCHOST_TYPE *base, void *handle, status_t status, void *userData); +/*! + * @brief card detect deinit function. + */ +static void SDMMCHOST_CardDetectDeinit(void); + +/*! + * @brief card detect deinit function. + * @param host base address. + * @param host detect card configuration. + */ +static status_t SDMMCHOST_CardDetectInit(SDMMCHOST_TYPE *base, const sdmmchost_detect_card_t *cd); + +/******************************************************************************* + * Variables + ******************************************************************************/ +static sdif_handle_t s_sdifHandle; +static uint32_t s_sdifDmaTable[SDIF_DMA_TABLE_WORDS]; +static volatile bool s_sdifTransferSuccessFlag = true; +/*! @brief Card detect flag. */ +static volatile bool s_sdInsertedFlag = false; +/******************************************************************************* + * Code + ******************************************************************************/ +static void SDMMCHOST_TransferCompleteCallback(SDMMCHOST_TYPE *base, void *handle, status_t status, void *userData) +{ + /* receive the right status, notify the event */ + if (status == kStatus_Success) + { + s_sdifTransferSuccessFlag = true; + } + else + { + s_sdifTransferSuccessFlag = false; + } + SDMMCEVENT_Notify(kSDMMCEVENT_TransferComplete); +} + +static status_t SDMMCHOST_TransferFunction(SDMMCHOST_TYPE *base, SDMMCHOST_TRANSFER *content) +{ + status_t error = kStatus_Success; + + sdif_dma_config_t dmaConfig; + + memset(s_sdifDmaTable, 0, sizeof(s_sdifDmaTable)); + memset(&dmaConfig, 0, sizeof(dmaConfig)); + + /* user DMA mode transfer data */ + if (content->data != NULL) + { + dmaConfig.enableFixBurstLen = false; + dmaConfig.mode = kSDIF_DualDMAMode; + dmaConfig.dmaDesBufferStartAddr = s_sdifDmaTable; + dmaConfig.dmaDesBufferLen = SDIF_DMA_TABLE_WORDS; + dmaConfig.dmaDesSkipLen = 0U; + } + + do + { + error = SDIF_TransferNonBlocking(base, &s_sdifHandle, &dmaConfig, content); + } while (error == kStatus_SDIF_SyncCmdTimeout); + + if ((error != kStatus_Success) || + (false == SDMMCEVENT_Wait(kSDMMCEVENT_TransferComplete, SDMMCHOST_TRANSFER_COMPLETE_TIMEOUT)) || + (!s_sdifTransferSuccessFlag)) + { + error = kStatus_Fail; + } + + return error; +} + +static void SDMMCHOST_DetectCardInsertByHost(SDIF_Type *base, void *userData) +{ + s_sdInsertedFlag = true; + SDMMCEVENT_Notify(kSDMMCEVENT_CardDetect); + /* application callback */ + if (userData && (((sdmmhostcard_usr_param_t *)userData)->cd) && + ((sdmmhostcard_usr_param_t *)userData)->cd->cardInserted) + { + ((sdmmhostcard_usr_param_t *)userData) + ->cd->cardInserted(true, ((sdmmhostcard_usr_param_t *)userData)->cd->userData); + } +} + +static void SDMMCHOST_DetectCardRemoveByHost(SDIF_Type *base, void *userData) +{ + s_sdInsertedFlag = false; + /* application callback */ + if (userData && (((sdmmhostcard_usr_param_t *)userData)->cd) && + ((sdmmhostcard_usr_param_t *)userData)->cd->cardRemoved) + { + ((sdmmhostcard_usr_param_t *)userData) + ->cd->cardRemoved(false, ((sdmmhostcard_usr_param_t *)userData)->cd->userData); + } +} + +static status_t SDMMCHOST_CardDetectInit(SDMMCHOST_TYPE *base, const sdmmchost_detect_card_t *cd) +{ + sdmmchost_detect_card_type_t cdType = kSDMMCHOST_DetectCardByHostCD; + + if (cd != NULL) + { + cdType = cd->cdType; + } + + /* for interrupt case, only kSDMMCHOST_DetectCardByHostCD can generate interrupt, so implement it only */ + if (cdType != kSDMMCHOST_DetectCardByHostCD) + { + return kStatus_Fail; + } + + if (!SDMMCEVENT_Create(kSDMMCEVENT_CardDetect)) + { + return kStatus_Fail; + } + /* enable the card detect interrupt */ + SDMMCHOST_CARD_DETECT_INSERT_ENABLE(base); + /* check if card is inserted */ + if (SDMMCHOST_CARD_DETECT_INSERT_STATUS(base, false)) + { + s_sdInsertedFlag = true; + /* application callback */ + if (cd && cd->cardInserted) + { + cd->cardInserted(true, cd->userData); + } + } + + return kStatus_Success; +} + +static void SDMMCHOST_CardDetectDeinit(void) +{ + SDMMCEVENT_Delete(kSDMMCEVENT_CardDetect); + s_sdInsertedFlag = false; +} + +void SDMMCHOST_Delay(uint32_t milliseconds) +{ + SDMMCEVENT_Delay(milliseconds); +} + +status_t SDMMCHOST_WaitCardDetectStatus(SDMMCHOST_TYPE *base, const sdmmchost_detect_card_t *cd, bool waitCardStatus) +{ + uint32_t timeout = SDMMCHOST_CARD_DETECT_TIMEOUT; + + if (cd != NULL) + { + timeout = cd->cdTimeOut_ms; + } + + if (waitCardStatus != s_sdInsertedFlag) + { + /* Wait card inserted. */ + do + { + if (!SDMMCEVENT_Wait(kSDMMCEVENT_CardDetect, timeout)) + { + return kStatus_Fail; + } + } while (waitCardStatus != s_sdInsertedFlag); + } + + return kStatus_Success; +} + +bool SDMMCHOST_IsCardPresent(void) +{ + return s_sdInsertedFlag; +} + +void SDMMCHOST_PowerOffCard(SDMMCHOST_TYPE *base, const sdmmchost_pwr_card_t *pwr) +{ + if (pwr != NULL) + { + pwr->powerOff(); + SDMMCHOST_Delay(pwr->powerOffDelay_ms); + } + else + { + /* disable the card power */ + SDIF_EnableCardPower(base, false); + /* Delay several milliseconds to make card stable. */ + SDMMCHOST_Delay(500U); + } +} + +void SDMMCHOST_PowerOnCard(SDMMCHOST_TYPE *base, const sdmmchost_pwr_card_t *pwr) +{ + /* use user define the power on function */ + if (pwr != NULL) + { + pwr->powerOn(); + SDMMCHOST_Delay(pwr->powerOnDelay_ms); + } + else + { + /* Enable the card power */ + SDIF_EnableCardPower(base, true); + /* Delay several milliseconds to make card stable. */ + SDMMCHOST_Delay(500U); + } +} + +status_t SDMMCHOST_Init(SDMMCHOST_CONFIG *host, void *userData) +{ + sdif_transfer_callback_t sdifCallback = {0}; + sdif_host_t *sdifHost = (sdif_host_t *)host; + + /* Initialize SDIF. */ + sdifHost->config.endianMode = kSDMMCHOST_EndianModeLittle; + sdifHost->config.responseTimeout = 0xFFU; + sdifHost->config.cardDetDebounce_Clock = 0xFFFFFFU; + sdifHost->config.dataTimeout = 0xFFFFFFU; + SDIF_Init(sdifHost->base, &(sdifHost->config)); + + /* Set callback for SDHC driver. */ + sdifCallback.TransferComplete = SDMMCHOST_TransferCompleteCallback; + sdifCallback.cardInserted = SDMMCHOST_DetectCardInsertByHost; + sdifCallback.cardRemoved = SDMMCHOST_DetectCardRemoveByHost; + /* Create handle for SDHC driver */ + SDIF_TransferCreateHandle(sdifHost->base, &s_sdifHandle, &sdifCallback, userData); + + /* Create transfer complete event. */ + if (false == SDMMCEVENT_Create(kSDMMCEVENT_TransferComplete)) + { + return kStatus_Fail; + } + + /* Define transfer function. */ + sdifHost->transfer = SDMMCHOST_TransferFunction; + + /* card detect init */ + SDMMCHOST_CardDetectInit(sdifHost->base, (userData == NULL) ? NULL : (((sdmmhostcard_usr_param_t *)userData)->cd)); + + return kStatus_Success; +} + +void SDMMCHOST_Reset(SDMMCHOST_TYPE *base) +{ + /* reserved for future */ +} + +void SDMMCHOST_Deinit(void *host) +{ + sdif_host_t *sdifHost = (sdif_host_t *)host; + SDIF_Deinit(sdifHost->base); + SDMMCEVENT_Delete(kSDMMCEVENT_TransferComplete); + SDMMCHOST_CardDetectDeinit(); +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/port/sdif/interrupt/fsl_sdmmc_event.c b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/port/sdif/interrupt/fsl_sdmmc_event.c new file mode 100644 index 000000000..5f374f813 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/port/sdif/interrupt/fsl_sdmmc_event.c @@ -0,0 +1,143 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_sdmmc_event.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Get event instance. + * @param eventType The event type + * @return The event instance's pointer. + */ +static volatile uint32_t *SDMMCEVENT_GetInstance(sdmmc_event_t eventType); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Card detect event. */ +static volatile uint32_t g_eventCardDetect; + +/*! @brief transfer complete event. */ +static volatile uint32_t g_eventTransferComplete; + +/*! @brief Time variable unites as milliseconds. */ +volatile uint32_t g_eventTimeMilliseconds; + +/******************************************************************************* + * Code + ******************************************************************************/ +void SDMMCEVENT_InitTimer(void) +{ + /* Set systick reload value to generate 1ms interrupt */ + SysTick_Config(CLOCK_GetFreq(kCLOCK_CoreSysClk) / 1000U); +} + +void SysTick_Handler(void) +{ + g_eventTimeMilliseconds++; +} + +static volatile uint32_t *SDMMCEVENT_GetInstance(sdmmc_event_t eventType) +{ + volatile uint32_t *event; + + switch (eventType) + { + case kSDMMCEVENT_TransferComplete: + event = &g_eventTransferComplete; + break; + case kSDMMCEVENT_CardDetect: + event = &g_eventCardDetect; + break; + default: + event = NULL; + break; + } + + return event; +} + +bool SDMMCEVENT_Create(sdmmc_event_t eventType) +{ + volatile uint32_t *event = SDMMCEVENT_GetInstance(eventType); + + if (event) + { + *event = 0; + return true; + } + else + { + return false; + } +} + +bool SDMMCEVENT_Wait(sdmmc_event_t eventType, uint32_t timeoutMilliseconds) +{ + uint32_t startTime; + uint32_t elapsedTime; + + volatile uint32_t *event = SDMMCEVENT_GetInstance(eventType); + + if (timeoutMilliseconds && event) + { + startTime = g_eventTimeMilliseconds; + do + { + elapsedTime = (g_eventTimeMilliseconds - startTime); + } while ((*event == 0U) && (elapsedTime < timeoutMilliseconds)); + *event = 0U; + + return ((elapsedTime < timeoutMilliseconds) ? true : false); + } + else + { + return false; + } +} + +bool SDMMCEVENT_Notify(sdmmc_event_t eventType) +{ + volatile uint32_t *event = SDMMCEVENT_GetInstance(eventType); + + if (event) + { + *event = 1U; + return true; + } + else + { + return false; + } +} + +void SDMMCEVENT_Delete(sdmmc_event_t eventType) +{ + volatile uint32_t *event = SDMMCEVENT_GetInstance(eventType); + + if (event) + { + *event = 0U; + } +} + +void SDMMCEVENT_Delay(uint32_t milliseconds) +{ + uint32_t startTime = g_eventTimeMilliseconds; + uint32_t periodTime = 0; + while (periodTime < milliseconds) + { + periodTime = g_eventTimeMilliseconds - startTime; + } +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/port/sdif/interrupt/fsl_sdmmc_host.c b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/port/sdif/interrupt/fsl_sdmmc_host.c new file mode 100644 index 000000000..88bf2a7ec --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/port/sdif/interrupt/fsl_sdmmc_host.c @@ -0,0 +1,311 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include "fsl_sdmmc_host.h" +#include "fsl_sdmmc_event.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief SDMMCHOST detect card insert status by host controller. + * @param base host base address. + * @param userData user can register a application card insert callback through userData. + */ +static void SDMMCHOST_DetectCardInsertByHost(SDMMCHOST_TYPE *base, void *userData); + +/*! + * @brief SDMMCHOST detect card remove status by host controller. + * @param base host base address. + * @param userData user can register a application card insert callback through userData. + */ +static void SDMMCHOST_DetectCardRemoveByHost(SDMMCHOST_TYPE *base, void *userData); + +/*! + * @brief SDMMCHOST transfer function. + * @param base host base address. + * @param content transfer configurations. + */ +static status_t SDMMCHOST_TransferFunction(SDMMCHOST_TYPE *base, SDMMCHOST_TRANSFER *content); + +/*! + * @brief SDMMCHOST transfer complete callback. + * @param base host base address. + * @param handle host handle. + * @param status interrupt status. + * @param userData user data. + */ +static void SDMMCHOST_TransferCompleteCallback(SDMMCHOST_TYPE *base, void *handle, status_t status, void *userData); + +/*! + * @brief card detect deinit function. + */ +static void SDMMCHOST_CardDetectDeinit(void); + +/*! + * @brief card detect deinit function. + * @param host base address. + * @param host detect card configuration. + */ +static status_t SDMMCHOST_CardDetectInit(SDMMCHOST_TYPE *base, const sdmmchost_detect_card_t *cd); +/******************************************************************************* + * Variables + ******************************************************************************/ + +sdif_handle_t g_sdifHandle; +static uint32_t s_sdifDmaTable[SDIF_DMA_TABLE_WORDS]; +volatile bool g_sdifTransferSuccessFlag = true; +/*! @brief Card detect flag. */ +static volatile bool s_sdInsertedFlag = false; +/******************************************************************************* + * Code + ******************************************************************************/ +static void SDMMCHOST_DetectCardInsertByHost(SDIF_Type *base, void *userData) +{ + s_sdInsertedFlag = true; + SDMMCEVENT_Notify(kSDMMCEVENT_CardDetect); + /* application callback */ + if (userData && (((sdmmhostcard_usr_param_t *)userData)->cd) && + ((sdmmhostcard_usr_param_t *)userData)->cd->cardInserted) + { + ((sdmmhostcard_usr_param_t *)userData) + ->cd->cardInserted(true, ((sdmmhostcard_usr_param_t *)userData)->cd->userData); + } +} + +static void SDMMCHOST_DetectCardRemoveByHost(SDIF_Type *base, void *userData) +{ + s_sdInsertedFlag = false; + /* application callback */ + if (userData && (((sdmmhostcard_usr_param_t *)userData)->cd) && + ((sdmmhostcard_usr_param_t *)userData)->cd->cardRemoved) + { + ((sdmmhostcard_usr_param_t *)userData) + ->cd->cardRemoved(false, ((sdmmhostcard_usr_param_t *)userData)->cd->userData); + } +} + +/* Transfer complete callback function. */ +static void SDMMCHOST_TransferCompleteCallback(SDMMCHOST_TYPE *base, void *handle, status_t status, void *userData) +{ + /* receive the right status, notify the event */ + if (status == kStatus_Success) + { + g_sdifTransferSuccessFlag = true; + } + else + { + g_sdifTransferSuccessFlag = false; + } + + SDMMCEVENT_Notify(kSDMMCEVENT_TransferComplete); +} + +/* User defined transfer function. */ +static status_t SDMMCHOST_TransferFunction(SDMMCHOST_TYPE *base, SDMMCHOST_TRANSFER *content) +{ + status_t error = kStatus_Success; + + sdif_dma_config_t dmaConfig; + + memset(s_sdifDmaTable, 0, sizeof(s_sdifDmaTable)); + memset(&dmaConfig, 0, sizeof(dmaConfig)); + + /* make sure the complete event is delete */ + SDMMCEVENT_Delete(kSDMMCEVENT_TransferComplete); + + /* user DMA mode transfer data */ + if (content->data != NULL) + { + dmaConfig.enableFixBurstLen = false; + dmaConfig.mode = kSDIF_DualDMAMode; + dmaConfig.dmaDesBufferStartAddr = s_sdifDmaTable; + dmaConfig.dmaDesBufferLen = SDIF_DMA_TABLE_WORDS; + dmaConfig.dmaDesSkipLen = 0U; + } + + do + { + error = SDIF_TransferNonBlocking(base, &g_sdifHandle, &dmaConfig, content); + } while (error == kStatus_SDIF_SyncCmdTimeout); + + if ((error != kStatus_Success) || + (false == SDMMCEVENT_Wait(kSDMMCEVENT_TransferComplete, SDMMCHOST_TRANSFER_COMPLETE_TIMEOUT)) || + (!g_sdifTransferSuccessFlag)) + { + error = kStatus_Fail; + } + + return error; +} + +static status_t SDMMCHOST_CardDetectInit(SDMMCHOST_TYPE *base, const sdmmchost_detect_card_t *cd) +{ + sdmmchost_detect_card_type_t cdType = kSDMMCHOST_DetectCardByHostCD; + + if (cd != NULL) + { + cdType = cd->cdType; + } + + /* for interrupt case, only kSDMMCHOST_DetectCardByHostCD can generate interrupt, so implement it only */ + if (cdType != kSDMMCHOST_DetectCardByHostCD) + { + return kStatus_Fail; + } + + if (!SDMMCEVENT_Create(kSDMMCEVENT_CardDetect)) + { + return kStatus_Fail; + } + /* enable the card detect interrupt */ + SDMMCHOST_CARD_DETECT_INSERT_ENABLE(base); + /* check if card is inserted */ + if (SDMMCHOST_CARD_DETECT_INSERT_STATUS(base, false)) + { + s_sdInsertedFlag = true; + /* application callback */ + if (cd && cd->cardInserted) + { + cd->cardInserted(true, cd->userData); + } + } + + return kStatus_Success; +} + +static void SDMMCHOST_CardDetectDeinit(void) +{ + SDMMCEVENT_Delete(kSDMMCEVENT_CardDetect); + s_sdInsertedFlag = false; +} + +void SDMMCHOST_Delay(uint32_t milliseconds) +{ + SDMMCEVENT_Delay(milliseconds); +} + +status_t SDMMCHOST_WaitCardDetectStatus(SDMMCHOST_TYPE *base, const sdmmchost_detect_card_t *cd, bool waitCardStatus) +{ + uint32_t timeout = SDMMCHOST_CARD_DETECT_TIMEOUT; + + if (cd != NULL) + { + timeout = cd->cdTimeOut_ms; + } + + if (waitCardStatus != s_sdInsertedFlag) + { + /* Wait card inserted. */ + do + { + if (!SDMMCEVENT_Wait(kSDMMCEVENT_CardDetect, timeout)) + { + return kStatus_Fail; + } + } while (waitCardStatus != s_sdInsertedFlag); + } + + return kStatus_Success; +} + +bool SDMMCHOST_IsCardPresent(void) +{ + return s_sdInsertedFlag; +} + +void SDMMCHOST_PowerOffCard(SDMMCHOST_TYPE *base, const sdmmchost_pwr_card_t *pwr) +{ + if (pwr != NULL) + { + pwr->powerOff(); + SDMMCHOST_Delay(pwr->powerOffDelay_ms); + } + else + { + /* disable the card power */ + SDIF_EnableCardPower(base, false); + /* Delay several milliseconds to make card stable. */ + SDMMCHOST_Delay(500U); + } +} + +void SDMMCHOST_PowerOnCard(SDMMCHOST_TYPE *base, const sdmmchost_pwr_card_t *pwr) +{ + /* use user define the power on function */ + if (pwr != NULL) + { + pwr->powerOn(); + SDMMCHOST_Delay(pwr->powerOnDelay_ms); + } + else + { + /* Enable the card power */ + SDIF_EnableCardPower(base, true); + /* Delay several milliseconds to make card stable. */ + SDMMCHOST_Delay(500U); + } +} + +status_t SDMMCHOST_Init(SDMMCHOST_CONFIG *host, void *userData) +{ + sdif_transfer_callback_t sdifCallback = {0}; + sdif_host_t *sdifHost = (sdif_host_t *)host; + + /* init event timer. */ + SDMMCEVENT_InitTimer(); + + /* Initialize SDIF. */ + sdifHost->config.endianMode = kSDMMCHOST_EndianModeLittle; + sdifHost->config.responseTimeout = 0xFFU; + sdifHost->config.cardDetDebounce_Clock = 0xFFFFFFU; + sdifHost->config.dataTimeout = 0xFFFFFFU; + SDIF_Init(sdifHost->base, &(sdifHost->config)); + + /* Set callback for SDIF driver. */ + sdifCallback.TransferComplete = SDMMCHOST_TransferCompleteCallback; + sdifCallback.cardInserted = SDMMCHOST_DetectCardInsertByHost; + sdifCallback.cardRemoved = SDMMCHOST_DetectCardRemoveByHost; + + /* Create handle for SDIF driver */ + SDIF_TransferCreateHandle(sdifHost->base, &g_sdifHandle, &sdifCallback, userData); + + /* Create transfer complete event. */ + if (false == SDMMCEVENT_Create(kSDMMCEVENT_TransferComplete)) + { + return kStatus_Fail; + } + + /* Define transfer function. */ + sdifHost->transfer = SDMMCHOST_TransferFunction; + + /* card detect init */ + SDMMCHOST_CardDetectInit(sdifHost->base, (userData == NULL) ? NULL : (((sdmmhostcard_usr_param_t *)userData)->cd)); + + return kStatus_Success; +} + +void SDMMCHOST_Reset(SDMMCHOST_TYPE *base) +{ + /* reserved for future */ +} + +void SDMMCHOST_Deinit(void *host) +{ + sdif_host_t *sdifHost = (sdif_host_t *)host; + SDIF_Deinit(sdifHost->base); + SDMMCHOST_CardDetectDeinit(); +} + +void SDMMCHOST_ErrorRecovery(SDMMCHOST_TYPE *base) +{ + /* reserved for future */ +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/port/sdif/polling/fsl_sdmmc_event.c b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/port/sdif/polling/fsl_sdmmc_event.c new file mode 100644 index 000000000..11a5b964f --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/port/sdif/polling/fsl_sdmmc_event.c @@ -0,0 +1,142 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include "fsl_sdmmc_event.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Get event instance. + * @param eventType The event type + * @return The event instance's pointer. + */ +static volatile uint32_t *SDMMCEVENT_GetInstance(sdmmc_event_t eventType); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Card detect event. */ +static volatile uint32_t g_eventCardDetect; + +/*! @brief transfer complete event. */ +static volatile uint32_t g_eventTransferComplete; + +/*! @brief Time variable unites as milliseconds. */ +volatile uint32_t g_eventTimeMilliseconds; + +/******************************************************************************* + * Code + ******************************************************************************/ +void SDMMCEVENT_InitTimer(void) +{ + /* Set systick reload value to generate 1ms interrupt */ + SysTick_Config(CLOCK_GetFreq(kCLOCK_CoreSysClk) / 1000U); +} + +void SysTick_Handler(void) +{ + g_eventTimeMilliseconds++; +} + +static volatile uint32_t *SDMMCEVENT_GetInstance(sdmmc_event_t eventType) +{ + volatile uint32_t *event; + + switch (eventType) + { + case kSDMMCEVENT_TransferComplete: + event = &g_eventTransferComplete; + break; + case kSDMMCEVENT_CardDetect: + event = &g_eventCardDetect; + break; + default: + event = NULL; + break; + } + + return event; +} + +bool SDMMCEVENT_Create(sdmmc_event_t eventType) +{ + volatile uint32_t *event = SDMMCEVENT_GetInstance(eventType); + + if (event) + { + *event = 0; + return true; + } + else + { + return false; + } +} + +bool SDMMCEVENT_Wait(sdmmc_event_t eventType, uint32_t timeoutMilliseconds) +{ + uint32_t startTime; + uint32_t elapsedTime; + + volatile uint32_t *event = SDMMCEVENT_GetInstance(eventType); + + if (timeoutMilliseconds && event) + { + startTime = g_eventTimeMilliseconds; + do + { + elapsedTime = (g_eventTimeMilliseconds - startTime); + } while ((*event == 0U) && (elapsedTime < timeoutMilliseconds)); + *event = 0U; + + return ((elapsedTime < timeoutMilliseconds) ? true : false); + } + else + { + return false; + } +} + +bool SDMMCEVENT_Notify(sdmmc_event_t eventType) +{ + volatile uint32_t *event = SDMMCEVENT_GetInstance(eventType); + + if (event) + { + *event = 1U; + return true; + } + else + { + return false; + } +} + +void SDMMCEVENT_Delete(sdmmc_event_t eventType) +{ + volatile uint32_t *event = SDMMCEVENT_GetInstance(eventType); + + if (event) + { + *event = 0U; + } +} + +void SDMMCEVENT_Delay(uint32_t milliseconds) +{ + uint32_t startTime = g_eventTimeMilliseconds; + uint32_t periodTime = 0; + while (periodTime < milliseconds) + { + periodTime = g_eventTimeMilliseconds - startTime; + } +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/port/sdif/polling/fsl_sdmmc_host.c b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/port/sdif/polling/fsl_sdmmc_host.c new file mode 100644 index 000000000..c56378648 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/port/sdif/polling/fsl_sdmmc_host.c @@ -0,0 +1,245 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_sdmmc_host.h" +#include "fsl_sdmmc_event.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief SDMMCHOST detect card insert status by host controller. + * @param base host base address. + * @param data3 flag indicate use data3 to detect card or not. + */ +static void SDMMCHOST_DetectCardInsertByHost(SDMMCHOST_TYPE *base, bool data3); + +/*! + * @brief SDMMCHOST detect card status by GPIO. + */ +static bool SDMMCHOST_DetectCardByGpio(void); + +/*! + * @brief SDMMCHOST transfer function. + * @param base host base address. + * @param content transfer configurations. + */ +static status_t SDMMCHOST_TransferFunction(SDMMCHOST_TYPE *base, SDMMCHOST_TRANSFER *content); + +/*! + * @brief card detect deinit function. + */ +static void SDMMCHOST_CardDetectDeinit(void); + +/*! + * @brief card detect deinit function. + * @param host base address. + * @param host detect card configuration. + */ +static status_t SDMMCHOST_CardDetectInit(SDMMCHOST_TYPE *base, const sdmmchost_detect_card_t *cd); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Card detect flag. */ +static volatile bool s_sdInsertedFlag = false; +/*! @brief DMA descriptor table. */ +static uint32_t s_sdifDmaTable[SDIF_DMA_TABLE_WORDS]; +/******************************************************************************* + * Code + ******************************************************************************/ +static bool SDMMCHOST_DetectCardByGpio(void) +{ + if (SDMMCHOST_CARD_DETECT_STATUS() != SDMMCHOST_CARD_INSERT_CD_LEVEL) + { + s_sdInsertedFlag = false; + } + else + { + s_sdInsertedFlag = true; + } + + return s_sdInsertedFlag; +} + +static void SDMMCHOST_DetectCardInsertByHost(SDMMCHOST_TYPE *base, bool data3) +{ + if (SDMMCHOST_CARD_DETECT_INSERT_STATUS(base, data3)) + { + s_sdInsertedFlag = true; + } +} + +/* User defined transfer function. */ +static status_t SDMMCHOST_TransferFunction(SDMMCHOST_TYPE *base, SDMMCHOST_TRANSFER *content) +{ + status_t error = kStatus_Success; + + sdif_dma_config_t dmaConfig; + + memset(s_sdifDmaTable, 0, sizeof(s_sdifDmaTable)); + memset(&dmaConfig, 0, sizeof(dmaConfig)); + + if (content->data != NULL) + { + dmaConfig.enableFixBurstLen = true; + dmaConfig.mode = kSDIF_ChainDMAMode; + dmaConfig.dmaDesBufferStartAddr = s_sdifDmaTable; + dmaConfig.dmaDesBufferLen = SDIF_DMA_TABLE_WORDS; + } + + if (kStatus_Success != SDIF_TransferBlocking(base, &dmaConfig, content)) + { + error = kStatus_Fail; + } + + return error; +} + +static status_t SDMMCHOST_CardDetectInit(SDMMCHOST_TYPE *base, const sdmmchost_detect_card_t *cd) +{ + sdmmchost_detect_card_type_t cdType = kSDMMCHOST_DetectCardByGpioCD; + + if (cd != NULL) + { + cdType = cd->cdType; + } + + if (cdType == kSDMMCHOST_DetectCardByGpioCD) + { + SDMMCHOST_CARD_DETECT_INIT(); + SDMMCHOST_DetectCardByGpio(); + } + else + { + /* enable card detect status */ + SDMMCHOST_CARD_DETECT_INSERT_ENABLE(base); + } + + return kStatus_Success; +} + +static void SDMMCHOST_CardDetectDeinit(void) +{ + s_sdInsertedFlag = false; +} + +void SDMMCHOST_Delay(uint32_t milliseconds) +{ + SDMMCEVENT_Delay(milliseconds); +} + +status_t SDMMCHOST_WaitCardDetectStatus(SDMMCHOST_TYPE *base, const sdmmchost_detect_card_t *cd, bool waitCardStatus) +{ + sdmmchost_detect_card_type_t cdType = kSDMMCHOST_DetectCardByGpioCD; + + if (cd != NULL) + { + cdType = cd->cdType; + } + + if (waitCardStatus != s_sdInsertedFlag) + { + /* Wait card inserted. */ + do + { + if (cdType == kSDMMCHOST_DetectCardByGpioCD) + { + SDMMCHOST_DetectCardByGpio(); + } + else + { + SDMMCHOST_DetectCardInsertByHost(base, cdType == kSDMMCHOST_DetectCardByHostDATA3); + } + + } while (waitCardStatus != s_sdInsertedFlag); + } + + return kStatus_Success; +} + +bool SDMMCHOST_IsCardPresent(void) +{ + return s_sdInsertedFlag; +} + +void SDMMCHOST_PowerOffCard(SDMMCHOST_TYPE *base, const sdmmchost_pwr_card_t *pwr) +{ + if (pwr != NULL) + { + pwr->powerOff(); + SDMMCHOST_Delay(pwr->powerOffDelay_ms); + } + else + { + /* disable the card power */ + SDIF_EnableCardPower(base, false); + /* Delay several milliseconds to make card stable. */ + SDMMCHOST_Delay(500U); + } +} + +void SDMMCHOST_PowerOnCard(SDMMCHOST_TYPE *base, const sdmmchost_pwr_card_t *pwr) +{ + /* use user define the power on function */ + if (pwr != NULL) + { + pwr->powerOn(); + SDMMCHOST_Delay(pwr->powerOnDelay_ms); + } + else + { + /* Enable the card power */ + SDIF_EnableCardPower(base, true); + /* Delay several milliseconds to make card stable. */ + SDMMCHOST_Delay(500U); + } +} + +status_t SDMMCHOST_Init(SDMMCHOST_CONFIG *host, void *userData) +{ + sdif_host_t *sdifHost = (sdif_host_t *)host; + + /* init event timer. */ + SDMMCEVENT_InitTimer(); + + /* Initialize SDIF. */ + sdifHost->config.endianMode = kSDMMCHOST_EndianModeLittle; + sdifHost->config.responseTimeout = 0xFFU; + sdifHost->config.cardDetDebounce_Clock = 0xFFFFFFU; + sdifHost->config.dataTimeout = 0xFFFFFFU; + SDIF_Init(sdifHost->base, &(sdifHost->config)); + + /* Define transfer function. */ + sdifHost->transfer = SDMMCHOST_TransferFunction; + + SDMMCHOST_CardDetectInit(sdifHost->base, (userData == NULL) ? NULL : (((sdmmhostcard_usr_param_t *)userData)->cd)); + + return kStatus_Success; +} + +void SDMMCHOST_Reset(SDMMCHOST_TYPE *base) +{ + /* reserved for future */ +} + +void SDMMCHOST_Deinit(void *host) +{ + sdif_host_t *sdifHost = (sdif_host_t *)host; + SDIF_Deinit(sdifHost->base); + SDMMCHOST_CardDetectDeinit(); +} + +void SDMMCHOST_ErrorRecovery(SDMMCHOST_TYPE *base) +{ + /* reserved for future */ +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/port/sdif/rt_thread/fsl_sdmmc_event.c b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/port/sdif/rt_thread/fsl_sdmmc_event.c new file mode 100644 index 000000000..06c95fa47 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/port/sdif/rt_thread/fsl_sdmmc_event.c @@ -0,0 +1,149 @@ +/* + * The Clear BSD License + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_sdmmc_event.h" + +#include + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Get event instance. + * @param eventType The event type + * @return The event instance's pointer. + */ +static volatile uint32_t *SDMMCEVENT_GetInstance(sdmmc_event_t eventType); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Card detect event. */ +static volatile uint32_t g_eventCardDetect; + +/*! @brief transfer complete event. */ +static volatile uint32_t g_eventTransferComplete; + + +/******************************************************************************* + * Code + ******************************************************************************/ +void SDMMCEVENT_InitTimer(void) +{ + +} + +static volatile uint32_t *SDMMCEVENT_GetInstance(sdmmc_event_t eventType) +{ + volatile uint32_t *event; + + switch (eventType) + { + case kSDMMCEVENT_TransferComplete: + event = &g_eventTransferComplete; + break; + case kSDMMCEVENT_CardDetect: + event = &g_eventCardDetect; + break; + default: + event = NULL; + break; + } + + return event; +} + +bool SDMMCEVENT_Create(sdmmc_event_t eventType) +{ + volatile uint32_t *event = SDMMCEVENT_GetInstance(eventType); + + if (event) + { + *event = 0; + return true; + } + else + { + return false; + } +} + +bool SDMMCEVENT_Wait(sdmmc_event_t eventType, uint32_t timeoutMilliseconds) +{ + volatile uint32_t *event = SDMMCEVENT_GetInstance(eventType); + rt_thread_delay(timeoutMilliseconds); + + if (event) + { + return true; + } + else + { + return false; + } +} + +bool SDMMCEVENT_Notify(sdmmc_event_t eventType) +{ + volatile uint32_t *event = SDMMCEVENT_GetInstance(eventType); + + if (event) + { + *event = 1U; + return true; + } + else + { + return false; + } +} + +void SDMMCEVENT_Delete(sdmmc_event_t eventType) +{ + volatile uint32_t *event = SDMMCEVENT_GetInstance(eventType); + + if (event) + { + *event = 0U; + } +} + +void SDMMCEVENT_Delay(uint32_t milliseconds) +{ + rt_thread_delay(milliseconds); +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/port/sdif/rt_thread/fsl_sdmmc_host.c b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/port/sdif/rt_thread/fsl_sdmmc_host.c new file mode 100644 index 000000000..65b93d888 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/port/sdif/rt_thread/fsl_sdmmc_host.c @@ -0,0 +1,274 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_sdmmc_host.h" +#include "fsl_sdmmc_event.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief SDMMCHOST detect card insert status by host controller. + * @param base host base address. + * @param data3 flag indicate use data3 to detect card or not. + */ +static void SDMMCHOST_DetectCardInsertByHost(SDMMCHOST_TYPE *base, bool data3); + +/*! + * @brief SDMMCHOST detect card status by GPIO. + */ +static bool SDMMCHOST_DetectCardByGpio(void); + +/*! + * @brief SDMMCHOST transfer function. + * @param base host base address. + * @param content transfer configurations. + */ +static status_t SDMMCHOST_TransferFunction(SDMMCHOST_TYPE *base, SDMMCHOST_TRANSFER *content); + +/*! + * @brief card detect deinit function. + */ +static void SDMMCHOST_CardDetectDeinit(void); + +/*! + * @brief card detect deinit function. + * @param host base address. + * @param host detect card configuration. + */ +static status_t SDMMCHOST_CardDetectInit(SDMMCHOST_TYPE *base, const sdmmchost_detect_card_t *cd); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Card detect flag. */ +static volatile bool s_sdInsertedFlag = false; +/*! @brief DMA descriptor table. */ +static uint32_t s_sdifDmaTable[SDIF_DMA_TABLE_WORDS]; +/******************************************************************************* + * Code + ******************************************************************************/ +static bool SDMMCHOST_DetectCardByGpio(void) +{ + if (SDMMCHOST_CARD_DETECT_STATUS() != SDMMCHOST_CARD_INSERT_CD_LEVEL) + { + s_sdInsertedFlag = false; + } + else + { + s_sdInsertedFlag = true; + } + + return s_sdInsertedFlag; +} + +static void SDMMCHOST_DetectCardInsertByHost(SDMMCHOST_TYPE *base, bool data3) +{ + if (SDMMCHOST_CARD_DETECT_INSERT_STATUS(base, data3)) + { + s_sdInsertedFlag = true; + } +} + +/* User defined transfer function. */ +static status_t SDMMCHOST_TransferFunction(SDMMCHOST_TYPE *base, SDMMCHOST_TRANSFER *content) +{ + status_t error = kStatus_Success; + + sdif_dma_config_t dmaConfig; + + memset(s_sdifDmaTable, 0, sizeof(s_sdifDmaTable)); + memset(&dmaConfig, 0, sizeof(dmaConfig)); + + if (content->data != NULL) + { + dmaConfig.enableFixBurstLen = true; + dmaConfig.mode = kSDIF_ChainDMAMode; + dmaConfig.dmaDesBufferStartAddr = s_sdifDmaTable; + dmaConfig.dmaDesBufferLen = SDIF_DMA_TABLE_WORDS; + } + + if (kStatus_Success != SDIF_TransferBlocking(base, &dmaConfig, content)) + { + error = kStatus_Fail; + } + + return error; +} + +static status_t SDMMCHOST_CardDetectInit(SDMMCHOST_TYPE *base, const sdmmchost_detect_card_t *cd) +{ + sdmmchost_detect_card_type_t cdType = kSDMMCHOST_DetectCardByGpioCD; + + if (cd != NULL) + { + cdType = cd->cdType; + } + + if (cdType == kSDMMCHOST_DetectCardByGpioCD) + { + SDMMCHOST_CARD_DETECT_INIT(); + SDMMCHOST_DetectCardByGpio(); + } + else + { + /* enable card detect status */ + SDMMCHOST_CARD_DETECT_INSERT_ENABLE(base); + } + + return kStatus_Success; +} + +static void SDMMCHOST_CardDetectDeinit(void) +{ + s_sdInsertedFlag = false; +} + +void SDMMCHOST_Delay(uint32_t milliseconds) +{ + SDMMCEVENT_Delay(milliseconds); +} + +status_t SDMMCHOST_WaitCardDetectStatus(SDMMCHOST_TYPE *base, const sdmmchost_detect_card_t *cd, bool waitCardStatus) +{ + sdmmchost_detect_card_type_t cdType = kSDMMCHOST_DetectCardByGpioCD; + + if (cd != NULL) + { + cdType = cd->cdType; + } + + if (waitCardStatus != s_sdInsertedFlag) + { + /* Wait card inserted. */ + do + { + if (cdType == kSDMMCHOST_DetectCardByGpioCD) + { + SDMMCHOST_DetectCardByGpio(); + } + else + { + SDMMCHOST_DetectCardInsertByHost(base, cdType == kSDMMCHOST_DetectCardByHostDATA3); + } + + } while (waitCardStatus != s_sdInsertedFlag); + } + + return kStatus_Success; +} + +bool SDMMCHOST_IsCardPresent(void) +{ + return s_sdInsertedFlag; +} + +void SDMMCHOST_PowerOffCard(SDMMCHOST_TYPE *base, const sdmmchost_pwr_card_t *pwr) +{ + if (pwr != NULL) + { + pwr->powerOff(); + SDMMCHOST_Delay(pwr->powerOffDelay_ms); + } + else + { + /* disable the card power */ + SDIF_EnableCardPower(base, false); + /* Delay several milliseconds to make card stable. */ + SDMMCHOST_Delay(500U); + } +} + +void SDMMCHOST_PowerOnCard(SDMMCHOST_TYPE *base, const sdmmchost_pwr_card_t *pwr) +{ + /* use user define the power on function */ + if (pwr != NULL) + { + pwr->powerOn(); + SDMMCHOST_Delay(pwr->powerOnDelay_ms); + } + else + { + /* Enable the card power */ + SDIF_EnableCardPower(base, true); + /* Delay several milliseconds to make card stable. */ + SDMMCHOST_Delay(500U); + } +} + +status_t SDMMCHOST_Init(SDMMCHOST_CONFIG *host, void *userData) +{ + sdif_host_t *sdifHost = (sdif_host_t *)host; + + /* init event timer. */ + SDMMCEVENT_InitTimer(); + + /* Initialize SDIF. */ + sdifHost->config.endianMode = kSDMMCHOST_EndianModeLittle; + sdifHost->config.responseTimeout = 0xFFU; + sdifHost->config.cardDetDebounce_Clock = 0xFFFFFFU; + sdifHost->config.dataTimeout = 0xFFFFFFU; + SDIF_Init(sdifHost->base, &(sdifHost->config)); + + /* Define transfer function. */ + sdifHost->transfer = SDMMCHOST_TransferFunction; + + /* Enable the card power here for mmc card case, because mmc card don't need card detect*/ + SDIF_EnableCardPower(sdifHost->base, true); + + SDMMCHOST_CardDetectInit(sdifHost->base, (sdmmchost_detect_card_t *)userData); + + return kStatus_Success; +} + +void SDMMCHOST_Reset(SDMMCHOST_TYPE *base) +{ + /* reserved for future */ +} + +void SDMMCHOST_Deinit(void *host) +{ + sdif_host_t *sdifHost = (sdif_host_t *)host; + SDIF_Deinit(sdifHost->base); + SDMMCHOST_CardDetectDeinit(); +} + +void SDMMCHOST_ErrorRecovery(SDMMCHOST_TYPE *base) +{ + /* reserved for future */ +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/src/fsl_mmc.c b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/src/fsl_mmc.c new file mode 100644 index 000000000..26796a357 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/src/fsl_mmc.c @@ -0,0 +1,2671 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include "fsl_mmc.h" + +/******************************************************************************* + * Definitons + ******************************************************************************/ +/*! @brief The divide value used to avoid float point calculation when calculate max speed in normal mode. */ +#define DIVIDER_IN_TRANSFER_SPEED (10U) + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Send SELECT_CARD command to set the card enter or exit transfer state. + * + * @param card Card descriptor. + * @param isSelected True to enter transfer state. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t inline MMC_SelectCard(mmc_card_t *card, bool isSelected); + +/*! + * @brief Wait write process complete. + * + * @param card Card descriptor. + * @retval kStatus_Timeout Operation timeout. + * @retval kStatus_Success Operate successfully. + */ +static status_t MMC_WaitWriteComplete(mmc_card_t *card); + +/*! + * @brief Send SET_BLOCK_COUNT command. + * + * @param card Card descriptor. + * @param blockCount Block count. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t inline MMC_SetBlockCount(mmc_card_t *card, uint32_t blockCount); + +/*! + * @brief Send GO_IDLE command to reset all cards to idle state + * + * @param card Card descriptor. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t inline MMC_GoIdle(mmc_card_t *card); + +/*! + * @brief Send STOP_TRANSMISSION command to card to stop ongoing data transferring. + * + * @param card Card descriptor. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t MMC_StopTransmission(mmc_card_t *card); + +/*! + * @brief Send SET_BLOCK_SIZE command to set the block length in bytes for MMC cards. + * + * @param card Card descriptor. + * @param blockSize Block size. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t inline MMC_SetBlockSize(mmc_card_t *card, uint32_t blockSize); + +/*! + * @brief switch voltage. + * + * @param card Card descriptor. + * @param opcode use to send operation condition + * @retval kStatus_SDMMC_HostNotSupport Host doesn't support the voltage window to access the card. + * @retval kStatus_Success Operate successfully. + */ +static status_t MMC_SwitchVoltage(mmc_card_t *card, uint32_t *opCode); + +/*! + * @brief Send SEND_OPERATION_CONDITION command to validate if the card support host's voltage window + * + * @param card Card descriptor. + * @param arg Command argument. + * @retval kStatus_SDMMC_TransferFailed Transfers failed. + * @retval kStatus_Timeout Operation timeout. + * @retval kStatus_Success Operate successfully. + */ +static status_t MMC_SendOperationCondition(mmc_card_t *card, uint32_t arg); + +/*! + * @brief Send SET_RCA command to set the relative address of the card. + * + * @param card Card descriptor. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t MMC_SetRelativeAddress(mmc_card_t *card); + +/*! + * @brief Decode CSD register content. + * + * @param card Card descriptor. + * @param rawCsd raw CSD register content. + */ +static void MMC_DecodeCsd(mmc_card_t *card, uint32_t *rawCsd); + +/*! + * @brief Set the card to max transfer speed in non-high speed mode. + * + * @param card Card descriptor. + */ +static void MMC_SetMaxFrequency(mmc_card_t *card); + +/*! + * @brief Set erase unit size of the card + * + * @param card Card descriptor. + * @retval kStatus_SDMMC_ConfigureExtendedCsdFailed Configure Extended CSD failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t MMC_SetMaxEraseUnitSize(mmc_card_t *card); + +/*! + * @brief Send SWITCH command to set the specific byte in Extended CSD. + * + * Example: + @code + mmc_extended_csd_config_t config; + config.accessMode = kMMC_ExtendedCsdAccessModeSetBits; + config.ByteIndex = 1U; + config.ByteValue = 0x033U; + config.commandSet = kMMC_CommandSetStandard; + MMC_SetExtendedCsdConfig(card, &config); + @endcode + * + * @param card Card descriptor. + * @param config Configuration for Extended CSD. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_SDMMC_WaitWriteCompleteFailed Wait write complete failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t MMC_SetExtendedCsdConfig(mmc_card_t *card, const mmc_extended_csd_config_t *config); + +/*! + * @brief Decode the Extended CSD register + * + * @param card Card descriptor. + * @param rawExtendedCsd Raw extended CSD register content. + */ +static void MMC_DecodeExtendedCsd(mmc_card_t *card, uint32_t *rawExtendedCsd); + +/*! + * @brief Send SEND_EXTENDED_CSD command to get the content of the Extended CSD register + * Allow read the special byte index value if targetAddr is not NULL + * @param card Card descriptor. + * @param targetAddr Pointer to store the target byte value. + * @param byteIndex Target byte index. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t MMC_SendExtendedCsd(mmc_card_t *card, uint8_t *targetAddr, uint32_t byteIndex); + +/*! + * @brief Set the power class of the card at specific bus width and host intended voltage window. + * + * @param card Card descriptor. + * @return The power class switch status. + */ +static status_t MMC_SetPowerClass(mmc_card_t *card); + +/*! + * @brief Send test pattern to get the functional pin in the MMC bus + * + * @param card Card descriptor. + * @param blockSize Test pattern block size. + * @param pattern Test pattern data buffer. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t MMC_SendTestPattern(mmc_card_t *card, uint32_t blockSize, uint32_t *pattern); + +/*! + * @brief Receive test pattern reversed by the card. + * + * @param card Card descriptor. + * @param blockSize Test pattern block size. + * @param pattern Test pattern data buffer. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t MMC_ReceiveTestPattern(mmc_card_t *card, uint32_t blockSize, uint32_t *pattern); + +/*! + * @brief Bus test procedure to get the functional data pin in the bus + * + * @param card Card descriptor. + * @param width Data bus width. + * @retval kStatus_SDMMC_SendTestPatternFailed Send test pattern failed. + * @retval kStatus_SDMMC_ReceiveTestPatternFailed Receive test pattern failed. + * @retval kStatus_Fail Test failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t MMC_TestDataBusWidth(mmc_card_t *card, mmc_data_bus_width_t width); + +/*! + * @brief Send SET_BUS_WIDTH command to set the bus width. + * + * @param card Card descriptor. + * @param width Data bus width. + * @retval kStatus_SDMMC_ConfigureExtendedCsdFailed Configure extended CSD failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t MMC_SetDataBusWidth(mmc_card_t *card, mmc_data_bus_width_t width); + +/*! + * @brief Set max the bus width automatically + * + * @param card Card descriptor. + * @param targetTiming switch target timing + * @retval kStatus_SDMMC_SetDataBusWidthFailed switch fail. + * @retval kStatus_Success switch success. + */ +static status_t MMC_SetMaxDataBusWidth(mmc_card_t *card, mmc_high_speed_timing_t targetTiming); + +/*! + * @brief Switch the card to high speed mode + * + * @param card Card descriptor. + * @retval kStatus_SDMMC_ConfigureExtendedCsdFailed Configure extended CSD failed. + * @retval kStatus_SDMMC_CardNotSupport Card doesn't support high speed. + * @retval kStatus_Success Operate successfully. + */ +static status_t MMC_SelectBusTiming(mmc_card_t *card); + +/*! + * @brief select card HS_TIMING value and card driver strength + * + * @param card Card descriptor. + * @param timing Timing interface value. + * @param driverStrength driver strength value. + * @retval kStatus_Success switch success. + * @retval kStatus_SDMMC_ConfigureExtendedCsdFailed , config extend csd register fail. + */ +static status_t MMC_SwitchHSTiming(mmc_card_t *card, uint8_t timing, uint8_t driverStrength); + +/*! + * @brief switch to HS400 mode. + * + * @param card Card descriptor. + * @retval kStatus_SDMMC_ConfigureExtendedCsdFailed Configure extended CSD failed. + * @retval kStatus_SDMMC_SwitchBusTimingFailed switch bus timing fail. + * @retval kStatus_SDMMC_SetDataBusWidthFailed switch bus width fail. + * @retval kStatus_Success Operate successfully. + */ +static status_t MMC_SwitchToHS400(mmc_card_t *card); + +/*! + * @brief switch to HS200 mode. + * + * @param card Card descriptor. + * @param freq Target frequency. + * @retval kStatus_SDMMC_ConfigureExtendedCsdFailed Configure extended CSD failed. + * @retval kStatus_SDMMC_TuningFail tuning fail. + * @retval kStatus_SDMMC_SetDataBusWidthFailed switch bus width fail. + * @retval kStatus_Success Operate successfully. + */ +static status_t MMC_SwitchToHS200(mmc_card_t *card, uint32_t freq); + +/*! + * @brief switch to HS400 mode. + * + * @param card Card descriptor. + * @retval kStatus_SDMMC_ConfigureExtendedCsdFailed Configure extended CSD failed. + * @retval kStatus_SDMMC_SetDataBusWidthFailed switch bus width fail. + * @retval kStatus_Success Operate successfully. + */ +static status_t MMC_SwitchToHighSpeed(mmc_card_t *card); + +/*! + * @brief Decode CID register + * + * @param card Card descriptor. + * @param rawCid Raw CID register content. + */ +static void MMC_DecodeCid(mmc_card_t *card, uint32_t *rawCid); + +/*! + * @brief Send ALL_SEND_CID command + * + * @param card Card descriptor. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t MMC_AllSendCid(mmc_card_t *card); + +/*! + * @brief Send SEND_CSD command to get CSD from card + * + * @param card Card descriptor. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t MMC_SendCsd(mmc_card_t *card); + +/*! + * @brief Check if the block range accessed is within current partition. + * + * @param card Card descriptor. + * @param startBlock Start block to access. + * @param blockCount Block count to access. + * @retval kStatus_InvalidArgument Invalid argument. + * @retval kStatus_Success Operate successfully. + */ +static status_t MMC_CheckBlockRange(mmc_card_t *card, uint32_t startBlock, uint32_t blockCount); + +/*! + * @brief Check if the erase group range accessed is within current partition. + * + * @param card Card descriptor. + * @param startGroup Start group to access. + * @param endGroup End group to access. + * @retval kStatus_InvalidArgument Invalid argument. + * @retval kStatus_Success Operate successfully. + */ +static status_t MMC_CheckEraseGroupRange(mmc_card_t *card, uint32_t startGroup, uint32_t endGroup); + +/*! + * @brief MMC excute tuning function. + * + * @param card Card descriptor. + * @retval kStatus_Success Operate successfully. + * @retval kStatus_SDMMC_TuningFail tuning fail. + * @retval kStatus_SDMMC_TransferFailed transfer fail + */ +static status_t inline MMC_ExecuteTuning(mmc_card_t *card); + +/*! + * @brief Read data from specific MMC card + * + * @param card Card descriptor. + * @param buffer Buffer to save received data. + * @param startBlock Start block to read. + * @param blockSize Block size. + * @param blockCount Block count to read. + * @retval kStatus_SDMMC_CardNotSupport Card doesn't support. + * @retval kStatus_SDMMC_WaitWriteCompleteFailed Wait write complete failed. + * @retval kStatus_SDMMC_SetBlockCountFailed Set block count failed. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_SDMMC_StopTransmissionFailed Stop transmission failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t MMC_Read( + mmc_card_t *card, uint8_t *buffer, uint32_t startBlock, uint32_t blockSize, uint32_t blockCount); + +/*! + * @brief Write data from specific MMC card + * + * @param card Card descriptor. + * @param buffer Buffer to hold the data to write. + * @param startBlock Start block to write. + * @param blockSize Block size. + * @param blockCount Block count to write. + * @retval kStatus_SDMMC_CardNotSupport Card doesn't support. + * @retval kStatus_SDMMC_SetBlockCountFailed Set block count failed. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_SDMMC_StopTransmissionFailed Stop transmission failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t MMC_Write( + mmc_card_t *card, const uint8_t *buffer, uint32_t startBlock, uint32_t blockSize, uint32_t blockCount); + +/*! + * @brief card transfer function wrapper + * This function is used to do tuning before transfer if the cmd won't casue re-tuning + * request, then you can call host transfer function directly + * @param card Card descriptor. + * @param content Transfer content. + * @param retry Retry times. + * @retval kStatus_SDMMC_TransferFailed transfer fail + * @retval kStatus_SDMMC_TuningFail tuning fail + * @retval kStatus_Success transfer success + */ +static status_t MMC_Transfer(mmc_card_t *card, SDMMCHOST_TRANSFER *content, uint32_t retry); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* Frequency unit defined in TRANSFER SPEED field in CSD */ +static const uint32_t g_transerSpeedFrequencyUnit[] = {100000U, 1000000U, 10000000U, 100000000U}; +/* The multiplying value defined in TRANSFER SPEED field in CSD */ +static const uint32_t g_transerSpeedMultiplierFactor[] = {0U, 10U, 12U, 13U, 15U, 20U, 26U, 30U, + 35U, 40U, 45U, 52U, 55U, 60U, 70U, 80U}; +/* g_sdmmc statement */ +extern uint32_t g_sdmmc[SDK_SIZEALIGN(SDMMC_GLOBAL_BUFFER_SIZE, SDMMC_DATA_BUFFER_ALIGN_CACHE)]; + +/******************************************************************************* + * Code + ******************************************************************************/ +static status_t inline MMC_SelectCard(mmc_card_t *card, bool isSelected) +{ + assert(card); + + return SDMMC_SelectCard(card->host.base, card->host.transfer, card->relativeAddress, isSelected); +} + +static status_t inline MMC_SetBlockCount(mmc_card_t *card, uint32_t blockCount) +{ + assert(card); + + return SDMMC_SetBlockCount(card->host.base, card->host.transfer, blockCount); +} + +static status_t inline MMC_GoIdle(mmc_card_t *card) +{ + assert(card); + + return SDMMC_GoIdle(card->host.base, card->host.transfer); +} + +static status_t inline MMC_SetBlockSize(mmc_card_t *card, uint32_t blockSize) +{ + assert(card); + + return SDMMC_SetBlockSize(card->host.base, card->host.transfer, blockSize); +} + +static status_t MMC_ExecuteTuning(mmc_card_t *card) +{ + assert(card); + + uint32_t blockSize = 0U; + + if (card->busWidth == kMMC_DataBusWidth4bit) + { + blockSize = 64U; + } + else if (card->busWidth == kMMC_DataBusWidth8bit) + { + blockSize = 128U; + } + else + { + /* do not need tuning in this situation */ + return kStatus_Success; + } + + return SDMMC_ExecuteTuning(card->host.base, card->host.transfer, kMMC_SendTuningBlock, blockSize); +} + +static status_t MMC_Transfer(mmc_card_t *card, SDMMCHOST_TRANSFER *content, uint32_t retry) +{ + assert(card->host.transfer); + assert(content); + status_t error; + + do + { + error = card->host.transfer(card->host.base, content); +#if SDMMC_ENABLE_SOFTWARE_TUNING + if (((error == SDMMCHOST_RETUNING_REQUEST) || (error == SDMMCHOST_TUNING_ERROR)) && + ((card->busTiming == kMMC_HighSpeed200Timing) || (card->busTiming == kMMC_HighSpeed400Timing))) + { + /* tuning error need reset tuning circuit */ + if (error == SDMMCHOST_TUNING_ERROR) + { + SDMMCHOST_RESET_TUNING(card->host.base, 100U); + } + /* execute re-tuning */ + if (MMC_ExecuteTuning(card) != kStatus_Success) + { + error = kStatus_SDMMC_TuningFail; + break; + } + else + { + continue; + } + } + else +#endif + if (error != kStatus_Success) + { + error = kStatus_SDMMC_TransferFailed; + } + else + { + } + + if (retry != 0U) + { + retry--; + } + else + { + break; + } + + } while (error != kStatus_Success); + + return error; +} + +static status_t MMC_WaitWriteComplete(mmc_card_t *card) +{ + assert(card); + + SDMMCHOST_TRANSFER content = {0}; + SDMMCHOST_COMMAND command = {0}; + + command.index = kSDMMC_SendStatus; + command.argument = card->relativeAddress << 16U; + command.responseType = kCARD_ResponseTypeR1; + + do + { + content.command = &command; + content.data = 0U; + if (kStatus_Success != MMC_Transfer(card, &content, 2U)) + { + return kStatus_SDMMC_TransferFailed; + } + + /* check the response error */ + if ((command.response[0U] & (SDMMC_R1_ALL_ERROR_FLAG | SDMMC_MASK(kSDMMC_R1SwitchErrorFlag)))) + { + return kStatus_SDMMC_WaitWriteCompleteFailed; + } + + if ((command.response[0U] & SDMMC_MASK(kSDMMC_R1ReadyForDataFlag)) && + (SDMMC_R1_CURRENT_STATE(command.response[0U]) != kSDMMC_R1StateProgram)) + { + break; + } + } while (true); + + return kStatus_Success; +} + +static status_t MMC_StopTransmission(mmc_card_t *card) +{ + assert(card); + + SDMMCHOST_TRANSFER content = {0}; + SDMMCHOST_COMMAND command = {0}; + + command.index = kSDMMC_StopTransmission; + command.argument = 0U; + command.type = kCARD_CommandTypeAbort; + command.responseType = kCARD_ResponseTypeR1b; + command.responseErrorFlags = SDMMC_R1_ALL_ERROR_FLAG; + + content.command = &command; + content.data = 0U; + if (kStatus_Success != MMC_Transfer(card, &content, 2U)) + { + return kStatus_SDMMC_TransferFailed; + } + + return kStatus_Success; +} + +static status_t MMC_SwitchVoltage(mmc_card_t *card, uint32_t *opCode) +{ + mmc_voltage_window_t tempVoltage = kMMC_VoltageWindowNone; + /* Get host's voltage window. */ + if (((kSDMMCHOST_SupportV330 != SDMMCHOST_NOT_SUPPORT) || (kSDMMCHOST_SupportV300 != SDMMCHOST_NOT_SUPPORT)) && + (card->ocr & MMC_OCR_V270TO360_MASK) && ((card->hostVoltageWindowVCC == kMMC_VoltageWindowNone) || + (card->hostVoltageWindowVCC == kMMC_VoltageWindows270to360))) + { + /* Save host intended voltage range */ + tempVoltage = kMMC_VoltageWindows270to360; + /* set the opcode */ + *opCode = MMC_OCR_V270TO360_MASK; + /* power off the card first */ + SDMMCHOST_ENABLE_MMC_POWER(false); + /* power off time */ + SDMMCHOST_Delay(1U); + /*switch voltage to 3.3V*/ + SDMMCHOST_SWITCH_VCC_TO_330V(); + /* repower the card */ + SDMMCHOST_ENABLE_MMC_POWER(true); + /* meet emmc spec, wait 1ms and 74 clocks */ + SDMMCHOST_Delay(2U); + } + + if ((kSDMMCHOST_SupportV180 != SDMMCHOST_NOT_SUPPORT) && (card->ocr & MMC_OCR_V170TO195_MASK) && + ((card->hostVoltageWindowVCC == kMMC_VoltageWindowNone) || + (card->hostVoltageWindowVCC == kMMC_VoltageWindow170to195))) + { + /* Save host intended voltage range */ + tempVoltage = kMMC_VoltageWindow170to195; + /* set the opcode */ + *opCode = MMC_OCR_V170TO195_MASK; + /* power off the card first */ + SDMMCHOST_ENABLE_MMC_POWER(false); + /* power off time */ + SDMMCHOST_Delay(1U); + /* switch voltage to 1.8V */ + SDMMCHOST_SWITCH_VCC_TO_180V(); + /* repower the card */ + SDMMCHOST_ENABLE_MMC_POWER(true); + /* meet emmc spec, wait 1ms and 74 clocks */ + SDMMCHOST_Delay(2U); + } + + card->hostVoltageWindowVCC = tempVoltage; + + return kStatus_Success; +} + +static status_t MMC_SendOperationCondition(mmc_card_t *card, uint32_t arg) +{ + assert(card); + assert(card->host.transfer); + + SDMMCHOST_COMMAND command = {0}; + SDMMCHOST_TRANSFER content = {0}; + status_t error; + uint32_t i = FSL_SDMMC_MAX_VOLTAGE_RETRIES; + + /* Send CMD1 with the intended voltage range in the argument(either 0x00FF8000 or 0x00000080) */ + command.index = kMMC_SendOperationCondition; + command.argument = arg; + command.responseType = kCARD_ResponseTypeR3; + + content.command = &command; + content.data = NULL; + do + { + if (kStatus_Success != card->host.transfer(card->host.base, &content)) + { + return kStatus_SDMMC_TransferFailed; + } + + /* record OCR register */ + card->ocr = command.response[0U]; + + if ((arg == 0U) && (command.response[0U] != 0U)) + { + error = kStatus_Success; + } + /* Repeat CMD1 until the busy bit is cleared. */ + else if (!(command.response[0U] & MMC_OCR_BUSY_MASK)) + { + error = kStatus_Timeout; + } + else + { + error = kStatus_Success; + if (((card->ocr & MMC_OCR_ACCESS_MODE_MASK) >> MMC_OCR_ACCESS_MODE_SHIFT) == kMMC_AccessModeSector) + { + card->flags |= kMMC_SupportHighCapacityFlag; + } + } + } while ((i--) && (error != kStatus_Success)); + + return error; +} + +static status_t MMC_SetRelativeAddress(mmc_card_t *card) +{ + assert(card); + assert(card->host.transfer); + + SDMMCHOST_COMMAND command = {0}; + SDMMCHOST_TRANSFER content = {0}; + + /* Send CMD3 with a chosen relative address, with value greater than 1 */ + command.index = kMMC_SetRelativeAddress; + command.argument = (MMC_DEFAULT_RELATIVE_ADDRESS << 16U); + command.responseType = kCARD_ResponseTypeR1; + + content.command = &command; + content.data = NULL; + if ((kStatus_Success == card->host.transfer(card->host.base, &content)) || + (!((command.response[0U]) & SDMMC_R1_ALL_ERROR_FLAG))) + { + card->relativeAddress = MMC_DEFAULT_RELATIVE_ADDRESS; + return kStatus_Success; + } + + return kStatus_SDMMC_TransferFailed; +} + +static void MMC_DecodeCsd(mmc_card_t *card, uint32_t *rawCsd) +{ + assert(card); + assert(rawCsd); + + mmc_csd_t *csd; + uint32_t multiplier; + + csd = &(card->csd); + csd->csdStructureVersion = (uint8_t)((rawCsd[3U] & 0xC0000000U) >> 30U); + csd->systemSpecificationVersion = (uint8_t)((rawCsd[3U] & 0x3C000000U) >> 26U); + csd->dataReadAccessTime1 = (uint8_t)((rawCsd[3U] & 0xFF0000U) >> 16U); + csd->dataReadAccessTime2 = (uint8_t)((rawCsd[3U] & 0xFF00U) >> 8U); + csd->transferSpeed = (uint8_t)(rawCsd[3U] & 0xFFU); + csd->cardCommandClass = (uint16_t)((rawCsd[2U] & 0xFFF00000U) >> 20U); + /* Max block length read/write one time */ + csd->readBlockLength = (uint8_t)((rawCsd[2U] & 0xF0000U) >> 16U); + if (rawCsd[2U] & 0x8000U) + { + csd->flags |= kMMC_CsdReadBlockPartialFlag; + } + if (rawCsd[2U] & 0x4000U) + { + csd->flags |= kMMC_CsdWriteBlockMisalignFlag; + } + if (rawCsd[2U] & 0x2000U) + { + csd->flags |= kMMC_CsdReadBlockMisalignFlag; + } + if (rawCsd[2U] & 0x1000U) + { + csd->flags |= kMMC_CsdDsrImplementedFlag; + } + csd->deviceSize = (uint16_t)(((rawCsd[2U] & 0x3FFU) << 2U) + ((rawCsd[1U] & 0xC0000000U) >> 30U)); + csd->readCurrentVddMin = (uint8_t)((rawCsd[1U] & 0x38000000U) >> 27U); + csd->readCurrentVddMax = (uint8_t)((rawCsd[1U] & 0x07000000U) >> 24U); + csd->writeCurrentVddMin = (uint8_t)((rawCsd[1U] & 0x00E00000U) >> 21U); + csd->writeCurrentVddMax = (uint8_t)((rawCsd[1U] & 0x001C0000U) >> 18U); + csd->deviceSizeMultiplier = (uint8_t)((rawCsd[1U] & 0x00038000U) >> 15U); + csd->eraseGroupSize = (uint8_t)((rawCsd[1U] & 0x00007C00U) >> 10U); + csd->eraseGroupSizeMultiplier = (uint8_t)((rawCsd[1U] & 0x000003E0U) >> 5U); + csd->writeProtectGroupSize = (uint8_t)(rawCsd[1U] & 0x0000001FU); + if (rawCsd[0U] & 0x80000000U) + { + csd->flags |= kMMC_CsdWriteProtectGroupEnabledFlag; + } + csd->defaultEcc = (uint8_t)((rawCsd[0U] & 0x60000000U) >> 29U); + csd->writeSpeedFactor = (uint8_t)((rawCsd[0U] & 0x1C000000U) >> 26U); + csd->maxWriteBlockLength = (uint8_t)((rawCsd[0U] & 0x03C00000U) >> 22U); + if (rawCsd[0U] & 0x00200000U) + { + csd->flags |= kMMC_CsdWriteBlockPartialFlag; + } + if (rawCsd[0U] & 0x00010000U) + { + csd->flags |= kMMC_ContentProtectApplicationFlag; + } + if (rawCsd[0U] & 0x00008000U) + { + csd->flags |= kMMC_CsdFileFormatGroupFlag; + } + if (rawCsd[0U] & 0x00004000U) + { + csd->flags |= kMMC_CsdCopyFlag; + } + if (rawCsd[0U] & 0x00002000U) + { + csd->flags |= kMMC_CsdPermanentWriteProtectFlag; + } + if (rawCsd[0U] & 0x00001000U) + { + csd->flags |= kMMC_CsdTemporaryWriteProtectFlag; + } + csd->fileFormat = (uint8_t)((rawCsd[0U] & 0x00000C00U) >> 10U); + csd->eccCode = (uint8_t)((rawCsd[0U] & 0x00000300U) >> 8U); + + /* Calculate the device total block count. */ + /* For the card capacity of witch higher than 2GB, the maximum possible value should be set to this register + is 0xFFF. */ + if (card->csd.deviceSize != 0xFFFU) + { + multiplier = (2U << (card->csd.deviceSizeMultiplier + 2U - 1U)); + card->userPartitionBlocks = (((card->csd.deviceSize + 1U) * multiplier) / FSL_SDMMC_DEFAULT_BLOCK_SIZE); + } + + card->blockSize = FSL_SDMMC_DEFAULT_BLOCK_SIZE; +} + +static void MMC_SetMaxFrequency(mmc_card_t *card) +{ + assert(card); + + uint32_t frequencyUnit; + uint32_t multiplierFactor; + uint32_t maxBusClock_Hz; + + /* g_fsdhcCommandUnitInTranSpeed and g_transerSpeedMultiplierFactor are used to calculate the max speed in normal + mode not high speed mode. + For cards supporting version 4.0, 4.1, and 4.2 of the specification, the value shall be 20MHz(0x2A). + For cards supporting version 4.3, the value shall be 26 MHz (0x32H). In High speed mode, the max + frequency is decided by CARD_TYPE in Extended CSD. */ + frequencyUnit = g_transerSpeedFrequencyUnit[READ_MMC_TRANSFER_SPEED_FREQUENCY_UNIT(card->csd)]; + multiplierFactor = g_transerSpeedMultiplierFactor[READ_MMC_TRANSFER_SPEED_MULTIPLIER(card->csd)]; + maxBusClock_Hz = (frequencyUnit * multiplierFactor) / DIVIDER_IN_TRANSFER_SPEED; + card->busClock_Hz = SDMMCHOST_SET_CARD_CLOCK(card->host.base, card->host.sourceClock_Hz, maxBusClock_Hz); +} + +static status_t MMC_SetMaxEraseUnitSize(mmc_card_t *card) +{ + assert(card); + + uint32_t erase_group_size; + uint32_t erase_group_multiplier; + mmc_extended_csd_config_t extendedCsdconfig; + + if (((!(card->flags & kMMC_SupportHighCapacityFlag)) || (card->extendedCsd.highCapacityEraseUnitSize == 0)) || + (card->extendedCsd.highCapacityEraseTimeout == 0)) + { + erase_group_size = card->csd.eraseGroupSize; + erase_group_multiplier = card->csd.eraseGroupSizeMultiplier; + card->eraseGroupBlocks = ((erase_group_size + 1U) * (erase_group_multiplier + 1U)); + } + else + { + /* Erase Unit Size = 512Kbyte * HC_ERASE_GRP_SIZE. Block size is 512 bytes. */ + card->eraseGroupBlocks = (card->extendedCsd.highCapacityEraseUnitSize * 1024U); + /* Enable high capacity erase unit size. */ + extendedCsdconfig.accessMode = kMMC_ExtendedCsdAccessModeSetBits; + extendedCsdconfig.ByteIndex = kMMC_ExtendedCsdIndexEraseGroupDefinition; + extendedCsdconfig.ByteValue = 0x01U; /* The high capacity erase unit size enable bit is bit 0 */ + extendedCsdconfig.commandSet = kMMC_CommandSetStandard; + if (kStatus_Success != MMC_SetExtendedCsdConfig(card, &extendedCsdconfig)) + { + return kStatus_SDMMC_ConfigureExtendedCsdFailed; + } + } + + return kStatus_Success; +} + +static status_t MMC_SetExtendedCsdConfig(mmc_card_t *card, const mmc_extended_csd_config_t *config) +{ + assert(card); + assert(card->host.transfer); + assert(config); + + uint32_t parameter = 0U; + SDMMCHOST_COMMAND command = {0}; + SDMMCHOST_TRANSFER content = {0}; + + parameter |= ((uint32_t)(config->commandSet) << MMC_SWITCH_COMMAND_SET_SHIFT); + parameter |= ((uint32_t)(config->ByteValue) << MMC_SWITCH_VALUE_SHIFT); + parameter |= ((uint32_t)(config->ByteIndex) << MMC_SWITCH_BYTE_INDEX_SHIFT); + parameter |= ((uint32_t)(config->accessMode) << MMC_SWITCH_ACCESS_MODE_SHIFT); + + command.index = kMMC_Switch; + command.argument = parameter; + command.responseType = kCARD_ResponseTypeR1b; /* Send switch command to set the pointed byte in Extended CSD. */ + command.responseErrorFlags = SDMMC_R1_ALL_ERROR_FLAG | SDMMC_MASK(kSDMMC_R1SwitchErrorFlag); + + content.command = &command; + content.data = NULL; + if (kStatus_Success != MMC_Transfer(card, &content, 2U)) + { + return kStatus_SDMMC_TransferFailed; + } + + /* Wait for the card write process complete because of that card read process and write process use one buffer. */ + if (kStatus_Success != MMC_WaitWriteComplete(card)) + { + return kStatus_SDMMC_WaitWriteCompleteFailed; + } + + return kStatus_Success; +} + +static void MMC_DecodeExtendedCsd(mmc_card_t *card, uint32_t *rawExtendedCsd) +{ + assert(card); + assert(rawExtendedCsd); + + uint8_t *buffer = (uint8_t *)rawExtendedCsd; + mmc_extended_csd_t *extendedCsd = &(card->extendedCsd); + + /* Extended CSD is transferred as a data block from least byte indexed 0. */ + extendedCsd->bootPartitionWP = buffer[173U]; + extendedCsd->bootWPStatus = buffer[174U]; + extendedCsd->highDensityEraseGroupDefinition = buffer[175U]; + extendedCsd->bootDataBusConditions = buffer[177U]; + extendedCsd->bootConfigProtect = buffer[178U]; + extendedCsd->partitionConfig = buffer[179U]; + extendedCsd->eraseMemoryContent = buffer[181U]; + extendedCsd->dataBusWidth = buffer[183U]; + extendedCsd->highSpeedTiming = buffer[185U]; + extendedCsd->powerClass = buffer[187U]; + extendedCsd->commandSetRevision = buffer[189U]; + extendedCsd->commandSet = buffer[191U]; + extendedCsd->extendecCsdVersion = buffer[192U]; + extendedCsd->csdStructureVersion = buffer[194U]; + extendedCsd->partitionAttribute = buffer[156U]; + extendedCsd->extPartitionSupport = buffer[494U]; + extendedCsd->cardType = buffer[196U]; + /* This field define the type of the card. The only currently valid values for this field are 0x01 and 0x03. */ + card->flags |= extendedCsd->cardType; + + extendedCsd->ioDriverStrength = buffer[197U]; + + extendedCsd->powerClass52MHz195V = buffer[200U]; + extendedCsd->powerClass26MHz195V = buffer[201U]; + extendedCsd->powerClass52MHz360V = buffer[202U]; + extendedCsd->powerClass26MHz360V = buffer[203U]; + extendedCsd->powerClass200MHZVCCQ130VVCC360V = buffer[236U]; + extendedCsd->powerClass200MHZVCCQ195VVCC360V = buffer[237U]; + extendedCsd->powerClass52MHZDDR195V = buffer[238U]; + extendedCsd->powerClass52MHZDDR360V = buffer[239U]; + extendedCsd->powerClass200MHZDDR360V = buffer[253U]; + extendedCsd->minimumReadPerformance4Bit26MHz = buffer[205U]; + extendedCsd->minimumWritePerformance4Bit26MHz = buffer[206U]; + extendedCsd->minimumReadPerformance8Bit26MHz4Bit52MHz = buffer[207U]; + extendedCsd->minimumWritePerformance8Bit26MHz4Bit52MHz = buffer[208U]; + extendedCsd->minimumReadPerformance8Bit52MHz = buffer[209U]; + extendedCsd->minimumWritePerformance8Bit52MHz = buffer[210U]; + extendedCsd->minReadPerformance8bitAt52MHZDDR = buffer[234U]; + extendedCsd->minWritePerformance8bitAt52MHZDDR = buffer[235U]; + /* Get user partition size. */ + extendedCsd->sectorCount = ((((uint32_t)buffer[215U]) << 24U) + (((uint32_t)buffer[214U]) << 16U) + + (((uint32_t)buffer[213U]) << 8U) + (uint32_t)buffer[212U]); + if (card->flags & kMMC_SupportHighCapacityFlag) + { + card->userPartitionBlocks = card->extendedCsd.sectorCount; + } + + extendedCsd->sleepAwakeTimeout = buffer[217U]; + extendedCsd->sleepCurrentVCCQ = buffer[219U]; + extendedCsd->sleepCurrentVCC = buffer[220U]; + extendedCsd->highCapacityWriteProtectGroupSize = buffer[221U]; + extendedCsd->reliableWriteSectorCount = buffer[222U]; + extendedCsd->highCapacityEraseTimeout = buffer[223U]; + extendedCsd->highCapacityEraseUnitSize = buffer[224U]; + extendedCsd->accessSize = buffer[225U]; + + /* Get boot partition size: 128KB * BOOT_SIZE_MULT*/ + card->bootPartitionBlocks = ((128U * 1024U * buffer[226U]) / FSL_SDMMC_DEFAULT_BLOCK_SIZE); + + /* Check if card support boot mode. */ + if (buffer[228U] & 0x1U) + { + card->flags |= kMMC_SupportAlternateBootFlag; + } + else if (buffer[228U] & 0x2U) + { + card->flags |= kMMC_SupportDDRBootFlag; + } + else if (buffer[228U] & 0x4U) + { + card->flags |= kMMC_SupportHighSpeedBootFlag; + } + else + { + } + /* cache size unit 1kb */ + extendedCsd->cacheSize = (((uint32_t)buffer[252U]) << 24) | (((uint32_t)buffer[251U]) << 16) | + (((uint32_t)buffer[250U]) << 8) | (((uint32_t)buffer[249U])); + + extendedCsd->supportedCommandSet = buffer[504U]; +} + +static status_t MMC_SendExtendedCsd(mmc_card_t *card, uint8_t *targetAddr, uint32_t byteIndex) +{ + assert(card); + assert(card->host.transfer); + + SDMMCHOST_COMMAND command = {0}; + SDMMCHOST_TRANSFER content = {0}; + SDMMCHOST_DATA data = {0}; + uint32_t i; + + command.index = kMMC_SendExtendedCsd; + command.argument = 0U; + command.responseType = kCARD_ResponseTypeR1; + + data.blockCount = 1U; + data.blockSize = MMC_EXTENDED_CSD_BYTES; + data.rxData = card->rawExtendedCsd; + + content.command = &command; + content.data = &data; + if ((kStatus_Success == card->host.transfer(card->host.base, &content)) && + (!(command.response[0U] & SDMMC_R1_ALL_ERROR_FLAG))) + { + /* The response is from bit 127:8 in R2, corresponding to command.response[3][31:0] to + command.response[0U][31:8] */ + switch (card->host.config.endianMode) + { + case kSDMMCHOST_EndianModeLittle: + /* Doesn't need to switch byte sequence when decode bytes as little endian sequence. */ + break; + case kSDMMCHOST_EndianModeBig: + /* In big endian mode, the SD bus byte transferred first is the byte stored in highest position + in a word which cause 4 byte's sequence in a word is not consistent with their original sequence + from card. */ + for (i = 0U; i < MMC_EXTENDED_CSD_BYTES / 4U; i++) + { + card->rawExtendedCsd[i] = SWAP_WORD_BYTE_SEQUENCE(card->rawExtendedCsd[i]); + } + break; + case kSDMMCHOST_EndianModeHalfWordBig: + for (i = 0U; i < MMC_EXTENDED_CSD_BYTES / 4U; i++) + { + card->rawExtendedCsd[i] = SWAP_HALF_WROD_BYTE_SEQUENCE(card->rawExtendedCsd[i]); + } + break; + default: + return kStatus_SDMMC_NotSupportYet; + } + if (targetAddr != NULL) + { + *targetAddr = ((uint8_t *)card->rawExtendedCsd)[byteIndex]; + } + else + { + MMC_DecodeExtendedCsd(card, card->rawExtendedCsd); + } + + return kStatus_Success; + } + + return kStatus_SDMMC_TransferFailed; +} + +static status_t MMC_SetPowerClass(mmc_card_t *card) +{ + assert(card); + + uint8_t mask = 0, shift = 0U; + uint8_t powerClass = 0; + mmc_extended_csd_config_t extendedCsdconfig; + + if ((card->busWidth == kMMC_DataBusWidth4bit) || (card->busWidth == kMMC_DataBusWidth4bitDDR)) + { + mask = MMC_POWER_CLASS_4BIT_MASK; /* The mask of 4 bit bus width's power class */ + shift = 0U; + } + else if ((card->busWidth == kMMC_DataBusWidth8bit) || (card->busWidth == kMMC_DataBusWidth8bitDDR)) + { + mask = MMC_POWER_CLASS_8BIT_MASK; /* The mask of 8 bit bus width's power class */ + shift = 4U; + } + else + { + return kStatus_Success; + } + + switch (card->hostVoltageWindowVCC) + { + case kMMC_VoltageWindows270to360: + + if (card->busTiming == kMMC_HighSpeed200Timing) + { + if (card->hostVoltageWindowVCCQ == kMMC_VoltageWindow170to195) + { + powerClass = ((card->extendedCsd.powerClass200MHZVCCQ195VVCC360V) & mask); + } + else if (card->hostVoltageWindowVCCQ == kMMC_VoltageWindow120) + { + powerClass = ((card->extendedCsd.powerClass200MHZVCCQ130VVCC360V) & mask); + } + } + else if (card->busTiming == kMMC_HighSpeed400Timing) + { + powerClass = ((card->extendedCsd.powerClass200MHZDDR360V) & mask); + } + else if ((card->busTiming == kMMC_HighSpeedTiming) && (card->busWidth > kMMC_DataBusWidth8bit)) + { + powerClass = ((card->extendedCsd.powerClass52MHZDDR360V) & mask); + } + else if ((card->busTiming == kMMC_HighSpeedTiming) && (card->busClock_Hz > MMC_CLOCK_26MHZ)) + { + powerClass = ((card->extendedCsd.powerClass52MHz360V) & mask); + } + else if (card->busTiming == kMMC_HighSpeedTiming) + { + powerClass = ((card->extendedCsd.powerClass26MHz360V) & mask); + } + + break; + + case kMMC_VoltageWindow170to195: + + if ((card->busTiming == kMMC_HighSpeedTiming) && (card->busClock_Hz <= MMC_CLOCK_26MHZ)) + { + powerClass = ((card->extendedCsd.powerClass26MHz195V) & mask); + } + else if ((card->busTiming == kMMC_HighSpeedTiming) && (card->busClock_Hz > MMC_CLOCK_26MHZ)) + { + powerClass = ((card->extendedCsd.powerClass52MHz195V) & mask); + } + else if ((card->busTiming == kMMC_HighSpeedTiming) && (card->busWidth > kMMC_DataBusWidth8bit)) + { + powerClass = ((card->extendedCsd.powerClass52MHZDDR195V) & mask); + } + + break; + default: + powerClass = 0; + break; + } + + /* due to 8bit power class position [7:4] */ + powerClass >>= shift; + + if (powerClass > 0U) + { + extendedCsdconfig.accessMode = kMMC_ExtendedCsdAccessModeWriteBits; + extendedCsdconfig.ByteIndex = kMMC_ExtendedCsdIndexPowerClass; + extendedCsdconfig.ByteValue = powerClass; + extendedCsdconfig.commandSet = kMMC_CommandSetStandard; + if (kStatus_Success != MMC_SetExtendedCsdConfig(card, &extendedCsdconfig)) + { + return kStatus_SDMMC_ConfigureExtendedCsdFailed; + } + /* restore power class */ + card->extendedCsd.powerClass = powerClass; + } + + return kStatus_Success; +} + +static status_t MMC_SendTestPattern(mmc_card_t *card, uint32_t blockSize, uint32_t *pattern) +{ + assert(card); + assert(card->host.transfer); + assert(blockSize <= FSL_SDMMC_DEFAULT_BLOCK_SIZE); + assert(pattern); + + SDMMCHOST_TRANSFER content = {0}; + SDMMCHOST_COMMAND command = {0}; + SDMMCHOST_DATA data = {0}; + + command.index = kMMC_SendingBusTest; + command.argument = 0U; + command.responseType = kCARD_ResponseTypeR1; + + /* Ignore errors in bus test procedure to improve chances that the test will work. */ + data.enableIgnoreError = true; + data.blockCount = 1U; + data.blockSize = blockSize; + data.txData = pattern; + + content.command = &command; + content.data = &data; + if ((kStatus_Success != card->host.transfer(card->host.base, &content)) || + (command.response[0U] & SDMMC_R1_ALL_ERROR_FLAG)) + { + return kStatus_SDMMC_TransferFailed; + } + + return kStatus_Success; +} + +static status_t MMC_ReceiveTestPattern(mmc_card_t *card, uint32_t blockSize, uint32_t *pattern) +{ + assert(card); + assert(card->host.transfer); + assert(blockSize <= FSL_SDMMC_DEFAULT_BLOCK_SIZE); + assert(pattern); + + SDMMCHOST_TRANSFER content = {0}; + SDMMCHOST_COMMAND command = {0}; + SDMMCHOST_DATA data = {0}; + + command.index = kMMC_BusTestRead; + command.responseType = kCARD_ResponseTypeR1; + + /* Ignore errors in bus test procedure to improve chances that the test will work. */ + data.enableIgnoreError = true; + data.blockCount = 1U; + data.blockSize = blockSize; + data.rxData = pattern; + + content.command = &command; + content.data = &data; + if ((kStatus_Success != card->host.transfer(card->host.base, &content)) || + ((command.response[0U]) & SDMMC_R1_ALL_ERROR_FLAG)) + { + return kStatus_SDMMC_TransferFailed; + } + + return kStatus_Success; +} + +static status_t MMC_TestDataBusWidth(mmc_card_t *card, mmc_data_bus_width_t width) +{ + assert(card); + + uint32_t blockSize = 0U; + uint32_t tempsendPattern = 0U; + uint32_t *tempPattern = g_sdmmc; + uint32_t xorMask = 0U; + uint32_t xorResult = 0U; + + /* For 8 data lines the data block would be (MSB to LSB): 0x0000_0000_0000_AA55, + For 4 data lines the data block would be (MSB to LSB): 0x0000_005A, + For only 1 data line the data block would be: 0x80 */ + switch (width) + { + case kMMC_DataBusWidth8bit: + case kMMC_DataBusWidth8bitDDR: + blockSize = 8U; + tempPattern[0U] = 0xAA55U; + xorMask = 0xFFFFU; + xorResult = 0xFFFFU; + break; + case kMMC_DataBusWidth4bit: + case kMMC_DataBusWidth4bitDDR: + blockSize = 4U; + tempPattern[0U] = 0x5AU; + xorMask = 0xFFU; + xorResult = 0xFFU; + break; + default: + blockSize = 4U; + tempPattern[0U] = 0x80U; + xorMask = 0xFFU; + xorResult = 0xC0U; + break; + } + switch (card->host.config.endianMode) + { + case kSDMMCHOST_EndianModeLittle: + /* Doesn't need to switch byte sequence when decodes bytes as little endian sequence. */ + break; + case kSDMMCHOST_EndianModeBig: + /* In big endian mode, the byte transferred first is the byte stored in highest byte position in a word + which will cause the card receive the inverted byte sequence in a word in bus test procedure. So the + sequence of 4 bytes stored in a word should be converted. */ + tempPattern[0] = SWAP_WORD_BYTE_SEQUENCE(tempPattern[0]); + xorMask = SWAP_WORD_BYTE_SEQUENCE(xorMask); + xorResult = SWAP_WORD_BYTE_SEQUENCE(xorResult); + break; + case kSDMMCHOST_EndianModeHalfWordBig: + /* In half word big endian mode, the byte transferred first is the lower byte in the higher half word. + 0xAA55U should be converted to 0xAA550000U to set the 0x55 to be the first byte to transfer. */ + tempPattern[0] = SWAP_HALF_WROD_BYTE_SEQUENCE(tempPattern[0]); + xorMask = SWAP_HALF_WROD_BYTE_SEQUENCE(xorMask); + xorResult = SWAP_HALF_WROD_BYTE_SEQUENCE(xorResult); + tempPattern[0] = SWAP_WORD_BYTE_SEQUENCE(tempPattern[0]); + xorMask = SWAP_WORD_BYTE_SEQUENCE(xorMask); + xorResult = SWAP_WORD_BYTE_SEQUENCE(xorResult); + break; + default: + return kStatus_SDMMC_NotSupportYet; + } + + if (kStatus_Success != MMC_SendTestPattern(card, blockSize, tempPattern)) + { + return kStatus_SDMMC_SendTestPatternFailed; + } + /* restore the send pattern */ + tempsendPattern = tempPattern[0U]; + /* reset the global buffer */ + tempPattern[0U] = 0U; + + if (kStatus_Success != MMC_ReceiveTestPattern(card, blockSize, tempPattern)) + { + return kStatus_SDMMC_ReceiveTestPatternFailed; + } + + /* XOR the send pattern and receive pattern */ + if (((tempPattern[0U] ^ tempsendPattern) & xorMask) != xorResult) + { + return kStatus_Fail; + } + + return kStatus_Success; +} + +static status_t MMC_SetDataBusWidth(mmc_card_t *card, mmc_data_bus_width_t width) +{ + assert(card); + + mmc_extended_csd_config_t extendedCsdconfig; + + /* Set data bus width */ + extendedCsdconfig.accessMode = kMMC_ExtendedCsdAccessModeWriteBits; + extendedCsdconfig.ByteIndex = kMMC_ExtendedCsdIndexBusWidth; + extendedCsdconfig.ByteValue = width; + extendedCsdconfig.commandSet = kMMC_CommandSetStandard; + if (kStatus_Success != MMC_SetExtendedCsdConfig(card, &extendedCsdconfig)) + { + return kStatus_SDMMC_ConfigureExtendedCsdFailed; + } + /* restore data bus width */ + card->extendedCsd.dataBusWidth = width; + + return kStatus_Success; +} + +static status_t MMC_SetMaxDataBusWidth(mmc_card_t *card, mmc_high_speed_timing_t targetTiming) +{ + assert(card); + + status_t error = kStatus_Fail; + + switch (card->busWidth) + { + case kMMC_DataBusWidth1bit: + case kMMC_DataBusWidth8bitDDR: + /* Test and set the data bus width for card. */ + if ((SDMMCHOST_NOT_SUPPORT != kSDMMCHOST_Support8BitBusWidth) && + (card->flags & (kMMC_SupportHighSpeedDDR52MHZ180V300VFlag | kMMC_SupportHighSpeedDDR52MHZ120VFlag)) && + ((targetTiming == kMMC_HighSpeedTiming) || (targetTiming == kMMC_HighSpeed400Timing))) + { + SDMMCHOST_SET_CARD_BUS_WIDTH(card->host.base, kSDMMCHOST_DATABUSWIDTH8BIT); + if ((kStatus_Success == MMC_TestDataBusWidth(card, kMMC_DataBusWidth8bitDDR)) && + (kStatus_Success == MMC_SetDataBusWidth(card, kMMC_DataBusWidth8bitDDR))) + { + error = kStatus_Success; + card->busWidth = kMMC_DataBusWidth8bitDDR; + break; + } + /* HS400 mode only support 8bit data bus */ + else if (card->busTiming == kMMC_HighSpeed400Timing) + { + return kStatus_SDMMC_SetDataBusWidthFailed; + } + } + case kMMC_DataBusWidth4bitDDR: + if ((SDMMCHOST_NOT_SUPPORT != kSDMMCHOST_Support4BitBusWidth) && + (card->flags & (kMMC_SupportHighSpeedDDR52MHZ180V300VFlag | kMMC_SupportHighSpeedDDR52MHZ120VFlag)) && + ((targetTiming == kMMC_HighSpeedTiming) || (targetTiming == kMMC_HighSpeed400Timing))) + { + SDMMCHOST_SET_CARD_BUS_WIDTH(card->host.base, kSDMMCHOST_DATABUSWIDTH4BIT); + if ((kStatus_Success == MMC_TestDataBusWidth(card, kMMC_DataBusWidth4bitDDR)) && + (kStatus_Success == MMC_SetDataBusWidth(card, kMMC_DataBusWidth4bitDDR))) + { + error = kStatus_Success; + card->busWidth = kMMC_DataBusWidth4bitDDR; + + break; + } + } + case kMMC_DataBusWidth8bit: + if ((SDMMCHOST_NOT_SUPPORT != kSDMMCHOST_Support8BitBusWidth) && + ((targetTiming == kMMC_HighSpeedTiming) || (targetTiming == kMMC_HighSpeed200Timing))) + { + SDMMCHOST_SET_CARD_BUS_WIDTH(card->host.base, kSDMMCHOST_DATABUSWIDTH8BIT); + if ((kStatus_Success == MMC_TestDataBusWidth(card, kMMC_DataBusWidth8bit)) && + (kStatus_Success == MMC_SetDataBusWidth(card, kMMC_DataBusWidth8bit))) + { + error = kStatus_Success; + card->busWidth = kMMC_DataBusWidth8bit; + break; + } + } + + case kMMC_DataBusWidth4bit: + if ((SDMMCHOST_NOT_SUPPORT != kSDMMCHOST_Support4BitBusWidth) && + ((targetTiming == kMMC_HighSpeedTiming) || (targetTiming == kMMC_HighSpeed200Timing))) + { + SDMMCHOST_SET_CARD_BUS_WIDTH(card->host.base, kSDMMCHOST_DATABUSWIDTH4BIT); + if ((kStatus_Success == MMC_TestDataBusWidth(card, kMMC_DataBusWidth4bit)) && + (kStatus_Success == MMC_SetDataBusWidth(card, kMMC_DataBusWidth4bit))) + { + error = kStatus_Success; + card->busWidth = kMMC_DataBusWidth4bit; + break; + } + /* HS200 mode only support 4bit/8bit data bus */ + else if (targetTiming == kMMC_HighSpeed200Timing) + { + return kStatus_SDMMC_SetDataBusWidthFailed; + } + } + default: + break; + } + + if (error == kStatus_Fail) + { + /* Card's data bus width will be default 1 bit mode. */ + SDMMCHOST_SET_CARD_BUS_WIDTH(card->host.base, kSDMMCHOST_DATABUSWIDTH1BIT); + } + + return kStatus_Success; +} + +static status_t MMC_SwitchHSTiming(mmc_card_t *card, uint8_t timing, uint8_t driverStrength) +{ + assert(card); + + uint8_t hsTiming = 0; + + mmc_extended_csd_config_t extendedCsdconfig; + + /* check the target driver strength support or not */ + if (((card->extendedCsd.ioDriverStrength & (1 << driverStrength)) == 0U) && + (card->extendedCsd.extendecCsdVersion >= kMMC_ExtendedCsdRevision17)) + { + return kStatus_SDMMC_NotSupportYet; + } + /* calucate the register value */ + hsTiming = (timing & 0xF) | (uint8_t)(driverStrength << 4U); + + /* Switch to high speed timing. */ + extendedCsdconfig.accessMode = kMMC_ExtendedCsdAccessModeWriteBits; + extendedCsdconfig.ByteIndex = kMMC_ExtendedCsdIndexHighSpeedTiming; + extendedCsdconfig.ByteValue = hsTiming; + extendedCsdconfig.commandSet = kMMC_CommandSetStandard; + if (kStatus_Success != MMC_SetExtendedCsdConfig(card, &extendedCsdconfig)) + { + return kStatus_SDMMC_ConfigureExtendedCsdFailed; + } + + card->extendedCsd.highSpeedTiming = hsTiming; + + return kStatus_Success; +} + +static status_t MMC_SwitchToHighSpeed(mmc_card_t *card) +{ + assert(card); + + uint32_t freq = 0U; + + /* check VCCQ voltage supply */ + if (kSDMMCHOST_SupportV180 != SDMMCHOST_NOT_SUPPORT) + { + if ((card->hostVoltageWindowVCCQ != kMMC_VoltageWindow170to195) && + (card->extendedCsd.extendecCsdVersion > kMMC_ExtendedCsdRevision10)) + { + SDMMCHOST_SWITCH_VOLTAGE180V(card->host.base, true); + card->hostVoltageWindowVCCQ = kMMC_VoltageWindow170to195; + } + } + else if (kSDMMCHOST_SupportV120 != SDMMCHOST_NOT_SUPPORT) + { + if ((card->hostVoltageWindowVCCQ != kMMC_VoltageWindow120) && + (card->extendedCsd.extendecCsdVersion >= kMMC_ExtendedCsdRevision16)) + { + SDMMCHOST_SWITCH_VOLTAGE120V(card->host.base, true); + card->hostVoltageWindowVCCQ = kMMC_VoltageWindow120; + } + } + else + { + card->hostVoltageWindowVCCQ = kMMC_VoltageWindows270to360; + } + + if (kStatus_Success != MMC_SwitchHSTiming(card, kMMC_HighSpeedTiming, kMMC_DriverStrength0)) + { + return kStatus_SDMMC_SwitchBusTimingFailed; + } + + if ((card->busWidth == kMMC_DataBusWidth4bitDDR) || (card->busWidth == kMMC_DataBusWidth8bitDDR)) + { + freq = MMC_CLOCK_DDR52; + SDMMCHOST_ENABLE_DDR_MODE(card->host.base, true, 0U); + } + else if (card->flags & kMMC_SupportHighSpeed52MHZFlag) + { + freq = MMC_CLOCK_52MHZ; + } + else if (card->flags & kMMC_SupportHighSpeed26MHZFlag) + { + freq = MMC_CLOCK_26MHZ; + } + + card->busClock_Hz = SDMMCHOST_SET_CARD_CLOCK(card->host.base, card->host.sourceClock_Hz, freq); + /* config io speed and strength */ + SDMMCHOST_CONFIG_MMC_IO(CARD_BUS_FREQ_100MHZ1, CARD_BUS_STRENGTH_7); + + /* Set card data width, it is nessesary to config the the data bus here, to meet emmc5.0 specification, + * when you are working in DDR mode , HS_TIMING must set before set bus width + */ + if (MMC_SetMaxDataBusWidth(card, kMMC_HighSpeedTiming) != kStatus_Success) + { + return kStatus_SDMMC_SetDataBusWidthFailed; + } + + card->busTiming = kMMC_HighSpeedTiming; + + return kStatus_Success; +} + +static status_t MMC_SwitchToHS200(mmc_card_t *card, uint32_t freq) +{ + assert(card); + + /* check VCCQ voltage supply */ + if (kSDMMCHOST_SupportV180 != SDMMCHOST_NOT_SUPPORT) + { + if (card->hostVoltageWindowVCCQ != kMMC_VoltageWindow170to195) + { + SDMMCHOST_SWITCH_VOLTAGE180V(card->host.base, true); + card->hostVoltageWindowVCCQ = kMMC_VoltageWindow170to195; + } + } + else if (kSDMMCHOST_SupportV120 != SDMMCHOST_NOT_SUPPORT) + { + if (card->hostVoltageWindowVCCQ != kMMC_VoltageWindow120) + { + SDMMCHOST_SWITCH_VOLTAGE120V(card->host.base, true); + card->hostVoltageWindowVCCQ = kMMC_VoltageWindow120; + } + } + else + { + return kStatus_SDMMC_InvalidVoltage; + } + + /* select bus width before select bus timing for HS200 mode */ + if (MMC_SetMaxDataBusWidth(card, kMMC_HighSpeed200Timing) != kStatus_Success) + { + return kStatus_SDMMC_SetDataBusWidthFailed; + } + + /* switch to HS200 mode */ + if (kStatus_Success != MMC_SwitchHSTiming(card, kMMC_HighSpeed200Timing, kMMC_DriverStrength0)) + { + return kStatus_SDMMC_SwitchBusTimingFailed; + } + + card->busClock_Hz = SDMMCHOST_SET_CARD_CLOCK(card->host.base, card->host.sourceClock_Hz, freq); + /* config io speed and strength */ + SDMMCHOST_CONFIG_MMC_IO(CARD_BUS_FREQ_200MHZ, CARD_BUS_STRENGTH_7); + + /* excute tuning for HS200 */ + if (MMC_ExecuteTuning(card) != kStatus_Success) + { + return kStatus_SDMMC_TuningFail; + } + + /* Wait for the card status ready. */ + if (kStatus_Success != MMC_WaitWriteComplete(card)) + { + return kStatus_SDMMC_WaitWriteCompleteFailed; + } + + card->busTiming = kMMC_HighSpeed200Timing; + + return kStatus_Success; +} + +static status_t MMC_SwitchToHS400(mmc_card_t *card) +{ + assert(card); + + /* check VCCQ voltage supply */ + if (kSDMMCHOST_SupportV180 != SDMMCHOST_NOT_SUPPORT) + { + if (card->hostVoltageWindowVCCQ != kMMC_VoltageWindow170to195) + { + SDMMCHOST_SWITCH_VOLTAGE180V(card->host.base, true); + card->hostVoltageWindowVCCQ = kMMC_VoltageWindow170to195; + } + } + else if (kSDMMCHOST_SupportV120 != SDMMCHOST_NOT_SUPPORT) + { + if (card->hostVoltageWindowVCCQ != kMMC_VoltageWindow120) + { + SDMMCHOST_SWITCH_VOLTAGE120V(card->host.base, true); + card->hostVoltageWindowVCCQ = kMMC_VoltageWindow120; + } + } + else + { + return kStatus_SDMMC_InvalidVoltage; + } + + /* check data bus width is 8 bit , otherwise return false */ + if (card->busWidth == kMMC_DataBusWidth8bit) + { + return kStatus_SDMMC_SwitchBusTimingFailed; + } + + /* switch to high speed first */ + card->busClock_Hz = SDMMCHOST_SET_CARD_CLOCK(card->host.base, card->host.sourceClock_Hz, MMC_CLOCK_52MHZ); + SDMMCHOST_CONFIG_MMC_IO(CARD_BUS_FREQ_100MHZ1, CARD_BUS_STRENGTH_5); + /*switch to high speed*/ + if (kStatus_Success != MMC_SwitchHSTiming(card, kMMC_HighSpeedTiming, kMMC_DriverStrength0)) + { + return kStatus_SDMMC_ConfigureExtendedCsdFailed; + } + card->busTiming = kMMC_HighSpeed400Timing; + /* switch to 8 bit DDR data bus width */ + if (kStatus_Success != MMC_SetDataBusWidth(card, kMMC_DataBusWidth8bitDDR)) + { + return kStatus_SDMMC_SetDataBusWidthFailed; + } + /* switch to HS400 */ + if (kStatus_Success != MMC_SwitchHSTiming(card, kMMC_HighSpeed400Timing, kMMC_DriverStrength0)) + { + return kStatus_SDMMC_SwitchBusTimingFailed; + } + /* config to target freq */ + card->busClock_Hz = + SDMMCHOST_SET_CARD_CLOCK(card->host.base, card->host.sourceClock_Hz, SDMMCHOST_SUPPORT_HS400_FREQ); + /* config io speed and strength */ + SDMMCHOST_CONFIG_MMC_IO(CARD_BUS_FREQ_200MHZ, CARD_BUS_STRENGTH_7); + /* enable HS400 mode */ + SDMMCHOST_ENABLE_HS400_MODE(card->host.base, true); + /* enable DDR mode */ + SDMMCHOST_ENABLE_DDR_MODE(card->host.base, true, 0U); + /* config strobe DLL */ + SDMMCHOST_CONFIG_STROBE_DLL(card->host.base, SDMMCHOST_STROBE_DLL_DELAY_TARGET, + SDMMCHOST_STROBE_DLL_DELAY_UPDATE_INTERVAL); + /* enable DLL */ + SDMMCHOST_ENABLE_STROBE_DLL(card->host.base, true); + + return kStatus_Success; +} + +static status_t MMC_SelectBusTiming(mmc_card_t *card) +{ + assert(card); + + mmc_high_speed_timing_t targetTiming = card->busTiming; + + switch (targetTiming) + { + case kMMC_HighSpeedTimingNone: + case kMMC_HighSpeed400Timing: + if ((card->flags & (kMMC_SupportHS400DDR200MHZ180VFlag | kMMC_SupportHS400DDR200MHZ120VFlag)) && + ((kSDMMCHOST_SupportHS400 != SDMMCHOST_NOT_SUPPORT))) + { + /* switch to HS200 perform tuning */ + if (kStatus_Success != MMC_SwitchToHS200(card, SDMMCHOST_SUPPORT_HS400_FREQ / 2U)) + { + return kStatus_SDMMC_SwitchBusTimingFailed; + } + /* switch to HS400 */ + if (kStatus_Success != MMC_SwitchToHS400(card)) + { + return kStatus_SDMMC_SwitchBusTimingFailed; + } + break; + } + case kMMC_HighSpeed200Timing: + if ((card->flags & (kMMC_SupportHS200200MHZ180VFlag | kMMC_SupportHS200200MHZ120VFlag)) && + ((kSDMMCHOST_SupportHS200 != SDMMCHOST_NOT_SUPPORT))) + { + if (kStatus_Success != MMC_SwitchToHS200(card, SDMMCHOST_SUPPORT_HS200_FREQ)) + { + return kStatus_SDMMC_SwitchBusTimingFailed; + } + break; + } + case kMMC_HighSpeedTiming: + if (kStatus_Success != MMC_SwitchToHighSpeed(card)) + { + return kStatus_SDMMC_SwitchBusTimingFailed; + } + break; + + default: + card->busTiming = kMMC_HighSpeedTimingNone; + } + + return kStatus_Success; +} + +static void MMC_DecodeCid(mmc_card_t *card, uint32_t *rawCid) +{ + assert(card); + assert(rawCid); + + mmc_cid_t *cid; + + cid = &(card->cid); + cid->manufacturerID = (uint8_t)((rawCid[3U] & 0xFF000000U) >> 24U); + cid->applicationID = (uint16_t)((rawCid[3U] & 0xFFFF00U) >> 8U); + + cid->productName[0U] = (uint8_t)((rawCid[3U] & 0xFFU)); + cid->productName[1U] = (uint8_t)((rawCid[2U] & 0xFF000000U) >> 24U); + cid->productName[2U] = (uint8_t)((rawCid[2U] & 0xFF0000U) >> 16U); + cid->productName[3U] = (uint8_t)((rawCid[2U] & 0xFF00U) >> 8U); + cid->productName[4U] = (uint8_t)((rawCid[2U] & 0xFFU)); + + cid->productVersion = (uint8_t)((rawCid[1U] & 0xFF000000U) >> 24U); + + cid->productSerialNumber = (uint32_t)((rawCid[1U] & 0xFFFFFFU) << 8U); + cid->productSerialNumber |= (uint32_t)((rawCid[0U] & 0xFF000000U) >> 24U); + + cid->manufacturerData = (uint16_t)((rawCid[0U] & 0xFFF00U) >> 8U); +} + +static status_t MMC_AllSendCid(mmc_card_t *card) +{ + assert(card); + assert(card->host.transfer); + + SDMMCHOST_TRANSFER content = {0}; + SDMMCHOST_COMMAND command = {0}; + + command.index = kSDMMC_AllSendCid; + command.argument = 0U; + command.responseType = kCARD_ResponseTypeR2; + + content.command = &command; + content.data = NULL; + if (kStatus_Success == card->host.transfer(card->host.base, &content)) + { + memcpy(card->rawCid, command.response, sizeof(card->rawCid)); + MMC_DecodeCid(card, command.response); + + return kStatus_Success; + } + + return kStatus_SDMMC_TransferFailed; +} + +static status_t MMC_SendCsd(mmc_card_t *card) +{ + assert(card); + assert(card->host.transfer); + + SDMMCHOST_COMMAND command = {0}; + SDMMCHOST_TRANSFER content = {0}; + + command.index = kSDMMC_SendCsd; + command.argument = (card->relativeAddress << 16U); + command.responseType = kCARD_ResponseTypeR2; + + content.command = &command; + content.data = 0U; + if (kStatus_Success == card->host.transfer(card->host.base, &content)) + { + memcpy(card->rawCsd, command.response, sizeof(card->rawCsd)); + /* The response is from bit 127:8 in R2, corresponding to command.response[3][31:0] to + command.response[0U][31:8]. */ + MMC_DecodeCsd(card, card->rawCsd); + + return kStatus_Success; + } + + return kStatus_SDMMC_TransferFailed; +} + +static status_t MMC_CheckBlockRange(mmc_card_t *card, uint32_t startBlock, uint32_t blockCount) +{ + assert(card); + assert(blockCount); + + status_t error = kStatus_Success; + uint32_t partitionBlocks; + + switch (card->currentPartition) + { + case kMMC_AccessPartitionUserAera: + { + partitionBlocks = card->userPartitionBlocks; + break; + } + case kMMC_AccessPartitionBoot1: + case kMMC_AccessPartitionBoot2: + { + /* Boot partition 1 and partition 2 have the same partition size. */ + partitionBlocks = card->bootPartitionBlocks; + break; + } + default: + error = kStatus_InvalidArgument; + break; + } + /* Check if the block range accessed is within current partition's block boundary. */ + if ((error == kStatus_Success) && ((startBlock + blockCount) > partitionBlocks)) + { + error = kStatus_InvalidArgument; + } + + return error; +} + +static status_t MMC_CheckEraseGroupRange(mmc_card_t *card, uint32_t startGroup, uint32_t endGroup) +{ + assert(card); + + status_t error = kStatus_Success; + uint32_t partitionBlocks; + uint32_t eraseGroupBoundary; + + switch (card->currentPartition) + { + case kMMC_AccessPartitionUserAera: + { + partitionBlocks = card->userPartitionBlocks; + break; + } + case kMMC_AccessPartitionBoot1: + case kMMC_AccessPartitionBoot2: + { + /* Boot partition 1 and partition 2 have the same partition size. */ + partitionBlocks = card->bootPartitionBlocks; + break; + } + default: + error = kStatus_InvalidArgument; + break; + } + + if (error == kStatus_Success) + { + /* Check if current partition's total block count is integer multiples of the erase group size. */ + if ((partitionBlocks % card->eraseGroupBlocks) == 0U) + { + eraseGroupBoundary = (partitionBlocks / card->eraseGroupBlocks); + } + else + { + /* Card will ignore the unavailable blocks within the last erase group automatically. */ + eraseGroupBoundary = (partitionBlocks / card->eraseGroupBlocks + 1U); + } + + /* Check if the group range accessed is within current partition's erase group boundary. */ + if ((startGroup > eraseGroupBoundary) || (endGroup > eraseGroupBoundary)) + { + error = kStatus_InvalidArgument; + } + } + + return error; +} + +static status_t MMC_Read( + mmc_card_t *card, uint8_t *buffer, uint32_t startBlock, uint32_t blockSize, uint32_t blockCount) +{ + assert(card); + assert(card->host.transfer); + assert(buffer); + assert(blockCount); + assert(blockSize); + assert(blockSize == FSL_SDMMC_DEFAULT_BLOCK_SIZE); + + SDMMCHOST_COMMAND command = {0}; + SDMMCHOST_DATA data = {0}; + SDMMCHOST_TRANSFER content = {0}; + status_t error; + + if (((card->flags & kMMC_SupportHighCapacityFlag) && (blockSize != 512U)) || (blockSize > card->blockSize) || + (blockSize > card->host.capability.maxBlockLength) || (blockSize % 4U)) + { + return kStatus_SDMMC_CardNotSupport; + } + + /* Wait for the card write process complete because of that card read process and write process use one buffer. */ + if (kStatus_Success != MMC_WaitWriteComplete(card)) + { + return kStatus_SDMMC_WaitWriteCompleteFailed; + } + + data.blockSize = blockSize; + data.blockCount = blockCount; + data.rxData = (uint32_t *)buffer; + data.enableAutoCommand12 = true; + command.index = kSDMMC_ReadMultipleBlock; + if (data.blockCount == 1U) + { + command.index = kSDMMC_ReadSingleBlock; + } + else + { + if ((!(data.enableAutoCommand12)) && (card->enablePreDefinedBlockCount)) + { + /* If enabled the pre-define count read/write feature of the card, need to set block count firstly. */ + if (kStatus_Success != MMC_SetBlockCount(card, blockCount)) + { + return kStatus_SDMMC_SetBlockCountFailed; + } + } + } + command.argument = startBlock; + if (!(card->flags & kMMC_SupportHighCapacityFlag)) + { + command.argument *= data.blockSize; + } + command.responseType = kCARD_ResponseTypeR1; + command.responseErrorFlags = SDMMC_R1_ALL_ERROR_FLAG; + + content.command = &command; + content.data = &data; + + /* should check tuning error during every transfer */ + error = MMC_Transfer(card, &content, 1U); + if (kStatus_Success != error) + { + return error; + } + + /* When host's AUTO_COMMAND12 feature isn't enabled and PRE_DEFINED_COUNT command isn't enabled in multiple + blocks transmission, sends STOP_TRANSMISSION command. */ + if ((blockCount > 1U) && (!(data.enableAutoCommand12)) && (!card->enablePreDefinedBlockCount)) + { + if (kStatus_Success != MMC_StopTransmission(card)) + { + return kStatus_SDMMC_StopTransmissionFailed; + } + } + + return kStatus_Success; +} + +static status_t MMC_Write( + mmc_card_t *card, const uint8_t *buffer, uint32_t startBlock, uint32_t blockSize, uint32_t blockCount) +{ + assert(card); + assert(card->host.transfer); + assert(buffer); + assert(blockCount); + assert(blockSize); + assert(blockSize == FSL_SDMMC_DEFAULT_BLOCK_SIZE); + + SDMMCHOST_COMMAND command = {0}; + SDMMCHOST_DATA data = {0}; + SDMMCHOST_TRANSFER content = {0}; + status_t error; + + /* Check address range */ + if (((card->flags & kMMC_SupportHighCapacityFlag) && (blockSize != 512U)) || (blockSize > card->blockSize) || + (blockSize > card->host.capability.maxBlockLength) || (blockSize % 4U)) + { + return kStatus_SDMMC_CardNotSupport; + } + + /* Wait for the card's buffer to be not full to write to improve the write performance. */ + while ((GET_SDMMCHOST_STATUS(card->host.base) & CARD_DATA0_STATUS_MASK) != CARD_DATA0_NOT_BUSY) + { + } + + /* Wait for the card write process complete */ + if (kStatus_Success != MMC_WaitWriteComplete(card)) + { + return kStatus_SDMMC_WaitWriteCompleteFailed; + } + + data.blockSize = blockSize; + data.blockCount = blockCount; + data.txData = (const uint32_t *)buffer; + data.enableAutoCommand12 = true; + + command.index = kSDMMC_WriteMultipleBlock; + if (data.blockCount == 1U) + { + command.index = kSDMMC_WriteSingleBlock; + } + else + { + if ((!(data.enableAutoCommand12)) && (card->enablePreDefinedBlockCount)) + { + /* If enabled the pre-define count read/write featue of the card, need to set block count firstly */ + if (kStatus_Success != MMC_SetBlockCount(card, blockCount)) + { + return kStatus_SDMMC_SetBlockCountFailed; + } + } + } + command.argument = startBlock; + if (!(card->flags & kMMC_SupportHighCapacityFlag)) + { + command.argument *= blockSize; + } + command.responseType = kCARD_ResponseTypeR1; + command.responseErrorFlags = SDMMC_R1_ALL_ERROR_FLAG; + + content.command = &command; + content.data = &data; + + /* should check tuning error during every transfer */ + error = MMC_Transfer(card, &content, 1U); + if (kStatus_Success != error) + { + return error; + } + + /* When host's AUTO_COMMAND12 feature isn't enabled and PRE_DEFINED_COUNT command isn't enabled in multiple + blocks transmission, sends STOP_TRANSMISSION command. */ + if ((blockCount > 1U) && (!(data.enableAutoCommand12)) && (!card->enablePreDefinedBlockCount)) + { + if (kStatus_Success != MMC_StopTransmission(card)) + { + return kStatus_SDMMC_StopTransmissionFailed; + } + } + + return kStatus_Success; +} + +status_t MMC_CardInit(mmc_card_t *card) +{ + assert(card); + assert((card->hostVoltageWindowVCC != kMMC_VoltageWindowNone) && + (card->hostVoltageWindowVCC != kMMC_VoltageWindow120)); + + uint32_t opcode = 0U; + + if (!card->isHostReady) + { + return kStatus_SDMMC_HostNotReady; + } + /* set DATA bus width */ + SDMMCHOST_SET_CARD_BUS_WIDTH(card->host.base, kSDMMCHOST_DATABUSWIDTH1BIT); + /* Set clock to 400KHz. */ + card->busClock_Hz = SDMMCHOST_SET_CARD_CLOCK(card->host.base, card->host.sourceClock_Hz, SDMMC_CLOCK_400KHZ); + /* get host capability first */ + GET_SDMMCHOST_CAPABILITY(card->host.base, &(card->host.capability)); + + /* Send CMD0 to reset the bus */ + if (kStatus_Success != MMC_GoIdle(card)) + { + return kStatus_SDMMC_GoIdleFailed; + } + + /* Hand-shaking with card to validata the voltage range Host first sending its expected + information.*/ + if (kStatus_Success != MMC_SendOperationCondition(card, 0U)) + { + return kStatus_SDMMC_HandShakeOperationConditionFailed; + } + + /* switch the host voltage which the card can support */ + if (kStatus_Success != MMC_SwitchVoltage(card, &opcode)) + { + return kStatus_SDMMC_HandShakeOperationConditionFailed; + } + + /* Get host's access mode. */ + if (card->host.capability.maxBlockLength >= FSL_SDMMC_DEFAULT_BLOCK_SIZE) + { + opcode |= kMMC_AccessModeSector << MMC_OCR_ACCESS_MODE_SHIFT; + } + else + { + opcode |= kMMC_AccessModeByte << MMC_OCR_ACCESS_MODE_SHIFT; + } + + if (kStatus_Success != MMC_SendOperationCondition(card, opcode)) + { + return kStatus_SDMMC_HandShakeOperationConditionFailed; + } + + /* Get card CID */ + if (kStatus_Success != MMC_AllSendCid(card)) + { + return kStatus_SDMMC_AllSendCidFailed; + } + + /* Set the card relative address */ + if (kStatus_Success != MMC_SetRelativeAddress(card)) + { + return kStatus_SDMMC_SetRelativeAddressFailed; + } + + /* Get the CSD register content */ + if (kStatus_Success != MMC_SendCsd(card)) + { + return kStatus_SDMMC_SendCsdFailed; + } + + /* Set to maximum speed in normal mode. */ + MMC_SetMaxFrequency(card); + + /* Send CMD7 with the card's relative address to place the card in transfer state. Puts current selected card in + transfer state. */ + if (kStatus_Success != MMC_SelectCard(card, true)) + { + return kStatus_SDMMC_SelectCardFailed; + } + + /* Get Extended CSD register content. */ + if (kStatus_Success != MMC_SendExtendedCsd(card, NULL, 0U)) + { + return kStatus_SDMMC_SendExtendedCsdFailed; + } + + /* set block size */ + if (kStatus_Success != MMC_SetBlockSize(card, FSL_SDMMC_DEFAULT_BLOCK_SIZE)) + { + return kStatus_SDMMC_SetCardBlockSizeFailed; + } + + /* switch to host support speed mode, then switch MMC data bus width and select power class */ + if (kStatus_Success != MMC_SelectBusTiming(card)) + { + return kStatus_SDMMC_SwitchBusTimingFailed; + } + + /* switch power class */ + if (kStatus_Success != MMC_SetPowerClass(card)) + { + return kStatus_SDMMC_SetPowerClassFail; + } + + /* Set to max erase unit size */ + if (kStatus_Success != MMC_SetMaxEraseUnitSize(card)) + { + return kStatus_SDMMC_EnableHighCapacityEraseFailed; + } + + /* Set card default to access non-boot partition */ + card->currentPartition = kMMC_AccessPartitionUserAera; + + return kStatus_Success; +} + +void MMC_CardDeinit(mmc_card_t *card) +{ + assert(card); + + MMC_SelectCard(card, false); +} + +status_t MMC_HostInit(mmc_card_t *card) +{ + assert(card); + + if ((!card->isHostReady) && SDMMCHOST_Init(&(card->host), NULL) != kStatus_Success) + { + return kStatus_Fail; + } + + /* set the host status flag, after the card re-plug in, don't need init host again */ + card->isHostReady = true; + + return kStatus_Success; +} + +void MMC_HostDeinit(mmc_card_t *card) +{ + assert(card); + + SDMMCHOST_Deinit(&(card->host)); + /* should re-init host */ + card->isHostReady = false; +} + +void MMC_HostReset(SDMMCHOST_CONFIG *host) +{ + SDMMCHOST_Reset(host->base); +} + +void MMC_PowerOnCard(SDMMCHOST_TYPE *base, const sdmmchost_pwr_card_t *pwr) +{ + SDMMCHOST_PowerOnCard(base, pwr); +} + +void MMC_PowerOffCard(SDMMCHOST_TYPE *base, const sdmmchost_pwr_card_t *pwr) +{ + SDMMCHOST_PowerOffCard(base, pwr); +} + +status_t MMC_Init(mmc_card_t *card) +{ + assert(card); + + if (!card->isHostReady) + { + if (MMC_HostInit(card) != kStatus_Success) + { + return kStatus_SDMMC_HostNotReady; + } + } + else + { + /* reset the host */ + MMC_HostReset(&(card->host)); + } + + /*first power off card*/ + MMC_PowerOffCard(card->host.base, card->usrParam.pwr); + + /*power on card*/ + MMC_PowerOnCard(card->host.base, card->usrParam.pwr); + + return MMC_CardInit(card); +} + +void MMC_Deinit(mmc_card_t *card) +{ + assert(card); + + MMC_CardDeinit(card); + MMC_HostDeinit(card); +} + +bool MMC_CheckReadOnly(mmc_card_t *card) +{ + assert(card); + + return ((card->csd.flags & kMMC_CsdPermanentWriteProtectFlag) || + (card->csd.flags & kMMC_CsdTemporaryWriteProtectFlag)); +} + +status_t MMC_SelectPartition(mmc_card_t *card, mmc_access_partition_t partitionNumber) +{ + assert(card); + + uint8_t bootConfig; + mmc_extended_csd_config_t extendedCsdconfig; + + bootConfig = card->extendedCsd.partitionConfig; + bootConfig &= ~MMC_PARTITION_CONFIG_PARTITION_ACCESS_MASK; + bootConfig |= ((uint32_t)partitionNumber << MMC_PARTITION_CONFIG_PARTITION_ACCESS_SHIFT); + + extendedCsdconfig.accessMode = kMMC_ExtendedCsdAccessModeWriteBits; + extendedCsdconfig.ByteIndex = kMMC_ExtendedCsdIndexPartitionConfig; + extendedCsdconfig.ByteValue = bootConfig; + extendedCsdconfig.commandSet = kMMC_CommandSetStandard; + if (kStatus_Success != MMC_SetExtendedCsdConfig(card, &extendedCsdconfig)) + { + return kStatus_SDMMC_ConfigureExtendedCsdFailed; + } + + /* Save current configuration. */ + card->extendedCsd.partitionConfig = bootConfig; + card->currentPartition = partitionNumber; + + return kStatus_Success; +} + +status_t MMC_ReadBlocks(mmc_card_t *card, uint8_t *buffer, uint32_t startBlock, uint32_t blockCount) +{ + assert(card); + assert(buffer); + assert(blockCount); + + uint32_t blockCountOneTime; /* The block count can be erased in one time sending READ_BLOCKS command. */ + uint32_t blockDone; /* The blocks has been read. */ + uint32_t blockLeft; /* Left blocks to be read. */ + uint8_t *nextBuffer; + bool dataAddrAlign = true; + + blockLeft = blockCount; + blockDone = 0U; + if (kStatus_Success != MMC_CheckBlockRange(card, startBlock, blockCount)) + { + return kStatus_InvalidArgument; + } + + while (blockLeft) + { + nextBuffer = (buffer + blockDone * FSL_SDMMC_DEFAULT_BLOCK_SIZE); + if (!card->noInteralAlign && (!dataAddrAlign || (((uint32_t)nextBuffer) & (sizeof(uint32_t) - 1U)))) + { + blockLeft--; + blockCountOneTime = 1U; + memset(g_sdmmc, 0U, FSL_SDMMC_DEFAULT_BLOCK_SIZE); + dataAddrAlign = false; + } + else + { + if (blockLeft > card->host.capability.maxBlockCount) + { + blockLeft = (blockLeft - card->host.capability.maxBlockCount); + blockCountOneTime = card->host.capability.maxBlockCount; + } + else + { + blockCountOneTime = blockLeft; + blockLeft = 0U; + } + } + + if (kStatus_Success != MMC_Read(card, dataAddrAlign ? nextBuffer : (uint8_t *)g_sdmmc, (startBlock + blockDone), + FSL_SDMMC_DEFAULT_BLOCK_SIZE, blockCountOneTime)) + { + return kStatus_SDMMC_TransferFailed; + } + + blockDone += blockCountOneTime; + + if (!card->noInteralAlign && (!dataAddrAlign)) + { + memcpy(nextBuffer, (uint8_t *)&g_sdmmc, FSL_SDMMC_DEFAULT_BLOCK_SIZE); + } + } + + return kStatus_Success; +} + +status_t MMC_WriteBlocks(mmc_card_t *card, const uint8_t *buffer, uint32_t startBlock, uint32_t blockCount) +{ + assert(card); + assert(buffer); + assert(blockCount); + + uint32_t blockCountOneTime; + uint32_t blockLeft; + uint32_t blockDone; + const uint8_t *nextBuffer; + bool dataAddrAlign = true; + + blockLeft = blockCount; + blockDone = 0U; + + if (kStatus_Success != MMC_CheckBlockRange(card, startBlock, blockCount)) + { + return kStatus_InvalidArgument; + } + + while (blockLeft) + { + nextBuffer = (buffer + blockDone * FSL_SDMMC_DEFAULT_BLOCK_SIZE); + if (!card->noInteralAlign && (!dataAddrAlign || (((uint32_t)nextBuffer) & (sizeof(uint32_t) - 1U)))) + { + blockLeft--; + blockCountOneTime = 1U; + memcpy((uint8_t *)&g_sdmmc, nextBuffer, FSL_SDMMC_DEFAULT_BLOCK_SIZE); + dataAddrAlign = false; + } + else + { + if (blockLeft > card->host.capability.maxBlockCount) + { + blockLeft = (blockLeft - card->host.capability.maxBlockCount); + blockCountOneTime = card->host.capability.maxBlockCount; + } + else + { + blockCountOneTime = blockLeft; + blockLeft = 0U; + } + } + + if (kStatus_Success != MMC_Write(card, dataAddrAlign ? nextBuffer : (uint8_t *)g_sdmmc, + (startBlock + blockDone), FSL_SDMMC_DEFAULT_BLOCK_SIZE, blockCountOneTime)) + { + return kStatus_SDMMC_TransferFailed; + } + + blockDone += blockCountOneTime; + if (!card->noInteralAlign) + { + memset(g_sdmmc, 0U, FSL_SDMMC_DEFAULT_BLOCK_SIZE); + } + } + + return kStatus_Success; +} + +status_t MMC_EraseGroups(mmc_card_t *card, uint32_t startGroup, uint32_t endGroup) +{ + assert(card); + assert(card->host.transfer); + + uint32_t startGroupAddress; + uint32_t endGroupAddress; + SDMMCHOST_COMMAND command = {0}; + SDMMCHOST_TRANSFER content = {0}; + + if (kStatus_Success != MMC_CheckEraseGroupRange(card, startGroup, endGroup)) + { + return kStatus_InvalidArgument; + } + + /* Wait for the card's buffer to be not full to write to improve the write performance. */ + while ((GET_SDMMCHOST_STATUS(card->host.base) & CARD_DATA0_STATUS_MASK) != CARD_DATA0_NOT_BUSY) + { + } + + if (kStatus_Success != MMC_WaitWriteComplete(card)) + { + return kStatus_SDMMC_WaitWriteCompleteFailed; + } + + /* Calculate the start group address and end group address */ + startGroupAddress = startGroup; + endGroupAddress = endGroup; + if (card->flags & kMMC_SupportHighCapacityFlag) + { + /* The implementation of a higher than 2GB of density of memory will not be backwards compatible with the + lower densities.First of all the address argument for higher than 2GB of density of memory is changed to + be sector address (512B sectors) instead of byte address */ + startGroupAddress = (startGroupAddress * (card->eraseGroupBlocks)); + endGroupAddress = (endGroupAddress * (card->eraseGroupBlocks)); + } + else + { + /* The address unit is byte when card capacity is lower than 2GB */ + startGroupAddress = (startGroupAddress * (card->eraseGroupBlocks) * FSL_SDMMC_DEFAULT_BLOCK_SIZE); + endGroupAddress = (endGroupAddress * (card->eraseGroupBlocks) * FSL_SDMMC_DEFAULT_BLOCK_SIZE); + } + + /* Set the start erase group address */ + command.index = kMMC_EraseGroupStart; + command.argument = startGroupAddress; + command.responseType = kCARD_ResponseTypeR1; + command.responseErrorFlags = SDMMC_R1_ALL_ERROR_FLAG; + + content.command = &command; + content.data = NULL; + if (kStatus_Success != MMC_Transfer(card, &content, 0U)) + { + return kStatus_SDMMC_TransferFailed; + } + + /* Set the end erase group address */ + command.index = kMMC_EraseGroupEnd; + command.argument = endGroupAddress; + + content.command = &command; + content.data = NULL; + if (kStatus_Success != MMC_Transfer(card, &content, 0U)) + { + return kStatus_SDMMC_TransferFailed; + } + + /* Start the erase process */ + command.index = kSDMMC_Erase; + command.argument = 0U; + command.responseType = kCARD_ResponseTypeR1b; + command.responseErrorFlags = SDMMC_R1_ALL_ERROR_FLAG; + + content.command = &command; + content.data = NULL; + if (kStatus_Success != MMC_Transfer(card, &content, 0U)) + { + return kStatus_SDMMC_TransferFailed; + } + + return kStatus_Success; +} + +status_t MMC_SetBootConfigWP(mmc_card_t *card, uint8_t wp) +{ + assert(card); + + mmc_extended_csd_config_t extendedCsdconfig; + extendedCsdconfig.accessMode = kMMC_ExtendedCsdAccessModeWriteBits; + extendedCsdconfig.ByteIndex = kMMC_ExtendedCsdIndexBootConfigWP; + extendedCsdconfig.ByteValue = wp; + extendedCsdconfig.commandSet = kMMC_CommandSetStandard; + if (kStatus_Success != MMC_SetExtendedCsdConfig(card, &extendedCsdconfig)) + { + return kStatus_SDMMC_ConfigureExtendedCsdFailed; + } + + card->extendedCsd.bootConfigProtect = wp; + + return kStatus_Success; +} + +status_t MMC_SetBootPartitionWP(mmc_card_t *card, mmc_boot_partition_wp_t bootPartitionWP) +{ + assert(card); + + mmc_extended_csd_config_t extendedCsdconfig; + extendedCsdconfig.accessMode = kMMC_ExtendedCsdAccessModeWriteBits; + extendedCsdconfig.ByteIndex = kMMC_ExtendedCsdIndexBootPartitionWP; + extendedCsdconfig.ByteValue = bootPartitionWP; + extendedCsdconfig.commandSet = kMMC_CommandSetStandard; + if (kStatus_Success != MMC_SetExtendedCsdConfig(card, &extendedCsdconfig)) + { + return kStatus_SDMMC_ConfigureExtendedCsdFailed; + } + + card->extendedCsd.bootPartitionWP = bootPartitionWP; + + return kStatus_Success; +} + +status_t MMC_SetBootConfig(mmc_card_t *card, const mmc_boot_config_t *config) +{ + assert(card); + assert(config); + + uint8_t bootParameter; + uint8_t bootBusWidth = config->bootDataBusWidth; + mmc_extended_csd_config_t extendedCsdconfig; + + if (card->extendedCsd.extendecCsdVersion <= + kMMC_ExtendedCsdRevision13) /* V4.3 or above version card support boot mode */ + { + return kStatus_SDMMC_NotSupportYet; + } + + /* Set the BOOT_CONFIG field of Extended CSD */ + bootParameter = card->extendedCsd.partitionConfig; + bootParameter &= ~(MMC_PARTITION_CONFIG_BOOT_ACK_MASK | MMC_PARTITION_CONFIG_PARTITION_ENABLE_MASK); + bootParameter |= ((config->enableBootAck ? 1U : 0U) << MMC_PARTITION_CONFIG_BOOT_ACK_SHIFT); + bootParameter |= ((uint32_t)(config->bootPartition) << MMC_PARTITION_CONFIG_PARTITION_ENABLE_SHIFT); + + extendedCsdconfig.accessMode = kMMC_ExtendedCsdAccessModeWriteBits; + extendedCsdconfig.ByteIndex = kMMC_ExtendedCsdIndexPartitionConfig; + extendedCsdconfig.ByteValue = bootParameter; + extendedCsdconfig.commandSet = kMMC_CommandSetStandard; + if (kStatus_Success != MMC_SetExtendedCsdConfig(card, &extendedCsdconfig)) + { + return kStatus_SDMMC_ConfigureExtendedCsdFailed; + } + + card->extendedCsd.partitionConfig = bootParameter; + + /* data bus remapping */ + if (bootBusWidth == kMMC_DataBusWidth1bit) + { + bootBusWidth = 0U; + } + else if ((bootBusWidth == kMMC_DataBusWidth4bit) || (bootBusWidth == kMMC_DataBusWidth4bitDDR)) + { + bootBusWidth = 1U; + } + else + { + bootBusWidth = 2U; + } + + /*Set BOOT_BUS_CONDITIONS in Extended CSD */ + bootParameter = card->extendedCsd.bootDataBusConditions; + bootParameter &= ~(MMC_BOOT_BUS_CONDITION_RESET_BUS_CONDITION_MASK | MMC_BOOT_BUS_CONDITION_BUS_WIDTH_MASK | + MMC_BOOT_BUS_CONDITION_BOOT_MODE_MASK); + bootParameter |= + ((config->retainBootbusCondition ? true : false) << MMC_BOOT_BUS_CONDITION_RESET_BUS_CONDITION_SHIFT); + bootParameter |= bootBusWidth << MMC_BOOT_BUS_CONDITION_BUS_WIDTH_SHIFT; + bootParameter |= (uint32_t)(config->bootTimingMode); + + extendedCsdconfig.accessMode = kMMC_ExtendedCsdAccessModeWriteBits; + extendedCsdconfig.ByteIndex = kMMC_ExtendedCsdIndexBootBusConditions; + extendedCsdconfig.ByteValue = bootParameter; + if (kStatus_Success != MMC_SetExtendedCsdConfig(card, &extendedCsdconfig)) + { + return kStatus_SDMMC_ConfigureBootFailed; + } + + card->extendedCsd.bootDataBusConditions = bootParameter; + /* check and configure the boot config write protect */ + bootParameter = config->pwrBootConfigProtection | ((uint8_t)(config->premBootConfigProtection) << 4U); + if (bootParameter != (card->extendedCsd.bootConfigProtect)) + { + if (kStatus_Success != MMC_SetBootConfigWP(card, bootParameter)) + { + return kStatus_SDMMC_ConfigureBootFailed; + } + } + /* check and configure the boot partition write protect */ + if (card->extendedCsd.bootPartitionWP != (uint8_t)(config->bootPartitionWP)) + { + if (kStatus_Success != MMC_SetBootPartitionWP(card, config->bootPartitionWP)) + { + return kStatus_SDMMC_ConfigureBootFailed; + } + } + + return kStatus_Success; +} + +status_t MMC_StartBoot(mmc_card_t *card, + const mmc_boot_config_t *mmcConfig, + uint8_t *buffer, + SDMMCHOST_BOOT_CONFIG *hostConfig) +{ + assert(card); + assert(mmcConfig); + assert(buffer); + + SDMMCHOST_COMMAND command = {0}; + SDMMCHOST_TRANSFER content = {0}; + SDMMCHOST_DATA data = {0}; + uint32_t tempClock = 0U; + + if (!card->isHostReady) + { + return kStatus_Fail; + } + + /* send card active */ + SDMMCHOST_SEND_CARD_ACTIVE(card->host.base, 100U); + /* config the host */ + SDMMCHOST_SETMMCBOOTCONFIG(card->host.base, hostConfig); + /* enable MMC boot */ + SDMMCHOST_ENABLE_MMC_BOOT(card->host.base, true); + + if (mmcConfig->bootTimingMode == kMMC_BootModeSDRWithDefaultTiming) + { + /* Set clock to 400KHz. */ + tempClock = SDMMC_CLOCK_400KHZ; + } + else + { + /* Set clock to 52MHZ. */ + tempClock = MMC_CLOCK_52MHZ; + } + SDMMCHOST_SET_CARD_CLOCK(card->host.base, card->host.sourceClock_Hz, tempClock); + + if (mmcConfig->bootTimingMode == kMMC_BootModeDDRTiming) + { + /* enable DDR mode */ + SDMMCHOST_ENABLE_DDR_MODE(card->host.base, true, 0U); + } + + /* data bus remapping */ + if (mmcConfig->bootDataBusWidth == kMMC_DataBusWidth1bit) + { + SDMMCHOST_SET_CARD_BUS_WIDTH(card->host.base, kSDMMCHOST_DATABUSWIDTH1BIT); + } + else if ((mmcConfig->bootDataBusWidth == kMMC_DataBusWidth4bit) || + (mmcConfig->bootDataBusWidth == kMMC_DataBusWidth4bitDDR)) + { + SDMMCHOST_SET_CARD_BUS_WIDTH(card->host.base, kSDMMCHOST_DATABUSWIDTH4BIT); + } + else + { + SDMMCHOST_SET_CARD_BUS_WIDTH(card->host.base, kSDMMCHOST_DATABUSWIDTH8BIT); + } + + if (kMMC_BootModeAlternative == (uint32_t)SDMMCHOST_GET_HOST_CONFIG_BOOT_MODE(hostConfig)) + { + /* alternative boot mode */ + command.argument = 0xFFFFFFFA; + } + + command.index = kSDMMC_GoIdleState; + + data.blockSize = SDMMCHOST_GET_HOST_CONFIG_BLOCK_SIZE(hostConfig); + data.blockCount = SDMMCHOST_GET_HOST_CONFIG_BLOCK_COUNT(hostConfig); + data.rxData = (uint32_t *)buffer; + SDMMCHOST_ENABLE_BOOT_FLAG(data); + + content.data = &data; + content.command = &command; + + /* should check tuning error during every transfer*/ + if (kStatus_Success != MMC_Transfer(card, &content, 1U)) + { + return kStatus_SDMMC_TransferFailed; + } + + return kStatus_Success; +} + +status_t MMC_ReadBootData(mmc_card_t *card, uint8_t *buffer, SDMMCHOST_BOOT_CONFIG *hostConfig) +{ + assert(card); + assert(buffer); + + SDMMCHOST_COMMAND command = {0}; + SDMMCHOST_TRANSFER content = {0}; + SDMMCHOST_DATA data = {0}; + + /* enable MMC boot */ + SDMMCHOST_ENABLE_MMC_BOOT(card->host.base, true); + /* config the host */ + SDMMCHOST_SETMMCBOOTCONFIG(card->host.base, hostConfig); + data.blockSize = SDMMCHOST_GET_HOST_CONFIG_BLOCK_SIZE(hostConfig); + data.blockCount = SDMMCHOST_GET_HOST_CONFIG_BLOCK_COUNT(hostConfig); + data.rxData = (uint32_t *)buffer; + SDMMCHOST_ENABLE_BOOT_CONTINOUS_FLAG(data); + /* no command should be send out */ + SDMMCHOST_EMPTY_CMD_FLAG(command); + + content.data = &data; + content.command = &command; + + /* should check tuning error during every transfer*/ + if (kStatus_Success != MMC_Transfer(card, &content, 1U)) + { + return kStatus_SDMMC_TransferFailed; + } + + return kStatus_Success; +} + +status_t MMC_StopBoot(mmc_card_t *card, uint32_t bootMode) +{ + assert(card); + /* Disable boot mode */ + if (kMMC_BootModeAlternative == bootMode) + { + /* Send CMD0 to reset the bus */ + if (kStatus_Success != MMC_GoIdle(card)) + { + return kStatus_SDMMC_GoIdleFailed; + } + } + /* disable MMC boot */ + SDMMCHOST_ENABLE_MMC_BOOT(card->host.base, false); + + return kStatus_Success; +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/src/fsl_sd.c b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/src/fsl_sd.c new file mode 100644 index 000000000..6e3599d32 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/src/fsl_sd.c @@ -0,0 +1,1982 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include "fsl_sd.h" + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Wait write process complete. + * + * @param card Card descriptor. + * @retval kStatus_Timeout Send command timeout. + * @retval kStatus_Success Operate successfully. + */ +static status_t SD_WaitWriteComplete(sd_card_t *card); + +/*! + * @brief send write success blocks. + * + * @param card Card descriptor. + * @param blocks blocks number wirte successed + * @retval kStatus_SDMMC_TransferFailed Send command failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t SD_SendWriteSuccessBlocks(sd_card_t *card, uint32_t *blocks); + +/*! + * @brief Send SEND_APPLICATION_COMMAND command. + * + * @param card Card descriptor. + * @param relativeaddress + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_SDMMC_CardNotSupport Card doesn't support. + * @retval kStatus_Success Operate successfully. + */ +static status_t inline SD_SendApplicationCmd(sd_card_t *card, uint32_t relativeAddress); + +/*! + * @brief Send GO_IDLE command to set the card to be idle state. + * + * @param card Card descriptor. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t inline SD_GoIdle(sd_card_t *card); + +/*! + * @brief Send STOP_TRANSMISSION command after multiple blocks read/write. + * + * @param card Card descriptor. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t SD_StopTransmission(sd_card_t *card); + +/*! + * @brief Send SET_BLOCK_SIZE command. + * + * @param card Card descriptor. + * @param blockSize Block size. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t inline SD_SetBlockSize(sd_card_t *card, uint32_t blockSize); + +/*! + * @brief Send GET_RCA command to get card relative address. + * + * @param card Card descriptor. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t SD_SendRca(sd_card_t *card); + +/*! + * @brief Send SWITCH_FUNCTION command to switch the card function group. + * + * @param card Card descriptor. + * @param mode 0 to check function group. 1 to switch function group + * @param group Function group + * @param number Function number in the function group. + * @param status Switch function status. + * @retval kStatus_SDMMC_SetCardBlockSizeFailed Set card block size failed. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t SD_SwitchFunction(sd_card_t *card, uint32_t mode, uint32_t group, uint32_t number, uint32_t *status); + +/*! + * @brief Decode raw SCR register content in the data blocks. + * + * @param card Card descriptor. + * @param rawScr Raw SCR register content. + */ +static void SD_DecodeScr(sd_card_t *card, uint32_t *rawScr); + +/*! + * @brief Send GET_SCR command. + * + * @param card Card descriptor. + * @retval kStatus_SDMMC_SendApplicationCommandFailed Send application command failed. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_SDMMC_NotSupportYet Not support yet. + * @retval kStatus_Success Operate successfully. + */ +static status_t SD_SendScr(sd_card_t *card); + +/*! + * @brief Switch the card to be high speed mode. + * + * @param card Card descriptor. + * @param group Group number. + * @param functio Function number. + * @retval kStatus_SDMMC_CardNotSupport Card not support. + * @retval kStatus_SDMMC_SwitchFailed Switch failed. + * @retval kStatus_SDMMC_NotSupportYet Not support yet. + * @retval kStatus_Fail Switch failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t SD_SelectFunction(sd_card_t *card, uint32_t group, uint32_t function); + +/*! + * @brief Send SET_DATA_WIDTH command to set SD bus width. + * + * @param card Card descriptor. + * @param width Data bus width. + * @retval kStatus_SDMMC_SendApplicationCommandFailed Send application command failed. + * @retval kStatus_InvalidArgument Invalid argument. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t SD_SetDataBusWidth(sd_card_t *card, sd_data_bus_width_t width); + +/*! + * @brief Decode raw CSD register content in the data blocks. + * + * @param card Card descriptor. + * @param rawCsd Raw CSD register content. + */ +static void SD_DecodeCsd(sd_card_t *card, uint32_t *rawCsd); + +/*! + * @brief Send SEND_CSD command to get CSD register content from Card. + * + * @param card Card descriptor. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t SD_SendCsd(sd_card_t *card); + +/*! + * @brief Decode raw CID register content in the data blocks. + * + * @param rawCid raw CID register content. + * @param card Card descriptor. + */ +static void SD_DecodeCid(sd_card_t *card, uint32_t *rawCid); + +/*! + * @brief Send GET_CID command to get CID from card. + * + * @param card Card descriptor. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t SD_AllSendCid(sd_card_t *card); + +/*! + * @brief Send SEND_OPERATION_CONDITION command. + * + * This function sends host capacity support information and asks the accessed card to send its operating condition + * register content. + * + * @param card Card descriptor. + * @param argument The argument of the send operation condition ncomamnd. + * @retval kStatus_SDMMC_SendApplicationCommandFailed Send application command failed. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_Timeout Timeout. + * @retval kStatus_Success Operate successfully. + */ +static status_t SD_ApplicationSendOperationCondition(sd_card_t *card, uint32_t argument); + +/*! + * @brief Send GET_INTERFACE_CONDITION command to get card interface condition. + * + * This function checks card interface condition, which includes host supply voltage information and asks the card + * whether card supports the specified host voltage. + * + * @param card Card descriptor. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_SDMMC_CardNotSupport Card doesn't support. + * @retval kStatus_Success Operate successfully. + */ +static status_t SD_SendInterfaceCondition(sd_card_t *card); + +/*! + * @brief Send switch voltage command + * switch card voltage to 1.8v + * + * @param card Card descriptor. + */ +static status_t SD_SwitchVoltage(sd_card_t *card); + +/*! + * @brief select bus timing + * select card timing + * @param card Card descriptor. + */ +static status_t SD_SelectBusTiming(sd_card_t *card); + +/*! + * @brief Decode sd 512 bit status + * @param card Card descriptor. + * @param 512 bits satus raw data. + */ +static void SD_DecodeStatus(sd_card_t *card, uint32_t *src); + +/*! + * @brief Read data from specific SD card. + * + * @param card Card descriptor. + * @param buffer Buffer to save data blocks read. + * @param startBlock Card start block number to be read. + * @param blockSize Block size. + * @param blockCount Block count. + * @retval kStatus_SDMMC_CardNotSupport Card doesn't support. + * @retval kStatus_SDMMC_WaitWriteCompleteFailed Wait write complete failed. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_SDMMC_StopTransmissionFailed Stop transmission failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t SD_Read(sd_card_t *card, uint8_t *buffer, uint32_t startBlock, uint32_t blockSize, uint32_t blockCount); + +/*! + * @brief Write data to specific card + * + * @param card Card descriptor. + * @param buffer Buffer to be sent. + * @param startBlock Card start block number to be written. + * @param blockSize Block size. + * @param blockCount Block count. + * @param blockWritten successfully write blocks + * @retval kStatus_SDMMC_CardNotSupport Card doesn't support. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_SDMMC_StopTransmissionFailed Stop transmission failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t SD_Write(sd_card_t *card, + const uint8_t *buffer, + uint32_t startBlock, + uint32_t blockSize, + uint32_t blockCount, + uint32_t *blockWritten); + +/*! + * @brief Erase data for the given block range. + * + * @param card Card descriptor. + * @param startBlock Card start block number to be erased. + * @param blockCount The block count to be erased. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t SD_Erase(sd_card_t *card, uint32_t startBlock, uint32_t blockCount); + +/*! + * @brief card transfer function. + * + * @param card Card descriptor. + * @param content Transfer content. + * @param retry Retry times + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_Success Operate successfully. + * @retval kStatus_SDMMC_TuningFail tuning fail + */ +static status_t SD_Transfer(sd_card_t *card, SDMMCHOST_TRANSFER *content, uint32_t retry); + +/*! + * @brief card execute tuning function. + * + * @param card Card descriptor. + * @retval kStatus_Success Operate successfully. + * @retval kStatus_SDMMC_TuningFail tuning fail. + * @retval kStatus_SDMMC_TransferFailed transfer fail + */ +static status_t inline SD_ExecuteTuning(sd_card_t *card); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* g_sdmmc statement */ +extern uint32_t g_sdmmc[SDK_SIZEALIGN(SDMMC_GLOBAL_BUFFER_SIZE, SDMMC_DATA_BUFFER_ALIGN_CACHE)]; +static uint32_t s_sdAuSizeMap[] = {0, + 16 * 1024, + 32 * 1024, + 64 * 1024, + 128 * 1024, + 256 * 1024, + 512 * 1024, + 1024 * 1024, + 2 * 1024 * 1024, + 4 * 1024 * 1024, + 8 * 1024 * 1024, + 12 * 1024 * 1024, + 16 * 1024 * 1024, + 24 * 1024 * 1024, + 32 * 1024 * 1024, + 64 * 1024 * 1024}; +/******************************************************************************* + * Code + ******************************************************************************/ +static status_t inline SD_SendApplicationCmd(sd_card_t *card, uint32_t relativeAddress) +{ + assert(card); + + return SDMMC_SendApplicationCommand(card->host.base, card->host.transfer, relativeAddress); +} + +static status_t inline SD_GoIdle(sd_card_t *card) +{ + assert(card); + + return SDMMC_GoIdle(card->host.base, card->host.transfer); +} + +static status_t inline SD_SetBlockSize(sd_card_t *card, uint32_t blockSize) +{ + assert(card); + + return SDMMC_SetBlockSize(card->host.base, card->host.transfer, blockSize); +} + +static status_t inline SD_ExecuteTuning(sd_card_t *card) +{ + assert(card); + + return SDMMC_ExecuteTuning(card->host.base, card->host.transfer, kSD_SendTuningBlock, 64U); +} + +static status_t SD_SwitchVoltage(sd_card_t *card) +{ + assert(card); + + if ((card->usrParam.cardVoltage != NULL) && (card->usrParam.cardVoltage->cardSignalLine1V8 != NULL)) + { + return SDMMC_SwitchToVoltage(card->host.base, card->host.transfer, + card->usrParam.cardVoltage->cardSignalLine1V8); + } + + return SDMMC_SwitchToVoltage(card->host.base, card->host.transfer, NULL); +} + +static status_t SD_StopTransmission(sd_card_t *card) +{ + assert(card); + + SDMMCHOST_TRANSFER content = {0}; + SDMMCHOST_COMMAND command = {0}; + status_t error = kStatus_Success; + + command.index = kSDMMC_StopTransmission; + command.argument = 0U; + command.type = kCARD_CommandTypeAbort; + command.responseType = kCARD_ResponseTypeR1b; + command.responseErrorFlags = SDMMC_R1_ALL_ERROR_FLAG; + + content.command = &command; + content.data = 0U; + error = card->host.transfer(card->host.base, &content); + if (kStatus_Success != error) + { + SDMMC_LOG("\r\nError: send CMD12 failed with host error %d, reponse %x\r\n", error, command.response[0U]); + return kStatus_SDMMC_TransferFailed; + } + + return kStatus_Success; +} + +static status_t SD_Transfer(sd_card_t *card, SDMMCHOST_TRANSFER *content, uint32_t retry) +{ + assert(card->host.transfer); + assert(content); + status_t error; + + do + { + error = card->host.transfer(card->host.base, content); +#if SDMMC_ENABLE_SOFTWARE_TUNING + if (((error == SDMMCHOST_RETUNING_REQUEST) || (error == SDMMCHOST_TUNING_ERROR)) && + (card->currentTiming == kSD_TimingSDR104Mode)) + { + /* tuning error need reset tuning circuit */ + if (error == SDMMCHOST_TUNING_ERROR) + { + SDMMCHOST_RESET_TUNING(card->host.base, 100U); + } + + /* execute re-tuning */ + if (SD_ExecuteTuning(card) != kStatus_Success) + { + error = kStatus_SDMMC_TuningFail; + break; + } + else + { + continue; + } + } + else +#endif + if (error != kStatus_Success) + { + /* if transfer data failed, send cmd12 to abort current transfer */ + if (content->data) + { + SD_StopTransmission(card); + } + } + + if (retry != 0U) + { + retry--; + } + else + { + break; + } + + } while (error != kStatus_Success); + + return error; +} + +static status_t SD_WaitWriteComplete(sd_card_t *card) +{ + assert(card); + + SDMMCHOST_TRANSFER content = {0}; + SDMMCHOST_COMMAND command = {0}; + status_t error = kStatus_Success; + + command.index = kSDMMC_SendStatus; + command.argument = card->relativeAddress << 16U; + command.responseType = kCARD_ResponseTypeR1; + + do + { + content.command = &command; + content.data = 0U; + error = SD_Transfer(card, &content, 2U); + if (kStatus_Success != error) + { + SDMMC_LOG("\r\nError: send CMD13 failed with host error %d, response %x", error, command.response[0U]); + break; + } + + if ((command.response[0U] & SDMMC_MASK(kSDMMC_R1ReadyForDataFlag)) && + (SDMMC_R1_CURRENT_STATE(command.response[0U]) != kSDMMC_R1StateProgram)) + { + break; + } + } while (true); + + return error; +} + +static status_t SD_SendWriteSuccessBlocks(sd_card_t *card, uint32_t *blocks) +{ + assert(card); + + SDMMCHOST_TRANSFER content = {0}; + SDMMCHOST_COMMAND command = {0}; + SDMMCHOST_DATA data = {0}; + status_t error = kStatus_Success; + + memset(g_sdmmc, 0U, sizeof(g_sdmmc)); + + /* Wait for the card write process complete because of that card read process and write process use one buffer. */ + if (kStatus_Success != SD_WaitWriteComplete(card)) + { + return kStatus_SDMMC_WaitWriteCompleteFailed; + } + + if (kStatus_Success != SD_SendApplicationCmd(card, card->relativeAddress)) + { + return kStatus_SDMMC_SendApplicationCommandFailed; + } + + command.index = kSD_ApplicationSendNumberWriteBlocks; + command.responseType = kCARD_ResponseTypeR1; + + data.blockSize = 4U; + data.blockCount = 1U; + data.rxData = &g_sdmmc[0]; + + content.command = &command; + content.data = &data; + error = card->host.transfer(card->host.base, &content); + if ((kStatus_Success != error) || ((command.response[0U]) & SDMMC_R1_ALL_ERROR_FLAG)) + { + SDMMC_LOG("\r\nError: send ACMD13 failed with host error %d, response %x", error, command.response[0U]); + } + else + { + *blocks = SWAP_WORD_BYTE_SEQUENCE(g_sdmmc[0]); + } + + return error; +} + +static status_t SD_SendRca(sd_card_t *card) +{ + assert(card); + + SDMMCHOST_TRANSFER content = {0}; + SDMMCHOST_COMMAND command = {0}; + status_t error = kStatus_Success; + + command.index = kSD_SendRelativeAddress; + command.argument = 0U; + command.responseType = kCARD_ResponseTypeR6; + + content.command = &command; + content.data = NULL; + + error = card->host.transfer(card->host.base, &content); + if (kStatus_Success == error) + { + card->relativeAddress = (command.response[0U] >> 16U); + } + else + { + SDMMC_LOG("\r\nError: send CMD3 failed with host error %d, response %x", error, command.response[0U]); + } + + return error; +} + +static status_t SD_SwitchFunction(sd_card_t *card, uint32_t mode, uint32_t group, uint32_t number, uint32_t *status) +{ + assert(card); + assert(status); + + SDMMCHOST_TRANSFER content = {0}; + SDMMCHOST_COMMAND command = {0}; + SDMMCHOST_DATA data = {0}; + status_t error = kStatus_Success; + + command.index = kSD_Switch; + command.argument = (mode << 31U | 0x00FFFFFFU); + command.argument &= ~((uint32_t)(0xFU) << (group * 4U)); + command.argument |= (number << (group * 4U)); + command.responseType = kCARD_ResponseTypeR1; + + data.blockSize = 64U; + data.blockCount = 1U; + data.rxData = status; + + content.command = &command; + content.data = &data; + error = card->host.transfer(card->host.base, &content); + if ((kStatus_Success != error) || ((command.response[0U]) & SDMMC_R1_ALL_ERROR_FLAG)) + { + SDMMC_LOG("\r\n\r\nError: send CMD6 failed with host error %d, response %x", error, command.response[0U]); + } + + return error; +} + +static void SD_DecodeScr(sd_card_t *card, uint32_t *rawScr) +{ + assert(card); + assert(rawScr); + + sd_scr_t *scr; + + scr = &(card->scr); + scr->scrStructure = (uint8_t)((rawScr[0U] & 0xF0000000U) >> 28U); + scr->sdSpecification = (uint8_t)((rawScr[0U] & 0xF000000U) >> 24U); + if ((uint8_t)((rawScr[0U] & 0x800000U) >> 23U)) + { + scr->flags |= kSD_ScrDataStatusAfterErase; + } + scr->sdSecurity = (uint8_t)((rawScr[0U] & 0x700000U) >> 20U); + scr->sdBusWidths = (uint8_t)((rawScr[0U] & 0xF0000U) >> 16U); + if ((uint8_t)((rawScr[0U] & 0x8000U) >> 15U)) + { + scr->flags |= kSD_ScrSdSpecification3; + } + scr->extendedSecurity = (uint8_t)((rawScr[0U] & 0x7800U) >> 10U); + scr->commandSupport = (uint8_t)(rawScr[0U] & 0x3U); + scr->reservedForManufacturer = rawScr[1U]; + /* Get specification version. */ + switch (scr->sdSpecification) + { + case 0U: + card->version = kSD_SpecificationVersion1_0; + break; + case 1U: + card->version = kSD_SpecificationVersion1_1; + break; + case 2U: + card->version = kSD_SpecificationVersion2_0; + if (card->scr.flags & kSD_ScrSdSpecification3) + { + card->version = kSD_SpecificationVersion3_0; + } + break; + default: + break; + } + if (card->scr.sdBusWidths & 0x4U) + { + card->flags |= kSD_Support4BitWidthFlag; + } + /* speed class control cmd */ + if (card->scr.commandSupport & 0x01U) + { + card->flags |= kSD_SupportSpeedClassControlCmd; + } + /* set block count cmd */ + if (card->scr.commandSupport & 0x02U) + { + card->flags |= kSD_SupportSetBlockCountCmd; + } +} + +static status_t SD_SendScr(sd_card_t *card) +{ + assert(card); + + SDMMCHOST_TRANSFER content = {0}; + SDMMCHOST_COMMAND command = {0}; + SDMMCHOST_DATA data = {0}; + uint32_t *rawScr = g_sdmmc; + status_t error = kStatus_Success; + + /* memset the global buffer */ + memset(g_sdmmc, 0U, sizeof(g_sdmmc)); + + if (kStatus_Success != SD_SendApplicationCmd(card, card->relativeAddress)) + { + return kStatus_SDMMC_SendApplicationCommandFailed; + } + + command.index = kSD_ApplicationSendScr; + command.responseType = kCARD_ResponseTypeR1; + command.argument = 0U; + + data.blockSize = 8U; + data.blockCount = 1U; + data.rxData = rawScr; + + content.data = &data; + content.command = &command; + error = card->host.transfer(card->host.base, &content); + if ((kStatus_Success != error) || ((command.response[0U]) & SDMMC_R1_ALL_ERROR_FLAG)) + { + SDMMC_LOG("\r\nError: send ACMD51 failed with host error %d, response %x", error, command.response[0U]); + } + else + { + /* SCR register data byte sequence from card is big endian(MSB first). */ + switch (card->host.config.endianMode) + { + case kSDMMCHOST_EndianModeLittle: + /* In little endian mode, SD bus byte transferred first is the byte stored in lowest byte position in a + word which will cause 4 byte's sequence in a word is not consistent with their original sequence from + card. So the sequence of 4 bytes received in a word should be converted. */ + rawScr[0U] = SWAP_WORD_BYTE_SEQUENCE(rawScr[0U]); + rawScr[1U] = SWAP_WORD_BYTE_SEQUENCE(rawScr[1U]); + break; + case kSDMMCHOST_EndianModeBig: + break; /* Doesn't need to switch byte sequence when decodes bytes as big endian sequence. */ + case kSDMMCHOST_EndianModeHalfWordBig: + rawScr[0U] = SWAP_HALF_WROD_BYTE_SEQUENCE(rawScr[0U]); + rawScr[1U] = SWAP_HALF_WROD_BYTE_SEQUENCE(rawScr[1U]); + break; + default: + return kStatus_SDMMC_NotSupportYet; + } + memcpy(card->rawScr, rawScr, sizeof(card->rawScr)); + /* decode scr */ + SD_DecodeScr(card, rawScr); + } + + return error; +} + +static status_t SD_SelectFunction(sd_card_t *card, uint32_t group, uint32_t function) +{ + assert(card); + + uint32_t *functionStatus = g_sdmmc; + uint16_t functionGroupInfo[6U] = {0}; + uint32_t currentFunctionStatus = 0U; + + /* memset the global buffer */ + memset(g_sdmmc, 0, sizeof(g_sdmmc)); + + /* check if card support CMD6 */ + if ((card->version <= kSD_SpecificationVersion1_0) || (!(card->csd.cardCommandClass & kSDMMC_CommandClassSwitch))) + { + SDMMC_LOG("\r\nError: current card not support CMD6"); + return kStatus_SDMMC_NotSupportYet; + } + + /* Check if card support high speed mode. */ + if (kStatus_Success != SD_SwitchFunction(card, kSD_SwitchCheck, group, function, functionStatus)) + { + return kStatus_SDMMC_TransferFailed; + } + + /* Switch function status byte sequence from card is big endian(MSB first). */ + switch (card->host.config.endianMode) + { + case kSDMMCHOST_EndianModeLittle: + /* In little endian mode, SD bus byte transferred first is the byte stored in lowest byte position in + a word which will cause 4 byte's sequence in a word is not consistent with their original sequence from + card. So the sequence of 4 bytes received in a word should be converted. */ + functionStatus[0U] = SWAP_WORD_BYTE_SEQUENCE(functionStatus[0U]); + functionStatus[1U] = SWAP_WORD_BYTE_SEQUENCE(functionStatus[1U]); + functionStatus[2U] = SWAP_WORD_BYTE_SEQUENCE(functionStatus[2U]); + functionStatus[3U] = SWAP_WORD_BYTE_SEQUENCE(functionStatus[3U]); + functionStatus[4U] = SWAP_WORD_BYTE_SEQUENCE(functionStatus[4U]); + break; + case kSDMMCHOST_EndianModeBig: + break; /* Doesn't need to switch byte sequence when decodes bytes as big endian sequence. */ + case kSDMMCHOST_EndianModeHalfWordBig: + functionStatus[0U] = SWAP_HALF_WROD_BYTE_SEQUENCE(functionStatus[0U]); + functionStatus[1U] = SWAP_HALF_WROD_BYTE_SEQUENCE(functionStatus[1U]); + functionStatus[2U] = SWAP_HALF_WROD_BYTE_SEQUENCE(functionStatus[2U]); + functionStatus[3U] = SWAP_HALF_WROD_BYTE_SEQUENCE(functionStatus[3U]); + functionStatus[4U] = SWAP_HALF_WROD_BYTE_SEQUENCE(functionStatus[4U]); + break; + default: + return kStatus_SDMMC_NotSupportYet; + } + /* -functionStatus[0U]---bit511~bit480; + -functionStatus[1U]---bit479~bit448; + -functionStatus[2U]---bit447~bit416; + -functionStatus[3U]---bit415~bit384; + -functionStatus[4U]---bit383~bit352; + According to the "switch function status[bits 511~0]" return by switch command in mode "check function": + -Check if function 1(high speed) in function group 1 is supported by checking if bit 401 is set; + -check if function 1 is ready and can be switched by checking if bits 379~376 equal value 1; + */ + functionGroupInfo[5U] = (uint16_t)functionStatus[0U]; + functionGroupInfo[4U] = (uint16_t)(functionStatus[1U] >> 16U); + functionGroupInfo[3U] = (uint16_t)(functionStatus[1U]); + functionGroupInfo[2U] = (uint16_t)(functionStatus[2U] >> 16U); + functionGroupInfo[1U] = (uint16_t)(functionStatus[2U]); + functionGroupInfo[0U] = (uint16_t)(functionStatus[3U] >> 16U); + currentFunctionStatus = ((functionStatus[3U] & 0xFFU) << 8U) | (functionStatus[4U] >> 24U); + + /* check if function is support */ + if (((functionGroupInfo[group] & (1 << function)) == 0U) || + ((currentFunctionStatus >> (group * 4U)) & 0xFU) != function) + { + SDMMC_LOG("\r\nError: current card not support function %d", function); + return kStatus_SDMMC_NotSupportYet; + } + + /* Switch to high speed mode. */ + if (kStatus_Success != SD_SwitchFunction(card, kSD_SwitchSet, group, function, functionStatus)) + { + return kStatus_SDMMC_TransferFailed; + } + + /* Switch function status byte sequence from card is big endian(MSB first). */ + switch (card->host.config.endianMode) + { + case kSDMMCHOST_EndianModeLittle: + /* In little endian mode is little endian, SD bus byte transferred first is the byte stored in lowest byte + position in a word which will cause 4 byte's sequence in a word is not consistent with their original + sequence from card. So the sequence of 4 bytes received in a word should be converted. */ + functionStatus[3U] = SWAP_WORD_BYTE_SEQUENCE(functionStatus[3U]); + functionStatus[4U] = SWAP_WORD_BYTE_SEQUENCE(functionStatus[4U]); + break; + case kSDMMCHOST_EndianModeBig: + break; /* Doesn't need to switch byte sequence when decodes bytes as big endian sequence. */ + case kSDMMCHOST_EndianModeHalfWordBig: + functionStatus[3U] = SWAP_HALF_WROD_BYTE_SEQUENCE(functionStatus[3U]); + functionStatus[4U] = SWAP_HALF_WROD_BYTE_SEQUENCE(functionStatus[4U]); + break; + default: + return kStatus_SDMMC_NotSupportYet; + } + /* According to the "switch function status[bits 511~0]" return by switch command in mode "set function": + -check if group 1 is successfully changed to function 1 by checking if bits 379~376 equal value 1; + */ + currentFunctionStatus = ((functionStatus[3U] & 0xFFU) << 8U) | (functionStatus[4U] >> 24U); + + if (((currentFunctionStatus >> (group * 4U)) & 0xFU) != function) + { + SDMMC_LOG("\r\nError: switch to function %d failed", function); + return kStatus_SDMMC_SwitchFailed; + } + + return kStatus_Success; +} + +static status_t SD_SetDataBusWidth(sd_card_t *card, sd_data_bus_width_t width) +{ + assert(card); + + SDMMCHOST_TRANSFER content = {0}; + SDMMCHOST_COMMAND command = {0}; + status_t error = kStatus_Success; + + if (kStatus_Success != SD_SendApplicationCmd(card, card->relativeAddress)) + { + return kStatus_SDMMC_SendApplicationCommandFailed; + } + + command.index = kSD_ApplicationSetBusWdith; + command.responseType = kCARD_ResponseTypeR1; + switch (width) + { + case kSD_DataBusWidth1Bit: + command.argument = 0U; + break; + case kSD_DataBusWidth4Bit: + command.argument = 2U; + break; + default: + return kStatus_InvalidArgument; + } + + content.command = &command; + content.data = NULL; + error = card->host.transfer(card->host.base, &content); + if ((kStatus_Success != error) || ((command.response[0U]) & SDMMC_R1_ALL_ERROR_FLAG)) + { + SDMMC_LOG("\r\nError: send ACMD6 failed with host error %d, response %x", error, command.response[0U]); + } + + return error; +} + +static void SD_DecodeCsd(sd_card_t *card, uint32_t *rawCsd) +{ + assert(card); + assert(rawCsd); + + sd_csd_t *csd; + + csd = &(card->csd); + csd->csdStructure = (uint8_t)((rawCsd[3U] & 0xC0000000U) >> 30U); + csd->dataReadAccessTime1 = (uint8_t)((rawCsd[3U] & 0xFF0000U) >> 16U); + csd->dataReadAccessTime2 = (uint8_t)((rawCsd[3U] & 0xFF00U) >> 8U); + csd->transferSpeed = (uint8_t)(rawCsd[3U] & 0xFFU); + csd->cardCommandClass = (uint16_t)((rawCsd[2U] & 0xFFF00000U) >> 20U); + csd->readBlockLength = (uint8_t)((rawCsd[2U] & 0xF0000U) >> 16U); + if (rawCsd[2U] & 0x8000U) + { + csd->flags |= kSD_CsdReadBlockPartialFlag; + } + if (rawCsd[2U] & 0x4000U) + { + csd->flags |= kSD_CsdReadBlockPartialFlag; + } + if (rawCsd[2U] & 0x2000U) + { + csd->flags |= kSD_CsdReadBlockMisalignFlag; + } + if (rawCsd[2U] & 0x1000U) + { + csd->flags |= kSD_CsdDsrImplementedFlag; + } + switch (csd->csdStructure) + { + case 0: + csd->deviceSize = (uint32_t)((rawCsd[2U] & 0x3FFU) << 2U); + csd->deviceSize |= (uint32_t)((rawCsd[1U] & 0xC0000000U) >> 30U); + csd->readCurrentVddMin = (uint8_t)((rawCsd[1U] & 0x38000000U) >> 27U); + csd->readCurrentVddMax = (uint8_t)((rawCsd[1U] & 0x7000000U) >> 24U); + csd->writeCurrentVddMin = (uint8_t)((rawCsd[1U] & 0xE00000U) >> 20U); + csd->writeCurrentVddMax = (uint8_t)((rawCsd[1U] & 0x1C0000U) >> 18U); + csd->deviceSizeMultiplier = (uint8_t)((rawCsd[1U] & 0x38000U) >> 15U); + + /* Get card total block count and block size. */ + card->blockCount = ((csd->deviceSize + 1U) << (csd->deviceSizeMultiplier + 2U)); + card->blockSize = (1U << (csd->readBlockLength)); + if (card->blockSize != FSL_SDMMC_DEFAULT_BLOCK_SIZE) + { + card->blockCount = (card->blockCount * card->blockSize); + card->blockSize = FSL_SDMMC_DEFAULT_BLOCK_SIZE; + card->blockCount = (card->blockCount / card->blockSize); + } + break; + case 1: + card->blockSize = FSL_SDMMC_DEFAULT_BLOCK_SIZE; + + csd->deviceSize = (uint32_t)((rawCsd[2U] & 0x3FU) << 16U); + csd->deviceSize |= (uint32_t)((rawCsd[1U] & 0xFFFF0000U) >> 16U); + if (csd->deviceSize >= 0xFFFFU) + { + card->flags |= kSD_SupportSdxcFlag; + } + + card->blockCount = ((csd->deviceSize + 1U) * 1024U); + break; + default: + break; + } + if ((uint8_t)((rawCsd[1U] & 0x4000U) >> 14U)) + { + csd->flags |= kSD_CsdEraseBlockEnabledFlag; + } + csd->eraseSectorSize = (uint8_t)((rawCsd[1U] & 0x3F80U) >> 7U); + csd->writeProtectGroupSize = (uint8_t)(rawCsd[1U] & 0x7FU); + if ((uint8_t)(rawCsd[0U] & 0x80000000U)) + { + csd->flags |= kSD_CsdWriteProtectGroupEnabledFlag; + } + csd->writeSpeedFactor = (uint8_t)((rawCsd[0U] & 0x1C000000U) >> 26U); + csd->writeBlockLength = (uint8_t)((rawCsd[0U] & 0x3C00000U) >> 22U); + if ((uint8_t)((rawCsd[0U] & 0x200000U) >> 21U)) + { + csd->flags |= kSD_CsdWriteBlockPartialFlag; + } + if ((uint8_t)((rawCsd[0U] & 0x8000U) >> 15U)) + { + csd->flags |= kSD_CsdFileFormatGroupFlag; + } + if ((uint8_t)((rawCsd[0U] & 0x4000U) >> 14U)) + { + csd->flags |= kSD_CsdCopyFlag; + } + if ((uint8_t)((rawCsd[0U] & 0x2000U) >> 13U)) + { + csd->flags |= kSD_CsdPermanentWriteProtectFlag; + } + if ((uint8_t)((rawCsd[0U] & 0x1000U) >> 12U)) + { + csd->flags |= kSD_CsdTemporaryWriteProtectFlag; + } + csd->fileFormat = (uint8_t)((rawCsd[0U] & 0xC00U) >> 10U); +} + +static status_t SD_SendCsd(sd_card_t *card) +{ + assert(card); + + SDMMCHOST_TRANSFER content = {0}; + SDMMCHOST_COMMAND command = {0}; + status_t error = kStatus_Success; + + command.index = kSDMMC_SendCsd; + command.argument = (card->relativeAddress << 16U); + command.responseType = kCARD_ResponseTypeR2; + + content.command = &command; + content.data = NULL; + error = card->host.transfer(card->host.base, &content); + if (kStatus_Success == error) + { + memcpy(card->rawCsd, command.response, sizeof(card->rawCsd)); + /* The response is from bit 127:8 in R2, corrisponding to command.response[3U]:command.response[0U][31U:8]. */ + SD_DecodeCsd(card, command.response); + } + else + { + error = kStatus_SDMMC_TransferFailed; + SDMMC_LOG("\r\nError: send CMD9(get csd) failed with host error %d, response %x", error, command.response[0U]); + } + + return error; +} + +static void SD_DecodeCid(sd_card_t *card, uint32_t *rawCid) +{ + assert(card); + assert(rawCid); + + sd_cid_t *cid; + + cid = &(card->cid); + cid->manufacturerID = (uint8_t)((rawCid[3U] & 0xFF000000U) >> 24U); + cid->applicationID = (uint16_t)((rawCid[3U] & 0xFFFF00U) >> 8U); + + cid->productName[0U] = (uint8_t)((rawCid[3U] & 0xFFU)); + cid->productName[1U] = (uint8_t)((rawCid[2U] & 0xFF000000U) >> 24U); + cid->productName[2U] = (uint8_t)((rawCid[2U] & 0xFF0000U) >> 16U); + cid->productName[3U] = (uint8_t)((rawCid[2U] & 0xFF00U) >> 8U); + cid->productName[4U] = (uint8_t)((rawCid[2U] & 0xFFU)); + + cid->productVersion = (uint8_t)((rawCid[1U] & 0xFF000000U) >> 24U); + + cid->productSerialNumber = (uint32_t)((rawCid[1U] & 0xFFFFFFU) << 8U); + cid->productSerialNumber |= (uint32_t)((rawCid[0U] & 0xFF000000U) >> 24U); + + cid->manufacturerData = (uint16_t)((rawCid[0U] & 0xFFF00U) >> 8U); +} + +static status_t SD_AllSendCid(sd_card_t *card) +{ + assert(card); + + SDMMCHOST_TRANSFER content = {0}; + SDMMCHOST_COMMAND command = {0}; + + command.index = kSDMMC_AllSendCid; + command.argument = 0U; + command.responseType = kCARD_ResponseTypeR2; + + content.command = &command; + content.data = NULL; + if (kStatus_Success == card->host.transfer(card->host.base, &content)) + { + memcpy(card->rawCid, command.response, sizeof(card->rawCid)); + SD_DecodeCid(card, command.response); + + return kStatus_Success; + } + + return kStatus_SDMMC_TransferFailed; +} + +static status_t SD_ApplicationSendOperationCondition(sd_card_t *card, uint32_t argument) +{ + assert(card); + + SDMMCHOST_TRANSFER content = {0}; + SDMMCHOST_COMMAND command = {0}; + status_t error = kStatus_Fail; + uint32_t i = FSL_SDMMC_MAX_VOLTAGE_RETRIES; + + command.index = kSD_ApplicationSendOperationCondition; + command.argument = argument; + command.responseType = kCARD_ResponseTypeR3; + + while (i--) + { + if (kStatus_Success != SD_SendApplicationCmd(card, 0U)) + { + continue; + } + + content.command = &command; + content.data = NULL; + error = card->host.transfer(card->host.base, &content); + if (kStatus_Success != error) + { + SDMMC_LOG("\r\nError: send ACMD41 failed with host error %d, response %x", error, command.response[0U]); + return kStatus_SDMMC_TransferFailed; + } + + /* Wait until card exit busy state. */ + if (command.response[0U] & SDMMC_MASK(kSD_OcrPowerUpBusyFlag)) + { + /* high capacity check */ + if (command.response[0U] & SDMMC_MASK(kSD_OcrCardCapacitySupportFlag)) + { + card->flags |= kSD_SupportHighCapacityFlag; + } + /* 1.8V support */ + if (command.response[0U] & SDMMC_MASK(kSD_OcrSwitch18AcceptFlag)) + { + card->flags |= kSD_SupportVoltage180v; + } + card->ocr = command.response[0U]; + + return kStatus_Success; + } + } + + SDMMC_LOG("\r\nError: send ACMD41 timeout"); + + return error; +} + +static status_t SD_SendInterfaceCondition(sd_card_t *card) +{ + assert(card); + + SDMMCHOST_TRANSFER content = {0}; + SDMMCHOST_COMMAND command = {0}; + uint32_t i = FSL_SDMMC_MAX_CMD_RETRIES; + status_t error = kStatus_Success; + + command.index = kSD_SendInterfaceCondition; + command.argument = 0x1AAU; + command.responseType = kCARD_ResponseTypeR7; + + content.command = &command; + content.data = NULL; + do + { + error = card->host.transfer(card->host.base, &content); + if (kStatus_Success != error) + { + SDMMC_LOG("\r\nError: send CMD8 failed with host error %d, response %x", error, command.response[0U]); + } + else + { + if ((command.response[0U] & 0xFFU) != 0xAAU) + { + error = kStatus_SDMMC_CardNotSupport; + SDMMC_LOG("\r\nError: card not support CMD8"); + } + else + { + error = kStatus_Success; + } + } + } while (--i && (error != kStatus_Success)); + + return error; +} + +static status_t SD_SelectBusTiming(sd_card_t *card) +{ + assert(card); + + status_t error = kStatus_SDMMC_SwitchBusTimingFailed; + + if (card->operationVoltage != kCARD_OperationVoltage180V) + { + /* Switch the card to high speed mode */ + if (card->host.capability.flags & kSDMMCHOST_SupportHighSpeed) + { + /* group 1, function 1 ->high speed mode*/ + error = SD_SelectFunction(card, kSD_GroupTimingMode, kSD_FunctionSDR25HighSpeed); + /* If the result isn't "switching to high speed mode(50MHZ) successfully or card doesn't support high speed + * mode". Return failed status. */ + if (error == kStatus_Success) + { + card->currentTiming = kSD_TimingSDR25HighSpeedMode; + card->busClock_Hz = + SDMMCHOST_SET_CARD_CLOCK(card->host.base, card->host.sourceClock_Hz, SD_CLOCK_50MHZ); + } + else if (error == kStatus_SDMMC_NotSupportYet) + { + /* if not support high speed, keep the card work at default mode */ + SDMMC_LOG("\r\nNote: High speed mode is not supported by card"); + return kStatus_Success; + } + } + else + { + /* if not support high speed, keep the card work at default mode */ + return kStatus_Success; + } + } + /* card is in UHS_I mode */ + else if ((kSDMMCHOST_SupportSDR104 != SDMMCHOST_NOT_SUPPORT) || + (kSDMMCHOST_SupportSDR50 != SDMMCHOST_NOT_SUPPORT) || (kSDMMCHOST_SupportDDR50 != SDMMCHOST_NOT_SUPPORT)) + { + switch (card->currentTiming) + { + /* if not select timing mode, sdmmc will handle it automatically*/ + case kSD_TimingSDR12DefaultMode: + case kSD_TimingSDR104Mode: + error = SD_SelectFunction(card, kSD_GroupTimingMode, kSD_FunctionSDR104); + if (error == kStatus_Success) + { + card->currentTiming = kSD_TimingSDR104Mode; + card->busClock_Hz = SDMMCHOST_SET_CARD_CLOCK(card->host.base, card->host.sourceClock_Hz, + SDMMCHOST_SUPPORT_SDR104_FREQ); + break; + } + SDMMC_LOG("\r\nNote: SDR104 mode is not supported by card"); + + case kSD_TimingDDR50Mode: + error = SD_SelectFunction(card, kSD_GroupTimingMode, kSD_FunctionDDR50); + if (error == kStatus_Success) + { + card->currentTiming = kSD_TimingDDR50Mode; + card->busClock_Hz = + SDMMCHOST_SET_CARD_CLOCK(card->host.base, card->host.sourceClock_Hz, SD_CLOCK_50MHZ); + SDMMCHOST_ENABLE_DDR_MODE(card->host.base, true, 0U); + break; + } + SDMMC_LOG("\r\nNote: DDR50 mode is not supported by card"); + + case kSD_TimingSDR50Mode: + error = SD_SelectFunction(card, kSD_GroupTimingMode, kSD_FunctionSDR50); + if (error == kStatus_Success) + { + card->currentTiming = kSD_TimingSDR50Mode; + card->busClock_Hz = + SDMMCHOST_SET_CARD_CLOCK(card->host.base, card->host.sourceClock_Hz, SD_CLOCK_100MHZ); + break; + } + SDMMC_LOG("\r\nNote: SDR50 mode is not supported by card"); + + case kSD_TimingSDR25HighSpeedMode: + error = SD_SelectFunction(card, kSD_GroupTimingMode, kSD_FunctionSDR25HighSpeed); + if (error == kStatus_Success) + { + card->currentTiming = kSD_TimingSDR25HighSpeedMode; + card->busClock_Hz = + SDMMCHOST_SET_CARD_CLOCK(card->host.base, card->host.sourceClock_Hz, SD_CLOCK_50MHZ); + } + break; + + default: + SDMMC_LOG("\r\nWarning: unknown timing mode"); + break; + } + } + else + { + } + + if (error == kStatus_Success) + { + /* SDR50 and SDR104 mode need tuning */ + if ((card->currentTiming == kSD_TimingSDR50Mode) || (card->currentTiming == kSD_TimingSDR104Mode)) + { + /* config IO strength in IOMUX*/ + if (card->currentTiming == kSD_TimingSDR50Mode) + { + SDMMCHOST_CONFIG_SD_IO(CARD_BUS_FREQ_100MHZ1, CARD_BUS_STRENGTH_7); + } + else + { + SDMMCHOST_CONFIG_SD_IO(CARD_BUS_FREQ_200MHZ, CARD_BUS_STRENGTH_7); + } + /* execute tuning */ + if (SD_ExecuteTuning(card) != kStatus_Success) + { + SDMMC_LOG("\r\nError: tuning failed for mode %d", card->currentTiming); + return kStatus_SDMMC_TuningFail; + } + } + else + { + /* set default IO strength to 4 to cover card adapter driver strength difference */ + SDMMCHOST_CONFIG_SD_IO(CARD_BUS_FREQ_100MHZ1, CARD_BUS_STRENGTH_4); + } + } + + return error; +} + +static void SD_DecodeStatus(sd_card_t *card, uint32_t *src) +{ + assert(card); + assert(src); + + card->stat.busWidth = (uint8_t)((src[0U] & 0xC0000000U) >> 30U); /* 511-510 */ + card->stat.secureMode = (uint8_t)((src[0U] & 0x20000000U) >> 29U); /* 509 */ + card->stat.cardType = (uint16_t)((src[0U] & 0x0000FFFFU)); /* 495-480 */ + card->stat.protectedSize = src[1U]; /* 479-448 */ + card->stat.speedClass = (uint8_t)((src[2U] & 0xFF000000U) >> 24U); /* 447-440 */ + card->stat.performanceMove = (uint8_t)((src[2U] & 0x00FF0000U) >> 16U); /* 439-432 */ + card->stat.auSize = (uint8_t)((src[2U] & 0x0000F000U) >> 12U); /* 431-428 */ + card->stat.eraseSize = (uint16_t)(((src[2U] & 0x000000FFU) << 8U) | ((src[3U] & 0xFF000000U) >> 24U)); /* 423-408 */ + card->stat.eraseTimeout = (((uint8_t)((src[3U] & 0x00FF0000U) >> 16U)) & 0xFCU) >> 2U; /* 407-402 */ + card->stat.eraseOffset = ((uint8_t)((src[3U] & 0x00FF0000U) >> 16U)) & 0x3U; /* 401-400 */ + card->stat.uhsSpeedGrade = (((uint8_t)((src[3U] & 0x0000FF00U) >> 8U)) & 0xF0U) >> 4U; /* 399-396 */ + card->stat.uhsAuSize = ((uint8_t)((src[3U] & 0x0000FF00U) >> 8U)) & 0xFU; /* 395-392 */ +} + +status_t SD_ReadStatus(sd_card_t *card) +{ + assert(card); + + uint32_t i = 0U; + SDMMCHOST_TRANSFER content = {0}; + SDMMCHOST_COMMAND command = {0}; + SDMMCHOST_DATA data = {0}; + status_t error = kStatus_Success; + + memset(g_sdmmc, 0U, sizeof(g_sdmmc)); + + /* wait card status ready. */ + if (kStatus_Success != SD_WaitWriteComplete(card)) + { + return kStatus_SDMMC_WaitWriteCompleteFailed; + } + + if (kStatus_Success != SD_SendApplicationCmd(card, card->relativeAddress)) + { + return kStatus_SDMMC_SendApplicationCommandFailed; + } + + command.index = kSDMMC_SendStatus; + command.responseType = kCARD_ResponseTypeR1; + + data.blockSize = 64U; + data.blockCount = 1U; + data.rxData = &g_sdmmc[0]; + + content.command = &command; + content.data = &data; + error = card->host.transfer(card->host.base, &content); + if ((kStatus_Success != error) || ((command.response[0U]) & SDMMC_R1_ALL_ERROR_FLAG)) + { + SDMMC_LOG("\r\nError: send ACMD13 failed with host error %d, response %x", error, command.response[0U]); + + return kStatus_SDMMC_TransferFailed; + } + + switch (card->host.config.endianMode) + { + case kSDMMCHOST_EndianModeLittle: + /* In little endian mode, SD bus byte transferred first is the byte stored in lowest byte position in + a word which will cause 4 byte's sequence in a word is not consistent with their original sequence from + card. So the sequence of 4 bytes received in a word should be converted. */ + for (i = 0U; i < 16; i++) + { + g_sdmmc[i] = SWAP_WORD_BYTE_SEQUENCE(g_sdmmc[i]); + } + break; + case kSDMMCHOST_EndianModeBig: + break; /* Doesn't need to switch byte sequence when decodes bytes as big endian sequence. */ + case kSDMMCHOST_EndianModeHalfWordBig: + for (i = 0U; i < 16; i++) + { + g_sdmmc[i] = SWAP_HALF_WROD_BYTE_SEQUENCE(g_sdmmc[i]); + } + break; + default: + return kStatus_SDMMC_NotSupportYet; + } + + SD_DecodeStatus(card, g_sdmmc); + + return kStatus_Success; +} + +status_t SD_SelectCard(sd_card_t *card, bool isSelected) +{ + assert(card); + + return SDMMC_SelectCard(card->host.base, card->host.transfer, card->relativeAddress, isSelected); +} + +status_t SD_SetDriverStrength(sd_card_t *card, sd_driver_strength_t driverStrength) +{ + assert(card); + + status_t error; + uint32_t strength = driverStrength; + + error = SD_SelectFunction(card, kSD_GroupDriverStrength, strength); + + return error; +} + +status_t SD_SetMaxCurrent(sd_card_t *card, sd_max_current_t maxCurrent) +{ + assert(card); + + status_t error; + uint32_t current = maxCurrent; + + error = SD_SelectFunction(card, kSD_GroupCurrentLimit, current); + + return error; +} + +static status_t SD_Read(sd_card_t *card, uint8_t *buffer, uint32_t startBlock, uint32_t blockSize, uint32_t blockCount) +{ + assert(card); + assert(buffer); + assert(blockCount); + assert(blockSize == FSL_SDMMC_DEFAULT_BLOCK_SIZE); + + SDMMCHOST_TRANSFER content = {0}; + SDMMCHOST_COMMAND command = {0}; + SDMMCHOST_DATA data = {0}; + + if (((card->flags & kSD_SupportHighCapacityFlag) && (blockSize != 512U)) || (blockSize > card->blockSize) || + (blockSize > card->host.capability.maxBlockLength) || (blockSize % 4)) + { + SDMMC_LOG("\r\nError: read with parameter, block size %d is not support", blockSize); + return kStatus_SDMMC_CardNotSupport; + } + + /* Wait for the card write process complete because of that card read process and write process use one buffer. */ + if (kStatus_Success != SD_WaitWriteComplete(card)) + { + return kStatus_SDMMC_WaitWriteCompleteFailed; + } + + data.blockSize = blockSize; + data.blockCount = blockCount; + data.rxData = (uint32_t *)buffer; + data.enableAutoCommand12 = true; + + command.index = (blockCount == 1U) ? kSDMMC_ReadSingleBlock : kSDMMC_ReadMultipleBlock; + command.argument = startBlock; + if (!(card->flags & kSD_SupportHighCapacityFlag)) + { + command.argument *= data.blockSize; + } + command.responseType = kCARD_ResponseTypeR1; + command.responseErrorFlags = SDMMC_R1_ALL_ERROR_FLAG; + + content.command = &command; + content.data = &data; + + return SD_Transfer(card, &content, 1U); +} + +static status_t SD_Write(sd_card_t *card, + const uint8_t *buffer, + uint32_t startBlock, + uint32_t blockSize, + uint32_t blockCount, + uint32_t *writtenBlocks) +{ + assert(card); + assert(buffer); + assert(blockCount); + assert(blockSize == FSL_SDMMC_DEFAULT_BLOCK_SIZE); + + SDMMCHOST_TRANSFER content = {0}; + SDMMCHOST_COMMAND command = {0}; + SDMMCHOST_DATA data = {0}; + status_t error; + + if (((card->flags & kSD_SupportHighCapacityFlag) && (blockSize != 512U)) || (blockSize > card->blockSize) || + (blockSize > card->host.capability.maxBlockLength) || (blockSize % 4U)) + { + SDMMC_LOG("\r\nError: write with parameter, block size %d is not support", blockSize); + return kStatus_SDMMC_CardNotSupport; + } + + /* Wait for the card write process complete because of that card read process and write process use one buffer.*/ + if (kStatus_Success != SD_WaitWriteComplete(card)) + { + return kStatus_SDMMC_WaitWriteCompleteFailed; + } + + /* Wait for the card's buffer to be not full to write to improve the write performance. */ + while ((GET_SDMMCHOST_STATUS(card->host.base) & CARD_DATA0_STATUS_MASK) != CARD_DATA0_NOT_BUSY) + { + } + + data.enableAutoCommand12 = true; + data.blockSize = blockSize; + command.responseType = kCARD_ResponseTypeR1; + command.responseErrorFlags = SDMMC_R1_ALL_ERROR_FLAG; + + command.index = (blockCount == 1U) ? kSDMMC_WriteSingleBlock : kSDMMC_WriteMultipleBlock; + command.argument = startBlock; + if (!(card->flags & kSD_SupportHighCapacityFlag)) + { + command.argument *= data.blockSize; + } + + *writtenBlocks = blockCount; + data.blockCount = blockCount; + data.txData = (const uint32_t *)(buffer); + + content.command = &command; + content.data = &data; + + error = SD_Transfer(card, &content, 0U); + if (error != kStatus_Success) + { + /* check the successfully written block */ + if ((SD_SendWriteSuccessBlocks(card, writtenBlocks) == kStatus_Success)) + { + if (*writtenBlocks) + { + /* written success, but not all the blocks are written */ + error = kStatus_Success; + } + } + SDMMC_LOG("\r\nWarning: write failed with block count %d, successed %d", blockCount, *writtenBlocks); + } + + return error; +} + +static status_t SD_Erase(sd_card_t *card, uint32_t startBlock, uint32_t blockCount) +{ + assert(card); + assert(blockCount); + + uint32_t eraseBlockStart; + uint32_t eraseBlockEnd; + SDMMCHOST_TRANSFER content = {0}; + SDMMCHOST_COMMAND command = {0}; + status_t error = kStatus_Success; + + /* Wait for the card write process complete because of that card read process and write process use one buffer.*/ + if (kStatus_Success != SD_WaitWriteComplete(card)) + { + return kStatus_SDMMC_WaitWriteCompleteFailed; + } + /* Wait for the card's buffer to be not full to write to improve the write performance. */ + while ((GET_SDMMCHOST_STATUS(card->host.base) & CARD_DATA0_STATUS_MASK) != CARD_DATA0_NOT_BUSY) + { + } + + eraseBlockStart = startBlock; + eraseBlockEnd = eraseBlockStart + blockCount - 1U; + if (!(card->flags & kSD_SupportHighCapacityFlag)) + { + eraseBlockStart = eraseBlockStart * FSL_SDMMC_DEFAULT_BLOCK_SIZE; + eraseBlockEnd = eraseBlockEnd * FSL_SDMMC_DEFAULT_BLOCK_SIZE; + } + + /* Send ERASE_WRITE_BLOCK_START command to set the start block number to erase. */ + command.index = kSD_EraseWriteBlockStart; + command.argument = eraseBlockStart; + command.responseType = kCARD_ResponseTypeR1; + command.responseErrorFlags = SDMMC_R1_ALL_ERROR_FLAG; + + content.command = &command; + content.data = NULL; + error = SD_Transfer(card, &content, 1U); + if (kStatus_Success != error) + { + SDMMC_LOG("\r\nError: send CMD32(erase start) failed with host error %d, response %x", error, + command.response[0U]); + return kStatus_SDMMC_TransferFailed; + } + + /* Send ERASE_WRITE_BLOCK_END command to set the end block number to erase. */ + command.index = kSD_EraseWriteBlockEnd; + command.argument = eraseBlockEnd; + + content.command = &command; + content.data = NULL; + error = SD_Transfer(card, &content, 0U); + if (kStatus_Success != error) + { + SDMMC_LOG("\r\nError: send CMD33(erase end) failed with host error %d, response %x", error, + command.response[0U]); + return kStatus_SDMMC_TransferFailed; + } + + /* Send ERASE command to start erase process. */ + command.index = kSDMMC_Erase; + command.argument = 0U; + command.responseType = kCARD_ResponseTypeR1b; + command.responseErrorFlags = SDMMC_R1_ALL_ERROR_FLAG; + + content.command = &command; + content.data = NULL; + error = SD_Transfer(card, &content, 0U); + if (kStatus_Success != error) + { + SDMMC_LOG("\r\nError: send CMD38(erase) failed with host error %d, response %x", error, command.response[0U]); + return kStatus_SDMMC_TransferFailed; + } + + return kStatus_Success; +} + +bool SD_CheckReadOnly(sd_card_t *card) +{ + assert(card); + + return ((card->csd.flags & kSD_CsdPermanentWriteProtectFlag) || + (card->csd.flags & kSD_CsdTemporaryWriteProtectFlag)); +} + +status_t SD_ReadBlocks(sd_card_t *card, uint8_t *buffer, uint32_t startBlock, uint32_t blockCount) +{ + assert(card); + assert(buffer); + assert(blockCount); + assert((blockCount + startBlock) <= card->blockCount); + + uint32_t blockCountOneTime; + uint32_t blockLeft; + uint32_t blockDone = 0U; + uint8_t *nextBuffer = buffer; + bool dataAddrAlign = true; + + blockLeft = blockCount; + + while (blockLeft) + { + nextBuffer = (buffer + blockDone * FSL_SDMMC_DEFAULT_BLOCK_SIZE); + if (!card->noInteralAlign && (!dataAddrAlign || (((uint32_t)nextBuffer) & (sizeof(uint32_t) - 1U)))) + { + blockLeft--; + blockCountOneTime = 1U; + memset(g_sdmmc, 0U, FSL_SDMMC_DEFAULT_BLOCK_SIZE); + dataAddrAlign = false; + } + else + { + if (blockLeft > card->host.capability.maxBlockCount) + { + blockLeft = (blockLeft - card->host.capability.maxBlockCount); + blockCountOneTime = card->host.capability.maxBlockCount; + } + else + { + blockCountOneTime = blockLeft; + blockLeft = 0U; + } + } + + if (kStatus_Success != SD_Read(card, dataAddrAlign ? nextBuffer : (uint8_t *)g_sdmmc, (startBlock + blockDone), + FSL_SDMMC_DEFAULT_BLOCK_SIZE, blockCountOneTime)) + { + return kStatus_SDMMC_TransferFailed; + } + + blockDone += blockCountOneTime; + + if (!card->noInteralAlign && (!dataAddrAlign)) + { + memcpy(nextBuffer, (uint8_t *)&g_sdmmc, FSL_SDMMC_DEFAULT_BLOCK_SIZE); + } + } + + return kStatus_Success; +} + +status_t SD_WriteBlocks(sd_card_t *card, const uint8_t *buffer, uint32_t startBlock, uint32_t blockCount) +{ + assert(card); + assert(buffer); + assert(blockCount); + assert((blockCount + startBlock) <= card->blockCount); + + uint32_t blockCountOneTime = 0U; /* The block count can be wrote in one time sending WRITE_BLOCKS command. */ + uint32_t blockWrittenOneTime = 0U; + uint32_t blockLeft = 0U; /* Left block count to be wrote. */ + const uint8_t *nextBuffer; + bool dataAddrAlign = true; + + blockLeft = blockCount; + while (blockLeft) + { + nextBuffer = (buffer + (blockCount - blockLeft) * FSL_SDMMC_DEFAULT_BLOCK_SIZE); + if (!card->noInteralAlign && (!dataAddrAlign || (((uint32_t)nextBuffer) & (sizeof(uint32_t) - 1U)))) + { + blockCountOneTime = 1U; + memcpy((uint8_t *)&g_sdmmc, nextBuffer, FSL_SDMMC_DEFAULT_BLOCK_SIZE); + dataAddrAlign = false; + } + else + { + if (blockLeft > card->host.capability.maxBlockCount) + { + blockCountOneTime = card->host.capability.maxBlockCount; + } + else + { + blockCountOneTime = blockLeft; + } + } + + if (kStatus_Success != SD_Write(card, dataAddrAlign ? nextBuffer : (uint8_t *)g_sdmmc, + (startBlock + blockCount - blockLeft), FSL_SDMMC_DEFAULT_BLOCK_SIZE, + blockCountOneTime, &blockWrittenOneTime)) + { + return kStatus_SDMMC_TransferFailed; + } + + blockLeft -= blockWrittenOneTime; + + if ((!card->noInteralAlign) && !dataAddrAlign) + { + memset(g_sdmmc, 0U, FSL_SDMMC_DEFAULT_BLOCK_SIZE); + } + } + + return kStatus_Success; +} + +status_t SD_EraseBlocks(sd_card_t *card, uint32_t startBlock, uint32_t blockCount) +{ + assert(card); + assert(blockCount); + assert((blockCount + startBlock) <= card->blockCount); + + uint32_t blockCountOneTime; /* The block count can be erased in one time sending ERASE_BLOCKS command. */ + uint32_t blockDone = 0U; /* The block count has been erased. */ + uint32_t blockLeft; /* Left block count to be erase. */ + status_t error; + uint32_t onetimeMaxEraseBlocks = 0U; + + /* sdsc card erasable sector is determined by CSD register */ + if (card->csd.csdStructure == 0U) + { + onetimeMaxEraseBlocks = card->csd.eraseSectorSize + 1U; + } + else + { + /* limit one time maximum erase size to 1 AU */ + if (card->stat.auSize >= SD_AU_START_VALUE) + { + onetimeMaxEraseBlocks = s_sdAuSizeMap[card->stat.auSize] / FSL_SDMMC_DEFAULT_BLOCK_SIZE; + } + } + + if (onetimeMaxEraseBlocks == 0U) + { + SDMMC_LOG( + "Warning: AU size in sd descriptor is not set properly, please check if SD_ReadStatus is called before\ + SD_EraseBlocks"); + return kStatus_SDMMC_AuSizeNotSetProperly; + } + + blockLeft = blockCount; + while (blockLeft) + { + if (blockLeft > onetimeMaxEraseBlocks) + { + blockCountOneTime = onetimeMaxEraseBlocks; + blockLeft = blockLeft - blockCountOneTime; + } + else + { + blockCountOneTime = blockLeft; + blockLeft = 0U; + } + + error = SD_Erase(card, (startBlock + blockDone), blockCountOneTime); + if (error != kStatus_Success) + { + return error; + } + + blockDone += blockCountOneTime; + } + + return kStatus_Success; +} + +status_t SD_ProbeBusVoltage(sd_card_t *card) +{ + assert(card); + + uint32_t applicationCommand41Argument = 0U; + status_t error = kStatus_Success; + + /* 3.3V voltage should be supported as default */ + applicationCommand41Argument |= + SDMMC_MASK(kSD_OcrVdd29_30Flag) | SDMMC_MASK(kSD_OcrVdd32_33Flag) | SDMMC_MASK(kSD_OcrVdd33_34Flag); + /* make sure card signal line voltage is 3.3v before initalization */ + if ((card->usrParam.cardVoltage != NULL) && (card->usrParam.cardVoltage->cardSignalLine3V3 != NULL)) + { + card->usrParam.cardVoltage->cardSignalLine3V3(); + } + else + { + SDMMCHOST_SWITCH_VOLTAGE180V(card->host.base, false); + } + card->operationVoltage = kCARD_OperationVoltage330V; + + /* allow user select the work voltage, if not select, sdmmc will handle it automatically */ + if (kSDMMCHOST_SupportV180 != SDMMCHOST_NOT_SUPPORT) + { + applicationCommand41Argument |= SDMMC_MASK(kSD_OcrSwitch18RequestFlag); + } + + do + { + /* card go idle */ + if (kStatus_Success != SD_GoIdle(card)) + { + error = kStatus_SDMMC_GoIdleFailed; + break; + } + + /* Check card's supported interface condition. */ + if (kStatus_Success == SD_SendInterfaceCondition(card)) + { + /* SDHC or SDXC card */ + applicationCommand41Argument |= SDMMC_MASK(kSD_OcrHostCapacitySupportFlag); + card->flags |= kSD_SupportSdhcFlag; + } + else + { + /* SDSC card */ + if (kStatus_Success != SD_GoIdle(card)) + { + error = kStatus_SDMMC_GoIdleFailed; + break; + } + } + /* Set card interface condition according to SDHC capability and card's supported interface condition. */ + if (kStatus_Success != SD_ApplicationSendOperationCondition(card, applicationCommand41Argument)) + { + error = kStatus_SDMMC_HandShakeOperationConditionFailed; + break; + } + + /* check if card support 1.8V */ + if ((card->flags & kSD_SupportVoltage180v)) + { + error = SD_SwitchVoltage(card); + if (kStatus_SDMMC_SwitchVoltageFail == error) + { + break; + } + + if (error == kStatus_SDMMC_SwitchVoltage18VFail33VSuccess) + { + applicationCommand41Argument &= ~SDMMC_MASK(kSD_OcrSwitch18RequestFlag); + card->flags &= ~kSD_SupportVoltage180v; + continue; + } + else + { + card->operationVoltage = kCARD_OperationVoltage180V; + break; + } + } + + break; + } while (1U); + + return error; +} + +status_t SD_CardInit(sd_card_t *card) +{ + assert(card); + assert(card->isHostReady == true); + + /* reset variables */ + card->flags = 0U; + /* set DATA bus width */ + SDMMCHOST_SET_CARD_BUS_WIDTH(card->host.base, kSDMMCHOST_DATABUSWIDTH1BIT); + /*set card freq to 400KHZ*/ + card->busClock_Hz = SDMMCHOST_SET_CARD_CLOCK(card->host.base, card->host.sourceClock_Hz, SDMMC_CLOCK_400KHZ); + /* send card active */ + SDMMCHOST_SEND_CARD_ACTIVE(card->host.base, 100U); + /* Get host capability. */ + GET_SDMMCHOST_CAPABILITY(card->host.base, &(card->host.capability)); + + /* probe bus voltage*/ + if (SD_ProbeBusVoltage(card) == kStatus_SDMMC_SwitchVoltageFail) + { + return kStatus_SDMMC_SwitchVoltageFail; + } + + /* Initialize card if the card is SD card. */ + if (kStatus_Success != SD_AllSendCid(card)) + { + return kStatus_SDMMC_AllSendCidFailed; + } + if (kStatus_Success != SD_SendRca(card)) + { + return kStatus_SDMMC_SendRelativeAddressFailed; + } + if (kStatus_Success != SD_SendCsd(card)) + { + return kStatus_SDMMC_SendCsdFailed; + } + if (kStatus_Success != SD_SelectCard(card, true)) + { + return kStatus_SDMMC_SelectCardFailed; + } + + /* Set to max frequency in non-high speed mode. */ + card->busClock_Hz = SDMMCHOST_SET_CARD_CLOCK(card->host.base, card->host.sourceClock_Hz, SD_CLOCK_25MHZ); + + if (kStatus_Success != SD_SendScr(card)) + { + return kStatus_SDMMC_SendScrFailed; + } + /* Set to 4-bit data bus mode. */ + if (((card->host.capability.flags) & kSDMMCHOST_Support4BitBusWidth) && (card->flags & kSD_Support4BitWidthFlag)) + { + if (kStatus_Success != SD_SetDataBusWidth(card, kSD_DataBusWidth4Bit)) + { + return kStatus_SDMMC_SetDataBusWidthFailed; + } + SDMMCHOST_SET_CARD_BUS_WIDTH(card->host.base, kSDMMCHOST_DATABUSWIDTH4BIT); + } + + /* set block size */ + if (SD_SetBlockSize(card, FSL_SDMMC_DEFAULT_BLOCK_SIZE)) + { + return kStatus_SDMMC_SetCardBlockSizeFailed; + } + + /* select bus timing */ + if (kStatus_Success != SD_SelectBusTiming(card)) + { + return kStatus_SDMMC_SwitchBusTimingFailed; + } + + /* try to get card current status */ + SD_ReadStatus(card); + + return kStatus_Success; +} + +void SD_CardDeinit(sd_card_t *card) +{ + assert(card); + + SD_SelectCard(card, false); +} + +status_t SD_HostInit(sd_card_t *card) +{ + assert(card); + + if ((!card->isHostReady) && SDMMCHOST_Init(&(card->host), (void *)(&(card->usrParam))) != kStatus_Success) + { + return kStatus_Fail; + } + + /* set the host status flag, after the card re-plug in, don't need init host again */ + card->isHostReady = true; + + return kStatus_Success; +} + +void SD_HostDeinit(sd_card_t *card) +{ + assert(card); + + SDMMCHOST_Deinit(&(card->host)); + /* should re-init host */ + card->isHostReady = false; +} + +void SD_HostReset(SDMMCHOST_CONFIG *host) +{ + SDMMCHOST_Reset(host->base); +} + +void SD_PowerOnCard(SDMMCHOST_TYPE *base, const sdmmchost_pwr_card_t *pwr) +{ + SDMMCHOST_PowerOnCard(base, pwr); +} + +void SD_PowerOffCard(SDMMCHOST_TYPE *base, const sdmmchost_pwr_card_t *pwr) +{ + SDMMCHOST_PowerOffCard(base, pwr); +} + +status_t SD_WaitCardDetectStatus(SDMMCHOST_TYPE *hostBase, const sdmmchost_detect_card_t *cd, bool waitCardStatus) +{ + return SDMMCHOST_WaitCardDetectStatus(hostBase, cd, waitCardStatus); +} + +bool SD_IsCardPresent(sd_card_t *card) +{ + return SDMMCHOST_IsCardPresent(); +} + +status_t SD_Init(sd_card_t *card) +{ + assert(card); + + if (!card->isHostReady) + { + if (SD_HostInit(card) != kStatus_Success) + { + return kStatus_SDMMC_HostNotReady; + } + } + else + { + SD_HostReset(&(card->host)); + } + SD_PowerOffCard(card->host.base, card->usrParam.pwr); + + if (SD_WaitCardDetectStatus(card->host.base, card->usrParam.cd, true) != kStatus_Success) + { + return kStatus_SDMMC_CardDetectFailed; + } + SD_PowerOnCard(card->host.base, card->usrParam.pwr); + + return SD_CardInit(card); +} + +void SD_Deinit(sd_card_t *card) +{ + /* card deinitialize */ + SD_CardDeinit(card); + /* host deinitialize */ + SD_HostDeinit(card); +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/src/fsl_sdio.c b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/src/fsl_sdio.c new file mode 100644 index 000000000..2c45f18e3 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/src/fsl_sdio.c @@ -0,0 +1,1700 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_sdio.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief define the tuple number will be read during init */ +#define SDIO_COMMON_CIS_TUPLE_NUM (3U) +/*! @brief SDIO retry times */ +#define SDIO_RETRY_TIMES (1000U) + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief probe bus voltage. + * @param card Card descriptor. + */ +static status_t SDIO_ProbeBusVoltage(sdio_card_t *card); + +/*! + * @brief send card operation condition + * @param card Card descriptor. + * @param command argment + * argument = 0U , means to get the operation condition + * argument !=0 , set the operation condition register + */ +static status_t SDIO_SendOperationCondition(sdio_card_t *card, uint32_t argument); + +/*! + * @brief card Send relative address + * @param card Card descriptor. + */ +static status_t SDIO_SendRca(sdio_card_t *card); + +/*! + * @brief card select card + * @param card Card descriptor. + * @param select/diselect flag + */ +static status_t inline SDIO_SelectCard(sdio_card_t *card, bool isSelected); + +/*! + * @brief card go idle + * @param card Card descriptor. + */ +static status_t inline SDIO_GoIdle(sdio_card_t *card); + +/*! + * @brief decode CIS + * @param card Card descriptor. + * @param func number + * @param data buffer pointer + * @param tuple code + * @param tuple link + */ +static status_t SDIO_DecodeCIS( + sdio_card_t *card, sdio_func_num_t func, uint8_t *dataBuffer, uint32_t tplCode, uint32_t tplLink); + +/*! + * @brief switch to the maxium support bus width, depend on the host and card's capability. + * @param card Card descriptor. + */ +static status_t SDIO_SetMaxDataBusWidth(sdio_card_t *card); + +/*! + * @brief sdio card excute tuning. + * @param card Card descriptor. + */ + +static status_t SDIO_ExecuteTuning(sdio_card_t *card); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* define the tuple list */ +static const uint32_t g_tupleList[SDIO_COMMON_CIS_TUPLE_NUM] = { + SDIO_TPL_CODE_MANIFID, + SDIO_TPL_CODE_FUNCID, + SDIO_TPL_CODE_FUNCE, +}; + +/* g_sdmmc statement */ +extern uint32_t g_sdmmc[SDK_SIZEALIGN(SDMMC_GLOBAL_BUFFER_SIZE, SDMMC_DATA_BUFFER_ALIGN_CACHE)]; +/******************************************************************************* + * Code + ******************************************************************************/ +static status_t inline SDIO_SelectCard(sdio_card_t *card, bool isSelected) +{ + assert(card); + + return SDMMC_SelectCard(card->host.base, card->host.transfer, card->relativeAddress, isSelected); +} + +static status_t inline SDIO_GoIdle(sdio_card_t *card) +{ + assert(card); + + return SDMMC_GoIdle(card->host.base, card->host.transfer); +} + +static status_t SDIO_SwitchVoltage(sdio_card_t *card) +{ + assert(card); + + if ((card->usrParam.cardVoltage != NULL) && (card->usrParam.cardVoltage->cardSignalLine1V8 != NULL)) + { + return SDMMC_SwitchToVoltage(card->host.base, card->host.transfer, + card->usrParam.cardVoltage->cardSignalLine1V8); + } + + return SDMMC_SwitchToVoltage(card->host.base, card->host.transfer, NULL); +} + +static status_t SDIO_ExecuteTuning(sdio_card_t *card) +{ + assert(card); + + return SDMMC_ExecuteTuning(card->host.base, card->host.transfer, kSD_SendTuningBlock, 64U); +} + +static status_t SDIO_SendRca(sdio_card_t *card) +{ + assert(card); + + uint32_t i = FSL_SDMMC_MAX_CMD_RETRIES; + + SDMMCHOST_TRANSFER content = {0}; + SDMMCHOST_COMMAND command = {0}; + + command.index = kSDIO_SendRelativeAddress; + command.argument = 0U; + command.responseType = kCARD_ResponseTypeR6; + command.responseErrorFlags = kSDIO_StatusR6Error | kSDIO_StatusIllegalCmd | kSDIO_StatusCmdCRCError; + + content.command = &command; + content.data = NULL; + + while (--i) + { + if (kStatus_Success == card->host.transfer(card->host.base, &content)) + { + /* check illegal state and cmd CRC error, may be the voltage or clock not stable, retry the cmd*/ + if (command.response[0U] & (kSDIO_StatusIllegalCmd | kSDIO_StatusCmdCRCError)) + { + continue; + } + + card->relativeAddress = (command.response[0U] >> 16U); + + return kStatus_Success; + } + } + + return kStatus_SDMMC_TransferFailed; +} + +status_t SDIO_CardInActive(sdio_card_t *card) +{ + assert(card); + + return SDMMC_SetCardInactive(card->host.base, card->host.transfer); +} + +static status_t SDIO_SendOperationCondition(sdio_card_t *card, uint32_t argument) +{ + assert(card); + + SDMMCHOST_TRANSFER content = {0U}; + SDMMCHOST_COMMAND command = {0U}; + uint32_t i = SDIO_RETRY_TIMES; + + command.index = kSDIO_SendOperationCondition; + command.argument = argument; + command.responseType = kCARD_ResponseTypeR4; + + content.command = &command; + content.data = NULL; + + while (--i) + { + if (kStatus_Success != card->host.transfer(card->host.base, &content) || (command.response[0U] == 0U)) + { + continue; + } + + /* if argument equal 0, then should check and save the info */ + if (argument == 0U) + { + /* check if memory present */ + if ((command.response[0U] & SDMMC_MASK(kSDIO_OcrMemPresent)) == SDMMC_MASK(kSDIO_OcrMemPresent)) + { + card->memPresentFlag = true; + } + /* save the io number */ + card->ioTotalNumber = (command.response[0U] & SDIO_OCR_IO_NUM_MASK) >> kSDIO_OcrIONumber; + /* save the operation condition */ + card->ocr = command.response[0U] & 0xFFFFFFU; + + break; + } + /* wait the card is ready for after initialization */ + else if (command.response[0U] & SDMMC_MASK(kSDIO_OcrPowerUpBusyFlag)) + { + break; + } + } + + return ((i != 0U) ? kStatus_Success : kStatus_Fail); +} + +status_t SDIO_IO_Write_Direct(sdio_card_t *card, sdio_func_num_t func, uint32_t regAddr, uint8_t *data, bool raw) +{ + assert(card); + assert(func <= kSDIO_FunctionNum7); + + SDMMCHOST_TRANSFER content = {0U}; + SDMMCHOST_COMMAND command = {0U}; + + command.index = kSDIO_RWIODirect; + command.argument = (func << SDIO_CMD_ARGUMENT_FUNC_NUM_POS) | + ((regAddr & SDIO_CMD_ARGUMENT_REG_ADDR_MASK) << SDIO_CMD_ARGUMENT_REG_ADDR_POS) | + (1U << SDIO_CMD_ARGUMENT_RW_POS) | ((raw ? 1U : 0U) << SDIO_DIRECT_CMD_ARGUMENT_RAW_POS) | + (*data & SDIO_DIRECT_CMD_DATA_MASK); + command.responseType = kCARD_ResponseTypeR5; + command.responseErrorFlags = (kSDIO_StatusCmdCRCError | kSDIO_StatusIllegalCmd | kSDIO_StatusError | + kSDIO_StatusFunctionNumError | kSDIO_StatusOutofRange); + + content.command = &command; + content.data = NULL; + + if (kStatus_Success != card->host.transfer(card->host.base, &content)) + { + return kStatus_SDMMC_TransferFailed; + } + + /* read data from response */ + *data = command.response[0U] & SDIO_DIRECT_CMD_DATA_MASK; + + return kStatus_Success; +} + +status_t SDIO_IO_Read_Direct(sdio_card_t *card, sdio_func_num_t func, uint32_t regAddr, uint8_t *data) +{ + assert(card); + assert(func <= kSDIO_FunctionNum7); + + SDMMCHOST_TRANSFER content = {0U}; + SDMMCHOST_COMMAND command = {0U}; + + command.index = kSDIO_RWIODirect; + command.argument = (func << SDIO_CMD_ARGUMENT_FUNC_NUM_POS) | + ((regAddr & SDIO_CMD_ARGUMENT_REG_ADDR_MASK) << SDIO_CMD_ARGUMENT_REG_ADDR_POS); + command.responseType = kCARD_ResponseTypeR5; + command.responseErrorFlags = (kSDIO_StatusCmdCRCError | kSDIO_StatusIllegalCmd | kSDIO_StatusError | + kSDIO_StatusFunctionNumError | kSDIO_StatusOutofRange); + + content.command = &command; + content.data = NULL; + + if (kStatus_Success != card->host.transfer(card->host.base, &content)) + { + return kStatus_SDMMC_TransferFailed; + } + + /* read data from response */ + *data = command.response[0U] & SDIO_DIRECT_CMD_DATA_MASK; + + return kStatus_Success; +} + +status_t SDIO_IO_RW_Direct(sdio_card_t *card, + sdio_io_direction_t direction, + sdio_func_num_t func, + uint32_t regAddr, + uint8_t dataIn, + uint8_t *dataOut) +{ + assert(card); + assert(func <= kSDIO_FunctionNum7); + + SDMMCHOST_TRANSFER content = {0U}; + SDMMCHOST_COMMAND command = {0U}; + + command.index = kSDIO_RWIODirect; + command.argument = (func << SDIO_CMD_ARGUMENT_FUNC_NUM_POS) | + ((regAddr & SDIO_CMD_ARGUMENT_REG_ADDR_MASK) << SDIO_CMD_ARGUMENT_REG_ADDR_POS); + + if ((dataOut != NULL) && (direction == kSDIO_IOWrite)) + { + command.argument |= (1U << SDIO_CMD_ARGUMENT_RW_POS) | (1U << SDIO_DIRECT_CMD_ARGUMENT_RAW_POS); + } + + if (direction == kSDIO_IOWrite) + { + command.argument |= dataIn & SDIO_DIRECT_CMD_DATA_MASK; + } + + command.responseType = kCARD_ResponseTypeR5; + command.responseErrorFlags = (kSDIO_StatusCmdCRCError | kSDIO_StatusIllegalCmd | kSDIO_StatusError | + kSDIO_StatusFunctionNumError | kSDIO_StatusOutofRange); + + command.responseType = kCARD_ResponseTypeR5; + command.responseErrorFlags = (kSDIO_StatusCmdCRCError | kSDIO_StatusIllegalCmd | kSDIO_StatusError | + kSDIO_StatusFunctionNumError | kSDIO_StatusOutofRange); + + content.command = &command; + content.data = NULL; + + if (kStatus_Success != card->host.transfer(card->host.base, &content)) + { + return kStatus_SDMMC_TransferFailed; + } + + if (dataOut != NULL) + { + /* read data from response */ + *dataOut = command.response[0U] & SDIO_DIRECT_CMD_DATA_MASK; + } + + return kStatus_Success; +} + +status_t SDIO_IO_Write_Extended( + sdio_card_t *card, sdio_func_num_t func, uint32_t regAddr, uint8_t *buffer, uint32_t count, uint32_t flags) +{ + assert(card); + assert(buffer); + assert(func <= kSDIO_FunctionNum7); + + SDMMCHOST_TRANSFER content = {0U}; + SDMMCHOST_COMMAND command = {0U}; + SDMMCHOST_DATA data = {0U}; + bool blockMode = false; + bool opCode = false; + + /* check if card support block mode */ + if ((card->cccrflags & kSDIO_CCCRSupportMultiBlock) && (flags & SDIO_EXTEND_CMD_BLOCK_MODE_MASK)) + { + blockMode = true; + } + + if (flags & SDIO_EXTEND_CMD_OP_CODE_MASK) + { + opCode = true; + } + + /* check the byte size counter in non-block mode + * so you need read CIS for each function first,before you do read/write + */ + if (!blockMode) + { + if ((func == kSDIO_FunctionNum0) && (card->commonCIS.fn0MaxBlkSize != 0U) && + (count > card->commonCIS.fn0MaxBlkSize)) + { + return kStatus_SDMMC_SDIO_InvalidArgument; + } + else if ((func != kSDIO_FunctionNum0) && (card->funcCIS[func - 1U].ioMaxBlockSize != 0U) && + (count > card->funcCIS[func - 1U].ioMaxBlockSize)) + { + return kStatus_SDMMC_SDIO_InvalidArgument; + } + } + + command.index = kSDIO_RWIOExtended; + command.argument = (func << SDIO_CMD_ARGUMENT_FUNC_NUM_POS) | + ((regAddr & SDIO_CMD_ARGUMENT_REG_ADDR_MASK) << SDIO_CMD_ARGUMENT_REG_ADDR_POS) | + (1U << SDIO_CMD_ARGUMENT_RW_POS) | (count & SDIO_EXTEND_CMD_COUNT_MASK) | + ((blockMode ? 1 : 0) << SDIO_EXTEND_CMD_ARGUMENT_BLOCK_MODE_POS | + ((opCode ? 1 : 0) << SDIO_EXTEND_CMD_ARGUMENT_OP_CODE_POS)); + command.responseType = kCARD_ResponseTypeR5; + command.responseErrorFlags = (kSDIO_StatusCmdCRCError | kSDIO_StatusIllegalCmd | kSDIO_StatusError | + kSDIO_StatusFunctionNumError | kSDIO_StatusOutofRange); + + if (blockMode) + { + if (func == kSDIO_FunctionNum0) + { + data.blockSize = card->io0blockSize; + } + else + { + data.blockSize = card->ioFBR[func - 1U].ioBlockSize; + } + data.blockCount = count; + } + else + { + data.blockSize = count; + data.blockCount = 1U; + } + data.txData = (uint32_t *)buffer; + + content.command = &command; + content.data = &data; + + if (kStatus_Success != card->host.transfer(card->host.base, &content)) + { + return kStatus_SDMMC_TransferFailed; + } + + return kStatus_Success; +} + +status_t SDIO_IO_Read_Extended( + sdio_card_t *card, sdio_func_num_t func, uint32_t regAddr, uint8_t *buffer, uint32_t count, uint32_t flags) +{ + assert(card); + assert(buffer); + assert(func <= kSDIO_FunctionNum7); + + SDMMCHOST_TRANSFER content = {0U}; + SDMMCHOST_COMMAND command = {0U}; + SDMMCHOST_DATA data = {0U}; + bool blockMode = false; + bool opCode = false; + + /* check if card support block mode */ + if ((card->cccrflags & kSDIO_CCCRSupportMultiBlock) && (flags & SDIO_EXTEND_CMD_BLOCK_MODE_MASK)) + { + blockMode = true; + } + + /* op code =0 : read/write to fixed addr + * op code =1 :read/write addr incrementing + */ + if (flags & SDIO_EXTEND_CMD_OP_CODE_MASK) + { + opCode = true; + } + + /* check the byte size counter in non-block mode + * so you need read CIS for each function first,before you do read/write + */ + if (!blockMode) + { + if ((func == kSDIO_FunctionNum0) && (card->commonCIS.fn0MaxBlkSize != 0U) && + (count > card->commonCIS.fn0MaxBlkSize)) + { + return kStatus_SDMMC_SDIO_InvalidArgument; + } + else if ((func != kSDIO_FunctionNum0) && (card->funcCIS[func - 1U].ioMaxBlockSize != 0U) && + (count > card->funcCIS[func - 1U].ioMaxBlockSize)) + { + return kStatus_SDMMC_SDIO_InvalidArgument; + } + } + + command.index = kSDIO_RWIOExtended; + command.argument = (func << SDIO_CMD_ARGUMENT_FUNC_NUM_POS) | + ((regAddr & SDIO_CMD_ARGUMENT_REG_ADDR_MASK) << SDIO_CMD_ARGUMENT_REG_ADDR_POS) | + (count & SDIO_EXTEND_CMD_COUNT_MASK) | + ((blockMode ? 1U : 0U) << SDIO_EXTEND_CMD_ARGUMENT_BLOCK_MODE_POS | + ((opCode ? 1U : 0U) << SDIO_EXTEND_CMD_ARGUMENT_OP_CODE_POS)); + command.responseType = kCARD_ResponseTypeR5; + command.responseErrorFlags = (kSDIO_StatusCmdCRCError | kSDIO_StatusIllegalCmd | kSDIO_StatusError | + kSDIO_StatusFunctionNumError | kSDIO_StatusOutofRange); + + if (blockMode) + { + if (func == kSDIO_FunctionNum0) + { + data.blockSize = card->io0blockSize; + } + else + { + data.blockSize = card->ioFBR[func - 1U].ioBlockSize; + } + data.blockCount = count; + } + else + { + data.blockSize = count; + data.blockCount = 1U; + } + data.rxData = (uint32_t *)buffer; + + content.command = &command; + content.data = &data; + + if (kStatus_Success != card->host.transfer(card->host.base, &content)) + { + return kStatus_SDMMC_TransferFailed; + } + + return kStatus_Success; +} + +status_t SDIO_IO_Transfer(sdio_card_t *card, + sdio_command_t cmd, + uint32_t argument, + uint32_t blockSize, + uint8_t *txData, + uint8_t *rxData, + uint16_t dataSize, + uint32_t *response) +{ + assert(card != NULL); + + uint32_t actualSize = dataSize; + SDMMCHOST_TRANSFER content = {0U}; + SDMMCHOST_COMMAND command = {0U}; + SDMMCHOST_DATA data = {0U}; + uint32_t i = SDIO_RETRY_TIMES; + uint32_t *dataAddr = (uint32_t *)(txData == NULL ? rxData : txData); + + if ((dataSize != 0U) && (txData != NULL) && (rxData != NULL)) + { + return kStatus_InvalidArgument; + } + + command.index = cmd; + command.argument = argument; + command.responseType = kCARD_ResponseTypeR5; + command.responseErrorFlags = (kSDIO_StatusCmdCRCError | kSDIO_StatusIllegalCmd | kSDIO_StatusError | + kSDIO_StatusFunctionNumError | kSDIO_StatusOutofRange); + content.command = &command; + content.data = NULL; + + if (dataSize) + { + /* if block size bigger than 1, then use block mode */ + if (argument & SDIO_EXTEND_CMD_BLOCK_MODE_MASK) + { + if (dataSize % blockSize != 0) + { + actualSize = ((dataSize / blockSize) + 1) * blockSize; + } + + data.blockCount = actualSize / blockSize; + data.blockSize = blockSize; + } + else + { + data.blockCount = 1; + data.blockSize = dataSize; + } + /* if data buffer address can not meet host controller internal DMA requirement, sdio driver will try to use + * internal align buffer if data size is not bigger than internal buffer size, + * Align address transfer always can get a better performance, so if you want sdio driver make buffer address + * align, you should + * redefine the SDMMC_GLOBAL_BUFFER_SIZE macro to a value which is big enough for your application. + */ + if (((uint32_t)dataAddr & (SDMMCHOST_DMA_BUFFER_ADDR_ALIGN - 1U)) && + (actualSize <= (SDMMC_GLOBAL_BUFFER_SIZE * sizeof(uint32_t))) && (!card->noInternalAlign)) + { + dataAddr = (uint32_t *)g_sdmmc; + memset(g_sdmmc, 0U, actualSize); + if (txData) + { + memcpy(g_sdmmc, txData, dataSize); + } + } + + if (rxData) + { + data.rxData = dataAddr; + } + else + { + data.txData = dataAddr; + } + + content.data = &data; + } + + do + { + if (kStatus_Success == card->host.transfer(card->host.base, &content)) + { + if ((rxData != NULL) && ((uint32_t)rxData & (SDMMCHOST_DMA_BUFFER_ADDR_ALIGN - 1U)) && + (actualSize <= (SDMMC_GLOBAL_BUFFER_SIZE * sizeof(uint32_t))) && (!card->noInternalAlign)) + { + memcpy(rxData, g_sdmmc, dataSize); + } + + if (response != NULL) + { + *response = command.response[0]; + } + + return kStatus_Success; + } + + } while (i--); + + return kStatus_Fail; +} + +status_t SDIO_GetCardCapability(sdio_card_t *card, sdio_func_num_t func) +{ + assert(card); + assert(func <= kSDIO_FunctionNum7); + + uint8_t *tempBuffer = (uint8_t *)g_sdmmc; + uint32_t i = 0U; + + memset(g_sdmmc, 0U, sizeof(g_sdmmc)); + + for (i = 0U; i <= SDIO_CCCR_REG_NUMBER; i++) + { + if (kStatus_Success != + SDIO_IO_RW_Direct(card, kSDIO_IORead, kSDIO_FunctionNum0, SDIO_FBR_BASE(func) + i, 0U, &tempBuffer[i])) + { + return kStatus_SDMMC_TransferFailed; + } + } + + switch (func) + { + case kSDIO_FunctionNum0: + + card->sdVersion = tempBuffer[kSDIO_RegSDVersion]; + card->sdioVersion = tempBuffer[kSDIO_RegCCCRSdioVer] >> 4U; + card->cccrVersioin = tempBuffer[kSDIO_RegCCCRSdioVer] & 0xFU; + /* continuous SPI interrupt */ + if (tempBuffer[kSDIO_RegBusInterface] & 0x40U) + { + card->cccrflags |= kSDIO_CCCRSupportContinuousSPIInt; + } + /* 8bit data bus */ + if (tempBuffer[kSDIO_RegBusInterface] & 0x4U) + { + card->cccrflags |= SDIO_CCCR_SUPPORT_8BIT_BUS; + } + + /* card capability register */ + card->cccrflags |= (tempBuffer[kSDIO_RegCardCapability] & 0xDFU); + /* master power control */ + if (tempBuffer[kSDIO_RegPowerControl] & 0x01U) + { + card->cccrflags |= kSDIO_CCCRSupportMasterPowerControl; + } + /* high speed flag */ + if (tempBuffer[kSDIO_RegBusSpeed] & 0x01U) + { + card->cccrflags |= SDIO_CCCR_SUPPORT_HIGHSPEED; + } + /* uhs mode flag */ + card->cccrflags |= (tempBuffer[kSDIO_RegUHSITimingSupport] & 7U) << 11U; + /* driver type flag */ + card->cccrflags |= (tempBuffer[kSDIO_RegDriverStrength] & 7U) << 14U; + /* low speed 4bit */ + if (tempBuffer[kSDIO_RegCardCapability] & 0x80U) + { + card->cccrflags |= kSDIO_CCCRSupportLowSpeed4Bit; + } + /* common CIS pointer */ + card->commonCISPointer = tempBuffer[kSDIO_RegCommonCISPointer] | + (tempBuffer[kSDIO_RegCommonCISPointer + 1U] << 8U) | + (tempBuffer[kSDIO_RegCommonCISPointer + 2U] << 16U); + + /* check card capability of support async interrupt */ + if ((tempBuffer[kSDIO_RegInterruptExtension] & SDIO_CCCR_ASYNC_INT_MASK) == SDIO_CCCR_ASYNC_INT_MASK) + { + card->cccrflags |= SDIO_CCCR_SUPPORT_ASYNC_INT; + } + + break; + + case kSDIO_FunctionNum1: + case kSDIO_FunctionNum2: + case kSDIO_FunctionNum3: + case kSDIO_FunctionNum4: + case kSDIO_FunctionNum5: + case kSDIO_FunctionNum6: + case kSDIO_FunctionNum7: + card->ioFBR[func - 1U].ioStdFunctionCode = tempBuffer[0U] & 0x0FU; + card->ioFBR[func - 1U].ioExtFunctionCode = tempBuffer[1U]; + card->ioFBR[func - 1U].ioPointerToCIS = tempBuffer[9U] | (tempBuffer[10U] << 8U) | (tempBuffer[11U] << 16U); + card->ioFBR[func - 1U].ioPointerToCSA = + tempBuffer[12U] | (tempBuffer[13U] << 8U) | (tempBuffer[14U] << 16U); + if (tempBuffer[2U] & 0x01U) + { + card->ioFBR[func - 1U].flags |= kSDIO_FBRSupportPowerSelection; + } + if (tempBuffer[0U] & 0x40U) + { + card->ioFBR[func - 1U].flags |= kSDIO_FBRSupportCSA; + } + + break; + + default: + break; + } + + return kStatus_Success; +} + +status_t SDIO_SetBlockSize(sdio_card_t *card, sdio_func_num_t func, uint32_t blockSize) +{ + assert(card); + assert(func <= kSDIO_FunctionNum7); + assert(blockSize <= SDIO_MAX_BLOCK_SIZE); + + uint8_t temp = 0U; + + /* check the block size for block mode + * so you need read CIS for each function first,before you do read/write + */ + if ((func == kSDIO_FunctionNum0) && (card->commonCIS.fn0MaxBlkSize != 0U) && + (blockSize > card->commonCIS.fn0MaxBlkSize)) + { + return kStatus_SDMMC_SDIO_InvalidArgument; + } + else if ((func != kSDIO_FunctionNum0) && (card->funcCIS[func - 1U].ioMaxBlockSize != 0U) && + (blockSize > card->funcCIS[func - 1U].ioMaxBlockSize)) + { + return kStatus_SDMMC_SDIO_InvalidArgument; + } + + temp = blockSize & 0xFFU; + + if (kStatus_Success != SDIO_IO_RW_Direct(card, kSDIO_IOWrite, kSDIO_FunctionNum0, + SDIO_FBR_BASE(func) + kSDIO_RegFN0BlockSizeLow, temp, &temp)) + { + return kStatus_SDMMC_SetCardBlockSizeFailed; + } + + temp = (blockSize >> 8U) & 0xFFU; + + if (kStatus_Success != SDIO_IO_RW_Direct(card, kSDIO_IOWrite, kSDIO_FunctionNum0, + SDIO_FBR_BASE(func) + kSDIO_RegFN0BlockSizeHigh, temp, &temp)) + { + return kStatus_SDMMC_SetCardBlockSizeFailed; + } + + /* record the current block size */ + if (func == kSDIO_FunctionNum0) + { + card->io0blockSize = blockSize; + } + else + { + card->ioFBR[func - 1U].ioBlockSize = blockSize; + } + + return kStatus_Success; +} + +status_t SDIO_CardReset(sdio_card_t *card) +{ + return SDIO_IO_RW_Direct(card, kSDIO_IOWrite, kSDIO_FunctionNum0, kSDIO_RegIOAbort, 0x08U, NULL); +} + +status_t SDIO_SetDataBusWidth(sdio_card_t *card, sdio_bus_width_t busWidth) +{ + assert(card); + + uint8_t regBusInterface = 0U; + + if (((busWidth == kSDIO_DataBus4Bit) && ((card->cccrflags & kSDIO_CCCRSupportHighSpeed) == 0U) && + ((card->cccrflags & kSDIO_CCCRSupportLowSpeed4Bit) == 0U)) || + (((SDMMCHOST_NOT_SUPPORT == kSDMMCHOST_Support8BitBusWidth) || + ((card->cccrflags & SDIO_CCCR_SUPPORT_8BIT_BUS) == 0U)) && + (busWidth == kSDIO_DataBus8Bit))) + { + return kStatus_SDMMC_SDIO_InvalidArgument; + } + + /* load bus interface register */ + if (kStatus_Success != + SDIO_IO_RW_Direct(card, kSDIO_IORead, kSDIO_FunctionNum0, kSDIO_RegBusInterface, 0U, ®BusInterface)) + { + return kStatus_SDMMC_TransferFailed; + } + /* set bus width */ + regBusInterface &= 0xFCU; + regBusInterface |= busWidth; + + /* write to register */ + if (kStatus_Success != SDIO_IO_RW_Direct(card, kSDIO_IOWrite, kSDIO_FunctionNum0, kSDIO_RegBusInterface, + regBusInterface, ®BusInterface)) + { + return kStatus_SDMMC_TransferFailed; + } + + if (busWidth == kSDIO_DataBus8Bit) + { + SDMMCHOST_SET_CARD_BUS_WIDTH(card->host.base, kSDMMCHOST_DATABUSWIDTH8BIT); + } + else if (busWidth == kSDIO_DataBus4Bit) + { + SDMMCHOST_SET_CARD_BUS_WIDTH(card->host.base, kSDMMCHOST_DATABUSWIDTH4BIT); + } + else + { + SDMMCHOST_SET_CARD_BUS_WIDTH(card->host.base, kSDMMCHOST_DATABUSWIDTH1BIT); + } + + return kStatus_Success; +} + +static status_t SDIO_SetMaxDataBusWidth(sdio_card_t *card) +{ + sdio_bus_width_t busWidth = kSDIO_DataBus1Bit; + + if ((SDMMCHOST_NOT_SUPPORT != kSDMMCHOST_Support8BitBusWidth) && + ((card->cccrflags & SDIO_CCCR_SUPPORT_8BIT_BUS) != 0U)) + { + busWidth = kSDIO_DataBus8Bit; + } + + /* switch data bus width */ + if (((card->cccrflags & kSDIO_CCCRSupportHighSpeed) || ((card->cccrflags & kSDIO_CCCRSupportLowSpeed4Bit) != 0U)) && + (busWidth == kSDIO_DataBus1Bit)) + { + busWidth = kSDIO_DataBus4Bit; + } + + return SDIO_SetDataBusWidth(card, busWidth); +} + +status_t SDIO_SwitchToHighSpeed(sdio_card_t *card) +{ + assert(card); + + uint8_t temp = 0U; + uint32_t retryTimes = SDIO_RETRY_TIMES; + status_t status = kStatus_SDMMC_SDIO_SwitchHighSpeedFail; + + if (card->cccrflags & SDIO_CCCR_SUPPORT_HIGHSPEED) + { + if (kStatus_Success != SDIO_IO_RW_Direct(card, kSDIO_IORead, kSDIO_FunctionNum0, kSDIO_RegBusSpeed, 0U, &temp)) + { + return kStatus_SDMMC_TransferFailed; + } + + temp &= ~SDIO_CCCR_BUS_SPEED_MASK; + temp |= SDIO_CCCR_ENABLE_HIGHSPEED_MODE; + + do + { + retryTimes--; + /* enable high speed mode */ + + if (kStatus_Success != + SDIO_IO_RW_Direct(card, kSDIO_IOWrite, kSDIO_FunctionNum0, kSDIO_RegBusSpeed, temp, &temp)) + { + continue; + } + /* either EHS=0 and SHS=0 ,the card is still in default mode */ + if ((temp & 0x03U) == 0x03U) + { + /* high speed mode , set freq to 50MHZ */ + card->busClock_Hz = + SDMMCHOST_SET_CARD_CLOCK(card->host.base, card->host.sourceClock_Hz, SD_CLOCK_50MHZ); + status = kStatus_Success; + break; + } + else + { + continue; + } + + } while (retryTimes); + } + else + { + /* default mode 25MHZ */ + card->busClock_Hz = SDMMCHOST_SET_CARD_CLOCK(card->host.base, card->host.sourceClock_Hz, SD_CLOCK_25MHZ); + status = kStatus_Success; + } + + return status; +} + +static status_t SDIO_SelectBusTiming(sdio_card_t *card) +{ + assert(card); + + uint32_t targetBusFreq = SD_CLOCK_25MHZ; + uint32_t targetTiming = 0U; + uint8_t temp = 0U; + uint32_t supportModeFlag = 0U; + + do + { + switch (card->currentTiming) + { + /* if not select timing mode, sdmmc will handle it automatically*/ + case kSD_TimingSDR12DefaultMode: + case kSD_TimingSDR104Mode: + if ((kSDMMCHOST_SupportSDR104 != SDMMCHOST_NOT_SUPPORT) && + ((card->cccrflags & SDIO_CCCR_SUPPORT_SDR104) == SDIO_CCCR_SUPPORT_SDR104)) + { + card->currentTiming = kSD_TimingSDR104Mode; + targetTiming = SDIO_CCCR_ENABLE_SDR104_MODE; + targetBusFreq = SDMMCHOST_SUPPORT_SDR104_FREQ; + supportModeFlag = SDIO_CCCR_SUPPORT_SDR104; + break; + } + + case kSD_TimingDDR50Mode: + if ((kSDMMCHOST_SupportDDR50 != SDMMCHOST_NOT_SUPPORT) && + ((card->cccrflags & SDIO_CCCR_SUPPORT_DDR50) == SDIO_CCCR_SUPPORT_DDR50)) + { + card->currentTiming = kSD_TimingDDR50Mode; + targetTiming = SDIO_CCCR_ENABLE_DDR50_MODE; + targetBusFreq = SD_CLOCK_50MHZ; + supportModeFlag = SDIO_CCCR_SUPPORT_DDR50; + break; + } + + case kSD_TimingSDR50Mode: + if ((kSDMMCHOST_SupportSDR50 != SDMMCHOST_NOT_SUPPORT) && + ((card->cccrflags & SDIO_CCCR_SUPPORT_SDR50) == SDIO_CCCR_SUPPORT_SDR50)) + { + card->currentTiming = kSD_TimingSDR50Mode; + targetTiming = SDIO_CCCR_ENABLE_SDR50_MODE; + targetBusFreq = SD_CLOCK_100MHZ; + supportModeFlag = SDIO_CCCR_SUPPORT_SDR50; + break; + } + + case kSD_TimingSDR25HighSpeedMode: + if ((card->host.capability.flags & kSDMMCHOST_SupportHighSpeed) && + (card->cccrflags & SDIO_CCCR_SUPPORT_HIGHSPEED) == SDIO_CCCR_SUPPORT_HIGHSPEED) + { + card->currentTiming = kSD_TimingSDR25HighSpeedMode; + targetTiming = SDIO_CCCR_ENABLE_HIGHSPEED_MODE; + targetBusFreq = SD_CLOCK_50MHZ; + supportModeFlag = SDIO_CCCR_SUPPORT_HIGHSPEED; + break; + } + + default: + /* default timing mode */ + card->currentTiming = kSD_TimingSDR12DefaultMode; + return kStatus_Success; + } + + if (kStatus_Success != SDIO_IO_RW_Direct(card, kSDIO_IORead, kSDIO_FunctionNum0, kSDIO_RegBusSpeed, 0U, &temp)) + { + return kStatus_SDMMC_TransferFailed; + } + + temp &= ~SDIO_CCCR_BUS_SPEED_MASK; + temp |= targetTiming; + + if (kStatus_Success != + SDIO_IO_RW_Direct(card, kSDIO_IOWrite, kSDIO_FunctionNum0, kSDIO_RegBusSpeed, temp, &temp)) + { + return kStatus_SDMMC_TransferFailed; + } + /* if cannot switch target timing, it will switch continuously until find a valid timing. */ + if ((temp & targetTiming) != targetTiming) + { + /* need add error log here */ + card->cccrflags &= ~supportModeFlag; + continue; + } + + break; + } while (1); + + card->busClock_Hz = SDMMCHOST_SET_CARD_CLOCK(card->host.base, card->host.sourceClock_Hz, targetBusFreq); + + /* enable DDR mode if it is the target mode */ + if (card->currentTiming == kSD_TimingDDR50Mode) + { + SDMMCHOST_ENABLE_DDR_MODE(card->host.base, true, 0U); + } + + /* SDR50 and SDR104 mode need tuning */ + if ((card->currentTiming == kSD_TimingSDR50Mode) || (card->currentTiming == kSD_TimingSDR104Mode)) + { + /* config IO strength in IOMUX*/ + if (card->currentTiming == kSD_TimingSDR50Mode) + { + SDMMCHOST_CONFIG_SD_IO(CARD_BUS_FREQ_100MHZ1, CARD_BUS_STRENGTH_7); + } + else + { + SDMMCHOST_CONFIG_SD_IO(CARD_BUS_FREQ_200MHZ, CARD_BUS_STRENGTH_7); + } + /* execute tuning */ + if (SDIO_ExecuteTuning(card) != kStatus_Success) + { + return kStatus_SDMMC_TuningFail; + } + } + else + { + /* set default IO strength to 4 to cover card adapter driver strength difference */ + SDMMCHOST_CONFIG_SD_IO(CARD_BUS_FREQ_100MHZ1, CARD_BUS_STRENGTH_4); + } + + return kStatus_Success; +} + +status_t SDIO_SetDriverStrength(sdio_card_t *card, sd_driver_strength_t driverStrength) +{ + uint8_t strength = 0U, temp = 0U; + + switch (driverStrength) + { + case kSD_DriverStrengthTypeA: + strength = SDIO_CCCR_ENABLE_DRIVER_TYPE_A; + break; + case kSD_DriverStrengthTypeC: + strength = SDIO_CCCR_ENABLE_DRIVER_TYPE_C; + break; + case kSD_DriverStrengthTypeD: + strength = SDIO_CCCR_ENABLE_DRIVER_TYPE_D; + break; + default: + strength = SDIO_CCCR_ENABLE_DRIVER_TYPE_B; + break; + } + + if (kStatus_Success != + SDIO_IO_RW_Direct(card, kSDIO_IORead, kSDIO_FunctionNum0, kSDIO_RegDriverStrength, 0U, &temp)) + { + return kStatus_SDMMC_TransferFailed; + } + + temp &= ~SDIO_CCCR_DRIVER_TYPE_MASK; + temp |= strength; + + return SDIO_IO_RW_Direct(card, kSDIO_IOWrite, kSDIO_FunctionNum0, kSDIO_RegDriverStrength, temp, &temp); +} + +status_t SDIO_EnableAsyncInterrupt(sdio_card_t *card, bool enable) +{ + assert(card); + + uint8_t eai = 0U; + + if ((card->cccrflags & SDIO_CCCR_SUPPORT_ASYNC_INT) == 0U) + { + return kStatus_SDMMC_NotSupportYet; + } + + /* load interrupt enable register */ + if (kStatus_Success != + SDIO_IO_RW_Direct(card, kSDIO_IORead, kSDIO_FunctionNum0, kSDIO_RegInterruptExtension, 0U, &eai)) + { + return kStatus_SDMMC_TransferFailed; + } + /* if already enable/disable , do not need enable/disable again */ + if (((eai)&SDIO_CCCR_ENABLE_AYNC_INT) == (enable ? SDIO_CCCR_ENABLE_AYNC_INT : 0U)) + { + return kStatus_Success; + } + + /* enable the eai */ + if (enable) + { + eai |= SDIO_CCCR_ENABLE_AYNC_INT; + } + else + { + eai &= ~(SDIO_CCCR_ENABLE_AYNC_INT); + } + + /* write to register */ + if (kStatus_Success != + SDIO_IO_RW_Direct(card, kSDIO_IOWrite, kSDIO_FunctionNum0, kSDIO_RegInterruptExtension, eai, &eai)) + { + return kStatus_SDMMC_TransferFailed; + } + + return kStatus_Success; +} + +static status_t SDIO_DecodeCIS( + sdio_card_t *card, sdio_func_num_t func, uint8_t *dataBuffer, uint32_t tplCode, uint32_t tplLink) +{ + assert(card); + assert(func <= kSDIO_FunctionNum7); + + if (func == kSDIO_FunctionNum0) + { + /* only decode MANIFID,FUNCID,FUNCE here */ + if (tplCode == SDIO_TPL_CODE_MANIFID) + { + card->commonCIS.mID = dataBuffer[0U] | (dataBuffer[1U] << 8U); + card->commonCIS.mInfo = dataBuffer[2U] | (dataBuffer[3U] << 8U); + } + else if (tplCode == SDIO_TPL_CODE_FUNCID) + { + card->commonCIS.funcID = dataBuffer[0U]; + } + else if (tplCode == SDIO_TPL_CODE_FUNCE) + { + /* max transfer block size and data size */ + card->commonCIS.fn0MaxBlkSize = dataBuffer[1U] | (dataBuffer[2U] << 8U); + /* max transfer speed */ + card->commonCIS.maxTransSpeed = dataBuffer[3U]; + } + else + { + /* reserved here */ + return kStatus_Fail; + } + } + else + { + /* only decode FUNCID,FUNCE here */ + if (tplCode == SDIO_TPL_CODE_FUNCID) + { + card->funcCIS[func].funcID = dataBuffer[0U]; + } + else if (tplCode == SDIO_TPL_CODE_FUNCE) + { + if (tplLink == 0x2A) + { + card->funcCIS[func - 1U].funcInfo = dataBuffer[1U]; + card->funcCIS[func - 1U].ioVersion = dataBuffer[2U]; + card->funcCIS[func - 1U].cardPSN = + dataBuffer[3U] | (dataBuffer[4U] << 8U) | (dataBuffer[5U] << 16U) | (dataBuffer[6U] << 24U); + card->funcCIS[func - 1U].ioCSASize = + dataBuffer[7U] | (dataBuffer[8U] << 8U) | (dataBuffer[9U] << 16U) | (dataBuffer[10U] << 24U); + card->funcCIS[func - 1U].ioCSAProperty = dataBuffer[11U]; + card->funcCIS[func - 1U].ioMaxBlockSize = dataBuffer[12U] | (dataBuffer[13U] << 8U); + card->funcCIS[func - 1U].ioOCR = + dataBuffer[14U] | (dataBuffer[15U] << 8U) | (dataBuffer[16U] << 16U) | (dataBuffer[17U] << 24U); + card->funcCIS[func - 1U].ioOPMinPwr = dataBuffer[18U]; + card->funcCIS[func - 1U].ioOPAvgPwr = dataBuffer[19U]; + card->funcCIS[func - 1U].ioOPMaxPwr = dataBuffer[20U]; + card->funcCIS[func - 1U].ioSBMinPwr = dataBuffer[21U]; + card->funcCIS[func - 1U].ioSBAvgPwr = dataBuffer[22U]; + card->funcCIS[func - 1U].ioSBMaxPwr = dataBuffer[23U]; + card->funcCIS[func - 1U].ioMinBandWidth = dataBuffer[24U] | (dataBuffer[25U] << 8U); + card->funcCIS[func - 1U].ioOptimumBandWidth = dataBuffer[26U] | (dataBuffer[27U] << 8U); + card->funcCIS[func - 1U].ioReadyTimeout = dataBuffer[28U] | (dataBuffer[29U] << 8U); + + card->funcCIS[func - 1U].ioHighCurrentAvgCurrent = dataBuffer[34U] | (dataBuffer[35U] << 8U); + card->funcCIS[func - 1U].ioHighCurrentMaxCurrent = dataBuffer[36U] | (dataBuffer[37U] << 8U); + card->funcCIS[func - 1U].ioLowCurrentAvgCurrent = dataBuffer[38U] | (dataBuffer[39U] << 8U); + card->funcCIS[func - 1U].ioLowCurrentMaxCurrent = dataBuffer[40U] | (dataBuffer[41U] << 8U); + } + else + { + return kStatus_Fail; + } + } + else + { + return kStatus_Fail; + } + } + + return kStatus_Success; +} + +status_t SDIO_ReadCIS(sdio_card_t *card, sdio_func_num_t func, const uint32_t *tupleList, uint32_t tupleNum) +{ + assert(card); + assert(func <= kSDIO_FunctionNum7); + assert(tupleList); + + uint8_t tplCode = 0U; + uint8_t tplLink = 0U; + uint32_t cisPtr = 0U; + uint32_t i = 0U, num = 0U; + bool tupleMatch = false; + + uint8_t dataBuffer[255U] = {0U}; + + /* get the CIS pointer for each function */ + if (func == kSDIO_FunctionNum0) + { + cisPtr = card->commonCISPointer; + } + else + { + cisPtr = card->ioFBR[func - 1U].ioPointerToCIS; + } + + if (0U == cisPtr) + { + return kStatus_SDMMC_SDIO_ReadCISFail; + } + + do + { + if (kStatus_Success != SDIO_IO_RW_Direct(card, kSDIO_IORead, kSDIO_FunctionNum0, cisPtr++, 0U, &tplCode)) + { + return kStatus_SDMMC_TransferFailed; + } + /* end of chain tuple */ + if (tplCode == 0xFFU) + { + break; + } + + if (tplCode == 0U) + { + continue; + } + + for (i = 0; i < tupleNum; i++) + { + if (tplCode == tupleList[i]) + { + tupleMatch = true; + break; + } + } + + if (kStatus_Success != SDIO_IO_RW_Direct(card, kSDIO_IORead, kSDIO_FunctionNum0, cisPtr++, 0U, &tplLink)) + { + return kStatus_SDMMC_TransferFailed; + } + /* end of chain tuple */ + if (tplLink == 0xFFU) + { + break; + } + + if (tupleMatch) + { + memset(dataBuffer, 0U, 255U); + for (i = 0; i < tplLink; i++) + { + if (kStatus_Success != + SDIO_IO_RW_Direct(card, kSDIO_IORead, kSDIO_FunctionNum0, cisPtr++, 0U, &dataBuffer[i])) + { + return kStatus_SDMMC_TransferFailed; + } + } + tupleMatch = false; + /* pharse the data */ + SDIO_DecodeCIS(card, func, dataBuffer, tplCode, tplLink); + /* read finish then return */ + if (++num == tupleNum) + { + break; + } + } + else + { + /* move pointer */ + cisPtr += tplLink; + /* tuple code not match,continue read tuple code */ + continue; + } + } while (1); + return kStatus_Success; +} + +static status_t SDIO_ProbeBusVoltage(sdio_card_t *card) +{ + assert(card); + + uint32_t ocr = 0U; + status_t error = kStatus_Success; + + /* application able to set the supported voltage window */ + if ((card->ocr & SDIO_OCR_VOLTAGE_WINDOW_MASK) != 0U) + { + ocr = card->ocr & SDIO_OCR_VOLTAGE_WINDOW_MASK; + } + else + { + /* 3.3V voltage should be supported as default */ + ocr |= SDMMC_MASK(kSD_OcrVdd29_30Flag) | SDMMC_MASK(kSD_OcrVdd32_33Flag) | SDMMC_MASK(kSD_OcrVdd33_34Flag); + } + + /* allow user select the work voltage, if not select, sdmmc will handle it automatically */ + if (kSDMMCHOST_SupportV180 != SDMMCHOST_NOT_SUPPORT) + { + ocr |= SDMMC_MASK(kSD_OcrSwitch18RequestFlag); + } + + do + { + /* card go idle */ + if (kStatus_Success != SDIO_GoIdle(card)) + { + return kStatus_SDMMC_GoIdleFailed; + } + + /* Get IO OCR-CMD5 with arg0 ,set new voltage if needed*/ + if (kStatus_Success != SDIO_SendOperationCondition(card, 0U)) + { + return kStatus_SDMMC_HandShakeOperationConditionFailed; + } + + if (kStatus_Success != SDIO_SendOperationCondition(card, ocr)) + { + return kStatus_SDMMC_InvalidVoltage; + } + + /* check if card support 1.8V */ + if ((card->ocr & SDMMC_MASK(kSD_OcrSwitch18AcceptFlag)) != 0U) + { + error = SDIO_SwitchVoltage(card); + if (kStatus_SDMMC_SwitchVoltageFail == error) + { + break; + } + + if (error == kStatus_SDMMC_SwitchVoltage18VFail33VSuccess) + { + ocr &= ~SDMMC_MASK(kSD_OcrSwitch18RequestFlag); + error = kStatus_Success; + continue; + } + else + { + card->operationVoltage = kCARD_OperationVoltage180V; + break; + } + } + + break; + } while (1U); + + return error; +} + +status_t SDIO_CardInit(sdio_card_t *card) +{ + assert(card); + + if (!card->isHostReady) + { + return kStatus_SDMMC_HostNotReady; + } + /* Identify mode ,set clock to 400KHZ. */ + card->busClock_Hz = SDMMCHOST_SET_CARD_CLOCK(card->host.base, card->host.sourceClock_Hz, SDMMC_CLOCK_400KHZ); + SDMMCHOST_SET_CARD_BUS_WIDTH(card->host.base, kSDMMCHOST_DATABUSWIDTH1BIT); + SDMMCHOST_SEND_CARD_ACTIVE(card->host.base, 100U); + + /* get host capability */ + GET_SDMMCHOST_CAPABILITY(card->host.base, &(card->host.capability)); + + if (SDIO_ProbeBusVoltage(card) != kStatus_Success) + { + return kStatus_SDMMC_SwitchVoltageFail; + } + + /* there is a memonly card */ + if ((card->ioTotalNumber == 0U) && (card->memPresentFlag)) + { + return kStatus_SDMMC_SDIO_InvalidCard; + } + + /* send relative address ,cmd3*/ + if (kStatus_Success != SDIO_SendRca(card)) + { + return kStatus_SDMMC_SendRelativeAddressFailed; + } + /* select card cmd7 */ + if (kStatus_Success != SDIO_SelectCard(card, true)) + { + return kStatus_SDMMC_SelectCardFailed; + } + + /* get card capability */ + if (kStatus_Success != SDIO_GetCardCapability(card, kSDIO_FunctionNum0)) + { + return kStatus_SDMMC_TransferFailed; + } + + /* read common CIS here */ + if (SDIO_ReadCIS(card, kSDIO_FunctionNum0, g_tupleList, SDIO_COMMON_CIS_TUPLE_NUM)) + { + return kStatus_SDMMC_SDIO_ReadCISFail; + } + + /* switch data bus width */ + if (kStatus_Success != SDIO_SetMaxDataBusWidth(card)) + { + return kStatus_SDMMC_SetDataBusWidthFailed; + } + + /* trying switch to card support timing mode. */ + if (kStatus_Success != SDIO_SelectBusTiming(card)) + { + return kStatus_SDMMC_SDIO_SwitchHighSpeedFail; + } + + return kStatus_Success; +} + +void SDIO_CardDeinit(sdio_card_t *card) +{ + assert(card); + + SDIO_CardReset(card); + SDIO_SelectCard(card, false); +} + +status_t SDIO_HostInit(sdio_card_t *card) +{ + assert(card); + + if ((!card->isHostReady) && SDMMCHOST_Init(&(card->host), (void *)(&(card->usrParam))) != kStatus_Success) + { + return kStatus_Fail; + } + + /* set the host status flag, after the card re-plug in, don't need init host again */ + card->isHostReady = true; + + SDMMCHOST_ENABLE_SDIO_INT(card->host.base); + + return kStatus_Success; +} + +void SDIO_HostDeinit(sdio_card_t *card) +{ + assert(card); + + SDMMCHOST_Deinit(&(card->host)); + + /* should re-init host */ + card->isHostReady = false; +} + +void SDIO_HostReset(SDMMCHOST_CONFIG *host) +{ + SDMMCHOST_Reset(host->base); +} + +status_t SDIO_WaitCardDetectStatus(SDMMCHOST_TYPE *hostBase, const sdmmchost_detect_card_t *cd, bool waitCardStatus) +{ + return SDMMCHOST_WaitCardDetectStatus(hostBase, cd, waitCardStatus); +} + +bool SDIO_IsCardPresent(sdio_card_t *card) +{ + return SDMMCHOST_IsCardPresent(); +} + +void SDIO_PowerOnCard(SDMMCHOST_TYPE *base, const sdmmchost_pwr_card_t *pwr) +{ + SDMMCHOST_PowerOnCard(base, pwr); +} + +void SDIO_PowerOffCard(SDMMCHOST_TYPE *base, const sdmmchost_pwr_card_t *pwr) +{ + SDMMCHOST_PowerOffCard(base, pwr); +} + +status_t SDIO_Init(sdio_card_t *card) +{ + assert(card); + assert(card->host.base); + + if (!card->isHostReady) + { + if (SDIO_HostInit(card) != kStatus_Success) + { + return kStatus_SDMMC_HostNotReady; + } + } + else + { + /* reset the host */ + SDIO_HostReset(&(card->host)); + } + /* power off card */ + SDIO_PowerOffCard(card->host.base, card->usrParam.pwr); + /* card detect */ + if (SDIO_WaitCardDetectStatus(card->host.base, card->usrParam.cd, true) != kStatus_Success) + { + return kStatus_SDMMC_CardDetectFailed; + } + /* power on card */ + SDIO_PowerOnCard(card->host.base, card->usrParam.pwr); + + return SDIO_CardInit(card); +} + +void SDIO_Deinit(sdio_card_t *card) +{ + assert(card); + + SDIO_CardDeinit(card); + SDIO_HostDeinit(card); +} + +status_t SDIO_EnableIOInterrupt(sdio_card_t *card, sdio_func_num_t func, bool enable) +{ + assert(card); + assert(func <= kSDIO_FunctionNum7); + + uint8_t intEn = 0U; + + /* load io interrupt enable register */ + if (kStatus_Success != SDIO_IO_RW_Direct(card, kSDIO_IORead, kSDIO_FunctionNum0, kSDIO_RegIOIntEnable, 0U, &intEn)) + { + return kStatus_SDMMC_TransferFailed; + } + + if (enable) + { + /* if already enable , do not need enable again */ + if ((((intEn >> func) & 0x01U) == 0x01U) && (intEn & 0x01U)) + { + return kStatus_Success; + } + + /* enable the interrupt and interrupt master */ + intEn |= (1U << func) | 0x01U; + card->ioIntNums++; + } + else + { + /* if already disable , do not need enable again */ + if (((intEn >> func) & 0x01U) == 0x00U) + { + return kStatus_Success; + } + + /* disable the interrupt, don't disable the interrupt master here */ + intEn &= ~(1U << func); + if (card->ioIntNums) + { + card->ioIntNums--; + } + } + + /* write to register */ + if (kStatus_Success != + SDIO_IO_RW_Direct(card, kSDIO_IOWrite, kSDIO_FunctionNum0, kSDIO_RegIOIntEnable, intEn, &intEn)) + { + return kStatus_SDMMC_TransferFailed; + } + + return kStatus_Success; +} + +status_t SDIO_GetPendingInterrupt(sdio_card_t *card, uint8_t *pendingInt) +{ + assert(card); + + /* load io interrupt enable register */ + + if (kStatus_Success != + SDIO_IO_RW_Direct(card, kSDIO_IORead, kSDIO_FunctionNum0, kSDIO_RegIOIntPending, 0U, pendingInt)) + { + return kStatus_SDMMC_TransferFailed; + } + + return kStatus_Success; +} + +status_t SDIO_EnableIO(sdio_card_t *card, sdio_func_num_t func, bool enable) +{ + assert(card); + assert(func <= kSDIO_FunctionNum7); + assert(func != kSDIO_FunctionNum0); + + uint8_t ioEn = 0U, ioReady = 0U; + volatile uint32_t i = SDIO_RETRY_TIMES; + uint32_t ioReadyTimeoutMS = card->funcCIS[func - 1U].ioReadyTimeout * SDIO_IO_READY_TIMEOUT_UNIT; + + if (ioReadyTimeoutMS != 0U) + { + /* do not poll the IO ready status, but use IO ready timeout */ + i = 1U; + } + + /* load io enable register */ + if (kStatus_Success != SDIO_IO_RW_Direct(card, kSDIO_IORead, kSDIO_FunctionNum0, kSDIO_RegIOEnable, 0U, &ioEn)) + { + return kStatus_SDMMC_TransferFailed; + } + /* if already enable/disable , do not need enable/disable again */ + if (((ioEn >> func) & 0x01U) == (enable ? 1U : 0U)) + { + return kStatus_Success; + } + + /* enable the io */ + if (enable) + { + ioEn |= (1U << func); + } + else + { + ioEn &= ~(1U << func); + } + + /* write to register */ + if (kStatus_Success != SDIO_IO_RW_Direct(card, kSDIO_IOWrite, kSDIO_FunctionNum0, kSDIO_RegIOEnable, ioEn, &ioEn)) + { + return kStatus_SDMMC_TransferFailed; + } + + /* if enable io, need check the IO ready status */ + if (enable) + { + do + { + SDMMCHOST_Delay(ioReadyTimeoutMS); + /* wait IO ready */ + if (kStatus_Success != + SDIO_IO_RW_Direct(card, kSDIO_IORead, kSDIO_FunctionNum0, kSDIO_RegIOReady, 0U, &ioReady)) + { + return kStatus_SDMMC_TransferFailed; + } + /* check if IO ready */ + if ((ioReady & (1 << func)) != 0U) + { + return kStatus_Success; + } + + i--; + } while (i); + + return kStatus_Fail; + } + + return kStatus_Success; +} + +status_t SDIO_SelectIO(sdio_card_t *card, sdio_func_num_t func) +{ + assert(card); + assert(func <= kSDIO_FunctionMemory); + + uint8_t ioSel = func; + + /* write to register */ + if (kStatus_Success != + SDIO_IO_RW_Direct(card, kSDIO_IOWrite, kSDIO_FunctionNum0, kSDIO_RegFunctionSelect, ioSel, &ioSel)) + { + return kStatus_SDMMC_TransferFailed; + } + + return kStatus_Success; +} + +status_t SDIO_AbortIO(sdio_card_t *card, sdio_func_num_t func) +{ + assert(card); + assert(func <= kSDIO_FunctionNum7); + + uint8_t ioAbort = func; + + /* write to register */ + if (kStatus_Success != + SDIO_IO_RW_Direct(card, kSDIO_IOWrite, kSDIO_FunctionNum0, kSDIO_RegIOAbort, ioAbort, &ioAbort)) + { + return kStatus_SDMMC_TransferFailed; + } + + return kStatus_Success; +} + +void SDIO_SetIOIRQHandler(sdio_card_t *card, sdio_func_num_t func, sdio_io_irq_handler_t handler) +{ + assert(card); + assert((func <= kSDIO_FunctionNum7) && (func != kSDIO_FunctionNum0)); + + card->ioIRQHandler[func - 1] = handler; + card->ioIntIndex = func; +} + +status_t SDIO_HandlePendingIOInterrupt(sdio_card_t *card) +{ + assert(card); + + uint8_t i = 0, pendingInt = 0; + + /* call IRQ handler directly if one IRQ handler only */ + if (card->ioIntNums == 1U) + { + if (card->ioIRQHandler[card->ioIntIndex - 1]) + { + (card->ioIRQHandler[card->ioIntIndex - 1])(card, card->ioIntIndex); + } + } + else + { + /* get pending int firstly */ + if (SDIO_GetPendingInterrupt(card, &pendingInt) != kStatus_Success) + { + return kStatus_SDMMC_TransferFailed; + } + + for (i = 1; i <= FSL_SDIO_MAX_IO_NUMS; i++) + { + if (pendingInt & (1 << i)) + { + if (card->ioIRQHandler[i - 1]) + { + (card->ioIRQHandler[i - 1])(card, i); + } + } + } + } + + return kStatus_Success; +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/src/fsl_sdmmc_common.c b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/src/fsl_sdmmc_common.c new file mode 100644 index 000000000..bffccc7bc --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/src/fsl_sdmmc_common.c @@ -0,0 +1,393 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_sdmmc_common.h" +/******************************************************************************* + * Variables + ******************************************************************************/ +SDK_ALIGN(uint32_t g_sdmmc[SDK_SIZEALIGN(SDMMC_GLOBAL_BUFFER_SIZE, SDMMC_DATA_BUFFER_ALIGN_CACHE)], + MAX(SDMMC_DATA_BUFFER_ALIGN_CACHE, SDMMCHOST_DMA_BUFFER_ADDR_ALIGN)); +/******************************************************************************* + * Code + ******************************************************************************/ +status_t SDMMC_SelectCard(SDMMCHOST_TYPE *base, + SDMMCHOST_TRANSFER_FUNCTION transfer, + uint32_t relativeAddress, + bool isSelected) +{ + assert(transfer); + + SDMMCHOST_TRANSFER content = {0}; + SDMMCHOST_COMMAND command = {0}; + + command.index = kSDMMC_SelectCard; + if (isSelected) + { + command.argument = relativeAddress << 16U; + command.responseType = kCARD_ResponseTypeR1; + } + else + { + command.argument = 0U; + command.responseType = kCARD_ResponseTypeNone; + } + + content.command = &command; + content.data = NULL; + if ((kStatus_Success != transfer(base, &content)) || (command.response[0U] & SDMMC_R1_ALL_ERROR_FLAG)) + { + return kStatus_SDMMC_TransferFailed; + } + + /* Wait until card to transfer state */ + return kStatus_Success; +} + +status_t SDMMC_SendApplicationCommand(SDMMCHOST_TYPE *base, + SDMMCHOST_TRANSFER_FUNCTION transfer, + uint32_t relativeAddress) +{ + assert(transfer); + + SDMMCHOST_TRANSFER content = {0}; + SDMMCHOST_COMMAND command = {0}; + + command.index = kSDMMC_ApplicationCommand; + command.argument = (relativeAddress << 16U); + command.responseType = kCARD_ResponseTypeR1; + + content.command = &command; + content.data = 0U; + if ((kStatus_Success != transfer(base, &content)) || (command.response[0U] & SDMMC_R1_ALL_ERROR_FLAG)) + { + return kStatus_SDMMC_TransferFailed; + } + + if (!(command.response[0U] & SDMMC_MASK(kSDMMC_R1ApplicationCommandFlag))) + { + return kStatus_SDMMC_CardNotSupport; + } + + return kStatus_Success; +} + +status_t SDMMC_SetBlockCount(SDMMCHOST_TYPE *base, SDMMCHOST_TRANSFER_FUNCTION transfer, uint32_t blockCount) +{ + assert(transfer); + + SDMMCHOST_TRANSFER content = {0}; + SDMMCHOST_COMMAND command = {0}; + + command.index = kSDMMC_SetBlockCount; + command.argument = blockCount; + command.responseType = kCARD_ResponseTypeR1; + + content.command = &command; + content.data = 0U; + if ((kStatus_Success != transfer(base, &content)) || (command.response[0U] & SDMMC_R1_ALL_ERROR_FLAG)) + { + return kStatus_SDMMC_TransferFailed; + } + + return kStatus_Success; +} + +status_t SDMMC_GoIdle(SDMMCHOST_TYPE *base, SDMMCHOST_TRANSFER_FUNCTION transfer) +{ + assert(transfer); + + SDMMCHOST_TRANSFER content = {0}; + SDMMCHOST_COMMAND command = {0}; + + command.index = kSDMMC_GoIdleState; + + content.command = &command; + content.data = 0U; + if (kStatus_Success != transfer(base, &content)) + { + return kStatus_SDMMC_TransferFailed; + } + + return kStatus_Success; +} + +status_t SDMMC_SetBlockSize(SDMMCHOST_TYPE *base, SDMMCHOST_TRANSFER_FUNCTION transfer, uint32_t blockSize) +{ + assert(transfer); + + SDMMCHOST_TRANSFER content = {0}; + SDMMCHOST_COMMAND command = {0}; + + command.index = kSDMMC_SetBlockLength; + command.argument = blockSize; + command.responseType = kCARD_ResponseTypeR1; + + content.command = &command; + content.data = 0U; + if ((kStatus_Success != transfer(base, &content)) || (command.response[0U] & SDMMC_R1_ALL_ERROR_FLAG)) + { + return kStatus_SDMMC_TransferFailed; + } + + return kStatus_Success; +} + +status_t SDMMC_SetCardInactive(SDMMCHOST_TYPE *base, SDMMCHOST_TRANSFER_FUNCTION transfer) +{ + assert(transfer); + + SDMMCHOST_TRANSFER content = {0}; + SDMMCHOST_COMMAND command = {0}; + + command.index = kSDMMC_GoInactiveState; + command.argument = 0U; + command.responseType = kCARD_ResponseTypeNone; + + content.command = &command; + content.data = 0U; + if ((kStatus_Success != transfer(base, &content))) + { + return kStatus_SDMMC_TransferFailed; + } + + return kStatus_Success; +} + +status_t SDMMC_SwitchVoltage(SDMMCHOST_TYPE *base, SDMMCHOST_TRANSFER_FUNCTION transfer) +{ + assert(transfer); + + SDMMCHOST_TRANSFER content = {0}; + SDMMCHOST_COMMAND command = {0}; + status_t error = kStatus_Success; + + if (kSDMMCHOST_SupportV180 != SDMMCHOST_NOT_SUPPORT) + { + command.index = kSD_VoltageSwitch; + command.argument = 0U; + command.responseType = kCARD_ResponseTypeR1; + + content.command = &command; + content.data = NULL; + if (kStatus_Success != transfer(base, &content)) + { + return kStatus_SDMMC_TransferFailed; + } + /* disable card clock */ + SDMMCHOST_ENABLE_CARD_CLOCK(base, false); + + /* check data line and cmd line status */ + if ((GET_SDMMCHOST_STATUS(base) & + (CARD_DATA1_STATUS_MASK | CARD_DATA2_STATUS_MASK | CARD_DATA3_STATUS_MASK | CARD_DATA0_NOT_BUSY)) != 0U) + { + return kStatus_SDMMC_SwitchVoltageFail; + } + + /* host switch to 1.8V */ + SDMMCHOST_SWITCH_VOLTAGE180V(base, true); + + SDMMCHOST_Delay(100U); + + /*enable sd clock*/ + SDMMCHOST_ENABLE_CARD_CLOCK(base, true); + /*enable force clock on*/ + SDMMCHOST_FORCE_SDCLOCK_ON(base, true); + /* dealy 1ms,not exactly correct when use while */ + SDMMCHOST_Delay(10U); + /*disable force clock on*/ + SDMMCHOST_FORCE_SDCLOCK_ON(base, false); + + /* check data line and cmd line status */ + if ((GET_SDMMCHOST_STATUS(base) & + (CARD_DATA1_STATUS_MASK | CARD_DATA2_STATUS_MASK | CARD_DATA3_STATUS_MASK | CARD_DATA0_NOT_BUSY)) == 0U) + { + error = kStatus_SDMMC_SwitchVoltageFail; + /* power reset the card */ + SDMMCHOST_ENABLE_SD_POWER(false); + SDMMCHOST_Delay(10U); + SDMMCHOST_ENABLE_SD_POWER(true); + SDMMCHOST_Delay(10U); + /* re-check the data line status */ + if ((GET_SDMMCHOST_STATUS(base) & + (CARD_DATA1_STATUS_MASK | CARD_DATA2_STATUS_MASK | CARD_DATA3_STATUS_MASK | CARD_DATA0_NOT_BUSY))) + { + error = kStatus_SDMMC_SwitchVoltage18VFail33VSuccess; + SDMMC_LOG( + "\r\nNote: Current card support 1.8V, but board don't support, so sdmmc switch back to 3.3V."); + } + else + { + SDMMC_LOG( + "\r\nError: Current card support 1.8V, but board don't support, sdmmc tried to switch back\ + to 3.3V, but failed, please check board setting."); + } + } + + return error; + } + else + { + return kStatus_SDMMC_HostNotSupport; + } +} + +status_t SDMMC_SwitchToVoltage(SDMMCHOST_TYPE *base, + SDMMCHOST_TRANSFER_FUNCTION transfer, + sdmmchost_card_switch_voltage_t switchVoltageFunc) +{ + assert(transfer); + + SDMMCHOST_TRANSFER content = {0}; + SDMMCHOST_COMMAND command = {0}; + status_t error = kStatus_Success; + + if (kSDMMCHOST_SupportV180 != SDMMCHOST_NOT_SUPPORT) + { + command.index = kSD_VoltageSwitch; + command.argument = 0U; + command.responseType = kCARD_ResponseTypeR1; + + content.command = &command; + content.data = NULL; + if (kStatus_Success != transfer(base, &content)) + { + return kStatus_SDMMC_TransferFailed; + } + /* disable card clock */ + SDMMCHOST_ENABLE_CARD_CLOCK(base, false); + + /* check data line and cmd line status */ + if ((GET_SDMMCHOST_STATUS(base) & + (CARD_DATA1_STATUS_MASK | CARD_DATA2_STATUS_MASK | CARD_DATA3_STATUS_MASK | CARD_DATA0_NOT_BUSY)) != 0U) + { + return kStatus_SDMMC_SwitchVoltageFail; + } + + if (switchVoltageFunc != NULL) + { + switchVoltageFunc(); + } + else + { + /* host switch to 1.8V */ + SDMMCHOST_SWITCH_VOLTAGE180V(base, true); + } + + SDMMCHOST_Delay(100U); + + /*enable sd clock*/ + SDMMCHOST_ENABLE_CARD_CLOCK(base, true); + /*enable force clock on*/ + SDMMCHOST_FORCE_SDCLOCK_ON(base, true); + /* dealy 1ms,not exactly correct when use while */ + SDMMCHOST_Delay(10U); + /*disable force clock on*/ + SDMMCHOST_FORCE_SDCLOCK_ON(base, false); + + /* check data line and cmd line status */ + if ((GET_SDMMCHOST_STATUS(base) & + (CARD_DATA1_STATUS_MASK | CARD_DATA2_STATUS_MASK | CARD_DATA3_STATUS_MASK | CARD_DATA0_NOT_BUSY)) == 0U) + { + error = kStatus_SDMMC_SwitchVoltageFail; + /* power reset the card */ + SDMMCHOST_ENABLE_SD_POWER(false); + SDMMCHOST_Delay(10U); + SDMMCHOST_ENABLE_SD_POWER(true); + SDMMCHOST_Delay(10U); + /* re-check the data line status */ + if ((GET_SDMMCHOST_STATUS(base) & + (CARD_DATA1_STATUS_MASK | CARD_DATA2_STATUS_MASK | CARD_DATA3_STATUS_MASK | CARD_DATA0_NOT_BUSY))) + { + error = kStatus_SDMMC_SwitchVoltage18VFail33VSuccess; + SDMMC_LOG( + "\r\nNote: Current card support 1.8V, but board don't support, so sdmmc switch back to 3.3V."); + } + else + { + SDMMC_LOG( + "\r\nError: Current card support 1.8V, but board don't support, sdmmc tried to switch back\ + to 3.3V, but failed, please check board setting."); + } + } + + return error; + } + else + { + return kStatus_SDMMC_HostNotSupport; + } +} + +status_t SDMMC_ExecuteTuning(SDMMCHOST_TYPE *base, + SDMMCHOST_TRANSFER_FUNCTION transfer, + uint32_t tuningCmd, + uint32_t blockSize) +{ + SDMMCHOST_TRANSFER content = {0U}; + SDMMCHOST_COMMAND command = {0U}; + SDMMCHOST_DATA data = {0U}; + uint32_t buffer[32U] = {0U}; + bool tuningError = true; + + command.index = tuningCmd; + command.argument = 0U; + command.responseType = kCARD_ResponseTypeR1; + + data.blockSize = blockSize; + data.blockCount = 1U; + data.rxData = buffer; + /* add this macro for adpter to different driver */ + SDMMCHOST_ENABLE_TUNING_FLAG(data); + + content.command = &command; + content.data = &data; + + /* enable the standard tuning */ + SDMMCHOST_EXECUTE_STANDARD_TUNING_ENABLE(base, true); + + while (true) + { + /* send tuning block */ + if ((kStatus_Success != transfer(base, &content))) + { + return kStatus_SDMMC_TransferFailed; + } + SDMMCHOST_Delay(1U); + + /*wait excute tuning bit clear*/ + if ((SDMMCHOST_EXECUTE_STANDARD_TUNING_STATUS(base) != 0U)) + { + continue; + } + + /* if tuning error , re-tuning again */ + if ((SDMMCHOST_CHECK_TUNING_ERROR(base) != 0U) && tuningError) + { + tuningError = false; + /* enable the standard tuning */ + SDMMCHOST_EXECUTE_STANDARD_TUNING_ENABLE(base, true); + SDMMCHOST_ADJUST_TUNING_DELAY(base, SDMMCHOST_STANDARD_TUNING_START); + } + else + { + break; + } + } + + /* check tuning result*/ + if (SDMMCHOST_EXECUTE_STANDARD_TUNING_RESULT(base) == 0U) + { + return kStatus_SDMMC_TuningFail; + } + +#if !SDMMC_ENABLE_SOFTWARE_TUNING + SDMMCHOST_AUTO_TUNING_ENABLE(base, true); +#endif + + return kStatus_Success; +} diff --git a/bsp/lpc55sxx/Libraries/drivers/SConscript b/bsp/lpc55sxx/Libraries/drivers/SConscript new file mode 100644 index 000000000..8becd8eba --- /dev/null +++ b/bsp/lpc55sxx/Libraries/drivers/SConscript @@ -0,0 +1,50 @@ +from building import * + +cwd = GetCurrentDir() + +src = [] + +if GetDepend('BSP_USING_PIN'): + src += ['drv_pin.c'] + +if GetDepend('BSP_USING_LED'): + src += ['drv_led.c'] + +if GetDepend('BSP_USING_KEY'): + src += ['drv_key.c'] + +if GetDepend('BSP_USING_UART'): + src += ['drv_uart.c'] + +if GetDepend('BSP_USING_RTC'): + src += ['drv_rtc.c'] + +if GetDepend('BSP_USING_SPI'): + src += ['drv_spi.c'] + +if GetDepend('BSP_USING_SDIO'): + src += ['drv_sd.c'] + +if GetDepend('BSP_USING_I2C'): + src += ['drv_i2c.c'] + +if GetDepend('BSP_USING_MMA8562I2C'): + src += ['drv_mma8562.c'] + +if GetDepend('BSP_USING_ADC'): + src += ['drv_adc.c'] + +if GetDepend('BSP_USING_HWTIMER'): + src += ['drv_hwtimer.c'] + +if GetDepend('BSP_USING_WDT'): + src += ['drv_wdt.c'] + +if GetDepend('BSP_USING_PWM'): + src += ['drv_pwm.c'] + +path = [cwd,cwd + '/config'] + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path) + +Return('group') diff --git a/bsp/lpc55sxx/Libraries/drivers/drv_adc.c b/bsp/lpc55sxx/Libraries/drivers/drv_adc.c new file mode 100644 index 000000000..e1f79c242 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/drivers/drv_adc.c @@ -0,0 +1,110 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-04-20 tyustli the first version. + * 2019-07-15 Magicoe The first version for LPC55S6x + * + */ +#include + +#ifdef BSP_USING_ADC + +#if !defined(BSP_USING_ADC0_CH0) +#error "Please define at least one BSP_USING_ADCx_CH0" +#endif + +#define LOG_TAG "drv.adc" +#include +#include "drv_adc.h" +#include "fsl_power.h" +#include "fsl_lpadc.h" +#include + +static rt_err_t lpc_lpadc_enabled(struct rt_adc_device *device, rt_uint32_t channel, rt_bool_t enabled) +{ + return RT_EOK; +} + +static rt_err_t lpc_lpadc_convert(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value) +{ + lpadc_conv_trigger_config_t mLpadcTriggerConfigStruct; + lpadc_conv_command_config_t mLpadcCommandConfigStruct; + lpadc_conv_result_t mLpadcResultConfigStruct; + + ADC_Type *base; + base = (ADC_Type *)(device->parent.user_data); + + /* Set conversion CMD configuration. */ + LPADC_GetDefaultConvCommandConfig(&mLpadcCommandConfigStruct); + mLpadcCommandConfigStruct.channelNumber = channel; + LPADC_SetConvCommandConfig(base, 1U, &mLpadcCommandConfigStruct); + + /* Set trigger configuration. */ + LPADC_GetDefaultConvTriggerConfig(&mLpadcTriggerConfigStruct); + mLpadcTriggerConfigStruct.targetCommandId = 1U; + mLpadcTriggerConfigStruct.enableHardwareTrigger = false; + LPADC_SetConvTriggerConfig(base, 0U, &mLpadcTriggerConfigStruct); /* Configurate the trigger0. */ + + LPADC_DoSoftwareTrigger(base, 1U); /* 1U is trigger0 mask. */ + while (!LPADC_GetConvResult(base, &mLpadcResultConfigStruct, 0U)); + + *value = ((mLpadcResultConfigStruct.convValue) >> 3U); + + return RT_EOK; +} + +static struct rt_adc_ops lpc_adc_ops = +{ + .enabled = lpc_lpadc_enabled, + .convert = lpc_lpadc_convert, +}; + +#if defined(BSP_USING_ADC0_CH0) +static struct rt_adc_device adc0_device; +#endif /* BSP_USING_ADC0_CH0 */ + + +int rt_hw_adc_init(void) +{ + int result = RT_EOK; + +#if defined(BSP_USING_ADC0_CH0) + lpadc_config_t mLpadcConfigStruct; + + CLOCK_SetClkDiv(kCLOCK_DivAdcAsyncClk, 16U, true); + CLOCK_AttachClk(kMAIN_CLK_to_ADC_CLK); + /* Disable LDOGPADC power down */ + POWER_DisablePD(kPDRUNCFG_PD_LDOGPADC); + + LPADC_GetDefaultConfig(&mLpadcConfigStruct); + mLpadcConfigStruct.enableAnalogPreliminary = true; + mLpadcConfigStruct.referenceVoltageSource = kLPADC_ReferenceVoltageAlt2; + mLpadcConfigStruct.conversionAverageMode = kLPADC_ConversionAverage128; + LPADC_Init(ADC0, &mLpadcConfigStruct); + + /* Request offset calibration. */ + //LPADC_DoOffsetCalibration(ADC0); + LPADC_SetOffsetValue(ADC0, 10U, 10U); + /* Request gain calibration. */ + LPADC_DoAutoCalibration(ADC0); + + result = rt_hw_adc_register(&adc0_device, "adc0", &lpc_adc_ops, ADC0); + + if (result != RT_EOK) + { + LOG_E("register adc0 device failed error code = %d\n", result); + } + +#endif /* BSP_USING_ADC0_CH0 */ + + return result; +} + +INIT_DEVICE_EXPORT(rt_hw_adc_init); + +#endif /* BSP_USING_ADC */ + diff --git a/bsp/lpc55sxx/Libraries/drivers/drv_adc.h b/bsp/lpc55sxx/Libraries/drivers/drv_adc.h new file mode 100644 index 000000000..0113b54f3 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/drivers/drv_adc.h @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-04-20 Lee the first version. + */ + +#ifndef DRV_ADC_H__ +#define DRV_ADC_H__ +#include + +int rt_hw_adc_init(void); + +#endif /* DRV_ADC_H__ */ + diff --git a/bsp/lpc55sxx/Libraries/drivers/drv_hwtimer.c b/bsp/lpc55sxx/Libraries/drivers/drv_hwtimer.c new file mode 100644 index 000000000..bbaf2d670 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/drivers/drv_hwtimer.c @@ -0,0 +1,321 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-04-17 WangBing the first version. + * 2019-04-22 tyustli add imxrt series support + * 2019-07-15 Magicoe The first version for LPC55S6x + * +*/ +#include + +#ifdef BSP_USING_HWTIMER + +#define LOG_TAG "drv.hwtimer" +#include + +#include +#include "drv_hwtimer.h" +#include "fsl_ctimer.h" + + +static void NVIC_Configuration(void) +{ +#ifdef BSP_USING_CTIMER0 + EnableIRQ(CTIMER0_IRQn); +#endif + +#ifdef BSP_USING_CTIMER1 + EnableIRQ(CTIMER1_IRQn); +#endif + +#ifdef BSP_USING_CTIMER2 + EnableIRQ(CTIMER2_IRQn); +#endif + +#ifdef BSP_USING_CTIMER3 + EnableIRQ(CTIMER3_IRQn); +#endif + +#ifdef BSP_USING_CTIMER4 + EnableIRQ(CTIMER4_IRQn); +#endif +} + +static rt_err_t lpc_ctimer_control(rt_hwtimer_t *timer, rt_uint32_t cmd, void *args) +{ + rt_err_t err = RT_EOK; + CTIMER_Type *hwtimer_dev; + hwtimer_dev = (CTIMER_Type *)timer->parent.user_data; + + RT_ASSERT(timer != RT_NULL); + + switch (cmd) + { + case HWTIMER_CTRL_FREQ_SET: + { + uint32_t clk; + uint32_t pre; + if(hwtimer_dev == CTIMER0) clk = CLOCK_GetFreq(kCLOCK_CTimer0); + if(hwtimer_dev == CTIMER1) clk = CLOCK_GetFreq(kCLOCK_CTimer1); + if(hwtimer_dev == CTIMER2) clk = CLOCK_GetFreq(kCLOCK_CTimer2); + if(hwtimer_dev == CTIMER3) clk = CLOCK_GetFreq(kCLOCK_CTimer3); + if(hwtimer_dev == CTIMER4) clk = CLOCK_GetFreq(kCLOCK_CTimer4); + + pre = clk / *((uint32_t *)args) - 1; + + hwtimer_dev->PR = pre; + } + break; + default: + err = -RT_ENOSYS; + break; + } + return err; +} + +static rt_uint32_t lpc_ctimer_count_get(rt_hwtimer_t *timer) +{ + rt_uint32_t CurrentTimer_Count; + CTIMER_Type *hwtimer_dev; + hwtimer_dev = (CTIMER_Type *)timer->parent.user_data; + + RT_ASSERT(timer != RT_NULL); + + CurrentTimer_Count = hwtimer_dev->TC; + + return CurrentTimer_Count; +} + +static void lpc_ctimer_init(rt_hwtimer_t *timer, rt_uint32_t state) +{ + CTIMER_Type *hwtimer_dev; + ctimer_config_t cfg; + hwtimer_dev = (CTIMER_Type *)timer->parent.user_data; + + RT_ASSERT(timer != RT_NULL); + + /* Use Main clock for some of the Ctimers */ + if(hwtimer_dev == CTIMER0) CLOCK_AttachClk(kMAIN_CLK_to_CTIMER0); + if(hwtimer_dev == CTIMER1) CLOCK_AttachClk(kMAIN_CLK_to_CTIMER1); + if(hwtimer_dev == CTIMER2) CLOCK_AttachClk(kMAIN_CLK_to_CTIMER2); + if(hwtimer_dev == CTIMER3) CLOCK_AttachClk(kMAIN_CLK_to_CTIMER3); + if(hwtimer_dev == CTIMER4) CLOCK_AttachClk(kMAIN_CLK_to_CTIMER4); + + CTIMER_Deinit(hwtimer_dev); + + if (state == 1) + { + NVIC_Configuration(); + CTIMER_GetDefaultConfig(&cfg); + CTIMER_Init(hwtimer_dev, &cfg); + } +} + +static rt_err_t lpc_ctimer_start(rt_hwtimer_t *timer, rt_uint32_t cnt, rt_hwtimer_mode_t mode) +{ + CTIMER_Type *hwtimer_dev; + hwtimer_dev = (CTIMER_Type *)timer->parent.user_data; + /* Match Configuration for Channel 0 */ + ctimer_match_config_t matchCfg; + + RT_ASSERT(timer != RT_NULL); + + /* Configuration*/ + matchCfg.enableCounterReset = true; + matchCfg.enableCounterStop = (mode == HWTIMER_MODE_ONESHOT) ? true : false;; + matchCfg.matchValue = cnt; + matchCfg.outControl = kCTIMER_Output_NoAction; + matchCfg.outPinInitState = false; + matchCfg.enableInterrupt = true; + + CTIMER_SetupMatch(hwtimer_dev, kCTIMER_Match_1, &matchCfg); + + NVIC_Configuration(); + + CTIMER_StartTimer(hwtimer_dev); + + return RT_EOK; +} + +static void lpc_ctimer_stop(rt_hwtimer_t *timer) +{ + CTIMER_Type *hwtimer_dev; + hwtimer_dev = (CTIMER_Type *)timer->parent.user_data; + + RT_ASSERT(timer != RT_NULL); + + CTIMER_StopTimer(hwtimer_dev); +} + +static const struct rt_hwtimer_ops lpc_hwtimer_ops = +{ + .init = lpc_ctimer_init, + .start = lpc_ctimer_start, + .stop = lpc_ctimer_stop, + .count_get = lpc_ctimer_count_get, + .control = lpc_ctimer_control, +}; + +static const struct rt_hwtimer_info lpc_hwtimer_info = +{ + 25000000, /* the maximum count frequency can be set */ + 6103, /* the minimum count frequency can be set */ + 0xFFFFFFFF, + HWTIMER_CNTMODE_UP, +}; + +#ifdef BSP_USING_CTIMER0 +static rt_hwtimer_t CTimer0; +#endif /* BSP_USING_HWTIMER0 */ + +#ifdef BSP_USING_CTIMER1 +static rt_hwtimer_t CTimer1; +#endif /* BSP_USING_HWTIMER1 */ + +#ifdef BSP_USING_CTIMER2 +static rt_hwtimer_t CTimer2; +#endif /* BSP_USING_HWTIMER2 */ + +#ifdef BSP_USING_CTIMER3 +static rt_hwtimer_t CTimer3; +#endif /* BSP_USING_HWTIMER3 */ + +#ifdef BSP_USING_CTIMER4 +static rt_hwtimer_t CTimer4; +#endif /* BSP_USING_HWTIMER4 */ + +int rt_hw_hwtimer_init(void) +{ + int ret = RT_EOK; + +#ifdef BSP_USING_CTIMER0 + CTimer0.info = &lpc_hwtimer_info; + CTimer0.ops = &lpc_hwtimer_ops; + ret = rt_device_hwtimer_register(&CTimer0, "ctimer0", CTIMER0); + + if (ret != RT_EOK) + { + LOG_E("CTIMER0 register failed\n"); + } +#endif + +#ifdef BSP_USING_CTIMER1 + CTimer1.info = &lpc_hwtimer_info; + CTimer1.ops = &lpc_hwtimer_ops; + ret = rt_device_hwtimer_register(&CTimer1, "ctimer1", CTIMER1); + + if (ret != RT_EOK) + { + LOG_E("CTIMER1 register failed\n"); + } +#endif + +#ifdef BSP_USING_CTIMER2 + CTimer2.info = &lpc_hwtimer_info; + CTimer2.ops = &lpc_hwtimer_ops; + ret = rt_device_hwtimer_register(&CTimer2, "ctimer2", CTIMER2); + + if (ret != RT_EOK) + { + LOG_E("CTIMER2 register failed\n"); + } +#endif + +#ifdef BSP_USING_CTIMER3 + CTimer3.info = &lpc_hwtimer_info; + CTimer3.ops = &lpc_hwtimer_ops; + ret = rt_device_hwtimer_register(&CTimer3, "ctimer3", CTIMER3); + + if (ret != RT_EOK) + { + LOG_E("CTIMER3 register failed\n"); + } +#endif + +#ifdef BSP_USING_CTIMER4 + CTimer4.info = &lpc_hwtimer_info; + CTimer4.ops = &lpc_hwtimer_ops; + ret = rt_device_hwtimer_register(&CTimer4, "ctimer4", CTIMER4); + + if (ret != RT_EOK) + { + LOG_E("CTIMER4 register failed\n"); + } +#endif + + return ret; +} + +INIT_DEVICE_EXPORT(rt_hw_hwtimer_init); + +#ifdef BSP_USING_CTIMER0 +void CTIMER0_IRQHandler(void) +{ + uint32_t int_stat; + /* Get Interrupt status flags */ + int_stat = CTIMER_GetStatusFlags(CTIMER0); + /* Clear the status flags that were set */ + CTIMER_ClearStatusFlags(CTIMER0, int_stat); + rt_device_hwtimer_isr(&CTimer0); + +} +#endif /* BSP_USING_HWTIMER0 */ + +#ifdef BSP_USING_CTIMER1 +void CTIMER1_IRQHandler(void) +{ + uint32_t int_stat; + /* Get Interrupt status flags */ + int_stat = CTIMER_GetStatusFlags(CTIMER1); + /* Clear the status flags that were set */ + CTIMER_ClearStatusFlags(CTIMER1, int_stat); + rt_device_hwtimer_isr(&CTimer1); + +} +#endif /* BSP_USING_HWTIMER1 */ + +#ifdef BSP_USING_CTIMER2 +void CTIMER2_IRQHandler(void) +{ + uint32_t int_stat; + /* Get Interrupt status flags */ + int_stat = CTIMER_GetStatusFlags(CTIMER2); + /* Clear the status flags that were set */ + CTIMER_ClearStatusFlags(CTIMER2, int_stat); + rt_device_hwtimer_isr(&CTimer2); + +} +#endif /* BSP_USING_HWTIMER2 */ + +#ifdef BSP_USING_CTIMER3 +void CTIMER3_IRQHandler(void) +{ + uint32_t int_stat; + /* Get Interrupt status flags */ + int_stat = CTIMER_GetStatusFlags(CTIMER3); + /* Clear the status flags that were set */ + CTIMER_ClearStatusFlags(CTIMER3, int_stat); + rt_device_hwtimer_isr(&CTimer3); + +} +#endif /* BSP_USING_HWTIMER3 */ + +#ifdef BSP_USING_CTIMER4 +void CTIMER4_IRQHandler(void) +{ + uint32_t int_stat; + /* Get Interrupt status flags */ + int_stat = CTIMER_GetStatusFlags(CTIMER4); + /* Clear the status flags that were set */ + CTIMER_ClearStatusFlags(CTIMER4, int_stat); + rt_device_hwtimer_isr(&CTimer4); + +} +#endif /* BSP_USING_HWTIMER4 */ + + +#endif /* BSP_USING_HWTIMER */ diff --git a/bsp/lpc55sxx/Libraries/drivers/drv_hwtimer.h b/bsp/lpc55sxx/Libraries/drivers/drv_hwtimer.h new file mode 100644 index 000000000..441665c6e --- /dev/null +++ b/bsp/lpc55sxx/Libraries/drivers/drv_hwtimer.h @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * +* Change Logs: +* Date Author Notes +* 2018-04-17 WangBing the first version. +*/ + +#ifndef DRV_HWTIMER_H__ +#define DRV_HWTIMER_H__ + +#include +#include + +int rt_hw_wdt_init(void); + +#endif + diff --git a/bsp/lpc55sxx/Libraries/drivers/drv_i2c.c b/bsp/lpc55sxx/Libraries/drivers/drv_i2c.c new file mode 100644 index 000000000..45273f155 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/drivers/drv_i2c.c @@ -0,0 +1,144 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-07-15 Magicoe The first version for LPC55S6x + */ + +#include +#include +#include "board.h" +#include "fsl_iocon.h" +#include "fsl_gpio.h" +#include "fsl_i2c.h" + +#ifdef RT_USING_I2C + +struct lpc_i2c_bus +{ + struct rt_i2c_bus_device parent; + I2C_Type *I2C; + char *device_name; +}; + +static rt_size_t lpc_i2c_xfer(struct rt_i2c_bus_device *bus, + struct rt_i2c_msg msgs[], rt_uint32_t num) +{ + struct rt_i2c_msg *msg; + i2c_master_transfer_t xfer = {0}; + rt_uint32_t i; + rt_err_t ret = RT_ERROR; + + struct lpc_i2c_bus *lpc_i2c = (struct lpc_i2c_bus *)bus; + + for (i = 0; i < num; i++) + { + msg = &msgs[i]; + + if (msg->flags & RT_I2C_RD) + { + xfer.slaveAddress = msg->addr; + xfer.direction = kI2C_Read; + xfer.subaddress = 0; + xfer.subaddressSize = 0; + xfer.data = msg->buf; + xfer.dataSize = msg->len; + if(i != 0) + xfer.flags = kI2C_TransferRepeatedStartFlag; + else + xfer.flags = kI2C_TransferDefaultFlag; + + if (I2C_MasterTransferBlocking(lpc_i2c->I2C, &xfer) != kStatus_Success) + { + i2c_dbg("i2c bus write failed,i2c bus stop!\n"); + goto out; + } + } + else + { + xfer.slaveAddress = msg->addr; + xfer.direction = kI2C_Write; + xfer.subaddress = 0; + xfer.subaddressSize = 0; + xfer.data = msg->buf; + xfer.dataSize = msg->len; + if(i == 0) + xfer.flags = kI2C_TransferNoStopFlag; + else + xfer.flags = kI2C_TransferDefaultFlag; + + if (I2C_MasterTransferBlocking(lpc_i2c->I2C, &xfer) != kStatus_Success) + { + i2c_dbg("i2c bus write failed,i2c bus stop!\n"); + goto out; + } + } + } + ret = i; + +out: + i2c_dbg("send stop condition\n"); + + return ret; +} + +static const struct rt_i2c_bus_device_ops i2c_ops = +{ + + lpc_i2c_xfer, + RT_NULL, + RT_NULL +}; + +int rt_hw_i2c_init(void) +{ + i2c_master_config_t masterConfig; +#ifdef BSP_USING_I2C1 + static struct lpc_i2c_bus lpc_i2c1; + /* attach 12 MHz clock to FLEXCOMM2 (I2C master for touch controller) */ + CLOCK_AttachClk(kFRO12M_to_FLEXCOMM1); + + I2C_MasterGetDefaultConfig(&masterConfig); + + /* Change the default baudrate configuration */ + masterConfig.baudRate_Bps = 100000U; + + /* Initialize the I2C master peripheral */ + I2C_MasterInit(I2C1, &masterConfig, 12000000); + + rt_memset((void *)&lpc_i2c1, 0, sizeof(struct lpc_i2c_bus)); + lpc_i2c1.parent.ops = &i2c_ops; + lpc_i2c1.I2C = I2C1; + lpc_i2c1.device_name = "LPC Flexcomm1 as I2C"; + rt_i2c_bus_device_register(&lpc_i2c1.parent, "i2c1"); +#endif /* BSP_USING_I2C1 */ + +#ifdef BSP_USING_I2C4 + static struct lpc_i2c_bus lpc_i2c4; + /* attach 12 MHz clock to FLEXCOMM2 (I2C master for touch controller) */ + CLOCK_AttachClk(kFRO12M_to_FLEXCOMM4); + + I2C_MasterGetDefaultConfig(&masterConfig); + + /* Change the default baudrate configuration */ + masterConfig.baudRate_Bps = 100000U; + + /* Initialize the I2C master peripheral */ + I2C_MasterInit(I2C4, &masterConfig, 12000000); + + rt_memset((void *)&lpc_i2c4, 0, sizeof(struct lpc_i2c_bus)); + lpc_i2c4.parent.ops = &i2c_ops; + lpc_i2c4.I2C = I2C4; + lpc_i2c4.device_name = "LPC Flexcomm4 as I2C"; + rt_i2c_bus_device_register(&lpc_i2c4.parent, BSP_USING_MMA8562I2C); + +#endif /* BSP_USING_I2C4 */ + + return 0; +} +INIT_DEVICE_EXPORT(rt_hw_i2c_init); + +#endif /* RT_USING_I2C */ diff --git a/bsp/lpc55sxx/Libraries/drivers/drv_i2c.h b/bsp/lpc55sxx/Libraries/drivers/drv_i2c.h new file mode 100644 index 000000000..ac303c736 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/drivers/drv_i2c.h @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-03-15 Liuguang the first version. + * 2019-07-19 Magicoe The first version for LPC55S6x + */ + +#ifndef __DRV_RTC_H__ +#define __DRV_RTC_H__ + +#include +#include + +extern int rt_hw_i2c_init(void); + +#endif diff --git a/bsp/lpc55sxx/Libraries/drivers/drv_key.c b/bsp/lpc55sxx/Libraries/drivers/drv_key.c new file mode 100644 index 000000000..3f8188feb --- /dev/null +++ b/bsp/lpc55sxx/Libraries/drivers/drv_key.c @@ -0,0 +1,168 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-07-19 Magicoe The first version for LPC55S6x, refered github.com/Guozhanxin/RTT-BeepPlayer-pkg + */ + +#include + +#include "rtconfig.h" + +#include "fsl_common.h" +#include "fsl_iocon.h" +#include "fsl_gpio.h" +#include "fsl_inputmux.h" +#include "drv_key.h" + +/**** Debug ****/ +#define DBG_ENABLE +#define DBG_SECTION_NAME "button" +#define DBG_LEVEL DBG_INFO +#define DBG_COLOR +#include + +#define MY_BUTTON_CALL(func, argv) \ + do { if ((func) != RT_NULL) func argv; } while (0) + +struct my_button_manage +{ + rt_uint8_t num; + rt_timer_t timer; + struct my_button *button_list[MY_BUTTON_LIST_MAX]; +}; + +static struct my_button_manage button_manage; + +int my_button_register(struct my_button *button) +{ + if (button->press_logic_level == 0) + { + rt_pin_mode(button->pin, PIN_MODE_INPUT_PULLUP); + } + else + { + rt_pin_mode(button->pin, PIN_MODE_INPUT_PULLDOWN); + } + + button->cnt = 0; + button->event = BUTTON_EVENT_NONE; + button_manage.button_list[button_manage.num++] = button; + + return 0; +} + +static void my_button_scan(void *param) +{ + rt_uint8_t i; + rt_uint16_t cnt_old; + + for (i = 0; i < button_manage.num; i++) + { + cnt_old = button_manage.button_list[i]->cnt; + + if (rt_pin_read(button_manage.button_list[i]->pin) == button_manage.button_list[i]->press_logic_level) + { + button_manage.button_list[i]->cnt ++; + + if (button_manage.button_list[i]->cnt == MY_BUTTON_DOWN_MS / MY_BUTTON_SCAN_SPACE_MS) /* BUTTON_DOWN */ + { + LOG_D("BUTTON_DOWN"); + button_manage.button_list[i]->event = BUTTON_EVENT_CLICK_DOWN; + MY_BUTTON_CALL(button_manage.button_list[i]->cb, (button_manage.button_list[i])); + } + else if (button_manage.button_list[i]->cnt == MY_BUTTON_HOLD_MS / MY_BUTTON_SCAN_SPACE_MS) /* BUTTON_HOLD */ + { + LOG_D("BUTTON_HOLD"); + button_manage.button_list[i]->event = BUTTON_EVENT_HOLD; + MY_BUTTON_CALL(button_manage.button_list[i]->cb, (button_manage.button_list[i])); + } + else if (button_manage.button_list[i]->cnt > MY_BUTTON_HOLD_MS / MY_BUTTON_SCAN_SPACE_MS) /* BUTTON_HOLD_CYC */ + { + LOG_D("BUTTON_HOLD_CYC"); + button_manage.button_list[i]->event = BUTTON_EVENT_HOLD_CYC; + if (button_manage.button_list[i]->hold_cyc_period && button_manage.button_list[i]->cnt % (button_manage.button_list[i]->hold_cyc_period / MY_BUTTON_SCAN_SPACE_MS) == 0) + MY_BUTTON_CALL(button_manage.button_list[i]->cb, (button_manage.button_list[i])); + } + } + else + { + button_manage.button_list[i]->cnt = 0; + if (cnt_old >= MY_BUTTON_DOWN_MS / MY_BUTTON_SCAN_SPACE_MS && cnt_old < MY_BUTTON_HOLD_MS / MY_BUTTON_SCAN_SPACE_MS) /* BUTTON_CLICK_UP */ + { + LOG_D("BUTTON_CLICK_UP"); + button_manage.button_list[i]->event = BUTTON_EVENT_CLICK_UP; + MY_BUTTON_CALL(button_manage.button_list[i]->cb, (button_manage.button_list[i])); + } + else if (cnt_old >= MY_BUTTON_HOLD_MS / MY_BUTTON_SCAN_SPACE_MS) /* BUTTON_HOLD_UP */ + { + LOG_D("BUTTON_HOLD_UP"); + button_manage.button_list[i]->event = BUTTON_EVENT_HOLD_UP; + MY_BUTTON_CALL(button_manage.button_list[i]->cb, (button_manage.button_list[i])); + } + } + } +} + +int my_button_start(void) +{ + if (button_manage.timer != RT_NULL) + return -1; + + /* Create Timer 1 */ + button_manage.timer = rt_timer_create("timer1", /* Timer name is: timer1 */ + my_button_scan, /* Timeout callback func */ + RT_NULL, /* Timeout func entry */ + RT_TICK_PER_SECOND * MY_BUTTON_SCAN_SPACE_MS / 1000, + RT_TIMER_FLAG_PERIODIC | RT_TIMER_FLAG_SOFT_TIMER); + /* Start Timer */ + if (button_manage.timer != RT_NULL) + rt_timer_start(button_manage.timer); + + return 0; +} + +#ifdef RT_USING_FINSH +#include + +#ifdef FINSH_USING_MSH + +#define KEY_PIN 51 +#define KEY_PRESS_VALUE 0 + +void key_cb(struct my_button *button) +{ + switch (button->event) + { + case BUTTON_EVENT_CLICK_UP: + rt_kprintf("This is click up callback!\n"); + break; + case BUTTON_EVENT_HOLD_CYC: + rt_kprintf("This is hold cyc callback!\n"); + break; + default: + ; + } +} + +void key_test(rt_uint32_t led_num, rt_uint32_t value) +{ + /* user app entry */ + static struct my_button key = {0}; + + key.press_logic_level = KEY_PRESS_VALUE; + key.hold_cyc_period = 100; + key.cb = (my_button_callback)key_cb; + key.pin = KEY_PIN; + + my_button_register(&key); + + my_button_start(); +} +MSH_CMD_EXPORT(key_test, key_test); + +#endif /* FINSH_USING_MSH */ +#endif /* RT_USING_FINSH */ diff --git a/bsp/lpc55sxx/Libraries/drivers/drv_key.h b/bsp/lpc55sxx/Libraries/drivers/drv_key.h new file mode 100644 index 000000000..b0fb9d409 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/drivers/drv_key.h @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-07-19 Magicoe The first version for LPC55S6x, refered github.com/Guozhanxin/RTT-BeepPlayer-pkg + */ + +#ifndef __DRV_KEY_H__ +#define __DRV_KEY_H__ + +#include +#include + +#define MY_BUTTON_DOWN_MS 50 +#define MY_BUTTON_HOLD_MS 700 + +#define MY_BUTTON_SCAN_SPACE_MS 20 +#define MY_BUTTON_LIST_MAX 10 + +typedef void (*my_button_callback)(void*); + +enum my_button_event +{ + BUTTON_EVENT_CLICK_DOWN, + BUTTON_EVENT_CLICK_UP, + BUTTON_EVENT_HOLD, + BUTTON_EVENT_HOLD_CYC, + BUTTON_EVENT_HOLD_UP, + BUTTON_EVENT_NONE +}; + +struct my_button +{ + rt_uint8_t press_logic_level; + rt_uint16_t cnt; + rt_uint16_t hold_cyc_period; + rt_uint16_t pin; + + enum my_button_event event; + + my_button_callback cb; +}; + +int my_button_register(struct my_button *button); +int my_button_start(void); + + +#endif diff --git a/bsp/lpc55sxx/Libraries/drivers/drv_led.c b/bsp/lpc55sxx/Libraries/drivers/drv_led.c new file mode 100644 index 000000000..d7c5a32ef --- /dev/null +++ b/bsp/lpc55sxx/Libraries/drivers/drv_led.c @@ -0,0 +1,160 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-07-19 Magicoe The first version for LPC55S6x + */ + +#include + +#include "rtconfig.h" + +#include "fsl_common.h" +#include "fsl_iocon.h" +#include "fsl_gpio.h" +#include "fsl_inputmux.h" + +#define LED_DEVICE_CTRL 0x81 /*LED control command*/ + +#define LED_NUM 2 + +struct led_ctrl +{ + uint8_t port; + uint32_t pin; +}; + +struct lpc_led +{ + /* inherit from rt_device */ + struct rt_device parent; + + struct led_ctrl ctrl[LED_NUM]; +}; + +static struct lpc_led led; + +static rt_err_t rt_led_init(rt_device_t dev) +{ + gpio_pin_config_t pin_config = {kGPIO_DigitalOutput, 1}; + + GPIO_PinInit(GPIO, 1, 7, &pin_config); + GPIO_PinInit(GPIO, 1, 6, &pin_config); + + led.ctrl[0].pin = 7; + led.ctrl[0].port = 1; + led.ctrl[1].pin = 6; + led.ctrl[1].port = 1; + + return RT_EOK; +} + +static rt_err_t rt_led_open(rt_device_t dev, rt_uint16_t oflag) +{ + return RT_EOK; +} + +static rt_err_t rt_led_close(rt_device_t dev) +{ + return RT_EOK; +} + +static rt_size_t rt_led_read(rt_device_t dev, rt_off_t pos, void *buffer, + rt_size_t size) +{ + rt_ubase_t index = 0; + rt_ubase_t nr = size; + rt_uint8_t *value = buffer; + + RT_ASSERT(dev == &led.parent); + RT_ASSERT((pos + size) <= LED_NUM); + + for (index = 0; index < nr; index++) + { + if(GPIO_PinRead(GPIO, led.ctrl[pos + index].port, led.ctrl[pos + index].pin) == 0) + { + *value = 0; + } + else + { + *value = 1; + } + value++; + } + return index; +} + +static rt_size_t rt_led_write(rt_device_t dev, rt_off_t pos, + const void *buffer, rt_size_t size) +{ + rt_ubase_t index = 0; + rt_ubase_t nw = size; + const rt_uint8_t *value = buffer; + + RT_ASSERT(dev == &led.parent); + RT_ASSERT((pos + size) <= LED_NUM); + + for (index = 0; index < nw; index++) + { + if (*value++) + { + GPIO_PinWrite(GPIO, led.ctrl[pos + index].port, led.ctrl[pos + index].pin, 0); + } + else + { + GPIO_PinWrite(GPIO, led.ctrl[pos + index].port, led.ctrl[pos + index].pin, 1); + } + } + return index; +} + +static rt_err_t rt_led_control(rt_device_t dev, int cmd, void *args) +{ + RT_ASSERT(dev == &led.parent); + + if (cmd == LED_DEVICE_CTRL) + { + rt_uint32_t *led_num = args; + *led_num = LED_NUM; + } + return RT_EOK; +} + +int rt_hw_led_init(void) +{ + led.parent.type = RT_Device_Class_Char; + led.parent.rx_indicate = RT_NULL; + led.parent.tx_complete = RT_NULL; + led.parent.init = rt_led_init; + led.parent.open = rt_led_open; + led.parent.close = rt_led_close; + led.parent.read = rt_led_read; + led.parent.write = rt_led_write; + led.parent.control = rt_led_control; + led.parent.user_data = RT_NULL; + + /* register a character device */ + rt_device_register(&led.parent, "led", RT_DEVICE_FLAG_RDWR); + /* init led device */ + rt_led_init(&led.parent); + return 0; +} + +INIT_DEVICE_EXPORT(rt_hw_led_init); + +#ifdef RT_USING_FINSH +#include +#include "msh.h" + +void led_test(rt_uint32_t led_num, rt_uint32_t value) +{ + rt_uint8_t led_value = value; + + rt_led_write(&led.parent, led_num, &led_value, 1); +} +FINSH_FUNCTION_EXPORT(led_test, e.g: led_test(0, 1).); + +#endif diff --git a/bsp/lpc55sxx/Libraries/drivers/drv_led.h b/bsp/lpc55sxx/Libraries/drivers/drv_led.h new file mode 100644 index 000000000..de45db906 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/drivers/drv_led.h @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-07-19 Magicoe The first version for LPC55S6x + */ + +#ifndef __DRV_LED_H__ +#define __DRV_LED_H__ + +#include +#include + +int rt_hw_led_init(void); + +#endif diff --git a/bsp/lpc55sxx/Libraries/drivers/drv_log.h b/bsp/lpc55sxx/Libraries/drivers/drv_log.h new file mode 100644 index 000000000..7e0bfee5b --- /dev/null +++ b/bsp/lpc55sxx/Libraries/drivers/drv_log.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-15 SummerGift first version + */ + +/* + * NOTE: DO NOT include this file on the header file. + */ + +#ifndef LOG_TAG +#define DBG_TAG "drv" +#else +#define DBG_TAG LOG_TAG +#endif /* LOG_TAG */ + +#ifdef DRV_DEBUG +#define DBG_LVL DBG_LOG +#else +#define DBG_LVL DBG_INFO +#endif /* DRV_DEBUG */ + +#include diff --git a/bsp/lpc55sxx/Libraries/drivers/drv_mma8562.c b/bsp/lpc55sxx/Libraries/drivers/drv_mma8562.c new file mode 100644 index 000000000..e009c8684 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/drivers/drv_mma8562.c @@ -0,0 +1,162 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-07-22 Magicoe The first version for LPC55S6x + */ + +#include +#include +#include + +#include "rtconfig.h" +#include "drv_mma8562.h" + +enum _mma8562_i2c_constants +{ + kMMA8562_ADDR = 0x1D, + kMMA8562_ADDR_With_SAO_Set = kMMA8562_ADDR | 1 +}; + +#define MMA8562_I2CBUS_NAME "i2c4" + +static struct rt_i2c_bus_device *mma8562_i2c_bus; + +//////////////////////////////////////////////////////////////////////////////// +// Code +//////////////////////////////////////////////////////////////////////////////// + + +rt_err_t mma8562_read_reg(rt_uint8_t reg, rt_uint8_t len, rt_uint8_t *buf) +{ + struct rt_i2c_msg msgs[2]; + + msgs[0].addr = kMMA8562_ADDR; + msgs[0].flags = RT_I2C_WR; + msgs[0].buf = ® + msgs[0].len = 1; + + msgs[1].addr = kMMA8562_ADDR; + msgs[1].flags = RT_I2C_RD; + msgs[1].buf = buf; + msgs[1].len = len; + + if (rt_i2c_transfer(mma8562_i2c_bus, msgs, 2) == 2) + { + return RT_EOK; + } + else + { + return -RT_ERROR; + } +} + +rt_err_t mma8562_write_reg(rt_uint8_t reg, rt_uint8_t data) +{ + rt_uint8_t buf[2]; + + buf[0] = reg; + buf[1] = data; + + if (rt_i2c_master_send(mma8562_i2c_bus, kMMA8562_ADDR, 0, buf ,2) == 2) + { + return RT_EOK; + } + else + { + return -RT_ERROR; + } +} + +#ifdef RT_USING_FINSH +#include +#include + +void get_mma8562(uint8_t data) +{ + volatile acceleration_t accel; + + uint8_t ucVal1 = 0; + uint8_t ucVal2 = 0; + uint8_t ucStatus = 0; + + do { + mma8562_read_reg(kMMA8562_STATUS, 1, &ucStatus); + } while (!(ucStatus & 0x08)); + + mma8562_read_reg(kMMA8562_OUT_X_MSB, 1, &ucVal1); + mma8562_read_reg(kMMA8562_OUT_X_LSB, 1, &ucVal2); + + accel.x = ucVal1*256 +ucVal2; + + mma8562_read_reg(kMMA8562_OUT_Y_MSB, 1, &ucVal1); + mma8562_read_reg(kMMA8562_OUT_Y_LSB, 1, &ucVal2); + accel.y = ucVal1*256 +ucVal2; + + mma8562_read_reg(kMMA8562_OUT_Z_MSB, 1, &ucVal1); + mma8562_read_reg(kMMA8562_OUT_Z_LSB, 1, &ucVal2); + accel.z = ucVal1*256 +ucVal2; + + rt_kprintf("*** MMA8562 X %d, Y %d, Z %d\r\n", (accel.x), (accel.y), (accel.z) ); +} +FINSH_FUNCTION_EXPORT(get_mma8562, get mma8562. e.g: get_mma8562(0)) +#endif + +int mma8562_hw_init(void) +{ + // Init the I2C port. + // Should be init in startup + uint8_t val = 0; + + mma8562_i2c_bus = rt_i2c_bus_device_find(MMA8562_I2CBUS_NAME); /* */ + + // Read WHO_AM_I register. + mma8562_read_reg(kMMA8562_WHO_AM_I, 1, &val); + if (val != kMMA8562_WHO_AM_I_Device_ID) + { + rt_kprintf("MMA8562: Unexpected result from WHO_AM_I (0x%02x)\n", val); + return RT_ERROR; + } + + /* please refer to the "example FXOS8700CQ Driver Code" in FXOS8700 datasheet. */ + /* write 0000 0000 = 0x00 to accelerometer control register 1 */ + /* standby */ + /* [7-1] = 0000 000 */ + /* [0]: active=0 */ + val = 0; + mma8562_write_reg( kMMA8562_CTRL_REG1, val); + + /* write 0000 0001= 0x01 to XYZ_DATA_CFG register */ + /* [7]: reserved */ + /* [6]: reserved */ + /* [5]: reserved */ + /* [4]: hpf_out=0 */ + /* [3]: reserved */ + /* [2]: reserved */ + /* [1-0]: fs=01 for accelerometer range of +/-4g range with 0.488mg/LSB */ + /* databyte = 0x01; */ + val = 0x01; + mma8562_write_reg(kMMA8562_XYZ_DATA_CFG, val); + + /* write 0000 1101 = 0x0D to accelerometer control register 1 */ + /* [7-6]: aslp_rate=00 */ + /* [5-3]: dr=001 for 200Hz data rate (when in hybrid mode) */ + /* [2]: lnoise=1 for low noise mode */ + /* [1]: f_read=0 for normal 16 bit reads */ + /* [0]: active=1 to take the part out of standby and enable sampling */ + /* databyte = 0x0D; */ + val = 0x0D; + mma8562_write_reg(kMMA8562_CTRL_REG1, val); + + return 0; +} + +INIT_DEVICE_EXPORT(mma8562_hw_init); + + +//////////////////////////////////////////////////////////////////////////////// +// EOF +//////////////////////////////////////////////////////////////////////////////// diff --git a/bsp/lpc55sxx/Libraries/drivers/drv_mma8562.h b/bsp/lpc55sxx/Libraries/drivers/drv_mma8562.h new file mode 100644 index 000000000..9eb95f814 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/drivers/drv_mma8562.h @@ -0,0 +1,111 @@ +/* + * Copyright (c) 2013, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/*! + * @file + * @brief Public interface for the MMA8562 accelerometer driver. + * @ingroup diag_accel + */ + +#ifndef __MMA8562_H__ +#define __MMA8562_H__ + +#include "stdint.h" + +//! @addtogroup diag_accel +//! @{ + +//////////////////////////////////////////////////////////////////////////////// +// Definitions +//////////////////////////////////////////////////////////////////////////////// + +//! @brief Error codes for the MMA8562 driver. +enum _mma8562_errors +{ + kMMA8562_Invalid_I2C_Address_Error = -128 +}; + +//! @brief Register definitions for the MMA8562. +enum _mma8562_constants +{ + kMMA8562_STATUS = 0x00, + kMMA8562_OUT_X_MSB = 0x01, + kMMA8562_OUT_X_LSB = 0x02, + kMMA8562_OUT_Y_MSB = 0x03, + kMMA8562_OUT_Y_LSB = 0x04, + kMMA8562_OUT_Z_MSB = 0x05, + kMMA8562_OUT_Z_LSB = 0x06, + kMMA8562_F_SETUP = 0x09, + kMMA8562_TRIG_CFG = 0x0a, + kMMA8562_SYSMOD = 0x0b, + kMMA8562_INT_SOURCE = 0x0c, + kMMA8562_WHO_AM_I = 0x0d, + kMMA8562_WHO_AM_I_Device_ID = 0x4a, + kMMA8562_XYZ_DATA_CFG = 0x0e, + kMMA8562_CTRL_REG1 = 0x2a, + kMMA8562_CTRL_REG2 = 0x2b, + kMMA8562_CTRL_REG3 = 0x2c, + kMMA8562_CTRL_REG4 = 0x2d, + kMMA8562_CTRL_REG5 = 0x2e +}; + +//! @brief 3D acceleration values. +typedef struct _acceleration { + int16_t x; + int16_t y; + int16_t z; +} acceleration_t; + +//////////////////////////////////////////////////////////////////////////////// +// API +//////////////////////////////////////////////////////////////////////////////// + +#if defined(__cplusplus) +extern "C" { +#endif + +extern int mma8562_hw_init(void); + +extern void get_mma8562(uint8_t data); + +extern rt_err_t mma8562_read_reg(rt_uint8_t reg, rt_uint8_t len, rt_uint8_t *buf); + +extern rt_err_t mma8562_write_reg(rt_uint8_t reg, rt_uint8_t data); + +#if defined(__cplusplus) +} +#endif + +//! @} + +#endif //__MMA8562_H__ +//////////////////////////////////////////////////////////////////////////////// +// EOF +//////////////////////////////////////////////////////////////////////////////// diff --git a/bsp/lpc55sxx/Libraries/drivers/drv_pin.c b/bsp/lpc55sxx/Libraries/drivers/drv_pin.c new file mode 100644 index 000000000..cc8d027c7 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/drivers/drv_pin.c @@ -0,0 +1,431 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-03-13 Liuguang the first version. + * 2018-03-19 Liuguang add GPIO interrupt mode support. + * 2018-11-30 yangjie The first version for LPC54114 + * 2019-07-20 Magicoe The first version for LPC55S6x + */ +#include "drv_pin.h" + +#include "fsl_common.h" +#include "fsl_iocon.h" +#include "fsl_gpio.h" +#include "fsl_gint.h" +#include "fsl_pint.h" +#include "fsl_inputmux.h" + +#ifdef RT_USING_PIN + +#if defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL +#error "Please don't define 'FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL'!" +#endif + +#define get_port(x) ((x-1) / 32) +#define get_pin(x) ((x-1) % 32) + +#define PIN_MAX_VAL 64 +#define IRQ_MAX_VAL 8 + +struct lpc_pin +{ + rt_uint16_t pin; + GPIO_Type *gpio; + rt_uint8_t gpio_port; + rt_uint32_t gpio_pin; +}; + + +#define __ARRAY_LEN(array) (sizeof(array)/sizeof(array[0])) +#define __LPC55S69_PIN_DEFAULT {0, 0, 0, 0} +#define __LPC55S69_PIN(INDEX, REG, PORT, PIN) {INDEX, REG, PORT, PIN} + +static struct rt_pin_ops lpc_pin_ops; + +static struct lpc_pin lpc_pin_map[] = +{ + __LPC55S69_PIN_DEFAULT, + + /* PIO0 / GPIO0 */ + __LPC55S69_PIN( 1, GPIO, 0, 0), /* PIO0_00 */ + __LPC55S69_PIN( 2, GPIO, 0, 1), /* PIO0_01 */ + __LPC55S69_PIN( 3, GPIO, 0, 2), /* PIO0_02 */ + __LPC55S69_PIN( 4, GPIO, 0, 3), /* PIO0_04 */ + __LPC55S69_PIN( 5, GPIO, 0, 4), /* PIO0_04 */ + __LPC55S69_PIN( 6, GPIO, 0, 5), /* PIO0_05 */ + __LPC55S69_PIN( 7, GPIO, 0, 6), /* PIO0_06 */ + __LPC55S69_PIN( 8, GPIO, 0, 7), /* PIO0_07 */ + __LPC55S69_PIN( 9, GPIO, 0, 8), /* PIO0_08 */ + __LPC55S69_PIN(10, GPIO, 0, 9), /* PIO0_09 */ + __LPC55S69_PIN(11, GPIO, 0, 10), /* PIO0_10 */ + __LPC55S69_PIN(12, GPIO, 0, 11), /* PIO0_11 */ + __LPC55S69_PIN(13, GPIO, 0, 12), /* PIO0_12 */ + __LPC55S69_PIN(14, GPIO, 0, 13), /* PIO0_13 */ + __LPC55S69_PIN(15, GPIO, 0, 14), /* PIO0_14 */ + __LPC55S69_PIN(16, GPIO, 0, 15), /* PIO0_15 */ + __LPC55S69_PIN(17, GPIO, 0, 16), /* PIO0_16 */ + __LPC55S69_PIN(18, GPIO, 0, 17), /* PIO0_17 */ + __LPC55S69_PIN(19, GPIO, 0, 18), /* PIO0_18 */ + __LPC55S69_PIN(20, GPIO, 0, 19), /* PIO0_19 */ + __LPC55S69_PIN(21, GPIO, 0, 20), /* PIO0_20 */ + __LPC55S69_PIN(22, GPIO, 0, 21), /* PIO0_21 */ + __LPC55S69_PIN(23, GPIO, 0, 22), /* PIO0_22 */ + __LPC55S69_PIN(24, GPIO, 0, 23), /* PIO0_23 */ + __LPC55S69_PIN(25, GPIO, 0, 24), /* PIO0_24 */ + __LPC55S69_PIN(26, GPIO, 0, 25), /* PIO0_25 */ + __LPC55S69_PIN(27, GPIO, 0, 26), /* PIO0_26 */ + __LPC55S69_PIN(28, GPIO, 0, 27), /* PIO0_27 */ + __LPC55S69_PIN(29, GPIO, 0, 28), /* PIO0_28 */ + __LPC55S69_PIN(30, GPIO, 0, 29), /* PIO0_29 */ + __LPC55S69_PIN(31, GPIO, 0, 30), /* PIO0_30 */ + __LPC55S69_PIN(32, GPIO, 0, 31), /* PIO0_31 */ + + + /* PIO1 / GPIO, 1 */ + __LPC55S69_PIN(33, GPIO, 1, 0), /* PIO1_00 */ + __LPC55S69_PIN(34, GPIO, 1, 1), /* PIO1_01 */ + __LPC55S69_PIN(35, GPIO, 1, 2), /* PIO1_02 */ + __LPC55S69_PIN(36, GPIO, 1, 3), /* PIO1_03 */ + __LPC55S69_PIN(37, GPIO, 1, 4), /* PIO1_04 */ + __LPC55S69_PIN(38, GPIO, 1, 5), /* PIO1_05 */ + __LPC55S69_PIN(39, GPIO, 1, 6), /* PIO1_06 */ + __LPC55S69_PIN(40, GPIO, 1, 7), /* PIO1_07 */ + __LPC55S69_PIN(41, GPIO, 1, 8), /* PIO1_08 */ + __LPC55S69_PIN(42, GPIO, 1, 9), /* PIO1_09 */ + __LPC55S69_PIN(43, GPIO, 1, 10), /* PIO1_10 */ + __LPC55S69_PIN(44, GPIO, 1, 11), /* PIO1_11 */ + __LPC55S69_PIN(45, GPIO, 1, 12), /* PIO1_12 */ + __LPC55S69_PIN(46, GPIO, 1, 13), /* PIO1_13 */ + __LPC55S69_PIN(47, GPIO, 1, 14), /* PIO1_14 */ + __LPC55S69_PIN(48, GPIO, 1, 15), /* PIO1_15 */ + __LPC55S69_PIN(49, GPIO, 1, 16), /* PIO1_16 */ + __LPC55S69_PIN(50, GPIO, 1, 17), /* PIO1_17 */ + __LPC55S69_PIN(51, GPIO, 1, 18), /* PIO1_18 */ + __LPC55S69_PIN(52, GPIO, 1, 19), /* PIO1_19 */ + __LPC55S69_PIN(53, GPIO, 1, 20), /* PIO1_20 */ + __LPC55S69_PIN(54, GPIO, 1, 21), /* PIO1_21 */ + __LPC55S69_PIN(55, GPIO, 1, 22), /* PIO1_22 */ + __LPC55S69_PIN(56, GPIO, 1, 23), /* PIO1_23 */ + __LPC55S69_PIN(57, GPIO, 1, 24), /* PIO1_24 */ + __LPC55S69_PIN(58, GPIO, 1, 25), /* PIO1_25 */ + __LPC55S69_PIN(59, GPIO, 1, 26), /* PIO1_26 */ + __LPC55S69_PIN(60, GPIO, 1, 27), /* PIO1_27 */ + __LPC55S69_PIN(61, GPIO, 1, 28), /* PIO1_28 */ + __LPC55S69_PIN(62, GPIO, 1, 29), /* PIO1_29 */ + __LPC55S69_PIN(63, GPIO, 1, 30), /* PIO1_30 */ + __LPC55S69_PIN(64, GPIO, 1, 31), /* PIO1_31 */ +}; + +struct rt_pin_irq_hdr pin_irq_hdr_tab[] = +{ + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, +}; + +static void lpc_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) +{ + int dir; + uint32_t pin_cfg; + + if ((pin > __ARRAY_LEN(lpc_pin_map)) || (pin == 0)) + { + return; + } + + switch (mode) + { + case PIN_MODE_OUTPUT: + { + dir = kGPIO_DigitalOutput; + pin_cfg = IOCON_FUNC0 | IOCON_DIGITAL_EN | IOCON_MODE_PULLUP; + } + break; + + case PIN_MODE_INPUT: + { + dir = kGPIO_DigitalInput; + pin_cfg = IOCON_FUNC0 | IOCON_INPFILT_OFF | IOCON_DIGITAL_EN; + } + break; + + case PIN_MODE_INPUT_PULLDOWN: + { + dir = kGPIO_DigitalInput; + pin_cfg = IOCON_FUNC0 | IOCON_INPFILT_OFF | IOCON_DIGITAL_EN | IOCON_MODE_PULLDOWN; + } + break; + + case PIN_MODE_INPUT_PULLUP: + { + dir = kGPIO_DigitalInput; + pin_cfg = IOCON_FUNC0 | IOCON_INPFILT_OFF | IOCON_DIGITAL_EN | IOCON_MODE_PULLUP; + } + break; + + case PIN_MODE_OUTPUT_OD: + { + dir = kGPIO_DigitalOutput; + pin_cfg = IOCON_FUNC0 | IOCON_OPENDRAIN_EN | IOCON_DIGITAL_EN; + } + break; + } + + /* Enable IOCON Clock */ + CLOCK_EnableClock(kCLOCK_Iocon); + IOCON->PIO[lpc_pin_map[pin].gpio_port][lpc_pin_map[pin].gpio_pin] = pin_cfg; + /* Disable IOCON Clock -- To Save Power */ + CLOCK_DisableClock(kCLOCK_Iocon); + + gpio_pin_config_t pin_config = {(gpio_pin_direction_t)dir, 1}; + GPIO_PinInit(GPIO, lpc_pin_map[pin].gpio_port, lpc_pin_map[pin].gpio_pin, &pin_config); +} + + +static void lpc_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value) +{ + if ((pin > __ARRAY_LEN(lpc_pin_map)) || (pin == 0)) + { + return; + } + + GPIO_PinWrite(lpc_pin_map[pin].gpio, lpc_pin_map[pin].gpio_port, lpc_pin_map[pin].gpio_pin, value); +} + +static int lpc_pin_read(rt_device_t dev, rt_base_t pin) +{ + int value; + if ((pin > __ARRAY_LEN(lpc_pin_map)) || (pin == 0)) + { + return RT_ERROR; + } + + value = GPIO_PinRead(lpc_pin_map[pin].gpio, lpc_pin_map[pin].gpio_port, lpc_pin_map[pin].gpio_pin); + + return value; +} + + +static void pin_irq_hdr(pint_pin_int_t pintr, uint32_t pmatch_status) +{ + int irqno = 0; + for(irqno = 0; irqno < IRQ_MAX_VAL; irqno ++) + { + if((irqno) == pintr) + { + break; + } + } + + if(irqno >= IRQ_MAX_VAL) + return; + + if (pin_irq_hdr_tab[irqno].hdr) + { + pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args); + } +} + + +void callback(pint_pin_int_t pintr, uint32_t pmatch_status) +{ + pin_irq_hdr(pintr, pmatch_status); +} + +/* IRQ handler functions overloading weak symbols in the startup */ +void PIN_INT0_IRQHandler(void) +{ + uint32_t pmstatus; + + /* Reset pattern match detection */ + pmstatus = PINT_PatternMatchResetDetectLogic(PINT); + + pin_irq_hdr(kPINT_PinInt0, pmstatus); + + if ((PINT->ISEL & 0x1U) == 0x0U) + { + /* Edge sensitive: clear Pin interrupt after callback */ + PINT_PinInterruptClrStatus(PINT, kPINT_PinInt0); + } +} + +static rt_err_t lpc_pin_attach_irq(struct rt_device *device, + rt_int32_t pin, + rt_uint32_t mode, + void (*hdr)(void *args), + void *args) +{ + int trigger_mode, pin_initx, pintsel, pin_cfg, i; + + if ((pin > __ARRAY_LEN(lpc_pin_map)) || (pin == 0)) + { + return RT_ERROR; + } + + switch (mode) + { + case PIN_IRQ_MODE_RISING: + trigger_mode = kPINT_PinIntEnableRiseEdge; + break; + case PIN_IRQ_MODE_FALLING: + trigger_mode = kPINT_PinIntEnableFallEdge; + break; + case PIN_IRQ_MODE_RISING_FALLING: + trigger_mode = kPINT_PinIntEnableBothEdges; + break; + case PIN_IRQ_MODE_HIGH_LEVEL: + trigger_mode = kPINT_PinIntEnableHighLevel; + break; + case PIN_IRQ_MODE_LOW_LEVEL: + trigger_mode = kPINT_PinIntEnableLowLevel; + break; + } + + /* Get inputmux_connection_t */ + pintsel = (pin - 1 + (0xC0U << 20)); + + for(i = 0; i < IRQ_MAX_VAL; i++) + { + if(pin_irq_hdr_tab[i].pin == -1) + { + pin_initx = kPINT_PinInt0 + i; + pin_irq_hdr_tab[i].pin = pin; + pin_irq_hdr_tab[i].mode = trigger_mode; + pin_irq_hdr_tab[i].hdr = hdr; + pin_irq_hdr_tab[i].args = args; + break; + } + } + + if(i >= IRQ_MAX_VAL) + return RT_ERROR; + + /* Initialize PINT */ + PINT_Init(PINT); + + /* Enable Input and IOCon clk */ + /* AttachSignal */ + /* Connect trigger sources to PINT */ + INPUTMUX_Init(INPUTMUX); + INPUTMUX_AttachSignal(INPUTMUX, i, (inputmux_connection_t)pintsel); + /* Turnoff clock to inputmux to save power. Clock is only needed to make changes */ + INPUTMUX_Deinit(INPUTMUX); + + pin_cfg = ((IOCON->PIO[lpc_pin_map[pin].gpio_port][lpc_pin_map[pin].gpio_pin] & + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK | IOCON_PIO_FILTEROFF_MASK))) /* Mask bits to zero which are setting */ + | IOCON_PIO_FUNC(0) /* Selects pin function.: PORT18 (pin 28) is configured as PIO1_8 */ + | IOCON_PIO_DIGIMODE(1) /* Select Analog/Digital mode.: Digital mode. */ + | IOCON_PIO_FILTEROFF(0)); /* Controls input glitch filter.: Filter enabled. Noise pulses below approximately 10 ns are filtered out. */ + + IOCON_PinMuxSet(IOCON, lpc_pin_map[pin].gpio_port, lpc_pin_map[pin].gpio_pin, pin_cfg); + + /* PINT_PinInterruptConfig */ + PINT_PinInterruptConfig(PINT, (pint_pin_int_t)pin_initx, (pint_pin_enable_t)(pin_irq_hdr_tab[i].mode), callback); + /* Enable callbacks for PINTx by Index */ + PINT_EnableCallbackByIndex(PINT, (pint_pin_int_t)pin_initx); + + return RT_EOK; +} + +static rt_err_t lpc_pin_detach_irq(struct rt_device *device, rt_int32_t pin) +{ + int i; + + if ((pin > __ARRAY_LEN(lpc_pin_map)) || (pin == 0)) + { + return RT_ERROR; + } + + for(i = 0; i < IRQ_MAX_VAL; i++) + { + if(pin_irq_hdr_tab[i].pin == pin) + { + pin_irq_hdr_tab[i].pin = -1; + pin_irq_hdr_tab[i].hdr = RT_NULL; + pin_irq_hdr_tab[i].mode = 0; + pin_irq_hdr_tab[i].args = RT_NULL; + break; + } + } + return RT_EOK; +} + +static rt_err_t lpc_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled) +{ + int irqn_type, i; + + if ((pin > __ARRAY_LEN(lpc_pin_map)) || (pin == 0)) + { + return RT_ERROR; + } + + for(i = 0; i < IRQ_MAX_VAL; i++) + { + if(pin_irq_hdr_tab[i].pin == pin) + { + switch(i) + { + case 0: irqn_type = PIN_INT0_IRQn; break; + case 1: irqn_type = PIN_INT1_IRQn; break; + case 2: irqn_type = PIN_INT2_IRQn; break; + case 3: irqn_type = PIN_INT3_IRQn; break; + case 4: irqn_type = PIN_INT4_IRQn; break; + case 5: irqn_type = PIN_INT5_IRQn; break; + case 6: irqn_type = PIN_INT6_IRQn; break; + case 7: irqn_type = PIN_INT7_IRQn; break; + default:break; + } + if(enabled) + { + /* PINT_EnableCallback */ + PINT_PinInterruptClrStatusAll(PINT); + NVIC_ClearPendingIRQ((IRQn_Type)irqn_type); + PINT_PinInterruptClrStatus(PINT, (pint_pin_int_t)(kPINT_PinInt0 + i)); + EnableIRQ((IRQn_Type)irqn_type); + } + else + { + /* PINT_DisableCallback */ + DisableIRQ((IRQn_Type)irqn_type); + PINT_PinInterruptClrStatus(PINT, (pint_pin_int_t)(kPINT_PinInt0 + i)); + NVIC_ClearPendingIRQ((IRQn_Type)irqn_type); + } + break; + } + } + + if(i >= IRQ_MAX_VAL) + return RT_ERROR; + + return RT_EOK; +} + +int rt_hw_pin_init(void) +{ + int ret = RT_EOK; + + lpc_pin_ops.pin_mode = lpc_pin_mode; + lpc_pin_ops.pin_read = lpc_pin_read; + lpc_pin_ops.pin_write = lpc_pin_write; + lpc_pin_ops.pin_attach_irq = lpc_pin_attach_irq; + lpc_pin_ops.pin_detach_irq = lpc_pin_detach_irq; + lpc_pin_ops.pin_irq_enable = lpc_pin_irq_enable; + + ret = rt_device_pin_register("pin", &lpc_pin_ops, RT_NULL); + + return ret; +} +INIT_BOARD_EXPORT(rt_hw_pin_init); + +#endif /*RT_USING_PIN */ + +// end file diff --git a/bsp/lpc55sxx/Libraries/drivers/drv_pin.h b/bsp/lpc55sxx/Libraries/drivers/drv_pin.h new file mode 100644 index 000000000..0c69698e6 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/drivers/drv_pin.h @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-03-13 Liuguang the first version. + * 2018-03-19 Liuguang add GPIO interrupt mode support. + * 2019-07-15 Magicoe The first version for LPC55S6x + */ + +#ifndef __DRV_PIN_H__ +#define __DRV_PIN_H__ + +#include +#include + +#define GET_PINS(PORTx, PINx) (32 * PORTx + PINx + 1) /* PORTx:0,1, PINx:0,1...31 */ + +extern int rt_hw_pin_init(void); + +#endif /* __DRV_PIN_H__ */ diff --git a/bsp/lpc55sxx/Libraries/drivers/drv_pwm.c b/bsp/lpc55sxx/Libraries/drivers/drv_pwm.c new file mode 100644 index 000000000..64d6cfd00 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/drivers/drv_pwm.c @@ -0,0 +1,257 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-04-28 tyustli first version + * 2019-07-15 Magicoe The first version for LPC55S6x, we can also use SCT as PWM + * + */ + +#include + +#ifdef RT_USING_PWM +#if !defined(BSP_USING_CTIMER2_MAT0) && !defined(BSP_USING_CTIMER2_MAT1) && \ + !defined(BSP_USING_CTIMER2_MAT2) +#error "Please define at least one BSP_USING_CTIMERx_MATx" +#else + #define BSP_USING_CTIMER2 +#endif + +#define LOG_TAG "drv.pwm" +#include + +#include +#include "fsl_ctimer.h" +#include "drv_pwm.h" + +#define DEFAULT_DUTY 50 +#define DEFAULT_FREQ 1000 + +static rt_err_t lpc_drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg); + +static struct rt_pwm_ops lpc_drv_ops = +{ + .control = lpc_drv_pwm_control +}; + +static rt_err_t lpc_drv_pwm_enable(struct rt_device_pwm *device, struct rt_pwm_configuration *configuration, rt_bool_t enable) +{ + CTIMER_Type *base; + + base = (CTIMER_Type *)device->parent.user_data; + + if (!enable) + { + /* Stop the timer */ + CTIMER_StopTimer(base); + } + else + { + /* Start the timer */ + CTIMER_StartTimer(base); + } + + return RT_EOK; +} + +static rt_err_t lpc_drv_pwm_get(struct rt_device_pwm *device, struct rt_pwm_configuration *configuration) +{ + uint8_t get_duty; + uint32_t get_frequence; + uint32_t pwmClock = 0; + CTIMER_Type *base; + + base = (CTIMER_Type *)device->parent.user_data; + +#ifdef BSP_USING_CTIMER2 + /* get frequence */ + pwmClock = CLOCK_GetFreq(kCLOCK_CTimer2) ; +#endif + + get_frequence = pwmClock / (base->MR[kCTIMER_Match_3] + 1); + + if(configuration->channel == 1) + { + /* get dutycycle */ + get_duty = (100*(base->MR[kCTIMER_Match_3] + 1 - base->MR[kCTIMER_Match_1]))/(base->MR[kCTIMER_Match_3] + 1); + } + + /* get dutycycle */ + /* conversion */ + configuration->period = 1000000000 / get_frequence; + configuration->pulse = get_duty * configuration->period / 100; + + rt_kprintf("*** PWM period %d, pulse %d\r\n", configuration->period, configuration->pulse); + + return RT_EOK; +} + +static rt_err_t lpc_drv_pwm_set(struct rt_device_pwm *device, struct rt_pwm_configuration *configuration) +{ + RT_ASSERT(configuration->period > 0); + RT_ASSERT(configuration->pulse <= configuration->period); + + ctimer_config_t config; + CTIMER_Type *base; + base = (CTIMER_Type *)device->parent.user_data; + + uint32_t pwmPeriod, pulsePeriod; + /* Run as a timer */ + config.mode = kCTIMER_TimerMode; + /* This field is ignored when mode is timer */ + config.input = kCTIMER_Capture_0; + /* Timer counter is incremented on every APB bus clock */ + config.prescale = 0; + + if(configuration->channel == 1) + { + /* Get the PWM period match value and pulse width match value of DEFAULT_FREQ PWM signal with DEFAULT_DUTY dutycycle */ + /* Calculate PWM period match value */ + pwmPeriod = (( CLOCK_GetFreq(kCLOCK_CTimer2) / (config.prescale + 1) ) / DEFAULT_FREQ) - 1; + + /* Calculate pulse width match value */ + if (DEFAULT_DUTY == 0) + { + pulsePeriod = pwmPeriod + 1; + } + else + { + pulsePeriod = (pwmPeriod * (100 - DEFAULT_DUTY)) / 100; + } + /* Match on channel 3 will define the PWM period */ + base->MR[kCTIMER_Match_3] = pwmPeriod; + /* This will define the PWM pulse period */ + base->MR[kCTIMER_Match_1] = pulsePeriod; + + } + + return RT_EOK; +} + +static rt_err_t lpc_drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg) +{ + struct rt_pwm_configuration *configuration = (struct rt_pwm_configuration *)arg; + + switch (cmd) + { + case PWM_CMD_ENABLE: + return lpc_drv_pwm_enable(device, configuration, RT_TRUE); + case PWM_CMD_DISABLE: + return lpc_drv_pwm_enable(device, configuration, RT_FALSE); + case PWM_CMD_SET: + return lpc_drv_pwm_set(device, configuration); + case PWM_CMD_GET: + return lpc_drv_pwm_get(device, configuration); + default: + return RT_EINVAL; + } +} + +int rt_hw_pwm_init(void) +{ + rt_err_t ret = RT_EOK; + +#ifdef BSP_USING_CTIMER2 + + static struct rt_device_pwm pwm1_device; + ctimer_config_t config; + uint32_t pwmPeriod, pulsePeriod; + + /* Use 12 MHz clock for some of the Ctimers */ + CLOCK_AttachClk(kMAIN_CLK_to_CTIMER2); + + /* Run as a timer */ + config.mode = kCTIMER_TimerMode; + /* This field is ignored when mode is timer */ + config.input = kCTIMER_Capture_0; + /* Timer counter is incremented on every APB bus clock */ + config.prescale = 0; + + CTIMER_Init(CTIMER2, &config); + +#ifdef BSP_USING_CTIMER2_MAT1 + /* Get the PWM period match value and pulse width match value of DEFAULT_FREQ PWM signal with DEFAULT_DUTY dutycycle */ + /* Calculate PWM period match value */ + pwmPeriod = (( CLOCK_GetFreq(kCLOCK_CTimer2) / (config.prescale + 1) ) / DEFAULT_FREQ) - 1; + + /* Calculate pulse width match value */ + if (DEFAULT_DUTY == 0) + { + pulsePeriod = pwmPeriod + 1; + } + else + { + pulsePeriod = (pwmPeriod * (100 - DEFAULT_DUTY)) / 100; + } + CTIMER_SetupPwmPeriod(CTIMER2, kCTIMER_Match_1 , pwmPeriod, pulsePeriod, false); +#endif + + ret = rt_device_pwm_register(&pwm1_device, "pwm1", &lpc_drv_ops, CTIMER2); + + if (ret != RT_EOK) + { + LOG_E("%s register failed", "pwm1"); + } + +#endif /* BSP_USING_CTIMER2 */ + + return ret; +} + +INIT_DEVICE_EXPORT(rt_hw_pwm_init); + + +#ifdef RT_USING_FINSH +#include + +#ifdef FINSH_USING_MSH + +rt_err_t rt_pwm_get(struct rt_device_pwm *device, int channel) +{ + rt_err_t result = RT_EOK; + struct rt_pwm_configuration configuration = {0}; + + if (!device) + { + return -RT_EIO; + } + + configuration.channel = channel; + result = rt_device_control(&device->parent, PWM_CMD_GET, &configuration); + + return result; +} + +static int pwm_get(int argc, char **argv) +{ + int result = 0; + struct rt_device_pwm *device = RT_NULL; + + if (argc != 3) + { + rt_kprintf("Usage: pwm_get pwm1 1\n"); + result = -RT_ERROR; + goto _exit; + } + + device = (struct rt_device_pwm *)rt_device_find(argv[1]); + if (!device) + { + result = -RT_EIO; + goto _exit; + } + + result = rt_pwm_get(device, atoi(argv[2])); + +_exit: + return result; +} +MSH_CMD_EXPORT(pwm_get, pwm_get pwm1 1); + +#endif /* FINSH_USING_MSH */ +#endif /* RT_USING_FINSH */ + +#endif /* RT_USING_PWM */ diff --git a/bsp/lpc55sxx/Libraries/drivers/drv_pwm.h b/bsp/lpc55sxx/Libraries/drivers/drv_pwm.h new file mode 100644 index 000000000..7260c0c58 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/drivers/drv_pwm.h @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-04-28 tyustli the first version. + * + */ + +#ifndef DRV_PWM_H__ +#define DRV_PWM_H__ + +#include + +int rt_hw_pwm_init(void); + +#endif diff --git a/bsp/lpc55sxx/Libraries/drivers/drv_rtc.c b/bsp/lpc55sxx/Libraries/drivers/drv_rtc.c new file mode 100644 index 000000000..5e160bc47 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/drivers/drv_rtc.c @@ -0,0 +1,153 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-03-15 Liuguang the first version. + * 2019-07-19 Magicoe The first version for LPC55S6x + */ + +#include "drv_rtc.h" + +#include "fsl_common.h" +#include "fsl_rtc.h" +#include + +#ifdef RT_USING_RTC + +#if defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL + #error "Please don't define 'FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL'!" +#endif + +static time_t get_timestamp(void) +{ + struct tm tm_new = {0}; + rtc_datetime_t rtcDate; + + /* Get date time */ + RTC_GetDatetime(RTC, &rtcDate); + + tm_new.tm_sec = rtcDate.second; + tm_new.tm_min = rtcDate.minute; + tm_new.tm_hour = rtcDate.hour; + + tm_new.tm_mday = rtcDate.day; + tm_new.tm_mon = rtcDate.month - 1; + tm_new.tm_year = rtcDate.year - 1900; + + return mktime(&tm_new); +} + +static int set_timestamp(time_t timestamp) +{ + struct tm *p_tm; + rtc_datetime_t rtcDate; + + p_tm = localtime(×tamp); + + rtcDate.second = p_tm->tm_sec ; + rtcDate.minute = p_tm->tm_min ; + rtcDate.hour = p_tm->tm_hour; + + rtcDate.day = p_tm->tm_mday; + rtcDate.month = p_tm->tm_mon + 1; + rtcDate.year = p_tm->tm_year + 1900; + + /* RTC time counter has to be stopped before setting the date & time in the TSR register */ + RTC_StopTimer(RTC); + + /* Set RTC time to default */ + RTC_SetDatetime(RTC, &rtcDate); + + /* Start the RTC time counter */ + RTC_StartTimer(RTC); + + return RT_EOK; +} + +static rt_err_t lpc_rtc_init(rt_device_t dev) +{ + /* Init RTC */ + RTC_Init(RTC); + + /* Start the RTC time counter */ + RTC_StartTimer(RTC); + + return RT_EOK; +} + +static rt_err_t lpc_rtc_open(rt_device_t dev, rt_uint16_t oflag) +{ + return RT_EOK; +} + +static rt_err_t lpc_rtc_close(rt_device_t dev) +{ + return RT_EOK; +} + +static rt_size_t lpc_rtc_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) +{ + return 0; +} + +static rt_size_t lpc_rtc_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) +{ + return 0; +} + +static rt_err_t lpc_rtc_control(rt_device_t dev, int cmd, void *args) +{ + RT_ASSERT(dev != RT_NULL); + + switch(cmd) + { + case RT_DEVICE_CTRL_RTC_GET_TIME: + { + *(uint32_t *)args = get_timestamp(); + } + break; + + case RT_DEVICE_CTRL_RTC_SET_TIME: + { + set_timestamp(*(time_t *)args); + } + break; + + default: + return RT_EINVAL; + } + + return RT_EOK; +} + +static struct rt_device device = +{ + .type = RT_Device_Class_RTC, + .init = lpc_rtc_init, + .open = lpc_rtc_open, + .close = lpc_rtc_close, + .read = lpc_rtc_read, + .write = lpc_rtc_write, + .control = lpc_rtc_control, +}; + +int rt_hw_rtc_init(void) +{ + rt_err_t ret = RT_EOK; + + ret = rt_device_register(&device, "rtc", RT_DEVICE_FLAG_RDWR); + if(ret != RT_EOK) + { + return ret; + } + + rt_device_open(&device, RT_DEVICE_OFLAG_RDWR); + + return RT_EOK; +} +INIT_DEVICE_EXPORT(rt_hw_rtc_init); + +#endif /*RT_USING_RTC */ diff --git a/bsp/lpc55sxx/Libraries/drivers/drv_rtc.h b/bsp/lpc55sxx/Libraries/drivers/drv_rtc.h new file mode 100644 index 000000000..a0623308a --- /dev/null +++ b/bsp/lpc55sxx/Libraries/drivers/drv_rtc.h @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-03-15 Liuguang the first version. + * 2019-07-19 Magicoe The first version for LPC55S6x + */ + +#ifndef __DRV_RTC_H__ +#define __DRV_RTC_H__ + +#include +#include + +int rt_hw_rtc_init(void); + +#endif diff --git a/bsp/lpc55sxx/Libraries/drivers/drv_sd.c b/bsp/lpc55sxx/Libraries/drivers/drv_sd.c new file mode 100644 index 000000000..e076ddf1f --- /dev/null +++ b/bsp/lpc55sxx/Libraries/drivers/drv_sd.c @@ -0,0 +1,243 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2017-08-08 Yang the first version + * 2019-07-19 Magicoe The first version for LPC55S6x + */ + +#include +#include + +#include "fsl_common.h" +#include "fsl_iocon.h" + +#include "fsl_sdif.h" + +#include "fsl_sd.h" + +#include "drv_sd.h" + +#include +#include +#include +#include "board.h" + +static struct mci_device *_mci_device; +static uint8_t sdio_buffer[1024]; + +#ifdef RT_USING_SDIO + +static rt_err_t rt_mci_init(rt_device_t dev) +{ + rt_err_t result = RT_EOK; + + return result; +} + +static rt_err_t rt_mci_open(rt_device_t dev, rt_uint16_t oflag) +{ + return RT_EOK; +} + +static rt_err_t rt_mci_close(rt_device_t dev) +{ + return RT_EOK; +} + +static rt_size_t rt_mci_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size) +{ + rt_uint8_t status = kStatus_Success; + struct mci_device *mci = (struct mci_device *)dev; + + rt_mutex_take(&mci->lock, RT_WAITING_FOREVER); + + { + /* non-aligned. */ + uint32_t i; + rt_size_t sector_adr; + uint8_t* copy_buffer; + + sector_adr = pos; + copy_buffer = (uint8_t*)buffer; + + for(i=0; icard, sdio_buffer, sector_adr, 1); + + memcpy(copy_buffer, sdio_buffer, mci->card.blockSize); + sector_adr ++; + copy_buffer += mci->card.blockSize; + } + } + + rt_mutex_release(&_mci_device->lock); + + if (status == kStatus_Success) return size; + + return 0; +} + +static rt_size_t rt_mci_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size) +{ + rt_uint8_t status = kStatus_Success; + struct mci_device *mci = (struct mci_device *)dev; + + rt_mutex_take(&mci->lock, RT_WAITING_FOREVER); + + { + /* non-aligned. */ + uint32_t i; + rt_size_t sector_adr; + uint8_t* copy_buffer; + + sector_adr = pos; + copy_buffer = (uint8_t*)buffer; + + for(i = 0; i < size; i++) + { + memcpy(sdio_buffer, copy_buffer, mci->card.blockSize); + + status = SD_WriteBlocks(&mci->card, sdio_buffer, sector_adr, 1); + + sector_adr ++; + copy_buffer += mci->card.blockSize; + + } + } + + /* release and exit */ + rt_mutex_release(&_mci_device->lock); + + if (status == kStatus_Success) return size; + + return 0; +} + +static rt_err_t rt_mci_control(rt_device_t dev, int cmd, void *args) +{ + struct mci_device *mci = (struct mci_device *)dev; + + RT_ASSERT(dev != RT_NULL); + + if (cmd == RT_DEVICE_CTRL_BLK_GETGEOME) + { + struct rt_device_blk_geometry *geometry; + + geometry = (struct rt_device_blk_geometry *)args; + if (geometry == RT_NULL) return -RT_ERROR; + + geometry->bytes_per_sector = mci->card.blockSize; + geometry->block_size = mci->card.csd.eraseSectorSize; + geometry->sector_count = mci->card.blockCount; + } + + return RT_EOK; +} + +/*! @brief SDMMC host detect card configuration */ +static const sdmmchost_detect_card_t s_sdCardDetect = { + .cdType = BOARD_SD_DETECT_TYPE, + .cdTimeOut_ms = (~0U), +}; + +/*! @brief Card descriptor. */ +sd_card_t g_sd; +int rt_hw_mci_init(void) +{ + _mci_device = (struct mci_device *)rt_malloc(sizeof(struct mci_device)); + if (_mci_device == RT_NULL) + { + rt_kprintf("mci_hw_init _mci_device rt_malloc failed!\n"); + return -RT_ERROR; + } + rt_memset(_mci_device, 0, sizeof(struct mci_device)); + + /* attach main clock to SDIF */ + CLOCK_AttachClk(kMAIN_CLK_to_SDIO_CLK); + /* need call this function to clear the halt bit in clock divider register */ + CLOCK_SetClkDiv(kCLOCK_DivSdioClk, (uint32_t)(SystemCoreClock / FSL_FEATURE_SDIF_MAX_SOURCE_CLOCK + 1U), true); + + _mci_device->card = g_sd; + + /* Save host information. */ + _mci_device->card.host.base = SDIF; + _mci_device->card.host.sourceClock_Hz = CLOCK_GetFreq(kCLOCK_SDio); + _mci_device->card.usrParam.cd = &s_sdCardDetect; +#if 1 + rt_kprintf("\r\nNeed wait a few seconds to SD init, Better Set SystemTick as 1000\r\n"); + rt_kprintf("SDCard Freq %d\r\n", _mci_device->card.host.sourceClock_Hz); +#endif + if (kStatus_Success != SD_HostInit(&_mci_device->card)) + { + memset(&_mci_device->card, 0U, sizeof(_mci_device->card)); + rt_kprintf("SD_Init failed!\n"); + return -RT_ERROR; + } + + /* power off card */ + SD_PowerOffCard(_mci_device->card.host.base, _mci_device->card.usrParam.pwr); + + /* check SD card insert */ + if(BOARD_SDIF_CD_STATUS() == true) + { + rt_kprintf("\r\nCard detect fail.\r\n"); + return kStatus_Fail; + } + + /* wait card insert */ + if (SD_WaitCardDetectStatus(_mci_device->card.host.base, &s_sdCardDetect, true) == kStatus_Success) + { + /* reset host once card re-plug in */ + SD_HostReset(&(_mci_device->card.host)); + /* power on the card */ + SD_PowerOnCard(_mci_device->card.host.base, _mci_device->card.usrParam.pwr); + } + else + { + rt_kprintf("\r\nCard detect fail.\r\n"); + return kStatus_Fail; + } + + /* Init card. */ + if (SD_CardInit(&_mci_device->card)) + { + rt_kprintf("\r\nSD card init failed.\r\n"); + return kStatus_Fail; + } + + /* initialize mutex lock */ + rt_mutex_init(&_mci_device->lock, "sdcard0", RT_IPC_FLAG_FIFO); + /* create finish event */ + _mci_device->finish_event = rt_event_create("sdcard0", RT_IPC_FLAG_FIFO); + + /* register sdcard device */ + _mci_device->parent.type = RT_Device_Class_Block; + + _mci_device->geometry.bytes_per_sector = 0; + _mci_device->geometry.sector_count = 0; + _mci_device->geometry.block_size = 0; + + _mci_device->parent.init = rt_mci_init; + _mci_device->parent.open = rt_mci_open; + _mci_device->parent.close = rt_mci_close; + _mci_device->parent.read = rt_mci_read; + _mci_device->parent.write = rt_mci_write; + _mci_device->parent.control = rt_mci_control; + + /* no private, no callback */ + _mci_device->parent.user_data = RT_NULL; + _mci_device->parent.rx_indicate = RT_NULL; + _mci_device->parent.tx_complete = RT_NULL; + + rt_device_register(&_mci_device->parent, "sdcard0", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_REMOVABLE ); + + return 0; +} +INIT_DEVICE_EXPORT(rt_hw_mci_init); + +#endif /* endif RT_USING_SDIO */ diff --git a/bsp/lpc55sxx/Libraries/drivers/drv_sd.h b/bsp/lpc55sxx/Libraries/drivers/drv_sd.h new file mode 100644 index 000000000..125f2b9a4 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/drivers/drv_sd.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-07-19 Magicoe The first version for LPC55S6x + */ + +#ifndef __DRV_SD_H__ +#define __DRV_SD_H__ + +#include +#include "rtdef.h" + +struct mci_device +{ + struct rt_device parent; /**< RT-Thread device struct */ + struct rt_device_blk_geometry geometry; /**< sector size, sector count */ + sd_card_t card; /**< Card descriptor */ + rt_event_t finish_event; /**< data send finish event*/ + rt_bool_t data_error; /**< data send error*/ + struct rt_mutex lock; +}; + +extern int rt_hw_mci_init(void); + +#endif // __DRV_SD_H__ diff --git a/bsp/lpc55sxx/Libraries/drivers/drv_spi.c b/bsp/lpc55sxx/Libraries/drivers/drv_spi.c new file mode 100644 index 000000000..53c4c3730 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/drivers/drv_spi.c @@ -0,0 +1,448 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-07-15 Magicoe The first version for LPC55S6x + */ +#include "drv_spi.h" + +#include "fsl_common.h" +#include "fsl_iocon.h" +#include "fsl_spi.h" + + +#if defined(BSP_USING_SPIBUS0) || \ + defined(BSP_USING_SPIBUS1) || \ + defined(BSP_USING_SPIBUS2) || \ + defined(BSP_USING_SPIBUS3) || \ + defined(BSP_USING_SPIBUS4) || \ + defined(BSP_USING_SPIBUS5) || \ + defined(BSP_USING_SPIBUS6) || \ + defined(BSP_USING_SPIBUS7) || \ + defined(BSP_USING_SPIBUS8) + +#if defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL + #error "Please don't define 'FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL'!" +#endif + +struct lpc_spi +{iteopuywqt[riouqwyyyyyyyyyyyy + SPI_Type *base; + struct rt_spi_configuration *cfg; + SYSCON_RSTn_t spi_rst; +}; + +struct lpc_sw_spi_cs +{ + rt_uint32_t pin; +}; + + +static uint32_t lpc_get_spi_freq(SPI_Type *base) +{ + uint32_t freq = 0; + +#if defined(BSP_USING_SPIBUS0) + if(base == SPI0) + { + freq = CLOCK_GetFreq(kCLOCK_Flexcomm0); + } +#endif + +#if defined(BSP_USING_SPIBUS1) + if(base == SPI1) + { + freq = CLOCK_GetFreq(kCLOCK_Flexcomm1); + } +#endif + +#if defined(BSP_USING_SPIBUS2) + if(base == SPI2) + { + freq = CLOCK_GetFreq(kCLOCK_Flexcomm2); + } +#endif + +#if defined(BSP_USING_SPIBUS3) + if(base == SPI3) + { + freq = CLOCK_GetFreq(kCLOCK_Flexcomm3); + } +#endif + +#if defined(BSP_USING_SPIBUS4) + if(base == SPI4) + { + freq = CLOCK_GetFreq(kCLOCK_Flexcomm4); + } +#endif + +#if defined(BSP_USING_SPIBUS5) + if(base == SPI5) + { + freq = CLOCK_GetFreq(kCLOCK_Flexcomm5); + } +#endif + +#if defined(BSP_USING_SPIBUS6) + if(base == SPI6) + { + freq = CLOCK_GetFreq(kCLOCK_Flexcomm6); + } +#endif + +#if defined(BSP_USING_SPIBUS7) + if(base == SPI7) + { + freq = CLOCK_GetFreq(kCLOCK_Flexcomm7); + } +#endif + + /* High Speed SPI - 50MHz */ +#if defined(BSP_USING_SPIBUS8) + if(base == SPI8) + { + freq = CLOCK_GetFreq(kCLOCK_HsLspi); + } +#endif + + return freq; +} + +static rt_err_t lpc_spi_init(SPI_Type *base, struct rt_spi_configuration *cfg) +{ + spi_master_config_t masterConfig = {0}; + + RT_ASSERT(cfg != RT_NULL); + + if(cfg->data_width != 8 && cfg->data_width != 16) + { + return (-RT_EINVAL); + } + + + SPI_MasterGetDefaultConfig(&masterConfig); + +#if defined(BSP_USING_SPIBUS8) + if(base == SPI8) + { + if(cfg->max_hz > 50*1000*1000) + { + cfg->max_hz = 50*1000*1000; + } + } +#else + if(cfg->max_hz > 12*1000*1000) + { + cfg->max_hz = 12*1000*1000; + } +#endif + + masterConfig.baudRate_Bps = cfg->max_hz; + + if(cfg->data_width == 8) + { + masterConfig.dataWidth = kSPI_Data8Bits; + } + else if(cfg->data_width == 16) + { + masterConfig.dataWidth = kSPI_Data16Bits; + } + + if(cfg->mode & RT_SPI_MSB) + { + masterConfig.direction = kSPI_MsbFirst; + } + else + { + masterConfig.direction = kSPI_LsbFirst; + } + + if(cfg->mode & RT_SPI_CPHA) + { + masterConfig.phase = kSPI_ClockPhaseSecondEdge; + } + else + { + masterConfig.phase = kSPI_ClockPhaseFirstEdge; + } + + if(cfg->mode & RT_SPI_CPOL) + { + masterConfig.polarity = kSPI_ClockPolarityActiveLow; + } + else + { + masterConfig.polarity = kSPI_ClockPolarityActiveHigh; + } + + SPI_MasterInit(base, &masterConfig, lpc_get_spi_freq(base)); + + return RT_EOK; +} + +rt_err_t lpc_spi_bus_attach_device(const char *bus_name, const char *device_name, rt_uint32_t pin) +{ + rt_err_t ret = RT_EOK; + + struct rt_spi_device *spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device)); + RT_ASSERT(spi_device != RT_NULL); + + struct lpc_sw_spi_cs *cs_pin = (struct lpc_sw_spi_cs *)rt_malloc(sizeof(struct lpc_sw_spi_cs)); + RT_ASSERT(cs_pin != RT_NULL); + + cs_pin->pin = pin; + rt_pin_mode(pin, PIN_MODE_OUTPUT); + rt_pin_write(pin, PIN_HIGH); + + ret = rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin); + + return ret; +} + +static rt_err_t spi_configure(struct rt_spi_device *device, struct rt_spi_configuration *cfg) +{ + rt_err_t ret = RT_EOK; + struct lpc_spi *spi = RT_NULL; + + RT_ASSERT(cfg != RT_NULL); + RT_ASSERT(device != RT_NULL); + + spi = (struct lpc_spi *)(device->bus->parent.user_data); + spi->cfg = cfg; + ret = lpc_spi_init(spi->base, cfg); + + return ret; +} + +#define SPISTEP(datalen) (((datalen) == 8) ? 1 : 2) +static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message) +{ + uint32_t length; + + RT_ASSERT(device != RT_NULL); + RT_ASSERT(device->bus != RT_NULL); + RT_ASSERT(device->bus->parent.user_data != RT_NULL); + + struct lpc_spi *spi = (struct lpc_spi *)(device->bus->parent.user_data); + struct lpc_sw_spi_cs *cs = device->parent.user_data; + + if(message->cs_take) + { + rt_pin_write(cs->pin, PIN_LOW); + } + + length = message->length; + const rt_uint8_t *txData = (uint8_t *)(message->send_buf); + rt_uint8_t *rxData = (uint8_t *)(message->recv_buf); + + rt_kprintf("*** spi send %d\r\n", length); + + while (length) + { + /* clear tx/rx errors and empty FIFOs */ + spi->base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK; + spi->base->FIFOSTAT |= SPI_FIFOSTAT_TXERR_MASK | SPI_FIFOSTAT_RXERR_MASK; + spi->base->FIFOWR = *txData | 0x07300000; + /* wait if TX FIFO of previous transfer is not empty */ + while ((spi->base->FIFOSTAT & SPI_FIFOSTAT_RXNOTEMPTY_MASK) == 0) { + } + if(rxData != NULL) + { + *rxData = spi->base->FIFORD; + rxData += SPISTEP(spi->cfg->data_width); + } + txData += SPISTEP(spi->cfg->data_width);; + length--; + } + + if(message->cs_release) + { + rt_pin_write(cs->pin, PIN_HIGH); + } + + return (message->length - length); +} + +#if defined(BSP_USING_SPIBUS0) +static struct lpc_spi spi0 = +{ + .base = SPI0 +}; +static struct rt_spi_bus spi0_bus = +{ + .parent.user_data = &spi0 +}; +#endif + +#if defined(BSP_USING_SPIBUS1) +static struct lpc_spi spi1 = +{ + .base = SPI1 +}; +static struct rt_spi_bus spi1_bus = +{ + .parent.user_data = &spi1 +}; +#endif + +#if defined(BSP_USING_SPIBUS2) +static struct lpc_spi spi2 = +{ + .base = SPI2 +}; +static struct rt_spi_bus spi2_bus = +{ + .parent.user_data = &spi2 +}; +#endif + +#if defined(BSP_USING_SPIBUS3) +static struct lpc_spi spi3 = +{ + .base = SPI3 +}; +static struct rt_spi_bus spi3_bus = +{ + .parent.user_data = &spi3 +}; +#endif + +#if defined(BSP_USING_SPIBUS4) +static struct lpc_spi spi4 = +{ + .base = SPI4 +}; +static struct rt_spi_bus spi4_bus = +{ + .parent.user_data = &spi4 +}; +#endif + +#if defined(BSP_USING_SPIBUS5) +static struct lpc_spi spi5 = +{ + .base = SPI5 +}; +static struct rt_spi_bus spi5_bus = +{ + .parent.user_data = &spi5 +}; +#endif + +#if defined(BSP_USING_SPIBUS6) +static struct lpc_spi spi6 = +{ + .base = SPI6 +}; +static struct rt_spi_bus spi6_bus = +{ + .parent.user_data = &spi6 +}; +#endif + +#if defined(BSP_USING_SPIBUS7) +static struct lpc_spi spi7 = +{ + .base = SPI7 +}; +static struct rt_spi_bus spi7_bus = +{ + .parent.user_data = &spi7 +}; +#endif + +#if defined(BSP_USING_SPIBUS8) +static struct lpc_spi spi8 = +{ + .base = SPI8 +}; +static struct rt_spi_bus spi8_bus = +{ + .parent.user_data = &spi8 +}; +#endif + + +static struct rt_spi_ops lpc_spi_ops = +{ + .configure = spi_configure, + .xfer = spixfer +}; + +int rt_hw_spi_init(void) +{ +#if defined(BSP_USING_SPIBUS0) + CLOCK_AttachClk(kFRO12M_to_FLEXCOMM0); + RESET_PeripheralReset(kFC0_RST_SHIFT_RSTn); + spi0.cfg = RT_NULL; + rt_spi_bus_register(&spi0_bus, "spi0", &lpc_spi_ops); +#endif + +#if defined(BSP_USING_SPIBUS1) + CLOCK_AttachClk(kFRO12M_to_FLEXCOMM1); + RESET_PeripheralReset(kFC1_RST_SHIFT_RSTn); + + spi1.cfg = RT_NULL; + rt_spi_bus_register(&spi1_bus, "spi1", &lpc_spi_ops); +#endif + +#if defined(BSP_USING_SPIBUS2) + CLOCK_AttachClk(kFRO12M_to_FLEXCOMM2); + RESET_PeripheralReset(kFC2_RST_SHIFT_RSTn); + spi2.cfg = RT_NULL; + rt_spi_bus_register(&spi2_bus, "spi2", &lpc_spi_ops); +#endif + +#if defined(BSP_USING_SPIBUS3) + CLOCK_AttachClk(kFRO12M_to_FLEXCOMM3); + RESET_PeripheralReset(kFC3_RST_SHIFT_RSTn); + spi3.cfg = RT_NULL; + rt_spi_bus_register(&spi3_bus, "spi3", &lpc_spi_ops); +#endif + +#if defined(BSP_USING_SPIBUS4) + CLOCK_AttachClk(kFRO12M_to_FLEXCOMM4); + RESET_PeripheralReset(kFC4_RST_SHIFT_RSTn); + spi4.cfg = RT_NULL; + rt_spi_bus_register(&spi4_bus, "spi4", &lpc_spi_ops); +#endif + +#if defined(BSP_USING_SPIBUS5) + CLOCK_AttachClk(kFRO12M_to_FLEXCOMM5); + RESET_PeripheralReset(kFC5_RST_SHIFT_RSTn); + spi5.cfg = RT_NULL; + rt_spi_bus_register(&spi5_bus, "spi5", &lpc_spi_ops); +#endif + +#if defined(BSP_USING_SPIBUS6) + CLOCK_AttachClk(kFRO12M_to_FLEXCOMM6); + RESET_PeripheralReset(kFC6_RST_SHIFT_RSTn); + spi6.cfg = RT_NULL; + rt_spi_bus_register(&spi6_bus, "spi6", &lpc_spi_ops); +#endif + +#if defined(BSP_USING_SPIBUS7) + CLOCK_AttachClk(kFRO12M_to_FLEXCOMM7); + RESET_PeripheralReset(kFC7_RST_SHIFT_RSTn); + spi7.cfg = RT_NULL; + rt_spi_bus_register(&spi7_bus, "spi7", &lpc_spi_ops); +#endif + +#if defined(BSP_USING_SPIBUS8) + CLOCK_AttachClk(kMAIN_CLK_to_HSLSPI); + RESET_PeripheralReset(kHSLSPI_RST_SHIFT_RSTn); + spi8.cfg = RT_NULL; + spi8.spi_rst = kHSLSPI_RST_SHIFT_RSTn; + rt_spi_bus_register(&spi8_bus, "spi8", &lpc_spi_ops); +#endif + + return RT_EOK; +} + +INIT_BOARD_EXPORT(rt_hw_spi_init); + +#endif diff --git a/bsp/lpc55sxx/Libraries/drivers/drv_spi.h b/bsp/lpc55sxx/Libraries/drivers/drv_spi.h new file mode 100644 index 000000000..6aeb91256 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/drivers/drv_spi.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __DRV_SPI_H__ +#define __DRV_SPI_H__ + +#include +#include + +int rt_hw_spi_init(void); +rt_err_t lpc_spi_bus_attach_device(const char *bus_name, const char *device_name, rt_uint32_t pin); + +#endif diff --git a/bsp/lpc55sxx/Libraries/drivers/drv_uart.c b/bsp/lpc55sxx/Libraries/drivers/drv_uart.c new file mode 100644 index 000000000..d9c325971 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/drivers/drv_uart.c @@ -0,0 +1,437 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-07-15 Magicoe The first version for LPC55S6x + */ + +#include +#include "drv_uart.h" + +#include "fsl_usart.h" +#include "fsl_common.h" +#include "fsl_iocon.h" + +#ifdef RT_USING_SERIAL + +#if defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL +#error "Please don't define 'FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL'!" +#endif + +#if !defined(BSP_USING_UART0) && \ + !defined(BSP_USING_UART1) && \ + !defined(BSP_USING_UART2) && \ + !defined(BSP_USING_UART3) && \ + !defined(BSP_USING_UART4) && \ + !defined(BSP_USING_UART5) && \ + !defined(BSP_USING_UART6) && \ + !defined(BSP_USING_UART7) +#error "Please define at least one UARTx" +#endif + +#include + +/* lpc uart driver */ +struct lpc_uart +{ + USART_Type *uart_base; + IRQn_Type irqn; + clock_name_t clock_src; + + struct rt_serial_device *serial; + char *device_name; +}; + +static void uart_isr(struct rt_serial_device *serial); + +#if defined(BSP_USING_UART0) +struct rt_serial_device serial0; + +void FLEXCOMM0_IRQHandler(void) +{ + uart_isr(&serial0); +} + +#endif /* BSP_USING_UART1 */ + +#if defined(BSP_USING_UART1) +struct rt_serial_device serial1; + +void FLEXCOMM1_IRQHandler(void) +{ + uart_isr(&serial1); +} + +#endif /* BSP_USING_UART1 */ + +#if defined(BSP_USING_UART2) +struct rt_serial_device serial2; + +void FLEXCOMM2_IRQHandler(void) +{ + uart_isr(&serial2); +} + +#endif /* BSP_USING_UART2 */ + +#if defined(BSP_USING_UART3) +struct rt_serial_device serial3; + +void FLEXCOMM3_IRQHandler(void) +{ + uart_isr(&serial3); +} + +#endif /* BSP_USING_UART3 */ + +#if defined(BSP_USING_UART4) +struct rt_serial_device serial4; + +void FLEXCOMM4_IRQHandler(void) +{ + uart_isr(&serial4); +} +#endif /* BSP_USING_UART4 */ + +#if defined(BSP_USING_UART5) +struct rt_serial_device serial5; + +void FLEXCOMM5_IRQHandler(void) +{ + uart_isr(&serial5); +} + +#endif /* BSP_USING_UART5 */ + +#if defined(BSP_USING_UART6) +struct rt_serial_device serial6; + +void FLEXCOMM6_IRQHandler(void) +{ + uart_isr(&serial6); +} + +#endif /* BSP_USING_UART6 */ + +#if defined(BSP_USING_UART7) +struct rt_serial_device serial7; + +void FLEXCOMM7_IRQHandler(void) +{ + uart_isr(&serial7); +} + +#endif /* BSP_USING_UART7 */ + +static const struct lpc_uart uarts[] = +{ +#ifdef BSP_USING_UART0 + { + USART0, + FLEXCOMM0_IRQn, + kCLOCK_Flexcomm0, + + &serial0, + "uart", + }, +#endif +#ifdef BSP_USING_UART1 + { + USART1, + FLEXCOMM1_IRQn, + kCLOCK_Flexcomm1, + + &serial1, + "uart1", + }, +#endif +#ifdef BSP_USING_UART2 + { + USART2, + FLEXCOMM2_IRQn, + kCLOCK_Flexcomm2, + + &serial2, + "uart2", + }, +#endif +#ifdef BSP_USING_UART3 + { + USART3, + FLEXCOMM3_IRQn, + kCLOCK_Flexcomm3, + + &serial3, + "uart3", + }, +#endif +#ifdef BSP_USING_UART4 + { + USART4, + FLEXCOMM4_IRQn, + kCLOCK_Flexcomm4, + + &serial4, + "uart4", + }, +#endif +#ifdef BSP_USING_UART5 + { + USART5, + FLEXCOMM5_IRQn, + kCLOCK_Flexcomm5, + + &serial5, + "uart5", + }, +#endif +#ifdef BSP_USING_UART6 + { + USART6, + FLEXCOMM6_IRQn, + kCLOCK_Flexcomm6, + + &serial6, + "uart6", + }, +#endif +#ifdef BSP_USING_UART7 + { + USART7, + FLEXCOMM7_IRQn, + kCLOCK_Flexcomm7, + + &serial7, + "uart7", + }, +#endif +}; + +/** +* @brief UART MSP Initialization +* This function configures the hardware resources used in this example: +* - Peripheral's clock enable +* - Peripheral's GPIO Configuration +* - NVIC configuration for UART interrupt request enable +* @param huart: UART handle pointer +* @retval None +*/ +void lpc_uart_gpio_init(struct lpc_uart *uart) +{ + if (uart->uart_base != RT_NULL) + { +#ifdef BSP_USING_UART0 + /* attach 12 MHz clock to FLEXCOMM0 (debug console) */ + CLOCK_AttachClk(kFRO12M_to_FLEXCOMM0); +#endif +#ifdef BSP_USING_UART1 + /* attach 12 MHz clock to FLEXCOMM1 (debug console) */ + CLOCK_AttachClk(kFRO12M_to_FLEXCOMM1); +#endif +#ifdef BSP_USING_UART2 + /* attach 12 MHz clock to FLEXCOMM2 (debug console) */ + CLOCK_AttachClk(kFRO12M_to_FLEXCOMM2); +#endif +#ifdef BSP_USING_UART3 + /* attach 12 MHz clock to FLEXCOMM3 (debug console) */ + CLOCK_AttachClk(kFRO12M_to_FLEXCOMM3); +#endif +#ifdef BSP_USING_UART4 + /* attach 12 MHz clock to FLEXCOMM4 (debug console) */ + CLOCK_AttachClk(kFRO12M_to_FLEXCOMM4); +#endif +#ifdef BSP_USING_UART5 + /* attach 12 MHz clock to FLEXCOMM5 (debug console) */ + CLOCK_AttachClk(kFRO12M_to_FLEXCOMM5); +#endif +#ifdef BSP_USING_UART6 + /* attach 12 MHz clock to FLEXCOMM6 (debug console) */ + CLOCK_AttachClk(kFRO12M_to_FLEXCOMM6); +#endif +#ifdef BSP_USING_UART7 + /* attach 12 MHz clock to FLEXCOMM7 (debug console) */ + CLOCK_AttachClk(kFRO12M_to_FLEXCOMM7); +#endif + } + else + { + RT_ASSERT(RT_NULL); + } +} + + +static rt_err_t lpc_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +{ + struct lpc_uart *uart; + usart_config_t config; + + RT_ASSERT(serial != RT_NULL); + RT_ASSERT(cfg != RT_NULL); + + uart = (struct lpc_uart *)serial->parent.user_data; + + lpc_uart_gpio_init(uart); + + /* + * config.baudRate_Bps = 115200U; + * config.parityMode = kUSART_ParityDisabled; + * config.stopBitCount = kUSART_OneStopBit; + * config.loopback = false; + * config.enableTx = false; + * config.enableRx = false; + */ + USART_GetDefaultConfig(&config); + config.baudRate_Bps = cfg->baud_rate; + + switch (cfg->data_bits) + { + case DATA_BITS_7: + config.bitCountPerChar = kUSART_7BitsPerChar; + break; + + default: + config.bitCountPerChar = kUSART_8BitsPerChar; + break; + } + + switch (cfg->stop_bits) + { + case STOP_BITS_2: + config.stopBitCount = kUSART_TwoStopBit; + break; + default: + config.stopBitCount = kUSART_OneStopBit; + break; + } + + switch (cfg->parity) + { + case PARITY_ODD: + config.parityMode = kUSART_ParityOdd; + break; + case PARITY_EVEN: + config.parityMode = kUSART_ParityEven; + break; + default: + config.parityMode = kUSART_ParityDisabled; + break; + } + + config.enableTx = true; + config.enableRx = true; + + USART_Init(uart->uart_base, &config, CLOCK_GetFreq(uart->clock_src)); + + return RT_EOK; +} + +static rt_err_t lpc_control(struct rt_serial_device *serial, int cmd, void *arg) +{ + struct lpc_uart *uart; + + RT_ASSERT(serial != RT_NULL); + uart = (struct lpc_uart *)serial->parent.user_data; + + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + /* disable rx irq */ + USART_DisableInterrupts(uart->uart_base, kUSART_RxLevelInterruptEnable); + DisableIRQ(uart->irqn); + break; + case RT_DEVICE_CTRL_SET_INT: + /* enable rx irq */ + USART_EnableInterrupts(uart->uart_base, kUSART_RxLevelInterruptEnable); + EnableIRQ(uart->irqn); + break; + } + + return RT_EOK; +} + +static int lpc_putc(struct rt_serial_device *serial, char ch) +{ + struct lpc_uart *uart; + + uart = (struct lpc_uart *)serial->parent.user_data; + + while (!(kUSART_TxFifoNotFullFlag & USART_GetStatusFlags(uart->uart_base))); + + USART_WriteByte(uart->uart_base, ch); + + return 1; +} + +static int lpc_getc(struct rt_serial_device *serial) +{ + struct lpc_uart *uart; + + uart = (struct lpc_uart *)serial->parent.user_data; + if (kUSART_RxFifoNotEmptyFlag & USART_GetStatusFlags(uart->uart_base)) + { + return USART_ReadByte(uart->uart_base); + } + else + { + return -1; + } +} + +/** + * Uart common interrupt process. This need add to uart ISR. + * + * @param serial serial device + */ +static void uart_isr(struct rt_serial_device *serial) +{ + struct lpc_uart *uart; + + RT_ASSERT(serial != RT_NULL); + + uart = (struct lpc_uart *) serial->parent.user_data; + RT_ASSERT(uart != RT_NULL); + + /* enter interrupt */ + rt_interrupt_enter(); + + /* UART in mode Receiver -------------------------------------------------*/ + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +static const struct rt_uart_ops lpc_uart_ops = +{ + lpc_configure, + lpc_control, + lpc_putc, + lpc_getc, +}; + +int rt_hw_uart_init(void) +{ + struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; + int i; + + for (i = 0; i < sizeof(uarts) / sizeof(uarts[0]); i++) + { + uarts[i].serial->ops = &lpc_uart_ops; + uarts[i].serial->config = config; + + /* register UART device */ + rt_hw_serial_register(uarts[i].serial, + uarts[i].device_name, + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + (void *)&uarts[i]); + } + + return 0; +} + +INIT_BOARD_EXPORT(rt_hw_uart_init); + +#endif /*BSP_USING_SERIAL */ diff --git a/bsp/lpc55sxx/Libraries/drivers/drv_uart.h b/bsp/lpc55sxx/Libraries/drivers/drv_uart.h new file mode 100644 index 000000000..603e2a248 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/drivers/drv_uart.h @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-07-15 Magicoe The first version for LPC55S6x + */ + +#ifndef __DRV_UART_H__ +#define __DRV_UART_H__ + +extern int rt_hw_uart_init(void); + + +#endif /* __DRV_UART_H__ */ diff --git a/bsp/lpc55sxx/Libraries/drivers/drv_wdt.c b/bsp/lpc55sxx/Libraries/drivers/drv_wdt.c new file mode 100644 index 000000000..65150a42f --- /dev/null +++ b/bsp/lpc55sxx/Libraries/drivers/drv_wdt.c @@ -0,0 +1,241 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-04-20 tyustli the first version. + * 2019-07-15 Magicoe The first version for LPC55S6x, timeout unit is S not mS + * + */ +#include + +#ifdef BSP_USING_WDT + +#if !defined(BSP_USING_WDT) +#error "Please define at least one BSP_USING_WDOGx" +#endif + +#define LOG_TAG "drv.wdt" +#include + +#include "drv_wdt.h" +#include +#include "rtdevice.h" + +#if defined(BSP_USING_WDT) +#include "fsl_wwdt.h" + +static rt_watchdog_t lpc_watchdog; +static wwdt_config_t WWDT1_config = +{ + /* Enable the watch dog */ + .enableWwdt = true, + /* Disable the watchdog timeout reset */ + .enableWatchdogReset = false, + /* Disable the watchdog protection for updating the timeout value */ + .enableWatchdogProtect = false, + /* Windowing is not in effect */ + .windowValue = 0xFFFFFFU, + /* Set the timeout value to the max */ + .timeoutValue = 0xFFFFFFU, + /* No warning is provided */ + .warningValue = 0, + /* Set clock frequency. */ + .clockFreq_Hz = 0U, +}; + +void WDT_BOD_IRQHandler(void) +{ + uint32_t wdtStatus = WWDT_GetStatusFlags(WWDT); + + /* The chip will reset before this happens */ + if (wdtStatus & kWWDT_TimeoutFlag) + { + /* A watchdog feed didn't occur prior to window timeout */ + /* Stop WDT */ + WWDT_Disable(WWDT); + WWDT_ClearStatusFlags(WWDT, kWWDT_TimeoutFlag); + /* Needs restart */ + WWDT_Enable(WWDT); + } + + /* Handle warning interrupt */ + if (wdtStatus & kWWDT_WarningFlag) + { + /* A watchdog feed didn't occur prior to warning timeout */ + WWDT_ClearStatusFlags(WWDT, kWWDT_WarningFlag); + /* User code. User can do urgent case before timeout reset. + * IE. user can backup the ram data or ram log to flash. + * the period is set by config.warningValue, user need to + * check the period between warning interrupt and timeout. + */ + } +} + +static rt_err_t lpc_wwdt_close(rt_watchdog_t *wdt) +{ + rt_uint32_t level; + WWDT_Type *base; + base = (WWDT_Type *)wdt->parent.user_data; + + level = rt_hw_interrupt_disable(); + WWDT_Disable(base); + rt_hw_interrupt_enable(level); + + return RT_EOK; +} + +static rt_err_t lpc_wwdt_open(rt_watchdog_t *wdt, rt_uint16_t oflag) +{ + WWDT_Type *base; + base = (WWDT_Type *)wdt->parent.user_data; + rt_uint32_t level; + + level = rt_hw_interrupt_disable(); + WWDT_Enable(base); + rt_hw_interrupt_enable(level); + + return RT_EOK; +} + +static rt_err_t lpc_wwdt_init(rt_watchdog_t *wdt) +{ + WWDT_Type *base; + base = (WWDT_Type *)wdt->parent.user_data; + + /* Enable FRO 1M clock for WWDT module. */ + SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK; + /* Set clock divider for WWDT clock source. */ + CLOCK_SetClkDiv(kCLOCK_DivWdtClk, 1U, true); + + WWDT_GetDefaultConfig(&WWDT1_config); + + /* + * Set watchdog feed time constant to approximately 4s + * Set watchdog warning time to 512 ticks after feed time constant + * Set watchdog window time to 1s + */ + /* The WDT divides the input frequency into it by 4 */ + WWDT1_config.timeoutValue = (CLOCK_GetFreq(kCLOCK_WdtClk) / 4) * 4; + WWDT1_config.warningValue = 512; + WWDT1_config.windowValue = (CLOCK_GetFreq(kCLOCK_WdtClk) / 4) * 1; + /* Configure WWDT to reset on timeout */ + WWDT1_config.enableWatchdogReset = true; + /* Setup watchdog clock frequency(Hz). */ + WWDT1_config.clockFreq_Hz = CLOCK_GetFreq(kCLOCK_WdtClk); + + WWDT_Init(base, &WWDT1_config); + lpc_wwdt_close(wdt); + + return RT_EOK; +} + +static rt_err_t lpc_wwdt_refresh(rt_watchdog_t *wdt) +{ + WWDT_Type *base; + base = (WWDT_Type *)wdt->parent.user_data; + + rt_uint32_t level; + + level = rt_hw_interrupt_disable(); + WWDT_Refresh(base); + rt_hw_interrupt_enable(level); + + return RT_EOK; +} + +/** + * @function control wdog + * + * @param + * wdt whick wdog used + * cmd control wdog options + * args argument of conrtol + * @retval rt_err_t the status of control result + * + * @attention wdog1 is can not get left time(register not exist) and wdogs unit is seconds + * + */ +static rt_err_t lpc_wwdt_control(rt_watchdog_t *wdt, int cmd, void *args) +{ + RT_ASSERT(wdt != NULL); + + WWDT_Type *base; + base = (WWDT_Type *)wdt->parent.user_data; + + switch(cmd) + { + case RT_DEVICE_CTRL_WDT_GET_TIMEOUT: + { + *(uint16_t *)args = WWDT1_config.timeoutValue; + } + break; + case RT_DEVICE_CTRL_WDT_SET_TIMEOUT: + { + RT_ASSERT(*(uint16_t *)args != 0); + + WWDT1_config.timeoutValue = (CLOCK_GetFreq(kCLOCK_WdtClk) / 4) * (*(uint16_t *)args) * 2; + WWDT1_config.warningValue = 512; + WWDT1_config.windowValue = (CLOCK_GetFreq(kCLOCK_WdtClk) / 4) * (*(uint16_t *)args) * 2 / 4; + + base->TC = WWDT_TC_COUNT(WWDT1_config.timeoutValue); + base->WINDOW = WWDT_WINDOW_WINDOW(WWDT1_config.windowValue); + base->WARNINT = WWDT_WARNINT_WARNINT(WWDT1_config.warningValue); + WWDT_Refresh(base); + + lpc_wwdt_close(wdt); + } + break; + case RT_DEVICE_CTRL_WDT_KEEPALIVE: + { + lpc_wwdt_refresh(wdt); + } + break; + case RT_DEVICE_CTRL_WDT_START: + { + lpc_wwdt_open(wdt, *(rt_uint32_t *)args); + } + break; + case RT_DEVICE_CTRL_WDT_STOP: + { + lpc_wwdt_close(wdt); + } + break; + default: + return RT_EINVAL; + } + + return RT_EOK; +} + +static struct rt_watchdog_ops lpc_wwdt_ops = +{ + .init = lpc_wwdt_init, + .control = lpc_wwdt_control, +}; + +#endif /* BSP_USING_WDT */ + +int rt_hw_wdt_init(void) +{ + rt_err_t ret = RT_EOK; + +#if defined (BSP_USING_WDT) + lpc_watchdog.ops = &lpc_wwdt_ops; + + ret = rt_hw_watchdog_register(&lpc_watchdog, "wdog1", RT_DEVICE_FLAG_RDWR, WWDT); + + if (ret != RT_EOK) + { + LOG_E("rt device register failed %d\n", ret); + } +#endif /* BSP_USING_WDT */ + + return ret; +} + +INIT_DEVICE_EXPORT(rt_hw_wdt_init); + +#endif /* BSP_USING_WDT */ diff --git a/bsp/lpc55sxx/Libraries/drivers/drv_wdt.h b/bsp/lpc55sxx/Libraries/drivers/drv_wdt.h new file mode 100644 index 000000000..2517fb81d --- /dev/null +++ b/bsp/lpc55sxx/Libraries/drivers/drv_wdt.h @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-04-20 Lee the first version. + * 2019-07-15 Magicoe The first version for LPC55S6x + */ + +#ifndef DRV_WDT_H__ +#define DRV_WDT_H__ + +#include + +int rt_hw_hwtimer_init(void); + +#endif /* __DRV_WDT_H__ */ + diff --git a/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/.config b/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/.config new file mode 100644 index 000000000..fe6c72013 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/.config @@ -0,0 +1,419 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# +CONFIG_SOC_LPC55S6x=y + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=100 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +CONFIG_RT_USING_TIMER_SOFT=y +CONFIG_RT_TIMER_THREAD_PRIO=4 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=512 +CONFIG_RT_DEBUG=y +# CONFIG_RT_DEBUG_COLOR is not set +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +# CONFIG_RT_USING_MEMHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMTRACE is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart" +CONFIG_RT_VER_NUM=0x40002 +# CONFIG_RT_USING_CPU_FFS is not set +CONFIG_ARCH_ARM_CORTEX_FPU=y +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 + +# +# C++ features +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Command shell +# +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_CMD_SIZE=80 +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_USING_MSH_DEFAULT=y +# CONFIG_FINSH_USING_MSH_ONLY is not set +CONFIG_FINSH_ARG_MAX=10 + +# +# Device virtual file system +# +CONFIG_RT_USING_DFS=y +CONFIG_DFS_USING_WORKDIR=y +CONFIG_DFS_FILESYSTEMS_MAX=2 +CONFIG_DFS_FILESYSTEM_TYPES_MAX=2 +CONFIG_DFS_FD_MAX=16 +# CONFIG_RT_USING_DFS_MNTTABLE is not set +# CONFIG_RT_USING_DFS_ELMFAT is not set +CONFIG_RT_USING_DFS_DEVFS=y +# CONFIG_RT_USING_DFS_ROMFS is not set +# CONFIG_RT_USING_DFS_RAMFS is not set +# CONFIG_RT_USING_DFS_UFFS is not set +# CONFIG_RT_USING_DFS_JFFS2 is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_PIPE_BUFSZ=512 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_SERIAL_USING_DMA=y +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_CAN is not set +CONFIG_RT_USING_HWTIMER=y +# CONFIG_RT_USING_CPUTIME is not set +CONFIG_RT_USING_I2C=y +CONFIG_RT_USING_I2C_BITOPS=y +CONFIG_RT_USING_PIN=y +CONFIG_RT_USING_ADC=y +CONFIG_RT_USING_PWM=y +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +CONFIG_RT_USING_RTC=y +# CONFIG_RT_USING_ALARM is not set +# CONFIG_RT_USING_SOFT_RTC is not set +CONFIG_RT_USING_SDIO=y +CONFIG_RT_SDIO_STACK_SIZE=512 +CONFIG_RT_SDIO_THREAD_PRIORITY=15 +CONFIG_RT_MMCSD_STACK_SIZE=1024 +CONFIG_RT_MMCSD_THREAD_PREORITY=22 +CONFIG_RT_MMCSD_MAX_PARTITION=16 +# CONFIG_RT_SDIO_DEBUG is not set +CONFIG_RT_USING_SPI=y +# CONFIG_RT_USING_QSPI is not set +# CONFIG_RT_USING_SPI_MSD is not set +# CONFIG_RT_USING_SFUD is not set +# CONFIG_RT_USING_ENC28J60 is not set +# CONFIG_RT_USING_SPI_WIFI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_WIFI is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# POSIX layer and C standard library +# +CONFIG_RT_USING_LIBC=y +# CONFIG_RT_USING_PTHREADS is not set +CONFIG_RT_USING_POSIX=y +# CONFIG_RT_USING_POSIX_MMAP is not set +# CONFIG_RT_USING_POSIX_TERMIOS is not set +# CONFIG_RT_USING_POSIX_AIO is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Network +# + +# +# Socket abstraction layer +# +# CONFIG_RT_USING_SAL is not set + +# +# Network interface device +# +# CONFIG_RT_USING_NETDEV is not set + +# +# light weight TCP/IP stack +# +# CONFIG_RT_USING_LWIP is not set + +# +# AT commands +# +# CONFIG_RT_USING_AT is not set + +# +# VBUS(Virtual Software BUS) +# +# CONFIG_RT_USING_VBUS is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_WIZNET is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOTKIT is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_libsodium is not set +# CONFIG_PKG_USING_TINYCRYPT is not set + +# +# language packages +# +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set + +# +# multimedia packages +# +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ADBD is not set + +# +# system packages +# +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_CMSIS is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_THREAD_POOL is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_SENSORS_DRIVERS is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_WM_LIBRARIES is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_AT24CXX is not set + +# +# miscellaneous packages +# +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_NNOM is not set +CONFIG_SOC_LPC55S6X_SERIES=y + +# +# Hardware Drivers Config +# +CONFIG_SOC_LPC55S6X=y + +# +# On-chip Peripheral Drivers +# +# CONFIG_BSP_USING_DMA is not set +CONFIG_BSP_USING_PIN=y +CONFIG_BSP_USING_UART=y +CONFIG_BSP_USING_UART0=y +# CONFIG_HW_UART0_BAUDRATE_9600 is not set +CONFIG_HW_UART0_BAUDRATE_115200=y +# CONFIG_BSP_USING_UART2 is not set +CONFIG_BSP_USING_I2C=y +# CONFIG_BSP_USING_I2C1 is not set +CONFIG_BSP_USING_I2C4=y +CONFIG_HW_I2C4_BAUDRATE_100kHZ=y +# CONFIG_HW_I2C4_BAUDRATE_400kHZ is not set +CONFIG_BSP_USING_SPI=y +# CONFIG_BSP_USING_SPI3 is not set +CONFIG_BSP_USING_SPI8=y +CONFIG_BSP_USING_ADC=y +CONFIG_BSP_USING_ADC0_CH0=y +# CONFIG_BSP_USING_ADC0_CH1 is not set +CONFIG_BSP_USING_SDIO=y +CONFIG_BSP_USING_RTC=y +# CONFIG_BSP_USING_WDT is not set +CONFIG_BSP_USING_HWTIMER=y +CONFIG_BSP_USING_CTIMER0=y +# CONFIG_BSP_USING_CTIMER1 is not set +# CONFIG_BSP_USING_CTIMER3 is not set +# CONFIG_BSP_USING_CTIMER4 is not set +CONFIG_BSP_USING_PWM=y +CONFIG_BSP_USING_CTIMER2_MAT0=y +# CONFIG_BSP_USING_CTIMER2_MAT1 is not set +# CONFIG_BSP_USING_CTIMER2_MAT2 is not set + +# +# Onboard Peripheral Drivers +# +CONFIG_BSP_USING_LED=y +CONFIG_BSP_USING_KEY=y +CONFIG_BSP_USING_MMA8562=y +CONFIG_BSP_USING_MMA8562I2C="i2c4" + +# +# Board extended module Drivers +# diff --git a/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/Kconfig b/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/Kconfig new file mode 100644 index 000000000..39775bd31 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/Kconfig @@ -0,0 +1,26 @@ +mainmenu "RT-Thread Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../../.." + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +config SOC_LPC55S6x + bool + select ARCH_ARM_CORTEX_M33 + default y + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" +source "../libraries/Kconfig" +source "board/Kconfig" diff --git a/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/README.md b/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/README.md new file mode 100644 index 000000000..647b7839b --- /dev/null +++ b/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/README.md @@ -0,0 +1,214 @@ +# LPC55S69-EVK æ¿çº§æ”¯æŒåŒ… + +## 1. 简介(Introduction) + +LPC55S69 是由æ©æ™ºæµ¦NXPåŠå¯¼ä½“推出的基于Cortex-M33内核的高性能å•ç‰‡æœº +包括如下硬件特性： + +| 硬件 | æè¿° | +| -- | -- | +|芯片型å·| LPC556x/LPC55S6x 全系列 | +|CPU| Cortex-M33 Dual Core, with FPU | +|主频| 150MHz | +|基本外设| 8个Flexcomm(ä»»æ„é…置为USART/SPI/I2C/I2S) / 1个50MHz SPI / åŒUSB(1高1全，支æŒä¸»ä»Ž) | +|特色| PowerQuad DSPå处ç†å™¨ / 安全外设:PRINCE/PUF/CASPER/AES-256/HASH | + +## 2. 硬件开å‘环境(Hardware development system) + +å¼€å‘æ¿ï¼ˆEVK） + +![å¼€å‘æ¿ç¤ºæ„图](./figures/board.png) + + + +## 3. 编译说明 + + +| 环境 | 说明 | +| ------------ | ------------------------------------------------------------ | +| PCæ“作系统 | Linux/MacOS/Windows | +| 编译器 | arm-none-eabi-gcc version 6.3.1 20170620 (release)/armcc/iar | +| 构建工具 | scons/mdk5/iar | +| ä¾èµ–软件环境 | Env工具/(MDK或IAR或arm-none-eabi-gcc)/git/调试器驱动 | + +1) 下载æºç  + +```bash + git clone https://github.com/RT-Thread/rt-thread.git +``` + +2) é…置工程并准备env + +（Linux/Mac） + +```bash + cd rt-thread/bsp/lpc55s69_evk + scons --menuconfig + source ~/.env/env.sh + pkgs --upgrade +``` + +（Windows） + +>在[RT-Thread官网][1]下载ENV工具包 + +3) é…ç½®èŠ¯ç‰‡åž‹å· + +（Linux/Mac） + +```bash + scons --menuconfig +``` + +（Windows(ENV环境中)） + +```bash + menuconfig +``` + +在menuconfig页é¢é…置并选择对应的芯片型å·ï¼Œè‹¥å¼€å‘环境为MDK/IAR，则需è¦ç”Ÿæˆå·¥ç¨‹ + +4) 生æˆå·¥ç¨‹(Mac/Linux下请跳过此步骤) + +（Windows IAR） + +```bash + SET RTT_CC=iar + scons --target=iar -s +``` + +（Windows MDK5）* + +```bash + scons --target=mdk5 -s +``` + +*该æ¿çº§æ”¯æŒåŒ…ä¸æ”¯æŒç”Ÿæˆmdk4的工程 + +**MDK 与 IAR 在生æˆå®Œæˆå·¥ç¨‹ä¹‹åŽä¸€å®šè¦åœ¨å·¥ç¨‹ä¸­æ‰‹åŠ¨é€‰æ‹©ä¸€æ¬¡èŠ¯ç‰‡ä¿¡å·ï¼Œå¦åˆ™ä¼šäº§ç”Ÿä¸¥é‡ç¼–译错误** + + + +5) 编译 + +使用MDK或IAR请å‚è§å¯¹åº”教程 + +（Windows arm-none-eabi-gcc） +使用以下指令设置gcc路径 + +```bash + SET RTT_EXEC_PATH=[GCC路径] +``` + +（Linux/Mac arm-none-eabi-gcc） +使用以下指令设置gcc路径 + +```bash + export RTT_EXEC_PATH=[GCC路径] +``` + +编译（WindowsLinux/Mac arm-none-eabi-gcc） + +```bash + scons -j4 +``` + +出现下列信æ¯å³ä¸ºç¼–译æˆåŠŸ + +```bash + LINK rtthread-lpc55s69.elf + arm-none-eabi-objcopy -O binary rtthread-lpc55s6x.elf rtthread.bin + arm-none-eabi-size rtthread-lpc55s69.elf + text data bss dec hex filename + 41596 356 1456 43408 a990 rtthread-lpc55s6x.elf + scons: done building targets. +``` + + +如果编译正确无误，会产生rtthread-lpc55s6x.elfã€rtthread.bin文件。其中rtthread.bin为二进制固件 + +## 3. 烧写åŠæ‰§è¡Œ + +烧写å¯ä»¥ä½¿ç”¨ä»¿çœŸå™¨ ISP等多ç§æ–¹å¼ 此处ä¸å†èµ˜è¿° + +### 3.1 è¿è¡Œç»“æžœ + +如果编译 & 烧写无误，会在Flexcomm0串å£*上看到RT-Threadçš„å¯åŠ¨logoä¿¡æ¯ï¼š + +```bash + \ | / +- RT - Thread Operating System + / | \ 4.0.1 build Jul 30 2019 + 2006 - 2019 Copyright by rt-thread team +uising armclang, version: 6120001 +msh /> +``` + +*é»˜è®¤ä¸²å£ + + +## 4. 驱动支æŒæƒ…况åŠè®¡åˆ’ + +| 驱动 | 支æŒæƒ…况 | 备注 | +| ---------- | :------: | :--------------------------: | +| UART | æ”¯æŒ | UART0/2 | +| GPIO | æ”¯æŒ | 自动根æ®èŠ¯ç‰‡åž‹å·é€‰æ‹©å¼•è„šå¸ƒå±€ | +| SPI | æ”¯æŒ | 支æŒHigh Speed SPI | +| USB Device | ä¸æ”¯æŒ | æš‚ä¸æ”¯æŒ | +| USB Host | ä¸æ”¯æŒ | æš‚ä¸æ”¯æŒ | +| Windowed WatchDog | ä¸æ”¯æŒ | æ”¯æŒ | +| ADC | ä¸æ”¯æŒ | æš‚ä¸æ”¯æŒ | +| I2C | æ”¯æŒ | å¯é…åˆMMA8562 | +| I2C Sensor | æ”¯æŒ | 获å–æ¿ä¸ŠMMA8562åŠ é€Ÿåº¦ä¼ æ„Ÿå™¨æ•°æ® | +| RTC | æ”¯æŒ | RTC时钟自动é…ç½® | +| SDIO | æ”¯æŒ | æ“作SDå¡ | +| I2S | ä¸æ”¯æŒ | æš‚ä¸æ”¯æŒ | + + +### 4.1 IO在æ¿çº§æ”¯æŒåŒ…中的映射情况 + +| PIOå· | æ¿çº§åŒ…中的定义 | +| -- | -- | +| PIO0_29 | Flexcomm0 USART RXD | +| PIO0_30 | Flexcomm0 USART TXD | +| | | +| PIO0_7 | SDIO SD0_CLK | +| PIO0_8 | SDIO SD0_CMD | +| PIO0_9 | SDIO SD0_POW_EN | +| PIO0_15 | SDIO SD0_WR_PRT | +| PIO0_17 | SDIO SD0_CARD_INT | +| PIO0_24 | SDIO SD0_D(0) | +| PIO0_25 | SDIO SD0_D(1) | +| PIO0_31 | SDIO SD0_D(2) | +| PIO1_0 | SDIO SD0_D(3) | +| | | +| PIO0_26 | High Speed SPI MOSI | +| PIO1_2 | High Speed SPI SCK | +| PIO1_3 | High Speed SPI MISO | +| | | +| PIO1_4 | GPIO1_4 output LED BLUE | +| PIO1_6 | GPIO1_6 output LED RED | +| PIO1_7 | GPIO1_7 output LED GREEN | +| | | +| PIO0_27 | Flexcomm2 USART TXD mikro BUS | +| PIO1_24 | Flexcomm2 USART RXD mikro BUS | +| | | +| PIO1_20 | Flexcomm4 I2C SCL | +| PIO1_21 | Flexcomm4 I2C SDA | + +## 5. menuconfig Bspèœå•è¯¦è§£ + +| 选项 | 解释 | +| -- | -- | +| Device type | 选择芯片型å·ï¼Œä¿®æ”¹æ­¤å¤„需修改MDK/IAR工程为相åŒèŠ¯ç‰‡åž‹å· | + +*部分选项需è¦åœ¨RT-Thread组件èœå•ä¸­å¼€å¯å¯¹åº”的设备框架æ‰èƒ½æ˜¾ç¤ºã€‚ + +## 6. è”ç³»äººä¿¡æ¯ + +维护人: +[Magicoe][2] < [magicoe@163.com][3] > + +[1]: https://www.rt-thread.org/page/download.html +[2]: https://github.com/Magicoe +[3]: mailto:magicoe@163.com diff --git a/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/SConscript b/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/SConscript new file mode 100644 index 000000000..c7ef7659e --- /dev/null +++ b/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/SConscript @@ -0,0 +1,14 @@ +# for module compiling +import os +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/SConstruct b/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/SConstruct new file mode 100644 index 000000000..36bd607bd --- /dev/null +++ b/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/SConstruct @@ -0,0 +1,65 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +if rtconfig.PLATFORM == 'armcc': + env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS, + # overwrite cflags, because cflags has '--C99' + CXXCOM = '$CXX -o $TARGET --cpp -c $CXXFLAGS $_CCCOMCOM $SOURCES') +else: + env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS, + CXXCOM = '$CXX -o $TARGET -c $CXXFLAGS $_CCCOMCOM $SOURCES') + +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM == 'iar': + env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map rtthread.map') + +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./') + +if os.path.exists(SDK_ROOT + '/Libraries'): + libraries_path_prefix = SDK_ROOT + '/Libraries' +else: + libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/Libraries' + +SDK_LIB = libraries_path_prefix +Export('SDK_LIB') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +objs = objs + SConscript('../Libraries/drivers/SConscript') +objs = objs + SConscript('../Libraries/LPC55S6X/SConscript') + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/applications/SConscript b/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/applications/SConscript new file mode 100644 index 000000000..78952a658 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/applications/SConscript @@ -0,0 +1,16 @@ +import rtconfig +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = [cwd] + +# add for startup script +if rtconfig.CROSS_TOOL == 'gcc': + CPPDEFINES = ['__START=entry'] +else: + CPPDEFINES = [] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES) + +Return('group') diff --git a/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/applications/main.c b/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/applications/main.c new file mode 100644 index 000000000..e03a8c633 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/applications/main.c @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-10-24 Magicoe first version + * + */ + +#include +#include "drv_pin.h" + +/* defined the LED pin: GPIO1_IO4 */ +/* GPIO1_4 is Blue LED */ +#define LEDB_PIN GET_PINS(1, 4) + +int main(void) +{ +#if defined(__CC_ARM) + rt_kprintf("using armcc, version: %d\n", __ARMCC_VERSION); +#elif defined(__CLANG_ARM) + rt_kprintf("using armclang, version: %d\n", __ARMCC_VERSION); +#elif defined(__ICCARM__) + rt_kprintf("using iccarm, version: %d\n", __VER__); +#elif defined(__GNUC__) + rt_kprintf("using gcc, version: %d.%d\n", __GNUC__, __GNUC_MINOR__); +#endif + + rt_pin_mode(LEDB_PIN, PIN_MODE_OUTPUT); /* Set GPIO as Output */ + while (1) + { + rt_pin_write(LEDB_PIN, PIN_HIGH); /* Set GPIO output 1 */ + rt_thread_mdelay(500); /* Delay 500mS */ + rt_pin_write(LEDB_PIN, PIN_LOW); /* Set GPIO output 0 */ + rt_thread_mdelay(500); /* Delay 500mS */ + } +} + +// end file diff --git a/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/board/Kconfig b/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/board/Kconfig new file mode 100644 index 000000000..158cad3c9 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/board/Kconfig @@ -0,0 +1,222 @@ +menu "Hardware Drivers Config" + +config SOC_LPC55S6X + bool + select SOC_LPC55S6X_SERIES + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +menu "On-chip Peripheral Drivers" + + config BSP_USING_DMA + bool "Enable DMA" + select RT_USING_DMA + default n + + config BSP_USING_PIN + bool "Enable GPIO" + select RT_USING_PIN + default y + + menuconfig BSP_USING_UART + config BSP_USING_UART + bool "Enable UART" + select RT_USING_UART + default y + + if BSP_USING_UART + config BSP_USING_UART0 + bool "Enable Flexcomm0 as UART" + default y + if BSP_USING_UART0 + choice + prompt "Select UART0 badurate" + default HW_UART0_BAUDRATE_115200 + + config HW_UART0_BAUDRATE_9600 + bool "Badurate 9600" + + config HW_UART0_BAUDRATE_115200 + bool "Badurate 115200" + endchoice + endif + + config BSP_USING_UART2 + bool "Enable Flexcomm2 as UART" + default n + if BSP_USING_UART2 + choice + prompt "Select UART2 badurate" + default HW_UART2_BAUDRATE_115200 + + config HW_UART2_BAUDRATE_9600 + bool "Badurate 9600" + + config HW_UART2_BAUDRATE_115200 + bool "Badurate 115200" + endchoice + endif + endif + + + menuconfig BSP_USING_I2C + config BSP_USING_I2C + bool "Enable I2C" + select RT_USING_I2C + default y + + if BSP_USING_I2C + config BSP_USING_I2C1 + bool "Enable Flexcomm1 I2C" + default y + if BSP_USING_I2C1 + choice + prompt "Select I2C1 badurate" + default HW_I2C1_BAUDRATE_100kHZ + + config HW_I2C1_BAUDRATE_100kHZ + bool "Badurate 100kHZ" + + config HW_I2C1_BAUDRATE_400kHZ + bool "Badurate 400kHZ" + endchoice + endif + + config BSP_USING_I2C4 + bool "Enable Flexcomm4 I2C" + default y + if BSP_USING_I2C4 + choice + prompt "Select I2C4 badurate" + default HW_I2C4_BAUDRATE_100kHZ + + config HW_I2C4_BAUDRATE_100kHZ + bool "Badurate 100kHZ" + + config HW_I2C4_BAUDRATE_400kHZ + bool "Badurate 400kHZ" + endchoice + endif + endif + + menuconfig BSP_USING_SPI + config BSP_USING_SPI + bool "Enable SPI" + select RT_USING_SPI + default y + + if BSP_USING_SPI + config BSP_USING_SPI3 + bool "Enable Flexcomm3 as SPI" + default n + + config BSP_USING_SPI8 + bool "Enable Flexcomm8 as High Speed SPI" + default y + endif + + menuconfig BSP_USING_ADC + config BSP_USING_ADC + bool "Enable ADC Channel" + select RT_USING_ADC + default y + + if BSP_USING_ADC + config BSP_USING_ADC0_CH0 + bool "Enable ADC0 Channel0" + default y + + config BSP_USING_ADC0_CH1 + bool "Enable ADC0 Channel1" + default n + endif + + config BSP_USING_SDIO + bool "Enable SDIO SD Card Interface" + select RT_USING_SDIO + default y + + config BSP_USING_RTC + bool "Enable RTC" + select RT_USING_RTC + default y + + config BSP_USING_WDT + bool "Enable WatchDog" + select RT_USING_WDT + default n + + menuconfig BSP_USING_HWTIMER + config BSP_USING_HWTIMER + bool "Enable Timer" + select RT_USING_HWTIMER + default y + + if BSP_USING_HWTIMER + config BSP_USING_CTIMER0 + bool "Enable CIMER0" + default y + + config BSP_USING_CTIMER1 + bool "Enable CIMER1" + default n + + config BSP_USING_CTIMER3 + bool "Enable CIMER3" + default n + + config BSP_USING_CTIMER4 + bool "Enable CIMER4" + default n + endif + + menuconfig BSP_USING_PWM + config BSP_USING_PWM + bool "Enable PWM" + select RT_USING_PWM + default y + + if BSP_USING_PWM + config BSP_USING_CTIMER2_MAT0 + bool "Enable CIMER2 Match0 as PWM output" + default y + + config BSP_USING_CTIMER2_MAT1 + bool "Enable CIMER2 Match1 as PWM output" + default n + + config BSP_USING_CTIMER2_MAT2 + bool "Enable CIMER2 Match2 as PWM output" + default n + endif +endmenu + +menu "Onboard Peripheral Drivers" + config BSP_USING_LED + bool "Enable RGB LED" + select RT_USING_LED + default y + + config BSP_USING_KEY + bool "Enable Button " + select RT_USING_KEY + default y + + config BSP_USING_MMA8562 + bool "Enable MMA8562" + select BSP_USING_I2C4 + default y + if BSP_USING_MMA8562 + config BSP_USING_MMA8562I2C + string "the device name for 3-Axis Sensor" + default "i2c4" + endif + +endmenu + +menu "Board extended module Drivers" + +endmenu + +endmenu diff --git a/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/board/MCUX_Config/LPCXpresso55S69.mex b/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/board/MCUX_Config/LPCXpresso55S69.mex new file mode 100644 index 000000000..4eac29e31 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/board/MCUX_Config/LPCXpresso55S69.mex @@ -0,0 +1,316 @@ + + + + LPC55S69 + LPC55S69JBD100 + + ksdk2_0 + + + + + Configuration imported from C:\NXP Working File\NXP\LPC5500\lpc5500_basic_enablement\lpc5500_lcd_camera_mdk + + + true + false + false + + + + + + + + + 6.0.0 + + + + Configures pin routing and optionally pin electrical features. + + true + cm33_core0 + true + + + + + true + + + + + true + + + + + true + + + + + true + + + + + true + + + + + true + + + + + true + + + + + true + + + + + true + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 6.0.0 + + + + + + + + + true + + + + + true + + + + + true + + + + + true + + + + + true + + + + + true + + + + + + + + + + + + + false + + + + + + + + true + + + + + true + + + + + true + + + + + true + + + + + true + + + + + true + + + + + + + + + + + + + + true + + + + + + + + true + + + + + INPUT + + + + + true + + + + + true + + + + + true + + + + + true + + + + + true + + + + + true + + + + + + + + + + + + + + + + + + + + + + false + + + + + + + N/A + + + + + + + N/A + + + + + + + + N/A + + + + + + \ No newline at end of file diff --git a/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/board/MCUX_Config/board/clock_config.c b/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/board/MCUX_Config/board/clock_config.c new file mode 100644 index 000000000..0333551ac --- /dev/null +++ b/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/board/MCUX_Config/board/clock_config.c @@ -0,0 +1,300 @@ +/* + * Copyright 2017-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ +/* + * How to set up clock using clock driver functions: + * + * 1. Setup clock sources. + * + * 2. Set up wait states of the flash. + * + * 3. Set up all dividers. + * + * 4. Set up all selectors to provide selected clocks. + */ + +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Clocks v6.0 +processor: LPC55S69 +package_id: LPC55S69JBD100 +mcu_data: ksdk2_0 +processor_version: 0.0.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +#include "fsl_power.h" +#include "fsl_clock.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* System clock frequency. */ +extern uint32_t SystemCoreClock; + +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ +void BOARD_InitBootClocks(void) +{ + BOARD_BootClockPLL150M(); +} + +/******************************************************************************* + ******************** Configuration BOARD_BootClockFRO12M ********************** + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockFRO12M +outputs: +- {id: System_clock.outFreq, value: 12 MHz} +settings: +- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable} +sources: +- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +void BOARD_BootClockFRO12M(void) +{ +#ifndef SDK_SECONDARY_CORE + /*!< Set up the clock sources */ + /*!< Configure FRO192M */ + POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */ + CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */ + + CLOCK_SetupFROClocking(96000000U); /* Enable FRO HF(96MHz) output */ + + POWER_SetVoltageForFreq(12000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ + CLOCK_SetFLASHAccessCyclesForFreq(12000000U); /*!< Set FLASH wait states for core */ + + /*!< Set up dividers */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO12M */ + + /*< Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK; +#endif +} + +/******************************************************************************* + ******************* Configuration BOARD_BootClockFROHF96M ********************* + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockFROHF96M +outputs: +- {id: System_clock.outFreq, value: 96 MHz} +settings: +- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable} +- {id: SYSCON.MAINCLKSELA.sel, value: ANACTRL.fro_hf_clk} +sources: +- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockFROHF96M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockFROHF96M configuration + ******************************************************************************/ +void BOARD_BootClockFROHF96M(void) +{ +#ifndef SDK_SECONDARY_CORE + /*!< Set up the clock sources */ + /*!< Configure FRO192M */ + POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */ + CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */ + + CLOCK_SetupFROClocking(96000000U); /* Enable FRO HF(96MHz) output */ + + POWER_SetVoltageForFreq(96000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ + CLOCK_SetFLASHAccessCyclesForFreq(96000000U); /*!< Set FLASH wait states for core */ + + /*!< Set up dividers */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */ + + /*< Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK; +#endif +} + +/******************************************************************************* + ******************** Configuration BOARD_BootClockPLL100M ********************* + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockPLL100M +outputs: +- {id: System_clock.outFreq, value: 100 MHz} +settings: +- {id: PLL0_Mode, value: Normal} +- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable} +- {id: ENABLE_CLKIN_ENA, value: Enabled} +- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled} +- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL0_BYPASS} +- {id: SYSCON.PLL0CLKSEL.sel, value: SYSCON.CLK_IN_EN} +- {id: SYSCON.PLL0M_MULT.scale, value: '100', locked: true} +- {id: SYSCON.PLL0N_DIV.scale, value: '4', locked: true} +- {id: SYSCON.PLL0_PDEC.scale, value: '4', locked: true} +sources: +- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz} +- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockPLL100M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockPLL100M configuration + ******************************************************************************/ +void BOARD_BootClockPLL100M(void) +{ +#ifndef SDK_SECONDARY_CORE + /*!< Set up the clock sources */ + /*!< Configure FRO192M */ + POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */ + CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */ + + CLOCK_SetupFROClocking(96000000U); /* Enable FRO HF(96MHz) output */ + + POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */ + POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */ + CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */ + SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */ + ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */ + + POWER_SetVoltageForFreq(100000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ + CLOCK_SetFLASHAccessCyclesForFreq(100000000U); /*!< Set FLASH wait states for core */ + + /*!< Set up PLL */ + CLOCK_AttachClk(kEXT_CLK_to_PLL0); /*!< Switch PLL0CLKSEL to EXT_CLK */ + POWER_DisablePD(kPDRUNCFG_PD_PLL0); /* Ensure PLL is on */ + POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG); + const pll_setup_t pll0Setup = { + .pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(54U) | SYSCON_PLL0CTRL_SELP(26U), + .pllndec = SYSCON_PLL0NDEC_NDIV(4U), + .pllpdec = SYSCON_PLL0PDEC_PDIV(2U), + .pllsscg = {0x0U,(SYSCON_PLL0SSCG1_MDIV_EXT(100U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)}, + .pllRate = 100000000U, + .flags = PLL_SETUPFLAG_WAITLOCK + }; + CLOCK_SetPLL0Freq(&pll0Setup); /*!< Configure PLL0 to the desired values */ + + /*!< Set up dividers */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + CLOCK_AttachClk(kPLL0_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL0 */ + + /*< Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKPLL100M_CORE_CLOCK; +#endif +} + +/******************************************************************************* + ******************** Configuration BOARD_BootClockPLL150M ********************* + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockPLL150M +called_from_default_init: true +outputs: +- {id: System_clock.outFreq, value: 150 MHz} +settings: +- {id: PLL0_Mode, value: Normal} +- {id: ENABLE_CLKIN_ENA, value: Enabled} +- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled} +- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL0_BYPASS} +- {id: SYSCON.PLL0CLKSEL.sel, value: SYSCON.CLK_IN_EN} +- {id: SYSCON.PLL0M_MULT.scale, value: '150', locked: true} +- {id: SYSCON.PLL0N_DIV.scale, value: '8', locked: true} +- {id: SYSCON.PLL0_PDEC.scale, value: '2', locked: true} +sources: +- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockPLL150M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockPLL150M configuration + ******************************************************************************/ +void BOARD_BootClockPLL150M(void) +{ +#ifndef SDK_SECONDARY_CORE + /*!< Set up the clock sources */ + /*!< Configure FRO192M */ + POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */ + CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */ + + POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */ + POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */ + CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */ + SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */ + ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */ + + POWER_SetVoltageForFreq(150000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ + CLOCK_SetFLASHAccessCyclesForFreq(150000000U); /*!< Set FLASH wait states for core */ + + /*!< Set up PLL */ + CLOCK_AttachClk(kEXT_CLK_to_PLL0); /*!< Switch PLL0CLKSEL to EXT_CLK */ + POWER_DisablePD(kPDRUNCFG_PD_PLL0); /* Ensure PLL is on */ + POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG); + const pll_setup_t pll0Setup = { + .pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(53U) | SYSCON_PLL0CTRL_SELP(31U), + .pllndec = SYSCON_PLL0NDEC_NDIV(8U), + .pllpdec = SYSCON_PLL0PDEC_PDIV(1U), + .pllsscg = {0x0U,(SYSCON_PLL0SSCG1_MDIV_EXT(150U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)}, + .pllRate = 150000000U, + .flags = PLL_SETUPFLAG_WAITLOCK + }; + CLOCK_SetPLL0Freq(&pll0Setup); /*!< Configure PLL0 to the desired values */ + + /*!< Set up dividers */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + CLOCK_AttachClk(kPLL0_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL0 */ + + /*< Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKPLL150M_CORE_CLOCK; +#endif +} + diff --git a/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/board/MCUX_Config/board/clock_config.h b/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/board/MCUX_Config/board/clock_config.h new file mode 100644 index 000000000..86a93f220 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/board/MCUX_Config/board/clock_config.h @@ -0,0 +1,147 @@ +/* + * Copyright 2017-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define BOARD_XTAL0_CLK_HZ 16000000U /*!< Board xtal frequency in Hz */ +#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32K frequency in Hz */ + +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes default configuration of clocks. + * + */ +void BOARD_InitBootClocks(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************** Configuration BOARD_BootClockFRO12M ********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK 12000000U /*!< Core clock frequency: 12000000Hz */ + + +/******************************************************************************* + * API for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockFRO12M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************* Configuration BOARD_BootClockFROHF96M ********************* + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockFROHF96M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK 96000000U /*!< Core clock frequency: 96000000Hz */ + + +/******************************************************************************* + * API for BOARD_BootClockFROHF96M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockFROHF96M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************** Configuration BOARD_BootClockPLL100M ********************* + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockPLL100M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKPLL100M_CORE_CLOCK 100000000U /*!< Core clock frequency: 100000000Hz */ + + +/******************************************************************************* + * API for BOARD_BootClockPLL100M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockPLL100M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************** Configuration BOARD_BootClockPLL150M ********************* + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockPLL150M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKPLL150M_CORE_CLOCK 150000000U /*!< Core clock frequency: 150000000Hz */ + + +/******************************************************************************* + * API for BOARD_BootClockPLL150M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockPLL150M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ + diff --git a/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/board/MCUX_Config/board/pin_mux.c b/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/board/MCUX_Config/board/pin_mux.c new file mode 100644 index 000000000..907fd2561 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/board/MCUX_Config/board/pin_mux.c @@ -0,0 +1,348 @@ +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v6.0 +processor: LPC55S69 +package_id: LPC55S69JBD100 +mcu_data: ksdk2_0 +processor_version: 6.0.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +#include "fsl_common.h" +#include "fsl_iocon.h" +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitPins(); +} + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'} +- pin_list: + - {pin_num: '92', peripheral: FLEXCOMM0, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO0_29/FC0_RXD_SDA_MOSI_DATA/SD1_D2/CTIMER2_MAT3/SCT0_OUT8/CMP0_OUT/PLU_OUT2/SECURE_GPIO0_29, + mode: inactive, slew_rate: standard, invert: disabled, open_drain: disabled} + - {pin_num: '94', peripheral: FLEXCOMM0, signal: TXD_SCL_MISO_WS, pin_signal: PIO0_30/FC0_TXD_SCL_MISO_WS/SD1_D3/CTIMER0_MAT0/SCT0_OUT9/SECURE_GPIO0_30, mode: inactive, + slew_rate: standard, invert: disabled, open_drain: disabled} + - {pin_num: '20', peripheral: ADC0, signal: 'CH, 0', pin_signal: PIO0_23/MCLK/CTIMER1_MAT2/CTIMER3_MAT3/SCT0_OUT4/FC0_CTS_SDA_SSEL0/SD1_D1/SECURE_GPIO0_23/ADC0_0} + - {pin_num: '8', peripheral: SDIF, signal: SD0_CARD_DET, pin_signal: PIO0_17/FC4_SSEL2/SD0_CARD_DET_N/SCT_GPI7/SCT0_OUT0/SD0_CARD_INT_N/PLU_IN2/SECURE_GPIO0_17} + - {pin_num: '70', peripheral: SDIF, signal: 'SD0_D, 0', pin_signal: PIO0_24/FC0_RXD_SDA_MOSI_DATA/SD0_D0/CT_INP8/SCT_GPI0/SECURE_GPIO0_24} + - {pin_num: '79', peripheral: SDIF, signal: 'SD0_D, 1', pin_signal: PIO0_25/FC0_TXD_SCL_MISO_WS/SD0_D1/CT_INP9/SCT_GPI1/SECURE_GPIO0_25} + - {pin_num: '23', peripheral: SDIF, signal: 'SD0_D, 2', pin_signal: PIO0_31/FC0_CTS_SDA_SSEL0/SD0_D2/CTIMER0_MAT1/SCT0_OUT3/SECURE_GPIO0_31/ADC0_3} + - {pin_num: '6', peripheral: SDIF, signal: SD0_CLK, pin_signal: PIO0_7/FC3_RTS_SCL_SSEL1/SD0_CLK/FC5_SCK/FC1_SCK/SECURE_GPIO0_7} + - {pin_num: '26', peripheral: SDIF, signal: SD0_CMD, pin_signal: PIO0_8/FC3_SSEL3/SD0_CMD/FC5_RXD_SDA_MOSI_DATA/SWO/SECURE_GPIO0_8} + - {pin_num: '55', peripheral: SDIF, signal: SD0_POW_EN, pin_signal: PIO0_9/FC3_SSEL2/SD0_POW_EN/FC5_TXD_SCL_MISO_WS/SECURE_GPIO0_9/ACMP0_B} + - {pin_num: '11', peripheral: SDIF, signal: 'SD0_D, 3', pin_signal: PIO1_0/FC0_RTS_SCL_SSEL1/SD0_D3/CT_INP2/SCT_GPI4/PLU_OUT3/ADC0_11} + - {pin_num: '61', peripheral: FLEXCOMM8, signal: HS_SPI_SCK, pin_signal: PIO1_2/CTIMER0_MAT3/SCT_GPI6/HS_SPI_SCK/USB1_PORTPWRN/PLU_OUT5} + - {pin_num: '62', peripheral: FLEXCOMM8, signal: HS_SPI_MISO, pin_signal: PIO1_3/SCT0_OUT4/HS_SPI_MISO/USB0_PORTPWRN/PLU_OUT6} + - {pin_num: '60', peripheral: FLEXCOMM8, signal: HS_SPI_MOSI, pin_signal: PIO0_26/FC2_RXD_SDA_MOSI_DATA/CLKOUT/CT_INP14/SCT0_OUT5/USB0_IDVALUE/FC0_SCK/HS_SPI_MOSI/SECURE_GPIO0_26} + - {pin_num: '9', peripheral: GPIO, signal: 'PIO1, 7', pin_signal: PIO1_7/FC0_RTS_SCL_SSEL1/SD0_D1/CTIMER2_MAT2/SCT_GPI4} + - {pin_num: '5', peripheral: GPIO, signal: 'PIO1, 6', pin_signal: PIO1_6/FC0_TXD_SCL_MISO_WS/SD0_D3/CTIMER2_MAT1/SCT_GPI3} + - {pin_num: '1', peripheral: CTIMER2, signal: 'MATCH, 1', pin_signal: PIO1_4/FC0_SCK/SD0_D0/CTIMER2_MAT1/SCT0_OUT0/FREQME_GPIO_CLK_A} + - {pin_num: '27', peripheral: FLEXCOMM2, signal: TXD_SCL_MISO_WS, pin_signal: PIO0_27/FC2_TXD_SCL_MISO_WS/CTIMER3_MAT2/SCT0_OUT6/FC7_RXD_SDA_MOSI_DATA/PLU_OUT0/SECURE_GPIO0_27} + - {pin_num: '3', peripheral: FLEXCOMM2, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO1_24/FC2_RXD_SDA_MOSI_DATA/SCT0_OUT1/SD1_D1/FC3_SSEL3/PLU_OUT6} + - {pin_num: '4', peripheral: FLEXCOMM4, signal: TXD_SCL_MISO_WS, pin_signal: PIO1_20/FC7_RTS_SCL_SSEL1/CT_INP14/FC4_TXD_SCL_MISO_WS/PLU_OUT2} + - {pin_num: '30', peripheral: FLEXCOMM4, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO1_21/FC7_CTS_SDA_SSEL0/CTIMER3_MAT2/FC4_RXD_SDA_MOSI_DATA/PLU_OUT3} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +/* Function assigned for the Cortex-M33 (Core #0) */ +void BOARD_InitPins(void) +{ + /* Enables the clock for the I/O controller.: Enable Clock. */ + CLOCK_EnableClock(kCLOCK_Iocon); + + IOCON->PIO[0][17] = ((IOCON->PIO[0][17] & + /* Mask bits to zero which are setting */ + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) + + /* Selects pin function. + * : PORT017 (pin 8) is configured as SD0_CARD_DET_N. */ + | IOCON_PIO_FUNC(PIO0_17_FUNC_ALT2) + + /* Select Digital mode. + * : Digital mode, digital input is enabled. */ + | IOCON_PIO_DIGIMODE(PIO0_17_DIGIMODE_DIGITAL)); + + IOCON->PIO[0][23] = ((IOCON->PIO[0][23] & + /* Mask bits to zero which are setting */ + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_MODE_MASK | IOCON_PIO_DIGIMODE_MASK | IOCON_PIO_ASW_MASK))) + + /* Selects pin function. + * : PORT023 (pin 20) is configured as ADC0_0. */ + | IOCON_PIO_FUNC(PIO0_23_FUNC_ALT0) + + /* Selects function mode (on-chip pull-up/pull-down resistor control). + * : Inactive. + * Inactive (no pull-down/pull-up resistor enabled). */ + | IOCON_PIO_MODE(PIO0_23_MODE_INACTIVE) + + /* Select Digital mode. + * : Analog mode, digital input is disabled. */ + | IOCON_PIO_DIGIMODE(PIO0_23_DIGIMODE_ANALOG) + + /* Analog switch input control. + * Usable only if DIGIMODE = 0b0: Analog switch is closed. */ + | IOCON_PIO_ASW(PIO0_23_ASW_ENABLE)); + + IOCON->PIO[0][24] = ((IOCON->PIO[0][24] & + /* Mask bits to zero which are setting */ + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) + + /* Selects pin function. + * : PORT024 (pin 70) is configured as SD0_D0. */ + | IOCON_PIO_FUNC(PIO0_24_FUNC_ALT2) + + /* Select Digital mode. + * : Digital mode, digital input is enabled. */ + | IOCON_PIO_DIGIMODE(PIO0_24_DIGIMODE_DIGITAL)); + + IOCON->PIO[0][25] = ((IOCON->PIO[0][25] & + /* Mask bits to zero which are setting */ + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) + + /* Selects pin function. + * : PORT025 (pin 79) is configured as SD0_D1. */ + | IOCON_PIO_FUNC(PIO0_25_FUNC_ALT2) + + /* Select Digital mode. + * : Digital mode, digital input is enabled. */ + | IOCON_PIO_DIGIMODE(PIO0_25_DIGIMODE_DIGITAL)); + + IOCON->PIO[0][26] = ((IOCON->PIO[0][26] & + /* Mask bits to zero which are setting */ + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) + + /* Selects pin function. + * : PORT026 (pin 60) is configured as HS_SPI_MOSI. */ + | IOCON_PIO_FUNC(0x09u) + + /* Select Digital mode. + * : Digital mode, digital input is enabled. */ + | IOCON_PIO_DIGIMODE(PIO0_26_DIGIMODE_DIGITAL)); + + IOCON->PIO[0][27] = ((IOCON->PIO[0][27] & + /* Mask bits to zero which are setting */ + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) + + /* Selects pin function. + * : PORT027 (pin 27) is configured as FC2_TXD_SCL_MISO_WS. */ + | IOCON_PIO_FUNC(PIO0_27_FUNC_ALT1) + + /* Select Digital mode. + * : Digital mode, digital input is enabled. */ + | IOCON_PIO_DIGIMODE(PIO0_27_DIGIMODE_DIGITAL)); + + const uint32_t port0_pin29_config = (/* Pin is configured as FC0_RXD_SDA_MOSI_DATA */ + IOCON_PIO_FUNC1 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT0 PIN29 (coords: 92) is configured as FC0_RXD_SDA_MOSI_DATA */ + IOCON_PinMuxSet(IOCON, 0U, 29U, port0_pin29_config); + + const uint32_t port0_pin30_config = (/* Pin is configured as FC0_TXD_SCL_MISO_WS */ + IOCON_PIO_FUNC1 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT0 PIN30 (coords: 94) is configured as FC0_TXD_SCL_MISO_WS */ + IOCON_PinMuxSet(IOCON, 0U, 30U, port0_pin30_config); + + IOCON->PIO[0][31] = ((IOCON->PIO[0][31] & + /* Mask bits to zero which are setting */ + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) + + /* Selects pin function. + * : PORT031 (pin 23) is configured as SD0_D2. */ + | IOCON_PIO_FUNC(PIO0_31_FUNC_ALT2) + + /* Select Digital mode. + * : Digital mode, digital input is enabled. */ + | IOCON_PIO_DIGIMODE(PIO0_31_DIGIMODE_DIGITAL)); + + IOCON->PIO[0][7] = ((IOCON->PIO[0][7] & + /* Mask bits to zero which are setting */ + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) + + /* Selects pin function. + * : PORT07 (pin 6) is configured as SD0_CLK. */ + | IOCON_PIO_FUNC(PIO0_7_FUNC_ALT2) + + /* Select Digital mode. + * : Digital mode, digital input is enabled. */ + | IOCON_PIO_DIGIMODE(PIO0_7_DIGIMODE_DIGITAL)); + + IOCON->PIO[0][8] = ((IOCON->PIO[0][8] & + /* Mask bits to zero which are setting */ + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) + + /* Selects pin function. + * : PORT08 (pin 26) is configured as SD0_CMD. */ + | IOCON_PIO_FUNC(PIO0_8_FUNC_ALT2) + + /* Select Digital mode. + * : Digital mode, digital input is enabled. */ + | IOCON_PIO_DIGIMODE(PIO0_8_DIGIMODE_DIGITAL)); + + IOCON->PIO[0][9] = ((IOCON->PIO[0][9] & + /* Mask bits to zero which are setting */ + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) + + /* Selects pin function. + * : PORT09 (pin 55) is configured as SD0_POW_EN. */ + | IOCON_PIO_FUNC(PIO0_9_FUNC_ALT2) + + /* Select Digital mode. + * : Digital mode, digital input is enabled. */ + | IOCON_PIO_DIGIMODE(PIO0_9_DIGIMODE_DIGITAL)); + + IOCON->PIO[1][0] = ((IOCON->PIO[1][0] & + /* Mask bits to zero which are setting */ + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) + + /* Selects pin function. + * : PORT10 (pin 11) is configured as SD0_D3. */ + | IOCON_PIO_FUNC(PIO1_0_FUNC_ALT2) + + /* Select Digital mode. + * : Digital mode, digital input is enabled. */ + | IOCON_PIO_DIGIMODE(PIO1_0_DIGIMODE_DIGITAL)); + + IOCON->PIO[1][2] = ((IOCON->PIO[1][2] & + /* Mask bits to zero which are setting */ + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) + + /* Selects pin function. + * : PORT12 (pin 61) is configured as HS_SPI_SCK. */ + | IOCON_PIO_FUNC(PIO1_2_FUNC_ALT6) + + /* Select Digital mode. + * : Digital mode, digital input is enabled. */ + | IOCON_PIO_DIGIMODE(PIO1_2_DIGIMODE_DIGITAL)); + + IOCON->PIO[1][20] = ((IOCON->PIO[1][20] & + /* Mask bits to zero which are setting */ + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) + + /* Selects pin function. + * : PORT120 (pin 4) is configured as FC4_TXD_SCL_MISO_WS. */ + | IOCON_PIO_FUNC(PIO1_20_FUNC_ALT5) + + /* Select Digital mode. + * : Digital mode, digital input is enabled. */ + | IOCON_PIO_DIGIMODE(PIO1_20_DIGIMODE_DIGITAL)); + + IOCON->PIO[1][21] = ((IOCON->PIO[1][21] & + /* Mask bits to zero which are setting */ + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) + + /* Selects pin function. + * : PORT121 (pin 30) is configured as FC4_RXD_SDA_MOSI_DATA. */ + | IOCON_PIO_FUNC(PIO1_21_FUNC_ALT5) + + /* Select Digital mode. + * : Digital mode, digital input is enabled. */ + | IOCON_PIO_DIGIMODE(PIO1_21_DIGIMODE_DIGITAL)); + + IOCON->PIO[1][24] = ((IOCON->PIO[1][24] & + /* Mask bits to zero which are setting */ + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) + + /* Selects pin function. + * : PORT124 (pin 3) is configured as FC2_RXD_SDA_MOSI_DATA. */ + | IOCON_PIO_FUNC(PIO1_24_FUNC_ALT1) + + /* Select Digital mode. + * : Digital mode, digital input is enabled. */ + | IOCON_PIO_DIGIMODE(PIO1_24_DIGIMODE_DIGITAL)); + + IOCON->PIO[1][3] = ((IOCON->PIO[1][3] & + /* Mask bits to zero which are setting */ + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) + + /* Selects pin function. + * : PORT13 (pin 62) is configured as HS_SPI_MISO. */ + | IOCON_PIO_FUNC(PIO1_3_FUNC_ALT6) + + /* Select Digital mode. + * : Digital mode, digital input is enabled. */ + | IOCON_PIO_DIGIMODE(PIO1_3_DIGIMODE_DIGITAL)); + + IOCON->PIO[1][4] = ((IOCON->PIO[1][4] & + /* Mask bits to zero which are setting */ + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) + + /* Selects pin function. + * : PORT14 (pin 1) is configured as CTIMER2_MAT1. */ + | IOCON_PIO_FUNC(PIO1_4_FUNC_ALT3) + + /* Select Digital mode. + * : Digital mode, digital input is enabled. */ + | IOCON_PIO_DIGIMODE(PIO1_4_DIGIMODE_DIGITAL)); + + IOCON->PIO[1][6] = ((IOCON->PIO[1][6] & + /* Mask bits to zero which are setting */ + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) + + /* Selects pin function. + * : PORT16 (pin 5) is configured as PIO1_6. */ + | IOCON_PIO_FUNC(PIO1_6_FUNC_ALT0) + + /* Select Digital mode. + * : Digital mode, digital input is enabled. */ + | IOCON_PIO_DIGIMODE(PIO1_6_DIGIMODE_DIGITAL)); + + IOCON->PIO[1][7] = ((IOCON->PIO[1][7] & + /* Mask bits to zero which are setting */ + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) + + /* Selects pin function. + * : PORT17 (pin 9) is configured as PIO1_7. */ + | IOCON_PIO_FUNC(PIO1_7_FUNC_ALT0) + + /* Select Digital mode. + * : Digital mode, digital input is enabled. */ + | IOCON_PIO_DIGIMODE(PIO1_7_DIGIMODE_DIGITAL)); +} +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/board/MCUX_Config/board/pin_mux.h b/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/board/MCUX_Config/board/pin_mux.h new file mode 100644 index 000000000..ef20f8c22 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/board/MCUX_Config/board/pin_mux.h @@ -0,0 +1,185 @@ +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief Enables digital function */ +#define IOCON_PIO_DIGITAL_EN 0x0100u +/*! + * @brief Selects pin function 1 */ +#define IOCON_PIO_FUNC1 0x01u +/*! + * @brief Input function is not inverted */ +#define IOCON_PIO_INV_DI 0x00u +/*! + * @brief No addition pin function */ +#define IOCON_PIO_MODE_INACT 0x00u +/*! + * @brief Open drain is disabled */ +#define IOCON_PIO_OPENDRAIN_DI 0x00u +/*! + * @brief Standard mode, output slew rate control is enabled */ +#define IOCON_PIO_SLEW_STANDARD 0x00u +/*! + * @brief Select Digital mode.: Digital mode, digital input is enabled. */ +#define PIO0_17_DIGIMODE_DIGITAL 0x01u +/*! + * @brief Selects pin function.: Alternative connection 2. */ +#define PIO0_17_FUNC_ALT2 0x02u +/*! + * @brief Analog switch input control. Usable only if DIGIMODE = 0b0: Analog switch is closed. */ +#define PIO0_23_ASW_ENABLE 0x01u +/*! + * @brief Select Digital mode.: Analog mode, digital input is disabled. */ +#define PIO0_23_DIGIMODE_ANALOG 0x00u +/*! + * @brief Selects pin function.: Alternative connection 0. */ +#define PIO0_23_FUNC_ALT0 0x00u +/*! + * @brief + * Selects function mode (on-chip pull-up/pull-down resistor control). + * : Inactive. + * Inactive (no pull-down/pull-up resistor enabled). + */ +#define PIO0_23_MODE_INACTIVE 0x00u +/*! + * @brief Select Digital mode.: Digital mode, digital input is enabled. */ +#define PIO0_24_DIGIMODE_DIGITAL 0x01u +/*! + * @brief Selects pin function.: Alternative connection 2. */ +#define PIO0_24_FUNC_ALT2 0x02u +/*! + * @brief Select Digital mode.: Digital mode, digital input is enabled. */ +#define PIO0_25_DIGIMODE_DIGITAL 0x01u +/*! + * @brief Selects pin function.: Alternative connection 2. */ +#define PIO0_25_FUNC_ALT2 0x02u +/*! + * @brief Select Digital mode.: Digital mode, digital input is enabled. */ +#define PIO0_26_DIGIMODE_DIGITAL 0x01u +/*! + * @brief Select Digital mode.: Digital mode, digital input is enabled. */ +#define PIO0_27_DIGIMODE_DIGITAL 0x01u +/*! + * @brief Selects pin function.: Alternative connection 1. */ +#define PIO0_27_FUNC_ALT1 0x01u +/*! + * @brief Select Digital mode.: Digital mode, digital input is enabled. */ +#define PIO0_31_DIGIMODE_DIGITAL 0x01u +/*! + * @brief Selects pin function.: Alternative connection 2. */ +#define PIO0_31_FUNC_ALT2 0x02u +/*! + * @brief Select Digital mode.: Digital mode, digital input is enabled. */ +#define PIO0_7_DIGIMODE_DIGITAL 0x01u +/*! + * @brief Selects pin function.: Alternative connection 2. */ +#define PIO0_7_FUNC_ALT2 0x02u +/*! + * @brief Select Digital mode.: Digital mode, digital input is enabled. */ +#define PIO0_8_DIGIMODE_DIGITAL 0x01u +/*! + * @brief Selects pin function.: Alternative connection 2. */ +#define PIO0_8_FUNC_ALT2 0x02u +/*! + * @brief Select Digital mode.: Digital mode, digital input is enabled. */ +#define PIO0_9_DIGIMODE_DIGITAL 0x01u +/*! + * @brief Selects pin function.: Alternative connection 2. */ +#define PIO0_9_FUNC_ALT2 0x02u +/*! + * @brief Select Digital mode.: Digital mode, digital input is enabled. */ +#define PIO1_0_DIGIMODE_DIGITAL 0x01u +/*! + * @brief Selects pin function.: Alternative connection 2. */ +#define PIO1_0_FUNC_ALT2 0x02u +/*! + * @brief Select Digital mode.: Digital mode, digital input is enabled. */ +#define PIO1_20_DIGIMODE_DIGITAL 0x01u +/*! + * @brief Selects pin function.: Alternative connection 5. */ +#define PIO1_20_FUNC_ALT5 0x05u +/*! + * @brief Select Digital mode.: Digital mode, digital input is enabled. */ +#define PIO1_21_DIGIMODE_DIGITAL 0x01u +/*! + * @brief Selects pin function.: Alternative connection 5. */ +#define PIO1_21_FUNC_ALT5 0x05u +/*! + * @brief Select Digital mode.: Digital mode, digital input is enabled. */ +#define PIO1_24_DIGIMODE_DIGITAL 0x01u +/*! + * @brief Selects pin function.: Alternative connection 1. */ +#define PIO1_24_FUNC_ALT1 0x01u +/*! + * @brief Select Digital mode.: Digital mode, digital input is enabled. */ +#define PIO1_2_DIGIMODE_DIGITAL 0x01u +/*! + * @brief Selects pin function.: Alternative connection 6. */ +#define PIO1_2_FUNC_ALT6 0x06u +/*! + * @brief Select Digital mode.: Digital mode, digital input is enabled. */ +#define PIO1_3_DIGIMODE_DIGITAL 0x01u +/*! + * @brief Selects pin function.: Alternative connection 6. */ +#define PIO1_3_FUNC_ALT6 0x06u +/*! + * @brief Select Digital mode.: Digital mode, digital input is enabled. */ +#define PIO1_4_DIGIMODE_DIGITAL 0x01u +/*! + * @brief Selects pin function.: Alternative connection 3. */ +#define PIO1_4_FUNC_ALT3 0x03u +/*! + * @brief Select Digital mode.: Digital mode, digital input is enabled. */ +#define PIO1_6_DIGIMODE_DIGITAL 0x01u +/*! + * @brief Selects pin function.: Alternative connection 0. */ +#define PIO1_6_FUNC_ALT0 0x00u +/*! + * @brief Select Digital mode.: Digital mode, digital input is enabled. */ +#define PIO1_7_DIGIMODE_DIGITAL 0x01u +/*! + * @brief Selects pin function.: Alternative connection 0. */ +#define PIO1_7_FUNC_ALT0 0x00u + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /* Function assigned for the Cortex-M33 (Core #0) */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/board/SConscript b/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/board/SConscript new file mode 100644 index 000000000..7f803bac9 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/board/SConscript @@ -0,0 +1,17 @@ +from building import * + +cwd = GetCurrentDir() + +# add the general drivers. +src = Split(""" +board.c +MCUX_Config/board/clock_config.c +MCUX_Config/board/pin_mux.c +""") + +CPPPATH = [cwd,cwd + '/MCUX_Config/board'] +CPPDEFINES = ['CPU_LPC55S69JBD100_cm33_core0'] + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES) + +Return('group') diff --git a/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/board/board.c b/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/board/board.c new file mode 100644 index 000000000..4a7fb3f88 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/board/board.c @@ -0,0 +1,98 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2009-01-05 Bernard first implementation + * 2010-02-04 Magicoe ported to LPC17xx + * 2010-05-02 Aozima update CMSIS to 130 + * 2017-08-02 XiaoYang porting to LPC54608 bsp + * 2019-08-05 Magicoe porting to LPC55S69-EVK bsp + */ + +#include +#include + +#include "board.h" +#include "clock_config.h" +#include "drv_uart.h" + +/** + * This is the timer interrupt service routine. + * + */ +void SysTick_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +/** + * This function will initial LPC55Sxx board. + */ +void rt_hw_board_init() +{ + /* Hardware Initialization */ + BOARD_InitPins(); + + CLOCK_EnableClock(kCLOCK_InputMux); + + CLOCK_EnableClock(kCLOCK_Gpio0); + CLOCK_EnableClock(kCLOCK_Gpio1); + + GPIO_PortInit(GPIO, 0); + GPIO_PortInit(GPIO, 1); + + /* NVIC Configuration */ +#define NVIC_VTOR_MASK 0x3FFFFF80 +#ifdef VECT_TAB_RAM + /* Set the Vector Table base location at 0x10000000 */ + SCB->VTOR = (0x10000000 & NVIC_VTOR_MASK); +#else /* VECT_TAB_FLASH */ + /* Set the Vector Table base location at 0x00000000 */ + SCB->VTOR = (0x00000000 & NVIC_VTOR_MASK); +#endif + + BOARD_BootClockPLL150M(); + //BOARD_BootClockFROHF96M(); + + /* init systick 1 systick = 1/(100M / 100) 100¸ösystick = 1s*/ + SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); + /* set pend exception priority */ + NVIC_SetPriority(PendSV_IRQn, (1 << __NVIC_PRIO_BITS) - 1); + + /*init uart device*/ + rt_hw_uart_init(); + +#ifdef RT_USING_CONSOLE + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif + +#ifdef RT_USING_COMPONENTS_INIT + /* initialization board with RT-Thread Components */ + rt_components_board_init(); +#endif + +#ifdef RT_USING_HEAP + rt_kprintf("sram heap, begin: 0x%p, end: 0x%p\n", HEAP_BEGIN, HEAP_END); + rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); +#endif +} + +/** + * This function will called when memory fault. + */ +void MemManage_Handler(void) +{ + extern void HardFault_Handler(void); + + rt_kprintf("Memory Fault!\n"); + HardFault_Handler(); +} diff --git a/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/board/board.h b/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/board/board.h new file mode 100644 index 000000000..f2fce5c09 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/board/board.h @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2009-09-22 Bernard add board.h to this bsp + * 2010-02-04 Magicoe add board.h to LPC176x bsp + * 2013-12-18 Bernard porting to LPC4088 bsp + * 2017-08-02 XiaoYang porting to LPC54608 bsp + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + + +#include + +#include + +#include "clock_config.h" +#include "fsl_common.h" +#include "fsl_reset.h" +#include "fsl_gpio.h" +#include "fsl_iocon.h" +#include "pin_mux.h" + +// + +// +#if defined(__CC_ARM) || defined(__CLANG_ARM) +extern int Image$$ARM_LIB_HEAP$$ZI$$Base; +#define HEAP_BEGIN ((void *)&Image$$ARM_LIB_HEAP$$ZI$$Base) +#elif defined(__ICCARM__) +#pragma section="HEAP" +#define HEAP_BEGIN (__segment_end("HEAP")) +#elif defined(__GNUC__) +extern int __bss_end; +#define HEAP_BEGIN ((void *)&__bss_end) +#endif +#define HEAP_END (void*)(0x20000000 + 0x40000) + +void rt_hw_board_init(void); + +#define BOARD_SDIF_BASEADDR SDIF +#define BOARD_SDIF_CLKSRC kCLOCK_SDio +#define BOARD_SDIF_CLK_FREQ CLOCK_GetFreq(kCLOCK_SDio) +#define BOARD_SDIF_CLK_ATTACH kMAIN_CLK_to_SDIO_CLK +#define BOARD_SDIF_IRQ SDIO_IRQn +#define BOARD_MMC_VCC_SUPPLY kMMC_VoltageWindows270to360 +#define BOARD_SD_CARD_DETECT_PIN 17 +#define BOARD_SD_CARD_DETECT_PORT 0 +#define BOARD_SD_CARD_DETECT_GPIO GPIO +#define BOARD_SD_DETECT_TYPE kSDMMCHOST_DetectCardByHostCD + +#define BOARD_SDIF_CD_GPIO_INIT() \ + { \ + CLOCK_EnableClock(kCLOCK_Gpio2); \ + GPIO_PinInit(BOARD_SD_CARD_DETECT_GPIO, BOARD_SD_CARD_DETECT_PORT, BOARD_SD_CARD_DETECT_PIN, \ + &(gpio_pin_config_t){kGPIO_DigitalInput, 0U}); \ + } +#define BOARD_SDIF_CD_STATUS() \ + GPIO_PinRead(BOARD_SD_CARD_DETECT_GPIO, BOARD_SD_CARD_DETECT_PORT, BOARD_SD_CARD_DETECT_PIN) + +#endif + + diff --git a/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/board/linker_scripts/LPC55S69_cm33_core0_flash.ld b/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/board/linker_scripts/LPC55S69_cm33_core0_flash.ld new file mode 100644 index 000000000..90f8ee7db --- /dev/null +++ b/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/board/linker_scripts/LPC55S69_cm33_core0_flash.ld @@ -0,0 +1,231 @@ +/* +** ################################################################### +** Processors: LPC55S69JBD100_cm33_core0 +** LPC55S69JET98_cm33_core0 +** +** Compiler: GNU C Compiler +** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.2 15 Aug 2018 +** Version: rev. 1.0, 2018-08-22 +** Build: b180921 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + + + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0800; +RPMSG_SHMEM_SIZE = DEFINED(__use_shmem__) ? 0x1800 : 0; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x00000000, LENGTH = 0x00000140 + m_text (RX) : ORIGIN = 0x00000140, LENGTH = 0x00071EC0 + m_core1_image (RX) : ORIGIN = 0x00072000, LENGTH = 0x00026000 + m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00033000 - RPMSG_SHMEM_SIZE + rpmsg_sh_mem (RW) : ORIGIN = 0x20033000 - RPMSG_SHMEM_SIZE, LENGTH = RPMSG_SHMEM_SIZE + m_usb_sram (RW) : ORIGIN = 0x40100000, LENGTH = 0x00004000 +} + +/* Define output sections */ +SECTIONS +{ + /* section for storing the secondary core image */ + .m0code : + { + . = ALIGN(4) ; + KEEP (*(.m0code)) + *(.m0code*) + . = ALIGN(4) ; + } > m_core1_image + + /* NOINIT section for rpmsg_sh_mem */ + .noinit_rpmsg_sh_mem (NOLOAD) : ALIGN(4) + { + *(.noinit.$rpmsg_sh_mem*) + . = ALIGN(4) ; + } > rpmsg_sh_mem + + /* The startup code goes first into internal flash */ + .interrupts : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + /* The program code and other data goes into internal flash */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.ramfunc*) /* for functions in ram */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + m_usb_bdt (NOLOAD) : + { + . = ALIGN(512); + *(m_usb_bdt) + } > m_usb_sram + + m_usb_global (NOLOAD) : + { + *(m_usb_global) + } > m_usb_sram + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/board/linker_scripts/LPC55S69_cm33_core0_flash_iar.icf b/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/board/linker_scripts/LPC55S69_cm33_core0_flash_iar.icf new file mode 100644 index 000000000..60a1ff514 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/board/linker_scripts/LPC55S69_cm33_core0_flash_iar.icf @@ -0,0 +1,111 @@ +/* +** ################################################################### +** Processors: LPC55S69JBD100_cm33_core0 +** LPC55S69JET98_cm33_core0 +** +** Compiler: IAR ANSI C/C++ Compiler for ARM +** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.2 15 Aug 2018 +** Version: rev. 1.0, 2018-08-22 +** Build: b180921 +** +** Abstract: +** Linker file for the IAR ANSI C/C++ Compiler for ARM +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + + +/* USB BDT size */ +define symbol usb_bdt_size = 0x0; +/* Stack and Heap Sizes */ +if (isdefinedsymbol(__stack_size__)) { + define symbol __size_cstack__ = __stack_size__; +} else { + define symbol __size_cstack__ = 0x800; +} + +if (isdefinedsymbol(__heap_size__)) { + define symbol __size_heap__ = __heap_size__; +} else { + define symbol __size_heap__ = 0x0400; +} + +define symbol m_interrupts_start = 0x00000000; +define symbol m_interrupts_end = 0x0000013F; + +define symbol m_text_start = 0x00000140; +define symbol m_text_end = 0x00071FFF; + +define exported symbol core1_image_start = 0x00072000; +define exported symbol core1_image_end = 0x00097FFF; + +if (isdefinedsymbol(__use_shmem__)) { + define symbol m_data_start = 0x20000000; + define symbol m_data_end = 0x200317FF; + define exported symbol rpmsg_sh_mem_start = 0x20031800; + define exported symbol rpmsg_sh_mem_end = 0x20032FFF; +} else { + define symbol m_data_start = 0x20000000; + define symbol m_data_end = 0x20032FFF; +} + +define symbol m_usb_sram_start = 0x40100000; +define symbol m_usb_sram_end = 0x40103FFF; + +define memory mem with size = 4G; + +define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] + | mem:[from m_text_start to m_text_end]; +define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; +define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; +if (isdefinedsymbol(__use_shmem__)) { + define region rpmsg_sh_mem_region = mem:[from rpmsg_sh_mem_start to rpmsg_sh_mem_end]; +} + +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block RW { readwrite }; +define block ZI { zi }; + +define region core1_region = mem:[from core1_image_start to core1_image_end]; +define block SEC_CORE_IMAGE_BLOCK { section __sec_core }; + +/* regions for USB */ +define region USB_BDT_region = mem:[from m_usb_sram_start to m_usb_sram_start + usb_bdt_size - 1]; +define region USB_SRAM_region = mem:[from m_usb_sram_start + usb_bdt_size to m_usb_sram_end]; +place in USB_BDT_region { section m_usb_bdt }; +place in USB_SRAM_region { section m_usb_global }; + +initialize by copy { readwrite, section .textrw }; + +if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) +{ + /* Required in a multi-threaded application */ + initialize by copy with packing = none { section __DLIB_PERTHREAD }; +} + +do not initialize { section .noinit, section m_usb_bdt, section m_usb_global }; +if (isdefinedsymbol(__use_shmem__)) { + do not initialize { section rpmsg_sh_mem_section }; +} + +place at address mem: m_interrupts_start { readonly section .intvec }; +place in TEXT_region { readonly }; +place in DATA_region { block RW }; +place in DATA_region { block ZI }; +place in DATA_region { last block HEAP }; +place in CSTACK_region { block CSTACK }; +if (isdefinedsymbol(__use_shmem__)) { + place in rpmsg_sh_mem_region { section rpmsg_sh_mem_section }; +} +place in core1_region { block SEC_CORE_IMAGE_BLOCK }; + diff --git a/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/board/linker_scripts/LPC55S69_cm33_core0_flash_mdk.scf b/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/board/linker_scripts/LPC55S69_cm33_core0_flash_mdk.scf new file mode 100644 index 000000000..7d91ff957 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/board/linker_scripts/LPC55S69_cm33_core0_flash_mdk.scf @@ -0,0 +1,104 @@ +#!armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -x c +/* +** ################################################################### +** Processors: LPC55S69JBD100_cm33_core0 +** LPC55S69JET98_cm33_core0 +** +** Compiler: Keil ARM C/C++ Compiler +** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.2 15 Aug 2018 +** Version: rev. 1.0, 2018-08-22 +** Build: b181008 +** +** Abstract: +** Linker file for the Keil ARM C/C++ Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + + +/* USB BDT size */ +#define usb_bdt_size 0x0 +/* Sizes */ +#if (defined(__stack_size__)) + #define Stack_Size __stack_size__ +#else + #define Stack_Size 0x1000 +#endif + +#if (defined(__heap_size__)) + #define Heap_Size __heap_size__ +#else + #define Heap_Size 0x1000 +#endif + +#define m_interrupts_start 0x00000000 +#define m_interrupts_size 0x00000200 + +#define m_text_start 0x00000200 +#define m_text_size 0x00071E00 + +#define m_core1_image_start 0x00072000 +#define m_core1_image_size 0x00026000 + +#if (defined(__use_shmem__)) + #define m_data_start 0x20000000 + #define m_data_size 0x00031800 + #define m_rpmsg_sh_mem_start 0x20031800 + #define m_rpmsg_sh_mem_size 0x00001800 +#else + #define m_data_start 0x20000000 + #define m_data_size 0x00033000 +#endif + +#define m_usb_sram_start 0x40100000 +#define m_usb_sram_size 0x00004000 + + +LR_m_text m_interrupts_start m_interrupts_size+m_text_size { ; load region size_region + + VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address + * (RESET,+FIRST) + } + + ER_m_text m_text_start FIXED m_text_size { ; load address = execution address + * (InRoot$$Sections) + * (+RO) + } + +#if (defined(__use_shmem__)) + RPMSG_SH_MEM m_rpmsg_sh_mem_start UNINIT m_rpmsg_sh_mem_size { ; Shared memory used by RPMSG + * (rpmsg_sh_mem_section) + } +#endif + + RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data + * (+RW +ZI) + } + ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up + } + ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down + } + + RW_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size { + * (m_usb_bdt) + } + + RW_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) { + * (m_usb_global) + } +} + +LR_CORE1_IMAGE m_core1_image_start { + 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a/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/project.ewd b/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/project.ewd new file mode 100644 index 000000000..882869846 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/project.ewd @@ -0,0 +1,1485 @@ + + + 3 + + rtthread-lpc55s6x + + ARM + + 1 + + C-SPY + 2 + + 30 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 1 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + IJET_ID + 2 + + 8 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + NULINK_ID + 2 + + 0 + 1 + 1 + + + + + + + PEMICRO_ID + 2 + + 3 + 1 + 1 + + + + + + + + STLINK_ID + 2 + + 6 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 1 + + + + + + + + TIFET_ID + 2 + + 1 + 1 + 1 + + + + + + + + + + + + + + + + + + + XDS100_ID + 2 + + 8 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\HWRTOSplugin\HWRTOSplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8BE.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + diff --git a/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/project.ewp b/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/project.ewp new file mode 100644 index 000000000..bb13acc40 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/project.ewp @@ -0,0 +1,1533 @@ + + 3 + + rtthread-lpc55s6x + + ARM + + 1 + + General + 3 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 35 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 10 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Kernel + + $PROJ_DIR$\..\..\..\src\clock.c + + + $PROJ_DIR$\..\..\..\src\components.c + + + $PROJ_DIR$\..\..\..\src\cpu.c + + + $PROJ_DIR$\..\..\..\src\device.c + + + $PROJ_DIR$\..\..\..\src\idle.c + + + $PROJ_DIR$\..\..\..\src\ipc.c + + + $PROJ_DIR$\..\..\..\src\irq.c + + + $PROJ_DIR$\..\..\..\src\kservice.c + + + $PROJ_DIR$\..\..\..\src\mem.c + + + $PROJ_DIR$\..\..\..\src\memheap.c + + + $PROJ_DIR$\..\..\..\src\mempool.c + + + $PROJ_DIR$\..\..\..\src\object.c + + + $PROJ_DIR$\..\..\..\src\scheduler.c + + + $PROJ_DIR$\..\..\..\src\signal.c + + + $PROJ_DIR$\..\..\..\src\thread.c + + + $PROJ_DIR$\..\..\..\src\timer.c + + + + Applications + + $PROJ_DIR$\applications\application.c + + + $PROJ_DIR$\applications\mnt.c + + + $PROJ_DIR$\applications\startup.c + + + + Drivers + + $PROJ_DIR$\board\board.c + + + $PROJ_DIR$\board\clock_config.c + + + $PROJ_DIR$\board\pin_mux.c + + + $PROJ_DIR$\..\Libraries\drivers\drv_pin.c + + + $PROJ_DIR$\..\Libraries\drivers\drv_led.c + + + $PROJ_DIR$\..\Libraries\drivers\drv_uart.c + + + $PROJ_DIR$\..\Libraries\drivers\drv_rtc.c + + + $PROJ_DIR$\..\Libraries\drivers\drv_spi.c + + + $PROJ_DIR$\..\Libraries\drivers\drv_sd.c + + + $PROJ_DIR$\..\Libraries\drivers\drv_i2c.c + + + $PROJ_DIR$\..\Libraries\drivers\drv_mma8562.c + + + $PROJ_DIR$\..\Libraries\drivers\drv_hwtimer.c + + + $PROJ_DIR$\..\Libraries\drivers\drv_wdt.c + + + $PROJ_DIR$\..\Libraries\drivers\drv_pwm.c + + + + cpu + + $PROJ_DIR$\..\..\..\libcpu\arm\common\backtrace.c + + + $PROJ_DIR$\..\..\..\libcpu\arm\common\div0.c + + + $PROJ_DIR$\..\..\..\libcpu\arm\common\showmem.c + + + $PROJ_DIR$\..\..\..\libcpu\arm\cortex-m4\cpuport.c + + + $PROJ_DIR$\..\..\..\libcpu\arm\cortex-m4\context_iar.S + + + + Filesystem + + $PROJ_DIR$\..\..\..\components\dfs\src\dfs.c + + + $PROJ_DIR$\..\..\..\components\dfs\src\dfs_file.c + + + $PROJ_DIR$\..\..\..\components\dfs\src\dfs_fs.c + + + $PROJ_DIR$\..\..\..\components\dfs\src\dfs_posix.c + + + $PROJ_DIR$\..\..\..\components\dfs\src\poll.c + + + $PROJ_DIR$\..\..\..\components\dfs\src\select.c + + + $PROJ_DIR$\..\..\..\components\dfs\filesystems\devfs\devfs.c + + + $PROJ_DIR$\..\..\..\components\dfs\filesystems\elmfat\dfs_elm.c + + + $PROJ_DIR$\..\..\..\components\dfs\filesystems\elmfat\ff.c + + + + DeviceDrivers + + $PROJ_DIR$\..\..\..\components\drivers\hwtimer\hwtimer.c + + + $PROJ_DIR$\..\..\..\components\drivers\i2c\i2c_core.c + + + $PROJ_DIR$\..\..\..\components\drivers\i2c\i2c_dev.c + + + $PROJ_DIR$\..\..\..\components\drivers\i2c\i2c-bit-ops.c + + + $PROJ_DIR$\..\..\..\components\drivers\misc\pin.c + + + $PROJ_DIR$\..\..\..\components\drivers\misc\adc.c + + + $PROJ_DIR$\..\..\..\components\drivers\misc\rt_drv_pwm.c + + + $PROJ_DIR$\..\..\..\components\drivers\rtc\rtc.c + + + $PROJ_DIR$\..\..\..\components\drivers\sdio\block_dev.c + + + $PROJ_DIR$\..\..\..\components\drivers\sdio\mmcsd_core.c + + + $PROJ_DIR$\..\..\..\components\drivers\sdio\sd.c + + + $PROJ_DIR$\..\..\..\components\drivers\sdio\sdio.c + + + $PROJ_DIR$\..\..\..\components\drivers\sdio\mmc.c + + + $PROJ_DIR$\..\..\..\components\drivers\serial\serial.c + + + $PROJ_DIR$\..\..\..\components\drivers\spi\spi_core.c + + + $PROJ_DIR$\..\..\..\components\drivers\spi\spi_dev.c + + + $PROJ_DIR$\..\..\..\components\drivers\src\completion.c + + + $PROJ_DIR$\..\..\..\components\drivers\src\dataqueue.c + + + $PROJ_DIR$\..\..\..\components\drivers\src\pipe.c + + + $PROJ_DIR$\..\..\..\components\drivers\src\ringblk_buf.c + + + $PROJ_DIR$\..\..\..\components\drivers\src\ringbuffer.c + + + $PROJ_DIR$\..\..\..\components\drivers\src\waitqueue.c + + + $PROJ_DIR$\..\..\..\components\drivers\src\workqueue.c + + + $PROJ_DIR$\..\..\..\components\drivers\watchdog\watchdog.c + + + + finsh + + $PROJ_DIR$\..\..\..\components\finsh\shell.c + + + $PROJ_DIR$\..\..\..\components\finsh\symbol.c + + + $PROJ_DIR$\..\..\..\components\finsh\cmd.c + + + $PROJ_DIR$\..\..\..\components\finsh\msh.c + + + $PROJ_DIR$\..\..\..\components\finsh\msh_cmd.c + + + $PROJ_DIR$\..\..\..\components\finsh\msh_file.c + + + $PROJ_DIR$\..\..\..\components\finsh\finsh_compiler.c + + + $PROJ_DIR$\..\..\..\components\finsh\finsh_error.c + + + $PROJ_DIR$\..\..\..\components\finsh\finsh_heap.c + + + $PROJ_DIR$\..\..\..\components\finsh\finsh_init.c + + + $PROJ_DIR$\..\..\..\components\finsh\finsh_node.c + + + $PROJ_DIR$\..\..\..\components\finsh\finsh_ops.c + + + $PROJ_DIR$\..\..\..\components\finsh\finsh_parser.c + + + $PROJ_DIR$\..\..\..\components\finsh\finsh_var.c + + + $PROJ_DIR$\..\..\..\components\finsh\finsh_vm.c + + + $PROJ_DIR$\..\..\..\components\finsh\finsh_token.c + + + + libc + + $PROJ_DIR$\..\..\..\components\libc\compilers\common\gmtime_r.c + + + + dlib + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\environ.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\libc.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\rmtx.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\stdio.c + + + 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$PROJ_DIR$\..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_sdif.c + + + $PROJ_DIR$\..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_spi.c + + + $PROJ_DIR$\..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_spi_dma.c + + + $PROJ_DIR$\..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_sysctl.c + + + $PROJ_DIR$\..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_usart.c + + + $PROJ_DIR$\..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_usart_dma.c + + + $PROJ_DIR$\..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_utick.c + + + $PROJ_DIR$\..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_wwdt.c + + + $PROJ_DIR$\..\Libraries\LPC55S6X\middleware\sdmmc\src\fsl_sd.c + + + $PROJ_DIR$\..\Libraries\LPC55S6X\middleware\sdmmc\src\fsl_sdmmc_common.c + + + $PROJ_DIR$\..\Libraries\LPC55S6X\middleware\sdmmc\port\sdif\rt_thread\fsl_sdmmc_event.c + + + $PROJ_DIR$\..\Libraries\LPC55S6X\middleware\sdmmc\port\sdif\rt_thread\fsl_sdmmc_host.c + + + $PROJ_DIR$\..\Libraries\LPC55S6X\LPC55S6X\iar\iar_lib_power_cm33_core0.a + + + diff --git a/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/project.eww b/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/project.eww new file mode 100644 index 000000000..c2cb02eb1 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/project.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\project.ewp + + + + + diff --git a/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/project.uvoptx b/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/project.uvoptx new file mode 100644 index 000000000..47b39900a --- /dev/null +++ b/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/project.uvoptx @@ -0,0 +1,1831 @@ + + + + 1.0 + +

### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rtthread-lpc55s6x + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 8 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 15 + + + + + + + + + + .\flashdebug.ini + BIN\CMSIS_AGDI_V8M.DLL + + + + 0 + DLGTARM + (6010=-1,-1,-1,-1,0)(6018=-1,-1,-1,-1,0)(6019=-1,-1,-1,-1,0)(6008=-1,-1,-1,-1,0)(6009=-1,-1,-1,-1,0)(6014=-1,-1,-1,-1,0)(6015=-1,-1,-1,-1,0)(6003=-1,-1,-1,-1,0)(6000=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI_V8M + -X"Any" -UAny -O206 -S9 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(6BA02477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO11 -FD20000000 -FC1000 -FN2 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### uVision Project, (C) Keil Software
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+ + + + + + + SARMV8M.DLL + -MPU + TCM.DLL + -pCM33 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4101 + + 1 + BIN\UL2V8M.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M33" + + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 2 + 0 + 1 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x44000 + + + 1 + 0x0 + 0x98000 + + + 1 + 0x40100000 + 0x4000 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x98000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x40100000 + 0x4000 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x44000 + + + 0 + 0x4000000 + 0x8000 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 3 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + + --target=arm-arm-none-eabi + CPU_LPC55S69JBD100_cm33_core0, RT_USING_ARM_LIBC + + .;..\..\..\include;applications;board;board\MCUX_Config;board\ports;..\Libraries\drivers;..\Libraries\drivers\config;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\dfs\include;..\..\..\components\dfs\filesystems\devfs;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\spi;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\finsh;..\..\..\components\libc\compilers\armlibc;..\..\..\components\libc\compilers\common;..\Libraries\LPC55S6X\CMSIS\Include;..\Libraries\LPC55S6X\components\codec;..\Libraries\LPC55S6X\LPC55S6X;..\Libraries\LPC55S6X\LPC55S6X\drivers;..\Libraries\LPC55S6X\middleware\sdmmc\inc;..\Libraries\LPC55S6X\middleware\sdmmc\port + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x02000000 + + .\board\linker_scripts\LPC55S69_cm33_core0_flash_mdk.scf + + + + + + + + + + + Kernel + + + clock.c + 1 + ..\..\..\src\clock.c + + + components.c + 1 + ..\..\..\src\components.c + + + device.c + 1 + ..\..\..\src\device.c + + + idle.c + 1 + ..\..\..\src\idle.c + + + ipc.c + 1 + ..\..\..\src\ipc.c + + + irq.c + 1 + ..\..\..\src\irq.c + + + kservice.c + 1 + ..\..\..\src\kservice.c + + + mem.c + 1 + ..\..\..\src\mem.c + + + mempool.c + 1 + ..\..\..\src\mempool.c + + + object.c + 1 + ..\..\..\src\object.c + + + scheduler.c + 1 + ..\..\..\src\scheduler.c + + + signal.c + 1 + ..\..\..\src\signal.c + + + thread.c + 1 + ..\..\..\src\thread.c + + + timer.c + 1 + ..\..\..\src\timer.c + + + + + Applications + + + main.c + 1 + applications\main.c + + + + + Drivers + + + board.c + 1 + board\board.c + + + clock_config.c + 1 + board\MCUX_Config\board\clock_config.c + + + pin_mux.c + 1 + board\MCUX_Config\board\pin_mux.c + + + drv_pin.c + 1 + ..\Libraries\drivers\drv_pin.c + + + drv_led.c + 1 + ..\Libraries\drivers\drv_led.c + + + drv_key.c + 1 + ..\Libraries\drivers\drv_key.c + + + drv_uart.c + 1 + ..\Libraries\drivers\drv_uart.c + + + drv_rtc.c + 1 + ..\Libraries\drivers\drv_rtc.c + + + drv_spi.c + 1 + ..\Libraries\drivers\drv_spi.c + + + drv_sd.c + 1 + ..\Libraries\drivers\drv_sd.c + + + drv_i2c.c + 1 + ..\Libraries\drivers\drv_i2c.c + + + drv_mma8562.c + 1 + ..\Libraries\drivers\drv_mma8562.c + + + drv_adc.c + 1 + ..\Libraries\drivers\drv_adc.c + + + drv_hwtimer.c + 1 + ..\Libraries\drivers\drv_hwtimer.c + + + drv_pwm.c + 1 + ..\Libraries\drivers\drv_pwm.c + + + + + cpu + + + backtrace.c + 1 + ..\..\..\libcpu\arm\common\backtrace.c + + + div0.c + 1 + ..\..\..\libcpu\arm\common\div0.c + + + showmem.c + 1 + ..\..\..\libcpu\arm\common\showmem.c + + + cpuport.c + 1 + ..\..\..\libcpu\arm\cortex-m4\cpuport.c + + + context_rvds.S + 2 + ..\..\..\libcpu\arm\cortex-m4\context_rvds.S + + + + + Filesystem + + + dfs.c + 1 + ..\..\..\components\dfs\src\dfs.c + + + dfs_file.c + 1 + ..\..\..\components\dfs\src\dfs_file.c + + + dfs_fs.c + 1 + ..\..\..\components\dfs\src\dfs_fs.c + + + dfs_posix.c + 1 + ..\..\..\components\dfs\src\dfs_posix.c + + + poll.c + 1 + ..\..\..\components\dfs\src\poll.c + + + select.c + 1 + ..\..\..\components\dfs\src\select.c + + + devfs.c + 1 + ..\..\..\components\dfs\filesystems\devfs\devfs.c + + + + + DeviceDrivers + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 0 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + hwtimer.c + 1 + ..\..\..\components\drivers\hwtimer\hwtimer.c + + + i2c_core.c + 1 + ..\..\..\components\drivers\i2c\i2c_core.c + + + i2c_dev.c + 1 + ..\..\..\components\drivers\i2c\i2c_dev.c + + + i2c-bit-ops.c + 1 + ..\..\..\components\drivers\i2c\i2c-bit-ops.c + + + pin.c + 1 + ..\..\..\components\drivers\misc\pin.c + + + adc.c + 1 + ..\..\..\components\drivers\misc\adc.c + + + rt_drv_pwm.c + 1 + ..\..\..\components\drivers\misc\rt_drv_pwm.c + + + rtc.c + 1 + ..\..\..\components\drivers\rtc\rtc.c + + + block_dev.c + 1 + ..\..\..\components\drivers\sdio\block_dev.c + + + mmcsd_core.c + 1 + ..\..\..\components\drivers\sdio\mmcsd_core.c + + + sd.c + 1 + ..\..\..\components\drivers\sdio\sd.c + + + sdio.c + 1 + ..\..\..\components\drivers\sdio\sdio.c + + + mmc.c + 1 + ..\..\..\components\drivers\sdio\mmc.c + + + serial.c + 1 + ..\..\..\components\drivers\serial\serial.c + + + spi_core.c + 1 + ..\..\..\components\drivers\spi\spi_core.c + + + spi_dev.c + 1 + ..\..\..\components\drivers\spi\spi_dev.c + + + completion.c + 1 + ..\..\..\components\drivers\src\completion.c + + + dataqueue.c + 1 + ..\..\..\components\drivers\src\dataqueue.c + + + pipe.c + 1 + ..\..\..\components\drivers\src\pipe.c + + + ringblk_buf.c + 1 + ..\..\..\components\drivers\src\ringblk_buf.c + + + ringbuffer.c + 1 + ..\..\..\components\drivers\src\ringbuffer.c + + + waitqueue.c + 1 + ..\..\..\components\drivers\src\waitqueue.c + + + workqueue.c + 1 + ..\..\..\components\drivers\src\workqueue.c + + + + + finsh + + + shell.c + 1 + ..\..\..\components\finsh\shell.c + + + cmd.c + 1 + ..\..\..\components\finsh\cmd.c + + + msh.c + 1 + ..\..\..\components\finsh\msh.c + + + msh_file.c + 1 + ..\..\..\components\finsh\msh_file.c + + + finsh_compiler.c + 1 + ..\..\..\components\finsh\finsh_compiler.c + + + finsh_error.c + 1 + ..\..\..\components\finsh\finsh_error.c + + + finsh_heap.c + 1 + ..\..\..\components\finsh\finsh_heap.c + + + finsh_init.c + 1 + ..\..\..\components\finsh\finsh_init.c + + + finsh_node.c + 1 + ..\..\..\components\finsh\finsh_node.c + + + finsh_ops.c + 1 + ..\..\..\components\finsh\finsh_ops.c + + + finsh_parser.c + 1 + ..\..\..\components\finsh\finsh_parser.c + + + finsh_var.c + 1 + ..\..\..\components\finsh\finsh_var.c + + + finsh_vm.c + 1 + ..\..\..\components\finsh\finsh_vm.c + + + finsh_token.c + 1 + ..\..\..\components\finsh\finsh_token.c + + + + + libc + + + libc.c + 1 + ..\..\..\components\libc\compilers\armlibc\libc.c + + + mem_std.c + 1 + ..\..\..\components\libc\compilers\armlibc\mem_std.c + + + stdio.c + 1 + ..\..\..\components\libc\compilers\armlibc\stdio.c + + + stubs.c + 1 + ..\..\..\components\libc\compilers\armlibc\stubs.c + + + time.c + 1 + ..\..\..\components\libc\compilers\common\time.c + + + + + Libraries + + + system_LPC55S69_cm33_core0.c + 1 + ..\Libraries\LPC55S6X\LPC55S6X\system_LPC55S69_cm33_core0.c + + + startup_LPC55S69_cm33_core0.s + 2 + ..\Libraries\LPC55S6X\LPC55S6X\arm\startup_LPC55S69_cm33_core0.s + + + fsl_anactrl.c + 1 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_anactrl.c + + + fsl_casper.c + 1 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_casper.c + + + fsl_clock.c + 1 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_clock.c + + + fsl_cmp.c + 1 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_cmp.c + + + fsl_common.c + 1 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_common.c + + + fsl_crc.c + 1 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_crc.c + + + fsl_ctimer.c + 1 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_ctimer.c + + + fsl_flexcomm.c + 1 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_flexcomm.c + + + fsl_dma.c + 1 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_dma.c + + + fsl_gint.c + 1 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_gint.c + + + fsl_gpio.c + 1 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_gpio.c + + + fsl_hashcrypt.c + 1 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_hashcrypt.c + + + fsl_i2c.c + 1 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_i2c.c + + + fsl_i2c_dma.c + 1 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_i2c_dma.c + + + fsl_i2s.c + 1 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_i2s.c + + + fsl_i2s_dma.c + 1 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_i2s_dma.c + + + fsl_iap.c + 1 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_iap.c + + + fsl_inputmux.c + 1 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_inputmux.c + + + fsl_lpadc.c + 1 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_lpadc.c + + + fsl_mrt.c + 1 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_mrt.c + + + fsl_ostimer.c + 1 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_ostimer.c + + + fsl_pint.c + 1 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_pint.c + + + fsl_plu.c + 1 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_plu.c + + + fsl_power.c + 1 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_power.c + + + fsl_powerquad_basic.c + 1 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_powerquad_basic.c + + + fsl_prince.c + 1 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_prince.c + + + fsl_puf.c + 1 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_puf.c + + + fsl_reset.c + 1 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_reset.c + + + fsl_rng.c + 1 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_rng.c + + + fsl_rtc.c + 1 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_rtc.c + + + fsl_sctimer.c + 1 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_sctimer.c + + + fsl_sdif.c + 1 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_sdif.c + + + fsl_spi.c + 1 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_spi.c + + + fsl_spi_dma.c + 1 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_spi_dma.c + + + fsl_sysctl.c + 1 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_sysctl.c + + + fsl_usart.c + 1 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_usart.c + + + fsl_usart_dma.c + 1 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_usart_dma.c + + + fsl_utick.c + 1 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_utick.c + + + fsl_wwdt.c + 1 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_wwdt.c + + + fsl_sd.c + 1 + ..\Libraries\LPC55S6X\middleware\sdmmc\src\fsl_sd.c + + + fsl_sdmmc_common.c + 1 + ..\Libraries\LPC55S6X\middleware\sdmmc\src\fsl_sdmmc_common.c + + + fsl_sdmmc_event.c + 1 + ..\Libraries\LPC55S6X\middleware\sdmmc\port\sdif\rt_thread\fsl_sdmmc_event.c + + + fsl_sdmmc_host.c + 1 + ..\Libraries\LPC55S6X\middleware\sdmmc\port\sdif\rt_thread\fsl_sdmmc_host.c + + + arm_keil_lib_power_cm33_core0.lib + 4 + ..\Libraries\LPC55S6X\LPC55S6X\arm\keil_lib_power_cm33_core0.lib + + + + + + + + + + + + + + diff --git a/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/rtconfig.h b/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/rtconfig.h new file mode 100644 index 000000000..b46ecc715 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/rtconfig.h @@ -0,0 +1,208 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ + +#define SOC_LPC55S6x + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 100 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_USING_IDLE_HOOK +#define RT_IDEL_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 +#define RT_USING_TIMER_SOFT +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 512 +#define RT_DEBUG + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart" +#define RT_VER_NUM 0x40002 +#define ARCH_ARM_CORTEX_FPU + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 + +/* C++ features */ + + +/* Command shell */ + +#define RT_USING_FINSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_USING_DESCRIPTION +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_CMD_SIZE 80 +#define FINSH_USING_MSH +#define FINSH_USING_MSH_DEFAULT +#define FINSH_ARG_MAX 10 + +/* Device virtual file system */ + +#define RT_USING_DFS +#define DFS_USING_WORKDIR +#define DFS_FILESYSTEMS_MAX 2 +#define DFS_FILESYSTEM_TYPES_MAX 2 +#define DFS_FD_MAX 16 +#define RT_USING_DFS_DEVFS + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_PIPE_BUFSZ 512 +#define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_HWTIMER +#define RT_USING_I2C +#define RT_USING_I2C_BITOPS +#define RT_USING_PIN +#define RT_USING_ADC +#define RT_USING_PWM +#define RT_USING_RTC +#define RT_USING_SDIO +#define RT_SDIO_STACK_SIZE 512 +#define RT_SDIO_THREAD_PRIORITY 15 +#define RT_MMCSD_STACK_SIZE 1024 +#define RT_MMCSD_THREAD_PREORITY 22 +#define RT_MMCSD_MAX_PARTITION 16 +#define RT_USING_SPI + +/* Using USB */ + + +/* POSIX layer and C standard library */ + +#define RT_USING_LIBC +#define RT_USING_POSIX + +/* Network */ + +/* Socket abstraction layer */ + + +/* Network interface device */ + + +/* light weight TCP/IP stack */ + + +/* AT commands */ + + +/* VBUS(Virtual Software BUS) */ + + +/* Utilities */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + + +/* multimedia packages */ + + +/* tools packages */ + + +/* system packages */ + + +/* peripheral libraries and drivers */ + + +/* miscellaneous packages */ + + +/* samples: kernel and components samples */ + +#define SOC_LPC55S6X_SERIES + +/* Hardware Drivers Config */ + +#define SOC_LPC55S6X + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_PIN +#define BSP_USING_UART +#define BSP_USING_UART0 +#define HW_UART0_BAUDRATE_115200 +#define BSP_USING_I2C +#define BSP_USING_I2C4 +#define HW_I2C4_BAUDRATE_100kHZ +#define BSP_USING_SPI +#define BSP_USING_SPI8 +#define BSP_USING_ADC +#define BSP_USING_ADC0_CH0 +#define BSP_USING_SDIO +#define BSP_USING_RTC +#define BSP_USING_HWTIMER +#define BSP_USING_CTIMER0 +#define BSP_USING_PWM +#define BSP_USING_CTIMER2_MAT0 + +/* Onboard Peripheral Drivers */ + +#define BSP_USING_LED +#define BSP_USING_KEY +#define BSP_USING_MMA8562 +#define BSP_USING_MMA8562I2C "i2c4" + +/* Board extended module Drivers */ + + +#endif diff --git a/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/rtconfig.py b/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/rtconfig.py new file mode 100644 index 000000000..25d2373c3 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/rtconfig.py @@ -0,0 +1,161 @@ +import os +import sys + +# toolchains options +ARCH='arm' +CPU='cortex-m4' +CROSS_TOOL='gcc' +BOARD_NAME = 'lpcxpresso' + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'C:\Users\XXYYZZ' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = r'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iar' + EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.3' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' +#BUILD = 'release' + +if PLATFORM == 'gcc': + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + CXX = PREFIX + 'g++' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + STRIP = PREFIX + 'strip' + + DEVICE = ' -mcpu=' + CPU + ' -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -Wall -D__FPU_PRESENT -eentry' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb -D__START=entry' + LFLAGS = DEVICE + ' -lm -lgcc -lc' + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -gdwarf-2' + AFLAGS += ' -gdwarf-2' + CFLAGS += ' -O0' + else: + CFLAGS += ' -O2 -Os' + + POST_ACTION = OBJCPY + ' -O binary --remove-section=.boot_data --remove-section=.image_vertor_table --remove-section=.ncache $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + + # module setting + CXXFLAGS = ' -Woverloaded-virtual -fno-exceptions -fno-rtti ' + M_CFLAGS = CFLAGS + ' -mlong-calls -fPIC ' + M_CXXFLAGS = CXXFLAGS + ' -mlong-calls -fPIC' + M_LFLAGS = DEVICE + CXXFLAGS + ' -Wl,--gc-sections,-z,max-page-size=0x4' +\ + ' -shared -fPIC -nostartfiles -static-libgcc' + M_POST_ACTION = STRIP + ' -R .hash $TARGET\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + CXX = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu ' + CPU + '.fp.sp' + CFLAGS = DEVICE + ' --apcs=interwork' + AFLAGS = DEVICE + LFLAGS = DEVICE + ' --libpath "' + EXEC_PATH + '/ARM/ARMCC/lib" --info sizes --info totals --info unused --info veneers --list rtthread.map --scatter "./LPC55S69_cm33_core0_flash.scf" ' + + LFLAGS += ' --keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab)' + + CFLAGS += ' --diag_suppress=66,1296,186,6134' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC' + LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB' + + EXEC_PATH += '/arm/bin40/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' --c99' + + POST_ACTION = 'fromelf -z $TARGET' + # POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iar': + CC = 'iccarm' + CXX = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = ' -D__FPU_PRESENT' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --debug' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=' + CPU + CFLAGS += ' -e' + CFLAGS += ' --fpu=None' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' -Ol' + CFLAGS += ' --use_c++_inline' + + AFLAGS = '' + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu ' + CPU + AFLAGS += ' --fpu None' + + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + LFLAGS = ' --config "board/linker_scripts/LPC55S69_cm33_core0_flash_iar.icf"' + LFLAGS += ' --redirect _Printf=_PrintfTiny' + LFLAGS += ' --redirect _Scanf=_ScanfSmall' + LFLAGS += ' --entry __iar_program_start' + + CXXFLAGS = CFLAGS + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT): + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT) + diff --git a/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/template.ewp b/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/template.ewp new file mode 100644 index 000000000..44742f8e4 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/template.ewp @@ -0,0 +1,1040 @@ + + + 3 + + rtthread-lpc55s6x + + ARM + + 1 + + General + 3 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 35 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 10 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + diff --git a/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/template.eww b/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/template.eww new file mode 100644 index 000000000..c2cb02eb1 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\project.ewp + + + + + diff --git a/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/template.uvoptx b/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/template.uvoptx new file mode 100644 index 000000000..eb8dbe313 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/template.uvoptx @@ -0,0 +1,199 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rtthread-lpc55s6x + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 8 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 15 + + + + + + + + + + .\flashdebug.ini + BIN\CMSIS_AGDI_V8M.DLL + + + + 0 + DLGTARM + (6010=-1,-1,-1,-1,0)(6018=-1,-1,-1,-1,0)(6019=-1,-1,-1,-1,0)(6008=-1,-1,-1,-1,0)(6009=-1,-1,-1,-1,0)(6014=-1,-1,-1,-1,0)(6015=-1,-1,-1,-1,0)(6003=-1,-1,-1,-1,0)(6000=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI_V8M + -X"Any" -UAny -O206 -S9 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(6BA02477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO11 -FD20000000 -FC1000 -FN2 -FF0LPC55XX_640.FLM -FS00 -FL098000 -FP0($$Device:LPC55S69JBD100$arm\LPC55XX_640.FLM) -FF1LPC55XX_S_640.FLM -FS110000000 -FL198000 -FP1($$Device:LPC55S69JBD100$arm\LPC55XX_S_640.FLM) + + + 0 + UL2V8M + UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000 -FN2 -FF0LPC55XX_640 -FS00 -FL098000 -FF1LPC55XX_S_640 -FS110000000 -FL198000 -FP0($$Device:LPC55S69JBD100$arm\LPC55XX_640.FLM) -FP1($$Device:LPC55S69JBD100$arm\LPC55XX_S_640.FLM)) + + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 0 + 0 + 2 + 5000000 + + + + + diff --git a/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/template.uvprojx b/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/template.uvprojx new file mode 100644 index 000000000..83318aa38 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/template.uvprojx @@ -0,0 +1,391 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rtthread-lpc55s6x + 0x4 + ARM-ADS + 6120000::V6.12::.\ARMCLANG + 6120000::V6.12::.\ARMCLANG + 1 + + + LPC55S69JBD100:cm33_core0 + NXP + NXP.LPC55S69_DFP.1.0.0 + http://mcuxpresso.nxp.com/cmsis_pack/repo/ + IRAM(0x20000000,0x044000) IRAM2(0x04000000,0x8000) IROM(0x00000000,0x098000) XRAM(0x40100000,0x4000) CPUTYPE("Cortex-M33") FPU3(SFPU) DSP TZ CLOCK(12000000) ELITTLE + + + UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000 -FN2 -FF0LPC55XX_640 -FS00 -FL098000 -FF1LPC55XX_S_640 -FS110000000 -FL198000 -FP0($$Device:LPC55S69JBD100$arm\LPC55XX_640.FLM) -FP1($$Device:LPC55S69JBD100$arm\LPC55XX_S_640.FLM)) + 0 + $$Device:LPC55S69JBD100$fsl_device_registers.h + + + + + + + + + + $$Device:LPC55S69JBD100$LPC55S69_cm33_core0.xml + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\ + rtthread-lpc55s6x + 1 + 0 + 0 + 1 + 1 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + + + + SARMV8M.DLL + -MPU + TCM.DLL + -pCM33 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4101 + + 1 + BIN\UL2V8M.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M33" + + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 2 + 0 + 1 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x44000 + + + 1 + 0x0 + 0x98000 + + + 1 + 0x40100000 + 0x4000 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x98000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x40100000 + 0x4000 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x44000 + + + 0 + 0x4000000 + 0x8000 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 3 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + + --target=arm-arm-none-eabi + CPU_LPC55S69JBD100_cm33_core0, ARM_MATH_CM33, RT_USING_ARM_LIBC + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x02000000 + + .\board\linker_scripts\LPC55S69_cm33_core0_flash_mdk.scf + + + --keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab) + + + + + + + + + + + + + + + diff --git a/bsp/lpc55sxx/README.md b/bsp/lpc55sxx/README.md new file mode 100644 index 000000000..bb3858c3e --- /dev/null +++ b/bsp/lpc55sxx/README.md @@ -0,0 +1,19 @@ +# LPC55Sxx BSP 说明 + +LPC55Sxx系列 BSP ç›®å‰æ”¯æŒæƒ…况如下表所示： + +| BSP 文件夹å称 | å¼€å‘æ¿å称 | +|:------------------------- |:-------------------------- | +| **LPC55S69 系列** | | +| LPC55S69-EVK | æ©æ™ºæµ¦ LPC55S69 EVK[[官方链接]( 没有安装 MCUXpresso 软件å¯ä»¥è®¿é—®[ NXP 官网](https://www.nxp.com/cn/support/developer-resources/software-development-tools/mcuxpresso-software-and-tools:MCUXPRESSO )下载 MCUXpresso 软件。 + +LPCXpresso55S69 BSP 默认åªæ”¯æŒ Flexcomm4作为I2C，开å‘者如果需è¦ä½¿ç”¨å…¶ä»–çš„Flexcomm接å£ä½œä¸º I2C，则需è¦è‡ªå·±æ·»åŠ ã€‚ + +![spi_config](figures/i2c_config.png) + +添加 I2C4 的外设支æŒéœ€è¦ä»¥ä¸‹å‡ æ­¥ï¼š + +### 1. 打开 MCUXpresso 工程 + +打开 BSP çš„ MCUXpresso é…置文件。 + +![1543486779576](figures/open_mcuxpresso.png) + +### 2. 按原ç†å›¾é…ç½® I2C1 的引脚，并生æˆä»£ç  + +按图示顺åºé…ç½® I2C1，并生æˆä»£ç ã€‚ + +![MCUXpresso Config Tool](figures/mcux_i2c.png) + +为 BSP 添加驱动时，MCUXpress工具å¯ä»¥å¿«é€Ÿçš„完æˆé…置管脚的工作。而外设åˆå§‹åŒ–，中断é…置，DMAé…置等等则由 RT-Thread æ供的驱动文件æ¥å®Œæˆã€‚ + +### 3. 修改 Kconfig 文件 + +打开 board 文件夹下的 Kconfig æ–‡ä»¶ï¼Œæ‹·è´ I2C4 çš„é…置项，并é‡å‘½å为 I2C1 。 + +![Kconfig文件](figures/Kconfig2.png) + +### 4. é‡æ–°é…置工程 + +ç»è¿‡ä¸Šä¸€æ­¥çš„修改，此时é‡æ–°æ‰“å¼€ ENV 工具，在 menuconfig 中就会出现添加的 I2C4 çš„é…置项。 + +![MenuConfig 图](figures/config5.png) + +### 5. 生æˆå·¥ç¨‹ï¼Œæ£€æŸ¥é©±åŠ¨æ–‡ä»¶ + +使用 ENV é‡æ–°ç”Ÿæˆå·¥ç¨‹å¹¶æ‰“开，检查原有驱动文件是å¦æ”¯æŒæ–°æ·»åŠ çš„驱动（查看是å¦æœ‰æ–°é©±åŠ¨çš„é…置文件，中断函数，DMAé…置和中断函数等等），如下图所示I2C1对应的代ç ç”±ä¹‹å‰çš„ç°è‰²å˜ä¸ºé«˜äº®ã€‚ + +![i2c_code](figures/i2c_code.png) + +### 6. 编译下载 + +检查完工程åŽï¼Œç¼–译下载到开å‘æ¿ï¼Œç¨‹åºä¼šè‡ªåŠ¨å¼€å§‹è¿è¡Œã€‚输入 `list_device` 命令，å¯ä»¥çœ‹åˆ° I2C1 总线已ç»æ³¨å†Œåˆ°å†…核，说明驱动已ç»æ·»åŠ æˆåŠŸã€‚ + +![list i2c1 device](figures/run_i2c.png) + +## 4. 注æ„事项 + +- éƒ¨åˆ†é©±åŠ¨å¦‚æžœæ²¡æœ‰é€‚é… BSP 所属的 LPC55Sxx 系列，请等待 RT-Thread 团队更新。 + + - 驱动文件对 LPC55Sxx 系列的支æŒæƒ…况å¯ä»¥æŸ¥çœ‹ [LPC55Sxx系列驱动介ç»æ–‡æ¡£](./LPC55Sxx系列驱动介ç».md)。 + +- 对于驱动文件或文档说明，有任何建议或者æ„è§ï¼Œæ¬¢è¿Žå馈到 [RT_Thread GitHub](https://github.com/RT-Thread/rt-thread) 网站或 [RT-Thread 官方论å›](https://www.rt-thread.org/qa/forum.php)。 + +## 5. 附录 + +### 5.1 外设é…置总结 + +当开å‘者想è¦åœ¨ BSP 中添加更多驱动时，需è¦ä½¿ç”¨ MCUXpresso 工具æ¥é…置这些外设。对于ç»å¤§å¤šæ•°é©±åŠ¨çš„é…置，åªéœ€è¦åœ¨å·¥å…·ä¸­ä½¿èƒ½ç›¸åº”的外设å³å¯ã€‚但是对于一些å¤æ‚的外设，则需è¦æ›´å¤šçš„é…置内容。下表展示了ä¸åŒé©±åŠ¨åœ¨ MCUXpresso 工具é…置步骤的总结： + +| åºå· | 驱动 | MCUXpresso 工程中的é…置情况（**加粗部分为必åšæ­¥éª¤**） | +| :--: | :------- | :----------------------------------------------- | +| 1 | GPIO | 无需任何æ“作 | +| 2 | UART | é…置所需è¦çš„引脚（或者使用默认引脚） | +| 3 | SPI | é…置所需è¦çš„引脚（或者使用默认引脚） | +| 4 | I2C | é…置所需è¦çš„引脚（或者使用默认引脚） | +| 5 | TIMER | 无需任何æ“作，详细内容å¯å‚考5.3章节 | +| 6 | PWM | é…置所需è¦çš„引脚（或者使用默认引脚） ，详细内容å¯å‚考5.3章节 | +| 7 | ADC | é…置所需è¦çš„引脚（或者使用默认引脚），详细内容å¯å‚考5.3章节 | +| 8 | RTC | 无需任何æ“作 | +| 9 | Watchdog | 无需任何æ“作 | + +### 5.2 å¤æ‚外设é…置说明 + +本章节ç€é‡ä»‹ç»é…置步骤较为å¤æ‚的驱动。 + +#### 5.2.1 Timer 外设驱动添加说明 + + 1. 打开 lpc55sxx/lpc55s69_nxp_evk/board/Kconfig ，添加 Kconfig 选项。选中自己添加的选项åŽï¼Œç”Ÿæˆä¸€é工程，如下图所示： + + ![timer Kconfig é…ç½®](figures/timer_config1.png) + + 2. 打开工程进行编译并下载，如下图所示： + +![timer 编译](figures/timer_config2.png) + + 3. 查看结果，输入 `list_device` 命令，å¯ä»¥çœ‹åˆ° gpt1 设备已ç»æ³¨å†Œåˆ°å†…核，说明驱动已ç»æ·»åŠ æˆåŠŸã€‚ + + ![timer 编译](figures/timer_config3.png) + +#### 5.2.2 PWM 外设驱动添加说明 + + 1. 打开 MCUXpresso 工程，设置 PWM 在 MCUXpresso 里的选项，如下图所示： + + ![pwm MCUXpresso é…ç½®](figures/pwm_config1.png) + + 2. 打开 lpc55sxx/lpc55s69_nxp_evk/board/Kconfig ，添加 Kconfig 选项。选中自己添加的选项åŽï¼Œç”Ÿæˆä¸€é工程，如下图所示： + + ![pwm Kconfig é…ç½®](figures/pwm_config2.png) + + 3. 打开工程进行编译并下载，如下图所示： + + ![pwm 编译](figures/pwm_config3.png) + +4. 查看结果，输入 `list_device` 命令，å¯ä»¥çœ‹åˆ° pwm 设备已ç»æ³¨å†Œåˆ°å†…核，说明驱动已ç»æ·»åŠ æˆåŠŸã€‚ + + ![pwm 编译](figures/pwm_device.png) + +#### 5.2.3 ADC 外设驱动添加说明 + + 1. 打开 MCUXpresso 工程，设置 ADC 在 MCUXpresso 里的引脚，如下图所示： ![adc MCUXpresso é…ç½®](figures/adc_config1.png) + + 2. 打开 lpc55sxx/lpc55s69_nxp_evk/board/board/Kconfig ，添加 Kconfig 选项。选中自己添加的选项åŽï¼Œç”Ÿæˆä¸€é工程，如下图所示：![adc Kconfig é…ç½®](figures/adc_config2.png) + 3. 打开工程进行编译并下载，如下图所示： + +![adc 编译](figures/adc_config3.png) + +4. 查看结果，输入 `list_device` 命令，å¯ä»¥çœ‹åˆ° adc0 设备已ç»æ³¨å†Œåˆ°å†…核，说明驱动已ç»æ·»åŠ æˆåŠŸã€‚ + + ![adc 编译](figures/adc_config4.png) diff --git "a/bsp/lpc55sxx/docs/LPC55Sxx\347\263\273\345\210\227\351\251\261\345\212\250\344\273\213\347\273\215.md" "b/bsp/lpc55sxx/docs/LPC55Sxx\347\263\273\345\210\227\351\251\261\345\212\250\344\273\213\347\273\215.md" new file mode 100644 index 000000000..173be3247 --- /dev/null +++ "b/bsp/lpc55sxx/docs/LPC55Sxx\347\263\273\345\210\227\351\251\261\345\212\250\344\273\213\347\273\215.md" @@ -0,0 +1,58 @@ +# 外设驱动介ç»ä¸Žåº”用 + +在 RT-Thread 实时æ“作系统中，å„ç§å„样的设备驱动是通过一套 I/O 设备管ç†æ¡†æž¶æ¥ç®¡ç†çš„。设备管ç†æ¡†æž¶ç»™ä¸Šå±‚应用æ供了一套标准的设备æ“作 API，开å‘者通过调用这些标准设备æ“作 API，å¯ä»¥é«˜æ•ˆåœ°å®Œæˆå’Œåº•å±‚硬件外设的交互。设备管ç†æ¡†æž¶çš„结构如下图所示： + +![rt_device](figures/rt_device.png) + +使用 I/O 设备管ç†æ¡†æž¶å¼€å‘应用程åºï¼Œæœ‰å¦‚下优点： + +- 使用åŒä¸€å¥—标准的 API å¼€å‘应用程åºï¼Œä½¿åº”用程åºå…·æœ‰æ›´å¥½çš„移æ¤æ€§ +- 底层驱动的å‡çº§å’Œä¿®æ”¹ä¸ä¼šå½±å“åˆ°ä¸Šå±‚ä»£ç  +- 驱动和应用程åºç›¸äº’独立，方便多个开å‘者ååŒå¼€å‘ + +## 1. é©±åŠ¨åˆ†ç±»ä»‹ç» + +本å°èŠ‚ä»‹ç» BSP æ供的ä¸åŒç±»åˆ«é©±åŠ¨çš„概念，对一个 BSP 而言，有如下三类驱动： + +- **æ¿è½½å¤–设驱动**：指 MCU 之外，开å‘æ¿ä¸Šå¤–设，例如 TF å¡ã€ä»¥å¤ªç½‘å’Œ LCD ç­‰ +- **片上外设驱动**：指 MCU 芯片上的外设，例如硬件定时器ã€ADC 和看门狗等 +- **扩展模å—驱动**：指å¯ä»¥é€šè¿‡æ‰©å±•æŽ¥å£æˆ–者æœé‚¦çº¿è¿žæŽ¥çš„å¼€å‘æ¿çš„模å—，例如 ESP8266 æ¨¡å— + +这三ç§å¤–设的示æ„图如下所示： + +![Peripheral](figures/Peripheral.png) + +## 2. 外设驱动的使用方法 + +å½“å‰ RT-Thread æ供的驱动库已ç»æ”¯æŒ LPC 多个系列的 BSP。点击下表中的驱动å称，å³å¯è·³è½¬åˆ°å¯¹åº”驱动框架的介ç»æ–‡æ¡£ã€‚å¼€å‘者å¯ä»¥é€šè¿‡é˜…读相关资料，了解如何在应用开å‘中通过设备驱动框架æ¥ä½¿ç”¨è¿™äº›å¤–设驱动。 + +### 2.1 片上外设 + +| åºå· | 驱动 | 简介 | +| ---- | ------------------------------------------------------------ | ------------------------------------------------ | +| 1 | [GPIO](https://www.rt-thread.org/document/site/programming-manual/device/pin/pin/) | æ“作 GPIO 管脚 | +| 2 | [UART](https://www.rt-thread.org/document/site/programming-manual/device/uart/uart/) | 通过串å£æ”¶å‘æ•°æ® | +| 3 | [soft I2C](https://www.rt-thread.org/document/site/programming-manual/device/i2c/i2c/) | 通过软件 I2C 或者硬件 I2C 收å‘æ•°æ® | +| 4 | [SPI](https://www.rt-thread.org/document/site/programming-manual/device/spi/spi/) | 通过 SPI 收å‘æ•°æ® | +| 5 | [ADC](https://www.rt-thread.org/document/site/programming-manual/device/adc/adc/) | 测é‡ç®¡è„šä¸Šçš„æ¨¡æ‹Ÿé‡ | +| 6 | [HWTIMER](https://www.rt-thread.org/document/site/programming-manual/device/hwtimer/hwtimer/) | 使用硬件定时器实现测é‡æ—¶é—´å’Œå®šæ—¶æ‰§è¡Œå›žè°ƒå‡½æ•°åŠŸèƒ½ | +| 7 | [PWM](https://www.rt-thread.org/document/site/programming-manual/device/pwm/pwm/) | 在特定的管脚输出 PWM 波形 | +| 8 | [RTC](https://www.rt-thread.org/document/site/programming-manual/device/rtc/rtc/) | 设置和读å–时间 | +| 9 | [WATCHDOG](https://www.rt-thread.org/document/site/programming-manual/device/watchdog/watchdog/) | 看门狗驱动 | + +### 2.2 æ¿è½½å¤–设 + +| åºå· | 驱动 | 简介 | +| ---- | ---- | ---------------------------- | +| 1 | SD | 适用于 SDIO 接å£çš„ SD(TF) å¡ | + +### 2.3 æ‰©å±•æ¨¡å— + +| åºå· | 驱动 | 简介 | +| ---- | ------- | ----------------- | +| 1 | ESP8266 | 串å£è½¬ WIFI æ¨¡å— | +| 2 | RW-007 | SPI接å£çš„WIFIæ¨¡å— | + +### 2.4 é©±åŠ¨ç¤ºä¾‹ä»£ç  + +在 RT-Thread çš„ `examples\test` 目录下，有 RT-Thread æ供的基于ä¸åŒå¤–设驱动的示例代ç ã€‚在 env å·¥å…·ä¸­å¼€å¯ BSP 中è¦æµ‹è¯•çš„驱动，并将 `examples\test` 中对应的驱动框架测试文件加入工程，å³å¯å¿«é€Ÿæµ‹è¯• BSP 中æ供的驱动。 \ No newline at end of file diff --git a/bsp/lpc55sxx/docs/figures/Kconfig.png b/bsp/lpc55sxx/docs/figures/Kconfig.png new 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