From 49ef3cdca540cc55e830acc910f4227b4bf05562 Mon Sep 17 00:00:00 2001 From: Meco Man <920369182@qq.com> Date: Mon, 29 Mar 2021 07:31:02 +0800 Subject: [PATCH] [fh8620] auto formatted --- bsp/fh8620/applications/main.c | 20 +- bsp/fh8620/drivers/acw.c | 136 +- bsp/fh8620/drivers/acw.h | 248 +- bsp/fh8620/drivers/dma.c | 16 +- bsp/fh8620/drivers/dma.h | 36 +- bsp/fh8620/drivers/dma_mem.c | 26 +- bsp/fh8620/drivers/dma_mem.h | 16 +- bsp/fh8620/drivers/fh_dma.c | 1936 +++++----- bsp/fh8620/drivers/fh_dma.h | 278 +- bsp/fh8620/drivers/gpio.c | 10 +- bsp/fh8620/drivers/gpio.h | 8 +- bsp/fh8620/drivers/i2c.c | 586 +-- bsp/fh8620/drivers/i2c.h | 6 +- bsp/fh8620/drivers/interrupt.c | 38 +- bsp/fh8620/drivers/interrupt.h | 8 +- bsp/fh8620/drivers/mem_process.c | 66 +- bsp/fh8620/drivers/mmc.c | 6 +- bsp/fh8620/drivers/mmc.h | 6 +- bsp/fh8620/drivers/pwm.c | 8 +- bsp/fh8620/drivers/pwm.h | 8 +- bsp/fh8620/drivers/sadc.c | 340 +- bsp/fh8620/drivers/sadc.h | 86 +- bsp/fh8620/drivers/spi_fh_adapt.c | 138 +- bsp/fh8620/drivers/spi_fh_adapt.h | 8 +- bsp/fh8620/drivers/ssi.c | 946 ++--- bsp/fh8620/drivers/ssi.h | 104 +- bsp/fh8620/drivers/trap.c | 126 +- bsp/fh8620/drivers/uart.c | 318 +- bsp/fh8620/drivers/uart.h | 8 +- bsp/fh8620/drivers/wdt.c | 8 +- bsp/fh8620/drivers/wdt.h | 8 +- bsp/fh8620/libraries/driverlib/fh_gpio.c | 10 +- bsp/fh8620/libraries/driverlib/fh_i2c.c | 8 +- bsp/fh8620/libraries/driverlib/fh_ictl.c | 48 +- bsp/fh8620/libraries/driverlib/fh_mmc.c | 6 +- bsp/fh8620/libraries/driverlib/fh_pwm.c | 6 +- bsp/fh8620/libraries/driverlib/fh_sdio.c | 3388 ++++++++--------- bsp/fh8620/libraries/driverlib/fh_spi.c | 6 +- bsp/fh8620/libraries/driverlib/fh_timer.c | 56 +- bsp/fh8620/libraries/driverlib/fh_uart.c | 244 +- bsp/fh8620/libraries/driverlib/fh_wdt.c | 6 +- bsp/fh8620/libraries/inc/fh_driverlib.h | 8 +- bsp/fh8620/libraries/inc/fh_gpio.h | 8 +- bsp/fh8620/libraries/inc/fh_i2c.h | 8 +- bsp/fh8620/libraries/inc/fh_ictl.h | 36 +- bsp/fh8620/libraries/inc/fh_mmc.h | 6 +- bsp/fh8620/libraries/inc/fh_pwm.h | 6 +- bsp/fh8620/libraries/inc/fh_sdio.h | 332 +- bsp/fh8620/libraries/inc/fh_spi.h | 12 +- bsp/fh8620/libraries/inc/fh_timer.h | 28 +- bsp/fh8620/libraries/inc/fh_uart.h | 114 +- bsp/fh8620/libraries/inc/fh_wdt.h | 8 +- bsp/fh8620/platform/board.h | 8 +- bsp/fh8620/platform/board_info.h | 28 +- bsp/fh8620/platform/common/board_info.c | 228 +- bsp/fh8620/platform/common/chkenv.c | 12 +- bsp/fh8620/platform/fh8620/arch.h | 68 +- bsp/fh8620/platform/fh8620/iot_cam/board.c | 338 +- .../platform/fh8620/iot_cam/board_def.h | 32 +- bsp/fh8620/platform/fh8620/iot_cam/iomux.c | 1270 +++--- bsp/fh8620/platform/fh8620/iot_cam/startup.c | 74 +- bsp/fh8620/platform/fh_arch.h | 8 +- bsp/fh8620/platform/fh_def.h | 50 +- bsp/fh8620/platform/plat-v2/arch.h | 68 +- bsp/fh8620/platform/plat-v2/clock.c | 3012 +++++++-------- bsp/fh8620/platform/plat-v2/clock.h | 20 +- bsp/fh8620/platform/plat-v2/fh_pmu.c | 36 +- bsp/fh8620/platform/plat-v2/fh_pmu.h | 10 +- bsp/fh8620/platform/plat-v2/iomux.c | 354 +- bsp/fh8620/platform/plat-v2/iomux.h | 214 +- bsp/fh8620/platform/plat-v2/reset.c | 14 +- bsp/fh8620/platform/plat-v2/timer.c | 84 +- bsp/fh8620/platform/plat-v2/timer.h | 8 +- bsp/fh8620/platform/platform_def.h | 8 +- bsp/fh8620/rtconfig.h | 48 +- 75 files changed, 7944 insertions(+), 7944 deletions(-) diff --git a/bsp/fh8620/applications/main.c b/bsp/fh8620/applications/main.c index fe690504d..366245b48 100644 --- a/bsp/fh8620/applications/main.c +++ b/bsp/fh8620/applications/main.c @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,7 +18,7 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes @@ -27,18 +27,18 @@ void init_thread(void *parameter) { - rt_components_init(); + rt_components_init(); - return ; + return ; } int rt_application_init(void) { - rt_thread_t tid; + rt_thread_t tid; - tid = rt_thread_create("init", init_thread, RT_NULL, - 4096, RT_THREAD_PRIORITY_MAX/3, 20); - if (tid) rt_thread_startup(tid); + tid = rt_thread_create("init", init_thread, RT_NULL, + 4096, RT_THREAD_PRIORITY_MAX/3, 20); + if (tid) rt_thread_startup(tid); - return 0; + return 0; } diff --git a/bsp/fh8620/drivers/acw.c b/bsp/fh8620/drivers/acw.c index 49e10a3bd..6099ff0aa 100644 --- a/bsp/fh8620/drivers/acw.c +++ b/bsp/fh8620/drivers/acw.c @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,7 +18,7 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes @@ -30,12 +30,12 @@ #include "dma.h" #ifdef RT_USING_FH_ACW #if 1 -typedef struct +typedef struct { - unsigned int base; - void *vbase; - unsigned int size; - unsigned int align; + unsigned int base; + void *vbase; + unsigned int size; + unsigned int align; }MEM_DESC; #define ACW_SELFTEST 0 int buffer_malloc_withname(MEM_DESC *mem, int size, int align, char* name); @@ -222,9 +222,9 @@ void fh_acw_stop_playback(struct fh_audio_cfg *audio_config) audio_config->playback.state = stopping; writel(0, audio_dev.reg_base + ACW_TXFIFO_CTRL);//tx fifo disable if(audio_config->plauback_trans->channel_number != ACW_PLY_DMA_CHAN) - goto free_mem; + goto free_mem; if(!audio_config->plauback_trans->first_lli) - goto free_channel; + goto free_channel; audio_config->playback_dma->ops->control(audio_config->playback_dma,RT_DEVICE_CTRL_DMA_CYCLIC_STOP,audio_config->plauback_trans); audio_config->playback_dma->ops->control(audio_config->playback_dma,RT_DEVICE_CTRL_DMA_CYCLIC_FREE,audio_config->plauback_trans); free_channel: @@ -259,9 +259,9 @@ void fh_acw_stop_capture(struct fh_audio_cfg *audio_config) writel(0, audio_dev.reg_base + 8);//rx fifo disable if(audio_config->capture_trans->channel_number != ACW_CAP_DMA_CHAN) - goto free_mem; + goto free_mem; if(!audio_config->capture_trans->first_lli) - goto free_channel; + goto free_channel; audio_config->capture_dma->ops->control(audio_config->capture_dma,RT_DEVICE_CTRL_DMA_CYCLIC_STOP,audio_config->capture_trans); audio_config->capture_dma->ops->control(audio_config->capture_dma,RT_DEVICE_CTRL_DMA_CYCLIC_FREE,audio_config->capture_trans); @@ -286,10 +286,10 @@ void switch_io_type(enum audio_type type, enum io_select io_type) { rt_kprintf("audio input changed to mic_in\n"); writel( reg & (~(1<<1)),audio_dev.reg_base + ACW_ADC_PATH_CTRL); - reg = readl(audio_dev.reg_base + ACW_ADC_PATH_CTRL); - reg = reg & (~(1<<3)); - reg |=(0x1<<3); - writel(reg, audio_dev.reg_base + ACW_ADC_PATH_CTRL); + reg = readl(audio_dev.reg_base + ACW_ADC_PATH_CTRL); + reg = reg & (~(1<<3)); + reg |=(0x1<<3); + writel(reg, audio_dev.reg_base + ACW_ADC_PATH_CTRL); } else if (line_in == io_type) { @@ -397,7 +397,7 @@ void switch_input_volume(int volume) param = get_param_from_volume(volume); if (param < 0) { - rt_kprintf("capture volume error\n"); + rt_kprintf("capture volume error\n"); return; } @@ -511,25 +511,25 @@ int register_tx_dma(struct fh_audio_cfg *audio_config) if(playback_trans->channel_number == ACW_PLY_DMA_CHAN){ - ret = rt_dma_dev->ops->control(rt_dma_dev,RT_DEVICE_CTRL_DMA_CYCLIC_PREPARE,playback_trans); - if(ret){ - rt_kprintf("can't playback cyclic prepare \n"); - return RT_ERROR; - } - ret = rt_dma_dev->ops->control(rt_dma_dev,RT_DEVICE_CTRL_DMA_CYCLIC_START,playback_trans); - if(ret){ - rt_kprintf("can't playback cyclic start \n"); - return RT_ERROR; - } + ret = rt_dma_dev->ops->control(rt_dma_dev,RT_DEVICE_CTRL_DMA_CYCLIC_PREPARE,playback_trans); + if(ret){ + rt_kprintf("can't playback cyclic prepare \n"); + return RT_ERROR; + } + ret = rt_dma_dev->ops->control(rt_dma_dev,RT_DEVICE_CTRL_DMA_CYCLIC_START,playback_trans); + if(ret){ + rt_kprintf("can't playback cyclic start \n"); + return RT_ERROR; + } } else - return RT_ERROR; + return RT_ERROR; return 0; } int register_rx_dma( struct fh_audio_cfg *audio_config) { - int ret; + int ret; struct dma_transfer *capture_slave; capture_slave = audio_config->capture_trans; struct rt_dma_device *rt_dma_dev; @@ -546,19 +546,19 @@ int register_rx_dma( struct fh_audio_cfg *audio_config) return RT_ERROR; } if(capture_slave->channel_number==ACW_CAP_DMA_CHAN){ - ret = rt_dma_dev->ops->control(rt_dma_dev,RT_DEVICE_CTRL_DMA_CYCLIC_PREPARE,capture_slave); - if(ret){ - rt_kprintf("can't capture cyclic prepare \n"); - return RT_ERROR; - } - ret = rt_dma_dev->ops->control(rt_dma_dev,RT_DEVICE_CTRL_DMA_CYCLIC_START,capture_slave); - if(ret){ - rt_kprintf("can't capture cyclic start \n"); - return RT_ERROR; - } + ret = rt_dma_dev->ops->control(rt_dma_dev,RT_DEVICE_CTRL_DMA_CYCLIC_PREPARE,capture_slave); + if(ret){ + rt_kprintf("can't capture cyclic prepare \n"); + return RT_ERROR; + } + ret = rt_dma_dev->ops->control(rt_dma_dev,RT_DEVICE_CTRL_DMA_CYCLIC_START,capture_slave); + if(ret){ + rt_kprintf("can't capture cyclic start \n"); + return RT_ERROR; + } } else - return RT_ERROR; + return RT_ERROR; writel(0x11,audio_dev.reg_base + ACW_RXFIFO_CTRL);//clear rx fifo writel(0x30029,audio_dev.reg_base + ACW_RXFIFO_CTRL);/*enable rx fifo*/ @@ -614,13 +614,13 @@ int fh_acw_start_playback(struct fh_audio_cfg *audio_config) audio_config->playback.state = running; ret = audio_request_playback_channel(audio_config); if(ret){ - rt_kprintf("can't request playback channel\n"); - return ret; + rt_kprintf("can't request playback channel\n"); + return ret; } ret = register_tx_dma(audio_config); if (ret < 0) { - rt_kprintf("can't register tx dma\n"); + rt_kprintf("can't register tx dma\n"); return ret; } rt_list_init(&(playback_wq.list)); @@ -638,7 +638,7 @@ int fh_acw_start_playback(struct fh_audio_cfg *audio_config) int fh_acw_start_capture(struct fh_audio_cfg *audio_config) { - int ret; + int ret; if(audio_config->capture.state == running) { return 0; @@ -654,8 +654,8 @@ int fh_acw_start_capture(struct fh_audio_cfg *audio_config) audio_config->capture.state = running; ret = audio_request_capture_channel(audio_config); if(ret){ - rt_kprintf("can't request capture channel \n"); - return ret; + rt_kprintf("can't request capture channel \n"); + return ret; } return register_rx_dma(audio_config); @@ -698,12 +698,12 @@ static void fh_acw_tx_dma_done(void *arg) audio_config->playback.hw_ptr = audio_config->playback.hw_ptr - audio_config->playback.size; } - int avail = avail_data_len(playback,audio_config); - if (avail > audio_config->playback.cfg.period_bytes) - { + int avail = avail_data_len(playback,audio_config); + if (avail > audio_config->playback.cfg.period_bytes) + { - rt_sem_release(&audio_config->sem_playback); - } + rt_sem_release(&audio_config->sem_playback); + } #endif } @@ -719,12 +719,12 @@ int arg_config_support(struct fh_audio_cfg_arg * cfg) ret = get_param_from_volume(cfg->volume); if (ret < 0) { - rt_kprintf("invalid volume\n"); + rt_kprintf("invalid volume\n"); return -EINVAL; } ret = get_factor_from_table(cfg->rate); if (ret < 0) { - rt_kprintf("invalid rate\n"); + rt_kprintf("invalid rate\n"); return -EINVAL; } return 0; @@ -1084,7 +1084,7 @@ static void fh_audio_interrupt(int irq, void *param) void audio_prealloc_dma_buffer(int aiaotype,struct fh_audio_cfg *audio_config) { - if(aiaotype == mic_in || aiaotype == line_in){ + if(aiaotype == mic_in || aiaotype == line_in){ audio_config->capture.area = (void *)fh_dma_mem_malloc(audio_config->capture.cfg.buffer_bytes \ + audio_config->capture.cfg.period_bytes); @@ -1093,8 +1093,8 @@ void audio_prealloc_dma_buffer(int aiaotype,struct fh_audio_cfg *audio_config) rt_kprintf("no enough mem for capture buffer alloc\n"); return ; } - } - if(aiaotype == speaker_out || aiaotype == line_out){ + } + if(aiaotype == speaker_out || aiaotype == line_out){ audio_config->playback.area = (void *)fh_dma_mem_malloc(audio_config->playback.cfg.buffer_bytes \ + audio_config->playback.cfg.period_bytes); @@ -1169,9 +1169,9 @@ int audio_request_capture_channel(struct fh_audio_cfg *audio_config){ rt_dma_dev->ops->control(rt_dma_dev,RT_DEVICE_CTRL_DMA_OPEN,dma_rx_transfer); ret = rt_dma_dev->ops->control(rt_dma_dev,RT_DEVICE_CTRL_DMA_REQUEST_CHANNEL,dma_rx_transfer); if(ret){ - rt_kprintf("can't request capture channel\n"); - dma_rx_transfer->channel_number =0xff; - return -ret; + rt_kprintf("can't request capture channel\n"); + dma_rx_transfer->channel_number =0xff; + return -ret; } } @@ -1219,9 +1219,9 @@ int audio_request_playback_channel(struct fh_audio_cfg *audio_config) rt_dma_dev->ops->control(rt_dma_dev,RT_DEVICE_CTRL_DMA_OPEN,dma_tx_transfer); ret = rt_dma_dev->ops->control(rt_dma_dev,RT_DEVICE_CTRL_DMA_REQUEST_CHANNEL,dma_tx_transfer); if(ret){ - rt_kprintf("can't request playbak channel\n"); - dma_tx_transfer->channel_number = 0xff; - return -ret; + rt_kprintf("can't request playbak channel\n"); + dma_tx_transfer->channel_number = 0xff; + return -ret; } return 0; @@ -1320,7 +1320,7 @@ void fh_acw_test(){ cfg.frame_bit = 16; cfg.io_type = mic_in; - + cfg.period_size = BUFF_SIZE/8; cfg.rate = 8000; cfg.volume = 80; @@ -1344,18 +1344,18 @@ void fh_acw_test(){ ret = acw_dev->control(acw_dev,AC_AI_EN,&cfg); if(ret) - acw_dev->control(acw_dev,AC_AI_DISABLE,&cfg); + acw_dev->control(acw_dev,AC_AI_DISABLE,&cfg); cfg.io_type = line_out; acw_dev->control(acw_dev,AC_INIT_PLAYBACK_MEM,&cfg); ret = acw_dev->control(acw_dev,AC_AO_EN,&cfg); if(ret){ - acw_dev->control(acw_dev,AC_AO_DISABLE,&cfg); + acw_dev->control(acw_dev,AC_AO_DISABLE,&cfg); // acw_dev->control(acw_dev,AC_SET_OUTPUT_MODE,&output); - return ; + return ; } - for(i=0;i<100;i++) + for(i=0;i<100;i++) { rx: @@ -1374,7 +1374,7 @@ tx: acw_dev->write(acw_dev,0,&rx_buff[0],1024*8); } - acw_dev->close(acw_dev); + acw_dev->close(acw_dev); } #ifdef RT_USING_FINSH diff --git a/bsp/fh8620/drivers/acw.h b/bsp/fh8620/drivers/acw.h index 2156d343f..82fce3b9f 100644 --- a/bsp/fh8620/drivers/acw.h +++ b/bsp/fh8620/drivers/acw.h @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,12 +18,12 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + #ifndef ACW_H_ #define ACW_H_ #include @@ -37,86 +37,86 @@ typedef unsigned long long dma_addr_t; struct scatterlist { #ifdef CONFIG_DEBUG_SG - unsigned long sg_magic; + unsigned long sg_magic; #endif - unsigned long page_link; - unsigned int offset; - unsigned int length; - dma_addr_t dma_address; + unsigned long page_link; + unsigned int offset; + unsigned int length; + dma_addr_t dma_address; #ifdef CONFIG_NEED_SG_DMA_LENGTH - unsigned int dma_length; + unsigned int dma_length; #endif }; #define readl(a) (*(volatile rt_uint32_t *)(a)) -#define rkqueue_struct rt_workqueue -#define work_struct rt_work -#define INIT_WORK(work,func) rt_work_init(work,func,RT_NULL); -#define queue_work rt_workqueue_dowork +#define rkqueue_struct rt_workqueue +#define work_struct rt_work +#define INIT_WORK(work,func) rt_work_init(work,func,RT_NULL); +#define queue_work rt_workqueue_dowork //timer -#define timer_list rt_timer -#define wait_queue_head_t struct rt_event -#define init_waitqueue_head(event_t) rt_event_init(event_t, "audio_event", RT_IPC_FLAG_FIFO) +#define timer_list rt_timer +#define wait_queue_head_t struct rt_event +#define init_waitqueue_head(event_t) rt_event_init(event_t, "audio_event", RT_IPC_FLAG_FIFO) typedef enum{ - AC_SR_8K = 8000, - AC_SR_16K = 16000, - AC_SR_32K = 32000, - AC_SR_441K = 44100, - AC_SR_48K = 48000, + AC_SR_8K = 8000, + AC_SR_16K = 16000, + AC_SR_32K = 32000, + AC_SR_441K = 44100, + AC_SR_48K = 48000, } FH_AC_SAMPLE_RATE_E; typedef enum{ - AC_BW_8 = 8, - AC_BW_16 = 16, - AC_BW_24 = 24, + AC_BW_8 = 8, + AC_BW_16 = 16, + AC_BW_24 = 24, } FH_AC_BIT_WIDTH_E; enum io_select{ - mic_in = 0, - line_in = 1, - speaker_out = 2, - line_out = 3, + mic_in = 0, + line_in = 1, + speaker_out = 2, + line_out = 3, }; struct fh_audio_cfg_arg{ - enum io_select io_type; - int volume; - int rate; - int frame_bit; - int channels; - int buffer_size; - int period_size; + enum io_select io_type; + int volume; + int rate; + int frame_bit; + int channels; + int buffer_size; + int period_size; }; typedef struct{ - unsigned int len; - unsigned char *data; + unsigned int len; + unsigned char *data; }FH_AC_FRAME_S; typedef enum{ - FH_AC_MIC_IN = 0, - FH_AC_LINE_IN = 1, - FH_AC_SPK_OUT = 2, - FH_AC_LINE_OUT = 3 + FH_AC_MIC_IN = 0, + FH_AC_LINE_IN = 1, + FH_AC_SPK_OUT = 2, + FH_AC_LINE_OUT = 3 }FH_AC_IO_TYPE_E; typedef struct { - FH_AC_IO_TYPE_E io_type; - FH_AC_SAMPLE_RATE_E sample_rate; - FH_AC_BIT_WIDTH_E bit_width; - unsigned int channels; - unsigned int period_size; - unsigned int volume; + FH_AC_IO_TYPE_E io_type; + FH_AC_SAMPLE_RATE_E sample_rate; + FH_AC_BIT_WIDTH_E bit_width; + unsigned int channels; + unsigned int period_size; + unsigned int volume; } FH_AC_CONFIG; struct device_dma_parameters { - /* - * a low level driver may set these to teach IOMMU code about - * sg limitations. - */ - unsigned int max_segment_size; - unsigned long segment_boundary_mask; + /* + * a low level driver may set these to teach IOMMU code about + * sg limitations. + */ + unsigned int max_segment_size; + unsigned long segment_boundary_mask; }; struct list_head { @@ -124,32 +124,32 @@ struct list_head { struct list_head *prev; }; struct dma_coherent_mem { - void *virt_base; - dma_addr_t device_base; - int size; - int flags; - unsigned long *bitmap; + void *virt_base; + dma_addr_t device_base; + int size; + int flags; + unsigned long *bitmap; }; struct device_acw{ - unsigned long long *dma_mask; /* dma mask (if dma'able device) */ - unsigned long long coherent_dma_mask;/* Like dma_mask, but for - alloc_coherent mappings as - not all hardware supports - 64 bit addresses for consistent - allocations such descriptors. */ - struct device_dma_parameters *dma_parms; + unsigned long long *dma_mask; /* dma mask (if dma'able device) */ + unsigned long long coherent_dma_mask;/* Like dma_mask, but for + alloc_coherent mappings as + not all hardware supports + 64 bit addresses for consistent + allocations such descriptors. */ + struct device_dma_parameters *dma_parms; - struct list_head dma_pools; + struct list_head dma_pools; - struct dma_coherent_mem *dma_mem; + struct dma_coherent_mem *dma_mem; }; #define false 0 #define true 1 -#define AC_INIT_CAPTURE_MEM 0x10 -#define AC_INIT_PLAYBACK_MEM 0x11 +#define AC_INIT_CAPTURE_MEM 0x10 +#define AC_INIT_PLAYBACK_MEM 0x11 #define AC_SET_VOL 0x12 @@ -160,73 +160,73 @@ struct device_acw{ #define AC_AI_EN 0x15 #define AC_AO_EN 0x16 #define AC_AI_DISABLE 0x17 -#define AC_AO_DISABLE 0x18 -#define AC_AI_PAUSE 0x19 -#define AC_AI_RESUME 0x1a -#define AC_AO_PAUSE 0x1b -#define AC_AO_RESUME 0x1c -#define AC_MIC_BOOST 0x1d +#define AC_AO_DISABLE 0x18 +#define AC_AI_PAUSE 0x19 +#define AC_AI_RESUME 0x1a +#define AC_AO_PAUSE 0x1b +#define AC_AO_RESUME 0x1c +#define AC_MIC_BOOST 0x1d -#define POLLIN 0x001 /* There is data to read. */ -#define POLLPRI 0x002 /* There is urgent data to read. */ -#define POLLOUT 0x004 /* Writing now will not block. */ +#define POLLIN 0x001 /* There is data to read. */ +#define POLLPRI 0x002 /* There is urgent data to read. */ +#define POLLOUT 0x004 /* Writing now will not block. */ /* These values are defined in XPG4.2. */ -# define POLLRDNORM 0x040 /* Normal data may be read. */ -# define POLLRDBAND 0x080 /* Priority data may be read. */ -# define POLLWRNORM 0x100 /* Writing now will not block. */ -# define POLLWRBAND 0x200 /* Priority data may be written. */ +# define POLLRDNORM 0x040 /* Normal data may be read. */ +# define POLLRDBAND 0x080 /* Priority data may be read. */ +# define POLLWRNORM 0x100 /* Writing now will not block. */ +# define POLLWRBAND 0x200 /* Priority data may be written. */ /* These are extensions for Linux. */ -# define POLLMSG 0x400 -# define POLLREMOVE 0x1000 -# define POLLRDHUP 0x2000 +# define POLLMSG 0x400 +# define POLLREMOVE 0x1000 +# define POLLRDHUP 0x2000 /* Event types always implicitly polled for. These bits need not be set in `events', but they will appear in `revents' to indicate the status of the file descriptor. */ -#define POLLERR 0x008 /* Error condition. */ -#define POLLHUP 0x010 /* Hung up. */ -#define POLLNVAL 0x020 /* Invalid polling request. */ - -#define EPERM 1 /* Operation not permitted */ -#define ENOENT 2 /* No such file or directory */ -#define ESRCH 3 /* No such process */ -#define EINTR 4 /* Interrupted system call */ -#define EIO 5 /* I/O error */ -#define ENXIO 6 /* No such device or address */ -#define E2BIG 7 /* Argument list too long */ -#define ENOEXEC 8 /* Exec format error */ -#define EBADF 9 /* Bad file number */ -#define ECHILD 10 /* No child processes */ -#define EAGAIN 11 /* Try again */ -#define ENOMEM 12 /* Out of memory */ -#define EACCES 13 /* Permission denied */ -#define EFAULT 14 /* Bad address */ -#define ENOTBLK 15 /* Block device required */ -#define EBUSY 16 /* Device or resource busy */ -#define EEXIST 17 /* File exists */ -#define EXDEV 18 /* Cross-device link */ -#define ENODEV 19 /* No such device */ -#define ENOTDIR 20 /* Not a directory */ -#define EISDIR 21 /* Is a directory */ -#define EINVAL 22 /* Invalid argument */ -#define ENFILE 23 /* File table overflow */ -#define EMFILE 24 /* Too many open files */ -#define ENOTTY 25 /* Not a typewriter */ -#define ETXTBSY 26 /* Text file busy */ -#define EFBIG 27 /* File too large */ -#define ENOSPC 28 /* No space left on device */ -#define ESPIPE 29 /* Illegal seek */ -#define EROFS 30 /* Read-only file system */ -#define EMLINK 31 /* Too many links */ -#define EPIPE 32 /* Broken pipe */ -#define EDOM 33 /* Math argument out of domain of func */ -#define ERANGE 34 /* Math result not representable */ +#define POLLERR 0x008 /* Error condition. */ +#define POLLHUP 0x010 /* Hung up. */ +#define POLLNVAL 0x020 /* Invalid polling request. */ + +#define EPERM 1 /* Operation not permitted */ +#define ENOENT 2 /* No such file or directory */ +#define ESRCH 3 /* No such process */ +#define EINTR 4 /* Interrupted system call */ +#define EIO 5 /* I/O error */ +#define ENXIO 6 /* No such device or address */ +#define E2BIG 7 /* Argument list too long */ +#define ENOEXEC 8 /* Exec format error */ +#define EBADF 9 /* Bad file number */ +#define ECHILD 10 /* No child processes */ +#define EAGAIN 11 /* Try again */ +#define ENOMEM 12 /* Out of memory */ +#define EACCES 13 /* Permission denied */ +#define EFAULT 14 /* Bad address */ +#define ENOTBLK 15 /* Block device required */ +#define EBUSY 16 /* Device or resource busy */ +#define EEXIST 17 /* File exists */ +#define EXDEV 18 /* Cross-device link */ +#define ENODEV 19 /* No such device */ +#define ENOTDIR 20 /* Not a directory */ +#define EISDIR 21 /* Is a directory */ +#define EINVAL 22 /* Invalid argument */ +#define ENFILE 23 /* File table overflow */ +#define EMFILE 24 /* Too many open files */ +#define ENOTTY 25 /* Not a typewriter */ +#define ETXTBSY 26 /* Text file busy */ +#define EFBIG 27 /* File too large */ +#define ENOSPC 28 /* No space left on device */ +#define ESPIPE 29 /* Illegal seek */ +#define EROFS 30 /* Read-only file system */ +#define EMLINK 31 /* Too many links */ +#define EPIPE 32 /* Broken pipe */ +#define EDOM 33 /* Math argument out of domain of func */ +#define ERANGE 34 /* Math result not representable */ extern void fh_audio_init(void); extern void fh_acw_test(); #endif diff --git a/bsp/fh8620/drivers/dma.c b/bsp/fh8620/drivers/dma.c index 394ac2a6a..3105f9261 100644 --- a/bsp/fh8620/drivers/dma.c +++ b/bsp/fh8620/drivers/dma.c @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,12 +18,12 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + /***************************************************************************** * Include Section * add all #include here @@ -88,7 +88,7 @@ static rt_err_t rt_dma_control(struct rt_device *dev, *****************************************************************************/ static rt_err_t rt_dma_init(struct rt_device *dev) { - struct rt_dma_device *dma; + struct rt_dma_device *dma; RT_ASSERT(dev != RT_NULL); dma = (struct rt_dma_device *)dev; @@ -107,7 +107,7 @@ static rt_err_t rt_dma_open(struct rt_device *dev, rt_uint16_t oflag) static rt_err_t rt_dma_close(struct rt_device *dev) { - struct rt_dma_device *dma; + struct rt_dma_device *dma; RT_ASSERT(dev != RT_NULL); dma = (struct rt_dma_device *)dev; @@ -124,7 +124,7 @@ static rt_err_t rt_dma_control(struct rt_device *dev, rt_uint8_t cmd, void *args) { - struct rt_dma_device *dma; + struct rt_dma_device *dma; RT_ASSERT(dev != RT_NULL); dma = (struct rt_dma_device *)dev; @@ -141,7 +141,7 @@ rt_err_t rt_hw_dma_register(struct rt_dma_device *dma, rt_uint32_t flag, void *data) { - rt_uint32_t ret; + rt_uint32_t ret; struct rt_device *device; RT_ASSERT(dma != RT_NULL); diff --git a/bsp/fh8620/drivers/dma.h b/bsp/fh8620/drivers/dma.h index c8c3fbf57..2ef325319 100644 --- a/bsp/fh8620/drivers/dma.h +++ b/bsp/fh8620/drivers/dma.h @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,7 +18,7 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes @@ -29,31 +29,31 @@ #include /**************************************************************************** * #include section -* add #include here if any +* add #include here if any ***************************************************************************/ /**************************************************************************** * #define section -* add constant #define here if any +* add constant #define here if any ***************************************************************************/ -#define RT_DEVICE_CTRL_DMA_OPEN (1) -#define RT_DEVICE_CTRL_DMA_CLOSE (2) -#define RT_DEVICE_CTRL_DMA_REQUEST_CHANNEL (3) -#define RT_DEVICE_CTRL_DMA_RELEASE_CHANNEL (4) -#define RT_DEVICE_CTRL_DMA_SINGLE_TRANSFER (5) +#define RT_DEVICE_CTRL_DMA_OPEN (1) +#define RT_DEVICE_CTRL_DMA_CLOSE (2) +#define RT_DEVICE_CTRL_DMA_REQUEST_CHANNEL (3) +#define RT_DEVICE_CTRL_DMA_RELEASE_CHANNEL (4) +#define RT_DEVICE_CTRL_DMA_SINGLE_TRANSFER (5) //cyclic add func below.... -#define RT_DEVICE_CTRL_DMA_CYCLIC_PREPARE (6) -#define RT_DEVICE_CTRL_DMA_CYCLIC_START (7) -#define RT_DEVICE_CTRL_DMA_CYCLIC_STOP (8) -#define RT_DEVICE_CTRL_DMA_CYCLIC_FREE (9) +#define RT_DEVICE_CTRL_DMA_CYCLIC_PREPARE (6) +#define RT_DEVICE_CTRL_DMA_CYCLIC_START (7) +#define RT_DEVICE_CTRL_DMA_CYCLIC_STOP (8) +#define RT_DEVICE_CTRL_DMA_CYCLIC_FREE (9) -//#define RT_DEVICE_CTRL_ (3) /* get the left time before reboot(in seconds) */ +//#define RT_DEVICE_CTRL_ (3) /* get the left time before reboot(in seconds) */ //#define RT_DEVICE_CTRL_ (4) /* refresh watchdog */ //#define RT_DEVICE_CTRL_ (5) /* start watchdog */ //#define RT_DEVICE_CTRL_ (6) /* stop watchdog */ @@ -64,13 +64,13 @@ /**************************************************************************** * ADT section -* add Abstract Data Type definition here +* add Abstract Data Type definition here ***************************************************************************/ struct rt_dma_ops; struct rt_dma_device { - // the parent must be the fitst para.. + // the parent must be the fitst para.. struct rt_device parent; struct rt_dma_ops *ops; }; @@ -91,7 +91,7 @@ struct rt_dma_ops /**************************************************************************** * section -* add function prototype here if any +* add function prototype here if any ***************************************************************************/ rt_err_t rt_hw_dma_register(struct rt_dma_device *dma, const char *name, diff --git a/bsp/fh8620/drivers/dma_mem.c b/bsp/fh8620/drivers/dma_mem.c index 52c9e56b4..9360ab5b8 100644 --- a/bsp/fh8620/drivers/dma_mem.c +++ b/bsp/fh8620/drivers/dma_mem.c @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,12 +18,12 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + /***************************************************************************** * Include Section * add all #include here @@ -86,27 +86,27 @@ static struct rt_memheap dma_heap = {0}; * what does this function returned? *****************************************************************************/ rt_err_t fh_dma_mem_init(rt_uint32_t *mem_start,rt_uint32_t size){ - return rt_memheap_init(&dma_heap,"dma_heap",mem_start,size); + return rt_memheap_init(&dma_heap,"dma_heap",mem_start,size); } void *fh_dma_mem_malloc(rt_uint32_t size){ - return rt_memheap_alloc(&dma_heap, size); + return rt_memheap_alloc(&dma_heap, size); } void fh_dma_mem_free(void *ptr){ - rt_memheap_free(ptr); + rt_memheap_free(ptr); } #ifdef FH_TEST_DMA_MEM int dma_mem_debug(void *ptr){ - //rt_memheap_free(ptr); - rt_kprintf("dma mem start 0x%08x\n",(rt_uint32_t)dma_heap.start_addr); - rt_kprintf("dma mem total size 0x%08x\n",dma_heap.pool_size); - rt_kprintf("dma mem left size 0x%08x\n",dma_heap.available_size); - rt_kprintf("dma mem max use size 0x%08x\n",dma_heap.max_used_size); - return 0; + //rt_memheap_free(ptr); + rt_kprintf("dma mem start 0x%08x\n",(rt_uint32_t)dma_heap.start_addr); + rt_kprintf("dma mem total size 0x%08x\n",dma_heap.pool_size); + rt_kprintf("dma mem left size 0x%08x\n",dma_heap.available_size); + rt_kprintf("dma mem max use size 0x%08x\n",dma_heap.max_used_size); + return 0; } #endif diff --git a/bsp/fh8620/drivers/dma_mem.h b/bsp/fh8620/drivers/dma_mem.h index b431703a4..fea422243 100644 --- a/bsp/fh8620/drivers/dma_mem.h +++ b/bsp/fh8620/drivers/dma_mem.h @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,12 +18,12 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + #ifndef DMA_MEM_H_ #define DMA_MEM_H_ @@ -36,20 +36,20 @@ #include /**************************************************************************** * #include section -* add #include here if any +* add #include here if any ***************************************************************************/ /**************************************************************************** * #define section -* add constant #define here if any +* add constant #define here if any ***************************************************************************/ /**************************************************************************** * ADT section -* add Abstract Data Type definition here +* add Abstract Data Type definition here ***************************************************************************/ @@ -61,7 +61,7 @@ /**************************************************************************** * section -* add function prototype here if any +* add function prototype here if any ***************************************************************************/ #ifdef RT_USING_DMA_MEM rt_err_t fh_dma_mem_init(rt_uint32_t *mem_start,rt_uint32_t size); diff --git a/bsp/fh8620/drivers/fh_dma.c b/bsp/fh8620/drivers/fh_dma.c index c50ae1e1d..d44ecf4e1 100644 --- a/bsp/fh8620/drivers/fh_dma.c +++ b/bsp/fh8620/drivers/fh_dma.c @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,12 +18,12 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + /***************************************************************************** * Include Section * add all #include here @@ -45,187 +45,187 @@ //#define DMA_DEBUG #ifdef DMA_DEBUG -#define FH_DMA_DEBUG(fmt, args...) \ - rt_kprintf(fmt,##args); +#define FH_DMA_DEBUG(fmt, args...) \ + rt_kprintf(fmt,##args); #else #define FH_DMA_DEBUG(fmt, args...) #endif -#define DMA_REG_BASE (0xEE000000) -#define DMA_CONTROLLER_NUMBER (1) +#define DMA_REG_BASE (0xEE000000) +#define DMA_CONTROLLER_NUMBER (1) -#define WORK_QUEUE_STACK_SIZE 512 -#define WORK_QUEUE_PRIORITY 12 +#define WORK_QUEUE_STACK_SIZE 512 +#define WORK_QUEUE_PRIORITY 12 -#define TEST_PER_NO (10) +#define TEST_PER_NO (10) -#define DESC_MAX_SIZE (20) +#define DESC_MAX_SIZE (20) /********************************* * * copy from the linux core start * *********************************/ //this is the ip reg offset....don't change!!!!!!! -#define DW_DMA_MAX_NR_CHANNELS 8 +#define DW_DMA_MAX_NR_CHANNELS 8 /* * Redefine this macro to handle differences between 32- and 64-bit * addressing, big vs. little endian, etc. */ -#define DW_REG(name) rt_uint32_t name; rt_uint32_t __pad_##name +#define DW_REG(name) rt_uint32_t name; rt_uint32_t __pad_##name /* Hardware register definitions. */ struct dw_dma_chan_regs { - DW_REG(SAR); /* Source Address Register */ - DW_REG(DAR); /* Destination Address Register */ - DW_REG(LLP); /* Linked List Pointer */ - rt_uint32_t CTL_LO; /* Control Register Low */ - rt_uint32_t CTL_HI; /* Control Register High */ - DW_REG(SSTAT); - DW_REG(DSTAT); - DW_REG(SSTATAR); - DW_REG(DSTATAR); - rt_uint32_t CFG_LO; /* Configuration Register Low */ - rt_uint32_t CFG_HI; /* Configuration Register High */ - DW_REG(SGR); - DW_REG(DSR); + DW_REG(SAR); /* Source Address Register */ + DW_REG(DAR); /* Destination Address Register */ + DW_REG(LLP); /* Linked List Pointer */ + rt_uint32_t CTL_LO; /* Control Register Low */ + rt_uint32_t CTL_HI; /* Control Register High */ + DW_REG(SSTAT); + DW_REG(DSTAT); + DW_REG(SSTATAR); + DW_REG(DSTATAR); + rt_uint32_t CFG_LO; /* Configuration Register Low */ + rt_uint32_t CFG_HI; /* Configuration Register High */ + DW_REG(SGR); + DW_REG(DSR); }; struct dw_dma_irq_regs { - DW_REG(XFER); - DW_REG(BLOCK); - DW_REG(SRC_TRAN); - DW_REG(DST_TRAN); - DW_REG(ERROR); + DW_REG(XFER); + DW_REG(BLOCK); + DW_REG(SRC_TRAN); + DW_REG(DST_TRAN); + DW_REG(ERROR); }; struct dw_dma_regs { - /* per-channel registers */ - struct dw_dma_chan_regs CHAN[DW_DMA_MAX_NR_CHANNELS]; - - /* irq handling */ - struct dw_dma_irq_regs RAW; /* r */ - struct dw_dma_irq_regs STATUS; /* r (raw & mask) */ - struct dw_dma_irq_regs MASK; /* rw (set = irq enabled) */ - struct dw_dma_irq_regs CLEAR; /* w (ack, affects "raw") */ - - DW_REG(STATUS_INT); /* r */ - - /* software handshaking */ - DW_REG(REQ_SRC); - DW_REG(REQ_DST); - DW_REG(SGL_REQ_SRC); - DW_REG(SGL_REQ_DST); - DW_REG(LAST_SRC); - DW_REG(LAST_DST); - - /* miscellaneous */ - DW_REG(CFG); - DW_REG(CH_EN); - DW_REG(ID); - DW_REG(TEST); - - /* optional encoded params, 0x3c8..0x3 */ + /* per-channel registers */ + struct dw_dma_chan_regs CHAN[DW_DMA_MAX_NR_CHANNELS]; + + /* irq handling */ + struct dw_dma_irq_regs RAW; /* r */ + struct dw_dma_irq_regs STATUS; /* r (raw & mask) */ + struct dw_dma_irq_regs MASK; /* rw (set = irq enabled) */ + struct dw_dma_irq_regs CLEAR; /* w (ack, affects "raw") */ + + DW_REG(STATUS_INT); /* r */ + + /* software handshaking */ + DW_REG(REQ_SRC); + DW_REG(REQ_DST); + DW_REG(SGL_REQ_SRC); + DW_REG(SGL_REQ_DST); + DW_REG(LAST_SRC); + DW_REG(LAST_DST); + + /* miscellaneous */ + DW_REG(CFG); + DW_REG(CH_EN); + DW_REG(ID); + DW_REG(TEST); + + /* optional encoded params, 0x3c8..0x3 */ }; /* Bitfields in CTL_LO */ -#define DWC_CTLL_INT_EN (1 << 0) /* irqs enabled? */ -#define DWC_CTLL_DST_WIDTH(n) ((n)<<1) /* bytes per element */ -#define DWC_CTLL_SRC_WIDTH(n) ((n)<<4) +#define DWC_CTLL_INT_EN (1 << 0) /* irqs enabled? */ +#define DWC_CTLL_DST_WIDTH(n) ((n)<<1) /* bytes per element */ +#define DWC_CTLL_SRC_WIDTH(n) ((n)<<4) #define DWC_CTLL_DST_INC_MODE(n) ((n)<<7) -#define DWC_CTLL_DST_INC (0<<7) /* DAR update/not */ -#define DWC_CTLL_DST_DEC (1<<7) -#define DWC_CTLL_DST_FIX (2<<7) +#define DWC_CTLL_DST_INC (0<<7) /* DAR update/not */ +#define DWC_CTLL_DST_DEC (1<<7) +#define DWC_CTLL_DST_FIX (2<<7) #define DWC_CTLL_SRC_INC_MODE(n) ((n)<<9) -#define DWC_CTLL_SRC_INC (0<<9) /* SAR update/not */ -#define DWC_CTLL_SRC_DEC (1<<9) -#define DWC_CTLL_SRC_FIX (2<<9) -#define DWC_CTLL_DST_MSIZE(n) ((n)<<11) /* burst, #elements */ -#define DWC_CTLL_SRC_MSIZE(n) ((n)<<14) -#define DWC_CTLL_S_GATH_EN (1 << 17) /* src gather, !FIX */ -#define DWC_CTLL_D_SCAT_EN (1 << 18) /* dst scatter, !FIX */ -#define DWC_CTLL_FC(n) ((n) << 20) -#define DWC_CTLL_FC_M2M (0 << 20) /* mem-to-mem */ -#define DWC_CTLL_FC_M2P (1 << 20) /* mem-to-periph */ -#define DWC_CTLL_FC_P2M (2 << 20) /* periph-to-mem */ -#define DWC_CTLL_FC_P2P (3 << 20) /* periph-to-periph */ +#define DWC_CTLL_SRC_INC (0<<9) /* SAR update/not */ +#define DWC_CTLL_SRC_DEC (1<<9) +#define DWC_CTLL_SRC_FIX (2<<9) +#define DWC_CTLL_DST_MSIZE(n) ((n)<<11) /* burst, #elements */ +#define DWC_CTLL_SRC_MSIZE(n) ((n)<<14) +#define DWC_CTLL_S_GATH_EN (1 << 17) /* src gather, !FIX */ +#define DWC_CTLL_D_SCAT_EN (1 << 18) /* dst scatter, !FIX */ +#define DWC_CTLL_FC(n) ((n) << 20) +#define DWC_CTLL_FC_M2M (0 << 20) /* mem-to-mem */ +#define DWC_CTLL_FC_M2P (1 << 20) /* mem-to-periph */ +#define DWC_CTLL_FC_P2M (2 << 20) /* periph-to-mem */ +#define DWC_CTLL_FC_P2P (3 << 20) /* periph-to-periph */ /* plus 4 transfer types for peripheral-as-flow-controller */ -#define DWC_CTLL_DMS(n) ((n)<<23) /* dst master select */ -#define DWC_CTLL_SMS(n) ((n)<<25) /* src master select */ -#define DWC_CTLL_LLP_D_EN (1 << 27) /* dest block chain */ -#define DWC_CTLL_LLP_S_EN (1 << 28) /* src block chain */ +#define DWC_CTLL_DMS(n) ((n)<<23) /* dst master select */ +#define DWC_CTLL_SMS(n) ((n)<<25) /* src master select */ +#define DWC_CTLL_LLP_D_EN (1 << 27) /* dest block chain */ +#define DWC_CTLL_LLP_S_EN (1 << 28) /* src block chain */ /* Bitfields in CTL_HI */ -#define DWC_CTLH_DONE 0x00001000 -#define DWC_CTLH_BLOCK_TS_MASK 0x00000fff +#define DWC_CTLH_DONE 0x00001000 +#define DWC_CTLH_BLOCK_TS_MASK 0x00000fff /* Bitfields in CFG_LO. Platform-configurable bits are in */ -#define DWC_CFGL_CH_PRIOR_MASK (0x7 << 5) /* priority mask */ -#define DWC_CFGL_CH_PRIOR(x) ((x) << 5) /* priority */ -#define DWC_CFGL_CH_SUSP (1 << 8) /* pause xfer */ -#define DWC_CFGL_FIFO_EMPTY (1 << 9) /* pause xfer */ +#define DWC_CFGL_CH_PRIOR_MASK (0x7 << 5) /* priority mask */ +#define DWC_CFGL_CH_PRIOR(x) ((x) << 5) /* priority */ +#define DWC_CFGL_CH_SUSP (1 << 8) /* pause xfer */ +#define DWC_CFGL_FIFO_EMPTY (1 << 9) /* pause xfer */ -#define DWC_CFGL_HS_DST (1 << 10) /* handshake w/dst */ -#define DWC_CFGL_HS_SRC (1 << 11) /* handshake w/src */ -#define DWC_CFGL_MAX_BURST(x) ((x) << 20) -#define DWC_CFGL_RELOAD_SAR (1 << 30) -#define DWC_CFGL_RELOAD_DAR (1 << 31) +#define DWC_CFGL_HS_DST (1 << 10) /* handshake w/dst */ +#define DWC_CFGL_HS_SRC (1 << 11) /* handshake w/src */ +#define DWC_CFGL_MAX_BURST(x) ((x) << 20) +#define DWC_CFGL_RELOAD_SAR (1 << 30) +#define DWC_CFGL_RELOAD_DAR (1 << 31) /* Bitfields in CFG_HI. Platform-configurable bits are in */ -#define DWC_CFGH_DS_UPD_EN (1 << 5) -#define DWC_CFGH_SS_UPD_EN (1 << 6) +#define DWC_CFGH_DS_UPD_EN (1 << 5) +#define DWC_CFGH_SS_UPD_EN (1 << 6) /* Bitfields in SGR */ -#define DWC_SGR_SGI(x) ((x) << 0) -#define DWC_SGR_SGC(x) ((x) << 20) +#define DWC_SGR_SGI(x) ((x) << 0) +#define DWC_SGR_SGC(x) ((x) << 20) /* Bitfields in DSR */ -#define DWC_DSR_DSI(x) ((x) << 0) -#define DWC_DSR_DSC(x) ((x) << 20) +#define DWC_DSR_DSI(x) ((x) << 0) +#define DWC_DSR_DSC(x) ((x) << 20) /* Bitfields in CFG */ -#define DW_CFG_DMA_EN (1 << 0) +#define DW_CFG_DMA_EN (1 << 0) -#define DW_REGLEN 0x400 +#define DW_REGLEN 0x400 /* Platform-configurable bits in CFG_HI */ -#define DWC_CFGH_FCMODE (1 << 0) -#define DWC_CFGH_FIFO_MODE (1 << 1) -#define DWC_CFGH_PROTCTL(x) ((x) << 2) -#define DWC_CFGH_SRC_PER(x) ((x) << 7) -#define DWC_CFGH_DST_PER(x) ((x) << 11) +#define DWC_CFGH_FCMODE (1 << 0) +#define DWC_CFGH_FIFO_MODE (1 << 1) +#define DWC_CFGH_PROTCTL(x) ((x) << 2) +#define DWC_CFGH_SRC_PER(x) ((x) << 7) +#define DWC_CFGH_DST_PER(x) ((x) << 11) /* Platform-configurable bits in CFG_LO */ -#define DWC_CFGL_LOCK_CH_XFER (0 << 12) /* scope of LOCK_CH */ -#define DWC_CFGL_LOCK_CH_BLOCK (1 << 12) -#define DWC_CFGL_LOCK_CH_XACT (2 << 12) -#define DWC_CFGL_LOCK_BUS_XFER (0 << 14) /* scope of LOCK_BUS */ -#define DWC_CFGL_LOCK_BUS_BLOCK (1 << 14) -#define DWC_CFGL_LOCK_BUS_XACT (2 << 14) -#define DWC_CFGL_LOCK_CH (1 << 15) /* channel lockout */ -#define DWC_CFGL_LOCK_BUS (1 << 16) /* busmaster lockout */ -#define DWC_CFGL_HS_DST_POL (1 << 18) /* dst handshake active low */ -#define DWC_CFGL_HS_SRC_POL (1 << 19) /* src handshake active low */ +#define DWC_CFGL_LOCK_CH_XFER (0 << 12) /* scope of LOCK_CH */ +#define DWC_CFGL_LOCK_CH_BLOCK (1 << 12) +#define DWC_CFGL_LOCK_CH_XACT (2 << 12) +#define DWC_CFGL_LOCK_BUS_XFER (0 << 14) /* scope of LOCK_BUS */ +#define DWC_CFGL_LOCK_BUS_BLOCK (1 << 14) +#define DWC_CFGL_LOCK_BUS_XACT (2 << 14) +#define DWC_CFGL_LOCK_CH (1 << 15) /* channel lockout */ +#define DWC_CFGL_LOCK_BUS (1 << 16) /* busmaster lockout */ +#define DWC_CFGL_HS_DST_POL (1 << 18) /* dst handshake active low */ +#define DWC_CFGL_HS_SRC_POL (1 << 19) /* src handshake active low */ -#define lift_shift_bit_num(bit_num) (1<regs)->name)) + __raw_readl(&(((struct dw_dma_regs *)dw->regs)->name)) #define dw_writel(dw, name, val) \ - __raw_writel((val), &(((struct dw_dma_regs *)dw->regs)->name)) + __raw_writel((val), &(((struct dw_dma_regs *)dw->regs)->name)) #define dw_readw(dw, name) \ - __raw_readw(&(((struct dw_dma_regs *)dw->regs)->name)) + __raw_readw(&(((struct dw_dma_regs *)dw->regs)->name)) #define dw_writew(dw, name, val) \ - __raw_writew((val), &(((struct dw_dma_regs *)dw->regs)->name)) + __raw_writew((val), &(((struct dw_dma_regs *)dw->regs)->name)) -#define CHANNEL0 (lift_shift_bit_num(0)) -#define CHANNEL1 (lift_shift_bit_num(1)) -#define CHANNEL2 (lift_shift_bit_num(2)) -#define CHANNEL3 (lift_shift_bit_num(3)) +#define CHANNEL0 (lift_shift_bit_num(0)) +#define CHANNEL1 (lift_shift_bit_num(1)) +#define CHANNEL2 (lift_shift_bit_num(2)) +#define CHANNEL3 (lift_shift_bit_num(3)) #define channel_set_bit(dw, reg, mask) \ - dw_writel(dw, reg, ((mask) << 8) | (mask)) + dw_writel(dw, reg, ((mask) << 8) | (mask)) #define channel_clear_bit(dw, reg, mask) \ - dw_writel(dw, reg, ((mask) << 8) | 0) + dw_writel(dw, reg, ((mask) << 8) | 0) @@ -275,83 +275,83 @@ struct dw_dma_regs { ***************************************************************************/ struct dw_dma{ - //vadd - void *regs; - //padd - rt_uint32_t paddr; - rt_uint32_t irq; - rt_uint32_t channel_max_number; - -#define CONTROLLER_STATUS_CLOSED (0) -#define CONTROLLER_STATUS_OPEN (1) - rt_uint32_t controller_status; -#define FH81_DMA_INIT_NOT_YET (0) -#define FH81_DMA_INIT_ALREADY (1) - rt_uint32_t init; - rt_uint32_t id; - char *name; - rt_uint32_t channel_work_done; + //vadd + void *regs; + //padd + rt_uint32_t paddr; + rt_uint32_t irq; + rt_uint32_t channel_max_number; + +#define CONTROLLER_STATUS_CLOSED (0) +#define CONTROLLER_STATUS_OPEN (1) + rt_uint32_t controller_status; +#define FH81_DMA_INIT_NOT_YET (0) +#define FH81_DMA_INIT_ALREADY (1) + rt_uint32_t init; + rt_uint32_t id; + char *name; + rt_uint32_t channel_work_done; }; struct dma_channel { -#define CHANNEL_STATUS_CLOSED (0) -#define CHANNEL_STATUS_OPEN (1) -#define CHANNEL_STATUS_IDLE (2) -#define CHANNEL_STATUS_BUSY (3) - - rt_uint32_t channel_status; //open, busy ,closed - rt_uint32_t desc_trans_size; - - //isr will set it complete. - struct rt_completion transfer_completion; - //add lock,when set the channel.lock it - struct rt_semaphore channel_lock; - //struct rt_mutex lock; - //rt_enter_critical(); - rt_list_t queue; - //active transfer now!!! - struct dma_transfer *active_trans; - -#define SINGLE_TRANSFER (0) -#define CYCLIC_TRANSFER (1) -#define DEFAULT_TRANSFER SINGLE_TRANSFER - rt_uint32_t open_flag; - // - - - - //new add para... - rt_uint32_t desc_total_no; - rt_uint32_t free_index; - rt_uint32_t used_index; - rt_uint32_t desc_left_cnt; - - rt_uint32_t allign_malloc; - struct dw_lli *base_lli; +#define CHANNEL_STATUS_CLOSED (0) +#define CHANNEL_STATUS_OPEN (1) +#define CHANNEL_STATUS_IDLE (2) +#define CHANNEL_STATUS_BUSY (3) + + rt_uint32_t channel_status; //open, busy ,closed + rt_uint32_t desc_trans_size; + + //isr will set it complete. + struct rt_completion transfer_completion; + //add lock,when set the channel.lock it + struct rt_semaphore channel_lock; + //struct rt_mutex lock; + //rt_enter_critical(); + rt_list_t queue; + //active transfer now!!! + struct dma_transfer *active_trans; + +#define SINGLE_TRANSFER (0) +#define CYCLIC_TRANSFER (1) +#define DEFAULT_TRANSFER SINGLE_TRANSFER + rt_uint32_t open_flag; + // + + + + //new add para... + rt_uint32_t desc_total_no; + rt_uint32_t free_index; + rt_uint32_t used_index; + rt_uint32_t desc_left_cnt; + + rt_uint32_t allign_malloc; + struct dw_lli *base_lli; }; struct fh81_dma{ - //core use ,this must be the first para!!!! - struct rt_dma_device parent; - //myown - struct dw_dma dwc; - //channel obj - struct dma_channel dma_channel[FH81_MAX_CHANNEL]; + //core use ,this must be the first para!!!! + struct rt_dma_device parent; + //myown + struct dw_dma dwc; + //channel obj + struct dma_channel dma_channel[FH81_MAX_CHANNEL]; - //struct rt_workqueue* isr_workqueue; - //struct rt_work *isr_work; + //struct rt_workqueue* isr_workqueue; + //struct rt_work *isr_work; }; -#define list_for_each_entry_safe(pos, n, head, member) \ - for (pos = rt_list_entry((head)->next, typeof(*pos), member), \ - n = rt_list_entry(pos->member.next, typeof(*pos), member); \ - &pos->member != (head); \ - pos = n, n = rt_list_entry(n->member.next, typeof(*n), member)) +#define list_for_each_entry_safe(pos, n, head, member) \ + for (pos = rt_list_entry((head)->next, typeof(*pos), member), \ + n = rt_list_entry(pos->member.next, typeof(*pos), member); \ + &pos->member != (head); \ + pos = n, n = rt_list_entry(n->member.next, typeof(*n), member)) /****************************************************************************** @@ -384,8 +384,8 @@ static void rt_fh_dma_cyclic_free(struct dma_transfer *p); static struct rt_dma_ops fh81_dma_ops = { - init, - control + init, + control }; @@ -398,7 +398,7 @@ static struct rt_dma_ops fh81_dma_ops = * e.g. * static uint8_t ufoo; *****************************************************************************/ -static struct fh81_dma fh81_dma_controller[DMA_CONTROLLER_NUMBER] = {0}; +static struct fh81_dma fh81_dma_controller[DMA_CONTROLLER_NUMBER] = {0}; /* function body */ /***************************************************************************** @@ -411,80 +411,80 @@ static struct fh81_dma fh81_dma_controller[DMA_CONTROLLER_NUMBER] = {0}; *****************************************************************************/ static rt_uint32_t allign_func(rt_uint32_t in_addr,rt_uint32_t allign_size){ - return (in_addr + allign_size-1) & (~(allign_size - 1)); + return (in_addr + allign_size-1) & (~(allign_size - 1)); } struct dw_lli * get_desc(struct fh81_dma *p_dma,struct dma_transfer *p_transfer,rt_uint32_t lli_size){ - struct dw_lli * ret_lli; - rt_uint32_t free_index; - rt_uint32_t allign_left; - rt_uint32_t totoal_desc; - rt_uint32_t actual_get_desc; - rt_uint32_t totoal_free_desc; - totoal_free_desc = p_dma->dma_channel[p_transfer->channel_number].desc_left_cnt; - free_index = p_dma->dma_channel[p_transfer->channel_number].free_index; - totoal_desc = p_dma->dma_channel[p_transfer->channel_number].desc_total_no; - allign_left = totoal_desc - free_index; - - //check first.. - if(totoal_free_desc < lli_size){ - rt_kprintf("not enough desc to get...\n"); - rt_kprintf("get size is %d,left is %d\n",lli_size,totoal_free_desc); - return RT_NULL; - } - //rt_kprintf("get desc in...\n"); - - //rt_kprintf("lli size is %d\n",lli_size); - if(lli_size > allign_left){ - //if allign desc not enough...just reset null.... - if((totoal_free_desc - allign_left) < lli_size){ - rt_kprintf("not enough desc to get...\n"); - rt_kprintf("app need size is %d, totoal left is %d, allign left is %d\n",lli_size,totoal_free_desc,allign_left); - rt_kprintf("from head to get desc size is %d, actual get is %d\n",(totoal_free_desc - allign_left),(allign_left +lli_size)); - return RT_NULL; - } - else{ - actual_get_desc = allign_left +lli_size; - free_index = 0; - } - } - - - //ret_lli = &p_dma->dma_channel[p_transfer->channel_number].base_lli[free_index]; - - ret_lli = &p_dma->dma_channel[p_transfer->channel_number].base_lli[free_index]; -// rt_kprintf("get desc base index addr:%08x\n",(rt_uint32_t)&p_dma->dma_channel[p_transfer->channel_number].base_lli[0]); -// rt_kprintf("get desc free index addr:%08x\n",(rt_uint32_t)ret_lli); -// rt_kprintf("get desc request size:%08x\n",lli_size); -// rt_kprintf("get desc total size:%08x\n",p_dma->dma_channel[p_transfer->channel_number].desc_total_no); -// rt_kprintf("one desc size is:%08x\n",sizeof( struct dw_lli)); - - p_dma->dma_channel[p_transfer->channel_number].free_index += actual_get_desc; - - //rt_kprintf("get desc free index addr:%08x\n",(rt_uint32_t)&p_dma->dma_channel[p_transfer->channel_number].base_lli[p_dma->dma_channel[p_transfer->channel_number].free_index]); - - p_dma->dma_channel[p_transfer->channel_number].free_index %= p_dma->dma_channel[p_transfer->channel_number].desc_total_no; - p_dma->dma_channel[p_transfer->channel_number].desc_left_cnt -= actual_get_desc; - p_transfer->lli_size = lli_size; - p_transfer->actual_lli_size = actual_get_desc; - return ret_lli; + struct dw_lli * ret_lli; + rt_uint32_t free_index; + rt_uint32_t allign_left; + rt_uint32_t totoal_desc; + rt_uint32_t actual_get_desc; + rt_uint32_t totoal_free_desc; + totoal_free_desc = p_dma->dma_channel[p_transfer->channel_number].desc_left_cnt; + free_index = p_dma->dma_channel[p_transfer->channel_number].free_index; + totoal_desc = p_dma->dma_channel[p_transfer->channel_number].desc_total_no; + allign_left = totoal_desc - free_index; + + //check first.. + if(totoal_free_desc < lli_size){ + rt_kprintf("not enough desc to get...\n"); + rt_kprintf("get size is %d,left is %d\n",lli_size,totoal_free_desc); + return RT_NULL; + } + //rt_kprintf("get desc in...\n"); + + //rt_kprintf("lli size is %d\n",lli_size); + if(lli_size > allign_left){ + //if allign desc not enough...just reset null.... + if((totoal_free_desc - allign_left) < lli_size){ + rt_kprintf("not enough desc to get...\n"); + rt_kprintf("app need size is %d, totoal left is %d, allign left is %d\n",lli_size,totoal_free_desc,allign_left); + rt_kprintf("from head to get desc size is %d, actual get is %d\n",(totoal_free_desc - allign_left),(allign_left +lli_size)); + return RT_NULL; + } + else{ + actual_get_desc = allign_left +lli_size; + free_index = 0; + } + } + + + //ret_lli = &p_dma->dma_channel[p_transfer->channel_number].base_lli[free_index]; + + ret_lli = &p_dma->dma_channel[p_transfer->channel_number].base_lli[free_index]; +// rt_kprintf("get desc base index addr:%08x\n",(rt_uint32_t)&p_dma->dma_channel[p_transfer->channel_number].base_lli[0]); +// rt_kprintf("get desc free index addr:%08x\n",(rt_uint32_t)ret_lli); +// rt_kprintf("get desc request size:%08x\n",lli_size); +// rt_kprintf("get desc total size:%08x\n",p_dma->dma_channel[p_transfer->channel_number].desc_total_no); +// rt_kprintf("one desc size is:%08x\n",sizeof( struct dw_lli)); + + p_dma->dma_channel[p_transfer->channel_number].free_index += actual_get_desc; + + //rt_kprintf("get desc free index addr:%08x\n",(rt_uint32_t)&p_dma->dma_channel[p_transfer->channel_number].base_lli[p_dma->dma_channel[p_transfer->channel_number].free_index]); + + p_dma->dma_channel[p_transfer->channel_number].free_index %= p_dma->dma_channel[p_transfer->channel_number].desc_total_no; + p_dma->dma_channel[p_transfer->channel_number].desc_left_cnt -= actual_get_desc; + p_transfer->lli_size = lli_size; + p_transfer->actual_lli_size = actual_get_desc; + return ret_lli; } rt_uint32_t put_desc(struct fh81_dma *p_dma,struct dma_transfer *p_transfer){ - struct dw_lli * ret_lli; - rt_uint32_t used_index; - rt_uint32_t lli_size; - //rt_kprintf("put desc in...\n"); - used_index = p_dma->dma_channel[p_transfer->channel_number].used_index; - lli_size = p_transfer->actual_lli_size; - p_dma->dma_channel[p_transfer->channel_number].used_index += lli_size; - p_dma->dma_channel[p_transfer->channel_number].used_index %= p_dma->dma_channel[p_transfer->channel_number].desc_total_no; - p_dma->dma_channel[p_transfer->channel_number].desc_left_cnt += lli_size; - p_transfer->lli_size = 0; - p_transfer->actual_lli_size = 0; - return 0; + struct dw_lli * ret_lli; + rt_uint32_t used_index; + rt_uint32_t lli_size; + //rt_kprintf("put desc in...\n"); + used_index = p_dma->dma_channel[p_transfer->channel_number].used_index; + lli_size = p_transfer->actual_lli_size; + p_dma->dma_channel[p_transfer->channel_number].used_index += lli_size; + p_dma->dma_channel[p_transfer->channel_number].used_index %= p_dma->dma_channel[p_transfer->channel_number].desc_total_no; + p_dma->dma_channel[p_transfer->channel_number].desc_left_cnt += lli_size; + p_transfer->lli_size = 0; + p_transfer->actual_lli_size = 0; + return 0; } /***************************************************************************** @@ -499,17 +499,17 @@ rt_uint32_t put_desc(struct fh81_dma *p_dma,struct dma_transfer *p_transfer){ static rt_err_t init (struct rt_dma_device *dma){ - //init the clk table + //init the clk table - struct fh81_dma *my_own = (struct fh81_dma *)dma->parent.user_data; + struct fh81_dma *my_own = (struct fh81_dma *)dma->parent.user_data; - FH_DMA_DEBUG("my_own value:0x%x\n",(rt_uint32_t)my_own); + FH_DMA_DEBUG("my_own value:0x%x\n",(rt_uint32_t)my_own); - //check the user data - RT_ASSERT(my_own != RT_NULL); + //check the user data + RT_ASSERT(my_own != RT_NULL); - return RT_EOK; + return RT_EOK; } @@ -528,12 +528,12 @@ static rt_err_t init (struct rt_dma_device *dma){ static void handle_dma_open(struct fh81_dma *p_dma){ - rt_uint32_t i; - struct dw_dma *temp_dwc; - temp_dwc = &p_dma->dwc; + rt_uint32_t i; + struct dw_dma *temp_dwc; + temp_dwc = &p_dma->dwc; - dw_writel(temp_dwc, CFG, 1); - p_dma->dwc.controller_status = CONTROLLER_STATUS_OPEN; + dw_writel(temp_dwc, CFG, 1); + p_dma->dwc.controller_status = CONTROLLER_STATUS_OPEN; } @@ -549,27 +549,27 @@ static void handle_dma_open(struct fh81_dma *p_dma){ static void handle_dma_close(struct fh81_dma *p_dma){ - rt_uint32_t i; - struct dw_dma *temp_dwc; - temp_dwc = &p_dma->dwc; + rt_uint32_t i; + struct dw_dma *temp_dwc; + temp_dwc = &p_dma->dwc; - //take lock - for(i=0;idwc.channel_max_number;i++){ - rt_sem_take(&p_dma->dma_channel[i].channel_lock, RT_WAITING_FOREVER); + //take lock + for(i=0;idwc.channel_max_number;i++){ + rt_sem_take(&p_dma->dma_channel[i].channel_lock, RT_WAITING_FOREVER); - channel_clear_bit(temp_dwc, CH_EN, lift_shift_bit_num(i)); - p_dma->dma_channel[i].channel_status = CHANNEL_STATUS_CLOSED; - } - dw_writel(temp_dwc, CFG, 0); - p_dma->dwc.controller_status = CONTROLLER_STATUS_CLOSED; + channel_clear_bit(temp_dwc, CH_EN, lift_shift_bit_num(i)); + p_dma->dma_channel[i].channel_status = CHANNEL_STATUS_CLOSED; + } + dw_writel(temp_dwc, CFG, 0); + p_dma->dwc.controller_status = CONTROLLER_STATUS_CLOSED; - //release lock - for(i=0;idwc.channel_max_number;i++){ - rt_sem_release(&p_dma->dma_channel[i].channel_lock); - } + //release lock + for(i=0;idwc.channel_max_number;i++){ + rt_sem_release(&p_dma->dma_channel[i].channel_lock); + } - //destroy the workqueue.. - //rt_workqueue_destroy(p_dma->isr_workqueue); + //destroy the workqueue.. + //rt_workqueue_destroy(p_dma->isr_workqueue); } @@ -584,26 +584,26 @@ static void handle_dma_close(struct fh81_dma *p_dma){ * what does this function returned? *****************************************************************************/ -#define CHANNEL_REAL_FREE (0) -#define CHANNEL_NOT_FREE (1) +#define CHANNEL_REAL_FREE (0) +#define CHANNEL_NOT_FREE (1) static rt_uint32_t check_channel_real_free(struct fh81_dma *p_dma,rt_uint32_t channel_number){ - struct dw_dma *temp_dwc; - temp_dwc = &p_dma->dwc; - rt_uint32_t ret_status; + struct dw_dma *temp_dwc; + temp_dwc = &p_dma->dwc; + rt_uint32_t ret_status; - RT_ASSERT(channel_number < p_dma->dwc.channel_max_number); + RT_ASSERT(channel_number < p_dma->dwc.channel_max_number); - ret_status = dw_readl(temp_dwc, CH_EN); - if(ret_status & lift_shift_bit_num(channel_number)){ - //the channel is still busy!!!error here - //FH_DMA_DEBUG("auto request channel error\n"); - return CHANNEL_NOT_FREE; - } - return CHANNEL_REAL_FREE; + ret_status = dw_readl(temp_dwc, CH_EN); + if(ret_status & lift_shift_bit_num(channel_number)){ + //the channel is still busy!!!error here + //FH_DMA_DEBUG("auto request channel error\n"); + return CHANNEL_NOT_FREE; + } + return CHANNEL_REAL_FREE; } @@ -620,110 +620,110 @@ static rt_uint32_t check_channel_real_free(struct fh81_dma *p_dma,rt_uint32_t c static rt_err_t handle_request_channel(struct fh81_dma *p_dma,struct dma_transfer *p_transfer){ - rt_uint32_t i; - struct dw_dma *temp_dwc; - temp_dwc = &p_dma->dwc; - rt_err_t ret_status = RT_EOK; + rt_uint32_t i; + struct dw_dma *temp_dwc; + temp_dwc = &p_dma->dwc; + rt_err_t ret_status = RT_EOK; - //handle if auto check channel... - if(p_transfer->channel_number == AUTO_FIND_CHANNEL){ - //check each channel lock,find a free channel... - for(i=0;idwc.channel_max_number;i++){ - ret_status = rt_sem_trytake(&p_dma->dma_channel[i].channel_lock); - if(ret_status == RT_EOK){ - break; - } - } + //handle if auto check channel... + if(p_transfer->channel_number == AUTO_FIND_CHANNEL){ + //check each channel lock,find a free channel... + for(i=0;idwc.channel_max_number;i++){ + ret_status = rt_sem_trytake(&p_dma->dma_channel[i].channel_lock); + if(ret_status == RT_EOK){ + break; + } + } - if(i < p_dma->dwc.channel_max_number){ - ret_status = check_channel_real_free(p_dma,i); - if(ret_status!= CHANNEL_REAL_FREE){ - FH_DMA_DEBUG("auto request channel error\n"); - RT_ASSERT(ret_status == CHANNEL_REAL_FREE); - } - //caution : channel is already locked here.... - p_transfer->channel_number = i; - //bind to the controller. - //p_transfer->dma_controller = p_dma; - p_dma->dma_channel[i].channel_status = CHANNEL_STATUS_OPEN; - } - else - return -RT_ENOMEM; + if(i < p_dma->dwc.channel_max_number){ + ret_status = check_channel_real_free(p_dma,i); + if(ret_status!= CHANNEL_REAL_FREE){ + FH_DMA_DEBUG("auto request channel error\n"); + RT_ASSERT(ret_status == CHANNEL_REAL_FREE); + } + //caution : channel is already locked here.... + p_transfer->channel_number = i; + //bind to the controller. + //p_transfer->dma_controller = p_dma; + p_dma->dma_channel[i].channel_status = CHANNEL_STATUS_OPEN; + } + else + return -RT_ENOMEM; - } + } - // request channel by user - else{ - // + // request channel by user + else{ + // - RT_ASSERT(p_transfer->channel_number < p_dma->dwc.channel_max_number); - ret_status = rt_sem_take(&p_dma->dma_channel[p_transfer->channel_number].channel_lock, RT_TICK_PER_SECOND*50); - if(ret_status != RT_EOK) - return -RT_ENOMEM; - //rt_enter_critical(); - ret_status = check_channel_real_free(p_dma,p_transfer->channel_number); - if(ret_status!= CHANNEL_REAL_FREE){ - FH_DMA_DEBUG("user request channel error\n"); - RT_ASSERT(ret_status == CHANNEL_REAL_FREE); - } + RT_ASSERT(p_transfer->channel_number < p_dma->dwc.channel_max_number); + ret_status = rt_sem_take(&p_dma->dma_channel[p_transfer->channel_number].channel_lock, RT_TICK_PER_SECOND*50); + if(ret_status != RT_EOK) + return -RT_ENOMEM; + //rt_enter_critical(); + ret_status = check_channel_real_free(p_dma,p_transfer->channel_number); + if(ret_status!= CHANNEL_REAL_FREE){ + FH_DMA_DEBUG("user request channel error\n"); + RT_ASSERT(ret_status == CHANNEL_REAL_FREE); + } - //bind to the controller - //p_transfer->dma_controller = p_dma; - p_dma->dma_channel[p_transfer->channel_number].channel_status = CHANNEL_STATUS_OPEN; - //rt_exit_critical(); - } + //bind to the controller + //p_transfer->dma_controller = p_dma; + p_dma->dma_channel[p_transfer->channel_number].channel_status = CHANNEL_STATUS_OPEN; + //rt_exit_critical(); + } - //malloc desc for this one channel... - //fix me.... + //malloc desc for this one channel... + //fix me.... - p_dma->dma_channel[p_transfer->channel_number].allign_malloc = (rt_uint32_t) rt_malloc( - (p_dma->dma_channel[p_transfer->channel_number].desc_total_no - * sizeof(struct dw_lli)) + CACHE_LINE_SIZE); + p_dma->dma_channel[p_transfer->channel_number].allign_malloc = (rt_uint32_t) rt_malloc( + (p_dma->dma_channel[p_transfer->channel_number].desc_total_no + * sizeof(struct dw_lli)) + CACHE_LINE_SIZE); - if(!p_dma->dma_channel[p_transfer->channel_number].allign_malloc){ - //release channel - rt_kprintf("[dma]: no mem to malloc channel%d desc..\n",p_transfer->channel_number); - p_dma->dma_channel[p_transfer->channel_number].channel_status = CHANNEL_STATUS_CLOSED; - rt_sem_release(&p_dma->dma_channel[p_transfer->channel_number].channel_lock); - return -RT_ENOMEM; - } + if(!p_dma->dma_channel[p_transfer->channel_number].allign_malloc){ + //release channel + rt_kprintf("[dma]: no mem to malloc channel%d desc..\n",p_transfer->channel_number); + p_dma->dma_channel[p_transfer->channel_number].channel_status = CHANNEL_STATUS_CLOSED; + rt_sem_release(&p_dma->dma_channel[p_transfer->channel_number].channel_lock); + return -RT_ENOMEM; + } - p_dma->dma_channel[p_transfer->channel_number].base_lli = - (struct dw_lli *) allign_func( - p_dma->dma_channel[p_transfer->channel_number].allign_malloc, - CACHE_LINE_SIZE); + p_dma->dma_channel[p_transfer->channel_number].base_lli = + (struct dw_lli *) allign_func( + p_dma->dma_channel[p_transfer->channel_number].allign_malloc, + CACHE_LINE_SIZE); - FH_DMA_DEBUG("dma desc addr is %x\n",(rt_uint32_t)p_dma->dma_channel[p_transfer->channel_number].base_lli); - //t1 = (UINT32)rt_malloc(GMAC_TX_RING_SIZE * sizeof(Gmac_Tx_DMA_Descriptors) + CACHE_LINE_SIZE); + FH_DMA_DEBUG("dma desc addr is %x\n",(rt_uint32_t)p_dma->dma_channel[p_transfer->channel_number].base_lli); + //t1 = (UINT32)rt_malloc(GMAC_TX_RING_SIZE * sizeof(Gmac_Tx_DMA_Descriptors) + CACHE_LINE_SIZE); - if(!p_dma->dma_channel[p_transfer->channel_number].base_lli){ - FH_DMA_DEBUG("request desc failed..\n"); - RT_ASSERT(p_dma->dma_channel[p_transfer->channel_number].base_lli != RT_NULL); - } + if(!p_dma->dma_channel[p_transfer->channel_number].base_lli){ + FH_DMA_DEBUG("request desc failed..\n"); + RT_ASSERT(p_dma->dma_channel[p_transfer->channel_number].base_lli != RT_NULL); + } - if((rt_uint32_t)p_dma->dma_channel[p_transfer->channel_number].base_lli % 32){ - rt_kprintf("malloc is not cache allign.."); + if((rt_uint32_t)p_dma->dma_channel[p_transfer->channel_number].base_lli % 32){ + rt_kprintf("malloc is not cache allign.."); - } + } - //rt_memset((void *)dma_trans_desc->first_lli, 0, lli_size * sizeof(struct dw_lli)); - rt_memset((void *) p_dma->dma_channel[p_transfer->channel_number].base_lli, - 0, - p_dma->dma_channel[p_transfer->channel_number].desc_total_no - * sizeof(struct dw_lli)); - - p_dma->dma_channel[p_transfer->channel_number].desc_left_cnt = p_dma->dma_channel[p_transfer->channel_number].desc_total_no; - p_dma->dma_channel[p_transfer->channel_number].free_index = 0; - p_dma->dma_channel[p_transfer->channel_number].used_index = 0; + //rt_memset((void *)dma_trans_desc->first_lli, 0, lli_size * sizeof(struct dw_lli)); + rt_memset((void *) p_dma->dma_channel[p_transfer->channel_number].base_lli, + 0, + p_dma->dma_channel[p_transfer->channel_number].desc_total_no + * sizeof(struct dw_lli)); + + p_dma->dma_channel[p_transfer->channel_number].desc_left_cnt = p_dma->dma_channel[p_transfer->channel_number].desc_total_no; + p_dma->dma_channel[p_transfer->channel_number].free_index = 0; + p_dma->dma_channel[p_transfer->channel_number].used_index = 0; - return RT_EOK; + return RT_EOK; } @@ -747,40 +747,40 @@ static rt_err_t handle_request_channel(struct fh81_dma *p_dma,struct dma_transf static rt_uint32_t handle_release_channel(struct fh81_dma *p_dma,struct dma_transfer *p_transfer){ - rt_uint32_t i; - struct dw_dma *temp_dwc; - temp_dwc = &p_dma->dwc; - rt_uint32_t ret_status; + rt_uint32_t i; + struct dw_dma *temp_dwc; + temp_dwc = &p_dma->dwc; + rt_uint32_t ret_status; - //rt_enter_critical(); - ret_status = p_dma->dma_channel[p_transfer->channel_number].channel_status; + //rt_enter_critical(); + ret_status = p_dma->dma_channel[p_transfer->channel_number].channel_status; - RT_ASSERT(p_transfer->channel_number < p_dma->dwc.channel_max_number); + RT_ASSERT(p_transfer->channel_number < p_dma->dwc.channel_max_number); - if(ret_status == CHANNEL_STATUS_CLOSED){ - FH_DMA_DEBUG("release channel error,reason: release a closed channel!!\n"); - RT_ASSERT(ret_status != CHANNEL_STATUS_CLOSED); - } + if(ret_status == CHANNEL_STATUS_CLOSED){ + FH_DMA_DEBUG("release channel error,reason: release a closed channel!!\n"); + RT_ASSERT(ret_status != CHANNEL_STATUS_CLOSED); + } - channel_clear_bit(temp_dwc, CH_EN, lift_shift_bit_num(p_transfer->channel_number)); - rt_sem_release(&p_dma->dma_channel[p_transfer->channel_number].channel_lock); - //p_transfer->dma_controller = RT_NULL; - p_dma->dma_channel[p_transfer->channel_number].channel_status = CHANNEL_STATUS_CLOSED; - p_dma->dma_channel[p_transfer->channel_number].open_flag = DEFAULT_TRANSFER; - //rt_exit_critical(); + channel_clear_bit(temp_dwc, CH_EN, lift_shift_bit_num(p_transfer->channel_number)); + rt_sem_release(&p_dma->dma_channel[p_transfer->channel_number].channel_lock); + //p_transfer->dma_controller = RT_NULL; + p_dma->dma_channel[p_transfer->channel_number].channel_status = CHANNEL_STATUS_CLOSED; + p_dma->dma_channel[p_transfer->channel_number].open_flag = DEFAULT_TRANSFER; + //rt_exit_critical(); - //release this channel malloc mem... - //fix me..... - rt_free((void *)p_dma->dma_channel[p_transfer->channel_number].allign_malloc); - p_dma->dma_channel[p_transfer->channel_number].allign_malloc = RT_NULL; - p_dma->dma_channel[p_transfer->channel_number].base_lli = RT_NULL; - p_dma->dma_channel[p_transfer->channel_number].desc_left_cnt = p_dma->dma_channel[p_transfer->channel_number].desc_total_no; - p_dma->dma_channel[p_transfer->channel_number].free_index = 0; - p_dma->dma_channel[p_transfer->channel_number].used_index = 0; + //release this channel malloc mem... + //fix me..... + rt_free((void *)p_dma->dma_channel[p_transfer->channel_number].allign_malloc); + p_dma->dma_channel[p_transfer->channel_number].allign_malloc = RT_NULL; + p_dma->dma_channel[p_transfer->channel_number].base_lli = RT_NULL; + p_dma->dma_channel[p_transfer->channel_number].desc_left_cnt = p_dma->dma_channel[p_transfer->channel_number].desc_total_no; + p_dma->dma_channel[p_transfer->channel_number].free_index = 0; + p_dma->dma_channel[p_transfer->channel_number].used_index = 0; - return RT_EOK; + return RT_EOK; } @@ -788,26 +788,26 @@ static rt_uint32_t handle_release_channel(struct fh81_dma *p_dma,struct dma_tra static rt_uint32_t cal_lli_size(struct dma_transfer *p_transfer){ - RT_ASSERT(p_transfer != RT_NULL); - RT_ASSERT(p_transfer->dma_controller != RT_NULL); - RT_ASSERT(p_transfer->src_width <= DW_DMA_SLAVE_WIDTH_32BIT); - rt_uint32_t lli_number = 0; - rt_uint32_t channel_max_trans_per_lli = 0; - channel_max_trans_per_lli = p_transfer->dma_controller->dma_channel[p_transfer->channel_number].desc_trans_size; + RT_ASSERT(p_transfer != RT_NULL); + RT_ASSERT(p_transfer->dma_controller != RT_NULL); + RT_ASSERT(p_transfer->src_width <= DW_DMA_SLAVE_WIDTH_32BIT); + rt_uint32_t lli_number = 0; + rt_uint32_t channel_max_trans_per_lli = 0; + channel_max_trans_per_lli = p_transfer->dma_controller->dma_channel[p_transfer->channel_number].desc_trans_size; - lli_number = (p_transfer->trans_len % channel_max_trans_per_lli) ? 1:0; - lli_number += p_transfer->trans_len / channel_max_trans_per_lli; + lli_number = (p_transfer->trans_len % channel_max_trans_per_lli) ? 1:0; + lli_number += p_transfer->trans_len / channel_max_trans_per_lli; - return lli_number; + return lli_number; } static void dump_lli(struct dw_lli *p_lli){ - FH_DMA_DEBUG("link_mem padd:0x%x\n sar:0x%x\n dar:0x%x\n llp:0x%x\n ctllo:0x%x\n ctlhi:0x%x\n sstat:0x%x\n dstat:0x%x\n", - (rt_uint32_t)p_lli,p_lli->sar, p_lli->dar, p_lli->llp, - p_lli->ctllo, p_lli->ctlhi,p_lli->sstat,p_lli->dstat); + FH_DMA_DEBUG("link_mem padd:0x%x\n sar:0x%x\n dar:0x%x\n llp:0x%x\n ctllo:0x%x\n ctlhi:0x%x\n sstat:0x%x\n dstat:0x%x\n", + (rt_uint32_t)p_lli,p_lli->sar, p_lli->dar, p_lli->llp, + p_lli->ctllo, p_lli->ctlhi,p_lli->sstat,p_lli->dstat); } /***************************************************************************** * Description: @@ -820,296 +820,296 @@ static void dump_lli(struct dw_lli *p_lli){ static void handle_single_transfer(struct fh81_dma *p_dma,struct dma_transfer *p_transfer){ - rt_uint32_t i; - struct dw_dma *temp_dwc; - temp_dwc = &p_dma->dwc; - volatile rt_uint32_t ret_status; - rt_list_t *p_controller_list; - rt_uint32_t lli_size,max_trans_size; - struct dw_lli *p_lli = RT_NULL; - struct dma_transfer *dma_trans_desc; - struct dma_transfer *_dma_trans_desc; + rt_uint32_t i; + struct dw_dma *temp_dwc; + temp_dwc = &p_dma->dwc; + volatile rt_uint32_t ret_status; + rt_list_t *p_controller_list; + rt_uint32_t lli_size,max_trans_size; + struct dw_lli *p_lli = RT_NULL; + struct dma_transfer *dma_trans_desc; + struct dma_transfer *_dma_trans_desc; - rt_uint32_t temp_src_add; - rt_uint32_t temp_dst_add; - rt_uint32_t trans_total_len = 0; - rt_uint32_t temp_trans_size = 0; - //rt_uint32_t dma_channl_no = 0; + rt_uint32_t temp_src_add; + rt_uint32_t temp_dst_add; + rt_uint32_t trans_total_len = 0; + rt_uint32_t temp_trans_size = 0; + //rt_uint32_t dma_channl_no = 0; - RT_ASSERT(p_transfer->channel_number < p_dma->dwc.channel_max_number); - RT_ASSERT(p_transfer->dma_number < DMA_CONTROLLER_NUMBER); - RT_ASSERT(&fh81_dma_controller[p_transfer->dma_number] == p_dma); - //when the dma transfer....the lock should be 0!!!! - //or user may not request the channel... - RT_ASSERT(p_dma->dma_channel[p_transfer->channel_number].channel_lock.value == 0); + RT_ASSERT(p_transfer->channel_number < p_dma->dwc.channel_max_number); + RT_ASSERT(p_transfer->dma_number < DMA_CONTROLLER_NUMBER); + RT_ASSERT(&fh81_dma_controller[p_transfer->dma_number] == p_dma); + //when the dma transfer....the lock should be 0!!!! + //or user may not request the channel... + RT_ASSERT(p_dma->dma_channel[p_transfer->channel_number].channel_lock.value == 0); - ret_status = p_dma->dma_channel[p_transfer->channel_number].channel_status; - if(ret_status == CHANNEL_STATUS_CLOSED){ - FH_DMA_DEBUG("transfer error,reason: use a closed channel..\n"); - RT_ASSERT(ret_status != CHANNEL_STATUS_CLOSED); - } - p_transfer->dma_controller = p_dma; + ret_status = p_dma->dma_channel[p_transfer->channel_number].channel_status; + if(ret_status == CHANNEL_STATUS_CLOSED){ + FH_DMA_DEBUG("transfer error,reason: use a closed channel..\n"); + RT_ASSERT(ret_status != CHANNEL_STATUS_CLOSED); + } + p_transfer->dma_controller = p_dma; - rt_list_init(&p_transfer->transfer_list); - max_trans_size = p_transfer->dma_controller->dma_channel[p_transfer->channel_number].desc_trans_size; - //add transfer to the controller's queue list - //here should insert before and handle after....this could be a fifo... - rt_list_insert_before(&p_dma->dma_channel[p_transfer->channel_number].queue , &p_transfer->transfer_list); + rt_list_init(&p_transfer->transfer_list); + max_trans_size = p_transfer->dma_controller->dma_channel[p_transfer->channel_number].desc_trans_size; + //add transfer to the controller's queue list + //here should insert before and handle after....this could be a fifo... + rt_list_insert_before(&p_dma->dma_channel[p_transfer->channel_number].queue , &p_transfer->transfer_list); - p_controller_list = &p_dma->dma_channel[p_transfer->channel_number].queue; + p_controller_list = &p_dma->dma_channel[p_transfer->channel_number].queue; - //here the driver could make a queue to cache the transfer and kick a thread to handle the queue~~~ - //but now,this is a easy version...,just handle the transfer now!!! - list_for_each_entry_safe(dma_trans_desc, _dma_trans_desc, p_controller_list, transfer_list) { + //here the driver could make a queue to cache the transfer and kick a thread to handle the queue~~~ + //but now,this is a easy version...,just handle the transfer now!!! + list_for_each_entry_safe(dma_trans_desc, _dma_trans_desc, p_controller_list, transfer_list) { - //the dma controller could see the active transfer ..... - p_transfer->dma_controller->dma_channel[p_transfer->channel_number].active_trans = dma_trans_desc; + //the dma controller could see the active transfer ..... + p_transfer->dma_controller->dma_channel[p_transfer->channel_number].active_trans = dma_trans_desc; - trans_total_len = p_transfer->trans_len; + trans_total_len = p_transfer->trans_len; - //handle desc - //step1:cal lli size... - lli_size = cal_lli_size(dma_trans_desc); - //step2:malloc lli_size mem - //dma_trans_desc->first_lli = (struct dw_lli *)rt_malloc(lli_size * sizeof(struct dw_lli)); + //handle desc + //step1:cal lli size... + lli_size = cal_lli_size(dma_trans_desc); + //step2:malloc lli_size mem + //dma_trans_desc->first_lli = (struct dw_lli *)rt_malloc(lli_size * sizeof(struct dw_lli)); - dma_trans_desc->first_lli = get_desc(p_dma,p_transfer,lli_size); + dma_trans_desc->first_lli = get_desc(p_dma,p_transfer,lli_size); - //not enough mem.. - if(dma_trans_desc->first_lli == RT_NULL){ + //not enough mem.. + if(dma_trans_desc->first_lli == RT_NULL){ - FH_DMA_DEBUG("transfer error,reason: not enough mem..\n"); - RT_ASSERT(dma_trans_desc->first_lli != RT_NULL); - } + FH_DMA_DEBUG("transfer error,reason: not enough mem..\n"); + RT_ASSERT(dma_trans_desc->first_lli != RT_NULL); + } - //bug here.... - rt_memset((void *)dma_trans_desc->first_lli, 0, lli_size * sizeof(struct dw_lli)); + //bug here.... + rt_memset((void *)dma_trans_desc->first_lli, 0, lli_size * sizeof(struct dw_lli)); - p_lli = dma_trans_desc->first_lli; + p_lli = dma_trans_desc->first_lli; - //warnning!!!!must check if the add is 32bits ally... - RT_ASSERT(((rt_uint32_t)p_lli & 0x03) == 0); + //warnning!!!!must check if the add is 32bits ally... + RT_ASSERT(((rt_uint32_t)p_lli & 0x03) == 0); - RT_ASSERT(dma_trans_desc->dst_inc_mode <=DW_DMA_SLAVE_FIX); - RT_ASSERT(dma_trans_desc->src_inc_mode <=DW_DMA_SLAVE_FIX); - //step3: set the mem.. - for(i=0;idst_inc_mode <=DW_DMA_SLAVE_FIX); + RT_ASSERT(dma_trans_desc->src_inc_mode <=DW_DMA_SLAVE_FIX); + //step3: set the mem.. + for(i=0;idst_inc_mode){ - case DW_DMA_SLAVE_INC: - temp_dst_add = dma_trans_desc->dst_add + i * max_trans_size * (1<dst_width); - break; - case DW_DMA_SLAVE_DEC: - temp_dst_add = dma_trans_desc->dst_add - i * max_trans_size * (1<dst_width); - break; - case DW_DMA_SLAVE_FIX: - temp_dst_add = dma_trans_desc->dst_add; - break; + switch(dma_trans_desc->dst_inc_mode){ + case DW_DMA_SLAVE_INC: + temp_dst_add = dma_trans_desc->dst_add + i * max_trans_size * (1<dst_width); + break; + case DW_DMA_SLAVE_DEC: + temp_dst_add = dma_trans_desc->dst_add - i * max_trans_size * (1<dst_width); + break; + case DW_DMA_SLAVE_FIX: + temp_dst_add = dma_trans_desc->dst_add; + break; - } + } - switch(dma_trans_desc->src_inc_mode){ - case DW_DMA_SLAVE_INC: - temp_src_add = dma_trans_desc->src_add + i * max_trans_size * (1<src_width); - break; - case DW_DMA_SLAVE_DEC: - temp_src_add = dma_trans_desc->src_add - i * max_trans_size * (1<src_width); - break; - case DW_DMA_SLAVE_FIX: - temp_src_add = dma_trans_desc->src_add ; - break; + switch(dma_trans_desc->src_inc_mode){ + case DW_DMA_SLAVE_INC: + temp_src_add = dma_trans_desc->src_add + i * max_trans_size * (1<src_width); + break; + case DW_DMA_SLAVE_DEC: + temp_src_add = dma_trans_desc->src_add - i * max_trans_size * (1<src_width); + break; + case DW_DMA_SLAVE_FIX: + temp_src_add = dma_trans_desc->src_add ; + break; - } + } - p_lli[i].sar = temp_src_add; - p_lli[i].dar = temp_dst_add; + p_lli[i].sar = temp_src_add; + p_lli[i].dar = temp_dst_add; - //para ctl - temp_trans_size = (trans_total_len / max_trans_size)? max_trans_size : (trans_total_len % max_trans_size); - trans_total_len -= temp_trans_size; + //para ctl + temp_trans_size = (trans_total_len / max_trans_size)? max_trans_size : (trans_total_len % max_trans_size); + trans_total_len -= temp_trans_size; - RT_ASSERT(dma_trans_desc->dst_width <=DW_DMA_SLAVE_WIDTH_32BIT); - RT_ASSERT(dma_trans_desc->src_width <=DW_DMA_SLAVE_WIDTH_32BIT); + RT_ASSERT(dma_trans_desc->dst_width <=DW_DMA_SLAVE_WIDTH_32BIT); + RT_ASSERT(dma_trans_desc->src_width <=DW_DMA_SLAVE_WIDTH_32BIT); - RT_ASSERT(dma_trans_desc->dst_msize <=DW_DMA_SLAVE_MSIZE_256); - RT_ASSERT(dma_trans_desc->src_msize <=DW_DMA_SLAVE_MSIZE_256); - RT_ASSERT(dma_trans_desc->fc_mode <=DMA_P2P); + RT_ASSERT(dma_trans_desc->dst_msize <=DW_DMA_SLAVE_MSIZE_256); + RT_ASSERT(dma_trans_desc->src_msize <=DW_DMA_SLAVE_MSIZE_256); + RT_ASSERT(dma_trans_desc->fc_mode <=DMA_P2P); - p_lli[i].ctllo = DWC_CTLL_INT_EN|DWC_CTLL_DST_WIDTH(dma_trans_desc->dst_width)|DWC_CTLL_SRC_WIDTH(dma_trans_desc->src_width) - |DWC_CTLL_DST_INC_MODE(dma_trans_desc->dst_inc_mode)|DWC_CTLL_SRC_INC_MODE(dma_trans_desc->src_inc_mode) - |DWC_CTLL_DST_MSIZE(dma_trans_desc->dst_msize)|DWC_CTLL_SRC_MSIZE(dma_trans_desc->src_msize)|DWC_CTLL_FC(dma_trans_desc->fc_mode) - |DWC_CTLL_DMS(0)|DWC_CTLL_SMS(0); - //block size - p_lli[i].ctlhi = temp_trans_size; + p_lli[i].ctllo = DWC_CTLL_INT_EN|DWC_CTLL_DST_WIDTH(dma_trans_desc->dst_width)|DWC_CTLL_SRC_WIDTH(dma_trans_desc->src_width) + |DWC_CTLL_DST_INC_MODE(dma_trans_desc->dst_inc_mode)|DWC_CTLL_SRC_INC_MODE(dma_trans_desc->src_inc_mode) + |DWC_CTLL_DST_MSIZE(dma_trans_desc->dst_msize)|DWC_CTLL_SRC_MSIZE(dma_trans_desc->src_msize)|DWC_CTLL_FC(dma_trans_desc->fc_mode) + |DWC_CTLL_DMS(0)|DWC_CTLL_SMS(0); + //block size + p_lli[i].ctlhi = temp_trans_size; - if(trans_total_len > 0){ - p_lli[i].llp = (rt_uint32_t)&p_lli[i+1]; - p_lli[i].ctllo |= DWC_CTLL_LLP_D_EN|DWC_CTLL_LLP_S_EN; - } + if(trans_total_len > 0){ + p_lli[i].llp = (rt_uint32_t)&p_lli[i+1]; + p_lli[i].ctllo |= DWC_CTLL_LLP_D_EN|DWC_CTLL_LLP_S_EN; + } - //flush cache to mem - mmu_clean_invalidated_dcache((rt_uint32_t)&p_lli[i],sizeof(struct dw_lli)); + //flush cache to mem + mmu_clean_invalidated_dcache((rt_uint32_t)&p_lli[i],sizeof(struct dw_lli)); - dump_lli(&p_lli[i]); - } + dump_lli(&p_lli[i]); + } - //clear the isr status + //clear the isr status - //set the dma config reg - //clear cfg reload reg - //ret_status = dw_readl(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_LO); - //ret_status &= ~(DWC_CFGL_RELOAD_SAR|DWC_CFGL_RELOAD_DAR); - dw_writel(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_LO,0); + //set the dma config reg + //clear cfg reload reg + //ret_status = dw_readl(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_LO); + //ret_status &= ~(DWC_CFGL_RELOAD_SAR|DWC_CFGL_RELOAD_DAR); + dw_writel(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_LO,0); - //set the first link add - //ret_status = dw_readl(temp_dwc,CHAN[dma_trans_desc->channel_number].LLP); - ret_status = 0; - ret_status = (rt_uint32_t)&p_lli[0]; - dw_writel(temp_dwc,CHAN[dma_trans_desc->channel_number].LLP,ret_status); + //set the first link add + //ret_status = dw_readl(temp_dwc,CHAN[dma_trans_desc->channel_number].LLP); + ret_status = 0; + ret_status = (rt_uint32_t)&p_lli[0]; + dw_writel(temp_dwc,CHAN[dma_trans_desc->channel_number].LLP,ret_status); - //set link enable - //ret_status = dw_readl(temp_dwc,CHAN[dma_trans_desc->channel_number].CTL_LO); - ret_status = 0; - ret_status =DWC_CTLL_LLP_D_EN|DWC_CTLL_LLP_S_EN; - dw_writel(temp_dwc,CHAN[dma_trans_desc->channel_number].CTL_LO,ret_status); + //set link enable + //ret_status = dw_readl(temp_dwc,CHAN[dma_trans_desc->channel_number].CTL_LO); + ret_status = 0; + ret_status =DWC_CTLL_LLP_D_EN|DWC_CTLL_LLP_S_EN; + dw_writel(temp_dwc,CHAN[dma_trans_desc->channel_number].CTL_LO,ret_status); - dw_writel(temp_dwc,CHAN[dma_trans_desc->channel_number].CTL_HI,0); - //set handshaking + dw_writel(temp_dwc,CHAN[dma_trans_desc->channel_number].CTL_HI,0); + //set handshaking - RT_ASSERT(dma_trans_desc->dst_hs <= DMA_SW_HANDSHAKING); - RT_ASSERT(dma_trans_desc->src_hs <= DMA_SW_HANDSHAKING); + RT_ASSERT(dma_trans_desc->dst_hs <= DMA_SW_HANDSHAKING); + RT_ASSERT(dma_trans_desc->src_hs <= DMA_SW_HANDSHAKING); - if(dma_trans_desc->dst_hs == DMA_SW_HANDSHAKING){ - ret_status = dw_readl(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_LO); - ret_status |= DWC_CFGL_HS_DST; - dw_writel(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_LO,ret_status); - } - else{ - ret_status = dw_readl(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_LO); - ret_status &= ~DWC_CFGL_HS_DST; - dw_writel(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_LO,ret_status); - } + if(dma_trans_desc->dst_hs == DMA_SW_HANDSHAKING){ + ret_status = dw_readl(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_LO); + ret_status |= DWC_CFGL_HS_DST; + dw_writel(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_LO,ret_status); + } + else{ + ret_status = dw_readl(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_LO); + ret_status &= ~DWC_CFGL_HS_DST; + dw_writel(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_LO,ret_status); + } - if(dma_trans_desc->src_hs == DMA_SW_HANDSHAKING){ - ret_status = dw_readl(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_LO); - ret_status |= DWC_CFGL_HS_SRC; - dw_writel(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_LO,ret_status); - } - else{ - ret_status = dw_readl(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_LO); - ret_status &= ~DWC_CFGL_HS_SRC; - dw_writel(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_LO,ret_status); - } + if(dma_trans_desc->src_hs == DMA_SW_HANDSHAKING){ + ret_status = dw_readl(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_LO); + ret_status |= DWC_CFGL_HS_SRC; + dw_writel(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_LO,ret_status); + } + else{ + ret_status = dw_readl(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_LO); + ret_status &= ~DWC_CFGL_HS_SRC; + dw_writel(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_LO,ret_status); + } - //only hw handshaking need this.. - switch(dma_trans_desc->fc_mode){ - case DMA_M2M: - break; - case DMA_M2P: - //set dst per... - RT_ASSERT(dma_trans_desc->dst_per < DMA_HW_HS_END); + //only hw handshaking need this.. + switch(dma_trans_desc->fc_mode){ + case DMA_M2M: + break; + case DMA_M2P: + //set dst per... + RT_ASSERT(dma_trans_desc->dst_per < DMA_HW_HS_END); - ret_status = dw_readl(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_HI); + ret_status = dw_readl(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_HI); - //clear 43 ~ 46 bit - ret_status &= ~0x7800; + //clear 43 ~ 46 bit + ret_status &= ~0x7800; - ret_status |= DWC_CFGH_DST_PER(dma_trans_desc->dst_per); - dw_writel(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_HI,ret_status); - //DWC_CFGH_SRC_PER + ret_status |= DWC_CFGH_DST_PER(dma_trans_desc->dst_per); + dw_writel(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_HI,ret_status); + //DWC_CFGH_SRC_PER - break; - case DMA_P2M: - //set src per... - RT_ASSERT(dma_trans_desc->src_per < DMA_HW_HS_END); + break; + case DMA_P2M: + //set src per... + RT_ASSERT(dma_trans_desc->src_per < DMA_HW_HS_END); - ret_status = dw_readl(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_HI); + ret_status = dw_readl(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_HI); - //clear 39 ~ 42 bit - ret_status &= ~0x780; + //clear 39 ~ 42 bit + ret_status &= ~0x780; - ret_status |= DWC_CFGH_SRC_PER(dma_trans_desc->src_per); - dw_writel(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_HI,ret_status); + ret_status |= DWC_CFGH_SRC_PER(dma_trans_desc->src_per); + dw_writel(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_HI,ret_status); - break; - case DMA_P2P: - //set src and dst.. - RT_ASSERT(dma_trans_desc->dst_per < DMA_HW_HS_END); - RT_ASSERT(dma_trans_desc->src_per < DMA_HW_HS_END); + break; + case DMA_P2P: + //set src and dst.. + RT_ASSERT(dma_trans_desc->dst_per < DMA_HW_HS_END); + RT_ASSERT(dma_trans_desc->src_per < DMA_HW_HS_END); - ret_status = dw_readl(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_HI); - ret_status &= ~0x7800; - ret_status &= ~0x780; - ret_status |= DWC_CFGH_SRC_PER(dma_trans_desc->src_per) | DWC_CFGH_DST_PER(dma_trans_desc->dst_per); - dw_writel(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_HI,ret_status); + ret_status = dw_readl(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_HI); + ret_status &= ~0x7800; + ret_status &= ~0x780; + ret_status |= DWC_CFGH_SRC_PER(dma_trans_desc->src_per) | DWC_CFGH_DST_PER(dma_trans_desc->dst_per); + dw_writel(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_HI,ret_status); - break; - default: - break; - } + break; + default: + break; + } - dma_trans_desc->dma_controller->dma_channel[dma_trans_desc->channel_number].channel_status = CHANNEL_STATUS_BUSY; - //enable isr... - channel_set_bit(temp_dwc, MASK.XFER, lift_shift_bit_num(dma_trans_desc->channel_number)); - channel_set_bit(temp_dwc, MASK.ERROR, lift_shift_bit_num(dma_trans_desc->channel_number)); - //close - channel_clear_bit(temp_dwc, MASK.BLOCK, lift_shift_bit_num(dma_trans_desc->channel_number)); + dma_trans_desc->dma_controller->dma_channel[dma_trans_desc->channel_number].channel_status = CHANNEL_STATUS_BUSY; + //enable isr... + channel_set_bit(temp_dwc, MASK.XFER, lift_shift_bit_num(dma_trans_desc->channel_number)); + channel_set_bit(temp_dwc, MASK.ERROR, lift_shift_bit_num(dma_trans_desc->channel_number)); + //close + channel_clear_bit(temp_dwc, MASK.BLOCK, lift_shift_bit_num(dma_trans_desc->channel_number)); - dw_writel(temp_dwc, CLEAR.XFER, 1<<(dma_trans_desc->channel_number)); - dw_writel(temp_dwc, CLEAR.BLOCK, 1<<(dma_trans_desc->channel_number)); - dw_writel(temp_dwc, CLEAR.SRC_TRAN, 1<<(dma_trans_desc->channel_number)); - dw_writel(temp_dwc, CLEAR.DST_TRAN, 1<<(dma_trans_desc->channel_number)); - dw_writel(temp_dwc, CLEAR.ERROR, 1<<(dma_trans_desc->channel_number)); + dw_writel(temp_dwc, CLEAR.XFER, 1<<(dma_trans_desc->channel_number)); + dw_writel(temp_dwc, CLEAR.BLOCK, 1<<(dma_trans_desc->channel_number)); + dw_writel(temp_dwc, CLEAR.SRC_TRAN, 1<<(dma_trans_desc->channel_number)); + dw_writel(temp_dwc, CLEAR.DST_TRAN, 1<<(dma_trans_desc->channel_number)); + dw_writel(temp_dwc, CLEAR.ERROR, 1<<(dma_trans_desc->channel_number)); - ret_status = dw_readl(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_HI); - FH_DMA_DEBUG("cfg_hi value:0x%x\n",ret_status); + ret_status = dw_readl(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_HI); + FH_DMA_DEBUG("cfg_hi value:0x%x\n",ret_status); - ret_status = dw_readl(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_LO); - FH_DMA_DEBUG("cfg_low value:0x%x\n",ret_status); + ret_status = dw_readl(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_LO); + FH_DMA_DEBUG("cfg_low value:0x%x\n",ret_status); - ret_status = dw_readl(temp_dwc, MASK.BLOCK); - FH_DMA_DEBUG("mask block value:0x%x\n",ret_status); + ret_status = dw_readl(temp_dwc, MASK.BLOCK); + FH_DMA_DEBUG("mask block value:0x%x\n",ret_status); - ret_status = dw_readl(temp_dwc, MASK.XFER); - FH_DMA_DEBUG("mask xfer value:0x%x\n",ret_status); + ret_status = dw_readl(temp_dwc, MASK.XFER); + FH_DMA_DEBUG("mask xfer value:0x%x\n",ret_status); - if(dma_trans_desc->prepare_callback){ - dma_trans_desc->prepare_callback(dma_trans_desc->prepare_para); - } - //enable the channle to transfer - channel_set_bit(temp_dwc, CH_EN, lift_shift_bit_num(dma_trans_desc->channel_number)); + if(dma_trans_desc->prepare_callback){ + dma_trans_desc->prepare_callback(dma_trans_desc->prepare_para); + } + //enable the channle to transfer + channel_set_bit(temp_dwc, CH_EN, lift_shift_bit_num(dma_trans_desc->channel_number)); - } + } } @@ -1124,85 +1124,85 @@ static void handle_single_transfer(struct fh81_dma *p_dma,struct dma_transfer * static rt_err_t control (struct rt_dma_device *dma, int cmd, void *arg){ - struct fh81_dma *my_own = (struct fh81_dma *)dma->parent.user_data; - rt_uint32_t i; - struct dw_dma *dwc; - dwc = &my_own->dwc; + struct fh81_dma *my_own = (struct fh81_dma *)dma->parent.user_data; + rt_uint32_t i; + struct dw_dma *dwc; + dwc = &my_own->dwc; - rt_err_t ret = RT_EOK; + rt_err_t ret = RT_EOK; - struct dma_transfer *p_dma_transfer = (struct dma_transfer *)arg; + struct dma_transfer *p_dma_transfer = (struct dma_transfer *)arg; - //FH_DMA_DEBUG("p_dma_transfer value:0x%x\n",(rt_uint32_t)p_dma_transfer); + //FH_DMA_DEBUG("p_dma_transfer value:0x%x\n",(rt_uint32_t)p_dma_transfer); - RT_ASSERT(my_own != RT_NULL); - RT_ASSERT(dwc != RT_NULL); + RT_ASSERT(my_own != RT_NULL); + RT_ASSERT(dwc != RT_NULL); - switch(cmd){ - case RT_DEVICE_CTRL_DMA_OPEN: + switch(cmd){ + case RT_DEVICE_CTRL_DMA_OPEN: - //open the controller.. - handle_dma_open(my_own); - break; - case RT_DEVICE_CTRL_DMA_CLOSE: + //open the controller.. + handle_dma_open(my_own); + break; + case RT_DEVICE_CTRL_DMA_CLOSE: - //close the controller.. - handle_dma_close(my_own); - break; - case RT_DEVICE_CTRL_DMA_REQUEST_CHANNEL: - //request a channel for the user - RT_ASSERT(p_dma_transfer != RT_NULL); - ret = handle_request_channel(my_own,p_dma_transfer); + //close the controller.. + handle_dma_close(my_own); + break; + case RT_DEVICE_CTRL_DMA_REQUEST_CHANNEL: + //request a channel for the user + RT_ASSERT(p_dma_transfer != RT_NULL); + ret = handle_request_channel(my_own,p_dma_transfer); - break; - case RT_DEVICE_CTRL_DMA_RELEASE_CHANNEL: - //release a channel - RT_ASSERT(p_dma_transfer != RT_NULL); + break; + case RT_DEVICE_CTRL_DMA_RELEASE_CHANNEL: + //release a channel + RT_ASSERT(p_dma_transfer != RT_NULL); - ret = handle_release_channel(my_own,p_dma_transfer); + ret = handle_release_channel(my_own,p_dma_transfer); - break; + break; - case RT_DEVICE_CTRL_DMA_SINGLE_TRANSFER: - //make a channel to transfer data. - RT_ASSERT(p_dma_transfer != RT_NULL); - //check if the dma channel is open,or return error. + case RT_DEVICE_CTRL_DMA_SINGLE_TRANSFER: + //make a channel to transfer data. + RT_ASSERT(p_dma_transfer != RT_NULL); + //check if the dma channel is open,or return error. - my_own->dma_channel[p_dma_transfer->channel_number].open_flag = SINGLE_TRANSFER; - handle_single_transfer(my_own,p_dma_transfer); - //then wait for the channel is complete.. - //caution that::we should be in the "rt_enter_critical()"when set the dma to work. - break; + my_own->dma_channel[p_dma_transfer->channel_number].open_flag = SINGLE_TRANSFER; + handle_single_transfer(my_own,p_dma_transfer); + //then wait for the channel is complete.. + //caution that::we should be in the "rt_enter_critical()"when set the dma to work. + break; - case RT_DEVICE_CTRL_DMA_CYCLIC_PREPARE: - RT_ASSERT(p_dma_transfer != RT_NULL); - my_own->dma_channel[p_dma_transfer->channel_number].open_flag = CYCLIC_TRANSFER; - rt_fh_dma_cyclic_prep(my_own,p_dma_transfer); - break; + case RT_DEVICE_CTRL_DMA_CYCLIC_PREPARE: + RT_ASSERT(p_dma_transfer != RT_NULL); + my_own->dma_channel[p_dma_transfer->channel_number].open_flag = CYCLIC_TRANSFER; + rt_fh_dma_cyclic_prep(my_own,p_dma_transfer); + break; - case RT_DEVICE_CTRL_DMA_CYCLIC_START: - rt_fh_dma_cyclic_start(p_dma_transfer); - break; + case RT_DEVICE_CTRL_DMA_CYCLIC_START: + rt_fh_dma_cyclic_start(p_dma_transfer); + break; - case RT_DEVICE_CTRL_DMA_CYCLIC_STOP: - rt_fh_dma_cyclic_stop(p_dma_transfer); - break; + case RT_DEVICE_CTRL_DMA_CYCLIC_STOP: + rt_fh_dma_cyclic_stop(p_dma_transfer); + break; - case RT_DEVICE_CTRL_DMA_CYCLIC_FREE: - rt_fh_dma_cyclic_free(p_dma_transfer); - break; + case RT_DEVICE_CTRL_DMA_CYCLIC_FREE: + rt_fh_dma_cyclic_free(p_dma_transfer); + break; - default: - break; + default: + break; - } + } - return ret; + return ret; } @@ -1213,55 +1213,55 @@ static void rt_fh81_dma_isr(int irq, void *param) { - RT_ASSERT(irq == DMAC_IRQn); - rt_uint32_t isr_channel_x,i,error,isr_channel_b; - struct fh81_dma *my_own = (struct fh81_dma *)param; - struct dw_dma *dwc; - struct dma_transfer *p_transfer; - dwc = &my_own->dwc; - //p_transfer = - //rt_kprintf("dma isr get in~~~\n"); - error = dw_readl(dwc,STATUS.ERROR); - if(error != 0){ - FH_DMA_DEBUG("dma isr error!!!!\n"); - RT_ASSERT(error == RT_NULL); - } - - isr_channel_x = dw_readl(dwc,STATUS.XFER); - isr_channel_b = dw_readl(dwc,STATUS.BLOCK); - //for single check the transfer status - //check which channel... - - for(i=0;idwc.channel_max_number;i++){ - - if(my_own->dma_channel[i].open_flag == SINGLE_TRANSFER){ - if(isr_channel_x & 1<dma_channel[i].active_trans; - - if(p_transfer->complete_callback){ - p_transfer->complete_callback(p_transfer->complete_para); - } - p_transfer->dma_controller->dma_channel[p_transfer->channel_number].channel_status = CHANNEL_STATUS_IDLE; - //here is a bug...do not free here - //rt_free(p_transfer->first_lli); - put_desc(my_own,p_transfer); - rt_list_remove(&p_transfer->transfer_list); - } - - } - - else if(my_own->dma_channel[i].open_flag == CYCLIC_TRANSFER){ - if(isr_channel_b & 1<dma_channel[i].active_trans; - dw_writel(dwc, CLEAR.BLOCK, 1<<(p_transfer->channel_number)); - if(p_transfer->complete_callback){ - p_transfer->complete_callback(p_transfer->complete_para); - } - } - } - } + RT_ASSERT(irq == DMAC_IRQn); + rt_uint32_t isr_channel_x,i,error,isr_channel_b; + struct fh81_dma *my_own = (struct fh81_dma *)param; + struct dw_dma *dwc; + struct dma_transfer *p_transfer; + dwc = &my_own->dwc; + //p_transfer = + //rt_kprintf("dma isr get in~~~\n"); + error = dw_readl(dwc,STATUS.ERROR); + if(error != 0){ + FH_DMA_DEBUG("dma isr error!!!!\n"); + RT_ASSERT(error == RT_NULL); + } + + isr_channel_x = dw_readl(dwc,STATUS.XFER); + isr_channel_b = dw_readl(dwc,STATUS.BLOCK); + //for single check the transfer status + //check which channel... + + for(i=0;idwc.channel_max_number;i++){ + + if(my_own->dma_channel[i].open_flag == SINGLE_TRANSFER){ + if(isr_channel_x & 1<dma_channel[i].active_trans; + + if(p_transfer->complete_callback){ + p_transfer->complete_callback(p_transfer->complete_para); + } + p_transfer->dma_controller->dma_channel[p_transfer->channel_number].channel_status = CHANNEL_STATUS_IDLE; + //here is a bug...do not free here + //rt_free(p_transfer->first_lli); + put_desc(my_own,p_transfer); + rt_list_remove(&p_transfer->transfer_list); + } + + } + + else if(my_own->dma_channel[i].open_flag == CYCLIC_TRANSFER){ + if(isr_channel_b & 1<dma_channel[i].active_trans; + dw_writel(dwc, CLEAR.BLOCK, 1<<(p_transfer->channel_number)); + if(p_transfer->complete_callback){ + p_transfer->complete_callback(p_transfer->complete_para); + } + } + } + } } @@ -1278,55 +1278,55 @@ static void rt_fh81_dma_isr(int irq, void *param) *****************************************************************************/ const char *channel_lock_name[FH81_MAX_CHANNEL] = { - "channel_0_lock", - "channel_1_lock", - "channel_2_lock", - "channel_3_lock", + "channel_0_lock", + "channel_1_lock", + "channel_2_lock", + "channel_3_lock", }; rt_err_t fh81_dma_register(struct fh81_dma * fh81_dma_p, char * dma_name){ - rt_uint32_t i; + rt_uint32_t i; - RT_ASSERT(fh81_dma_p != RT_NULL); - RT_ASSERT(dma_name != RT_NULL); - //RT_ASSERT(fh81_dma_p->dwc.init != FH81_DMA_INIT_ALREADY); + RT_ASSERT(fh81_dma_p != RT_NULL); + RT_ASSERT(dma_name != RT_NULL); + //RT_ASSERT(fh81_dma_p->dwc.init != FH81_DMA_INIT_ALREADY); - if(fh81_dma_p->dwc.init == FH81_DMA_INIT_ALREADY) - return 0; + if(fh81_dma_p->dwc.init == FH81_DMA_INIT_ALREADY) + return 0; - struct rt_dma_device *rt_dma; - rt_dma = &fh81_dma_p->parent; - rt_dma->ops = &fh81_dma_ops; + struct rt_dma_device *rt_dma; + rt_dma = &fh81_dma_p->parent; + rt_dma->ops = &fh81_dma_ops; - //soc para set - fh81_dma_p->dwc.name = dma_name; - fh81_dma_p->dwc.regs =(void *)DMA_REG_BASE; - fh81_dma_p->dwc.paddr = DMA_REG_BASE; - fh81_dma_p->dwc.irq = DMAC_IRQn; - fh81_dma_p->dwc.channel_max_number = FH81_MAX_CHANNEL; - fh81_dma_p->dwc.controller_status = CONTROLLER_STATUS_CLOSED; - fh81_dma_p->dwc.init = FH81_DMA_INIT_ALREADY; - fh81_dma_p->dwc.id = 0; - //channel set - for(i=0;idma_channel[i].channel_status = CHANNEL_STATUS_CLOSED; - fh81_dma_p->dma_channel[i].desc_total_no = DESC_MAX_SIZE; - //rt_completion_init(&(fh81_dma_p->dma_channel[i].transfer_completion)); - rt_list_init(&(fh81_dma_p->dma_channel[i].queue)); - fh81_dma_p->dma_channel[i].desc_trans_size = FH81_CHANNEL_MAX_TRANSFER_SIZE; - rt_sem_init(&fh81_dma_p->dma_channel[i].channel_lock, channel_lock_name[i], 1, RT_IPC_FLAG_FIFO); - } + //soc para set + fh81_dma_p->dwc.name = dma_name; + fh81_dma_p->dwc.regs =(void *)DMA_REG_BASE; + fh81_dma_p->dwc.paddr = DMA_REG_BASE; + fh81_dma_p->dwc.irq = DMAC_IRQn; + fh81_dma_p->dwc.channel_max_number = FH81_MAX_CHANNEL; + fh81_dma_p->dwc.controller_status = CONTROLLER_STATUS_CLOSED; + fh81_dma_p->dwc.init = FH81_DMA_INIT_ALREADY; + fh81_dma_p->dwc.id = 0; + //channel set + for(i=0;idma_channel[i].channel_status = CHANNEL_STATUS_CLOSED; + fh81_dma_p->dma_channel[i].desc_total_no = DESC_MAX_SIZE; + //rt_completion_init(&(fh81_dma_p->dma_channel[i].transfer_completion)); + rt_list_init(&(fh81_dma_p->dma_channel[i].queue)); + fh81_dma_p->dma_channel[i].desc_trans_size = FH81_CHANNEL_MAX_TRANSFER_SIZE; + rt_sem_init(&fh81_dma_p->dma_channel[i].channel_lock, channel_lock_name[i], 1, RT_IPC_FLAG_FIFO); + } - //isr - rt_hw_interrupt_install(fh81_dma_p->dwc.irq, rt_fh81_dma_isr, - (void *)fh81_dma_p, "dma_isr"); - rt_hw_interrupt_umask(fh81_dma_p->dwc.irq); + //isr + rt_hw_interrupt_install(fh81_dma_p->dwc.irq, rt_fh81_dma_isr, + (void *)fh81_dma_p, "dma_isr"); + rt_hw_interrupt_umask(fh81_dma_p->dwc.irq); - return rt_hw_dma_register(rt_dma,dma_name,RT_DEVICE_FLAG_RDWR,fh81_dma_p); + return rt_hw_dma_register(rt_dma,dma_name,RT_DEVICE_FLAG_RDWR,fh81_dma_p); } @@ -1334,10 +1334,10 @@ rt_err_t fh81_dma_register(struct fh81_dma * fh81_dma_p, static void rt_fh_dma_cyclic_stop(struct dma_transfer *p){ - struct fh81_dma *my_own = p->dma_controller; - struct dw_dma *dwc; - dwc = &my_own->dwc; - channel_clear_bit(dwc, CH_EN, 1<<(p->channel_number)); + struct fh81_dma *my_own = p->dma_controller; + struct dw_dma *dwc; + dwc = &my_own->dwc; + channel_clear_bit(dwc, CH_EN, 1<<(p->channel_number)); } @@ -1345,45 +1345,45 @@ static void rt_fh_dma_cyclic_stop(struct dma_transfer *p){ static void rt_fh_dma_cyclic_start(struct dma_transfer *p){ - struct fh81_dma *my_own = p->dma_controller; - struct dw_dma *dwc; - dwc = &my_own->dwc; - volatile uint32_t ret_status; - struct dw_lli *p_lli = RT_NULL; - p_lli = p->first_lli; + struct fh81_dma *my_own = p->dma_controller; + struct dw_dma *dwc; + dwc = &my_own->dwc; + volatile uint32_t ret_status; + struct dw_lli *p_lli = RT_NULL; + p_lli = p->first_lli; - //32bit ally - RT_ASSERT(((uint32_t)p_lli & 0x03) == 0); + //32bit ally + RT_ASSERT(((uint32_t)p_lli & 0x03) == 0); - dw_writel(dwc, CLEAR.XFER, 1<<(p->channel_number)); - dw_writel(dwc, CLEAR.BLOCK, 1<<(p->channel_number)); - dw_writel(dwc, CLEAR.ERROR, 1<<(p->channel_number)); + dw_writel(dwc, CLEAR.XFER, 1<<(p->channel_number)); + dw_writel(dwc, CLEAR.BLOCK, 1<<(p->channel_number)); + dw_writel(dwc, CLEAR.ERROR, 1<<(p->channel_number)); - //enable isr - channel_set_bit(dwc, MASK.BLOCK, lift_shift_bit_num(p->channel_number)); - //disable isr - channel_clear_bit(dwc, MASK.XFER, lift_shift_bit_num(p->channel_number)); + //enable isr + channel_set_bit(dwc, MASK.BLOCK, lift_shift_bit_num(p->channel_number)); + //disable isr + channel_clear_bit(dwc, MASK.XFER, lift_shift_bit_num(p->channel_number)); - ret_status = dw_readl(dwc,CHAN[p->channel_number].CFG_LO); - ret_status &= ~(DWC_CFGL_RELOAD_SAR|DWC_CFGL_RELOAD_DAR); - dw_writel(dwc,CHAN[p->channel_number].CFG_LO,ret_status); + ret_status = dw_readl(dwc,CHAN[p->channel_number].CFG_LO); + ret_status &= ~(DWC_CFGL_RELOAD_SAR|DWC_CFGL_RELOAD_DAR); + dw_writel(dwc,CHAN[p->channel_number].CFG_LO,ret_status); - //set the first link add - ret_status = dw_readl(dwc,CHAN[p->channel_number].LLP); - ret_status = (uint32_t)&p_lli[0]; - dw_writel(dwc,CHAN[p->channel_number].LLP,ret_status); + //set the first link add + ret_status = dw_readl(dwc,CHAN[p->channel_number].LLP); + ret_status = (uint32_t)&p_lli[0]; + dw_writel(dwc,CHAN[p->channel_number].LLP,ret_status); - //set link enable - //ret_status = dw_readl(dwc,CHAN[p->channel_number].CTL_LO); - ret_status =DWC_CTLL_LLP_D_EN|DWC_CTLL_LLP_S_EN; - dw_writel(dwc,CHAN[p->channel_number].CTL_LO,ret_status); + //set link enable + //ret_status = dw_readl(dwc,CHAN[p->channel_number].CTL_LO); + ret_status =DWC_CTLL_LLP_D_EN|DWC_CTLL_LLP_S_EN; + dw_writel(dwc,CHAN[p->channel_number].CTL_LO,ret_status); - //clear ctl_hi - dw_writel(dwc,CHAN[p->channel_number].CTL_HI,0); + //clear ctl_hi + dw_writel(dwc,CHAN[p->channel_number].CTL_HI,0); - //enable channle - channel_set_bit(dwc, CH_EN, 1<<(p->channel_number)); + //enable channle + channel_set_bit(dwc, CH_EN, 1<<(p->channel_number)); } @@ -1391,228 +1391,228 @@ static void rt_fh_dma_cyclic_start(struct dma_transfer *p){ static void rt_fh_dma_cyclic_prep(struct fh81_dma * fh81_dma_p,struct dma_transfer *p) { - //bind the controller to the transfer - p->dma_controller = fh81_dma_p; - //bind active transfer - fh81_dma_p->dma_channel[p->channel_number].active_trans = p; - //p_transfer->dma_controller->dma_channel[p_transfer->channel_number].active_trans = dma_trans_desc; - struct fh81_dma *my_own = p->dma_controller; - struct dw_dma *dwc; - dwc = &my_own->dwc; - volatile uint32_t ret_status; - struct dw_lli *p_lli = RT_NULL; - uint32_t periods,i; - uint32_t temp_src_add; - uint32_t temp_dst_add; - uint32_t buf_len = p->trans_len; - uint32_t period_len = p->period_len; + //bind the controller to the transfer + p->dma_controller = fh81_dma_p; + //bind active transfer + fh81_dma_p->dma_channel[p->channel_number].active_trans = p; + //p_transfer->dma_controller->dma_channel[p_transfer->channel_number].active_trans = dma_trans_desc; + struct fh81_dma *my_own = p->dma_controller; + struct dw_dma *dwc; + dwc = &my_own->dwc; + volatile uint32_t ret_status; + struct dw_lli *p_lli = RT_NULL; + uint32_t periods,i; + uint32_t temp_src_add; + uint32_t temp_dst_add; + uint32_t buf_len = p->trans_len; + uint32_t period_len = p->period_len; - struct dma_transfer * dma_trans_desc = p; - //check first... - RT_ASSERT(buf_len % period_len == 0); + struct dma_transfer * dma_trans_desc = p; + //check first... + RT_ASSERT(buf_len % period_len == 0); - //cal the periods... - periods = buf_len / period_len; + //cal the periods... + periods = buf_len / period_len; - //get desc.... - //dma_trans_desc->first_lli = (struct dw_lli *)rt_malloc(periods * sizeof(struct dw_lli)); - dma_trans_desc->first_lli = get_desc(fh81_dma_p,dma_trans_desc,periods); + //get desc.... + //dma_trans_desc->first_lli = (struct dw_lli *)rt_malloc(periods * sizeof(struct dw_lli)); + dma_trans_desc->first_lli = get_desc(fh81_dma_p,dma_trans_desc,periods); - if(dma_trans_desc->first_lli == RT_NULL){ + if(dma_trans_desc->first_lli == RT_NULL){ - FH_DMA_DEBUG("transfer error,reason: not enough mem..\n"); - RT_ASSERT(dma_trans_desc->first_lli != RT_NULL); - } + FH_DMA_DEBUG("transfer error,reason: not enough mem..\n"); + RT_ASSERT(dma_trans_desc->first_lli != RT_NULL); + } - rt_memset((void *)dma_trans_desc->first_lli, 0, periods * sizeof(struct dw_lli)); - p_lli = dma_trans_desc->first_lli; + rt_memset((void *)dma_trans_desc->first_lli, 0, periods * sizeof(struct dw_lli)); + p_lli = dma_trans_desc->first_lli; - RT_ASSERT(((uint32_t)p_lli & 0x03) == 0); + RT_ASSERT(((uint32_t)p_lli & 0x03) == 0); - RT_ASSERT(dma_trans_desc->dst_inc_mode <=DW_DMA_SLAVE_FIX); - RT_ASSERT(dma_trans_desc->src_inc_mode <=DW_DMA_SLAVE_FIX); - //step3: set the mem.. - for(i=0;idst_inc_mode){ - case DW_DMA_SLAVE_INC: - temp_dst_add = dma_trans_desc->dst_add + i * period_len * (1<dst_width); - break; - case DW_DMA_SLAVE_DEC: - temp_dst_add = dma_trans_desc->dst_add - i * period_len * (1<dst_width); - break; - case DW_DMA_SLAVE_FIX: - temp_dst_add = dma_trans_desc->dst_add; - break; + RT_ASSERT(dma_trans_desc->dst_inc_mode <=DW_DMA_SLAVE_FIX); + RT_ASSERT(dma_trans_desc->src_inc_mode <=DW_DMA_SLAVE_FIX); + //step3: set the mem.. + for(i=0;idst_inc_mode){ + case DW_DMA_SLAVE_INC: + temp_dst_add = dma_trans_desc->dst_add + i * period_len * (1<dst_width); + break; + case DW_DMA_SLAVE_DEC: + temp_dst_add = dma_trans_desc->dst_add - i * period_len * (1<dst_width); + break; + case DW_DMA_SLAVE_FIX: + temp_dst_add = dma_trans_desc->dst_add; + break; - } + } - switch(dma_trans_desc->src_inc_mode){ - case DW_DMA_SLAVE_INC: - temp_src_add = dma_trans_desc->src_add + i * period_len * (1<src_width); - break; - case DW_DMA_SLAVE_DEC: - temp_src_add = dma_trans_desc->src_add - i * period_len * (1<src_width); - break; - case DW_DMA_SLAVE_FIX: - temp_src_add = dma_trans_desc->src_add ; - break; - - } - - - p_lli[i].sar = temp_src_add; - p_lli[i].dar = temp_dst_add; - - //para ctl - - - RT_ASSERT(dma_trans_desc->dst_width <=DW_DMA_SLAVE_WIDTH_32BIT); - RT_ASSERT(dma_trans_desc->src_width <=DW_DMA_SLAVE_WIDTH_32BIT); - - RT_ASSERT(dma_trans_desc->dst_msize <=DW_DMA_SLAVE_MSIZE_256); - RT_ASSERT(dma_trans_desc->src_msize <=DW_DMA_SLAVE_MSIZE_256); - RT_ASSERT(dma_trans_desc->fc_mode <=DMA_P2P); + switch(dma_trans_desc->src_inc_mode){ + case DW_DMA_SLAVE_INC: + temp_src_add = dma_trans_desc->src_add + i * period_len * (1<src_width); + break; + case DW_DMA_SLAVE_DEC: + temp_src_add = dma_trans_desc->src_add - i * period_len * (1<src_width); + break; + case DW_DMA_SLAVE_FIX: + temp_src_add = dma_trans_desc->src_add ; + break; + + } + + + p_lli[i].sar = temp_src_add; + p_lli[i].dar = temp_dst_add; + + //para ctl + + + RT_ASSERT(dma_trans_desc->dst_width <=DW_DMA_SLAVE_WIDTH_32BIT); + RT_ASSERT(dma_trans_desc->src_width <=DW_DMA_SLAVE_WIDTH_32BIT); + + RT_ASSERT(dma_trans_desc->dst_msize <=DW_DMA_SLAVE_MSIZE_256); + RT_ASSERT(dma_trans_desc->src_msize <=DW_DMA_SLAVE_MSIZE_256); + RT_ASSERT(dma_trans_desc->fc_mode <=DMA_P2P); - p_lli[i].ctllo = DWC_CTLL_INT_EN|DWC_CTLL_DST_WIDTH(dma_trans_desc->dst_width)|DWC_CTLL_SRC_WIDTH(dma_trans_desc->src_width) - |DWC_CTLL_DST_INC_MODE(dma_trans_desc->dst_inc_mode)|DWC_CTLL_SRC_INC_MODE(dma_trans_desc->src_inc_mode) - |DWC_CTLL_DST_MSIZE(dma_trans_desc->dst_msize)|DWC_CTLL_SRC_MSIZE(dma_trans_desc->src_msize)|DWC_CTLL_FC(dma_trans_desc->fc_mode) - |DWC_CTLL_DMS(0)|DWC_CTLL_SMS(0); - //block size - p_lli[i].ctlhi = period_len; + p_lli[i].ctllo = DWC_CTLL_INT_EN|DWC_CTLL_DST_WIDTH(dma_trans_desc->dst_width)|DWC_CTLL_SRC_WIDTH(dma_trans_desc->src_width) + |DWC_CTLL_DST_INC_MODE(dma_trans_desc->dst_inc_mode)|DWC_CTLL_SRC_INC_MODE(dma_trans_desc->src_inc_mode) + |DWC_CTLL_DST_MSIZE(dma_trans_desc->dst_msize)|DWC_CTLL_SRC_MSIZE(dma_trans_desc->src_msize)|DWC_CTLL_FC(dma_trans_desc->fc_mode) + |DWC_CTLL_DMS(0)|DWC_CTLL_SMS(0); + //block size + p_lli[i].ctlhi = period_len; - p_lli[i].llp = (uint32_t)&p_lli[i+1]; - p_lli[i].ctllo |= DWC_CTLL_LLP_D_EN|DWC_CTLL_LLP_S_EN; - - - //flush cache to mem - mmu_clean_invalidated_dcache((uint32_t)&p_lli[i],sizeof(struct dw_lli)); + p_lli[i].llp = (uint32_t)&p_lli[i+1]; + p_lli[i].ctllo |= DWC_CTLL_LLP_D_EN|DWC_CTLL_LLP_S_EN; + + + //flush cache to mem + mmu_clean_invalidated_dcache((uint32_t)&p_lli[i],sizeof(struct dw_lli)); - dump_lli(&p_lli[i]); - } - //make a ring here - p_lli[periods -1 ].llp = (uint32_t)&p_lli[0]; + dump_lli(&p_lli[i]); + } + //make a ring here + p_lli[periods -1 ].llp = (uint32_t)&p_lli[0]; - mmu_clean_invalidated_dcache((uint32_t)&p_lli[periods -1 ],sizeof(struct dw_lli)); + mmu_clean_invalidated_dcache((uint32_t)&p_lli[periods -1 ],sizeof(struct dw_lli)); - //parse the handshake - RT_ASSERT(dma_trans_desc->dst_hs <= DMA_SW_HANDSHAKING); - RT_ASSERT(dma_trans_desc->src_hs <= DMA_SW_HANDSHAKING); + //parse the handshake + RT_ASSERT(dma_trans_desc->dst_hs <= DMA_SW_HANDSHAKING); + RT_ASSERT(dma_trans_desc->src_hs <= DMA_SW_HANDSHAKING); - //dst handshake - dw_writel(dwc,CHAN[dma_trans_desc->channel_number].CFG_LO,0); - ret_status = 0; - if(dma_trans_desc->dst_hs == DMA_SW_HANDSHAKING){ - ret_status |= DWC_CFGL_HS_DST; - } - else{ - ret_status &= ~DWC_CFGL_HS_DST; - } - dw_writel(dwc,CHAN[dma_trans_desc->channel_number].CFG_LO,ret_status); + //dst handshake + dw_writel(dwc,CHAN[dma_trans_desc->channel_number].CFG_LO,0); + ret_status = 0; + if(dma_trans_desc->dst_hs == DMA_SW_HANDSHAKING){ + ret_status |= DWC_CFGL_HS_DST; + } + else{ + ret_status &= ~DWC_CFGL_HS_DST; + } + dw_writel(dwc,CHAN[dma_trans_desc->channel_number].CFG_LO,ret_status); - //src handshake - ret_status = dw_readl(dwc,CHAN[dma_trans_desc->channel_number].CFG_LO); - if(dma_trans_desc->src_hs == DMA_SW_HANDSHAKING){ - ret_status |= DWC_CFGL_HS_SRC; - } - else{ - ret_status &= ~DWC_CFGL_HS_SRC; - } - dw_writel(dwc,CHAN[dma_trans_desc->channel_number].CFG_LO,ret_status); - - - //only hw handshaking need this.. - switch(dma_trans_desc->fc_mode){ - case DMA_M2M: - break; - case DMA_M2P: - //set dst per... - RT_ASSERT(dma_trans_desc->dst_per < DMA_HW_HS_END); - ret_status = dw_readl(dwc,CHAN[dma_trans_desc->channel_number].CFG_HI); - //clear 43 ~ 46 bit - ret_status &= ~0x7800; - ret_status |= DWC_CFGH_DST_PER(dma_trans_desc->dst_per); - dw_writel(dwc,CHAN[dma_trans_desc->channel_number].CFG_HI,ret_status); - //DWC_CFGH_SRC_PER + //src handshake + ret_status = dw_readl(dwc,CHAN[dma_trans_desc->channel_number].CFG_LO); + if(dma_trans_desc->src_hs == DMA_SW_HANDSHAKING){ + ret_status |= DWC_CFGL_HS_SRC; + } + else{ + ret_status &= ~DWC_CFGL_HS_SRC; + } + dw_writel(dwc,CHAN[dma_trans_desc->channel_number].CFG_LO,ret_status); + + + //only hw handshaking need this.. + switch(dma_trans_desc->fc_mode){ + case DMA_M2M: + break; + case DMA_M2P: + //set dst per... + RT_ASSERT(dma_trans_desc->dst_per < DMA_HW_HS_END); + ret_status = dw_readl(dwc,CHAN[dma_trans_desc->channel_number].CFG_HI); + //clear 43 ~ 46 bit + ret_status &= ~0x7800; + ret_status |= DWC_CFGH_DST_PER(dma_trans_desc->dst_per); + dw_writel(dwc,CHAN[dma_trans_desc->channel_number].CFG_HI,ret_status); + //DWC_CFGH_SRC_PER - break; - case DMA_P2M: - //set src per... - RT_ASSERT(dma_trans_desc->src_per < DMA_HW_HS_END); - ret_status = dw_readl(dwc,CHAN[dma_trans_desc->channel_number].CFG_HI); - //clear 39 ~ 42 bit - ret_status &= ~0x780; - ret_status |= DWC_CFGH_SRC_PER(dma_trans_desc->src_per); - dw_writel(dwc,CHAN[dma_trans_desc->channel_number].CFG_HI,ret_status); + break; + case DMA_P2M: + //set src per... + RT_ASSERT(dma_trans_desc->src_per < DMA_HW_HS_END); + ret_status = dw_readl(dwc,CHAN[dma_trans_desc->channel_number].CFG_HI); + //clear 39 ~ 42 bit + ret_status &= ~0x780; + ret_status |= DWC_CFGH_SRC_PER(dma_trans_desc->src_per); + dw_writel(dwc,CHAN[dma_trans_desc->channel_number].CFG_HI,ret_status); - break; - case DMA_P2P: - //set src and dst.. - RT_ASSERT(dma_trans_desc->dst_per < DMA_HW_HS_END); - RT_ASSERT(dma_trans_desc->src_per < DMA_HW_HS_END); + break; + case DMA_P2P: + //set src and dst.. + RT_ASSERT(dma_trans_desc->dst_per < DMA_HW_HS_END); + RT_ASSERT(dma_trans_desc->src_per < DMA_HW_HS_END); - ret_status = dw_readl(dwc,CHAN[dma_trans_desc->channel_number].CFG_HI); - ret_status &= ~0x7800; - ret_status &= ~0x780; - ret_status |= DWC_CFGH_SRC_PER(dma_trans_desc->src_per) | DWC_CFGH_DST_PER(dma_trans_desc->dst_per); - dw_writel(dwc,CHAN[dma_trans_desc->channel_number].CFG_HI,ret_status); + ret_status = dw_readl(dwc,CHAN[dma_trans_desc->channel_number].CFG_HI); + ret_status &= ~0x7800; + ret_status &= ~0x780; + ret_status |= DWC_CFGH_SRC_PER(dma_trans_desc->src_per) | DWC_CFGH_DST_PER(dma_trans_desc->dst_per); + dw_writel(dwc,CHAN[dma_trans_desc->channel_number].CFG_HI,ret_status); - break; - default: - break; - } + break; + default: + break; + } - dma_trans_desc->dma_controller->dma_channel[dma_trans_desc->channel_number].channel_status = CHANNEL_STATUS_BUSY; + dma_trans_desc->dma_controller->dma_channel[dma_trans_desc->channel_number].channel_status = CHANNEL_STATUS_BUSY; - if(dma_trans_desc->prepare_callback){ - dma_trans_desc->prepare_callback(dma_trans_desc->prepare_para); - } + if(dma_trans_desc->prepare_callback){ + dma_trans_desc->prepare_callback(dma_trans_desc->prepare_para); + } } static void rt_fh_dma_cyclic_free(struct dma_transfer *p){ - struct fh81_dma *my_own = p->dma_controller; - struct dw_dma *dwc; - dwc = &my_own->dwc; - volatile uint32_t ret_status; - struct dw_lli *p_lli = RT_NULL; - p_lli = p->first_lli; + struct fh81_dma *my_own = p->dma_controller; + struct dw_dma *dwc; + dwc = &my_own->dwc; + volatile uint32_t ret_status; + struct dw_lli *p_lli = RT_NULL; + p_lli = p->first_lli; - //close channel first.. - channel_clear_bit(dwc, CH_EN, 1<<(p->channel_number)); + //close channel first.. + channel_clear_bit(dwc, CH_EN, 1<<(p->channel_number)); - //check if close really - while (dw_readl(dwc, CH_EN) & 1<<(p->channel_number)); + //check if close really + while (dw_readl(dwc, CH_EN) & 1<<(p->channel_number)); - dw_writel(dwc, CLEAR.XFER, 1<<(p->channel_number)); - dw_writel(dwc, CLEAR.BLOCK, 1<<(p->channel_number)); - dw_writel(dwc, CLEAR.ERROR, 1<<(p->channel_number)); + dw_writel(dwc, CLEAR.XFER, 1<<(p->channel_number)); + dw_writel(dwc, CLEAR.BLOCK, 1<<(p->channel_number)); + dw_writel(dwc, CLEAR.ERROR, 1<<(p->channel_number)); - //rt_free(p->first_lli); - put_desc(my_own,p); + //rt_free(p->first_lli); + put_desc(my_own,p); } void rt_fh_dma_init(void){ - fh81_dma_register(&fh81_dma_controller[0],"fh81_dma"); + fh81_dma_register(&fh81_dma_controller[0],"fh81_dma"); } diff --git a/bsp/fh8620/drivers/fh_dma.h b/bsp/fh8620/drivers/fh_dma.h index faceac2de..477718d0a 100644 --- a/bsp/fh8620/drivers/fh_dma.h +++ b/bsp/fh8620/drivers/fh_dma.h @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,19 +18,19 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + #ifndef FH_DMA_H_ #define FH_DMA_H_ /**************************************************************************** * #include section -* add #include here if any +* add #include here if any ***************************************************************************/ #include @@ -43,24 +43,24 @@ *********************************/ -#define FH81_MAX_CHANNEL (4) -#define FH81_CHANNEL_MAX_TRANSFER_SIZE (4095) +#define FH81_MAX_CHANNEL (4) +#define FH81_CHANNEL_MAX_TRANSFER_SIZE (4095) enum DMA_HW_HS_MAP{ - ACODEC_RX = 0, - ACODEC_TX, - SPI0_RX, - SPI0_TX, - SPI1_RX, - SPI1_TX, - UART0_RX, - UART0_TX, - UART1_RX, - UART1_TX, - DMA_HW_HS_END, + ACODEC_RX = 0, + ACODEC_TX, + SPI0_RX, + SPI0_TX, + SPI1_RX, + SPI1_TX, + UART0_RX, + UART0_TX, + UART1_RX, + UART1_TX, + DMA_HW_HS_END, }; /********************************* @@ -76,7 +76,7 @@ typedef void (*user_prepare)(void *prepare_para); -/**************************** i'm cut-off line ************************************/ +/**************************** i'm cut-off line ************************************/ @@ -88,128 +88,128 @@ struct fh81_dma; struct dw_lli { - /* values that are not changed by hardware */ - rt_uint32_t sar; - rt_uint32_t dar; - rt_uint32_t llp; /* chain to next lli */ - rt_uint32_t ctllo; - /* values that may get written back: */ - rt_uint32_t ctlhi; - /* sstat and dstat can snapshot peripheral register state. - * silicon config may discard either or both... - */ - rt_uint32_t sstat; - rt_uint32_t dstat; - rt_uint32_t reserve; + /* values that are not changed by hardware */ + rt_uint32_t sar; + rt_uint32_t dar; + rt_uint32_t llp; /* chain to next lli */ + rt_uint32_t ctllo; + /* values that may get written back: */ + rt_uint32_t ctlhi; + /* sstat and dstat can snapshot peripheral register state. + * silicon config may discard either or both... + */ + rt_uint32_t sstat; + rt_uint32_t dstat; + rt_uint32_t reserve; }; //transfer use below struct dma_transfer{ - //this is private for the dma drive....app don't touch it,the driver will manger it - //link interface for more transfer to the controller... - rt_list_t transfer_list; - struct fh81_dma *dma_controller; - //this the mem add....the dma controller will load the setting to move data .... - //user don't touch it - struct dw_lli *first_lli; - rt_uint32_t lli_size; - //new add for allign get desc... - rt_uint32_t actual_lli_size; - - - //user could set paras below~~~ -#define AUTO_FIND_CHANNEL (0xff) - //transfer with which dma channel...if the data is 0xff, the driver will auto find a free channel. - rt_uint32_t channel_number; - //which dma you want to use...for fh81....only 0!!! - rt_uint32_t dma_number; - - - //user should set the para below -#define DMA_M2M (0) // MEM <=> MEM -#define DMA_M2P (1) // MEM => peripheral A -#define DMA_P2M (2) // MEM <= peripheral A -#define DMA_P2P (3) // peripheral A <=> peripheral B - rt_uint32_t fc_mode;//ip->mem. mem->mem. mem->ip - - - - -#define DMA_HW_HANDSHAKING (0) -#define DMA_SW_HANDSHAKING (1) - rt_uint32_t src_hs; //src - //if use hw handshaking ,you need to set the hw handshaking number, this SOC defined - rt_uint32_t src_per; //src hw handshake number - //rt_uint32_t irq_mode;//for each transfer,irq maybe not same. suggest for the default(transfer isr) - -#define DW_DMA_SLAVE_WIDTH_8BIT (0) -#define DW_DMA_SLAVE_WIDTH_16BIT (1) -#define DW_DMA_SLAVE_WIDTH_32BIT (2) - rt_uint32_t src_width; - - //the user should reference the hw handshaking watermark.. -#define DW_DMA_SLAVE_MSIZE_1 (0) -#define DW_DMA_SLAVE_MSIZE_4 (1) -#define DW_DMA_SLAVE_MSIZE_8 (2) -#define DW_DMA_SLAVE_MSIZE_16 (3) -#define DW_DMA_SLAVE_MSIZE_32 (4) -#define DW_DMA_SLAVE_MSIZE_64 (5) -#define DW_DMA_SLAVE_MSIZE_128 (6) -#define DW_DMA_SLAVE_MSIZE_256 (7) - rt_uint32_t src_msize; - rt_uint32_t src_add; -#define DW_DMA_SLAVE_INC (0) -#define DW_DMA_SLAVE_DEC (1) -#define DW_DMA_SLAVE_FIX (2) - rt_uint32_t src_inc_mode; //increase mode: increase or not change - - -//#define DMA_DST_HW_HANDSHAKING (0) -//#define DMA_DST_SW_HANDSHAKING (1) - rt_uint32_t dst_hs; //src - //if use hw handshaking ,you need to set the hw handshaking number, this SOC defined - rt_uint32_t dst_per; //dst hw handshake number -//#define DW_DMA_SLAVE_WIDTH_8BIT (0) -//#define DW_DMA_SLAVE_WIDTH_16BIT (1) -//#define DW_DMA_SLAVE_WIDTH_32BIT (2) - rt_uint32_t dst_width; -//#define DW_DMA_SLAVE_MSIZE_1 (0) -//#define DW_DMA_SLAVE_MSIZE_4 (1) -//#define DW_DMA_SLAVE_MSIZE_8 (2) -//#define DW_DMA_SLAVE_MSIZE_16 (3) -//#define DW_DMA_SLAVE_MSIZE_32 (4) -//#define DW_DMA_SLAVE_MSIZE_64 (5) -//#define DW_DMA_SLAVE_MSIZE_128 (6) -//#define DW_DMA_SLAVE_MSIZE_256 (7) - rt_uint32_t dst_msize; - rt_uint32_t dst_add; -//#define DW_DMA_SLAVE_INC (0) -//#define DW_DMA_SLAVE_DEC (1) -//#define DW_DMA_SLAVE_FIX (2) - rt_uint32_t dst_inc_mode; //increase mode: increase or not change - - - //total sizes, unit: src_width/DW_DMA_SLAVE_WIDTH_8BIT... - //exg: src_width = DW_DMA_SLAVE_WIDTH_32BIT. trans_len = 2...means that: the dma will transfer 2*4 bytes.. - //exg: src_width = DW_DMA_SLAVE_WIDTH_8BIT. trans_len = 6...means that: the dma will transfer 1*6 bytes.. - rt_uint32_t trans_len; - - - - //this is used when dma finish transfer job - dma_complete_callback complete_callback; - void *complete_para; //for the driver data use the dma driver. - - - //this is used when dma before work..the user maybe need to set his own private para.. - user_prepare prepare_callback; - void *prepare_para; - - - //add cyclic para... - //period len.. - rt_uint32_t period_len; + //this is private for the dma drive....app don't touch it,the driver will manger it + //link interface for more transfer to the controller... + rt_list_t transfer_list; + struct fh81_dma *dma_controller; + //this the mem add....the dma controller will load the setting to move data .... + //user don't touch it + struct dw_lli *first_lli; + rt_uint32_t lli_size; + //new add for allign get desc... + rt_uint32_t actual_lli_size; + + + //user could set paras below~~~ +#define AUTO_FIND_CHANNEL (0xff) + //transfer with which dma channel...if the data is 0xff, the driver will auto find a free channel. + rt_uint32_t channel_number; + //which dma you want to use...for fh81....only 0!!! + rt_uint32_t dma_number; + + + //user should set the para below +#define DMA_M2M (0) // MEM <=> MEM +#define DMA_M2P (1) // MEM => peripheral A +#define DMA_P2M (2) // MEM <= peripheral A +#define DMA_P2P (3) // peripheral A <=> peripheral B + rt_uint32_t fc_mode;//ip->mem. mem->mem. mem->ip + + + + +#define DMA_HW_HANDSHAKING (0) +#define DMA_SW_HANDSHAKING (1) + rt_uint32_t src_hs; //src + //if use hw handshaking ,you need to set the hw handshaking number, this SOC defined + rt_uint32_t src_per; //src hw handshake number + //rt_uint32_t irq_mode;//for each transfer,irq maybe not same. suggest for the default(transfer isr) + +#define DW_DMA_SLAVE_WIDTH_8BIT (0) +#define DW_DMA_SLAVE_WIDTH_16BIT (1) +#define DW_DMA_SLAVE_WIDTH_32BIT (2) + rt_uint32_t src_width; + + //the user should reference the hw handshaking watermark.. +#define DW_DMA_SLAVE_MSIZE_1 (0) +#define DW_DMA_SLAVE_MSIZE_4 (1) +#define DW_DMA_SLAVE_MSIZE_8 (2) +#define DW_DMA_SLAVE_MSIZE_16 (3) +#define DW_DMA_SLAVE_MSIZE_32 (4) +#define DW_DMA_SLAVE_MSIZE_64 (5) +#define DW_DMA_SLAVE_MSIZE_128 (6) +#define DW_DMA_SLAVE_MSIZE_256 (7) + rt_uint32_t src_msize; + rt_uint32_t src_add; +#define DW_DMA_SLAVE_INC (0) +#define DW_DMA_SLAVE_DEC (1) +#define DW_DMA_SLAVE_FIX (2) + rt_uint32_t src_inc_mode; //increase mode: increase or not change + + +//#define DMA_DST_HW_HANDSHAKING (0) +//#define DMA_DST_SW_HANDSHAKING (1) + rt_uint32_t dst_hs; //src + //if use hw handshaking ,you need to set the hw handshaking number, this SOC defined + rt_uint32_t dst_per; //dst hw handshake number +//#define DW_DMA_SLAVE_WIDTH_8BIT (0) +//#define DW_DMA_SLAVE_WIDTH_16BIT (1) +//#define DW_DMA_SLAVE_WIDTH_32BIT (2) + rt_uint32_t dst_width; +//#define DW_DMA_SLAVE_MSIZE_1 (0) +//#define DW_DMA_SLAVE_MSIZE_4 (1) +//#define DW_DMA_SLAVE_MSIZE_8 (2) +//#define DW_DMA_SLAVE_MSIZE_16 (3) +//#define DW_DMA_SLAVE_MSIZE_32 (4) +//#define DW_DMA_SLAVE_MSIZE_64 (5) +//#define DW_DMA_SLAVE_MSIZE_128 (6) +//#define DW_DMA_SLAVE_MSIZE_256 (7) + rt_uint32_t dst_msize; + rt_uint32_t dst_add; +//#define DW_DMA_SLAVE_INC (0) +//#define DW_DMA_SLAVE_DEC (1) +//#define DW_DMA_SLAVE_FIX (2) + rt_uint32_t dst_inc_mode; //increase mode: increase or not change + + + //total sizes, unit: src_width/DW_DMA_SLAVE_WIDTH_8BIT... + //exg: src_width = DW_DMA_SLAVE_WIDTH_32BIT. trans_len = 2...means that: the dma will transfer 2*4 bytes.. + //exg: src_width = DW_DMA_SLAVE_WIDTH_8BIT. trans_len = 6...means that: the dma will transfer 1*6 bytes.. + rt_uint32_t trans_len; + + + + //this is used when dma finish transfer job + dma_complete_callback complete_callback; + void *complete_para; //for the driver data use the dma driver. + + + //this is used when dma before work..the user maybe need to set his own private para.. + user_prepare prepare_callback; + void *prepare_para; + + + //add cyclic para... + //period len.. + rt_uint32_t period_len; }; @@ -223,13 +223,13 @@ struct dma_transfer{ /**************************************************************************** * #define section -* add constant #define here if any +* add constant #define here if any ***************************************************************************/ /**************************************************************************** * ADT section -* add Abstract Data Type definition here +* add Abstract Data Type definition here ***************************************************************************/ @@ -240,7 +240,7 @@ struct dma_transfer{ /**************************************************************************** * section -* add function prototype here if any +* add function prototype here if any ***************************************************************************/ rt_err_t fh81_dma_register(struct fh81_dma * fh81_dma_p, char * dma_name); diff --git a/bsp/fh8620/drivers/gpio.c b/bsp/fh8620/drivers/gpio.c index fc3fff639..7a0dca36d 100644 --- a/bsp/fh8620/drivers/gpio.c +++ b/bsp/fh8620/drivers/gpio.c @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,7 +18,7 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes @@ -410,10 +410,10 @@ int fh_gpio_probe(void *priv_data) int i; if(gpio_obj->id == 0){ - rt_hw_interrupt_install(gpio_obj->irq, fh_gpio_interrupt, (void *)gpio_obj, "gpio_0"); + rt_hw_interrupt_install(gpio_obj->irq, fh_gpio_interrupt, (void *)gpio_obj, "gpio_0"); } else if(gpio_obj->id == 1){ - rt_hw_interrupt_install(gpio_obj->irq, fh_gpio_interrupt, (void *)gpio_obj, "gpio_1"); + rt_hw_interrupt_install(gpio_obj->irq, fh_gpio_interrupt, (void *)gpio_obj, "gpio_1"); } diff --git a/bsp/fh8620/drivers/gpio.h b/bsp/fh8620/drivers/gpio.h index 7fe4d236b..97b613871 100644 --- a/bsp/fh8620/drivers/gpio.h +++ b/bsp/fh8620/drivers/gpio.h @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,12 +18,12 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + #ifndef GPIO_H_ #define GPIO_H_ diff --git a/bsp/fh8620/drivers/i2c.c b/bsp/fh8620/drivers/i2c.c index 0f9636853..66931666e 100644 --- a/bsp/fh8620/drivers/i2c.c +++ b/bsp/fh8620/drivers/i2c.c @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,12 +18,12 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + #include #include #include "i2c.h" @@ -50,25 +50,25 @@ static void fh_i2c_xfer_init(struct rt_i2c_bus_device *dev, struct rt_i2c_msg ms { struct i2c_driver *i2c_drv = (struct i2c_driver *)dev->priv; struct fh_i2c_obj *i2c_obj = (struct fh_i2c_obj *)i2c_drv->priv; - rt_uint32_t ic_con; + rt_uint32_t ic_con; - /* if the slave address is ten bit address, ERROR*/ + /* if the slave address is ten bit address, ERROR*/ if (msgs[i2c_drv->msg_write_idx].flags & I2C_M_TEN) { rt_kprintf("ERROR: %s, ten bit address is NOT supported\n", __func__); return; } - /* Disable the adapter */ - I2C_WaitMasterIdle(i2c_obj); + /* Disable the adapter */ + I2C_WaitMasterIdle(i2c_obj); - I2C_Enable(i2c_obj, RT_FALSE); + I2C_Enable(i2c_obj, RT_FALSE); - /* set the slave (target) address */ - I2C_SetSlaveAddress(i2c_obj, msgs[i2c_drv->msg_write_idx].addr); + /* set the slave (target) address */ + I2C_SetSlaveAddress(i2c_obj, msgs[i2c_drv->msg_write_idx].addr); - /* Enable interrupts */ - I2C_SetInterruptMask(i2c_obj, DW_IC_INTR_DEFAULT_MASK); + /* Enable interrupts */ + I2C_SetInterruptMask(i2c_obj, DW_IC_INTR_DEFAULT_MASK); /* Enable the adapter */ I2C_Enable(i2c_obj, RT_TRUE); @@ -76,30 +76,30 @@ static void fh_i2c_xfer_init(struct rt_i2c_bus_device *dev, struct rt_i2c_msg ms static rt_size_t fh_i2c_xfer(struct rt_i2c_bus_device *dev, - struct rt_i2c_msg msgs[], rt_uint32_t num) + struct rt_i2c_msg msgs[], rt_uint32_t num) { struct i2c_driver *i2c_drv = (struct i2c_driver *)dev->priv; struct fh_i2c_obj *i2c_obj = (struct fh_i2c_obj *)i2c_drv->priv; int ret; - struct rt_i2c_msg *pmsg = RT_NULL; + struct rt_i2c_msg *pmsg = RT_NULL; - PRINT_I2C_DBG(">>>>>>>>>>>>>%s start\n", __func__); + PRINT_I2C_DBG(">>>>>>>>>>>>>%s start\n", __func__); rt_completion_init(&i2c_drv->transfer_completion); ret = rt_mutex_take(i2c_drv->lock, RT_WAITING_FOREVER); - if (ret != RT_EOK) { - goto done; - } - - i2c_drv->msgs = msgs; - i2c_drv->msgs_num = num; - i2c_drv->msg_read_idx = 0; - i2c_drv->msg_write_idx = 0; - i2c_drv->cmd_err = 0; - i2c_drv->msg_err = 0; - i2c_drv->status = STATUS_IDLE; - i2c_obj->abort_source = 0; + if (ret != RT_EOK) { + goto done; + } + + i2c_drv->msgs = msgs; + i2c_drv->msgs_num = num; + i2c_drv->msg_read_idx = 0; + i2c_drv->msg_write_idx = 0; + i2c_drv->cmd_err = 0; + i2c_drv->msg_err = 0; + i2c_drv->status = STATUS_IDLE; + i2c_obj->abort_source = 0; ret = I2C_WaitDeviceIdle(i2c_obj); if (ret < 0) @@ -108,51 +108,51 @@ static rt_size_t fh_i2c_xfer(struct rt_i2c_bus_device *dev, //goto done; } - fh_i2c_xfer_init(dev, msgs, num); + fh_i2c_xfer_init(dev, msgs, num); - ret = rt_completion_wait(&i2c_drv->transfer_completion, RT_TICK_PER_SECOND); - PRINT_I2C_DBG("%s transfer finished\n", "rt_completion_wait"); + ret = rt_completion_wait(&i2c_drv->transfer_completion, RT_TICK_PER_SECOND); + PRINT_I2C_DBG("%s transfer finished\n", "rt_completion_wait"); if(ret) - { + { rt_kprintf("ERROR: %s, transfer timeout\n", __func__); I2C_SetDataCmd(i2c_obj, 0x200); I2C_Init(i2c_obj); - ret = -RT_ETIMEOUT; - goto done; - } - - if (i2c_drv->msg_err) - { - rt_kprintf("i2c_priv->msg_err: %d\n", i2c_drv->msg_err); - ret = i2c_drv->msg_err; - goto done; - } - - /* no error */ - if (!i2c_drv->cmd_err) - { - /* Disable the adapter */ - I2C_WaitMasterIdle(i2c_obj); - I2C_Enable(i2c_obj, RT_FALSE); - ret = num; - goto done; - } - - /* We have an error */ - if (i2c_drv->cmd_err == DW_IC_ERR_TX_ABRT) - { - rt_kprintf("ERROR: %s, i2c_priv>cmd_err == DW_IC_ERR_TX_ABRT\n", __func__); - ret = I2C_HandleTxAbort(i2c_obj); - goto done; - } - - ret = 1; + ret = -RT_ETIMEOUT; + goto done; + } + + if (i2c_drv->msg_err) + { + rt_kprintf("i2c_priv->msg_err: %d\n", i2c_drv->msg_err); + ret = i2c_drv->msg_err; + goto done; + } + + /* no error */ + if (!i2c_drv->cmd_err) + { + /* Disable the adapter */ + I2C_WaitMasterIdle(i2c_obj); + I2C_Enable(i2c_obj, RT_FALSE); + ret = num; + goto done; + } + + /* We have an error */ + if (i2c_drv->cmd_err == DW_IC_ERR_TX_ABRT) + { + rt_kprintf("ERROR: %s, i2c_priv>cmd_err == DW_IC_ERR_TX_ABRT\n", __func__); + ret = I2C_HandleTxAbort(i2c_obj); + goto done; + } + + ret = 1; done: I2C_Enable(i2c_obj, RT_FALSE); rt_mutex_release(i2c_drv->lock); PRINT_I2C_DBG(">>>>>>>>>>>>>%s end\n", __func__); - return ret; + return ret; } @@ -167,164 +167,164 @@ static void i2c_fh_xfer_msg(struct rt_i2c_bus_device *dev) { struct i2c_driver *i2c_drv = (struct i2c_driver *)dev->priv; struct fh_i2c_obj *i2c_obj = (struct fh_i2c_obj *)i2c_drv->priv; - struct rt_i2c_msg *msgs = i2c_drv->msgs; - rt_uint32_t intr_mask, cmd; - int tx_limit, rx_limit; - rt_uint32_t addr = msgs[i2c_drv->msg_write_idx].addr; - rt_uint32_t buf_len = i2c_drv->tx_buf_len; - rt_uint8_t *buf = i2c_drv->tx_buf; - - PRINT_I2C_DBG("%s start, msgs_num: %d, write_idx: %d\n", __func__, i2c_drv->msgs_num, i2c_drv->msg_write_idx); - - intr_mask = DW_IC_INTR_DEFAULT_MASK; - - for (; i2c_drv->msg_write_idx < i2c_drv->msgs_num; i2c_drv->msg_write_idx++) - { - /* - * if target address has changed, we need to - * reprogram the target address in the i2c - * adapter when we are done with this transfer - */ - if (msgs[i2c_drv->msg_write_idx].addr != addr) { - rt_kprintf( - "ERROR: %s, invalid target address\n", __func__); - i2c_drv->msg_err = 1; - break; - } - - if (msgs[i2c_drv->msg_write_idx].len == 0) { - rt_kprintf( - "ERROR: %s, invalid message length\n", __func__); - i2c_drv->msg_err = 1; - break; - } - - if (!(i2c_drv->status & STATUS_WRITE_IN_PROGRESS)) - { - /* new i2c_msg */ - buf = msgs[i2c_drv->msg_write_idx].buf; - buf_len = msgs[i2c_drv->msg_write_idx].len; - - PRINT_I2C_DBG("new msg: len: %d, buf: 0x%x\n", buf_len, buf[0]); - } - - tx_limit = i2c_obj->config.tx_fifo_depth - I2C_GetTransmitFifoLevel(i2c_obj); - rx_limit = i2c_obj->config.rx_fifo_depth - I2C_GetReceiveFifoLevel(i2c_obj); - - while (buf_len > 0 && tx_limit > 0 && rx_limit > 0) - { - if (msgs[i2c_drv->msg_write_idx].flags & RT_I2C_RD) - { - cmd = 0x100; - rx_limit--; - } - else - { - cmd = *buf++; - } - - tx_limit--; buf_len--; - - if(!buf_len) - { - //2015-11-8 ar0130 bug fixed - while(I2C_GetTransmitFifoLevel(i2c_obj)); - cmd |= 0x200; - } - - I2C_SetDataCmd(i2c_obj, cmd); - } - - i2c_drv->tx_buf = buf; - i2c_drv->tx_buf_len = buf_len; - - if (buf_len > 0) - { - /* more bytes to be written */ - i2c_drv->status |= STATUS_WRITE_IN_PROGRESS; - break; - } - else - { - i2c_drv->status &= ~STATUS_WRITE_IN_PROGRESS; - } - } - - /* - * If i2c_msg index search is completed, we don't need TX_EMPTY - * interrupt any more. - */ - - if (i2c_drv->msg_write_idx == i2c_drv->msgs_num) - intr_mask &= ~DW_IC_INTR_TX_EMPTY; - - if (i2c_drv->msg_err) - { - rt_kprintf("ERROR: %s, msg_err: %d\n", __func__, i2c_drv->msg_err); - intr_mask = 0; - } - - I2C_SetInterruptMask(i2c_obj, intr_mask); - - PRINT_I2C_DBG("%s end\n", __func__); + struct rt_i2c_msg *msgs = i2c_drv->msgs; + rt_uint32_t intr_mask, cmd; + int tx_limit, rx_limit; + rt_uint32_t addr = msgs[i2c_drv->msg_write_idx].addr; + rt_uint32_t buf_len = i2c_drv->tx_buf_len; + rt_uint8_t *buf = i2c_drv->tx_buf; + + PRINT_I2C_DBG("%s start, msgs_num: %d, write_idx: %d\n", __func__, i2c_drv->msgs_num, i2c_drv->msg_write_idx); + + intr_mask = DW_IC_INTR_DEFAULT_MASK; + + for (; i2c_drv->msg_write_idx < i2c_drv->msgs_num; i2c_drv->msg_write_idx++) + { + /* + * if target address has changed, we need to + * reprogram the target address in the i2c + * adapter when we are done with this transfer + */ + if (msgs[i2c_drv->msg_write_idx].addr != addr) { + rt_kprintf( + "ERROR: %s, invalid target address\n", __func__); + i2c_drv->msg_err = 1; + break; + } + + if (msgs[i2c_drv->msg_write_idx].len == 0) { + rt_kprintf( + "ERROR: %s, invalid message length\n", __func__); + i2c_drv->msg_err = 1; + break; + } + + if (!(i2c_drv->status & STATUS_WRITE_IN_PROGRESS)) + { + /* new i2c_msg */ + buf = msgs[i2c_drv->msg_write_idx].buf; + buf_len = msgs[i2c_drv->msg_write_idx].len; + + PRINT_I2C_DBG("new msg: len: %d, buf: 0x%x\n", buf_len, buf[0]); + } + + tx_limit = i2c_obj->config.tx_fifo_depth - I2C_GetTransmitFifoLevel(i2c_obj); + rx_limit = i2c_obj->config.rx_fifo_depth - I2C_GetReceiveFifoLevel(i2c_obj); + + while (buf_len > 0 && tx_limit > 0 && rx_limit > 0) + { + if (msgs[i2c_drv->msg_write_idx].flags & RT_I2C_RD) + { + cmd = 0x100; + rx_limit--; + } + else + { + cmd = *buf++; + } + + tx_limit--; buf_len--; + + if(!buf_len) + { + //2015-11-8 ar0130 bug fixed + while(I2C_GetTransmitFifoLevel(i2c_obj)); + cmd |= 0x200; + } + + I2C_SetDataCmd(i2c_obj, cmd); + } + + i2c_drv->tx_buf = buf; + i2c_drv->tx_buf_len = buf_len; + + if (buf_len > 0) + { + /* more bytes to be written */ + i2c_drv->status |= STATUS_WRITE_IN_PROGRESS; + break; + } + else + { + i2c_drv->status &= ~STATUS_WRITE_IN_PROGRESS; + } + } + + /* + * If i2c_msg index search is completed, we don't need TX_EMPTY + * interrupt any more. + */ + + if (i2c_drv->msg_write_idx == i2c_drv->msgs_num) + intr_mask &= ~DW_IC_INTR_TX_EMPTY; + + if (i2c_drv->msg_err) + { + rt_kprintf("ERROR: %s, msg_err: %d\n", __func__, i2c_drv->msg_err); + intr_mask = 0; + } + + I2C_SetInterruptMask(i2c_obj, intr_mask); + + PRINT_I2C_DBG("%s end\n", __func__); } static void i2c_fh_read(struct rt_i2c_bus_device *dev) { - struct i2c_driver *i2c_drv = (struct i2c_driver *)dev->priv; - struct fh_i2c_obj *i2c_obj = (struct fh_i2c_obj *)i2c_drv->priv; - struct rt_i2c_msg *msgs = i2c_drv->msgs; - int rx_valid; - - PRINT_I2C_DBG("%s start, msgs_num: %d, read_idx: %d\n", __func__, i2c_drv->msgs_num, i2c_drv->msg_read_idx); - - for (; i2c_drv->msg_read_idx < i2c_drv->msgs_num; i2c_drv->msg_read_idx++) - { - rt_uint32_t len; - rt_uint8_t *buf; - - if (!(msgs[i2c_drv->msg_read_idx].flags & RT_I2C_RD)) - continue; - - if (!(i2c_drv->status & STATUS_READ_IN_PROGRESS)) - { - len = msgs[i2c_drv->msg_read_idx].len; - buf = msgs[i2c_drv->msg_read_idx].buf; - } - else - { - PRINT_I2C_DBG("STATUS_READ_IN_PROGRESS\n"); - len = i2c_drv->rx_buf_len; - buf = i2c_drv->rx_buf; - } - - rx_valid = I2C_GetReceiveFifoLevel(i2c_obj); - - if(rx_valid == 0) - { - rt_kprintf("ERROR: %s, rx_valid == 0\n", __func__); - } - PRINT_I2C_DBG("%s, len=%d, rx_valid=%d\n", __func__, len, rx_valid); - for (; len > 0 && rx_valid > 0; len--, rx_valid--) - { - *buf++ = I2C_GetData(i2c_obj); - } - - PRINT_I2C_DBG("i2c_fh_read, len: %d, buf[0]: 0x%x\n", msgs[i2c_drv->msg_read_idx].len, msgs[i2c_drv->msg_read_idx].buf[0]); - - if (len > 0) - { - PRINT_I2C_DBG("len > 0\n"); - i2c_drv->status |= STATUS_READ_IN_PROGRESS; - i2c_drv->rx_buf_len = len; - i2c_drv->rx_buf = buf; - return; - } - else - i2c_drv->status &= ~STATUS_READ_IN_PROGRESS; - } - - PRINT_I2C_DBG("%s end\n", __func__); + struct i2c_driver *i2c_drv = (struct i2c_driver *)dev->priv; + struct fh_i2c_obj *i2c_obj = (struct fh_i2c_obj *)i2c_drv->priv; + struct rt_i2c_msg *msgs = i2c_drv->msgs; + int rx_valid; + + PRINT_I2C_DBG("%s start, msgs_num: %d, read_idx: %d\n", __func__, i2c_drv->msgs_num, i2c_drv->msg_read_idx); + + for (; i2c_drv->msg_read_idx < i2c_drv->msgs_num; i2c_drv->msg_read_idx++) + { + rt_uint32_t len; + rt_uint8_t *buf; + + if (!(msgs[i2c_drv->msg_read_idx].flags & RT_I2C_RD)) + continue; + + if (!(i2c_drv->status & STATUS_READ_IN_PROGRESS)) + { + len = msgs[i2c_drv->msg_read_idx].len; + buf = msgs[i2c_drv->msg_read_idx].buf; + } + else + { + PRINT_I2C_DBG("STATUS_READ_IN_PROGRESS\n"); + len = i2c_drv->rx_buf_len; + buf = i2c_drv->rx_buf; + } + + rx_valid = I2C_GetReceiveFifoLevel(i2c_obj); + + if(rx_valid == 0) + { + rt_kprintf("ERROR: %s, rx_valid == 0\n", __func__); + } + PRINT_I2C_DBG("%s, len=%d, rx_valid=%d\n", __func__, len, rx_valid); + for (; len > 0 && rx_valid > 0; len--, rx_valid--) + { + *buf++ = I2C_GetData(i2c_obj); + } + + PRINT_I2C_DBG("i2c_fh_read, len: %d, buf[0]: 0x%x\n", msgs[i2c_drv->msg_read_idx].len, msgs[i2c_drv->msg_read_idx].buf[0]); + + if (len > 0) + { + PRINT_I2C_DBG("len > 0\n"); + i2c_drv->status |= STATUS_READ_IN_PROGRESS; + i2c_drv->rx_buf_len = len; + i2c_drv->rx_buf = buf; + return; + } + else + i2c_drv->status &= ~STATUS_READ_IN_PROGRESS; + } + + PRINT_I2C_DBG("%s end\n", __func__); } /* @@ -336,44 +336,44 @@ static void fh_i2c_interrupt(int this_irq, void *dev_id) struct i2c_driver *i2c_drv = dev_id; struct rt_i2c_bus_device *i2c_bus_dev = i2c_drv->i2c_bus_dev; struct fh_i2c_obj *i2c_obj = (struct fh_i2c_obj *)i2c_drv->priv; - rt_uint32_t stat; - - stat = I2C_ClearAndGetInterrupts(i2c_obj); - PRINT_I2C_DBG("status: 0x%x, mask: 0x%x\n", stat, I2C_GetInterruptMask(i2c_obj)); - - if (stat & DW_IC_INTR_TX_ABRT) - { - PRINT_I2C_DBG("DW_IC_INTR_TX_ABRT\n"); - i2c_drv->cmd_err |= DW_IC_ERR_TX_ABRT; - i2c_drv->status = STATUS_IDLE; - - /* - * Anytime TX_ABRT is set, the contents of the tx/rx - * buffers are flushed. Make sure to skip them. - */ - I2C_SetInterruptMask(i2c_obj, 0); - goto tx_aborted; - } - - if (stat & DW_IC_INTR_RX_FULL) - { - i2c_fh_read(i2c_bus_dev); - } - - if (stat & DW_IC_INTR_TX_EMPTY) - { - i2c_fh_xfer_msg(i2c_bus_dev); - } - - /* - * No need to modify or disable the interrupt mask here. - * i2c_fh_xfer_msg() will take care of it according to - * the current transmit status. - */ + rt_uint32_t stat; + + stat = I2C_ClearAndGetInterrupts(i2c_obj); + PRINT_I2C_DBG("status: 0x%x, mask: 0x%x\n", stat, I2C_GetInterruptMask(i2c_obj)); + + if (stat & DW_IC_INTR_TX_ABRT) + { + PRINT_I2C_DBG("DW_IC_INTR_TX_ABRT\n"); + i2c_drv->cmd_err |= DW_IC_ERR_TX_ABRT; + i2c_drv->status = STATUS_IDLE; + + /* + * Anytime TX_ABRT is set, the contents of the tx/rx + * buffers are flushed. Make sure to skip them. + */ + I2C_SetInterruptMask(i2c_obj, 0); + goto tx_aborted; + } + + if (stat & DW_IC_INTR_RX_FULL) + { + i2c_fh_read(i2c_bus_dev); + } + + if (stat & DW_IC_INTR_TX_EMPTY) + { + i2c_fh_xfer_msg(i2c_bus_dev); + } + + /* + * No need to modify or disable the interrupt mask here. + * i2c_fh_xfer_msg() will take care of it according to + * the current transmit status. + */ tx_aborted: - if ((stat & (DW_IC_INTR_TX_ABRT | DW_IC_INTR_STOP_DET)) || i2c_drv->msg_err) - rt_completion_done(&i2c_drv->transfer_completion); + if ((stat & (DW_IC_INTR_TX_ABRT | DW_IC_INTR_STOP_DET)) || i2c_drv->msg_err) + rt_completion_done(&i2c_drv->transfer_completion); } @@ -464,64 +464,64 @@ void rt_hw_i2c_init(void) } static rt_err_t fh_i2c_read_reg(struct rt_i2c_bus_device *fh81_i2c, - rt_uint16_t reg, rt_uint8_t *data) { - struct rt_i2c_msg msg[2]; - rt_uint8_t send_buf[2]; - rt_uint8_t recv_buf[1] = {0}; + rt_uint16_t reg, rt_uint8_t *data) { + struct rt_i2c_msg msg[2]; + rt_uint8_t send_buf[2]; + rt_uint8_t recv_buf[1] = {0}; - PRINT_I2C_DBG("%s start\n", __func__); + PRINT_I2C_DBG("%s start\n", __func__); - // send_buf[0] = ((reg >> 8) & 0xff); - send_buf[0] = (reg & 0xFF); + // send_buf[0] = ((reg >> 8) & 0xff); + send_buf[0] = (reg & 0xFF); - msg[0].addr = 0x51; - msg[0].flags = RT_I2C_WR; - msg[0].len = 1; - msg[0].buf = send_buf; + msg[0].addr = 0x51; + msg[0].flags = RT_I2C_WR; + msg[0].len = 1; + msg[0].buf = send_buf; - msg[1].addr = 0x51; - msg[1].flags = RT_I2C_RD; - msg[1].len = 1; - msg[1].buf = recv_buf; + msg[1].addr = 0x51; + msg[1].flags = RT_I2C_RD; + msg[1].len = 1; + msg[1].buf = recv_buf; - rt_i2c_transfer(fh81_i2c, msg, 2); - *data = recv_buf[0]; - return RT_EOK; + rt_i2c_transfer(fh81_i2c, msg, 2); + *data = recv_buf[0]; + return RT_EOK; } static rt_err_t fh_i2c_write_reg(struct rt_i2c_bus_device *fh81_i2c, - rt_uint16_t reg, rt_uint8_t data) { - struct rt_i2c_msg msg; - rt_uint8_t send_buf[3]; + rt_uint16_t reg, rt_uint8_t data) { + struct rt_i2c_msg msg; + rt_uint8_t send_buf[3]; - PRINT_I2C_DBG("%s start\n", __func__); + PRINT_I2C_DBG("%s start\n", __func__); - // send_buf[0] = ((reg >> 8) & 0xff); - send_buf[1] = (reg & 0xFF); - send_buf[2] = data; + // send_buf[0] = ((reg >> 8) & 0xff); + send_buf[1] = (reg & 0xFF); + send_buf[2] = data; - msg.addr = 0x51; - msg.flags = RT_I2C_WR; - msg.len = 2; - msg.buf = send_buf; + msg.addr = 0x51; + msg.flags = RT_I2C_WR; + msg.len = 2; + msg.buf = send_buf; - rt_i2c_transfer(fh81_i2c, &msg, 1); - PRINT_I2C_DBG("%s end\n", __func__); - return RT_EOK; + rt_i2c_transfer(fh81_i2c, &msg, 1); + PRINT_I2C_DBG("%s end\n", __func__); + return RT_EOK; } void i2c_test_sensor() { - struct rt_i2c_bus_device *fh81_i2c; - struct rt_i2c_msg msg[2]; - rt_uint8_t data[1] = { 0x00 }; + struct rt_i2c_bus_device *fh81_i2c; + struct rt_i2c_msg msg[2]; + rt_uint8_t data[1] = { 0x00 }; - fh81_i2c = rt_i2c_bus_device_find("i2c1"); + fh81_i2c = rt_i2c_bus_device_find("i2c1"); - fh_i2c_write_reg(fh81_i2c, 0x04, 0x02); + fh_i2c_write_reg(fh81_i2c, 0x04, 0x02); - fh_i2c_read_reg(fh81_i2c, 0x02, data); + fh_i2c_read_reg(fh81_i2c, 0x02, data); - rt_kprintf("data read from 0x3038 is 0x%x\r\n", data[0]); - PRINT_I2C_DBG("%s end\n", __func__); + rt_kprintf("data read from 0x3038 is 0x%x\r\n", data[0]); + PRINT_I2C_DBG("%s end\n", __func__); } #ifdef RT_USING_FINSH #include diff --git a/bsp/fh8620/drivers/i2c.h b/bsp/fh8620/drivers/i2c.h index 9046bd81c..15e4d7e8f 100644 --- a/bsp/fh8620/drivers/i2c.h +++ b/bsp/fh8620/drivers/i2c.h @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,7 +18,7 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes diff --git a/bsp/fh8620/drivers/interrupt.c b/bsp/fh8620/drivers/interrupt.c index ab522fab7..4cb250d8e 100644 --- a/bsp/fh8620/drivers/interrupt.c +++ b/bsp/fh8620/drivers/interrupt.c @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,7 +18,7 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes @@ -105,10 +105,10 @@ void rt_hw_interrupt_init(void) { rt_int32_t i; register rt_uint32_t idx; - fh_intc *p = (fh_intc *)INTC_REG_BASE; + fh_intc *p = (fh_intc *)INTC_REG_BASE; - ictl_close_all_isr(p); + ictl_close_all_isr(p); /* init exceptions table */ for(idx=0; idx < MAX_HANDLERS; idx++) { @@ -137,27 +137,27 @@ void rt_hw_interrupt_init(void) void rt_hw_interrupt_mask(int irq) { - fh_intc *p = (fh_intc *)INTC_REG_BASE; + fh_intc *p = (fh_intc *)INTC_REG_BASE; /* Disable irq on AIC */ - ictl_mask_isr(p,irq); + ictl_mask_isr(p,irq); -// if (irq < 32) -// p->IRQ_EN_L &= ~(1 << irq); -// else -// p->IRQ_EN_H &= ~(1 << (irq - 32)); +// if (irq < 32) +// p->IRQ_EN_L &= ~(1 << irq); +// else +// p->IRQ_EN_H &= ~(1 << (irq - 32)); } void rt_hw_interrupt_umask(int irq) { - fh_intc *p = (fh_intc *)INTC_REG_BASE; + fh_intc *p = (fh_intc *)INTC_REG_BASE; /* Enable irq on AIC */ - ictl_unmask_isr(p,irq); + ictl_unmask_isr(p,irq); // if (irq < 32) -// p->IRQ_EN_L |= 1 << irq; -// else -// p->IRQ_EN_H |= 1 << (irq - 32); +// p->IRQ_EN_L |= 1 << irq; +// else +// p->IRQ_EN_H |= 1 << (irq - 32); } /** @@ -168,7 +168,7 @@ void rt_hw_interrupt_umask(int irq) * @param name the interrupt name * @return old handler */ -rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, +rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, void *param, const char *name) { rt_isr_handler_t old_handler = RT_NULL; @@ -182,7 +182,7 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, irq_desc[vector].param = param; #ifdef RT_USING_INTERRUPT_INFO rt_snprintf(irq_desc[vector].name, RT_NAME_MAX - 1, "%s", name); - irq_desc[vector].counter = 0; + irq_desc[vector].counter = 0; #endif } } @@ -195,7 +195,7 @@ void list_irq(void) { #ifdef RT_USING_INTERRUPT_INFO - int irq; + int irq; rt_kprintf("number\tcount\tname\n"); for (irq = 0; irq < MAX_HANDLERS; irq++) { diff --git a/bsp/fh8620/drivers/interrupt.h b/bsp/fh8620/drivers/interrupt.h index fd4283b95..6f62b0d95 100644 --- a/bsp/fh8620/drivers/interrupt.h +++ b/bsp/fh8620/drivers/interrupt.h @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,7 +18,7 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes @@ -35,6 +35,6 @@ void rt_hw_interrupt_init(void); void rt_hw_interrupt_mask(int irq); void rt_hw_interrupt_umask(int irq); rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, - void *param, const char *name); + void *param, const char *name); #endif /* INTERRUPT_H_ */ diff --git a/bsp/fh8620/drivers/mem_process.c b/bsp/fh8620/drivers/mem_process.c index 4ef7e2d59..e1424bd6a 100644 --- a/bsp/fh8620/drivers/mem_process.c +++ b/bsp/fh8620/drivers/mem_process.c @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,7 +18,7 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes @@ -28,52 +28,52 @@ #include #include "mmu.h" -#define CHANGLINE_SIZE (1) +#define CHANGLINE_SIZE (1) //#define FH_DBG_MEM_PROCESS #ifdef FH_DBG_MEM_PROCESS void mem_input(rt_uint32_t t_addr, rt_uint32_t t_size, rt_uint8_t t_value) { - rt_kprintf("mem process add:%x \tsize:%x\tvalue:%x\n", t_addr, t_size, - t_value); + rt_kprintf("mem process add:%x \tsize:%x\tvalue:%x\n", t_addr, t_size, + t_value); - rt_memset((void *) t_addr, t_value, t_size); + rt_memset((void *) t_addr, t_value, t_size); - mmu_clean_invalidated_dcache(t_addr, t_size); + mmu_clean_invalidated_dcache(t_addr, t_size); } void mem_output(rt_uint32_t t_addr, rt_uint32_t t_size) { - rt_uint32_t i; - rt_uint32_t cnt = 0; - rt_uint32_t value; - rt_uint32_t addr, size; + rt_uint32_t i; + rt_uint32_t cnt = 0; + rt_uint32_t value; + rt_uint32_t addr, size; - addr = t_addr; - if (t_size % 4) { - rt_kprintf("mem must be alligned\n"); - } - size = t_size / 4; - rt_int32_t *p = (rt_uint32_t *) t_addr; + addr = t_addr; + if (t_size % 4) { + rt_kprintf("mem must be alligned\n"); + } + size = t_size / 4; + rt_int32_t *p = (rt_uint32_t *) t_addr; - //mmu_clean_invalidated_dcache(addr,t_size); - rt_kprintf("mem process add:0x%x \tsize:0x%x\n", addr, t_size); - rt_kprintf("0x%08x:", addr); - for (i = 0; i < size; i++) { - value = *p++; - if ((cnt / CHANGLINE_SIZE) && (cnt % CHANGLINE_SIZE == 0)) { - rt_kprintf("\n"); - } - if (cnt / CHANGLINE_SIZE && (cnt % CHANGLINE_SIZE) == 0) { - rt_kprintf("0x%08x:", addr + i * 4); - } - rt_kprintf("\t%08x", value); - cnt++; + //mmu_clean_invalidated_dcache(addr,t_size); + rt_kprintf("mem process add:0x%x \tsize:0x%x\n", addr, t_size); + rt_kprintf("0x%08x:", addr); + for (i = 0; i < size; i++) { + value = *p++; + if ((cnt / CHANGLINE_SIZE) && (cnt % CHANGLINE_SIZE == 0)) { + rt_kprintf("\n"); + } + if (cnt / CHANGLINE_SIZE && (cnt % CHANGLINE_SIZE) == 0) { + rt_kprintf("0x%08x:", addr + i * 4); + } + rt_kprintf("\t%08x", value); + cnt++; - } - rt_kprintf("\n"); + } + rt_kprintf("\n"); } #endif diff --git a/bsp/fh8620/drivers/mmc.c b/bsp/fh8620/drivers/mmc.c index 399efd582..1b1097497 100644 --- a/bsp/fh8620/drivers/mmc.c +++ b/bsp/fh8620/drivers/mmc.c @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,7 +18,7 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes diff --git a/bsp/fh8620/drivers/mmc.h b/bsp/fh8620/drivers/mmc.h index 5de1f5643..1a0a6c66d 100644 --- a/bsp/fh8620/drivers/mmc.h +++ b/bsp/fh8620/drivers/mmc.h @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,7 +18,7 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes diff --git a/bsp/fh8620/drivers/pwm.c b/bsp/fh8620/drivers/pwm.c index 58c9703d7..497527a2f 100644 --- a/bsp/fh8620/drivers/pwm.c +++ b/bsp/fh8620/drivers/pwm.c @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,7 +18,7 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes @@ -193,7 +193,7 @@ int fh_pwm_probe(void *priv_data) rt_kprintf("ERROR: %s rt_device calloc failed\n", __func__); return -RT_ENOMEM; } - + pwm_dev->user_data = &pwm_drv; pwm_dev->open =fh_pwm_open; pwm_dev->close = fh_pwm_close; diff --git a/bsp/fh8620/drivers/pwm.h b/bsp/fh8620/drivers/pwm.h index 3693ab797..b40fa89ff 100644 --- a/bsp/fh8620/drivers/pwm.h +++ b/bsp/fh8620/drivers/pwm.h @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,12 +18,12 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + #ifndef PWM_H_ #define PWM_H_ diff --git a/bsp/fh8620/drivers/sadc.c b/bsp/fh8620/drivers/sadc.c index b1654d295..403b92cd7 100644 --- a/bsp/fh8620/drivers/sadc.c +++ b/bsp/fh8620/drivers/sadc.c @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,7 +18,7 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes @@ -50,123 +50,123 @@ -#define __raw_writeb(v,a) ( *(volatile unsigned char *)(a) = (v)) -#define __raw_writew(v,a) ( *(volatile unsigned short *)(a) = (v)) -#define __raw_writel(v,a) ( *(volatile unsigned int *)(a) = (v)) +#define __raw_writeb(v,a) ( *(volatile unsigned char *)(a) = (v)) +#define __raw_writew(v,a) ( *(volatile unsigned short *)(a) = (v)) +#define __raw_writel(v,a) ( *(volatile unsigned int *)(a) = (v)) -#define __raw_readb(a) ( *(volatile unsigned char *)(a)) -#define __raw_readw(a) ( *(volatile unsigned short *)(a)) -#define __raw_readl(a) ( *(volatile unsigned int *)(a)) +#define __raw_readb(a) ( *(volatile unsigned char *)(a)) +#define __raw_readw(a) ( *(volatile unsigned short *)(a)) +#define __raw_readl(a) ( *(volatile unsigned int *)(a)) #define wrap_readl(wrap, name) \ - __raw_readl(&(((struct wrap_sadc_reg *)wrap->regs)->name)) + __raw_readl(&(((struct wrap_sadc_reg *)wrap->regs)->name)) #define wrap_writel(wrap, name, val) \ - __raw_writel((val), &(((struct wrap_sadc_reg *)wrap->regs)->name)) + __raw_writel((val), &(((struct wrap_sadc_reg *)wrap->regs)->name)) #define wrap_readw(wrap, name) \ - __raw_readw(&(((struct wrap_sadc_reg *)wrap->regs)->name)) + __raw_readw(&(((struct wrap_sadc_reg *)wrap->regs)->name)) #define wrap_writew(wrap, name, val) \ - __raw_writew((val), &(((struct wrap_sadc_reg *)wrap->regs)->name)) + __raw_writew((val), &(((struct wrap_sadc_reg *)wrap->regs)->name)) #define wrap_readb(wrap, name) \ - __raw_readb(&(((struct wrap_sadc_reg *)wrap->regs)->name)) + __raw_readb(&(((struct wrap_sadc_reg *)wrap->regs)->name)) #define wrap_writeb(wrap, name, val) \ - __raw_writeb((val), &(((struct wrap_sadc_reg *)wrap->regs)->name)) + __raw_writeb((val), &(((struct wrap_sadc_reg *)wrap->regs)->name)) -#define IOCTL_GET_SADC_DATA 1 -#define IOCTL_SADC_POWER_DOWN 0xff -#define SADC_WRAP_BASE (0xf1200000) -#define SADC_IRQn (23) -#define SADC_MAX_CONTROLLER (1) -#define SADC_STATUS_COLESD (0) -#define SADC_STATUS_OPEN (1) +#define IOCTL_GET_SADC_DATA 1 +#define IOCTL_SADC_POWER_DOWN 0xff +#define SADC_WRAP_BASE (0xf1200000) +#define SADC_IRQn (23) +#define SADC_MAX_CONTROLLER (1) +#define SADC_STATUS_COLESD (0) +#define SADC_STATUS_OPEN (1) rt_err_t fh_sadc_isr_read_data(struct wrap_sadc_obj *sadc, rt_uint32_t channel, - rt_uint16_t *buf) { - rt_uint32_t xainsel = 1 << channel; - rt_uint32_t xversel = 0; - rt_uint32_t xpwdb = 1; - //cnt - rt_uint32_t sel2sam_pre_cnt = 2; - rt_uint32_t sam_cnt = 2; - rt_uint32_t sam2sel_pos_cnt = 2; - //time out - rt_uint32_t eoc_tos = 0xff; - rt_uint32_t eoc_toe = 0xff; - rt_uint32_t time_out = 0xffff; - //set isr en.. - rt_uint32_t sadc_isr = 0x01; - //start - rt_uint32_t sadc_cmd = 0x01; - //get data - rt_uint32_t temp_data = 0; - rt_err_t ret; + rt_uint16_t *buf) { + rt_uint32_t xainsel = 1 << channel; + rt_uint32_t xversel = 0; + rt_uint32_t xpwdb = 1; + //cnt + rt_uint32_t sel2sam_pre_cnt = 2; + rt_uint32_t sam_cnt = 2; + rt_uint32_t sam2sel_pos_cnt = 2; + //time out + rt_uint32_t eoc_tos = 0xff; + rt_uint32_t eoc_toe = 0xff; + rt_uint32_t time_out = 0xffff; + //set isr en.. + rt_uint32_t sadc_isr = 0x01; + //start + rt_uint32_t sadc_cmd = 0x01; + //get data + rt_uint32_t temp_data = 0; + rt_err_t ret; - //control... - wrap_writel(sadc, sadc_control, xainsel | (xversel << 8) | (xpwdb << 12)); + //control... + wrap_writel(sadc, sadc_control, xainsel | (xversel << 8) | (xpwdb << 12)); - wrap_writel(sadc, sadc_cnt, - sel2sam_pre_cnt | (sam_cnt << 8) | (sam2sel_pos_cnt << 16)); + wrap_writel(sadc, sadc_cnt, + sel2sam_pre_cnt | (sam_cnt << 8) | (sam2sel_pos_cnt << 16)); - wrap_writel(sadc, sadc_timeout, - eoc_tos | (eoc_toe << 8) | (time_out << 16)); + wrap_writel(sadc, sadc_timeout, + eoc_tos | (eoc_toe << 8) | (time_out << 16)); - wrap_writel(sadc, sadc_ier, sadc_isr); + wrap_writel(sadc, sadc_ier, sadc_isr); - wrap_writel(sadc, sadc_cmd, sadc_cmd); + wrap_writel(sadc, sadc_cmd, sadc_cmd); // ret = rt_completion_wait(&sadc->completion, RT_TICK_PER_SECOND / 2); - ret = rt_sem_take(&sadc->completion, 5000); - if(ret != RT_EOK) - return ret; - - switch (channel) { - case 0: - case 1: - //read channel 0 1 - temp_data = wrap_readl(sadc, sadc_dout0); - break; - - case 2: - case 3: - //read channel 2 3 - temp_data = wrap_readl(sadc, sadc_dout1); - break; - - case 4: - case 5: - //read channel 4 5 - temp_data = wrap_readl(sadc, sadc_dout2); - break; - - case 6: - case 7: - //read channel 6 7 - temp_data = wrap_readl(sadc, sadc_dout3); - break; - default: - break; - } - if (channel % 2) { - //read low 16bit - *buf = (rt_uint16_t) (temp_data & 0xffff); - } else { - //read high 16bit - *buf = (rt_uint16_t) (temp_data >> 16); - } - return RT_EOK; + ret = rt_sem_take(&sadc->completion, 5000); + if(ret != RT_EOK) + return ret; + + switch (channel) { + case 0: + case 1: + //read channel 0 1 + temp_data = wrap_readl(sadc, sadc_dout0); + break; + + case 2: + case 3: + //read channel 2 3 + temp_data = wrap_readl(sadc, sadc_dout1); + break; + + case 4: + case 5: + //read channel 4 5 + temp_data = wrap_readl(sadc, sadc_dout2); + break; + + case 6: + case 7: + //read channel 6 7 + temp_data = wrap_readl(sadc, sadc_dout3); + break; + default: + break; + } + if (channel % 2) { + //read low 16bit + *buf = (rt_uint16_t) (temp_data & 0xffff); + } else { + //read high 16bit + *buf = (rt_uint16_t) (temp_data >> 16); + } + return RT_EOK; } @@ -204,41 +204,41 @@ static rt_err_t fh_sadc_close(rt_device_t dev) static rt_err_t fh_sadc_ioctl(rt_device_t dev, int cmd, void *arg) { - rt_uint32_t control_reg; - struct wrap_sadc_obj *sadc_pri =(struct wrap_sadc_obj *)dev->user_data; - rt_uint32_t ad_data; - rt_uint16_t ad_raw_data; - - SADC_INFO *sadc_info = (SADC_INFO *)arg; - rt_err_t ret; - switch(cmd){ - case SADC_CMD_READ_RAW_DATA: - ret = fh_sadc_isr_read_data(sadc_pri, sadc_info->channel, &ad_raw_data); - if(ret != RT_EOK) - return ret; - sadc_info->sadc_data = ad_raw_data; - - break; - case SADC_CMD_READ_VOLT: - ret = fh_sadc_isr_read_data(sadc_pri, sadc_info->channel, &ad_raw_data); - if(ret != RT_EOK) - return ret; - - ad_data = ad_raw_data * SADC_REF; - ad_data /= SADC_MAX_AD_VALUE; - sadc_info->sadc_data = ad_data; - - break; - case SADC_CMD_DISABLE: - control_reg = wrap_readl(sadc_pri, sadc_control); - control_reg &= ~(1 << 12); - wrap_writel(sadc_pri, sadc_control, control_reg); - - break; - default : - rt_kprintf("wrong para...\n"); - return RT_EIO; - } + rt_uint32_t control_reg; + struct wrap_sadc_obj *sadc_pri =(struct wrap_sadc_obj *)dev->user_data; + rt_uint32_t ad_data; + rt_uint16_t ad_raw_data; + + SADC_INFO *sadc_info = (SADC_INFO *)arg; + rt_err_t ret; + switch(cmd){ + case SADC_CMD_READ_RAW_DATA: + ret = fh_sadc_isr_read_data(sadc_pri, sadc_info->channel, &ad_raw_data); + if(ret != RT_EOK) + return ret; + sadc_info->sadc_data = ad_raw_data; + + break; + case SADC_CMD_READ_VOLT: + ret = fh_sadc_isr_read_data(sadc_pri, sadc_info->channel, &ad_raw_data); + if(ret != RT_EOK) + return ret; + + ad_data = ad_raw_data * SADC_REF; + ad_data /= SADC_MAX_AD_VALUE; + sadc_info->sadc_data = ad_data; + + break; + case SADC_CMD_DISABLE: + control_reg = wrap_readl(sadc_pri, sadc_control); + control_reg &= ~(1 << 12); + wrap_writel(sadc_pri, sadc_control, control_reg); + + break; + default : + rt_kprintf("wrong para...\n"); + return RT_EIO; + } return RT_EOK; } @@ -249,25 +249,25 @@ static void fh_sadc_interrupt(int irq, void *param) { rt_uint32_t isr_status; - struct wrap_sadc_obj *sadc = (struct wrap_sadc_obj *) param; + struct wrap_sadc_obj *sadc = (struct wrap_sadc_obj *) param; - isr_status = wrap_readl(sadc, sadc_int_status); + isr_status = wrap_readl(sadc, sadc_int_status); - if (isr_status & 0x01) { - //close isr - rt_uint32_t sadc_isr = 0x00; + if (isr_status & 0x01) { + //close isr + rt_uint32_t sadc_isr = 0x00; - wrap_writel(sadc, sadc_ier, sadc_isr); - //clear status.. + wrap_writel(sadc, sadc_ier, sadc_isr); + //clear status.. - wrap_writel(sadc, sadc_int_status, isr_status); + wrap_writel(sadc, sadc_int_status, isr_status); - rt_sem_release(&sadc->completion); - // rt_completion_done(&sadc->completion); - } else { - //add error handle process - rt_kprintf("sadc maybe error!\n"); - } + rt_sem_release(&sadc->completion); + // rt_completion_done(&sadc->completion); + } else { + //add error handle process + rt_kprintf("sadc maybe error!\n"); + } } @@ -282,13 +282,13 @@ int fh_sadc_probe(void *priv_data) //caution this is a read only data...if the driver want to use.malloc and copy it.. struct wrap_sadc_obj *sadc_obj = (struct wrap_sadc_obj *)priv_data; if(sadc_obj->init_flag == SADC_INIT_ALREADY) - return RT_EFULL; + return RT_EFULL; //malloc a rt device.. sadc_dev = RT_KERNEL_MALLOC(sizeof(struct rt_device)); if(!sadc_dev){ - return RT_ENOMEM; + return RT_ENOMEM; } rt_memset(sadc_dev, 0, sizeof(struct rt_device)); PRINT_SADC_DBG("id:%d,\treg:%x,\tirq:%d\n",sadc_obj->id,(rt_uint32_t)sadc_obj->regs,sadc_obj->irq_no); @@ -304,8 +304,8 @@ int fh_sadc_probe(void *priv_data) struct wrap_sadc_obj *sadc_pri = RT_KERNEL_MALLOC(sizeof(struct wrap_sadc_obj)); if(!sadc_pri){ - RT_KERNEL_FREE(sadc_dev); - return RT_ENOMEM; + RT_KERNEL_FREE(sadc_dev); + return RT_ENOMEM; } //copy platform data to pri data.. @@ -349,23 +349,23 @@ int fh_sadc_probe(void *priv_data) int fh_sadc_exit(void *priv_data) { - PRINT_SADC_DBG("%s\n",__func__); - struct wrap_sadc_obj *sadc_obj = (struct wrap_sadc_obj *)priv_data; + PRINT_SADC_DBG("%s\n",__func__); + struct wrap_sadc_obj *sadc_obj = (struct wrap_sadc_obj *)priv_data; - struct wrap_sadc_obj *sadc_pri = sadc_obj->rt_dev->user_data; - //release sem; - rt_sem_detach(&sadc_pri->completion); - //sadc_pri->completion = RT_NULL; + struct wrap_sadc_obj *sadc_pri = sadc_obj->rt_dev->user_data; + //release sem; + rt_sem_detach(&sadc_pri->completion); + //sadc_pri->completion = RT_NULL; - //release lock; - rt_mutex_detach(&sadc_pri->lock); + //release lock; + rt_mutex_detach(&sadc_pri->lock); - RT_KERNEL_FREE(sadc_obj->rt_dev->user_data); + RT_KERNEL_FREE(sadc_obj->rt_dev->user_data); - sadc_obj->rt_dev->user_data = RT_NULL; - RT_KERNEL_FREE(sadc_obj->rt_dev); - sadc_obj->rt_dev = RT_NULL; + sadc_obj->rt_dev->user_data = RT_NULL; + RT_KERNEL_FREE(sadc_obj->rt_dev); + sadc_obj->rt_dev = RT_NULL; return 0; } @@ -386,23 +386,23 @@ void rt_hw_sadc_init(void) #ifdef FH_TEST_SADC int fh_sadc_test(void){ - rt_device_t sadc_dev; - SADC_INFO info; - info.channel = 0; - info.sadc_data = 0; - sadc_dev = rt_device_find("sadc"); - if(!sadc_dev){ - rt_kprintf("cann't find the sadc dev\n"); - } - sadc_dev->init(sadc_dev); - sadc_dev->open(sadc_dev,0); - while(1) - { - sadc_dev->control(sadc_dev,SADC_CMD_READ_VOLT,&info); - rt_kprintf("channel:%d,volt:%dmv\n",info.channel,info.sadc_data); - } - - return 0; + rt_device_t sadc_dev; + SADC_INFO info; + info.channel = 0; + info.sadc_data = 0; + sadc_dev = rt_device_find("sadc"); + if(!sadc_dev){ + rt_kprintf("cann't find the sadc dev\n"); + } + sadc_dev->init(sadc_dev); + sadc_dev->open(sadc_dev,0); + while(1) + { + sadc_dev->control(sadc_dev,SADC_CMD_READ_VOLT,&info); + rt_kprintf("channel:%d,volt:%dmv\n",info.channel,info.sadc_data); + } + + return 0; } #endif diff --git a/bsp/fh8620/drivers/sadc.h b/bsp/fh8620/drivers/sadc.h index d28ed9ba2..afe168bd2 100644 --- a/bsp/fh8620/drivers/sadc.h +++ b/bsp/fh8620/drivers/sadc.h @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,12 +18,12 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + #ifndef SADC_H_ #define SADC_H_ @@ -33,57 +33,57 @@ /**************************************************************************** * #define section - * add constant #define here if any + * add constant #define here if any ***************************************************************************/ //#define FH_SADC_PROC_FILE "driver/sadc" -#define MAX_CHANNEL_NO (8) -#define SADC_REF (3300) -#define SADC_MAX_AD_VALUE (0x3ff) -#define LOOP_MODE (0x55) -#define ISR_MODE (0xAA) +#define MAX_CHANNEL_NO (8) +#define SADC_REF (3300) +#define SADC_MAX_AD_VALUE (0x3ff) +#define LOOP_MODE (0x55) +#define ISR_MODE (0xAA) -#define SADC_INIT_ALREADY (0x33) -#define SADC_INIT_NOT_YET (0) +#define SADC_INIT_ALREADY (0x33) +#define SADC_INIT_NOT_YET (0) -#define SADC_CMD_READ_RAW_DATA (0x22) -#define SADC_CMD_READ_VOLT (0x33) -#define SADC_CMD_DISABLE (0x44) +#define SADC_CMD_READ_RAW_DATA (0x22) +#define SADC_CMD_READ_VOLT (0x33) +#define SADC_CMD_DISABLE (0x44) /**************************************************************************** * ADT section - * add Abstract Data Type definition here + * add Abstract Data Type definition here ***************************************************************************/ struct wrap_sadc_reg { - rt_uint32_t sadc_cmd; - rt_uint32_t sadc_control; - rt_uint32_t sadc_ier; - rt_uint32_t sadc_int_status; - rt_uint32_t sadc_dout0; - rt_uint32_t sadc_dout1; - rt_uint32_t sadc_dout2; - rt_uint32_t sadc_dout3; - rt_uint32_t sadc_debuge0; - rt_uint32_t sadc_status; - rt_uint32_t sadc_cnt; - rt_uint32_t sadc_timeout; + rt_uint32_t sadc_cmd; + rt_uint32_t sadc_control; + rt_uint32_t sadc_ier; + rt_uint32_t sadc_int_status; + rt_uint32_t sadc_dout0; + rt_uint32_t sadc_dout1; + rt_uint32_t sadc_dout2; + rt_uint32_t sadc_dout3; + rt_uint32_t sadc_debuge0; + rt_uint32_t sadc_status; + rt_uint32_t sadc_cnt; + rt_uint32_t sadc_timeout; }; struct wrap_sadc_obj { - rt_uint32_t id; - void *regs; - rt_uint32_t irq_no; - rt_uint32_t init_flag; - rt_uint32_t active_channel_no; - rt_uint32_t active_channel_status; - rt_uint16_t channel_data[MAX_CHANNEL_NO]; - rt_uint32_t error_rec; - rt_uint32_t en_isr; - rt_uint32_t sample_mode; - struct rt_mutex lock; - struct rt_semaphore completion; + rt_uint32_t id; + void *regs; + rt_uint32_t irq_no; + rt_uint32_t init_flag; + rt_uint32_t active_channel_no; + rt_uint32_t active_channel_status; + rt_uint16_t channel_data[MAX_CHANNEL_NO]; + rt_uint32_t error_rec; + rt_uint32_t en_isr; + rt_uint32_t sample_mode; + struct rt_mutex lock; + struct rt_semaphore completion; //bind to the rtdev.. rt_device_t rt_dev; @@ -91,8 +91,8 @@ struct wrap_sadc_obj { }; typedef struct{ - rt_uint32_t channel; - rt_uint32_t sadc_data; + rt_uint32_t channel; + rt_uint32_t sadc_data; }SADC_INFO; @@ -102,7 +102,7 @@ typedef struct{ /**************************************************************************** * section - * add function prototype here if any + * add function prototype here if any ***************************************************************************/ void rt_hw_sadc_init(void); #endif diff --git a/bsp/fh8620/drivers/spi_fh_adapt.c b/bsp/fh8620/drivers/spi_fh_adapt.c index 291fe9a4f..437b30d1c 100644 --- a/bsp/fh8620/drivers/spi_fh_adapt.c +++ b/bsp/fh8620/drivers/spi_fh_adapt.c @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,12 +18,12 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + /* * spi_fh_adapt.c * @@ -60,9 +60,9 @@ #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) -#define WX_MANU_ID 0xEF +#define WX_MANU_ID 0xEF #define AT_MANU_ID 0x1F /* atmel */ -#define SST_MANU_ID 0xBF +#define SST_MANU_ID 0xBF #define GD_MANU_ID 0xC8 @@ -70,50 +70,50 @@ #define SPI_ADAPT_DEBUG #ifdef SPI_ADAPT_DEBUG -#define CMD_JEDEC_ID 0x9f +#define CMD_JEDEC_ID 0x9f -#define FH_SPI_ADAPT_DEBUG(fmt, args...) \ - rt_kprintf(fmt,##args); +#define FH_SPI_ADAPT_DEBUG(fmt, args...) \ + rt_kprintf(fmt,##args); #else #define FH_SPI_ADAPT_DEBUG(fmt, args...) #endif struct fh_flash_id{ - unsigned char id; - rt_err_t (*fh_flash_init)(struct flash_platform_data *plat_flash); - char *name; + unsigned char id; + rt_err_t (*fh_flash_init)(struct flash_platform_data *plat_flash); + char *name; }; const struct fh_flash_id id_map[] = { #ifdef RT_USING_W25QXX - WX_MANU_ID,w25qxx_init,"winbond", + WX_MANU_ID,w25qxx_init,"winbond", #endif #ifdef RT_USING_AT45DBXX - AT_MANU_ID,at45dbxx_init,"atmel", + AT_MANU_ID,at45dbxx_init,"atmel", #endif #ifdef RT_USING_SST25VFXX - SST_MANU_ID,sst25vfxx_init,"SST", + SST_MANU_ID,sst25vfxx_init,"SST", #endif #ifdef RT_USING_GD - GD_MANU_ID,gd_init,"GD", + GD_MANU_ID,gd_init,"GD", #endif }; struct fh_flash_id * fh_flash_check_id_map(unsigned char id){ - struct fh_flash_id *p_map = RT_NULL; - unsigned int i; - for (i = 0; i < ARRAY_SIZE(id_map); i++) { - p_map = (struct fh_flash_id *)&id_map[i]; - if (p_map->id == id){ - return p_map; - } - } - return RT_NULL; + struct fh_flash_id *p_map = RT_NULL; + unsigned int i; + for (i = 0; i < ARRAY_SIZE(id_map); i++) { + p_map = (struct fh_flash_id *)&id_map[i]; + if (p_map->id == id){ + return p_map; + } + } + return RT_NULL; } @@ -144,50 +144,50 @@ int fh_flash_adapt_probe(void *priv_data) /* init flash */ - rt_uint8_t cmd; - rt_uint8_t id_recv[3]; - uint16_t memory_type_capacity; - rt_err_t ret; - - cmd = 0xFF; /* reset SPI FLASH, cancel all cmd in processing. */ - rt_spi_send(rt_spi_device, &cmd, 1); - /* read flash id */ - cmd = CMD_JEDEC_ID; - rt_spi_send_then_recv(rt_spi_device, &cmd, 1, id_recv, 3); - - //if the flash is already connect. - if(id_recv[0] != 0xff){ - flash_model =fh_flash_check_id_map(id_recv[0]); - if(flash_model){ - ret = flash_model->fh_flash_init(plat_flash); - if(ret != RT_EOK){ - rt_kprintf("flash:%s init error\n",flash_model->name); - rt_kprintf("use default flash ops..\n"); - //flash_model->fh_flash_adapt_init =flash_default_init; - ret = flash_default_init(plat_flash); - } - } - else{ - rt_kprintf( - "use default flash ops...\nunrecognized flash id is :%02X %02X %02X\n", - id_recv[0], id_recv[1], id_recv[2]); - ret = flash_default_init(plat_flash); - - } - - int i; - for(i=0; inr_parts; i++) - { - fh_spi_partition_register(plat_flash->flash_name, &plat_flash->parts[i]); - } - - return ret; - - } - else{ - rt_kprintf("please check if you connect the flash already...\n"); - return RT_ENOSYS; - } + rt_uint8_t cmd; + rt_uint8_t id_recv[3]; + uint16_t memory_type_capacity; + rt_err_t ret; + + cmd = 0xFF; /* reset SPI FLASH, cancel all cmd in processing. */ + rt_spi_send(rt_spi_device, &cmd, 1); + /* read flash id */ + cmd = CMD_JEDEC_ID; + rt_spi_send_then_recv(rt_spi_device, &cmd, 1, id_recv, 3); + + //if the flash is already connect. + if(id_recv[0] != 0xff){ + flash_model =fh_flash_check_id_map(id_recv[0]); + if(flash_model){ + ret = flash_model->fh_flash_init(plat_flash); + if(ret != RT_EOK){ + rt_kprintf("flash:%s init error\n",flash_model->name); + rt_kprintf("use default flash ops..\n"); + //flash_model->fh_flash_adapt_init =flash_default_init; + ret = flash_default_init(plat_flash); + } + } + else{ + rt_kprintf( + "use default flash ops...\nunrecognized flash id is :%02X %02X %02X\n", + id_recv[0], id_recv[1], id_recv[2]); + ret = flash_default_init(plat_flash); + + } + + int i; + for(i=0; inr_parts; i++) + { + fh_spi_partition_register(plat_flash->flash_name, &plat_flash->parts[i]); + } + + return ret; + + } + else{ + rt_kprintf("please check if you connect the flash already...\n"); + return RT_ENOSYS; + } } diff --git a/bsp/fh8620/drivers/spi_fh_adapt.h b/bsp/fh8620/drivers/spi_fh_adapt.h index 171fdf718..3e3cc365a 100644 --- a/bsp/fh8620/drivers/spi_fh_adapt.h +++ b/bsp/fh8620/drivers/spi_fh_adapt.h @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,12 +18,12 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + /* * spi_fh_adapt.h * diff --git a/bsp/fh8620/drivers/ssi.c b/bsp/fh8620/drivers/ssi.c index e5cb99042..c87a4352a 100644 --- a/bsp/fh8620/drivers/ssi.c +++ b/bsp/fh8620/drivers/ssi.c @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,12 +18,12 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + #include #include #include "fh_arch.h" @@ -49,20 +49,20 @@ #endif -#define RX_DMA_CHANNEL AUTO_FIND_CHANNEL -#define TX_DMA_CHANNEL AUTO_FIND_CHANNEL +#define RX_DMA_CHANNEL AUTO_FIND_CHANNEL +#define TX_DMA_CHANNEL AUTO_FIND_CHANNEL -#define DMA_OR_ISR_THRESHOLD 20 -#define MALLOC_DMA_MEM_SIZE 0x1000 +#define DMA_OR_ISR_THRESHOLD 20 +#define MALLOC_DMA_MEM_SIZE 0x1000 //static rt_uint32_t allign_func(rt_uint32_t in_addr,rt_uint32_t allign_size){ -// return (in_addr + allign_size-1) & (~(allign_size - 1)); +// return (in_addr + allign_size-1) & (~(allign_size - 1)); //} void * fh_get_spi_dev_pri_data(struct rt_spi_device* device){ - return device->parent.user_data; + return device->parent.user_data; } static rt_err_t fh_spi_configure(struct rt_spi_device* device, @@ -87,54 +87,54 @@ static rt_err_t fh_spi_configure(struct rt_spi_device* device, PRINT_SPI_DBG("\tmax_hz: 0x%x\n", configuration->max_hz); do{ - status = SPI_ReadStatus(spi_obj); - } + status = SPI_ReadStatus(spi_obj); + } while(status & SPI_STATUS_BUSY); - /* data_width */ - if(configuration->data_width <= 8){ - config->data_size = SPI_DATA_SIZE_8BIT; - } - else if(configuration->data_width <= 16){ - config->data_size = SPI_DATA_SIZE_16BIT; - } - else{ - return -RT_ERROR; - } - - if(configuration->max_hz > spi_control->max_hz) - spi_hz = spi_control->max_hz; - else - spi_hz = configuration->max_hz; - - //fixme: div - config->clk_div = spi_control->clk_in/spi_hz; - //config->clk_div = 8; - PRINT_SPI_DBG("config hz:%d spi div:%d\n",spi_hz,config->clk_div); - /* CPOL */ - if(configuration->mode & RT_SPI_CPOL){ - config->clk_polarity = SPI_POLARITY_HIGH; - } - else{ - config->clk_polarity = SPI_POLARITY_LOW; - } - - /* CPHA */ - if(configuration->mode & RT_SPI_CPHA){ - config->clk_phase = SPI_PHASE_TX_FIRST; - } - else{ - config->clk_phase = SPI_PHASE_RX_FIRST; - } - - config->frame_format = SPI_FORMAT_MOTOROLA; - config->transfer_mode = SPI_MODE_TX_RX; - - SPI_Enable(spi_obj, 0); - SPI_SetParameter(spi_obj); - SPI_DisableInterrupt(spi_obj, SPI_IRQ_ALL); - SPI_Enable(spi_obj, 1); + /* data_width */ + if(configuration->data_width <= 8){ + config->data_size = SPI_DATA_SIZE_8BIT; + } + else if(configuration->data_width <= 16){ + config->data_size = SPI_DATA_SIZE_16BIT; + } + else{ + return -RT_ERROR; + } + + if(configuration->max_hz > spi_control->max_hz) + spi_hz = spi_control->max_hz; + else + spi_hz = configuration->max_hz; + + //fixme: div + config->clk_div = spi_control->clk_in/spi_hz; + //config->clk_div = 8; + PRINT_SPI_DBG("config hz:%d spi div:%d\n",spi_hz,config->clk_div); + /* CPOL */ + if(configuration->mode & RT_SPI_CPOL){ + config->clk_polarity = SPI_POLARITY_HIGH; + } + else{ + config->clk_polarity = SPI_POLARITY_LOW; + } + + /* CPHA */ + if(configuration->mode & RT_SPI_CPHA){ + config->clk_phase = SPI_PHASE_TX_FIRST; + } + else{ + config->clk_phase = SPI_PHASE_RX_FIRST; + } + + config->frame_format = SPI_FORMAT_MOTOROLA; + config->transfer_mode = SPI_MODE_TX_RX; + + SPI_Enable(spi_obj, 0); + SPI_SetParameter(spi_obj); + SPI_DisableInterrupt(spi_obj, SPI_IRQ_ALL); + SPI_Enable(spi_obj, 1); return RT_EOK; } @@ -142,8 +142,8 @@ static rt_err_t fh_spi_configure(struct rt_spi_device* device, static void xfer_dma_done(void *arg) { - struct spi_controller *spi_control = (struct spi_controller *)arg; - spi_control->dma_complete_times++; + struct spi_controller *spi_control = (struct spi_controller *)arg; + spi_control->dma_complete_times++; struct fh_spi_obj *spi_obj; int ret; @@ -151,72 +151,72 @@ static void xfer_dma_done(void *arg) spi_obj = &spi_control->obj; - //rt_kprintf("spi dma isr done.....\n"); - if (spi_control->dma_complete_times == 2) { - spi_control->dma_complete_times = 0; + //rt_kprintf("spi dma isr done.....\n"); + if (spi_control->dma_complete_times == 2) { + spi_control->dma_complete_times = 0; - //add memcpy to user buff - if(spi_control->current_message->recv_buf){ - rt_memcpy((void*)spi_control->current_message->recv_buf,(void*)spi_control->dma.rx_dummy_buff,spi_control->current_message->length); - } + //add memcpy to user buff + if(spi_control->current_message->recv_buf){ + rt_memcpy((void*)spi_control->current_message->recv_buf,(void*)spi_control->dma.rx_dummy_buff,spi_control->current_message->length); + } - SPI_Enable(spi_obj,0); - SPI_DisableDma(spi_obj,SPI_TX_DMA|SPI_RX_DMA); - SPI_Enable(spi_obj,1); + SPI_Enable(spi_obj,0); + SPI_DisableDma(spi_obj,SPI_TX_DMA|SPI_RX_DMA); + SPI_Enable(spi_obj,1); - rt_completion_done(&spi_control->transfer_completion); - } + rt_completion_done(&spi_control->transfer_completion); + } } void dma_set_tx_data(struct spi_controller *spi_control){ - struct dma_transfer *trans; - rt_uint32_t hs_no; - struct rt_spi_message* current_message = spi_control->current_message; - trans = &spi_control->dma.tx_trans; - hs_no = spi_control->dma.tx_hs; + struct dma_transfer *trans; + rt_uint32_t hs_no; + struct rt_spi_message* current_message = spi_control->current_message; + trans = &spi_control->dma.tx_trans; + hs_no = spi_control->dma.tx_hs; - struct fh_spi_obj *spi_obj; - spi_obj = &spi_control->obj; + struct fh_spi_obj *spi_obj; + spi_obj = &spi_control->obj; - if(current_message->length > MALLOC_DMA_MEM_SIZE){ - rt_kprintf("[spi_dma]message len too large..\n"); - rt_kprintf("[spi_dma] message len is %d,max len is %d\n",current_message->length,MALLOC_DMA_MEM_SIZE); - RT_ASSERT(current_message->length <= MALLOC_DMA_MEM_SIZE); - } + if(current_message->length > MALLOC_DMA_MEM_SIZE){ + rt_kprintf("[spi_dma]message len too large..\n"); + rt_kprintf("[spi_dma] message len is %d,max len is %d\n",current_message->length,MALLOC_DMA_MEM_SIZE); + RT_ASSERT(current_message->length <= MALLOC_DMA_MEM_SIZE); + } - rt_memset((void*)spi_control->dma.tx_dummy_buff,0xff,current_message->length); - //copy tx data.... - if(current_message->send_buf){ - rt_memcpy(spi_control->dma.tx_dummy_buff,current_message->send_buf,current_message->length); - } + rt_memset((void*)spi_control->dma.tx_dummy_buff,0xff,current_message->length); + //copy tx data.... + if(current_message->send_buf){ + rt_memcpy(spi_control->dma.tx_dummy_buff,current_message->send_buf,current_message->length); + } - trans->dma_number = 0; - trans->dst_add = (rt_uint32_t)(spi_obj->base + OFFSET_SPI_DR); + trans->dma_number = 0; + trans->dst_add = (rt_uint32_t)(spi_obj->base + OFFSET_SPI_DR); - trans->dst_hs = DMA_HW_HANDSHAKING; - trans->dst_inc_mode = DW_DMA_SLAVE_FIX; - trans->dst_msize = DW_DMA_SLAVE_MSIZE_1; - trans->dst_per = hs_no; - trans->dst_width = DW_DMA_SLAVE_WIDTH_8BIT; - trans->fc_mode = DMA_M2P; + trans->dst_hs = DMA_HW_HANDSHAKING; + trans->dst_inc_mode = DW_DMA_SLAVE_FIX; + trans->dst_msize = DW_DMA_SLAVE_MSIZE_1; + trans->dst_per = hs_no; + trans->dst_width = DW_DMA_SLAVE_WIDTH_8BIT; + trans->fc_mode = DMA_M2P; - trans->src_add = (rt_uint32_t)spi_control->dma.tx_dummy_buff; + trans->src_add = (rt_uint32_t)spi_control->dma.tx_dummy_buff; - trans->src_inc_mode = DW_DMA_SLAVE_INC; - trans->src_msize = DW_DMA_SLAVE_MSIZE_1; + trans->src_inc_mode = DW_DMA_SLAVE_INC; + trans->src_msize = DW_DMA_SLAVE_MSIZE_1; - trans->src_width = DW_DMA_SLAVE_WIDTH_8BIT; - trans->trans_len = current_message->length; + trans->src_width = DW_DMA_SLAVE_WIDTH_8BIT; + trans->trans_len = current_message->length; - trans->complete_callback = (void *)xfer_dma_done; - trans->complete_para = (void *)spi_control; + trans->complete_callback = (void *)xfer_dma_done; + trans->complete_para = (void *)spi_control; @@ -225,153 +225,153 @@ void dma_set_tx_data(struct spi_controller *spi_control){ void dma_set_rx_data(struct spi_controller *spi_control){ - struct dma_transfer *trans; - rt_uint32_t hs_no; - struct rt_spi_message* current_message = spi_control->current_message; - trans = &spi_control->dma.rx_trans; - hs_no = spi_control->dma.rx_hs; + struct dma_transfer *trans; + rt_uint32_t hs_no; + struct rt_spi_message* current_message = spi_control->current_message; + trans = &spi_control->dma.rx_trans; + hs_no = spi_control->dma.rx_hs; - struct fh_spi_obj *spi_obj; - spi_obj = &spi_control->obj; + struct fh_spi_obj *spi_obj; + spi_obj = &spi_control->obj; - if(current_message->length > MALLOC_DMA_MEM_SIZE){ - rt_kprintf("[spi_dma]message len too large..len is %d\n",current_message->length); - RT_ASSERT(current_message->length <= MALLOC_DMA_MEM_SIZE); - } + if(current_message->length > MALLOC_DMA_MEM_SIZE){ + rt_kprintf("[spi_dma]message len too large..len is %d\n",current_message->length); + RT_ASSERT(current_message->length <= MALLOC_DMA_MEM_SIZE); + } - //rt_memset((void *)spi_control->dma.rx_dummy_buff,0,MALLOC_DMA_MEM_SIZE); + //rt_memset((void *)spi_control->dma.rx_dummy_buff,0,MALLOC_DMA_MEM_SIZE); - trans->dma_number = 0; - trans->fc_mode = DMA_P2M; + trans->dma_number = 0; + trans->fc_mode = DMA_P2M; - trans->dst_add = (rt_uint32_t)spi_control->dma.rx_dummy_buff; - trans->dst_inc_mode = DW_DMA_SLAVE_INC; - trans->dst_msize = DW_DMA_SLAVE_MSIZE_1; - trans->dst_width = DW_DMA_SLAVE_WIDTH_8BIT; + trans->dst_add = (rt_uint32_t)spi_control->dma.rx_dummy_buff; + trans->dst_inc_mode = DW_DMA_SLAVE_INC; + trans->dst_msize = DW_DMA_SLAVE_MSIZE_1; + trans->dst_width = DW_DMA_SLAVE_WIDTH_8BIT; - trans->src_add = (rt_uint32_t)(spi_obj->base + OFFSET_SPI_DR); - trans->src_inc_mode = DW_DMA_SLAVE_FIX; - trans->src_msize = DW_DMA_SLAVE_MSIZE_1; - trans->src_width = DW_DMA_SLAVE_WIDTH_8BIT; - trans->src_hs = DMA_HW_HANDSHAKING; - trans->src_per = hs_no; - trans->trans_len = current_message->length; + trans->src_add = (rt_uint32_t)(spi_obj->base + OFFSET_SPI_DR); + trans->src_inc_mode = DW_DMA_SLAVE_FIX; + trans->src_msize = DW_DMA_SLAVE_MSIZE_1; + trans->src_width = DW_DMA_SLAVE_WIDTH_8BIT; + trans->src_hs = DMA_HW_HANDSHAKING; + trans->src_per = hs_no; + trans->trans_len = current_message->length; - trans->complete_callback = (void *)xfer_dma_done; - trans->complete_para = (void *)spi_control; + trans->complete_callback = (void *)xfer_dma_done; + trans->complete_para = (void *)spi_control; } rt_uint32_t xfer_data_dma(struct spi_controller *spi_control){ - int ret; + int ret; - struct fh_spi_obj *spi_obj; - spi_obj = &spi_control->obj; + struct fh_spi_obj *spi_obj; + spi_obj = &spi_control->obj; - struct rt_dma_device *dma_dev = spi_control->dma.dma_dev; + struct rt_dma_device *dma_dev = spi_control->dma.dma_dev; - //tx data prepare - dma_set_tx_data(spi_control); - //rx data prepare - dma_set_rx_data(spi_control); - //dma go... + //tx data prepare + dma_set_tx_data(spi_control); + //rx data prepare + dma_set_rx_data(spi_control); + //dma go... - SPI_Enable(spi_obj,0); + SPI_Enable(spi_obj,0); - //SPI_WriteTxDmaLevel(spi_obj,SPI_FIFO_DEPTH / 4); - SPI_WriteTxDmaLevel(spi_obj,1); - //SPI_WriteTxDmaLevel(spi_obj,0); - SPI_WriteRxDmaLevel(spi_obj,0); - SPI_EnableDma(spi_obj,SPI_TX_DMA|SPI_RX_DMA); - SPI_Enable(spi_obj,1); + //SPI_WriteTxDmaLevel(spi_obj,SPI_FIFO_DEPTH / 4); + SPI_WriteTxDmaLevel(spi_obj,1); + //SPI_WriteTxDmaLevel(spi_obj,0); + SPI_WriteRxDmaLevel(spi_obj,0); + SPI_EnableDma(spi_obj,SPI_TX_DMA|SPI_RX_DMA); + SPI_Enable(spi_obj,1); - dma_dev->ops->control(dma_dev,RT_DEVICE_CTRL_DMA_SINGLE_TRANSFER,(void *)&spi_control->dma.rx_trans); - dma_dev->ops->control(dma_dev,RT_DEVICE_CTRL_DMA_SINGLE_TRANSFER,(void *)&spi_control->dma.tx_trans); + dma_dev->ops->control(dma_dev,RT_DEVICE_CTRL_DMA_SINGLE_TRANSFER,(void *)&spi_control->dma.rx_trans); + dma_dev->ops->control(dma_dev,RT_DEVICE_CTRL_DMA_SINGLE_TRANSFER,(void *)&spi_control->dma.tx_trans); - ret = rt_completion_wait(&spi_control->transfer_completion, RT_TICK_PER_SECOND*50); - //release channel.. + ret = rt_completion_wait(&spi_control->transfer_completion, RT_TICK_PER_SECOND*50); + //release channel.. - //dma_dev->ops->control(dma_dev,RT_DEVICE_CTRL_DMA_RELEASE_CHANNEL,(void *)&spi_control->dma.tx_trans); - //dma_dev->ops->control(dma_dev,RT_DEVICE_CTRL_DMA_RELEASE_CHANNEL,(void *)&spi_control->dma.rx_trans); + //dma_dev->ops->control(dma_dev,RT_DEVICE_CTRL_DMA_RELEASE_CHANNEL,(void *)&spi_control->dma.tx_trans); + //dma_dev->ops->control(dma_dev,RT_DEVICE_CTRL_DMA_RELEASE_CHANNEL,(void *)&spi_control->dma.rx_trans); - if(ret) - { - rt_kprintf("ERROR: %s, transfer timeout\n", __func__); - return -RT_ETIMEOUT; - } + if(ret) + { + rt_kprintf("ERROR: %s, transfer timeout\n", __func__); + return -RT_ETIMEOUT; + } - return RT_EOK; + return RT_EOK; } rt_uint32_t xfer_data_isr(struct spi_controller *spi_control){ - int ret; - struct fh_spi_obj *spi_obj; - spi_obj = &spi_control->obj; + int ret; + struct fh_spi_obj *spi_obj; + spi_obj = &spi_control->obj; SPI_SetTxLevel(spi_obj, SPI_FIFO_DEPTH / 2); SPI_EnableInterrupt(spi_obj, SPI_IRQ_TXEIM); - ret = rt_completion_wait(&spi_control->transfer_completion, RT_TICK_PER_SECOND*50); - if(ret) - { - rt_kprintf("ERROR: %s, transfer timeout\n", __func__); - return -RT_ETIMEOUT; - } - - return RT_EOK; + ret = rt_completion_wait(&spi_control->transfer_completion, RT_TICK_PER_SECOND*50); + if(ret) + { + rt_kprintf("ERROR: %s, transfer timeout\n", __func__); + return -RT_ETIMEOUT; + } + + return RT_EOK; } void fix_spi_xfer_mode(struct spi_controller *spi_control){ - //switch dma or isr....first check dma ...is error .use isr xfer... - struct rt_dma_device * rt_dma_dev; - struct dma_transfer *tx_trans; - struct dma_transfer *rx_trans; - int ret; - //retry to check if the dma status... - if(spi_control->dma.dma_flag == DMA_BIND_OK){ - //if transfer data too short...use isr.. - if(spi_control->current_message->length < DMA_OR_ISR_THRESHOLD){ - spi_control->xfer_mode = XFER_USE_ISR; - return; - } + //switch dma or isr....first check dma ...is error .use isr xfer... + struct rt_dma_device * rt_dma_dev; + struct dma_transfer *tx_trans; + struct dma_transfer *rx_trans; + int ret; + //retry to check if the dma status... + if(spi_control->dma.dma_flag == DMA_BIND_OK){ + //if transfer data too short...use isr.. + if(spi_control->current_message->length < DMA_OR_ISR_THRESHOLD){ + spi_control->xfer_mode = XFER_USE_ISR; + return; + } #if(0) - rt_dma_dev = spi_control->dma.dma_dev; - //first request channel - - tx_trans = &spi_control->dma.tx_trans; - rx_trans = &spi_control->dma.rx_trans; - tx_trans->channel_number = TX_DMA_CHANNEL; - rx_trans->channel_number = RX_DMA_CHANNEL; - - - ret = rt_dma_dev->ops->control(rt_dma_dev,RT_DEVICE_CTRL_DMA_REQUEST_CHANNEL,(void *)tx_trans); - if(ret != RT_EOK){ - spi_control->xfer_mode = XFER_USE_ISR; - return; - } - - ret = rt_dma_dev->ops->control(rt_dma_dev,RT_DEVICE_CTRL_DMA_REQUEST_CHANNEL,(void *)rx_trans); - if(ret != RT_EOK){ - //release tx channel... - rt_dma_dev->ops->control(rt_dma_dev,RT_DEVICE_CTRL_DMA_RELEASE_CHANNEL,(void *)&tx_trans); - spi_control->xfer_mode = XFER_USE_ISR; - return; - } + rt_dma_dev = spi_control->dma.dma_dev; + //first request channel + + tx_trans = &spi_control->dma.tx_trans; + rx_trans = &spi_control->dma.rx_trans; + tx_trans->channel_number = TX_DMA_CHANNEL; + rx_trans->channel_number = RX_DMA_CHANNEL; + + + ret = rt_dma_dev->ops->control(rt_dma_dev,RT_DEVICE_CTRL_DMA_REQUEST_CHANNEL,(void *)tx_trans); + if(ret != RT_EOK){ + spi_control->xfer_mode = XFER_USE_ISR; + return; + } + + ret = rt_dma_dev->ops->control(rt_dma_dev,RT_DEVICE_CTRL_DMA_REQUEST_CHANNEL,(void *)rx_trans); + if(ret != RT_EOK){ + //release tx channel... + rt_dma_dev->ops->control(rt_dma_dev,RT_DEVICE_CTRL_DMA_RELEASE_CHANNEL,(void *)&tx_trans); + spi_control->xfer_mode = XFER_USE_ISR; + return; + } #endif - spi_control->xfer_mode = XFER_USE_DMA; - //if error use isr mode - } - else - spi_control->xfer_mode = XFER_USE_ISR; + spi_control->xfer_mode = XFER_USE_DMA; + //if error use isr mode + } + else + spi_control->xfer_mode = XFER_USE_ISR; @@ -392,7 +392,7 @@ static rt_uint32_t fh_spi_xfer(struct rt_spi_device* device, struct rt_spi_messa spi_control->transfered_len = 0; spi_control->received_len = 0; - rt_sem_take(&spi_control->xfer_lock, RT_WAITING_FOREVER); + rt_sem_take(&spi_control->xfer_lock, RT_WAITING_FOREVER); rt_completion_init(&spi_control->transfer_completion); @@ -400,52 +400,52 @@ static rt_uint32_t fh_spi_xfer(struct rt_spi_device* device, struct rt_spi_messa /* take CS */ if(message->cs_take) { - if(spi_slave->plat_slave.actice_level == ACTIVE_LOW) - gpio_direction_output(spi_slave->plat_slave.cs_pin, 0); - else - gpio_direction_output(spi_slave->plat_slave.cs_pin, 1); + if(spi_slave->plat_slave.actice_level == ACTIVE_LOW) + gpio_direction_output(spi_slave->plat_slave.cs_pin, 0); + else + gpio_direction_output(spi_slave->plat_slave.cs_pin, 1); - //here will always use the slave_0 because that the cs is gpio... - SPI_EnableSlaveen(spi_obj, 0); + //here will always use the slave_0 because that the cs is gpio... + SPI_EnableSlaveen(spi_obj, 0); } //fix transfer mode ..... fix_spi_xfer_mode(spi_control); - switch(spi_control->xfer_mode){ - case XFER_USE_DMA: - PRINT_SPI_DBG("use dma xfer.....###############\n"); - ret = xfer_data_dma(spi_control); - if(ret == RT_EOK){ - break; - } - else{ - //use the isr mode to transfer - spi_control->xfer_mode = XFER_USE_ISR; - rt_kprintf("%s dma transfer error no:%x\n",__func__,ret); - } - case XFER_USE_ISR: - PRINT_SPI_DBG("use isr xfer.....&&&&&&&&&&&&&\n"); - ret = xfer_data_isr(spi_control); - if(ret != RT_EOK) - rt_kprintf("%s isr transfer error no:%x\n",__func__,ret); - break; - - default: - rt_kprintf("%s unknow xfer func...\n",__func__); - while(1) - ; - } + switch(spi_control->xfer_mode){ + case XFER_USE_DMA: + PRINT_SPI_DBG("use dma xfer.....###############\n"); + ret = xfer_data_dma(spi_control); + if(ret == RT_EOK){ + break; + } + else{ + //use the isr mode to transfer + spi_control->xfer_mode = XFER_USE_ISR; + rt_kprintf("%s dma transfer error no:%x\n",__func__,ret); + } + case XFER_USE_ISR: + PRINT_SPI_DBG("use isr xfer.....&&&&&&&&&&&&&\n"); + ret = xfer_data_isr(spi_control); + if(ret != RT_EOK) + rt_kprintf("%s isr transfer error no:%x\n",__func__,ret); + break; + + default: + rt_kprintf("%s unknow xfer func...\n",__func__); + while(1) + ; + } /* release CS */ if(message->cs_release) { - if(spi_slave->plat_slave.actice_level == ACTIVE_LOW) - gpio_direction_output(spi_slave->plat_slave.cs_pin, 1); - else - gpio_direction_output(spi_slave->plat_slave.cs_pin, 0); - SPI_DisableSlaveen(spi_obj, 0); + if(spi_slave->plat_slave.actice_level == ACTIVE_LOW) + gpio_direction_output(spi_slave->plat_slave.cs_pin, 1); + else + gpio_direction_output(spi_slave->plat_slave.cs_pin, 0); + SPI_DisableSlaveen(spi_obj, 0); } rt_sem_release(&spi_control->xfer_lock); @@ -479,73 +479,73 @@ static void fh_spi_interrupt(int irq, void *param) // - if(spi_control->current_message == RT_NULL){ - rt_kprintf("ERROR: %s, current_message is incorrect\n", __func__); - } - - status = SPI_InterruptStatus(spi_obj); - PRINT_SPI_DBG("status: 0x%x\n", status); - //fixme: ??recv overflow, underflow; tran overflow?? - if(status & SPI_ISR_ERROR){ - rt_kprintf("ERROR: %s, status=%d\n", __func__, status); - SPI_ClearInterrupt(spi_obj); - //fixme: handle error - return; - } - - rx_fifo_capability = SPI_ReadRxFifoLevel(spi_obj); - tx_fifo_capability = MIN( - (SPI_FIFO_DEPTH - SPI_ReadTxFifoLevel(spi_obj)) / 2, - (spi_control->current_message->length - spi_control->transfered_len)); - - - PRINT_SPI_DBG("rx_fifo_capability=%d\n", rx_fifo_capability); - - //rx - spi_control->received_len += rx_fifo_capability; - while(rx_fifo_capability) - { - data = SPI_ReadData(spi_obj); - if(spi_control->current_message->recv_buf){ - *(rt_uint8_t *)spi_control->current_message->recv_buf++ = data; - } - PRINT_SPI_DBG("rx, data: 0x%x\n", data); - //rt_kprintf("rx, data: 0x%x\n", data); - rx_fifo_capability--; - } - - if(spi_control->received_len == spi_control->current_message->length) - { - - //rt_kprintf("asdasdq4902834908dklfkldjsdhgkljshfgljkhsgfkljhsdfkljghklj"); - SPI_DisableInterrupt(spi_obj, SPI_ISR_FLAG); - PRINT_SPI_DBG("finished, length=%d, received_len=%d\n", spi_control->current_message->length, spi_control->received_len); - rt_completion_done(&spi_control->transfer_completion); - - - return; - } - - //tx - - spi_control->transfered_len +=tx_fifo_capability; - if(spi_control->current_message->send_buf){ - p = (rt_uint8_t *)spi_control->current_message->send_buf; - while(tx_fifo_capability){ - PRINT_SPI_DBG("tx, data: 0x%x\n", *p); - //rt_kprintf("tx, data: 0x%x\n", *p); - SPI_WriteData(spi_obj, *p++); - tx_fifo_capability--; - } - spi_control->current_message->send_buf = p; - } - else{ - while(tx_fifo_capability){ - - SPI_WriteData(spi_obj, 0xff); - tx_fifo_capability--; - } - } + if(spi_control->current_message == RT_NULL){ + rt_kprintf("ERROR: %s, current_message is incorrect\n", __func__); + } + + status = SPI_InterruptStatus(spi_obj); + PRINT_SPI_DBG("status: 0x%x\n", status); + //fixme: ??recv overflow, underflow; tran overflow?? + if(status & SPI_ISR_ERROR){ + rt_kprintf("ERROR: %s, status=%d\n", __func__, status); + SPI_ClearInterrupt(spi_obj); + //fixme: handle error + return; + } + + rx_fifo_capability = SPI_ReadRxFifoLevel(spi_obj); + tx_fifo_capability = MIN( + (SPI_FIFO_DEPTH - SPI_ReadTxFifoLevel(spi_obj)) / 2, + (spi_control->current_message->length - spi_control->transfered_len)); + + + PRINT_SPI_DBG("rx_fifo_capability=%d\n", rx_fifo_capability); + + //rx + spi_control->received_len += rx_fifo_capability; + while(rx_fifo_capability) + { + data = SPI_ReadData(spi_obj); + if(spi_control->current_message->recv_buf){ + *(rt_uint8_t *)spi_control->current_message->recv_buf++ = data; + } + PRINT_SPI_DBG("rx, data: 0x%x\n", data); + //rt_kprintf("rx, data: 0x%x\n", data); + rx_fifo_capability--; + } + + if(spi_control->received_len == spi_control->current_message->length) + { + + //rt_kprintf("asdasdq4902834908dklfkldjsdhgkljshfgljkhsgfkljhsdfkljghklj"); + SPI_DisableInterrupt(spi_obj, SPI_ISR_FLAG); + PRINT_SPI_DBG("finished, length=%d, received_len=%d\n", spi_control->current_message->length, spi_control->received_len); + rt_completion_done(&spi_control->transfer_completion); + + + return; + } + + //tx + + spi_control->transfered_len +=tx_fifo_capability; + if(spi_control->current_message->send_buf){ + p = (rt_uint8_t *)spi_control->current_message->send_buf; + while(tx_fifo_capability){ + PRINT_SPI_DBG("tx, data: 0x%x\n", *p); + //rt_kprintf("tx, data: 0x%x\n", *p); + SPI_WriteData(spi_obj, *p++); + tx_fifo_capability--; + } + spi_control->current_message->send_buf = p; + } + else{ + while(tx_fifo_capability){ + + SPI_WriteData(spi_obj, 0xff); + tx_fifo_capability--; + } + } @@ -568,28 +568,28 @@ int fh_spi_probe(void *priv_data) struct spi_control_platform_data *plat_data; int i,ret; - struct rt_dma_device * rt_dma_dev; - struct dma_transfer *tx_trans; - struct dma_transfer *rx_trans; + struct rt_dma_device * rt_dma_dev; + struct dma_transfer *tx_trans; + struct dma_transfer *rx_trans; //check data... plat_data = (struct spi_control_platform_data *)priv_data; if(!plat_data){ - rt_kprintf("ERROR:platform data null...\n"); - return -RT_ENOMEM; + rt_kprintf("ERROR:platform data null...\n"); + return -RT_ENOMEM; } if(plat_data->slave_no > FH_SPI_SLAVE_MAX_NO){ - rt_kprintf("ERROR:spi controller not support %d slave..\n",plat_data->slave_no); - return -RT_ENOMEM; + rt_kprintf("ERROR:spi controller not support %d slave..\n",plat_data->slave_no); + return -RT_ENOMEM; } //malloc data spi_control = (struct spi_controller*)rt_malloc(sizeof(struct spi_controller)); if(!spi_control){ - rt_kprintf("ERROR:no mem for malloc the spi controller..\n"); - goto error_malloc_bus; + rt_kprintf("ERROR:no mem for malloc the spi controller..\n"); + goto error_malloc_bus; } rt_memset(spi_control, 0, sizeof(struct spi_controller)); @@ -624,77 +624,77 @@ int fh_spi_probe(void *priv_data) if(plat_data->transfer_mode == USE_DMA_TRANSFER){ spi_control->dma.dma_dev = (struct rt_dma_device *)rt_device_find(plat_data->dma_name); - if(spi_control->dma.dma_dev == RT_NULL){ - rt_kprintf("can't find dma dev\n"); - //goto error_malloc_slave; - //spi_control->dma_xfer_flag = USE_ISR_TRANSFER; -// spi_control->dma.dma_flag = DMA_BIND_ERROR; -// spi_control->xfer_mode = XFER_USE_ISR; - goto BIND_DMA_ERROR; - } - else{ - - spi_control->dma.control = spi_control; - spi_control->dma.rx_hs = plat_data->rx_hs_no; - spi_control->dma.tx_hs = plat_data->tx_hs_no; - spi_control->dma.dma_name = plat_data->dma_name; - - spi_control->dma.rx_dummy_buff = fh_dma_mem_malloc(MALLOC_DMA_MEM_SIZE); - if(!spi_control->dma.rx_dummy_buff){ - rt_kprintf("malloc rx dma buff failed...\n"); - //spi_control->xfer_mode = XFER_USE_ISR; - goto BIND_DMA_ERROR; - } - - - - spi_control->dma.tx_dummy_buff = fh_dma_mem_malloc(MALLOC_DMA_MEM_SIZE); - if(!spi_control->dma.tx_dummy_buff){ - rt_kprintf("malloc tx dma buff failed...\n"); - fh_dma_mem_free(spi_control->dma.rx_dummy_buff); - //spi_control->xfer_mode = XFER_USE_ISR; - goto BIND_DMA_ERROR; - } - - if(((rt_uint32_t)spi_control->dma.tx_dummy_buff % 4)||((rt_uint32_t)spi_control->dma.rx_dummy_buff % 4)){ - rt_kprintf("dma malloc buff not allign..\n"); - fh_dma_mem_free(spi_control->dma.rx_dummy_buff); - fh_dma_mem_free(spi_control->dma.tx_dummy_buff); - goto BIND_DMA_ERROR; - } - - //open dma dev. - spi_control->dma.dma_dev->ops->control(spi_control->dma.dma_dev,RT_DEVICE_CTRL_DMA_OPEN,RT_NULL); - - //request channel - rt_dma_dev = spi_control->dma.dma_dev; - //first request channel - tx_trans = &spi_control->dma.tx_trans; - rx_trans = &spi_control->dma.rx_trans; - tx_trans->channel_number = TX_DMA_CHANNEL; - rx_trans->channel_number = RX_DMA_CHANNEL; - - ret = rt_dma_dev->ops->control(rt_dma_dev,RT_DEVICE_CTRL_DMA_REQUEST_CHANNEL,(void *)tx_trans); - if(ret != RT_EOK){ - goto BIND_DMA_ERROR; - } - - ret = rt_dma_dev->ops->control(rt_dma_dev,RT_DEVICE_CTRL_DMA_REQUEST_CHANNEL,(void *)rx_trans); - if(ret != RT_EOK){ - //release tx channel... - rt_dma_dev->ops->control(rt_dma_dev,RT_DEVICE_CTRL_DMA_RELEASE_CHANNEL,(void *)&tx_trans); - goto BIND_DMA_ERROR; - } - - //spi_control->xfer_mode = XFER_USE_DMA; - spi_control->dma.dma_flag = DMA_BIND_OK; - } + if(spi_control->dma.dma_dev == RT_NULL){ + rt_kprintf("can't find dma dev\n"); + //goto error_malloc_slave; + //spi_control->dma_xfer_flag = USE_ISR_TRANSFER; +// spi_control->dma.dma_flag = DMA_BIND_ERROR; +// spi_control->xfer_mode = XFER_USE_ISR; + goto BIND_DMA_ERROR; + } + else{ + + spi_control->dma.control = spi_control; + spi_control->dma.rx_hs = plat_data->rx_hs_no; + spi_control->dma.tx_hs = plat_data->tx_hs_no; + spi_control->dma.dma_name = plat_data->dma_name; + + spi_control->dma.rx_dummy_buff = fh_dma_mem_malloc(MALLOC_DMA_MEM_SIZE); + if(!spi_control->dma.rx_dummy_buff){ + rt_kprintf("malloc rx dma buff failed...\n"); + //spi_control->xfer_mode = XFER_USE_ISR; + goto BIND_DMA_ERROR; + } + + + + spi_control->dma.tx_dummy_buff = fh_dma_mem_malloc(MALLOC_DMA_MEM_SIZE); + if(!spi_control->dma.tx_dummy_buff){ + rt_kprintf("malloc tx dma buff failed...\n"); + fh_dma_mem_free(spi_control->dma.rx_dummy_buff); + //spi_control->xfer_mode = XFER_USE_ISR; + goto BIND_DMA_ERROR; + } + + if(((rt_uint32_t)spi_control->dma.tx_dummy_buff % 4)||((rt_uint32_t)spi_control->dma.rx_dummy_buff % 4)){ + rt_kprintf("dma malloc buff not allign..\n"); + fh_dma_mem_free(spi_control->dma.rx_dummy_buff); + fh_dma_mem_free(spi_control->dma.tx_dummy_buff); + goto BIND_DMA_ERROR; + } + + //open dma dev. + spi_control->dma.dma_dev->ops->control(spi_control->dma.dma_dev,RT_DEVICE_CTRL_DMA_OPEN,RT_NULL); + + //request channel + rt_dma_dev = spi_control->dma.dma_dev; + //first request channel + tx_trans = &spi_control->dma.tx_trans; + rx_trans = &spi_control->dma.rx_trans; + tx_trans->channel_number = TX_DMA_CHANNEL; + rx_trans->channel_number = RX_DMA_CHANNEL; + + ret = rt_dma_dev->ops->control(rt_dma_dev,RT_DEVICE_CTRL_DMA_REQUEST_CHANNEL,(void *)tx_trans); + if(ret != RT_EOK){ + goto BIND_DMA_ERROR; + } + + ret = rt_dma_dev->ops->control(rt_dma_dev,RT_DEVICE_CTRL_DMA_REQUEST_CHANNEL,(void *)rx_trans); + if(ret != RT_EOK){ + //release tx channel... + rt_dma_dev->ops->control(rt_dma_dev,RT_DEVICE_CTRL_DMA_RELEASE_CHANNEL,(void *)&tx_trans); + goto BIND_DMA_ERROR; + } + + //spi_control->xfer_mode = XFER_USE_DMA; + spi_control->dma.dma_flag = DMA_BIND_OK; + } } else{ BIND_DMA_ERROR: - spi_control->dma.dma_flag = DMA_BIND_ERROR; - //spi_control->xfer_mode = XFER_USE_ISR; + spi_control->dma.dma_flag = DMA_BIND_ERROR; + //spi_control->xfer_mode = XFER_USE_ISR; } @@ -702,80 +702,80 @@ BIND_DMA_ERROR: control_slave = &spi_control->spi_slave; for(i=0;islave_no;i++){ - spi_slave = (struct spi_slave_info*)rt_malloc(sizeof(struct spi_slave_info)); - if(!spi_slave){ - rt_kprintf("ERROR:no mem for malloc the spi_slave%d..\n",i); - goto error_malloc_slave; - } - rt_memset(spi_slave, 0, sizeof(struct spi_slave_info)); + spi_slave = (struct spi_slave_info*)rt_malloc(sizeof(struct spi_slave_info)); + if(!spi_slave){ + rt_kprintf("ERROR:no mem for malloc the spi_slave%d..\n",i); + goto error_malloc_slave; + } + rt_memset(spi_slave, 0, sizeof(struct spi_slave_info)); + + //parse platform data... + spi_slave->id = i; + //bind to the spi control....will easy to find all the data... + spi_slave->control = spi_control; + spi_slave->plat_slave.cs_pin = plat_data->plat_slave[i].cs_pin; + spi_slave->plat_slave.actice_level = plat_data->plat_slave[i].actice_level; + rt_sprintf(spi_dev_name, "%s%d%s%d", "ssi", spi_control->id,"_",spi_slave->id); + + *control_slave = spi_slave; + control_slave = &spi_slave->next; + + //register slave dev... + ret = rt_spi_bus_attach_device(&spi_slave->spi_device,spi_dev_name,spi_bus_name,spi_slave); + if(ret != RT_EOK){ + rt_kprintf("register dev to bus failed...\n"); + goto error_malloc_slave; + } - //parse platform data... - spi_slave->id = i; - //bind to the spi control....will easy to find all the data... - spi_slave->control = spi_control; - spi_slave->plat_slave.cs_pin = plat_data->plat_slave[i].cs_pin; - spi_slave->plat_slave.actice_level = plat_data->plat_slave[i].actice_level; - rt_sprintf(spi_dev_name, "%s%d%s%d", "ssi", spi_control->id,"_",spi_slave->id); + } - *control_slave = spi_slave; - control_slave = &spi_slave->next; - //register slave dev... - ret = rt_spi_bus_attach_device(&spi_slave->spi_device,spi_dev_name,spi_bus_name,spi_slave); - if(ret != RT_EOK){ - rt_kprintf("register dev to bus failed...\n"); - goto error_malloc_slave; - } - } + //request gpio... + spi_slave = spi_control->spi_slave; + while(spi_slave != RT_NULL) + { + next_slave = spi_slave->next; + ret = gpio_request(spi_slave->plat_slave.cs_pin); + if(ret!=0){ + rt_kprintf("request gpio_%d failed...\n",spi_slave->plat_slave.cs_pin); + goto error_malloc_slave; + } - //request gpio... - spi_slave = spi_control->spi_slave; - while(spi_slave != RT_NULL) - { - next_slave = spi_slave->next; - - ret = gpio_request(spi_slave->plat_slave.cs_pin); - if(ret!=0){ - rt_kprintf("request gpio_%d failed...\n",spi_slave->plat_slave.cs_pin); - goto error_malloc_slave; - } - - - PRINT_SPI_DBG("spi_slave info addr:%x,id:%d,cs:%d,active:%d\n",(rt_uint32_t)spi_slave, spi_slave->id, - spi_slave->plat_slave.cs_pin, - spi_slave->plat_slave.actice_level); - spi_slave = next_slave; - } - - //this will be used in platform exit.. - plat_data->control = spi_control; + PRINT_SPI_DBG("spi_slave info addr:%x,id:%d,cs:%d,active:%d\n",(rt_uint32_t)spi_slave, spi_slave->id, + spi_slave->plat_slave.cs_pin, + spi_slave->plat_slave.actice_level); + spi_slave = next_slave; + } + + //this will be used in platform exit.. + plat_data->control = spi_control; return RT_EOK; error_malloc_slave: - //free the slaveinfo already malloc - spi_slave = spi_control->spi_slave; - while(spi_slave != RT_NULL) - { - next_slave = spi_slave->next; - gpio_release(spi_slave->plat_slave.cs_pin); - rt_free(spi_slave); - spi_slave = next_slave; - } - //mask isr - rt_hw_interrupt_mask(spi_control->irq); - //release sem .. - rt_sem_detach(&spi_control->xfer_lock); - - //free the control malloc . - rt_free(spi_control); - - //fixme:unregister spi_bus... + //free the slaveinfo already malloc + spi_slave = spi_control->spi_slave; + while(spi_slave != RT_NULL) + { + next_slave = spi_slave->next; + gpio_release(spi_slave->plat_slave.cs_pin); + rt_free(spi_slave); + spi_slave = next_slave; + } + //mask isr + rt_hw_interrupt_mask(spi_control->irq); + //release sem .. + rt_sem_detach(&spi_control->xfer_lock); + + //free the control malloc . + rt_free(spi_control); + + //fixme:unregister spi_bus... error_malloc_bus: - return -RT_ENOMEM; + return -RT_ENOMEM; @@ -793,22 +793,22 @@ int fh_spi_exit(void *priv_data) plat_data = (struct spi_control_platform_data *)priv_data; spi_control = plat_data->control; - spi_slave = spi_control->spi_slave; - - while(spi_slave != RT_NULL) - { - next_slave = spi_slave->next; - gpio_release(spi_slave->plat_slave.cs_pin); - rt_free(spi_slave); - spi_slave = next_slave; - } - //mask isr - rt_hw_interrupt_mask(spi_control->irq); - //release sem .. - rt_sem_detach(&spi_control->xfer_lock); - - //free the control malloc . - rt_free(spi_control); + spi_slave = spi_control->spi_slave; + + while(spi_slave != RT_NULL) + { + next_slave = spi_slave->next; + gpio_release(spi_slave->plat_slave.cs_pin); + rt_free(spi_slave); + spi_slave = next_slave; + } + //mask isr + rt_hw_interrupt_mask(spi_control->irq); + //release sem .. + rt_sem_detach(&spi_control->xfer_lock); + + //free the control malloc . + rt_free(spi_control); //fixme free all the malloc data ... return 0; @@ -835,20 +835,20 @@ void rt_hw_spi_init(void) } #if(0) -#define TEST_SPI_BUFF_SIZE 0x100 +#define TEST_SPI_BUFF_SIZE 0x100 static rt_uint8_t tx_buf[TEST_SPI_BUFF_SIZE] = {0}; static rt_uint8_t rx_buf[TEST_SPI_BUFF_SIZE] = {0}; int ssi_test(void){ - struct rt_spi_device * rt_spi_device; + struct rt_spi_device * rt_spi_device; - int ret; - rt_spi_device = (struct rt_spi_device *)rt_device_find("ssi1_0"); + int ret; + rt_spi_device = (struct rt_spi_device *)rt_device_find("ssi1_0"); - if(rt_spi_device == RT_NULL) - { - rt_kprintf("%s spi device %s not found!\r\n",__func__ ,"ssi1_0"); - return -RT_ENOSYS; - } + if(rt_spi_device == RT_NULL) + { + rt_kprintf("%s spi device %s not found!\r\n",__func__ ,"ssi1_0"); + return -RT_ENOSYS; + } /* config spi */ { @@ -865,7 +865,7 @@ int ssi_test(void){ ret = rt_memcmp(tx_buf,rx_buf,TEST_SPI_BUFF_SIZE); if(ret != 0){ - rt_kprintf("compare error ..error data %x\n",ret); + rt_kprintf("compare error ..error data %x\n",ret); } rt_kprintf("test done \n"); return 0; diff --git a/bsp/fh8620/drivers/ssi.h b/bsp/fh8620/drivers/ssi.h index 3559729ca..bad2df838 100644 --- a/bsp/fh8620/drivers/ssi.h +++ b/bsp/fh8620/drivers/ssi.h @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,12 +18,12 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + #ifndef SSI_H_ #define SSI_H_ #include "libraries/inc/fh_driverlib.h" @@ -32,37 +32,37 @@ #include "fh_dma.h" #define SPI_PRIV(drv) ( (struct fh_spi_obj)(drv->priv) ) -#define FH_SPI_SLAVE_MAX_NO 2 +#define FH_SPI_SLAVE_MAX_NO 2 struct spi_controller; //platform use below struct spi_slave_platform_data{ - rt_uint32_t cs_pin; -#define ACTIVE_LOW 1 -#define ACTIVE_HIGH 2 - rt_uint32_t actice_level; + rt_uint32_t cs_pin; +#define ACTIVE_LOW 1 +#define ACTIVE_HIGH 2 + rt_uint32_t actice_level; }; struct spi_control_platform_data{ - rt_uint32_t id; - rt_uint32_t irq; - rt_uint32_t base; - rt_uint32_t max_hz; - rt_uint32_t slave_no; - rt_uint32_t clk_in; - //handshake no... - rt_uint32_t rx_hs_no; - rt_uint32_t tx_hs_no; - - char *dma_name; - //isr will be the default... -#define USE_ISR_TRANSFER 0 -#define USE_DMA_TRANSFER 1 - rt_uint32_t transfer_mode; - struct spi_controller *control; - struct spi_slave_platform_data plat_slave[FH_SPI_SLAVE_MAX_NO]; + rt_uint32_t id; + rt_uint32_t irq; + rt_uint32_t base; + rt_uint32_t max_hz; + rt_uint32_t slave_no; + rt_uint32_t clk_in; + //handshake no... + rt_uint32_t rx_hs_no; + rt_uint32_t tx_hs_no; + + char *dma_name; + //isr will be the default... +#define USE_ISR_TRANSFER 0 +#define USE_DMA_TRANSFER 1 + rt_uint32_t transfer_mode; + struct spi_controller *control; + struct spi_slave_platform_data plat_slave[FH_SPI_SLAVE_MAX_NO]; }; @@ -81,15 +81,15 @@ struct spi_slave_info struct spi_dma { - char *dma_name; -#define DMA_BIND_OK 0 -#define DMA_BIND_ERROR 1 - rt_uint32_t dma_flag; + char *dma_name; +#define DMA_BIND_OK 0 +#define DMA_BIND_ERROR 1 + rt_uint32_t dma_flag; //bind to the dma dev.. - rt_uint32_t rx_hs; - rt_uint32_t tx_hs; - rt_uint8_t *rx_dummy_buff; - rt_uint8_t *tx_dummy_buff; + rt_uint32_t rx_hs; + rt_uint32_t tx_hs; + rt_uint8_t *rx_dummy_buff; + rt_uint8_t *tx_dummy_buff; struct rt_dma_device *dma_dev; struct dma_transfer tx_trans; struct dma_transfer rx_trans; @@ -98,28 +98,28 @@ struct spi_dma struct spi_controller { - rt_uint32_t id; - rt_uint32_t irq; - rt_uint32_t base; - rt_uint32_t max_hz; - rt_uint32_t slave_no; - rt_uint32_t clk_in; - //bind to the platform data.... - struct spi_control_platform_data *plat_data; - - //rt_uint32_t dma_xfer_flag; - -#define XFER_USE_ISR 0 -#define XFER_USE_DMA 1 - rt_uint32_t xfer_mode; - - struct spi_dma dma; - rt_uint32_t dma_complete_times; + rt_uint32_t id; + rt_uint32_t irq; + rt_uint32_t base; + rt_uint32_t max_hz; + rt_uint32_t slave_no; + rt_uint32_t clk_in; + //bind to the platform data.... + struct spi_control_platform_data *plat_data; + + //rt_uint32_t dma_xfer_flag; + +#define XFER_USE_ISR 0 +#define XFER_USE_DMA 1 + rt_uint32_t xfer_mode; + + struct spi_dma dma; + rt_uint32_t dma_complete_times; struct rt_spi_bus spi_bus; struct spi_slave_info *spi_slave; struct rt_spi_message* current_message; struct rt_completion transfer_completion; - struct rt_semaphore xfer_lock; + struct rt_semaphore xfer_lock; struct fh_spi_obj obj; rt_uint32_t received_len; rt_uint32_t transfered_len; diff --git a/bsp/fh8620/drivers/trap.c b/bsp/fh8620/drivers/trap.c index 7d8105795..b12004918 100644 --- a/bsp/fh8620/drivers/trap.c +++ b/bsp/fh8620/drivers/trap.c @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,12 +18,12 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + #include #include #include "fh_arch.h" @@ -47,13 +47,13 @@ extern long list_thread(void); void rt_hw_show_register (struct rt_hw_register *regs) { - rt_kprintf("Execption:\n"); - rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3); - rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7); - rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10); - rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip); - rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc); - rt_kprintf("cpsr:0x%08x\n", regs->cpsr); + rt_kprintf("Execption:\n"); + rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3); + rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7); + rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10); + rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip); + rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc); + rt_kprintf("cpsr:0x%08x\n", regs->cpsr); } /** @@ -66,15 +66,15 @@ void rt_hw_show_register (struct rt_hw_register *regs) */ void rt_hw_trap_udef(struct rt_hw_register *regs) { - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("undefined instruction\n"); - rt_kprintf("thread - %s stack:\n", rt_current_thread->name); + rt_kprintf("undefined instruction\n"); + rt_kprintf("thread - %s stack:\n", rt_current_thread->name); #ifdef RT_USING_FINSH - list_thread(); + list_thread(); #endif - rt_hw_cpu_shutdown(); + rt_hw_cpu_shutdown(); } /** @@ -88,10 +88,10 @@ void rt_hw_trap_udef(struct rt_hw_register *regs) */ void rt_hw_trap_swi(struct rt_hw_register *regs) { - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("software interrupt\n"); - rt_hw_cpu_shutdown(); + rt_kprintf("software interrupt\n"); + rt_hw_cpu_shutdown(); } /** @@ -104,15 +104,15 @@ void rt_hw_trap_swi(struct rt_hw_register *regs) */ void rt_hw_trap_pabt(struct rt_hw_register *regs) { - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("prefetch abort\n"); - rt_kprintf("thread - %s stack:\n", rt_current_thread->name); + rt_kprintf("prefetch abort\n"); + rt_kprintf("thread - %s stack:\n", rt_current_thread->name); #ifdef RT_USING_FINSH - list_thread(); + list_thread(); #endif - rt_hw_cpu_shutdown(); + rt_hw_cpu_shutdown(); } /** @@ -125,15 +125,15 @@ void rt_hw_trap_pabt(struct rt_hw_register *regs) */ void rt_hw_trap_dabt(struct rt_hw_register *regs) { - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("data abort\n"); - rt_kprintf("thread - %s stack:\n", rt_current_thread->name); + rt_kprintf("data abort\n"); + rt_kprintf("thread - %s stack:\n", rt_current_thread->name); #ifdef RT_USING_FINSH - list_thread(); + list_thread(); #endif - rt_hw_cpu_shutdown(); + rt_hw_cpu_shutdown(); } /** @@ -145,45 +145,45 @@ void rt_hw_trap_dabt(struct rt_hw_register *regs) */ void rt_hw_trap_resv(struct rt_hw_register *regs) { - rt_kprintf("not used\n"); - rt_hw_show_register(regs); - rt_hw_cpu_shutdown(); + rt_kprintf("not used\n"); + rt_hw_show_register(regs); + rt_hw_cpu_shutdown(); } extern struct rt_irq_desc irq_desc[]; void rt_hw_trap_irq() { - rt_isr_handler_t isr_func; - rt_uint32_t irqstat_l, irqstat_h, irq; - void *param; - - fh_intc *p = (fh_intc *)INTC_REG_BASE; - - irqstat_l = p->IRQ_FINALSTATUS_L; - irqstat_h = p->IRQ_FINALSTATUS_H; - if (irqstat_l) - { - irq = __rt_ffs(irqstat_l) - 1; - } - else if(irqstat_h) - { - irq = __rt_ffs(irqstat_h) - 1 + 32; - } - else - { - rt_kprintf("No interrupt occur\n"); - return; - } - - /* get interrupt service routine */ - isr_func = irq_desc[irq].handler; - param = irq_desc[irq].param; - - /* turn to interrupt service routine */ - if(isr_func){ - isr_func(irq, param); - } + rt_isr_handler_t isr_func; + rt_uint32_t irqstat_l, irqstat_h, irq; + void *param; + + fh_intc *p = (fh_intc *)INTC_REG_BASE; + + irqstat_l = p->IRQ_FINALSTATUS_L; + irqstat_h = p->IRQ_FINALSTATUS_H; + if (irqstat_l) + { + irq = __rt_ffs(irqstat_l) - 1; + } + else if(irqstat_h) + { + irq = __rt_ffs(irqstat_h) - 1 + 32; + } + else + { + rt_kprintf("No interrupt occur\n"); + return; + } + + /* get interrupt service routine */ + isr_func = irq_desc[irq].handler; + param = irq_desc[irq].param; + + /* turn to interrupt service routine */ + if(isr_func){ + isr_func(irq, param); + } #ifdef RT_USING_INTERRUPT_INFO irq_desc[irq].counter ++; #endif @@ -191,7 +191,7 @@ void rt_hw_trap_irq() void rt_hw_trap_fiq() { - rt_kprintf("fast interrupt request\n"); + rt_kprintf("fast interrupt request\n"); } /*@}*/ diff --git a/bsp/fh8620/drivers/uart.c b/bsp/fh8620/drivers/uart.c index 4b264d920..89df32d75 100644 --- a/bsp/fh8620/drivers/uart.c +++ b/bsp/fh8620/drivers/uart.c @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,12 +18,12 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + #include #include #include "fh_arch.h" @@ -32,35 +32,35 @@ void rt_fh_uart_handler(int vector, void *param) { - int status; - unsigned int ret; - struct fh_uart *uart; - unsigned int reg_status; - rt_device_t dev = (rt_device_t)param; - uart = (struct fh_uart *)dev->user_data; - status = uart_get_iir_status(uart->uart_port); - if (status & UART_IIR_NOINT) - { - return; - } - if(status & UART_IIR_THREMPTY){ - //first close tx isr - uart_disable_irq(uart->uart_port,UART_IER_ETBEI); - - rt_hw_serial_isr((struct rt_serial_device *)dev, RT_SERIAL_EVENT_TX_DONE); - } - else if((status & UART_IIR_CHRTOUT)==UART_IIR_CHRTOUT){ - //bug.... - //if no data in rx fifo - reg_status = uart_get_status(uart->uart_port); - if((reg_status & 1<<3) == 0) - ret = uart_getc(uart->uart_port); - } - else{ - rt_interrupt_enter(); - rt_hw_serial_isr((struct rt_serial_device *)dev, RT_SERIAL_EVENT_RX_IND); - rt_interrupt_leave(); - } + int status; + unsigned int ret; + struct fh_uart *uart; + unsigned int reg_status; + rt_device_t dev = (rt_device_t)param; + uart = (struct fh_uart *)dev->user_data; + status = uart_get_iir_status(uart->uart_port); + if (status & UART_IIR_NOINT) + { + return; + } + if(status & UART_IIR_THREMPTY){ + //first close tx isr + uart_disable_irq(uart->uart_port,UART_IER_ETBEI); + + rt_hw_serial_isr((struct rt_serial_device *)dev, RT_SERIAL_EVENT_TX_DONE); + } + else if((status & UART_IIR_CHRTOUT)==UART_IIR_CHRTOUT){ + //bug.... + //if no data in rx fifo + reg_status = uart_get_status(uart->uart_port); + if((reg_status & 1<<3) == 0) + ret = uart_getc(uart->uart_port); + } + else{ + rt_interrupt_enter(); + rt_hw_serial_isr((struct rt_serial_device *)dev, RT_SERIAL_EVENT_RX_IND); + rt_interrupt_leave(); + } } /** @@ -69,67 +69,67 @@ void rt_fh_uart_handler(int vector, void *param) static rt_err_t fh_uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg) { - int div; - enum data_bits data_mode; - enum stop_bits stop_mode; - enum parity parity_mode; - struct fh_uart *uart; + int div; + enum data_bits data_mode; + enum stop_bits stop_mode; + enum parity parity_mode; + struct fh_uart *uart; - RT_ASSERT(serial != RT_NULL); + RT_ASSERT(serial != RT_NULL); RT_ASSERT(cfg != RT_NULL); - uart = (struct fh_uart *)serial->parent.user_data; - - switch (cfg->data_bits) - { - case DATA_BITS_8: - data_mode = UART_DATA_BIT8; - break; - case DATA_BITS_7: - data_mode = UART_DATA_BIT7; - break; - case DATA_BITS_6: - data_mode = UART_DATA_BIT6; - break; - case DATA_BITS_5: - data_mode = UART_DATA_BIT5; - break; - default: - data_mode = UART_DATA_BIT8; - break; - } - - switch (cfg->stop_bits) - { - case STOP_BITS_2: - stop_mode = UART_STOP_BIT2; - break; - case STOP_BITS_1: - default: - stop_mode = UART_STOP_BIT1; - break; - } - - switch (cfg->parity) - { - case PARITY_ODD: - parity_mode = UART_PARITY_ODD; - break; - case PARITY_EVEN: - parity_mode = UART_PARITY_EVEN; - break; - case PARITY_NONE: - default: - parity_mode = UART_PARITY_NONE; - break; - } + uart = (struct fh_uart *)serial->parent.user_data; + + switch (cfg->data_bits) + { + case DATA_BITS_8: + data_mode = UART_DATA_BIT8; + break; + case DATA_BITS_7: + data_mode = UART_DATA_BIT7; + break; + case DATA_BITS_6: + data_mode = UART_DATA_BIT6; + break; + case DATA_BITS_5: + data_mode = UART_DATA_BIT5; + break; + default: + data_mode = UART_DATA_BIT8; + break; + } + + switch (cfg->stop_bits) + { + case STOP_BITS_2: + stop_mode = UART_STOP_BIT2; + break; + case STOP_BITS_1: + default: + stop_mode = UART_STOP_BIT1; + break; + } + + switch (cfg->parity) + { + case PARITY_ODD: + parity_mode = UART_PARITY_ODD; + break; + case PARITY_EVEN: + parity_mode = UART_PARITY_EVEN; + break; + case PARITY_NONE: + default: + parity_mode = UART_PARITY_NONE; + break; + } uart_disable_irq(uart->uart_port, UART_IER_ERBFI); - uart_configure(uart->uart_port, data_mode, - stop_mode, parity_mode, - cfg->baud_rate, UART_CLOCK_FREQ); + uart_configure(uart->uart_port, data_mode, + stop_mode, parity_mode, + cfg->baud_rate, UART_CLOCK_FREQ); - uart_enable_irq(uart->uart_port, UART_IER_ERBFI); + uart_enable_irq(uart->uart_port, UART_IER_ERBFI); return RT_EOK; } @@ -146,13 +146,13 @@ static rt_err_t fh_uart_control(struct rt_serial_device *serial, { case RT_DEVICE_CTRL_CLR_INT: /* disable rx irq */ - rt_hw_interrupt_mask(uart->irq); - uart_disable_irq(uart->uart_port,UART_IER_ERBFI); + rt_hw_interrupt_mask(uart->irq); + uart_disable_irq(uart->uart_port,UART_IER_ERBFI); break; case RT_DEVICE_CTRL_SET_INT: /* enable rx irq */ - rt_hw_interrupt_umask(uart->irq); - uart_enable_irq(uart->uart_port,UART_IER_ERBFI); + rt_hw_interrupt_umask(uart->irq); + uart_enable_irq(uart->uart_port,UART_IER_ERBFI); break; } @@ -161,33 +161,33 @@ static rt_err_t fh_uart_control(struct rt_serial_device *serial, static int fh_uart_putc(struct rt_serial_device *serial, char c) { - struct fh_uart *uart = serial->parent.user_data; - unsigned int ret; - ret = uart_get_status(uart->uart_port); - if(serial->parent.open_flag & RT_DEVICE_FLAG_INT_TX){ - //RT_DEVICE_FLAG_INT_TX - - if(c == '\n'){ - fh_uart_putc(serial,'\r'); - } - if(ret & UART_USR_TFNF){ - uart_putc(uart->uart_port, c); - return 1; - } - //open tx isr here.. - uart_enable_irq(uart->uart_port,UART_IER_ETBEI); - return -1; - } - //poll mode - else{ + struct fh_uart *uart = serial->parent.user_data; + unsigned int ret; + ret = uart_get_status(uart->uart_port); + if(serial->parent.open_flag & RT_DEVICE_FLAG_INT_TX){ + //RT_DEVICE_FLAG_INT_TX + + if(c == '\n'){ + fh_uart_putc(serial,'\r'); + } + if(ret & UART_USR_TFNF){ + uart_putc(uart->uart_port, c); + return 1; + } + //open tx isr here.. + uart_enable_irq(uart->uart_port,UART_IER_ETBEI); + return -1; + } + //poll mode + else{ - while(!(uart_get_status(uart->uart_port) & UART_USR_TFNF)) - ; - uart_putc(uart->uart_port, c); - return 1; + while(!(uart_get_status(uart->uart_port) & UART_USR_TFNF)) + ; + uart_putc(uart->uart_port, c); + return 1; - } + } @@ -196,16 +196,16 @@ static int fh_uart_putc(struct rt_serial_device *serial, char c) static int fh_uart_getc(struct rt_serial_device *serial) { int result; - struct fh_uart *uart = serial->parent.user_data; + struct fh_uart *uart = serial->parent.user_data; - if (uart_is_rx_ready(uart->uart_port)) - { - result = uart_getc(uart->uart_port); - } - else - { - result = -1; - } + if (uart_is_rx_ready(uart->uart_port)) + { + result = uart_getc(uart->uart_port); + } + else + { + result = -1; + } return result; } @@ -222,8 +222,8 @@ static const struct rt_uart_ops fh_uart_ops = #if defined(RT_USING_UART0) static struct rt_serial_device serial0; struct fh_uart uart0 = { - (uart *)UART0_REG_BASE, - UART0_IRQn + (uart *)UART0_REG_BASE, + UART0_IRQn }; #endif @@ -231,8 +231,8 @@ struct fh_uart uart0 = { #if defined(RT_USING_UART1) static struct rt_serial_device serial1; struct fh_uart uart1 = { - (uart *)UART1_REG_BASE, - UART1_IRQn + (uart *)UART1_REG_BASE, + UART1_IRQn }; #endif @@ -245,45 +245,45 @@ struct fh_uart uart1 = { */ void rt_hw_uart_init(void) { - struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; + struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; #if defined(RT_USING_UART0) #if(0) - serial0.ops = &fh_uart_ops; - serial0.config = config; - - /* register vcom device */ - rt_hw_serial_register(&serial0, "uart0", - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM | RT_DEVICE_FLAG_INT_TX | RT_DEVICE_FLAG_STANDALONE, - &uart0); - rt_hw_interrupt_install(uart0.irq, rt_fh_uart_handler, - (void *)&(serial0.parent), "UART0"); - rt_hw_interrupt_umask(uart0.irq); + serial0.ops = &fh_uart_ops; + serial0.config = config; + + /* register vcom device */ + rt_hw_serial_register(&serial0, "uart0", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM | RT_DEVICE_FLAG_INT_TX | RT_DEVICE_FLAG_STANDALONE, + &uart0); + rt_hw_interrupt_install(uart0.irq, rt_fh_uart_handler, + (void *)&(serial0.parent), "UART0"); + rt_hw_interrupt_umask(uart0.irq); #endif - serial0.ops = &fh_uart_ops; - serial0.config = config; + serial0.ops = &fh_uart_ops; + serial0.config = config; - /* register vcom device */ - rt_hw_serial_register(&serial0, "uart0", - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM , - &uart0); - rt_hw_interrupt_install(uart0.irq, rt_fh_uart_handler, - (void *)&(serial0.parent), "UART0"); - rt_hw_interrupt_umask(uart0.irq); + /* register vcom device */ + rt_hw_serial_register(&serial0, "uart0", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM , + &uart0); + rt_hw_interrupt_install(uart0.irq, rt_fh_uart_handler, + (void *)&(serial0.parent), "UART0"); + rt_hw_interrupt_umask(uart0.irq); #endif #if defined(RT_USING_UART1) - serial1.ops = &fh_uart_ops; - serial1.config = config; - - /* register vcom device */ - rt_hw_serial_register(&serial1, "uart1", - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM , - &uart1); - rt_hw_interrupt_install(uart1.irq, rt_fh_uart_handler, - (void *)&(serial1.parent), "UART1"); - rt_hw_interrupt_umask(uart1.irq); + serial1.ops = &fh_uart_ops; + serial1.config = config; + + /* register vcom device */ + rt_hw_serial_register(&serial1, "uart1", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM , + &uart1); + rt_hw_interrupt_install(uart1.irq, rt_fh_uart_handler, + (void *)&(serial1.parent), "UART1"); + rt_hw_interrupt_umask(uart1.irq); #endif diff --git a/bsp/fh8620/drivers/uart.h b/bsp/fh8620/drivers/uart.h index d4459f02f..c7af24523 100644 --- a/bsp/fh8620/drivers/uart.h +++ b/bsp/fh8620/drivers/uart.h @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,12 +18,12 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + #ifndef UART_H_ #define UART_H_ diff --git a/bsp/fh8620/drivers/wdt.c b/bsp/fh8620/drivers/wdt.c index 1d67007a6..f7f292df8 100644 --- a/bsp/fh8620/drivers/wdt.c +++ b/bsp/fh8620/drivers/wdt.c @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,12 +18,12 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + #include "fh_def.h" #include "wdt.h" #include "interrupt.h" diff --git a/bsp/fh8620/drivers/wdt.h b/bsp/fh8620/drivers/wdt.h index 768a2e073..71673d24a 100644 --- a/bsp/fh8620/drivers/wdt.h +++ b/bsp/fh8620/drivers/wdt.h @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,12 +18,12 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + #ifndef WDT_H_ #define WDT_H_ diff --git a/bsp/fh8620/libraries/driverlib/fh_gpio.c b/bsp/fh8620/libraries/driverlib/fh_gpio.c index e3e58f9a1..7c3938696 100644 --- a/bsp/fh8620/libraries/driverlib/fh_gpio.c +++ b/bsp/fh8620/libraries/driverlib/fh_gpio.c @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,10 +18,10 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - - \ No newline at end of file + + diff --git a/bsp/fh8620/libraries/driverlib/fh_i2c.c b/bsp/fh8620/libraries/driverlib/fh_i2c.c index 661703e71..cc91561b9 100644 --- a/bsp/fh8620/libraries/driverlib/fh_i2c.c +++ b/bsp/fh8620/libraries/driverlib/fh_i2c.c @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,12 +18,12 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + #include "inc/fh_driverlib.h" int I2C_WaitMasterIdle(struct fh_i2c_obj *i2c_obj) diff --git a/bsp/fh8620/libraries/driverlib/fh_ictl.c b/bsp/fh8620/libraries/driverlib/fh_ictl.c index a53c8dba3..10edbb27f 100644 --- a/bsp/fh8620/libraries/driverlib/fh_ictl.c +++ b/bsp/fh8620/libraries/driverlib/fh_ictl.c @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,25 +18,25 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + #include "inc/fh_driverlib.h" void ictl_close_all_isr(fh_intc *p){ - if(p){ - //enable all interrupts - p->IRQ_EN_L = 0xffffffff; - p->IRQ_EN_H = 0xffffffff; - //mask all interrupts - p->IRQ_MASK_L = 0xffffffff; - p->IRQ_MASK_H = 0xffffffff; - } + if(p){ + //enable all interrupts + p->IRQ_EN_L = 0xffffffff; + p->IRQ_EN_H = 0xffffffff; + //mask all interrupts + p->IRQ_MASK_L = 0xffffffff; + p->IRQ_MASK_H = 0xffffffff; + } } @@ -44,13 +44,13 @@ void ictl_close_all_isr(fh_intc *p){ void ictl_mask_isr(fh_intc *p,int irq){ - if(p){ + if(p){ - if (irq < 32) - p->IRQ_MASK_L |= (1 << irq); - else - p->IRQ_MASK_H |= (1 << (irq - 32)); - } + if (irq < 32) + p->IRQ_MASK_L |= (1 << irq); + else + p->IRQ_MASK_H |= (1 << (irq - 32)); + } } @@ -58,12 +58,12 @@ void ictl_mask_isr(fh_intc *p,int irq){ void ictl_unmask_isr(fh_intc *p,int irq){ - if(p){ - if (irq < 32) - p->IRQ_MASK_L &= ~(1 << irq); - else - p->IRQ_MASK_H &= ~(1 << (irq - 32)); + if(p){ + if (irq < 32) + p->IRQ_MASK_L &= ~(1 << irq); + else + p->IRQ_MASK_H &= ~(1 << (irq - 32)); - } + } } diff --git a/bsp/fh8620/libraries/driverlib/fh_mmc.c b/bsp/fh8620/libraries/driverlib/fh_mmc.c index 5995e634f..0b644d29e 100644 --- a/bsp/fh8620/libraries/driverlib/fh_mmc.c +++ b/bsp/fh8620/libraries/driverlib/fh_mmc.c @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,7 +18,7 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes diff --git a/bsp/fh8620/libraries/driverlib/fh_pwm.c b/bsp/fh8620/libraries/driverlib/fh_pwm.c index af19110a4..7b71e78f2 100644 --- a/bsp/fh8620/libraries/driverlib/fh_pwm.c +++ b/bsp/fh8620/libraries/driverlib/fh_pwm.c @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,7 +18,7 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes diff --git a/bsp/fh8620/libraries/driverlib/fh_sdio.c b/bsp/fh8620/libraries/driverlib/fh_sdio.c index 8c9e69e07..edc415106 100644 --- a/bsp/fh8620/libraries/driverlib/fh_sdio.c +++ b/bsp/fh8620/libraries/driverlib/fh_sdio.c @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,7 +18,7 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes @@ -34,15 +34,15 @@ #define SDC_USE_IDMA #define INSTRUCTIONS_PER_USEC 1000 -#define CMD_TIMEOUT_USEC 100000 -#define DATA_READY_TIMEOUT_USEC 200000 +#define CMD_TIMEOUT_USEC 100000 +#define DATA_READY_TIMEOUT_USEC 200000 #define DMA_TRANSFER_TIMEOUT_TICKS 300 #define DATA_TRANSFER_OVER_TIMEOUT_USEC 1000 #define ACMD41_RETRY_COUNT 1000//100000 -#define CIU_CLK 50000//25000//25000 //27MHz -#define MMC_FOD_VALUE 125 /* 125 KHz */ -#define NORM_FOD_VALUE 25000//5000//25000 /* 25 MHz */ +#define CIU_CLK 50000//25000//25000 //27MHz +#define MMC_FOD_VALUE 125 /* 125 KHz */ +#define NORM_FOD_VALUE 25000//5000//25000 /* 25 MHz */ #define MMC_FOD_DIVIDER_VALUE (((CIU_CLK+MMC_FOD_VALUE*2-1)/(MMC_FOD_VALUE*2))) #ifdef SDCARD_CLK_DIVIDER #define ONE_BIT_BUS_FREQ SDCARD_CLK_DIVIDER @@ -56,1118 +56,1118 @@ static sdc_t sdc_array[2]; static void plat_loop(unsigned int macrosecond) { - unsigned int clk; - - while (macrosecond-- > 0) { - for(clk=INSTRUCTIONS_PER_USEC; clk>0; clk--); - } + unsigned int clk; + + while (macrosecond-- > 0) { + for(clk=INSTRUCTIONS_PER_USEC; clk>0; clk--); + } } static int synopmob_execute_command(unsigned int base, unsigned int cmd_register, unsigned int arg_register) { - unsigned int retries = CMD_TIMEOUT_USEC; - - synopmob_set_register(base + RINTSTS, 0xfffe); //clear interrupts, FIXME - synopmob_set_register(base+CMDARG, arg_register); - synopmob_set_register(base+CMD, cmd_register | (0x80000000|0x20000000/*fixed to use hold*/)); - - while (retries-- > 0) { - if (!(synopmob_read_register(base+CMD) & 0x80000000/*CMD done bit*/)) - return 0; - plat_loop(1); - } - - return ERRCMDRETRIESOVER; + unsigned int retries = CMD_TIMEOUT_USEC; + + synopmob_set_register(base + RINTSTS, 0xfffe); //clear interrupts, FIXME + synopmob_set_register(base+CMDARG, arg_register); + synopmob_set_register(base+CMD, cmd_register | (0x80000000|0x20000000/*fixed to use hold*/)); + + while (retries-- > 0) { + if (!(synopmob_read_register(base+CMD) & 0x80000000/*CMD done bit*/)) + return 0; + plat_loop(1); + } + + return ERRCMDRETRIESOVER; } static int synopmob_wait_command_done(unsigned int base, unsigned int* inst, unsigned int flag) { - unsigned int retries = CMD_TIMEOUT_USEC; - unsigned int sts; - - while (retries-- > 0) { - sts = synopmob_read_register(base+RINTSTS); - if (sts && ((sts & flag) == flag) ) { - *inst = sts; - return 0; - } - plat_loop(1); - } - return ERRCMDRETRIESOVER; + unsigned int retries = CMD_TIMEOUT_USEC; + unsigned int sts; + + while (retries-- > 0) { + sts = synopmob_read_register(base+RINTSTS); + if (sts && ((sts & flag) == flag) ) { + *inst = sts; + return 0; + } + plat_loop(1); + } + return ERRCMDRETRIESOVER; } static int synopmob_wait_data_ready(unsigned int base) { - unsigned int retries = DATA_READY_TIMEOUT_USEC; - - while (retries-- > 0) { - if (!((synopmob_read_register(base+STATUS)) & 0x00000200)) { - return 0; - } - - plat_loop(1); - } - return ERRDATANOTREADY; + unsigned int retries = DATA_READY_TIMEOUT_USEC; + + while (retries-- > 0) { + if (!((synopmob_read_register(base+STATUS)) & 0x00000200)) { + return 0; + } + + plat_loop(1); + } + return ERRDATANOTREADY; } static int synopmob_handle_standard_rinsts(unsigned int raw_int_stat) { - int error_status = 0; - - if ( raw_int_stat & INTMASK_ERROR) { - if (raw_int_stat & INTMSK_RESP_ERR) { - error_status = ERRRESPRECEP; - } - if (raw_int_stat & INTMSK_RCRC) { - error_status = ERRRESPCRC; - } - if (raw_int_stat & INTMSK_DCRC) { - error_status = ERRDCRC; - } - if (raw_int_stat & INTMSK_RTO) { - error_status = ERRRESPTIMEOUT; - } - if (raw_int_stat & INTMSK_DTO) { - error_status = ERRDRTIMEOUT; - } - if (raw_int_stat & INTMSK_HTO) { - error_status = ERRUNDERWRITE; - } - if (raw_int_stat & INTMSK_FRUN) { - error_status = ERROVERREAD; - } - if (raw_int_stat & INTMSK_HLE) { - error_status = ERRHLE; - } - if (raw_int_stat & INTMSK_SBE) { - error_status = ERRSTARTBIT; - } - if (raw_int_stat & INTMSK_EBE) { - error_status = ERRENDBITERR; - } - } + int error_status = 0; + + if ( raw_int_stat & INTMASK_ERROR) { + if (raw_int_stat & INTMSK_RESP_ERR) { + error_status = ERRRESPRECEP; + } + if (raw_int_stat & INTMSK_RCRC) { + error_status = ERRRESPCRC; + } + if (raw_int_stat & INTMSK_DCRC) { + error_status = ERRDCRC; + } + if (raw_int_stat & INTMSK_RTO) { + error_status = ERRRESPTIMEOUT; + } + if (raw_int_stat & INTMSK_DTO) { + error_status = ERRDRTIMEOUT; + } + if (raw_int_stat & INTMSK_HTO) { + error_status = ERRUNDERWRITE; + } + if (raw_int_stat & INTMSK_FRUN) { + error_status = ERROVERREAD; + } + if (raw_int_stat & INTMSK_HLE) { + error_status = ERRHLE; + } + if (raw_int_stat & INTMSK_SBE) { + error_status = ERRSTARTBIT; + } + if (raw_int_stat & INTMSK_EBE) { + error_status = ERRENDBITERR; + } + } //SDIO_PRINTF("------- %s, line %d raw_int_stat = %08x-------\n", __FUNCTION__, __LINE__, raw_int_stat); - return error_status; + return error_status; } static int synopmob_check_r1_resp(unsigned int the_response) { - int retval = 0; - - if (the_response & R1CS_ERROR_OCCURED_MAP) { - if (the_response & R1CS_ADDRESS_OUT_OF_RANGE) { - retval = ERRADDRESSRANGE; - } else if (the_response & R1CS_ADDRESS_MISALIGN) { - retval = ERRADDRESSMISALIGN; - } else if (the_response & R1CS_BLOCK_LEN_ERR) { - retval = ERRBLOCKLEN; - } else if (the_response & R1CS_ERASE_SEQ_ERR) { - retval = ERRERASESEQERR; - } else if (the_response & R1CS_ERASE_PARAM) { - retval = ERRERASEPARAM; - } else if (the_response & R1CS_WP_VIOLATION) { - retval = ERRPROT; - } else if (the_response & R1CS_CARD_IS_LOCKED) { - retval = ERRCARDLOCKED; - } else if (the_response & R1CS_LCK_UNLCK_FAILED) { - retval = ERRCARDLOCKED; - } else if (the_response & R1CS_COM_CRC_ERROR) { - retval = ERRCRC; - } else if (the_response & R1CS_ILLEGAL_COMMAND) { - retval = ERRILLEGALCOMMAND; - } else if (the_response & R1CS_CARD_ECC_FAILED) { - retval = ERRECCFAILED; - } else if (the_response & R1CS_CC_ERROR) { - retval = ERRCCERR; - } else if (the_response & R1CS_ERROR) { - retval = ERRUNKNOWN; - } else if (the_response & R1CS_UNDERRUN) { - retval = ERRUNDERRUN; - } else if (the_response & R1CS_OVERRUN) { - retval = ERROVERRUN; - } else if (the_response & R1CS_CSD_OVERWRITE) { - retval = ERRCSDOVERWRITE; - } else if (the_response & R1CS_WP_ERASE_SKIP) { - retval = ERRPROT; - } else if (the_response & R1CS_ERASE_RESET) { - retval = ERRERASERESET; - } else if (the_response & R1CS_SWITCH_ERROR) { - retval = ERRFSMSTATE; - } - } - - return retval; + int retval = 0; + + if (the_response & R1CS_ERROR_OCCURED_MAP) { + if (the_response & R1CS_ADDRESS_OUT_OF_RANGE) { + retval = ERRADDRESSRANGE; + } else if (the_response & R1CS_ADDRESS_MISALIGN) { + retval = ERRADDRESSMISALIGN; + } else if (the_response & R1CS_BLOCK_LEN_ERR) { + retval = ERRBLOCKLEN; + } else if (the_response & R1CS_ERASE_SEQ_ERR) { + retval = ERRERASESEQERR; + } else if (the_response & R1CS_ERASE_PARAM) { + retval = ERRERASEPARAM; + } else if (the_response & R1CS_WP_VIOLATION) { + retval = ERRPROT; + } else if (the_response & R1CS_CARD_IS_LOCKED) { + retval = ERRCARDLOCKED; + } else if (the_response & R1CS_LCK_UNLCK_FAILED) { + retval = ERRCARDLOCKED; + } else if (the_response & R1CS_COM_CRC_ERROR) { + retval = ERRCRC; + } else if (the_response & R1CS_ILLEGAL_COMMAND) { + retval = ERRILLEGALCOMMAND; + } else if (the_response & R1CS_CARD_ECC_FAILED) { + retval = ERRECCFAILED; + } else if (the_response & R1CS_CC_ERROR) { + retval = ERRCCERR; + } else if (the_response & R1CS_ERROR) { + retval = ERRUNKNOWN; + } else if (the_response & R1CS_UNDERRUN) { + retval = ERRUNDERRUN; + } else if (the_response & R1CS_OVERRUN) { + retval = ERROVERRUN; + } else if (the_response & R1CS_CSD_OVERWRITE) { + retval = ERRCSDOVERWRITE; + } else if (the_response & R1CS_WP_ERASE_SKIP) { + retval = ERRPROT; + } else if (the_response & R1CS_ERASE_RESET) { + retval = ERRERASERESET; + } else if (the_response & R1CS_SWITCH_ERROR) { + retval = ERRFSMSTATE; + } + } + + return retval; } static int synopmob_check_r5_resp(unsigned int the_resp) { - int ret = 0; - - if (the_resp & R5_IO_ERR_BITS) { - if (the_resp & R5_IO_CRC_ERR) { - ret = ERRDCRC; - } else if (the_resp & R5_IO_BAD_CMD) { - ret = ERRILLEGALCOMMAND; - } else if (the_resp & R5_IO_GEN_ERR) { - ret = ERRUNKNOWN; - } else if (the_resp & R5_IO_FUNC_ERR) { - ret = ERRBADFUNC; - } else if (the_resp & R5_IO_OUT_RANGE) { - ret = ERRADDRESSRANGE; - } - } - - return ret; + int ret = 0; + + if (the_resp & R5_IO_ERR_BITS) { + if (the_resp & R5_IO_CRC_ERR) { + ret = ERRDCRC; + } else if (the_resp & R5_IO_BAD_CMD) { + ret = ERRILLEGALCOMMAND; + } else if (the_resp & R5_IO_GEN_ERR) { + ret = ERRUNKNOWN; + } else if (the_resp & R5_IO_FUNC_ERR) { + ret = ERRBADFUNC; + } else if (the_resp & R5_IO_OUT_RANGE) { + ret = ERRADDRESSRANGE; + } + } + + return ret; } static int sd_send_cmd0(sdc_t* sdc) { - int ret; - unsigned int intst; - unsigned int base = sdc->ip_base; - - ret = synopmob_execute_command(base, 0x4000, 0); - if (!ret) { - ret = synopmob_wait_command_done(base, &intst, INTMSK_CMD_DONE); - if (!ret) { - synopmob_set_register(base+RINTSTS, intst); - return synopmob_handle_standard_rinsts(intst); - } - } - - return ret; + int ret; + unsigned int intst; + unsigned int base = sdc->ip_base; + + ret = synopmob_execute_command(base, 0x4000, 0); + if (!ret) { + ret = synopmob_wait_command_done(base, &intst, INTMSK_CMD_DONE); + if (!ret) { + synopmob_set_register(base+RINTSTS, intst); + return synopmob_handle_standard_rinsts(intst); + } + } + + return ret; } static int sd_send_cmd2(sdc_t* sdc) { - int ret; - unsigned int intst; - unsigned int base = sdc->ip_base; - - ret = synopmob_execute_command(base, 0xC2, 0); - if (!ret) { - ret = synopmob_wait_command_done(base, &intst, INTMSK_CMD_DONE); - if (!ret) { - synopmob_set_register(base+RINTSTS, intst); - return synopmob_handle_standard_rinsts(intst); - } - } - - return ret; + int ret; + unsigned int intst; + unsigned int base = sdc->ip_base; + + ret = synopmob_execute_command(base, 0xC2, 0); + if (!ret) { + ret = synopmob_wait_command_done(base, &intst, INTMSK_CMD_DONE); + if (!ret) { + synopmob_set_register(base+RINTSTS, intst); + return synopmob_handle_standard_rinsts(intst); + } + } + + return ret; } static int sd_send_cmd3(sdc_t* sdc) { - int ret; - unsigned int intst; - unsigned int resp; - unsigned int base = sdc->ip_base; - - ret = synopmob_execute_command(base, 0x43, 0); - if (!ret) { - ret = synopmob_wait_command_done(base, &intst, INTMSK_CMD_DONE); - if (!ret) { - synopmob_set_register(base+RINTSTS, intst); - ret = synopmob_handle_standard_rinsts(intst); - if (!ret) { - resp = synopmob_read_register(base+RESP0); - sdc->rca = resp >> 16; - resp = (resp & 0x1fff) | (((resp>>13)&1)<<19) | (((resp>>14)&3)<<22); - return synopmob_check_r1_resp(resp); - } - } - } - - return ret; + int ret; + unsigned int intst; + unsigned int resp; + unsigned int base = sdc->ip_base; + + ret = synopmob_execute_command(base, 0x43, 0); + if (!ret) { + ret = synopmob_wait_command_done(base, &intst, INTMSK_CMD_DONE); + if (!ret) { + synopmob_set_register(base+RINTSTS, intst); + ret = synopmob_handle_standard_rinsts(intst); + if (!ret) { + resp = synopmob_read_register(base+RESP0); + sdc->rca = resp >> 16; + resp = (resp & 0x1fff) | (((resp>>13)&1)<<19) | (((resp>>14)&3)<<22); + return synopmob_check_r1_resp(resp); + } + } + } + + return ret; } static int sd_send_cmd_r1(sdc_t* sdc, unsigned int cmd, unsigned int arg, unsigned int buzy) { - int ret; - unsigned int intst; - unsigned int resp; - unsigned int base = sdc->ip_base; - - ret = synopmob_execute_command(base, cmd, arg); - if (!ret) { - ret = synopmob_wait_command_done(base, &intst, INTMSK_CMD_DONE); - if (!ret) { - synopmob_set_register(base+RINTSTS, intst); - ret = synopmob_handle_standard_rinsts(intst); - if (!ret) { - resp = synopmob_read_register(base+RESP0); - ret = synopmob_check_r1_resp(resp); - if (buzy && !ret) { - ret = synopmob_wait_data_ready(base); - } - } - } - } - - return ret; + int ret; + unsigned int intst; + unsigned int resp; + unsigned int base = sdc->ip_base; + + ret = synopmob_execute_command(base, cmd, arg); + if (!ret) { + ret = synopmob_wait_command_done(base, &intst, INTMSK_CMD_DONE); + if (!ret) { + synopmob_set_register(base+RINTSTS, intst); + ret = synopmob_handle_standard_rinsts(intst); + if (!ret) { + resp = synopmob_read_register(base+RESP0); + ret = synopmob_check_r1_resp(resp); + if (buzy && !ret) { + ret = synopmob_wait_data_ready(base); + } + } + } + } + + return ret; } static int sd_send_cmd7(sdc_t* sdc) { - return sd_send_cmd_r1(sdc, 0x47, sdc->rca<<16, 1); + return sd_send_cmd_r1(sdc, 0x47, sdc->rca<<16, 1); } static int sd_send_uncmd7(sdc_t* sdc) { - int ret; - unsigned int intst; - unsigned int base = sdc->ip_base; - - ret = synopmob_execute_command(base, 0x7, 0); - if (!ret) { - ret = synopmob_wait_command_done(base, &intst, INTMSK_CMD_DONE); - if (!ret) { - synopmob_set_register(base+RINTSTS, intst); - ret = synopmob_handle_standard_rinsts(intst); - } - } - - return ret; + int ret; + unsigned int intst; + unsigned int base = sdc->ip_base; + + ret = synopmob_execute_command(base, 0x7, 0); + if (!ret) { + ret = synopmob_wait_command_done(base, &intst, INTMSK_CMD_DONE); + if (!ret) { + synopmob_set_register(base+RINTSTS, intst); + ret = synopmob_handle_standard_rinsts(intst); + } + } + + return ret; } static int sd_send_cmd16(sdc_t* sdc) { - return sd_send_cmd_r1(sdc, 0x50, 512, 0); + return sd_send_cmd_r1(sdc, 0x50, 512, 0); } static int sd_send_cmd55(sdc_t* sdc) { - return sd_send_cmd_r1(sdc, 0x77, sdc->rca<<16, 0); + return sd_send_cmd_r1(sdc, 0x77, sdc->rca<<16, 0); } static int sd_send_acmd6(sdc_t* sdc, unsigned int bitwidth) { - unsigned int cmd_arg; - int ret; - unsigned int base = sdc->ip_base; - - ret = sd_send_cmd55(sdc); - if (!ret) { - cmd_arg = 0; //default to 1bit mode - if (bitwidth == 4) { - cmd_arg = 2; // 4bit mode - } - ret = sd_send_cmd_r1(sdc, 0x2046, cmd_arg, 0); - if (!ret) { - if (bitwidth == 4) { - synopmob_set_register(base+CTYPE, FOUR_BIT_MODE); - } - else { - synopmob_set_register(base+CTYPE, ONE_BIT_MODE); - } - } - } - - return ret; + unsigned int cmd_arg; + int ret; + unsigned int base = sdc->ip_base; + + ret = sd_send_cmd55(sdc); + if (!ret) { + cmd_arg = 0; //default to 1bit mode + if (bitwidth == 4) { + cmd_arg = 2; // 4bit mode + } + ret = sd_send_cmd_r1(sdc, 0x2046, cmd_arg, 0); + if (!ret) { + if (bitwidth == 4) { + synopmob_set_register(base+CTYPE, FOUR_BIT_MODE); + } + else { + synopmob_set_register(base+CTYPE, ONE_BIT_MODE); + } + } + } + + return ret; } #ifdef SDC_USE_IDMA static int sdc_read_write_block(HSDC handle, unsigned int rw, unsigned int blk, unsigned int num, unsigned char* buffer) { - sdc_t* sdc = (sdc_t*)handle; - volatile DmaDesc *pDmaDesc = sdc->pDmaDesc; - int ret; - unsigned int intsts = 0; - unsigned int cmd; - unsigned int multi = 0; - unsigned int base = sdc->ip_base; - int loop_for_command_done_check = DATA_TRANSFER_OVER_TIMEOUT_USEC; - rt_err_t err; - - // valid check - if (synopmob_read_register(base+CDETECT) & 1) { - return ERRCARDNOTCONN; - } - if (!num || num > 16) { - return ERRNOTSUPPORTED; - } - if (blk + num > sdc->sectors) { - return ERRADDRESSRANGE; - } - - if ( rw ) { - flush_dcache_range((unsigned long)buffer, num << 9); - } - else { - // to avoid memset bug? - inv_dcache_range((unsigned long)buffer, num << 9); - } - - err = rt_sem_take(sdc->mutex, RT_WAITING_FOREVER); - if (err != RT_EOK) { - return ERRNORES; - } - - // reset - synopmob_set_bits(base+CTRL, FIFO_RESET); //reset FIFO - while (synopmob_read_register(base+CTRL) & FIFO_RESET); - synopmob_set_register(base + RINTSTS, 0xfffe); //clear interrupts - - cmd = 0x2658; // write - if ( !rw ) { - cmd = 0x2251; //read - } - //if (num > 1) { - if (num >= 1) { // some card fail on sigle-block mode, so use multi-block instead of sigle-block mode. - cmd++; - multi++; - } - if (sdc->card_type == SD_TYPE) { - blk <<= 9; //SD stadand capability card use 512 unit. - } - num <<= 9; - - pDmaDesc->desc0 |= DescOwnByDma | DescFirstDesc | DescLastDesc; - pDmaDesc->desc1 = ((num << DescBuf1SizeShift) & DescBuf1SizMsk); - pDmaDesc->desc2 = (unsigned int)buffer; - flush_dcache_range((unsigned long)pDmaDesc, sizeof(DmaDesc)); // add SZ_ADJUST - synopmob_set_register(base + DBADDR, (unsigned int)(pDmaDesc)); // add SZ_ADJUST - synopmob_set_register(base+BLKSIZ, 512); - synopmob_set_register(base+BYTCNT, num); - synopmob_set_bits(base + CTRL, CTRL_USE_IDMAC); - synopmob_set_bits(base + BMOD,BMOD_DE); - - ret = synopmob_execute_command(base, cmd, blk); - if ( !ret ) { - ret = ERRIDMA; - synopmob_set_bits(base+CTRL, INT_ENABLE); - err = rt_sem_take(sdc->sem, DMA_TRANSFER_TIMEOUT_TICKS); - if ( !err ) { - while (--loop_for_command_done_check > 0) { - intsts = synopmob_read_register(base+RINTSTS); - if ((intsts & (INTMSK_CMD_DONE|INTMSK_DAT_OVER)) == (INTMSK_CMD_DONE|INTMSK_DAT_OVER)) { - break; - } - plat_loop(1); - } - ret = synopmob_handle_standard_rinsts(intsts); - if (!ret ) { - if( !loop_for_command_done_check || !(sdc->idsts & 0x100)) { //normal interrupt - ret = ERRIDMA; - } - } - } - } - - if (ret) { - char* op = "read"; - if (rw) - op = "write"; - - SDIO_PRINTF("sdc_read_write_block(%s) fail:, ret = %d\n", op, ret); - } - - synopmob_clear_bits(base+CTRL, INT_ENABLE); - synopmob_clear_bits(base + CTRL, CTRL_USE_IDMAC); - synopmob_clear_bits(base + BMOD,BMOD_DE); - - synopmob_set_register(base+BLKSIZ, 512); - synopmob_set_register(base+BYTCNT, 512); - - synopmob_set_register(base + RINTSTS, 0xfffe); - - if ( !ret && rw) { - ret = synopmob_wait_data_ready(base); - } - - if (!ret && multi ) { //send STOP_TRANSACTION command - ret = sd_send_cmd_r1(sdc, 0x404c, 0, 1); - } - - rt_sem_release(sdc->mutex); - - if ( !rw && !ret ) { //read - inv_dcache_range((unsigned long)buffer, num); - } - - return ret; + sdc_t* sdc = (sdc_t*)handle; + volatile DmaDesc *pDmaDesc = sdc->pDmaDesc; + int ret; + unsigned int intsts = 0; + unsigned int cmd; + unsigned int multi = 0; + unsigned int base = sdc->ip_base; + int loop_for_command_done_check = DATA_TRANSFER_OVER_TIMEOUT_USEC; + rt_err_t err; + + // valid check + if (synopmob_read_register(base+CDETECT) & 1) { + return ERRCARDNOTCONN; + } + if (!num || num > 16) { + return ERRNOTSUPPORTED; + } + if (blk + num > sdc->sectors) { + return ERRADDRESSRANGE; + } + + if ( rw ) { + flush_dcache_range((unsigned long)buffer, num << 9); + } + else { + // to avoid memset bug? + inv_dcache_range((unsigned long)buffer, num << 9); + } + + err = rt_sem_take(sdc->mutex, RT_WAITING_FOREVER); + if (err != RT_EOK) { + return ERRNORES; + } + + // reset + synopmob_set_bits(base+CTRL, FIFO_RESET); //reset FIFO + while (synopmob_read_register(base+CTRL) & FIFO_RESET); + synopmob_set_register(base + RINTSTS, 0xfffe); //clear interrupts + + cmd = 0x2658; // write + if ( !rw ) { + cmd = 0x2251; //read + } + //if (num > 1) { + if (num >= 1) { // some card fail on sigle-block mode, so use multi-block instead of sigle-block mode. + cmd++; + multi++; + } + if (sdc->card_type == SD_TYPE) { + blk <<= 9; //SD stadand capability card use 512 unit. + } + num <<= 9; + + pDmaDesc->desc0 |= DescOwnByDma | DescFirstDesc | DescLastDesc; + pDmaDesc->desc1 = ((num << DescBuf1SizeShift) & DescBuf1SizMsk); + pDmaDesc->desc2 = (unsigned int)buffer; + flush_dcache_range((unsigned long)pDmaDesc, sizeof(DmaDesc)); // add SZ_ADJUST + synopmob_set_register(base + DBADDR, (unsigned int)(pDmaDesc)); // add SZ_ADJUST + synopmob_set_register(base+BLKSIZ, 512); + synopmob_set_register(base+BYTCNT, num); + synopmob_set_bits(base + CTRL, CTRL_USE_IDMAC); + synopmob_set_bits(base + BMOD,BMOD_DE); + + ret = synopmob_execute_command(base, cmd, blk); + if ( !ret ) { + ret = ERRIDMA; + synopmob_set_bits(base+CTRL, INT_ENABLE); + err = rt_sem_take(sdc->sem, DMA_TRANSFER_TIMEOUT_TICKS); + if ( !err ) { + while (--loop_for_command_done_check > 0) { + intsts = synopmob_read_register(base+RINTSTS); + if ((intsts & (INTMSK_CMD_DONE|INTMSK_DAT_OVER)) == (INTMSK_CMD_DONE|INTMSK_DAT_OVER)) { + break; + } + plat_loop(1); + } + ret = synopmob_handle_standard_rinsts(intsts); + if (!ret ) { + if( !loop_for_command_done_check || !(sdc->idsts & 0x100)) { //normal interrupt + ret = ERRIDMA; + } + } + } + } + + if (ret) { + char* op = "read"; + if (rw) + op = "write"; + + SDIO_PRINTF("sdc_read_write_block(%s) fail:, ret = %d\n", op, ret); + } + + synopmob_clear_bits(base+CTRL, INT_ENABLE); + synopmob_clear_bits(base + CTRL, CTRL_USE_IDMAC); + synopmob_clear_bits(base + BMOD,BMOD_DE); + + synopmob_set_register(base+BLKSIZ, 512); + synopmob_set_register(base+BYTCNT, 512); + + synopmob_set_register(base + RINTSTS, 0xfffe); + + if ( !ret && rw) { + ret = synopmob_wait_data_ready(base); + } + + if (!ret && multi ) { //send STOP_TRANSACTION command + ret = sd_send_cmd_r1(sdc, 0x404c, 0, 1); + } + + rt_sem_release(sdc->mutex); + + if ( !rw && !ret ) { //read + inv_dcache_range((unsigned long)buffer, num); + } + + return ret; } #else //no IDMA static int sdc_read_write_block(HSDC handle, unsigned int rw, unsigned int blk, unsigned int num, unsigned char* buffer) { - sdc_t* sdc = (sdc_t*)handle; - volatile DmaDesc *pDmaDesc = sdc->pDmaDesc; - int ret; - unsigned int intsts = 0; - unsigned int entries; - unsigned int cmd; - unsigned int multi = 0; - unsigned int base = sdc->ip_base; - int loop_for_command_done_check = DATA_TRANSFER_OVER_TIMEOUT_USEC; - rt_err_t err; - - // valid check - if (synopmob_read_register(base+CDETECT) & 1) { - return ERRCARDNOTCONN; - } - if (!num || num > 16) { - return ERRNOTSUPPORTED; - } - if (blk + num > sdc->sectors) { - return ERRADDRESSRANGE; - } - - if ( rw ) { - flush_dcache_range((unsigned long)buffer, num << 9); - } - else { - // to avoid memset bug? - inv_dcache_range((unsigned long)buffer, num << 9); - } - - err = rt_sem_take(sdc->mutex, RT_WAITING_FOREVER); - if (err != RT_EOK) { - return ERRNORES; - } - - // reset - synopmob_set_bits(base+CTRL, FIFO_RESET); //reset FIFO - while (synopmob_read_register(base+CTRL) & FIFO_RESET); - synopmob_set_register(base + RINTSTS, 0xfffe); //clear interrupts - - cmd = 0x2658; // write - if ( !rw ) { - cmd = 0x2251; //read - } - if (num > 1) { - cmd++; - multi++; - } - if (sdc->card_type == SD_TYPE) { - blk <<= 9; //SD stadand capability card use 512 unit. - } - num <<= 9; - - synopmob_set_register(base+BLKSIZ, 512); - synopmob_set_register(base+BYTCNT, num); - - ret = synopmob_execute_command(base, cmd, blk); - if ( !ret ) { - while (1) { - ret = synopmob_wait_command_done(base, &intsts, 0); - if (ret) - break; - - ret = synopmob_handle_standard_rinsts(intsts); - if (ret) - break; - - if (!rw && (intsts & (INTMSK_RXDR|INTMSK_DAT_OVER)) ){ - while (num > 0 ) { - entries = synopmob_read_register(base + STATUS); - if (!GET_FIFO_COUNT(entries)) - break; - *((volatile unsigned int*)buffer) = synopmob_read_register(base + FIFODAT); - buffer += 4; - num -= 4; - } - } - - if (rw && ( intsts & INTMSK_TXDR ) ) { - while (num > 0) { - entries = synopmob_read_register(base+STATUS); - if ( entries & 8 ) { //FIFO is full - break; - } - synopmob_set_register(base+FIFODAT, *((volatile unsigned int*)buffer)); - buffer += 4; - num -= 4; - } - } - - if ( intsts & INTMSK_DAT_OVER ) { - break; - } - - if (intsts & INTMSK_CMD_DONE) { - entries = synopmob_read_register(base+RESP0); - ret = synopmob_check_r1_resp(entries); - if (ret) { - break; - } - } - - synopmob_set_register(base+RINTSTS, intsts); //write to clear - intsts = 0; - } - - if (intsts) { - synopmob_set_register(base+RINTSTS, intsts); //write to clear - } - } - - synopmob_set_register(base+BLKSIZ, 512); - synopmob_set_register(base+BYTCNT, 512); - synopmob_set_register(base + RINTSTS, 0xfffe); - - if ( !ret && rw) { - ret = synopmob_wait_data_ready(base); - } - - if (!ret && multi ) { //send STOP_TRANSACTION command - ret = sd_send_cmd_r1(sdc, 0x404c, 0, 1); - } - - rt_sem_release(sdc->mutex); - - if ( !rw && !ret ) { //read - inv_dcache_range((unsigned long)buffer, num); - } - - return ret; + sdc_t* sdc = (sdc_t*)handle; + volatile DmaDesc *pDmaDesc = sdc->pDmaDesc; + int ret; + unsigned int intsts = 0; + unsigned int entries; + unsigned int cmd; + unsigned int multi = 0; + unsigned int base = sdc->ip_base; + int loop_for_command_done_check = DATA_TRANSFER_OVER_TIMEOUT_USEC; + rt_err_t err; + + // valid check + if (synopmob_read_register(base+CDETECT) & 1) { + return ERRCARDNOTCONN; + } + if (!num || num > 16) { + return ERRNOTSUPPORTED; + } + if (blk + num > sdc->sectors) { + return ERRADDRESSRANGE; + } + + if ( rw ) { + flush_dcache_range((unsigned long)buffer, num << 9); + } + else { + // to avoid memset bug? + inv_dcache_range((unsigned long)buffer, num << 9); + } + + err = rt_sem_take(sdc->mutex, RT_WAITING_FOREVER); + if (err != RT_EOK) { + return ERRNORES; + } + + // reset + synopmob_set_bits(base+CTRL, FIFO_RESET); //reset FIFO + while (synopmob_read_register(base+CTRL) & FIFO_RESET); + synopmob_set_register(base + RINTSTS, 0xfffe); //clear interrupts + + cmd = 0x2658; // write + if ( !rw ) { + cmd = 0x2251; //read + } + if (num > 1) { + cmd++; + multi++; + } + if (sdc->card_type == SD_TYPE) { + blk <<= 9; //SD stadand capability card use 512 unit. + } + num <<= 9; + + synopmob_set_register(base+BLKSIZ, 512); + synopmob_set_register(base+BYTCNT, num); + + ret = synopmob_execute_command(base, cmd, blk); + if ( !ret ) { + while (1) { + ret = synopmob_wait_command_done(base, &intsts, 0); + if (ret) + break; + + ret = synopmob_handle_standard_rinsts(intsts); + if (ret) + break; + + if (!rw && (intsts & (INTMSK_RXDR|INTMSK_DAT_OVER)) ){ + while (num > 0 ) { + entries = synopmob_read_register(base + STATUS); + if (!GET_FIFO_COUNT(entries)) + break; + *((volatile unsigned int*)buffer) = synopmob_read_register(base + FIFODAT); + buffer += 4; + num -= 4; + } + } + + if (rw && ( intsts & INTMSK_TXDR ) ) { + while (num > 0) { + entries = synopmob_read_register(base+STATUS); + if ( entries & 8 ) { //FIFO is full + break; + } + synopmob_set_register(base+FIFODAT, *((volatile unsigned int*)buffer)); + buffer += 4; + num -= 4; + } + } + + if ( intsts & INTMSK_DAT_OVER ) { + break; + } + + if (intsts & INTMSK_CMD_DONE) { + entries = synopmob_read_register(base+RESP0); + ret = synopmob_check_r1_resp(entries); + if (ret) { + break; + } + } + + synopmob_set_register(base+RINTSTS, intsts); //write to clear + intsts = 0; + } + + if (intsts) { + synopmob_set_register(base+RINTSTS, intsts); //write to clear + } + } + + synopmob_set_register(base+BLKSIZ, 512); + synopmob_set_register(base+BYTCNT, 512); + synopmob_set_register(base + RINTSTS, 0xfffe); + + if ( !ret && rw) { + ret = synopmob_wait_data_ready(base); + } + + if (!ret && multi ) { //send STOP_TRANSACTION command + ret = sd_send_cmd_r1(sdc, 0x404c, 0, 1); + } + + rt_sem_release(sdc->mutex); + + if ( !rw && !ret ) { //read + inv_dcache_range((unsigned long)buffer, num); + } + + return ret; } #endif //SDC_USE_IDMA int sdc_write_block(HSDC handle, unsigned int blk, unsigned int num, unsigned char* buffer) { - return sdc_read_write_block(handle, 1, blk, num, buffer); + return sdc_read_write_block(handle, 1, blk, num, buffer); } int sdc_read_block(HSDC handle, unsigned int blk, unsigned int num, unsigned char* buffer) { - return sdc_read_write_block(handle, 0, blk, num, buffer); + return sdc_read_write_block(handle, 0, blk, num, buffer); } int sdc_erase_block(HSDC handle, unsigned int blk, unsigned int num) { - int ret; - sdc_t* sdc = (sdc_t*)handle; - - if (sdc->card_type == SD_TYPE) { - blk <<= 9; //SD stadand capability card use 512 unit. - num = ((num-1)<<9) + blk; - } - else { - num = blk + num - 1; - } - - ret = sd_send_cmd_r1(sdc, 0x40|32, blk, 0); // cmd32 - if (!ret) { - ret = sd_send_cmd_r1(sdc, 0x40|33, num, 0); // cmd33 - if (!ret) { - ret = sd_send_cmd_r1(sdc, 0x40|38, 0, 1); // cmd38 - } - } - - return ret; + int ret; + sdc_t* sdc = (sdc_t*)handle; + + if (sdc->card_type == SD_TYPE) { + blk <<= 9; //SD stadand capability card use 512 unit. + num = ((num-1)<<9) + blk; + } + else { + num = blk + num - 1; + } + + ret = sd_send_cmd_r1(sdc, 0x40|32, blk, 0); // cmd32 + if (!ret) { + ret = sd_send_cmd_r1(sdc, 0x40|33, num, 0); // cmd33 + if (!ret) { + ret = sd_send_cmd_r1(sdc, 0x40|38, 0, 1); // cmd38 + } + } + + return ret; } int sdc_get_sector_num(HSDC handle) { - return ((sdc_t*)handle)->sectors; + return ((sdc_t*)handle)->sectors; } static int sd_send_cmd9(sdc_t* sdc) { - int ret; - unsigned int intst; - unsigned int resp0; - unsigned int resp1; - unsigned int resp2; - unsigned int resp3; - unsigned int base = sdc->ip_base; - unsigned int C_SIZE; - unsigned int C_SIZE_MULT; - unsigned int READ_BL_LEN; - - ret = synopmob_execute_command(base, 0xC9, sdc->rca<<16); - if (!ret) { - ret = synopmob_wait_command_done(base, &intst, INTMSK_CMD_DONE); - if (!ret) { - synopmob_set_register(base+RINTSTS, intst); - ret = synopmob_handle_standard_rinsts(intst); - if (!ret) { - sdc->csd[0] = resp0 = synopmob_read_register(base+RESP0); - sdc->csd[1] = resp1 = synopmob_read_register(base+RESP1); - sdc->csd[2] = resp2 = synopmob_read_register(base+RESP2); - sdc->csd[3] = resp3 = synopmob_read_register(base+RESP3); - - if ((resp3>>30) == 0) { //CSD version 1.0 - C_SIZE = (resp1 >> 30) | ((resp2 & 0x3ff)<<2); - C_SIZE_MULT = ((resp1 >> 15) & 0x07); - READ_BL_LEN = ((resp2 >> 16) & 0xf); - sdc->sectors = ((((C_SIZE+1)<<(C_SIZE_MULT+2))<<(READ_BL_LEN))>>9); - } - else { //CSD version 2.0 - sdc->sectors = (((resp1 >> 16)+1)<<10); - } - } - } - } - - return ret; + int ret; + unsigned int intst; + unsigned int resp0; + unsigned int resp1; + unsigned int resp2; + unsigned int resp3; + unsigned int base = sdc->ip_base; + unsigned int C_SIZE; + unsigned int C_SIZE_MULT; + unsigned int READ_BL_LEN; + + ret = synopmob_execute_command(base, 0xC9, sdc->rca<<16); + if (!ret) { + ret = synopmob_wait_command_done(base, &intst, INTMSK_CMD_DONE); + if (!ret) { + synopmob_set_register(base+RINTSTS, intst); + ret = synopmob_handle_standard_rinsts(intst); + if (!ret) { + sdc->csd[0] = resp0 = synopmob_read_register(base+RESP0); + sdc->csd[1] = resp1 = synopmob_read_register(base+RESP1); + sdc->csd[2] = resp2 = synopmob_read_register(base+RESP2); + sdc->csd[3] = resp3 = synopmob_read_register(base+RESP3); + + if ((resp3>>30) == 0) { //CSD version 1.0 + C_SIZE = (resp1 >> 30) | ((resp2 & 0x3ff)<<2); + C_SIZE_MULT = ((resp1 >> 15) & 0x07); + READ_BL_LEN = ((resp2 >> 16) & 0xf); + sdc->sectors = ((((C_SIZE+1)<<(C_SIZE_MULT+2))<<(READ_BL_LEN))>>9); + } + else { //CSD version 2.0 + sdc->sectors = (((resp1 >> 16)+1)<<10); + } + } + } + } + + return ret; } static int sd_send_cmd5(sdc_t* sdc, unsigned int arg, unsigned int* resp) { - unsigned int cmd_reg = 0x45; - unsigned int intst; - int ret; - unsigned int base = sdc->ip_base; - - ret = synopmob_execute_command(base, cmd_reg, arg); - if (!ret) { - ret = synopmob_wait_command_done(base, &intst, INTMSK_CMD_DONE); - if (!ret) { - synopmob_set_register(base+RINTSTS, intst); - ret = synopmob_handle_standard_rinsts(intst); - if (!ret) { - *resp = synopmob_read_register(base+RESP0); - } - } - } - - return ret; + unsigned int cmd_reg = 0x45; + unsigned int intst; + int ret; + unsigned int base = sdc->ip_base; + + ret = synopmob_execute_command(base, cmd_reg, arg); + if (!ret) { + ret = synopmob_wait_command_done(base, &intst, INTMSK_CMD_DONE); + if (!ret) { + synopmob_set_register(base+RINTSTS, intst); + ret = synopmob_handle_standard_rinsts(intst); + if (!ret) { + *resp = synopmob_read_register(base+RESP0); + } + } + } + + return ret; } static int sd_send_cmd8(sdc_t* sdc) { - int ret; - unsigned int cmd_reg = 0x48; - unsigned int intst; - unsigned int err = 0; - unsigned int base = sdc->ip_base; - - ret = synopmob_execute_command(base, cmd_reg, 0x000001A5); - if (!ret) { - while (1) { - ret = synopmob_wait_command_done(base, &intst, 0); - if (!ret) { - synopmob_set_register(base+RINTSTS, intst); - err |= synopmob_handle_standard_rinsts(intst); - if (intst & INTMSK_CMD_DONE) { - break; - } - } - } - } - - return err; + int ret; + unsigned int cmd_reg = 0x48; + unsigned int intst; + unsigned int err = 0; + unsigned int base = sdc->ip_base; + + ret = synopmob_execute_command(base, cmd_reg, 0x000001A5); + if (!ret) { + while (1) { + ret = synopmob_wait_command_done(base, &intst, 0); + if (!ret) { + synopmob_set_register(base+RINTSTS, intst); + err |= synopmob_handle_standard_rinsts(intst); + if (intst & INTMSK_CMD_DONE) { + break; + } + } + } + } + + return err; } static int sd_send_acmd41(sdc_t* sdc, int* hcs) { - unsigned int cmd_reg = 0x69; - unsigned int resp; - int ret = 0; - unsigned int count = ACMD41_RETRY_COUNT; - unsigned int cmd_arg = 0xff8000; - unsigned int base = sdc->ip_base; - - if (*hcs) { - cmd_arg |= (1<<30); - } - while ( count > 0) { - SDC_WHERE(); - ret = sd_send_cmd55(sdc); - if (ret) - break; - - SDC_WHERE(); - ret = synopmob_execute_command(base, cmd_reg, cmd_arg); - if (ret) - break; - - SDC_WHERE(); - ret = synopmob_wait_command_done(base, &resp, INTMSK_CMD_DONE); - if ( ret ) - break; - - SDC_WHERE(); - synopmob_set_register(base+RINTSTS, resp); - ret = synopmob_handle_standard_rinsts(resp); - if (!ret) { - SDC_WHERE(); - resp = synopmob_read_register(base+RESP0); - if (resp & 0x80000000) { //card is ready. - SDC_WHERE(); - if ( !(resp & (1<<30)) ) { - SDC_WHERE(); - *hcs = 0; - } - if ( (resp & 0x00ff8000) != 0x00ff8000 ) { //not supported voltage - ret = ERRHARDWARE; - } - break; - } - } - - --count; - plat_loop(1); - } - - if (!count) - ret = ERRACMD41TIMEOUT; - - return ret; + unsigned int cmd_reg = 0x69; + unsigned int resp; + int ret = 0; + unsigned int count = ACMD41_RETRY_COUNT; + unsigned int cmd_arg = 0xff8000; + unsigned int base = sdc->ip_base; + + if (*hcs) { + cmd_arg |= (1<<30); + } + while ( count > 0) { + SDC_WHERE(); + ret = sd_send_cmd55(sdc); + if (ret) + break; + + SDC_WHERE(); + ret = synopmob_execute_command(base, cmd_reg, cmd_arg); + if (ret) + break; + + SDC_WHERE(); + ret = synopmob_wait_command_done(base, &resp, INTMSK_CMD_DONE); + if ( ret ) + break; + + SDC_WHERE(); + synopmob_set_register(base+RINTSTS, resp); + ret = synopmob_handle_standard_rinsts(resp); + if (!ret) { + SDC_WHERE(); + resp = synopmob_read_register(base+RESP0); + if (resp & 0x80000000) { //card is ready. + SDC_WHERE(); + if ( !(resp & (1<<30)) ) { + SDC_WHERE(); + *hcs = 0; + } + if ( (resp & 0x00ff8000) != 0x00ff8000 ) { //not supported voltage + ret = ERRHARDWARE; + } + break; + } + } + + --count; + plat_loop(1); + } + + if (!count) + ret = ERRACMD41TIMEOUT; + + return ret; } static int sd_send_acmd51(sdc_t* sdc) //Send SCR { - unsigned int cmd_reg = 0x2273; - unsigned int resp; - int ret; - unsigned int intst = 0; - unsigned int entries; - int count = 1; - unsigned int base = sdc->ip_base; - - ret = sd_send_cmd55(sdc); - if (!ret) { - synopmob_set_register(base+BLKSIZ, 8); - synopmob_set_register(base+BYTCNT, 8); - ret = synopmob_execute_command(base, cmd_reg, 0); - if (!ret) { - while (1) { - ret = synopmob_wait_command_done(base, &intst, 0); - if (ret) { - break; - } - - ret = synopmob_handle_standard_rinsts(intst); - if (ret) { - break; - } - - if (intst & INTMSK_CMD_DONE) { - resp = synopmob_read_register(base+RESP0); - ret = synopmob_check_r1_resp(resp); - if (ret) - break; - } - - if (intst & INTMSK_DAT_OVER) { - entries = synopmob_read_register(base + STATUS); - if (GET_FIFO_COUNT(entries) == 2) { - while (count >= 0) { - entries = synopmob_read_register(base + FIFODAT); - sdc->scr[count--] = BE32_TO_CPU(entries); - } - } - break; - } - - synopmob_set_register(base+RINTSTS, intst); - intst = 0; - } - - if (intst) { - synopmob_set_register(base+RINTSTS, intst); - } - } - - synopmob_set_register(base+BLKSIZ, 512); - synopmob_set_register(base+BYTCNT, 512); - } - - return ret; + unsigned int cmd_reg = 0x2273; + unsigned int resp; + int ret; + unsigned int intst = 0; + unsigned int entries; + int count = 1; + unsigned int base = sdc->ip_base; + + ret = sd_send_cmd55(sdc); + if (!ret) { + synopmob_set_register(base+BLKSIZ, 8); + synopmob_set_register(base+BYTCNT, 8); + ret = synopmob_execute_command(base, cmd_reg, 0); + if (!ret) { + while (1) { + ret = synopmob_wait_command_done(base, &intst, 0); + if (ret) { + break; + } + + ret = synopmob_handle_standard_rinsts(intst); + if (ret) { + break; + } + + if (intst & INTMSK_CMD_DONE) { + resp = synopmob_read_register(base+RESP0); + ret = synopmob_check_r1_resp(resp); + if (ret) + break; + } + + if (intst & INTMSK_DAT_OVER) { + entries = synopmob_read_register(base + STATUS); + if (GET_FIFO_COUNT(entries) == 2) { + while (count >= 0) { + entries = synopmob_read_register(base + FIFODAT); + sdc->scr[count--] = BE32_TO_CPU(entries); + } + } + break; + } + + synopmob_set_register(base+RINTSTS, intst); + intst = 0; + } + + if (intst) { + synopmob_set_register(base+RINTSTS, intst); + } + } + + synopmob_set_register(base+BLKSIZ, 512); + synopmob_set_register(base+BYTCNT, 512); + } + + return ret; } -static int sd_send_cmd6(sdc_t* sdc, unsigned int cmd_arg, unsigned int* data_buff) +static int sd_send_cmd6(sdc_t* sdc, unsigned int cmd_arg, unsigned int* data_buff) { - unsigned int cmd_reg = 0x2246; - unsigned int resp; - int ret; - unsigned int intst = 0; - unsigned int entries; - int count = 64; - unsigned int base = sdc->ip_base; - - synopmob_set_register(base+BLKSIZ, 64); - synopmob_set_register(base+BYTCNT, 64); - ret = synopmob_execute_command(base, cmd_reg, cmd_arg); - if (!ret) { - while (1) { - ret = synopmob_wait_command_done(base, &intst, 0); - if (ret) { - break; - } - - ret = synopmob_handle_standard_rinsts(intst); - if (ret) { - break; - } - - if (intst & INTMSK_CMD_DONE) { - resp = synopmob_read_register(base+RESP0); - ret = synopmob_check_r1_resp(resp); - if (ret) - break; - } - - while (count > 0) { - entries = synopmob_read_register(base + STATUS); - if ( !GET_FIFO_COUNT(entries) ) { - break; - } - *(data_buff++) = synopmob_read_register(base + FIFODAT); - count -= 4; - } - - if (intst & INTMSK_DAT_OVER) { - break; - } - - synopmob_set_register(base+RINTSTS, intst); //write to clear - intst = 0; - } - - if (intst) { - synopmob_set_register(base+RINTSTS, intst); //write to clear - } - } - - synopmob_set_register(base+BLKSIZ, 512); - synopmob_set_register(base+BYTCNT, 512); - - return ret; + unsigned int cmd_reg = 0x2246; + unsigned int resp; + int ret; + unsigned int intst = 0; + unsigned int entries; + int count = 64; + unsigned int base = sdc->ip_base; + + synopmob_set_register(base+BLKSIZ, 64); + synopmob_set_register(base+BYTCNT, 64); + ret = synopmob_execute_command(base, cmd_reg, cmd_arg); + if (!ret) { + while (1) { + ret = synopmob_wait_command_done(base, &intst, 0); + if (ret) { + break; + } + + ret = synopmob_handle_standard_rinsts(intst); + if (ret) { + break; + } + + if (intst & INTMSK_CMD_DONE) { + resp = synopmob_read_register(base+RESP0); + ret = synopmob_check_r1_resp(resp); + if (ret) + break; + } + + while (count > 0) { + entries = synopmob_read_register(base + STATUS); + if ( !GET_FIFO_COUNT(entries) ) { + break; + } + *(data_buff++) = synopmob_read_register(base + FIFODAT); + count -= 4; + } + + if (intst & INTMSK_DAT_OVER) { + break; + } + + synopmob_set_register(base+RINTSTS, intst); //write to clear + intst = 0; + } + + if (intst) { + synopmob_set_register(base+RINTSTS, intst); //write to clear + } + } + + synopmob_set_register(base+BLKSIZ, 512); + synopmob_set_register(base+BYTCNT, 512); + + return ret; } static int synopmob_send_clock_only_cmd(unsigned int base) { - return synopmob_execute_command(base, 0x202000, 0); + return synopmob_execute_command(base, 0x202000, 0); } static int synopmob_disable_all_clocks(unsigned int base) { - synopmob_set_register(base+CLKENA, 0); - return synopmob_send_clock_only_cmd(base); + synopmob_set_register(base+CLKENA, 0); + return synopmob_send_clock_only_cmd(base); } static int synopmob_enable_clocks_with_val(unsigned int base, unsigned int val) { - synopmob_set_register(base+CLKENA, val); - return synopmob_send_clock_only_cmd(base); + synopmob_set_register(base+CLKENA, val); + return synopmob_send_clock_only_cmd(base); } static int synopmob_set_clk_freq(sdc_t* sdc, unsigned int divider) { - #define MAX_DIVIDER_VALUE 0xff - - unsigned int orig_clkena; - int retval; - unsigned int base = sdc->ip_base; - - if (divider > MAX_DIVIDER_VALUE) { - return 0xffffffff; - } - - /* To make sure we dont disturb enable/disable settings of the cards*/ - orig_clkena = synopmob_read_register(base+CLKENA); - - /* Disable all clocks before changing frequency the of card clocks */ - if ((retval = synopmob_disable_all_clocks(base)) != 0) { - return retval; - } - /* Program the clock divider in our case it is divider 0 */ - synopmob_clear_bits(base+CLKDIV, MAX_DIVIDER_VALUE); - synopmob_set_bits(base+CLKDIV, divider); - - /*Send the command to CIU using synopmob_send_clock_only_cmd and enable the clocks in CLKENA register */ - if ((retval = synopmob_send_clock_only_cmd(base)) != 0) { - synopmob_enable_clocks_with_val(base, orig_clkena); - return retval; - } - - return synopmob_enable_clocks_with_val(base, orig_clkena); + #define MAX_DIVIDER_VALUE 0xff + + unsigned int orig_clkena; + int retval; + unsigned int base = sdc->ip_base; + + if (divider > MAX_DIVIDER_VALUE) { + return 0xffffffff; + } + + /* To make sure we dont disturb enable/disable settings of the cards*/ + orig_clkena = synopmob_read_register(base+CLKENA); + + /* Disable all clocks before changing frequency the of card clocks */ + if ((retval = synopmob_disable_all_clocks(base)) != 0) { + return retval; + } + /* Program the clock divider in our case it is divider 0 */ + synopmob_clear_bits(base+CLKDIV, MAX_DIVIDER_VALUE); + synopmob_set_bits(base+CLKDIV, divider); + + /*Send the command to CIU using synopmob_send_clock_only_cmd and enable the clocks in CLKENA register */ + if ((retval = synopmob_send_clock_only_cmd(base)) != 0) { + synopmob_enable_clocks_with_val(base, orig_clkena); + return retval; + } + + return synopmob_enable_clocks_with_val(base, orig_clkena); } static int enum_sd_card(sdc_t* sdc) { - int ret; - int count = 1000; - int hcs = 0; - unsigned int buffer[16]; - unsigned int base = sdc->ip_base; - - if (synopmob_read_register(base+CDETECT) & 1) { - return ERRCARDNOTCONN; - } - - #if 0 - synopmob_set_bits(0x98500004, (1<<24)); //set to output mode - synopmob_set_bits(0x98500000, (1<<24)); //power off - plat_loop(1000000/5); //Lets give some ramp down period - synopmob_clear_bits(0x98500000, (1<<24)); //power on - plat_loop(1000000/5);//Lets give some ramp down period - #endif - - synopmob_set_register(base+CTYPE, ONE_BIT_MODE); - - synopmob_set_register(base+CLKENA, 0x00000001); /*enable clock, non-low-power mode*/ - ret = synopmob_set_clk_freq(sdc, MMC_FOD_DIVIDER_VALUE); - - if ( !ret ) { - plat_loop(1000); //enough for 74 clock. - SDC_WHERE(); - ret = sd_send_cmd0(sdc); //CMD0 has no response - } - - if ( !ret ) { - SDC_WHERE(); - ret = sd_send_cmd8(sdc); //even if CMD8 get response, it may be V1.0 card. - if (!ret) { - hcs = 1; - } - SDC_WHERE(); - ret = sd_send_acmd41(sdc, &hcs); - } - - if (!ret) { - SDC_WHERE(); - ret = sd_send_cmd2(sdc); //CID - } - - if (!ret) { - SDC_WHERE(); - ret = sd_send_cmd3(sdc); //get RCA - } - - if (!ret) { - SDC_WHERE(); - ret = sd_send_cmd9(sdc); //CSD - } - - if (!ret) { - SDC_WHERE(); - ret = sd_send_cmd7(sdc); //select the card - } - - if (!ret && (sdc->wkmod & SDC_WKMOD_4WIRE) ) { - SDC_WHERE(); - ret = sd_send_acmd51(sdc); //SCR - if (!ret && (sdc->scr[1] & 0x00040000)) { // 4bit mode supported? - ret = sd_send_acmd6(sdc, 4); //switch to 4bit mode - } - } - - if (!ret && (sdc->wkmod & SDC_WKMOD_50M_HI_SPEED) && (sdc->csd[2] & 0x40000000) ) { //judge whether class10 is supported? CMD6 is belonging to class10. - SDC_WHERE(); - ret = sd_send_cmd6(sdc, 0x00fffff1, buffer); //switch to high speed mode. - if ( !ret && (*(((unsigned char*)buffer)+13)&0x02) ) { //the card support high speed mode? - SDC_WHERE(); - ret = sd_send_cmd6(sdc, 0x80fffff1, buffer); //switch to high speed mode. - if (!ret && ((*(((unsigned char*)buffer)+16) & 0xf) == 1) ) { - //switch to high speed mode sucess. - sd_send_uncmd7(sdc); //deselect the card - sd_send_cmd9(sdc); //CSD - ret = sd_send_cmd7(sdc); //select the card - } - } - } - - if (!ret && (sdc->wkmod & (SDC_WKMOD_50M_HI_SPEED|SDC_WKMOD_25M_STAND_SPEED))) { - if ( (sdc->csd[3] & 0xff) == 0x5A ) { //50MHz high speed mode. - SDC_WHERE(); - ret = synopmob_set_clk_freq(sdc, (((CIU_CLK)/(50000*2)))); - } - else if ( (sdc->csd[3] & 0xff) == 0x32 ) { - SDC_WHERE(); //25MHz standard speed mode. - ret = synopmob_set_clk_freq(sdc, sdc_clk_divider/*ONE_BIT_BUS_FREQ*/); - } - } - - if (!ret) { - sdc->card_type = SD_TYPE; - if (hcs) { - sdc->card_type = SD_2_0_TYPE; - } - } - - return ret; + int ret; + int count = 1000; + int hcs = 0; + unsigned int buffer[16]; + unsigned int base = sdc->ip_base; + + if (synopmob_read_register(base+CDETECT) & 1) { + return ERRCARDNOTCONN; + } + + #if 0 + synopmob_set_bits(0x98500004, (1<<24)); //set to output mode + synopmob_set_bits(0x98500000, (1<<24)); //power off + plat_loop(1000000/5); //Lets give some ramp down period + synopmob_clear_bits(0x98500000, (1<<24)); //power on + plat_loop(1000000/5);//Lets give some ramp down period + #endif + + synopmob_set_register(base+CTYPE, ONE_BIT_MODE); + + synopmob_set_register(base+CLKENA, 0x00000001); /*enable clock, non-low-power mode*/ + ret = synopmob_set_clk_freq(sdc, MMC_FOD_DIVIDER_VALUE); + + if ( !ret ) { + plat_loop(1000); //enough for 74 clock. + SDC_WHERE(); + ret = sd_send_cmd0(sdc); //CMD0 has no response + } + + if ( !ret ) { + SDC_WHERE(); + ret = sd_send_cmd8(sdc); //even if CMD8 get response, it may be V1.0 card. + if (!ret) { + hcs = 1; + } + SDC_WHERE(); + ret = sd_send_acmd41(sdc, &hcs); + } + + if (!ret) { + SDC_WHERE(); + ret = sd_send_cmd2(sdc); //CID + } + + if (!ret) { + SDC_WHERE(); + ret = sd_send_cmd3(sdc); //get RCA + } + + if (!ret) { + SDC_WHERE(); + ret = sd_send_cmd9(sdc); //CSD + } + + if (!ret) { + SDC_WHERE(); + ret = sd_send_cmd7(sdc); //select the card + } + + if (!ret && (sdc->wkmod & SDC_WKMOD_4WIRE) ) { + SDC_WHERE(); + ret = sd_send_acmd51(sdc); //SCR + if (!ret && (sdc->scr[1] & 0x00040000)) { // 4bit mode supported? + ret = sd_send_acmd6(sdc, 4); //switch to 4bit mode + } + } + + if (!ret && (sdc->wkmod & SDC_WKMOD_50M_HI_SPEED) && (sdc->csd[2] & 0x40000000) ) { //judge whether class10 is supported? CMD6 is belonging to class10. + SDC_WHERE(); + ret = sd_send_cmd6(sdc, 0x00fffff1, buffer); //switch to high speed mode. + if ( !ret && (*(((unsigned char*)buffer)+13)&0x02) ) { //the card support high speed mode? + SDC_WHERE(); + ret = sd_send_cmd6(sdc, 0x80fffff1, buffer); //switch to high speed mode. + if (!ret && ((*(((unsigned char*)buffer)+16) & 0xf) == 1) ) { + //switch to high speed mode sucess. + sd_send_uncmd7(sdc); //deselect the card + sd_send_cmd9(sdc); //CSD + ret = sd_send_cmd7(sdc); //select the card + } + } + } + + if (!ret && (sdc->wkmod & (SDC_WKMOD_50M_HI_SPEED|SDC_WKMOD_25M_STAND_SPEED))) { + if ( (sdc->csd[3] & 0xff) == 0x5A ) { //50MHz high speed mode. + SDC_WHERE(); + ret = synopmob_set_clk_freq(sdc, (((CIU_CLK)/(50000*2)))); + } + else if ( (sdc->csd[3] & 0xff) == 0x32 ) { + SDC_WHERE(); //25MHz standard speed mode. + ret = synopmob_set_clk_freq(sdc, sdc_clk_divider/*ONE_BIT_BUS_FREQ*/); + } + } + + if (!ret) { + sdc->card_type = SD_TYPE; + if (hcs) { + sdc->card_type = SD_2_0_TYPE; + } + } + + return ret; } int sdio_drv_creg_read(HSDC handle, int addr, int fn, unsigned int *resp) { - sdc_t* sdc = (sdc_t*)handle; - unsigned int arg; - unsigned int cmd_reg = 0x74; - unsigned int intst; - int ret; - unsigned int base = sdc->ip_base; - rt_err_t err; + sdc_t* sdc = (sdc_t*)handle; + unsigned int arg; + unsigned int cmd_reg = 0x74; + unsigned int intst; + int ret; + unsigned int base = sdc->ip_base; + rt_err_t err; if(resp) { *resp = 0; } - - err = rt_sem_take(sdc->mutex, RT_WAITING_FOREVER); - if (err != RT_EOK) { - return ERRNORES; - } - - arg = (fn << 28) | (addr << 9); - ret = synopmob_execute_command(base, cmd_reg, arg); - if (!ret) { - ret = synopmob_wait_command_done(base, &intst, INTMSK_CMD_DONE); - if (!ret) { - synopmob_set_register(base+RINTSTS, intst); //write to clear - ret = synopmob_handle_standard_rinsts(intst); - if (!ret) { - *resp = synopmob_read_register(base+RESP0); - ret = synopmob_check_r5_resp(*resp); - } - } - } - - rt_sem_release(sdc->mutex); - - if (ret) { - ret++; - ret--; - SDIO_PRINTF("sdio_drv_creg_read fail:, ret = %d\n", ret); - } - - return ret; + + err = rt_sem_take(sdc->mutex, RT_WAITING_FOREVER); + if (err != RT_EOK) { + return ERRNORES; + } + + arg = (fn << 28) | (addr << 9); + ret = synopmob_execute_command(base, cmd_reg, arg); + if (!ret) { + ret = synopmob_wait_command_done(base, &intst, INTMSK_CMD_DONE); + if (!ret) { + synopmob_set_register(base+RINTSTS, intst); //write to clear + ret = synopmob_handle_standard_rinsts(intst); + if (!ret) { + *resp = synopmob_read_register(base+RESP0); + ret = synopmob_check_r5_resp(*resp); + } + } + } + + rt_sem_release(sdc->mutex); + + if (ret) { + ret++; + ret--; + SDIO_PRINTF("sdio_drv_creg_read fail:, ret = %d\n", ret); + } + + return ret; } int sdio_drv_creg_write(HSDC handle, int addr, int fn, unsigned char data, unsigned int *resp) { - sdc_t* sdc = (sdc_t*)handle; - unsigned int arg; - unsigned int cmd_reg = 0x74; - unsigned int intst; - int ret; - unsigned int base = sdc->ip_base; - rt_err_t err; - - err = rt_sem_take(sdc->mutex, RT_WAITING_FOREVER); - if (err != RT_EOK) { - return ERRNORES; - } - - arg = (1 << 31) | (fn << 28) | (1 << 27) | (addr << 9) | data; - ret = synopmob_execute_command(base, cmd_reg, arg); - if (!ret) { - ret = synopmob_wait_command_done(base, &intst, INTMSK_CMD_DONE); - if (!ret) { - synopmob_set_register(base+RINTSTS, intst); //write to clear - ret = synopmob_handle_standard_rinsts(intst); - if (!ret) { - *resp = synopmob_read_register(base+RESP0); - ret = synopmob_check_r5_resp(*resp); - } - } - } - - rt_sem_release(sdc->mutex); - if (ret) { - ret++; - ret--; - SDIO_PRINTF("sdio_drv_creg_write fail:, ret = %d\n", ret); - } - - return ret; + sdc_t* sdc = (sdc_t*)handle; + unsigned int arg; + unsigned int cmd_reg = 0x74; + unsigned int intst; + int ret; + unsigned int base = sdc->ip_base; + rt_err_t err; + + err = rt_sem_take(sdc->mutex, RT_WAITING_FOREVER); + if (err != RT_EOK) { + return ERRNORES; + } + + arg = (1 << 31) | (fn << 28) | (1 << 27) | (addr << 9) | data; + ret = synopmob_execute_command(base, cmd_reg, arg); + if (!ret) { + ret = synopmob_wait_command_done(base, &intst, INTMSK_CMD_DONE); + if (!ret) { + synopmob_set_register(base+RINTSTS, intst); //write to clear + ret = synopmob_handle_standard_rinsts(intst); + if (!ret) { + *resp = synopmob_read_register(base+RESP0); + ret = synopmob_check_r5_resp(*resp); + } + } + } + + rt_sem_release(sdc->mutex); + if (ret) { + ret++; + ret--; + SDIO_PRINTF("sdio_drv_creg_write fail:, ret = %d\n", ret); + } + + return ret; } #define ARC_REG_DC_IVDL 0x4A @@ -1184,153 +1184,153 @@ extern void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size); extern void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size); void inv_dcache_range(unsigned long start, unsigned long len) { - mmu_invalidate_dcache(start, len); + mmu_invalidate_dcache(start, len); } void flush_dcache_range(unsigned long start, unsigned long len) { - mmu_clean_dcache(start, len); + mmu_clean_dcache(start, len); } int g_use_bcm43362 = 0; static int sdio_drv_read_write(sdc_t* sdc, unsigned int rw, unsigned int addr, unsigned int fn, unsigned int bcnt, - unsigned int bsize, unsigned char *buf) + unsigned int bsize, unsigned char *buf) { - volatile DmaDesc *pDmaDesc = sdc->pDmaDesc; - int ret; - unsigned int intsts = 0; - unsigned int cmd = 0x2275; - unsigned int base = sdc->ip_base; - unsigned int arg; - unsigned int num; - int loop_for_command_done_check = 10000;//DATA_TRANSFER_OVER_TIMEOUT_USEC; - rt_err_t err; + volatile DmaDesc *pDmaDesc = sdc->pDmaDesc; + int ret; + unsigned int intsts = 0; + unsigned int cmd = 0x2275; + unsigned int base = sdc->ip_base; + unsigned int arg; + unsigned int num; + int loop_for_command_done_check = 10000;//DATA_TRANSFER_OVER_TIMEOUT_USEC; + rt_err_t err; //SDIO_PRINTF("------- %s, line %d buf = %08x size = %d -------\n", __FUNCTION__, __LINE__, buf, bsize); - arg = (fn << 28) | (addr << 9); - - if (g_use_bcm43362) { - arg |= (1 << 26); //OPcode = 1............, for AP6181. - } - - if (bcnt == 1 && bsize <= 512) - arg |= (bsize & 0x1ff); - else - arg |= ((1 << 27) | bcnt); - if ( rw ) { - cmd |= 0x400; - arg |= (1 << 31); - } - num = bsize*bcnt; - - if ( rw ) { - flush_dcache_range((unsigned long)buf, num); - } - else { - inv_dcache_range((unsigned long)buf, num); - } - - err = rt_sem_take(sdc->mutex, RT_WAITING_FOREVER); - if (err != RT_EOK) { - return ERRNORES; - } + arg = (fn << 28) | (addr << 9); + + if (g_use_bcm43362) { + arg |= (1 << 26); //OPcode = 1............, for AP6181. + } + + if (bcnt == 1 && bsize <= 512) + arg |= (bsize & 0x1ff); + else + arg |= ((1 << 27) | bcnt); + if ( rw ) { + cmd |= 0x400; + arg |= (1 << 31); + } + num = bsize*bcnt; + + if ( rw ) { + flush_dcache_range((unsigned long)buf, num); + } + else { + inv_dcache_range((unsigned long)buf, num); + } + + err = rt_sem_take(sdc->mutex, RT_WAITING_FOREVER); + if (err != RT_EOK) { + return ERRNORES; + } //synopmob_set_bits(base+FIFOTH, 0x2 << 28); - // reset - synopmob_set_bits(base+CTRL, FIFO_RESET); //reset FIFO - while (synopmob_read_register(base+CTRL) & FIFO_RESET); - synopmob_set_register(base + RINTSTS, 0xfffe); //clear interrupts - - //pDmaDesc->desc0 = 0; - pDmaDesc->desc0 |= DescOwnByDma | DescFirstDesc | DescLastDesc; - pDmaDesc->desc1 = ((num << DescBuf1SizeShift) & DescBuf1SizMsk); - pDmaDesc->desc2 = (unsigned int)buf; - //pDmaDesc->desc3 = 0; - flush_dcache_range((unsigned int)pDmaDesc, sizeof(DmaDesc)); - synopmob_set_register(base+DBADDR, (unsigned int)pDmaDesc); - synopmob_set_register(base+BLKSIZ, bsize); - synopmob_set_register(base+BYTCNT, num); - synopmob_set_bits(base + CTRL, CTRL_USE_IDMAC); - synopmob_set_bits(base + BMOD,BMOD_DE); + // reset + synopmob_set_bits(base+CTRL, FIFO_RESET); //reset FIFO + while (synopmob_read_register(base+CTRL) & FIFO_RESET); + synopmob_set_register(base + RINTSTS, 0xfffe); //clear interrupts + + //pDmaDesc->desc0 = 0; + pDmaDesc->desc0 |= DescOwnByDma | DescFirstDesc | DescLastDesc; + pDmaDesc->desc1 = ((num << DescBuf1SizeShift) & DescBuf1SizMsk); + pDmaDesc->desc2 = (unsigned int)buf; + //pDmaDesc->desc3 = 0; + flush_dcache_range((unsigned int)pDmaDesc, sizeof(DmaDesc)); + synopmob_set_register(base+DBADDR, (unsigned int)pDmaDesc); + synopmob_set_register(base+BLKSIZ, bsize); + synopmob_set_register(base+BYTCNT, num); + synopmob_set_bits(base + CTRL, CTRL_USE_IDMAC); + synopmob_set_bits(base + BMOD,BMOD_DE); //SDIO_PRINTF("pDmaDesc = %08x, %08x / %08x / %08x / %08x\n", pDmaDesc, pDmaDesc->desc0, pDmaDesc->desc1, pDmaDesc->desc2, pDmaDesc->desc3); - ret = synopmob_execute_command(base, cmd, arg); - if ( !ret ) { - ret = ERRIDMA; - err = rt_sem_take(sdc->sem, DMA_TRANSFER_TIMEOUT_TICKS); - if ( !err ) { - while (--loop_for_command_done_check > 0) { - intsts = synopmob_read_register(base+RINTSTS); - if ((intsts & (INTMSK_CMD_DONE|INTMSK_DAT_OVER)) == (INTMSK_CMD_DONE|INTMSK_DAT_OVER)) { - break; - } - plat_loop(1); - } - ret = synopmob_handle_standard_rinsts(intsts); - if (!ret ) { - if( !loop_for_command_done_check || !(sdc->idsts & 0x100)) { //normal interrupt + ret = synopmob_execute_command(base, cmd, arg); + if ( !ret ) { + ret = ERRIDMA; + err = rt_sem_take(sdc->sem, DMA_TRANSFER_TIMEOUT_TICKS); + if ( !err ) { + while (--loop_for_command_done_check > 0) { + intsts = synopmob_read_register(base+RINTSTS); + if ((intsts & (INTMSK_CMD_DONE|INTMSK_DAT_OVER)) == (INTMSK_CMD_DONE|INTMSK_DAT_OVER)) { + break; + } + plat_loop(1); + } + ret = synopmob_handle_standard_rinsts(intsts); + if (!ret ) { + if( !loop_for_command_done_check || !(sdc->idsts & 0x100)) { //normal interrupt SDIO_PRINTF("------- %s, line %d idsts = %08x check = %d -------\n", __FUNCTION__, __LINE__, sdc->idsts, loop_for_command_done_check); - ret = ERRIDMA; - } - } - else + ret = ERRIDMA; + } + } + else SDIO_PRINTF("------- %s, line %d intsts = %08x buf = %08x -------\n", __FUNCTION__, __LINE__, intsts, buf); - } - } - - if (!ret) { - synopmob_set_register(base + RINTSTS, 0xfffe); //clear interrupts - synopmob_clear_bits(base + CTRL, CTRL_USE_IDMAC); - synopmob_clear_bits(base + BMOD,BMOD_DE); - synopmob_set_register(base+BLKSIZ, 512); - synopmob_set_register(base+BYTCNT, 512); - } - else { - char* op = "read"; - if (rw) - op = "write"; - + } + } + + if (!ret) { + synopmob_set_register(base + RINTSTS, 0xfffe); //clear interrupts + synopmob_clear_bits(base + CTRL, CTRL_USE_IDMAC); + synopmob_clear_bits(base + BMOD,BMOD_DE); + synopmob_set_register(base+BLKSIZ, 512); + synopmob_set_register(base+BYTCNT, 512); + } + else { + char* op = "read"; + if (rw) + op = "write"; + SDIO_PRINTF("sdio_drv_read_write1(%s) fail:, ret = %d\n", op, ret); - } - - if ( rw && !ret ) { //write - ret = synopmob_wait_data_ready(base); - } - - rt_sem_release(sdc->mutex); - - if ( !rw && !ret ) { //read - inv_dcache_range((unsigned long)buf, num); - } - + } + + if ( rw && !ret ) { //write + ret = synopmob_wait_data_ready(base); + } + + rt_sem_release(sdc->mutex); + + if ( !rw && !ret ) { //read + inv_dcache_range((unsigned long)buf, num); + } + if (ret) { - char* op = "read"; - if (rw) - op = "write"; - - SDIO_PRINTF("sdio_drv_read_write2(%s) fail:, ret = %d\n", op, ret); + char* op = "read"; + if (rw) + op = "write"; + + SDIO_PRINTF("sdio_drv_read_write2(%s) fail:, ret = %d\n", op, ret); } - return ret; - //return ret ? 0/*false*/ : 1/*true*/; + return ret; + //return ret ? 0/*false*/ : 1/*true*/; } int sdio_drv_read(HSDC handle, unsigned int addr, unsigned int fn, unsigned int bcnt, - unsigned int bsize, unsigned char *buf) + unsigned int bsize, unsigned char *buf) { - return sdio_drv_read_write((sdc_t*)handle, 0, addr, fn, bcnt, bsize, buf); + return sdio_drv_read_write((sdc_t*)handle, 0, addr, fn, bcnt, bsize, buf); } int sdio_drv_write(HSDC handle, unsigned int addr, unsigned int fn, unsigned int bcnt, - unsigned int bsize, unsigned char *buf) + unsigned int bsize, unsigned char *buf) { - return sdio_drv_read_write((sdc_t*)handle, 1, addr, fn, bcnt, bsize, buf); + return sdio_drv_read_write((sdc_t*)handle, 1, addr, fn, bcnt, bsize, buf); } static void dumpchain(DmaDesc *pChain) { int i = 0; DmaDesc *tmp_pChain = pChain; - + while(tmp_pChain && i < 10) { SDIO_PRINTF("[%d]: chain =%p, buf = %p, size = %d, csi = %08x, next = %p\n", i, tmp_pChain, (DmaDesc *)tmp_pChain->desc2, tmp_pChain->desc1, tmp_pChain->desc0, (DmaDesc *)tmp_pChain->desc3); @@ -1346,711 +1346,711 @@ static void dumpchain(DmaDesc *pChain) #if 1 int sdio_drv_chain_write(sdc_t* sdc, unsigned int addr, unsigned int fn, unsigned int bcnt, unsigned int bsize, buf_chain_t *chain) { - int ret; - unsigned int intsts = 0; - unsigned int cmd = 0x2275; - unsigned int base = sdc->ip_base; - unsigned int arg; - unsigned int num; - unsigned int chain_len = 0; - int loop_for_command_done_check = DATA_TRANSFER_OVER_TIMEOUT_USEC; - rt_err_t err; - unsigned int rw = 1; - DmaDesc *tmpDesc = (DmaDesc *)chain; - DmaDesc *lastDesc = (void*)0; - - arg = (fn << 28) | (addr << 9); - if (bcnt == 1 && bsize <= 512) - arg |= (bsize & 0x1ff); - else - arg |= ((1 << 27) | bcnt); - if ( rw ) { - cmd |= 0x400; - arg |= (1 << 31); - } - num = bsize*bcnt; - - err = rt_sem_take(sdc->mutex, RT_WAITING_FOREVER); - if (err != RT_EOK) { - return ERRNORES; - } - - // reset - synopmob_set_bits(base+CTRL, FIFO_RESET); //reset FIFO - while (synopmob_read_register(base+CTRL) & FIFO_RESET); - synopmob_set_register(base + RINTSTS, 0xfffe); //clear interrupts - + int ret; + unsigned int intsts = 0; + unsigned int cmd = 0x2275; + unsigned int base = sdc->ip_base; + unsigned int arg; + unsigned int num; + unsigned int chain_len = 0; + int loop_for_command_done_check = DATA_TRANSFER_OVER_TIMEOUT_USEC; + rt_err_t err; + unsigned int rw = 1; + DmaDesc *tmpDesc = (DmaDesc *)chain; + DmaDesc *lastDesc = (void*)0; + + arg = (fn << 28) | (addr << 9); + if (bcnt == 1 && bsize <= 512) + arg |= (bsize & 0x1ff); + else + arg |= ((1 << 27) | bcnt); + if ( rw ) { + cmd |= 0x400; + arg |= (1 << 31); + } + num = bsize*bcnt; + + err = rt_sem_take(sdc->mutex, RT_WAITING_FOREVER); + if (err != RT_EOK) { + return ERRNORES; + } + + // reset + synopmob_set_bits(base+CTRL, FIFO_RESET); //reset FIFO + while (synopmob_read_register(base+CTRL) & FIFO_RESET); + synopmob_set_register(base + RINTSTS, 0xfffe); //clear interrupts + while(tmpDesc != 0) { // make sure size is little than DescBuf1SizMsk if(tmpDesc->desc1 > (DescBuf1SizMsk >> DescBuf1SizeShift)) { - // TBD... fix me + // TBD... fix me rt_sem_release(sdc->mutex); return 0; } // TBD... fix me, we must align tmpDesc->desc2 to 4 ? - + tmpDesc->desc0 = DescOwnByDma | DescSecAddrChained; - + // is it last node? if(tmpDesc->desc3 == 0 || tmpDesc->desc3 == (unsigned int)chain) { - tmpDesc->desc0 |= DescLastDesc; - lastDesc = tmpDesc; + tmpDesc->desc0 |= DescLastDesc; + lastDesc = tmpDesc; } else { - tmpDesc->desc0 |= DescDisInt; //disable interrupt... + tmpDesc->desc0 |= DescDisInt; //disable interrupt... } - + // is it first node? if((char *)tmpDesc == (char *)chain) { - tmpDesc->desc0 |= DescFirstDesc; - } + tmpDesc->desc0 |= DescFirstDesc; + } flush_dcache_range(tmpDesc->desc2, tmpDesc->desc1); - + tmpDesc = (DmaDesc *)tmpDesc->desc3; chain_len += sizeof(buf_chain_t); if((char *)tmpDesc == (char *)chain) { - break; + break; } } lastDesc->desc3 = (unsigned int)chain; - //FIXME, chain must be continuous arrry. - flush_dcache_range((unsigned long)chain, chain_len); - - synopmob_set_register(base+DBADDR, (unsigned int)(chain)); - - synopmob_set_register(base+BLKSIZ, bsize); - synopmob_set_register(base+BYTCNT, num); - synopmob_set_bits(base + CTRL, CTRL_USE_IDMAC); - synopmob_set_bits(base + BMOD,BMOD_DE); - - ret = synopmob_execute_command(base, cmd, arg); - if ( !ret ) { - ret = ERRIDMA; - err = rt_sem_take(sdc->sem, DMA_TRANSFER_TIMEOUT_TICKS); - if ( !err ) { - while (--loop_for_command_done_check > 0) { - intsts = synopmob_read_register(base+RINTSTS); - if ((intsts & (INTMSK_CMD_DONE|INTMSK_DAT_OVER)) == (INTMSK_CMD_DONE|INTMSK_DAT_OVER)) { - break; - } - plat_loop(1); - } - ret = synopmob_handle_standard_rinsts(intsts); - if (!ret ) { - if( !loop_for_command_done_check || !(sdc->idsts & 0x100)) { //normal interrupt - ret = ERRIDMA; - } - } - } - } - - if (!ret) { - synopmob_set_register(base + RINTSTS, 0xfffe); //clear interrupts - synopmob_clear_bits(base + CTRL, CTRL_USE_IDMAC); - synopmob_clear_bits(base + BMOD,BMOD_DE); - synopmob_set_register(base+BLKSIZ, 512); - synopmob_set_register(base+BYTCNT, 512); - } - else { - char* op = "read"; - if (rw) - op = "write"; - - SDIO_PRINTF("sdio_drv_chain_write1(%s) fail:, ret = %d, bsize = %d * %d\n", op, ret, bsize, bcnt); - dumpchain((DmaDesc *)chain); - } - - if ( rw && !ret ) { - ret = synopmob_wait_data_ready(base); - } - - rt_sem_release(sdc->mutex); - - if (ret) { - ret++; - ret--; - SDIO_PRINTF("sdio_drv_chain_write2, fail:, ret = %d\n", ret); - } - - return ret; - //return ret ? 0/*false*/ : 1/*true*/; + //FIXME, chain must be continuous arrry. + flush_dcache_range((unsigned long)chain, chain_len); + + synopmob_set_register(base+DBADDR, (unsigned int)(chain)); + + synopmob_set_register(base+BLKSIZ, bsize); + synopmob_set_register(base+BYTCNT, num); + synopmob_set_bits(base + CTRL, CTRL_USE_IDMAC); + synopmob_set_bits(base + BMOD,BMOD_DE); + + ret = synopmob_execute_command(base, cmd, arg); + if ( !ret ) { + ret = ERRIDMA; + err = rt_sem_take(sdc->sem, DMA_TRANSFER_TIMEOUT_TICKS); + if ( !err ) { + while (--loop_for_command_done_check > 0) { + intsts = synopmob_read_register(base+RINTSTS); + if ((intsts & (INTMSK_CMD_DONE|INTMSK_DAT_OVER)) == (INTMSK_CMD_DONE|INTMSK_DAT_OVER)) { + break; + } + plat_loop(1); + } + ret = synopmob_handle_standard_rinsts(intsts); + if (!ret ) { + if( !loop_for_command_done_check || !(sdc->idsts & 0x100)) { //normal interrupt + ret = ERRIDMA; + } + } + } + } + + if (!ret) { + synopmob_set_register(base + RINTSTS, 0xfffe); //clear interrupts + synopmob_clear_bits(base + CTRL, CTRL_USE_IDMAC); + synopmob_clear_bits(base + BMOD,BMOD_DE); + synopmob_set_register(base+BLKSIZ, 512); + synopmob_set_register(base+BYTCNT, 512); + } + else { + char* op = "read"; + if (rw) + op = "write"; + + SDIO_PRINTF("sdio_drv_chain_write1(%s) fail:, ret = %d, bsize = %d * %d\n", op, ret, bsize, bcnt); + dumpchain((DmaDesc *)chain); + } + + if ( rw && !ret ) { + ret = synopmob_wait_data_ready(base); + } + + rt_sem_release(sdc->mutex); + + if (ret) { + ret++; + ret--; + SDIO_PRINTF("sdio_drv_chain_write2, fail:, ret = %d\n", ret); + } + + return ret; + //return ret ? 0/*false*/ : 1/*true*/; } #elif 0 int sdio_drv_chain_write(sdc_t* sdc, unsigned int addr, unsigned int fn, unsigned int bcnt, unsigned int bsize, buf_chain_t *chain) { - //static volatile DmaDesc __attribute__ ((aligned(32))) st_pchain[4]; - volatile DmaDesc *st_pchain = (DmaDesc *)0x9a700000; - - int ret; - unsigned int intsts = 0; - unsigned int cmd = 0x2275; - unsigned int base = sdc->ip_base; - unsigned int arg; - unsigned int num; - unsigned int chain_len = 0; - int loop_for_command_done_check = DATA_TRANSFER_OVER_TIMEOUT_USEC; - char err; - unsigned int rw = 1; - - buf_chain_t *usrchain; - unsigned int desc0; - unsigned int length = 0; - - if (!chain) { - return 0; - } - - arg = (fn << 28) | (addr << 9); - if (bcnt == 1 && bsize <= 512) - arg |= (bsize & 0x1ff); - else - arg |= ((1 << 27) | bcnt); - if ( rw ) { - cmd |= 0x400; - arg |= (1 << 31); - } - num = bsize*bcnt; - - OSSemPend(sdc->mutex, 0, &err); - if (err != OS_NO_ERR) { - return ERRNORES; - } - - // reset - synopmob_set_bits(base+CTRL, FIFO_RESET); //reset FIFO - while (synopmob_read_register(base+CTRL) & FIFO_RESET); - synopmob_set_register(base + RINTSTS, 0xfffe); //clear interrupts - - usrchain = chain; - while (1) { - if(usrchain->size > (DescBuf1SizMsk >> DescBuf1SizeShift)) { - // TBD... fix me - OSSemPost (sdc->mutex); - return 0; - } - length += usrchain->size; - desc0 = DescOwnByDma | DescSecAddrChained; - if (!usrchain->next || usrchain->next == chain) { - desc0 |= DescLastDesc; - } - else { - desc0 |= DescDisInt; //disable interrupt... - } - - if(usrchain == chain) { - desc0 |= DescFirstDesc; - } - - st_pchain[chain_len].desc0 = desc0; - st_pchain[chain_len].desc1 = (unsigned int)usrchain->size; - st_pchain[chain_len].desc2 = (unsigned int)usrchain->buf; - st_pchain[chain_len].desc3 = (unsigned int)(&st_pchain[chain_len+1]); - flush_dcache_range((unsigned int)usrchain->buf, usrchain->size); - - usrchain = usrchain->next; - if( !usrchain || usrchain == chain) { - break; - } - if (++chain_len >= 4) { - while(1) SDIO_PRINTF("sdio_drv_chain_write:long chain!\n"); - } - } - st_pchain[chain_len].desc3 = (unsigned int)(&st_pchain[0]); - - if (length != num) { - while (1) SDIO_PRINTF("sdio_drv_chain_write:too long packet!\n"); - } - - synopmob_set_register(base+DBADDR, (unsigned int)(st_pchain)); - - synopmob_set_register(base+BLKSIZ, bsize); - synopmob_set_register(base+BYTCNT, num); - synopmob_set_bits(base + CTRL, CTRL_USE_IDMAC); - synopmob_set_bits(base + BMOD,BMOD_DE); - - ret = synopmob_execute_command(base, cmd, arg); - if ( !ret ) { - ret = ERRIDMA; - OSSemPend(sdc->sem, DMA_TRANSFER_TIMEOUT_TICKS, &err); - if ( !err ) { - while (--loop_for_command_done_check > 0) { - intsts = synopmob_read_register(base+RINTSTS); - if ((intsts & (INTMSK_CMD_DONE|INTMSK_DAT_OVER)) == (INTMSK_CMD_DONE|INTMSK_DAT_OVER)) { - break; - } - plat_loop(1); - } - ret = synopmob_handle_standard_rinsts(intsts); - if (!ret ) { - if( !loop_for_command_done_check || !(sdc->idsts & 0x100)) { //normal interrupt - ret = ERRIDMA; - } - } - } - } - - if (!ret) { - synopmob_set_register(base + RINTSTS, 0xfffe); //clear interrupts - synopmob_clear_bits(base + CTRL, CTRL_USE_IDMAC); - synopmob_clear_bits(base + BMOD,BMOD_DE); - synopmob_set_register(base+BLKSIZ, 512); - synopmob_set_register(base+BYTCNT, 512); - } - else { - char* op = "read"; - if (rw) - op = "write"; - - SDIO_PRINTF("sdio_drv_chain_write1(%s) fail:, ret = %d\n", op, ret); - } - - if ( rw && !ret ) { - ret = synopmob_wait_data_ready(base); - } - - OSSemPost (sdc->mutex); - - return ret; - //return ret ? 0/*false*/ : 1/*true*/; + //static volatile DmaDesc __attribute__ ((aligned(32))) st_pchain[4]; + volatile DmaDesc *st_pchain = (DmaDesc *)0x9a700000; + + int ret; + unsigned int intsts = 0; + unsigned int cmd = 0x2275; + unsigned int base = sdc->ip_base; + unsigned int arg; + unsigned int num; + unsigned int chain_len = 0; + int loop_for_command_done_check = DATA_TRANSFER_OVER_TIMEOUT_USEC; + char err; + unsigned int rw = 1; + + buf_chain_t *usrchain; + unsigned int desc0; + unsigned int length = 0; + + if (!chain) { + return 0; + } + + arg = (fn << 28) | (addr << 9); + if (bcnt == 1 && bsize <= 512) + arg |= (bsize & 0x1ff); + else + arg |= ((1 << 27) | bcnt); + if ( rw ) { + cmd |= 0x400; + arg |= (1 << 31); + } + num = bsize*bcnt; + + OSSemPend(sdc->mutex, 0, &err); + if (err != OS_NO_ERR) { + return ERRNORES; + } + + // reset + synopmob_set_bits(base+CTRL, FIFO_RESET); //reset FIFO + while (synopmob_read_register(base+CTRL) & FIFO_RESET); + synopmob_set_register(base + RINTSTS, 0xfffe); //clear interrupts + + usrchain = chain; + while (1) { + if(usrchain->size > (DescBuf1SizMsk >> DescBuf1SizeShift)) { + // TBD... fix me + OSSemPost (sdc->mutex); + return 0; + } + length += usrchain->size; + desc0 = DescOwnByDma | DescSecAddrChained; + if (!usrchain->next || usrchain->next == chain) { + desc0 |= DescLastDesc; + } + else { + desc0 |= DescDisInt; //disable interrupt... + } + + if(usrchain == chain) { + desc0 |= DescFirstDesc; + } + + st_pchain[chain_len].desc0 = desc0; + st_pchain[chain_len].desc1 = (unsigned int)usrchain->size; + st_pchain[chain_len].desc2 = (unsigned int)usrchain->buf; + st_pchain[chain_len].desc3 = (unsigned int)(&st_pchain[chain_len+1]); + flush_dcache_range((unsigned int)usrchain->buf, usrchain->size); + + usrchain = usrchain->next; + if( !usrchain || usrchain == chain) { + break; + } + if (++chain_len >= 4) { + while(1) SDIO_PRINTF("sdio_drv_chain_write:long chain!\n"); + } + } + st_pchain[chain_len].desc3 = (unsigned int)(&st_pchain[0]); + + if (length != num) { + while (1) SDIO_PRINTF("sdio_drv_chain_write:too long packet!\n"); + } + + synopmob_set_register(base+DBADDR, (unsigned int)(st_pchain)); + + synopmob_set_register(base+BLKSIZ, bsize); + synopmob_set_register(base+BYTCNT, num); + synopmob_set_bits(base + CTRL, CTRL_USE_IDMAC); + synopmob_set_bits(base + BMOD,BMOD_DE); + + ret = synopmob_execute_command(base, cmd, arg); + if ( !ret ) { + ret = ERRIDMA; + OSSemPend(sdc->sem, DMA_TRANSFER_TIMEOUT_TICKS, &err); + if ( !err ) { + while (--loop_for_command_done_check > 0) { + intsts = synopmob_read_register(base+RINTSTS); + if ((intsts & (INTMSK_CMD_DONE|INTMSK_DAT_OVER)) == (INTMSK_CMD_DONE|INTMSK_DAT_OVER)) { + break; + } + plat_loop(1); + } + ret = synopmob_handle_standard_rinsts(intsts); + if (!ret ) { + if( !loop_for_command_done_check || !(sdc->idsts & 0x100)) { //normal interrupt + ret = ERRIDMA; + } + } + } + } + + if (!ret) { + synopmob_set_register(base + RINTSTS, 0xfffe); //clear interrupts + synopmob_clear_bits(base + CTRL, CTRL_USE_IDMAC); + synopmob_clear_bits(base + BMOD,BMOD_DE); + synopmob_set_register(base+BLKSIZ, 512); + synopmob_set_register(base+BYTCNT, 512); + } + else { + char* op = "read"; + if (rw) + op = "write"; + + SDIO_PRINTF("sdio_drv_chain_write1(%s) fail:, ret = %d\n", op, ret); + } + + if ( rw && !ret ) { + ret = synopmob_wait_data_ready(base); + } + + OSSemPost (sdc->mutex); + + return ret; + //return ret ? 0/*false*/ : 1/*true*/; } #else static unsigned char __attribute__ ((aligned(32))) st_net_buf[2*1024]; int sdio_drv_chain_write(sdc_t* sdc, unsigned int addr, unsigned int fn, unsigned int bcnt, unsigned int bsize, buf_chain_t *chain) { - static volatile DmaDesc __attribute__ ((aligned(32))) st_pchain; - - int ret; - unsigned int intsts = 0; - unsigned int cmd = 0x2275; - unsigned int base = sdc->ip_base; - unsigned int arg; - unsigned int num; - int loop_for_command_done_check = DATA_TRANSFER_OVER_TIMEOUT_USEC; - rt_err_t err; - unsigned int rw = 1; - - buf_chain_t *usrchain; - unsigned int length = 0; - - if (!chain) { - return 0; - } - - arg = (fn << 28) | (addr << 9); - if (bcnt == 1 && bsize <= 512) - arg |= (bsize & 0x1ff); - else - arg |= ((1 << 27) | bcnt); - if ( rw ) { - cmd |= 0x400; - arg |= (1 << 31); - } - num = bsize*bcnt; - - err = rt_sem_take(sdc->mutex, RT_WAITING_FOREVER); - if (err != RT_EOK) { - return ERRNORES; - } - - - // reset - synopmob_set_bits(base+CTRL, FIFO_RESET); //reset FIFO - while (synopmob_read_register(base+CTRL) & FIFO_RESET); - synopmob_set_register(base + RINTSTS, 0xfffe); //clear interrupts - - usrchain = chain; - while (1) { - if (length + usrchain->size >= sizeof(st_net_buf)) { - while(1) SDIO_PRINTF("too long net pkt\n"); - } - - memcpy(st_net_buf + length, usrchain->buf, usrchain->size); - length += usrchain->size; - usrchain = usrchain->next; - if (!usrchain || usrchain->next == chain) { - break; - } - } - - st_pchain.desc0 = DescOwnByDma | DescSecAddrChained | DescLastDesc | DescFirstDesc; - st_pchain.desc1 = length; - st_pchain.desc2 = (unsigned int)st_net_buf; - st_pchain.desc3 = (unsigned int)&st_pchain; - flush_dcache_range((unsigned long)st_net_buf, length); - - if (length != num) { - while (1) SDIO_PRINTF("sdio_drv_chain_write:too long packet!\n"); - } - - synopmob_set_register(base+DBADDR, (unsigned int)(&st_pchain)); - - synopmob_set_register(base+BLKSIZ, bsize); - synopmob_set_register(base+BYTCNT, num); - synopmob_set_bits(base + CTRL, CTRL_USE_IDMAC); - synopmob_set_bits(base + BMOD,BMOD_DE); - - ret = synopmob_execute_command(base, cmd, arg); - if ( !ret ) { - ret = ERRIDMA; - err = rt_sem_take(sdc->sem, DMA_TRANSFER_TIMEOUT_TICKS); - if ( !err ) { - while (--loop_for_command_done_check > 0) { - intsts = synopmob_read_register(base+RINTSTS); - if ((intsts & (INTMSK_CMD_DONE|INTMSK_DAT_OVER)) == (INTMSK_CMD_DONE|INTMSK_DAT_OVER)) { - break; - } - plat_loop(1); - } - ret = synopmob_handle_standard_rinsts(intsts); - if (!ret ) { - if( !loop_for_command_done_check || !(sdc->idsts & 0x100)) { //normal interrupt - ret = ERRIDMA; - } - } - } - } - - if (!ret) { - synopmob_set_register(base + RINTSTS, 0xfffe); //clear interrupts - synopmob_clear_bits(base + CTRL, CTRL_USE_IDMAC); - synopmob_clear_bits(base + BMOD,BMOD_DE); - synopmob_set_register(base+BLKSIZ, 512); - synopmob_set_register(base+BYTCNT, 512); - } - else { - char* op = "read"; - if (rw) - op = "write"; - - SDIO_PRINTF("sdio_drv_chain_write1(%s) fail:, ret = %d\n", op, ret); - } - - if ( rw && !ret ) { - ret = synopmob_wait_data_ready(base); - } - - rt_sem_release(sdc->mutex); - - return ret; - //return ret ? 0/*false*/ : 1/*true*/; + static volatile DmaDesc __attribute__ ((aligned(32))) st_pchain; + + int ret; + unsigned int intsts = 0; + unsigned int cmd = 0x2275; + unsigned int base = sdc->ip_base; + unsigned int arg; + unsigned int num; + int loop_for_command_done_check = DATA_TRANSFER_OVER_TIMEOUT_USEC; + rt_err_t err; + unsigned int rw = 1; + + buf_chain_t *usrchain; + unsigned int length = 0; + + if (!chain) { + return 0; + } + + arg = (fn << 28) | (addr << 9); + if (bcnt == 1 && bsize <= 512) + arg |= (bsize & 0x1ff); + else + arg |= ((1 << 27) | bcnt); + if ( rw ) { + cmd |= 0x400; + arg |= (1 << 31); + } + num = bsize*bcnt; + + err = rt_sem_take(sdc->mutex, RT_WAITING_FOREVER); + if (err != RT_EOK) { + return ERRNORES; + } + + + // reset + synopmob_set_bits(base+CTRL, FIFO_RESET); //reset FIFO + while (synopmob_read_register(base+CTRL) & FIFO_RESET); + synopmob_set_register(base + RINTSTS, 0xfffe); //clear interrupts + + usrchain = chain; + while (1) { + if (length + usrchain->size >= sizeof(st_net_buf)) { + while(1) SDIO_PRINTF("too long net pkt\n"); + } + + memcpy(st_net_buf + length, usrchain->buf, usrchain->size); + length += usrchain->size; + usrchain = usrchain->next; + if (!usrchain || usrchain->next == chain) { + break; + } + } + + st_pchain.desc0 = DescOwnByDma | DescSecAddrChained | DescLastDesc | DescFirstDesc; + st_pchain.desc1 = length; + st_pchain.desc2 = (unsigned int)st_net_buf; + st_pchain.desc3 = (unsigned int)&st_pchain; + flush_dcache_range((unsigned long)st_net_buf, length); + + if (length != num) { + while (1) SDIO_PRINTF("sdio_drv_chain_write:too long packet!\n"); + } + + synopmob_set_register(base+DBADDR, (unsigned int)(&st_pchain)); + + synopmob_set_register(base+BLKSIZ, bsize); + synopmob_set_register(base+BYTCNT, num); + synopmob_set_bits(base + CTRL, CTRL_USE_IDMAC); + synopmob_set_bits(base + BMOD,BMOD_DE); + + ret = synopmob_execute_command(base, cmd, arg); + if ( !ret ) { + ret = ERRIDMA; + err = rt_sem_take(sdc->sem, DMA_TRANSFER_TIMEOUT_TICKS); + if ( !err ) { + while (--loop_for_command_done_check > 0) { + intsts = synopmob_read_register(base+RINTSTS); + if ((intsts & (INTMSK_CMD_DONE|INTMSK_DAT_OVER)) == (INTMSK_CMD_DONE|INTMSK_DAT_OVER)) { + break; + } + plat_loop(1); + } + ret = synopmob_handle_standard_rinsts(intsts); + if (!ret ) { + if( !loop_for_command_done_check || !(sdc->idsts & 0x100)) { //normal interrupt + ret = ERRIDMA; + } + } + } + } + + if (!ret) { + synopmob_set_register(base + RINTSTS, 0xfffe); //clear interrupts + synopmob_clear_bits(base + CTRL, CTRL_USE_IDMAC); + synopmob_clear_bits(base + BMOD,BMOD_DE); + synopmob_set_register(base+BLKSIZ, 512); + synopmob_set_register(base+BYTCNT, 512); + } + else { + char* op = "read"; + if (rw) + op = "write"; + + SDIO_PRINTF("sdio_drv_chain_write1(%s) fail:, ret = %d\n", op, ret); + } + + if ( rw && !ret ) { + ret = synopmob_wait_data_ready(base); + } + + rt_sem_release(sdc->mutex); + + return ret; + //return ret ? 0/*false*/ : 1/*true*/; } #endif #endif static int sdio_card_reset(sdc_t* sdc) { - unsigned int resp; - int ret; + unsigned int resp; + int ret; - /* Soft Reset card */ + /* Soft Reset card */ sdio_drv_creg_write(sdc, 0x6, 0, 0x8, &resp); - return 0; + return 0; } static int enum_sdio_card(sdc_t* sdc) { - int ret; - unsigned int resp; - unsigned int base = sdc->ip_base; - - #if 0 - synopmob_set_bits(0x98500004, (1<<24)); //set to output mode - synopmob_set_bits(0x98500000, (1<<24)); //power off - plat_loop(1000000/5); //Lets give some ramp down period - synopmob_clear_bits(0x98500000, (1<<24)); //power on - plat_loop(1000000/5);//Lets give some ramp down period - #endif - - synopmob_set_register(base+CTYPE, ONE_BIT_MODE); - - synopmob_set_register(base+CLKENA, 0x00000001); /*enable clock, non-low-power mode*/ - ret = synopmob_set_clk_freq(sdc, MMC_FOD_DIVIDER_VALUE); - - if ( !ret ) { - plat_loop(100); //enough for 74 clock. - #if 0 - sdio_card_reset(sdc); - plat_loop(100000); - #endif - ret = sd_send_cmd5(sdc, 0, &resp); - if (!ret) { - resp &= 0x00ffffff; - ret = sd_send_cmd5(sdc, resp, &resp); - } - } - - if (!ret) { - ret = sd_send_cmd3(sdc); //get RCA - } - - if (!ret) { - ret = sd_send_cmd7(sdc); //select the card - } - - - if (!g_use_bcm43362) - { - sdio_drv_creg_read(sdc, 0x13, 0, &resp); - if ((resp & 1) && (sdc->wkmod & (SDC_WKMOD_4WIRE|SDC_WKMOD_25M_STAND_SPEED|SDC_WKMOD_50M_HI_SPEED))){ //high speed support? - if (sdc->wkmod & SDC_WKMOD_4WIRE) { - sdio_drv_creg_read(sdc, 0x7, 0, &resp); - resp &= 0xfc; - resp |= (1 << 1); - sdio_drv_creg_write(sdc, 0x7, 0, resp, &resp); //switch to 4bit mode - sdio_drv_creg_read(sdc, 0x7, 0, &resp); - if ((resp & 0x3) != 0x2) { - return ERRCARDINTERNAL; // 4bit mode failed - } - synopmob_set_register(base+CTYPE, FOUR_BIT_MODE); - } - if (sdc->wkmod & (SDC_WKMOD_25M_STAND_SPEED|SDC_WKMOD_50M_HI_SPEED)) { - ret = synopmob_set_clk_freq(sdc, ONE_BIT_BUS_FREQ); - //ret = synopmob_set_clk_freq(sdc, 0); - } - } - - sdio_drv_creg_read(sdc, 0x3, 0, &resp); - if (!ret) { - sdio_drv_creg_read(sdc, 0x0, 0, &resp); //card version - sdio_drv_creg_write(sdc, 0x4, 0, 0x3, &resp); //enable interrupts in card - sdio_drv_creg_write(sdc, 0x2, 0, 0x2, &resp); //Eable IO in card - do { - sdio_drv_creg_read(sdc, 0x3, 0, &resp); - } while (!(resp & 2)); - } - } //g_use_bcm43362 - - sdc->card_type = SDIO_TYPE; - - synopmob_set_bits(base+CTRL, INT_ENABLE); - - return ret; + int ret; + unsigned int resp; + unsigned int base = sdc->ip_base; + + #if 0 + synopmob_set_bits(0x98500004, (1<<24)); //set to output mode + synopmob_set_bits(0x98500000, (1<<24)); //power off + plat_loop(1000000/5); //Lets give some ramp down period + synopmob_clear_bits(0x98500000, (1<<24)); //power on + plat_loop(1000000/5);//Lets give some ramp down period + #endif + + synopmob_set_register(base+CTYPE, ONE_BIT_MODE); + + synopmob_set_register(base+CLKENA, 0x00000001); /*enable clock, non-low-power mode*/ + ret = synopmob_set_clk_freq(sdc, MMC_FOD_DIVIDER_VALUE); + + if ( !ret ) { + plat_loop(100); //enough for 74 clock. + #if 0 + sdio_card_reset(sdc); + plat_loop(100000); + #endif + ret = sd_send_cmd5(sdc, 0, &resp); + if (!ret) { + resp &= 0x00ffffff; + ret = sd_send_cmd5(sdc, resp, &resp); + } + } + + if (!ret) { + ret = sd_send_cmd3(sdc); //get RCA + } + + if (!ret) { + ret = sd_send_cmd7(sdc); //select the card + } + + + if (!g_use_bcm43362) + { + sdio_drv_creg_read(sdc, 0x13, 0, &resp); + if ((resp & 1) && (sdc->wkmod & (SDC_WKMOD_4WIRE|SDC_WKMOD_25M_STAND_SPEED|SDC_WKMOD_50M_HI_SPEED))){ //high speed support? + if (sdc->wkmod & SDC_WKMOD_4WIRE) { + sdio_drv_creg_read(sdc, 0x7, 0, &resp); + resp &= 0xfc; + resp |= (1 << 1); + sdio_drv_creg_write(sdc, 0x7, 0, resp, &resp); //switch to 4bit mode + sdio_drv_creg_read(sdc, 0x7, 0, &resp); + if ((resp & 0x3) != 0x2) { + return ERRCARDINTERNAL; // 4bit mode failed + } + synopmob_set_register(base+CTYPE, FOUR_BIT_MODE); + } + if (sdc->wkmod & (SDC_WKMOD_25M_STAND_SPEED|SDC_WKMOD_50M_HI_SPEED)) { + ret = synopmob_set_clk_freq(sdc, ONE_BIT_BUS_FREQ); + //ret = synopmob_set_clk_freq(sdc, 0); + } + } + + sdio_drv_creg_read(sdc, 0x3, 0, &resp); + if (!ret) { + sdio_drv_creg_read(sdc, 0x0, 0, &resp); //card version + sdio_drv_creg_write(sdc, 0x4, 0, 0x3, &resp); //enable interrupts in card + sdio_drv_creg_write(sdc, 0x2, 0, 0x2, &resp); //Eable IO in card + do { + sdio_drv_creg_read(sdc, 0x3, 0, &resp); + } while (!(resp & 2)); + } + } //g_use_bcm43362 + + sdc->card_type = SDIO_TYPE; + + synopmob_set_bits(base+CTRL, INT_ENABLE); + + return ret; } int sdio_high_speed_mode(HSDC handle, int bitwidth, int freq) { - int ret; - sdc_t* sdc = (sdc_t*)handle; + int ret; + sdc_t* sdc = (sdc_t*)handle; - if (bitwidth == 4) - { - synopmob_set_register(sdc->ip_base+CTYPE, FOUR_BIT_MODE); - } + if (bitwidth == 4) + { + synopmob_set_register(sdc->ip_base+CTYPE, FOUR_BIT_MODE); + } - ret = synopmob_set_clk_freq(sdc, /*ONE_BIT_BUS_FREQ*/1); - if (ret != 0) - { - SDIO_PRINTF("sdio_high_speed_mode fail:, ret = %d\n", ret); - } + ret = synopmob_set_clk_freq(sdc, /*ONE_BIT_BUS_FREQ*/1); + if (ret != 0) + { + SDIO_PRINTF("sdio_high_speed_mode fail:, ret = %d\n", ret); + } - return ret; + return ret; } static int common_init(unsigned int which, unsigned int sdio, unsigned int wkmod, unsigned int* dma_desc, HSDC* phandle) { - int ret = ERRNORES; - sdc_t* sdc; - unsigned int base; - unsigned int temp; - unsigned int fifo_thresh; - volatile DmaDesc *pDmaDesc; - rt_sem_t sem; - rt_sem_t mutex; - - base = SDC0_REG_BASE; - temp = PMU_SDC0_RST_BIT; - if (which > 0) { - base = SDC1_REG_BASE; - temp = PMU_SDC1_RST_BIT; - } - + int ret = ERRNORES; + sdc_t* sdc; + unsigned int base; + unsigned int temp; + unsigned int fifo_thresh; + volatile DmaDesc *pDmaDesc; + rt_sem_t sem; + rt_sem_t mutex; + + base = SDC0_REG_BASE; + temp = PMU_SDC0_RST_BIT; + if (which > 0) { + base = SDC1_REG_BASE; + temp = PMU_SDC1_RST_BIT; + } + #if 0 - //PMU_RST_MODULE(temp); plat_loop(1); - temp = synopmob_read_register(PMU_REG_CLK_DIV3); - temp &= (~(0x0f<<8)); - temp |= (0xf<<8); - synopmob_set_register(PMU_REG_CLK_DIV3, temp); + //PMU_RST_MODULE(temp); plat_loop(1); + temp = synopmob_read_register(PMU_REG_CLK_DIV3); + temp &= (~(0x0f<<8)); + temp |= (0xf<<8); + synopmob_set_register(PMU_REG_CLK_DIV3, temp); #endif - *phandle = (HSDC)0; - - sdc = &sdc_array[which]; - sem = sdc->sem; - mutex = sdc->mutex; - memset((void *)sdc, 0, sizeof(*sdc)); - sdc->wkmod = wkmod; - sdc->idma_support = 0; - sdc->ip_base = base; - sdc->rca = 0; - sdc->card_type = NONE_TYPE; - if (!sem) { - sem = rt_sem_create("fh_sdio_sem", 0, RT_IPC_FLAG_PRIO);//OSSemCreate (0); - if ( !sem ) { - return ret; - } - } - sdc->sem = sem; - - if (!mutex) { - mutex = rt_sem_create("fh_sdio_mutex", 1, RT_IPC_FLAG_PRIO);//OSSemCreate (1); - if ( !mutex ) { - return ret; - } - } - sdc->mutex = mutex; - - synopmob_set_bits(base + CTRL, CTRL_RESET); //reset host controller - plat_loop(100); - - synopmob_clear_bits(base + CTRL,CTRL_USE_IDMAC); - sdc->idma_support = 1; //fixed to support IDMA - - pDmaDesc = (volatile DmaDesc *)dma_desc; - sdc->pDmaDesc = pDmaDesc; - if (sdc->idma_support) { - synopmob_set_bits(base + CTRL, DMA_RESET); - plat_loop(100); - synopmob_set_bits(base + CTRL, FIFO_RESET); - plat_loop(100); - synopmob_set_bits(base + BMOD, BMOD_SWR); - plat_loop(100); - - //synopmob_set_bits(base + BMOD,BMOD_DE); - pDmaDesc->desc0 = DescSecAddrChained; - pDmaDesc->desc1 = 0; - pDmaDesc->desc2 = 0; - pDmaDesc->desc3 = (unsigned int)(pDmaDesc); - synopmob_set_register(base + DBADDR, (unsigned int)(pDmaDesc)); - } - - synopmob_set_register(base+CTYPE, ONE_BIT_MODE); - - synopmob_set_register(base+RINTSTS, 0xffffffff);//clear interrupt. - synopmob_clear_bits(base+CTRL, INT_ENABLE); - synopmob_set_register(base+INTMSK, 0); // mask all INTR - synopmob_set_register(base+IDINTEN, IDMAINTBITS); //Enable DMA INTR - - - synopmob_set_register(base+TMOUT, 0xffffffff); /* Set Data and Response timeout to Maximum Value*/ - - /* Set the card Debounce to allow the CDETECT fluctuations to settle down*/ - synopmob_set_register(base+DEBNCE, 0x0FFFFF); - - fifo_thresh = synopmob_read_register(base+FIFOTH); - //fifo_thresh = GET_FIFO_DEPTH(fifo_thresh) / 2; - fifo_thresh = (GET_FIFO_DEPTH(fifo_thresh) + 1) / 2; - sdc->fifo_depth = fifo_thresh * 2; - sdc->fifo_threth = fifo_thresh; - /* Tx Watermark */ - synopmob_clear_bits(base+FIFOTH, 0xfff); - synopmob_set_bits(base+FIFOTH, fifo_thresh); - /* Rx Watermark */ - synopmob_clear_bits(base+FIFOTH, 0x0fff0000); - synopmob_set_bits(base+FIFOTH, (fifo_thresh-1) << 16); - //synopmob_set_bits(base+FIFOTH, 2<< 28); - - if (!sdio) { - ret = enum_sd_card(sdc); - } - else { - ret = enum_sdio_card(sdc); - } - - if (!ret) { - *phandle = (HSDC)sdc; - } - - return ret; + *phandle = (HSDC)0; + + sdc = &sdc_array[which]; + sem = sdc->sem; + mutex = sdc->mutex; + memset((void *)sdc, 0, sizeof(*sdc)); + sdc->wkmod = wkmod; + sdc->idma_support = 0; + sdc->ip_base = base; + sdc->rca = 0; + sdc->card_type = NONE_TYPE; + if (!sem) { + sem = rt_sem_create("fh_sdio_sem", 0, RT_IPC_FLAG_PRIO);//OSSemCreate (0); + if ( !sem ) { + return ret; + } + } + sdc->sem = sem; + + if (!mutex) { + mutex = rt_sem_create("fh_sdio_mutex", 1, RT_IPC_FLAG_PRIO);//OSSemCreate (1); + if ( !mutex ) { + return ret; + } + } + sdc->mutex = mutex; + + synopmob_set_bits(base + CTRL, CTRL_RESET); //reset host controller + plat_loop(100); + + synopmob_clear_bits(base + CTRL,CTRL_USE_IDMAC); + sdc->idma_support = 1; //fixed to support IDMA + + pDmaDesc = (volatile DmaDesc *)dma_desc; + sdc->pDmaDesc = pDmaDesc; + if (sdc->idma_support) { + synopmob_set_bits(base + CTRL, DMA_RESET); + plat_loop(100); + synopmob_set_bits(base + CTRL, FIFO_RESET); + plat_loop(100); + synopmob_set_bits(base + BMOD, BMOD_SWR); + plat_loop(100); + + //synopmob_set_bits(base + BMOD,BMOD_DE); + pDmaDesc->desc0 = DescSecAddrChained; + pDmaDesc->desc1 = 0; + pDmaDesc->desc2 = 0; + pDmaDesc->desc3 = (unsigned int)(pDmaDesc); + synopmob_set_register(base + DBADDR, (unsigned int)(pDmaDesc)); + } + + synopmob_set_register(base+CTYPE, ONE_BIT_MODE); + + synopmob_set_register(base+RINTSTS, 0xffffffff);//clear interrupt. + synopmob_clear_bits(base+CTRL, INT_ENABLE); + synopmob_set_register(base+INTMSK, 0); // mask all INTR + synopmob_set_register(base+IDINTEN, IDMAINTBITS); //Enable DMA INTR + + + synopmob_set_register(base+TMOUT, 0xffffffff); /* Set Data and Response timeout to Maximum Value*/ + + /* Set the card Debounce to allow the CDETECT fluctuations to settle down*/ + synopmob_set_register(base+DEBNCE, 0x0FFFFF); + + fifo_thresh = synopmob_read_register(base+FIFOTH); + //fifo_thresh = GET_FIFO_DEPTH(fifo_thresh) / 2; + fifo_thresh = (GET_FIFO_DEPTH(fifo_thresh) + 1) / 2; + sdc->fifo_depth = fifo_thresh * 2; + sdc->fifo_threth = fifo_thresh; + /* Tx Watermark */ + synopmob_clear_bits(base+FIFOTH, 0xfff); + synopmob_set_bits(base+FIFOTH, fifo_thresh); + /* Rx Watermark */ + synopmob_clear_bits(base+FIFOTH, 0x0fff0000); + synopmob_set_bits(base+FIFOTH, (fifo_thresh-1) << 16); + //synopmob_set_bits(base+FIFOTH, 2<< 28); + + if (!sdio) { + ret = enum_sd_card(sdc); + } + else { + ret = enum_sdio_card(sdc); + } + + if (!ret) { + *phandle = (HSDC)sdc; + } + + return ret; } int sdc_is_connected(unsigned int which) { - unsigned int base = SDC0_REG_BASE; - - if (which > 0) - base = SDC1_REG_BASE; + unsigned int base = SDC0_REG_BASE; + + if (which > 0) + base = SDC1_REG_BASE; - return !(synopmob_read_register(base+CDETECT) & 1); + return !(synopmob_read_register(base+CDETECT) & 1); } int sdc_init(unsigned int which, unsigned int wkmod, unsigned int* dma_desc, HSDC* phandle) { - return common_init(which, 0, wkmod, dma_desc, phandle); + return common_init(which, 0, wkmod, dma_desc, phandle); } int sdio_init(unsigned int which, unsigned int wkmod, unsigned int* dma_desc, HSDC* phandle) { - return common_init(which, 1, wkmod, dma_desc, phandle); + return common_init(which, 1, wkmod, dma_desc, phandle); } int sdio_enable_card_int(HSDC handle, int enable) { - unsigned int base = ((sdc_t*)handle)->ip_base; - - if (enable) { - //synopmob_set_register(base+INTMSK, INTMSK_SDIO); - synopmob_set_register(base+INTMSK, (synopmob_read_register(base+INTMSK) | INTMSK_SDIO )); - } - else { - //synopmob_set_register(base+INTMSK, 0); - synopmob_set_register(base+INTMSK, (synopmob_read_register(base+INTMSK) & ~INTMSK_SDIO )); - } - - return 0; + unsigned int base = ((sdc_t*)handle)->ip_base; + + if (enable) { + //synopmob_set_register(base+INTMSK, INTMSK_SDIO); + synopmob_set_register(base+INTMSK, (synopmob_read_register(base+INTMSK) | INTMSK_SDIO )); + } + else { + //synopmob_set_register(base+INTMSK, 0); + synopmob_set_register(base+INTMSK, (synopmob_read_register(base+INTMSK) & ~INTMSK_SDIO )); + } + + return 0; } int sdio_set_card_int_cb(HSDC handle, void (*cb)(void)) { - ((sdc_t*)handle)->cb = cb; + ((sdc_t*)handle)->cb = cb; - return 0; + return 0; } static void OSSDCISR(sdc_t* sdc) { - unsigned int sts; - unsigned int base; - - base = sdc->ip_base; - sts = synopmob_read_register(base+IDSTS); - if ( sts ) { - synopmob_set_register(base+IDSTS, sts); - sdc->idsts = sts; - rt_sem_release(sdc->sem); - } - - //sts = synopmob_read_register(base+RINTSTS); - sts = synopmob_read_register(base+MINTSTS); - sts &= INTMSK_SDIO; - if ( sts ) { //interrupt from WIFI card. - //synopmob_set_register(base+INTMSK, 0); //mask all the interrupt - synopmob_set_register(base+INTMSK, synopmob_read_register(base+INTMSK) & ~INTMSK_SDIO ); //mask sdio interrupt - synopmob_set_register(base+RINTSTS, sts); - synopmob_set_register(base+MINTSTS, sts); - if (sdc->cb) { - sdc->cb(); - } - } + unsigned int sts; + unsigned int base; + + base = sdc->ip_base; + sts = synopmob_read_register(base+IDSTS); + if ( sts ) { + synopmob_set_register(base+IDSTS, sts); + sdc->idsts = sts; + rt_sem_release(sdc->sem); + } + + //sts = synopmob_read_register(base+RINTSTS); + sts = synopmob_read_register(base+MINTSTS); + sts &= INTMSK_SDIO; + if ( sts ) { //interrupt from WIFI card. + //synopmob_set_register(base+INTMSK, 0); //mask all the interrupt + synopmob_set_register(base+INTMSK, synopmob_read_register(base+INTMSK) & ~INTMSK_SDIO ); //mask sdio interrupt + synopmob_set_register(base+RINTSTS, sts); + synopmob_set_register(base+MINTSTS, sts); + if (sdc->cb) { + sdc->cb(); + } + } } void OSSDCINTR_0(int vector, void *param) { - OSSDCISR(&sdc_array[0]); + OSSDCISR(&sdc_array[0]); } void OSSDCINTR_1(int vector, void *param) { - OSSDCISR(&sdc_array[1]); + OSSDCISR(&sdc_array[1]); } void fh_sdio0_init(void) { int sd0_irq = SDC0_IRQn; - + rt_hw_interrupt_install(sd0_irq, OSSDCINTR_0, NULL, NULL); rt_hw_interrupt_umask(sd0_irq); } @@ -2058,7 +2058,7 @@ void fh_sdio0_init(void) void fh_sdio1_init(void) { int sd1_irq = SDC1_IRQn; - + rt_hw_interrupt_install(sd1_irq, OSSDCINTR_1, NULL, NULL); rt_hw_interrupt_umask(sd1_irq); } @@ -2071,14 +2071,14 @@ void fh_sdio_init(void) int sdc_deinit(HSDC handle) { - return -1; // TBD... fix me + return -1; // TBD... fix me } int sdc_set_clk_divider(unsigned int divider) { if(divider > 255) return -1; - + sdc_clk_divider = divider; return 0; } diff --git a/bsp/fh8620/libraries/driverlib/fh_spi.c b/bsp/fh8620/libraries/driverlib/fh_spi.c index 14d803973..14e47ad73 100644 --- a/bsp/fh8620/libraries/driverlib/fh_spi.c +++ b/bsp/fh8620/libraries/driverlib/fh_spi.c @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,7 +18,7 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes diff --git a/bsp/fh8620/libraries/driverlib/fh_timer.c b/bsp/fh8620/libraries/driverlib/fh_timer.c index f3034adea..eab30888a 100644 --- a/bsp/fh8620/libraries/driverlib/fh_timer.c +++ b/bsp/fh8620/libraries/driverlib/fh_timer.c @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,12 +18,12 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + /***************************************************************************** * Include Section * add all #include here @@ -79,66 +79,66 @@ *****************************************************************************/ int timer_init(timer *tim) { - tim->TIMER_CTRL_REG = 0; + tim->TIMER_CTRL_REG = 0; } int timer_set_mode(timer *tim, enum timer_mode mode) { - switch (mode) - { - case TIMER_MODE_PERIODIC: - tim->TIMER_CTRL_REG |= TIMER_CTRL_MODE; - break; - case TIMER_MODE_ONESHOT: - tim->TIMER_CTRL_REG |= TIMER_CTRL_MODE; - break; - default: - rt_kprintf("Not support TIMER mode\n"); - return -1; - break; - } - - return 0; + switch (mode) + { + case TIMER_MODE_PERIODIC: + tim->TIMER_CTRL_REG |= TIMER_CTRL_MODE; + break; + case TIMER_MODE_ONESHOT: + tim->TIMER_CTRL_REG |= TIMER_CTRL_MODE; + break; + default: + rt_kprintf("Not support TIMER mode\n"); + return -1; + break; + } + + return 0; } void timer_set_period(timer *tim, UINT32 period, UINT32 clock) { - tim->TIMER_LOAD_COUNT = clock/period; + tim->TIMER_LOAD_COUNT = clock/period; } void timer_enable(timer *tim) { - tim->TIMER_CTRL_REG |= TIMER_CTRL_ENABLE; + tim->TIMER_CTRL_REG |= TIMER_CTRL_ENABLE; } void timer_disable(timer *tim) { - tim->TIMER_CTRL_REG &= ~TIMER_CTRL_ENABLE; + tim->TIMER_CTRL_REG &= ~TIMER_CTRL_ENABLE; } void timer_enable_irq(timer *tim) { - tim->TIMER_CTRL_REG &= ~TIMER_CTRL_INTMASK; + tim->TIMER_CTRL_REG &= ~TIMER_CTRL_INTMASK; } void timer_disable_irq(timer *tim) { - tim->TIMER_CTRL_REG |= TIMER_CTRL_INTMASK; + tim->TIMER_CTRL_REG |= TIMER_CTRL_INTMASK; } UINT32 timer_get_status(timer *tim) { - return tim->TIMER_INT_STATUS; + return tim->TIMER_INT_STATUS; } UINT32 timer_get_eoi(timer *tim) { - return tim->TIMER_EOI; + return tim->TIMER_EOI; } UINT32 timer_get_value(timer *tim) { - return tim->TIMER_LOAD_COUNT - tim->TIMER_CURRENT_VALUE; + return tim->TIMER_LOAD_COUNT - tim->TIMER_CURRENT_VALUE; } diff --git a/bsp/fh8620/libraries/driverlib/fh_uart.c b/bsp/fh8620/libraries/driverlib/fh_uart.c index 0d9ad1f35..75b453c9f 100644 --- a/bsp/fh8620/libraries/driverlib/fh_uart.c +++ b/bsp/fh8620/libraries/driverlib/fh_uart.c @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,12 +18,12 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + /***************************************************************************** * Include Section * add all #include here @@ -79,33 +79,33 @@ int uart_init(uart *port) { - port->UART_IER = 0; - port->UART_LCR = 0; - //port->UART_DLL = 0; - //port->UART_DLH = 0; + port->UART_IER = 0; + port->UART_LCR = 0; + //port->UART_DLL = 0; + //port->UART_DLH = 0; } UINT32 uart_get_status(uart *port) { - return port->UART_USR; + return port->UART_USR; } void uart_configure(uart *port, enum data_bits data_bit, - enum stop_bits stop_bit, enum parity parity, - UINT32 buard_rate, UINT32 uart_clk) + enum stop_bits stop_bit, enum parity parity, + UINT32 buard_rate, UINT32 uart_clk) { - UINT32 divisor; - UINT32 freq; - UINT32 baud_div; - UINT32 lcr_reg = 0; - UINT32 ret; - - /*divisor = DIV(buard_rate); - port->UART_LCR |= UART_LCR_DLAB; - port->UART_DLL = divisor & 0xFF; - port->UART_DLH = (divisor >> 8) & 0xFF; - port->UART_LCR &= ~UART_LCR_DLAB;*/ + UINT32 divisor; + UINT32 freq; + UINT32 baud_div; + UINT32 lcr_reg = 0; + UINT32 ret; + + /*divisor = DIV(buard_rate); + port->UART_LCR |= UART_LCR_DLAB; + port->UART_DLL = divisor & 0xFF; + port->UART_DLH = (divisor >> 8) & 0xFF; + port->UART_LCR &= ~UART_LCR_DLAB;*/ do{ //clear fifo... @@ -113,141 +113,141 @@ void uart_configure(uart *port, enum data_bits data_bit, //read status.. ret = uart_get_status(port); }while(ret & UART_USR_BUSY); - switch (data_bit) { - case UART_DATA_BIT5: - lcr_reg |= UART_LCR_DLS5; - break; - case UART_DATA_BIT6: - lcr_reg |= UART_LCR_DLS6; - break; - case UART_DATA_BIT7: - lcr_reg |= UART_LCR_DLS7; - break; - case UART_DATA_BIT8: - lcr_reg |= UART_LCR_DLS8; - break; - default: - lcr_reg |= UART_LCR_DLS8; - break; - } - - switch (stop_bit) { - case UART_STOP_BIT1: - lcr_reg |= UART_LCR_STOP1; - break; - case UART_STOP_BIT2: - lcr_reg |= UART_LCR_STOP2; - break; - default: - lcr_reg |= UART_LCR_STOP1; - break; - } - - switch (parity) { - case UART_PARITY_EVEN: - lcr_reg |= UART_LCR_EVEN | UART_LCR_PEN; - break; - case UART_PARITY_ODD: - lcr_reg |= UART_LCR_PEN; - break; - case UART_PARITY_ST: - lcr_reg |= UART_LCR_SP; - break; - case UART_PARITY_NONE: - default: - break; - } - - - - switch (buard_rate) { - case 115200: - baud_div = BAUDRATE_115200; - break; - case 57600: - baud_div = BAUDRATE_57600; - break; - case 38400: - baud_div = BAUDRATE_38400; - break; - case 19200: - baud_div = BAUDRATE_19200; - break; - case 9600: - baud_div = BAUDRATE_9600; - break; - default: - baud_div = BAUDRATE_115200; - break; - } - - //clear fifo - port->UART_FCR = UART_FCR_RFIFOR | UART_FCR_XFIFOR; - - //div - ret = port->UART_LCR; - ret |= UART_LCR_DLAB; - port->UART_LCR = ret; - port->RBRTHRDLL = baud_div & 0x00ff; - port->DLHIER = (baud_div & 0x00ff)>>8; - /* clear DLAB */ - ret = ret & 0x7f; - port->UART_LCR = ret; - - //line control - port->UART_LCR = lcr_reg; - //fifo control - port->UART_FCR = UART_FCR_FIFOE | UART_FCR_RFIFOR | UART_FCR_XFIFOR | UART_FCR_TET_1_4 | UART_FCR_RT_ONE; + switch (data_bit) { + case UART_DATA_BIT5: + lcr_reg |= UART_LCR_DLS5; + break; + case UART_DATA_BIT6: + lcr_reg |= UART_LCR_DLS6; + break; + case UART_DATA_BIT7: + lcr_reg |= UART_LCR_DLS7; + break; + case UART_DATA_BIT8: + lcr_reg |= UART_LCR_DLS8; + break; + default: + lcr_reg |= UART_LCR_DLS8; + break; + } + + switch (stop_bit) { + case UART_STOP_BIT1: + lcr_reg |= UART_LCR_STOP1; + break; + case UART_STOP_BIT2: + lcr_reg |= UART_LCR_STOP2; + break; + default: + lcr_reg |= UART_LCR_STOP1; + break; + } + + switch (parity) { + case UART_PARITY_EVEN: + lcr_reg |= UART_LCR_EVEN | UART_LCR_PEN; + break; + case UART_PARITY_ODD: + lcr_reg |= UART_LCR_PEN; + break; + case UART_PARITY_ST: + lcr_reg |= UART_LCR_SP; + break; + case UART_PARITY_NONE: + default: + break; + } + + + + switch (buard_rate) { + case 115200: + baud_div = BAUDRATE_115200; + break; + case 57600: + baud_div = BAUDRATE_57600; + break; + case 38400: + baud_div = BAUDRATE_38400; + break; + case 19200: + baud_div = BAUDRATE_19200; + break; + case 9600: + baud_div = BAUDRATE_9600; + break; + default: + baud_div = BAUDRATE_115200; + break; + } + + //clear fifo + port->UART_FCR = UART_FCR_RFIFOR | UART_FCR_XFIFOR; + + //div + ret = port->UART_LCR; + ret |= UART_LCR_DLAB; + port->UART_LCR = ret; + port->RBRTHRDLL = baud_div & 0x00ff; + port->DLHIER = (baud_div & 0x00ff)>>8; + /* clear DLAB */ + ret = ret & 0x7f; + port->UART_LCR = ret; + + //line control + port->UART_LCR = lcr_reg; + //fifo control + port->UART_FCR = UART_FCR_FIFOE | UART_FCR_RFIFOR | UART_FCR_XFIFOR | UART_FCR_TET_1_4 | UART_FCR_RT_ONE; } int uart_enable_irq(uart *port, UINT32 mode) { - unsigned int ret; - ret = port->UART_IER; - ret |= mode; - port->UART_IER = ret; + unsigned int ret; + ret = port->UART_IER; + ret |= mode; + port->UART_IER = ret; } int uart_disable_irq(uart *port, UINT32 mode) { - unsigned int ret; - ret = port->UART_IER; - ret &= ~mode; + unsigned int ret; + ret = port->UART_IER; + ret &= ~mode; - port->UART_IER = ret; + port->UART_IER = ret; } UINT32 uart_get_iir_status(uart *port) { - return port->UART_IIR; + return port->UART_IIR; } UINT32 uart_get_line_status(uart *port) { - return port->UART_LSR; + return port->UART_LSR; } UINT32 uart_is_rx_ready(uart *port) { - return port->UART_LSR & UART_LSR_DR; + return port->UART_LSR & UART_LSR_DR; } UINT8 uart_getc(uart *port) { - return port->UART_RBR & 0xFF; + return port->UART_RBR & 0xFF; } void uart_putc(uart *port, UINT8 c) { - //while(!(port->UART_USR & UART_USR_TFNF)); - port->UART_THR = c; + //while(!(port->UART_USR & UART_USR_TFNF)); + port->UART_THR = c; } void uart_set_fifo_mode(uart *port, UINT32 fifo_mode) { - port->UART_FCR = fifo_mode; + port->UART_FCR = fifo_mode; } diff --git a/bsp/fh8620/libraries/driverlib/fh_wdt.c b/bsp/fh8620/libraries/driverlib/fh_wdt.c index 002a929bb..33e3defa1 100644 --- a/bsp/fh8620/libraries/driverlib/fh_wdt.c +++ b/bsp/fh8620/libraries/driverlib/fh_wdt.c @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,7 +18,7 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes diff --git a/bsp/fh8620/libraries/inc/fh_driverlib.h b/bsp/fh8620/libraries/inc/fh_driverlib.h index 9bb6b8c75..9f45eb836 100644 --- a/bsp/fh8620/libraries/inc/fh_driverlib.h +++ b/bsp/fh8620/libraries/inc/fh_driverlib.h @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,12 +18,12 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + #include #include #include "fh_def.h" diff --git a/bsp/fh8620/libraries/inc/fh_gpio.h b/bsp/fh8620/libraries/inc/fh_gpio.h index 62d1823eb..3d98a44be 100644 --- a/bsp/fh8620/libraries/inc/fh_gpio.h +++ b/bsp/fh8620/libraries/inc/fh_gpio.h @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,12 +18,12 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + #ifndef FH_GPIO_H_ #define FH_GPIO_H_ diff --git a/bsp/fh8620/libraries/inc/fh_i2c.h b/bsp/fh8620/libraries/inc/fh_i2c.h index 4debd9926..069aa8f27 100644 --- a/bsp/fh8620/libraries/inc/fh_i2c.h +++ b/bsp/fh8620/libraries/inc/fh_i2c.h @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,12 +18,12 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + #ifndef FH_I2C_H_ #define FH_I2C_H_ diff --git a/bsp/fh8620/libraries/inc/fh_ictl.h b/bsp/fh8620/libraries/inc/fh_ictl.h index 9796c99af..695971537 100644 --- a/bsp/fh8620/libraries/inc/fh_ictl.h +++ b/bsp/fh8620/libraries/inc/fh_ictl.h @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,7 +18,7 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes @@ -30,21 +30,21 @@ #include "fh_def.h" typedef struct { - RwReg IRQ_EN_L; - RwReg IRQ_EN_H; - RwReg IRQ_MASK_L; - RwReg IRQ_MASK_H; - RwReg IRQ_FORCE_L; - RwReg IRQ_FORCE_H; - RwReg IRQ_RAWSTARUS_L; - RwReg IRQ_RAWSTARUS_H; - RwReg IRQ_STATUS_L; - RwReg IRQ_STATUS_H; - RwReg IRQ_MASKSTATUS_L; - RwReg IRQ_MASKSTATUS_H; - RwReg IRQ_FINALSTATUS_L; - RwReg IRQ_FINALSTATUS_H; - RwReg IRQ_VECTOR; + RwReg IRQ_EN_L; + RwReg IRQ_EN_H; + RwReg IRQ_MASK_L; + RwReg IRQ_MASK_H; + RwReg IRQ_FORCE_L; + RwReg IRQ_FORCE_H; + RwReg IRQ_RAWSTARUS_L; + RwReg IRQ_RAWSTARUS_H; + RwReg IRQ_STATUS_L; + RwReg IRQ_STATUS_H; + RwReg IRQ_MASKSTATUS_L; + RwReg IRQ_MASKSTATUS_H; + RwReg IRQ_FINALSTATUS_L; + RwReg IRQ_FINALSTATUS_H; + RwReg IRQ_VECTOR; }fh_intc; diff --git a/bsp/fh8620/libraries/inc/fh_mmc.h b/bsp/fh8620/libraries/inc/fh_mmc.h index 4aaf416ce..d999ecf7d 100644 --- a/bsp/fh8620/libraries/inc/fh_mmc.h +++ b/bsp/fh8620/libraries/inc/fh_mmc.h @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,7 +18,7 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes diff --git a/bsp/fh8620/libraries/inc/fh_pwm.h b/bsp/fh8620/libraries/inc/fh_pwm.h index 011da4390..6281a5f12 100644 --- a/bsp/fh8620/libraries/inc/fh_pwm.h +++ b/bsp/fh8620/libraries/inc/fh_pwm.h @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,7 +18,7 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes diff --git a/bsp/fh8620/libraries/inc/fh_sdio.h b/bsp/fh8620/libraries/inc/fh_sdio.h index b268dbd32..f4791605e 100644 --- a/bsp/fh8620/libraries/inc/fh_sdio.h +++ b/bsp/fh8620/libraries/inc/fh_sdio.h @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,7 +18,7 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes @@ -32,53 +32,53 @@ //#define __ASIC_BRANCH__ enum { - CTRL = 0x0, /** Control */ - PWREN = 0x4, /** Power-enable */ - CLKDIV = 0x8, /** Clock divider */ - CLKSRC = 0xC, /** Clock source */ - CLKENA = 0x10, /** Clock enable */ - TMOUT = 0x14, /** Timeout */ - CTYPE = 0x18, /** Card type */ - BLKSIZ = 0x1C, /** Block Size */ - BYTCNT = 0x20, /** Byte count */ - INTMSK = 0x24, /** Interrupt Mask */ - CMDARG = 0x28, /** Command Argument */ - CMD = 0x2C, /** Command */ - RESP0 = 0x30, /** Response 0 */ - RESP1 = 0x34, /** Response 1 */ - RESP2 = 0x38, /** Response 2 */ - RESP3 = 0x3C, /** Response 3 */ - MINTSTS = 0x40, /** Masked interrupt status */ - RINTSTS = 0x44, /** Raw interrupt status */ - STATUS = 0x48, /** Status */ - FIFOTH = 0x4C, /** FIFO threshold */ - CDETECT = 0x50, /** Card detect */ - WRTPRT = 0x54, /** Write protect */ - GPIO = 0x58, /** General Purpose IO */ - TCBCNT = 0x5C, /** Transferred CIU byte count */ - TBBCNT = 0x60, /** Transferred host/DMA to/from byte count */ - DEBNCE = 0x64, /** Card detect debounce */ - USRID = 0x68, /** User ID */ - VERID = 0x6C, /** Version ID */ - HCON = 0x70, /** Hardware Configuration */ - UHSREG = 0x74, /** Reserved */ - BMOD = 0x80, /** Bus mode Register */ - PLDMND = 0x84, /** Poll Demand */ - DBADDR = 0x88, /** Descriptor Base Address */ - IDSTS = 0x8C, /** Internal DMAC Status */ - IDINTEN = 0x90, /** Internal DMAC Interrupt Enable */ - DSCADDR = 0x94, /** Current Host Descriptor Address */ - BUFADDR = 0x98, /** Current Host Buffer Address */ - FIFODAT = 0x200, /** FIFO data read write */ + CTRL = 0x0, /** Control */ + PWREN = 0x4, /** Power-enable */ + CLKDIV = 0x8, /** Clock divider */ + CLKSRC = 0xC, /** Clock source */ + CLKENA = 0x10, /** Clock enable */ + TMOUT = 0x14, /** Timeout */ + CTYPE = 0x18, /** Card type */ + BLKSIZ = 0x1C, /** Block Size */ + BYTCNT = 0x20, /** Byte count */ + INTMSK = 0x24, /** Interrupt Mask */ + CMDARG = 0x28, /** Command Argument */ + CMD = 0x2C, /** Command */ + RESP0 = 0x30, /** Response 0 */ + RESP1 = 0x34, /** Response 1 */ + RESP2 = 0x38, /** Response 2 */ + RESP3 = 0x3C, /** Response 3 */ + MINTSTS = 0x40, /** Masked interrupt status */ + RINTSTS = 0x44, /** Raw interrupt status */ + STATUS = 0x48, /** Status */ + FIFOTH = 0x4C, /** FIFO threshold */ + CDETECT = 0x50, /** Card detect */ + WRTPRT = 0x54, /** Write protect */ + GPIO = 0x58, /** General Purpose IO */ + TCBCNT = 0x5C, /** Transferred CIU byte count */ + TBBCNT = 0x60, /** Transferred host/DMA to/from byte count */ + DEBNCE = 0x64, /** Card detect debounce */ + USRID = 0x68, /** User ID */ + VERID = 0x6C, /** Version ID */ + HCON = 0x70, /** Hardware Configuration */ + UHSREG = 0x74, /** Reserved */ + BMOD = 0x80, /** Bus mode Register */ + PLDMND = 0x84, /** Poll Demand */ + DBADDR = 0x88, /** Descriptor Base Address */ + IDSTS = 0x8C, /** Internal DMAC Status */ + IDINTEN = 0x90, /** Internal DMAC Interrupt Enable */ + DSCADDR = 0x94, /** Current Host Descriptor Address */ + BUFADDR = 0x98, /** Current Host Buffer Address */ + FIFODAT = 0x200, /** FIFO data read write */ }; /* Control register definitions */ -#define CTRL_RESET 0x00000001 +#define CTRL_RESET 0x00000001 #define FIFO_RESET 0x00000002 -#define DMA_RESET 0x00000004 -#define INT_ENABLE 0x00000010 -#define READ_WAIT 0x00000040 -#define CTRL_USE_IDMAC 0x02000000 +#define DMA_RESET 0x00000004 +#define INT_ENABLE 0x00000010 +#define READ_WAIT 0x00000040 +#define CTRL_USE_IDMAC 0x02000000 /* Interrupt mask defines */ #define INTMSK_CDETECT 0x00000001 @@ -102,11 +102,11 @@ enum { #define INTMASK_ERROR (INTMSK_RESP_ERR|INTMSK_RCRC|INTMSK_DCRC|INTMSK_RTO|INTMSK_DTO|INTMSK_HTO|INTMSK_FRUN|INTMSK_HLE|INTMSK_SBE|INTMSK_EBE) /*BMOD register define */ -#define BMOD_SWR 0x00000001 -#define BMOD_DE 0x00000080 +#define BMOD_SWR 0x00000001 +#define BMOD_DE 0x00000080 /* for STATUS register */ -#define GET_FIFO_COUNT(x) (((x)&0x3ffe0000)>>17) +#define GET_FIFO_COUNT(x) (((x)&0x3ffe0000)>>17) #define GET_FIFO_DEPTH(x) ((((x)&0x0FFF0000)>>16)+1) /* for IDMA intr register */ @@ -122,62 +122,62 @@ enum { /* Define Card status bits (R1 response) */ #define R1CS_ADDRESS_OUT_OF_RANGE 0x80000000 -#define R1CS_ADDRESS_MISALIGN 0x40000000 -#define R1CS_BLOCK_LEN_ERR 0x20000000 -#define R1CS_ERASE_SEQ_ERR 0x10000000 -#define R1CS_ERASE_PARAM 0x08000000 -#define R1CS_WP_VIOLATION 0x04000000 -#define R1CS_CARD_IS_LOCKED 0x02000000 -#define R1CS_LCK_UNLCK_FAILED 0x01000000 -#define R1CS_COM_CRC_ERROR 0x00800000 -#define R1CS_ILLEGAL_COMMAND 0x00400000 -#define R1CS_CARD_ECC_FAILED 0x00200000 -#define R1CS_CC_ERROR 0x00100000 -#define R1CS_ERROR 0x00080000 -#define R1CS_UNDERRUN 0x00040000 -#define R1CS_OVERRUN 0x00020000 -#define R1CS_CSD_OVERWRITE 0x00010000 -#define R1CS_WP_ERASE_SKIP 0x00008000 -#define R1CS_RESERVED_0 0x00004000 -#define R1CS_ERASE_RESET 0x00002000 -#define R1CS_CURRENT_STATE_MASK 0x00001e00 -#define R1CS_READY_FOR_DATA 0x00000100 -#define R1CS_SWITCH_ERROR 0x00000080 -#define R1CS_RESERVED_1 0x00000040 -#define R1CS_APP_CMD 0x00000020 -#define R1CS_RESERVED_2 0x00000010 -#define R1CS_APP_SPECIFIC_MASK 0x0000000c -#define R1CS_MANUFAC_TEST_MASK 0x00000003 -#define R1CS_ERROR_OCCURED_MAP 0xfdffa080 -#define R1CS_CURRENT_STATE(x) (((x)&R1CS_CURRENT_STATE_MASK)>>9) +#define R1CS_ADDRESS_MISALIGN 0x40000000 +#define R1CS_BLOCK_LEN_ERR 0x20000000 +#define R1CS_ERASE_SEQ_ERR 0x10000000 +#define R1CS_ERASE_PARAM 0x08000000 +#define R1CS_WP_VIOLATION 0x04000000 +#define R1CS_CARD_IS_LOCKED 0x02000000 +#define R1CS_LCK_UNLCK_FAILED 0x01000000 +#define R1CS_COM_CRC_ERROR 0x00800000 +#define R1CS_ILLEGAL_COMMAND 0x00400000 +#define R1CS_CARD_ECC_FAILED 0x00200000 +#define R1CS_CC_ERROR 0x00100000 +#define R1CS_ERROR 0x00080000 +#define R1CS_UNDERRUN 0x00040000 +#define R1CS_OVERRUN 0x00020000 +#define R1CS_CSD_OVERWRITE 0x00010000 +#define R1CS_WP_ERASE_SKIP 0x00008000 +#define R1CS_RESERVED_0 0x00004000 +#define R1CS_ERASE_RESET 0x00002000 +#define R1CS_CURRENT_STATE_MASK 0x00001e00 +#define R1CS_READY_FOR_DATA 0x00000100 +#define R1CS_SWITCH_ERROR 0x00000080 +#define R1CS_RESERVED_1 0x00000040 +#define R1CS_APP_CMD 0x00000020 +#define R1CS_RESERVED_2 0x00000010 +#define R1CS_APP_SPECIFIC_MASK 0x0000000c +#define R1CS_MANUFAC_TEST_MASK 0x00000003 +#define R1CS_ERROR_OCCURED_MAP 0xfdffa080 +#define R1CS_CURRENT_STATE(x) (((x)&R1CS_CURRENT_STATE_MASK)>>9) /* R5 response */ -#define R5_IO_CRC_ERR 0x00008000 -#define R5_IO_BAD_CMD 0x00004000 -#define R5_IO_GEN_ERR 0x00000800 -#define R5_IO_FUNC_ERR 0x00000200 +#define R5_IO_CRC_ERR 0x00008000 +#define R5_IO_BAD_CMD 0x00004000 +#define R5_IO_GEN_ERR 0x00000800 +#define R5_IO_FUNC_ERR 0x00000200 #define R5_IO_OUT_RANGE 0x00000100 -#define R5_IO_ERR_BITS 0x0000cb00 +#define R5_IO_ERR_BITS 0x0000cb00 enum { - NONE_TYPE = 0, - SD_TYPE, - SD_2_0_TYPE, - SDIO_TYPE, + NONE_TYPE = 0, + SD_TYPE, + SD_2_0_TYPE, + SDIO_TYPE, }; enum { - CARD_STATE_EMPTY = -1, - CARD_STATE_IDLE = 0, - CARD_STATE_READY = 1, - CARD_STATE_IDENT = 2, - CARD_STATE_STBY = 3, - CARD_STATE_TRAN = 4, - CARD_STATE_DATA = 5, - CARD_STATE_RCV = 6, - CARD_STATE_PRG = 7, - CARD_STATE_DIS = 8, - CARD_STATE_INA = 9 + CARD_STATE_EMPTY = -1, + CARD_STATE_IDLE = 0, + CARD_STATE_READY = 1, + CARD_STATE_IDENT = 2, + CARD_STATE_STBY = 3, + CARD_STATE_TRAN = 4, + CARD_STATE_DATA = 5, + CARD_STATE_RCV = 6, + CARD_STATE_PRG = 7, + CARD_STATE_DIS = 8, + CARD_STATE_INA = 9 }; enum DmaDescriptorDES1 // Buffer's size field of Descriptor @@ -204,28 +204,28 @@ enum DmaDescriptorDES0 // Control and status word of DMA descriptor DES0 }; typedef struct DmaDescStruct { - unsigned int desc0; /* control and status information of descriptor */ - unsigned int desc1; /* buffer sizes */ - unsigned int desc2; /* physical address of the buffer 1 */ - unsigned int desc3; /* physical address of the buffer 2 */ + unsigned int desc0; /* control and status information of descriptor */ + unsigned int desc1; /* buffer sizes */ + unsigned int desc2; /* physical address of the buffer 1 */ + unsigned int desc3; /* physical address of the buffer 2 */ }DmaDesc; typedef struct { - unsigned int wkmod; - volatile DmaDesc *pDmaDesc; - unsigned int idma_support; - unsigned int rca; - unsigned int ip_base; - unsigned int card_type; - unsigned int fifo_depth; - unsigned int fifo_threth; - unsigned int sectors; - unsigned int scr[2]; - unsigned int csd[4]; - unsigned int idsts; - rt_sem_t sem; - rt_sem_t mutex; - void (*cb)(void); + unsigned int wkmod; + volatile DmaDesc *pDmaDesc; + unsigned int idma_support; + unsigned int rca; + unsigned int ip_base; + unsigned int card_type; + unsigned int fifo_depth; + unsigned int fifo_threth; + unsigned int sectors; + unsigned int scr[2]; + unsigned int csd[4]; + unsigned int idsts; + rt_sem_t sem; + rt_sem_t mutex; + void (*cb)(void); } sdc_t; #define ONE_BIT_MODE (0) @@ -244,55 +244,55 @@ typedef struct { enum { - ERRNOERROR = 0, - - // for raw interrupt status error - ERRRESPRECEP, // 1 - ERRRESPCRC, - ERRDCRC, - ERRRESPTIMEOUT, - ERRDRTIMEOUT, - ERRUNDERWRITE, - ERROVERREAD, - ERRHLE, - ERRSTARTBIT, - ERRENDBITERR, // 10 - - // for R1 response - ERRADDRESSRANGE, // 11 - ERRADDRESSMISALIGN, - ERRBLOCKLEN, - ERRERASESEQERR, - ERRERASEPARAM, - ERRPROT, - ERRCARDLOCKED, - ERRCRC, - ERRILLEGALCOMMAND, - ERRECCFAILED, - ERRCCERR, - ERRUNKNOWN, - ERRUNDERRUN, - ERROVERRUN, - ERRCSDOVERWRITE, - ERRERASERESET, - ERRFSMSTATE, // 27 - - // for R5 response - ERRBADFUNC, // 28 - - // others - ERRCARDNOTCONN, // 29 - ERRCARDWPROTECT, - ERRCMDRETRIESOVER, - ERRNOTSUPPORTED, - ERRHARDWARE, - ERRDATANOTREADY, - ERRCARDINTERNAL, - ERRACMD41TIMEOUT, - ERRIDMA, - ERRNORES, - - ERRNOTEQUAL, + ERRNOERROR = 0, + + // for raw interrupt status error + ERRRESPRECEP, // 1 + ERRRESPCRC, + ERRDCRC, + ERRRESPTIMEOUT, + ERRDRTIMEOUT, + ERRUNDERWRITE, + ERROVERREAD, + ERRHLE, + ERRSTARTBIT, + ERRENDBITERR, // 10 + + // for R1 response + ERRADDRESSRANGE, // 11 + ERRADDRESSMISALIGN, + ERRBLOCKLEN, + ERRERASESEQERR, + ERRERASEPARAM, + ERRPROT, + ERRCARDLOCKED, + ERRCRC, + ERRILLEGALCOMMAND, + ERRECCFAILED, + ERRCCERR, + ERRUNKNOWN, + ERRUNDERRUN, + ERROVERRUN, + ERRCSDOVERWRITE, + ERRERASERESET, + ERRFSMSTATE, // 27 + + // for R5 response + ERRBADFUNC, // 28 + + // others + ERRCARDNOTCONN, // 29 + ERRCARDWPROTECT, + ERRCMDRETRIESOVER, + ERRNOTSUPPORTED, + ERRHARDWARE, + ERRDATANOTREADY, + ERRCARDINTERNAL, + ERRACMD41TIMEOUT, + ERRIDMA, + ERRNORES, + + ERRNOTEQUAL, }; #ifdef __ASIC_BRANCH__ @@ -352,5 +352,5 @@ extern int sdio_drv_creg_write(HSDC handle, int addr, int fn, unsigned char data extern void inv_dcache_range(unsigned long start, unsigned long len); extern void flush_dcache_range(unsigned long start, unsigned long len); - + #endif //__sdcard_h__ diff --git a/bsp/fh8620/libraries/inc/fh_spi.h b/bsp/fh8620/libraries/inc/fh_spi.h index d81c2428b..689a85b3f 100644 --- a/bsp/fh8620/libraries/inc/fh_spi.h +++ b/bsp/fh8620/libraries/inc/fh_spi.h @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,12 +18,12 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + #ifndef FH_SPI_H_ #define FH_SPI_H_ @@ -97,8 +97,8 @@ #define SPI_STATUS_BUSY (1) -#define SPI_TX_DMA (1<<1) -#define SPI_RX_DMA (1<<0) +#define SPI_TX_DMA (1<<1) +#define SPI_RX_DMA (1<<0) struct spi_config diff --git a/bsp/fh8620/libraries/inc/fh_timer.h b/bsp/fh8620/libraries/inc/fh_timer.h index 715a73b25..9f88bff22 100644 --- a/bsp/fh8620/libraries/inc/fh_timer.h +++ b/bsp/fh8620/libraries/inc/fh_timer.h @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,7 +18,7 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes @@ -29,7 +29,7 @@ /**************************************************************************** * #include section - * add #include here if any + * add #include here if any ***************************************************************************/ #include "fh_def.h" @@ -38,7 +38,7 @@ /**************************************************************************** * #define section - * add constant #define here if any + * add constant #define here if any ***************************************************************************/ #define TIMER_CTRL_ENABLE (1u << 0) #define TIMER_CTRL_MODE (1u << 1) @@ -49,19 +49,19 @@ /**************************************************************************** * ADT section - * add Abstract Data Type definition here + * add Abstract Data Type definition here ***************************************************************************/ typedef struct { - RwReg TIMER_LOAD_COUNT; - RwReg TIMER_CURRENT_VALUE; - RwReg TIMER_CTRL_REG; - RwReg TIMER_EOI; - RwReg TIMER_INT_STATUS; + RwReg TIMER_LOAD_COUNT; + RwReg TIMER_CURRENT_VALUE; + RwReg TIMER_CTRL_REG; + RwReg TIMER_EOI; + RwReg TIMER_INT_STATUS; }timer; enum timer_mode { - TIMER_MODE_PERIODIC = 0, - TIMER_MODE_ONESHOT = 1, + TIMER_MODE_PERIODIC = 0, + TIMER_MODE_ONESHOT = 1, }; @@ -73,7 +73,7 @@ typedef struct { /**************************************************************************** * section -* add function prototype here if any +* add function prototype here if any ***************************************************************************/ diff --git a/bsp/fh8620/libraries/inc/fh_uart.h b/bsp/fh8620/libraries/inc/fh_uart.h index 87da9ee2f..34d2a9bb9 100644 --- a/bsp/fh8620/libraries/inc/fh_uart.h +++ b/bsp/fh8620/libraries/inc/fh_uart.h @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,7 +18,7 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes @@ -29,13 +29,13 @@ /**************************************************************************** * #include section - * add #include here if any + * add #include here if any ***************************************************************************/ #include "fh_def.h" /**************************************************************************** * #define section - * add constant #define here if any + * add constant #define here if any ***************************************************************************/ #define UART_RBR RBRTHRDLL @@ -120,53 +120,53 @@ #define UART_IIR_FIFOSE (0x03 << 6) //uart baudrate cofig -//#define UART_CLOCK_FREQ (27000000) //27MHZ +//#define UART_CLOCK_FREQ (27000000) //27MHZ // -//#define DIV(n) (((UART_CLOCK_FREQ/(n))+8)/16) +//#define DIV(n) (((UART_CLOCK_FREQ/(n))+8)/16) /**************************************************************************** * ADT section - * add Abstract Data Type definition here + * add Abstract Data Type definition here ***************************************************************************/ typedef struct { - RwReg RBRTHRDLL; /* UART_RBR, UART_THR, UART_DLL */ - RwReg DLHIER; /* UART_DLH, UART_IER */ - RwReg IIRFCR; /* UART_IIR, UART_FCR */ - RwReg UART_LCR; /*(0x000c) */ - RwReg UART_MCR; /*(0x0010) */ - RwReg UART_LSR; /*(0x0014) */ - RwReg UART_MSR; /*(0x0018) */ - RwReg UART_SCR; /*(0x001c) */ - RwReg reserved[20]; - RwReg UART_FAR; /* (0x0070) */ - RwReg UART_TFR; /* (0x0074) */ - RwReg UART_RFW; /* (0x0078) */ - RwReg UART_USR; /* (0x007c) */ - RwReg UART_TFL; /* (0x0080) */ - RwReg UART_RFL; /* (0x0084) */ - RwReg UART_SRR; /* (0x0088) */ - RwReg reserved1[3]; - RwReg UART_SFE; /* (0x0098) */ - RwReg UART_SRT; /* (0x009c) */ - RwReg UART_STET; /* (0x00a0) */ - RwReg UART_HTX; /* (0x00a4) */ - RwReg UART_DMASA; /* (0x00a8) */ - RwReg reserved2[18]; - RwReg UART_CPR; /* (0x00f4) */ - RwReg UART_UCV; /* (0x00f8) */ - RwReg UART_CTR; /* (0x00fc) */ + RwReg RBRTHRDLL; /* UART_RBR, UART_THR, UART_DLL */ + RwReg DLHIER; /* UART_DLH, UART_IER */ + RwReg IIRFCR; /* UART_IIR, UART_FCR */ + RwReg UART_LCR; /*(0x000c) */ + RwReg UART_MCR; /*(0x0010) */ + RwReg UART_LSR; /*(0x0014) */ + RwReg UART_MSR; /*(0x0018) */ + RwReg UART_SCR; /*(0x001c) */ + RwReg reserved[20]; + RwReg UART_FAR; /* (0x0070) */ + RwReg UART_TFR; /* (0x0074) */ + RwReg UART_RFW; /* (0x0078) */ + RwReg UART_USR; /* (0x007c) */ + RwReg UART_TFL; /* (0x0080) */ + RwReg UART_RFL; /* (0x0084) */ + RwReg UART_SRR; /* (0x0088) */ + RwReg reserved1[3]; + RwReg UART_SFE; /* (0x0098) */ + RwReg UART_SRT; /* (0x009c) */ + RwReg UART_STET; /* (0x00a0) */ + RwReg UART_HTX; /* (0x00a4) */ + RwReg UART_DMASA; /* (0x00a8) */ + RwReg reserved2[18]; + RwReg UART_CPR; /* (0x00f4) */ + RwReg UART_UCV; /* (0x00f8) */ + RwReg UART_CTR; /* (0x00fc) */ }uart; struct fh_uart { - uart *uart_port; - int irq; + uart *uart_port; + int irq; }; @@ -174,34 +174,34 @@ struct fh_uart { enum data_bits { - UART_DATA_BIT5 = 0, - UART_DATA_BIT6 = 1, - UART_DATA_BIT7 = 2, - UART_DATA_BIT8 = 3 + UART_DATA_BIT5 = 0, + UART_DATA_BIT6 = 1, + UART_DATA_BIT7 = 2, + UART_DATA_BIT8 = 3 }; enum stop_bits { - UART_STOP_BIT1 = 0, - UART_STOP_BIT1_5 = 1, - UART_STOP_BIT2 = 2 + UART_STOP_BIT1 = 0, + UART_STOP_BIT1_5 = 1, + UART_STOP_BIT2 = 2 }; enum parity { - UART_PARITY_NONE = 0, - UART_PARITY_EVEN = 1, - UART_PARITY_ODD = 2, - UART_PARITY_ST = 3 /* Stick Parity */ + UART_PARITY_NONE = 0, + UART_PARITY_EVEN = 1, + UART_PARITY_ODD = 2, + UART_PARITY_ST = 3 /* Stick Parity */ }; -#define UART_CLOCK_FREQ (30000000) //30MHZ +#define UART_CLOCK_FREQ (30000000) //30MHZ typedef enum enum_uart_baudrate{ - BAUDRATE_9600 = (((UART_CLOCK_FREQ/9600)+8)/16), - BAUDRATE_19200 = (((UART_CLOCK_FREQ/19200)+8)/16), - BAUDRATE_38400 = (((UART_CLOCK_FREQ/38400)+8)/16), - BAUDRATE_57600 = (((UART_CLOCK_FREQ/57600)+8)/16), - BAUDRATE_115200 = (((UART_CLOCK_FREQ/115200)+8)/16), - BAUDRATE_194000 = (((UART_CLOCK_FREQ/194000)+8)/16), + BAUDRATE_9600 = (((UART_CLOCK_FREQ/9600)+8)/16), + BAUDRATE_19200 = (((UART_CLOCK_FREQ/19200)+8)/16), + BAUDRATE_38400 = (((UART_CLOCK_FREQ/38400)+8)/16), + BAUDRATE_57600 = (((UART_CLOCK_FREQ/57600)+8)/16), + BAUDRATE_115200 = (((UART_CLOCK_FREQ/115200)+8)/16), + BAUDRATE_194000 = (((UART_CLOCK_FREQ/194000)+8)/16), }uart_baudrate_e; /**************************************************************************** @@ -213,8 +213,8 @@ extern int uart_init(uart *port); extern UINT32 uart_get_status(uart *port); extern void uart_configure(uart *port, enum data_bits data_bit, - enum stop_bits stop_bit, enum parity parity, - UINT32 buard_rate, UINT32 uart_clk); + enum stop_bits stop_bit, enum parity parity, + UINT32 buard_rate, UINT32 uart_clk); extern int uart_enable_irq(uart *port, UINT32 mode); @@ -235,7 +235,7 @@ extern void uart_set_fifo_mode(uart *port, UINT32 fifo_mode); /**************************************************************************** * section -* add function prototype here if any +* add function prototype here if any ***************************************************************************/ diff --git a/bsp/fh8620/libraries/inc/fh_wdt.h b/bsp/fh8620/libraries/inc/fh_wdt.h index a90331dbd..7804a3a53 100644 --- a/bsp/fh8620/libraries/inc/fh_wdt.h +++ b/bsp/fh8620/libraries/inc/fh_wdt.h @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,12 +18,12 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + #ifndef FH_WDT_H_ #define FH_WDT_H_ diff --git a/bsp/fh8620/platform/board.h b/bsp/fh8620/platform/board.h index 46b276b05..ac8708ec9 100644 --- a/bsp/fh8620/platform/board.h +++ b/bsp/fh8620/platform/board.h @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,12 +18,12 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + #ifndef __BOARD_H__ #define __BOARD_H__ #include "platform_def.h" diff --git a/bsp/fh8620/platform/board_info.h b/bsp/fh8620/platform/board_info.h index 71f8d3c19..d86907621 100644 --- a/bsp/fh8620/platform/board_info.h +++ b/bsp/fh8620/platform/board_info.h @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,12 +18,12 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + #ifndef __BOARD_INFO_H__ #define __BOARD_INFO_H__ @@ -33,32 +33,32 @@ extern "C" { /**************************************************************************** * #include section - * add #include here if any + * add #include here if any ***************************************************************************/ /**************************************************************************** * #define section - * add constant #define here if any + * add constant #define here if any ***************************************************************************/ /**************************************************************************** * ADT section - * add Abstract Data Type definition here + * add Abstract Data Type definition here ***************************************************************************/ typedef int (*probe_p)(void *); typedef int (*exit_p)(void *); struct fh_board_ops { - //void *ops_data; - probe_p probe; - probe_p exit; + //void *ops_data; + probe_p probe; + probe_p exit; }; struct fh_board_info { - char *name; - void *data; - struct fh_board_ops *ops; + char *name; + void *data; + struct fh_board_ops *ops; }; @@ -73,7 +73,7 @@ void fh_print_all_board_info(void); void fh_free_all_info(void); /**************************************************************************** * section - * add function prototype here if any + * add function prototype here if any ***************************************************************************/ #ifdef __cplusplus diff --git a/bsp/fh8620/platform/common/board_info.c b/bsp/fh8620/platform/common/board_info.c index aa56cbac6..6bb95bfaa 100644 --- a/bsp/fh8620/platform/common/board_info.c +++ b/bsp/fh8620/platform/common/board_info.c @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,12 +18,12 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + /***************************************************************************** * Include Section * add all #include here @@ -36,27 +36,27 @@ * add all #define here *****************************************************************************/ struct fh_board_info_list_node { - struct fh_board_info obj; - rt_list_t list; + struct fh_board_info obj; + rt_list_t list; }; -#define CHECK_TEST_LIST_EMPTY \ - if(rt_list_isempty(&board_info_head.list)) \ - rt_kprintf("board info is null...please register first..\n") +#define CHECK_TEST_LIST_EMPTY \ + if(rt_list_isempty(&board_info_head.list)) \ + rt_kprintf("board info is null...please register first..\n") /**************************************************************************** * ADT section * add definition of user defined Data Type that only be used in this file here ***************************************************************************/ -#define list_for_each_entry_safe(pos, n, head, member) \ - for (pos = rt_list_entry((head)->next, typeof(*pos), member), \ - n = rt_list_entry(pos->member.next, typeof(*pos), member); \ - &pos->member != (head); \ - pos = n, n = rt_list_entry(n->member.next, typeof(*n), member)) +#define list_for_each_entry_safe(pos, n, head, member) \ + for (pos = rt_list_entry((head)->next, typeof(*pos), member), \ + n = rt_list_entry(pos->member.next, typeof(*pos), member); \ + &pos->member != (head); \ + pos = n, n = rt_list_entry(n->member.next, typeof(*n), member)) -#define PARA_ERROR (-1) -#define PROBE_FUNC_MISS (-2) +#define PARA_ERROR (-1) +#define PROBE_FUNC_MISS (-2) /****************************************************************************** * Function prototype section @@ -104,45 +104,45 @@ static struct fh_board_info_list_node board_info_head; int fh_board_info_init(void) { - memset(&board_info_head, 0x0, sizeof(struct fh_board_info_list_node)); - rt_list_init(&board_info_head.list); - board_info_head.obj.name = "NO INFO"; - return 0; + memset(&board_info_head, 0x0, sizeof(struct fh_board_info_list_node)); + rt_list_init(&board_info_head.list); + board_info_head.obj.name = "NO INFO"; + return 0; } void fh_free_all_info(void) { - rt_list_t *p_list; - struct fh_board_info_list_node *info_node; - struct fh_board_info_list_node *_info_node; - p_list = &board_info_head.list; - - CHECK_TEST_LIST_EMPTY; - - list_for_each_entry_safe(info_node, _info_node, p_list, list) - { - - if (info_node->obj.ops->exit) { - info_node->obj.ops->exit(info_node->obj.data); - } - rt_kprintf("soc free list name:(%s)\n", info_node->obj.name); - rt_free(info_node); - } - fh_board_info_init(); + rt_list_t *p_list; + struct fh_board_info_list_node *info_node; + struct fh_board_info_list_node *_info_node; + p_list = &board_info_head.list; + + CHECK_TEST_LIST_EMPTY; + + list_for_each_entry_safe(info_node, _info_node, p_list, list) + { + + if (info_node->obj.ops->exit) { + info_node->obj.ops->exit(info_node->obj.data); + } + rt_kprintf("soc free list name:(%s)\n", info_node->obj.name); + rt_free(info_node); + } + fh_board_info_init(); } void fh_print_all_board_info(void) { - rt_list_t *p_list; + rt_list_t *p_list; - struct fh_board_info_list_node *info_node; - struct fh_board_info_list_node *_info_node; - p_list = &board_info_head.list; + struct fh_board_info_list_node *info_node; + struct fh_board_info_list_node *_info_node; + p_list = &board_info_head.list; - CHECK_TEST_LIST_EMPTY; + CHECK_TEST_LIST_EMPTY; - list_for_each_entry_safe(info_node, _info_node, p_list, list) - { - rt_kprintf("%s\n", info_node->obj.name); - } + list_for_each_entry_safe(info_node, _info_node, p_list, list) + { + rt_kprintf("%s\n", info_node->obj.name); + } } /***************************************************************************** @@ -157,94 +157,94 @@ void fh_print_all_board_info(void) { //register the platform info such as base add,isr no.. //caution:do not free the name and data because of here not copy struct fh_board_info *fh_board_info_register(char *info_name, void *data) { - rt_list_t *p_list; - struct fh_board_info_list_node *new_node; - struct fh_board_info_list_node *info_node; - struct fh_board_info_list_node *_info_node; - p_list = &board_info_head.list; - - if (RT_NULL == info_name || RT_NULL == data) { - rt_kprintf("info name or info data is NULL!\n"); - return RT_NULL; - } - - //check if the func is already in the test list.... + rt_list_t *p_list; + struct fh_board_info_list_node *new_node; + struct fh_board_info_list_node *info_node; + struct fh_board_info_list_node *_info_node; + p_list = &board_info_head.list; + + if (RT_NULL == info_name || RT_NULL == data) { + rt_kprintf("info name or info data is NULL!\n"); + return RT_NULL; + } + + //check if the func is already in the test list.... #if(0) - list_for_each_entry_safe(info_node, _info_node, p_list, list) { - if (!memcmp(info_node->obj.name, info_name, strlen(info_name))) { - rt_kprintf("info_name(%s) is already registered\n", info_name); - return RT_NULL; - } - } + list_for_each_entry_safe(info_node, _info_node, p_list, list) { + if (!memcmp(info_node->obj.name, info_name, strlen(info_name))) { + rt_kprintf("info_name(%s) is already registered\n", info_name); + return RT_NULL; + } + } #endif - new_node = (struct fh_board_info_list_node *) rt_malloc( - sizeof(struct fh_board_info_list_node)); - if (!new_node) { - rt_kprintf("malloc new_list_node failed~\n"); - return RT_NULL; - } - - new_node->obj.name = info_name; - new_node->obj.data = data; - //here insert "before" and test is "after" will make the list like a fifo... - rt_list_insert_before(&board_info_head.list, &new_node->list); - return &new_node->obj; + new_node = (struct fh_board_info_list_node *) rt_malloc( + sizeof(struct fh_board_info_list_node)); + if (!new_node) { + rt_kprintf("malloc new_list_node failed~\n"); + return RT_NULL; + } + + new_node->obj.name = info_name; + new_node->obj.data = data; + //here insert "before" and test is "after" will make the list like a fifo... + rt_list_insert_before(&board_info_head.list, &new_node->list); + return &new_node->obj; } //back the platform info static void *fh_get_board_info_data(char *info_name) { - rt_list_t *p_list; - struct fh_board_info_list_node *info_node; - struct fh_board_info_list_node *_info_node; - p_list = &board_info_head.list; + rt_list_t *p_list; + struct fh_board_info_list_node *info_node; + struct fh_board_info_list_node *_info_node; + p_list = &board_info_head.list; - //check info name - if (RT_NULL == info_name) { - rt_kprintf("info name is NULL!\n"); - return RT_NULL; - } + //check info name + if (RT_NULL == info_name) { + rt_kprintf("info name is NULL!\n"); + return RT_NULL; + } - CHECK_TEST_LIST_EMPTY; + CHECK_TEST_LIST_EMPTY; - list_for_each_entry_safe(info_node, _info_node, p_list, list) - { - if (!strcmp(info_node->obj.name, info_name)) { - return info_node->obj.data; - } - } + list_for_each_entry_safe(info_node, _info_node, p_list, list) + { + if (!strcmp(info_node->obj.name, info_name)) { + return info_node->obj.data; + } + } - rt_kprintf("Can't find the board info name:%s\n", info_name); + rt_kprintf("Can't find the board info name:%s\n", info_name); } int fh_board_driver_register(char *info_name, struct fh_board_ops *ops) { - rt_list_t *p_list; - struct fh_board_info_list_node *new_node; - struct fh_board_info_list_node *info_node; - struct fh_board_info_list_node *_info_node; - p_list = &board_info_head.list; + rt_list_t *p_list; + struct fh_board_info_list_node *new_node; + struct fh_board_info_list_node *info_node; + struct fh_board_info_list_node *_info_node; + p_list = &board_info_head.list; - if (RT_NULL == info_name || RT_NULL == ops) { - rt_kprintf("info name or ops func is NULL!\n"); - return PARA_ERROR; - } + if (RT_NULL == info_name || RT_NULL == ops) { + rt_kprintf("info name or ops func is NULL!\n"); + return PARA_ERROR; + } - list_for_each_entry_safe(info_node, _info_node, p_list, list) - { - if (!strcmp(info_node->obj.name, info_name)) { + list_for_each_entry_safe(info_node, _info_node, p_list, list) + { + if (!strcmp(info_node->obj.name, info_name)) { - info_node->obj.ops = ops; - if (info_node->obj.ops->probe) { - info_node->obj.ops->probe(info_node->obj.data); - } + info_node->obj.ops = ops; + if (info_node->obj.ops->probe) { + info_node->obj.ops->probe(info_node->obj.data); + } - //return info_node->obj.data; - } - } + //return info_node->obj.data; + } + } - //rt_kprintf("Can't find the board info name:%s\n",info_name); + //rt_kprintf("Can't find the board info name:%s\n",info_name); - return 0; + return 0; } diff --git a/bsp/fh8620/platform/common/chkenv.c b/bsp/fh8620/platform/common/chkenv.c index 563b5bb55..e2d8f18b2 100644 --- a/bsp/fh8620/platform/common/chkenv.c +++ b/bsp/fh8620/platform/common/chkenv.c @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,12 +18,12 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + /***************************************************************************** * Include Section * add all #include here @@ -47,11 +47,11 @@ * * **************************/ -#if RT_NAME_MAX != 16 +#if RT_NAME_MAX != 16 #error "define RT_NAME_MAX 16" #endif -#if RT_TICK_PER_SECOND != 100 +#if RT_TICK_PER_SECOND != 100 #warning "RT_TICK_PER_SECOND = 100" #endif diff --git a/bsp/fh8620/platform/fh8620/arch.h b/bsp/fh8620/platform/fh8620/arch.h index df0e7f196..306c1239e 100644 --- a/bsp/fh8620/platform/fh8620/arch.h +++ b/bsp/fh8620/platform/fh8620/arch.h @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,12 +18,12 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + #ifndef ARCH_H_ #define ARCH_H_ @@ -31,37 +31,37 @@ /*****************************/ /* BSP CONTROLLER BASE */ /*****************************/ -#define INTC_REG_BASE (0xE0200000) -#define SDC0_REG_BASE (0xE2000000) -#define SDC1_REG_BASE (0xE2100000) -#define TVE_REG_BASE (0xE8000000) -#define VOU_REG_BASE (0xE8100000) -#define AES_REG_BASE (0xE8200000) -#define JPEG_REG_BASE (0xE8300000) -#define ISPB_REG_BASE (0xEA000000) -#define ISPF_REG_BASE (0xEA100000) -#define VPU_REG_BASE (0xEC000000) -#define VCU_REG_BASE (0xEC100000) -#define DDRC_REG_BASE (0xED000000) -#define DMAC_REG_BASE (0xEE000000) -#define GMAC_REG_BASE (0xEF000000) -#define PMU_REG_BASE (0xF0000000) -#define I2C0_REG_BASE (0xF0200000) -#define GPIO0_REG_BASE (0xF0300000) +#define INTC_REG_BASE (0xE0200000) +#define SDC0_REG_BASE (0xE2000000) +#define SDC1_REG_BASE (0xE2100000) +#define TVE_REG_BASE (0xE8000000) +#define VOU_REG_BASE (0xE8100000) +#define AES_REG_BASE (0xE8200000) +#define JPEG_REG_BASE (0xE8300000) +#define ISPB_REG_BASE (0xEA000000) +#define ISPF_REG_BASE (0xEA100000) +#define VPU_REG_BASE (0xEC000000) +#define VCU_REG_BASE (0xEC100000) +#define DDRC_REG_BASE (0xED000000) +#define DMAC_REG_BASE (0xEE000000) +#define GMAC_REG_BASE (0xEF000000) +#define PMU_REG_BASE (0xF0000000) +#define I2C0_REG_BASE (0xF0200000) +#define GPIO0_REG_BASE (0xF0300000) #define GPIO1_REG_BASE (0xf4000000) -#define PWM_REG_BASE (0xF0400000) -#define SPI0_REG_BASE (0xF0500000) -#define SPI1_REG_BASE (0xF0600000) -#define UART0_REG_BASE (0xF0700000) -#define UART1_REG_BASE (0xF0800000) -#define I2S_REG_BASE (0xF0900000) -#define ACODEC_REG_BASE (0xF0A00000) -#define I2C1_REG_BASE (0xF0B00000) -#define TMR_REG_BASE (0xF0C00000) -#define WDT_REG_BASE (0xF0D00000) -#define DPHY_REG_BASE (0xF1000000) -#define MIPIC_REG_BASE (0xF1100000) -#define SADC_REG_BASE (0xF1200000) +#define PWM_REG_BASE (0xF0400000) +#define SPI0_REG_BASE (0xF0500000) +#define SPI1_REG_BASE (0xF0600000) +#define UART0_REG_BASE (0xF0700000) +#define UART1_REG_BASE (0xF0800000) +#define I2S_REG_BASE (0xF0900000) +#define ACODEC_REG_BASE (0xF0A00000) +#define I2C1_REG_BASE (0xF0B00000) +#define TMR_REG_BASE (0xF0C00000) +#define WDT_REG_BASE (0xF0D00000) +#define DPHY_REG_BASE (0xF1000000) +#define MIPIC_REG_BASE (0xF1100000) +#define SADC_REG_BASE (0xF1200000) diff --git a/bsp/fh8620/platform/fh8620/iot_cam/board.c b/bsp/fh8620/platform/fh8620/iot_cam/board.c index 8e45b9be9..a726ce5ef 100644 --- a/bsp/fh8620/platform/fh8620/iot_cam/board.c +++ b/bsp/fh8620/platform/fh8620/iot_cam/board.c @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,12 +18,12 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + /***************************************************************************** * Include Section * add all #include here @@ -67,15 +67,15 @@ #ifndef HW_SDCARD_POWER_GPIO - #define HW_SDCARD_POWER_GPIO 63 //not used + #define HW_SDCARD_POWER_GPIO 63 //not used #endif /**************************************************************************** * ADT section * add definition of user defined Data Type that only be used in this file here ***************************************************************************/ struct st_platform_info { - char *name; - void *private_data; + char *name; + void *private_data; }; /****************************************************************************** @@ -101,14 +101,14 @@ struct st_platform_info { void fh_mmc_reset(struct fh_mmc_obj *mmc_obj) { - rt_uint32_t value; - if (mmc_obj->id) - fh_pmu_write(REG_PMU_SWRST_AHB_CTRL, 0xfffffffd); - else - fh_pmu_write(REG_PMU_SWRST_AHB_CTRL, 0xfffffffb); - do { - fh_pmu_read(REG_PMU_SWRST_AHB_CTRL, &value); - } while (value != 0xffffffff); + rt_uint32_t value; + if (mmc_obj->id) + fh_pmu_write(REG_PMU_SWRST_AHB_CTRL, 0xfffffffd); + else + fh_pmu_write(REG_PMU_SWRST_AHB_CTRL, 0xfffffffb); + do { + fh_pmu_read(REG_PMU_SWRST_AHB_CTRL, &value); + } while (value != 0xffffffff); } static struct fh_mmc_obj mmc0_obj = @@ -130,8 +130,8 @@ static struct fh_mmc_obj mmc1_obj = }; #ifdef RT_USING_SPI -#define SPI0_CLK_IN (50000000) -#define SPI0_MAX_BAUD (SPI0_CLK_IN/2) +#define SPI0_CLK_IN (50000000) +#define SPI0_MAX_BAUD (SPI0_CLK_IN/2) static struct spi_control_platform_data spi0_platform_data = { @@ -152,8 +152,8 @@ static struct spi_control_platform_data spi0_platform_data = }; -#define SPI1_CLK_IN (50000000) -#define SPI1_MAX_BAUD (SPI1_CLK_IN/2) +#define SPI1_CLK_IN (50000000) +#define SPI1_MAX_BAUD (SPI1_CLK_IN/2) static struct spi_control_platform_data spi1_platform_data = { @@ -217,10 +217,10 @@ static struct fh_wdt_obj wdt_obj = #ifdef RT_USING_SADC static struct wrap_sadc_obj sadc_obj = { - .id = 0, - .regs = (void *)SADC_REG_BASE, - .irq_no = SADC_IRQn, - .sample_mode = ISR_MODE, + .id = 0, + .regs = (void *)SADC_REG_BASE, + .irq_no = SADC_IRQn, + .sample_mode = ISR_MODE, }; #endif @@ -366,8 +366,8 @@ struct st_platform_info plat_sadc = #endif const static struct st_platform_info *platform_info[] = { - &plat_mmc0, - //&plat_mmc1,//by PeterJiang, wifi don't use SDIO framework... + &plat_mmc0, + //&plat_mmc1,//by PeterJiang, wifi don't use SDIO framework... #ifdef RT_USING_SPI &plat_spi0, #endif @@ -400,168 +400,168 @@ const static struct st_platform_info *platform_info[] = { void clock_init(void) { - //UINT32 reg; - //gate enable, spi0, gmac, uart0, timer0, wdt, pts + //UINT32 reg; + //gate enable, spi0, gmac, uart0, timer0, wdt, pts #ifdef YG_TEK - fh_pmu_write_mask(REG_PMU_PAD_MAC_TXER_CFG, 0x100000, 0x100000); + fh_pmu_write_mask(REG_PMU_PAD_MAC_TXER_CFG, 0x100000, 0x100000); #endif - //SPI0 - fh_pmu_write_mask(REG_PMU_CLK_DIV3, 0xb, 0xff); + //SPI0 + fh_pmu_write_mask(REG_PMU_CLK_DIV3, 0xb, 0xff); - //GMAC - fh_pmu_write_mask(REG_PMU_CLK_DIV6, 0x5000000, 0xf000000); + //GMAC + fh_pmu_write_mask(REG_PMU_CLK_DIV6, 0x5000000, 0xf000000); - //UART0 - fh_pmu_write_mask(REG_PMU_CLK_DIV4, 0x1, 0xf); + //UART0 + fh_pmu_write_mask(REG_PMU_CLK_DIV4, 0x1, 0xf); - //TIMER0 - fh_pmu_write_mask(REG_PMU_CLK_DIV5, 0x1d0000, 0x3f0000); + //TIMER0 + fh_pmu_write_mask(REG_PMU_CLK_DIV5, 0x1d0000, 0x3f0000); - //PTS - fh_pmu_write_mask(REG_PMU_CLK_DIV2, 0x23, 0x3f); + //PTS + fh_pmu_write_mask(REG_PMU_CLK_DIV2, 0x23, 0x3f); - //WDT - //fh_pmu_write_mask(REG_PMU_CLK_DIV5, 0x1d00, 0x3f00); - fh_pmu_write_mask(REG_PMU_CLK_DIV5, 0x3500, 0x3f00); + //WDT + //fh_pmu_write_mask(REG_PMU_CLK_DIV5, 0x1d00, 0x3f00); + fh_pmu_write_mask(REG_PMU_CLK_DIV5, 0x3500, 0x3f00); - //clock enable - fh_pmu_write_mask(REG_PMU_CLK_GATE, 0, 0x720ba080); + //clock enable + fh_pmu_write_mask(REG_PMU_CLK_GATE, 0, 0x720ba080); //sd0_drv_sel - fh_pmu_write_mask(REG_PMU_CLK_SEL, 0x200000, 0x300000); + fh_pmu_write_mask(REG_PMU_CLK_SEL, 0x200000, 0x300000); //sd0_sample_sel - fh_pmu_write_mask(REG_PMU_CLK_SEL, 0x00000, 0x30000); + fh_pmu_write_mask(REG_PMU_CLK_SEL, 0x00000, 0x30000); - //sd1_drv_sel - fh_pmu_write_mask(REG_PMU_CLK_SEL, 0x2000, 0x3000); - //sd1_sample_sel - fh_pmu_write_mask(REG_PMU_CLK_SEL, 0x000, 0x300); + //sd1_drv_sel + fh_pmu_write_mask(REG_PMU_CLK_SEL, 0x2000, 0x3000); + //sd1_sample_sel + fh_pmu_write_mask(REG_PMU_CLK_SEL, 0x000, 0x300); } void fh_platform_info_register(void){ - struct fh_board_info *test_info; - int i; - - for(i=0;iname,platform_info[i]->private_data); - if(!test_info){ - rt_kprintf("info_name(%s) failed registered\n", platform_info[i]->name); - } - } + struct fh_board_info *test_info; + int i; + + for(i=0;iname,platform_info[i]->private_data); + if(!test_info){ + rt_kprintf("info_name(%s) failed registered\n", platform_info[i]->name); + } + } } void rt_hw_board_init() { - /* initialize the system clock */ - rt_hw_clock_init(); - //add iomux init 2015-3-11 by yu.zhang for fh81(fullhan) - //iomux_init(); + /* initialize the system clock */ + rt_hw_clock_init(); + //add iomux init 2015-3-11 by yu.zhang for fh81(fullhan) + //iomux_init(); fh_iomux_init(PMU_REG_BASE + 0x5c); - //add clk init 2015-3-11 by yu.zhang for fh81(fullhan) - clock_init(); - /* initialize uart */ - rt_hw_uart_init(); - rt_console_set_device(RT_CONSOLE_DEVICE_NAME); - /* initialize timer1 */ - rt_hw_timer_init(); - //board data info init... - fh_board_info_init(); - fh_platform_info_register(); + //add clk init 2015-3-11 by yu.zhang for fh81(fullhan) + clock_init(); + /* initialize uart */ + rt_hw_uart_init(); + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); + /* initialize timer1 */ + rt_hw_timer_init(); + //board data info init... + fh_board_info_init(); + fh_platform_info_register(); } void rt_board_driver_init(){ - //add board init lock here... - /*rt_show_version();*/ - int ret; + //add board init lock here... + /*rt_show_version();*/ + int ret; /* Filesystem Initialization */ #ifdef RT_USING_DFS - { - /* init the device filesystem */ - dfs_init(); - rt_kprintf("DFS initialized!\n"); + { + /* init the device filesystem */ + dfs_init(); + rt_kprintf("DFS initialized!\n"); #if defined(RT_USING_DFS_ELMFAT) - /* init the elm chan FatFs filesystam*/ - elm_init(); - rt_kprintf("ELM initialized!\n"); + /* init the elm chan FatFs filesystam*/ + elm_init(); + rt_kprintf("ELM initialized!\n"); #endif #if defined(RT_USING_DFS_ROMFS) - dfs_romfs_init(); - if (dfs_mount(RT_NULL, "/rom", "rom", 0, &romfs_root) == 0) - { - rt_kprintf("ROM File System initialized!\n"); - } - else - rt_kprintf("ROM File System initialzation failed!\n"); + dfs_romfs_init(); + if (dfs_mount(RT_NULL, "/rom", "rom", 0, &romfs_root) == 0) + { + rt_kprintf("ROM File System initialized!\n"); + } + else + rt_kprintf("ROM File System initialzation failed!\n"); #endif #if defined(RT_USING_DFS_DEVFS) - devfs_init(); - if (dfs_mount(RT_NULL, "/dev", "devfs", 0, 0) == 0) - rt_kprintf("Device File System initialized!\n"); - else - rt_kprintf("Device File System initialzation failed!\n"); + devfs_init(); + if (dfs_mount(RT_NULL, "/dev", "devfs", 0, 0) == 0) + rt_kprintf("Device File System initialized!\n"); + else + rt_kprintf("Device File System initialzation failed!\n"); - #ifdef RT_USING_NEWLIB - /* init libc */ - libc_system_init(RT_CONSOLE_DEVICE_NAME); - #endif + #ifdef RT_USING_NEWLIB + /* init libc */ + libc_system_init(RT_CONSOLE_DEVICE_NAME); + #endif #endif #if defined(RT_USING_DFS_UFFS) - { - /* init the uffs filesystem */ - dfs_uffs_init(); + { + /* init the uffs filesystem */ + dfs_uffs_init(); - /* mount flash device as flash directory */ - if(dfs_mount("nand0", "/nand0", "uffs", 0, 0) == 0) - rt_kprintf("UFFS File System initialized!\n"); - else - rt_kprintf("UFFS File System initialzation failed!\n"); - } + /* mount flash device as flash directory */ + if(dfs_mount("nand0", "/nand0", "uffs", 0, 0) == 0) + rt_kprintf("UFFS File System initialized!\n"); + else + rt_kprintf("UFFS File System initialzation failed!\n"); + } #endif #ifdef RT_USING_DFS_RAMFS - dfs_ramfs_init(); - { - rt_uint8_t *ramfs_pool = RT_NULL; - struct dfs_ramfs* ramfs; - ramfs_pool = rt_malloc(0x800000); - if(ramfs_pool) - { - ramfs =(struct dfs_ramfs*) dfs_ramfs_create((rt_uint8_t*)ramfs_pool, 0x800000); - if (ramfs != RT_NULL) - { - if (dfs_mount(RT_NULL, "/", "ram", 0, ramfs) == 0) - { - rt_kprintf("Mount RAMDisk done!\n"); - } - else - { - rt_kprintf("Mount RAMDisk failed.\n"); - } - } - } - else - { - rt_kprintf("alloc ramfs poll failed\n"); - } - } -#endif - } + dfs_ramfs_init(); + { + rt_uint8_t *ramfs_pool = RT_NULL; + struct dfs_ramfs* ramfs; + ramfs_pool = rt_malloc(0x800000); + if(ramfs_pool) + { + ramfs =(struct dfs_ramfs*) dfs_ramfs_create((rt_uint8_t*)ramfs_pool, 0x800000); + if (ramfs != RT_NULL) + { + if (dfs_mount(RT_NULL, "/", "ram", 0, ramfs) == 0) + { + rt_kprintf("Mount RAMDisk done!\n"); + } + else + { + rt_kprintf("Mount RAMDisk failed.\n"); + } + } + } + else + { + rt_kprintf("alloc ramfs poll failed\n"); + } + } +#endif + } #endif /* Filesystem Initialization end*/ #ifdef RT_USING_GPIO { rt_hw_gpio_init(); - rt_kprintf("GPIO initialized!\n"); + rt_kprintf("GPIO initialized!\n"); #ifdef RT_USING_SDIO //wifi @@ -572,7 +572,7 @@ void rt_board_driver_init(){ //micro sd gpio_request(HW_SDCARD_POWER_GPIO); gpio_direction_output(HW_SDCARD_POWER_GPIO, 0); - rt_kprintf("SDIO initialized!\n"); + rt_kprintf("SDIO initialized!\n"); #endif //sensor gpio_request(HW_CIS_RST_GPIO); @@ -585,7 +585,7 @@ void rt_board_driver_init(){ #ifdef RT_USING_SDIO #ifndef RT_USING_WIFI_MARVEL rt_hw_mmc_init(); - rt_kprintf("MMC initialized!\n"); + rt_kprintf("MMC initialized!\n"); rt_thread_delay(RT_TICK_PER_SECOND*2); /* mount sd card fat partition 1 as root directory */ #ifdef RT_USING_DFS_ELMFAT @@ -601,56 +601,56 @@ void rt_board_driver_init(){ #ifdef RT_USING_FH_DMA - { + { rt_fh_dma_init(); - rt_kprintf("DMA initialized!\n"); - } + rt_kprintf("DMA initialized!\n"); + } #endif #ifdef RT_USING_FH_ACW - { - fh_audio_init(); - rt_kprintf("AUDIO initialized!\n"); - } + { + fh_audio_init(); + rt_kprintf("AUDIO initialized!\n"); + } #endif #ifdef RT_USING_LWIP - { - /* init lwip system */ - lwip_sys_init(); - rt_kprintf("LWIP SYS initialized!\n"); - eth_system_device_init(); - rt_kprintf("ETH initialized!\n"); - } + { + /* init lwip system */ + lwip_sys_init(); + rt_kprintf("LWIP SYS initialized!\n"); + eth_system_device_init(); + rt_kprintf("ETH initialized!\n"); + } #endif #ifdef RT_USING_GMAC /* register ethernetif device */ rt_app_fh_gmac_init(); - rt_kprintf("GMAC initialized!\n"); + rt_kprintf("GMAC initialized!\n"); #endif #ifdef RT_USING_I2C - { - rt_hw_i2c_init(); - rt_kprintf("I2C initialized!\n"); - } + { + rt_hw_i2c_init(); + rt_kprintf("I2C initialized!\n"); + } #endif #ifdef RT_USING_PWM { rt_hw_pwm_init(); - rt_kprintf("PWM initialized!\n"); + rt_kprintf("PWM initialized!\n"); } #endif #ifdef RT_USING_WDT { rt_hw_wdt_init(); - rt_kprintf("WDT initialized!\n"); + rt_kprintf("WDT initialized!\n"); } #endif @@ -658,7 +658,7 @@ void rt_board_driver_init(){ #ifdef RT_USING_SPI { rt_hw_spi_init(); - rt_kprintf("SPI initialized!\n"); + rt_kprintf("SPI initialized!\n"); } #endif @@ -668,21 +668,21 @@ void rt_board_driver_init(){ rt_kprintf("FLASH initialized!\n"); #endif - rt_kprintf("init done\n"); + rt_kprintf("init done\n"); #ifdef RT_USING_SADC rt_hw_sadc_init(); - rt_kprintf("SADC initialized!\n"); + rt_kprintf("SADC initialized!\n"); #endif #ifdef RT_USING_ENC28J60 - gpio_request(ENC28J60_INT); - gpio_direction_input(ENC28J60_INT); - gpio_set_irq_type(ENC28J60_INT, IRQ_TYPE_EDGE_FALLING); - rt_hw_interrupt_install(gpio_to_irq(ENC28J60_INT), (void *)enc28j60_isr, RT_NULL, RT_NULL); - gpio_irq_enable(gpio_to_irq(ENC28J60_INT)); - gpio_release(ENC28J60_INT); - - enc28j60_attach(ENC28J60_SPI_DEV); + gpio_request(ENC28J60_INT); + gpio_direction_input(ENC28J60_INT); + gpio_set_irq_type(ENC28J60_INT, IRQ_TYPE_EDGE_FALLING); + rt_hw_interrupt_install(gpio_to_irq(ENC28J60_INT), (void *)enc28j60_isr, RT_NULL, RT_NULL); + gpio_irq_enable(gpio_to_irq(ENC28J60_INT)); + gpio_release(ENC28J60_INT); + + enc28j60_attach(ENC28J60_SPI_DEV); #endif } diff --git a/bsp/fh8620/platform/fh8620/iot_cam/board_def.h b/bsp/fh8620/platform/fh8620/iot_cam/board_def.h index 48551b709..902375f42 100644 --- a/bsp/fh8620/platform/fh8620/iot_cam/board_def.h +++ b/bsp/fh8620/platform/fh8620/iot_cam/board_def.h @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,18 +18,18 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + #ifndef BOARD_DEF_H_ #define BOARD_DEF_H_ /* *********************** - * SECTION: DRIVE + * SECTION: DRIVE * ***********************/ // Basic drive.. #define RT_USING_UART1 @@ -49,22 +49,22 @@ #define CONFIG_PLAT_V2 #ifndef FH_DDR_START -#define FH_DDR_START 0xA0000000 -#define FH_DDR_END 0xA1000000 +#define FH_DDR_START 0xA0000000 +#define FH_DDR_END 0xA1000000 -#define FH_RTT_OS_MEM_SIZE 0x00600000 -#define FH_DMA_MEM_SIZE 0x20000 /* 128k */ +#define FH_RTT_OS_MEM_SIZE 0x00600000 +#define FH_DMA_MEM_SIZE 0x20000 /* 128k */ -#define FH_RTT_OS_MEM_END (FH_DDR_START + FH_RTT_OS_MEM_SIZE) -#define FH_SDK_MEM_START (FH_RTT_OS_MEM_END + FH_DMA_MEM_SIZE) -#define FH_RTT_OS_HEAP_END FH_SDK_MEM_START -#define FH_SDK_MEM_SIZE (FH_DDR_END - FH_SDK_MEM_START) +#define FH_RTT_OS_MEM_END (FH_DDR_START + FH_RTT_OS_MEM_SIZE) +#define FH_SDK_MEM_START (FH_RTT_OS_MEM_END + FH_DMA_MEM_SIZE) +#define FH_RTT_OS_HEAP_END FH_SDK_MEM_START +#define FH_SDK_MEM_SIZE (FH_DDR_END - FH_SDK_MEM_START) #endif /* end of FH_DDR_START*/ - + /* *********************** - * SECTION: DRIVE COMPONENT + * SECTION: DRIVE COMPONENT * ***********************/ -#define UART_NAME "uart1" +#define UART_NAME "uart1" #define RT_USING_DMA_MEM #define RT_USING_MCI0 diff --git a/bsp/fh8620/platform/fh8620/iot_cam/iomux.c b/bsp/fh8620/platform/fh8620/iot_cam/iomux.c index ee0bb6326..dc699c445 100644 --- a/bsp/fh8620/platform/fh8620/iot_cam/iomux.c +++ b/bsp/fh8620/platform/fh8620/iot_cam/iomux.c @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,650 +18,650 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + #include "rtdef.h" #include "iomux.h" #include "rtconfig.h" Iomux_Pad fh_iomux_cfg[] = { - { - .func_name = { "RESETN", "", "", "", }, - .reg_type = 9, - .func_sel = 0, - .pupd = IOMUX_PUPD_UP, - .drv_cur = -1, - }, - { - .func_name = { "TEST", "", "", "", }, - .reg_type = 9, - .func_sel = 0, - .pupd = IOMUX_PUPD_DOWN, - .drv_cur = -1, - }, - { - .func_name = { "CIS_CLK", "", "", "", }, - .reg_type = 5, - .func_sel = 0, - .pupd = IOMUX_PUPD_NONE, - .drv_cur = 1, - }, - { - .func_name = { "CIS_HSYNC", "GPIO20", "", "", }, - .reg_type = 20, - .func_sel = 0, - .pupd = IOMUX_PUPD_DOWN, - .drv_cur = 1, - }, - { - .func_name = { "CIS_VSYNC", "GPIO21", "", "", }, - .reg_type = 20, - .func_sel = 0, - .pupd = IOMUX_PUPD_DOWN, - .drv_cur = 1, - }, - { - .func_name = { "CIS_PCLK", "", "", "", }, - .reg_type = 9, - .func_sel = 0, - .pupd = IOMUX_PUPD_DOWN, - .drv_cur = 0, - }, - { - .func_name = { "CIS_D0", "GPIO22", "", "", }, - .reg_type = 20, - .func_sel = 0, - .pupd = IOMUX_PUPD_DOWN, - .drv_cur = 1, - }, - { - .func_name = { "CIS_D1", "GPIO23", "", "", }, - .reg_type = 20, - .func_sel = 0, - .pupd = IOMUX_PUPD_DOWN, - .drv_cur = 1, - }, - { - .func_name = { "CIS_D2", "GPIO24", "", "", }, - .reg_type = 20, - .func_sel = 0, - .pupd = IOMUX_PUPD_DOWN, - .drv_cur = 1, - }, - { - .func_name = { "CIS_D3", "GPIO25", "", "", }, - .reg_type = 20, - .func_sel = 0, - .pupd = IOMUX_PUPD_DOWN, - .drv_cur = 1, - }, - { - .func_name = { "CIS_D4", "GPIO26", "", "", }, - .reg_type = 20, - .func_sel = 0, - .pupd = IOMUX_PUPD_DOWN, - .drv_cur = 1, - }, - { - .func_name = { "CIS_D5", "GPIO27", "", "", }, - .reg_type = 20, - .func_sel = 0, - .pupd = IOMUX_PUPD_DOWN, - .drv_cur = 1, - }, - { - .func_name = { "CIS_D6", "GPIO28", "", "", }, - .reg_type = 20, - .func_sel = 0, - .pupd = IOMUX_PUPD_DOWN, - .drv_cur = 1, - }, - { - .func_name = { "CIS_D7", "GPIO29", "", "", }, - .reg_type = 20, - .func_sel = 0, - .pupd = IOMUX_PUPD_DOWN, - .drv_cur = 1, - }, - { - .func_name = { "CIS_D8", "GPIO30", "", "", }, - .reg_type = 20, - .func_sel = 0, - .pupd = IOMUX_PUPD_DOWN, - .drv_cur = 1, - }, - { - .func_name = { "CIS_D9", "GPIO31", "", "", }, - .reg_type = 20, - .func_sel = 0, - .pupd = IOMUX_PUPD_DOWN, - .drv_cur = 1, - }, - { - .func_name = { "CIS_D10", "GPIO32", "", "", }, - .reg_type = 20, - .func_sel = 0, - .pupd = IOMUX_PUPD_DOWN, - .drv_cur = 1, - }, - { - .func_name = { "CIS_D11", "GPIO33", "", "", }, - .reg_type = 20, - .func_sel = 0, - .pupd = IOMUX_PUPD_DOWN, - .drv_cur = 1, - }, - { - .func_name = { "MAC_REF_CLK", "", "", "", }, - .reg_type = 17, - .func_sel = 0, - .pupd = IOMUX_PUPD_NONE, - .drv_cur = 3, - }, - { - .func_name = { "MAC_MDC", "GPIO34", "", "", }, - .reg_type = 20, - .func_sel = 1, - .pupd = IOMUX_PUPD_NONE, - .drv_cur = 0, - }, - { - .func_name = { "MAC_MDIO", "", "", "", }, - .reg_type = 17, - .func_sel = 0, - .pupd = IOMUX_PUPD_DOWN, - .drv_cur = 1, - }, - { - .func_name = { "MAC_COL", "GPIO35", "", "", }, - .reg_type = 20, - .func_sel = 1, - .pupd = IOMUX_PUPD_DOWN, - .drv_cur = 1, - }, - { - .func_name = { "MAC_CRS", "GPIO36", "", "", }, - .reg_type = 20, - .func_sel = 1, - .pupd = IOMUX_PUPD_DOWN, - .drv_cur = 1, - }, - { - .func_name = { "MAC_RXCK", "", "", "", }, - .reg_type = 9, - .func_sel = 0, - .pupd = IOMUX_PUPD_DOWN, - .drv_cur = -1, - }, - { - .func_name = { "MAC_RXD0", "", "", "", }, - .reg_type = 17, - .func_sel = 0, - .pupd = IOMUX_PUPD_DOWN, - .drv_cur = -1, - }, + { + .func_name = { "RESETN", "", "", "", }, + .reg_type = 9, + .func_sel = 0, + .pupd = IOMUX_PUPD_UP, + .drv_cur = -1, + }, + { + .func_name = { "TEST", "", "", "", }, + .reg_type = 9, + .func_sel = 0, + .pupd = IOMUX_PUPD_DOWN, + .drv_cur = -1, + }, + { + .func_name = { "CIS_CLK", "", "", "", }, + .reg_type = 5, + .func_sel = 0, + .pupd = IOMUX_PUPD_NONE, + .drv_cur = 1, + }, + { + .func_name = { "CIS_HSYNC", "GPIO20", "", "", }, + .reg_type = 20, + .func_sel = 0, + .pupd = IOMUX_PUPD_DOWN, + .drv_cur = 1, + }, + { + .func_name = { "CIS_VSYNC", "GPIO21", "", "", }, + .reg_type = 20, + .func_sel = 0, + .pupd = IOMUX_PUPD_DOWN, + .drv_cur = 1, + }, + { + .func_name = { "CIS_PCLK", "", "", "", }, + .reg_type = 9, + .func_sel = 0, + .pupd = IOMUX_PUPD_DOWN, + .drv_cur = 0, + }, + { + .func_name = { "CIS_D0", "GPIO22", "", "", }, + .reg_type = 20, + .func_sel = 0, + .pupd = IOMUX_PUPD_DOWN, + .drv_cur = 1, + }, + { + .func_name = { "CIS_D1", "GPIO23", "", "", }, + .reg_type = 20, + .func_sel = 0, + .pupd = IOMUX_PUPD_DOWN, + .drv_cur = 1, + }, + { + .func_name = { "CIS_D2", "GPIO24", "", "", }, + .reg_type = 20, + .func_sel = 0, + .pupd = IOMUX_PUPD_DOWN, + .drv_cur = 1, + }, + { + .func_name = { "CIS_D3", "GPIO25", "", "", }, + .reg_type = 20, + .func_sel = 0, + .pupd = IOMUX_PUPD_DOWN, + .drv_cur = 1, + }, + { + .func_name = { "CIS_D4", "GPIO26", "", "", }, + .reg_type = 20, + .func_sel = 0, + .pupd = IOMUX_PUPD_DOWN, + .drv_cur = 1, + }, + { + .func_name = { "CIS_D5", "GPIO27", "", "", }, + .reg_type = 20, + .func_sel = 0, + .pupd = IOMUX_PUPD_DOWN, + .drv_cur = 1, + }, + { + .func_name = { "CIS_D6", "GPIO28", "", "", }, + .reg_type = 20, + .func_sel = 0, + .pupd = IOMUX_PUPD_DOWN, + .drv_cur = 1, + }, + { + .func_name = { "CIS_D7", "GPIO29", "", "", }, + .reg_type = 20, + .func_sel = 0, + .pupd = IOMUX_PUPD_DOWN, + .drv_cur = 1, + }, + { + .func_name = { "CIS_D8", "GPIO30", "", "", }, + .reg_type = 20, + .func_sel = 0, + .pupd = IOMUX_PUPD_DOWN, + .drv_cur = 1, + }, + { + .func_name = { "CIS_D9", "GPIO31", "", "", }, + .reg_type = 20, + .func_sel = 0, + .pupd = IOMUX_PUPD_DOWN, + .drv_cur = 1, + }, + { + .func_name = { "CIS_D10", "GPIO32", "", "", }, + .reg_type = 20, + .func_sel = 0, + .pupd = IOMUX_PUPD_DOWN, + .drv_cur = 1, + }, + { + .func_name = { "CIS_D11", "GPIO33", "", "", }, + .reg_type = 20, + .func_sel = 0, + .pupd = IOMUX_PUPD_DOWN, + .drv_cur = 1, + }, + { + .func_name = { "MAC_REF_CLK", "", "", "", }, + .reg_type = 17, + .func_sel = 0, + .pupd = IOMUX_PUPD_NONE, + .drv_cur = 3, + }, + { + .func_name = { "MAC_MDC", "GPIO34", "", "", }, + .reg_type = 20, + .func_sel = 1, + .pupd = IOMUX_PUPD_NONE, + .drv_cur = 0, + }, + { + .func_name = { "MAC_MDIO", "", "", "", }, + .reg_type = 17, + .func_sel = 0, + .pupd = IOMUX_PUPD_DOWN, + .drv_cur = 1, + }, + { + .func_name = { "MAC_COL", "GPIO35", "", "", }, + .reg_type = 20, + .func_sel = 1, + .pupd = IOMUX_PUPD_DOWN, + .drv_cur = 1, + }, + { + .func_name = { "MAC_CRS", "GPIO36", "", "", }, + .reg_type = 20, + .func_sel = 1, + .pupd = IOMUX_PUPD_DOWN, + .drv_cur = 1, + }, + { + .func_name = { "MAC_RXCK", "", "", "", }, + .reg_type = 9, + .func_sel = 0, + .pupd = IOMUX_PUPD_DOWN, + .drv_cur = -1, + }, + { + .func_name = { "MAC_RXD0", "", "", "", }, + .reg_type = 17, + .func_sel = 0, + .pupd = IOMUX_PUPD_DOWN, + .drv_cur = -1, + }, - { - .func_name = { "MAC_RXD1", "GPIO38", "", "", }, - .reg_type = 20, - .func_sel = 1, - .pupd = IOMUX_PUPD_DOWN, - .drv_cur = 1, - }, - { - .func_name = { "MAC_RXD2", "GPIO39", "", "", }, - .reg_type = 20, - .func_sel = 1, - .pupd = IOMUX_PUPD_DOWN, - .drv_cur = 1, - }, - { - .func_name = { "MAC_RXD3", "GPIO40", "", "", }, - .reg_type = 20, - .func_sel = 1, - .pupd = IOMUX_PUPD_DOWN, - .drv_cur = 1, - }, - { - .func_name = { "MAC_RXDV", "GPIO41", "", "", }, - .reg_type = 20, - .func_sel = 1, - .pupd = IOMUX_PUPD_DOWN, - .drv_cur = 1, - }, - { - .func_name = { "MAC_TXCK", "", "", "", }, - .reg_type = 9, - .func_sel = 0, - .pupd = IOMUX_PUPD_DOWN, - .drv_cur = -1, - }, - { - .func_name = { "MAC_TXD0", "GPIO42", "", "", }, - .reg_type = 20, - .func_sel = 1, - .pupd = IOMUX_PUPD_DOWN, - .drv_cur = 1, - }, - { - .func_name = { "MAC_TXD1", "GPIO43", "", "", }, - .reg_type = 20, - .func_sel = 1, - .pupd = IOMUX_PUPD_DOWN, - .drv_cur = 1, - }, - { - .func_name = { "MAC_TXD2", "GPIO44", "", "", }, - .reg_type = 20, - .func_sel = 1, - .pupd = IOMUX_PUPD_DOWN, - .drv_cur = 1, - }, - { - .func_name = { "MAC_TXD3", "GPIO45", "", "", }, - .reg_type = 20, - .func_sel = 1, - .pupd = IOMUX_PUPD_DOWN, - .drv_cur = 1, - }, - { - .func_name = { "MAC_TXEN", "GPIO46", "", "", }, - .reg_type = 20, - .func_sel = 1, - .pupd = IOMUX_PUPD_DOWN, - .drv_cur = 1, - }, - { - .func_name = { "MAC_RXER", "GPIO47", "", "", }, - .reg_type = 20, - .func_sel = 1, - .pupd = IOMUX_PUPD_DOWN, - .drv_cur = 1, - }, - { - .func_name = { "GPIO0", "ARC_JTAG_TCK", "GPIO0", "CIS_SSI0_CSN1", }, - .reg_type = 21, - .func_sel = 0, - .pupd = IOMUX_PUPD_NONE, - .drv_cur = 1, - }, - { - .func_name = { "GPIO1", "ARC_JTAG_TRSTN", "GPIO1", "CIS_SSI0_RXD", }, - .reg_type = 21, - .func_sel = 0, - .pupd = IOMUX_PUPD_NONE, - .drv_cur = 1, - }, - { - .func_name = { "GPIO2", "ARC_JTAG_TMS", "", "", }, - .reg_type = 20, - .func_sel = 0, - .pupd = IOMUX_PUPD_NONE, - .drv_cur = 1, - }, - { - .func_name = { "GPIO3", "ARC_JTAG_TDI", "", "", }, - .reg_type = 20, - .func_sel = 0, - .pupd = IOMUX_PUPD_NONE, - .drv_cur = 1, - }, - { - .func_name = { "GPIO4", "ARC_JTAG_TDO", "", "", }, - .reg_type = 20, - .func_sel = 0, - .pupd = IOMUX_PUPD_NONE, - .drv_cur = 1, - }, - { - .func_name = { "JTAG_TCK", "GPIO5", "", "", }, - .reg_type = 20, - .func_sel = 1, - .pupd = IOMUX_PUPD_NONE, - .drv_cur = 1, - }, - { - .func_name = { "JTAG_TRSTN", "GPIO6", "", "", }, - .reg_type = 20, - .func_sel = 1, - .pupd = IOMUX_PUPD_NONE, - .drv_cur = 1, - }, - { - .func_name = { "JTAG_TMS", "GPIO7", "", "", }, - .reg_type = 20, - .func_sel = 1, - .pupd = IOMUX_PUPD_DOWN, - .drv_cur = 1, - }, - { - .func_name = { "JTAG_TDI", "GPIO8", "", "", }, - .reg_type = 20, - .func_sel = 1, - .pupd = IOMUX_PUPD_NONE, - .drv_cur = 1, - }, - { - .func_name = { "JTAG_TDO", "GPIO9", "", "", }, - .reg_type = 20, - .func_sel = 1, - .pupd = IOMUX_PUPD_NONE, - .drv_cur = 1, - }, - { - .func_name = { "GPIO10", "UART1_OUT", "", "", }, - .reg_type = 20, - .func_sel = 1, - .pupd = IOMUX_PUPD_UP, - .drv_cur = 1, - }, - { - .func_name = { "GPIO11", "UART1_IN", "", "", }, - .reg_type = 20, - .func_sel = 1, - .pupd = IOMUX_PUPD_UP, - .drv_cur = 1, - }, - { - .func_name = { "GPIO12", "PWM_OUT0", "", "", }, - .reg_type = 20, - .func_sel = 1, - .pupd = IOMUX_PUPD_NONE, - .drv_cur = 1, - }, - { - .func_name = { "GPIO13", "PWM_OUT1", "", "", }, - .reg_type = 20, - .func_sel = 0, - .pupd = IOMUX_PUPD_NONE, - .drv_cur = 1, - }, - { - .func_name = { "GPIO14", "PWM_OUT2", "", "", }, - .reg_type = 20, - .func_sel = 0, - .pupd = IOMUX_PUPD_NONE, - .drv_cur = 1, - }, - { - .func_name = { "RESERVED", "", "", "", }, - .reg_type = 20, - .func_sel = 0, - }, - { - .func_name = { "RESERVED", "", "", "", }, - .reg_type = 20, - .func_sel = 0, - }, - { - .func_name = { "RESERVED", "", "", "", }, - .reg_type = 20, - .func_sel = 0, - }, - { - .func_name = { "RESERVED", "", "", "", }, - .reg_type = 20, - .func_sel = 0, - }, - { - .func_name = { "RESERVED", "", "", "", }, - .reg_type = 20, - .func_sel = 0, - }, - { - .func_name = { "UART0_IN", "GPIO48", "UART0_IN", " I2S_WS", }, - .reg_type = 21, - .func_sel = 0, - .pupd = IOMUX_PUPD_UP, - .drv_cur = 1, - }, - { - .func_name = { "UART0_OUT", "GPIO49", "UART0_OUT", "I2S_CLK", }, - .reg_type = 20, - .func_sel = 0, - .pupd = IOMUX_PUPD_DOWN, - .drv_cur = 1, - }, - { - .func_name = { "CIS_SCL", "GPIO56", "CIS_SCL", "CIS_SSI0_CLK", }, - .reg_type = 13, - .func_sel = 0, - .pupd = IOMUX_PUPD_NONE, - .drv_cur = 1, - }, - { - .func_name = { "CIS_SDA", "GPIO57", "CIS_SDA", "CIS_SSI0_TXD", }, - .reg_type = 13, - .func_sel = 0, - .pupd = IOMUX_PUPD_NONE, - .drv_cur = 1, - }, - { - .func_name = { "SCL1", "GPIO50", "SCL1", "I2S_DI", }, - .reg_type = 21, - .func_sel = 1, - .pupd = IOMUX_PUPD_NONE, - .drv_cur = 1, - }, - { - .func_name = { "SDA1", "GPIO51", "I2S_DO", "", }, - .reg_type = 21, - .func_sel = 1, - .pupd = IOMUX_PUPD_NONE, - .drv_cur = 1, - }, - { - .func_name = { "SSI0_CLK", "", "", "", }, - .reg_type = 5, - .func_sel = 0, - .pupd = IOMUX_PUPD_NONE, - .drv_cur = 1, - }, - { - .func_name = { "SSI0_TXD", "", "", "", }, - .reg_type = 5, - .func_sel = 0, - .pupd = IOMUX_PUPD_NONE, - .drv_cur = 1, - }, - { - .func_name = { "SSI0_CSN0", "GPIO54", "", "", }, - .reg_type = 20, - .func_sel = 1, - .pupd = IOMUX_PUPD_DOWN, - .drv_cur = 1, - }, - { - .func_name = { "SSI0_CSN1", "GPIO55", "", "", }, - .reg_type = 20, - .func_sel = 1, - .pupd = IOMUX_PUPD_DOWN, - .drv_cur = 1, - }, - { - .func_name = { "SSI0_RXD", "", "", "", }, - .reg_type = 17, - .func_sel = 0, - .pupd = IOMUX_PUPD_DOWN, - .drv_cur = -1, - }, - { - .func_name = { "SD0_CD", "GPIO52", "", "", }, - .reg_type = 20, - .func_sel = 0, - .pupd = IOMUX_PUPD_DOWN, - .drv_cur = 1, - }, - { - .func_name = { "SD0_WP", "GPIO53", "", "", }, - .reg_type = 20, - .func_sel = 0, - .pupd = IOMUX_PUPD_DOWN, - .drv_cur = 1, - }, - { - .func_name = { "SD0_CLK", "", "", "", }, - .reg_type = 5, - .func_sel = 0, - .pupd = IOMUX_PUPD_NONE, - .drv_cur = 3, - }, - { - .func_name = { "SD0_CMD_RSP", "", "", "", }, - .reg_type = 17, - .func_sel = 0, - .pupd = IOMUX_PUPD_UP, - .drv_cur = 3, - }, - { - .func_name = { "SD0_DATA0", "", "", "", }, - .reg_type = 17, - .func_sel = 0, - .pupd = IOMUX_PUPD_UP, - .drv_cur = 3, - }, - { - .func_name = { "SD0_DATA1", "", "", "", }, - .reg_type = 17, - .func_sel = 0, - .pupd = IOMUX_PUPD_UP, - .drv_cur = 2, - }, - { - .func_name = { "SD0_DATA2", "", "", "", }, - .reg_type = 17, - .func_sel = 0, - .pupd = IOMUX_PUPD_UP, - .drv_cur = 3, - }, - { - .func_name = { "SD0_DATA3", "", "", "", }, - .reg_type = 17, - .func_sel = 0, - .pupd = IOMUX_PUPD_UP, - .drv_cur = 3, - }, - { - .func_name = { "SD1_CLK", "SSI1_CLK", "", "", }, - .reg_type = 8, - .func_sel = 0, - .pupd = IOMUX_PUPD_NONE, - .drv_cur = 1, - }, - { - .func_name = { "SD1_CD", "GPIO_58", "", "", }, - .reg_type = 20, - .func_sel = 0, - .pupd = IOMUX_PUPD_DOWN, - .drv_cur = 1, - }, - { - .func_name = { "SD1_WP", "GPIO_59", "", "", }, - .reg_type = 20, - .func_sel = 0, - .pupd = IOMUX_PUPD_DOWN, - .drv_cur = 1, - }, - { - .func_name = { "SD1_DATA0", "SSI1_TXD", "", "", }, - .reg_type = 20, - .func_sel = 0, - .pupd = IOMUX_PUPD_UP, - .drv_cur = 3, - }, - { - .func_name = { "SD1_DATA1", "SSI1_CSN0", "", "", }, - .reg_type = 20, - .func_sel = 0, - .pupd = IOMUX_PUPD_UP, - .drv_cur = 3, - }, - { - .func_name = { "SD1_DATA2", "SSI1_CSN1", "", "", }, - .reg_type = 20, - .func_sel = 0, - .pupd = IOMUX_PUPD_UP, - .drv_cur = 3, - }, - { - .func_name = { "SD1_DATA3", "", "", "", }, - .reg_type = 17, - .func_sel = 0, - .pupd = IOMUX_PUPD_UP, - .drv_cur = 3, - }, - { - .func_name = { "SD1_CMD_RSP", "SSI1_RXD", "", "", }, - .reg_type = 20, - .func_sel = 0, - .pupd = IOMUX_PUPD_UP, - .drv_cur = 3, - }, - { - .func_name = { "RESERVED", "", "", "", }, - .reg_type = 20, - .func_sel = 0, - }, - { - .func_name = { "RESERVED", "", "", "", }, - .reg_type = 20, - .func_sel = 0, - }, - { - .func_name = { "RESERVED", "", "", "", }, - .reg_type = 20, - .func_sel = 0, - }, - { - .func_name = { "RESERVED", "", "", "", }, - .reg_type = 20, - .func_sel = 0, - }, - { - .func_name = { "CLK_SW0", "", "", "", }, - .reg_type = 9, - .func_sel = 0, - .pupd = IOMUX_PUPD_UP, - .drv_cur = -1, - }, - { - .func_name = { "CLK_SW1", "", "", "", }, - .reg_type = 9, - .func_sel = 0, - .pupd = IOMUX_PUPD_UP, - .drv_cur = -1, - }, - { - .func_name = { "CLK_SW2", "", "", "", }, - .reg_type = 9, - .func_sel = 0, - .pupd = IOMUX_PUPD_UP, - .drv_cur = -1, - }, - { - .func_name = { "CLK_SW3", "", "", "", }, - .reg_type = 9, - .func_sel = 0, - .pupd = IOMUX_PUPD_UP, - .drv_cur = -1, - }, - { - .func_name = { "RESERVED", "", "", "", }, - .reg_type = 20, - .func_sel = 0, - }, - { - .func_name = { "MAC_TXER", "GPIO37", "", "", }, - .reg_type = 20, - .func_sel = 1, - .pupd = IOMUX_PUPD_DOWN, - .drv_cur = 1, - }, + { + .func_name = { "MAC_RXD1", "GPIO38", "", "", }, + .reg_type = 20, + .func_sel = 1, + .pupd = IOMUX_PUPD_DOWN, + .drv_cur = 1, + }, + { + .func_name = { "MAC_RXD2", "GPIO39", "", "", }, + .reg_type = 20, + .func_sel = 1, + .pupd = IOMUX_PUPD_DOWN, + .drv_cur = 1, + }, + { + .func_name = { "MAC_RXD3", "GPIO40", "", "", }, + .reg_type = 20, + .func_sel = 1, + .pupd = IOMUX_PUPD_DOWN, + .drv_cur = 1, + }, + { + .func_name = { "MAC_RXDV", "GPIO41", "", "", }, + .reg_type = 20, + .func_sel = 1, + .pupd = IOMUX_PUPD_DOWN, + .drv_cur = 1, + }, + { + .func_name = { "MAC_TXCK", "", "", "", }, + .reg_type = 9, + .func_sel = 0, + .pupd = IOMUX_PUPD_DOWN, + .drv_cur = -1, + }, + { + .func_name = { "MAC_TXD0", "GPIO42", "", "", }, + .reg_type = 20, + .func_sel = 1, + .pupd = IOMUX_PUPD_DOWN, + .drv_cur = 1, + }, + { + .func_name = { "MAC_TXD1", "GPIO43", "", "", }, + .reg_type = 20, + .func_sel = 1, + .pupd = IOMUX_PUPD_DOWN, + .drv_cur = 1, + }, + { + .func_name = { "MAC_TXD2", "GPIO44", "", "", }, + .reg_type = 20, + .func_sel = 1, + .pupd = IOMUX_PUPD_DOWN, + .drv_cur = 1, + }, + { + .func_name = { "MAC_TXD3", "GPIO45", "", "", }, + .reg_type = 20, + .func_sel = 1, + .pupd = IOMUX_PUPD_DOWN, + .drv_cur = 1, + }, + { + .func_name = { "MAC_TXEN", "GPIO46", "", "", }, + .reg_type = 20, + .func_sel = 1, + .pupd = IOMUX_PUPD_DOWN, + .drv_cur = 1, + }, + { + .func_name = { "MAC_RXER", "GPIO47", "", "", }, + .reg_type = 20, + .func_sel = 1, + .pupd = IOMUX_PUPD_DOWN, + .drv_cur = 1, + }, + { + .func_name = { "GPIO0", "ARC_JTAG_TCK", "GPIO0", "CIS_SSI0_CSN1", }, + .reg_type = 21, + .func_sel = 0, + .pupd = IOMUX_PUPD_NONE, + .drv_cur = 1, + }, + { + .func_name = { "GPIO1", "ARC_JTAG_TRSTN", "GPIO1", "CIS_SSI0_RXD", }, + .reg_type = 21, + .func_sel = 0, + .pupd = IOMUX_PUPD_NONE, + .drv_cur = 1, + }, + { + .func_name = { "GPIO2", "ARC_JTAG_TMS", "", "", }, + .reg_type = 20, + .func_sel = 0, + .pupd = IOMUX_PUPD_NONE, + .drv_cur = 1, + }, + { + .func_name = { "GPIO3", "ARC_JTAG_TDI", "", "", }, + .reg_type = 20, + .func_sel = 0, + .pupd = IOMUX_PUPD_NONE, + .drv_cur = 1, + }, + { + .func_name = { "GPIO4", "ARC_JTAG_TDO", "", "", }, + .reg_type = 20, + .func_sel = 0, + .pupd = IOMUX_PUPD_NONE, + .drv_cur = 1, + }, + { + .func_name = { "JTAG_TCK", "GPIO5", "", "", }, + .reg_type = 20, + .func_sel = 1, + .pupd = IOMUX_PUPD_NONE, + .drv_cur = 1, + }, + { + .func_name = { "JTAG_TRSTN", "GPIO6", "", "", }, + .reg_type = 20, + .func_sel = 1, + .pupd = IOMUX_PUPD_NONE, + .drv_cur = 1, + }, + { + .func_name = { "JTAG_TMS", "GPIO7", "", "", }, + .reg_type = 20, + .func_sel = 1, + .pupd = IOMUX_PUPD_DOWN, + .drv_cur = 1, + }, + { + .func_name = { "JTAG_TDI", "GPIO8", "", "", }, + .reg_type = 20, + .func_sel = 1, + .pupd = IOMUX_PUPD_NONE, + .drv_cur = 1, + }, + { + .func_name = { "JTAG_TDO", "GPIO9", "", "", }, + .reg_type = 20, + .func_sel = 1, + .pupd = IOMUX_PUPD_NONE, + .drv_cur = 1, + }, + { + .func_name = { "GPIO10", "UART1_OUT", "", "", }, + .reg_type = 20, + .func_sel = 1, + .pupd = IOMUX_PUPD_UP, + .drv_cur = 1, + }, + { + .func_name = { "GPIO11", "UART1_IN", "", "", }, + .reg_type = 20, + .func_sel = 1, + .pupd = IOMUX_PUPD_UP, + .drv_cur = 1, + }, + { + .func_name = { "GPIO12", "PWM_OUT0", "", "", }, + .reg_type = 20, + .func_sel = 1, + .pupd = IOMUX_PUPD_NONE, + .drv_cur = 1, + }, + { + .func_name = { "GPIO13", "PWM_OUT1", "", "", }, + .reg_type = 20, + .func_sel = 0, + .pupd = IOMUX_PUPD_NONE, + .drv_cur = 1, + }, + { + .func_name = { "GPIO14", "PWM_OUT2", "", "", }, + .reg_type = 20, + .func_sel = 0, + .pupd = IOMUX_PUPD_NONE, + .drv_cur = 1, + }, + { + .func_name = { "RESERVED", "", "", "", }, + .reg_type = 20, + .func_sel = 0, + }, + { + .func_name = { "RESERVED", "", "", "", }, + .reg_type = 20, + .func_sel = 0, + }, + { + .func_name = { "RESERVED", "", "", "", }, + .reg_type = 20, + .func_sel = 0, + }, + { + .func_name = { "RESERVED", "", "", "", }, + .reg_type = 20, + .func_sel = 0, + }, + { + .func_name = { "RESERVED", "", "", "", }, + .reg_type = 20, + .func_sel = 0, + }, + { + .func_name = { "UART0_IN", "GPIO48", "UART0_IN", " I2S_WS", }, + .reg_type = 21, + .func_sel = 0, + .pupd = IOMUX_PUPD_UP, + .drv_cur = 1, + }, + { + .func_name = { "UART0_OUT", "GPIO49", "UART0_OUT", "I2S_CLK", }, + .reg_type = 20, + .func_sel = 0, + .pupd = IOMUX_PUPD_DOWN, + .drv_cur = 1, + }, + { + .func_name = { "CIS_SCL", "GPIO56", "CIS_SCL", "CIS_SSI0_CLK", }, + .reg_type = 13, + .func_sel = 0, + .pupd = IOMUX_PUPD_NONE, + .drv_cur = 1, + }, + { + .func_name = { "CIS_SDA", "GPIO57", "CIS_SDA", "CIS_SSI0_TXD", }, + .reg_type = 13, + .func_sel = 0, + .pupd = IOMUX_PUPD_NONE, + .drv_cur = 1, + }, + { + .func_name = { "SCL1", "GPIO50", "SCL1", "I2S_DI", }, + .reg_type = 21, + .func_sel = 1, + .pupd = IOMUX_PUPD_NONE, + .drv_cur = 1, + }, + { + .func_name = { "SDA1", "GPIO51", "I2S_DO", "", }, + .reg_type = 21, + .func_sel = 1, + .pupd = IOMUX_PUPD_NONE, + .drv_cur = 1, + }, + { + .func_name = { "SSI0_CLK", "", "", "", }, + .reg_type = 5, + .func_sel = 0, + .pupd = IOMUX_PUPD_NONE, + .drv_cur = 1, + }, + { + .func_name = { "SSI0_TXD", "", "", "", }, + .reg_type = 5, + .func_sel = 0, + .pupd = IOMUX_PUPD_NONE, + .drv_cur = 1, + }, + { + .func_name = { "SSI0_CSN0", "GPIO54", "", "", }, + .reg_type = 20, + .func_sel = 1, + .pupd = IOMUX_PUPD_DOWN, + .drv_cur = 1, + }, + { + .func_name = { "SSI0_CSN1", "GPIO55", "", "", }, + .reg_type = 20, + .func_sel = 1, + .pupd = IOMUX_PUPD_DOWN, + .drv_cur = 1, + }, + { + .func_name = { "SSI0_RXD", "", "", "", }, + .reg_type = 17, + .func_sel = 0, + .pupd = IOMUX_PUPD_DOWN, + .drv_cur = -1, + }, + { + .func_name = { "SD0_CD", "GPIO52", "", "", }, + .reg_type = 20, + .func_sel = 0, + .pupd = IOMUX_PUPD_DOWN, + .drv_cur = 1, + }, + { + .func_name = { "SD0_WP", "GPIO53", "", "", }, + .reg_type = 20, + .func_sel = 0, + .pupd = IOMUX_PUPD_DOWN, + .drv_cur = 1, + }, + { + .func_name = { "SD0_CLK", "", "", "", }, + .reg_type = 5, + .func_sel = 0, + .pupd = IOMUX_PUPD_NONE, + .drv_cur = 3, + }, + { + .func_name = { "SD0_CMD_RSP", "", "", "", }, + .reg_type = 17, + .func_sel = 0, + .pupd = IOMUX_PUPD_UP, + .drv_cur = 3, + }, + { + .func_name = { "SD0_DATA0", "", "", "", }, + .reg_type = 17, + .func_sel = 0, + .pupd = IOMUX_PUPD_UP, + .drv_cur = 3, + }, + { + .func_name = { "SD0_DATA1", "", "", "", }, + .reg_type = 17, + .func_sel = 0, + .pupd = IOMUX_PUPD_UP, + .drv_cur = 2, + }, + { + .func_name = { "SD0_DATA2", "", "", "", }, + .reg_type = 17, + .func_sel = 0, + .pupd = IOMUX_PUPD_UP, + .drv_cur = 3, + }, + { + .func_name = { "SD0_DATA3", "", "", "", }, + .reg_type = 17, + .func_sel = 0, + .pupd = IOMUX_PUPD_UP, + .drv_cur = 3, + }, + { + .func_name = { "SD1_CLK", "SSI1_CLK", "", "", }, + .reg_type = 8, + .func_sel = 0, + .pupd = IOMUX_PUPD_NONE, + .drv_cur = 1, + }, + { + .func_name = { "SD1_CD", "GPIO_58", "", "", }, + .reg_type = 20, + .func_sel = 0, + .pupd = IOMUX_PUPD_DOWN, + .drv_cur = 1, + }, + { + .func_name = { "SD1_WP", "GPIO_59", "", "", }, + .reg_type = 20, + .func_sel = 0, + .pupd = IOMUX_PUPD_DOWN, + .drv_cur = 1, + }, + { + .func_name = { "SD1_DATA0", "SSI1_TXD", "", "", }, + .reg_type = 20, + .func_sel = 0, + .pupd = IOMUX_PUPD_UP, + .drv_cur = 3, + }, + { + .func_name = { "SD1_DATA1", "SSI1_CSN0", "", "", }, + .reg_type = 20, + .func_sel = 0, + .pupd = IOMUX_PUPD_UP, + .drv_cur = 3, + }, + { + .func_name = { "SD1_DATA2", "SSI1_CSN1", "", "", }, + .reg_type = 20, + .func_sel = 0, + .pupd = IOMUX_PUPD_UP, + .drv_cur = 3, + }, + { + .func_name = { "SD1_DATA3", "", "", "", }, + .reg_type = 17, + .func_sel = 0, + .pupd = IOMUX_PUPD_UP, + .drv_cur = 3, + }, + { + .func_name = { "SD1_CMD_RSP", "SSI1_RXD", "", "", }, + .reg_type = 20, + .func_sel = 0, + .pupd = IOMUX_PUPD_UP, + .drv_cur = 3, + }, + { + .func_name = { "RESERVED", "", "", "", }, + .reg_type = 20, + .func_sel = 0, + }, + { + .func_name = { "RESERVED", "", "", "", }, + .reg_type = 20, + .func_sel = 0, + }, + { + .func_name = { "RESERVED", "", "", "", }, + .reg_type = 20, + .func_sel = 0, + }, + { + .func_name = { "RESERVED", "", "", "", }, + .reg_type = 20, + .func_sel = 0, + }, + { + .func_name = { "CLK_SW0", "", "", "", }, + .reg_type = 9, + .func_sel = 0, + .pupd = IOMUX_PUPD_UP, + .drv_cur = -1, + }, + { + .func_name = { "CLK_SW1", "", "", "", }, + .reg_type = 9, + .func_sel = 0, + .pupd = IOMUX_PUPD_UP, + .drv_cur = -1, + }, + { + .func_name = { "CLK_SW2", "", "", "", }, + .reg_type = 9, + .func_sel = 0, + .pupd = IOMUX_PUPD_UP, + .drv_cur = -1, + }, + { + .func_name = { "CLK_SW3", "", "", "", }, + .reg_type = 9, + .func_sel = 0, + .pupd = IOMUX_PUPD_UP, + .drv_cur = -1, + }, + { + .func_name = { "RESERVED", "", "", "", }, + .reg_type = 20, + .func_sel = 0, + }, + { + .func_name = { "MAC_TXER", "GPIO37", "", "", }, + .reg_type = 20, + .func_sel = 1, + .pupd = IOMUX_PUPD_DOWN, + .drv_cur = 1, + }, }; diff --git a/bsp/fh8620/platform/fh8620/iot_cam/startup.c b/bsp/fh8620/platform/fh8620/iot_cam/startup.c index ebadf0677..6787dc7f3 100644 --- a/bsp/fh8620/platform/fh8620/iot_cam/startup.c +++ b/bsp/fh8620/platform/fh8620/iot_cam/startup.c @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,12 +18,12 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + #include #include #include @@ -50,13 +50,13 @@ extern void rt_system_heap_init(void*, void*); extern void rt_hw_finsh_init(void); extern void rt_application_init(void); -static struct mem_desc fh_mem_desc[] = +static struct mem_desc fh_mem_desc[] = { - { 0xA0000000, FH_RTT_OS_MEM_END-1, 0xA0000000, SECT_RWX_CB, 0, SECT_MAPPED }, - { FH_RTT_OS_MEM_END, FH_DDR_END-1, FH_RTT_OS_MEM_END, SECT_RWNX_NCNB, 0, SECT_MAPPED }, - { 0xFFFF0000, 0xFFFF1000-1, 0xA0000000, SECT_TO_PAGE, PAGE_ROX_CB, PAGE_MAPPED }, /* isr vector table */ - { 0xE0000000, 0xF1300000-1, 0xE0000000, SECT_RWNX_NCNB, 0, SECT_MAPPED }, /* io table */ - { 0xF4000000, 0xF4100000-1, 0xF4000000, SECT_RWNX_NCNB, 0, SECT_MAPPED }, /* GPIO#1 io table */ + { 0xA0000000, FH_RTT_OS_MEM_END-1, 0xA0000000, SECT_RWX_CB, 0, SECT_MAPPED }, + { FH_RTT_OS_MEM_END, FH_DDR_END-1, FH_RTT_OS_MEM_END, SECT_RWNX_NCNB, 0, SECT_MAPPED }, + { 0xFFFF0000, 0xFFFF1000-1, 0xA0000000, SECT_TO_PAGE, PAGE_ROX_CB, PAGE_MAPPED }, /* isr vector table */ + { 0xE0000000, 0xF1300000-1, 0xE0000000, SECT_RWNX_NCNB, 0, SECT_MAPPED }, /* io table */ + { 0xF4000000, 0xF4100000-1, 0xF4000000, SECT_RWNX_NCNB, 0, SECT_MAPPED }, /* GPIO#1 io table */ }; rt_uint8_t _irq_stack_start[1024]; @@ -72,46 +72,46 @@ extern unsigned char __bss_end; */ void rtthread_startup(void) { - /* disable interrupt first */ - rt_hw_interrupt_disable(); - /* initialize hardware interrupt */ - rt_hw_interrupt_init(); + /* disable interrupt first */ + rt_hw_interrupt_disable(); + /* initialize hardware interrupt */ + rt_hw_interrupt_init(); - /* initialize mmu */ - rt_hw_mmu_init(fh_mem_desc, sizeof(fh_mem_desc)/sizeof(fh_mem_desc[0])); + /* initialize mmu */ + rt_hw_mmu_init(fh_mem_desc, sizeof(fh_mem_desc)/sizeof(fh_mem_desc[0])); - rt_system_heap_init((void*)&__bss_end, (void*)FH_RTT_OS_MEM_END); + rt_system_heap_init((void*)&__bss_end, (void*)FH_RTT_OS_MEM_END); #ifdef RT_USING_DMA_MEM - //just use the last 100KB - fh_dma_mem_init((rt_uint32_t *)FH_RTT_OS_MEM_END, FH_DMA_MEM_SIZE); + //just use the last 100KB + fh_dma_mem_init((rt_uint32_t *)FH_RTT_OS_MEM_END, FH_DMA_MEM_SIZE); #endif - /* initialize board */ - rt_hw_board_init(); + /* initialize board */ + rt_hw_board_init(); - /* show version */ - rt_show_version(); + /* show version */ + rt_show_version(); - /* initialize timer system */ - rt_system_timer_init(); + /* initialize timer system */ + rt_system_timer_init(); - /* initialize scheduler system */ - rt_system_scheduler_init(); + /* initialize scheduler system */ + rt_system_scheduler_init(); - /* initialize application */ - rt_application_init(); + /* initialize application */ + rt_application_init(); - /* initialize system timer thread */ - rt_system_timer_thread_init(); + /* initialize system timer thread */ + rt_system_timer_thread_init(); - /* initialize idle thread */ - rt_thread_idle_init(); + /* initialize idle thread */ + rt_thread_idle_init(); - /* start scheduler */ - rt_system_scheduler_start(); + /* start scheduler */ + rt_system_scheduler_start(); - /* never reach here */ + /* never reach here */ - return ; + return ; } diff --git a/bsp/fh8620/platform/fh_arch.h b/bsp/fh8620/platform/fh_arch.h index 2cbe36718..a8360cda5 100644 --- a/bsp/fh8620/platform/fh_arch.h +++ b/bsp/fh8620/platform/fh_arch.h @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,12 +18,12 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + #ifndef FH_ARCH_H_ #define FH_ARCH_H_ diff --git a/bsp/fh8620/platform/fh_def.h b/bsp/fh8620/platform/fh_def.h index 57bedcb9e..4a97709d5 100644 --- a/bsp/fh8620/platform/fh_def.h +++ b/bsp/fh8620/platform/fh_def.h @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,12 +18,12 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + #ifndef FH_DEF_H_ #define FH_DEF_H_ @@ -32,29 +32,29 @@ #define MIN(a,b) ((a) < (b) ? (a) : (b)) #define MAX(a,b) ((a) > (b) ? (a) : (b)) -typedef char SINT8; -typedef short SINT16; -typedef int SINT32; -typedef long long SINT64; -typedef unsigned char UINT8; -typedef unsigned short UINT16; -typedef unsigned int UINT32; -typedef unsigned long long UINT64; +typedef char SINT8; +typedef short SINT16; +typedef int SINT32; +typedef long long SINT64; +typedef unsigned char UINT8; +typedef unsigned short UINT16; +typedef unsigned int UINT32; +typedef unsigned long long UINT64; #ifndef TYPE_DEFINED -typedef unsigned char uchar; -typedef signed char int8; -typedef unsigned char uint8; -typedef signed short int16; -typedef unsigned short uint16; -typedef signed int int32; -typedef unsigned int uint32; -typedef signed long long int64; -typedef unsigned long long uint64; -typedef float ieee_single; -typedef double ieee_double; - -typedef unsigned long boolean; +typedef unsigned char uchar; +typedef signed char int8; +typedef unsigned char uint8; +typedef signed short int16; +typedef unsigned short uint16; +typedef signed int int32; +typedef unsigned int uint32; +typedef signed long long int64; +typedef unsigned long long uint64; +typedef float ieee_single; +typedef double ieee_double; + +typedef unsigned long boolean; #define TYPE_DEFINED diff --git a/bsp/fh8620/platform/plat-v2/arch.h b/bsp/fh8620/platform/plat-v2/arch.h index bb32d96ea..c8d23c016 100644 --- a/bsp/fh8620/platform/plat-v2/arch.h +++ b/bsp/fh8620/platform/plat-v2/arch.h @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,53 +18,53 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + #ifndef ARCH_H_ #define ARCH_H_ /*****************************/ /* BSP CONTROLLER BASE */ /*****************************/ -#define INTC_REG_BASE (0xE0200000) -#define SDC0_REG_BASE (0xE2000000) -#define SDC1_REG_BASE (0xE2100000) -#define TVE_REG_BASE (0xE8000000) -#define VOU_REG_BASE (0xE8100000) -#define AES_REG_BASE (0xE8200000) +#define INTC_REG_BASE (0xE0200000) +#define SDC0_REG_BASE (0xE2000000) +#define SDC1_REG_BASE (0xE2100000) +#define TVE_REG_BASE (0xE8000000) +#define VOU_REG_BASE (0xE8100000) +#define AES_REG_BASE (0xE8200000) /* -#define JPEG_REG_BASE (0xE8300000) -#define ISPB_REG_BASE (0xEA000000) -#define ISPF_REG_BASE (0xEA100000) -#define VPU_REG_BASE (0xEC000000) -#define VCU_REG_BASE (0xEC100000) -#define DDRC_REG_BASE (0xED000000) +#define JPEG_REG_BASE (0xE8300000) +#define ISPB_REG_BASE (0xEA000000) +#define ISPF_REG_BASE (0xEA100000) +#define VPU_REG_BASE (0xEC000000) +#define VCU_REG_BASE (0xEC100000) +#define DDRC_REG_BASE (0xED000000) */ -#define DMAC_REG_BASE (0xEE000000) -#define GMAC_REG_BASE (0xEF000000) -#define PMU_REG_BASE (0xF0000000) -#define I2C0_REG_BASE (0xF0200000) -#define GPIO0_REG_BASE (0xF0300000) +#define DMAC_REG_BASE (0xEE000000) +#define GMAC_REG_BASE (0xEF000000) +#define PMU_REG_BASE (0xF0000000) +#define I2C0_REG_BASE (0xF0200000) +#define GPIO0_REG_BASE (0xF0300000) #define GPIO1_REG_BASE (0xf4000000) -#define PWM_REG_BASE (0xF0400000) -#define SPI0_REG_BASE (0xF0500000) -#define SPI1_REG_BASE (0xF0600000) -#define UART0_REG_BASE (0xF0700000) -#define UART1_REG_BASE (0xF0800000) -/*#define I2S_REG_BASE (0xF0900000)*/ -#define ACODEC_REG_BASE (0xF0A00000) -#define I2C1_REG_BASE (0xF0B00000) -#define TMR_REG_BASE (0xF0C00000) -#define WDT_REG_BASE (0xF0D00000) +#define PWM_REG_BASE (0xF0400000) +#define SPI0_REG_BASE (0xF0500000) +#define SPI1_REG_BASE (0xF0600000) +#define UART0_REG_BASE (0xF0700000) +#define UART1_REG_BASE (0xF0800000) +/*#define I2S_REG_BASE (0xF0900000)*/ +#define ACODEC_REG_BASE (0xF0A00000) +#define I2C1_REG_BASE (0xF0B00000) +#define TMR_REG_BASE (0xF0C00000) +#define WDT_REG_BASE (0xF0D00000) /* -#define DPHY_REG_BASE (0xF1000000) -#define MIPIC_REG_BASE (0xF1100000) +#define DPHY_REG_BASE (0xF1000000) +#define MIPIC_REG_BASE (0xF1100000) */ -#define SADC_REG_BASE (0xF1200000) +#define SADC_REG_BASE (0xF1200000) typedef enum IRQn { diff --git a/bsp/fh8620/platform/plat-v2/clock.c b/bsp/fh8620/platform/plat-v2/clock.c index 1c82348c7..335b4c3ce 100644 --- a/bsp/fh8620/platform/plat-v2/clock.c +++ b/bsp/fh8620/platform/plat-v2/clock.c @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,12 +18,12 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + #include "clock.h" #include #include "fh_arch.h" @@ -40,8 +40,8 @@ //#define FH_DBG_CLK -#define FH_CLK_DIV_DEFAULT_VALUE 0x55aaaa55 -#define FH_CLK_GATE_DEFAULT_VALUE 0xaa5555aa +#define FH_CLK_DIV_DEFAULT_VALUE 0x55aaaa55 +#define FH_CLK_GATE_DEFAULT_VALUE 0xaa5555aa #define CONFIG_PAE_PTS_CLOCK (1000000) #define TICKS_PER_USEC (CONFIG_PAE_PTS_CLOCK / 1000000) @@ -50,15 +50,15 @@ #define fh_clk_err(p,fmt,args...)\ - rt_kprintf("clk_err: %s->\t"fmt,p->name, ##args) + rt_kprintf("clk_err: %s->\t"fmt,p->name, ##args) #ifdef FH_CLK_DEBUG #define fh_clk_debug(p,fmt,args...)\ - rt_kprintf("%s:\t\t"fmt,p->name, ##args) + rt_kprintf("%s:\t\t"fmt,p->name, ##args) #define fh_clk_debug_no_handle(fmt,args...)\ - rt_kprintf(fmt, ##args) + rt_kprintf(fmt, ##args) #else //#define fh_clk_err(p,fmt,args...) #define fh_clk_debug(p,fmt,args...) @@ -77,48 +77,48 @@ static struct fh_clk_tree fh_clk_tree; -#define FH_TIMER_WRITEL(offset,value) __raw_writel(value,(fh_clk_tree.c_base_addr + offset)) -#define FH_TIMER_READL(offset) __raw_readl((fh_clk_tree.c_base_addr + offset)) +#define FH_TIMER_WRITEL(offset,value) __raw_writel(value,(fh_clk_tree.c_base_addr + offset)) +#define FH_TIMER_READL(offset) __raw_readl((fh_clk_tree.c_base_addr + offset)) enum clk_gate_enum{ -#define CLK_GATE (1) -#define CLK_UNGATE (0) - ISP_ACLK_GATE = (1<<0), - HCLK_GATE = (1<<1), - CPU_FCLK0_GATE = (1<<3), - VCU_CLK_GATE = (1<<4), - VOU_CLK_GATE = (1<<5), - MCLK_GATE = (1<<6), - SPI0_CLK_GATE = (1<<7), - SPI1_CLK_GATE = (1<<8), - SDC0_CLK_GATE = (1<<9), - SDC1_CLK_GATE = (1<<10), - AC_MCLK_GATE = (1<<11), ///// - I2C0_CLK_GATE = (1<<12), - UART0_CLK_GATE = (1<<13), - UART1_CLK_GATE = (1<<14), - //can't change - WDT_CLK_GATE = (1<<15), - - PWM_CLK_GATE = (1<<16), - TMR0_CLK_GATE = (1<<17), - TMR1_CLK_GATE = (1<<18), - PTS_CLK_GATE = (1<<19), - MIPI_DPHY_CLK20M_GATE = (1<<20), - MIPI_P32_CLK_GATE = (1<<21), - PIX_CLK_GATE = (1<<22), //// - CIS_CLK_OUT_GATE = (1<<23), - I2S_SCLK_GATE = (1<<24), ////// - ETH_REF_CLK_GATE = (1<<25), - SADC_CLK_GATE = (1<<26), - I2C1_CLK_GATE = (1<<27), - ETH_RX_CLK_GATE = (1<<28), ///// - ETH_TX_CLK_GATE = (1<<29), ///// - ETH_RMII_CLK_GATE = (1<<30),//// +#define CLK_GATE (1) +#define CLK_UNGATE (0) + ISP_ACLK_GATE = (1<<0), + HCLK_GATE = (1<<1), + CPU_FCLK0_GATE = (1<<3), + VCU_CLK_GATE = (1<<4), + VOU_CLK_GATE = (1<<5), + MCLK_GATE = (1<<6), + SPI0_CLK_GATE = (1<<7), + SPI1_CLK_GATE = (1<<8), + SDC0_CLK_GATE = (1<<9), + SDC1_CLK_GATE = (1<<10), + AC_MCLK_GATE = (1<<11), ///// + I2C0_CLK_GATE = (1<<12), + UART0_CLK_GATE = (1<<13), + UART1_CLK_GATE = (1<<14), + //can't change + WDT_CLK_GATE = (1<<15), + + PWM_CLK_GATE = (1<<16), + TMR0_CLK_GATE = (1<<17), + TMR1_CLK_GATE = (1<<18), + PTS_CLK_GATE = (1<<19), + MIPI_DPHY_CLK20M_GATE = (1<<20), + MIPI_P32_CLK_GATE = (1<<21), + PIX_CLK_GATE = (1<<22), //// + CIS_CLK_OUT_GATE = (1<<23), + I2S_SCLK_GATE = (1<<24), ////// + ETH_REF_CLK_GATE = (1<<25), + SADC_CLK_GATE = (1<<26), + I2C1_CLK_GATE = (1<<27), + ETH_RX_CLK_GATE = (1<<28), ///// + ETH_TX_CLK_GATE = (1<<29), ///// + ETH_RMII_CLK_GATE = (1<<30),//// }; @@ -130,96 +130,96 @@ enum clk_gate_enum{ typedef void (*clk_update)(struct fh_clk* p_clk); //update func... -void clk_in_update(struct fh_clk* p_clk); -void pll1_clk_update(struct fh_clk* p_clk); -void pll0_clk_update(struct fh_clk* p_clk); +void clk_in_update(struct fh_clk* p_clk); +void pll1_clk_update(struct fh_clk* p_clk); +void pll0_clk_update(struct fh_clk* p_clk); void cis_pclk_update(struct fh_clk* p_clk); -void ddr_clk_update(struct fh_clk* p_clk); -void ddr_clk_update(struct fh_clk* p_clk); -void fclk_update(struct fh_clk* p_clk); -void aclk_update(struct fh_clk* p_clk); -void hclk_update(struct fh_clk* p_clk); -void pclk_update(struct fh_clk* p_clk); -void isp_aclk_update(struct fh_clk* p_clk); -void vcu_clk_update(struct fh_clk* p_clk); -void vou_clk_update(struct fh_clk* p_clk); -void mipi_p32_clk_update(struct fh_clk* p_clk); -void cis_clk_out_update(struct fh_clk* p_clk); -void pts_update(struct fh_clk* p_clk); -void mipi_pix_clk_update(struct fh_clk* p_clk); -void spi0_clk_update(struct fh_clk* p_clk); -void spi1_clk_update(struct fh_clk* p_clk); -void mipi_dphy_clk20m_update(struct fh_clk* p_clk); -void i2c0_clk_update(struct fh_clk* p_clk); -void i2c1_clk_update(struct fh_clk* p_clk); -void uart0_clk_update(struct fh_clk* p_clk); -void uart1_clk_update(struct fh_clk* p_clk); -void pwm_clk_update(struct fh_clk* p_clk); -void time0_clk_update(struct fh_clk* p_clk); -void time1_clk_update(struct fh_clk* p_clk); -void sadc_clk_update(struct fh_clk* p_clk); -void sdc0_clk2x_update(struct fh_clk* p_clk); -void sdc0_clk_update(struct fh_clk* p_clk); -void sdc0_clk_out_update(struct fh_clk* p_clk); -void sdc0_clk_sample_update(struct fh_clk* p_clk); -void sdc0_clk_drv_update(struct fh_clk* p_clk); -void sdc1_clk2x_update(struct fh_clk* p_clk); -void sdc1_clk_update(struct fh_clk* p_clk); -void sdc1_clk_out_update(struct fh_clk* p_clkt); -void sdc1_clk_sample_update(struct fh_clk* p_clk); -void sdc1_clk_drv_update(struct fh_clk* p_clk); -void eth_ref_clk_update(struct fh_clk* p_clk); -void wdt_clk_update(struct fh_clk* p_clk); +void ddr_clk_update(struct fh_clk* p_clk); +void ddr_clk_update(struct fh_clk* p_clk); +void fclk_update(struct fh_clk* p_clk); +void aclk_update(struct fh_clk* p_clk); +void hclk_update(struct fh_clk* p_clk); +void pclk_update(struct fh_clk* p_clk); +void isp_aclk_update(struct fh_clk* p_clk); +void vcu_clk_update(struct fh_clk* p_clk); +void vou_clk_update(struct fh_clk* p_clk); +void mipi_p32_clk_update(struct fh_clk* p_clk); +void cis_clk_out_update(struct fh_clk* p_clk); +void pts_update(struct fh_clk* p_clk); +void mipi_pix_clk_update(struct fh_clk* p_clk); +void spi0_clk_update(struct fh_clk* p_clk); +void spi1_clk_update(struct fh_clk* p_clk); +void mipi_dphy_clk20m_update(struct fh_clk* p_clk); +void i2c0_clk_update(struct fh_clk* p_clk); +void i2c1_clk_update(struct fh_clk* p_clk); +void uart0_clk_update(struct fh_clk* p_clk); +void uart1_clk_update(struct fh_clk* p_clk); +void pwm_clk_update(struct fh_clk* p_clk); +void time0_clk_update(struct fh_clk* p_clk); +void time1_clk_update(struct fh_clk* p_clk); +void sadc_clk_update(struct fh_clk* p_clk); +void sdc0_clk2x_update(struct fh_clk* p_clk); +void sdc0_clk_update(struct fh_clk* p_clk); +void sdc0_clk_out_update(struct fh_clk* p_clk); +void sdc0_clk_sample_update(struct fh_clk* p_clk); +void sdc0_clk_drv_update(struct fh_clk* p_clk); +void sdc1_clk2x_update(struct fh_clk* p_clk); +void sdc1_clk_update(struct fh_clk* p_clk); +void sdc1_clk_out_update(struct fh_clk* p_clkt); +void sdc1_clk_sample_update(struct fh_clk* p_clk); +void sdc1_clk_drv_update(struct fh_clk* p_clk); +void eth_ref_clk_update(struct fh_clk* p_clk); +void wdt_clk_update(struct fh_clk* p_clk); rt_int32_t check_pix_clk_source(rt_uint32_t offset,rt_uint32_t mask,rt_uint32_t *value); -void pix_update(struct fh_clk* p_clk); +void pix_update(struct fh_clk* p_clk); struct fh_clk_div{ //some has prediv.... //this two could have or...... -#define PRE_DIV_CAL_ALREADY (0x80000000) -#define PRE_DIV_ENABLE (0x01) -#define DIV_ENABLE (0x10) - rt_uint32_t div_flag; - - rt_uint32_t pdiv_value; - - //rt_uint32_t hw_div_value; - rt_uint32_t sw_div_value; - rt_uint32_t sw_div_multi; - //rt_uint32_t clk_in_hz; - rt_uint32_t reg_offset; - rt_uint32_t reg_mask; - //rt_uint32_t rate; +#define PRE_DIV_CAL_ALREADY (0x80000000) +#define PRE_DIV_ENABLE (0x01) +#define DIV_ENABLE (0x10) + rt_uint32_t div_flag; + + rt_uint32_t pdiv_value; + + //rt_uint32_t hw_div_value; + rt_uint32_t sw_div_value; + rt_uint32_t sw_div_multi; + //rt_uint32_t clk_in_hz; + rt_uint32_t reg_offset; + rt_uint32_t reg_mask; + //rt_uint32_t rate; }; struct fh_clk_mux{ -//#define MUX_LEVEL_1 (1) -//#define MUX_LEVEL_2 (2) -//#define MAX_MUX_LEVEL MUX_LEVEL_2 -// rt_uint32_t lev; -#define HAS_MUX (0) -#define HAS_NO_MUX (1) - rt_uint32_t mux_flag; - rt_uint32_t hw_mux_value; - rt_uint32_t sw_mux_value; - rt_uint32_t reg_offset; - rt_uint32_t reg_mask; +//#define MUX_LEVEL_1 (1) +//#define MUX_LEVEL_2 (2) +//#define MAX_MUX_LEVEL MUX_LEVEL_2 +// rt_uint32_t lev; +#define HAS_MUX (0) +#define HAS_NO_MUX (1) + rt_uint32_t mux_flag; + rt_uint32_t hw_mux_value; + rt_uint32_t sw_mux_value; + rt_uint32_t reg_offset; + rt_uint32_t reg_mask; }; struct fh_clk_gate{ -#define HAS_GATE (0) -#define HAS_NO_GATE (1) - rt_uint32_t gate_flag; -#define CLK_UNGATE (0) -#define CLK_GATE (1) - //rt_uint32_t hw_status; - rt_uint32_t sw_status; - //rt_uint32_t value; +#define HAS_GATE (0) +#define HAS_NO_GATE (1) + rt_uint32_t gate_flag; +#define CLK_UNGATE (0) +#define CLK_GATE (1) + //rt_uint32_t hw_status; + rt_uint32_t sw_status; + //rt_uint32_t value; - rt_uint32_t reg_offset; - rt_uint32_t reg_mask; + rt_uint32_t reg_offset; + rt_uint32_t reg_mask; }; @@ -234,7 +234,7 @@ struct fh_clk_gate{ * ***************/ struct fh_clk_level_1{ - rt_uint32_t clk_in_out; + rt_uint32_t clk_in_out; }; @@ -244,7 +244,7 @@ struct fh_clk_level_1{ * ***************/ struct fh_clk_level_2{ - rt_uint32_t clk_in_out; + rt_uint32_t clk_in_out; }; /*************** @@ -253,19 +253,19 @@ struct fh_clk_level_2{ * ***************/ struct fh_clk_level_3_ddr{ - //rt_uint32_t mux_level; + //rt_uint32_t mux_level; - struct fh_clk_mux mux[2]; - struct fh_clk_gate gate; - struct fh_clk_div div; + struct fh_clk_mux mux[2]; + struct fh_clk_gate gate; + struct fh_clk_div div; }; struct fh_clk_level_3_sdc{ -#define DIFF_REFERENCE (0x80000000) +#define DIFF_REFERENCE (0x80000000) - rt_uint32_t phase_diff; - rt_uint32_t reg_offset; - rt_uint32_t reg_mask; + rt_uint32_t phase_diff; + rt_uint32_t reg_offset; + rt_uint32_t reg_mask; }; @@ -274,26 +274,26 @@ struct fh_clk_level_3_gmac{ }; struct fh_clk_level_3_normal{ - struct fh_clk_mux mux; - struct fh_clk_gate gate; - struct fh_clk_div div; + struct fh_clk_mux mux; + struct fh_clk_gate gate; + struct fh_clk_div div; }; struct fh_clk_level_3 { -#define LEVEL_PERI_NORMAL (0x301) -#define LEVEL_PERI_DDR (0x302) -#define LEVEL_PERI_SDC (0x303) -#define LEVEL_PERI_GMAC (0x304) - rt_uint32_t peri_flag; - union - { - struct fh_clk_level_3_ddr ddr; - struct fh_clk_level_3_sdc sdc; - struct fh_clk_level_3_gmac gmac; - struct fh_clk_level_3_normal normal; - }obj; +#define LEVEL_PERI_NORMAL (0x301) +#define LEVEL_PERI_DDR (0x302) +#define LEVEL_PERI_SDC (0x303) +#define LEVEL_PERI_GMAC (0x304) + rt_uint32_t peri_flag; + union + { + struct fh_clk_level_3_ddr ddr; + struct fh_clk_level_3_sdc sdc; + struct fh_clk_level_3_gmac gmac; + struct fh_clk_level_3_normal normal; + }obj; }; @@ -301,34 +301,34 @@ struct fh_clk_level_3 { struct fh_clk { - char *name; -#define LEVEL_CRYSTAL (0x100) -#define LEVEL_PLL (0x200) -#define LEVEL_PERIPHERAL (0x300) - rt_uint32_t level; + char *name; +#define LEVEL_CRYSTAL (0x100) +#define LEVEL_PLL (0x200) +#define LEVEL_PERIPHERAL (0x300) + rt_uint32_t level; -#define ROOT_NODE (RT_NULL) - struct fh_clk *parent; +#define ROOT_NODE (RT_NULL) + struct fh_clk *parent; - union - { - struct fh_clk_level_1 crystal; - struct fh_clk_level_2 pll; - struct fh_clk_level_3 peri; - }clk; + union + { + struct fh_clk_level_1 crystal; + struct fh_clk_level_2 pll; + struct fh_clk_level_3 peri; + }clk; - rt_uint32_t clk_out_rate; -#define CLK_HAS_NO_GATE (0x80000000) - rt_uint32_t gate; + rt_uint32_t clk_out_rate; +#define CLK_HAS_NO_GATE (0x80000000) + rt_uint32_t gate; - clk_update update_func; + clk_update update_func; - //struct fh_clk_tree *p_tree; + //struct fh_clk_tree *p_tree; }; struct fh_clk_tree{ - rt_uint32_t c_base_addr; - struct fh_clk **clk_head; + rt_uint32_t c_base_addr; + struct fh_clk **clk_head; }; @@ -340,105 +340,105 @@ struct fh_clk_tree{ * * ********/ -#define CRYSTAL_HZ (24000000) +#define CRYSTAL_HZ (24000000) struct fh_clk clk_in = { - .name = "clk_in", - .level = LEVEL_CRYSTAL, - .parent = ROOT_NODE, - .clk.crystal.clk_in_out = CRYSTAL_HZ, - //.clk_out_rate = clk_in.clk.crystal.clk_in_out, - .clk_out_rate = CRYSTAL_HZ, - .update_func = clk_in_update, + .name = "clk_in", + .level = LEVEL_CRYSTAL, + .parent = ROOT_NODE, + .clk.crystal.clk_in_out = CRYSTAL_HZ, + //.clk_out_rate = clk_in.clk.crystal.clk_in_out, + .clk_out_rate = CRYSTAL_HZ, + .update_func = clk_in_update, }; -#define CIS_PCLK_HZ (108000000) +#define CIS_PCLK_HZ (108000000) struct fh_clk cis_pclk = { - .name = "cis_pclk", - .level = LEVEL_CRYSTAL, - .parent = ROOT_NODE, - .clk.crystal.clk_in_out = CIS_PCLK_HZ, - //.clk_out_rate = clk_in.clk.crystal.clk_in_out, - .clk_out_rate = CIS_PCLK_HZ, - .update_func = cis_pclk_update, + .name = "cis_pclk", + .level = LEVEL_CRYSTAL, + .parent = ROOT_NODE, + .clk.crystal.clk_in_out = CIS_PCLK_HZ, + //.clk_out_rate = clk_in.clk.crystal.clk_in_out, + .clk_out_rate = CIS_PCLK_HZ, + .update_func = cis_pclk_update, }; -#define PLL0_HZ (864000000) +#define PLL0_HZ (864000000) struct fh_clk pll0 = { - .name = "pll0", - .level = LEVEL_PLL, - .parent = &clk_in, - .clk.crystal.clk_in_out = PLL0_HZ, - //.clk_out_rate = pll0.clk.crystal.clk_in_out, - .clk_out_rate = PLL0_HZ, - .update_func = pll0_clk_update, + .name = "pll0", + .level = LEVEL_PLL, + .parent = &clk_in, + .clk.crystal.clk_in_out = PLL0_HZ, + //.clk_out_rate = pll0.clk.crystal.clk_in_out, + .clk_out_rate = PLL0_HZ, + .update_func = pll0_clk_update, }; -#define PLL1_HZ (600000000) +#define PLL1_HZ (600000000) struct fh_clk pll1 = { - .name = "pll1", - .level = LEVEL_PLL, - .parent = &clk_in, - .clk.crystal.clk_in_out = PLL1_HZ, - .clk_out_rate = PLL1_HZ, - .update_func = pll1_clk_update, + .name = "pll1", + .level = LEVEL_PLL, + .parent = &clk_in, + .clk.crystal.clk_in_out = PLL1_HZ, + .clk_out_rate = PLL1_HZ, + .update_func = pll1_clk_update, }; //NEED_CAUTION parent not fix... static struct fh_clk ddr_clk_normal = { - .name = "ddr_normal", - .level = LEVEL_PERIPHERAL, - //.parent = &clk_in, - .clk.peri.peri_flag = LEVEL_PERI_DDR, - //0:xtal_clk - //1:pll0_clk -#define MUX0_XTAL_CLK (0) -#define MUX0_PLL0_CLK (1) - - .clk.peri.obj.ddr.mux[0].reg_offset = REG_PMU_SYS_CTRL, - .clk.peri.obj.ddr.mux[0].reg_mask = 1<<0, - - //0:pll0 clk default 864/2M - //1:pll1 clk default 600M -#define MUX1_PLL0_CLK (0) -#define MUX1_PLL1_CLK (1) - .clk.peri.obj.ddr.mux[1].reg_offset = REG_PMU_CLK_SEL, - .clk.peri.obj.ddr.mux[1].reg_mask = 1<<24, - - //gate - //.clk.peri.obj.ddr.gate.enable_status = CLK_ENABLE, + .name = "ddr_normal", + .level = LEVEL_PERIPHERAL, + //.parent = &clk_in, + .clk.peri.peri_flag = LEVEL_PERI_DDR, + //0:xtal_clk + //1:pll0_clk +#define MUX0_XTAL_CLK (0) +#define MUX0_PLL0_CLK (1) + + .clk.peri.obj.ddr.mux[0].reg_offset = REG_PMU_SYS_CTRL, + .clk.peri.obj.ddr.mux[0].reg_mask = 1<<0, + + //0:pll0 clk default 864/2M + //1:pll1 clk default 600M +#define MUX1_PLL0_CLK (0) +#define MUX1_PLL1_CLK (1) + .clk.peri.obj.ddr.mux[1].reg_offset = REG_PMU_CLK_SEL, + .clk.peri.obj.ddr.mux[1].reg_mask = 1<<24, + + //gate + //.clk.peri.obj.ddr.gate.enable_status = CLK_ENABLE, #ifdef FH_CLK_GATE_DEFAULT - .clk.peri.obj.ddr.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, + .clk.peri.obj.ddr.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, #else - .clk.peri.obj.ddr.gate.sw_status = CLK_UNGATE, + .clk.peri.obj.ddr.gate.sw_status = CLK_UNGATE, #endif - .clk.peri.obj.ddr.gate.gate_flag = HAS_GATE, - .clk.peri.obj.ddr.gate.reg_offset = REG_PMU_CLK_GATE, - .clk.peri.obj.ddr.gate.reg_mask = MCLK_GATE, + .clk.peri.obj.ddr.gate.gate_flag = HAS_GATE, + .clk.peri.obj.ddr.gate.reg_offset = REG_PMU_CLK_GATE, + .clk.peri.obj.ddr.gate.reg_mask = MCLK_GATE, - //div - //clk in maybe cry or pll - .clk.peri.obj.ddr.div.div_flag = DIV_ENABLE, - //.clk.peri.obj.ddr.div.pdiv_value = 2, + //div + //clk in maybe cry or pll + .clk.peri.obj.ddr.div.div_flag = DIV_ENABLE, + //.clk.peri.obj.ddr.div.pdiv_value = 2, #ifdef FH_CLK_DIV_DEFAULT - .clk.peri.obj.ddr.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, + .clk.peri.obj.ddr.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, #else - .clk.peri.obj.ddr.div.sw_div_value = 1, + .clk.peri.obj.ddr.div.sw_div_value = 1, #endif - .clk.peri.obj.ddr.div.sw_div_multi =1, - .clk.peri.obj.ddr.div.reg_offset = REG_PMU_CLK_DIV1, - .clk.peri.obj.ddr.div.reg_mask = 0xff <<0, + .clk.peri.obj.ddr.div.sw_div_multi =1, + .clk.peri.obj.ddr.div.reg_offset = REG_PMU_CLK_DIV1, + .clk.peri.obj.ddr.div.reg_mask = 0xff <<0, - .update_func = ddr_clk_update, + .update_func = ddr_clk_update, }; @@ -450,121 +450,121 @@ static struct fh_clk ddr_clk_normal = { //NEED_CAUTION parent not fix... static struct fh_clk ddr_clk_div2 = { - .name = "ddr_div2", - .level = LEVEL_PERIPHERAL, - //.parent = &clk_in, - .clk.peri.peri_flag = LEVEL_PERI_DDR, - //0:xtal_clk - //1:pll0_clk - .clk.peri.obj.ddr.mux[0].reg_offset = REG_PMU_SYS_CTRL, - .clk.peri.obj.ddr.mux[0].reg_mask = 1<<0, - - //0:pll0 clk default 864/2M - //1:pll1 clk default 600M - .clk.peri.obj.ddr.mux[1].reg_offset = REG_PMU_CLK_SEL, - .clk.peri.obj.ddr.mux[1].reg_mask = 1<<24, - - //gate - //.clk.peri.obj.ddr.gate.enable_status = CLK_ENABLE, + .name = "ddr_div2", + .level = LEVEL_PERIPHERAL, + //.parent = &clk_in, + .clk.peri.peri_flag = LEVEL_PERI_DDR, + //0:xtal_clk + //1:pll0_clk + .clk.peri.obj.ddr.mux[0].reg_offset = REG_PMU_SYS_CTRL, + .clk.peri.obj.ddr.mux[0].reg_mask = 1<<0, + + //0:pll0 clk default 864/2M + //1:pll1 clk default 600M + .clk.peri.obj.ddr.mux[1].reg_offset = REG_PMU_CLK_SEL, + .clk.peri.obj.ddr.mux[1].reg_mask = 1<<24, + + //gate + //.clk.peri.obj.ddr.gate.enable_status = CLK_ENABLE, #ifdef FH_CLK_GATE_DEFAULT - .clk.peri.obj.ddr.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, + .clk.peri.obj.ddr.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, #else - .clk.peri.obj.ddr.gate.sw_status = CLK_UNGATE, + .clk.peri.obj.ddr.gate.sw_status = CLK_UNGATE, #endif - .clk.peri.obj.ddr.gate.gate_flag = HAS_GATE, - .clk.peri.obj.ddr.gate.reg_offset = REG_PMU_CLK_GATE, - .clk.peri.obj.ddr.gate.reg_mask = MCLK_GATE, - - //div - //clk in maybe cry or pll - .clk.peri.obj.ddr.div.div_flag = PRE_DIV_ENABLE | DIV_ENABLE, - .clk.peri.obj.ddr.div.pdiv_value = 2, + .clk.peri.obj.ddr.gate.gate_flag = HAS_GATE, + .clk.peri.obj.ddr.gate.reg_offset = REG_PMU_CLK_GATE, + .clk.peri.obj.ddr.gate.reg_mask = MCLK_GATE, + + //div + //clk in maybe cry or pll + .clk.peri.obj.ddr.div.div_flag = PRE_DIV_ENABLE | DIV_ENABLE, + .clk.peri.obj.ddr.div.pdiv_value = 2, #ifdef FH_CLK_DIV_DEFAULT - .clk.peri.obj.ddr.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, + .clk.peri.obj.ddr.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, #else - .clk.peri.obj.ddr.div.sw_div_value = 1, + .clk.peri.obj.ddr.div.sw_div_value = 1, #endif - .clk.peri.obj.ddr.div.sw_div_multi =1, - .clk.peri.obj.ddr.div.reg_offset = REG_PMU_CLK_DIV1, - .clk.peri.obj.ddr.div.reg_mask = 0xff <<0, + .clk.peri.obj.ddr.div.sw_div_multi =1, + .clk.peri.obj.ddr.div.reg_offset = REG_PMU_CLK_DIV1, + .clk.peri.obj.ddr.div.reg_mask = 0xff <<0, - .update_func = ddr_clk_update, + .update_func = ddr_clk_update, }; static struct fh_clk cpu_fclk = { - .name = "cpu_fclk", - .level = LEVEL_PERIPHERAL, -// //.parent = &clk_in, - .clk.peri.peri_flag = LEVEL_PERI_NORMAL, + .name = "cpu_fclk", + .level = LEVEL_PERIPHERAL, +// //.parent = &clk_in, + .clk.peri.peri_flag = LEVEL_PERI_NORMAL, - //0:xtal_clk - //1:pll0_clk - .clk.peri.obj.normal.mux.reg_offset = REG_PMU_SYS_CTRL, - .clk.peri.obj.normal.mux.reg_mask = 1<<0, + //0:xtal_clk + //1:pll0_clk + .clk.peri.obj.normal.mux.reg_offset = REG_PMU_SYS_CTRL, + .clk.peri.obj.normal.mux.reg_mask = 1<<0, - //gate - .clk.peri.obj.normal.gate.gate_flag = HAS_NO_GATE, - //.clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, - //.clk.peri.obj.normal.gate.reg_mask = CPU_FCLK0_GATE, + //gate + .clk.peri.obj.normal.gate.gate_flag = HAS_NO_GATE, + //.clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, + //.clk.peri.obj.normal.gate.reg_mask = CPU_FCLK0_GATE, - //div - .clk.peri.obj.normal.div.div_flag = DIV_ENABLE, + //div + .clk.peri.obj.normal.div.div_flag = DIV_ENABLE, #ifdef FH_CLK_DIV_DEFAULT - .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, + .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, #else - .clk.peri.obj.normal.div.sw_div_value = 0, + .clk.peri.obj.normal.div.sw_div_value = 0, #endif - .clk.peri.obj.normal.div.sw_div_multi =1, - .clk.peri.obj.normal.div.reg_offset =REG_PMU_CLK_DIV0, - .clk.peri.obj.normal.div.reg_mask = 0xff << 0, + .clk.peri.obj.normal.div.sw_div_multi =1, + .clk.peri.obj.normal.div.reg_offset =REG_PMU_CLK_DIV0, + .clk.peri.obj.normal.div.reg_mask = 0xff << 0, - .update_func = fclk_update, + .update_func = fclk_update, }; //NEED_CAUTION parent not fix... static struct fh_clk cpu_aclk = { - .name = "cpu_aclk", - .level = LEVEL_PERIPHERAL, -// //.parent = &clk_in, - .clk.peri.peri_flag = LEVEL_PERI_NORMAL, + .name = "cpu_aclk", + .level = LEVEL_PERIPHERAL, +// //.parent = &clk_in, + .clk.peri.peri_flag = LEVEL_PERI_NORMAL, - //0:xtal_clk - //1:pll0_clk - .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX, -// .clk.peri.obj.normal.mux.reg_offset = REG_PMU_SYS_CTRL, -// .clk.peri.obj.normal.mux.reg_mask = 1<<0, + //0:xtal_clk + //1:pll0_clk + .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX, +// .clk.peri.obj.normal.mux.reg_offset = REG_PMU_SYS_CTRL, +// .clk.peri.obj.normal.mux.reg_mask = 1<<0, - //gate - .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, + //gate + .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, #ifdef FH_CLK_GATE_DEFAULT - .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, + .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, #else - .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, + .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, #endif - .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, - .clk.peri.obj.normal.gate.reg_mask = CPU_FCLK0_GATE, + .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, + .clk.peri.obj.normal.gate.reg_mask = CPU_FCLK0_GATE, - //div - .clk.peri.obj.normal.div.div_flag = PRE_DIV_ENABLE, - .clk.peri.obj.normal.div.pdiv_value = 2, -// .clk.peri.obj.normal.div.reg_offset =REG_PMU_CLK_DIV0, -// .clk.peri.obj.normal.div.reg_mask = 0xff << 0, + //div + .clk.peri.obj.normal.div.div_flag = PRE_DIV_ENABLE, + .clk.peri.obj.normal.div.pdiv_value = 2, +// .clk.peri.obj.normal.div.reg_offset =REG_PMU_CLK_DIV0, +// .clk.peri.obj.normal.div.reg_mask = 0xff << 0, - .update_func = aclk_update, + .update_func = aclk_update, }; @@ -572,282 +572,282 @@ static struct fh_clk cpu_aclk = { static struct fh_clk cpu_hclk = { - .name = "cpu_hclk", - .level = LEVEL_PERIPHERAL, -// //.parent = &clk_in, - .clk.peri.peri_flag = LEVEL_PERI_NORMAL, + .name = "cpu_hclk", + .level = LEVEL_PERIPHERAL, +// //.parent = &clk_in, + .clk.peri.peri_flag = LEVEL_PERI_NORMAL, - //0:xtal_clk - //1:pll0_clk - .clk.peri.obj.normal.mux.reg_offset = REG_PMU_SYS_CTRL, - .clk.peri.obj.normal.mux.reg_mask = 1<<0, + //0:xtal_clk + //1:pll0_clk + .clk.peri.obj.normal.mux.reg_offset = REG_PMU_SYS_CTRL, + .clk.peri.obj.normal.mux.reg_mask = 1<<0, - //gate - .clk.peri.obj.normal.gate.gate_flag = HAS_NO_GATE, - //.clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, - //.clk.peri.obj.normal.gate.reg_mask = CPU_FCLK0_GATE, + //gate + .clk.peri.obj.normal.gate.gate_flag = HAS_NO_GATE, + //.clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, + //.clk.peri.obj.normal.gate.reg_mask = CPU_FCLK0_GATE, - //div - .clk.peri.obj.normal.div.div_flag = DIV_ENABLE, + //div + .clk.peri.obj.normal.div.div_flag = DIV_ENABLE, #ifdef FH_CLK_DIV_DEFAULT - .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, + .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, #else - .clk.peri.obj.normal.div.sw_div_value = 1, + .clk.peri.obj.normal.div.sw_div_value = 1, #endif - .clk.peri.obj.normal.div.sw_div_multi =1, - .clk.peri.obj.normal.div.reg_offset =REG_PMU_CLK_DIV0, - .clk.peri.obj.normal.div.reg_mask = 0xff << 16, + .clk.peri.obj.normal.div.sw_div_multi =1, + .clk.peri.obj.normal.div.reg_offset =REG_PMU_CLK_DIV0, + .clk.peri.obj.normal.div.reg_mask = 0xff << 16, - .update_func = hclk_update, + .update_func = hclk_update, }; //NEED_CAUTION parent not fix... static struct fh_clk cpu_pclk = { - .name = "cpu_pclk", - .level = LEVEL_PERIPHERAL, -// //.parent = &clk_in, - .clk.peri.peri_flag = LEVEL_PERI_NORMAL, + .name = "cpu_pclk", + .level = LEVEL_PERIPHERAL, +// //.parent = &clk_in, + .clk.peri.peri_flag = LEVEL_PERI_NORMAL, - //0:xtal_clk - //1:pll0_clk - .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX, + //0:xtal_clk + //1:pll0_clk + .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX, - //gate - .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, + //gate + .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, #ifdef FH_CLK_GATE_DEFAULT - .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, + .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, #else - .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, + .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, #endif - .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, - .clk.peri.obj.normal.gate.reg_mask = HCLK_GATE, + .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, + .clk.peri.obj.normal.gate.reg_mask = HCLK_GATE, - //div - .clk.peri.obj.normal.div.div_flag = PRE_DIV_ENABLE, - .clk.peri.obj.normal.div.pdiv_value = 2, -// .clk.peri.obj.normal.div.reg_offset =REG_PMU_CLK_DIV0, -// .clk.peri.obj.normal.div.reg_mask = 0xff << 0, + //div + .clk.peri.obj.normal.div.div_flag = PRE_DIV_ENABLE, + .clk.peri.obj.normal.div.pdiv_value = 2, +// .clk.peri.obj.normal.div.reg_offset =REG_PMU_CLK_DIV0, +// .clk.peri.obj.normal.div.reg_mask = 0xff << 0, - .update_func = pclk_update, + .update_func = pclk_update, }; //NEED_CAUTION parent not fix... static struct fh_clk isp_aclk = { - .name = "isp_aclk", - .level = LEVEL_PERIPHERAL, -// //.parent = &clk_in, - .clk.peri.peri_flag = LEVEL_PERI_NORMAL, + .name = "isp_aclk", + .level = LEVEL_PERIPHERAL, +// //.parent = &clk_in, + .clk.peri.peri_flag = LEVEL_PERI_NORMAL, - //0:xtal_clk - //1:pll0_clk - .clk.peri.obj.normal.mux.reg_offset = REG_PMU_SYS_CTRL, - .clk.peri.obj.normal.mux.reg_mask = 1<<0, + //0:xtal_clk + //1:pll0_clk + .clk.peri.obj.normal.mux.reg_offset = REG_PMU_SYS_CTRL, + .clk.peri.obj.normal.mux.reg_mask = 1<<0, - //gate - .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, - .clk.peri.obj.normal.gate.reg_mask = ISP_ACLK_GATE, - .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, + //gate + .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, + .clk.peri.obj.normal.gate.reg_mask = ISP_ACLK_GATE, + .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, #ifdef FH_CLK_GATE_DEFAULT - .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, + .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, #else - .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, + .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, #endif - //div - .clk.peri.obj.normal.div.div_flag = DIV_ENABLE, - .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV0, - .clk.peri.obj.normal.div.reg_mask = 0x03 << 8, - .clk.peri.obj.normal.div.sw_div_multi =1, + //div + .clk.peri.obj.normal.div.div_flag = DIV_ENABLE, + .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV0, + .clk.peri.obj.normal.div.reg_mask = 0x03 << 8, + .clk.peri.obj.normal.div.sw_div_multi =1, #ifdef FH_CLK_DIV_DEFAULT - .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, + .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, #else - .clk.peri.obj.normal.div.sw_div_value = 1, + .clk.peri.obj.normal.div.sw_div_value = 1, #endif - .update_func = isp_aclk_update, + .update_func = isp_aclk_update, }; // ////NEED_CAUTION parent not fix... static struct fh_clk vcu_clk = { - .name = "vcu_clk", - .level = LEVEL_PERIPHERAL, -// //.parent = &clk_in, - .clk.peri.peri_flag = LEVEL_PERI_NORMAL, + .name = "vcu_clk", + .level = LEVEL_PERIPHERAL, +// //.parent = &clk_in, + .clk.peri.peri_flag = LEVEL_PERI_NORMAL, - //0:xtal_clk - //1:pll0_clk - .clk.peri.obj.normal.mux.reg_offset = REG_PMU_SYS_CTRL, - .clk.peri.obj.normal.mux.reg_mask = 1<<0, + //0:xtal_clk + //1:pll0_clk + .clk.peri.obj.normal.mux.reg_offset = REG_PMU_SYS_CTRL, + .clk.peri.obj.normal.mux.reg_mask = 1<<0, - //gate - .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, - .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, - .clk.peri.obj.normal.gate.reg_mask = VCU_CLK_GATE, + //gate + .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, + .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, + .clk.peri.obj.normal.gate.reg_mask = VCU_CLK_GATE, #ifdef FH_CLK_GATE_DEFAULT - .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, + .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, #else - .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, + .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, #endif - //div - .clk.peri.obj.normal.div.div_flag = DIV_ENABLE, - .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV0, - .clk.peri.obj.normal.div.reg_mask = 0x03 << 24, - .clk.peri.obj.normal.div.sw_div_multi =1, + //div + .clk.peri.obj.normal.div.div_flag = DIV_ENABLE, + .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV0, + .clk.peri.obj.normal.div.reg_mask = 0x03 << 24, + .clk.peri.obj.normal.div.sw_div_multi =1, #ifdef FH_CLK_DIV_DEFAULT - .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, + .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, #else - .clk.peri.obj.normal.div.sw_div_value = 1, + .clk.peri.obj.normal.div.sw_div_value = 1, #endif - .update_func = vcu_clk_update, + .update_func = vcu_clk_update, }; static struct fh_clk vou_clk = { - .name = "vou_clk", - .level = LEVEL_PERIPHERAL, -// //.parent = &clk_in, - .clk.peri.peri_flag = LEVEL_PERI_NORMAL, + .name = "vou_clk", + .level = LEVEL_PERIPHERAL, +// //.parent = &clk_in, + .clk.peri.peri_flag = LEVEL_PERI_NORMAL, - //0:xtal_clk - //1:pll0_clk - .clk.peri.obj.normal.mux.reg_offset = REG_PMU_SYS_CTRL, - .clk.peri.obj.normal.mux.reg_mask = 1<<0, + //0:xtal_clk + //1:pll0_clk + .clk.peri.obj.normal.mux.reg_offset = REG_PMU_SYS_CTRL, + .clk.peri.obj.normal.mux.reg_mask = 1<<0, - //gate - .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, - .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, - .clk.peri.obj.normal.gate.reg_mask = VOU_CLK_GATE, + //gate + .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, + .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, + .clk.peri.obj.normal.gate.reg_mask = VOU_CLK_GATE, #ifdef FH_CLK_GATE_DEFAULT - .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, + .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, #else - .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, + .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, #endif - //div - .clk.peri.obj.normal.div.div_flag = DIV_ENABLE, - .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV1, - .clk.peri.obj.normal.div.reg_mask = 0x3f << 8, - .clk.peri.obj.normal.div.sw_div_multi =1, + //div + .clk.peri.obj.normal.div.div_flag = DIV_ENABLE, + .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV1, + .clk.peri.obj.normal.div.reg_mask = 0x3f << 8, + .clk.peri.obj.normal.div.sw_div_multi =1, #ifdef FH_CLK_DIV_DEFAULT - .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, + .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, #else - .clk.peri.obj.normal.div.sw_div_value = 1, + .clk.peri.obj.normal.div.sw_div_value = 1, #endif - .update_func = vou_clk_update, + .update_func = vou_clk_update, }; static struct fh_clk mipi_p32_clk = { - .name = "mipi_p32_clk", - .level = LEVEL_PERIPHERAL, -// //.parent = &clk_in, - .clk.peri.peri_flag = LEVEL_PERI_NORMAL, + .name = "mipi_p32_clk", + .level = LEVEL_PERIPHERAL, +// //.parent = &clk_in, + .clk.peri.peri_flag = LEVEL_PERI_NORMAL, - //0:xtal_clk - //1:pll0_clk - .clk.peri.obj.normal.mux.reg_offset = REG_PMU_SYS_CTRL, - .clk.peri.obj.normal.mux.reg_mask = 1<<0, + //0:xtal_clk + //1:pll0_clk + .clk.peri.obj.normal.mux.reg_offset = REG_PMU_SYS_CTRL, + .clk.peri.obj.normal.mux.reg_mask = 1<<0, - //gate - .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, - .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, - .clk.peri.obj.normal.gate.reg_mask = MIPI_P32_CLK_GATE, + //gate + .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, + .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, + .clk.peri.obj.normal.gate.reg_mask = MIPI_P32_CLK_GATE, #ifdef FH_CLK_GATE_DEFAULT - .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, + .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, #else - .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, + .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, #endif - //div - .clk.peri.obj.normal.div.div_flag = DIV_ENABLE, - .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV2, - .clk.peri.obj.normal.div.reg_mask = 0x0f << 16, - .clk.peri.obj.normal.div.sw_div_multi =1, + //div + .clk.peri.obj.normal.div.div_flag = DIV_ENABLE, + .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV2, + .clk.peri.obj.normal.div.reg_mask = 0x0f << 16, + .clk.peri.obj.normal.div.sw_div_multi =1, #ifdef FH_CLK_DIV_DEFAULT - .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, + .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, #else - .clk.peri.obj.normal.div.sw_div_value = 1, + .clk.peri.obj.normal.div.sw_div_value = 1, #endif - .update_func = mipi_p32_clk_update, + .update_func = mipi_p32_clk_update, }; static struct fh_clk cis_clk_out = { - .name = "cis_clk_out", - .level = LEVEL_PERIPHERAL, -// //.parent = &clk_in, - .clk.peri.peri_flag = LEVEL_PERI_NORMAL, + .name = "cis_clk_out", + .level = LEVEL_PERIPHERAL, +// //.parent = &clk_in, + .clk.peri.peri_flag = LEVEL_PERI_NORMAL, - //0:xtal_clk - //1:pll0_clk - .clk.peri.obj.normal.mux.reg_offset = REG_PMU_SYS_CTRL, - .clk.peri.obj.normal.mux.reg_mask = 1<<0, + //0:xtal_clk + //1:pll0_clk + .clk.peri.obj.normal.mux.reg_offset = REG_PMU_SYS_CTRL, + .clk.peri.obj.normal.mux.reg_mask = 1<<0, - //gate - .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, - .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, - .clk.peri.obj.normal.gate.reg_mask = CIS_CLK_OUT_GATE, + //gate + .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, + .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, + .clk.peri.obj.normal.gate.reg_mask = CIS_CLK_OUT_GATE, #ifdef FH_CLK_GATE_DEFAULT - .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, + .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, #else - .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, + .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, #endif - //div - .clk.peri.obj.normal.div.div_flag = DIV_ENABLE, - .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV1, - .clk.peri.obj.normal.div.reg_mask = 0xff << 16, - .clk.peri.obj.normal.div.sw_div_multi =1, + //div + .clk.peri.obj.normal.div.div_flag = DIV_ENABLE, + .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV1, + .clk.peri.obj.normal.div.reg_mask = 0xff << 16, + .clk.peri.obj.normal.div.sw_div_multi =1, #ifdef FH_CLK_DIV_DEFAULT - .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, + .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, #else - .clk.peri.obj.normal.div.sw_div_value = 3, + .clk.peri.obj.normal.div.sw_div_value = 3, #endif - .update_func = cis_clk_out_update, + .update_func = cis_clk_out_update, }; @@ -855,43 +855,43 @@ static struct fh_clk cis_clk_out = { static struct fh_clk pts_clk = { - .name = "pts_clk", - .level = LEVEL_PERIPHERAL, -// //.parent = &clk_in, - .clk.peri.peri_flag = LEVEL_PERI_NORMAL, + .name = "pts_clk", + .level = LEVEL_PERIPHERAL, +// //.parent = &clk_in, + .clk.peri.peri_flag = LEVEL_PERI_NORMAL, - //0:xtal_clk - //1:pll0_clk - .clk.peri.obj.normal.mux.reg_offset = REG_PMU_SYS_CTRL, - .clk.peri.obj.normal.mux.reg_mask = 1<<0, + //0:xtal_clk + //1:pll0_clk + .clk.peri.obj.normal.mux.reg_offset = REG_PMU_SYS_CTRL, + .clk.peri.obj.normal.mux.reg_mask = 1<<0, - //gate - .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, - .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, - .clk.peri.obj.normal.gate.reg_mask = PTS_CLK_GATE, + //gate + .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, + .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, + .clk.peri.obj.normal.gate.reg_mask = PTS_CLK_GATE, #ifdef FH_CLK_GATE_DEFAULT - .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, + .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, #else - .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, + .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, #endif - //div - .clk.peri.obj.normal.div.div_flag = DIV_ENABLE | PRE_DIV_ENABLE, - .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV2, - .clk.peri.obj.normal.div.reg_mask = 0xff << 0, - .clk.peri.obj.normal.div.sw_div_multi =1, + //div + .clk.peri.obj.normal.div.div_flag = DIV_ENABLE | PRE_DIV_ENABLE, + .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV2, + .clk.peri.obj.normal.div.reg_mask = 0xff << 0, + .clk.peri.obj.normal.div.sw_div_multi =1, #ifdef FH_CLK_DIV_DEFAULT - .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, + .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, #else - .clk.peri.obj.normal.div.sw_div_value = 35, + .clk.peri.obj.normal.div.sw_div_value = 35, #endif - .clk.peri.obj.normal.div.pdiv_value = 12, + .clk.peri.obj.normal.div.pdiv_value = 12, - .update_func = pts_update, + .update_func = pts_update, }; @@ -899,31 +899,31 @@ static struct fh_clk pts_clk = { static struct fh_clk mipi_pix_clk = { - .name = "mipi_pix_clk_i", - .level = LEVEL_PERIPHERAL, - .clk.peri.peri_flag = LEVEL_PERI_NORMAL, + .name = "mipi_pix_clk_i", + .level = LEVEL_PERIPHERAL, + .clk.peri.peri_flag = LEVEL_PERI_NORMAL, - //0:xtal_clk - //1:pll0_clk - .clk.peri.obj.normal.mux.reg_offset = REG_PMU_SYS_CTRL, - .clk.peri.obj.normal.mux.reg_mask = 1<<0, + //0:xtal_clk + //1:pll0_clk + .clk.peri.obj.normal.mux.reg_offset = REG_PMU_SYS_CTRL, + .clk.peri.obj.normal.mux.reg_mask = 1<<0, - //gate - .clk.peri.obj.normal.gate.gate_flag = HAS_NO_GATE, + //gate + .clk.peri.obj.normal.gate.gate_flag = HAS_NO_GATE, - //div - .clk.peri.obj.normal.div.div_flag = DIV_ENABLE, - .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV2, - .clk.peri.obj.normal.div.reg_mask = 0x0f << 24, - .clk.peri.obj.normal.div.sw_div_multi =1, + //div + .clk.peri.obj.normal.div.div_flag = DIV_ENABLE, + .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV2, + .clk.peri.obj.normal.div.reg_mask = 0x0f << 24, + .clk.peri.obj.normal.div.sw_div_multi =1, #ifdef FH_CLK_DIV_DEFAULT - .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, + .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, #else - .clk.peri.obj.normal.div.sw_div_value = 3, + .clk.peri.obj.normal.div.sw_div_value = 3, #endif - .update_func = mipi_pix_clk_update, + .update_func = mipi_pix_clk_update, }; @@ -931,37 +931,37 @@ static struct fh_clk mipi_pix_clk = { static struct fh_clk pix_clk = { - .name = "pix_clk", - .level = LEVEL_PERIPHERAL, -// //.parent = &clk_in, - .clk.peri.peri_flag = LEVEL_PERI_NORMAL, + .name = "pix_clk", + .level = LEVEL_PERIPHERAL, +// //.parent = &clk_in, + .clk.peri.peri_flag = LEVEL_PERI_NORMAL, - //0:xtal_clk - //1:pll0_clk -#define CIS_PIX_CLK (0) -#define CIS_PIX_CLK_OPPOSITE (1) -#define MIPI_PIX_CLK (2) + //0:xtal_clk + //1:pll0_clk +#define CIS_PIX_CLK (0) +#define CIS_PIX_CLK_OPPOSITE (1) +#define MIPI_PIX_CLK (2) - .clk.peri.obj.normal.mux.reg_offset = REG_PMU_CLK_SEL, - .clk.peri.obj.normal.mux.reg_mask = 3<<4, + .clk.peri.obj.normal.mux.reg_offset = REG_PMU_CLK_SEL, + .clk.peri.obj.normal.mux.reg_mask = 3<<4, - //gate - .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, - .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, - .clk.peri.obj.normal.gate.reg_mask = PIX_CLK_GATE, + //gate + .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, + .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, + .clk.peri.obj.normal.gate.reg_mask = PIX_CLK_GATE, #ifdef FH_CLK_GATE_DEFAULT - .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, + .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, #else - .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, + .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, #endif - //div - .clk.peri.obj.normal.div.div_flag = 0, + //div + .clk.peri.obj.normal.div.div_flag = 0, - .update_func = pix_update, + .update_func = pix_update, }; @@ -971,41 +971,41 @@ static struct fh_clk pix_clk = { static struct fh_clk spi0_clk = { - .name = "spi0_clk", - .level = LEVEL_PERIPHERAL, -// //.parent = &clk_in, - .clk.peri.peri_flag = LEVEL_PERI_NORMAL, + .name = "spi0_clk", + .level = LEVEL_PERIPHERAL, +// //.parent = &clk_in, + .clk.peri.peri_flag = LEVEL_PERI_NORMAL, - .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX, + .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX, - //gate - .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, - .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, - .clk.peri.obj.normal.gate.reg_mask = SPI0_CLK_GATE, + //gate + .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, + .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, + .clk.peri.obj.normal.gate.reg_mask = SPI0_CLK_GATE, #ifdef FH_CLK_GATE_DEFAULT - .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, + .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, #else - .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, + .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, #endif - //div - .clk.peri.obj.normal.div.div_flag = DIV_ENABLE, - .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV3, - .clk.peri.obj.normal.div.reg_mask = 0xff << 0, - .clk.peri.obj.normal.div.sw_div_multi =1, + //div + .clk.peri.obj.normal.div.div_flag = DIV_ENABLE, + .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV3, + .clk.peri.obj.normal.div.reg_mask = 0xff << 0, + .clk.peri.obj.normal.div.sw_div_multi =1, #ifdef FH_CLK_DIV_DEFAULT - .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, + .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, #else - .clk.peri.obj.normal.div.sw_div_value = 11, + .clk.peri.obj.normal.div.sw_div_value = 11, #endif - .update_func = spi0_clk_update, + .update_func = spi0_clk_update, }; @@ -1013,46 +1013,46 @@ static struct fh_clk spi0_clk = { static struct fh_clk spi1_clk = { - .name = "spi1_clk", - .level = LEVEL_PERIPHERAL, -// //.parent = &clk_in, - .clk.peri.peri_flag = LEVEL_PERI_NORMAL, + .name = "spi1_clk", + .level = LEVEL_PERIPHERAL, +// //.parent = &clk_in, + .clk.peri.peri_flag = LEVEL_PERI_NORMAL, - .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX, - //gate - .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, - .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, - .clk.peri.obj.normal.gate.reg_mask = SPI1_CLK_GATE, + .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX, + //gate + .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, + .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, + .clk.peri.obj.normal.gate.reg_mask = SPI1_CLK_GATE, #ifdef FH_CLK_GATE_DEFAULT - .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, + .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, #else - .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, + .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, #endif - //div - .clk.peri.obj.normal.div.div_flag = DIV_ENABLE, - .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV3, - .clk.peri.obj.normal.div.reg_mask = 0xff << 16, - .clk.peri.obj.normal.div.sw_div_multi =1, + //div + .clk.peri.obj.normal.div.div_flag = DIV_ENABLE, + .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV3, + .clk.peri.obj.normal.div.reg_mask = 0xff << 16, + .clk.peri.obj.normal.div.sw_div_multi =1, #ifdef FH_CLK_DIV_DEFAULT - .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, + .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, #else - .clk.peri.obj.normal.div.sw_div_value = 11, + .clk.peri.obj.normal.div.sw_div_value = 11, #endif #ifdef RT_USING_SPI1 - .clk.peri.obj.normal.div.sw_div_value = 11, + .clk.peri.obj.normal.div.sw_div_value = 11, #endif - .update_func = spi1_clk_update, + .update_func = spi1_clk_update, }; @@ -1060,200 +1060,200 @@ static struct fh_clk spi1_clk = { static struct fh_clk mipi_dphy_clk20m = { - .name = "mipi_dphy_clk20m", - .level = LEVEL_PERIPHERAL, -// //.parent = &clk_in, - .clk.peri.peri_flag = LEVEL_PERI_NORMAL, + .name = "mipi_dphy_clk20m", + .level = LEVEL_PERIPHERAL, +// //.parent = &clk_in, + .clk.peri.peri_flag = LEVEL_PERI_NORMAL, - .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX, + .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX, - //gate - .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, - .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, - .clk.peri.obj.normal.gate.reg_mask = MIPI_DPHY_CLK20M_GATE, + //gate + .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, + .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, + .clk.peri.obj.normal.gate.reg_mask = MIPI_DPHY_CLK20M_GATE, #ifdef FH_CLK_GATE_DEFAULT - .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, + .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, #else - .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, + .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, #endif - //div - .clk.peri.obj.normal.div.div_flag = PRE_DIV_ENABLE, -// .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV3, -// .clk.peri.obj.normal.div.reg_mask = 0xff << 16, - .clk.peri.obj.normal.div.sw_div_multi =1, - .clk.peri.obj.normal.div.pdiv_value = 30, -// .clk.peri.obj.normal.div.sw_div_value = 11, + //div + .clk.peri.obj.normal.div.div_flag = PRE_DIV_ENABLE, +// .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV3, +// .clk.peri.obj.normal.div.reg_mask = 0xff << 16, + .clk.peri.obj.normal.div.sw_div_multi =1, + .clk.peri.obj.normal.div.pdiv_value = 30, +// .clk.peri.obj.normal.div.sw_div_value = 11, - .update_func = mipi_dphy_clk20m_update, + .update_func = mipi_dphy_clk20m_update, }; static struct fh_clk i2c0_clk = { - .name = "i2c0_clk", - .level = LEVEL_PERIPHERAL, -// //.parent = &clk_in, - .clk.peri.peri_flag = LEVEL_PERI_NORMAL, + .name = "i2c0_clk", + .level = LEVEL_PERIPHERAL, +// //.parent = &clk_in, + .clk.peri.peri_flag = LEVEL_PERI_NORMAL, - .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX, + .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX, - //gate - .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, - .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, - .clk.peri.obj.normal.gate.reg_mask = I2C0_CLK_GATE, + //gate + .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, + .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, + .clk.peri.obj.normal.gate.reg_mask = I2C0_CLK_GATE, #ifdef FH_CLK_GATE_DEFAULT - .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, + .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, #else - .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, + .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, #endif - //div - .clk.peri.obj.normal.div.div_flag = DIV_ENABLE | PRE_DIV_ENABLE, - .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV4, - .clk.peri.obj.normal.div.reg_mask = 0x3f << 16, - .clk.peri.obj.normal.div.sw_div_multi = 1, + //div + .clk.peri.obj.normal.div.div_flag = DIV_ENABLE | PRE_DIV_ENABLE, + .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV4, + .clk.peri.obj.normal.div.reg_mask = 0x3f << 16, + .clk.peri.obj.normal.div.sw_div_multi = 1, #ifdef FH_CLK_DIV_DEFAULT - .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, + .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, #else - .clk.peri.obj.normal.div.sw_div_value = 1, + .clk.peri.obj.normal.div.sw_div_value = 1, #endif - .clk.peri.obj.normal.div.pdiv_value = 20, + .clk.peri.obj.normal.div.pdiv_value = 20, - .update_func = i2c0_clk_update, + .update_func = i2c0_clk_update, }; static struct fh_clk i2c1_clk = { - .name = "i2c1_clk", - .level = LEVEL_PERIPHERAL, -// //.parent = &clk_in, - .clk.peri.peri_flag = LEVEL_PERI_NORMAL, + .name = "i2c1_clk", + .level = LEVEL_PERIPHERAL, +// //.parent = &clk_in, + .clk.peri.peri_flag = LEVEL_PERI_NORMAL, - .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX, + .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX, - //gate - .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, - .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, - .clk.peri.obj.normal.gate.reg_mask = I2C1_CLK_GATE, + //gate + .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, + .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, + .clk.peri.obj.normal.gate.reg_mask = I2C1_CLK_GATE, #ifdef FH_CLK_GATE_DEFAULT - .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, + .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, #else - .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, + .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, #endif - //div - .clk.peri.obj.normal.div.div_flag = DIV_ENABLE | PRE_DIV_ENABLE, - .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV4, - .clk.peri.obj.normal.div.reg_mask = 0x3f << 24, - .clk.peri.obj.normal.div.sw_div_multi = 1, + //div + .clk.peri.obj.normal.div.div_flag = DIV_ENABLE | PRE_DIV_ENABLE, + .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV4, + .clk.peri.obj.normal.div.reg_mask = 0x3f << 24, + .clk.peri.obj.normal.div.sw_div_multi = 1, #ifdef FH_CLK_DIV_DEFAULT - .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, + .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, #else - .clk.peri.obj.normal.div.sw_div_value = 1, + .clk.peri.obj.normal.div.sw_div_value = 1, #endif - .clk.peri.obj.normal.div.pdiv_value = 20, + .clk.peri.obj.normal.div.pdiv_value = 20, - .update_func = i2c1_clk_update, + .update_func = i2c1_clk_update, }; static struct fh_clk uart0_clk = { - .name = "uart0_clk", - .level = LEVEL_PERIPHERAL, -// //.parent = &clk_in, - .clk.peri.peri_flag = LEVEL_PERI_NORMAL, + .name = "uart0_clk", + .level = LEVEL_PERIPHERAL, +// //.parent = &clk_in, + .clk.peri.peri_flag = LEVEL_PERI_NORMAL, - .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX, + .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX, - //gate - .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, - .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, - .clk.peri.obj.normal.gate.reg_mask = UART0_CLK_GATE, + //gate + .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, + .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, + .clk.peri.obj.normal.gate.reg_mask = UART0_CLK_GATE, #ifdef FH_CLK_GATE_DEFAULT - .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, + .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, #else - .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, + .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, #endif - //div - .clk.peri.obj.normal.div.div_flag = DIV_ENABLE | PRE_DIV_ENABLE, - .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV4, - .clk.peri.obj.normal.div.reg_mask = 0x1f << 0, - .clk.peri.obj.normal.div.sw_div_multi = 1, + //div + .clk.peri.obj.normal.div.div_flag = DIV_ENABLE | PRE_DIV_ENABLE, + .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV4, + .clk.peri.obj.normal.div.reg_mask = 0x1f << 0, + .clk.peri.obj.normal.div.sw_div_multi = 1, #ifdef FH_CLK_DIV_DEFAULT - .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, + .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, #else - .clk.peri.obj.normal.div.sw_div_value = 1, + .clk.peri.obj.normal.div.sw_div_value = 1, #endif - .clk.peri.obj.normal.div.pdiv_value = 10, + .clk.peri.obj.normal.div.pdiv_value = 10, - .update_func = uart0_clk_update, + .update_func = uart0_clk_update, }; static struct fh_clk uart1_clk = { - .name = "uart1_clk", - .level = LEVEL_PERIPHERAL, -// //.parent = &clk_in, - .clk.peri.peri_flag = LEVEL_PERI_NORMAL, + .name = "uart1_clk", + .level = LEVEL_PERIPHERAL, +// //.parent = &clk_in, + .clk.peri.peri_flag = LEVEL_PERI_NORMAL, - .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX, + .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX, - //gate - .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, - .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, - .clk.peri.obj.normal.gate.reg_mask = UART1_CLK_GATE, + //gate + .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, + .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, + .clk.peri.obj.normal.gate.reg_mask = UART1_CLK_GATE, #ifdef FH_CLK_GATE_DEFAULT - .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, + .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, #else - .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, + .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, #endif - //div - .clk.peri.obj.normal.div.div_flag = DIV_ENABLE | PRE_DIV_ENABLE, - .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV4, - .clk.peri.obj.normal.div.reg_mask = 0x1f << 8, - .clk.peri.obj.normal.div.sw_div_multi = 1, + //div + .clk.peri.obj.normal.div.div_flag = DIV_ENABLE | PRE_DIV_ENABLE, + .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV4, + .clk.peri.obj.normal.div.reg_mask = 0x1f << 8, + .clk.peri.obj.normal.div.sw_div_multi = 1, #ifdef FH_CLK_DIV_DEFAULT - .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, + .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, #else - .clk.peri.obj.normal.div.sw_div_value = 1, + .clk.peri.obj.normal.div.sw_div_value = 1, #endif - .clk.peri.obj.normal.div.pdiv_value = 10, + .clk.peri.obj.normal.div.pdiv_value = 10, - .update_func = uart1_clk_update, + .update_func = uart1_clk_update, }; @@ -1261,131 +1261,131 @@ static struct fh_clk uart1_clk = { static struct fh_clk pwm_clk = { - .name = "pwm_clk", - .level = LEVEL_PERIPHERAL, -// //.parent = &clk_in, - .clk.peri.peri_flag = LEVEL_PERI_NORMAL, + .name = "pwm_clk", + .level = LEVEL_PERIPHERAL, +// //.parent = &clk_in, + .clk.peri.peri_flag = LEVEL_PERI_NORMAL, - .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX, + .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX, - //gate - .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, - .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, - .clk.peri.obj.normal.gate.reg_mask = PWM_CLK_GATE, + //gate + .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, + .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, + .clk.peri.obj.normal.gate.reg_mask = PWM_CLK_GATE, #ifdef FH_CLK_GATE_DEFAULT - .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, + .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, #else - .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, + .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, #endif - //div - .clk.peri.obj.normal.div.div_flag = DIV_ENABLE | PRE_DIV_ENABLE, - .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV5, - .clk.peri.obj.normal.div.reg_mask = 0x3f << 0, - .clk.peri.obj.normal.div.sw_div_multi = 1, + //div + .clk.peri.obj.normal.div.div_flag = DIV_ENABLE | PRE_DIV_ENABLE, + .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV5, + .clk.peri.obj.normal.div.reg_mask = 0x3f << 0, + .clk.peri.obj.normal.div.sw_div_multi = 1, #ifdef FH_CLK_DIV_DEFAULT - .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, + .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, #else - .clk.peri.obj.normal.div.sw_div_value = 29, + .clk.peri.obj.normal.div.sw_div_value = 29, #endif - .clk.peri.obj.normal.div.pdiv_value = 20, + .clk.peri.obj.normal.div.pdiv_value = 20, - .update_func = pwm_clk_update, + .update_func = pwm_clk_update, }; static struct fh_clk time0_clk = { - .name = "time0_clk", - .level = LEVEL_PERIPHERAL, -// //.parent = &clk_in, - .clk.peri.peri_flag = LEVEL_PERI_NORMAL, + .name = "time0_clk", + .level = LEVEL_PERIPHERAL, +// //.parent = &clk_in, + .clk.peri.peri_flag = LEVEL_PERI_NORMAL, - .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX, - //gate - .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, - .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, - .clk.peri.obj.normal.gate.reg_mask = TMR0_CLK_GATE, + .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX, + //gate + .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, + .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, + .clk.peri.obj.normal.gate.reg_mask = TMR0_CLK_GATE, #ifdef FH_CLK_GATE_DEFAULT - .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, + .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, #else - .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, + .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, #endif - //div - .clk.peri.obj.normal.div.div_flag = DIV_ENABLE | PRE_DIV_ENABLE, - .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV5, - .clk.peri.obj.normal.div.reg_mask = 0x3f << 16, - .clk.peri.obj.normal.div.sw_div_multi = 1, + //div + .clk.peri.obj.normal.div.div_flag = DIV_ENABLE | PRE_DIV_ENABLE, + .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV5, + .clk.peri.obj.normal.div.reg_mask = 0x3f << 16, + .clk.peri.obj.normal.div.sw_div_multi = 1, #ifdef FH_CLK_DIV_DEFAULT - .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, + .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, #else - .clk.peri.obj.normal.div.sw_div_value = 29, + .clk.peri.obj.normal.div.sw_div_value = 29, #endif - .clk.peri.obj.normal.div.pdiv_value = 20, + .clk.peri.obj.normal.div.pdiv_value = 20, - .update_func = time0_clk_update, + .update_func = time0_clk_update, }; static struct fh_clk time1_clk = { - .name = "time1_clk", - .level = LEVEL_PERIPHERAL, -// //.parent = &clk_in, + .name = "time1_clk", + .level = LEVEL_PERIPHERAL, +// //.parent = &clk_in, - .clk.peri.peri_flag = LEVEL_PERI_NORMAL, + .clk.peri.peri_flag = LEVEL_PERI_NORMAL, - .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX, + .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX, - //gate - .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, - .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, - .clk.peri.obj.normal.gate.reg_mask = TMR1_CLK_GATE, + //gate + .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, + .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, + .clk.peri.obj.normal.gate.reg_mask = TMR1_CLK_GATE, #ifdef FH_CLK_GATE_DEFAULT - .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, + .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, #else - .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, + .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, #endif - //div - .clk.peri.obj.normal.div.div_flag = DIV_ENABLE | PRE_DIV_ENABLE, - .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV5, - .clk.peri.obj.normal.div.reg_mask = 0x3f << 24, - .clk.peri.obj.normal.div.sw_div_multi = 1, + //div + .clk.peri.obj.normal.div.div_flag = DIV_ENABLE | PRE_DIV_ENABLE, + .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV5, + .clk.peri.obj.normal.div.reg_mask = 0x3f << 24, + .clk.peri.obj.normal.div.sw_div_multi = 1, #ifdef FH_CLK_DIV_DEFAULT - .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, + .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, #else - .clk.peri.obj.normal.div.sw_div_value = 29, + .clk.peri.obj.normal.div.sw_div_value = 29, #endif - .clk.peri.obj.normal.div.pdiv_value = 20, + .clk.peri.obj.normal.div.pdiv_value = 20, - .update_func = time1_clk_update, + .update_func = time1_clk_update, }; @@ -1393,227 +1393,227 @@ static struct fh_clk time1_clk = { static struct fh_clk sadc_clk = { - .name = "sadc_clk", - .level = LEVEL_PERIPHERAL, -// //.parent = &clk_in, - .clk.peri.peri_flag = LEVEL_PERI_NORMAL, + .name = "sadc_clk", + .level = LEVEL_PERIPHERAL, +// //.parent = &clk_in, + .clk.peri.peri_flag = LEVEL_PERI_NORMAL, - .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX, + .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX, - //gate - .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, - .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, - .clk.peri.obj.normal.gate.reg_mask = SADC_CLK_GATE, + //gate + .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, + .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, + .clk.peri.obj.normal.gate.reg_mask = SADC_CLK_GATE, #ifdef FH_CLK_GATE_DEFAULT - .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, + .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, #else - .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, + .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, #endif - //div - .clk.peri.obj.normal.div.div_flag = PRE_DIV_ENABLE, - .clk.peri.obj.normal.div.sw_div_multi = 1, - .clk.peri.obj.normal.div.pdiv_value = 120, + //div + .clk.peri.obj.normal.div.div_flag = PRE_DIV_ENABLE, + .clk.peri.obj.normal.div.sw_div_multi = 1, + .clk.peri.obj.normal.div.pdiv_value = 120, - .update_func = sadc_clk_update, + .update_func = sadc_clk_update, }; static struct fh_clk sdc0_clk2x = { - .name = "sdc0_clk2x", - .level = LEVEL_PERIPHERAL, -// //.parent = &clk_in, - .clk.peri.peri_flag = LEVEL_PERI_NORMAL, + .name = "sdc0_clk2x", + .level = LEVEL_PERIPHERAL, +// //.parent = &clk_in, + .clk.peri.peri_flag = LEVEL_PERI_NORMAL, - .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX, + .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX, - //gate - .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, + //gate + .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, - .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, - .clk.peri.obj.normal.gate.reg_mask = SDC0_CLK_GATE, + .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, + .clk.peri.obj.normal.gate.reg_mask = SDC0_CLK_GATE, #ifdef FH_CLK_GATE_DEFAULT - .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, + .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, #else - .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, + .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, #endif - //div - .clk.peri.obj.normal.div.div_flag = DIV_ENABLE | PRE_DIV_ENABLE, - .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV3, - .clk.peri.obj.normal.div.reg_mask = 0x0f << 8, - .clk.peri.obj.normal.div.sw_div_multi = 1, + //div + .clk.peri.obj.normal.div.div_flag = DIV_ENABLE | PRE_DIV_ENABLE, + .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV3, + .clk.peri.obj.normal.div.reg_mask = 0x0f << 8, + .clk.peri.obj.normal.div.sw_div_multi = 1, #ifdef FH_CLK_DIV_DEFAULT - .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, + .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, #else - .clk.peri.obj.normal.div.sw_div_value = 5, + .clk.peri.obj.normal.div.sw_div_value = 5, #endif - .clk.peri.obj.normal.div.pdiv_value = 2, + .clk.peri.obj.normal.div.pdiv_value = 2, - .update_func = sdc0_clk2x_update, + .update_func = sdc0_clk2x_update, }; static struct fh_clk sdc0_clk = { - .name = "sdc0_clk", - .level = LEVEL_PERIPHERAL, -// //.parent = &clk_in, - .clk.peri.peri_flag = LEVEL_PERI_SDC, - .clk.peri.obj.sdc.phase_diff = DIFF_SDC_REFCLK_0 | DIFF_REFERENCE, -// .clk.peri.obj.sdc.reg_offset = REG_PMU_CLK_SEL, -// .clk.peri.obj.sdc.reg_mask = 0x0, + .name = "sdc0_clk", + .level = LEVEL_PERIPHERAL, +// //.parent = &clk_in, + .clk.peri.peri_flag = LEVEL_PERI_SDC, + .clk.peri.obj.sdc.phase_diff = DIFF_SDC_REFCLK_0 | DIFF_REFERENCE, +// .clk.peri.obj.sdc.reg_offset = REG_PMU_CLK_SEL, +// .clk.peri.obj.sdc.reg_mask = 0x0, - .update_func = sdc0_clk_update, + .update_func = sdc0_clk_update, }; static struct fh_clk sdc0_clk_out = { - .name = "sdc0_clk_out", - .level = LEVEL_PERIPHERAL, -// //.parent = &clk_in, - .clk.peri.peri_flag = LEVEL_PERI_SDC, - .clk.peri.obj.sdc.phase_diff = DIFF_SDC_REFCLK_0, -// .clk.peri.obj.sdc.reg_offset = REG_PMU_CLK_SEL, -// .clk.peri.obj.sdc.reg_mask = 0x0, - - .update_func = sdc0_clk_out_update, + .name = "sdc0_clk_out", + .level = LEVEL_PERIPHERAL, +// //.parent = &clk_in, + .clk.peri.peri_flag = LEVEL_PERI_SDC, + .clk.peri.obj.sdc.phase_diff = DIFF_SDC_REFCLK_0, +// .clk.peri.obj.sdc.reg_offset = REG_PMU_CLK_SEL, +// .clk.peri.obj.sdc.reg_mask = 0x0, + + .update_func = sdc0_clk_out_update, }; static struct fh_clk sdc0_clk_sample = { - .name = "sdc0_clk_sample", - .level = LEVEL_PERIPHERAL, + .name = "sdc0_clk_sample", + .level = LEVEL_PERIPHERAL, - .clk.peri.peri_flag = LEVEL_PERI_SDC, - .clk.peri.obj.sdc.phase_diff = DIFF_SDC_REFCLK_0, - .clk.peri.obj.sdc.reg_offset = REG_PMU_CLK_SEL, - .clk.peri.obj.sdc.reg_mask = 3<16, + .clk.peri.peri_flag = LEVEL_PERI_SDC, + .clk.peri.obj.sdc.phase_diff = DIFF_SDC_REFCLK_0, + .clk.peri.obj.sdc.reg_offset = REG_PMU_CLK_SEL, + .clk.peri.obj.sdc.reg_mask = 3<16, - .update_func = sdc0_clk_sample_update, + .update_func = sdc0_clk_sample_update, }; static struct fh_clk sdc0_clk_drive = { - .name = "sdc0_clk_drive", - .level = LEVEL_PERIPHERAL, + .name = "sdc0_clk_drive", + .level = LEVEL_PERIPHERAL, - .clk.peri.peri_flag = LEVEL_PERI_SDC, - .clk.peri.obj.sdc.phase_diff = DIFF_SDC_REFCLK_0, - .clk.peri.obj.sdc.reg_offset = REG_PMU_CLK_SEL, - .clk.peri.obj.sdc.reg_mask = 3<20, + .clk.peri.peri_flag = LEVEL_PERI_SDC, + .clk.peri.obj.sdc.phase_diff = DIFF_SDC_REFCLK_0, + .clk.peri.obj.sdc.reg_offset = REG_PMU_CLK_SEL, + .clk.peri.obj.sdc.reg_mask = 3<20, - .update_func = sdc0_clk_drv_update, + .update_func = sdc0_clk_drv_update, }; static struct fh_clk sdc1_clk2x = { - .name = "sdc1_clk2x", - .level = LEVEL_PERIPHERAL, -// //.parent = &clk_in, - .clk.peri.peri_flag = LEVEL_PERI_NORMAL, + .name = "sdc1_clk2x", + .level = LEVEL_PERIPHERAL, +// //.parent = &clk_in, + .clk.peri.peri_flag = LEVEL_PERI_NORMAL, - .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX, + .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX, - //gate - .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, - .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, - .clk.peri.obj.normal.gate.reg_mask = SDC1_CLK_GATE, + //gate + .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, + .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, + .clk.peri.obj.normal.gate.reg_mask = SDC1_CLK_GATE, #ifdef FH_CLK_GATE_DEFAULT - .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, + .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, #else - .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, + .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, #endif - //div - .clk.peri.obj.normal.div.div_flag = DIV_ENABLE | PRE_DIV_ENABLE, - .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV3, - .clk.peri.obj.normal.div.reg_mask = 0x0f << 24, - .clk.peri.obj.normal.div.sw_div_multi = 1, + //div + .clk.peri.obj.normal.div.div_flag = DIV_ENABLE | PRE_DIV_ENABLE, + .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV3, + .clk.peri.obj.normal.div.reg_mask = 0x0f << 24, + .clk.peri.obj.normal.div.sw_div_multi = 1, #ifdef FH_CLK_DIV_DEFAULT - .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, + .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, #else - .clk.peri.obj.normal.div.sw_div_value = 5, + .clk.peri.obj.normal.div.sw_div_value = 5, #endif - .clk.peri.obj.normal.div.pdiv_value = 2, + .clk.peri.obj.normal.div.pdiv_value = 2, - .update_func = sdc1_clk2x_update, + .update_func = sdc1_clk2x_update, }; static struct fh_clk sdc1_clk = { - .name = "sdc1_clk", - .level = LEVEL_PERIPHERAL, -// //.parent = &clk_in, - .clk.peri.peri_flag = LEVEL_PERI_SDC, - .clk.peri.obj.sdc.phase_diff = DIFF_SDC_REFCLK_0 | DIFF_REFERENCE, -// .clk.peri.obj.sdc.reg_offset = REG_PMU_CLK_SEL, -// .clk.peri.obj.sdc.reg_mask = 0x0, - - .update_func = sdc1_clk_update, + .name = "sdc1_clk", + .level = LEVEL_PERIPHERAL, +// //.parent = &clk_in, + .clk.peri.peri_flag = LEVEL_PERI_SDC, + .clk.peri.obj.sdc.phase_diff = DIFF_SDC_REFCLK_0 | DIFF_REFERENCE, +// .clk.peri.obj.sdc.reg_offset = REG_PMU_CLK_SEL, +// .clk.peri.obj.sdc.reg_mask = 0x0, + + .update_func = sdc1_clk_update, }; static struct fh_clk sdc1_clk_out = { - .name = "sdc1_clk_out", - .level = LEVEL_PERIPHERAL, -// //.parent = &clk_in, - .clk.peri.peri_flag = LEVEL_PERI_SDC, - .clk.peri.obj.sdc.phase_diff = DIFF_SDC_REFCLK_0, -// .clk.peri.obj.sdc.reg_offset = REG_PMU_CLK_SEL, -// .clk.peri.obj.sdc.reg_mask = 0x0, - - .update_func = sdc1_clk_out_update, + .name = "sdc1_clk_out", + .level = LEVEL_PERIPHERAL, +// //.parent = &clk_in, + .clk.peri.peri_flag = LEVEL_PERI_SDC, + .clk.peri.obj.sdc.phase_diff = DIFF_SDC_REFCLK_0, +// .clk.peri.obj.sdc.reg_offset = REG_PMU_CLK_SEL, +// .clk.peri.obj.sdc.reg_mask = 0x0, + + .update_func = sdc1_clk_out_update, }; static struct fh_clk sdc1_clk_sample = { - .name = "sdc1_clk_sample", - .level = LEVEL_PERIPHERAL, -// //.parent = &clk_in, - .clk.peri.peri_flag = LEVEL_PERI_SDC, - .clk.peri.obj.sdc.phase_diff = DIFF_SDC_REFCLK_0, - .clk.peri.obj.sdc.reg_offset = REG_PMU_CLK_SEL, - .clk.peri.obj.sdc.reg_mask = 3<8, - - .update_func = sdc1_clk_sample_update, + .name = "sdc1_clk_sample", + .level = LEVEL_PERIPHERAL, +// //.parent = &clk_in, + .clk.peri.peri_flag = LEVEL_PERI_SDC, + .clk.peri.obj.sdc.phase_diff = DIFF_SDC_REFCLK_0, + .clk.peri.obj.sdc.reg_offset = REG_PMU_CLK_SEL, + .clk.peri.obj.sdc.reg_mask = 3<8, + + .update_func = sdc1_clk_sample_update, }; static struct fh_clk sdc1_clk_drive = { - .name = "sdc1_clk_drive", - .level = LEVEL_PERIPHERAL, -// //.parent = &clk_in, - .clk.peri.peri_flag = LEVEL_PERI_SDC, - .clk.peri.obj.sdc.phase_diff = DIFF_SDC_REFCLK_0, - .clk.peri.obj.sdc.reg_offset = REG_PMU_CLK_SEL, - .clk.peri.obj.sdc.reg_mask = 3<12, - - .update_func = sdc1_clk_drv_update, + .name = "sdc1_clk_drive", + .level = LEVEL_PERIPHERAL, +// //.parent = &clk_in, + .clk.peri.peri_flag = LEVEL_PERI_SDC, + .clk.peri.obj.sdc.phase_diff = DIFF_SDC_REFCLK_0, + .clk.peri.obj.sdc.reg_offset = REG_PMU_CLK_SEL, + .clk.peri.obj.sdc.reg_mask = 3<12, + + .update_func = sdc1_clk_drv_update, }; @@ -1621,826 +1621,826 @@ static struct fh_clk sdc1_clk_drive = { static struct fh_clk eth_ref_clk = { - .name = "eth_ref_clk", - .level = LEVEL_PERIPHERAL, -// //.parent = &clk_in, - .clk.peri.peri_flag = LEVEL_PERI_NORMAL, + .name = "eth_ref_clk", + .level = LEVEL_PERIPHERAL, +// //.parent = &clk_in, + .clk.peri.peri_flag = LEVEL_PERI_NORMAL, - .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX, + .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX, - //gate - .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, - .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, - .clk.peri.obj.normal.gate.reg_mask = ETH_REF_CLK_GATE, + //gate + .clk.peri.obj.normal.gate.gate_flag = HAS_GATE, + .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE, + .clk.peri.obj.normal.gate.reg_mask = ETH_REF_CLK_GATE, #ifdef FH_CLK_GATE_DEFAULT - .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, + .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE, #else - .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, + .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE, #endif - //div - .clk.peri.obj.normal.div.div_flag = DIV_ENABLE | PRE_DIV_ENABLE, - .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV6, - .clk.peri.obj.normal.div.reg_mask = 0x0f << 24, - .clk.peri.obj.normal.div.sw_div_multi = 1, + //div + .clk.peri.obj.normal.div.div_flag = DIV_ENABLE | PRE_DIV_ENABLE, + .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV6, + .clk.peri.obj.normal.div.reg_mask = 0x0f << 24, + .clk.peri.obj.normal.div.sw_div_multi = 1, #ifdef FH_CLK_DIV_DEFAULT - .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, + .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, #else - .clk.peri.obj.normal.div.sw_div_value = 5, + .clk.peri.obj.normal.div.sw_div_value = 5, #endif - .clk.peri.obj.normal.div.pdiv_value = 2, + .clk.peri.obj.normal.div.pdiv_value = 2, - .update_func = eth_ref_clk_update, + .update_func = eth_ref_clk_update, }; static struct fh_clk wdt_clk = { - .name = "wdt_clk", - .level = LEVEL_PERIPHERAL, -// //.parent = &clk_in, - .clk.peri.peri_flag = LEVEL_PERI_NORMAL, - .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX, + .name = "wdt_clk", + .level = LEVEL_PERIPHERAL, +// //.parent = &clk_in, + .clk.peri.peri_flag = LEVEL_PERI_NORMAL, + .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX, - //gate - .clk.peri.obj.normal.gate.gate_flag = HAS_NO_GATE, + //gate + .clk.peri.obj.normal.gate.gate_flag = HAS_NO_GATE, - //div - .clk.peri.obj.normal.div.div_flag = DIV_ENABLE, - .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV5, - .clk.peri.obj.normal.div.reg_mask = 0x3f << 8, - .clk.peri.obj.normal.div.sw_div_multi = 1, + //div + .clk.peri.obj.normal.div.div_flag = DIV_ENABLE, + .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV5, + .clk.peri.obj.normal.div.reg_mask = 0x3f << 8, + .clk.peri.obj.normal.div.sw_div_multi = 1, #ifdef FH_CLK_DIV_DEFAULT - .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, + .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE, #else - .clk.peri.obj.normal.div.sw_div_value = 29, + .clk.peri.obj.normal.div.sw_div_value = 29, #endif - .update_func = wdt_clk_update, + .update_func = wdt_clk_update, }; struct fh_clk *fh_clk_array[] = { - &clk_in, - &cis_pclk, - &pll0, - &pll1, - &ddr_clk_normal, - &ddr_clk_div2, - &cpu_fclk, - &cpu_aclk, - &cpu_hclk, - &cpu_pclk, - &isp_aclk, - &vcu_clk, - &vou_clk, - &mipi_p32_clk, - &cis_clk_out, - &pts_clk, - &mipi_pix_clk, - &pix_clk, - - //pll1 - &sdc0_clk2x, - &sdc0_clk, - &sdc0_clk_out, - &sdc0_clk_sample, - &sdc0_clk_drive, - - &sdc1_clk2x, - &sdc1_clk, - &sdc1_clk_out, - &sdc1_clk_sample, - &sdc1_clk_drive, - - - &spi0_clk, - &spi1_clk, - &mipi_dphy_clk20m, - &i2c0_clk, - &i2c1_clk, - &uart0_clk, - &uart1_clk, - &pwm_clk, - &time0_clk, - &time1_clk, - &sadc_clk, - ð_ref_clk, - - &wdt_clk, + &clk_in, + &cis_pclk, + &pll0, + &pll1, + &ddr_clk_normal, + &ddr_clk_div2, + &cpu_fclk, + &cpu_aclk, + &cpu_hclk, + &cpu_pclk, + &isp_aclk, + &vcu_clk, + &vou_clk, + &mipi_p32_clk, + &cis_clk_out, + &pts_clk, + &mipi_pix_clk, + &pix_clk, + + //pll1 + &sdc0_clk2x, + &sdc0_clk, + &sdc0_clk_out, + &sdc0_clk_sample, + &sdc0_clk_drive, + + &sdc1_clk2x, + &sdc1_clk, + &sdc1_clk_out, + &sdc1_clk_sample, + &sdc1_clk_drive, + + + &spi0_clk, + &spi1_clk, + &mipi_dphy_clk20m, + &i2c0_clk, + &i2c1_clk, + &uart0_clk, + &uart1_clk, + &pwm_clk, + &time0_clk, + &time1_clk, + &sadc_clk, + ð_ref_clk, + + &wdt_clk, }; static inline rt_int32_t wrap_read_reg(rt_uint32_t offset, rt_uint32_t mask, - rt_uint32_t *value) + rt_uint32_t *value) { - rt_uint32_t temp_v, temp_shift; - - /* if(fh_pmu_status() == PMU_STATUS_CLOSE) - return -1;*/ - temp_v = FH_TIMER_READL(offset); - temp_v &= mask; - temp_shift = __rt_ffs(mask); - temp_v = temp_v >> (temp_shift - 1); - *value = temp_v; - return 0; + rt_uint32_t temp_v, temp_shift; + + /* if(fh_pmu_status() == PMU_STATUS_CLOSE) + return -1;*/ + temp_v = FH_TIMER_READL(offset); + temp_v &= mask; + temp_shift = __rt_ffs(mask); + temp_v = temp_v >> (temp_shift - 1); + *value = temp_v; + return 0; } static inline rt_int32_t wrap_write_reg(rt_uint32_t offset, rt_uint32_t mask, - rt_uint32_t value) + rt_uint32_t value) { - rt_uint32_t temp_v, temp_shift; - - /* - if(fh_pmu_status() == PMU_STATUS_CLOSE) - return -1; - */ - - temp_v = FH_TIMER_READL(offset); - temp_v &= ~mask; - temp_shift = __rt_ffs(mask); - temp_v |= value << (temp_shift - 1); - FH_TIMER_WRITEL(offset, temp_v); - return 0; + rt_uint32_t temp_v, temp_shift; + + /* + if(fh_pmu_status() == PMU_STATUS_CLOSE) + return -1; + */ + + temp_v = FH_TIMER_READL(offset); + temp_v &= ~mask; + temp_shift = __rt_ffs(mask); + temp_v |= value << (temp_shift - 1); + FH_TIMER_WRITEL(offset, temp_v); + return 0; } rt_int32_t check_pix_clk_source(rt_uint32_t offset, rt_uint32_t mask, - rt_uint32_t *value) + rt_uint32_t *value) { - rt_uint32_t mux0; - rt_int32_t ret; - ret = wrap_read_reg(offset, mask, &mux0); + rt_uint32_t mux0; + rt_int32_t ret; + ret = wrap_read_reg(offset, mask, &mux0); - if (ret != 0) { - return ret; - } + if (ret != 0) { + return ret; + } - *value = mux0; - return 0; + *value = mux0; + return 0; } rt_int32_t check_xtal_pll0(rt_uint32_t offset, rt_uint32_t mask, - rt_uint32_t *value) + rt_uint32_t *value) { - rt_uint32_t mux0; - rt_int32_t ret; - ret = wrap_read_reg(offset, mask, &mux0); - - if (ret != 0) { - return ret; - } - if (mux0 == MUX0_PLL0_CLK) - *value = MUX0_PLL0_CLK; - else - *value = MUX0_XTAL_CLK; - - return 0; + rt_uint32_t mux0; + rt_int32_t ret; + ret = wrap_read_reg(offset, mask, &mux0); + + if (ret != 0) { + return ret; + } + if (mux0 == MUX0_PLL0_CLK) + *value = MUX0_PLL0_CLK; + else + *value = MUX0_XTAL_CLK; + + return 0; } void cal_pll0_prediv(rt_uint32_t *div_flag, rt_uint32_t *pre_value) { - if (!(*div_flag & PRE_DIV_CAL_ALREADY)) { - //before has got the prediv value.. - if (*div_flag & PRE_DIV_ENABLE) { + if (!(*div_flag & PRE_DIV_CAL_ALREADY)) { + //before has got the prediv value.. + if (*div_flag & PRE_DIV_ENABLE) { - *pre_value *= 2; - } else { - *pre_value = 2; - } - *div_flag |= PRE_DIV_ENABLE | PRE_DIV_CAL_ALREADY; - } + *pre_value *= 2; + } else { + *pre_value = 2; + } + *div_flag |= PRE_DIV_ENABLE | PRE_DIV_CAL_ALREADY; + } } rt_int32_t sw_div_process(rt_uint32_t div_flag, rt_uint32_t offset, - rt_uint32_t mask, rt_uint32_t *div_value) + rt_uint32_t mask, rt_uint32_t *div_value) { - //rt_kprintf("----------div go----------\n"); - rt_uint32_t div; - rt_int32_t ret; - if (div_flag & DIV_ENABLE) { - ret = wrap_read_reg(offset, mask, &div); - if (ret != 0) { - return ret; - } + //rt_kprintf("----------div go----------\n"); + rt_uint32_t div; + rt_int32_t ret; + if (div_flag & DIV_ENABLE) { + ret = wrap_read_reg(offset, mask, &div); + if (ret != 0) { + return ret; + } // -// rt_kprintf("hw value is %x\n",div); -// rt_kprintf("sw value is %x\n",div_value); +// rt_kprintf("hw value is %x\n",div); +// rt_kprintf("sw value is %x\n",div_value); // -// rt_kprintf("offset is %x,value :%x\n",offset + 0xf0000000,*(rt_uint32_t*)(offset + 0xf0000000)); -// rt_kprintf("mask is %x\n",mask); - - //if use the hw default value.... - - if (*div_value == FH_CLK_DIV_DEFAULT_VALUE) { - *div_value = div; - return 0; - } - - if (div != *div_value) { - ret = wrap_write_reg(offset, mask, *div_value); - if (ret != 0) { - return ret; - } - } - } - //rt_kprintf("----------div done----------\n"); - return 0; - //*div_flag |= PRE_DIV_ENABLE; +// rt_kprintf("offset is %x,value :%x\n",offset + 0xf0000000,*(rt_uint32_t*)(offset + 0xf0000000)); +// rt_kprintf("mask is %x\n",mask); + + //if use the hw default value.... + + if (*div_value == FH_CLK_DIV_DEFAULT_VALUE) { + *div_value = div; + return 0; + } + + if (div != *div_value) { + ret = wrap_write_reg(offset, mask, *div_value); + if (ret != 0) { + return ret; + } + } + } + //rt_kprintf("----------div done----------\n"); + return 0; + //*div_flag |= PRE_DIV_ENABLE; } void cal_baud_hz(rt_uint32_t clk_in, rt_uint32_t div_flag, rt_uint32_t pre_div, - rt_uint32_t div, rt_uint32_t div_multi, rt_uint32_t *baud_out) + rt_uint32_t div, rt_uint32_t div_multi, rt_uint32_t *baud_out) { - //div += 1; - if (div_flag & PRE_DIV_ENABLE) { - *baud_out = (clk_in / pre_div); - } else { - *baud_out = clk_in; - } + //div += 1; + if (div_flag & PRE_DIV_ENABLE) { + *baud_out = (clk_in / pre_div); + } else { + *baud_out = clk_in; + } - if (div_flag & DIV_ENABLE) { - *baud_out /= ((div + 1) * div_multi); - } + if (div_flag & DIV_ENABLE) { + *baud_out /= ((div + 1) * div_multi); + } } void cal_baud_div(rt_uint32_t clk_in, rt_uint32_t div_flag, rt_uint32_t pre_div, - rt_uint32_t *div, rt_uint32_t div_multi, rt_uint32_t baud_out) + rt_uint32_t *div, rt_uint32_t div_multi, rt_uint32_t baud_out) { - //div += 1; - rt_uint32_t temp_baud_hz, temp_baud_div; - - if (div_flag & DIV_ENABLE) { - if (div_flag & PRE_DIV_ENABLE) { - temp_baud_hz = (clk_in / pre_div); - } else { - temp_baud_hz = clk_in; - } - temp_baud_div = temp_baud_hz / baud_out; - *div = temp_baud_div - 1; - } + //div += 1; + rt_uint32_t temp_baud_hz, temp_baud_div; + + if (div_flag & DIV_ENABLE) { + if (div_flag & PRE_DIV_ENABLE) { + temp_baud_hz = (clk_in / pre_div); + } else { + temp_baud_hz = clk_in; + } + temp_baud_div = temp_baud_hz / baud_out; + *div = temp_baud_div - 1; + } } rt_int32_t process_gate(rt_uint32_t gate_flag, rt_uint32_t reg_offset, - rt_uint32_t reg_mask, rt_uint32_t *sw_status, - rt_uint32_t *pclk_status) + rt_uint32_t reg_mask, rt_uint32_t *sw_status, + rt_uint32_t *pclk_status) { - //rt_kprintf("----------gate go----------\n"); - rt_uint32_t hw_gate; - rt_int32_t ret; - if (gate_flag == HAS_GATE) { - ret = wrap_read_reg(reg_offset, reg_mask, &hw_gate); - if (ret != 0) { - return ret; - } - - if (*sw_status == FH_CLK_GATE_DEFAULT_VALUE) { - *sw_status = hw_gate; - *pclk_status = *sw_status; - return 0; - } - -// rt_kprintf("gate hw is :%x\n",hw_gate); -// rt_kprintf("gate sw is :%x\n",sw_status); - if (hw_gate != *sw_status) { - //update the gate.. -// rt_kprintf("gate reg offset is :%x\n",reg_offset); -// rt_kprintf("gate reg mask is :%x\n",reg_mask); -// rt_kprintf("gate reg write is :%x\n",sw_status); - ret = wrap_write_reg(reg_offset, reg_mask, *sw_status); - if (ret != 0) { - return ret; - } - } - - *pclk_status = *sw_status; - } - - else { - *pclk_status |= CLK_HAS_NO_GATE; - } - //rt_kprintf("---------gate done---------\n"); - return 0; + //rt_kprintf("----------gate go----------\n"); + rt_uint32_t hw_gate; + rt_int32_t ret; + if (gate_flag == HAS_GATE) { + ret = wrap_read_reg(reg_offset, reg_mask, &hw_gate); + if (ret != 0) { + return ret; + } + + if (*sw_status == FH_CLK_GATE_DEFAULT_VALUE) { + *sw_status = hw_gate; + *pclk_status = *sw_status; + return 0; + } + +// rt_kprintf("gate hw is :%x\n",hw_gate); +// rt_kprintf("gate sw is :%x\n",sw_status); + if (hw_gate != *sw_status) { + //update the gate.. +// rt_kprintf("gate reg offset is :%x\n",reg_offset); +// rt_kprintf("gate reg mask is :%x\n",reg_mask); +// rt_kprintf("gate reg write is :%x\n",sw_status); + ret = wrap_write_reg(reg_offset, reg_mask, *sw_status); + if (ret != 0) { + return ret; + } + } + + *pclk_status = *sw_status; + } + + else { + *pclk_status |= CLK_HAS_NO_GATE; + } + //rt_kprintf("---------gate done---------\n"); + return 0; } void clk_handle(struct fh_clk* p_clk, struct fh_clk *parent) { - //rt_uint32_t div; - //rt_uint32_t sw_gate; - rt_uint32_t phase; - rt_int32_t ret; - p_clk->parent = parent; -// switch - //fh_clk_debug(p_clk,"----parent----\t ----clk out rate----\n "); - if (p_clk->parent) - //rt_kprintf("%-8.*s 0x%02x", RT_NAME_MAX, thread->name, thread->current_priority); - fh_clk_debug(p_clk, "parent:'%s'\n", p_clk->parent->name); - else - fh_clk_debug(p_clk, "'root node'\n"); - - switch (p_clk->level) { - - case LEVEL_CRYSTAL: - //fh_clk_debug(p_clk,"clk out:%d\n",p_clk->clk_out_rate); - break; - case LEVEL_PLL: - //fh_clk_debug(p_clk,"%d\n",p_clk->clk_out_rate); - break; - case LEVEL_PERIPHERAL: - - switch (p_clk->clk.peri.peri_flag) { - - case LEVEL_PERI_NORMAL: - //div = p_clk->clk.peri.obj.normal.div.sw_div_value; - ret = - sw_div_process( - p_clk->clk.peri.obj.normal.div.div_flag, - p_clk->clk.peri.obj.normal.div.reg_offset, - p_clk->clk.peri.obj.normal.div.reg_mask, - &p_clk->clk.peri.obj.normal.div.sw_div_value); - - if (ret != 0) { - fh_clk_err(p_clk, - "div process failed.error no:%x\n", - ret); - break; - } - - //fh_clk_debug(p_clk,"hw div is %d\n",p_clk->clk.peri.obj.ddr.div.hw_div_value); -// fh_clk_debug(p_clk,"sw div is %d\n",p_clk->clk.peri.obj.normal.div.sw_div_value); -// fh_clk_debug(p_clk,"pre div is %d\n",p_clk->clk.peri.obj.normal.div.pdiv_value); -// fh_clk_debug(p_clk,"clk in is %d\n",p_clk->parent->clk_out_rate); -// fh_clk_debug(p_clk,"peri flag is %x\n",p_clk->clk.peri.obj.normal.div.div_flag); - //hw will self add 1.. - - cal_baud_hz(p_clk->parent->clk_out_rate, - p_clk->clk.peri.obj.normal.div.div_flag, - p_clk->clk.peri.obj.normal.div.pdiv_value, - p_clk->clk.peri.obj.normal.div.sw_div_value, - p_clk->clk.peri.obj.normal.div.sw_div_multi, - &p_clk->clk_out_rate); - - //fh_clk_debug_no_handle("%d\n",p_clk->clk_out_rate); - //fix the gate.. - //sw_gate = p_clk->clk.peri.obj.normal.gate.sw_status; - ret = - process_gate( - p_clk->clk.peri.obj.normal.gate.gate_flag, - p_clk->clk.peri.obj.normal.gate.reg_offset, - p_clk->clk.peri.obj.normal.gate.reg_mask, - &p_clk->clk.peri.obj.normal.gate.sw_status, - &p_clk->gate); - - if (ret != 0) { - fh_clk_err(p_clk, - "gate process failed.error no:%x\n", - ret); - break; - } - - break; - case LEVEL_PERI_DDR: - //rt_uint32_t mux0,mux1; - //div = p_clk->clk.peri.obj.ddr.div.sw_div_value; - - ret = - sw_div_process( - p_clk->clk.peri.obj.ddr.div.div_flag, - p_clk->clk.peri.obj.ddr.div.reg_offset, - p_clk->clk.peri.obj.ddr.div.reg_mask, - &p_clk->clk.peri.obj.ddr.div.sw_div_value); - - if (ret != 0) { - fh_clk_err(p_clk, - "div process failed.error no:%x\n", - ret); - break; - } - -// fh_clk_debug(p_clk,"sw div is %d\n",p_clk->clk.peri.obj.ddr.div.sw_div_value); -// fh_clk_debug(p_clk,"pre div is %d\n",p_clk->clk.peri.obj.ddr.div.pdiv_value); -// fh_clk_debug(p_clk,"clk in is %d\n",p_clk->parent->clk_out_rate); -// fh_clk_debug(p_clk,"peri flag is %x\n",p_clk->clk.peri.obj.ddr.div.div_flag); - - cal_baud_hz(p_clk->parent->clk_out_rate, - p_clk->clk.peri.obj.ddr.div.div_flag, - p_clk->clk.peri.obj.ddr.div.pdiv_value, - p_clk->clk.peri.obj.ddr.div.sw_div_value, - p_clk->clk.peri.obj.ddr.div.sw_div_multi, - &p_clk->clk_out_rate); - - //fh_clk_debug_no_handle("%d\n",p_clk->clk_out_rate); - //fix the gate.. - //fh_clk_debug(p_clk,"gate reg add is:%x\t mask is:%x\n",p_clk->clk.peri.obj.ddr.gate.reg_offset,p_clk->clk.peri.obj.ddr.gate.reg_mask); - //sw_gate = p_clk->clk.peri.obj.ddr.gate.sw_status; - - ret = process_gate( - p_clk->clk.peri.obj.ddr.gate.gate_flag, - p_clk->clk.peri.obj.ddr.gate.reg_offset, - p_clk->clk.peri.obj.ddr.gate.reg_mask, - &p_clk->clk.peri.obj.ddr.gate.sw_status, - &p_clk->gate); - - if (ret != 0) { - fh_clk_err(p_clk, - "gate process failed.error no:%x\n", - ret); - break; - } - - break; - case LEVEL_PERI_SDC: - //just need to handle the phase.... - p_clk->clk_out_rate = p_clk->parent->clk_out_rate; - if (p_clk->clk.peri.obj.sdc.phase_diff & DIFF_REFERENCE) { - //fh_clk_debug(p_clk,"this is the reference..no need to process..\n"); - break; - } - - //baud ... - - //phase.. - //fh_clk_debug_no_handle("%d\n",p_clk->clk_out_rate); - //hw status.. - ret = wrap_read_reg(p_clk->clk.peri.obj.sdc.reg_offset, - p_clk->clk.peri.obj.sdc.reg_mask, - &phase); - - if (ret != 0) { - fh_clk_err(p_clk, - "read pmu failed.error no:%x\n", - ret); - break; - } - -// fh_clk_debug(p_clk,"hw phase is :%x\n",phase); -// fh_clk_debug(p_clk,"sw phase is :%x\n",p_clk->clk.peri.obj.sdc.phase_diff); - if (phase != p_clk->clk.peri.obj.sdc.phase_diff) { - //update the hw para.. - ret = - wrap_write_reg( - p_clk->clk.peri.obj.sdc.reg_offset, - p_clk->clk.peri.obj.sdc.reg_mask, - p_clk->clk.peri.obj.sdc.phase_diff); - if (ret != 0) { - fh_clk_err(p_clk, - "write pmu failed.error no:%x\n", - ret); - break; - } - } - - break; - case LEVEL_PERI_GMAC: - break; - default: - break; - - } - } - - fh_clk_debug(p_clk, "clk out:%d\n", p_clk->clk_out_rate); + //rt_uint32_t div; + //rt_uint32_t sw_gate; + rt_uint32_t phase; + rt_int32_t ret; + p_clk->parent = parent; +// switch + //fh_clk_debug(p_clk,"----parent----\t ----clk out rate----\n "); + if (p_clk->parent) + //rt_kprintf("%-8.*s 0x%02x", RT_NAME_MAX, thread->name, thread->current_priority); + fh_clk_debug(p_clk, "parent:'%s'\n", p_clk->parent->name); + else + fh_clk_debug(p_clk, "'root node'\n"); + + switch (p_clk->level) { + + case LEVEL_CRYSTAL: + //fh_clk_debug(p_clk,"clk out:%d\n",p_clk->clk_out_rate); + break; + case LEVEL_PLL: + //fh_clk_debug(p_clk,"%d\n",p_clk->clk_out_rate); + break; + case LEVEL_PERIPHERAL: + + switch (p_clk->clk.peri.peri_flag) { + + case LEVEL_PERI_NORMAL: + //div = p_clk->clk.peri.obj.normal.div.sw_div_value; + ret = + sw_div_process( + p_clk->clk.peri.obj.normal.div.div_flag, + p_clk->clk.peri.obj.normal.div.reg_offset, + p_clk->clk.peri.obj.normal.div.reg_mask, + &p_clk->clk.peri.obj.normal.div.sw_div_value); + + if (ret != 0) { + fh_clk_err(p_clk, + "div process failed.error no:%x\n", + ret); + break; + } + + //fh_clk_debug(p_clk,"hw div is %d\n",p_clk->clk.peri.obj.ddr.div.hw_div_value); +// fh_clk_debug(p_clk,"sw div is %d\n",p_clk->clk.peri.obj.normal.div.sw_div_value); +// fh_clk_debug(p_clk,"pre div is %d\n",p_clk->clk.peri.obj.normal.div.pdiv_value); +// fh_clk_debug(p_clk,"clk in is %d\n",p_clk->parent->clk_out_rate); +// fh_clk_debug(p_clk,"peri flag is %x\n",p_clk->clk.peri.obj.normal.div.div_flag); + //hw will self add 1.. + + cal_baud_hz(p_clk->parent->clk_out_rate, + p_clk->clk.peri.obj.normal.div.div_flag, + p_clk->clk.peri.obj.normal.div.pdiv_value, + p_clk->clk.peri.obj.normal.div.sw_div_value, + p_clk->clk.peri.obj.normal.div.sw_div_multi, + &p_clk->clk_out_rate); + + //fh_clk_debug_no_handle("%d\n",p_clk->clk_out_rate); + //fix the gate.. + //sw_gate = p_clk->clk.peri.obj.normal.gate.sw_status; + ret = + process_gate( + p_clk->clk.peri.obj.normal.gate.gate_flag, + p_clk->clk.peri.obj.normal.gate.reg_offset, + p_clk->clk.peri.obj.normal.gate.reg_mask, + &p_clk->clk.peri.obj.normal.gate.sw_status, + &p_clk->gate); + + if (ret != 0) { + fh_clk_err(p_clk, + "gate process failed.error no:%x\n", + ret); + break; + } + + break; + case LEVEL_PERI_DDR: + //rt_uint32_t mux0,mux1; + //div = p_clk->clk.peri.obj.ddr.div.sw_div_value; + + ret = + sw_div_process( + p_clk->clk.peri.obj.ddr.div.div_flag, + p_clk->clk.peri.obj.ddr.div.reg_offset, + p_clk->clk.peri.obj.ddr.div.reg_mask, + &p_clk->clk.peri.obj.ddr.div.sw_div_value); + + if (ret != 0) { + fh_clk_err(p_clk, + "div process failed.error no:%x\n", + ret); + break; + } + +// fh_clk_debug(p_clk,"sw div is %d\n",p_clk->clk.peri.obj.ddr.div.sw_div_value); +// fh_clk_debug(p_clk,"pre div is %d\n",p_clk->clk.peri.obj.ddr.div.pdiv_value); +// fh_clk_debug(p_clk,"clk in is %d\n",p_clk->parent->clk_out_rate); +// fh_clk_debug(p_clk,"peri flag is %x\n",p_clk->clk.peri.obj.ddr.div.div_flag); + + cal_baud_hz(p_clk->parent->clk_out_rate, + p_clk->clk.peri.obj.ddr.div.div_flag, + p_clk->clk.peri.obj.ddr.div.pdiv_value, + p_clk->clk.peri.obj.ddr.div.sw_div_value, + p_clk->clk.peri.obj.ddr.div.sw_div_multi, + &p_clk->clk_out_rate); + + //fh_clk_debug_no_handle("%d\n",p_clk->clk_out_rate); + //fix the gate.. + //fh_clk_debug(p_clk,"gate reg add is:%x\t mask is:%x\n",p_clk->clk.peri.obj.ddr.gate.reg_offset,p_clk->clk.peri.obj.ddr.gate.reg_mask); + //sw_gate = p_clk->clk.peri.obj.ddr.gate.sw_status; + + ret = process_gate( + p_clk->clk.peri.obj.ddr.gate.gate_flag, + p_clk->clk.peri.obj.ddr.gate.reg_offset, + p_clk->clk.peri.obj.ddr.gate.reg_mask, + &p_clk->clk.peri.obj.ddr.gate.sw_status, + &p_clk->gate); + + if (ret != 0) { + fh_clk_err(p_clk, + "gate process failed.error no:%x\n", + ret); + break; + } + + break; + case LEVEL_PERI_SDC: + //just need to handle the phase.... + p_clk->clk_out_rate = p_clk->parent->clk_out_rate; + if (p_clk->clk.peri.obj.sdc.phase_diff & DIFF_REFERENCE) { + //fh_clk_debug(p_clk,"this is the reference..no need to process..\n"); + break; + } + + //baud ... + + //phase.. + //fh_clk_debug_no_handle("%d\n",p_clk->clk_out_rate); + //hw status.. + ret = wrap_read_reg(p_clk->clk.peri.obj.sdc.reg_offset, + p_clk->clk.peri.obj.sdc.reg_mask, + &phase); + + if (ret != 0) { + fh_clk_err(p_clk, + "read pmu failed.error no:%x\n", + ret); + break; + } + +// fh_clk_debug(p_clk,"hw phase is :%x\n",phase); +// fh_clk_debug(p_clk,"sw phase is :%x\n",p_clk->clk.peri.obj.sdc.phase_diff); + if (phase != p_clk->clk.peri.obj.sdc.phase_diff) { + //update the hw para.. + ret = + wrap_write_reg( + p_clk->clk.peri.obj.sdc.reg_offset, + p_clk->clk.peri.obj.sdc.reg_mask, + p_clk->clk.peri.obj.sdc.phase_diff); + if (ret != 0) { + fh_clk_err(p_clk, + "write pmu failed.error no:%x\n", + ret); + break; + } + } + + break; + case LEVEL_PERI_GMAC: + break; + default: + break; + + } + } + + fh_clk_debug(p_clk, "clk out:%d\n", p_clk->clk_out_rate); } // void clk_in_update(struct fh_clk* p_clk) { - clk_handle(p_clk, RT_NULL); + clk_handle(p_clk, RT_NULL); } void cis_pclk_update(struct fh_clk* p_clk) { - clk_handle(p_clk, RT_NULL); + clk_handle(p_clk, RT_NULL); } void pll1_clk_update(struct fh_clk* p_clk) { - clk_handle(p_clk, &clk_in); + clk_handle(p_clk, &clk_in); } void pll0_clk_update(struct fh_clk* p_clk) { - clk_handle(p_clk, &clk_in); + clk_handle(p_clk, &clk_in); } void ddr_clk_update(struct fh_clk* p_clk) { - //check if pll0 or pll1 - rt_uint32_t mux0, mux1; - rt_int32_t ret; - struct fh_clk* parent; - //1 step: fix the parent.. - ret = wrap_read_reg(p_clk->clk.peri.obj.ddr.mux[1].reg_offset, - p_clk->clk.peri.obj.ddr.mux[1].reg_mask, &mux1); - if (ret != 0) { - fh_clk_err(p_clk, "read pmu failed.error no:%x\n", ret); - return; - } - - if (mux1 == MUX1_PLL0_CLK) { - ret = check_xtal_pll0(p_clk->clk.peri.obj.ddr.mux[0].reg_offset, - p_clk->clk.peri.obj.ddr.mux[0].reg_mask, &mux0); - if (ret != 0) { - fh_clk_err(p_clk, "read pmu failed.error no:%x\n", ret); - return; - } - if (mux0 == MUX0_PLL0_CLK) { - //ddr normal parent is pll0 - parent = &pll0; - } else { - //ddr normal parent is xtal - parent = &clk_in; - } - } else { - //ddr normal parent is pll1 - parent = &pll1; - } - p_clk->clk.peri.obj.ddr.mux[0].mux_flag = HAS_MUX; - p_clk->clk.peri.obj.ddr.mux[1].mux_flag = HAS_MUX; - clk_handle(p_clk, parent); + //check if pll0 or pll1 + rt_uint32_t mux0, mux1; + rt_int32_t ret; + struct fh_clk* parent; + //1 step: fix the parent.. + ret = wrap_read_reg(p_clk->clk.peri.obj.ddr.mux[1].reg_offset, + p_clk->clk.peri.obj.ddr.mux[1].reg_mask, &mux1); + if (ret != 0) { + fh_clk_err(p_clk, "read pmu failed.error no:%x\n", ret); + return; + } + + if (mux1 == MUX1_PLL0_CLK) { + ret = check_xtal_pll0(p_clk->clk.peri.obj.ddr.mux[0].reg_offset, + p_clk->clk.peri.obj.ddr.mux[0].reg_mask, &mux0); + if (ret != 0) { + fh_clk_err(p_clk, "read pmu failed.error no:%x\n", ret); + return; + } + if (mux0 == MUX0_PLL0_CLK) { + //ddr normal parent is pll0 + parent = &pll0; + } else { + //ddr normal parent is xtal + parent = &clk_in; + } + } else { + //ddr normal parent is pll1 + parent = &pll1; + } + p_clk->clk.peri.obj.ddr.mux[0].mux_flag = HAS_MUX; + p_clk->clk.peri.obj.ddr.mux[1].mux_flag = HAS_MUX; + clk_handle(p_clk, parent); } void fclk_update(struct fh_clk* p_clk) { - //check if pll0 or xtal - rt_uint32_t mux0; - rt_int32_t ret; - struct fh_clk* parent; //1 step: fix the parent.. - - //mux0 = check_xtal_pll0(p_clk->clk.peri.obj.ddr.mux[0].reg_offset,p_clk->clk.peri.obj.ddr.mux[0].reg_mask); - ret = check_xtal_pll0(p_clk->clk.peri.obj.normal.mux.reg_offset, - p_clk->clk.peri.obj.normal.mux.reg_mask, &mux0); - if (ret != 0) { - fh_clk_err(p_clk, "read pmu failed.error no:%x\n", ret); - return; - } - - //fh_clk_debug(p_clk,"mux0 wrap value is %x\n",mux0); - if (mux0 == MUX0_PLL0_CLK) { - //ddr normal parent is pll0 - parent = &pll0; - } else { - //ddr normal parent is xtal - parent = &clk_in; - } - p_clk->clk.peri.obj.normal.mux.mux_flag = HAS_MUX; - //2 step:fix the div... - if (mux0 == MUX0_PLL0_CLK) { - //cal_pll0_prediv(&p_clk->clk.peri.obj.ddr.div.div_flag,&p_clk->clk.peri.obj.ddr.div.pdiv_value); - cal_pll0_prediv(&p_clk->clk.peri.obj.normal.div.div_flag, - &p_clk->clk.peri.obj.normal.div.pdiv_value); - } - clk_handle(p_clk, parent); + //check if pll0 or xtal + rt_uint32_t mux0; + rt_int32_t ret; + struct fh_clk* parent; //1 step: fix the parent.. + + //mux0 = check_xtal_pll0(p_clk->clk.peri.obj.ddr.mux[0].reg_offset,p_clk->clk.peri.obj.ddr.mux[0].reg_mask); + ret = check_xtal_pll0(p_clk->clk.peri.obj.normal.mux.reg_offset, + p_clk->clk.peri.obj.normal.mux.reg_mask, &mux0); + if (ret != 0) { + fh_clk_err(p_clk, "read pmu failed.error no:%x\n", ret); + return; + } + + //fh_clk_debug(p_clk,"mux0 wrap value is %x\n",mux0); + if (mux0 == MUX0_PLL0_CLK) { + //ddr normal parent is pll0 + parent = &pll0; + } else { + //ddr normal parent is xtal + parent = &clk_in; + } + p_clk->clk.peri.obj.normal.mux.mux_flag = HAS_MUX; + //2 step:fix the div... + if (mux0 == MUX0_PLL0_CLK) { + //cal_pll0_prediv(&p_clk->clk.peri.obj.ddr.div.div_flag,&p_clk->clk.peri.obj.ddr.div.pdiv_value); + cal_pll0_prediv(&p_clk->clk.peri.obj.normal.div.div_flag, + &p_clk->clk.peri.obj.normal.div.pdiv_value); + } + clk_handle(p_clk, parent); } void pix_update(struct fh_clk* p_clk) { - //check if pll0 or xtal - rt_uint32_t mux0; - rt_int32_t ret; - struct fh_clk* parent; //1 step: fix the parent.. + //check if pll0 or xtal + rt_uint32_t mux0; + rt_int32_t ret; + struct fh_clk* parent; //1 step: fix the parent.. #if(1) - //mux0 = check_xtal_pll0(p_clk->clk.peri.obj.ddr.mux[0].reg_offset,p_clk->clk.peri.obj.ddr.mux[0].reg_mask); - ret = check_pix_clk_source(p_clk->clk.peri.obj.normal.mux.reg_offset, - p_clk->clk.peri.obj.normal.mux.reg_mask, &mux0); - if (ret != 0) { - fh_clk_err(p_clk, "read pmu failed.error no:%x\n", ret); - return; - } -//#define CIS_PIX_CLK (0) -//#define CIS_PIX_CLK_OPPOSITE (1) -//#define MIPI_PIX_CLK (2) - - //fh_clk_debug(p_clk,"mux0 wrap value is %x\n",mux0); - if (mux0 == CIS_PIX_CLK || mux0 == CIS_PIX_CLK_OPPOSITE) { - //ddr normal parent is pll0 - parent = &cis_pclk; - } else { - parent = &mipi_pix_clk; - } - p_clk->clk.peri.obj.normal.mux.mux_flag = HAS_MUX; + //mux0 = check_xtal_pll0(p_clk->clk.peri.obj.ddr.mux[0].reg_offset,p_clk->clk.peri.obj.ddr.mux[0].reg_mask); + ret = check_pix_clk_source(p_clk->clk.peri.obj.normal.mux.reg_offset, + p_clk->clk.peri.obj.normal.mux.reg_mask, &mux0); + if (ret != 0) { + fh_clk_err(p_clk, "read pmu failed.error no:%x\n", ret); + return; + } +//#define CIS_PIX_CLK (0) +//#define CIS_PIX_CLK_OPPOSITE (1) +//#define MIPI_PIX_CLK (2) + + //fh_clk_debug(p_clk,"mux0 wrap value is %x\n",mux0); + if (mux0 == CIS_PIX_CLK || mux0 == CIS_PIX_CLK_OPPOSITE) { + //ddr normal parent is pll0 + parent = &cis_pclk; + } else { + parent = &mipi_pix_clk; + } + p_clk->clk.peri.obj.normal.mux.mux_flag = HAS_MUX; #endif - clk_handle(p_clk, parent); + clk_handle(p_clk, parent); } void aclk_update(struct fh_clk* p_clk) { - clk_handle(p_clk, &cpu_fclk); + clk_handle(p_clk, &cpu_fclk); } void hclk_update(struct fh_clk* p_clk) { - fclk_update(p_clk); + fclk_update(p_clk); } void pclk_update(struct fh_clk* p_clk) { - clk_handle(p_clk, &cpu_hclk); + clk_handle(p_clk, &cpu_hclk); } void isp_aclk_update(struct fh_clk* p_clk) { - fclk_update(p_clk); + fclk_update(p_clk); } void vcu_clk_update(struct fh_clk* p_clk) { - fclk_update(p_clk); + fclk_update(p_clk); } void vou_clk_update(struct fh_clk* p_clk) { - fclk_update(p_clk); + fclk_update(p_clk); } void mipi_p32_clk_update(struct fh_clk* p_clk) { - fclk_update(p_clk); + fclk_update(p_clk); } void cis_clk_out_update(struct fh_clk* p_clk) { - fclk_update(p_clk); + fclk_update(p_clk); } void pts_update(struct fh_clk* p_clk) { - fclk_update(p_clk); + fclk_update(p_clk); } void mipi_pix_clk_update(struct fh_clk* p_clk) { - fclk_update(p_clk); + fclk_update(p_clk); } void spi0_clk_update(struct fh_clk* p_clk) { - clk_handle(p_clk, &pll1); + clk_handle(p_clk, &pll1); } void spi1_clk_update(struct fh_clk* p_clk) { - clk_handle(p_clk, &pll1); + clk_handle(p_clk, &pll1); } void mipi_dphy_clk20m_update(struct fh_clk* p_clk) { - clk_handle(p_clk, &pll1); + clk_handle(p_clk, &pll1); } void i2c0_clk_update(struct fh_clk* p_clk) { - clk_handle(p_clk, &pll1); + clk_handle(p_clk, &pll1); } void i2c1_clk_update(struct fh_clk* p_clk) { - clk_handle(p_clk, &pll1); + clk_handle(p_clk, &pll1); } void uart0_clk_update(struct fh_clk* p_clk) { - clk_handle(p_clk, &pll1); + clk_handle(p_clk, &pll1); } void pwm_clk_update(struct fh_clk* p_clk) { - clk_handle(p_clk, &pll1); + clk_handle(p_clk, &pll1); } void time0_clk_update(struct fh_clk* p_clk) { - clk_handle(p_clk, &pll1); + clk_handle(p_clk, &pll1); } void time1_clk_update(struct fh_clk* p_clk) { - clk_handle(p_clk, &pll1); + clk_handle(p_clk, &pll1); } void uart1_clk_update(struct fh_clk* p_clk) { - clk_handle(p_clk, &pll1); + clk_handle(p_clk, &pll1); } void sadc_clk_update(struct fh_clk* p_clk) { - clk_handle(p_clk, &pll1); + clk_handle(p_clk, &pll1); } //sdc0... void sdc0_clk2x_update(struct fh_clk* p_clk) { - clk_handle(p_clk, &pll1); + clk_handle(p_clk, &pll1); } void sdc0_clk_update(struct fh_clk* p_clk) { - clk_handle(p_clk, &sdc0_clk2x); + clk_handle(p_clk, &sdc0_clk2x); } void sdc0_clk_out_update(struct fh_clk* p_clk) { - clk_handle(p_clk, &sdc0_clk); + clk_handle(p_clk, &sdc0_clk); } void sdc0_clk_sample_update(struct fh_clk* p_clk) { - clk_handle(p_clk, &sdc0_clk2x); + clk_handle(p_clk, &sdc0_clk2x); } void sdc0_clk_drv_update(struct fh_clk* p_clk) { - clk_handle(p_clk, &sdc0_clk2x); + clk_handle(p_clk, &sdc0_clk2x); } void sdc1_clk2x_update(struct fh_clk* p_clk) { - clk_handle(p_clk, &pll1); + clk_handle(p_clk, &pll1); } void sdc1_clk_update(struct fh_clk* p_clk) { - clk_handle(p_clk, &sdc1_clk2x); + clk_handle(p_clk, &sdc1_clk2x); } void sdc1_clk_out_update(struct fh_clk* p_clk) { - clk_handle(p_clk, &sdc1_clk); + clk_handle(p_clk, &sdc1_clk); } void sdc1_clk_sample_update(struct fh_clk* p_clk) { - clk_handle(p_clk, &sdc1_clk2x); + clk_handle(p_clk, &sdc1_clk2x); } void sdc1_clk_drv_update(struct fh_clk* p_clk) { - clk_handle(p_clk, &sdc1_clk2x); + clk_handle(p_clk, &sdc1_clk2x); } void eth_ref_clk_update(struct fh_clk* p_clk) { - clk_handle(p_clk, &pll1); + clk_handle(p_clk, &pll1); } void wdt_clk_update(struct fh_clk* p_clk) { - clk_handle(p_clk, &cpu_pclk); + clk_handle(p_clk, &cpu_pclk); } /** * @brief System Clock Configuration */ -#define CLK_CONTROL_BASE PMU_REG_BASE +#define CLK_CONTROL_BASE PMU_REG_BASE void rt_hw_clock_init(void) { - struct fh_clk *p; - int i; - fh_clk_tree.c_base_addr = CLK_CONTROL_BASE; - fh_clk_tree.clk_head = fh_clk_array; - - //first open all the clock.. - FH_TIMER_WRITEL(REG_PMU_CLK_GATE, 0x0); - for (i = 0; i < sizeof(fh_clk_array) / sizeof(struct fh_clk *); i++) { - p = fh_clk_tree.clk_head[i]; - if (p->update_func) - p->update_func(p); - } + struct fh_clk *p; + int i; + fh_clk_tree.c_base_addr = CLK_CONTROL_BASE; + fh_clk_tree.clk_head = fh_clk_array; + + //first open all the clock.. + FH_TIMER_WRITEL(REG_PMU_CLK_GATE, 0x0); + for (i = 0; i < sizeof(fh_clk_array) / sizeof(struct fh_clk *); i++) { + p = fh_clk_tree.clk_head[i]; + if (p->update_func) + p->update_func(p); + } } /*************** @@ -2453,196 +2453,196 @@ void rt_hw_clock_init(void) struct fh_clk *clk_get(const char *name) { - struct fh_clk *p; - int i; + struct fh_clk *p; + int i; - for (i = 0; i < sizeof(fh_clk_array) / sizeof(struct fh_clk *); i++) { - p = fh_clk_tree.clk_head[i]; - if (!strcmp(p->name, name)) { - return p; - } - } + for (i = 0; i < sizeof(fh_clk_array) / sizeof(struct fh_clk *); i++) { + p = fh_clk_tree.clk_head[i]; + if (!strcmp(p->name, name)) { + return p; + } + } - return RT_NULL; + return RT_NULL; } // -//#define HAS_GATE (0) -//#define HAS_NO_GATE (1) -// rt_uint32_t gate_flag; -//#define CLK_UNGATE (0) -//#define CLK_GATE (1) +//#define HAS_GATE (0) +//#define HAS_NO_GATE (1) +// rt_uint32_t gate_flag; +//#define CLK_UNGATE (0) +//#define CLK_GATE (1) void clk_gate_control(struct fh_clk *p_clk, rt_uint32_t status) { - if (status > CLK_GATE) - return; + if (status > CLK_GATE) + return; - if (p_clk->level == LEVEL_PERIPHERAL) { + if (p_clk->level == LEVEL_PERIPHERAL) { - switch (p_clk->clk.peri.peri_flag) { - case LEVEL_PERI_NORMAL: + switch (p_clk->clk.peri.peri_flag) { + case LEVEL_PERI_NORMAL: - if (p_clk->clk.peri.obj.normal.gate.gate_flag - == HAS_GATE) { - p_clk->clk.peri.obj.normal.gate.sw_status = - status; - } else { - rt_kprintf("[%-16.15s]: no gate...\t\n", - p_clk->name); - } + if (p_clk->clk.peri.obj.normal.gate.gate_flag + == HAS_GATE) { + p_clk->clk.peri.obj.normal.gate.sw_status = + status; + } else { + rt_kprintf("[%-16.15s]: no gate...\t\n", + p_clk->name); + } - break; - case LEVEL_PERI_DDR: - if (p_clk->clk.peri.obj.ddr.gate.gate_flag == HAS_GATE) { - p_clk->clk.peri.obj.ddr.gate.sw_status = status; - } else { - rt_kprintf("[%-16.15s]: no gate...\t\n", - p_clk->name); - } + break; + case LEVEL_PERI_DDR: + if (p_clk->clk.peri.obj.ddr.gate.gate_flag == HAS_GATE) { + p_clk->clk.peri.obj.ddr.gate.sw_status = status; + } else { + rt_kprintf("[%-16.15s]: no gate...\t\n", + p_clk->name); + } - break; + break; - default: - break; - } + default: + break; + } - p_clk->update_func(p_clk); + p_clk->update_func(p_clk); - } + } } void clk_gate(struct fh_clk *p_clk) { - clk_gate_control(p_clk, CLK_GATE); + clk_gate_control(p_clk, CLK_GATE); } void clk_ungate(struct fh_clk *p_clk) { - clk_gate_control(p_clk, CLK_UNGATE); + clk_gate_control(p_clk, CLK_UNGATE); } rt_uint32_t clk_get_rate(struct fh_clk *p_clk) { - rt_uint32_t rate; - //first update the status - p_clk->update_func(p_clk); - rate = p_clk->clk_out_rate; - return rate; + rt_uint32_t rate; + //first update the status + p_clk->update_func(p_clk); + rate = p_clk->clk_out_rate; + return rate; } void clk_set_rate(struct fh_clk *p_clk, rt_uint32_t rate_value) { - rt_uint32_t clk_in, div_flag, pre_div, div_multi, baud_out; - - if (p_clk->level == LEVEL_PERIPHERAL) { - - switch (p_clk->clk.peri.peri_flag) { - case LEVEL_PERI_NORMAL: - - clk_in = p_clk->parent->clk_out_rate; - div_flag = p_clk->clk.peri.obj.normal.div.div_flag; - pre_div = p_clk->clk.peri.obj.normal.div.pdiv_value; - div_multi = p_clk->clk.peri.obj.normal.div.sw_div_multi; - baud_out = rate_value; - - cal_baud_div(clk_in, div_flag, pre_div, - &p_clk->clk.peri.obj.normal.div.sw_div_value, - div_multi, baud_out); - - break; - case LEVEL_PERI_DDR: - //rt_uint32_t mux0,mux1; - clk_in = p_clk->parent->clk_out_rate; - div_flag = p_clk->clk.peri.obj.ddr.div.div_flag; - pre_div = p_clk->clk.peri.obj.ddr.div.pdiv_value; - div_multi = p_clk->clk.peri.obj.ddr.div.sw_div_multi; - baud_out = rate_value; - - cal_baud_div(clk_in, div_flag, pre_div, - &p_clk->clk.peri.obj.ddr.div.sw_div_value, - div_multi, baud_out); - break; - case LEVEL_PERI_SDC: - fh_clk_debug(p_clk, - "sdc can't set baud,please set the 'sdcx_clk2x'\n"); - break; - case LEVEL_PERI_GMAC: - fh_clk_debug(p_clk, "gmac not support set baud\n"); - break; - default: - break; - } - p_clk->update_func(p_clk); - - } + rt_uint32_t clk_in, div_flag, pre_div, div_multi, baud_out; + + if (p_clk->level == LEVEL_PERIPHERAL) { + + switch (p_clk->clk.peri.peri_flag) { + case LEVEL_PERI_NORMAL: + + clk_in = p_clk->parent->clk_out_rate; + div_flag = p_clk->clk.peri.obj.normal.div.div_flag; + pre_div = p_clk->clk.peri.obj.normal.div.pdiv_value; + div_multi = p_clk->clk.peri.obj.normal.div.sw_div_multi; + baud_out = rate_value; + + cal_baud_div(clk_in, div_flag, pre_div, + &p_clk->clk.peri.obj.normal.div.sw_div_value, + div_multi, baud_out); + + break; + case LEVEL_PERI_DDR: + //rt_uint32_t mux0,mux1; + clk_in = p_clk->parent->clk_out_rate; + div_flag = p_clk->clk.peri.obj.ddr.div.div_flag; + pre_div = p_clk->clk.peri.obj.ddr.div.pdiv_value; + div_multi = p_clk->clk.peri.obj.ddr.div.sw_div_multi; + baud_out = rate_value; + + cal_baud_div(clk_in, div_flag, pre_div, + &p_clk->clk.peri.obj.ddr.div.sw_div_value, + div_multi, baud_out); + break; + case LEVEL_PERI_SDC: + fh_clk_debug(p_clk, + "sdc can't set baud,please set the 'sdcx_clk2x'\n"); + break; + case LEVEL_PERI_GMAC: + fh_clk_debug(p_clk, "gmac not support set baud\n"); + break; + default: + break; + } + p_clk->update_func(p_clk); + + } } rt_uint32_t sdc_get_phase(struct fh_clk *p_clk) { - if (p_clk->level == LEVEL_PERIPHERAL) { - if (p_clk->clk.peri.peri_flag == LEVEL_PERI_SDC) { + if (p_clk->level == LEVEL_PERIPHERAL) { + if (p_clk->clk.peri.peri_flag == LEVEL_PERI_SDC) { - p_clk->update_func(p_clk); - return p_clk->clk.peri.obj.sdc.phase_diff; - } - } - return SDC_CLK_PARA_ERROR; + p_clk->update_func(p_clk); + return p_clk->clk.peri.obj.sdc.phase_diff; + } + } + return SDC_CLK_PARA_ERROR; } rt_uint32_t sdc_set_phase(struct fh_clk *p_clk, rt_uint32_t phase) { - if (phase > DIFF_SDC_REFCLK_270) - return SDC_CLK_PARA_ERROR; + if (phase > DIFF_SDC_REFCLK_270) + return SDC_CLK_PARA_ERROR; - if (p_clk->level == LEVEL_PERIPHERAL) { - if (p_clk->clk.peri.peri_flag == LEVEL_PERI_SDC) { - p_clk->clk.peri.obj.sdc.phase_diff = phase; - p_clk->update_func(p_clk); - return SDC_CLK_PARA_OK; - } - } - return SDC_CLK_PARA_ERROR; + if (p_clk->level == LEVEL_PERIPHERAL) { + if (p_clk->clk.peri.peri_flag == LEVEL_PERI_SDC) { + p_clk->clk.peri.obj.sdc.phase_diff = phase; + p_clk->update_func(p_clk); + return SDC_CLK_PARA_OK; + } + } + return SDC_CLK_PARA_ERROR; } #ifdef FH_DBG_CLK int fh_clk_nlist() { - struct fh_clk *p; - int i; + struct fh_clk *p; + int i; - for(i = 0;iupdate_func(p); - rt_kprintf("[%-16.15s]:\t\t[baud]:%d\t\n",p->name,p->clk_out_rate); - } + for(i = 0;iupdate_func(p); + rt_kprintf("[%-16.15s]:\t\t[baud]:%d\t\n",p->name,p->clk_out_rate); + } - return 0; + return 0; } int fh_clk_glist() { - struct fh_clk *p; - int i; - rt_kprintf("first bit set means has no gate..\n"); - for(i = 0;iupdate_func(p); - if(!(p->gate & CLK_HAS_NO_GATE)) - rt_kprintf("[%-16.15s]:\t\t[gate]:%d\t\n",p->name,p->gate); - else - rt_kprintf("[%-16.15s]:\t\t[gate]:no gate..\t\n",p->name); - } - - return 0; + struct fh_clk *p; + int i; + rt_kprintf("first bit set means has no gate..\n"); + for(i = 0;iupdate_func(p); + if(!(p->gate & CLK_HAS_NO_GATE)) + rt_kprintf("[%-16.15s]:\t\t[gate]:%d\t\n",p->name,p->gate); + else + rt_kprintf("[%-16.15s]:\t\t[gate]:no gate..\t\n",p->name); + } + + return 0; } #endif diff --git a/bsp/fh8620/platform/plat-v2/clock.h b/bsp/fh8620/platform/plat-v2/clock.h index 60b0ed653..cdf94b017 100644 --- a/bsp/fh8620/platform/plat-v2/clock.h +++ b/bsp/fh8620/platform/plat-v2/clock.h @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,12 +18,12 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + #ifndef TIMER_H_ #define TIMER_H_ @@ -43,12 +43,12 @@ void fh_pmu_open(void); void fh_pmu_close(void); */ -#define DIFF_SDC_REFCLK_0 (0) -#define DIFF_SDC_REFCLK_90 (1) -#define DIFF_SDC_REFCLK_180 (2) -#define DIFF_SDC_REFCLK_270 (3) -#define SDC_CLK_PARA_ERROR (0xffff0000) -#define SDC_CLK_PARA_OK (0) +#define DIFF_SDC_REFCLK_0 (0) +#define DIFF_SDC_REFCLK_90 (1) +#define DIFF_SDC_REFCLK_180 (2) +#define DIFF_SDC_REFCLK_270 (3) +#define SDC_CLK_PARA_ERROR (0xffff0000) +#define SDC_CLK_PARA_OK (0) void clk_gate(struct fh_clk *p_clk); diff --git a/bsp/fh8620/platform/plat-v2/fh_pmu.c b/bsp/fh8620/platform/plat-v2/fh_pmu.c index 8f518efd9..d17f215a1 100644 --- a/bsp/fh8620/platform/plat-v2/fh_pmu.c +++ b/bsp/fh8620/platform/plat-v2/fh_pmu.c @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,45 +18,45 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + #include "rtdebug.h" #include "arch.h" #include "fh_pmu.h" #include "fh_def.h" -#define FH_PMU_WRITEL(offset,value) SET_REG((PMU_REG_BASE + offset),value) -#define FH_PMU_WRITEL_MASK(offset,value, mask) SET_REG_M((PMU_REG_BASE + offset), value, mask) -#define FH_PMU_READL(offset) GET_REG((PMU_REG_BASE + offset)) +#define FH_PMU_WRITEL(offset,value) SET_REG((PMU_REG_BASE + offset),value) +#define FH_PMU_WRITEL_MASK(offset,value, mask) SET_REG_M((PMU_REG_BASE + offset), value, mask) +#define FH_PMU_READL(offset) GET_REG((PMU_REG_BASE + offset)) -#define PMU_OFFSET_MAX 0x1d0 +#define PMU_OFFSET_MAX 0x1d0 int fh_pmu_read(rt_uint32_t offset, rt_uint32_t *value) { - RT_ASSERT(offset < PMU_OFFSET_MAX); + RT_ASSERT(offset < PMU_OFFSET_MAX); - *value = FH_PMU_READL(offset); - return 0; + *value = FH_PMU_READL(offset); + return 0; } int fh_pmu_write(rt_uint32_t offset, const rt_uint32_t value) { - RT_ASSERT(offset < PMU_OFFSET_MAX); + RT_ASSERT(offset < PMU_OFFSET_MAX); - FH_PMU_WRITEL(offset, value); - return 0; + FH_PMU_WRITEL(offset, value); + return 0; } int fh_pmu_write_mask(rt_uint32_t offset, const rt_uint32_t value, - const rt_uint32_t mask) + const rt_uint32_t mask) { - RT_ASSERT(offset < PMU_OFFSET_MAX); + RT_ASSERT(offset < PMU_OFFSET_MAX); - FH_PMU_WRITEL_MASK(offset, value, mask); - return 0; + FH_PMU_WRITEL_MASK(offset, value, mask); + return 0; } diff --git a/bsp/fh8620/platform/plat-v2/fh_pmu.h b/bsp/fh8620/platform/plat-v2/fh_pmu.h index 19a6279d1..4ecedd2fd 100644 --- a/bsp/fh8620/platform/plat-v2/fh_pmu.h +++ b/bsp/fh8620/platform/plat-v2/fh_pmu.h @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,12 +18,12 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + #ifndef FH_PMU_H_ #define FH_PMU_H_ @@ -36,7 +36,7 @@ #define REG_PMU_PLL0_CTRL (0x010) #define REG_PMU_PLL1_CTRL (0x014) #define REG_PMU_ARC_CLK_GATE (0x018) -#define REG_PMU_CLK_GATE (0x01c) +#define REG_PMU_CLK_GATE (0x01c) #define REG_PMU_CLK_SEL (0x020) #define REG_PMU_CLK_DIV0 (0x024) #define REG_PMU_CLK_DIV1 (0x028) diff --git a/bsp/fh8620/platform/plat-v2/iomux.c b/bsp/fh8620/platform/plat-v2/iomux.c index 67acf6ca7..51b14f593 100644 --- a/bsp/fh8620/platform/plat-v2/iomux.c +++ b/bsp/fh8620/platform/plat-v2/iomux.c @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,34 +18,34 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + #include "rtdebug.h" #include "iomux.h" static void fh_iomux_setmfs(Iomux_Pad *pad) { - switch (pad->reg_type) { - case 8: - (IOMUX_PADTYPE(8)pad->reg)->bit.mfs = pad->func_sel; - break; - case 13: - (IOMUX_PADTYPE(13)pad->reg)->bit.mfs = pad->func_sel; - break; - case 20: - (IOMUX_PADTYPE(20)pad->reg)->bit.mfs = pad->func_sel; - break; - case 21: - (IOMUX_PADTYPE(21)pad->reg)->bit.mfs = pad->func_sel; - break; - default: - break; - } + switch (pad->reg_type) { + case 8: + (IOMUX_PADTYPE(8)pad->reg)->bit.mfs = pad->func_sel; + break; + case 13: + (IOMUX_PADTYPE(13)pad->reg)->bit.mfs = pad->func_sel; + break; + case 20: + (IOMUX_PADTYPE(20)pad->reg)->bit.mfs = pad->func_sel; + break; + case 21: + (IOMUX_PADTYPE(21)pad->reg)->bit.mfs = pad->func_sel; + break; + default: + break; + } } @@ -53,50 +53,50 @@ static void fh_iomux_setmfs(Iomux_Pad *pad) static int fh_iomux_getmfs(Iomux_Pad *pad) { - int mfs; - - switch (pad->reg_type) { - case 8: - mfs = (IOMUX_PADTYPE(8)pad->reg)->bit.mfs; - break; - case 13: - mfs = (IOMUX_PADTYPE(13)pad->reg)->bit.mfs; - break; - case 20: - mfs = (IOMUX_PADTYPE(20)pad->reg)->bit.mfs; - break; - case 21: - mfs = (IOMUX_PADTYPE(21)pad->reg)->bit.mfs; - break; - default: - mfs = -1; - break; - - } - return mfs; + int mfs; + + switch (pad->reg_type) { + case 8: + mfs = (IOMUX_PADTYPE(8)pad->reg)->bit.mfs; + break; + case 13: + mfs = (IOMUX_PADTYPE(13)pad->reg)->bit.mfs; + break; + case 20: + mfs = (IOMUX_PADTYPE(20)pad->reg)->bit.mfs; + break; + case 21: + mfs = (IOMUX_PADTYPE(21)pad->reg)->bit.mfs; + break; + default: + mfs = -1; + break; + + } + return mfs; } static void fh_iomux_print() { - int i; - UINT32 reg; + int i; + UINT32 reg; - for (i = 0; i < ARRAY_SIZE(fh81_iomux_cfg); i++) { - int curr_func; + for (i = 0; i < ARRAY_SIZE(fh81_iomux_cfg); i++) { + int curr_func; - curr_func = fh81_iomux_getmfs(iomux_obj, &iomux_obj.pads[i]); - reg = readl((UINT32)iomux_obj.pads[i].reg); + curr_func = fh81_iomux_getmfs(iomux_obj, &iomux_obj.pads[i]); + reg = readl((UINT32)iomux_obj.pads[i].reg); - if (curr_func < 0) - rt_kprintf("\t%d\t\t%-8s(no mfs)\t0x%08x\n", i, iomux_obj.pads[i].func_name[0], - reg); - else - rt_kprintf("\t%d\t\t%-16s\t0x%08x\n", i, iomux_obj.pads[i].func_name[curr_func], - reg); + if (curr_func < 0) + rt_kprintf("\t%d\t\t%-8s(no mfs)\t0x%08x\n", i, iomux_obj.pads[i].func_name[0], + reg); + else + rt_kprintf("\t%d\t\t%-16s\t0x%08x\n", i, iomux_obj.pads[i].func_name[curr_func], + reg); - } + } } @@ -105,90 +105,90 @@ static void fh_iomux_print() static void fh_iomux_setcur(Iomux_Pad *pad) { - switch (pad->reg_type) { - case 5: - (IOMUX_PADTYPE(5)pad->reg)->bit.e8_e4 = pad->drv_cur; - break; - case 8: - (IOMUX_PADTYPE(8)pad->reg)->bit.e8_e4 = pad->drv_cur; - break; - case 13: - (IOMUX_PADTYPE(13)pad->reg)->bit.e4_e2 = pad->drv_cur; - break; - case 17: - (IOMUX_PADTYPE(17)pad->reg)->bit.e8_e4 = pad->drv_cur; - break; - case 20: - (IOMUX_PADTYPE(20)pad->reg)->bit.e4_e2 = pad->drv_cur; - break; - case 21: - (IOMUX_PADTYPE(21)pad->reg)->bit.e4_e2 = pad->drv_cur; - break; - default: - break; - } + switch (pad->reg_type) { + case 5: + (IOMUX_PADTYPE(5)pad->reg)->bit.e8_e4 = pad->drv_cur; + break; + case 8: + (IOMUX_PADTYPE(8)pad->reg)->bit.e8_e4 = pad->drv_cur; + break; + case 13: + (IOMUX_PADTYPE(13)pad->reg)->bit.e4_e2 = pad->drv_cur; + break; + case 17: + (IOMUX_PADTYPE(17)pad->reg)->bit.e8_e4 = pad->drv_cur; + break; + case 20: + (IOMUX_PADTYPE(20)pad->reg)->bit.e4_e2 = pad->drv_cur; + break; + case 21: + (IOMUX_PADTYPE(21)pad->reg)->bit.e4_e2 = pad->drv_cur; + break; + default: + break; + } } static void fh_iomux_setpupd(Iomux_Pad *pad) { - switch (pad->reg_type) { - case 9: - (IOMUX_PADTYPE(9)pad->reg)->bit.pu_pd = pad->pupd; - break; - case 17: - (IOMUX_PADTYPE(17)pad->reg)->bit.pu_pd = pad->pupd; - break; - case 20: - (IOMUX_PADTYPE(20)pad->reg)->bit.pu_pd = pad->pupd; - break; - case 21: - (IOMUX_PADTYPE(21)pad->reg)->bit.pu_pd = pad->pupd; - break; - default: - break; - } + switch (pad->reg_type) { + case 9: + (IOMUX_PADTYPE(9)pad->reg)->bit.pu_pd = pad->pupd; + break; + case 17: + (IOMUX_PADTYPE(17)pad->reg)->bit.pu_pd = pad->pupd; + break; + case 20: + (IOMUX_PADTYPE(20)pad->reg)->bit.pu_pd = pad->pupd; + break; + case 21: + (IOMUX_PADTYPE(21)pad->reg)->bit.pu_pd = pad->pupd; + break; + default: + break; + } } static void fh_iomux_setrest(Iomux_Pad *pad) { - switch (pad->reg_type) { - case 5: - (IOMUX_PADTYPE(5)pad->reg)->bit.sr = 0; - break; - case 8: - (IOMUX_PADTYPE(8)pad->reg)->bit.sr = 0; - break; - case 9: - (IOMUX_PADTYPE(9)pad->reg)->bit.ie = 1; - (IOMUX_PADTYPE(9)pad->reg)->bit.smt = 1; - break; - case 13: - (IOMUX_PADTYPE(13)pad->reg)->bit.ie = 1; - (IOMUX_PADTYPE(13)pad->reg)->bit.smt = 1; - break; - case 17: - (IOMUX_PADTYPE(17)pad->reg)->bit.sr = 0; - (IOMUX_PADTYPE(17)pad->reg)->bit.ie = 1; - (IOMUX_PADTYPE(17)pad->reg)->bit.e = 1; - (IOMUX_PADTYPE(17)pad->reg)->bit.smt = 1; - break; - case 20: - (IOMUX_PADTYPE(20)pad->reg)->bit.sr = 0; - (IOMUX_PADTYPE(20)pad->reg)->bit.ie = 1; - (IOMUX_PADTYPE(20)pad->reg)->bit.smt = 1; - break; - case 21: - (IOMUX_PADTYPE(21)pad->reg)->bit.sr = 0; - (IOMUX_PADTYPE(21)pad->reg)->bit.ie = 1; - (IOMUX_PADTYPE(21)pad->reg)->bit.smt = 1; - break; - default: - break; - } + switch (pad->reg_type) { + case 5: + (IOMUX_PADTYPE(5)pad->reg)->bit.sr = 0; + break; + case 8: + (IOMUX_PADTYPE(8)pad->reg)->bit.sr = 0; + break; + case 9: + (IOMUX_PADTYPE(9)pad->reg)->bit.ie = 1; + (IOMUX_PADTYPE(9)pad->reg)->bit.smt = 1; + break; + case 13: + (IOMUX_PADTYPE(13)pad->reg)->bit.ie = 1; + (IOMUX_PADTYPE(13)pad->reg)->bit.smt = 1; + break; + case 17: + (IOMUX_PADTYPE(17)pad->reg)->bit.sr = 0; + (IOMUX_PADTYPE(17)pad->reg)->bit.ie = 1; + (IOMUX_PADTYPE(17)pad->reg)->bit.e = 1; + (IOMUX_PADTYPE(17)pad->reg)->bit.smt = 1; + break; + case 20: + (IOMUX_PADTYPE(20)pad->reg)->bit.sr = 0; + (IOMUX_PADTYPE(20)pad->reg)->bit.ie = 1; + (IOMUX_PADTYPE(20)pad->reg)->bit.smt = 1; + break; + case 21: + (IOMUX_PADTYPE(21)pad->reg)->bit.sr = 0; + (IOMUX_PADTYPE(21)pad->reg)->bit.ie = 1; + (IOMUX_PADTYPE(21)pad->reg)->bit.smt = 1; + break; + default: + break; + } } @@ -198,13 +198,13 @@ extern const int fh_iomux_cfg_count; void __fh_setiomux(Iomux_Pad *pad, void *iobase) { - UINT32 regvalue = 0; - pad->reg = ®value; - fh_iomux_setmfs(pad); - fh_iomux_setcur(pad); - fh_iomux_setpupd(pad); - fh_iomux_setrest(pad); - SET_REG(iobase, regvalue); + UINT32 regvalue = 0; + pad->reg = ®value; + fh_iomux_setmfs(pad); + fh_iomux_setcur(pad); + fh_iomux_setpupd(pad); + fh_iomux_setrest(pad); + SET_REG(iobase, regvalue); } static UINT32 g_iomux_base; @@ -212,73 +212,73 @@ static UINT32 g_iomux_base; void fh_iomux_init(UINT32 base) { -// return; - int i; -// int test_cnt = 0; - UINT32 reg; - g_iomux_base = base; +// return; + int i; +// int test_cnt = 0; + UINT32 reg; + g_iomux_base = base; - iomux_obj.pbase = (void *)base; + iomux_obj.pbase = (void *)base; -// iomux_obj.vbase = (UINT32 *)rt_malloc(1024); - iomux_obj.pads = fh_iomux_cfg; +// iomux_obj.vbase = (UINT32 *)rt_malloc(1024); + iomux_obj.pads = fh_iomux_cfg; - for (i = 0; i < fh_iomux_cfg_count; i++) { + for (i = 0; i < fh_iomux_cfg_count; i++) { #if (1) - iomux_obj.pads[i].id = i; - iomux_obj.pads[i].reg_offset = i * 4; - iomux_obj.pads[i].reg = ®//(UINT32 *)(iomux_obj.vbase + iomux_obj.pads[i].reg_offset); - fh_iomux_setmfs(&fh_iomux_cfg[i]); - fh_iomux_setcur(&fh_iomux_cfg[i]); - fh_iomux_setpupd(&fh_iomux_cfg[i]); - fh_iomux_setrest(&fh_iomux_cfg[i]); - SET_REG(iomux_obj.pbase + iomux_obj.pads[i].reg_offset, reg); -// *((UINT32 *)(iomux_obj.vbase + iomux_obj.pads[i].reg_offset))); - //rt_kprintf("addr: 0x%x, pmu data: 0x%x\n", iomux_obj.pbase + iomux_obj.pads[i].reg_offset, GET_REG(iomux_obj.pbase + iomux_obj.pads[i].reg_offset)); -// test_cnt++; + iomux_obj.pads[i].id = i; + iomux_obj.pads[i].reg_offset = i * 4; + iomux_obj.pads[i].reg = ®//(UINT32 *)(iomux_obj.vbase + iomux_obj.pads[i].reg_offset); + fh_iomux_setmfs(&fh_iomux_cfg[i]); + fh_iomux_setcur(&fh_iomux_cfg[i]); + fh_iomux_setpupd(&fh_iomux_cfg[i]); + fh_iomux_setrest(&fh_iomux_cfg[i]); + SET_REG(iomux_obj.pbase + iomux_obj.pads[i].reg_offset, reg); +// *((UINT32 *)(iomux_obj.vbase + iomux_obj.pads[i].reg_offset))); + //rt_kprintf("addr: 0x%x, pmu data: 0x%x\n", iomux_obj.pbase + iomux_obj.pads[i].reg_offset, GET_REG(iomux_obj.pbase + iomux_obj.pads[i].reg_offset)); +// test_cnt++; #else #ifdef FH_USING_JTAG - if (strncmp(fh_iomux_cfg[i].func_name[0], "JTAG", 4) == 0) - continue; + if (strncmp(fh_iomux_cfg[i].func_name[0], "JTAG", 4) == 0) + continue; #endif /* - if (strncmp(fh_iomux_cfg[i].func_name[1], "UART1", 5) == 0) - break; + if (strncmp(fh_iomux_cfg[i].func_name[1], "UART1", 5) == 0) + break; */ - __fh_setiomux(&fh_iomux_cfg[i], (void *) base + i * 4); + __fh_setiomux(&fh_iomux_cfg[i], (void *) base + i * 4); #endif - } + } #ifdef CONFIG_RMII - //(IOMUX_PADTYPE(17)(iomux_obj.pads[18]).reg)->bit.e = 1; - reg = GET_REG(0xf00000a4); - reg |= (1 << 13); - SET_REG(0xf00000a4, reg); + //(IOMUX_PADTYPE(17)(iomux_obj.pads[18]).reg)->bit.e = 1; + reg = GET_REG(0xf00000a4); + reg |= (1 << 13); + SET_REG(0xf00000a4, reg); #else - //(IOMUX_PADTYPE(17)(iomux_obj.pads[18]).reg)->bit.e = 0; - reg = GET_REG(0xf00000a4); - reg &= ~(1 << 13); - SET_REG(0xf00000a4, reg); + //(IOMUX_PADTYPE(17)(iomux_obj.pads[18]).reg)->bit.e = 0; + reg = GET_REG(0xf00000a4); + reg &= ~(1 << 13); + SET_REG(0xf00000a4, reg); #endif #ifdef IOMUX_DEBUG - fh_iomux_print(iomux_obj); + fh_iomux_print(iomux_obj); #endif - //rt_free(iomux_obj.vbase); - //iomux_obj.vbase = 0; + //rt_free(iomux_obj.vbase); + //iomux_obj.vbase = 0; } void fh_iomux_pin_switch(int pin_num, int func_num) { - RT_ASSERT(pin_num < fh_iomux_cfg_count); - __fh_setiomux(&fh_iomux_cfg[pin_num], (void *)g_iomux_base + pin_num * 4); - /* - fh_iomux_cfg[pin_num].func_sel = func_num; - fh_iomux_setmfs(&fh_iomux_cfg[pin_num]); - SET_REG(iomux_obj.pbase + iomux_obj.pads[pin_num].reg_offset, *((UINT32 *)(iomux_obj.vbase + iomux_obj.pads[pin_num].reg_offset))); - */ + RT_ASSERT(pin_num < fh_iomux_cfg_count); + __fh_setiomux(&fh_iomux_cfg[pin_num], (void *)g_iomux_base + pin_num * 4); + /* + fh_iomux_cfg[pin_num].func_sel = func_num; + fh_iomux_setmfs(&fh_iomux_cfg[pin_num]); + SET_REG(iomux_obj.pbase + iomux_obj.pads[pin_num].reg_offset, *((UINT32 *)(iomux_obj.vbase + iomux_obj.pads[pin_num].reg_offset))); + */ } diff --git a/bsp/fh8620/platform/plat-v2/iomux.h b/bsp/fh8620/platform/plat-v2/iomux.h index e03273b2b..a0aa8d338 100644 --- a/bsp/fh8620/platform/plat-v2/iomux.h +++ b/bsp/fh8620/platform/plat-v2/iomux.h @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,12 +18,12 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + #ifndef IOMUX_H_ #define IOMUX_H_ @@ -126,179 +126,179 @@ #define PMU_PAD_MAC_TXER (92) -#define IOMUX_PADTYPE(n) (Iomux_PadType##n *) -#define IOMUX_PUPD_NONE 0 -#define IOMUX_PUPD_DOWN 1 -#define IOMUX_PUPD_UP 2 -#define IOMUX_PUPD_KEEPER 3 +#define IOMUX_PADTYPE(n) (Iomux_PadType##n *) +#define IOMUX_PUPD_NONE 0 +#define IOMUX_PUPD_DOWN 1 +#define IOMUX_PUPD_UP 2 +#define IOMUX_PUPD_KEEPER 3 //#define IOMUX_DEBUG typedef union { - struct - { - UINT32 sr :1; - UINT32 reserved_3_1 :3; + struct + { + UINT32 sr :1; + UINT32 reserved_3_1 :3; - UINT32 e8_e4 :2; - UINT32 reserved_31_6 :24; + UINT32 e8_e4 :2; + UINT32 reserved_31_6 :24; - }bit; - UINT32 dw; + }bit; + UINT32 dw; }Iomux_PadType5; typedef union { - struct - { - UINT32 sr :1; - UINT32 reserved_3_1 :3; + struct + { + UINT32 sr :1; + UINT32 reserved_3_1 :3; - UINT32 e8_e4 :2; - UINT32 reserved_7_6 :2; + UINT32 e8_e4 :2; + UINT32 reserved_7_6 :2; - UINT32 mfs :1; - UINT32 reserved_31_9 :23; + UINT32 mfs :1; + UINT32 reserved_31_9 :23; - }bit; - UINT32 dw; + }bit; + UINT32 dw; }Iomux_PadType8; typedef union { - struct - { - UINT32 smt :1; - UINT32 reserved_3_1 :3; + struct + { + UINT32 smt :1; + UINT32 reserved_3_1 :3; - UINT32 ie :1; - UINT32 reserved_7_5 :3; + UINT32 ie :1; + UINT32 reserved_7_5 :3; - UINT32 pu_pd :2; - UINT32 reserved_31_10 :22; + UINT32 pu_pd :2; + UINT32 reserved_31_10 :22; - }bit; - UINT32 dw; + }bit; + UINT32 dw; }Iomux_PadType9; typedef union { - struct - { - UINT32 e4_e2 :2; - UINT32 reserved_3_2 :2; + struct + { + UINT32 e4_e2 :2; + UINT32 reserved_3_2 :2; - UINT32 smt :1; - UINT32 reserved_7_5 :3; + UINT32 smt :1; + UINT32 reserved_7_5 :3; - UINT32 ie :1; - UINT32 reserved_11_9 :3; + UINT32 ie :1; + UINT32 reserved_11_9 :3; - UINT32 mfs :2; - UINT32 reserved_31_14 :18; + UINT32 mfs :2; + UINT32 reserved_31_14 :18; - }bit; - UINT32 dw; + }bit; + UINT32 dw; }Iomux_PadType13; typedef union { - struct - { - UINT32 sr :1; - UINT32 reserved_3_1 :3; + struct + { + UINT32 sr :1; + UINT32 reserved_3_1 :3; - UINT32 e8_e4 :2; - UINT32 reserved_7_6 :2; + UINT32 e8_e4 :2; + UINT32 reserved_7_6 :2; - UINT32 smt :1; - UINT32 reserved_11_9 :3; + UINT32 smt :1; + UINT32 reserved_11_9 :3; - UINT32 ie :1; - UINT32 e :1; //only for PAD_MAC_REF_CLK_CFG (0x00a4) - UINT32 reserved_15_12 :2; + UINT32 ie :1; + UINT32 e :1; //only for PAD_MAC_REF_CLK_CFG (0x00a4) + UINT32 reserved_15_12 :2; - UINT32 pu_pd :2; - UINT32 reserved_31_18 :14; + UINT32 pu_pd :2; + UINT32 reserved_31_18 :14; - }bit; - UINT32 dw; + }bit; + UINT32 dw; }Iomux_PadType17; typedef union { - struct - { - UINT32 sr :1; - UINT32 reserved_3_1 :3; + struct + { + UINT32 sr :1; + UINT32 reserved_3_1 :3; - UINT32 e4_e2 :2; - UINT32 reserved_7_6 :2; + UINT32 e4_e2 :2; + UINT32 reserved_7_6 :2; - UINT32 smt :1; - UINT32 reserved_11_9 :3; + UINT32 smt :1; + UINT32 reserved_11_9 :3; - UINT32 ie :1; - UINT32 reserved_15_13 :3; + UINT32 ie :1; + UINT32 reserved_15_13 :3; - UINT32 pu_pd :2; - UINT32 reserved_19_18 :2; + UINT32 pu_pd :2; + UINT32 reserved_19_18 :2; - UINT32 mfs :1; - UINT32 reserved_31_21 :11; + UINT32 mfs :1; + UINT32 reserved_31_21 :11; - }bit; - UINT32 dw; + }bit; + UINT32 dw; }Iomux_PadType20; typedef union { - struct - { - UINT32 sr :1; - UINT32 reserved_3_1 :3; + struct + { + UINT32 sr :1; + UINT32 reserved_3_1 :3; - UINT32 e4_e2 :2; - UINT32 reserved_7_6 :2; + UINT32 e4_e2 :2; + UINT32 reserved_7_6 :2; - UINT32 smt :1; - UINT32 reserved_11_9 :3; + UINT32 smt :1; + UINT32 reserved_11_9 :3; - UINT32 ie :1; - UINT32 reserved_15_13 :3; + UINT32 ie :1; + UINT32 reserved_15_13 :3; - UINT32 pu_pd :2; - UINT32 reserved_19_18 :2; + UINT32 pu_pd :2; + UINT32 reserved_19_18 :2; - UINT32 mfs :2; - UINT32 reserved_31_21 :10; + UINT32 mfs :2; + UINT32 reserved_31_21 :10; - }bit; - UINT32 dw; + }bit; + UINT32 dw; }Iomux_PadType21; typedef struct { int id; - UINT32* reg; - UINT32 reg_offset; - char* func_name[4]; - int reg_type; - int func_sel; - int drv_cur; - int pupd; - //UINT32 value; + UINT32* reg; + UINT32 reg_offset; + char* func_name[4]; + int reg_type; + int func_sel; + int drv_cur; + int pupd; + //UINT32 value; }Iomux_Pad; typedef struct { - void *vbase; - void *pbase; - Iomux_Pad *pads; + void *vbase; + void *pbase; + Iomux_Pad *pads; }Iomux_Object; diff --git a/bsp/fh8620/platform/plat-v2/reset.c b/bsp/fh8620/platform/plat-v2/reset.c index 654a0745e..aa7024169 100644 --- a/bsp/fh8620/platform/plat-v2/reset.c +++ b/bsp/fh8620/platform/plat-v2/reset.c @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,12 +18,12 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + #include #include #include "fh_pmu.h" @@ -32,13 +32,13 @@ void machine_reset(void) { - fh_pmu_write(REG_PMU_SWRST_MAIN_CTRL, 0x7fffffff); + fh_pmu_write(REG_PMU_SWRST_MAIN_CTRL, 0x7fffffff); } void machine_shutdown(void) { - while(1) - ; + while(1) + ; } diff --git a/bsp/fh8620/platform/plat-v2/timer.c b/bsp/fh8620/platform/plat-v2/timer.c index de831db3c..96bcc6f39 100644 --- a/bsp/fh8620/platform/plat-v2/timer.c +++ b/bsp/fh8620/platform/plat-v2/timer.c @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,7 +18,7 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes @@ -43,48 +43,48 @@ static unsigned long long timestamp; rt_uint32_t read_pts(void) { - return GET_REG(REG_PAE_PTS_REG); + return GET_REG(REG_PAE_PTS_REG); } unsigned long long get_ticks(void) { - rt_uint32_t now = read_pts(); - if (now >= lastdec) { - /* normal mode */ - timestamp += now - lastdec; - } else { - now = read_pts(); - if (now >= lastdec) - timestamp += now - lastdec; - else { - /* we have an overflow ... */ - timestamp += now + 0xffffffff - lastdec; - } - } - lastdec = now; - return timestamp / (TICKS_PER_USEC * 10); + rt_uint32_t now = read_pts(); + if (now >= lastdec) { + /* normal mode */ + timestamp += now - lastdec; + } else { + now = read_pts(); + if (now >= lastdec) + timestamp += now - lastdec; + else { + /* we have an overflow ... */ + timestamp += now + 0xffffffff - lastdec; + } + } + lastdec = now; + return timestamp / (TICKS_PER_USEC * 10); } void udelay(unsigned long usec) { - unsigned long long tmp; - rt_uint32_t tmo; - tmo = (usec + 9) / 10; - tmp = get_ticks() + tmo; /* get current timestamp */ + unsigned long long tmp; + rt_uint32_t tmo; + tmo = (usec + 9) / 10; + tmp = get_ticks() + tmo; /* get current timestamp */ - while (get_ticks() < tmp) - /* loop till event */ - /*NOP*/; + while (get_ticks() < tmp) + /* loop till event */ + /*NOP*/; } void rt_timer_handler(int vector, void *param) { - timer *tim = param; + timer *tim = param; - rt_interrupt_enter(); - timer_get_eoi(tim); - rt_tick_increase(); - rt_interrupt_leave(); + rt_interrupt_enter(); + timer_get_eoi(tim); + rt_tick_increase(); + rt_interrupt_leave(); } /** @@ -92,18 +92,18 @@ void rt_timer_handler(int vector, void *param) */ void rt_hw_timer_init() { - timer *tim = (timer *) TMR_REG_BASE; - timer_init(tim); - /* install interrupt handler */ - rt_hw_interrupt_install(TMR0_IRQn, rt_timer_handler, (void *) tim, - "sys_tick"); - rt_hw_interrupt_umask(TMR0_IRQn); + timer *tim = (timer *) TMR_REG_BASE; + timer_init(tim); + /* install interrupt handler */ + rt_hw_interrupt_install(TMR0_IRQn, rt_timer_handler, (void *) tim, + "sys_tick"); + rt_hw_interrupt_umask(TMR0_IRQn); - timer_set_mode(tim, TIMER_MODE_PERIODIC); - timer_set_period(tim, RT_TICK_PER_SECOND, TIMER_CLOCK); - //timer_set_period(tim, RT_TIMER_TICK_PER_SECOND, TIMER_CLOCK); - timer_enable_irq(tim); - timer_enable(tim); + timer_set_mode(tim, TIMER_MODE_PERIODIC); + timer_set_period(tim, RT_TICK_PER_SECOND, TIMER_CLOCK); + //timer_set_period(tim, RT_TIMER_TICK_PER_SECOND, TIMER_CLOCK); + timer_enable_irq(tim); + timer_enable(tim); } diff --git a/bsp/fh8620/platform/plat-v2/timer.h b/bsp/fh8620/platform/plat-v2/timer.h index 5ee024a09..bbccdfa82 100644 --- a/bsp/fh8620/platform/plat-v2/timer.h +++ b/bsp/fh8620/platform/plat-v2/timer.h @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,12 +18,12 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + #ifndef TIMER_H_ #define TIMER_H_ diff --git a/bsp/fh8620/platform/platform_def.h b/bsp/fh8620/platform/platform_def.h index b51186398..a576220f3 100644 --- a/bsp/fh8620/platform/platform_def.h +++ b/bsp/fh8620/platform/platform_def.h @@ -1,8 +1,8 @@ /* * This file is part of FH8620 BSP for RT-Thread distribution. * - * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. - * All rights reserved + * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,12 +18,12 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * - * Visit http://www.fullhan.com to get contact with Fullhan. + * Visit http://www.fullhan.com to get contact with Fullhan. * * Change Logs: * Date Author Notes */ - + #ifndef PLATFORM_DEF_H_ #define PLATFORM_DEF_H_ diff --git a/bsp/fh8620/rtconfig.h b/bsp/fh8620/rtconfig.h index 8b7ce31be..78749abdf 100644 --- a/bsp/fh8620/rtconfig.h +++ b/bsp/fh8620/rtconfig.h @@ -5,19 +5,19 @@ // // -#define RT_NAME_MAX 16 +#define RT_NAME_MAX 16 // -#define RT_ALIGN_SIZE 4 +#define RT_ALIGN_SIZE 4 // // 8 // 32 // 256 // -#define RT_THREAD_PRIORITY_MAX 256 +#define RT_THREAD_PRIORITY_MAX 256 // -#define RT_TICK_PER_SECOND 100 +#define RT_TICK_PER_SECOND 100 // -#define IDLE_THREAD_STACK_SIZE 512 +#define IDLE_THREAD_STACK_SIZE 512 // // #define RT_USING_MODULE // @@ -36,11 +36,11 @@ //
// #define RT_USING_TIMER_SOFT // -#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_PRIO 4 // -#define RT_TIMER_THREAD_STACK_SIZE 512 +#define RT_TIMER_THREAD_STACK_SIZE 512 // -#define RT_TIMER_TICK_PER_SECOND 100 +#define RT_TIMER_TICK_PER_SECOND 100 //
//
@@ -86,13 +86,13 @@ // //#define RT_USING_RTC // -#define RT_MMCSD_THREAD_PREORITY 15 +#define RT_MMCSD_THREAD_PREORITY 15 //
#define RT_USING_CONSOLE // -#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLEBUF_SIZE 128 // -#define RT_CONSOLE_DEVICE_NAME "uart1" +#define RT_CONSOLE_DEVICE_NAME "uart1" //
// @@ -105,7 +105,7 @@ // #define FINSH_USING_DESCRIPTION // -#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_THREAD_STACK_SIZE 4096 //
//
@@ -124,9 +124,9 @@ // #define DFS_USING_WORKDIR // -#define DFS_FILESYSTEMS_MAX 2 +#define DFS_FILESYSTEMS_MAX 2 // -#define DFS_FD_MAX 16 +#define DFS_FD_MAX 16 // #define RT_USING_DFS_ELMFAT // @@ -138,13 +138,13 @@ // 2 // 3 // -#define RT_DFS_ELM_USE_LFN 3 +#define RT_DFS_ELM_USE_LFN 3 // -#define RT_DFS_ELM_CODE_PAGE 936 +#define RT_DFS_ELM_CODE_PAGE 936 // #define RT_DFS_ELM_CODE_PAGE_FILE // -#define RT_DFS_ELM_MAX_LFN 255 +#define RT_DFS_ELM_MAX_LFN 255 // #define RT_DFS_ELM_MAX_SECTOR_SIZE 4096 // @@ -174,19 +174,19 @@ // #define RT_LWIP_DHCP // -#define RT_LWIP_TCPTHREAD_PRIORITY 12 +#define RT_LWIP_TCPTHREAD_PRIORITY 12 // -#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8 +#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8 // -#define RT_LWIP_TCPTHREAD_STACKSIZE 4096 +#define RT_LWIP_TCPTHREAD_STACKSIZE 4096 // -#define RT_LWIP_ETHTHREAD_PRIORITY 14 +#define RT_LWIP_ETHTHREAD_PRIORITY 14 // -#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8 +#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8 // -#define RT_LWIP_ETHTHREAD_STACKSIZE 512 +#define RT_LWIP_ETHTHREAD_STACKSIZE 512 // -#define RT_LWIP_IPADDR "192.168.1.30" +#define RT_LWIP_IPADDR "192.168.1.30" // #define RT_LWIP_GWADDR "192.168.1.1" // -- GitLab