From 2fcd4bccbdc9ebc00ba4de3d4dd9327b325545bc Mon Sep 17 00:00:00 2001 From: dzzxzz Date: Wed, 14 Apr 2010 00:31:17 +0000 Subject: [PATCH] add BSP for Renesas M16C62P git-svn-id: https://rt-thread.googlecode.com/svn/trunk@620 bbd45198-f89e-11dd-88c7-29a3b14d5316 --- bsp/m16c62p/application.c | 52 + bsp/m16c62p/board.c | 36 + bsp/m16c62p/board.h | 21 + bsp/m16c62p/bsp.c | 108 ++ bsp/m16c62p/bsp.h | 30 + bsp/m16c62p/cstartup.s34 | 327 ++++++ bsp/m16c62p/lnkm30627fhp.xcl | 236 +++++ bsp/m16c62p/rtconfig.h | 151 +++ bsp/m16c62p/rtt2m16c.dep | 1572 +++++++++++++++++++++++++++ bsp/m16c62p/rtt2m16c.ewd | 737 +++++++++++++ bsp/m16c62p/rtt2m16c.ewp | 1936 ++++++++++++++++++++++++++++++++++ bsp/m16c62p/rtt2m16c.eww | 10 + bsp/m16c62p/startup.c | 103 ++ bsp/m16c62p/uart.c | 288 +++++ bsp/m16c62p/uart.h | 8 + bsp/m16c62p/vectors.s34 | 68 ++ 16 files changed, 5683 insertions(+) create mode 100644 bsp/m16c62p/application.c create mode 100644 bsp/m16c62p/board.c create mode 100644 bsp/m16c62p/board.h create mode 100644 bsp/m16c62p/bsp.c create mode 100644 bsp/m16c62p/bsp.h create mode 100644 bsp/m16c62p/cstartup.s34 create mode 100644 bsp/m16c62p/lnkm30627fhp.xcl create mode 100644 bsp/m16c62p/rtconfig.h create mode 100644 bsp/m16c62p/rtt2m16c.dep create mode 100644 bsp/m16c62p/rtt2m16c.ewd create mode 100644 bsp/m16c62p/rtt2m16c.ewp create mode 100644 bsp/m16c62p/rtt2m16c.eww create mode 100644 bsp/m16c62p/startup.c create mode 100644 bsp/m16c62p/uart.c create mode 100644 bsp/m16c62p/uart.h create mode 100644 bsp/m16c62p/vectors.s34 diff --git a/bsp/m16c62p/application.c b/bsp/m16c62p/application.c new file mode 100644 index 000000000..22129d300 --- /dev/null +++ b/bsp/m16c62p/application.c @@ -0,0 +1,52 @@ +/* + * File : application.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2009, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2009-01-05 Bernard the first version + * 2010-04-09 fify modified for M16C + * + * For : Renesas M16C + * Toolchain : IAR's EW for M16C v3.401 +*/ + +#include +#include "bsp.h" + +static struct rt_thread led; + +static rt_uint8_t led_stack[256]; + +static void rt_thread_entry_led(void* parameter) +{ + while (1) + { + /* led off */ + led_off(); + rt_thread_delay(100); /* sleep 1 second and switch to other thread */ + /* led on */ + led_on(); + rt_thread_delay(100); + } +} + +int rt_application_init(void) +{ + /* create led thread */ + rt_thread_init(&led, + "led", + rt_thread_entry_led, RT_NULL, + &led_stack[0], sizeof(led_stack), + 5, 32); + + if (&led != RT_NULL) + rt_thread_startup(&led); + + return 0; +} diff --git a/bsp/m16c62p/board.c b/bsp/m16c62p/board.c new file mode 100644 index 000000000..644010079 --- /dev/null +++ b/bsp/m16c62p/board.c @@ -0,0 +1,36 @@ +/* + * File : board.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2009, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2010-04-09 fify the first version + * + * For : Renesas M16C + * Toolchain : IAR's EW for M16C v3.401 +*/ + +#include +#include + +#include "uart.h" +#include "board.h" + +/** + * This function will initial m16c board. + */ +void rt_hw_board_init() +{ +#ifdef RT_USING_UART0 + rt_hw_uart_init(); + rt_console_set_device("uart0"); +#endif + + rt_kprintf("\r\n\r\nSystemInit......\r\n"); +} + diff --git a/bsp/m16c62p/board.h b/bsp/m16c62p/board.h new file mode 100644 index 000000000..1a2664cff --- /dev/null +++ b/bsp/m16c62p/board.h @@ -0,0 +1,21 @@ +/* + * File : board.h + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2009, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2009-09-22 Bernard add board.h to this bsp + * 2010-02-04 Magicoe add board.h to LPC176x bsp + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +void rt_hw_board_init(void); + +#endif diff --git a/bsp/m16c62p/bsp.c b/bsp/m16c62p/bsp.c new file mode 100644 index 000000000..f19616b98 --- /dev/null +++ b/bsp/m16c62p/bsp.c @@ -0,0 +1,108 @@ +/* + * File : bsp.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2009, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2010-04-09 fify the first version + * + * For : Renesas M16C + * Toolchain : IAR's EW for M16C v3.401 +*/ + +#include "iom16c62p.h" +#include "bsp.h" +#include "rtconfig.h" + +void led_init(void) +{ + pu37 = 1; + pd11_0 = 1; + + led_off(); +} + +void led_on(void) +{ + p11_0 = 1; +} + +void led_off(void) +{ + p11_0 = 0; +} + +static void mcu_init(void) +{ + volatile rt_uint32_t count; + /* Configure clock for divide by 1 mode */ + prcr |= 0x01; /* Enable access to clock registers PRCR.PRC0 = 1 */ + cm1 = 0x20; /* Set CM16, CM17 divide ratio to 1: */ + /* ... main clock on in high drive no PLL */ + cm0 &= ~0x40; /* Set divide ratio to 1 CM0.CM06 = 0 */ + + /* Configure main PLL */ + prcr |= 0x02; /* Allow writing to processor mode register PRCR.PRC0 = 1 */ + pm2 |= 0x01; /* Set SFR access to 2 wait, which is required for */ + /* ... operation greater than 16 MHz PM2.PM20 = 1 */ + prcr &= ~0x02; /* Protect processor mode register PRCR.PRC0 = 0 */ + plc0 = 0x91; /* Enable and turn on PLL */ + + count = 20000; /* Delay while PLL stabilizes */ + while (count > 0) { + count--; + } + + cm1 |= 0x02; /* Switch to PLL CM1.CM11 = 1 */ + prcr &= ~0x01; /* Protect clock control register PRCR.PRC0 = 0 */ + + prcr |= 0x02; /* Allow writing to processor mode register PRCR.PRC0 = 1 */ + pm1 |= 0x01; /* Enable data flash area PM1.PM10 = 1 */ + prcr &= ~0x02; /* Protect processor mode register PRCR.PRC0 = 0 */ +} + +/* +********************************************************************************************************* +* TICKER INITIALIZATION +* +* Description : This function is called to initialize rt-thread's tick source (typically a timer generating +* interrupts every 1 to 100 mS). +* +* We decided to use Timer #B0 as the tick interrupt source. +* +* Arguments : none +* +* Returns : +* +* Notes : (1) Timer B channel 0 is setup as a periodic timer, generating an interrupt +* OS_TICKS_PER_SEC times per second. The timer counts down and generates an interrupt +* when it underflows. +* +* (2) The timer ISR handler, rt_hw_timer_handler(), is placed into the vector table in vectors.s34. +********************************************************************************************************* +*/ + +static void timer_tick_init(void) +{ + /* Set timer to timer mode */ + /* Set count source as PLL clock / 8 (f8) */ + tb0mr = 0x40; + /* Assign timer value and reload value */ + tb0 = (CPU_CLK_FREQ / 8) / RT_TICK_PER_SECOND; + /* Set timer B channel 0 interrupt level = 7 */ + /* Clear interrupt request */ + tb0ic = 0x07; + tabsr |= 0x20; /* Start timer */ +} + +void system_init(void) +{ + mcu_init(); + led_init(); /* Initialize the I/Os for the LED controls */ + timer_tick_init(); /* Initialize the rt-thread tick interrupt */ +} diff --git a/bsp/m16c62p/bsp.h b/bsp/m16c62p/bsp.h new file mode 100644 index 000000000..248a183b1 --- /dev/null +++ b/bsp/m16c62p/bsp.h @@ -0,0 +1,30 @@ +/* + * File : bsp.h + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2009, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2010-04-09 fify the first version + * + * For : Renesas M16C + * Toolchain : IAR's EW for M16C v3.401 +*/ + +#ifndef __BSP_H__ +#define __BSP_H__ + +#include + +#define CPU_CLK_FREQ 14000000 /* CPU frequency, in Hz*/ + +void system_init(void); + +void led_on(void); +void led_off(void); + +#endif diff --git a/bsp/m16c62p/cstartup.s34 b/bsp/m16c62p/cstartup.s34 new file mode 100644 index 000000000..9bded3e3a --- /dev/null +++ b/bsp/m16c62p/cstartup.s34 @@ -0,0 +1,327 @@ +;----------------------------------------------------------------------- +; +; This file contains the M16C C startup routine and must usually +; be tailored to suit customer's hardware. +; +; Copyright 2002 IAR Systems. All rights reserved. +; +; $Revision: 1.16 $ +; +;----------------------------------------------------------------------- + + MODULE ?cstart + + PUBLIC __program_start + PUBLIC __data16_init + PUBLIC __data16_zero + PUBLIC ?cstart_call_ctors + + EXTERN main + EXTERN exit + EXTERN __call_ctors + EXTERN __low_level_init + EXTERN ?GENERIC_MOVE_LONG_L08 + EXTERN RelocatableVectTbl + + ;------------------------------------------------------ + ; Useful macros + ;------------------------------------------------------ + + ; Load 24-bit constant value to (high,low) +LD24 MACRO value,high,low + MOV.B #BYTE3(value),high + MOV.W #LWRD(value),low + ENDM + + ; Load 32-bit constant value to (high,low) +LD32 MACRO value,high,low + MOV.W #HWRD(value),high + MOV.W #LWRD(value),low + ENDM + + ; Load a stack-pointer with last even address of segment +LDSTACK MACRO segment,reg + LDC #sfe(segment), reg + ENDM + + + ;------------------------------------------------------ + ; __program_start - Reset vector should point to here. + ; + ; Calls __low_level_init to perform initialization + ; before initializing segments and calling main. + ; If the function returns 0 no segment initialization + ; should take place. + ; + ; Link with your own version of __low_level_init to + ; override the default action: do nothing but return 1. + ;------------------------------------------------------ + + RSEG CSTACK + RSEG ISTACK + RSEG CSTART:CODE:NOROOT + REQUIRE call_main + +__program_start: + LDC #sfe(ISTACK), ISP ; Set up interrupt stack + FSET I ; Select interrupt stack + LDC #sfe(CSTACK), SP ; Set up C stack + LDINTB #RelocatableVectTbl ; Set up INTB register + JSR.A __low_level_init ; Call __low_level_init + + ;----------------------------------------------------------- + ; Run-time test whether we should do segment initialization + ;----------------------------------------------------------- + TST.B R0L, R0L + JNE do_segment_init + JMP skip_segment_init + +do_segment_init: + + ;------------------------------------------------------ + ; Perform segment initialization of DATA16 memory. + ;------------------------------------------------------ + + RSEG DATA16_Z + RSEG CSTART:CODE:NOROOT + +__data16_zero: + MOV.W #sizeof(DATA16_Z), R3 + MOV.W #sfb(DATA16_Z), A1 + MOV.B #0, R0L + SSTR.B + + RSEG DATA16_I + RSEG DATA16_ID + RSEG CSTART:CODE:NOROOT + +__data16_init: + MOV.W #sizeof(DATA16_ID), R3 + MOV.W #sfb(DATA16_I), A1 + LD24 sfb(DATA16_ID), R1H, A0 + SMOVF.B + + + + RSEG CSTART:CODE:NOROOT +skip_segment_init: + ; Fall through to next required CSTART segment part + + + ;------------------------------------------------------ + ; Call constructors + ;------------------------------------------------------ + + RSEG DIFUNCT + RSEG CSTART:CODE:NOROOT + + PUBLIC ?cstart_call_ctors + EXTERN __call_ctors + +?cstart_call_ctors: + PUSH.W #HWRD(sfe(DIFUNCT)) + PUSH.W #LWRD(sfe(DIFUNCT)) + LD32 sfb(DIFUNCT),R2,R0 + JSR.A __call_ctors + + + ; Fall through to next required CSTART segment part + + + ;------------------------------------------------------ + ; Call main and exit + ;------------------------------------------------------ + + ; This segment part is marked as ROOT, since it must + ; be preserved by the linker. + ; + RSEG CSTART:CODE:NOROOT + +call_main: + MOV.W #0, R0 ; Call main with argc = 0 + JSR.A main + JMP.A exit ; Argument to exit is return value of main + + ;------------------------------------------------------ + ; Fixed interrupt table. + ; + ; We install all fixed interrupts in a segment called + ; INTVEC1. All fixed interrupts have a hard coded name. + ; Write an interrupt handler in C using this name, with + ; no vector specification, and it will replace the + ; default handler. + ;------------------------------------------------------ + + EXTERN __undefined_instruction_handler + EXTERN __overflow_handler + EXTERN __break_instruction_handler + EXTERN __address_match_handler + EXTERN __single_step_handler + EXTERN __watchdog_timer_handler + EXTERN __DBC_handler + EXTERN __NMI_handler + + ; Labels for the ID Code Check Function. + ; (To be initialized in the linker file) + EXTERN _ID_CODE_1 + EXTERN _ID_CODE_2 + EXTERN _ID_CODE_3 + EXTERN _ID_CODE_4 + EXTERN _ID_CODE_5 + EXTERN _ID_CODE_6 + EXTERN _ID_CODE_7 + EXTERN _OFS_VALUE + + PUBLIC ??intvec_start + + COMMON INTVEC1:NOROOT +??intvec_start: + DC24 __undefined_instruction_handler + DC8 _ID_CODE_1 + DC24 __overflow_handler + DC8 _ID_CODE_2 + DC24 __break_instruction_handler + DC8 0 + DC24 __address_match_handler + DC8 _ID_CODE_3 + DC24 __single_step_handler + DC8 _ID_CODE_4 + DC24 __watchdog_timer_handler + DC8 _ID_CODE_5 + DC24 __DBC_handler + DC8 _ID_CODE_6 + DC24 __NMI_handler + DC8 _ID_CODE_7 + DC24 __program_start ; Reset vector + DC8 _OFS_VALUE + + ENDMOD + + + ;------------------------------------------------------ + ; Default handlers for fixed interrupts + ;------------------------------------------------------ + + MODULE __undefined_instruction + EXTERN ??reit + REQUIRE ??reit + PUBLIC __undefined_instruction_handler + RSEG CSTART:CODE:NOROOT(1) +__undefined_instruction_handler: + ; Fall through to ??reit + ENDMOD + + MODULE __overflow + EXTERN ??reit + REQUIRE ??reit + PUBLIC __overflow_handler + RSEG CSTART:CODE:NOROOT(1) +__overflow_handler: + ; Fall through to ??reit + ENDMOD + + MODULE __break_instruction + EXTERN ??reit + REQUIRE ??reit + PUBLIC __break_instruction_handler + RSEG CSTART:CODE:NOROOT(1) +__break_instruction_handler: + ; Fall through to ??reit + ENDMOD + + MODULE __address_match + EXTERN ??reit + REQUIRE ??reit + PUBLIC __address_match_handler + RSEG CSTART:CODE:NOROOT(1) +__address_match_handler: + ; Fall through to ??reit + ENDMOD + + MODULE __single_step + EXTERN ??reit + REQUIRE ??reit + PUBLIC __single_step_handler + RSEG CSTART:CODE:NOROOT(1) +__single_step_handler: + ; Fall through to ??reit + ENDMOD + + MODULE __watchdog_timer + EXTERN ??reit + REQUIRE ??reit + PUBLIC __watchdog_timer_handler + RSEG CSTART:CODE:NOROOT(1) +__watchdog_timer_handler: + ; Fall through to ??reit + ENDMOD + + MODULE __DBC + EXTERN ??reit + REQUIRE ??reit + PUBLIC __DBC_handler + RSEG CSTART:CODE:NOROOT(1) +__DBC_handler: + ; Fall through to ??reit + ENDMOD + + MODULE __NMI + EXTERN ??reit + REQUIRE ??reit + PUBLIC __NMI_handler + RSEG CSTART:CODE:NOROOT(1) +__NMI_handler: + ; Fall through to ??reit + ENDMOD + + ;------------------------------------------------------ + ; Return from interrupt + ;------------------------------------------------------ + MODULE __reit + PUBLIC ??reit + RSEG CSTART:CODE:NOROOT(1) + EXTERN ??intvec_start + REQUIRE ??intvec_start +??reit: + REIT + + ENDMOD + + + ;------------------------------------------------------ + ; FUNCTION: __low_level_init + ; + ; You can replace this routine by linking with your + ; own version. + ; + ; The default action is to do nothing and return 1. + ;------------------------------------------------------ + + MODULE __low_level_init + PUBLIC __low_level_init + RSEG CSTART:CODE:NOROOT + +__low_level_init: + MOV.B #1,R0L + RTS + + ENDMOD + + + ;------------------------------------------------------ + ; __overflow - This variable is used by the intrinsic + ; functions __RMPA_W_overflow and + ; __RMPA_B_overflow. + ;------------------------------------------------------ + + MODULE __overflow + PUBLIC __overflow + EXTERN __data13_zero + + RSEG DATA13_Z:NEAR:NOROOT + +__overflow: + DC8 0 + REQUIRE __data13_zero + + END diff --git a/bsp/m16c62p/lnkm30627fhp.xcl b/bsp/m16c62p/lnkm30627fhp.xcl new file mode 100644 index 000000000..3471b20ca --- /dev/null +++ b/bsp/m16c62p/lnkm30627fhp.xcl @@ -0,0 +1,236 @@ +//================================================================ +// +// IAR XLINK command file for the IAR C/C++ Compiler for +// Renesas M16C/R8C +// +// This is an example XLINK command file for use with the +// M30627FHP derivative. +// +// Derivative group: m16c 62p +// +// +// Usage: xlink your_file(s) -f this_file clm16c*.r48 +// +// Copyright 2001-2008 IAR Systems AB. +// +// $Revision: 2144 $ +// +//================================================================ + +//================================================================ +// The M16C IAR C/EC++ Compiler places code and data into named +// segments which are referred to by the IAR XLINK Linker. The +// table below shows the available segments. +// +// SEGMENT REFERENCE +// ================= +// +// Segment Description +// ------- ----------- +// BITVARS Bit variables. +// CODE The program code. +// CSTACK The stack used by C or Embedded C++ programs. +// CSTART The startup code. +// DATA16_HEAP Heap data used by malloc and free. Used by CLib and DLib +// FAR_HEAP Heap used by malloc and free in DLib +// DATA20_HEAP Heap used by malloc and free in DLib +// +// x_AC Non-initialized located const objects. +// x_AN Non-initialized located non-const objects. +// x_C Constant data, including string literals. +// x_I Initialized data. +// x_ID Data that is copied to x_I by cstartup. +// x_N Uninitialized data. +// x_Z zero initialized data. +// +// Where x can be one of: +// DATA13 (Range: 0-0x1FFF) +// DATA16 (Range: 0-0xFFFF, except DATA16_ID) +// DATA20 (Range: 0-0xFFFFF) +// FAR (Range: 0-0xFFFFF) +// +// DIFUNCT Pointers to code, typically EC++ constructors +// FLIST Jump table for __tiny_func functions. +// INTVEC Contains reset and interrupt vectors. +// INTVEC1 Contains the fixed reset and interrupt vectors. +// ISTACK The stack used by interrupts and exceptions. +//================================================================ + +// Define CPU +-cm16c + +//================================================================ +// USER DEFINITIONS +// Please customize according to your preferences. +//================================================================ + +// Size of the user stack +// Uncomment for command line use +//-D_CSTACK_SIZE=100 + +// Size of the interrupt stack +// Uncomment for command line use +//-D_ISTACK_SIZE=40 + +// Size of the heap +// Uncomment for command line use +//-D_DATA16_HEAP_SIZE=400 +//-D_FAR_HEAP_SIZE=400 +//-D_DATA20_HEAP_SIZE=400 + +// Reserved memory +// Reservation of RAM and ROM memory not to be used by the application. +// Preset for use with the E8 emulator. +// NOTE! Set these values to zero to utilize the whole RAM and ROM memory. +-D_RESERVED_RAM_SIZE=80 +-D_RESERVED_ROM_SIZE=800 + +//================================================================ +// Memory Definitions +//================================================================ + +// Memory areas available for the application +-D_USER_RAM_BEGIN=(00400+_RESERVED_RAM_SIZE) +-D_USER_RAM_END=07FFF +-D_DATA_FLASH_BEGIN=0F000 +-D_DATA_FLASH_END=0FFFF +-D_USER_ROM_BEGIN=(A0000+_RESERVED_ROM_SIZE) +-D_USER_ROM_END=FFFFF + +// Relocatable "bit" segment (must be in near area). +// As BITVARS contains bit addresses, the address has to be recalculated. +// Byte address 400 --> 400 * 8 = bit address 2000 +-D_BITVAR_BEGIN=2000 // address 400 +-D_BITVAR_END=FFFF // address 1FFF + +// ID code and OFS value written to ROM memory +-D_ID_CODE_1=FF +-D_ID_CODE_2=FF +-D_ID_CODE_3=FF +-D_ID_CODE_4=FF +-D_ID_CODE_5=FF +-D_ID_CODE_6=FF +-D_ID_CODE_7=FF +-D_OFS_VALUE=FF + +// _OFS2_VALUE has to be defined. It is only used in some R8C devices and will +// not result in any additional code or data for any other device. +-D_OFS2_VALUE=FF + +// ======================= +// DATA13 RAM +// ======================= + +-Z(NEAR)DATA13_AN=0-01FFF +-Z(NEAR)DATA13_I=_USER_RAM_BEGIN-01FFF +-Z(NEAR)DATA13_Z,DATA13_N=_USER_RAM_BEGIN-01FFF + +// Relocatable "bit" segment. As BITVARS contains bit addresses, +// the desired (byte) address has to be multiplied by 8. +-Z(BIT)BITVARS=_BITVAR_BEGIN-_BITVAR_END + +// ======================= +// DATA16 RAM +// ======================= + +// Set up interrupt stack +-Z(NEAR)ISTACK+_ISTACK_SIZE#_USER_RAM_BEGIN-_USER_RAM_END + +// Set up user stack +-Z(NEAR)CSTACK+_CSTACK_SIZE#_USER_RAM_BEGIN-_USER_RAM_END + +// Set up near heap +-Z(NEAR)DATA16_HEAP+_DATA16_HEAP_SIZE=_USER_RAM_BEGIN-_USER_RAM_END + +// Near variables +-Z(NEAR)DATA16_I,DATA16_Z,DATA16_N,DATA16_AN=_USER_RAM_BEGIN-_USER_RAM_END + +// User defined near DATA segments + + +// ======================= +// DATA16 ROM +// ======================= +// Data flash +-Z(CONST)DATA_FLASH=_DATA_FLASH_BEGIN-_DATA_FLASH_END + +// Constant segments (in ROM), reachable for near pointers +// (Use declaration -Z(CONST)DATA16_C if near ROM exists) + +// User defined near CONST segments + +// ======================= +// FAR/DATA20 RAM +// ======================= + +// Far and huge data segments +-Z(FAR)FAR_I,FAR_Z,FAR_N,FAR_AN=_USER_RAM_BEGIN-_USER_RAM_END +-Z(FAR)FAR_HEAP+_FAR_HEAP_SIZE=_USER_RAM_BEGIN-_USER_RAM_END +-Z(HUGE)DATA20_I,DATA20_Z,DATA20_N,DATA20_AN=_USER_RAM_BEGIN-_USER_RAM_END +-Z(HUGE)DATA20_HEAP+_DATA20_HEAP_SIZE=_USER_RAM_BEGIN-_USER_RAM_END + +// User defined far & huge DATA segments + +// ======================= +// FAR/DATA20 ROM +// ======================= + +// Fixed interrupt vector table +-Z(CONST)INTVEC1=FFFDC-FFFFF + + +// Special page table +-Z(CONST)FLIST=FFE00-FFFDB + +// Variable vector table (growing downwards from _USER_ROM_END) +// The added -1 is too assure that all vectors start at even +// addresses. +-Z(CONST)INTVEC=D0000-(_USER_ROM_END-1) + +// Constant and initializer segments (in ROM) +-Z(FARCONST)FAR_ID=_USER_ROM_BEGIN-_USER_ROM_END +-Z(FARCONST)FAR_C=_USER_ROM_BEGIN-_USER_ROM_END +-Z(HUGECONST)DATA20_C,DATA20_ID,CHECKSUM=_USER_ROM_BEGIN-_USER_ROM_END +-Z(FARCONST)DATA16_ID,DATA13_ID,DIFUNCT=_USER_ROM_BEGIN-_USER_ROM_END + +// User defined far & huge CONST segments + +// CODE segments +// TINYFUNC code must be located above 0xF0000 +-P(CODE)TINYFUNC=F0000-_USER_ROM_END + +// Startup code +-P(CODE)CSTART=D0000-_USER_ROM_END + +// "Regular" code +-P(CODE)CODE=_USER_ROM_BEGIN-_USER_ROM_END +// User defined CODE segments + +// ======================== +// IAR C library formatting +// ======================== + +// Uncomment for command line use +//-e_small_write=_formatted_write +//-e_medium_read=_formatted_read + +// ======================== +// Output files +// ======================== +// Use the -O option to create one or more output files +// at the same link session. Formats flags, file name and +// extension is optional. Please un-comment the wanted +// output formats below. +// +// CAUTION: Do not combine other output formats with -rt (special +// UBROF for Terminal I/O in C-SPY). Output files are valid but +// contain code that expects to be run under C-SPY. + +// Motorola output +//-Omotorola=.mot + +// IEEE-695 output with format flags for the Renesas debugger +//-Oieee695,lbm=.x30 + +// ELF/DWARF output with format flags for the Renesas debugger +//-Oelf,spc=.elf diff --git a/bsp/m16c62p/rtconfig.h b/bsp/m16c62p/rtconfig.h new file mode 100644 index 000000000..01fded108 --- /dev/null +++ b/bsp/m16c62p/rtconfig.h @@ -0,0 +1,151 @@ +/* RT-Thread config file */ +#ifndef __RTTHREAD_CFG_H__ +#define __RTTHREAD_CFG_H__ + +/* RT_NAME_MAX*/ +#define RT_NAME_MAX 8 + +/* RT_ALIGN_SIZE*/ +#define RT_ALIGN_SIZE 4 + +/* PRIORITY_MAX */ +#define RT_THREAD_PRIORITY_MAX 32 + +/* Tick per Second */ +#define RT_TICK_PER_SECOND 100 + +/* SECTION: RT_DEBUG */ +/* Thread Debug */ +#define RT_DEBUG +///#define SCHEDULER_DEBUG + +#define RT_USING_OVERFLOW_CHECK + +/* Using Hook */ +///#define RT_USING_HOOK + +/* Using Software Timer */ +/* #define RT_USING_TIMER_SOFT */ +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 512 +#define RT_TIMER_TICK_PER_SECOND 10 + +/* SECTION: IPC */ +/* Using Semaphore */ +#define RT_USING_SEMAPHORE + +/* Using Mutex */ +#define RT_USING_MUTEX + +/* Using Event */ +#define RT_USING_EVENT + +/* Using MailBox */ +#define RT_USING_MAILBOX + +/* Using Message Queue */ +#define RT_USING_MESSAGEQUEUE + +/* SECTION: Memory Management */ +/* Using Memory Pool Management*/ +#define RT_USING_MEMPOOL + +/* Using Dynamic Heap Management */ +#define RT_USING_HEAP + +/* Using Small MM */ +#define RT_USING_SMALL_MEM + +/* SECTION: Device System */ +/* Using Device System */ +#define RT_USING_DEVICE +/* RT_USING_UART */ +#define RT_USING_UART0 +#define RT_UART_RX_BUFFER_SIZE 64 + +/* SECTION: Console options */ +/* the buffer size of console */ +#define RT_CONSOLEBUF_SIZE 128 + +/* SECTION: finsh, a C-Express shell */ +/* Using FinSH as Shell*/ +#define RT_USING_FINSH +/* Using symbol table */ +///#define FINSH_USING_SYMTAB +///#define FINSH_USING_DESCRIPTION + +/* SECTION: device filesystem support */ +/* #define RT_USING_DFS */ +///#define RT_USING_DFS_ELMFAT + +/* the max number of mounted filesystem */ +///#define DFS_FILESYSTEMS_MAX 2 +/* the max number of opened files */ +///#define DFS_FD_MAX 4 +/* the max number of cached sector */ +///#define DFS_CACHE_MAX_NUM 4 + +/* SECTION: lwip, a lighwight TCP/IP protocol stack */ +//#define RT_USING_LWIP + +/* Enable ICMP protocol*/ +///#define RT_LWIP_ICMP +/* Enable UDP protocol*/ +///#define RT_LWIP_UDP +/* Enable TCP protocol*/ +///#define RT_LWIP_TCP +/* Enable DNS */ +///#define RT_LWIP_DNS + +/* the number of simulatenously active TCP connections*/ +///#define RT_LWIP_TCP_PCB_NUM 5 + +/* ip address of target*/ +///#define RT_LWIP_IPADDR0 192 +///#define RT_LWIP_IPADDR1 168 +///#define RT_LWIP_IPADDR2 1 +///#define RT_LWIP_IPADDR3 30 + +/* gateway address of target*/ +#define RT_LWIP_GWADDR0 192 +#define RT_LWIP_GWADDR1 168 +#define RT_LWIP_GWADDR2 1 +#define RT_LWIP_GWADDR3 1 + +/* mask address of target*/ +#define RT_LWIP_MSKADDR0 255 +#define RT_LWIP_MSKADDR1 255 +#define RT_LWIP_MSKADDR2 255 +#define RT_LWIP_MSKADDR3 0 + +/* tcp thread options */ +#define RT_LWIP_TCPTHREAD_PRIORITY 12 +#define RT_LWIP_TCPTHREAD_MBOX_SIZE 4 +#define RT_LWIP_TCPTHREAD_STACKSIZE 1024 + +/* ethernet if thread options */ +#define RT_LWIP_ETHTHREAD_PRIORITY 15 +#define RT_LWIP_ETHTHREAD_MBOX_SIZE 4 +#define RT_LWIP_ETHTHREAD_STACKSIZE 512 + +/* SECTION: RT-Thread/GUI */ +/* #define RT_USING_RTGUI */ + +/* name length of RTGUI object */ +#define RTGUI_NAME_MAX 12 +/* support 16 weight font */ +#define RTGUI_USING_FONT16 +/* support Chinese font */ +#define RTGUI_USING_FONTHZ +/* use DFS as file interface */ +#define RTGUI_USING_DFS_FILERW +/* use font file as Chinese font */ +#define RTGUI_USING_HZ_FILE +/* use small size in RTGUI */ +#define RTGUI_USING_SMALL_SIZE +/* use mouse cursor */ +/* #define RTGUI_USING_MOUSE_CURSOR */ +/* default font size in RTGUI */ +#define RTGUI_DEFAULT_FONT_SIZE 16 + +#endif diff --git a/bsp/m16c62p/rtt2m16c.dep b/bsp/m16c62p/rtt2m16c.dep new file mode 100644 index 000000000..b4dd7fbb2 --- /dev/null +++ b/bsp/m16c62p/rtt2m16c.dep @@ -0,0 +1,1572 @@ + + + + 2 + 1321277198 + + Debug + + $PROJ_DIR$\Debug\Obj\finsh_compiler.r34 + $PROJ_DIR$\application.c + $PROJ_DIR$\board.c + $PROJ_DIR$\bsp.c + $PROJ_DIR$\cstartup.s34 + $PROJ_DIR$\lnkm30627fhp.xcl + $PROJ_DIR$\rtconfig.h + $PROJ_DIR$\startup.c + $PROJ_DIR$\uart.c + $PROJ_DIR$\vectors.s34 + $PROJ_DIR$\..\..\finsh\cmd.c + $PROJ_DIR$\..\..\finsh\finsh.h + $PROJ_DIR$\..\..\finsh\finsh_compiler.c + $PROJ_DIR$\..\..\finsh\finsh_error.c + $PROJ_DIR$\..\..\finsh\finsh_error.h + $PROJ_DIR$\..\..\finsh\finsh_heap.c + $PROJ_DIR$\..\..\finsh\finsh_heap.h + $PROJ_DIR$\..\..\finsh\finsh_init.c + $PROJ_DIR$\..\..\finsh\finsh_node.c + $PROJ_DIR$\..\..\finsh\finsh_node.h + $PROJ_DIR$\..\..\finsh\finsh_ops.c + $PROJ_DIR$\..\..\finsh\finsh_ops.h + $PROJ_DIR$\..\..\finsh\finsh_parser.c + $PROJ_DIR$\..\..\finsh\finsh_parser.h + $PROJ_DIR$\..\..\finsh\finsh_token.c + $PROJ_DIR$\..\..\finsh\finsh_token.h + $PROJ_DIR$\..\..\finsh\finsh_var.c + $PROJ_DIR$\..\..\finsh\finsh_var.h + $PROJ_DIR$\..\..\finsh\finsh_vm.c + $PROJ_DIR$\..\..\finsh\finsh_vm.h + $PROJ_DIR$\..\..\finsh\shell.c + $PROJ_DIR$\Debug\Obj\finsh_node.r34 + $PROJ_DIR$\Debug\Obj\finsh_ops.r34 + $PROJ_DIR$\Debug\Obj\slab.r34 + $PROJ_DIR$\Debug\Obj\idle.r34 + $PROJ_DIR$\Debug\Obj\shell.pbi + $PROJ_DIR$\Debug\Obj\application.pbi + $PROJ_DIR$\Debug\Obj\uart.r34 + $PROJ_DIR$\Debug\Obj\finsh_var.r34 + $PROJ_DIR$\Debug\Obj\finsh_token.r34 + $PROJ_DIR$\Debug\Obj\irq.r34 + $PROJ_DIR$\Debug\Obj\timer.r34 + $PROJ_DIR$\Debug\Obj\mem.pbi + $PROJ_DIR$\Debug\Obj\finsh_vm.r34 + $PROJ_DIR$\Debug\Obj\irq.pbi + $PROJ_DIR$\Debug\Obj\ipc.r34 + $PROJ_DIR$\Debug\Obj\bsp.pbi + $PROJ_DIR$\Debug\Obj\bsp.r34 + $PROJ_DIR$\Debug\Obj\vectors.r34 + $PROJ_DIR$\Debug\Obj\shell.r34 + $PROJ_DIR$\Debug\Obj\finsh_parser.r34 + $PROJ_DIR$\Debug\Exe\rtt2m16c.d34 + $PROJ_DIR$\Debug\Obj\finsh_token.pbi + $PROJ_DIR$\Debug\Obj\mempool.r34 + $PROJ_DIR$\Debug\Obj\slab.pbi + $PROJ_DIR$\Debug\Obj\thread.pbi + $PROJ_DIR$\Debug\Obj\object.r34 + $PROJ_DIR$\Debug\Obj\scheduler.r34 + $PROJ_DIR$\Debug\Obj\finsh_parser.pbi + $PROJ_DIR$\Debug\Obj\startup.r34 + $PROJ_DIR$\Debug\Obj\application.r34 + $PROJ_DIR$\Debug\Obj\cmd.r34 + $PROJ_DIR$\Debug\Obj\rtt2m16c.pbd + $PROJ_DIR$\Debug\Obj\device.pbi + $PROJ_DIR$\Debug\Obj\symbol.pbi + $PROJ_DIR$\Debug\Obj\stack.r34 + $PROJ_DIR$\uart.h + $PROJ_DIR$\Debug\Obj\stack.pbi + $PROJ_DIR$\Debug\Obj\finsh_var.pbi + $PROJ_DIR$\Debug\Obj\interrupt.pbi + $PROJ_DIR$\Debug\Obj\device.r34 + $PROJ_DIR$\Debug\Obj\thread.r34 + $PROJ_DIR$\Debug\Obj\ipc.pbi + $PROJ_DIR$\Debug\Obj\cstartup.r34 + $PROJ_DIR$\Debug\Obj\interrupt.r34 + $PROJ_DIR$\Debug\Obj\board.r34 + $PROJ_DIR$\Debug\Obj\scheduler.pbi + $PROJ_DIR$\Debug\Obj\clock.r34 + $PROJ_DIR$\Debug\Obj\idle.pbi + $PROJ_DIR$\Debug\Obj\finsh_compiler.pbi + $PROJ_DIR$\Debug\Obj\finsh_heap.r34 + $TOOLKIT_DIR$\inc\iom16c62p.h + $PROJ_DIR$\Debug\Obj\uart.pbi + $PROJ_DIR$\Debug\Obj\finsh_ops.pbi + $PROJ_DIR$\board.h + $PROJ_DIR$\Debug\Obj\object.pbi + $PROJ_DIR$\Debug\Obj\finsh_heap.pbi + $PROJ_DIR$\Debug\Obj\startup.pbi + $PROJ_DIR$\bsp.h + $PROJ_DIR$\Debug\Obj\cmd.pbi + $PROJ_DIR$\Debug\Obj\context.r34 + $PROJ_DIR$\Debug\Obj\finsh_error.r34 + $PROJ_DIR$\Debug\Obj\finsh_init.r34 + $PROJ_DIR$\..\..\finsh\symbol.c + $PROJ_DIR$\..\..\include\rtdef.h + $PROJ_DIR$\..\..\include\rthw.h + $PROJ_DIR$\..\..\include\rtthread.h + $PROJ_DIR$\..\..\src\clock.c + $PROJ_DIR$\..\..\src\device.c + $PROJ_DIR$\..\..\src\idle.c + $PROJ_DIR$\..\..\src\ipc.c + $PROJ_DIR$\..\..\src\irq.c + $PROJ_DIR$\..\..\src\kservice.c + $PROJ_DIR$\..\..\src\kservice.h + $PROJ_DIR$\..\..\src\mem.c + $PROJ_DIR$\..\..\src\mempool.c + $PROJ_DIR$\..\..\src\object.c + $PROJ_DIR$\..\..\src\scheduler.c + $PROJ_DIR$\..\..\src\slab.c + $PROJ_DIR$\..\..\src\thread.c + $PROJ_DIR$\..\..\src\timer.c + $PROJ_DIR$\..\..\libcpu\m16c\context.asm + $PROJ_DIR$\..\..\libcpu\m16c\interrupt.c + $PROJ_DIR$\..\..\libcpu\m16c\stack.c + $PROJ_DIR$\Debug\Obj\kservice.pbi + $PROJ_DIR$\Debug\Obj\kservice.r34 + $PROJ_DIR$\Debug\Obj\symbol.r34 + $PROJ_DIR$\Debug\Obj\mem.r34 + $PROJ_DIR$\Debug\Obj\finsh_init.pbi + $PROJ_DIR$\Debug\Obj\timer.pbi + $PROJ_DIR$\Debug\Obj\finsh_error.pbi + $PROJ_DIR$\Debug\Obj\finsh_node.pbi + $PROJ_DIR$\Debug\Obj\clock.pbi + $PROJ_DIR$\Debug\Obj\mempool.pbi + $PROJ_DIR$\Debug\Obj\finsh_vm.pbi + $PROJ_DIR$\Debug\Obj\board.pbi + + + $PROJ_DIR$\application.c + + + ICCM16C + 60 + + + BICOMP + 36 + + + + + BICOMP + 96 94 6 88 + + + + + $PROJ_DIR$\board.c + + + ICCM16C + 75 + + + BICOMP + 125 + + + + + BICOMP + 95 96 94 6 66 84 + + + + + $PROJ_DIR$\bsp.c + + + ICCM16C + 47 + + + BICOMP + 46 + + + + + BICOMP + 81 88 96 94 6 + + + + + $PROJ_DIR$\cstartup.s34 + + + AM16C + 73 + + + + + $PROJ_DIR$\startup.c + + + ICCM16C + 59 + + + BICOMP + 87 + + + + + BICOMP + 95 96 94 6 81 84 88 + + + + + $PROJ_DIR$\uart.c + + + ICCM16C + 37 + + + BICOMP + 82 + + + + + BICOMP + 95 96 94 6 81 88 66 + + + + + $PROJ_DIR$\vectors.s34 + + + AM16C + 48 + + + + + $PROJ_DIR$\..\..\finsh\cmd.c + + + ICCM16C + 61 + + + BICOMP + 89 + + + + + BICOMP + 96 94 6 11 + + + + + $PROJ_DIR$\..\..\finsh\finsh_compiler.c + + + ICCM16C + 0 + + + BICOMP + 79 + + + + + BICOMP + 11 96 94 6 19 14 27 21 29 + + + + + $PROJ_DIR$\..\..\finsh\finsh_error.c + + + ICCM16C + 91 + + + BICOMP + 120 + + + + + BICOMP + 14 11 96 94 6 + + + + + $PROJ_DIR$\..\..\finsh\finsh_heap.c + + + ICCM16C + 80 + + + BICOMP + 86 + + + + + BICOMP + 11 96 94 6 27 + + + + + $PROJ_DIR$\..\..\finsh\finsh_init.c + + + ICCM16C + 92 + + + BICOMP + 118 + + + + + BICOMP + 11 96 94 6 19 29 27 23 14 16 + + + + + $PROJ_DIR$\..\..\finsh\finsh_node.c + + + ICCM16C + 31 + + + BICOMP + 121 + + + + + BICOMP + 11 96 94 6 19 14 27 16 + + + + + $PROJ_DIR$\..\..\finsh\finsh_ops.c + + + ICCM16C + 32 + + + BICOMP + 83 + + + + + BICOMP + 21 29 11 96 94 6 27 + + + + + $PROJ_DIR$\..\..\finsh\finsh_parser.c + + + ICCM16C + 50 + + + BICOMP + 58 + + + + + BICOMP + 11 96 94 6 25 19 14 23 27 + + + + + $PROJ_DIR$\..\..\finsh\finsh_token.c + + + ICCM16C + 39 + + + BICOMP + 52 + + + + + BICOMP + 11 96 94 6 25 14 + + + + + $PROJ_DIR$\..\..\finsh\finsh_var.c + + + ICCM16C + 38 + + + BICOMP + 68 + + + + + BICOMP + 11 96 94 6 27 + + + + + $PROJ_DIR$\..\..\finsh\finsh_vm.c + + + ICCM16C + 43 + + + BICOMP + 124 + + + + + BICOMP + 11 96 94 6 29 27 21 + + + + + $PROJ_DIR$\..\..\finsh\shell.c + + + ICCM16C + 49 + + + BICOMP + 35 + + + + + BICOMP + 96 94 6 95 11 + + + + + [ROOT_NODE] + + + XLINK + 51 + + + + + $PROJ_DIR$\Debug\Obj\rtt2m16c.pbd + + + BILINK + 36 125 46 122 89 63 79 120 86 118 121 83 58 52 68 124 78 69 72 44 114 42 123 85 76 35 54 67 87 64 55 119 82 + + + + + $PROJ_DIR$\..\..\finsh\symbol.c + + + ICCM16C + 116 + + + BICOMP + 64 + + + + + BICOMP + 11 96 94 6 + + + + + $PROJ_DIR$\..\..\src\clock.c + + + ICCM16C + 77 + + + BICOMP + 122 + + + + + BICOMP + 96 94 6 + + + + + $PROJ_DIR$\..\..\src\device.c + + + ICCM16C + 70 + + + BICOMP + 63 + + + + + BICOMP + 96 94 6 103 + + + + + $PROJ_DIR$\..\..\src\idle.c + + + ICCM16C + 34 + + + BICOMP + 78 + + + + + BICOMP + 95 96 94 6 103 + + + + + $PROJ_DIR$\..\..\src\ipc.c + + + ICCM16C + 45 + + + BICOMP + 72 + + + + + BICOMP + 96 94 6 95 103 + + + + + $PROJ_DIR$\..\..\src\irq.c + + + ICCM16C + 40 + + + BICOMP + 44 + + + + + BICOMP + 95 96 94 6 + + + + + $PROJ_DIR$\..\..\src\kservice.c + + + ICCM16C + 115 + + + BICOMP + 114 + + + + + BICOMP + 96 94 6 95 + + + + + $PROJ_DIR$\..\..\src\mem.c + + + ICCM16C + 117 + + + BICOMP + 42 + + + + + BICOMP + 96 94 6 11 + + + + + $PROJ_DIR$\..\..\src\mempool.c + + + ICCM16C + 53 + + + BICOMP + 123 + + + + + BICOMP + 95 96 94 6 103 + + + + + $PROJ_DIR$\..\..\src\object.c + + + ICCM16C + 56 + + + BICOMP + 85 + + + + + BICOMP + 96 94 6 95 103 + + + + + $PROJ_DIR$\..\..\src\scheduler.c + + + ICCM16C + 57 + + + BICOMP + 76 + + + + + BICOMP + 96 94 6 95 103 + + + + + $PROJ_DIR$\..\..\src\slab.c + + + ICCM16C + 33 + + + BICOMP + 54 + + + + + BICOMP + 95 96 94 6 + + + + + $PROJ_DIR$\..\..\src\thread.c + + + ICCM16C + 71 + + + BICOMP + 55 + + + + + BICOMP + 96 94 6 95 103 + + + + + $PROJ_DIR$\..\..\src\timer.c + + + ICCM16C + 41 + + + BICOMP + 119 + + + + + BICOMP + 96 94 6 95 103 + + + + + $PROJ_DIR$\..\..\libcpu\m16c\context.asm + + + AM16C + 90 + + + + + $PROJ_DIR$\..\..\libcpu\m16c\interrupt.c + + + ICCM16C + 74 + + + BICOMP + 69 + + + + + BICOMP + 96 94 6 + + + + + $PROJ_DIR$\..\..\libcpu\m16c\stack.c + + + ICCM16C + 65 + + + BICOMP + 67 + + + + + BICOMP + 96 94 6 + + + + + + Release + + $PROJ_DIR$\application.c + $PROJ_DIR$\board.c + $PROJ_DIR$\bsp.c + $PROJ_DIR$\cstartup.s34 + $PROJ_DIR$\rtconfig.h + $PROJ_DIR$\startup.c + $PROJ_DIR$\uart.c + $PROJ_DIR$\vectors.s34 + $PROJ_DIR$\..\..\finsh\cmd.c + $PROJ_DIR$\..\..\finsh\finsh.h + $PROJ_DIR$\..\..\finsh\finsh_compiler.c + $PROJ_DIR$\..\..\finsh\finsh_error.c + $PROJ_DIR$\..\..\finsh\finsh_error.h + $PROJ_DIR$\..\..\finsh\finsh_heap.c + $PROJ_DIR$\..\..\finsh\finsh_heap.h + $PROJ_DIR$\..\..\finsh\finsh_init.c + $PROJ_DIR$\..\..\finsh\finsh_node.c + $PROJ_DIR$\..\..\finsh\finsh_node.h + $PROJ_DIR$\..\..\finsh\finsh_ops.c + $PROJ_DIR$\..\..\finsh\finsh_ops.h + $PROJ_DIR$\..\..\finsh\finsh_parser.c + $PROJ_DIR$\..\..\finsh\finsh_parser.h + $PROJ_DIR$\..\..\finsh\finsh_token.c + $PROJ_DIR$\..\..\finsh\finsh_token.h + $PROJ_DIR$\..\..\finsh\finsh_var.c + $PROJ_DIR$\..\..\finsh\finsh_var.h + $PROJ_DIR$\..\..\finsh\finsh_vm.c + $PROJ_DIR$\..\..\finsh\finsh_vm.h + $PROJ_DIR$\..\..\finsh\shell.c + $PROJ_DIR$\Release\Obj\context.r34 + $PROJ_DIR$\uart.h + $PROJ_DIR$\Release\Obj\finsh_compiler.pbi + $PROJ_DIR$\Release\Obj\timer.r34 + $PROJ_DIR$\Release\Obj\mempool.pbi + $PROJ_DIR$\Release\Obj\stack.r34 + $PROJ_DIR$\Release\Obj\rtt2m16c.pbd + $PROJ_DIR$\Release\Obj\board.pbi + $PROJ_DIR$\Release\Obj\symbol.pbi + $PROJ_DIR$\Release\Obj\finsh_ops.pbi + $PROJ_DIR$\Release\Obj\finsh_heap.pbi + $PROJ_DIR$\Release\Obj\startup.pbi + $PROJ_DIR$\Release\Obj\finsh_token.r34 + $PROJ_DIR$\Release\Obj\ipc.pbi + $PROJ_DIR$\Release\Obj\finsh_parser.pbi + $PROJ_DIR$\Release\Obj\timer.pbi + $PROJ_DIR$\Release\Obj\idle.pbi + $PROJ_DIR$\Release\Obj\clock.pbi + $PROJ_DIR$\Release\Obj\shell.pbi + $PROJ_DIR$\Release\Obj\scheduler.pbi + $PROJ_DIR$\Release\Obj\object.pbi + $PROJ_DIR$\Release\Obj\interrupt.pbi + $PROJ_DIR$\Release\Obj\thread.pbi + $PROJ_DIR$\Release\Exe\rtt2m16c.dbg + $PROJ_DIR$\Release\Obj\slab.pbi + $PROJ_DIR$\Release\Obj\startup.r34 + $PROJ_DIR$\Release\Obj\thread.r34 + $PROJ_DIR$\Release\Obj\stack.pbi + $PROJ_DIR$\Release\Obj\device.r34 + $PROJ_DIR$\Release\Obj\shell.r34 + $PROJ_DIR$\Release\Obj\kservice.r34 + $PROJ_DIR$\Release\Obj\clock.r34 + $PROJ_DIR$\Release\Obj\finsh_error.r34 + $PROJ_DIR$\Release\Obj\finsh_parser.r34 + $PROJ_DIR$\Release\Obj\finsh_compiler.r34 + $PROJ_DIR$\Release\Obj\ipc.r34 + $PROJ_DIR$\Release\Obj\irq.r34 + $PROJ_DIR$\Release\Obj\finsh_init.r34 + $PROJ_DIR$\Release\Obj\finsh_node.r34 + $PROJ_DIR$\Release\Obj\mem.r34 + $PROJ_DIR$\Release\Obj\finsh_vm.r34 + $PROJ_DIR$\Release\Obj\scheduler.r34 + $PROJ_DIR$\Release\Obj\cmd.r34 + $PROJ_DIR$\Release\Obj\finsh_ops.r34 + $PROJ_DIR$\Release\Obj\vectors.r34 + $PROJ_DIR$\Release\Obj\application.pbi + $PROJ_DIR$\Release\Obj\finsh_var.r34 + $PROJ_DIR$\Release\Obj\finsh_init.pbi + $PROJ_DIR$\Release\Obj\bsp.r34 + $PROJ_DIR$\Release\Obj\finsh_node.pbi + $PROJ_DIR$\Release\Obj\board.r34 + $PROJ_DIR$\Release\Obj\finsh_error.pbi + $PROJ_DIR$\Release\Obj\bsp.pbi + $PROJ_DIR$\Release\Obj\application.r34 + $PROJ_DIR$\Release\Obj\cstartup.r34 + $PROJ_DIR$\Release\Obj\symbol.r34 + $PROJ_DIR$\Release\Obj\finsh_heap.r34 + $PROJ_DIR$\Release\Obj\finsh_token.pbi + $PROJ_DIR$\Release\Obj\slab.r34 + $PROJ_DIR$\Release\Obj\object.r34 + $PROJ_DIR$\Release\Obj\mempool.r34 + $PROJ_DIR$\Release\Obj\mem.pbi + $PROJ_DIR$\Release\Obj\uart.r34 + $PROJ_DIR$\Release\Obj\finsh_vm.pbi + $PROJ_DIR$\Release\Obj\kservice.pbi + $PROJ_DIR$\Release\Obj\irq.pbi + $PROJ_DIR$\Release\Obj\device.pbi + $PROJ_DIR$\Release\Obj\cmd.pbi + $PROJ_DIR$\Release\Obj\uart.pbi + $PROJ_DIR$\Release\Obj\finsh_var.pbi + $PROJ_DIR$\Release\Obj\interrupt.r34 + $PROJ_DIR$\Release\Obj\idle.r34 + $TOOLKIT_DIR$\inc\iom16c62p.h + $PROJ_DIR$\board.h + $PROJ_DIR$\bsp.h + $PROJ_DIR$\..\..\finsh\symbol.c + $PROJ_DIR$\..\..\src\clock.c + $PROJ_DIR$\..\..\src\device.c + $PROJ_DIR$\..\..\src\idle.c + $PROJ_DIR$\..\..\src\ipc.c + $PROJ_DIR$\..\..\src\irq.c + $PROJ_DIR$\..\..\src\kservice.c + $PROJ_DIR$\..\..\src\kservice.h + $PROJ_DIR$\..\..\src\mem.c + $PROJ_DIR$\..\..\src\mempool.c + $PROJ_DIR$\..\..\src\object.c + $PROJ_DIR$\..\..\src\scheduler.c + $PROJ_DIR$\..\..\src\slab.c + $PROJ_DIR$\..\..\src\thread.c + $PROJ_DIR$\..\..\src\timer.c + $PROJ_DIR$\..\..\libcpu\m16c\context.asm + $PROJ_DIR$\..\..\libcpu\m16c\interrupt.c + $PROJ_DIR$\..\..\libcpu\m16c\stack.c + + + $PROJ_DIR$\application.c + + + ICCM16C + 82 + + + BICOMP + 74 + + + + + BICOMP + 103 + + + + + $PROJ_DIR$\board.c + + + ICCM16C + 79 + + + BICOMP + 36 + + + + + BICOMP + 30 102 + + + + + $PROJ_DIR$\bsp.c + + + ICCM16C + 77 + + + BICOMP + 81 + + + + + BICOMP + 101 103 4 + + + + + $PROJ_DIR$\cstartup.s34 + + + AM16C + 83 + + + + + $PROJ_DIR$\startup.c + + + ICCM16C + 54 + + + BICOMP + 40 + + + + + BICOMP + 101 102 103 + + + + + $PROJ_DIR$\uart.c + + + ICCM16C + 91 + + + BICOMP + 97 + + + + + BICOMP + 101 103 30 + + + + + $PROJ_DIR$\vectors.s34 + + + AM16C + 73 + + + + + $PROJ_DIR$\..\..\finsh\cmd.c + + + ICCM16C + 71 + + + BICOMP + 96 + + + + + BICOMP + 9 + + + + + $PROJ_DIR$\..\..\finsh\finsh_compiler.c + + + ICCM16C + 63 + + + BICOMP + 31 + + + + + BICOMP + 17 12 25 19 27 + + + + + $PROJ_DIR$\..\..\finsh\finsh_error.c + + + ICCM16C + 61 + + + BICOMP + 80 + + + + + BICOMP + 12 + + + + + $PROJ_DIR$\..\..\finsh\finsh_heap.c + + + ICCM16C + 85 + + + BICOMP + 39 + + + + + BICOMP + 25 + + + + + $PROJ_DIR$\..\..\finsh\finsh_init.c + + + ICCM16C + 66 + + + BICOMP + 76 + + + + + BICOMP + 17 27 25 21 12 14 + + + + + $PROJ_DIR$\..\..\finsh\finsh_node.c + + + ICCM16C + 67 + + + BICOMP + 78 + + + + + BICOMP + 17 12 25 14 + + + + + $PROJ_DIR$\..\..\finsh\finsh_ops.c + + + ICCM16C + 72 + + + BICOMP + 38 + + + + + BICOMP + 19 27 25 + + + + + $PROJ_DIR$\..\..\finsh\finsh_parser.c + + + ICCM16C + 62 + + + BICOMP + 43 + + + + + BICOMP + 23 17 12 21 25 + + + + + $PROJ_DIR$\..\..\finsh\finsh_token.c + + + ICCM16C + 41 + + + BICOMP + 86 + + + + + BICOMP + 23 12 + + + + + $PROJ_DIR$\..\..\finsh\finsh_var.c + + + ICCM16C + 75 + + + BICOMP + 98 + + + + + BICOMP + 25 + + + + + $PROJ_DIR$\..\..\finsh\finsh_vm.c + + + ICCM16C + 69 + + + BICOMP + 92 + + + + + BICOMP + 27 25 19 + + + + + $PROJ_DIR$\..\..\finsh\shell.c + + + ICCM16C + 58 + + + BICOMP + 47 + + + + + BICOMP + 9 + + + + + [ROOT_NODE] + + + XLINK + 52 + + + + + $PROJ_DIR$\Release\Obj\rtt2m16c.pbd + + + BILINK + 74 36 81 46 96 95 31 80 39 76 78 38 43 86 98 92 45 50 42 94 93 90 33 49 48 47 53 56 40 37 51 44 97 + + + + + $PROJ_DIR$\..\..\finsh\symbol.c + + + ICCM16C + 84 + + + BICOMP + 37 + + + + + BICOMP + 9 + + + + + $PROJ_DIR$\..\..\src\clock.c + + + ICCM16C + 60 + + + BICOMP + 46 + + + + + $PROJ_DIR$\..\..\src\device.c + + + ICCM16C + 57 + + + BICOMP + 95 + + + + + BICOMP + 111 + + + + + $PROJ_DIR$\..\..\src\idle.c + + + ICCM16C + 100 + + + BICOMP + 45 + + + + + BICOMP + 111 + + + + + $PROJ_DIR$\..\..\src\ipc.c + + + ICCM16C + 64 + + + BICOMP + 42 + + + + + BICOMP + 111 + + + + + $PROJ_DIR$\..\..\src\irq.c + + + ICCM16C + 65 + + + BICOMP + 94 + + + + + $PROJ_DIR$\..\..\src\kservice.c + + + ICCM16C + 59 + + + BICOMP + 93 + + + + + $PROJ_DIR$\..\..\src\mem.c + + + ICCM16C + 68 + + + BICOMP + 90 + + + + + $PROJ_DIR$\..\..\src\mempool.c + + + ICCM16C + 89 + + + BICOMP + 33 + + + + + BICOMP + 111 + + + + + $PROJ_DIR$\..\..\src\object.c + + + ICCM16C + 88 + + + BICOMP + 49 + + + + + BICOMP + 111 + + + + + $PROJ_DIR$\..\..\src\scheduler.c + + + ICCM16C + 70 + + + BICOMP + 48 + + + + + BICOMP + 111 + + + + + $PROJ_DIR$\..\..\src\slab.c + + + ICCM16C + 87 + + + BICOMP + 53 + + + + + $PROJ_DIR$\..\..\src\thread.c + + + ICCM16C + 55 + + + BICOMP + 51 + + + + + BICOMP + 111 + + + + + $PROJ_DIR$\..\..\src\timer.c + + + ICCM16C + 32 + + + BICOMP + 44 + + + + + BICOMP + 111 + + + + + $PROJ_DIR$\..\..\libcpu\m16c\context.asm + + + AM16C + 29 + + + + + $PROJ_DIR$\..\..\libcpu\m16c\interrupt.c + + + ICCM16C + 99 + + + BICOMP + 50 + + + + + $PROJ_DIR$\..\..\libcpu\m16c\stack.c + + + ICCM16C + 34 + + + BICOMP + 56 + + + + + [MULTI_TOOL] + XLINK + + + + + diff --git a/bsp/m16c62p/rtt2m16c.ewd b/bsp/m16c62p/rtt2m16c.ewd new file mode 100644 index 000000000..32fc0ff88 --- /dev/null +++ b/bsp/m16c62p/rtt2m16c.ewd @@ -0,0 +1,737 @@ + + + + 2 + + Debug + + M16C + + 1 + + C-SPY + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + M16CEMU + 1 + + 0 + 1 + 1 + + + + + + + + + + + M16CEMUCPE + 1 + + 0 + 1 + 1 + + + + + + + + M16CEMUE100 + 1 + + 0 + 1 + 1 + + + + + + + + M16CEMUE8 + 1 + + 0 + 1 + 1 + + + + + M16CEMUE8A + 1 + + 0 + 1 + 1 + + + + + M16CROM + 1 + + 1 + 1 + 1 + + + + + + + + + + + + + + + M16CSIM + 2 + + 0 + 1 + 1 + + + + + M16CUSBROM + 1 + + 1 + 1 + 1 + + + + + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\Profiling\Profiling.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + + + Release + + M16C + + 0 + + C-SPY + 2 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + M16CEMU + 1 + + 0 + 1 + 0 + + + + + + + + + + + M16CEMUCPE + 1 + + 0 + 1 + 0 + + + + + + + + M16CEMUE100 + 1 + + 0 + 1 + 0 + + + + + + + + M16CEMUE8 + 1 + + 0 + 1 + 0 + + + + + M16CEMUE8A + 1 + + 0 + 1 + 0 + + + + + M16CROM + 1 + + 1 + 1 + 0 + + + + + + + + + + + + + + + M16CSIM + 2 + + 0 + 1 + 0 + + + + + M16CUSBROM + 1 + + 1 + 1 + 0 + + + + + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\Profiling\Profiling.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + + + + diff --git a/bsp/m16c62p/rtt2m16c.ewp b/bsp/m16c62p/rtt2m16c.ewp new file mode 100644 index 000000000..025989ebd --- /dev/null +++ b/bsp/m16c62p/rtt2m16c.ewp @@ -0,0 +1,1936 @@ + + + + 2 + + Debug + + M16C + + 1 + + General + 2 + + 10 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCM16C + 3 + + 18 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AM16C + 3 + + 6 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + XLINK + 2 + + 17 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + XAR + 1 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + M16C + + 0 + + General + 2 + + 10 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCM16C + 3 + + 18 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AM16C + 3 + + 6 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + XLINK + 2 + + 17 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + XAR + 1 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + bsp + + m16c62p + + $PROJ_DIR$\application.c + + + $PROJ_DIR$\board.c + + + $PROJ_DIR$\bsp.c + + + $PROJ_DIR$\cstartup.s34 + + + $PROJ_DIR$\lnkm30627fhp.xcl + + + $PROJ_DIR$\rtconfig.h + + + $PROJ_DIR$\startup.c + + + $PROJ_DIR$\uart.c + + + $PROJ_DIR$\vectors.s34 + + + + + finsh + + $PROJ_DIR$\..\..\finsh\cmd.c + + + $PROJ_DIR$\..\..\finsh\finsh.h + + + $PROJ_DIR$\..\..\finsh\finsh_compiler.c + + + $PROJ_DIR$\..\..\finsh\finsh_error.c + + + $PROJ_DIR$\..\..\finsh\finsh_error.h + + + $PROJ_DIR$\..\..\finsh\finsh_heap.c + + + $PROJ_DIR$\..\..\finsh\finsh_heap.h + + + $PROJ_DIR$\..\..\finsh\finsh_init.c + + + $PROJ_DIR$\..\..\finsh\finsh_node.c + + + $PROJ_DIR$\..\..\finsh\finsh_node.h + + + $PROJ_DIR$\..\..\finsh\finsh_ops.c + + + $PROJ_DIR$\..\..\finsh\finsh_ops.h + + + $PROJ_DIR$\..\..\finsh\finsh_parser.c + + + $PROJ_DIR$\..\..\finsh\finsh_parser.h + + + $PROJ_DIR$\..\..\finsh\finsh_token.c + + + $PROJ_DIR$\..\..\finsh\finsh_token.h + + + $PROJ_DIR$\..\..\finsh\finsh_var.c + + + $PROJ_DIR$\..\..\finsh\finsh_var.h + + + $PROJ_DIR$\..\..\finsh\finsh_vm.c + + + $PROJ_DIR$\..\..\finsh\finsh_vm.h + + + $PROJ_DIR$\..\..\finsh\shell.c + + + $PROJ_DIR$\..\..\finsh\symbol.c + + + + include + + $PROJ_DIR$\..\..\include\rtdef.h + + + $PROJ_DIR$\..\..\include\rthw.h + + + $PROJ_DIR$\..\..\include\rtthread.h + + + + kernel + + $PROJ_DIR$\..\..\src\clock.c + + + $PROJ_DIR$\..\..\src\device.c + + + $PROJ_DIR$\..\..\src\idle.c + + + $PROJ_DIR$\..\..\src\ipc.c + + + $PROJ_DIR$\..\..\src\irq.c + + + $PROJ_DIR$\..\..\src\kservice.c + + + $PROJ_DIR$\..\..\src\kservice.h + + + $PROJ_DIR$\..\..\src\mem.c + + + $PROJ_DIR$\..\..\src\mempool.c + + + $PROJ_DIR$\..\..\src\object.c + + + $PROJ_DIR$\..\..\src\scheduler.c + + + $PROJ_DIR$\..\..\src\slab.c + + + $PROJ_DIR$\..\..\src\thread.c + + + $PROJ_DIR$\..\..\src\timer.c + + + + libcpu + + m16c + + $PROJ_DIR$\..\..\libcpu\m16c\context.asm + + + $PROJ_DIR$\..\..\libcpu\m16c\interrupt.c + + + $PROJ_DIR$\..\..\libcpu\m16c\stack.c + + + + + + diff --git a/bsp/m16c62p/rtt2m16c.eww b/bsp/m16c62p/rtt2m16c.eww new file mode 100644 index 000000000..2119268ed --- /dev/null +++ b/bsp/m16c62p/rtt2m16c.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\rtt2m16c.ewp + + + + + diff --git a/bsp/m16c62p/startup.c b/bsp/m16c62p/startup.c new file mode 100644 index 000000000..b3b4fbff9 --- /dev/null +++ b/bsp/m16c62p/startup.c @@ -0,0 +1,103 @@ +/* + * File : startup.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2009, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2009-01-05 Bernard first implementation + * 2010-04-09 fify for M16C + */ + +#include +#include + +#include "iom16c62p.h" +#include "board.h" +#include "bsp.h" + +extern int rt_application_init(void); +#ifdef RT_USING_FINSH +extern void finsh_system_init(void); +extern void finsh_set_device(const char* device); +#endif + +#ifdef RT_USING_HEAP +#ifdef __ICCM16C__ +#pragma section="DATA16_HEAP" +#endif +#endif + +/** + * This function will startup RT-Thread RTOS. + */ +void rtthread_startup(void) +{ + /* init board */ + rt_hw_board_init(); + + /* show version */ + rt_show_version(); + + /* init tick */ + rt_system_tick_init(); + + /* init kernel object */ + rt_system_object_init(); + + /* init timer system */ + rt_system_timer_init(); + +#ifdef RT_USING_HEAP +#ifdef __ICCM16C__ + rt_system_heap_init(__segment_begin("DATA16_HEAP"),__segment_end("DATA16_HEAP")); +#endif +#endif + + /* init scheduler system */ + rt_system_scheduler_init(); + +#ifdef RT_USING_DEVICE + /* init all device */ + rt_device_init_all(); +#endif + + /* init application */ + rt_application_init(); + +#ifdef RT_USING_FINSH + /* init finsh */ + finsh_system_init(); + finsh_set_device("uart0"); +#endif + + /* init timer thread */ + rt_system_timer_thread_init(); + + /* init idle thread */ + rt_thread_idle_init(); + + /* start scheduler */ + rt_system_scheduler_start(); + + /* never reach here */ + return ; +} + +int main(void) +{ + /* disable interrupt first */ + rt_hw_interrupt_disable(); + + /* init system setting */ + system_init(); + + /* startup RT-Thread RTOS */ + rtthread_startup(); + + return 0; +} diff --git a/bsp/m16c62p/uart.c b/bsp/m16c62p/uart.c new file mode 100644 index 000000000..8506b4033 --- /dev/null +++ b/bsp/m16c62p/uart.c @@ -0,0 +1,288 @@ +/* + * File : board.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2009 RT-Thread Develop Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2010-03-08 Bernard The first version for LPC17xx + * 2010-04-10 fify Modified for M16C +*/ + +#include +#include +#include "iom16c62p.h" +#include "bsp.h" +#include "uart.h" + +#if defined(RT_USING_UART0) && defined(RT_USING_DEVICE) + +struct rt_uart_m16c +{ + struct rt_device parent; + + /* buffer for reception */ + rt_uint8_t read_index, save_index; + rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE]; +}uart_device; + +void u0rec_handler(void) +{ + rt_ubase_t level; + rt_uint8_t c; + + struct rt_uart_m16c* uart = &uart_device; + + while(ri_u0c1 == 0) + ; + c = (char) u0rb; + + /* Receive Data Available */ + uart->rx_buffer[uart->save_index] = c; + + level = rt_hw_interrupt_disable(); + uart->save_index ++; + if (uart->save_index >= RT_UART_RX_BUFFER_SIZE) + uart->save_index = 0; + rt_hw_interrupt_enable(level); + + /* invoke callback */ + if(uart->parent.rx_indicate != RT_NULL) + { + rt_size_t length; + if (uart->read_index > uart->save_index) + length = RT_UART_RX_BUFFER_SIZE - uart->read_index + uart->save_index; + else + length = uart->save_index - uart->read_index; + + uart->parent.rx_indicate(&uart->parent, length); + } +} + +static rt_err_t rt_uart_init (rt_device_t dev) +{ + /* set UART0 bit rate generator bit rate can be calculated by: + bit rate = ((BRG count source / 16)/baud rate) - 1 + Baud rate is based on main crystal or PLL not CPU core clock */ + //pclk1 = 1; /// seleck F1SIO + u0brg = (unsigned char)(((CPU_CLK_FREQ/16)/BAUD_RATE)-1); //(N+1) + + /* UART Transmit/Receive Control Register 2 */ + ucon = 0x00; + /* 00000000 + b0 U0IRS UART0 transmit irq cause select bit, 0 = transmit buffer empty + b1 U1IRS UART1 transmit irq cause select bit, 0 = transmit buffer empty + b2 U0RRM UART0 continuous receive mode enable bit, set to 0 in UART mode + b3 U1RRM UART1 continuous receive mode enable bit, set to 0 in UART mode + b4 CLKMD0 CLK/CLKS select bit 0, set to 0 in UART mode + b5 CLKMD1 CLK/CLKS select bit 1, set to 0 in UART mode + b6 RCSP Separate CTS/RTS bit, + b7 Reserved, set to 0 */ + + /* UART0 transmit/receive control register 0 */ + /* f1 count source, CTS/RTS disabled, CMOS output */ + u0c0 = 0x10; + /* 00010000 + b1:b0 CLK01:CLK0 BRG count source select bits //01 F8SIO + b2 CRS CTS/RTS function select bit + b3 TXEPT Transmit register empty flag + b4 CRD CTS/RTS disable bit + b5 NCH Data output select bit + b6 CKPOL CLK polarity select bit,set to 0 in UART mode + b7 UFORM Transfer format select bit,set to 0 in UART mode */ + + /* UART0 transmit/receive control register 1 */ + /* disable transmit and receive, no error output pin, data not inverted */ + u0c1 = 0x00; + /* 00000000 + b0 TE Transmit enable bit + b1 TI Transmit buffer empty flag + b2 RE Receive enable bit + b3 RI Receive complete flag + b5:b4 Reserved, set to 0 + b6 UOLCH Data logic select bit + b7 UOERE Error signal output enable bit */ + + /* UART0 transmit/receive mode register */ + /* 8-bit data,asynch mode, internal clock, 1 stop bit, no parity */ + u0mr = 0x05; + /* 00000101 + b2:b0 SMD12:SMD1 Serial I/O Mode select bits + b3 CKDIR Internal/External clock select bit, CKDIR + b4 STPS Stop bit length select bit, STPS + b5 PRY Odd/even parity select bit, PRY + b6 PRYE Parity enable bit, PRYE + b7 IOPOL TxD, RxD I/O polarity reverse bit */ + + /* clear UART0 receive buffer by reading */ + u0tb = u0rb; + /* clear UART0 transmit buffer */ + u0tb = 0; + + /* disable irqs before setting irq registers */ + //DISABLE_IRQ + /* Enable UART0 receive interrupt, priority level 4 */ + asm("fset i"); + s0ric = 0x04; + asm("fclr i"); + /* Enable all interrupts */ + //ENABLE_IRQ + + /* UART0 transmit/receive control register 1 */ + /* enable transmit and receive */ + u0c1 = 0x05; + /* 00000101 enable transmit and receive + b0 TE Transmit enable bit + b1 TI Transmit buffer empty flag + b2 RE Receive enable bit + b3 RI Receive complete flag + b5:b4 Reserved, set to 0 + b6 UOLCH Data logic select bit + b7 UOERE Error signal output enable bit */ + + return RT_EOK; +} + +static rt_err_t rt_uart_open(rt_device_t dev, rt_uint16_t oflag) +{ + RT_ASSERT(dev != RT_NULL); + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + /* Enable the UART Interrupt */ + } + + return RT_EOK; +} + +static rt_err_t rt_uart_close(rt_device_t dev) +{ + RT_ASSERT(dev != RT_NULL); + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + /* Disable the UART Interrupt */ + } + + return RT_EOK; +} + +static rt_size_t rt_uart_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) +{ + rt_uint8_t* ptr; + struct rt_uart_m16c *uart = (struct rt_uart_m16c*)dev; + RT_ASSERT(uart != RT_NULL); + + /* point to buffer */ + ptr = (rt_uint8_t*) buffer; + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + while (size) + { + /* interrupt receive */ + rt_base_t level; + + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + if (uart->read_index != uart->save_index) + { + *ptr = uart->rx_buffer[uart->read_index]; + + uart->read_index ++; + if (uart->read_index >= RT_UART_RX_BUFFER_SIZE) + uart->read_index = 0; + } + else + { + /* no data in rx buffer */ + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + break; + } + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + + ptr ++; + size --; + } + + return (rt_uint32_t)ptr - (rt_uint32_t)buffer; + } + + return 0; +} + +static rt_size_t rt_uart_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) +{ + char *ptr; + ptr = (char*)buffer; + + if (dev->flag & RT_DEVICE_FLAG_STREAM) + { + /* stream mode */ + while (size) + { + if (*ptr == '\n') + { + while(ti_u0c1 == 0) + ; + u0tb = '\r'; + } + + /* THRE status, contain valid data */ + while(ti_u0c1 == 0) + ; + u0tb = *ptr; + + ptr ++; + size --; + } + } + else + { + while ( size != 0 ) + { + /* THRE status, contain valid data */ + while(ti_u0c1 == 0) + ; + u0tb = *ptr; + + ptr++; + size--; + } + } + + return (rt_size_t) ptr - (rt_size_t) buffer; +} + +void rt_hw_uart_init(void) +{ + struct rt_uart_m16c* uart; + + /* get uart device */ + uart = &uart_device; + + /* device initialization */ + uart->parent.type = RT_Device_Class_Char; + rt_memset(uart->rx_buffer, 0, sizeof(uart->rx_buffer)); + uart->read_index = uart->save_index = 0; + + /* device interface */ + uart->parent.init = rt_uart_init; + uart->parent.open = rt_uart_open; + uart->parent.close = rt_uart_close; + uart->parent.read = rt_uart_read; + uart->parent.write = rt_uart_write; + uart->parent.control = RT_NULL; + uart->parent.private = RT_NULL; + + rt_device_register(&uart->parent, + "uart0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STREAM | RT_DEVICE_FLAG_INT_RX); +} +#endif /* end of UART */ + +/*@}*/ diff --git a/bsp/m16c62p/uart.h b/bsp/m16c62p/uart.h new file mode 100644 index 000000000..ca7510e96 --- /dev/null +++ b/bsp/m16c62p/uart.h @@ -0,0 +1,8 @@ +#ifndef __UART_H__ +#define __UART_H__ + +#define BAUD_RATE 9600 + +void rt_hw_uart_init(void); + +#endif diff --git a/bsp/m16c62p/vectors.s34 b/bsp/m16c62p/vectors.s34 new file mode 100644 index 000000000..f80ed655c --- /dev/null +++ b/bsp/m16c62p/vectors.s34 @@ -0,0 +1,68 @@ +/* + * File : vectors.s34 + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2009, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2010-04-09 fify the first version + * + * For : Renesas M16C + * Toolchain : IAR's EW for M16C v3.401 +*/ + +;******************************************************************************************************** +; RELOCATABLE EXCEPTION VECTOR TABLE +;******************************************************************************************************** + + MODULE ?vectors + + EXTERN rt_hw_timer_handler + EXTERN rt_hw_uart0_receive_handler + + PUBLIC RelocatableVectTbl + + RSEG INTVEC:NOROOT + +RelocatableVectTbl: + ORG 0 + DC32 0 ; Vector 0: BRK + DC32 0 ; Vector 1: Reserved + DC32 0 ; Vector 2: Reserved + DC32 0 ; Vector 3: Reserved + DC32 0 ; Vector 4: INT3 + DC32 0 ; Vector 5: Timer B5 + DC32 0 ; Vector 6: Timer B4, UART1 Bus Collision Detect + DC32 0 ; Vector 7: Timer B3, UART0 Bus Collision Detect + DC32 0 ; Vector 8: SI/O4, INT5 + DC32 0 ; Vector 9: SI/O3, INT4 + DC32 0 ; Vector 10: UART2 Bus Collision Detect + DC32 0 ; Vector 11: DMA0 + DC32 0 ; Vector 12: DMA1 + DC32 0 ; Vector 13: Key Input Interrupt + DC32 0 ; Vector 14: A/D + DC32 0 ; Vector 15: UART2 Transmit, NACK2 + DC32 0 ; Vector 16: UART2 Receive, ACK2 + DC32 0 ; Vector 17: UART0 Transmit, NACK0 + DC32 rt_hw_uart0_receive_handler ; Vector 18: UART0 Receive, ACK0 + DC32 0 ; Vector 19: UART1 Transmit, NACK1 + DC32 0 ; Vector 20: UART1 Receive, ACK1 + DC32 0 ; Vector 21: Timer A0 + DC32 0 ; Vector 22: Timer A1 + DC32 0 ; Vector 23: Timer A2 + DC32 0 ; Vector 24: Timer A3 + DC32 0 ; Vector 25: Timer A4 + DC32 rt_hw_timer_handler ; Vector 26: Timer B0 + DC32 0 ; Vector 27: Timer B1 + DC32 0 ; Vector 28: Timer B2 + DC32 0 ; Vector 29: + DC32 0 ; Vector 30: + DC32 0 ; Vector 31: + + ENDMOD + + END -- GitLab