diff --git a/bsp/stm32f4xx-HAL/drivers/drv_pwm.c b/bsp/stm32f4xx-HAL/drivers/drv_pwm.c index a84745aa2565fc5b1174058364b091e2426b6ba7..c5be0e1267b66d0d561ed862e5e3744918dc1bc8 100644 --- a/bsp/stm32f4xx-HAL/drivers/drv_pwm.c +++ b/bsp/stm32f4xx-HAL/drivers/drv_pwm.c @@ -25,14 +25,17 @@ #include #include #include + #define MAX_PERIOD 65535 #define MIN_PERIOD 3 #define MIN_PULSE 2 + static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg); static struct rt_pwm_ops drv_ops = { - .control = drv_pwm_control + drv_pwm_control }; + static rt_err_t drv_pwm_enable(TIM_HandleTypeDef * htim, struct rt_pwm_configuration *configuration, rt_bool_t enable) { rt_uint32_t channel = 0x04 * configuration->channel; @@ -43,11 +46,12 @@ static rt_err_t drv_pwm_enable(TIM_HandleTypeDef * htim, struct rt_pwm_configura HAL_TIM_PWM_Start(htim, channel); return RT_EOK; } + static rt_err_t drv_pwm_get(TIM_HandleTypeDef * htim, struct rt_pwm_configuration *configuration) { rt_uint32_t channel = 0x04 * configuration->channel; rt_uint32_t tim_clock; - #if (RT_HSE_HCLK > 100000000UL)//100M +#if (RT_HSE_HCLK > 100000000UL)//100M if(htim->Instance == TIM1 && htim->Instance == TIM8) { tim_clock = SystemCoreClock; @@ -72,6 +76,7 @@ static rt_err_t drv_pwm_get(TIM_HandleTypeDef * htim, struct rt_pwm_configuratio configuration->pulse = (__HAL_TIM_GET_COMPARE(htim, channel) + 1) * (htim->Instance->PSC + 1) * 1000UL / tim_clock; return RT_EOK; } + static rt_err_t drv_pwm_set(TIM_HandleTypeDef * htim, struct rt_pwm_configuration *configuration) { rt_uint32_t period, pulse; @@ -111,6 +116,7 @@ static rt_err_t drv_pwm_set(TIM_HandleTypeDef * htim, struct rt_pwm_configuratio __HAL_TIM_SET_COMPARE(htim, channel, pulse - 1 ); return RT_EOK; } + static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg) { struct rt_pwm_configuration * configuration = (struct rt_pwm_configuration *)arg; @@ -130,7 +136,9 @@ static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg return RT_EINVAL; } } + static void HAL_TIM_MspPostInit(TIM_HandleTypeDef* timHandle); + #ifdef BSP_USING_PWM1 TIM_HandleTypeDef htim1; #endif @@ -179,30 +187,35 @@ static void MX_TIM1_Init(void) sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; sConfigOC.OCIdleState = TIM_OCIDLESTATE_RESET; sConfigOC.OCNIdleState = TIM_OCNIDLESTATE_RESET; + #ifdef BSP_USING_PWM1_CH1 if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) { RT_ASSERT(0); } -#endif +#endif /* BSP_USING_PWM1_CH1 */ + #ifdef BSP_USING_PWM1_CH2 if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) { RT_ASSERT(0); } -#endif +#endif /* BSP_USING_PWM1_CH2 */ + #ifdef BSP_USING_PWM1_CH3 if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_3) != HAL_OK) { RT_ASSERT(0); } -#endif +#endif /* BSP_USING_PWM1_CH3 */ + #ifdef BSP_USING_PWM1_CH4 if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_4) != HAL_OK) { RT_ASSERT(0); } -#endif +#endif /* BSP_USING_PWM1_CH4 */ + sBreakDeadTimeConfig.OffStateRunMode = TIM_OSSR_DISABLE; sBreakDeadTimeConfig.OffStateIDLEMode = TIM_OSSI_DISABLE; sBreakDeadTimeConfig.LockLevel = TIM_LOCKLEVEL_OFF; @@ -210,13 +223,14 @@ static void MX_TIM1_Init(void) sBreakDeadTimeConfig.BreakState = TIM_BREAK_DISABLE; sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH; sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE; + if (HAL_TIMEx_ConfigBreakDeadTime(&htim1, &sBreakDeadTimeConfig) != HAL_OK) { RT_ASSERT(0); } HAL_TIM_MspPostInit(&htim1); } -#endif +#endif /* BSP_USING_PWM1 */ #ifdef BSP_USING_PWM2 static void MX_TIM2_Init(void) @@ -245,33 +259,39 @@ static void MX_TIM2_Init(void) sConfigOC.Pulse = 0; sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; + #ifdef BSP_USING_PWM2_CH1 if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) { RT_ASSERT(0); } -#endif +#endif /* BSP_USING_PWM2_CH1 */ + #ifdef BSP_USING_PWM2_CH2 if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) { RT_ASSERT(0); } -#endif +#endif /* BSP_USING_PWM2_CH2 */ + #ifdef BSP_USING_PWM2_CH3 if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_3) != HAL_OK) { RT_ASSERT(0); } -#endif +#endif /* BSP_USING_PWM2_CH3 */ + #ifdef BSP_USING_PWM2_CH4 if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_4) != HAL_OK) { RT_ASSERT(0); } -#endif +#endif /* BSP_USING_PWM2_CH3 */ + HAL_TIM_MspPostInit(&htim2); } -#endif +#endif /* BSP_USING_PWM2 */ + #ifdef BSP_USING_PWM3 void MX_TIM3_Init(void) { @@ -304,28 +324,33 @@ void MX_TIM3_Init(void) { RT_ASSERT(0); } -#endif +#endif /* BSP_USING_PWM3_CH1 */ + #ifdef BSP_USING_PWM3_CH2 if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) { RT_ASSERT(0); } -#endif +#endif /* BSP_USING_PWM3_CH2 */ + #ifdef BSP_USING_PWM3_CH3 if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_3) != HAL_OK) { RT_ASSERT(0); } -#endif +#endif /* BSP_USING_PWM3_CH3 */ + #ifdef BSP_USING_PWM3_CH4 if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_4) != HAL_OK) { RT_ASSERT(0); } -#endif +#endif /* BSP_USING_PWM3_CH4 */ + HAL_TIM_MspPostInit(&htim3); } -#endif +#endif /* BSP_USING_PWM3 */ + #ifdef BSP_USING_PWM4 void MX_TIM4_Init(void) { @@ -358,28 +383,33 @@ void MX_TIM4_Init(void) { RT_ASSERT(0); } -#endif +#endif /* BSP_USING_PWM4_CH1 */ + #ifdef BSP_USING_PWM4_CH2 if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) { RT_ASSERT(0); } -#endif +#endif /* BSP_USING_PWM4_CH2 */ + #ifdef BSP_USING_PWM4_CH3 if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_3) != HAL_OK) { RT_ASSERT(0); } -#endif +#endif /* BSP_USING_PWM4_CH3 */ + #ifdef BSP_USING_PWM4_CH4 if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_4) != HAL_OK) { RT_ASSERT(0); } -#endif +#endif /* BSP_USING_PWM4_CH4 */ + HAL_TIM_MspPostInit(&htim4); } -#endif +#endif /* BSP_USING_PWM4 */ + #ifdef BSP_USING_PWM5 void MX_TIM5_Init(void) { @@ -412,22 +442,26 @@ void MX_TIM5_Init(void) { RT_ASSERT(0); } -#endif +#endif /* BSP_USING_PWM5_CH1 */ + #ifdef BSP_USING_PWM5_CH2 if (HAL_TIM_PWM_ConfigChannel(&htim5, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) { RT_ASSERT(0); } -#endif +#endif /* BSP_USING_PWM5_CH2 */ + #ifdef BSP_USING_PWM5_CH3 if (HAL_TIM_PWM_ConfigChannel(&htim5, &sConfigOC, TIM_CHANNEL_3) != HAL_OK) { RT_ASSERT(0); } -#endif +#endif /* BSP_USING_PWM5_CH3 */ + HAL_TIM_MspPostInit(&htim5); } -#endif +#endif /* BSP_USING_PWM5 */ + void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef* tim_pwmHandle) { if(tim_pwmHandle->Instance==TIM1) @@ -451,7 +485,8 @@ void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef* tim_pwmHandle) __HAL_RCC_TIM5_CLK_ENABLE(); } } -void HAL_TIM_MspPostInit(TIM_HandleTypeDef* timHandle) + +static void HAL_TIM_MspPostInit(TIM_HandleTypeDef* timHandle) { GPIO_InitTypeDef GPIO_InitStruct; if(timHandle->Instance==TIM1) @@ -581,18 +616,22 @@ int drv_pwm_init(void) MX_TIM1_Init(); rt_device_pwm_register(rt_calloc(1,sizeof(struct rt_device_pwm)), "pwm1", &drv_ops, &htim1); #endif + #ifdef BSP_USING_PWM2 MX_TIM2_Init(); rt_device_pwm_register(rt_calloc(1,sizeof(struct rt_device_pwm)), "pwm2", &drv_ops, &htim2); #endif + #ifdef BSP_USING_PWM3 MX_TIM3_Init(); rt_device_pwm_register(rt_calloc(1,sizeof(struct rt_device_pwm)), "pwm3", &drv_ops, &htim3); #endif + #ifdef BSP_USING_PWM4 MX_TIM4_Init(); rt_device_pwm_register(rt_calloc(1,sizeof(struct rt_device_pwm)), "pwm4", &drv_ops, &htim4); #endif + #ifdef BSP_USING_PWM5 MX_TIM5_Init(); rt_device_pwm_register(rt_calloc(1,sizeof(struct rt_device_pwm)), "pwm5", &drv_ops, &htim5);