diff --git a/libcpu/mips/loongson_1b/interrupt.c b/libcpu/mips/loongson_1b/interrupt.c
index 107ca5df682027716e3493e829c053082451163f..be65da914caa2c0bc1bdf7a71b64680e818f8180 100644
--- a/libcpu/mips/loongson_1b/interrupt.c
+++ b/libcpu/mips/loongson_1b/interrupt.c
@@ -30,7 +30,7 @@ void rt_interrupt_dispatch(void *ptreg);
 void rt_hw_timer_handler();
 
 static struct ls1b_intc_regs volatile *ls1b_hw0_icregs
-	= (struct ls1b_intc_regs volatile *)(LS1B_INTREG_BASE);
+= (struct ls1b_intc_regs volatile *)(LS1B_INTREG_BASE);
 
 /**
  * @addtogroup Loongson LS1B
@@ -40,7 +40,7 @@ static struct ls1b_intc_regs volatile *ls1b_hw0_icregs
 
 static void rt_hw_interrupt_handler(int vector, void *param)
 {
-	rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
+    rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
 }
 
 /**
@@ -48,26 +48,26 @@ static void rt_hw_interrupt_handler(int vector, void *param)
  */
 void rt_hw_interrupt_init(void)
 {
-	rt_int32_t idx;
+    rt_int32_t idx;
 
-	/* pci active low */ 
-	ls1b_hw0_icregs->int_pol = -1; 	   //must be done here 20110802 lgnq
-	/* make all interrupts level triggered */ 	
-	(ls1b_hw0_icregs+0)->int_edge = 0x0000e000;
-	/* mask all interrupts */
-	(ls1b_hw0_icregs+0)->int_clr = 0xffffffff;
+    /* pci active low */
+    ls1b_hw0_icregs->int_pol = -1;	   //must be done here 20110802 lgnq
+    /* make all interrupts level triggered */
+    (ls1b_hw0_icregs+0)->int_edge = 0x0000e000;
+    /* mask all interrupts */
+    (ls1b_hw0_icregs+0)->int_clr = 0xffffffff;
 
     rt_memset(irq_handle_table, 0x00, sizeof(irq_handle_table));
-	for (idx = 0; idx < MAX_INTR; idx ++)
-	{
-		irq_handle_table[idx].handler = rt_hw_interrupt_handler;
-	}
-
-	/* init interrupt nest, and context in thread sp */
-	rt_interrupt_nest = 0;
-	rt_interrupt_from_thread = 0;
-	rt_interrupt_to_thread = 0;
-	rt_thread_switch_interrupt_flag = 0;
+    for (idx = 0; idx < MAX_INTR; idx ++)
+    {
+        irq_handle_table[idx].handler = rt_hw_interrupt_handler;
+    }
+
+    /* init interrupt nest, and context in thread sp */
+    rt_interrupt_nest = 0;
+    rt_interrupt_from_thread = 0;
+    rt_interrupt_to_thread = 0;
+    rt_thread_switch_interrupt_flag = 0;
 }
 
 /**
@@ -76,8 +76,8 @@ void rt_hw_interrupt_init(void)
  */
 void rt_hw_interrupt_mask(int vector)
 {
-	/* mask interrupt */
-	(ls1b_hw0_icregs+(vector>>5))->int_en &= ~(1 << (vector&0x1f));
+    /* mask interrupt */
+    (ls1b_hw0_icregs+(vector>>5))->int_en &= ~(1 << (vector&0x1f));
 }
 
 /**
@@ -86,7 +86,7 @@ void rt_hw_interrupt_mask(int vector)
  */
 void rt_hw_interrupt_umask(int vector)
 {
-	(ls1b_hw0_icregs+(vector>>5))->int_en |= (1 << (vector&0x1f));
+    (ls1b_hw0_icregs+(vector>>5))->int_en |= (1 << (vector&0x1f));
 }
 
 /**
@@ -100,8 +100,8 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
 {
     rt_isr_handler_t old_handler = RT_NULL;
 
-	if (vector >= 0 && vector < MAX_INTR)
-	{
+    if (vector >= 0 && vector < MAX_INTR)
+    {
         old_handler = irq_handle_table[vector].handler;
 
 #ifdef RT_USING_INTERRUPT_INFO
@@ -118,71 +118,71 @@ void rt_interrupt_dispatch(void *ptreg)
 {
     int irq;
     void *param;
-	rt_isr_handler_t irq_func;
-	static rt_uint32_t status = 0;
-	rt_uint32_t c0_status;
-	rt_uint32_t c0_cause;
-	volatile rt_uint32_t cause_im;
-	volatile rt_uint32_t status_im;
-	rt_uint32_t pending_im;
-
-	/* check os timer */
-	c0_status = read_c0_status();
-	c0_cause = read_c0_cause();
-
-	cause_im = c0_cause & ST0_IM;
-	status_im = c0_status & ST0_IM;
-	pending_im = cause_im & status_im;
-
-	if (pending_im & CAUSEF_IP7)
-	{
-		rt_hw_timer_handler();
-	}
-
-	if (pending_im & CAUSEF_IP2)
-	{
-		/* the hardware interrupt */
-		status = ls1b_hw0_icregs->int_isr;
-		if (!status) 
-			return;
-
-		for (irq = MAX_INTR; irq > 0; --irq)
-		{
-			if ((status & (1 << irq)))
-			{
-				status &= ~(1 << irq);
+    rt_isr_handler_t irq_func;
+    static rt_uint32_t status = 0;
+    rt_uint32_t c0_status;
+    rt_uint32_t c0_cause;
+    volatile rt_uint32_t cause_im;
+    volatile rt_uint32_t status_im;
+    rt_uint32_t pending_im;
+
+    /* check os timer */
+    c0_status = read_c0_status();
+    c0_cause = read_c0_cause();
+
+    cause_im = c0_cause & ST0_IM;
+    status_im = c0_status & ST0_IM;
+    pending_im = cause_im & status_im;
+
+    if (pending_im & CAUSEF_IP7)
+    {
+        rt_hw_timer_handler();
+    }
+
+    if (pending_im & CAUSEF_IP2)
+    {
+        /* the hardware interrupt */
+        status = ls1b_hw0_icregs->int_isr;
+        if (!status)
+            return;
+
+        for (irq = MAX_INTR; irq > 0; --irq)
+        {
+            if ((status & (1 << irq)))
+            {
+                status &= ~(1 << irq);
 
                 irq_func = irq_handle_table[irq].handler;
                 param = irq_handle_table[irq].param;
 
-				/* do interrupt */
+                /* do interrupt */
                 irq_func(irq, param);
 
 #ifdef RT_USING_INTERRUPT_INFO
                 irq_handle_table[irq].counter++;
 #endif /* RT_USING_INTERRUPT_INFO */
 
-				/* ack interrupt */
-				ls1b_hw0_icregs->int_clr |= (1 << irq);
-			}
-		}
-	}
-	else if (pending_im & CAUSEF_IP3)
-	{		
-		rt_kprintf("%s %d\r\n", __FUNCTION__, __LINE__);
-	}
-	else if (pending_im & CAUSEF_IP4)
-	{		
-		rt_kprintf("%s %d\r\n", __FUNCTION__, __LINE__);
-	}
-	else if (pending_im & CAUSEF_IP5)
-	{		
-		rt_kprintf("%s %d\r\n", __FUNCTION__, __LINE__);
-	}
-	else if (pending_im & CAUSEF_IP6)
-	{		
-		rt_kprintf("%s %d\r\n", __FUNCTION__, __LINE__);
-	}
+                /* ack interrupt */
+                ls1b_hw0_icregs->int_clr |= (1 << irq);
+            }
+        }
+    }
+    else if (pending_im & CAUSEF_IP3)
+    {
+        rt_kprintf("%s %d\r\n", __FUNCTION__, __LINE__);
+    }
+    else if (pending_im & CAUSEF_IP4)
+    {
+        rt_kprintf("%s %d\r\n", __FUNCTION__, __LINE__);
+    }
+    else if (pending_im & CAUSEF_IP5)
+    {
+        rt_kprintf("%s %d\r\n", __FUNCTION__, __LINE__);
+    }
+    else if (pending_im & CAUSEF_IP6)
+    {
+        rt_kprintf("%s %d\r\n", __FUNCTION__, __LINE__);
+    }
 }
 
 /*@}*/