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6db0ee13
编写于
12月 02, 2016
作者:
M
me-no-dev
浏览文件
操作
浏览文件
下载
电子邮件补丁
差异文件
Optimize GPIO and account for micros overflow in delayMicroseconds
上级
3c81739b
变更
3
显示空白变更内容
内联
并排
Showing
3 changed file
with
86 addition
and
69 deletion
+86
-69
cores/esp32/esp32-hal-gpio.c
cores/esp32/esp32-hal-gpio.c
+72
-63
cores/esp32/esp32-hal-misc.c
cores/esp32/esp32-hal-misc.c
+10
-6
cores/esp32/esp32-hal.h
cores/esp32/esp32-hal.h
+4
-0
未找到文件。
cores/esp32/esp32-hal-gpio.c
浏览文件 @
6db0ee13
...
@@ -22,51 +22,58 @@
...
@@ -22,51 +22,58 @@
#include "soc/gpio_reg.h"
#include "soc/gpio_reg.h"
#include "soc/io_mux_reg.h"
#include "soc/io_mux_reg.h"
#include "soc/gpio_struct.h"
#include "soc/gpio_struct.h"
#include "
driver/gpio
.h"
#include "
soc/rtc_io_reg
.h"
#define ETS_GPIO_INUM 4
#define ETS_GPIO_INUM 4
const
uint8_t
esp32_gpioToFn
[
40
]
=
{
typedef
struct
{
0x44
,
//0
uint32_t
mux
;
/*!< Register to modify various pin settings */
0x88
,
//1
uint32_t
pud
;
/*!< Register to modify to enable or disable pullups or pulldowns */
0x40
,
//2
uint32_t
pu
;
/*!< Bit to set or clear in the above register to enable or disable the pullup, respectively */
0x84
,
//3
uint32_t
pd
;
/*!< Bit to set or clear in the above register to enable or disable the pulldown, respectively */
0x48
,
//4
}
esp32_gpioMux_t
;
0x6c
,
//5
0x60
,
//6
const
DRAM_ATTR
esp32_gpioMux_t
esp32_gpioMux
[
GPIO_PIN_COUNT
]
=
{
0x64
,
//7
{
DR_REG_IO_MUX_BASE
+
0x44
,
RTC_IO_TOUCH_PAD1_REG
,
RTC_IO_TOUCH_PAD1_RUE_M
,
RTC_IO_TOUCH_PAD1_RDE_M
},
0x68
,
//8
{
DR_REG_IO_MUX_BASE
+
0x88
,
0
,
0
,
0
},
0x54
,
//9
{
DR_REG_IO_MUX_BASE
+
0x40
,
RTC_IO_TOUCH_PAD2_REG
,
RTC_IO_TOUCH_PAD2_RUE_M
,
RTC_IO_TOUCH_PAD2_RDE_M
},
0x58
,
//10
{
DR_REG_IO_MUX_BASE
+
0x84
,
0
,
0
,
0
},
0x5c
,
//11
{
DR_REG_IO_MUX_BASE
+
0x48
,
RTC_IO_TOUCH_PAD0_REG
,
RTC_IO_TOUCH_PAD0_RUE_M
,
RTC_IO_TOUCH_PAD0_RDE_M
},
0x34
,
//12
{
DR_REG_IO_MUX_BASE
+
0x6c
,
0
,
0
,
0
},
0x38
,
//13
{
DR_REG_IO_MUX_BASE
+
0x60
,
0
,
0
,
0
},
0x30
,
//14
{
DR_REG_IO_MUX_BASE
+
0x64
,
0
,
0
,
0
},
0x3c
,
//15
{
DR_REG_IO_MUX_BASE
+
0x68
,
0
,
0
,
0
},
0x4c
,
//16
{
DR_REG_IO_MUX_BASE
+
0x54
,
0
,
0
,
0
},
0x50
,
//17
{
DR_REG_IO_MUX_BASE
+
0x58
,
0
,
0
,
0
},
0x70
,
//18
{
DR_REG_IO_MUX_BASE
+
0x5c
,
0
,
0
,
0
},
0x74
,
//19
{
DR_REG_IO_MUX_BASE
+
0x34
,
RTC_IO_TOUCH_PAD5_REG
,
RTC_IO_TOUCH_PAD5_RUE_M
,
RTC_IO_TOUCH_PAD5_RDE_M
},
0x78
,
//20
{
DR_REG_IO_MUX_BASE
+
0x38
,
RTC_IO_TOUCH_PAD4_REG
,
RTC_IO_TOUCH_PAD4_RUE_M
,
RTC_IO_TOUCH_PAD4_RDE_M
},
0x7c
,
//21
{
DR_REG_IO_MUX_BASE
+
0x30
,
RTC_IO_TOUCH_PAD6_REG
,
RTC_IO_TOUCH_PAD6_RUE_M
,
RTC_IO_TOUCH_PAD6_RDE_M
},
0x80
,
//22
{
DR_REG_IO_MUX_BASE
+
0x3c
,
RTC_IO_TOUCH_PAD3_REG
,
RTC_IO_TOUCH_PAD3_RUE_M
,
RTC_IO_TOUCH_PAD3_RDE_M
},
0x8c
,
//23
{
DR_REG_IO_MUX_BASE
+
0x4c
,
0
,
0
,
0
},
0xFF
,
//N/A
{
DR_REG_IO_MUX_BASE
+
0x50
,
0
,
0
,
0
},
0x24
,
//25
{
DR_REG_IO_MUX_BASE
+
0x70
,
0
,
0
,
0
},
0x28
,
//26
{
DR_REG_IO_MUX_BASE
+
0x74
,
0
,
0
,
0
},
0x2c
,
//27
{
DR_REG_IO_MUX_BASE
+
0x78
,
0
,
0
,
0
},
0xFF
,
//N/A
{
DR_REG_IO_MUX_BASE
+
0x7c
,
0
,
0
,
0
},
0xFF
,
//N/A
{
DR_REG_IO_MUX_BASE
+
0x80
,
0
,
0
,
0
},
0xFF
,
//N/A
{
DR_REG_IO_MUX_BASE
+
0x8c
,
0
,
0
,
0
},
0xFF
,
//N/A
{
0
,
0
,
0
,
0
},
0x1c
,
//32
{
DR_REG_IO_MUX_BASE
+
0x24
,
RTC_IO_PAD_DAC1_REG
,
RTC_IO_PDAC1_RUE_M
,
RTC_IO_PDAC1_RDE_M
},
0x20
,
//33
{
DR_REG_IO_MUX_BASE
+
0x28
,
RTC_IO_PAD_DAC2_REG
,
RTC_IO_PDAC2_RUE_M
,
RTC_IO_PDAC2_RDE_M
},
0x14
,
//34
{
DR_REG_IO_MUX_BASE
+
0x2c
,
RTC_IO_TOUCH_PAD7_REG
,
RTC_IO_TOUCH_PAD7_RUE_M
,
RTC_IO_TOUCH_PAD7_RDE_M
},
0x18
,
//35
{
0
,
0
,
0
,
0
},
0x04
,
//36
{
0
,
0
,
0
,
0
},
0x08
,
//37
{
0
,
0
,
0
,
0
},
0x0c
,
//38
{
0
,
0
,
0
,
0
},
0x10
//39
{
DR_REG_IO_MUX_BASE
+
0x1c
,
RTC_IO_XTAL_32K_PAD_REG
,
RTC_IO_X32P_RUE_M
,
RTC_IO_X32P_RDE_M
},
{
DR_REG_IO_MUX_BASE
+
0x20
,
RTC_IO_XTAL_32K_PAD_REG
,
RTC_IO_X32N_RUE_M
,
RTC_IO_X32N_RDE_M
},
{
DR_REG_IO_MUX_BASE
+
0x14
,
0
,
0
,
0
},
{
DR_REG_IO_MUX_BASE
+
0x18
,
0
,
0
,
0
},
{
DR_REG_IO_MUX_BASE
+
0x04
,
0
,
0
,
0
},
{
DR_REG_IO_MUX_BASE
+
0x08
,
0
,
0
,
0
},
{
DR_REG_IO_MUX_BASE
+
0x0c
,
0
,
0
,
0
},
{
DR_REG_IO_MUX_BASE
+
0x10
,
0
,
0
,
0
}
};
};
typedef
void
(
*
voidFuncPtr
)(
void
);
typedef
void
(
*
voidFuncPtr
)(
void
);
...
@@ -74,18 +81,26 @@ static voidFuncPtr __pinInterruptHandlers[GPIO_PIN_COUNT] = {0,};
...
@@ -74,18 +81,26 @@ static voidFuncPtr __pinInterruptHandlers[GPIO_PIN_COUNT] = {0,};
extern
void
IRAM_ATTR
__pinMode
(
uint8_t
pin
,
uint8_t
mode
)
extern
void
IRAM_ATTR
__pinMode
(
uint8_t
pin
,
uint8_t
mode
)
{
{
uint32_t
pinFunction
=
0
,
pinControl
=
0
;
if
(
pin
>
39
||
esp32_gpioToFn
[
pin
]
==
0xFF
)
{
if
(
pin
>
39
||
!
esp32_gpioMux
[
pin
].
mux
)
{
return
;
return
;
}
}
uint32_t
pinFunction
=
0
,
pinControl
=
0
;
const
esp32_gpioMux_t
*
mux
=
&
esp32_gpioMux
[
pin
];
if
(
mode
&
INPUT
)
{
if
(
mode
&
INPUT
)
{
if
(
pin
<
32
)
{
if
(
pin
<
32
)
{
GPIO
.
enable_w1tc
=
((
uint32_t
)
1
<<
pin
);
GPIO
.
enable_w1tc
=
((
uint32_t
)
1
<<
pin
);
}
else
{
}
else
{
GPIO
.
enable1_w1tc
.
val
=
((
uint32_t
)
1
<<
(
pin
-
32
));
GPIO
.
enable1_w1tc
.
val
=
((
uint32_t
)
1
<<
(
pin
-
32
));
}
}
if
(
mode
&
PULLUP
)
{
pinFunction
|=
FUN_PU
;
}
else
if
(
mode
&
PULLDOWN
)
{
pinFunction
|=
FUN_PD
;
}
}
else
if
(
mode
&
OUTPUT
)
{
}
else
if
(
mode
&
OUTPUT
)
{
if
(
pin
<
32
)
{
if
(
pin
<
32
)
{
GPIO
.
enable_w1ts
=
((
uint32_t
)
1
<<
pin
);
GPIO
.
enable_w1ts
=
((
uint32_t
)
1
<<
pin
);
...
@@ -105,19 +120,18 @@ extern void IRAM_ATTR __pinMode(uint8_t pin, uint8_t mode)
...
@@ -105,19 +120,18 @@ extern void IRAM_ATTR __pinMode(uint8_t pin, uint8_t mode)
pinFunction
|=
((
uint32_t
)(
mode
>>
5
)
<<
MCU_SEL_S
);
pinFunction
|=
((
uint32_t
)(
mode
>>
5
)
<<
MCU_SEL_S
);
}
}
ESP_REG
(
DR_REG_IO_MUX_BASE
+
esp32_gpioToFn
[
pin
]
)
=
pinFunction
;
ESP_REG
(
mux
->
mux
)
=
pinFunction
;
if
(
mux
->
pud
){
if
((
mode
&
INPUT
)
&&
(
mode
&
(
PULLUP
|
PULLDOWN
)))
{
if
((
mode
&
INPUT
)
&&
(
mode
&
(
PULLUP
|
PULLDOWN
)))
{
if
(
mode
&
PULLUP
)
{
if
(
mode
&
PULLUP
)
{
gpio_pullup_en
(
pin
);
ESP_REG
(
mux
->
pud
)
=
(
ESP_REG
(
mux
->
pud
)
|
mux
->
pu
)
&
~
(
mux
->
pd
);
gpio_pulldown_dis
(
pin
);
}
else
{
}
else
{
gpio_pulldown_en
(
pin
);
ESP_REG
(
mux
->
pud
)
=
(
ESP_REG
(
mux
->
pud
)
|
mux
->
pd
)
&
~
(
mux
->
pu
);
gpio_pullup_dis
(
pin
);
}
}
}
else
{
}
else
{
gpio_pullup_dis
(
pin
);
ESP_REG
(
mux
->
pud
)
=
ESP_REG
(
mux
->
pud
)
&
~
(
mux
->
pu
|
mux
->
pd
);
gpio_pulldown_dis
(
pin
);
}
}
}
if
(
mode
&
OPEN_DRAIN
)
{
if
(
mode
&
OPEN_DRAIN
)
{
...
@@ -129,19 +143,16 @@ extern void IRAM_ATTR __pinMode(uint8_t pin, uint8_t mode)
...
@@ -129,19 +143,16 @@ extern void IRAM_ATTR __pinMode(uint8_t pin, uint8_t mode)
extern
void
IRAM_ATTR
__digitalWrite
(
uint8_t
pin
,
uint8_t
val
)
extern
void
IRAM_ATTR
__digitalWrite
(
uint8_t
pin
,
uint8_t
val
)
{
{
if
(
pin
>
39
)
{
return
;
}
if
(
val
)
{
if
(
val
)
{
if
(
pin
<
32
)
{
if
(
pin
<
32
)
{
GPIO
.
out_w1ts
=
((
uint32_t
)
1
<<
pin
);
GPIO
.
out_w1ts
=
((
uint32_t
)
1
<<
pin
);
}
else
{
}
else
if
(
pin
<
35
)
{
GPIO
.
out1_w1ts
.
val
=
((
uint32_t
)
1
<<
(
pin
-
32
));
GPIO
.
out1_w1ts
.
val
=
((
uint32_t
)
1
<<
(
pin
-
32
));
}
}
}
else
{
}
else
{
if
(
pin
<
32
)
{
if
(
pin
<
32
)
{
GPIO
.
out_w1tc
=
((
uint32_t
)
1
<<
pin
);
GPIO
.
out_w1tc
=
((
uint32_t
)
1
<<
pin
);
}
else
{
}
else
if
(
pin
<
35
)
{
GPIO
.
out1_w1tc
.
val
=
((
uint32_t
)
1
<<
(
pin
-
32
));
GPIO
.
out1_w1tc
.
val
=
((
uint32_t
)
1
<<
(
pin
-
32
));
}
}
}
}
...
@@ -149,14 +160,12 @@ extern void IRAM_ATTR __digitalWrite(uint8_t pin, uint8_t val)
...
@@ -149,14 +160,12 @@ extern void IRAM_ATTR __digitalWrite(uint8_t pin, uint8_t val)
extern
int
IRAM_ATTR
__digitalRead
(
uint8_t
pin
)
extern
int
IRAM_ATTR
__digitalRead
(
uint8_t
pin
)
{
{
if
(
pin
>
39
)
{
return
0
;
}
if
(
pin
<
32
)
{
if
(
pin
<
32
)
{
return
(
GPIO
.
in
>>
pin
)
&
0x1
;
return
(
GPIO
.
in
>>
pin
)
&
0x1
;
}
else
{
}
else
if
(
pin
<
40
)
{
return
(
GPIO
.
in1
.
val
>>
(
pin
-
32
))
&
0x1
;
return
(
GPIO
.
in1
.
val
>>
(
pin
-
32
))
&
0x1
;
}
}
return
0
;
}
}
...
...
cores/esp32/esp32-hal-misc.c
浏览文件 @
6db0ee13
...
@@ -68,7 +68,6 @@ uint32_t IRAM_ATTR micros()
...
@@ -68,7 +68,6 @@ uint32_t IRAM_ATTR micros()
uint32_t
ccount
;
uint32_t
ccount
;
__asm__
__volatile__
(
"rsr %0, ccount"
:
"=a"
(
ccount
)
);
__asm__
__volatile__
(
"rsr %0, ccount"
:
"=a"
(
ccount
)
);
return
ccount
/
CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ
;
return
ccount
/
CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ
;
//return system_get_time();
}
}
uint32_t
IRAM_ATTR
millis
()
uint32_t
IRAM_ATTR
millis
()
...
@@ -81,12 +80,17 @@ void delay(uint32_t ms)
...
@@ -81,12 +80,17 @@ void delay(uint32_t ms)
vTaskDelay
(
ms
/
portTICK_PERIOD_MS
);
vTaskDelay
(
ms
/
portTICK_PERIOD_MS
);
}
}
void
delayMicroseconds
(
uint32_t
us
)
void
IRAM_ATTR
delayMicroseconds
(
uint32_t
us
)
{
{
if
(
us
)
{
uint32_t
m
=
micros
();
unsigned
long
endat
=
micros
();
if
(
us
){
endat
+=
us
;
uint32_t
e
=
(
m
+
us
)
%
((
0xFFFFFFFF
/
CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ
)
+
1
);
while
(
micros
()
<
endat
)
{
if
(
m
>
e
){
//overflow
while
(
micros
()
>
e
){
NOP
();
}
}
while
(
micros
()
<
e
){
NOP
();
NOP
();
}
}
}
}
...
...
cores/esp32/esp32-hal.h
浏览文件 @
6db0ee13
...
@@ -34,6 +34,10 @@ extern "C" {
...
@@ -34,6 +34,10 @@ extern "C" {
#include <math.h>
#include <math.h>
#include "sdkconfig.h"
#include "sdkconfig.h"
#ifndef F_CPU
#define F_CPU (CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ * 1000000U)
#endif
#ifndef CONFIG_DISABLE_HAL_LOCKS
#ifndef CONFIG_DISABLE_HAL_LOCKS
#define CONFIG_DISABLE_HAL_LOCKS 0
#define CONFIG_DISABLE_HAL_LOCKS 0
#endif
#endif
...
...
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